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140,383 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv | 90,320,290 | uart_ctrl_virtual_seq_lib.sv | sv | 313 | 124 | [] | [] | [] | null | line:21: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: Unsupported: classes\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:24: syntax error, unexpected rand\n rand int unsigned num_u2a_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:26: Unsupported: new constructor\n function new(string name="concurrent_u2a_a2u_rand_trans_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr <= 6);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr <= 9);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:52: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:56: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(raw_seq, p_sequencer.apb_seqr, {num_of_wr == num_a2u_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {num_of_tx == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: syntax error, unexpected \',\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:66: syntax error, unexpected endclass\nendclass : concurrent_u2a_a2u_rand_trans_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: Unsupported: classes\nclass u2a_incr_payload_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_incr_payload_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:71: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:73: Unsupported: new constructor\n function new(string name="u2a_incr_payload_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr > 2) && (num_u2a_wr <= 10);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr == 0);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:93: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:99: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {cnt == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:100: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:105: syntax error, unexpected endclass\nendclass : u2a_incr_payload_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: Unsupported: classes\nclass u2a_bad_parity_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_bad_parity_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:110: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:112: Unsupported: new constructor\n function new(string name="u2a_bad_parity_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,464 | function | function new(string name="u2a_bad_parity_vseq");
super.new(name);
endfunction | function new(string name="u2a_bad_parity_vseq"); |
super.new(name);
endfunction | 0 |
140,384 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv | 90,320,290 | uart_ctrl_virtual_seq_lib.sv | sv | 313 | 124 | [] | [] | [] | null | line:21: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: Unsupported: classes\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:24: syntax error, unexpected rand\n rand int unsigned num_u2a_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:26: Unsupported: new constructor\n function new(string name="concurrent_u2a_a2u_rand_trans_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr <= 6);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr <= 9);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:52: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:56: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(raw_seq, p_sequencer.apb_seqr, {num_of_wr == num_a2u_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {num_of_tx == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: syntax error, unexpected \',\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:66: syntax error, unexpected endclass\nendclass : concurrent_u2a_a2u_rand_trans_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: Unsupported: classes\nclass u2a_incr_payload_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_incr_payload_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:71: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:73: Unsupported: new constructor\n function new(string name="u2a_incr_payload_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr > 2) && (num_u2a_wr <= 10);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr == 0);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:93: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:99: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {cnt == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:100: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:105: syntax error, unexpected endclass\nendclass : u2a_incr_payload_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: Unsupported: classes\nclass u2a_bad_parity_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_bad_parity_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:110: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:112: Unsupported: new constructor\n function new(string name="u2a_bad_parity_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,464 | function | function new(string name="uart_1_stopbit_rx_traffic_vseq");
super.new(name);
endfunction | function new(string name="uart_1_stopbit_rx_traffic_vseq"); |
super.new(name);
endfunction | 0 |
140,385 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv | 90,320,290 | uart_ctrl_virtual_seq_lib.sv | sv | 313 | 124 | [] | [] | [] | null | line:21: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: Unsupported: classes\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:24: syntax error, unexpected rand\n rand int unsigned num_u2a_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:26: Unsupported: new constructor\n function new(string name="concurrent_u2a_a2u_rand_trans_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr <= 6);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr <= 9);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:52: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:56: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(raw_seq, p_sequencer.apb_seqr, {num_of_wr == num_a2u_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {num_of_tx == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: syntax error, unexpected \',\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:66: syntax error, unexpected endclass\nendclass : concurrent_u2a_a2u_rand_trans_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: Unsupported: classes\nclass u2a_incr_payload_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_incr_payload_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:71: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:73: Unsupported: new constructor\n function new(string name="u2a_incr_payload_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr > 2) && (num_u2a_wr <= 10);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr == 0);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:93: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:99: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {cnt == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:100: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:105: syntax error, unexpected endclass\nendclass : u2a_incr_payload_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: Unsupported: classes\nclass u2a_bad_parity_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_bad_parity_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:110: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:112: Unsupported: new constructor\n function new(string name="u2a_bad_parity_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,464 | function | function new(string name="uart_rx_tx_fifo_coverage_vseq");
super.new(name);
endfunction | function new(string name="uart_rx_tx_fifo_coverage_vseq"); |
super.new(name);
endfunction | 0 |
140,386 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv | 90,320,290 | test_lib.sv | sv | 79 | 105 | [] | [] | [] | null | line:10: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:13: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:49: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(apb_write_to_uart_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:50: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(apb_master_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:57: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:66: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:67: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(uart_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,466 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | 0 |
140,387 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv | 90,320,290 | test_lib.sv | sv | 79 | 105 | [] | [] | [] | null | line:10: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:13: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:49: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(apb_write_to_uart_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:50: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(apb_master_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:57: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:66: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:67: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(uart_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,466 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,388 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv | 90,320,290 | test_lib.sv | sv | 79 | 105 | [] | [] | [] | null | line:10: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:13: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:49: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(apb_write_to_uart_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:50: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(apb_master_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:57: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:66: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:67: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(uart_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,466 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
set_config_string("uart_ctrl_tb0.apb0.master.sequencer", "default_sequence", "apb_write_to_uart_seq");
set_config_string("uart_ctrl_tb0.uart0.Tx.sequencer", "default_sequence", "uart_write_to_apb_seq");
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
set_config_string("uart_ctrl_tb0.apb0.master.sequencer", "default_sequence", "apb_write_to_uart_seq");
set_config_string("uart_ctrl_tb0.uart0.Tx.sequencer", "default_sequence", "uart_write_to_apb_seq");
endfunction | 0 |
140,390 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv | 90,320,290 | test_lib.sv | sv | 79 | 105 | [] | [] | [] | null | line:10: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:13: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:49: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(apb_write_to_uart_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:50: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(apb_master_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:57: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:66: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:67: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(uart_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,466 | function | function new(string name="apb_write_to_uart_seq");
super.new(name);
endfunction | function new(string name="apb_write_to_uart_seq"); |
super.new(name);
endfunction | 0 |
140,391 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv | 90,320,290 | test_lib.sv | sv | 79 | 105 | [] | [] | [] | null | line:10: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:10: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:13: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:25: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:31: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:33: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:49: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(apb_write_to_uart_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:50: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(apb_master_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:57: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:66: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:67: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n`uvm_declare_p_sequencer(uart_sequencer)\n^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,466 | function | function new(string name="uart_write_to_apb_seq");
super.new(name);
endfunction | function new(string name="uart_write_to_apb_seq"); |
super.new(name);
endfunction | 0 |
140,392 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | 0 |
140,393 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,394 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | 0 |
140,396 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.virtual_sequencer.run_phase",
"default_sequence", a2u_u2a_vseq::type_id::get());
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.virtual_sequencer.run_phase",
"default_sequence", a2u_u2a_vseq::type_id::get());
endfunction | 0 |
140,397 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,398 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name="apb_config_seq");
super.new(name);
endfunction | function new(string name="apb_config_seq"); |
super.new(name);
endfunction | 0 |
140,399 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name="apb_write_to_uart_seq");
super.new(name);
endfunction | function new(string name="apb_write_to_uart_seq"); |
super.new(name);
endfunction | 0 |
140,400 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name="uart_write_to_apb_seq");
super.new(name);
endfunction | function new(string name="uart_write_to_apb_seq"); |
super.new(name);
endfunction | 0 |
140,401 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name="base_vseq");
super.new(name);
endfunction | function new(string name="base_vseq"); |
super.new(name);
endfunction | 0 |
140,402 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv | 90,320,290 | test_lib1.sv | sv | 216 | 93 | [] | [] | [] | null | line:13: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:16: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(uart_ctrl_base_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:18: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:23: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:28: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:37: Unsupported: extends\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:39: syntax error, unexpected \'(\'\n`uvm_component_utils(u2a_a2u_rand_test)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:61: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(u2a_a2u_vseq_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:80: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_config_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:88: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:92: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h83", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:93: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 1 to 8\'h01", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:94: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Div Latch 2 to 8\'h00", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:95: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Set Line Control Reg to 8\'h03", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:96: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_CONFIG_SEQ", "Configuring the UART Controller Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:106: syntax error, unexpected IDENTIFIER\n constraint num_transfers_c {num_transfers inside {[2:8]};}\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:108: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_to_uart_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_TO_UART_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:123: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(transfer.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:124: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("APB_TO_UART_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:127: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("APB_TO_UART_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:138: syntax error, unexpected IDENTIFIER\n constraint num_frames_c {num_frames inside {[1:5]};}\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:140: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(uart_write_to_apb_seq)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:149: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_TO_APB_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:155: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:156: Define or directive not defined: \'`uvm_info\'\n #20 `uvm_info("UART_TO_APB_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:159: Define or directive not defined: \'`uvm_info\'\n # 10 `uvm_info("UART_TO_APB_SEQ", "Completed...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:169: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:170: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:173: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:174: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:192: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(a2u_u2a_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:193: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: Define or directive not defined: \'`uvm_info\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:207: syntax error, unexpected \',\'\n `uvm_info("A2U_U2A_VSEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:208: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:211: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/test_lib1.sv:212: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,467 | function | function new(string name="a2u_u2a_vseq");
super.new(name);
endfunction | function new(string name="a2u_u2a_vseq"); |
super.new(name);
endfunction | 0 |
140,403 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv | 90,320,290 | uart_ctrl_simple_tb.sv | sv | 80 | 95 | [] | [] | [] | null | line:8: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:26: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No APB config. creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 16 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,468 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,404 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv | 90,320,290 | uart_ctrl_simple_tb.sv | sv | 80 | 95 | [] | [] | [] | null | line:8: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:26: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No APB config. creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 16 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,468 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "apb_cfg", apb_cfg)) begin
`uvm_info("NOCONFIG", "No APB config. creating...", UVM_LOW)
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "uart_cfg", uart_cfg))
uart_cfg = uart_config::type_id::create("uart_cfg", this);
uvm_config_object::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_object::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_object::set(this, "*scbd", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "apb_cfg", apb_cfg)) begin
`uvm_info("NOCONFIG", "No APB config. creating...", UVM_LOW)
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "uart_cfg", uart_cfg))
uart_cfg = uart_config::type_id::create("uart_cfg", this);
uvm_config_object::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_object::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_object::set(this, "*scbd", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | 0 |
140,405 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv | 90,320,290 | uart_ctrl_simple_tb.sv | sv | 80 | 95 | [] | [] | [] | null | line:8: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:26: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:35: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No APB config. creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: Hierarchical class references\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: Unsupported: scoped class reference\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:38: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_simple_tb.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 16 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,468 | function | function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.is_active == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | function void uart_ctrl_tb::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.is_active == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | 0 |
140,406 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv | 90,320,290 | uart_ctrl_test.sv | sv | 47 | 100 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:23: Cannot find include file: tb/uart_ctrl_simple_tb.sv\n `include "tb/uart_ctrl_simple_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:24: Cannot find include file: tb/test_lib1.sv\n `include "tb/test_lib1.sv" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:34: Unsupported: Ignoring delay on this delayed statement.\n #51 reset <= 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:36: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/tb/uart_ctrl_test.sv:40: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);\n ^\n%Error: Exiting due to 9 error(s), 2 warning(s)\n' | 308,469 | module | module top;
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
`include "tb/uart_ctrl_simple_tb.sv"
`include "tb/test_lib1.sv"
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
reset <= 1'b0;
clk <= 1'b0;
#51 reset <= 1'b1;
end
always #5 clk = ~clk;
initial begin
uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "uvm_test_top.uart_ctrl_tb0.uart0*", "vif", uart_if0);
run_test();
end
endmodule | module top; |
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
`include "tb/uart_ctrl_simple_tb.sv"
`include "tb/test_lib1.sv"
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
reset <= 1'b0;
clk <= 1'b0;
#51 reset <= 1'b1;
end
always #5 clk = ~clk;
initial begin
uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "uvm_test_top.uart_ctrl_tb0.uart0*", "vif", uart_if0);
run_test();
end
endmodule | 0 |
140,407 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv | 90,320,290 | uart_rx_driver.sv | sv | 230 | 127 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: Unsupported: classes\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:33: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:36: syntax error, unexpected IDENTIFIER\n uart_config cfg;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:46: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:47: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_brgr, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:48: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_bdiv, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:49: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:57: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:61: syntax error, unexpected extern\n extern virtual task get_and_drive();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:70: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:72: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:73: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:78: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:79: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:80: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:85: Unsupported: fork statements\n fork\n ^~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:89: End label \'run_phase\' does not match begin label \'reset\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Hierarchical class references\ntask uart_rx_driver::reset();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: scoped class reference\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:60: Unsupported: Out of class block function declaration\n extern virtual task reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:93: syntax error, unexpected \'@\'\n @(negedge vif.reset);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: Hierarchical class references\ntask uart_rx_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: scoped class reference\ntask uart_rx_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Out of class block function declaration\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:106: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:107: syntax error, unexpected \'@\'\n @(negedge vif.reset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:108: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset asserted", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:115: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:122: Unsupported: this\n if(req.is_active()) this.end_tr(req);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:123: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:128: syntax error, unexpected \'@\'\n @(posedge vif.clock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:142: syntax error, unexpected endtask\nendtask : gen_sample_rate\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:148: syntax error, unexpected IDENTIFIER, expecting "\'{"\n bit [7:0] payload_byte;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:157: Unsupported: this\n void\'(this.begin_tr(frame));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:159: Unsupported: wait statements\n wait((!cfg.rts_en)||(!vif.cts_n));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:177: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,476 | function | function new(string name, uvm_component parent);
super.new(name,parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,408 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv | 90,320,290 | uart_rx_driver.sv | sv | 230 | 127 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: Unsupported: classes\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:33: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:36: syntax error, unexpected IDENTIFIER\n uart_config cfg;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:46: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:47: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_brgr, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:48: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_bdiv, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:49: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:57: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:61: syntax error, unexpected extern\n extern virtual task get_and_drive();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:70: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:72: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:73: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:78: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:79: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:80: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:85: Unsupported: fork statements\n fork\n ^~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:89: End label \'run_phase\' does not match begin label \'reset\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Hierarchical class references\ntask uart_rx_driver::reset();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: scoped class reference\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:60: Unsupported: Out of class block function declaration\n extern virtual task reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:93: syntax error, unexpected \'@\'\n @(negedge vif.reset);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: Hierarchical class references\ntask uart_rx_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: scoped class reference\ntask uart_rx_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Out of class block function declaration\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:106: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:107: syntax error, unexpected \'@\'\n @(negedge vif.reset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:108: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset asserted", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:115: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:122: Unsupported: this\n if(req.is_active()) this.end_tr(req);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:123: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:128: syntax error, unexpected \'@\'\n @(posedge vif.clock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:142: syntax error, unexpected endtask\nendtask : gen_sample_rate\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:148: syntax error, unexpected IDENTIFIER, expecting "\'{"\n bit [7:0] payload_byte;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:157: Unsupported: this\n void\'(this.begin_tr(frame));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:159: Unsupported: wait statements\n wait((!cfg.rts_en)||(!vif.cts_n));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:177: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,476 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task reset();
extern virtual task get_and_drive();
extern virtual task gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk);
extern virtual task send_rx_frame(input uart_frame frame);
extern virtual function void report_phase(uvm_phase phase);
endclass : uart_rx_driver
function void uart_rx_driver::build_phase(uvm_phase phase);
super.build_phase(phase);
if(cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "uart_config not set for this component")
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task reset();
extern virtual task get_and_drive();
extern virtual task gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk);
extern virtual task send_rx_frame(input uart_frame frame);
extern virtual function void report_phase(uvm_phase phase);
endclass : uart_rx_driver
function void uart_rx_driver::build_phase(uvm_phase phase);
super.build_phase(phase);
if(cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "uart_config not set for this component")
endfunction | 0 |
140,409 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv | 90,320,290 | uart_rx_driver.sv | sv | 230 | 127 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: Unsupported: classes\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:33: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:36: syntax error, unexpected IDENTIFIER\n uart_config cfg;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:46: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:47: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_brgr, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:48: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_bdiv, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:49: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:57: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:61: syntax error, unexpected extern\n extern virtual task get_and_drive();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:70: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:72: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:73: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:78: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:79: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:80: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:85: Unsupported: fork statements\n fork\n ^~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:89: End label \'run_phase\' does not match begin label \'reset\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Hierarchical class references\ntask uart_rx_driver::reset();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: scoped class reference\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:60: Unsupported: Out of class block function declaration\n extern virtual task reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:93: syntax error, unexpected \'@\'\n @(negedge vif.reset);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: Hierarchical class references\ntask uart_rx_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: scoped class reference\ntask uart_rx_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Out of class block function declaration\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:106: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:107: syntax error, unexpected \'@\'\n @(negedge vif.reset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:108: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset asserted", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:115: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:122: Unsupported: this\n if(req.is_active()) this.end_tr(req);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:123: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:128: syntax error, unexpected \'@\'\n @(posedge vif.clock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:142: syntax error, unexpected endtask\nendtask : gen_sample_rate\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:148: syntax error, unexpected IDENTIFIER, expecting "\'{"\n bit [7:0] payload_byte;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:157: Unsupported: this\n void\'(this.begin_tr(frame));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:159: Unsupported: wait statements\n wait((!cfg.rts_en)||(!vif.cts_n));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:177: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,476 | function | function void uart_rx_driver::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | function void uart_rx_driver::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | 0 |
140,410 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv | 90,320,290 | uart_rx_driver.sv | sv | 230 | 127 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: Unsupported: classes\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_rx_driver extends uvm_driver #(uart_frame) ;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:33: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:36: syntax error, unexpected IDENTIFIER\n uart_config cfg;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:45: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(uart_rx_driver)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:46: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:47: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_brgr, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:48: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_bdiv, UVM_DEFAULT + UVM_NOPRINT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:49: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:57: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:61: syntax error, unexpected extern\n extern virtual task get_and_drive();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:70: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:72: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:73: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:78: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:79: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:80: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:85: Unsupported: fork statements\n fork\n ^~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:89: End label \'run_phase\' does not match begin label \'reset\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Hierarchical class references\ntask uart_rx_driver::reset();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: scoped class reference\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:60: Unsupported: Out of class block function declaration\n extern virtual task reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:93: syntax error, unexpected \'@\'\n @(negedge vif.reset);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:94: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Reset Asserted", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: Hierarchical class references\ntask uart_rx_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:103: Unsupported: scoped class reference\ntask uart_rx_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:92: Unsupported: Out of class block function declaration\ntask uart_rx_driver::reset();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:106: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:107: syntax error, unexpected \'@\'\n @(negedge vif.reset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:108: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Reset asserted", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:115: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:122: Unsupported: this\n if(req.is_active()) this.end_tr(req);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:123: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:128: syntax error, unexpected \'@\'\n @(posedge vif.clock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:142: syntax error, unexpected endtask\nendtask : gen_sample_rate\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:148: syntax error, unexpected IDENTIFIER, expecting "\'{"\n bit [7:0] payload_byte;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:151: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:157: Unsupported: this\n void\'(this.begin_tr(frame));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:159: Unsupported: wait statements\n wait((!cfg.rts_en)||(!vif.cts_n));\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:160: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Driver - Modem RTS or CTS asserted", UVM_HIGH)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:164: Unsupported: Ignoring delay on this delayed statement.\n #1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:169: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/examples/uart_rx_driver.sv:177: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,476 | function | function void uart_rx_driver::report_phase(uvm_phase phase);
`uvm_info(get_type_name(),
$sformatf("UART Frames Sent:%0d", num_frames_sent),
UVM_LOW )
endfunction | function void uart_rx_driver::report_phase(uvm_phase phase); |
`uvm_info(get_type_name(),
$sformatf("UART Frames Sent:%0d", num_frames_sent),
UVM_LOW )
endfunction | 0 |
140,411 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv | 90,320,290 | uart_monitor.sv | sv | 248 | 128 | [] | ['apache license'] | ['all rights reserved'] | null | line:32: before: "virtual" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: virtual classes\nvirtual class uart_monitor extends uvm_monitor;\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: classes\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:36: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:39: syntax error, unexpected IDENTIFIER\n uart_config cfg; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:57: syntax error, unexpected IDENTIFIER\n uart_frame cur_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:59: Define or directive not defined: \'`uvm_field_utils_begin\'\n `uvm_field_utils_begin(uart_monitor)\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:60: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:61: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:62: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:63: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cur_frame, UVM_DEFAULT | UVM_NOPRINT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:64: Define or directive not defined: \'`uvm_field_utils_end\'\n `uvm_field_utils_end\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:66: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup uart_trans_frame_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n NUM_STOP_BITS : coverpoint cfg.nbstop {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:68: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ONE = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:69: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins TWO = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:71: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n DATA_LENGTH : coverpoint cfg.char_length {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:72: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EIGHT = {0,1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:73: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SEVEN = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:74: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SIX = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:76: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_MODE : coverpoint cfg.parity_mode {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:77: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EVEN = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ODD = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SPACE = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins MARK = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:82: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_ERROR: coverpoint cur_frame.error_bits[1]\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins good = { 0 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins bad = { 1 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n DATA_LENGTH_x_PARITY_MODE: cross DATA_LENGTH, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:89: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n PARITY_ERROR_x_PARITY_MODE: cross PARITY_ERROR, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: Unsupported: new constructor\n function new (string name = "", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:102: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:103: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:105: syntax error, unexpected extern\n extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:114: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:116: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:117: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this somponent")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:121: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:122: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:123: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:129: Unsupported: wait statements\n wait (vif.reset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:132: syntax error, unexpected ::, expecting \';\'\n cur_frame = uart_frame::type_id::create("cur_frame", this);\n ^~\n : ... Perhaps \'uart_frame\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:134: Unsupported: fork statements\n fork\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,481 | function | function new (string name = "", uvm_component parent);
super.new(name, parent);
uart_trans_frame_cg = new();
uart_trans_frame_cg.set_inst_name ("uart_trans_frame_cg");
frame_collected_port = new("frame_collected_port", this);
endfunction | function new (string name = "", uvm_component parent); |
super.new(name, parent);
uart_trans_frame_cg = new();
uart_trans_frame_cg.set_inst_name ("uart_trans_frame_cg");
frame_collected_port = new("frame_collected_port", this);
endfunction | 0 |
140,412 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv | 90,320,290 | uart_monitor.sv | sv | 248 | 128 | [] | ['apache license'] | ['all rights reserved'] | null | line:32: before: "virtual" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: virtual classes\nvirtual class uart_monitor extends uvm_monitor;\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: classes\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:36: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:39: syntax error, unexpected IDENTIFIER\n uart_config cfg; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:57: syntax error, unexpected IDENTIFIER\n uart_frame cur_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:59: Define or directive not defined: \'`uvm_field_utils_begin\'\n `uvm_field_utils_begin(uart_monitor)\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:60: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:61: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:62: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:63: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cur_frame, UVM_DEFAULT | UVM_NOPRINT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:64: Define or directive not defined: \'`uvm_field_utils_end\'\n `uvm_field_utils_end\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:66: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup uart_trans_frame_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n NUM_STOP_BITS : coverpoint cfg.nbstop {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:68: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ONE = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:69: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins TWO = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:71: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n DATA_LENGTH : coverpoint cfg.char_length {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:72: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EIGHT = {0,1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:73: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SEVEN = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:74: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SIX = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:76: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_MODE : coverpoint cfg.parity_mode {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:77: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EVEN = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ODD = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SPACE = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins MARK = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:82: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_ERROR: coverpoint cur_frame.error_bits[1]\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins good = { 0 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins bad = { 1 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n DATA_LENGTH_x_PARITY_MODE: cross DATA_LENGTH, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:89: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n PARITY_ERROR_x_PARITY_MODE: cross PARITY_ERROR, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: Unsupported: new constructor\n function new (string name = "", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:102: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:103: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:105: syntax error, unexpected extern\n extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:114: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:116: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:117: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this somponent")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:121: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:122: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:123: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:129: Unsupported: wait statements\n wait (vif.reset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:132: syntax error, unexpected ::, expecting \';\'\n cur_frame = uart_frame::type_id::create("cur_frame", this);\n ^~\n : ... Perhaps \'uart_frame\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:134: Unsupported: fork statements\n fork\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,481 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk, ref bit sop_detected);
extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);
extern virtual function void perform_coverage();
extern virtual task collect_frame();
extern virtual task wait_for_sop(ref bit sop_detected);
extern virtual task sample_and_store();
endclass: uart_monitor
function void uart_monitor::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "uart_config not set for this somponent")
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task gen_sample_rate(ref bit [15:0] ua_brgr, ref bit sample_clk, ref bit sop_detected);
extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);
extern virtual function void perform_coverage();
extern virtual task collect_frame();
extern virtual task wait_for_sop(ref bit sop_detected);
extern virtual task sample_and_store();
endclass: uart_monitor
function void uart_monitor::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "uart_config not set for this somponent")
endfunction | 0 |
140,413 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv | 90,320,290 | uart_monitor.sv | sv | 248 | 128 | [] | ['apache license'] | ['all rights reserved'] | null | line:32: before: "virtual" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: virtual classes\nvirtual class uart_monitor extends uvm_monitor;\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: classes\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:36: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:39: syntax error, unexpected IDENTIFIER\n uart_config cfg; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:57: syntax error, unexpected IDENTIFIER\n uart_frame cur_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:59: Define or directive not defined: \'`uvm_field_utils_begin\'\n `uvm_field_utils_begin(uart_monitor)\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:60: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:61: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:62: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:63: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cur_frame, UVM_DEFAULT | UVM_NOPRINT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:64: Define or directive not defined: \'`uvm_field_utils_end\'\n `uvm_field_utils_end\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:66: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup uart_trans_frame_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n NUM_STOP_BITS : coverpoint cfg.nbstop {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:68: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ONE = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:69: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins TWO = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:71: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n DATA_LENGTH : coverpoint cfg.char_length {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:72: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EIGHT = {0,1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:73: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SEVEN = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:74: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SIX = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:76: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_MODE : coverpoint cfg.parity_mode {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:77: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EVEN = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ODD = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SPACE = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins MARK = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:82: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_ERROR: coverpoint cur_frame.error_bits[1]\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins good = { 0 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins bad = { 1 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n DATA_LENGTH_x_PARITY_MODE: cross DATA_LENGTH, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:89: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n PARITY_ERROR_x_PARITY_MODE: cross PARITY_ERROR, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: Unsupported: new constructor\n function new (string name = "", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:102: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:103: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:105: syntax error, unexpected extern\n extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:114: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:116: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:117: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this somponent")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:121: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:122: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:123: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:129: Unsupported: wait statements\n wait (vif.reset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:132: syntax error, unexpected ::, expecting \';\'\n cur_frame = uart_frame::type_id::create("cur_frame", this);\n ^~\n : ... Perhaps \'uart_frame\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:134: Unsupported: fork statements\n fork\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,481 | function | function void uart_monitor::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | function void uart_monitor::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | 0 |
140,414 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv | 90,320,290 | uart_monitor.sv | sv | 248 | 128 | [] | ['apache license'] | ['all rights reserved'] | null | line:32: before: "virtual" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: virtual classes\nvirtual class uart_monitor extends uvm_monitor;\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: Unsupported: classes\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:32: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nvirtual class uart_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:36: Unsupported: virtual interface\n virtual interface uart_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:39: syntax error, unexpected IDENTIFIER\n uart_config cfg; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:57: syntax error, unexpected IDENTIFIER\n uart_frame cur_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:59: Define or directive not defined: \'`uvm_field_utils_begin\'\n `uvm_field_utils_begin(uart_monitor)\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:60: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:61: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:62: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:63: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cur_frame, UVM_DEFAULT | UVM_NOPRINT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:64: Define or directive not defined: \'`uvm_field_utils_end\'\n `uvm_field_utils_end\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:66: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup uart_trans_frame_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:67: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n NUM_STOP_BITS : coverpoint cfg.nbstop {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:68: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ONE = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:69: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins TWO = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:71: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n DATA_LENGTH : coverpoint cfg.char_length {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:72: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EIGHT = {0,1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:73: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SEVEN = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:74: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SIX = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:76: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_MODE : coverpoint cfg.parity_mode {\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:77: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins EVEN = {0};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins ODD = {1};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins SPACE = {2};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins MARK = {3};\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:82: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n PARITY_ERROR: coverpoint cur_frame.error_bits[1]\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:84: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins good = { 0 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:85: Unsupported: SystemVerilog 2005 reserved word not implemented: \'bins\'\n bins bad = { 1 };\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:88: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n DATA_LENGTH_x_PARITY_MODE: cross DATA_LENGTH, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:89: Unsupported: SystemVerilog 2005 reserved word not implemented: \'cross\'\n PARITY_ERROR_x_PARITY_MODE: cross PARITY_ERROR, PARITY_MODE;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:91: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: Unsupported: new constructor\n function new (string name = "", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:93: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:102: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:103: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:105: syntax error, unexpected extern\n extern virtual task start_synchronizer(ref bit serial_d1, ref bit serial_b);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:114: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:116: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:117: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "uart_config not set for this somponent")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:121: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:122: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual uart_if)::get(this, "","vif",vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:123: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:127: syntax error, unexpected \',\'\n `uvm_info(get_type_name(),"Start Running", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:129: Unsupported: wait statements\n wait (vif.reset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:130: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Detected Reset Done", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:132: syntax error, unexpected ::, expecting \';\'\n cur_frame = uart_frame::type_id::create("cur_frame", this);\n ^~\n : ... Perhaps \'uart_frame\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/uart/sv/uart_monitor.sv:134: Unsupported: fork statements\n fork\n ^~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,481 | function | function void uart_monitor::perform_coverage();
uart_trans_frame_cg.sample();
endfunction | function void uart_monitor::perform_coverage(); |
uart_trans_frame_cg.sample();
endfunction | 0 |
140,415 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv | 90,320,290 | ex8-1_interrupt.sv | sv | 42 | 85 | [] | [] | [] | null | line:7: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:8: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:10: Cannot find include file: sv/apb_if.sv\n`include "sv/apb_if.sv" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:11: Cannot find include file: sv/apb_pkg.sv\n`include "sv/apb_pkg.sv" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:7: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:16: Unsupported: classes\nclass apb_interrupt_from_uart extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_interrupt_from_uart extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:18: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_interrupt_from_uart)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:19: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:21: Unsupported: new constructor\n function new(string name="apb_interrupt_from_uart");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:22: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:22: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:22: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:26: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:28: syntax error, unexpected \'@\'\n @(p_sequencer.vif.ua_int);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:29: Define or directive not defined: \'`uvm_info\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:29: syntax error, unexpected \',\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:31: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { addr == 8\'h02; direction == APB_READ; })\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:31: syntax error, unexpected \',\'\n `uvm_do_with(req, { addr == 8\'h02; direction == APB_READ; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:31: syntax error, unexpected \';\'\n `uvm_do_with(req, { addr == 8\'h02; direction == APB_READ; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:32: Define or directive not defined: \'`uvm_info\'\n if (req.data[1]) `uvm_info("INTERRUPT", "Rx EMPTY Interrupt occurred", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:33: Define or directive not defined: \'`uvm_info\'\n if (req.data[2]) `uvm_info("INTERRUPT", "Rx FULL Interrupt occurred", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:34: Define or directive not defined: \'`uvm_info\'\n if (req.data[3]) `uvm_info("INTERRUPT", "Tx EMPTY Interrupt occurred", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:35: Define or directive not defined: \'`uvm_info\'\n if (req.data[4]) `uvm_info("INTERRUPT", "Tx FULL Interrupt occurred", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-1_interrupt.sv:41: syntax error, unexpected endclass\nendclass : apb_interrupt_from_uart\n^~~~~~~~\n%Error: Exiting due to 24 error(s)\n' | 308,505 | function | function new(string name="apb_interrupt_from_uart");
super.new(name);
endfunction | function new(string name="apb_interrupt_from_uart"); |
super.new(name);
endfunction | 0 |
140,416 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
`define DATA_SIZE 8
`define MAX_PL 10
class lower_env_item extends uvm_sequence_item;
rand bit [`DATA_SIZE-1:0] payload[];
rand int unsigned pl_size;
constraint pload_cst { pl_size < `MAX_PL;
payload.size() == pl_size; }
`uvm_object_utils_begin(lower_env_item)
`uvm_field_array_int(payload, UVM_DEFAULT)
`uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)
`uvm_object_utils_end
function new (string name="lower_env_item");
super.new(name);
endfunction : new
endclass : lower_env_item
class upper_env_item extends uvm_sequence_item;
rand int unsigned max_item_size;
rand int unsigned num_items;
rand lower_env_item item[];
constraint item_cst { num_items == item.size();
num_items inside {[1:4]}; }
constraint item_size_cst { max_item_size inside {[10:20]};}
`uvm_object_utils_begin(upper_env_item)
`uvm_field_int(max_item_size, UVM_DEFAULT)
`uvm_field_int(num_items, UVM_DEFAULT)
`uvm_field_array_object(item, UVM_DEFAULT)
`uvm_object_utils_end
function new(input string name="upper_env_item");
super.new(name);
endfunction : new
function void post_randomize();
foreach(item[i]) begin
item[i] = lower_env_item::type_id::create($sformatf("item[%0d]", i));
if (!item[i].randomize() with {pl_size <= max_item_size; })
`uvm_error("RANDFAIL", "Item Randomization Failed")
end
endfunction : post_randomize
endclass : upper_env_item
class upper_env_item_seq extends uvm_sequence #(lower_env_item);
`uvm_object_utils(upper_env_item_seq)
function new(string name="upper_env_item_seq");
super.new(name);
endfunction : new
upper_env_item upper_item;
virtual task pre_body();
if (starting_phase !=null)
starting_phase.raise_objection(this, "Running sequence");
endtask
virtual task post_body();
if (starting_phase !=null)
starting_phase.drop_objection(this, "Completed sequence");
endtask
virtual task body();
`uvm_create(upper_item)
void'(upper_item.randomize());
`uvm_info("UPPER_SEQ",
{"Executing Upper Item:\n%s", upper_item.sprint()}, UVM_LOW)
for (int i=0; i<upper_item.num_items; i++)
`uvm_send(upper_item.item[i])
endtask : body
endclass : upper_env_item_seq
typedef class lower_env_sequencer;
class lower_env_base_seq extends uvm_sequence #(lower_env_item);
`uvm_object_utils(lower_env_base_seq)
`uvm_declare_p_sequencer(lower_env_sequencer)
function new(string name="lower_env_base_seq");
super.new(name);
endfunction : new
virtual task body();
`uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)
`uvm_do(req)
endtask : body
endclass : lower_env_base_seq
class lower_env_sequencer extends uvm_sequencer#(lower_env_item);
`uvm_component_utils(lower_env_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : lower_env_sequencer
class lower_env_driver extends uvm_driver#(lower_env_item);
`uvm_component_utils(lower_env_driver)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
task run();
get_and_drive();
endtask : run
task get_and_drive();
while (1) begin
seq_item_port.get_next_item(req);
send_to_dut(req);
seq_item_port.item_done();
end
endtask
task send_to_dut(lower_env_item item);
#10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\n%s", item.sprint()}, UVM_LOW)
endtask : send_to_dut
endclass : lower_env_driver
class simple_test extends uvm_test;
lower_env_driver driver;
lower_env_sequencer sequencer;
`uvm_component_utils(simple_test)
function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
uvm_config_wrapper::set(this, "sequencer.run_phase", "default_sequence", upper_env_item_seq::get_type());
sequencer = lower_env_sequencer::type_id::create("sequencer", this);
driver = lower_env_driver::type_id::create("driver", this);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
driver.rsp_port.connect(sequencer.rsp_export);
endfunction : connect_phase
function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction : start_of_simulation_phase
endclass : simple_test
initial begin
`uvm_info("TOP", "Beginning Test", UVM_LOW)
run_test("simple_test");
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
`define DATA_SIZE 8
`define MAX_PL 10
class lower_env_item extends uvm_sequence_item;
rand bit [`DATA_SIZE-1:0] payload[];
rand int unsigned pl_size;
constraint pload_cst { pl_size < `MAX_PL;
payload.size() == pl_size; }
`uvm_object_utils_begin(lower_env_item)
`uvm_field_array_int(payload, UVM_DEFAULT)
`uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)
`uvm_object_utils_end
function new (string name="lower_env_item");
super.new(name);
endfunction : new
endclass : lower_env_item
class upper_env_item extends uvm_sequence_item;
rand int unsigned max_item_size;
rand int unsigned num_items;
rand lower_env_item item[];
constraint item_cst { num_items == item.size();
num_items inside {[1:4]}; }
constraint item_size_cst { max_item_size inside {[10:20]};}
`uvm_object_utils_begin(upper_env_item)
`uvm_field_int(max_item_size, UVM_DEFAULT)
`uvm_field_int(num_items, UVM_DEFAULT)
`uvm_field_array_object(item, UVM_DEFAULT)
`uvm_object_utils_end
function new(input string name="upper_env_item");
super.new(name);
endfunction : new
function void post_randomize();
foreach(item[i]) begin
item[i] = lower_env_item::type_id::create($sformatf("item[%0d]", i));
if (!item[i].randomize() with {pl_size <= max_item_size; })
`uvm_error("RANDFAIL", "Item Randomization Failed")
end
endfunction : post_randomize
endclass : upper_env_item
class upper_env_item_seq extends uvm_sequence #(lower_env_item);
`uvm_object_utils(upper_env_item_seq)
function new(string name="upper_env_item_seq");
super.new(name);
endfunction : new
upper_env_item upper_item;
virtual task pre_body();
if (starting_phase !=null)
starting_phase.raise_objection(this, "Running sequence");
endtask
virtual task post_body();
if (starting_phase !=null)
starting_phase.drop_objection(this, "Completed sequence");
endtask
virtual task body();
`uvm_create(upper_item)
void'(upper_item.randomize());
`uvm_info("UPPER_SEQ",
{"Executing Upper Item:\n%s", upper_item.sprint()}, UVM_LOW)
for (int i=0; i<upper_item.num_items; i++)
`uvm_send(upper_item.item[i])
endtask : body
endclass : upper_env_item_seq
typedef class lower_env_sequencer;
class lower_env_base_seq extends uvm_sequence #(lower_env_item);
`uvm_object_utils(lower_env_base_seq)
`uvm_declare_p_sequencer(lower_env_sequencer)
function new(string name="lower_env_base_seq");
super.new(name);
endfunction : new
virtual task body();
`uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)
`uvm_do(req)
endtask : body
endclass : lower_env_base_seq
class lower_env_sequencer extends uvm_sequencer#(lower_env_item);
`uvm_component_utils(lower_env_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : lower_env_sequencer
class lower_env_driver extends uvm_driver#(lower_env_item);
`uvm_component_utils(lower_env_driver)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
task run();
get_and_drive();
endtask : run
task get_and_drive();
while (1) begin
seq_item_port.get_next_item(req);
send_to_dut(req);
seq_item_port.item_done();
end
endtask
task send_to_dut(lower_env_item item);
#10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\n%s", item.sprint()}, UVM_LOW)
endtask : send_to_dut
endclass : lower_env_driver
class simple_test extends uvm_test;
lower_env_driver driver;
lower_env_sequencer sequencer;
`uvm_component_utils(simple_test)
function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
uvm_config_wrapper::set(this, "sequencer.run_phase", "default_sequence", upper_env_item_seq::get_type());
sequencer = lower_env_sequencer::type_id::create("sequencer", this);
driver = lower_env_driver::type_id::create("driver", this);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
driver.rsp_port.connect(sequencer.rsp_export);
endfunction : connect_phase
function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction : start_of_simulation_phase
endclass : simple_test
initial begin
`uvm_info("TOP", "Beginning Test", UVM_LOW)
run_test("simple_test");
end
endmodule | 0 |
140,417 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new (string name="lower_env_item");
super.new(name);
endfunction | function new (string name="lower_env_item"); |
super.new(name);
endfunction | 0 |
140,418 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new(input string name="upper_env_item");
super.new(name);
endfunction | function new(input string name="upper_env_item"); |
super.new(name);
endfunction | 0 |
140,419 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function void post_randomize();
foreach(item[i]) begin
item[i] = lower_env_item::type_id::create($sformatf("item[%0d]", i));
if (!item[i].randomize() with {pl_size <= max_item_size; })
`uvm_error("RANDFAIL", "Item Randomization Failed")
end
endfunction | function void post_randomize(); |
foreach(item[i]) begin
item[i] = lower_env_item::type_id::create($sformatf("item[%0d]", i));
if (!item[i].randomize() with {pl_size <= max_item_size; })
`uvm_error("RANDFAIL", "Item Randomization Failed")
end
endfunction | 0 |
140,420 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new(string name="upper_env_item_seq");
super.new(name);
endfunction | function new(string name="upper_env_item_seq"); |
super.new(name);
endfunction | 0 |
140,421 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new(string name="lower_env_base_seq");
super.new(name);
endfunction | function new(string name="lower_env_base_seq"); |
super.new(name);
endfunction | 0 |
140,422 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,423 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,424 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction | function new(string name="simple_test", uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,425 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function void build_phase(uvm_phase phase);
uvm_config_wrapper::set(this, "sequencer.run_phase", "default_sequence", upper_env_item_seq::get_type());
sequencer = lower_env_sequencer::type_id::create("sequencer", this);
driver = lower_env_driver::type_id::create("driver", this);
endfunction | function void build_phase(uvm_phase phase); |
uvm_config_wrapper::set(this, "sequencer.run_phase", "default_sequence", upper_env_item_seq::get_type());
sequencer = lower_env_sequencer::type_id::create("sequencer", this);
driver = lower_env_driver::type_id::create("driver", this);
endfunction | 0 |
140,426 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function void connect_phase(uvm_phase phase);
driver.seq_item_port.connect(sequencer.seq_item_export);
driver.rsp_port.connect(sequencer.rsp_export);
endfunction | function void connect_phase(uvm_phase phase); |
driver.seq_item_port.connect(sequencer.seq_item_export);
driver.rsp_port.connect(sequencer.rsp_export);
endfunction | 0 |
140,427 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv | 90,320,290 | ex8-2a_single_layer_arch.sv | sv | 173 | 110 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: Unsupported: classes\nclass lower_env_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint pload_cst { pl_size < 10;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:18: syntax error, unexpected \'(\', expecting IDENTIFIER\n payload.size() == pl_size; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:20: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(payload, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:22: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(pl_size, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:23: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_cst { num_items == item.size();\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:39: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint item_size_cst { max_item_size inside {[10:20]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:41: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_env_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(max_item_size, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_items, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:44: Define or directive not defined: \'`uvm_field_array_object\'\n `uvm_field_array_object(item, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:45: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: syntax error, unexpected \'(\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n if (!item[i].randomize() with {pl_size <= max_item_size; })\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:56: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("RANDFAIL", "Item Randomization Failed") \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:64: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_env_item_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:75: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:80: syntax error, unexpected \'(\', expecting IDENTIFIER\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:85: Define or directive not defined: \'`uvm_create\'\n `uvm_create(upper_item)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:86: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(upper_item.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UPPER_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:90: Define or directive not defined: \'`uvm_send\'\n `uvm_send(upper_item.item[i])\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: Unsupported: classes\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:95: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_env_base_seq extends uvm_sequence #(lower_env_item);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:96: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(lower_env_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:97: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info("LOWER_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:103: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:109: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:117: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_env_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:131: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:136: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:146: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:158: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.seq_item_port.connect(sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:159: syntax error, unexpected \'.\', expecting IDENTIFIER\n driver.rsp_port.connect(sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2a_single_layer_arch.sv:168: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,506 | function | function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction | function void start_of_simulation_phase(uvm_phase phase); |
this.print();
endfunction | 0 |
140,428 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv | 90,320,290 | ex8-2_interrupt_sequence.sv | sv | 82 | 77 | [] | [] | [] | null | line:8: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:10: Cannot find include file: sv/apb_types.sv\n`include "sv/apb_types.sv" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:11: Cannot find include file: sv/apb_transfer.sv\n`include "sv/apb_transfer.sv" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: Unsupported: classes\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:19: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_status_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:20: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:22: Unsupported: new constructor\n function new(string name="read_status_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: syntax error, unexpected \',\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:38: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(interrupt_handler_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: syntax error, unexpected \'(\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:47: syntax error, unexpected \'@\'\n @(p_sequencer.interrupt);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: syntax error, unexpected \',\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:50: Define or directive not defined: \'`uvm_do\'\n `uvm_do(interrupt_reset_seq)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:51: syntax error, unexpected IDENTIFIER\n ungrab(p_sequencer);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:56: Unsupported: new constructor\n function new(string name="interrupt_handler_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:60: syntax error, unexpected endclass\nendclass : interrupt_handler_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:64: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:67: Unsupported: event data types\n event interrupt;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:74: syntax error, unexpected ::, expecting \';\'\n interrupt_seq = interrupt_handler_seq::type_id::create("interrupt_seq");\n ^~\n : ... Perhaps \'interrupt_handler_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:75: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:76: Unsupported: this\n interrupt_seq.start(this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:78: Unsupported: super\n super.run();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:81: syntax error, unexpected endclass\nendclass : apb_master_sequencer\n^~~~~~~~\n%Error: Exiting due to 38 error(s)\n' | 308,507 | function | function new(string name="read_status_seq");
super.new(name);
endfunction | function new(string name="read_status_seq"); |
super.new(name);
endfunction | 0 |
140,429 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv | 90,320,290 | ex8-2_interrupt_sequence.sv | sv | 82 | 77 | [] | [] | [] | null | line:8: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:10: Cannot find include file: sv/apb_types.sv\n`include "sv/apb_types.sv" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:11: Cannot find include file: sv/apb_transfer.sv\n`include "sv/apb_transfer.sv" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: Unsupported: classes\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:19: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_status_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:20: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:22: Unsupported: new constructor\n function new(string name="read_status_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: syntax error, unexpected \',\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:38: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(interrupt_handler_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: syntax error, unexpected \'(\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:47: syntax error, unexpected \'@\'\n @(p_sequencer.interrupt);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: syntax error, unexpected \',\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:50: Define or directive not defined: \'`uvm_do\'\n `uvm_do(interrupt_reset_seq)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:51: syntax error, unexpected IDENTIFIER\n ungrab(p_sequencer);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:56: Unsupported: new constructor\n function new(string name="interrupt_handler_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:60: syntax error, unexpected endclass\nendclass : interrupt_handler_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:64: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:67: Unsupported: event data types\n event interrupt;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:74: syntax error, unexpected ::, expecting \';\'\n interrupt_seq = interrupt_handler_seq::type_id::create("interrupt_seq");\n ^~\n : ... Perhaps \'interrupt_handler_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:75: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:76: Unsupported: this\n interrupt_seq.start(this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:78: Unsupported: super\n super.run();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:81: syntax error, unexpected endclass\nendclass : apb_master_sequencer\n^~~~~~~~\n%Error: Exiting due to 38 error(s)\n' | 308,507 | function | function new(string name="interrupt_handler_seq");
super.new(name);
endfunction | function new(string name="interrupt_handler_seq"); |
super.new(name);
endfunction | 0 |
140,430 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv | 90,320,290 | ex8-2_interrupt_sequence.sv | sv | 82 | 77 | [] | [] | [] | null | line:8: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:10: Cannot find include file: sv/apb_types.sv\n`include "sv/apb_types.sv" \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:11: Cannot find include file: sv/apb_transfer.sv\n`include "sv/apb_transfer.sv" \n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: Unsupported: classes\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass read_status_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:19: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_status_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:20: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:22: Unsupported: new constructor\n function new(string name="read_status_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:23: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:27: syntax error, unexpected \',\'\n `uvm_info("RD_STATUS_REG_SEQ", "Executing...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:38: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(interrupt_handler_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:39: syntax error, unexpected \'(\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:47: syntax error, unexpected \'@\'\n @(p_sequencer.interrupt);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:48: syntax error, unexpected \',\'\n `uvm_info("INTERRUPT_SEQ", "Executing Sequence", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:50: Define or directive not defined: \'`uvm_do\'\n `uvm_do(interrupt_reset_seq)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:51: syntax error, unexpected IDENTIFIER\n ungrab(p_sequencer);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:56: Unsupported: new constructor\n function new(string name="interrupt_handler_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:57: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:60: syntax error, unexpected endclass\nendclass : interrupt_handler_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:62: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:64: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:67: Unsupported: event data types\n event interrupt;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:69: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:74: syntax error, unexpected ::, expecting \';\'\n interrupt_seq = interrupt_handler_seq::type_id::create("interrupt_seq");\n ^~\n : ... Perhaps \'interrupt_handler_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:75: Unsupported: fork statements\n fork\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:76: Unsupported: this\n interrupt_seq.start(this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:78: Unsupported: super\n super.run();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-2_interrupt_sequence.sv:81: syntax error, unexpected endclass\nendclass : apb_master_sequencer\n^~~~~~~~\n%Error: Exiting due to 38 error(s)\n' | 308,507 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,431 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
class lower_item extends uvm_sequence_item;
rand byte byte_array[];
rand int unsigned num_bytes;
constraint a_cst { num_bytes inside {[1:16]};
byte_array.size() == num_bytes; }
`uvm_object_utils_begin(lower_item)
`uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)
`uvm_field_array_int(byte_array, UVM_DEFAULT)
`uvm_object_utils_end
function new (string name="lower_item");
super.new(name);
endfunction : new
endclass : lower_item
class upper_item extends uvm_sequence_item;
rand byte header;
rand bit [31:0] word;
rand byte footer;
`uvm_object_utils_begin(upper_item)
`uvm_field_int(header, UVM_DEFAULT)
`uvm_field_int(word, UVM_DEFAULT)
`uvm_field_int(footer, UVM_DEFAULT)
`uvm_object_utils_end
function new(input string name="upper_item");
super.new(name);
endfunction : new
endclass : upper_item
class upper_sequencer extends uvm_sequencer#(upper_item);
`uvm_component_utils(upper_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : upper_sequencer
class lower_sequencer extends uvm_sequencer#(lower_item);
uvm_seq_item_pull_port #(upper_item) upper_seq_item_port;
`uvm_component_utils(lower_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
upper_seq_item_port = new("upper_seq_item_port", this);
endfunction : new
endclass : lower_sequencer
class lower_driver extends uvm_driver#(lower_item);
`uvm_component_utils(lower_driver)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
task run_phase(uvm_phase phase);
while (1) begin
seq_item_port.get_next_item(req);
send_to_dut(req);
seq_item_port.item_done();
end
endtask: run
task send_to_dut(lower_item item);
#10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\n%s", item.sprint()}, UVM_LOW)
endtask : send_to_dut
endclass : lower_driver
class upper_to_lower_seq extends uvm_sequence #(lower_item);
`uvm_object_utils(upper_to_lower_seq)
`uvm_declare_p_sequencer(lower_sequencer)
function new(string name="upper_to_lower_seq");
super.new(name);
endfunction : new
upper_item u_item;
lower_item l_item;
virtual task body();
forever begin
`uvm_do_with(l_item,
{ l_item.num_bytes == 6;
l_item.byte_array[0] == u_item.header;
l_item.byte_array[1] == u_item.word[7:0];
l_item.byte_array[2] == u_item.word[15:8];
l_item.byte_array[3] == u_item.word[23:16];
l_item.byte_array[4] == u_item.word[31:24];
l_item.byte_array[5] == u_item.footer;
})
end
endtask : body
virtual task pre_do(bit is_item);
if (is_item)
p_sequencer.upper_seq_item_port.get_next_item(u_item);
`uvm_info("UP2LOW_SEQ",
{"Executing Upper Item:\n%s", u_item.sprint()}, UVM_LOW)
endtask : pre_do
virtual function void post_do(uvm_sequence_item this_item);
p_sequencer.upper_seq_item_port.item_done(u_item);
endfunction : post_do
endclass : upper_to_lower_seq
class simple_test extends uvm_test;
lower_driver l_driver;
lower_sequencer l_sequencer;
upper_sequencer u_sequencer;
`uvm_component_utils(simple_test)
function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "l_sequencer.run_phase", "default_sequence", upper_to_lower_seq::get_type());
l_driver = lower_driver::type_id::create("l_driver", this);
l_sequencer = lower_sequencer::type_id::create("l_sequencer", this);
u_sequencer = upper_sequencer::type_id::create("u_sequencer", this);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
l_driver.seq_item_port.connect(l_sequencer.seq_item_export);
l_driver.rsp_port.connect(l_sequencer.rsp_export);
l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);
endfunction : connect_phase
function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction : start_of_simulation_phase
endclass : simple_test
initial begin
`uvm_info("TOP", "Beginning Test", UVM_LOW)
run_test("simple_test");
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
class lower_item extends uvm_sequence_item;
rand byte byte_array[];
rand int unsigned num_bytes;
constraint a_cst { num_bytes inside {[1:16]};
byte_array.size() == num_bytes; }
`uvm_object_utils_begin(lower_item)
`uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)
`uvm_field_array_int(byte_array, UVM_DEFAULT)
`uvm_object_utils_end
function new (string name="lower_item");
super.new(name);
endfunction : new
endclass : lower_item
class upper_item extends uvm_sequence_item;
rand byte header;
rand bit [31:0] word;
rand byte footer;
`uvm_object_utils_begin(upper_item)
`uvm_field_int(header, UVM_DEFAULT)
`uvm_field_int(word, UVM_DEFAULT)
`uvm_field_int(footer, UVM_DEFAULT)
`uvm_object_utils_end
function new(input string name="upper_item");
super.new(name);
endfunction : new
endclass : upper_item
class upper_sequencer extends uvm_sequencer#(upper_item);
`uvm_component_utils(upper_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : upper_sequencer
class lower_sequencer extends uvm_sequencer#(lower_item);
uvm_seq_item_pull_port #(upper_item) upper_seq_item_port;
`uvm_component_utils(lower_sequencer)
function new(string name, uvm_component parent);
super.new(name, parent);
upper_seq_item_port = new("upper_seq_item_port", this);
endfunction : new
endclass : lower_sequencer
class lower_driver extends uvm_driver#(lower_item);
`uvm_component_utils(lower_driver)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
task run_phase(uvm_phase phase);
while (1) begin
seq_item_port.get_next_item(req);
send_to_dut(req);
seq_item_port.item_done();
end
endtask: run
task send_to_dut(lower_item item);
#10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\n%s", item.sprint()}, UVM_LOW)
endtask : send_to_dut
endclass : lower_driver
class upper_to_lower_seq extends uvm_sequence #(lower_item);
`uvm_object_utils(upper_to_lower_seq)
`uvm_declare_p_sequencer(lower_sequencer)
function new(string name="upper_to_lower_seq");
super.new(name);
endfunction : new
upper_item u_item;
lower_item l_item;
virtual task body();
forever begin
`uvm_do_with(l_item,
{ l_item.num_bytes == 6;
l_item.byte_array[0] == u_item.header;
l_item.byte_array[1] == u_item.word[7:0];
l_item.byte_array[2] == u_item.word[15:8];
l_item.byte_array[3] == u_item.word[23:16];
l_item.byte_array[4] == u_item.word[31:24];
l_item.byte_array[5] == u_item.footer;
})
end
endtask : body
virtual task pre_do(bit is_item);
if (is_item)
p_sequencer.upper_seq_item_port.get_next_item(u_item);
`uvm_info("UP2LOW_SEQ",
{"Executing Upper Item:\n%s", u_item.sprint()}, UVM_LOW)
endtask : pre_do
virtual function void post_do(uvm_sequence_item this_item);
p_sequencer.upper_seq_item_port.item_done(u_item);
endfunction : post_do
endclass : upper_to_lower_seq
class simple_test extends uvm_test;
lower_driver l_driver;
lower_sequencer l_sequencer;
upper_sequencer u_sequencer;
`uvm_component_utils(simple_test)
function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "l_sequencer.run_phase", "default_sequence", upper_to_lower_seq::get_type());
l_driver = lower_driver::type_id::create("l_driver", this);
l_sequencer = lower_sequencer::type_id::create("l_sequencer", this);
u_sequencer = upper_sequencer::type_id::create("u_sequencer", this);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
l_driver.seq_item_port.connect(l_sequencer.seq_item_export);
l_driver.rsp_port.connect(l_sequencer.rsp_export);
l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);
endfunction : connect_phase
function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction : start_of_simulation_phase
endclass : simple_test
initial begin
`uvm_info("TOP", "Beginning Test", UVM_LOW)
run_test("simple_test");
end
endmodule | 0 |
140,432 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new (string name="lower_item");
super.new(name);
endfunction | function new (string name="lower_item"); |
super.new(name);
endfunction | 0 |
140,433 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new(input string name="upper_item");
super.new(name);
endfunction | function new(input string name="upper_item"); |
super.new(name);
endfunction | 0 |
140,434 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,435 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new(string name, uvm_component parent);
super.new(name, parent);
upper_seq_item_port = new("upper_seq_item_port", this);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
upper_seq_item_port = new("upper_seq_item_port", this);
endfunction | 0 |
140,436 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,437 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new(string name="upper_to_lower_seq");
super.new(name);
endfunction | function new(string name="upper_to_lower_seq"); |
super.new(name);
endfunction | 0 |
140,438 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function void post_do(uvm_sequence_item this_item);
p_sequencer.upper_seq_item_port.item_done(u_item);
endfunction | function void post_do(uvm_sequence_item this_item); |
p_sequencer.upper_seq_item_port.item_done(u_item);
endfunction | 0 |
140,439 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function new(string name="simple_test", uvm_component parent);
super.new(name, parent);
endfunction | function new(string name="simple_test", uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,440 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "l_sequencer.run_phase", "default_sequence", upper_to_lower_seq::get_type());
l_driver = lower_driver::type_id::create("l_driver", this);
l_sequencer = lower_sequencer::type_id::create("l_sequencer", this);
u_sequencer = upper_sequencer::type_id::create("u_sequencer", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uvm_config_wrapper::set(this, "l_sequencer.run_phase", "default_sequence", upper_to_lower_seq::get_type());
l_driver = lower_driver::type_id::create("l_driver", this);
l_sequencer = lower_sequencer::type_id::create("l_sequencer", this);
u_sequencer = upper_sequencer::type_id::create("u_sequencer", this);
endfunction | 0 |
140,441 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
l_driver.seq_item_port.connect(l_sequencer.seq_item_export);
l_driver.rsp_port.connect(l_sequencer.rsp_export);
l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);
endfunction | function void connect_phase(uvm_phase phase); |
super.connect_phase(phase);
l_driver.seq_item_port.connect(l_sequencer.seq_item_export);
l_driver.rsp_port.connect(l_sequencer.rsp_export);
l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);
endfunction | 0 |
140,442 | data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv | 90,320,290 | ex8-3_layered_sequencers.sv | sv | 169 | 112 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: Unsupported: classes\nclass lower_item extends uvm_sequence_item;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:13: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass lower_item extends uvm_sequence_item;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint a_cst { num_bytes inside {[1:16]}; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:17: syntax error, unexpected \'(\', expecting IDENTIFIER\n byte_array.size() == num_bytes; }\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:19: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(lower_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:20: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(num_bytes, UVM_DEFAULT | UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:21: Define or directive not defined: \'`uvm_field_array_int\'\n `uvm_field_array_int(byte_array, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:22: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:36: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(upper_item)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:37: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(header, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:38: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(word, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:39: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(footer, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:40: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:49: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(upper_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:59: syntax error, unexpected \'(\'\n `uvm_component_utils(lower_sequencer)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:68: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(lower_driver)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:76: syntax error, unexpected \'(\', expecting IDENTIFIER\n seq_item_port.item_done();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:80: Define or directive not defined: \'`uvm_info\'\n #10 `uvm_info("LOWER_DRIVER", {"Executing Lower Item:\\n%s", item.sprint()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:90: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(upper_to_lower_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:91: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(lower_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:99: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:101: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(l_item,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:103: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[0] == u_item.header;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:104: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[1] == u_item.word[7:0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:105: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[2] == u_item.word[15:8];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:106: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[3] == u_item.word[23:16];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:107: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[4] == u_item.word[31:24];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:108: syntax error, unexpected \'[\', expecting IDENTIFIER\n l_item.byte_array[5] == u_item.footer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:116: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.get_next_item(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:117: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UP2LOW_SEQ",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:126: syntax error, unexpected \'.\', expecting IDENTIFIER\n p_sequencer.upper_seq_item_port.item_done(u_item);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(simple_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:136: syntax error, unexpected \'(\'\n`uvm_component_utils(simple_test)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:151: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.seq_item_port.connect(l_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:152: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_driver.rsp_port.connect(l_sequencer.rsp_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:153: syntax error, unexpected \'.\', expecting IDENTIFIER\n l_sequencer.upper_seq_item_port.connect(u_sequencer.seq_item_export);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/8_stimulus_generation_topics/ex8-3_layered_sequencers.sv:164: Define or directive not defined: \'`uvm_info\'\n `uvm_info("TOP", "Beginning Test", UVM_LOW)\n ^~~~~~~~~\n%Error: Cannot continue\n' | 308,508 | function | function void start_of_simulation_phase(uvm_phase phase);
this.print();
endfunction | function void start_of_simulation_phase(uvm_phase phase); |
this.print();
endfunction | 0 |
140,443 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv | 90,320,290 | ex9-10_uart_config_seq.sv | sv | 29 | 76 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:7: Unsupported: classes\nclass uart_ctrl_config_reg_seq extends base_reg_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_config_reg_seq extends base_reg_seq;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:9: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(uart_ctrl_config_reg_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:10: Unsupported: new constructor\n function new(string name="uart_ctrl_config_reg_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:11: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:11: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:11: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:14: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:15: syntax error, unexpected IDENTIFIER\n uvm_status_e status;\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:16: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:16: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:25: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Sequence Completed", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-10_uart_config_seq.sv:25: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", "Sequence Completed", UVM_HIGH)\n ^\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,510 | function | function new(string name="uart_ctrl_config_reg_seq");
super.new(name);
endfunction | function new(string name="uart_ctrl_config_reg_seq"); |
super.new(name);
endfunction | 0 |
140,444 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv | 90,320,290 | ex9-11_uvm_built_in_seq.sv | sv | 34 | 76 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:7: Unsupported: classes\nclass built_in_seq extends base_reg_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass built_in_seq extends base_reg_seq;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:11: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(built_in_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:12: Unsupported: new constructor\n function new(string name="built_in_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:13: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:13: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:13: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:16: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:17: syntax error, unexpected IDENTIFIER\n uvm_status_e status;\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:18: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:18: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Sequence Completed", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-11_uvm_built_in_seq.sv:30: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", "Sequence Completed", UVM_HIGH)\n ^\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,511 | function | function new(string name="built_in_seq");
super.new(name);
endfunction | function new(string name="built_in_seq"); |
super.new(name);
endfunction | 0 |
140,445 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv | 90,320,290 | ex9-12_multi_reg_seq.sv | sv | 40 | 76 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:7: Unsupported: classes\nclass multi_reg_seq extends base_reg_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass multi_reg_seq extends base_reg_seq;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:11: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(multi_reg_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:12: Unsupported: new constructor\n function new(string name="multi_reg_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:13: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:13: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:13: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:16: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:17: syntax error, unexpected IDENTIFIER\n uvm_status_e status;\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:19: syntax error, unexpected IDENTIFIER, expecting "\'{"\n bit [63:0] rval;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:21: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:21: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", "Executing Sequence", UVM_HIGH)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(model.randomize()); \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:27: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", $sformatf("%s UPDATE:0x%h",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:27: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", $sformatf("%s UPDATE:0x%h",\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:33: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", $sformatf("%s READ:0x%h",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:33: syntax error, unexpected \',\'\n `uvm_info("REG_SEQ", $sformatf("%s READ:0x%h",\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-12_multi_reg_seq.sv:36: Define or directive not defined: \'`uvm_info\'\n `uvm_info("REG_SEQ", "Sequence Completed", UVM_HIGH)\n ^~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,512 | function | function new(string name="multi_reg_seq");
super.new(name);
endfunction | function new(string name="multi_reg_seq"); |
super.new(name);
endfunction | 0 |
140,446 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv | 90,320,290 | ex9-13_iregGen_coverage.sv | sv | 42 | 103 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: Unsupported: classes\nclass ua_div_latch0_c extends uvm_reg;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ua_div_latch0_c extends uvm_reg;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_div_val { div_val.value == 1; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:12: syntax error, unexpected ::, expecting \';\'\n div_val = uvm_reg_field::type_id::create("div_val");\n ^~\n : ... Perhaps \'uvm_reg_field\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Unsupported: this\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup wr_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: syntax error, unexpected IDENTIFIER\n covergroup wr_cg;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup rd_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \')\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \',\' or \';\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:33: Define or directive not defined: \'`uvm_register_cb\'\n `uvm_register_cb(ua_div_latch0_c, uvm_reg_cbs) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:34: Define or directive not defined: \'`uvm_set_super_type\'\n `uvm_set_super_type(ua_div_latch0_c, uvm_reg)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(ua_div_latch0_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:36: Unsupported: new constructor\n function new(input string name="unnamed-ua_div_latch0_c");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: super\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: new with arguments\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: dotted new\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:41: syntax error, unexpected endclass\nendclass : ua_div_latch0_c\n^~~~~~~~\n%Error: Exiting due to 23 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,513 | function | function void build();
div_val = uvm_reg_field::type_id::create("div_val");
div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h00>>0, 1, 1, 1);
wr_cg.set_inst_name($sformatf("%s.wcov", get_full_name()));
rd_cg.set_inst_name($sformatf("%s.rcov", get_full_name()));
endfunction | function void build(); |
div_val = uvm_reg_field::type_id::create("div_val");
div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h00>>0, 1, 1, 1);
wr_cg.set_inst_name($sformatf("%s.wcov", get_full_name()));
rd_cg.set_inst_name($sformatf("%s.rcov", get_full_name()));
endfunction | 0 |
140,447 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv | 90,320,290 | ex9-13_iregGen_coverage.sv | sv | 42 | 103 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: Unsupported: classes\nclass ua_div_latch0_c extends uvm_reg;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ua_div_latch0_c extends uvm_reg;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_div_val { div_val.value == 1; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:12: syntax error, unexpected ::, expecting \';\'\n div_val = uvm_reg_field::type_id::create("div_val");\n ^~\n : ... Perhaps \'uvm_reg_field\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Unsupported: this\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup wr_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: syntax error, unexpected IDENTIFIER\n covergroup wr_cg;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup rd_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \')\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \',\' or \';\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:33: Define or directive not defined: \'`uvm_register_cb\'\n `uvm_register_cb(ua_div_latch0_c, uvm_reg_cbs) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:34: Define or directive not defined: \'`uvm_set_super_type\'\n `uvm_set_super_type(ua_div_latch0_c, uvm_reg)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(ua_div_latch0_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:36: Unsupported: new constructor\n function new(input string name="unnamed-ua_div_latch0_c");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: super\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: new with arguments\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: dotted new\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:41: syntax error, unexpected endclass\nendclass : ua_div_latch0_c\n^~~~~~~~\n%Error: Exiting due to 23 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,513 | function | function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);
super.sample(data, byte_en, is_read, map);
if(!is_read) wr_cg.sample();
if(is_read) rd_cg.sample();
endfunction | function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map); |
super.sample(data, byte_en, is_read, map);
if(!is_read) wr_cg.sample();
if(is_read) rd_cg.sample();
endfunction | 0 |
140,448 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv | 90,320,290 | ex9-13_iregGen_coverage.sv | sv | 42 | 103 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: Unsupported: classes\nclass ua_div_latch0_c extends uvm_reg;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ua_div_latch0_c extends uvm_reg;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_div_val { div_val.value == 1; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:12: syntax error, unexpected ::, expecting \';\'\n div_val = uvm_reg_field::type_id::create("div_val");\n ^~\n : ... Perhaps \'uvm_reg_field\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Unsupported: this\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:13: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n div_val.configure(this, 8, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h00>>0, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup wr_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:18: syntax error, unexpected IDENTIFIER\n covergroup wr_cg;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'covergroup\'\n covergroup rd_cg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: \'coverpoint\'\n div_val : coverpoint div_val.value[7:0];\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: \'endgroup\'\n endgroup\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \')\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:27: syntax error, unexpected IDENTIFIER, expecting \',\' or \';\'\n protected virtual function void sample(uvm_reg_data_t data, byte_en, bit is_read, uvm_reg_map map);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:33: Define or directive not defined: \'`uvm_register_cb\'\n `uvm_register_cb(ua_div_latch0_c, uvm_reg_cbs) \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:34: Define or directive not defined: \'`uvm_set_super_type\'\n `uvm_set_super_type(ua_div_latch0_c, uvm_reg)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(ua_div_latch0_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:36: Unsupported: new constructor\n function new(input string name="unnamed-ua_div_latch0_c");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: super\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: new with arguments\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:37: Unsupported: dotted new\n super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-13_iregGen_coverage.sv:41: syntax error, unexpected endclass\nendclass : ua_div_latch0_c\n^~~~~~~~\n%Error: Exiting due to 23 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,513 | function | function new(input string name="unnamed-ua_div_latch0_c");
super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));
wr_cg=new;
rd_cg=new;
endfunction | function new(input string name="unnamed-ua_div_latch0_c"); |
super.new(name, 8, build_coverage(UVM_CVR_FIELD_VALS));
wr_cg=new;
rd_cg=new;
endfunction | 0 |
140,449 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv | 90,320,290 | ex9-4_ua_lcr.sv | sv | 47 | 90 | [] | [] | [] | null | line:11: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:11: Unsupported: classes\nclass ua_lcr_c extends uvm_reg;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:11: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ua_lcr_c extends uvm_reg;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_char_lngth { char_lngth.value != 2\'b00; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_break_ctrl { break_ctrl.value == 1\'b0; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:24: syntax error, unexpected ::, expecting \';\'\n char_lngth = uvm_reg_field::type_id::create("char_lngth");\n ^~\n : ... Perhaps \'uvm_reg_field\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:25: Unsupported: this\n char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>0, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:25: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>0, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:26: syntax error, unexpected ::, expecting \';\'\n num_stop_bits = uvm_reg_field::type_id::create("num_stop_bits");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:27: Unsupported: this\n num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>2, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:27: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>2, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:28: syntax error, unexpected ::, expecting \';\'\n p_en = uvm_reg_field::type_id::create("p_en");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:29: Unsupported: this\n p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>3, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:29: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>3, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:30: syntax error, unexpected ::, expecting \';\'\n parity_even = uvm_reg_field::type_id::create("parity_even");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:31: Unsupported: this\n parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>4, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:31: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>4, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:32: syntax error, unexpected ::, expecting \';\'\n parity_sticky = uvm_reg_field::type_id::create("parity_sticky");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:33: Unsupported: this\n parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>5, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:33: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>5, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:34: syntax error, unexpected ::, expecting \';\'\n break_ctrl = uvm_reg_field::type_id::create("break_ctrl");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:35: Unsupported: this\n break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>6, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:35: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>6, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:36: syntax error, unexpected ::, expecting \';\'\n div_latch_access = uvm_reg_field::type_id::create("div_latch_access");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:37: Unsupported: this\n div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>7, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:37: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>7, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:40: Define or directive not defined: \'`uvm_register_cb\'\n `uvm_register_cb(ua_lcr_c, uvm_reg_cbs)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:40: syntax error, unexpected \'(\'\n `uvm_register_cb(ua_lcr_c, uvm_reg_cbs)\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:41: Define or directive not defined: \'`uvm_set_super_type\'\n `uvm_set_super_type(ua_lcr_c, uvm_reg)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:42: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(ua_lcr_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:43: Unsupported: new constructor\n function new(input string name="unnamed-ua_lcr_c");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: super\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: new with arguments\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: dotted new\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:46: syntax error, unexpected endclass\nendclass : ua_lcr_c\n^~~~~~~~\n%Error: Exiting due to 34 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,515 | function | function void build();
char_lngth = uvm_reg_field::type_id::create("char_lngth");
char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>0, 1, 1, 1);
num_stop_bits = uvm_reg_field::type_id::create("num_stop_bits");
num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>2, 1, 1, 1);
p_en = uvm_reg_field::type_id::create("p_en");
p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>3, 1, 1, 1);
parity_even = uvm_reg_field::type_id::create("parity_even");
parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>4, 1, 1, 1);
parity_sticky = uvm_reg_field::type_id::create("parity_sticky");
parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>5, 1, 1, 1);
break_ctrl = uvm_reg_field::type_id::create("break_ctrl");
break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>6, 1, 1, 1);
div_latch_access = uvm_reg_field::type_id::create("div_latch_access");
div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>7, 1, 1, 1);
endfunction | function void build(); |
char_lngth = uvm_reg_field::type_id::create("char_lngth");
char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>0, 1, 1, 1);
num_stop_bits = uvm_reg_field::type_id::create("num_stop_bits");
num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>2, 1, 1, 1);
p_en = uvm_reg_field::type_id::create("p_en");
p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>3, 1, 1, 1);
parity_even = uvm_reg_field::type_id::create("parity_even");
parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>4, 1, 1, 1);
parity_sticky = uvm_reg_field::type_id::create("parity_sticky");
parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>5, 1, 1, 1);
break_ctrl = uvm_reg_field::type_id::create("break_ctrl");
break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>6, 1, 1, 1);
div_latch_access = uvm_reg_field::type_id::create("div_latch_access");
div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH'h03>>7, 1, 1, 1);
endfunction | 0 |
140,450 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv | 90,320,290 | ex9-4_ua_lcr.sv | sv | 47 | 90 | [] | [] | [] | null | line:11: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:11: Unsupported: classes\nclass ua_lcr_c extends uvm_reg;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:11: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass ua_lcr_c extends uvm_reg;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_char_lngth { char_lngth.value != 2\'b00; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_break_ctrl { break_ctrl.value == 1\'b0; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:24: syntax error, unexpected ::, expecting \';\'\n char_lngth = uvm_reg_field::type_id::create("char_lngth");\n ^~\n : ... Perhaps \'uvm_reg_field\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:25: Unsupported: this\n char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>0, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:25: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n char_lngth.configure(this, 2, 0, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>0, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:26: syntax error, unexpected ::, expecting \';\'\n num_stop_bits = uvm_reg_field::type_id::create("num_stop_bits");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:27: Unsupported: this\n num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>2, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:27: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n num_stop_bits.configure(this, 1, 2, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>2, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:28: syntax error, unexpected ::, expecting \';\'\n p_en = uvm_reg_field::type_id::create("p_en");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:29: Unsupported: this\n p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>3, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:29: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n p_en.configure(this, 1, 3, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>3, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:30: syntax error, unexpected ::, expecting \';\'\n parity_even = uvm_reg_field::type_id::create("parity_even");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:31: Unsupported: this\n parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>4, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:31: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n parity_even.configure(this, 1, 4, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>4, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:32: syntax error, unexpected ::, expecting \';\'\n parity_sticky = uvm_reg_field::type_id::create("parity_sticky");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:33: Unsupported: this\n parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>5, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:33: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n parity_sticky.configure(this, 1, 5, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>5, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:34: syntax error, unexpected ::, expecting \';\'\n break_ctrl = uvm_reg_field::type_id::create("break_ctrl");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:35: Unsupported: this\n break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>6, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:35: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n break_ctrl.configure(this, 1, 6, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>6, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:36: syntax error, unexpected ::, expecting \';\'\n div_latch_access = uvm_reg_field::type_id::create("div_latch_access");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:37: Unsupported: this\n div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>7, 1, 1, 1);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:37: Define or directive not defined: \'`UVM_REG_DATA_WIDTH\'\n div_latch_access.configure(this, 1, 7, "RW", 0, `UVM_REG_DATA_WIDTH\'h03>>7, 1, 1, 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:40: Define or directive not defined: \'`uvm_register_cb\'\n `uvm_register_cb(ua_lcr_c, uvm_reg_cbs)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:40: syntax error, unexpected \'(\'\n `uvm_register_cb(ua_lcr_c, uvm_reg_cbs)\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:41: Define or directive not defined: \'`uvm_set_super_type\'\n `uvm_set_super_type(ua_lcr_c, uvm_reg)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:42: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(ua_lcr_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:43: Unsupported: new constructor\n function new(input string name="unnamed-ua_lcr_c");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: super\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: new with arguments\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:44: Unsupported: dotted new\n super.new(name, 8, UVM_NO_COVERAGE);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-4_ua_lcr.sv:46: syntax error, unexpected endclass\nendclass : ua_lcr_c\n^~~~~~~~\n%Error: Exiting due to 34 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,515 | function | function new(input string name="unnamed-ua_lcr_c");
super.new(name, 8, UVM_NO_COVERAGE);
endfunction | function new(input string name="unnamed-ua_lcr_c"); |
super.new(name, 8, UVM_NO_COVERAGE);
endfunction | 0 |
140,451 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv | 90,320,290 | ex9-6_extend_rf.sv | sv | 28 | 79 | [] | [] | [] | null | line:13: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:14: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:15: Cannot find include file: uart_ctrl_regs.sv\n`include "uart_ctrl_regs.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:13: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:16: Unsupported: classes\nclass nocheck_rf_c extends uart_ctrl_rf_c;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass nocheck_rf_c extends uart_ctrl_rf_c;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:19: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:23: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(nocheck_rf_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:23: syntax error, unexpected \'(\'\n `uvm_object_utils(nocheck_rf_c)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:24: Unsupported: new constructor\n function new(input string name="rf");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:27: syntax error, unexpected endclass\nendclass : nocheck_rf_c\n^~~~~~~~\n%Error: Exiting due to 13 error(s)\n' | 308,517 | function | function void build();
super.build();
ua_int_id.priority_bit.set_compare(UVM_NO_CHECK);
endfunction | function void build(); |
super.build();
ua_int_id.priority_bit.set_compare(UVM_NO_CHECK);
endfunction | 0 |
140,452 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv | 90,320,290 | ex9-6_extend_rf.sv | sv | 28 | 79 | [] | [] | [] | null | line:13: before: "import" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:14: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:15: Cannot find include file: uart_ctrl_regs.sv\n`include "uart_ctrl_regs.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:13: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:16: Unsupported: classes\nclass nocheck_rf_c extends uart_ctrl_rf_c;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass nocheck_rf_c extends uart_ctrl_rf_c;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:19: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:23: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(nocheck_rf_c)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:23: syntax error, unexpected \'(\'\n `uvm_object_utils(nocheck_rf_c)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:24: Unsupported: new constructor\n function new(input string name="rf");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:25: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-6_extend_rf.sv:27: syntax error, unexpected endclass\nendclass : nocheck_rf_c\n^~~~~~~~\n%Error: Exiting due to 13 error(s)\n' | 308,517 | function | function new(input string name="rf");
super.new(name);
endfunction | function new(input string name="rf"); |
super.new(name);
endfunction | 0 |
140,453 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv | 90,320,290 | ex9-7_uart_ctrl_env.sv | sv | 67 | 96 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: Unsupported: classes\nclass uart_ctrl_env extends uvm_env; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_env extends uvm_env; \n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:17: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:18: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:19: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg2apb, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:20: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:21: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: scoped class reference\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:41: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No apb_slave_config ..", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: scoped class reference\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 21 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,518 | function | function new(input string name, input uvm_component parent=null);
super.new(name,parent);
endfunction | function new(input string name, input uvm_component parent=null); |
super.new(name,parent);
endfunction | 0 |
140,454 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv | 90,320,290 | ex9-7_uart_ctrl_env.sv | sv | 67 | 96 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: Unsupported: classes\nclass uart_ctrl_env extends uvm_env; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_env extends uvm_env; \n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:17: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:18: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:19: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg2apb, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:20: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:21: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: scoped class reference\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:41: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No apb_slave_config ..", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: scoped class reference\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 21 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,518 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_env
function void uart_ctrl_env::build_phase(uvm_phase phase);
uart_config uart_cfg;
apb_slave_config apb_slave_cfg;
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "No uart_ctrl_config creating...", UVM_LOW)
set_inst_override_by_type("cfg", uart_ctrl_config::get_type(),
default_uart_ctrl_config::get_type());
cfg = uart_ctrl_config::type_id::create("cfg");
end
if (apb_slave_cfg == null)
if (!uvm_config_db#(apb_slave_config)::get(this, "", "apb_slave_cfg", apb_slave_cfg)) begin
`uvm_info("NOCONFIG", "No apb_slave_config ..", UVM_LOW)
apb_slave_cfg = cfg.apb_cfg.slave_configs[0];
end
uvm_config_object::set(this, "monitor", "cfg", cfg);
uart_cfg = cfg.uart_cfg;
reg2apb = reg_to_apb_adapter::type_id::create("reg2apb");
apb_predictor = uvm_reg_predictor#(apb_transfer)::type_id::create("apb_predictor", this);
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_env
function void uart_ctrl_env::build_phase(uvm_phase phase);
uart_config uart_cfg;
apb_slave_config apb_slave_cfg;
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "No uart_ctrl_config creating...", UVM_LOW)
set_inst_override_by_type("cfg", uart_ctrl_config::get_type(),
default_uart_ctrl_config::get_type());
cfg = uart_ctrl_config::type_id::create("cfg");
end
if (apb_slave_cfg == null)
if (!uvm_config_db#(apb_slave_config)::get(this, "", "apb_slave_cfg", apb_slave_cfg)) begin
`uvm_info("NOCONFIG", "No apb_slave_config ..", UVM_LOW)
apb_slave_cfg = cfg.apb_cfg.slave_configs[0];
end
uvm_config_object::set(this, "monitor", "cfg", cfg);
uart_cfg = cfg.uart_cfg;
reg2apb = reg_to_apb_adapter::type_id::create("reg2apb");
apb_predictor = uvm_reg_predictor#(apb_transfer)::type_id::create("apb_predictor", this);
endfunction | 0 |
140,455 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv | 90,320,290 | ex9-7_uart_ctrl_env.sv | sv | 67 | 96 | [] | [] | [] | null | line:6: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: Unsupported: classes\nclass uart_ctrl_env extends uvm_env; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:6: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_env extends uvm_env; \n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:17: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:18: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:19: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg2apb, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:20: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:21: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:29: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: scoped class reference\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:30: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:41: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No apb_slave_config ..", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: Hierarchical class references\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: Unsupported: scoped class reference\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:34: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_env::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-7_uart_ctrl_env.sv:61: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 21 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,518 | function | function void uart_ctrl_env::connect_phase(uvm_phase phase);
super.connect_phase(phase);
apb_predictor.map = reg_model.default_map;
apb_predictor.adapter = reg2apb;
endfunction | function void uart_ctrl_env::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
apb_predictor.map = reg_model.default_map;
apb_predictor.adapter = reg2apb;
endfunction | 0 |
140,456 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv | 90,320,290 | ex9-8_uart_ctrl_tb.sv | sv | 131 | 96 | [] | [] | [] | null | line:11: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:29: syntax error, unexpected IDENTIFIER\n uvm_table_printer printer = new();\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:32: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:33: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:34: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:35: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:36: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:49: syntax error, unexpected endclass\nendclass : uart_ctrl_tb\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:51: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:54: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:55: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config, creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:71: syntax error, unexpected ::\n if (coverage_enable == 1) uvm_reg::include_coverage("*", UVM_CVR_ALL);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:72: syntax error, unexpected ::, expecting \';\'\n reg_model = uart_ctrl_reg_model_c::type_id::create("reg_model");\n ^~\n : ... Perhaps \'uart_ctrl_reg_model_c\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:77: syntax error, unexpected ::\n uvm_config_object::set(this, "*", "reg_model", reg_model);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:80: syntax error, unexpected ::, expecting \';\'\n apb0 = apb_pkg::apb_env::type_id::create("apb0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:81: syntax error, unexpected ::, expecting \';\'\n uart0 = uart_pkg::uart_env::type_id::create("uart0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:82: syntax error, unexpected ::, expecting \';\'\n uart_ctrl0 = uart_ctrl_env::type_id::create("uart_ctrl0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:83: syntax error, unexpected ::, expecting \';\'\n virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Hierarchical class references\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: scoped class reference\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:47: Unsupported: Out of class block function declaration\n extern virtual task reset_reg_model();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::reset_reg_model();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: scoped class reference\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Out of class block function declaration\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:119: Unsupported: wait statements\n wait (top.reset == 1)\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: scoped class reference\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Out of class block function declaration\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 40 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,519 | function | function new(input string name, input uvm_component parent=null);
super.new(name,parent);
endfunction | function new(input string name, input uvm_component parent=null); |
super.new(name,parent);
endfunction | 0 |
140,457 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv | 90,320,290 | ex9-8_uart_ctrl_tb.sv | sv | 131 | 96 | [] | [] | [] | null | line:11: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:29: syntax error, unexpected IDENTIFIER\n uvm_table_printer printer = new();\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:32: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:33: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:34: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:35: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:36: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:49: syntax error, unexpected endclass\nendclass : uart_ctrl_tb\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:51: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:54: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:55: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config, creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:71: syntax error, unexpected ::\n if (coverage_enable == 1) uvm_reg::include_coverage("*", UVM_CVR_ALL);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:72: syntax error, unexpected ::, expecting \';\'\n reg_model = uart_ctrl_reg_model_c::type_id::create("reg_model");\n ^~\n : ... Perhaps \'uart_ctrl_reg_model_c\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:77: syntax error, unexpected ::\n uvm_config_object::set(this, "*", "reg_model", reg_model);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:80: syntax error, unexpected ::, expecting \';\'\n apb0 = apb_pkg::apb_env::type_id::create("apb0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:81: syntax error, unexpected ::, expecting \';\'\n uart0 = uart_pkg::uart_env::type_id::create("uart0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:82: syntax error, unexpected ::, expecting \';\'\n uart_ctrl0 = uart_ctrl_env::type_id::create("uart_ctrl0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:83: syntax error, unexpected ::, expecting \';\'\n virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Hierarchical class references\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: scoped class reference\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:47: Unsupported: Out of class block function declaration\n extern virtual task reset_reg_model();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::reset_reg_model();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: scoped class reference\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Out of class block function declaration\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:119: Unsupported: wait statements\n wait (top.reset == 1)\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: scoped class reference\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Out of class block function declaration\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 40 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,519 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task reset_reg_model();
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "No uart_ctrl_config, creating...", UVM_LOW)
cfg = uart_ctrl_config::type_id::create("cfg", this);
cfg.apb_cfg.add_master("master", UVM_ACTIVE);
cfg.apb_cfg.add_slave("uart0", 32'h000000, 32'h81FFFF, 0, UVM_PASSIVE);
`uvm_info(get_type_name(), {"Printing cfg:\n", cfg.sprint()}, UVM_MEDIUM)
end
uvm_config_object::set(this, "apb0", "cfg", cfg.apb_cfg);
uvm_config_object::set(this, "uart0", "cfg", cfg.uart_cfg);
uvm_config_object::set(this, "uart_ctrl0", "cfg", cfg);
uvm_config_object::set(this, "virtual_sequencer", "cfg", cfg);
uvm_config_object::set(this, "uart_ctrl0", "apb_slave_cfg", cfg.apb_cfg.slave_configs[0]);
if (reg_model == null) begin
if (coverage_enable == 1) uvm_reg::include_coverage("*", UVM_CVR_ALL);
reg_model = uart_ctrl_reg_model_c::type_id::create("reg_model");
reg_model.build();
reg_model.lock_model();
end
uvm_config_object::set(this, "*", "reg_model", reg_model);
apb0 = apb_pkg::apb_env::type_id::create("apb0",this);
uart0 = uart_pkg::uart_env::type_id::create("uart0",this);
uart_ctrl0 = uart_ctrl_env::type_id::create("uart_ctrl0",this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer",this);
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual task reset_reg_model();
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "No uart_ctrl_config, creating...", UVM_LOW)
cfg = uart_ctrl_config::type_id::create("cfg", this);
cfg.apb_cfg.add_master("master", UVM_ACTIVE);
cfg.apb_cfg.add_slave("uart0", 32'h000000, 32'h81FFFF, 0, UVM_PASSIVE);
`uvm_info(get_type_name(), {"Printing cfg:\n", cfg.sprint()}, UVM_MEDIUM)
end
uvm_config_object::set(this, "apb0", "cfg", cfg.apb_cfg);
uvm_config_object::set(this, "uart0", "cfg", cfg.uart_cfg);
uvm_config_object::set(this, "uart_ctrl0", "cfg", cfg);
uvm_config_object::set(this, "virtual_sequencer", "cfg", cfg);
uvm_config_object::set(this, "uart_ctrl0", "apb_slave_cfg", cfg.apb_cfg.slave_configs[0]);
if (reg_model == null) begin
if (coverage_enable == 1) uvm_reg::include_coverage("*", UVM_CVR_ALL);
reg_model = uart_ctrl_reg_model_c::type_id::create("reg_model");
reg_model.build();
reg_model.lock_model();
end
uvm_config_object::set(this, "*", "reg_model", reg_model);
apb0 = apb_pkg::apb_env::type_id::create("apb0",this);
uart0 = uart_pkg::uart_env::type_id::create("uart0",this);
uart_ctrl0 = uart_ctrl_env::type_id::create("uart_ctrl0",this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer",this);
endfunction | 0 |
140,458 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv | 90,320,290 | ex9-8_uart_ctrl_tb.sv | sv | 131 | 96 | [] | [] | [] | null | line:11: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:11: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:29: syntax error, unexpected IDENTIFIER\n uvm_table_printer printer = new();\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:32: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:33: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(reg_model, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:34: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:35: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:36: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: Unsupported: new constructor\n function new(input string name, input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(input string name, input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:49: syntax error, unexpected endclass\nendclass : uart_ctrl_tb\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:51: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:54: syntax error, unexpected \'#\'\n if (!uvm_config_db#(uart_ctrl_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:55: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "No uart_ctrl_config, creating...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:59: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), {"Printing cfg:\\n", cfg.sprint()}, UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:71: syntax error, unexpected ::\n if (coverage_enable == 1) uvm_reg::include_coverage("*", UVM_CVR_ALL);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:72: syntax error, unexpected ::, expecting \';\'\n reg_model = uart_ctrl_reg_model_c::type_id::create("reg_model");\n ^~\n : ... Perhaps \'uart_ctrl_reg_model_c\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:77: syntax error, unexpected ::\n uvm_config_object::set(this, "*", "reg_model", reg_model);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:80: syntax error, unexpected ::, expecting \';\'\n apb0 = apb_pkg::apb_env::type_id::create("apb0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:81: syntax error, unexpected ::, expecting \';\'\n uart0 = uart_pkg::uart_env::type_id::create("uart0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:82: syntax error, unexpected ::, expecting \';\'\n uart_ctrl0 = uart_ctrl_env::type_id::create("uart_ctrl0",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:83: syntax error, unexpected ::, expecting \';\'\n virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Hierarchical class references\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: scoped class reference\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:47: Unsupported: Out of class block function declaration\n extern virtual task reset_reg_model();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::reset_reg_model();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: scoped class reference\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:87: Unsupported: Out of class block function declaration\n function void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:120: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Resetting Registers", UVM_LOW);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:119: Unsupported: wait statements\n wait (top.reset == 1)\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: Hierarchical class references\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: Unsupported: scoped class reference\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:117: Unsupported: Out of class block function declaration\ntask uart_ctrl_tb::reset_reg_model();\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-8_uart_ctrl_tb.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask uart_ctrl_tb::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 40 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,519 | function | function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
reg_model.default_map.set_sequencer(apb0.master.sequencer, uart_ctrl0.reg2apb);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
uart_ctrl0.set_slave_config(cfg.apb_cfg.slave_configs[0], 0);
uart0.Rx.monitor.frame_collected_port.connect(uart_ctrl0.monitor.uart_rx_in);
uart0.Tx.monitor.frame_collected_port.connect(uart_ctrl0.monitor.uart_tx_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.monitor.apb_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.apb_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.apb_predictor.bus_in);
uart_ctrl0.uart_cfg_out.connect(uart0.dut_cfg_port_in);
endfunction | function void uart_ctrl_tb::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
reg_model.default_map.set_sequencer(apb0.master.sequencer, uart_ctrl0.reg2apb);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
uart_ctrl0.set_slave_config(cfg.apb_cfg.slave_configs[0], 0);
uart0.Rx.monitor.frame_collected_port.connect(uart_ctrl0.monitor.uart_rx_in);
uart0.Tx.monitor.frame_collected_port.connect(uart_ctrl0.monitor.uart_tx_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.monitor.apb_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.apb_in);
apb0.bus_monitor.item_collected_port.connect(uart_ctrl0.apb_predictor.bus_in);
uart_ctrl0.uart_cfg_out.connect(uart0.dut_cfg_port_in);
endfunction | 0 |
140,459 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv | 90,320,290 | ex9-9_base_reg_seq.sv | sv | 67 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:7: Unsupported: classes\nclass base_reg_seq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass base_reg_seq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:11: Unsupported: new constructor\n function new(string name="base_reg_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:15: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_reg_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:15: syntax error, unexpected \'(\'\n `uvm_object_utils(base_reg_seq)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:25: syntax error, unexpected IDENTIFIER\n uvm_object temp_object;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:28: syntax error, unexpected ::\n if (uvm_config_object::get(get_sequencer(), "", "reg_model", temp_object))\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:29: Unsupported or unknown PLI call: $cast\n if (!($cast(model, temp_object)))\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:30: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("BAD_CONFIG",\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:34: Unsupported or unknown PLI call: $cast\n if (!($cast(model, temp_reg_block)))\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:35: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("BAD_CONFIG",\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:38: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("NO_REG_CONFIG", "Register model is not set. Exiting..")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:48: syntax error, unexpected endtask\n endtask : pre_start\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:56: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:58: syntax error, unexpected endtask\n endtask\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:62: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:64: syntax error, unexpected endtask\n endtask\n ^~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,520 | function | function new(string name="base_reg_seq");
super.new(name);
endfunction | function new(string name="base_reg_seq"); |
super.new(name);
endfunction | 0 |
140,460 | data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv | 90,320,290 | ex9-9_base_reg_seq.sv | sv | 67 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:7: Unsupported: classes\nclass base_reg_seq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass base_reg_seq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:11: Unsupported: new constructor\n function new(string name="base_reg_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:15: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_reg_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:15: syntax error, unexpected \'(\'\n `uvm_object_utils(base_reg_seq)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:25: syntax error, unexpected IDENTIFIER\n uvm_object temp_object;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:28: syntax error, unexpected ::\n if (uvm_config_object::get(get_sequencer(), "", "reg_model", temp_object))\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:29: Unsupported or unknown PLI call: $cast\n if (!($cast(model, temp_object)))\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:30: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("BAD_CONFIG",\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:34: Unsupported or unknown PLI call: $cast\n if (!($cast(model, temp_reg_block)))\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:35: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("BAD_CONFIG",\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:38: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("NO_REG_CONFIG", "Register model is not set. Exiting..")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:48: syntax error, unexpected endtask\n endtask : pre_start\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:56: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:58: syntax error, unexpected endtask\n endtask\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:62: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/9_register_and_memory_package/ex9-9_base_reg_seq.sv:64: syntax error, unexpected endtask\n endtask\n ^~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,520 | function | function void get_model();
uvm_object temp_object;
uvm_reg_block temp_reg_block;
if (model==null) begin
if (uvm_config_object::get(get_sequencer(), "", "reg_model", temp_object))
if (!($cast(model, temp_object)))
`uvm_fatal("BAD_CONFIG",
"Sequence reg model is not derived from uart_ctrl_reg_model_c.")
else if (uvm_config_db#(uvm_reg_block)::get(get_sequencer(), "",
"reg_model", temp_reg_block))
if (!($cast(model, temp_reg_block)))
`uvm_fatal("BAD_CONFIG",
"Sequence reg model is not derived from uart_ctrl_reg_model_c.")
else
`uvm_fatal("NO_REG_CONFIG", "Register model is not set. Exiting..")
end
endfunction | function void get_model(); |
uvm_object temp_object;
uvm_reg_block temp_reg_block;
if (model==null) begin
if (uvm_config_object::get(get_sequencer(), "", "reg_model", temp_object))
if (!($cast(model, temp_object)))
`uvm_fatal("BAD_CONFIG",
"Sequence reg model is not derived from uart_ctrl_reg_model_c.")
else if (uvm_config_db#(uvm_reg_block)::get(get_sequencer(), "",
"reg_model", temp_reg_block))
if (!($cast(model, temp_reg_block)))
`uvm_fatal("BAD_CONFIG",
"Sequence reg model is not derived from uart_ctrl_reg_model_c.")
else
`uvm_fatal("NO_REG_CONFIG", "Register model is not set. Exiting..")
end
endfunction | 0 |
140,461 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv | 90,320,290 | simple_test1.sv | sv | 84 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:9: Cannot find include file: sv/apb_master_seq_lib.sv\n`include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.sv\n sv/apb_master_seq_lib.sv\n sv/apb_master_seq_lib.sv.v\n sv/apb_master_seq_lib.sv.sv\n obj_dir/sv/apb_master_seq_lib.sv\n obj_dir/sv/apb_master_seq_lib.sv.v\n obj_dir/sv/apb_master_seq_lib.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:10: Cannot find include file: sv/apb_slave_seq_lib.sv\n`include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: Unsupported: classes\nclass simple_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:17: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: Unsupported: classes\nclass simple_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:50: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:77: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n' | 308,530 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,462 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv | 90,320,290 | simple_test1.sv | sv | 84 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:9: Cannot find include file: sv/apb_master_seq_lib.sv\n`include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.sv\n sv/apb_master_seq_lib.sv\n sv/apb_master_seq_lib.sv.v\n sv/apb_master_seq_lib.sv.sv\n obj_dir/sv/apb_master_seq_lib.sv\n obj_dir/sv/apb_master_seq_lib.sv.v\n obj_dir/sv/apb_master_seq_lib.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:10: Cannot find include file: sv/apb_slave_seq_lib.sv\n`include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: Unsupported: classes\nclass simple_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:17: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: Unsupported: classes\nclass simple_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:50: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:77: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n' | 308,530 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
endfunction | 0 |
140,463 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv | 90,320,290 | simple_test1.sv | sv | 84 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:9: Cannot find include file: sv/apb_master_seq_lib.sv\n`include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.sv\n sv/apb_master_seq_lib.sv\n sv/apb_master_seq_lib.sv.v\n sv/apb_master_seq_lib.sv.sv\n obj_dir/sv/apb_master_seq_lib.sv\n obj_dir/sv/apb_master_seq_lib.sv.v\n obj_dir/sv/apb_master_seq_lib.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:10: Cannot find include file: sv/apb_slave_seq_lib.sv\n`include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: Unsupported: classes\nclass simple_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:17: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: Unsupported: classes\nclass simple_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:50: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:77: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n' | 308,530 | function | function new(string name = "simple_test", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "simple_test", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,464 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv | 90,320,290 | simple_test1.sv | sv | 84 | 81 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:9: Cannot find include file: sv/apb_master_seq_lib.sv\n`include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples,data/full_repos/permissive/90320290/sv/apb_master_seq_lib.sv.sv\n sv/apb_master_seq_lib.sv\n sv/apb_master_seq_lib.sv.v\n sv/apb_master_seq_lib.sv.sv\n obj_dir/sv/apb_master_seq_lib.sv\n obj_dir/sv/apb_master_seq_lib.sv.v\n obj_dir/sv/apb_master_seq_lib.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:10: Cannot find include file: sv/apb_slave_seq_lib.sv\n`include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: Unsupported: classes\nclass simple_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:14: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:17: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: Unsupported: classes\nclass simple_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:48: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:50: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:59: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/examples/simple_test1.sv:77: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n' | 308,530 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_int::set(this, "*", "coverage_enable", 0);
uvm_config_db #(uvm_object_wrapper)::set(this,
"tb0.apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
tb0 = simple_tb::type_id::create("tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uvm_config_int::set(this, "*", "coverage_enable", 0);
uvm_config_db #(uvm_object_wrapper)::set(this,
"tb0.apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
tb0 = simple_tb::type_id::create("tb0", this);
endfunction | 0 |
140,465 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv | 90,320,290 | apb_master_driver_orig.sv | sv | 168 | 92 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: Unsupported: classes\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:36: syntax error, unexpected IDENTIFIER\n apb_config cfg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:39: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:40: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:41: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:49: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:53: syntax error, unexpected extern\n extern virtual protected task reset();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:62: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:64: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:65: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:70: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:71: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:72: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:79: End label \'run_phase\' does not match begin label \'get_and_drive\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: Hierarchical class references\ntask apb_master_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: scoped class reference\ntask apb_master_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:52: Unsupported: Out of class block function declaration\n extern virtual protected task get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:87: Unsupported: fork statements\n fork \n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:88: syntax error, unexpected \'@\'\n @(negedge vif.preset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:90: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", "get_and_drive: Reset dropped", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:98: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:106: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:113: Unsupported: wait statements\n wait(!vif.preset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:121: syntax error, unexpected endtask\nendtask : reset\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:128: syntax error, unexpected \'@\'\n repeat(trans.transmit_delay) @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:152: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:158: syntax error, unexpected \'@\'\n @(posedge vif.pclock iff vif.pready); \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:164: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,541 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,466 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv | 90,320,290 | apb_master_driver_orig.sv | sv | 168 | 92 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: Unsupported: classes\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:36: syntax error, unexpected IDENTIFIER\n apb_config cfg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:39: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:40: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:41: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:49: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:53: syntax error, unexpected extern\n extern virtual protected task reset();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:62: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:64: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:65: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:70: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:71: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:72: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:79: End label \'run_phase\' does not match begin label \'get_and_drive\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: Hierarchical class references\ntask apb_master_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: scoped class reference\ntask apb_master_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:52: Unsupported: Out of class block function declaration\n extern virtual protected task get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:87: Unsupported: fork statements\n fork \n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:88: syntax error, unexpected \'@\'\n @(negedge vif.preset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:90: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", "get_and_drive: Reset dropped", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:98: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:106: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:113: Unsupported: wait statements\n wait(!vif.preset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:121: syntax error, unexpected endtask\nendtask : reset\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:128: syntax error, unexpected \'@\'\n repeat(trans.transmit_delay) @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:152: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:158: syntax error, unexpected \'@\'\n @(posedge vif.pclock iff vif.pready); \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:164: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,541 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual protected task get_and_drive();
extern virtual protected task reset();
extern virtual protected task drive_transfer (apb_transfer trans);
extern virtual protected task drive_address_phase (apb_transfer trans);
extern virtual protected task drive_data_phase (apb_transfer trans);
endclass : apb_master_driver
function void apb_master_driver::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "apb_config not set for this component")
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual task run_phase(uvm_phase phase);
extern virtual protected task get_and_drive();
extern virtual protected task reset();
extern virtual protected task drive_transfer (apb_transfer trans);
extern virtual protected task drive_address_phase (apb_transfer trans);
extern virtual protected task drive_data_phase (apb_transfer trans);
endclass : apb_master_driver
function void apb_master_driver::build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_error("NOCONFIG", "apb_config not set for this component")
endfunction | 0 |
140,467 | data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv | 90,320,290 | apb_master_driver_orig.sv | sv | 168 | 92 | [] | ['apache license'] | ['all rights reserved'] | null | line:30: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: Unsupported: classes\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:30: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_driver extends uvm_driver #(apb_transfer);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:36: syntax error, unexpected IDENTIFIER\n apb_config cfg;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:39: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_driver)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:40: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:41: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:49: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:53: syntax error, unexpected extern\n extern virtual protected task reset();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:62: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:64: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:65: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:70: Unsupported: super\n super.connect_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:71: syntax error, unexpected \'#\'\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:72: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Warning-ENDLABEL: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:79: End label \'run_phase\' does not match begin label \'get_and_drive\'\nendtask : run_phase\n ^~~~~~~~~\n ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: Hierarchical class references\ntask apb_master_driver::get_and_drive();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:82: Unsupported: scoped class reference\ntask apb_master_driver::get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:52: Unsupported: Out of class block function declaration\n extern virtual protected task get_and_drive();\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:87: Unsupported: fork statements\n fork \n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:88: syntax error, unexpected \'@\'\n @(negedge vif.preset)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:90: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", "get_and_drive: Reset dropped", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:98: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:106: syntax error, unexpected end, expecting join or join_any or join_none\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:113: Unsupported: wait statements\n wait(!vif.preset);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:115: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER", $sformatf("Reset observed"), UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:121: syntax error, unexpected endtask\nendtask : reset\n^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:128: syntax error, unexpected \'@\'\n repeat(trans.transmit_delay) @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: Define or directive not defined: \'`uvm_info\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:133: syntax error, unexpected \',\'\n `uvm_info("APB_MASTER_DRIVER_TR", $sformatf("APB Finished Driving Transfer \\n%s",\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:152: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:158: syntax error, unexpected \'@\'\n @(posedge vif.pclock iff vif.pready); \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/apb/sv/apb_master_driver_orig.sv:164: syntax error, unexpected \'@\'\n @(posedge vif.pclock);\n ^\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,541 | function | function void apb_master_driver::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | function void apb_master_driver::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | 0 |
140,471 | data/full_repos/permissive/90330506/verilog/src/CC_controller.v | 90,330,506 | CC_controller.v | v | 42 | 68 | [] | [] | [] | null | line:13: before: ";" | null | 1: b"%Error: data/full_repos/permissive/90330506/verilog/src/CC_controller.v:13: Define or directive not defined: '`ENV_BITDEPTH'\n parameter env_bitdepth = `ENV_BITDEPTH; \n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/src/CC_controller.v:13: syntax error, unexpected ';', expecting TYPE-IDENTIFIER\n parameter env_bitdepth = `ENV_BITDEPTH; \n ^\n%Error: Exiting due to 2 error(s)\n" | 308,560 | module | module CC_controller(
i_clk,
i_reset,
i_SPI_flag,
i_SPI_note_status,
i_SPI_voice_index,
i_voice_index,
i_pipeline_state,
i_sample,
o_voice_index_next,
o_sample
);
parameter env_bitdepth = `ENV_BITDEPTH;
input wire i_clk;
input wire i_reset;
input wire i_SPI_flag;
input wire i_SPI_note_status;
input wire [7:0] i_SPI_voice_index;
input wire[7:0] i_voice_index;
input wire[1:0] i_pipeline_state;
input wire signed [15:0] i_sample;
output reg [7:0] o_voice_index_next;
output reg signed [15:0] o_sample;
reg [env_bitdepth-1:0] attackCoef = 24'd16775986;
reg [env_bitdepth-1:0] decayCoef = 24'd16769492;
reg [env_bitdepth-1:0] sustainLevel = 24'd11744051;
reg [env_bitdepth-1:0] releaseCoef = 24'd16769492;
reg [env_bitdepth-1:0] attackBase = 24'd1599;
reg [env_bitdepth-1:0] decayBase = 24'd5406;
reg signed [env_bitdepth-1:0] releaseBase = -24'sd1;
endmodule | module CC_controller(
i_clk,
i_reset,
i_SPI_flag,
i_SPI_note_status,
i_SPI_voice_index,
i_voice_index,
i_pipeline_state,
i_sample,
o_voice_index_next,
o_sample
); |
parameter env_bitdepth = `ENV_BITDEPTH;
input wire i_clk;
input wire i_reset;
input wire i_SPI_flag;
input wire i_SPI_note_status;
input wire [7:0] i_SPI_voice_index;
input wire[7:0] i_voice_index;
input wire[1:0] i_pipeline_state;
input wire signed [15:0] i_sample;
output reg [7:0] o_voice_index_next;
output reg signed [15:0] o_sample;
reg [env_bitdepth-1:0] attackCoef = 24'd16775986;
reg [env_bitdepth-1:0] decayCoef = 24'd16769492;
reg [env_bitdepth-1:0] sustainLevel = 24'd11744051;
reg [env_bitdepth-1:0] releaseCoef = 24'd16769492;
reg [env_bitdepth-1:0] attackBase = 24'd1599;
reg [env_bitdepth-1:0] decayBase = 24'd5406;
reg signed [env_bitdepth-1:0] releaseBase = -24'sd1;
endmodule | 3 |
140,474 | data/full_repos/permissive/90330506/verilog/src/midi_synth.v | 90,330,506 | midi_synth.v | v | 35 | 401 | [] | [] | [] | [(3, 34)] | null | null | 1: b"%Error: data/full_repos/permissive/90330506/verilog/src/midi_synth.v:26: Cannot find file containing module: 'spi_controller'\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_controller\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_controller.v\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_controller.sv\n spi_controller\n spi_controller.v\n spi_controller.sv\n obj_dir/spi_controller\n obj_dir/spi_controller.v\n obj_dir/spi_controller.sv\n%Error: data/full_repos/permissive/90330506/verilog/src/midi_synth.v:27: Cannot find file containing module: 'voice_controller'\n voice_controller voice_controller(.i_clk(i_clk),.i_reset(i_reset),.i_SPI_note_status(SPI_note_status),.i_SPI_voice_index(SPI_voice_index),.i_SPI_tuning_code(SPI_tuning_code),.i_SPI_velocity(SPI_velocity),.i_SPI_flag_dds(SPI_flag_dds),.i_SPI_flag_adsr(SPI_flag_adsr),.o_mixed_sample(output_sample));\n ^~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 308,563 | module | module midi_synth(
input wire i_clk,
input wire i_reset,
input wire i_SPI_sclk,
input wire i_SPI_mosi,
output wire [15:0] o_dac_out,
output wire [7:0] leds_0,
output wire [7:0] leds_1,
output wire [7:0] leds_2,
output wire [1:0] byte_counter_debug
);
wire SPI_note_status;
wire [7:0] SPI_voice_index;
wire [31:0] SPI_tuning_code;
wire [6:0] SPI_velocity;
wire SPI_flag_dds;
wire SPI_flag_adsr;
wire signed [23:0] output_sample;
spi_controller spi_controller(.i_clk(i_clk),.i_reset(i_reset),.i_SPI_sclk(i_SPI_sclk),.i_SPI_mosi(i_SPI_mosi),.o_SPI_note_status(SPI_note_status),.o_SPI_voice_index(SPI_voice_index),.o_SPI_tuning_code(SPI_tuning_code),.o_SPI_velocity(SPI_velocity),.o_SPI_flag_dds(SPI_flag_dds),.o_SPI_flag_adsr(SPI_flag_adsr),.leds_0(leds_0),.leds_1(leds_1),.leds_2(leds_2),.byte_counter_debug(byte_counter_debug));
voice_controller voice_controller(.i_clk(i_clk),.i_reset(i_reset),.i_SPI_note_status(SPI_note_status),.i_SPI_voice_index(SPI_voice_index),.i_SPI_tuning_code(SPI_tuning_code),.i_SPI_velocity(SPI_velocity),.i_SPI_flag_dds(SPI_flag_dds),.i_SPI_flag_adsr(SPI_flag_adsr),.o_mixed_sample(output_sample));
assign o_dac_out = output_sample[17:2] + 16'sd32768;
endmodule | module midi_synth(
input wire i_clk,
input wire i_reset,
input wire i_SPI_sclk,
input wire i_SPI_mosi,
output wire [15:0] o_dac_out,
output wire [7:0] leds_0,
output wire [7:0] leds_1,
output wire [7:0] leds_2,
output wire [1:0] byte_counter_debug
); |
wire SPI_note_status;
wire [7:0] SPI_voice_index;
wire [31:0] SPI_tuning_code;
wire [6:0] SPI_velocity;
wire SPI_flag_dds;
wire SPI_flag_adsr;
wire signed [23:0] output_sample;
spi_controller spi_controller(.i_clk(i_clk),.i_reset(i_reset),.i_SPI_sclk(i_SPI_sclk),.i_SPI_mosi(i_SPI_mosi),.o_SPI_note_status(SPI_note_status),.o_SPI_voice_index(SPI_voice_index),.o_SPI_tuning_code(SPI_tuning_code),.o_SPI_velocity(SPI_velocity),.o_SPI_flag_dds(SPI_flag_dds),.o_SPI_flag_adsr(SPI_flag_adsr),.leds_0(leds_0),.leds_1(leds_1),.leds_2(leds_2),.byte_counter_debug(byte_counter_debug));
voice_controller voice_controller(.i_clk(i_clk),.i_reset(i_reset),.i_SPI_note_status(SPI_note_status),.i_SPI_voice_index(SPI_voice_index),.i_SPI_tuning_code(SPI_tuning_code),.i_SPI_velocity(SPI_velocity),.i_SPI_flag_dds(SPI_flag_dds),.i_SPI_flag_adsr(SPI_flag_adsr),.o_mixed_sample(output_sample));
assign o_dac_out = output_sample[17:2] + 16'sd32768;
endmodule | 3 |
140,475 | data/full_repos/permissive/90330506/verilog/src/neg_edge_det.v | 90,330,506 | neg_edge_det.v | v | 14 | 31 | [] | [] | [] | [(1, 13)] | null | data/verilator_xmls/1b37ace7-1764-4798-b866-50b37fbd9f7c.xml | null | 308,564 | module | module neg_edge_det(
input wire sig,
input wire clk,
output wire pe
);
reg sig_dly;
always @ (posedge clk) begin
sig_dly <= sig;
end
assign pe = ~sig & sig_dly;
endmodule | module neg_edge_det(
input wire sig,
input wire clk,
output wire pe
); |
reg sig_dly;
always @ (posedge clk) begin
sig_dly <= sig;
end
assign pe = ~sig & sig_dly;
endmodule | 3 |
140,476 | data/full_repos/permissive/90330506/verilog/src/ram.v | 90,330,506 | ram.v | v | 33 | 138 | [] | [] | [] | [(2, 32)] | null | data/verilator_xmls/9a707e2a-36c8-49ab-9cdd-b98e80c8a793.xml | null | 308,566 | module | module ram (i_clk, i_reset, din, mask, addr, write_en, dout);
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input [data_width-1:0] mask;
input wire write_en;
input wire i_clk;
input wire i_reset;
output wire [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge i_clk)
begin
if (i_reset == 1'b1)
;
else if (write_en)
mem[(addr)] <= (din & mask) | (mem[(addr)]&~mask);
end
assign dout = mem[addr];
integer i;
initial
begin
for (i=0; i<(1<<addr_width); i=i+1) mem[i] <= {data_width{1'b0}};
end
endmodule | module ram (i_clk, i_reset, din, mask, addr, write_en, dout); |
parameter addr_width = 8;
parameter data_width = 8;
input [addr_width-1:0] addr;
input [data_width-1:0] din;
input [data_width-1:0] mask;
input wire write_en;
input wire i_clk;
input wire i_reset;
output wire [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0];
always @(posedge i_clk)
begin
if (i_reset == 1'b1)
;
else if (write_en)
mem[(addr)] <= (din & mask) | (mem[(addr)]&~mask);
end
assign dout = mem[addr];
integer i;
initial
begin
for (i=0; i<(1<<addr_width); i=i+1) mem[i] <= {data_width{1'b0}};
end
endmodule | 3 |
140,477 | data/full_repos/permissive/90330506/verilog/src/sine_table.v | 90,330,506 | sine_table.v | v | 1,038 | 39 | [] | [] | [] | [(1, 1037)] | null | data/verilator_xmls/11610ae8-b470-477f-959b-3ede8f2167d2.xml | null | 308,567 | module | module sine_table(
input wire [9:0] theta,
output reg signed [15:0] sine_sample
);
always @(theta) begin
case(theta)
10'd0: sine_sample = -16'sd0;
10'd1: sine_sample = -16'sd201;
10'd2: sine_sample = -16'sd402;
10'd3: sine_sample = -16'sd603;
10'd4: sine_sample = -16'sd804;
10'd5: sine_sample = -16'sd1005;
10'd6: sine_sample = -16'sd1206;
10'd7: sine_sample = -16'sd1407;
10'd8: sine_sample = -16'sd1608;
10'd9: sine_sample = -16'sd1809;
10'd10: sine_sample = -16'sd2009;
10'd11: sine_sample = -16'sd2210;
10'd12: sine_sample = -16'sd2410;
10'd13: sine_sample = -16'sd2611;
10'd14: sine_sample = -16'sd2811;
10'd15: sine_sample = -16'sd3012;
10'd16: sine_sample = -16'sd3212;
10'd17: sine_sample = -16'sd3412;
10'd18: sine_sample = -16'sd3612;
10'd19: sine_sample = -16'sd3811;
10'd20: sine_sample = -16'sd4011;
10'd21: sine_sample = -16'sd4210;
10'd22: sine_sample = -16'sd4410;
10'd23: sine_sample = -16'sd4609;
10'd24: sine_sample = -16'sd4808;
10'd25: sine_sample = -16'sd5007;
10'd26: sine_sample = -16'sd5205;
10'd27: sine_sample = -16'sd5404;
10'd28: sine_sample = -16'sd5602;
10'd29: sine_sample = -16'sd5800;
10'd30: sine_sample = -16'sd5998;
10'd31: sine_sample = -16'sd6195;
10'd32: sine_sample = -16'sd6393;
10'd33: sine_sample = -16'sd6590;
10'd34: sine_sample = -16'sd6786;
10'd35: sine_sample = -16'sd6983;
10'd36: sine_sample = -16'sd7179;
10'd37: sine_sample = -16'sd7375;
10'd38: sine_sample = -16'sd7571;
10'd39: sine_sample = -16'sd7767;
10'd40: sine_sample = -16'sd7962;
10'd41: sine_sample = -16'sd8157;
10'd42: sine_sample = -16'sd8351;
10'd43: sine_sample = -16'sd8545;
10'd44: sine_sample = -16'sd8739;
10'd45: sine_sample = -16'sd8933;
10'd46: sine_sample = -16'sd9126;
10'd47: sine_sample = -16'sd9319;
10'd48: sine_sample = -16'sd9512;
10'd49: sine_sample = -16'sd9704;
10'd50: sine_sample = -16'sd9896;
10'd51: sine_sample = -16'sd10087;
10'd52: sine_sample = -16'sd10278;
10'd53: sine_sample = -16'sd10469;
10'd54: sine_sample = -16'sd10659;
10'd55: sine_sample = -16'sd10849;
10'd56: sine_sample = -16'sd11039;
10'd57: sine_sample = -16'sd11228;
10'd58: sine_sample = -16'sd11417;
10'd59: sine_sample = -16'sd11605;
10'd60: sine_sample = -16'sd11793;
10'd61: sine_sample = -16'sd11980;
10'd62: sine_sample = -16'sd12167;
10'd63: sine_sample = -16'sd12353;
10'd64: sine_sample = -16'sd12539;
10'd65: sine_sample = -16'sd12725;
10'd66: sine_sample = -16'sd12910;
10'd67: sine_sample = -16'sd13094;
10'd68: sine_sample = -16'sd13279;
10'd69: sine_sample = -16'sd13462;
10'd70: sine_sample = -16'sd13645;
10'd71: sine_sample = -16'sd13828;
10'd72: sine_sample = -16'sd14010;
10'd73: sine_sample = -16'sd14191;
10'd74: sine_sample = -16'sd14372;
10'd75: sine_sample = -16'sd14553;
10'd76: sine_sample = -16'sd14732;
10'd77: sine_sample = -16'sd14912;
10'd78: sine_sample = -16'sd15090;
10'd79: sine_sample = -16'sd15269;
10'd80: sine_sample = -16'sd15446;
10'd81: sine_sample = -16'sd15623;
10'd82: sine_sample = -16'sd15800;
10'd83: sine_sample = -16'sd15976;
10'd84: sine_sample = -16'sd16151;
10'd85: sine_sample = -16'sd16325;
10'd86: sine_sample = -16'sd16499;
10'd87: sine_sample = -16'sd16673;
10'd88: sine_sample = -16'sd16846;
10'd89: sine_sample = -16'sd17018;
10'd90: sine_sample = -16'sd17189;
10'd91: sine_sample = -16'sd17360;
10'd92: sine_sample = -16'sd17530;
10'd93: sine_sample = -16'sd17700;
10'd94: sine_sample = -16'sd17869;
10'd95: sine_sample = -16'sd18037;
10'd96: sine_sample = -16'sd18204;
10'd97: sine_sample = -16'sd18371;
10'd98: sine_sample = -16'sd18537;
10'd99: sine_sample = -16'sd18703;
10'd100: sine_sample = -16'sd18868;
10'd101: sine_sample = -16'sd19032;
10'd102: sine_sample = -16'sd19195;
10'd103: sine_sample = -16'sd19357;
10'd104: sine_sample = -16'sd19519;
10'd105: sine_sample = -16'sd19680;
10'd106: sine_sample = -16'sd19841;
10'd107: sine_sample = -16'sd20000;
10'd108: sine_sample = -16'sd20159;
10'd109: sine_sample = -16'sd20317;
10'd110: sine_sample = -16'sd20475;
10'd111: sine_sample = -16'sd20631;
10'd112: sine_sample = -16'sd20787;
10'd113: sine_sample = -16'sd20942;
10'd114: sine_sample = -16'sd21096;
10'd115: sine_sample = -16'sd21250;
10'd116: sine_sample = -16'sd21403;
10'd117: sine_sample = -16'sd21554;
10'd118: sine_sample = -16'sd21705;
10'd119: sine_sample = -16'sd21856;
10'd120: sine_sample = -16'sd22005;
10'd121: sine_sample = -16'sd22154;
10'd122: sine_sample = -16'sd22301;
10'd123: sine_sample = -16'sd22448;
10'd124: sine_sample = -16'sd22594;
10'd125: sine_sample = -16'sd22739;
10'd126: sine_sample = -16'sd22884;
10'd127: sine_sample = -16'sd23027;
10'd128: sine_sample = -16'sd23170;
10'd129: sine_sample = -16'sd23311;
10'd130: sine_sample = -16'sd23452;
10'd131: sine_sample = -16'sd23592;
10'd132: sine_sample = -16'sd23731;
10'd133: sine_sample = -16'sd23870;
10'd134: sine_sample = -16'sd24007;
10'd135: sine_sample = -16'sd24143;
10'd136: sine_sample = -16'sd24279;
10'd137: sine_sample = -16'sd24413;
10'd138: sine_sample = -16'sd24547;
10'd139: sine_sample = -16'sd24680;
10'd140: sine_sample = -16'sd24811;
10'd141: sine_sample = -16'sd24942;
10'd142: sine_sample = -16'sd25072;
10'd143: sine_sample = -16'sd25201;
10'd144: sine_sample = -16'sd25329;
10'd145: sine_sample = -16'sd25456;
10'd146: sine_sample = -16'sd25582;
10'd147: sine_sample = -16'sd25708;
10'd148: sine_sample = -16'sd25832;
10'd149: sine_sample = -16'sd25955;
10'd150: sine_sample = -16'sd26077;
10'd151: sine_sample = -16'sd26198;
10'd152: sine_sample = -16'sd26319;
10'd153: sine_sample = -16'sd26438;
10'd154: sine_sample = -16'sd26556;
10'd155: sine_sample = -16'sd26674;
10'd156: sine_sample = -16'sd26790;
10'd157: sine_sample = -16'sd26905;
10'd158: sine_sample = -16'sd27019;
10'd159: sine_sample = -16'sd27133;
10'd160: sine_sample = -16'sd27245;
10'd161: sine_sample = -16'sd27356;
10'd162: sine_sample = -16'sd27466;
10'd163: sine_sample = -16'sd27575;
10'd164: sine_sample = -16'sd27683;
10'd165: sine_sample = -16'sd27790;
10'd166: sine_sample = -16'sd27896;
10'd167: sine_sample = -16'sd28001;
10'd168: sine_sample = -16'sd28105;
10'd169: sine_sample = -16'sd28208;
10'd170: sine_sample = -16'sd28310;
10'd171: sine_sample = -16'sd28411;
10'd172: sine_sample = -16'sd28510;
10'd173: sine_sample = -16'sd28609;
10'd174: sine_sample = -16'sd28706;
10'd175: sine_sample = -16'sd28803;
10'd176: sine_sample = -16'sd28898;
10'd177: sine_sample = -16'sd28992;
10'd178: sine_sample = -16'sd29085;
10'd179: sine_sample = -16'sd29177;
10'd180: sine_sample = -16'sd29268;
10'd181: sine_sample = -16'sd29358;
10'd182: sine_sample = -16'sd29447;
10'd183: sine_sample = -16'sd29534;
10'd184: sine_sample = -16'sd29621;
10'd185: sine_sample = -16'sd29706;
10'd186: sine_sample = -16'sd29791;
10'd187: sine_sample = -16'sd29874;
10'd188: sine_sample = -16'sd29956;
10'd189: sine_sample = -16'sd30037;
10'd190: sine_sample = -16'sd30117;
10'd191: sine_sample = -16'sd30195;
10'd192: sine_sample = -16'sd30273;
10'd193: sine_sample = -16'sd30349;
10'd194: sine_sample = -16'sd30424;
10'd195: sine_sample = -16'sd30498;
10'd196: sine_sample = -16'sd30571;
10'd197: sine_sample = -16'sd30643;
10'd198: sine_sample = -16'sd30714;
10'd199: sine_sample = -16'sd30783;
10'd200: sine_sample = -16'sd30852;
10'd201: sine_sample = -16'sd30919;
10'd202: sine_sample = -16'sd30985;
10'd203: sine_sample = -16'sd31050;
10'd204: sine_sample = -16'sd31113;
10'd205: sine_sample = -16'sd31176;
10'd206: sine_sample = -16'sd31237;
10'd207: sine_sample = -16'sd31297;
10'd208: sine_sample = -16'sd31356;
10'd209: sine_sample = -16'sd31414;
10'd210: sine_sample = -16'sd31470;
10'd211: sine_sample = -16'sd31526;
10'd212: sine_sample = -16'sd31580;
10'd213: sine_sample = -16'sd31633;
10'd214: sine_sample = -16'sd31685;
10'd215: sine_sample = -16'sd31736;
10'd216: sine_sample = -16'sd31785;
10'd217: sine_sample = -16'sd31833;
10'd218: sine_sample = -16'sd31880;
10'd219: sine_sample = -16'sd31926;
10'd220: sine_sample = -16'sd31971;
10'd221: sine_sample = -16'sd32014;
10'd222: sine_sample = -16'sd32057;
10'd223: sine_sample = -16'sd32098;
10'd224: sine_sample = -16'sd32137;
10'd225: sine_sample = -16'sd32176;
10'd226: sine_sample = -16'sd32213;
10'd227: sine_sample = -16'sd32250;
10'd228: sine_sample = -16'sd32285;
10'd229: sine_sample = -16'sd32318;
10'd230: sine_sample = -16'sd32351;
10'd231: sine_sample = -16'sd32382;
10'd232: sine_sample = -16'sd32412;
10'd233: sine_sample = -16'sd32441;
10'd234: sine_sample = -16'sd32469;
10'd235: sine_sample = -16'sd32495;
10'd236: sine_sample = -16'sd32521;
10'd237: sine_sample = -16'sd32545;
10'd238: sine_sample = -16'sd32567;
10'd239: sine_sample = -16'sd32589;
10'd240: sine_sample = -16'sd32609;
10'd241: sine_sample = -16'sd32628;
10'd242: sine_sample = -16'sd32646;
10'd243: sine_sample = -16'sd32663;
10'd244: sine_sample = -16'sd32678;
10'd245: sine_sample = -16'sd32692;
10'd246: sine_sample = -16'sd32705;
10'd247: sine_sample = -16'sd32717;
10'd248: sine_sample = -16'sd32728;
10'd249: sine_sample = -16'sd32737;
10'd250: sine_sample = -16'sd32745;
10'd251: sine_sample = -16'sd32752;
10'd252: sine_sample = -16'sd32757;
10'd253: sine_sample = -16'sd32761;
10'd254: sine_sample = -16'sd32765;
10'd255: sine_sample = -16'sd32766;
10'd256: sine_sample = -16'sd32767;
10'd257: sine_sample = -16'sd32766;
10'd258: sine_sample = -16'sd32765;
10'd259: sine_sample = -16'sd32761;
10'd260: sine_sample = -16'sd32757;
10'd261: sine_sample = -16'sd32752;
10'd262: sine_sample = -16'sd32745;
10'd263: sine_sample = -16'sd32737;
10'd264: sine_sample = -16'sd32728;
10'd265: sine_sample = -16'sd32717;
10'd266: sine_sample = -16'sd32705;
10'd267: sine_sample = -16'sd32692;
10'd268: sine_sample = -16'sd32678;
10'd269: sine_sample = -16'sd32663;
10'd270: sine_sample = -16'sd32646;
10'd271: sine_sample = -16'sd32628;
10'd272: sine_sample = -16'sd32609;
10'd273: sine_sample = -16'sd32589;
10'd274: sine_sample = -16'sd32567;
10'd275: sine_sample = -16'sd32545;
10'd276: sine_sample = -16'sd32521;
10'd277: sine_sample = -16'sd32495;
10'd278: sine_sample = -16'sd32469;
10'd279: sine_sample = -16'sd32441;
10'd280: sine_sample = -16'sd32412;
10'd281: sine_sample = -16'sd32382;
10'd282: sine_sample = -16'sd32351;
10'd283: sine_sample = -16'sd32318;
10'd284: sine_sample = -16'sd32285;
10'd285: sine_sample = -16'sd32250;
10'd286: sine_sample = -16'sd32213;
10'd287: sine_sample = -16'sd32176;
10'd288: sine_sample = -16'sd32137;
10'd289: sine_sample = -16'sd32098;
10'd290: sine_sample = -16'sd32057;
10'd291: sine_sample = -16'sd32014;
10'd292: sine_sample = -16'sd31971;
10'd293: sine_sample = -16'sd31926;
10'd294: sine_sample = -16'sd31880;
10'd295: sine_sample = -16'sd31833;
10'd296: sine_sample = -16'sd31785;
10'd297: sine_sample = -16'sd31736;
10'd298: sine_sample = -16'sd31685;
10'd299: sine_sample = -16'sd31633;
10'd300: sine_sample = -16'sd31580;
10'd301: sine_sample = -16'sd31526;
10'd302: sine_sample = -16'sd31470;
10'd303: sine_sample = -16'sd31414;
10'd304: sine_sample = -16'sd31356;
10'd305: sine_sample = -16'sd31297;
10'd306: sine_sample = -16'sd31237;
10'd307: sine_sample = -16'sd31176;
10'd308: sine_sample = -16'sd31113;
10'd309: sine_sample = -16'sd31050;
10'd310: sine_sample = -16'sd30985;
10'd311: sine_sample = -16'sd30919;
10'd312: sine_sample = -16'sd30852;
10'd313: sine_sample = -16'sd30783;
10'd314: sine_sample = -16'sd30714;
10'd315: sine_sample = -16'sd30643;
10'd316: sine_sample = -16'sd30571;
10'd317: sine_sample = -16'sd30498;
10'd318: sine_sample = -16'sd30424;
10'd319: sine_sample = -16'sd30349;
10'd320: sine_sample = -16'sd30273;
10'd321: sine_sample = -16'sd30195;
10'd322: sine_sample = -16'sd30117;
10'd323: sine_sample = -16'sd30037;
10'd324: sine_sample = -16'sd29956;
10'd325: sine_sample = -16'sd29874;
10'd326: sine_sample = -16'sd29791;
10'd327: sine_sample = -16'sd29706;
10'd328: sine_sample = -16'sd29621;
10'd329: sine_sample = -16'sd29534;
10'd330: sine_sample = -16'sd29447;
10'd331: sine_sample = -16'sd29358;
10'd332: sine_sample = -16'sd29268;
10'd333: sine_sample = -16'sd29177;
10'd334: sine_sample = -16'sd29085;
10'd335: sine_sample = -16'sd28992;
10'd336: sine_sample = -16'sd28898;
10'd337: sine_sample = -16'sd28803;
10'd338: sine_sample = -16'sd28706;
10'd339: sine_sample = -16'sd28609;
10'd340: sine_sample = -16'sd28510;
10'd341: sine_sample = -16'sd28411;
10'd342: sine_sample = -16'sd28310;
10'd343: sine_sample = -16'sd28208;
10'd344: sine_sample = -16'sd28105;
10'd345: sine_sample = -16'sd28001;
10'd346: sine_sample = -16'sd27896;
10'd347: sine_sample = -16'sd27790;
10'd348: sine_sample = -16'sd27683;
10'd349: sine_sample = -16'sd27575;
10'd350: sine_sample = -16'sd27466;
10'd351: sine_sample = -16'sd27356;
10'd352: sine_sample = -16'sd27245;
10'd353: sine_sample = -16'sd27133;
10'd354: sine_sample = -16'sd27019;
10'd355: sine_sample = -16'sd26905;
10'd356: sine_sample = -16'sd26790;
10'd357: sine_sample = -16'sd26674;
10'd358: sine_sample = -16'sd26556;
10'd359: sine_sample = -16'sd26438;
10'd360: sine_sample = -16'sd26319;
10'd361: sine_sample = -16'sd26198;
10'd362: sine_sample = -16'sd26077;
10'd363: sine_sample = -16'sd25955;
10'd364: sine_sample = -16'sd25832;
10'd365: sine_sample = -16'sd25708;
10'd366: sine_sample = -16'sd25582;
10'd367: sine_sample = -16'sd25456;
10'd368: sine_sample = -16'sd25329;
10'd369: sine_sample = -16'sd25201;
10'd370: sine_sample = -16'sd25072;
10'd371: sine_sample = -16'sd24942;
10'd372: sine_sample = -16'sd24811;
10'd373: sine_sample = -16'sd24680;
10'd374: sine_sample = -16'sd24547;
10'd375: sine_sample = -16'sd24413;
10'd376: sine_sample = -16'sd24279;
10'd377: sine_sample = -16'sd24143;
10'd378: sine_sample = -16'sd24007;
10'd379: sine_sample = -16'sd23870;
10'd380: sine_sample = -16'sd23731;
10'd381: sine_sample = -16'sd23592;
10'd382: sine_sample = -16'sd23452;
10'd383: sine_sample = -16'sd23311;
10'd384: sine_sample = -16'sd23170;
10'd385: sine_sample = -16'sd23027;
10'd386: sine_sample = -16'sd22884;
10'd387: sine_sample = -16'sd22739;
10'd388: sine_sample = -16'sd22594;
10'd389: sine_sample = -16'sd22448;
10'd390: sine_sample = -16'sd22301;
10'd391: sine_sample = -16'sd22154;
10'd392: sine_sample = -16'sd22005;
10'd393: sine_sample = -16'sd21856;
10'd394: sine_sample = -16'sd21705;
10'd395: sine_sample = -16'sd21554;
10'd396: sine_sample = -16'sd21403;
10'd397: sine_sample = -16'sd21250;
10'd398: sine_sample = -16'sd21096;
10'd399: sine_sample = -16'sd20942;
10'd400: sine_sample = -16'sd20787;
10'd401: sine_sample = -16'sd20631;
10'd402: sine_sample = -16'sd20475;
10'd403: sine_sample = -16'sd20317;
10'd404: sine_sample = -16'sd20159;
10'd405: sine_sample = -16'sd20000;
10'd406: sine_sample = -16'sd19841;
10'd407: sine_sample = -16'sd19680;
10'd408: sine_sample = -16'sd19519;
10'd409: sine_sample = -16'sd19357;
10'd410: sine_sample = -16'sd19195;
10'd411: sine_sample = -16'sd19032;
10'd412: sine_sample = -16'sd18868;
10'd413: sine_sample = -16'sd18703;
10'd414: sine_sample = -16'sd18537;
10'd415: sine_sample = -16'sd18371;
10'd416: sine_sample = -16'sd18204;
10'd417: sine_sample = -16'sd18037;
10'd418: sine_sample = -16'sd17869;
10'd419: sine_sample = -16'sd17700;
10'd420: sine_sample = -16'sd17530;
10'd421: sine_sample = -16'sd17360;
10'd422: sine_sample = -16'sd17189;
10'd423: sine_sample = -16'sd17018;
10'd424: sine_sample = -16'sd16846;
10'd425: sine_sample = -16'sd16673;
10'd426: sine_sample = -16'sd16499;
10'd427: sine_sample = -16'sd16325;
10'd428: sine_sample = -16'sd16151;
10'd429: sine_sample = -16'sd15976;
10'd430: sine_sample = -16'sd15800;
10'd431: sine_sample = -16'sd15623;
10'd432: sine_sample = -16'sd15446;
10'd433: sine_sample = -16'sd15269;
10'd434: sine_sample = -16'sd15090;
10'd435: sine_sample = -16'sd14912;
10'd436: sine_sample = -16'sd14732;
10'd437: sine_sample = -16'sd14553;
10'd438: sine_sample = -16'sd14372;
10'd439: sine_sample = -16'sd14191;
10'd440: sine_sample = -16'sd14010;
10'd441: sine_sample = -16'sd13828;
10'd442: sine_sample = -16'sd13645;
10'd443: sine_sample = -16'sd13462;
10'd444: sine_sample = -16'sd13279;
10'd445: sine_sample = -16'sd13094;
10'd446: sine_sample = -16'sd12910;
10'd447: sine_sample = -16'sd12725;
10'd448: sine_sample = -16'sd12539;
10'd449: sine_sample = -16'sd12353;
10'd450: sine_sample = -16'sd12167;
10'd451: sine_sample = -16'sd11980;
10'd452: sine_sample = -16'sd11793;
10'd453: sine_sample = -16'sd11605;
10'd454: sine_sample = -16'sd11417;
10'd455: sine_sample = -16'sd11228;
10'd456: sine_sample = -16'sd11039;
10'd457: sine_sample = -16'sd10849;
10'd458: sine_sample = -16'sd10659;
10'd459: sine_sample = -16'sd10469;
10'd460: sine_sample = -16'sd10278;
10'd461: sine_sample = -16'sd10087;
10'd462: sine_sample = -16'sd9896;
10'd463: sine_sample = -16'sd9704;
10'd464: sine_sample = -16'sd9512;
10'd465: sine_sample = -16'sd9319;
10'd466: sine_sample = -16'sd9126;
10'd467: sine_sample = -16'sd8933;
10'd468: sine_sample = -16'sd8739;
10'd469: sine_sample = -16'sd8545;
10'd470: sine_sample = -16'sd8351;
10'd471: sine_sample = -16'sd8157;
10'd472: sine_sample = -16'sd7962;
10'd473: sine_sample = -16'sd7767;
10'd474: sine_sample = -16'sd7571;
10'd475: sine_sample = -16'sd7375;
10'd476: sine_sample = -16'sd7179;
10'd477: sine_sample = -16'sd6983;
10'd478: sine_sample = -16'sd6786;
10'd479: sine_sample = -16'sd6590;
10'd480: sine_sample = -16'sd6393;
10'd481: sine_sample = -16'sd6195;
10'd482: sine_sample = -16'sd5998;
10'd483: sine_sample = -16'sd5800;
10'd484: sine_sample = -16'sd5602;
10'd485: sine_sample = -16'sd5404;
10'd486: sine_sample = -16'sd5205;
10'd487: sine_sample = -16'sd5007;
10'd488: sine_sample = -16'sd4808;
10'd489: sine_sample = -16'sd4609;
10'd490: sine_sample = -16'sd4410;
10'd491: sine_sample = -16'sd4210;
10'd492: sine_sample = -16'sd4011;
10'd493: sine_sample = -16'sd3811;
10'd494: sine_sample = -16'sd3612;
10'd495: sine_sample = -16'sd3412;
10'd496: sine_sample = -16'sd3212;
10'd497: sine_sample = -16'sd3012;
10'd498: sine_sample = -16'sd2811;
10'd499: sine_sample = -16'sd2611;
10'd500: sine_sample = -16'sd2410;
10'd501: sine_sample = -16'sd2210;
10'd502: sine_sample = -16'sd2009;
10'd503: sine_sample = -16'sd1809;
10'd504: sine_sample = -16'sd1608;
10'd505: sine_sample = -16'sd1407;
10'd506: sine_sample = -16'sd1206;
10'd507: sine_sample = -16'sd1005;
10'd508: sine_sample = -16'sd804;
10'd509: sine_sample = -16'sd603;
10'd510: sine_sample = -16'sd402;
10'd511: sine_sample = -16'sd201;
10'd512: sine_sample = -16'sd0;
10'd513: sine_sample = 16'sd201;
10'd514: sine_sample = 16'sd402;
10'd515: sine_sample = 16'sd603;
10'd516: sine_sample = 16'sd804;
10'd517: sine_sample = 16'sd1005;
10'd518: sine_sample = 16'sd1206;
10'd519: sine_sample = 16'sd1407;
10'd520: sine_sample = 16'sd1608;
10'd521: sine_sample = 16'sd1809;
10'd522: sine_sample = 16'sd2009;
10'd523: sine_sample = 16'sd2210;
10'd524: sine_sample = 16'sd2410;
10'd525: sine_sample = 16'sd2611;
10'd526: sine_sample = 16'sd2811;
10'd527: sine_sample = 16'sd3012;
10'd528: sine_sample = 16'sd3212;
10'd529: sine_sample = 16'sd3412;
10'd530: sine_sample = 16'sd3612;
10'd531: sine_sample = 16'sd3811;
10'd532: sine_sample = 16'sd4011;
10'd533: sine_sample = 16'sd4210;
10'd534: sine_sample = 16'sd4410;
10'd535: sine_sample = 16'sd4609;
10'd536: sine_sample = 16'sd4808;
10'd537: sine_sample = 16'sd5007;
10'd538: sine_sample = 16'sd5205;
10'd539: sine_sample = 16'sd5404;
10'd540: sine_sample = 16'sd5602;
10'd541: sine_sample = 16'sd5800;
10'd542: sine_sample = 16'sd5998;
10'd543: sine_sample = 16'sd6195;
10'd544: sine_sample = 16'sd6393;
10'd545: sine_sample = 16'sd6590;
10'd546: sine_sample = 16'sd6786;
10'd547: sine_sample = 16'sd6983;
10'd548: sine_sample = 16'sd7179;
10'd549: sine_sample = 16'sd7375;
10'd550: sine_sample = 16'sd7571;
10'd551: sine_sample = 16'sd7767;
10'd552: sine_sample = 16'sd7962;
10'd553: sine_sample = 16'sd8157;
10'd554: sine_sample = 16'sd8351;
10'd555: sine_sample = 16'sd8545;
10'd556: sine_sample = 16'sd8739;
10'd557: sine_sample = 16'sd8933;
10'd558: sine_sample = 16'sd9126;
10'd559: sine_sample = 16'sd9319;
10'd560: sine_sample = 16'sd9512;
10'd561: sine_sample = 16'sd9704;
10'd562: sine_sample = 16'sd9896;
10'd563: sine_sample = 16'sd10087;
10'd564: sine_sample = 16'sd10278;
10'd565: sine_sample = 16'sd10469;
10'd566: sine_sample = 16'sd10659;
10'd567: sine_sample = 16'sd10849;
10'd568: sine_sample = 16'sd11039;
10'd569: sine_sample = 16'sd11228;
10'd570: sine_sample = 16'sd11417;
10'd571: sine_sample = 16'sd11605;
10'd572: sine_sample = 16'sd11793;
10'd573: sine_sample = 16'sd11980;
10'd574: sine_sample = 16'sd12167;
10'd575: sine_sample = 16'sd12353;
10'd576: sine_sample = 16'sd12539;
10'd577: sine_sample = 16'sd12725;
10'd578: sine_sample = 16'sd12910;
10'd579: sine_sample = 16'sd13094;
10'd580: sine_sample = 16'sd13279;
10'd581: sine_sample = 16'sd13462;
10'd582: sine_sample = 16'sd13645;
10'd583: sine_sample = 16'sd13828;
10'd584: sine_sample = 16'sd14010;
10'd585: sine_sample = 16'sd14191;
10'd586: sine_sample = 16'sd14372;
10'd587: sine_sample = 16'sd14553;
10'd588: sine_sample = 16'sd14732;
10'd589: sine_sample = 16'sd14912;
10'd590: sine_sample = 16'sd15090;
10'd591: sine_sample = 16'sd15269;
10'd592: sine_sample = 16'sd15446;
10'd593: sine_sample = 16'sd15623;
10'd594: sine_sample = 16'sd15800;
10'd595: sine_sample = 16'sd15976;
10'd596: sine_sample = 16'sd16151;
10'd597: sine_sample = 16'sd16325;
10'd598: sine_sample = 16'sd16499;
10'd599: sine_sample = 16'sd16673;
10'd600: sine_sample = 16'sd16846;
10'd601: sine_sample = 16'sd17018;
10'd602: sine_sample = 16'sd17189;
10'd603: sine_sample = 16'sd17360;
10'd604: sine_sample = 16'sd17530;
10'd605: sine_sample = 16'sd17700;
10'd606: sine_sample = 16'sd17869;
10'd607: sine_sample = 16'sd18037;
10'd608: sine_sample = 16'sd18204;
10'd609: sine_sample = 16'sd18371;
10'd610: sine_sample = 16'sd18537;
10'd611: sine_sample = 16'sd18703;
10'd612: sine_sample = 16'sd18868;
10'd613: sine_sample = 16'sd19032;
10'd614: sine_sample = 16'sd19195;
10'd615: sine_sample = 16'sd19357;
10'd616: sine_sample = 16'sd19519;
10'd617: sine_sample = 16'sd19680;
10'd618: sine_sample = 16'sd19841;
10'd619: sine_sample = 16'sd20000;
10'd620: sine_sample = 16'sd20159;
10'd621: sine_sample = 16'sd20317;
10'd622: sine_sample = 16'sd20475;
10'd623: sine_sample = 16'sd20631;
10'd624: sine_sample = 16'sd20787;
10'd625: sine_sample = 16'sd20942;
10'd626: sine_sample = 16'sd21096;
10'd627: sine_sample = 16'sd21250;
10'd628: sine_sample = 16'sd21403;
10'd629: sine_sample = 16'sd21554;
10'd630: sine_sample = 16'sd21705;
10'd631: sine_sample = 16'sd21856;
10'd632: sine_sample = 16'sd22005;
10'd633: sine_sample = 16'sd22154;
10'd634: sine_sample = 16'sd22301;
10'd635: sine_sample = 16'sd22448;
10'd636: sine_sample = 16'sd22594;
10'd637: sine_sample = 16'sd22739;
10'd638: sine_sample = 16'sd22884;
10'd639: sine_sample = 16'sd23027;
10'd640: sine_sample = 16'sd23170;
10'd641: sine_sample = 16'sd23311;
10'd642: sine_sample = 16'sd23452;
10'd643: sine_sample = 16'sd23592;
10'd644: sine_sample = 16'sd23731;
10'd645: sine_sample = 16'sd23870;
10'd646: sine_sample = 16'sd24007;
10'd647: sine_sample = 16'sd24143;
10'd648: sine_sample = 16'sd24279;
10'd649: sine_sample = 16'sd24413;
10'd650: sine_sample = 16'sd24547;
10'd651: sine_sample = 16'sd24680;
10'd652: sine_sample = 16'sd24811;
10'd653: sine_sample = 16'sd24942;
10'd654: sine_sample = 16'sd25072;
10'd655: sine_sample = 16'sd25201;
10'd656: sine_sample = 16'sd25329;
10'd657: sine_sample = 16'sd25456;
10'd658: sine_sample = 16'sd25582;
10'd659: sine_sample = 16'sd25708;
10'd660: sine_sample = 16'sd25832;
10'd661: sine_sample = 16'sd25955;
10'd662: sine_sample = 16'sd26077;
10'd663: sine_sample = 16'sd26198;
10'd664: sine_sample = 16'sd26319;
10'd665: sine_sample = 16'sd26438;
10'd666: sine_sample = 16'sd26556;
10'd667: sine_sample = 16'sd26674;
10'd668: sine_sample = 16'sd26790;
10'd669: sine_sample = 16'sd26905;
10'd670: sine_sample = 16'sd27019;
10'd671: sine_sample = 16'sd27133;
10'd672: sine_sample = 16'sd27245;
10'd673: sine_sample = 16'sd27356;
10'd674: sine_sample = 16'sd27466;
10'd675: sine_sample = 16'sd27575;
10'd676: sine_sample = 16'sd27683;
10'd677: sine_sample = 16'sd27790;
10'd678: sine_sample = 16'sd27896;
10'd679: sine_sample = 16'sd28001;
10'd680: sine_sample = 16'sd28105;
10'd681: sine_sample = 16'sd28208;
10'd682: sine_sample = 16'sd28310;
10'd683: sine_sample = 16'sd28411;
10'd684: sine_sample = 16'sd28510;
10'd685: sine_sample = 16'sd28609;
10'd686: sine_sample = 16'sd28706;
10'd687: sine_sample = 16'sd28803;
10'd688: sine_sample = 16'sd28898;
10'd689: sine_sample = 16'sd28992;
10'd690: sine_sample = 16'sd29085;
10'd691: sine_sample = 16'sd29177;
10'd692: sine_sample = 16'sd29268;
10'd693: sine_sample = 16'sd29358;
10'd694: sine_sample = 16'sd29447;
10'd695: sine_sample = 16'sd29534;
10'd696: sine_sample = 16'sd29621;
10'd697: sine_sample = 16'sd29706;
10'd698: sine_sample = 16'sd29791;
10'd699: sine_sample = 16'sd29874;
10'd700: sine_sample = 16'sd29956;
10'd701: sine_sample = 16'sd30037;
10'd702: sine_sample = 16'sd30117;
10'd703: sine_sample = 16'sd30195;
10'd704: sine_sample = 16'sd30273;
10'd705: sine_sample = 16'sd30349;
10'd706: sine_sample = 16'sd30424;
10'd707: sine_sample = 16'sd30498;
10'd708: sine_sample = 16'sd30571;
10'd709: sine_sample = 16'sd30643;
10'd710: sine_sample = 16'sd30714;
10'd711: sine_sample = 16'sd30783;
10'd712: sine_sample = 16'sd30852;
10'd713: sine_sample = 16'sd30919;
10'd714: sine_sample = 16'sd30985;
10'd715: sine_sample = 16'sd31050;
10'd716: sine_sample = 16'sd31113;
10'd717: sine_sample = 16'sd31176;
10'd718: sine_sample = 16'sd31237;
10'd719: sine_sample = 16'sd31297;
10'd720: sine_sample = 16'sd31356;
10'd721: sine_sample = 16'sd31414;
10'd722: sine_sample = 16'sd31470;
10'd723: sine_sample = 16'sd31526;
10'd724: sine_sample = 16'sd31580;
10'd725: sine_sample = 16'sd31633;
10'd726: sine_sample = 16'sd31685;
10'd727: sine_sample = 16'sd31736;
10'd728: sine_sample = 16'sd31785;
10'd729: sine_sample = 16'sd31833;
10'd730: sine_sample = 16'sd31880;
10'd731: sine_sample = 16'sd31926;
10'd732: sine_sample = 16'sd31971;
10'd733: sine_sample = 16'sd32014;
10'd734: sine_sample = 16'sd32057;
10'd735: sine_sample = 16'sd32098;
10'd736: sine_sample = 16'sd32137;
10'd737: sine_sample = 16'sd32176;
10'd738: sine_sample = 16'sd32213;
10'd739: sine_sample = 16'sd32250;
10'd740: sine_sample = 16'sd32285;
10'd741: sine_sample = 16'sd32318;
10'd742: sine_sample = 16'sd32351;
10'd743: sine_sample = 16'sd32382;
10'd744: sine_sample = 16'sd32412;
10'd745: sine_sample = 16'sd32441;
10'd746: sine_sample = 16'sd32469;
10'd747: sine_sample = 16'sd32495;
10'd748: sine_sample = 16'sd32521;
10'd749: sine_sample = 16'sd32545;
10'd750: sine_sample = 16'sd32567;
10'd751: sine_sample = 16'sd32589;
10'd752: sine_sample = 16'sd32609;
10'd753: sine_sample = 16'sd32628;
10'd754: sine_sample = 16'sd32646;
10'd755: sine_sample = 16'sd32663;
10'd756: sine_sample = 16'sd32678;
10'd757: sine_sample = 16'sd32692;
10'd758: sine_sample = 16'sd32705;
10'd759: sine_sample = 16'sd32717;
10'd760: sine_sample = 16'sd32728;
10'd761: sine_sample = 16'sd32737;
10'd762: sine_sample = 16'sd32745;
10'd763: sine_sample = 16'sd32752;
10'd764: sine_sample = 16'sd32757;
10'd765: sine_sample = 16'sd32761;
10'd766: sine_sample = 16'sd32765;
10'd767: sine_sample = 16'sd32766;
10'd768: sine_sample = 16'sd32767;
10'd769: sine_sample = 16'sd32766;
10'd770: sine_sample = 16'sd32765;
10'd771: sine_sample = 16'sd32761;
10'd772: sine_sample = 16'sd32757;
10'd773: sine_sample = 16'sd32752;
10'd774: sine_sample = 16'sd32745;
10'd775: sine_sample = 16'sd32737;
10'd776: sine_sample = 16'sd32728;
10'd777: sine_sample = 16'sd32717;
10'd778: sine_sample = 16'sd32705;
10'd779: sine_sample = 16'sd32692;
10'd780: sine_sample = 16'sd32678;
10'd781: sine_sample = 16'sd32663;
10'd782: sine_sample = 16'sd32646;
10'd783: sine_sample = 16'sd32628;
10'd784: sine_sample = 16'sd32609;
10'd785: sine_sample = 16'sd32589;
10'd786: sine_sample = 16'sd32567;
10'd787: sine_sample = 16'sd32545;
10'd788: sine_sample = 16'sd32521;
10'd789: sine_sample = 16'sd32495;
10'd790: sine_sample = 16'sd32469;
10'd791: sine_sample = 16'sd32441;
10'd792: sine_sample = 16'sd32412;
10'd793: sine_sample = 16'sd32382;
10'd794: sine_sample = 16'sd32351;
10'd795: sine_sample = 16'sd32318;
10'd796: sine_sample = 16'sd32285;
10'd797: sine_sample = 16'sd32250;
10'd798: sine_sample = 16'sd32213;
10'd799: sine_sample = 16'sd32176;
10'd800: sine_sample = 16'sd32137;
10'd801: sine_sample = 16'sd32098;
10'd802: sine_sample = 16'sd32057;
10'd803: sine_sample = 16'sd32014;
10'd804: sine_sample = 16'sd31971;
10'd805: sine_sample = 16'sd31926;
10'd806: sine_sample = 16'sd31880;
10'd807: sine_sample = 16'sd31833;
10'd808: sine_sample = 16'sd31785;
10'd809: sine_sample = 16'sd31736;
10'd810: sine_sample = 16'sd31685;
10'd811: sine_sample = 16'sd31633;
10'd812: sine_sample = 16'sd31580;
10'd813: sine_sample = 16'sd31526;
10'd814: sine_sample = 16'sd31470;
10'd815: sine_sample = 16'sd31414;
10'd816: sine_sample = 16'sd31356;
10'd817: sine_sample = 16'sd31297;
10'd818: sine_sample = 16'sd31237;
10'd819: sine_sample = 16'sd31176;
10'd820: sine_sample = 16'sd31113;
10'd821: sine_sample = 16'sd31050;
10'd822: sine_sample = 16'sd30985;
10'd823: sine_sample = 16'sd30919;
10'd824: sine_sample = 16'sd30852;
10'd825: sine_sample = 16'sd30783;
10'd826: sine_sample = 16'sd30714;
10'd827: sine_sample = 16'sd30643;
10'd828: sine_sample = 16'sd30571;
10'd829: sine_sample = 16'sd30498;
10'd830: sine_sample = 16'sd30424;
10'd831: sine_sample = 16'sd30349;
10'd832: sine_sample = 16'sd30273;
10'd833: sine_sample = 16'sd30195;
10'd834: sine_sample = 16'sd30117;
10'd835: sine_sample = 16'sd30037;
10'd836: sine_sample = 16'sd29956;
10'd837: sine_sample = 16'sd29874;
10'd838: sine_sample = 16'sd29791;
10'd839: sine_sample = 16'sd29706;
10'd840: sine_sample = 16'sd29621;
10'd841: sine_sample = 16'sd29534;
10'd842: sine_sample = 16'sd29447;
10'd843: sine_sample = 16'sd29358;
10'd844: sine_sample = 16'sd29268;
10'd845: sine_sample = 16'sd29177;
10'd846: sine_sample = 16'sd29085;
10'd847: sine_sample = 16'sd28992;
10'd848: sine_sample = 16'sd28898;
10'd849: sine_sample = 16'sd28803;
10'd850: sine_sample = 16'sd28706;
10'd851: sine_sample = 16'sd28609;
10'd852: sine_sample = 16'sd28510;
10'd853: sine_sample = 16'sd28411;
10'd854: sine_sample = 16'sd28310;
10'd855: sine_sample = 16'sd28208;
10'd856: sine_sample = 16'sd28105;
10'd857: sine_sample = 16'sd28001;
10'd858: sine_sample = 16'sd27896;
10'd859: sine_sample = 16'sd27790;
10'd860: sine_sample = 16'sd27683;
10'd861: sine_sample = 16'sd27575;
10'd862: sine_sample = 16'sd27466;
10'd863: sine_sample = 16'sd27356;
10'd864: sine_sample = 16'sd27245;
10'd865: sine_sample = 16'sd27133;
10'd866: sine_sample = 16'sd27019;
10'd867: sine_sample = 16'sd26905;
10'd868: sine_sample = 16'sd26790;
10'd869: sine_sample = 16'sd26674;
10'd870: sine_sample = 16'sd26556;
10'd871: sine_sample = 16'sd26438;
10'd872: sine_sample = 16'sd26319;
10'd873: sine_sample = 16'sd26198;
10'd874: sine_sample = 16'sd26077;
10'd875: sine_sample = 16'sd25955;
10'd876: sine_sample = 16'sd25832;
10'd877: sine_sample = 16'sd25708;
10'd878: sine_sample = 16'sd25582;
10'd879: sine_sample = 16'sd25456;
10'd880: sine_sample = 16'sd25329;
10'd881: sine_sample = 16'sd25201;
10'd882: sine_sample = 16'sd25072;
10'd883: sine_sample = 16'sd24942;
10'd884: sine_sample = 16'sd24811;
10'd885: sine_sample = 16'sd24680;
10'd886: sine_sample = 16'sd24547;
10'd887: sine_sample = 16'sd24413;
10'd888: sine_sample = 16'sd24279;
10'd889: sine_sample = 16'sd24143;
10'd890: sine_sample = 16'sd24007;
10'd891: sine_sample = 16'sd23870;
10'd892: sine_sample = 16'sd23731;
10'd893: sine_sample = 16'sd23592;
10'd894: sine_sample = 16'sd23452;
10'd895: sine_sample = 16'sd23311;
10'd896: sine_sample = 16'sd23170;
10'd897: sine_sample = 16'sd23027;
10'd898: sine_sample = 16'sd22884;
10'd899: sine_sample = 16'sd22739;
10'd900: sine_sample = 16'sd22594;
10'd901: sine_sample = 16'sd22448;
10'd902: sine_sample = 16'sd22301;
10'd903: sine_sample = 16'sd22154;
10'd904: sine_sample = 16'sd22005;
10'd905: sine_sample = 16'sd21856;
10'd906: sine_sample = 16'sd21705;
10'd907: sine_sample = 16'sd21554;
10'd908: sine_sample = 16'sd21403;
10'd909: sine_sample = 16'sd21250;
10'd910: sine_sample = 16'sd21096;
10'd911: sine_sample = 16'sd20942;
10'd912: sine_sample = 16'sd20787;
10'd913: sine_sample = 16'sd20631;
10'd914: sine_sample = 16'sd20475;
10'd915: sine_sample = 16'sd20317;
10'd916: sine_sample = 16'sd20159;
10'd917: sine_sample = 16'sd20000;
10'd918: sine_sample = 16'sd19841;
10'd919: sine_sample = 16'sd19680;
10'd920: sine_sample = 16'sd19519;
10'd921: sine_sample = 16'sd19357;
10'd922: sine_sample = 16'sd19195;
10'd923: sine_sample = 16'sd19032;
10'd924: sine_sample = 16'sd18868;
10'd925: sine_sample = 16'sd18703;
10'd926: sine_sample = 16'sd18537;
10'd927: sine_sample = 16'sd18371;
10'd928: sine_sample = 16'sd18204;
10'd929: sine_sample = 16'sd18037;
10'd930: sine_sample = 16'sd17869;
10'd931: sine_sample = 16'sd17700;
10'd932: sine_sample = 16'sd17530;
10'd933: sine_sample = 16'sd17360;
10'd934: sine_sample = 16'sd17189;
10'd935: sine_sample = 16'sd17018;
10'd936: sine_sample = 16'sd16846;
10'd937: sine_sample = 16'sd16673;
10'd938: sine_sample = 16'sd16499;
10'd939: sine_sample = 16'sd16325;
10'd940: sine_sample = 16'sd16151;
10'd941: sine_sample = 16'sd15976;
10'd942: sine_sample = 16'sd15800;
10'd943: sine_sample = 16'sd15623;
10'd944: sine_sample = 16'sd15446;
10'd945: sine_sample = 16'sd15269;
10'd946: sine_sample = 16'sd15090;
10'd947: sine_sample = 16'sd14912;
10'd948: sine_sample = 16'sd14732;
10'd949: sine_sample = 16'sd14553;
10'd950: sine_sample = 16'sd14372;
10'd951: sine_sample = 16'sd14191;
10'd952: sine_sample = 16'sd14010;
10'd953: sine_sample = 16'sd13828;
10'd954: sine_sample = 16'sd13645;
10'd955: sine_sample = 16'sd13462;
10'd956: sine_sample = 16'sd13279;
10'd957: sine_sample = 16'sd13094;
10'd958: sine_sample = 16'sd12910;
10'd959: sine_sample = 16'sd12725;
10'd960: sine_sample = 16'sd12539;
10'd961: sine_sample = 16'sd12353;
10'd962: sine_sample = 16'sd12167;
10'd963: sine_sample = 16'sd11980;
10'd964: sine_sample = 16'sd11793;
10'd965: sine_sample = 16'sd11605;
10'd966: sine_sample = 16'sd11417;
10'd967: sine_sample = 16'sd11228;
10'd968: sine_sample = 16'sd11039;
10'd969: sine_sample = 16'sd10849;
10'd970: sine_sample = 16'sd10659;
10'd971: sine_sample = 16'sd10469;
10'd972: sine_sample = 16'sd10278;
10'd973: sine_sample = 16'sd10087;
10'd974: sine_sample = 16'sd9896;
10'd975: sine_sample = 16'sd9704;
10'd976: sine_sample = 16'sd9512;
10'd977: sine_sample = 16'sd9319;
10'd978: sine_sample = 16'sd9126;
10'd979: sine_sample = 16'sd8933;
10'd980: sine_sample = 16'sd8739;
10'd981: sine_sample = 16'sd8545;
10'd982: sine_sample = 16'sd8351;
10'd983: sine_sample = 16'sd8157;
10'd984: sine_sample = 16'sd7962;
10'd985: sine_sample = 16'sd7767;
10'd986: sine_sample = 16'sd7571;
10'd987: sine_sample = 16'sd7375;
10'd988: sine_sample = 16'sd7179;
10'd989: sine_sample = 16'sd6983;
10'd990: sine_sample = 16'sd6786;
10'd991: sine_sample = 16'sd6590;
10'd992: sine_sample = 16'sd6393;
10'd993: sine_sample = 16'sd6195;
10'd994: sine_sample = 16'sd5998;
10'd995: sine_sample = 16'sd5800;
10'd996: sine_sample = 16'sd5602;
10'd997: sine_sample = 16'sd5404;
10'd998: sine_sample = 16'sd5205;
10'd999: sine_sample = 16'sd5007;
10'd1000: sine_sample = 16'sd4808;
10'd1001: sine_sample = 16'sd4609;
10'd1002: sine_sample = 16'sd4410;
10'd1003: sine_sample = 16'sd4210;
10'd1004: sine_sample = 16'sd4011;
10'd1005: sine_sample = 16'sd3811;
10'd1006: sine_sample = 16'sd3612;
10'd1007: sine_sample = 16'sd3412;
10'd1008: sine_sample = 16'sd3212;
10'd1009: sine_sample = 16'sd3012;
10'd1010: sine_sample = 16'sd2811;
10'd1011: sine_sample = 16'sd2611;
10'd1012: sine_sample = 16'sd2410;
10'd1013: sine_sample = 16'sd2210;
10'd1014: sine_sample = 16'sd2009;
10'd1015: sine_sample = 16'sd1809;
10'd1016: sine_sample = 16'sd1608;
10'd1017: sine_sample = 16'sd1407;
10'd1018: sine_sample = 16'sd1206;
10'd1019: sine_sample = 16'sd1005;
10'd1020: sine_sample = 16'sd804;
10'd1021: sine_sample = 16'sd603;
10'd1022: sine_sample = 16'sd402;
10'd1023: sine_sample = 16'sd201;
default: sine_sample = 16'sd0;
endcase
end
endmodule | module sine_table(
input wire [9:0] theta,
output reg signed [15:0] sine_sample
); |
always @(theta) begin
case(theta)
10'd0: sine_sample = -16'sd0;
10'd1: sine_sample = -16'sd201;
10'd2: sine_sample = -16'sd402;
10'd3: sine_sample = -16'sd603;
10'd4: sine_sample = -16'sd804;
10'd5: sine_sample = -16'sd1005;
10'd6: sine_sample = -16'sd1206;
10'd7: sine_sample = -16'sd1407;
10'd8: sine_sample = -16'sd1608;
10'd9: sine_sample = -16'sd1809;
10'd10: sine_sample = -16'sd2009;
10'd11: sine_sample = -16'sd2210;
10'd12: sine_sample = -16'sd2410;
10'd13: sine_sample = -16'sd2611;
10'd14: sine_sample = -16'sd2811;
10'd15: sine_sample = -16'sd3012;
10'd16: sine_sample = -16'sd3212;
10'd17: sine_sample = -16'sd3412;
10'd18: sine_sample = -16'sd3612;
10'd19: sine_sample = -16'sd3811;
10'd20: sine_sample = -16'sd4011;
10'd21: sine_sample = -16'sd4210;
10'd22: sine_sample = -16'sd4410;
10'd23: sine_sample = -16'sd4609;
10'd24: sine_sample = -16'sd4808;
10'd25: sine_sample = -16'sd5007;
10'd26: sine_sample = -16'sd5205;
10'd27: sine_sample = -16'sd5404;
10'd28: sine_sample = -16'sd5602;
10'd29: sine_sample = -16'sd5800;
10'd30: sine_sample = -16'sd5998;
10'd31: sine_sample = -16'sd6195;
10'd32: sine_sample = -16'sd6393;
10'd33: sine_sample = -16'sd6590;
10'd34: sine_sample = -16'sd6786;
10'd35: sine_sample = -16'sd6983;
10'd36: sine_sample = -16'sd7179;
10'd37: sine_sample = -16'sd7375;
10'd38: sine_sample = -16'sd7571;
10'd39: sine_sample = -16'sd7767;
10'd40: sine_sample = -16'sd7962;
10'd41: sine_sample = -16'sd8157;
10'd42: sine_sample = -16'sd8351;
10'd43: sine_sample = -16'sd8545;
10'd44: sine_sample = -16'sd8739;
10'd45: sine_sample = -16'sd8933;
10'd46: sine_sample = -16'sd9126;
10'd47: sine_sample = -16'sd9319;
10'd48: sine_sample = -16'sd9512;
10'd49: sine_sample = -16'sd9704;
10'd50: sine_sample = -16'sd9896;
10'd51: sine_sample = -16'sd10087;
10'd52: sine_sample = -16'sd10278;
10'd53: sine_sample = -16'sd10469;
10'd54: sine_sample = -16'sd10659;
10'd55: sine_sample = -16'sd10849;
10'd56: sine_sample = -16'sd11039;
10'd57: sine_sample = -16'sd11228;
10'd58: sine_sample = -16'sd11417;
10'd59: sine_sample = -16'sd11605;
10'd60: sine_sample = -16'sd11793;
10'd61: sine_sample = -16'sd11980;
10'd62: sine_sample = -16'sd12167;
10'd63: sine_sample = -16'sd12353;
10'd64: sine_sample = -16'sd12539;
10'd65: sine_sample = -16'sd12725;
10'd66: sine_sample = -16'sd12910;
10'd67: sine_sample = -16'sd13094;
10'd68: sine_sample = -16'sd13279;
10'd69: sine_sample = -16'sd13462;
10'd70: sine_sample = -16'sd13645;
10'd71: sine_sample = -16'sd13828;
10'd72: sine_sample = -16'sd14010;
10'd73: sine_sample = -16'sd14191;
10'd74: sine_sample = -16'sd14372;
10'd75: sine_sample = -16'sd14553;
10'd76: sine_sample = -16'sd14732;
10'd77: sine_sample = -16'sd14912;
10'd78: sine_sample = -16'sd15090;
10'd79: sine_sample = -16'sd15269;
10'd80: sine_sample = -16'sd15446;
10'd81: sine_sample = -16'sd15623;
10'd82: sine_sample = -16'sd15800;
10'd83: sine_sample = -16'sd15976;
10'd84: sine_sample = -16'sd16151;
10'd85: sine_sample = -16'sd16325;
10'd86: sine_sample = -16'sd16499;
10'd87: sine_sample = -16'sd16673;
10'd88: sine_sample = -16'sd16846;
10'd89: sine_sample = -16'sd17018;
10'd90: sine_sample = -16'sd17189;
10'd91: sine_sample = -16'sd17360;
10'd92: sine_sample = -16'sd17530;
10'd93: sine_sample = -16'sd17700;
10'd94: sine_sample = -16'sd17869;
10'd95: sine_sample = -16'sd18037;
10'd96: sine_sample = -16'sd18204;
10'd97: sine_sample = -16'sd18371;
10'd98: sine_sample = -16'sd18537;
10'd99: sine_sample = -16'sd18703;
10'd100: sine_sample = -16'sd18868;
10'd101: sine_sample = -16'sd19032;
10'd102: sine_sample = -16'sd19195;
10'd103: sine_sample = -16'sd19357;
10'd104: sine_sample = -16'sd19519;
10'd105: sine_sample = -16'sd19680;
10'd106: sine_sample = -16'sd19841;
10'd107: sine_sample = -16'sd20000;
10'd108: sine_sample = -16'sd20159;
10'd109: sine_sample = -16'sd20317;
10'd110: sine_sample = -16'sd20475;
10'd111: sine_sample = -16'sd20631;
10'd112: sine_sample = -16'sd20787;
10'd113: sine_sample = -16'sd20942;
10'd114: sine_sample = -16'sd21096;
10'd115: sine_sample = -16'sd21250;
10'd116: sine_sample = -16'sd21403;
10'd117: sine_sample = -16'sd21554;
10'd118: sine_sample = -16'sd21705;
10'd119: sine_sample = -16'sd21856;
10'd120: sine_sample = -16'sd22005;
10'd121: sine_sample = -16'sd22154;
10'd122: sine_sample = -16'sd22301;
10'd123: sine_sample = -16'sd22448;
10'd124: sine_sample = -16'sd22594;
10'd125: sine_sample = -16'sd22739;
10'd126: sine_sample = -16'sd22884;
10'd127: sine_sample = -16'sd23027;
10'd128: sine_sample = -16'sd23170;
10'd129: sine_sample = -16'sd23311;
10'd130: sine_sample = -16'sd23452;
10'd131: sine_sample = -16'sd23592;
10'd132: sine_sample = -16'sd23731;
10'd133: sine_sample = -16'sd23870;
10'd134: sine_sample = -16'sd24007;
10'd135: sine_sample = -16'sd24143;
10'd136: sine_sample = -16'sd24279;
10'd137: sine_sample = -16'sd24413;
10'd138: sine_sample = -16'sd24547;
10'd139: sine_sample = -16'sd24680;
10'd140: sine_sample = -16'sd24811;
10'd141: sine_sample = -16'sd24942;
10'd142: sine_sample = -16'sd25072;
10'd143: sine_sample = -16'sd25201;
10'd144: sine_sample = -16'sd25329;
10'd145: sine_sample = -16'sd25456;
10'd146: sine_sample = -16'sd25582;
10'd147: sine_sample = -16'sd25708;
10'd148: sine_sample = -16'sd25832;
10'd149: sine_sample = -16'sd25955;
10'd150: sine_sample = -16'sd26077;
10'd151: sine_sample = -16'sd26198;
10'd152: sine_sample = -16'sd26319;
10'd153: sine_sample = -16'sd26438;
10'd154: sine_sample = -16'sd26556;
10'd155: sine_sample = -16'sd26674;
10'd156: sine_sample = -16'sd26790;
10'd157: sine_sample = -16'sd26905;
10'd158: sine_sample = -16'sd27019;
10'd159: sine_sample = -16'sd27133;
10'd160: sine_sample = -16'sd27245;
10'd161: sine_sample = -16'sd27356;
10'd162: sine_sample = -16'sd27466;
10'd163: sine_sample = -16'sd27575;
10'd164: sine_sample = -16'sd27683;
10'd165: sine_sample = -16'sd27790;
10'd166: sine_sample = -16'sd27896;
10'd167: sine_sample = -16'sd28001;
10'd168: sine_sample = -16'sd28105;
10'd169: sine_sample = -16'sd28208;
10'd170: sine_sample = -16'sd28310;
10'd171: sine_sample = -16'sd28411;
10'd172: sine_sample = -16'sd28510;
10'd173: sine_sample = -16'sd28609;
10'd174: sine_sample = -16'sd28706;
10'd175: sine_sample = -16'sd28803;
10'd176: sine_sample = -16'sd28898;
10'd177: sine_sample = -16'sd28992;
10'd178: sine_sample = -16'sd29085;
10'd179: sine_sample = -16'sd29177;
10'd180: sine_sample = -16'sd29268;
10'd181: sine_sample = -16'sd29358;
10'd182: sine_sample = -16'sd29447;
10'd183: sine_sample = -16'sd29534;
10'd184: sine_sample = -16'sd29621;
10'd185: sine_sample = -16'sd29706;
10'd186: sine_sample = -16'sd29791;
10'd187: sine_sample = -16'sd29874;
10'd188: sine_sample = -16'sd29956;
10'd189: sine_sample = -16'sd30037;
10'd190: sine_sample = -16'sd30117;
10'd191: sine_sample = -16'sd30195;
10'd192: sine_sample = -16'sd30273;
10'd193: sine_sample = -16'sd30349;
10'd194: sine_sample = -16'sd30424;
10'd195: sine_sample = -16'sd30498;
10'd196: sine_sample = -16'sd30571;
10'd197: sine_sample = -16'sd30643;
10'd198: sine_sample = -16'sd30714;
10'd199: sine_sample = -16'sd30783;
10'd200: sine_sample = -16'sd30852;
10'd201: sine_sample = -16'sd30919;
10'd202: sine_sample = -16'sd30985;
10'd203: sine_sample = -16'sd31050;
10'd204: sine_sample = -16'sd31113;
10'd205: sine_sample = -16'sd31176;
10'd206: sine_sample = -16'sd31237;
10'd207: sine_sample = -16'sd31297;
10'd208: sine_sample = -16'sd31356;
10'd209: sine_sample = -16'sd31414;
10'd210: sine_sample = -16'sd31470;
10'd211: sine_sample = -16'sd31526;
10'd212: sine_sample = -16'sd31580;
10'd213: sine_sample = -16'sd31633;
10'd214: sine_sample = -16'sd31685;
10'd215: sine_sample = -16'sd31736;
10'd216: sine_sample = -16'sd31785;
10'd217: sine_sample = -16'sd31833;
10'd218: sine_sample = -16'sd31880;
10'd219: sine_sample = -16'sd31926;
10'd220: sine_sample = -16'sd31971;
10'd221: sine_sample = -16'sd32014;
10'd222: sine_sample = -16'sd32057;
10'd223: sine_sample = -16'sd32098;
10'd224: sine_sample = -16'sd32137;
10'd225: sine_sample = -16'sd32176;
10'd226: sine_sample = -16'sd32213;
10'd227: sine_sample = -16'sd32250;
10'd228: sine_sample = -16'sd32285;
10'd229: sine_sample = -16'sd32318;
10'd230: sine_sample = -16'sd32351;
10'd231: sine_sample = -16'sd32382;
10'd232: sine_sample = -16'sd32412;
10'd233: sine_sample = -16'sd32441;
10'd234: sine_sample = -16'sd32469;
10'd235: sine_sample = -16'sd32495;
10'd236: sine_sample = -16'sd32521;
10'd237: sine_sample = -16'sd32545;
10'd238: sine_sample = -16'sd32567;
10'd239: sine_sample = -16'sd32589;
10'd240: sine_sample = -16'sd32609;
10'd241: sine_sample = -16'sd32628;
10'd242: sine_sample = -16'sd32646;
10'd243: sine_sample = -16'sd32663;
10'd244: sine_sample = -16'sd32678;
10'd245: sine_sample = -16'sd32692;
10'd246: sine_sample = -16'sd32705;
10'd247: sine_sample = -16'sd32717;
10'd248: sine_sample = -16'sd32728;
10'd249: sine_sample = -16'sd32737;
10'd250: sine_sample = -16'sd32745;
10'd251: sine_sample = -16'sd32752;
10'd252: sine_sample = -16'sd32757;
10'd253: sine_sample = -16'sd32761;
10'd254: sine_sample = -16'sd32765;
10'd255: sine_sample = -16'sd32766;
10'd256: sine_sample = -16'sd32767;
10'd257: sine_sample = -16'sd32766;
10'd258: sine_sample = -16'sd32765;
10'd259: sine_sample = -16'sd32761;
10'd260: sine_sample = -16'sd32757;
10'd261: sine_sample = -16'sd32752;
10'd262: sine_sample = -16'sd32745;
10'd263: sine_sample = -16'sd32737;
10'd264: sine_sample = -16'sd32728;
10'd265: sine_sample = -16'sd32717;
10'd266: sine_sample = -16'sd32705;
10'd267: sine_sample = -16'sd32692;
10'd268: sine_sample = -16'sd32678;
10'd269: sine_sample = -16'sd32663;
10'd270: sine_sample = -16'sd32646;
10'd271: sine_sample = -16'sd32628;
10'd272: sine_sample = -16'sd32609;
10'd273: sine_sample = -16'sd32589;
10'd274: sine_sample = -16'sd32567;
10'd275: sine_sample = -16'sd32545;
10'd276: sine_sample = -16'sd32521;
10'd277: sine_sample = -16'sd32495;
10'd278: sine_sample = -16'sd32469;
10'd279: sine_sample = -16'sd32441;
10'd280: sine_sample = -16'sd32412;
10'd281: sine_sample = -16'sd32382;
10'd282: sine_sample = -16'sd32351;
10'd283: sine_sample = -16'sd32318;
10'd284: sine_sample = -16'sd32285;
10'd285: sine_sample = -16'sd32250;
10'd286: sine_sample = -16'sd32213;
10'd287: sine_sample = -16'sd32176;
10'd288: sine_sample = -16'sd32137;
10'd289: sine_sample = -16'sd32098;
10'd290: sine_sample = -16'sd32057;
10'd291: sine_sample = -16'sd32014;
10'd292: sine_sample = -16'sd31971;
10'd293: sine_sample = -16'sd31926;
10'd294: sine_sample = -16'sd31880;
10'd295: sine_sample = -16'sd31833;
10'd296: sine_sample = -16'sd31785;
10'd297: sine_sample = -16'sd31736;
10'd298: sine_sample = -16'sd31685;
10'd299: sine_sample = -16'sd31633;
10'd300: sine_sample = -16'sd31580;
10'd301: sine_sample = -16'sd31526;
10'd302: sine_sample = -16'sd31470;
10'd303: sine_sample = -16'sd31414;
10'd304: sine_sample = -16'sd31356;
10'd305: sine_sample = -16'sd31297;
10'd306: sine_sample = -16'sd31237;
10'd307: sine_sample = -16'sd31176;
10'd308: sine_sample = -16'sd31113;
10'd309: sine_sample = -16'sd31050;
10'd310: sine_sample = -16'sd30985;
10'd311: sine_sample = -16'sd30919;
10'd312: sine_sample = -16'sd30852;
10'd313: sine_sample = -16'sd30783;
10'd314: sine_sample = -16'sd30714;
10'd315: sine_sample = -16'sd30643;
10'd316: sine_sample = -16'sd30571;
10'd317: sine_sample = -16'sd30498;
10'd318: sine_sample = -16'sd30424;
10'd319: sine_sample = -16'sd30349;
10'd320: sine_sample = -16'sd30273;
10'd321: sine_sample = -16'sd30195;
10'd322: sine_sample = -16'sd30117;
10'd323: sine_sample = -16'sd30037;
10'd324: sine_sample = -16'sd29956;
10'd325: sine_sample = -16'sd29874;
10'd326: sine_sample = -16'sd29791;
10'd327: sine_sample = -16'sd29706;
10'd328: sine_sample = -16'sd29621;
10'd329: sine_sample = -16'sd29534;
10'd330: sine_sample = -16'sd29447;
10'd331: sine_sample = -16'sd29358;
10'd332: sine_sample = -16'sd29268;
10'd333: sine_sample = -16'sd29177;
10'd334: sine_sample = -16'sd29085;
10'd335: sine_sample = -16'sd28992;
10'd336: sine_sample = -16'sd28898;
10'd337: sine_sample = -16'sd28803;
10'd338: sine_sample = -16'sd28706;
10'd339: sine_sample = -16'sd28609;
10'd340: sine_sample = -16'sd28510;
10'd341: sine_sample = -16'sd28411;
10'd342: sine_sample = -16'sd28310;
10'd343: sine_sample = -16'sd28208;
10'd344: sine_sample = -16'sd28105;
10'd345: sine_sample = -16'sd28001;
10'd346: sine_sample = -16'sd27896;
10'd347: sine_sample = -16'sd27790;
10'd348: sine_sample = -16'sd27683;
10'd349: sine_sample = -16'sd27575;
10'd350: sine_sample = -16'sd27466;
10'd351: sine_sample = -16'sd27356;
10'd352: sine_sample = -16'sd27245;
10'd353: sine_sample = -16'sd27133;
10'd354: sine_sample = -16'sd27019;
10'd355: sine_sample = -16'sd26905;
10'd356: sine_sample = -16'sd26790;
10'd357: sine_sample = -16'sd26674;
10'd358: sine_sample = -16'sd26556;
10'd359: sine_sample = -16'sd26438;
10'd360: sine_sample = -16'sd26319;
10'd361: sine_sample = -16'sd26198;
10'd362: sine_sample = -16'sd26077;
10'd363: sine_sample = -16'sd25955;
10'd364: sine_sample = -16'sd25832;
10'd365: sine_sample = -16'sd25708;
10'd366: sine_sample = -16'sd25582;
10'd367: sine_sample = -16'sd25456;
10'd368: sine_sample = -16'sd25329;
10'd369: sine_sample = -16'sd25201;
10'd370: sine_sample = -16'sd25072;
10'd371: sine_sample = -16'sd24942;
10'd372: sine_sample = -16'sd24811;
10'd373: sine_sample = -16'sd24680;
10'd374: sine_sample = -16'sd24547;
10'd375: sine_sample = -16'sd24413;
10'd376: sine_sample = -16'sd24279;
10'd377: sine_sample = -16'sd24143;
10'd378: sine_sample = -16'sd24007;
10'd379: sine_sample = -16'sd23870;
10'd380: sine_sample = -16'sd23731;
10'd381: sine_sample = -16'sd23592;
10'd382: sine_sample = -16'sd23452;
10'd383: sine_sample = -16'sd23311;
10'd384: sine_sample = -16'sd23170;
10'd385: sine_sample = -16'sd23027;
10'd386: sine_sample = -16'sd22884;
10'd387: sine_sample = -16'sd22739;
10'd388: sine_sample = -16'sd22594;
10'd389: sine_sample = -16'sd22448;
10'd390: sine_sample = -16'sd22301;
10'd391: sine_sample = -16'sd22154;
10'd392: sine_sample = -16'sd22005;
10'd393: sine_sample = -16'sd21856;
10'd394: sine_sample = -16'sd21705;
10'd395: sine_sample = -16'sd21554;
10'd396: sine_sample = -16'sd21403;
10'd397: sine_sample = -16'sd21250;
10'd398: sine_sample = -16'sd21096;
10'd399: sine_sample = -16'sd20942;
10'd400: sine_sample = -16'sd20787;
10'd401: sine_sample = -16'sd20631;
10'd402: sine_sample = -16'sd20475;
10'd403: sine_sample = -16'sd20317;
10'd404: sine_sample = -16'sd20159;
10'd405: sine_sample = -16'sd20000;
10'd406: sine_sample = -16'sd19841;
10'd407: sine_sample = -16'sd19680;
10'd408: sine_sample = -16'sd19519;
10'd409: sine_sample = -16'sd19357;
10'd410: sine_sample = -16'sd19195;
10'd411: sine_sample = -16'sd19032;
10'd412: sine_sample = -16'sd18868;
10'd413: sine_sample = -16'sd18703;
10'd414: sine_sample = -16'sd18537;
10'd415: sine_sample = -16'sd18371;
10'd416: sine_sample = -16'sd18204;
10'd417: sine_sample = -16'sd18037;
10'd418: sine_sample = -16'sd17869;
10'd419: sine_sample = -16'sd17700;
10'd420: sine_sample = -16'sd17530;
10'd421: sine_sample = -16'sd17360;
10'd422: sine_sample = -16'sd17189;
10'd423: sine_sample = -16'sd17018;
10'd424: sine_sample = -16'sd16846;
10'd425: sine_sample = -16'sd16673;
10'd426: sine_sample = -16'sd16499;
10'd427: sine_sample = -16'sd16325;
10'd428: sine_sample = -16'sd16151;
10'd429: sine_sample = -16'sd15976;
10'd430: sine_sample = -16'sd15800;
10'd431: sine_sample = -16'sd15623;
10'd432: sine_sample = -16'sd15446;
10'd433: sine_sample = -16'sd15269;
10'd434: sine_sample = -16'sd15090;
10'd435: sine_sample = -16'sd14912;
10'd436: sine_sample = -16'sd14732;
10'd437: sine_sample = -16'sd14553;
10'd438: sine_sample = -16'sd14372;
10'd439: sine_sample = -16'sd14191;
10'd440: sine_sample = -16'sd14010;
10'd441: sine_sample = -16'sd13828;
10'd442: sine_sample = -16'sd13645;
10'd443: sine_sample = -16'sd13462;
10'd444: sine_sample = -16'sd13279;
10'd445: sine_sample = -16'sd13094;
10'd446: sine_sample = -16'sd12910;
10'd447: sine_sample = -16'sd12725;
10'd448: sine_sample = -16'sd12539;
10'd449: sine_sample = -16'sd12353;
10'd450: sine_sample = -16'sd12167;
10'd451: sine_sample = -16'sd11980;
10'd452: sine_sample = -16'sd11793;
10'd453: sine_sample = -16'sd11605;
10'd454: sine_sample = -16'sd11417;
10'd455: sine_sample = -16'sd11228;
10'd456: sine_sample = -16'sd11039;
10'd457: sine_sample = -16'sd10849;
10'd458: sine_sample = -16'sd10659;
10'd459: sine_sample = -16'sd10469;
10'd460: sine_sample = -16'sd10278;
10'd461: sine_sample = -16'sd10087;
10'd462: sine_sample = -16'sd9896;
10'd463: sine_sample = -16'sd9704;
10'd464: sine_sample = -16'sd9512;
10'd465: sine_sample = -16'sd9319;
10'd466: sine_sample = -16'sd9126;
10'd467: sine_sample = -16'sd8933;
10'd468: sine_sample = -16'sd8739;
10'd469: sine_sample = -16'sd8545;
10'd470: sine_sample = -16'sd8351;
10'd471: sine_sample = -16'sd8157;
10'd472: sine_sample = -16'sd7962;
10'd473: sine_sample = -16'sd7767;
10'd474: sine_sample = -16'sd7571;
10'd475: sine_sample = -16'sd7375;
10'd476: sine_sample = -16'sd7179;
10'd477: sine_sample = -16'sd6983;
10'd478: sine_sample = -16'sd6786;
10'd479: sine_sample = -16'sd6590;
10'd480: sine_sample = -16'sd6393;
10'd481: sine_sample = -16'sd6195;
10'd482: sine_sample = -16'sd5998;
10'd483: sine_sample = -16'sd5800;
10'd484: sine_sample = -16'sd5602;
10'd485: sine_sample = -16'sd5404;
10'd486: sine_sample = -16'sd5205;
10'd487: sine_sample = -16'sd5007;
10'd488: sine_sample = -16'sd4808;
10'd489: sine_sample = -16'sd4609;
10'd490: sine_sample = -16'sd4410;
10'd491: sine_sample = -16'sd4210;
10'd492: sine_sample = -16'sd4011;
10'd493: sine_sample = -16'sd3811;
10'd494: sine_sample = -16'sd3612;
10'd495: sine_sample = -16'sd3412;
10'd496: sine_sample = -16'sd3212;
10'd497: sine_sample = -16'sd3012;
10'd498: sine_sample = -16'sd2811;
10'd499: sine_sample = -16'sd2611;
10'd500: sine_sample = -16'sd2410;
10'd501: sine_sample = -16'sd2210;
10'd502: sine_sample = -16'sd2009;
10'd503: sine_sample = -16'sd1809;
10'd504: sine_sample = -16'sd1608;
10'd505: sine_sample = -16'sd1407;
10'd506: sine_sample = -16'sd1206;
10'd507: sine_sample = -16'sd1005;
10'd508: sine_sample = -16'sd804;
10'd509: sine_sample = -16'sd603;
10'd510: sine_sample = -16'sd402;
10'd511: sine_sample = -16'sd201;
10'd512: sine_sample = -16'sd0;
10'd513: sine_sample = 16'sd201;
10'd514: sine_sample = 16'sd402;
10'd515: sine_sample = 16'sd603;
10'd516: sine_sample = 16'sd804;
10'd517: sine_sample = 16'sd1005;
10'd518: sine_sample = 16'sd1206;
10'd519: sine_sample = 16'sd1407;
10'd520: sine_sample = 16'sd1608;
10'd521: sine_sample = 16'sd1809;
10'd522: sine_sample = 16'sd2009;
10'd523: sine_sample = 16'sd2210;
10'd524: sine_sample = 16'sd2410;
10'd525: sine_sample = 16'sd2611;
10'd526: sine_sample = 16'sd2811;
10'd527: sine_sample = 16'sd3012;
10'd528: sine_sample = 16'sd3212;
10'd529: sine_sample = 16'sd3412;
10'd530: sine_sample = 16'sd3612;
10'd531: sine_sample = 16'sd3811;
10'd532: sine_sample = 16'sd4011;
10'd533: sine_sample = 16'sd4210;
10'd534: sine_sample = 16'sd4410;
10'd535: sine_sample = 16'sd4609;
10'd536: sine_sample = 16'sd4808;
10'd537: sine_sample = 16'sd5007;
10'd538: sine_sample = 16'sd5205;
10'd539: sine_sample = 16'sd5404;
10'd540: sine_sample = 16'sd5602;
10'd541: sine_sample = 16'sd5800;
10'd542: sine_sample = 16'sd5998;
10'd543: sine_sample = 16'sd6195;
10'd544: sine_sample = 16'sd6393;
10'd545: sine_sample = 16'sd6590;
10'd546: sine_sample = 16'sd6786;
10'd547: sine_sample = 16'sd6983;
10'd548: sine_sample = 16'sd7179;
10'd549: sine_sample = 16'sd7375;
10'd550: sine_sample = 16'sd7571;
10'd551: sine_sample = 16'sd7767;
10'd552: sine_sample = 16'sd7962;
10'd553: sine_sample = 16'sd8157;
10'd554: sine_sample = 16'sd8351;
10'd555: sine_sample = 16'sd8545;
10'd556: sine_sample = 16'sd8739;
10'd557: sine_sample = 16'sd8933;
10'd558: sine_sample = 16'sd9126;
10'd559: sine_sample = 16'sd9319;
10'd560: sine_sample = 16'sd9512;
10'd561: sine_sample = 16'sd9704;
10'd562: sine_sample = 16'sd9896;
10'd563: sine_sample = 16'sd10087;
10'd564: sine_sample = 16'sd10278;
10'd565: sine_sample = 16'sd10469;
10'd566: sine_sample = 16'sd10659;
10'd567: sine_sample = 16'sd10849;
10'd568: sine_sample = 16'sd11039;
10'd569: sine_sample = 16'sd11228;
10'd570: sine_sample = 16'sd11417;
10'd571: sine_sample = 16'sd11605;
10'd572: sine_sample = 16'sd11793;
10'd573: sine_sample = 16'sd11980;
10'd574: sine_sample = 16'sd12167;
10'd575: sine_sample = 16'sd12353;
10'd576: sine_sample = 16'sd12539;
10'd577: sine_sample = 16'sd12725;
10'd578: sine_sample = 16'sd12910;
10'd579: sine_sample = 16'sd13094;
10'd580: sine_sample = 16'sd13279;
10'd581: sine_sample = 16'sd13462;
10'd582: sine_sample = 16'sd13645;
10'd583: sine_sample = 16'sd13828;
10'd584: sine_sample = 16'sd14010;
10'd585: sine_sample = 16'sd14191;
10'd586: sine_sample = 16'sd14372;
10'd587: sine_sample = 16'sd14553;
10'd588: sine_sample = 16'sd14732;
10'd589: sine_sample = 16'sd14912;
10'd590: sine_sample = 16'sd15090;
10'd591: sine_sample = 16'sd15269;
10'd592: sine_sample = 16'sd15446;
10'd593: sine_sample = 16'sd15623;
10'd594: sine_sample = 16'sd15800;
10'd595: sine_sample = 16'sd15976;
10'd596: sine_sample = 16'sd16151;
10'd597: sine_sample = 16'sd16325;
10'd598: sine_sample = 16'sd16499;
10'd599: sine_sample = 16'sd16673;
10'd600: sine_sample = 16'sd16846;
10'd601: sine_sample = 16'sd17018;
10'd602: sine_sample = 16'sd17189;
10'd603: sine_sample = 16'sd17360;
10'd604: sine_sample = 16'sd17530;
10'd605: sine_sample = 16'sd17700;
10'd606: sine_sample = 16'sd17869;
10'd607: sine_sample = 16'sd18037;
10'd608: sine_sample = 16'sd18204;
10'd609: sine_sample = 16'sd18371;
10'd610: sine_sample = 16'sd18537;
10'd611: sine_sample = 16'sd18703;
10'd612: sine_sample = 16'sd18868;
10'd613: sine_sample = 16'sd19032;
10'd614: sine_sample = 16'sd19195;
10'd615: sine_sample = 16'sd19357;
10'd616: sine_sample = 16'sd19519;
10'd617: sine_sample = 16'sd19680;
10'd618: sine_sample = 16'sd19841;
10'd619: sine_sample = 16'sd20000;
10'd620: sine_sample = 16'sd20159;
10'd621: sine_sample = 16'sd20317;
10'd622: sine_sample = 16'sd20475;
10'd623: sine_sample = 16'sd20631;
10'd624: sine_sample = 16'sd20787;
10'd625: sine_sample = 16'sd20942;
10'd626: sine_sample = 16'sd21096;
10'd627: sine_sample = 16'sd21250;
10'd628: sine_sample = 16'sd21403;
10'd629: sine_sample = 16'sd21554;
10'd630: sine_sample = 16'sd21705;
10'd631: sine_sample = 16'sd21856;
10'd632: sine_sample = 16'sd22005;
10'd633: sine_sample = 16'sd22154;
10'd634: sine_sample = 16'sd22301;
10'd635: sine_sample = 16'sd22448;
10'd636: sine_sample = 16'sd22594;
10'd637: sine_sample = 16'sd22739;
10'd638: sine_sample = 16'sd22884;
10'd639: sine_sample = 16'sd23027;
10'd640: sine_sample = 16'sd23170;
10'd641: sine_sample = 16'sd23311;
10'd642: sine_sample = 16'sd23452;
10'd643: sine_sample = 16'sd23592;
10'd644: sine_sample = 16'sd23731;
10'd645: sine_sample = 16'sd23870;
10'd646: sine_sample = 16'sd24007;
10'd647: sine_sample = 16'sd24143;
10'd648: sine_sample = 16'sd24279;
10'd649: sine_sample = 16'sd24413;
10'd650: sine_sample = 16'sd24547;
10'd651: sine_sample = 16'sd24680;
10'd652: sine_sample = 16'sd24811;
10'd653: sine_sample = 16'sd24942;
10'd654: sine_sample = 16'sd25072;
10'd655: sine_sample = 16'sd25201;
10'd656: sine_sample = 16'sd25329;
10'd657: sine_sample = 16'sd25456;
10'd658: sine_sample = 16'sd25582;
10'd659: sine_sample = 16'sd25708;
10'd660: sine_sample = 16'sd25832;
10'd661: sine_sample = 16'sd25955;
10'd662: sine_sample = 16'sd26077;
10'd663: sine_sample = 16'sd26198;
10'd664: sine_sample = 16'sd26319;
10'd665: sine_sample = 16'sd26438;
10'd666: sine_sample = 16'sd26556;
10'd667: sine_sample = 16'sd26674;
10'd668: sine_sample = 16'sd26790;
10'd669: sine_sample = 16'sd26905;
10'd670: sine_sample = 16'sd27019;
10'd671: sine_sample = 16'sd27133;
10'd672: sine_sample = 16'sd27245;
10'd673: sine_sample = 16'sd27356;
10'd674: sine_sample = 16'sd27466;
10'd675: sine_sample = 16'sd27575;
10'd676: sine_sample = 16'sd27683;
10'd677: sine_sample = 16'sd27790;
10'd678: sine_sample = 16'sd27896;
10'd679: sine_sample = 16'sd28001;
10'd680: sine_sample = 16'sd28105;
10'd681: sine_sample = 16'sd28208;
10'd682: sine_sample = 16'sd28310;
10'd683: sine_sample = 16'sd28411;
10'd684: sine_sample = 16'sd28510;
10'd685: sine_sample = 16'sd28609;
10'd686: sine_sample = 16'sd28706;
10'd687: sine_sample = 16'sd28803;
10'd688: sine_sample = 16'sd28898;
10'd689: sine_sample = 16'sd28992;
10'd690: sine_sample = 16'sd29085;
10'd691: sine_sample = 16'sd29177;
10'd692: sine_sample = 16'sd29268;
10'd693: sine_sample = 16'sd29358;
10'd694: sine_sample = 16'sd29447;
10'd695: sine_sample = 16'sd29534;
10'd696: sine_sample = 16'sd29621;
10'd697: sine_sample = 16'sd29706;
10'd698: sine_sample = 16'sd29791;
10'd699: sine_sample = 16'sd29874;
10'd700: sine_sample = 16'sd29956;
10'd701: sine_sample = 16'sd30037;
10'd702: sine_sample = 16'sd30117;
10'd703: sine_sample = 16'sd30195;
10'd704: sine_sample = 16'sd30273;
10'd705: sine_sample = 16'sd30349;
10'd706: sine_sample = 16'sd30424;
10'd707: sine_sample = 16'sd30498;
10'd708: sine_sample = 16'sd30571;
10'd709: sine_sample = 16'sd30643;
10'd710: sine_sample = 16'sd30714;
10'd711: sine_sample = 16'sd30783;
10'd712: sine_sample = 16'sd30852;
10'd713: sine_sample = 16'sd30919;
10'd714: sine_sample = 16'sd30985;
10'd715: sine_sample = 16'sd31050;
10'd716: sine_sample = 16'sd31113;
10'd717: sine_sample = 16'sd31176;
10'd718: sine_sample = 16'sd31237;
10'd719: sine_sample = 16'sd31297;
10'd720: sine_sample = 16'sd31356;
10'd721: sine_sample = 16'sd31414;
10'd722: sine_sample = 16'sd31470;
10'd723: sine_sample = 16'sd31526;
10'd724: sine_sample = 16'sd31580;
10'd725: sine_sample = 16'sd31633;
10'd726: sine_sample = 16'sd31685;
10'd727: sine_sample = 16'sd31736;
10'd728: sine_sample = 16'sd31785;
10'd729: sine_sample = 16'sd31833;
10'd730: sine_sample = 16'sd31880;
10'd731: sine_sample = 16'sd31926;
10'd732: sine_sample = 16'sd31971;
10'd733: sine_sample = 16'sd32014;
10'd734: sine_sample = 16'sd32057;
10'd735: sine_sample = 16'sd32098;
10'd736: sine_sample = 16'sd32137;
10'd737: sine_sample = 16'sd32176;
10'd738: sine_sample = 16'sd32213;
10'd739: sine_sample = 16'sd32250;
10'd740: sine_sample = 16'sd32285;
10'd741: sine_sample = 16'sd32318;
10'd742: sine_sample = 16'sd32351;
10'd743: sine_sample = 16'sd32382;
10'd744: sine_sample = 16'sd32412;
10'd745: sine_sample = 16'sd32441;
10'd746: sine_sample = 16'sd32469;
10'd747: sine_sample = 16'sd32495;
10'd748: sine_sample = 16'sd32521;
10'd749: sine_sample = 16'sd32545;
10'd750: sine_sample = 16'sd32567;
10'd751: sine_sample = 16'sd32589;
10'd752: sine_sample = 16'sd32609;
10'd753: sine_sample = 16'sd32628;
10'd754: sine_sample = 16'sd32646;
10'd755: sine_sample = 16'sd32663;
10'd756: sine_sample = 16'sd32678;
10'd757: sine_sample = 16'sd32692;
10'd758: sine_sample = 16'sd32705;
10'd759: sine_sample = 16'sd32717;
10'd760: sine_sample = 16'sd32728;
10'd761: sine_sample = 16'sd32737;
10'd762: sine_sample = 16'sd32745;
10'd763: sine_sample = 16'sd32752;
10'd764: sine_sample = 16'sd32757;
10'd765: sine_sample = 16'sd32761;
10'd766: sine_sample = 16'sd32765;
10'd767: sine_sample = 16'sd32766;
10'd768: sine_sample = 16'sd32767;
10'd769: sine_sample = 16'sd32766;
10'd770: sine_sample = 16'sd32765;
10'd771: sine_sample = 16'sd32761;
10'd772: sine_sample = 16'sd32757;
10'd773: sine_sample = 16'sd32752;
10'd774: sine_sample = 16'sd32745;
10'd775: sine_sample = 16'sd32737;
10'd776: sine_sample = 16'sd32728;
10'd777: sine_sample = 16'sd32717;
10'd778: sine_sample = 16'sd32705;
10'd779: sine_sample = 16'sd32692;
10'd780: sine_sample = 16'sd32678;
10'd781: sine_sample = 16'sd32663;
10'd782: sine_sample = 16'sd32646;
10'd783: sine_sample = 16'sd32628;
10'd784: sine_sample = 16'sd32609;
10'd785: sine_sample = 16'sd32589;
10'd786: sine_sample = 16'sd32567;
10'd787: sine_sample = 16'sd32545;
10'd788: sine_sample = 16'sd32521;
10'd789: sine_sample = 16'sd32495;
10'd790: sine_sample = 16'sd32469;
10'd791: sine_sample = 16'sd32441;
10'd792: sine_sample = 16'sd32412;
10'd793: sine_sample = 16'sd32382;
10'd794: sine_sample = 16'sd32351;
10'd795: sine_sample = 16'sd32318;
10'd796: sine_sample = 16'sd32285;
10'd797: sine_sample = 16'sd32250;
10'd798: sine_sample = 16'sd32213;
10'd799: sine_sample = 16'sd32176;
10'd800: sine_sample = 16'sd32137;
10'd801: sine_sample = 16'sd32098;
10'd802: sine_sample = 16'sd32057;
10'd803: sine_sample = 16'sd32014;
10'd804: sine_sample = 16'sd31971;
10'd805: sine_sample = 16'sd31926;
10'd806: sine_sample = 16'sd31880;
10'd807: sine_sample = 16'sd31833;
10'd808: sine_sample = 16'sd31785;
10'd809: sine_sample = 16'sd31736;
10'd810: sine_sample = 16'sd31685;
10'd811: sine_sample = 16'sd31633;
10'd812: sine_sample = 16'sd31580;
10'd813: sine_sample = 16'sd31526;
10'd814: sine_sample = 16'sd31470;
10'd815: sine_sample = 16'sd31414;
10'd816: sine_sample = 16'sd31356;
10'd817: sine_sample = 16'sd31297;
10'd818: sine_sample = 16'sd31237;
10'd819: sine_sample = 16'sd31176;
10'd820: sine_sample = 16'sd31113;
10'd821: sine_sample = 16'sd31050;
10'd822: sine_sample = 16'sd30985;
10'd823: sine_sample = 16'sd30919;
10'd824: sine_sample = 16'sd30852;
10'd825: sine_sample = 16'sd30783;
10'd826: sine_sample = 16'sd30714;
10'd827: sine_sample = 16'sd30643;
10'd828: sine_sample = 16'sd30571;
10'd829: sine_sample = 16'sd30498;
10'd830: sine_sample = 16'sd30424;
10'd831: sine_sample = 16'sd30349;
10'd832: sine_sample = 16'sd30273;
10'd833: sine_sample = 16'sd30195;
10'd834: sine_sample = 16'sd30117;
10'd835: sine_sample = 16'sd30037;
10'd836: sine_sample = 16'sd29956;
10'd837: sine_sample = 16'sd29874;
10'd838: sine_sample = 16'sd29791;
10'd839: sine_sample = 16'sd29706;
10'd840: sine_sample = 16'sd29621;
10'd841: sine_sample = 16'sd29534;
10'd842: sine_sample = 16'sd29447;
10'd843: sine_sample = 16'sd29358;
10'd844: sine_sample = 16'sd29268;
10'd845: sine_sample = 16'sd29177;
10'd846: sine_sample = 16'sd29085;
10'd847: sine_sample = 16'sd28992;
10'd848: sine_sample = 16'sd28898;
10'd849: sine_sample = 16'sd28803;
10'd850: sine_sample = 16'sd28706;
10'd851: sine_sample = 16'sd28609;
10'd852: sine_sample = 16'sd28510;
10'd853: sine_sample = 16'sd28411;
10'd854: sine_sample = 16'sd28310;
10'd855: sine_sample = 16'sd28208;
10'd856: sine_sample = 16'sd28105;
10'd857: sine_sample = 16'sd28001;
10'd858: sine_sample = 16'sd27896;
10'd859: sine_sample = 16'sd27790;
10'd860: sine_sample = 16'sd27683;
10'd861: sine_sample = 16'sd27575;
10'd862: sine_sample = 16'sd27466;
10'd863: sine_sample = 16'sd27356;
10'd864: sine_sample = 16'sd27245;
10'd865: sine_sample = 16'sd27133;
10'd866: sine_sample = 16'sd27019;
10'd867: sine_sample = 16'sd26905;
10'd868: sine_sample = 16'sd26790;
10'd869: sine_sample = 16'sd26674;
10'd870: sine_sample = 16'sd26556;
10'd871: sine_sample = 16'sd26438;
10'd872: sine_sample = 16'sd26319;
10'd873: sine_sample = 16'sd26198;
10'd874: sine_sample = 16'sd26077;
10'd875: sine_sample = 16'sd25955;
10'd876: sine_sample = 16'sd25832;
10'd877: sine_sample = 16'sd25708;
10'd878: sine_sample = 16'sd25582;
10'd879: sine_sample = 16'sd25456;
10'd880: sine_sample = 16'sd25329;
10'd881: sine_sample = 16'sd25201;
10'd882: sine_sample = 16'sd25072;
10'd883: sine_sample = 16'sd24942;
10'd884: sine_sample = 16'sd24811;
10'd885: sine_sample = 16'sd24680;
10'd886: sine_sample = 16'sd24547;
10'd887: sine_sample = 16'sd24413;
10'd888: sine_sample = 16'sd24279;
10'd889: sine_sample = 16'sd24143;
10'd890: sine_sample = 16'sd24007;
10'd891: sine_sample = 16'sd23870;
10'd892: sine_sample = 16'sd23731;
10'd893: sine_sample = 16'sd23592;
10'd894: sine_sample = 16'sd23452;
10'd895: sine_sample = 16'sd23311;
10'd896: sine_sample = 16'sd23170;
10'd897: sine_sample = 16'sd23027;
10'd898: sine_sample = 16'sd22884;
10'd899: sine_sample = 16'sd22739;
10'd900: sine_sample = 16'sd22594;
10'd901: sine_sample = 16'sd22448;
10'd902: sine_sample = 16'sd22301;
10'd903: sine_sample = 16'sd22154;
10'd904: sine_sample = 16'sd22005;
10'd905: sine_sample = 16'sd21856;
10'd906: sine_sample = 16'sd21705;
10'd907: sine_sample = 16'sd21554;
10'd908: sine_sample = 16'sd21403;
10'd909: sine_sample = 16'sd21250;
10'd910: sine_sample = 16'sd21096;
10'd911: sine_sample = 16'sd20942;
10'd912: sine_sample = 16'sd20787;
10'd913: sine_sample = 16'sd20631;
10'd914: sine_sample = 16'sd20475;
10'd915: sine_sample = 16'sd20317;
10'd916: sine_sample = 16'sd20159;
10'd917: sine_sample = 16'sd20000;
10'd918: sine_sample = 16'sd19841;
10'd919: sine_sample = 16'sd19680;
10'd920: sine_sample = 16'sd19519;
10'd921: sine_sample = 16'sd19357;
10'd922: sine_sample = 16'sd19195;
10'd923: sine_sample = 16'sd19032;
10'd924: sine_sample = 16'sd18868;
10'd925: sine_sample = 16'sd18703;
10'd926: sine_sample = 16'sd18537;
10'd927: sine_sample = 16'sd18371;
10'd928: sine_sample = 16'sd18204;
10'd929: sine_sample = 16'sd18037;
10'd930: sine_sample = 16'sd17869;
10'd931: sine_sample = 16'sd17700;
10'd932: sine_sample = 16'sd17530;
10'd933: sine_sample = 16'sd17360;
10'd934: sine_sample = 16'sd17189;
10'd935: sine_sample = 16'sd17018;
10'd936: sine_sample = 16'sd16846;
10'd937: sine_sample = 16'sd16673;
10'd938: sine_sample = 16'sd16499;
10'd939: sine_sample = 16'sd16325;
10'd940: sine_sample = 16'sd16151;
10'd941: sine_sample = 16'sd15976;
10'd942: sine_sample = 16'sd15800;
10'd943: sine_sample = 16'sd15623;
10'd944: sine_sample = 16'sd15446;
10'd945: sine_sample = 16'sd15269;
10'd946: sine_sample = 16'sd15090;
10'd947: sine_sample = 16'sd14912;
10'd948: sine_sample = 16'sd14732;
10'd949: sine_sample = 16'sd14553;
10'd950: sine_sample = 16'sd14372;
10'd951: sine_sample = 16'sd14191;
10'd952: sine_sample = 16'sd14010;
10'd953: sine_sample = 16'sd13828;
10'd954: sine_sample = 16'sd13645;
10'd955: sine_sample = 16'sd13462;
10'd956: sine_sample = 16'sd13279;
10'd957: sine_sample = 16'sd13094;
10'd958: sine_sample = 16'sd12910;
10'd959: sine_sample = 16'sd12725;
10'd960: sine_sample = 16'sd12539;
10'd961: sine_sample = 16'sd12353;
10'd962: sine_sample = 16'sd12167;
10'd963: sine_sample = 16'sd11980;
10'd964: sine_sample = 16'sd11793;
10'd965: sine_sample = 16'sd11605;
10'd966: sine_sample = 16'sd11417;
10'd967: sine_sample = 16'sd11228;
10'd968: sine_sample = 16'sd11039;
10'd969: sine_sample = 16'sd10849;
10'd970: sine_sample = 16'sd10659;
10'd971: sine_sample = 16'sd10469;
10'd972: sine_sample = 16'sd10278;
10'd973: sine_sample = 16'sd10087;
10'd974: sine_sample = 16'sd9896;
10'd975: sine_sample = 16'sd9704;
10'd976: sine_sample = 16'sd9512;
10'd977: sine_sample = 16'sd9319;
10'd978: sine_sample = 16'sd9126;
10'd979: sine_sample = 16'sd8933;
10'd980: sine_sample = 16'sd8739;
10'd981: sine_sample = 16'sd8545;
10'd982: sine_sample = 16'sd8351;
10'd983: sine_sample = 16'sd8157;
10'd984: sine_sample = 16'sd7962;
10'd985: sine_sample = 16'sd7767;
10'd986: sine_sample = 16'sd7571;
10'd987: sine_sample = 16'sd7375;
10'd988: sine_sample = 16'sd7179;
10'd989: sine_sample = 16'sd6983;
10'd990: sine_sample = 16'sd6786;
10'd991: sine_sample = 16'sd6590;
10'd992: sine_sample = 16'sd6393;
10'd993: sine_sample = 16'sd6195;
10'd994: sine_sample = 16'sd5998;
10'd995: sine_sample = 16'sd5800;
10'd996: sine_sample = 16'sd5602;
10'd997: sine_sample = 16'sd5404;
10'd998: sine_sample = 16'sd5205;
10'd999: sine_sample = 16'sd5007;
10'd1000: sine_sample = 16'sd4808;
10'd1001: sine_sample = 16'sd4609;
10'd1002: sine_sample = 16'sd4410;
10'd1003: sine_sample = 16'sd4210;
10'd1004: sine_sample = 16'sd4011;
10'd1005: sine_sample = 16'sd3811;
10'd1006: sine_sample = 16'sd3612;
10'd1007: sine_sample = 16'sd3412;
10'd1008: sine_sample = 16'sd3212;
10'd1009: sine_sample = 16'sd3012;
10'd1010: sine_sample = 16'sd2811;
10'd1011: sine_sample = 16'sd2611;
10'd1012: sine_sample = 16'sd2410;
10'd1013: sine_sample = 16'sd2210;
10'd1014: sine_sample = 16'sd2009;
10'd1015: sine_sample = 16'sd1809;
10'd1016: sine_sample = 16'sd1608;
10'd1017: sine_sample = 16'sd1407;
10'd1018: sine_sample = 16'sd1206;
10'd1019: sine_sample = 16'sd1005;
10'd1020: sine_sample = 16'sd804;
10'd1021: sine_sample = 16'sd603;
10'd1022: sine_sample = 16'sd402;
10'd1023: sine_sample = 16'sd201;
default: sine_sample = 16'sd0;
endcase
end
endmodule | 3 |
140,478 | data/full_repos/permissive/90330506/verilog/src/spi_controller.v | 90,330,506 | spi_controller.v | v | 127 | 95 | [] | [] | [] | [(2, 126)] | null | null | 1: b'%Error: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:26: Cannot find file containing module: \'spi_slave\'\n spi_slave spi_slave (i_reset,1\'b1,8\'b0,1\'b1,1\'b0,i_SPI_sclk,i_SPI_mosi,sdout,SPI_done,rdata);\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_slave\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_slave.v\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/spi_slave.sv\n spi_slave\n spi_slave.v\n spi_slave.sv\n obj_dir/spi_slave\n obj_dir/spi_slave.v\n obj_dir/spi_slave.sv\n%Error: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:32: Cannot find file containing module: \'two_flop_cdc\'\n two_flop_cdc two_flop_cdc(.i_clk(i_clk), .i_sig(SPI_done), .o_sig(SPI_done_meta_stable));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:33: Cannot find file containing module: \'pos_edge_det\'\n pos_edge_det pos_edge_det (.sig(SPI_done_meta_stable), .clk(i_clk), .pe(done_sync));\n ^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:46: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'7\'h0\' generates 7 bits.\n : ... In instance spi_controller\n o_SPI_tuning_code <= 7\'b0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:79: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'31\'h0\' generates 31 bits.\n : ... In instance spi_controller\n o_SPI_tuning_code <= 31\'b0; \n ^~\n%Error: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:116: Cannot find file containing module: \'tuning_code_lookup\'\n tuning_code_lookup tuning_code_lookup(.midi_byte(midi_byte),.tuning_code(tuning_code));\n ^~~~~~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:121: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'midi_byte\' generates 7 bits.\n : ... In instance spi_controller\n leds_0 <= midi_byte;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/spi_controller.v:122: Operator ASSIGNDLY expects 8 bits on the Assign RHS, but Assign RHS\'s VARREF \'o_SPI_velocity\' generates 7 bits.\n : ... In instance spi_controller\n leds_2 <= o_SPI_velocity;\n ^~\n%Error: Exiting due to 4 error(s), 4 warning(s)\n' | 308,568 | module | module spi_controller (
input wire i_clk,
input wire i_reset,
input wire i_SPI_sclk,
input wire i_SPI_mosi,
output reg o_SPI_note_status,
output reg [7:0] o_SPI_voice_index,
output reg [31:0] o_SPI_tuning_code,
output reg [6:0] o_SPI_velocity,
output reg o_SPI_flag_dds,
output reg o_SPI_flag_adsr,
output reg [7:0] leds_0,leds_1,leds_2,
output wire [1:0] byte_counter_debug
);
parameter NOTEON = 8'h90;
parameter NOTEOFF = 8'h80;
wire [7:0] rdata;
wire sdout;
wire SPI_done;
spi_slave spi_slave (i_reset,1'b1,8'b0,1'b1,1'b0,i_SPI_sclk,i_SPI_mosi,sdout,SPI_done,rdata);
wire SPI_done_meta_stable;
wire done_sync;
two_flop_cdc two_flop_cdc(.i_clk(i_clk), .i_sig(SPI_done), .o_sig(SPI_done_meta_stable));
pos_edge_det pos_edge_det (.sig(SPI_done_meta_stable), .clk(i_clk), .pe(done_sync));
reg [1:0] byte_counter;
assign byte_counter_debug[0] = done_sync;
assign byte_counter_debug[1] = SPI_done;
wire [31:0] tuning_code;
reg [6:0] midi_byte;
always @(posedge i_clk) begin
if (i_reset == 1'b1) begin
o_SPI_note_status <= 1'b1;
o_SPI_voice_index <= 8'b0;
o_SPI_tuning_code <= 7'b0;
o_SPI_velocity <= 7'b0;
o_SPI_flag_dds <= 1'b0;
o_SPI_flag_adsr <= 1'b0;
byte_counter <= 2'd0;
end
else begin
case (byte_counter)
0:
begin
o_SPI_flag_dds <= 1'b0;
o_SPI_flag_adsr <= 1'b0;
if (done_sync) begin
if (rdata == NOTEON) begin
o_SPI_note_status <= 1'b1;
byte_counter <= 2'd1;
end
else if (rdata == NOTEOFF) begin
o_SPI_note_status <= 1'b0;
byte_counter <= 2'd1;
end
end
end
1:
begin
if (done_sync) begin
if (o_SPI_note_status == 1'b1) begin
o_SPI_voice_index <= rdata;
byte_counter <= 2'd2;
end
else if (o_SPI_note_status == 1'b0) begin
o_SPI_voice_index <= rdata;
o_SPI_tuning_code <= 31'b0;
midi_byte <= 7'b0;
o_SPI_velocity <= 7'b0;
o_SPI_flag_adsr <= 1'b1;
byte_counter <= 2'd0;
end
end
end
2:
begin
if (done_sync) begin
if (rdata[7] == 1'b0) begin
midi_byte <= rdata[6:0];
byte_counter <= 2'd3;
end
else
byte_counter <= 2'd0;
end
end
3:
begin
if (done_sync) begin
if (rdata[7] == 1'b0) begin
o_SPI_tuning_code <= tuning_code;
o_SPI_velocity <= rdata[6:0];
byte_counter <= 2'd0;
o_SPI_flag_adsr <= 1'b1;
o_SPI_flag_dds <= 1'b1;
end
else
byte_counter <= 2'd0;
end
end
endcase
end
end
tuning_code_lookup tuning_code_lookup(.midi_byte(midi_byte),.tuning_code(tuning_code));
always @(posedge i_clk) begin
if (o_SPI_flag_adsr | o_SPI_flag_dds) begin
leds_0 <= midi_byte;
leds_2 <= o_SPI_velocity;
end
end
endmodule | module spi_controller (
input wire i_clk,
input wire i_reset,
input wire i_SPI_sclk,
input wire i_SPI_mosi,
output reg o_SPI_note_status,
output reg [7:0] o_SPI_voice_index,
output reg [31:0] o_SPI_tuning_code,
output reg [6:0] o_SPI_velocity,
output reg o_SPI_flag_dds,
output reg o_SPI_flag_adsr,
output reg [7:0] leds_0,leds_1,leds_2,
output wire [1:0] byte_counter_debug
); |
parameter NOTEON = 8'h90;
parameter NOTEOFF = 8'h80;
wire [7:0] rdata;
wire sdout;
wire SPI_done;
spi_slave spi_slave (i_reset,1'b1,8'b0,1'b1,1'b0,i_SPI_sclk,i_SPI_mosi,sdout,SPI_done,rdata);
wire SPI_done_meta_stable;
wire done_sync;
two_flop_cdc two_flop_cdc(.i_clk(i_clk), .i_sig(SPI_done), .o_sig(SPI_done_meta_stable));
pos_edge_det pos_edge_det (.sig(SPI_done_meta_stable), .clk(i_clk), .pe(done_sync));
reg [1:0] byte_counter;
assign byte_counter_debug[0] = done_sync;
assign byte_counter_debug[1] = SPI_done;
wire [31:0] tuning_code;
reg [6:0] midi_byte;
always @(posedge i_clk) begin
if (i_reset == 1'b1) begin
o_SPI_note_status <= 1'b1;
o_SPI_voice_index <= 8'b0;
o_SPI_tuning_code <= 7'b0;
o_SPI_velocity <= 7'b0;
o_SPI_flag_dds <= 1'b0;
o_SPI_flag_adsr <= 1'b0;
byte_counter <= 2'd0;
end
else begin
case (byte_counter)
0:
begin
o_SPI_flag_dds <= 1'b0;
o_SPI_flag_adsr <= 1'b0;
if (done_sync) begin
if (rdata == NOTEON) begin
o_SPI_note_status <= 1'b1;
byte_counter <= 2'd1;
end
else if (rdata == NOTEOFF) begin
o_SPI_note_status <= 1'b0;
byte_counter <= 2'd1;
end
end
end
1:
begin
if (done_sync) begin
if (o_SPI_note_status == 1'b1) begin
o_SPI_voice_index <= rdata;
byte_counter <= 2'd2;
end
else if (o_SPI_note_status == 1'b0) begin
o_SPI_voice_index <= rdata;
o_SPI_tuning_code <= 31'b0;
midi_byte <= 7'b0;
o_SPI_velocity <= 7'b0;
o_SPI_flag_adsr <= 1'b1;
byte_counter <= 2'd0;
end
end
end
2:
begin
if (done_sync) begin
if (rdata[7] == 1'b0) begin
midi_byte <= rdata[6:0];
byte_counter <= 2'd3;
end
else
byte_counter <= 2'd0;
end
end
3:
begin
if (done_sync) begin
if (rdata[7] == 1'b0) begin
o_SPI_tuning_code <= tuning_code;
o_SPI_velocity <= rdata[6:0];
byte_counter <= 2'd0;
o_SPI_flag_adsr <= 1'b1;
o_SPI_flag_dds <= 1'b1;
end
else
byte_counter <= 2'd0;
end
end
endcase
end
end
tuning_code_lookup tuning_code_lookup(.midi_byte(midi_byte),.tuning_code(tuning_code));
always @(posedge i_clk) begin
if (o_SPI_flag_adsr | o_SPI_flag_dds) begin
leds_0 <= midi_byte;
leds_2 <= o_SPI_velocity;
end
end
endmodule | 3 |
140,479 | data/full_repos/permissive/90330506/verilog/src/spi_slave.v | 90,330,506 | spi_slave.v | v | 96 | 81 | [] | ['general public license', 'free software foundation'] | [] | [(46, 95)] | null | data/verilator_xmls/022c2d50-1d6c-43ac-bdc0-6a20d91b40dd.xml | null | 308,569 | module | module spi_slave (reset,ten,tdata,mlb,ss,sck,sdin, sdout,done,rdata);
input wire reset,ss,sck,sdin,ten,mlb;
input wire [7:0] tdata;
output wire sdout;
output reg done;
output reg [7:0] rdata;
reg [7:0] treg,rreg;
reg [3:0] nb;
wire sout;
assign sout=mlb?treg[7]:treg[0];
assign sdout=( (!ss)&&ten )?sout:1'bz;
always @(posedge sck)
begin
if (reset==1'b1)
begin rreg = 8'h00; rdata = 8'h00; done = 0; nb = 0; end
else if (!ss) begin
if(mlb==0)
begin rreg ={sdin,rreg[7:1]}; end
else
begin rreg ={rreg[6:0],sdin}; end
nb=nb+4'd1;
if(nb!=8) done=0;
else begin rdata=rreg; done=1; nb=0; end
end
end
always @(negedge sck)
begin
if (reset==1'b1)
begin treg = 8'hFF; end
else begin
if(!ss) begin
if(nb==0) treg=tdata;
else begin
if(mlb==0)
begin treg = {1'b1,treg[7:1]}; end
else
begin treg = {treg[6:0],1'b1}; end
end
end
end
end
endmodule | module spi_slave (reset,ten,tdata,mlb,ss,sck,sdin, sdout,done,rdata); |
input wire reset,ss,sck,sdin,ten,mlb;
input wire [7:0] tdata;
output wire sdout;
output reg done;
output reg [7:0] rdata;
reg [7:0] treg,rreg;
reg [3:0] nb;
wire sout;
assign sout=mlb?treg[7]:treg[0];
assign sdout=( (!ss)&&ten )?sout:1'bz;
always @(posedge sck)
begin
if (reset==1'b1)
begin rreg = 8'h00; rdata = 8'h00; done = 0; nb = 0; end
else if (!ss) begin
if(mlb==0)
begin rreg ={sdin,rreg[7:1]}; end
else
begin rreg ={rreg[6:0],sdin}; end
nb=nb+4'd1;
if(nb!=8) done=0;
else begin rdata=rreg; done=1; nb=0; end
end
end
always @(negedge sck)
begin
if (reset==1'b1)
begin treg = 8'hFF; end
else begin
if(!ss) begin
if(nb==0) treg=tdata;
else begin
if(mlb==0)
begin treg = {1'b1,treg[7:1]}; end
else
begin treg = {treg[6:0],1'b1}; end
end
end
end
end
endmodule | 3 |
140,480 | data/full_repos/permissive/90330506/verilog/src/square_wave.v | 90,330,506 | square_wave.v | v | 16 | 40 | [] | [] | [] | [(1, 15)] | null | data/verilator_xmls/104a8fd1-92f7-462c-b6e6-59db49f2c042.xml | null | 308,570 | module | module square_wave(
input wire [9:0] theta,
output reg signed [15:0] square_sample
);
always @(theta) begin
if (theta >= 10'd512)
square_sample <= 16'sd32767;
else
square_sample <= -16'sd32767;
end
endmodule | module square_wave(
input wire [9:0] theta,
output reg signed [15:0] square_sample
); |
always @(theta) begin
if (theta >= 10'd512)
square_sample <= 16'sd32767;
else
square_sample <= -16'sd32767;
end
endmodule | 3 |
140,482 | data/full_repos/permissive/90330506/verilog/src/tuning_code_lookup.v | 90,330,506 | tuning_code_lookup.v | v | 142 | 41 | [] | [] | [] | [(1, 141)] | null | data/verilator_xmls/78f34381-4cc9-4d63-a661-4b546c79c472.xml | null | 308,572 | module | module tuning_code_lookup(
input wire [6:0] midi_byte,
output reg [31:0] tuning_code
);
always @(midi_byte) begin
case(midi_byte)
7'd0: tuning_code = 32'd1685510;
7'd1: tuning_code = 32'd1785736;
7'd2: tuning_code = 32'd1891921;
7'd3: tuning_code = 32'd2004420;
7'd4: tuning_code = 32'd2123609;
7'd5: tuning_code = 32'd2249886;
7'd6: tuning_code = 32'd2383671;
7'd7: tuning_code = 32'd2525411;
7'd8: tuning_code = 32'd2675580;
7'd9: tuning_code = 32'd2834678;
7'd10: tuning_code = 32'd3003237;
7'd11: tuning_code = 32'd3181819;
7'd12: tuning_code = 32'd3371020;
7'd13: tuning_code = 32'd3571471;
7'd14: tuning_code = 32'd3783842;
7'd15: tuning_code = 32'd4008841;
7'd16: tuning_code = 32'd4247219;
7'd17: tuning_code = 32'd4499771;
7'd18: tuning_code = 32'd4767342;
7'd19: tuning_code = 32'd5050823;
7'd20: tuning_code = 32'd5351160;
7'd21: tuning_code = 32'd5669357;
7'd22: tuning_code = 32'd6006474;
7'd23: tuning_code = 32'd6363638;
7'd24: tuning_code = 32'd6742039;
7'd25: tuning_code = 32'd7142942;
7'd26: tuning_code = 32'd7567683;
7'd27: tuning_code = 32'd8017681;
7'd28: tuning_code = 32'd8494437;
7'd29: tuning_code = 32'd8999543;
7'd30: tuning_code = 32'd9534684;
7'd31: tuning_code = 32'd10101645;
7'd32: tuning_code = 32'd10702321;
7'd33: tuning_code = 32'd11338714;
7'd34: tuning_code = 32'd12012949;
7'd35: tuning_code = 32'd12727276;
7'd36: tuning_code = 32'd13484079;
7'd37: tuning_code = 32'd14285884;
7'd38: tuning_code = 32'd15135367;
7'd39: tuning_code = 32'd16035363;
7'd40: tuning_code = 32'd16988875;
7'd41: tuning_code = 32'd17999086;
7'd42: tuning_code = 32'd19069367;
7'd43: tuning_code = 32'd20203291;
7'd44: tuning_code = 32'd21404641;
7'd45: tuning_code = 32'd22677427;
7'd46: tuning_code = 32'd24025897;
7'd47: tuning_code = 32'd25454552;
7'd48: tuning_code = 32'd26968158;
7'd49: tuning_code = 32'd28571768;
7'd50: tuning_code = 32'd30270734;
7'd51: tuning_code = 32'd32070725;
7'd52: tuning_code = 32'd33977750;
7'd53: tuning_code = 32'd35998172;
7'd54: tuning_code = 32'd38138735;
7'd55: tuning_code = 32'd40406582;
7'd56: tuning_code = 32'd42809282;
7'd57: tuning_code = 32'd45354855;
7'd58: tuning_code = 32'd48051795;
7'd59: tuning_code = 32'd50909103;
7'd60: tuning_code = 32'd53936316;
7'd61: tuning_code = 32'd57143536;
7'd62: tuning_code = 32'd60541468;
7'd63: tuning_code = 32'd64141451;
7'd64: tuning_code = 32'd67955500;
7'd65: tuning_code = 32'd71996344;
7'd66: tuning_code = 32'd76277469;
7'd67: tuning_code = 32'd80813164;
7'd68: tuning_code = 32'd85618565;
7'd69: tuning_code = 32'd90709709;
7'd70: tuning_code = 32'd96103589;
7'd71: tuning_code = 32'd101818206;
7'd72: tuning_code = 32'd107872632;
7'd73: tuning_code = 32'd114287072;
7'd74: tuning_code = 32'd121082935;
7'd75: tuning_code = 32'd128282901;
7'd76: tuning_code = 32'd135910999;
7'd77: tuning_code = 32'd143992688;
7'd78: tuning_code = 32'd152554939;
7'd79: tuning_code = 32'd161626327;
7'd80: tuning_code = 32'd171237129;
7'd81: tuning_code = 32'd181419419;
7'd82: tuning_code = 32'd192207179;
7'd83: tuning_code = 32'd203636412;
7'd84: tuning_code = 32'd215745263;
7'd85: tuning_code = 32'd228574144;
7'd86: tuning_code = 32'd242165870;
7'd87: tuning_code = 32'd256565802;
7'd88: tuning_code = 32'd271821999;
7'd89: tuning_code = 32'd287985376;
7'd90: tuning_code = 32'd305109877;
7'd91: tuning_code = 32'd323252655;
7'd92: tuning_code = 32'd342474258;
7'd93: tuning_code = 32'd362838837;
7'd94: tuning_code = 32'd384414357;
7'd95: tuning_code = 32'd407272824;
7'd96: tuning_code = 32'd431490527;
7'd97: tuning_code = 32'd457148289;
7'd98: tuning_code = 32'd484331740;
7'd99: tuning_code = 32'd513131604;
7'd100: tuning_code = 32'd543643997;
7'd101: tuning_code = 32'd575970752;
7'd102: tuning_code = 32'd610219755;
7'd103: tuning_code = 32'd646505310;
7'd104: tuning_code = 32'd684948516;
7'd105: tuning_code = 32'd725677674;
7'd106: tuning_code = 32'd768828714;
7'd107: tuning_code = 32'd814545649;
7'd108: tuning_code = 32'd862981054;
7'd109: tuning_code = 32'd914296577;
7'd110: tuning_code = 32'd968663481;
7'd111: tuning_code = 32'd1026263209;
7'd112: tuning_code = 32'd1087287995;
7'd113: tuning_code = 32'd1151941504;
7'd114: tuning_code = 32'd1220439510;
7'd115: tuning_code = 32'd1293010620;
7'd116: tuning_code = 32'd1369897032;
7'd117: tuning_code = 32'd1451355349;
7'd118: tuning_code = 32'd1537657429;
7'd119: tuning_code = 32'd1629091297;
7'd120: tuning_code = 32'd1725962107;
7'd121: tuning_code = 32'd1828593155;
7'd122: tuning_code = 32'd1937326962;
7'd123: tuning_code = 32'd2052526418;
7'd124: tuning_code = 32'd2174575990;
7'd125: tuning_code = 32'd2303883007;
7'd126: tuning_code = 32'd2440879020;
7'd127: tuning_code = 32'd2586021239;
default: tuning_code <= 32'd66213;
endcase
end
endmodule | module tuning_code_lookup(
input wire [6:0] midi_byte,
output reg [31:0] tuning_code
); |
always @(midi_byte) begin
case(midi_byte)
7'd0: tuning_code = 32'd1685510;
7'd1: tuning_code = 32'd1785736;
7'd2: tuning_code = 32'd1891921;
7'd3: tuning_code = 32'd2004420;
7'd4: tuning_code = 32'd2123609;
7'd5: tuning_code = 32'd2249886;
7'd6: tuning_code = 32'd2383671;
7'd7: tuning_code = 32'd2525411;
7'd8: tuning_code = 32'd2675580;
7'd9: tuning_code = 32'd2834678;
7'd10: tuning_code = 32'd3003237;
7'd11: tuning_code = 32'd3181819;
7'd12: tuning_code = 32'd3371020;
7'd13: tuning_code = 32'd3571471;
7'd14: tuning_code = 32'd3783842;
7'd15: tuning_code = 32'd4008841;
7'd16: tuning_code = 32'd4247219;
7'd17: tuning_code = 32'd4499771;
7'd18: tuning_code = 32'd4767342;
7'd19: tuning_code = 32'd5050823;
7'd20: tuning_code = 32'd5351160;
7'd21: tuning_code = 32'd5669357;
7'd22: tuning_code = 32'd6006474;
7'd23: tuning_code = 32'd6363638;
7'd24: tuning_code = 32'd6742039;
7'd25: tuning_code = 32'd7142942;
7'd26: tuning_code = 32'd7567683;
7'd27: tuning_code = 32'd8017681;
7'd28: tuning_code = 32'd8494437;
7'd29: tuning_code = 32'd8999543;
7'd30: tuning_code = 32'd9534684;
7'd31: tuning_code = 32'd10101645;
7'd32: tuning_code = 32'd10702321;
7'd33: tuning_code = 32'd11338714;
7'd34: tuning_code = 32'd12012949;
7'd35: tuning_code = 32'd12727276;
7'd36: tuning_code = 32'd13484079;
7'd37: tuning_code = 32'd14285884;
7'd38: tuning_code = 32'd15135367;
7'd39: tuning_code = 32'd16035363;
7'd40: tuning_code = 32'd16988875;
7'd41: tuning_code = 32'd17999086;
7'd42: tuning_code = 32'd19069367;
7'd43: tuning_code = 32'd20203291;
7'd44: tuning_code = 32'd21404641;
7'd45: tuning_code = 32'd22677427;
7'd46: tuning_code = 32'd24025897;
7'd47: tuning_code = 32'd25454552;
7'd48: tuning_code = 32'd26968158;
7'd49: tuning_code = 32'd28571768;
7'd50: tuning_code = 32'd30270734;
7'd51: tuning_code = 32'd32070725;
7'd52: tuning_code = 32'd33977750;
7'd53: tuning_code = 32'd35998172;
7'd54: tuning_code = 32'd38138735;
7'd55: tuning_code = 32'd40406582;
7'd56: tuning_code = 32'd42809282;
7'd57: tuning_code = 32'd45354855;
7'd58: tuning_code = 32'd48051795;
7'd59: tuning_code = 32'd50909103;
7'd60: tuning_code = 32'd53936316;
7'd61: tuning_code = 32'd57143536;
7'd62: tuning_code = 32'd60541468;
7'd63: tuning_code = 32'd64141451;
7'd64: tuning_code = 32'd67955500;
7'd65: tuning_code = 32'd71996344;
7'd66: tuning_code = 32'd76277469;
7'd67: tuning_code = 32'd80813164;
7'd68: tuning_code = 32'd85618565;
7'd69: tuning_code = 32'd90709709;
7'd70: tuning_code = 32'd96103589;
7'd71: tuning_code = 32'd101818206;
7'd72: tuning_code = 32'd107872632;
7'd73: tuning_code = 32'd114287072;
7'd74: tuning_code = 32'd121082935;
7'd75: tuning_code = 32'd128282901;
7'd76: tuning_code = 32'd135910999;
7'd77: tuning_code = 32'd143992688;
7'd78: tuning_code = 32'd152554939;
7'd79: tuning_code = 32'd161626327;
7'd80: tuning_code = 32'd171237129;
7'd81: tuning_code = 32'd181419419;
7'd82: tuning_code = 32'd192207179;
7'd83: tuning_code = 32'd203636412;
7'd84: tuning_code = 32'd215745263;
7'd85: tuning_code = 32'd228574144;
7'd86: tuning_code = 32'd242165870;
7'd87: tuning_code = 32'd256565802;
7'd88: tuning_code = 32'd271821999;
7'd89: tuning_code = 32'd287985376;
7'd90: tuning_code = 32'd305109877;
7'd91: tuning_code = 32'd323252655;
7'd92: tuning_code = 32'd342474258;
7'd93: tuning_code = 32'd362838837;
7'd94: tuning_code = 32'd384414357;
7'd95: tuning_code = 32'd407272824;
7'd96: tuning_code = 32'd431490527;
7'd97: tuning_code = 32'd457148289;
7'd98: tuning_code = 32'd484331740;
7'd99: tuning_code = 32'd513131604;
7'd100: tuning_code = 32'd543643997;
7'd101: tuning_code = 32'd575970752;
7'd102: tuning_code = 32'd610219755;
7'd103: tuning_code = 32'd646505310;
7'd104: tuning_code = 32'd684948516;
7'd105: tuning_code = 32'd725677674;
7'd106: tuning_code = 32'd768828714;
7'd107: tuning_code = 32'd814545649;
7'd108: tuning_code = 32'd862981054;
7'd109: tuning_code = 32'd914296577;
7'd110: tuning_code = 32'd968663481;
7'd111: tuning_code = 32'd1026263209;
7'd112: tuning_code = 32'd1087287995;
7'd113: tuning_code = 32'd1151941504;
7'd114: tuning_code = 32'd1220439510;
7'd115: tuning_code = 32'd1293010620;
7'd116: tuning_code = 32'd1369897032;
7'd117: tuning_code = 32'd1451355349;
7'd118: tuning_code = 32'd1537657429;
7'd119: tuning_code = 32'd1629091297;
7'd120: tuning_code = 32'd1725962107;
7'd121: tuning_code = 32'd1828593155;
7'd122: tuning_code = 32'd1937326962;
7'd123: tuning_code = 32'd2052526418;
7'd124: tuning_code = 32'd2174575990;
7'd125: tuning_code = 32'd2303883007;
7'd126: tuning_code = 32'd2440879020;
7'd127: tuning_code = 32'd2586021239;
default: tuning_code <= 32'd66213;
endcase
end
endmodule | 3 |
140,483 | data/full_repos/permissive/90330506/verilog/src/two_flop_cdc.v | 90,330,506 | two_flop_cdc.v | v | 17 | 32 | [] | [] | [] | [(1, 16)] | null | data/verilator_xmls/88505e41-7e1d-47c2-a596-9283a597bcc4.xml | null | 308,573 | module | module two_flop_cdc(
input wire i_clk,
input wire i_sig,
output wire o_sig
);
reg [1:0] cdc;
always @(posedge i_clk) begin
cdc[0] <= i_sig;
cdc[1] <= cdc[0];
end
assign o_sig = cdc[1];
endmodule | module two_flop_cdc(
input wire i_clk,
input wire i_sig,
output wire o_sig
); |
reg [1:0] cdc;
always @(posedge i_clk) begin
cdc[0] <= i_sig;
cdc[1] <= cdc[0];
end
assign o_sig = cdc[1];
endmodule | 3 |
140,484 | data/full_repos/permissive/90330506/verilog/src/voice_controller.v | 90,330,506 | voice_controller.v | v | 118 | 246 | [] | [] | [] | [(2, 117)] | null | null | 1: b'%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:23: Cannot find file containing module: \'dds\'\n dds dds (.i_clk(i_clk),\n ^~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/dds\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/dds.v\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/dds.sv\n dds\n dds.v\n dds.sv\n obj_dir/dds\n obj_dir/dds.v\n obj_dir/dds.sv\n%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:39: Cannot find file containing module: \'wavetable\'\n wavetable wavetable(.i_clk(i_clk),.i_reset(i_reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:45: Cannot find file containing module: \'ADSR\'\n ADSR ADSR (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:97: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'adsr_output\' generates 16 bits.\n : ... In instance voice_controller\n mixer_buffer <= mixer_buffer + adsr_output;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:100: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'adsr_output\' generates 16 bits.\n : ... In instance voice_controller\n o_mixed_sample <= mixer_buffer + adsr_output; \n ^\n%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:112: Cannot find file containing module: \'bus_change_detector\'\n bus_change_detector #(.BUS_WIDTH(10)) bus_change_detector_phase(.i_clk(i_clk), .i_bus(phase), .o_bus_change(change_phase_pulse));\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:113: Cannot find file containing module: \'bus_change_detector\'\n bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_wavetable(.i_clk(i_clk), .i_bus(wavetable_output), .o_bus_change(change_wavetable_pulse));\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/src/voice_controller.v:114: Cannot find file containing module: \'bus_change_detector\'\n bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_adsr(.i_clk(i_clk), .i_bus(adsr_output), .o_bus_change(change_adsr_pulse));\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n' | 308,574 | module | module voice_controller(
input wire i_clk,
input wire i_reset,
input wire i_SPI_note_status,
input wire [7:0] i_SPI_voice_index,
input wire [31:0] i_SPI_tuning_code,
input wire [6:0] i_SPI_velocity,
input wire i_SPI_flag_dds,
input wire i_SPI_flag_adsr,
output reg signed [23:0] o_mixed_sample
);
reg [7:0] voice_index;
wire [9:0] phase;
wire [7:0] dds_voice_index_next;
reg [1:0] pipeline_state ;
dds dds (.i_clk(i_clk),
.i_reset(i_reset),
.i_SPI_flag(i_SPI_flag_dds),
.i_SPI_tuning_code(i_SPI_tuning_code),
.i_SPI_voice_index(i_SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(phase),
.o_voice_index_next(dds_voice_index_next)
);
reg [3:0] wave_select;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(i_clk),.i_reset(i_reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
wire [7:0] adsr_voice_index_next;
wire signed [15:0] adsr_output;
ADSR ADSR (
.i_clk(i_clk),
.i_reset(i_reset),
.i_SPI_flag(i_SPI_flag_adsr),
.i_SPI_note_status(i_SPI_note_status),
.i_SPI_voice_index(i_SPI_voice_index),
.i_voice_index(wavetable_voice_index_next),
.i_pipeline_state(pipeline_state),
.i_sample(wavetable_output),
.o_voice_index_next(adsr_voice_index_next),
.o_sample(adsr_output)
);
always @(posedge i_clk) begin
if (i_reset) begin
pipeline_state <= 2'b0;
wave_select <= 4'd0;
end
else begin
if (pipeline_state < 2'd2)
pipeline_state <= pipeline_state + 1'b1;
else
pipeline_state <= 2'd0;
end
end
reg signed [23:0] mixer_buffer;
always @(posedge i_clk) begin
if (i_reset) begin
voice_index <= 8'd0;
end
else begin
if (pipeline_state == 2'd0)
voice_index <= voice_index + 1'b1;
end
end
always @(posedge i_clk) begin
if (i_reset) begin
o_mixed_sample <= 24'sd0;
mixer_buffer <= 24'sd0;
end
else begin
if (pipeline_state == 2'd2) begin
mixer_buffer <= mixer_buffer + adsr_output;
if (voice_index == 8'h00) begin
o_mixed_sample <= mixer_buffer + adsr_output;
mixer_buffer <= 24'sd0;
end
end
end
end
wire change_phase_pulse;
wire change_wavetable_pulse;
wire change_adsr_pulse;
bus_change_detector #(.BUS_WIDTH(10)) bus_change_detector_phase(.i_clk(i_clk), .i_bus(phase), .o_bus_change(change_phase_pulse));
bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_wavetable(.i_clk(i_clk), .i_bus(wavetable_output), .o_bus_change(change_wavetable_pulse));
bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_adsr(.i_clk(i_clk), .i_bus(adsr_output), .o_bus_change(change_adsr_pulse));
endmodule | module voice_controller(
input wire i_clk,
input wire i_reset,
input wire i_SPI_note_status,
input wire [7:0] i_SPI_voice_index,
input wire [31:0] i_SPI_tuning_code,
input wire [6:0] i_SPI_velocity,
input wire i_SPI_flag_dds,
input wire i_SPI_flag_adsr,
output reg signed [23:0] o_mixed_sample
); |
reg [7:0] voice_index;
wire [9:0] phase;
wire [7:0] dds_voice_index_next;
reg [1:0] pipeline_state ;
dds dds (.i_clk(i_clk),
.i_reset(i_reset),
.i_SPI_flag(i_SPI_flag_dds),
.i_SPI_tuning_code(i_SPI_tuning_code),
.i_SPI_voice_index(i_SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(phase),
.o_voice_index_next(dds_voice_index_next)
);
reg [3:0] wave_select;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(i_clk),.i_reset(i_reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
wire [7:0] adsr_voice_index_next;
wire signed [15:0] adsr_output;
ADSR ADSR (
.i_clk(i_clk),
.i_reset(i_reset),
.i_SPI_flag(i_SPI_flag_adsr),
.i_SPI_note_status(i_SPI_note_status),
.i_SPI_voice_index(i_SPI_voice_index),
.i_voice_index(wavetable_voice_index_next),
.i_pipeline_state(pipeline_state),
.i_sample(wavetable_output),
.o_voice_index_next(adsr_voice_index_next),
.o_sample(adsr_output)
);
always @(posedge i_clk) begin
if (i_reset) begin
pipeline_state <= 2'b0;
wave_select <= 4'd0;
end
else begin
if (pipeline_state < 2'd2)
pipeline_state <= pipeline_state + 1'b1;
else
pipeline_state <= 2'd0;
end
end
reg signed [23:0] mixer_buffer;
always @(posedge i_clk) begin
if (i_reset) begin
voice_index <= 8'd0;
end
else begin
if (pipeline_state == 2'd0)
voice_index <= voice_index + 1'b1;
end
end
always @(posedge i_clk) begin
if (i_reset) begin
o_mixed_sample <= 24'sd0;
mixer_buffer <= 24'sd0;
end
else begin
if (pipeline_state == 2'd2) begin
mixer_buffer <= mixer_buffer + adsr_output;
if (voice_index == 8'h00) begin
o_mixed_sample <= mixer_buffer + adsr_output;
mixer_buffer <= 24'sd0;
end
end
end
end
wire change_phase_pulse;
wire change_wavetable_pulse;
wire change_adsr_pulse;
bus_change_detector #(.BUS_WIDTH(10)) bus_change_detector_phase(.i_clk(i_clk), .i_bus(phase), .o_bus_change(change_phase_pulse));
bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_wavetable(.i_clk(i_clk), .i_bus(wavetable_output), .o_bus_change(change_wavetable_pulse));
bus_change_detector #(.BUS_WIDTH(16)) bus_change_detector_adsr(.i_clk(i_clk), .i_bus(adsr_output), .o_bus_change(change_adsr_pulse));
endmodule | 3 |
140,485 | data/full_repos/permissive/90330506/verilog/src/wavetable.v | 90,330,506 | wavetable.v | v | 91 | 52 | [] | [] | [] | [(2, 90)] | null | null | 1: b"%Error: data/full_repos/permissive/90330506/verilog/src/wavetable.v:29: Cannot find file containing module: 'sine_table'\n sine_table sine_table\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/sine_table\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/sine_table.v\n data/full_repos/permissive/90330506/verilog/src,data/full_repos/permissive/90330506/sine_table.sv\n sine_table\n sine_table.v\n sine_table.sv\n obj_dir/sine_table\n obj_dir/sine_table.v\n obj_dir/sine_table.sv\n%Error: data/full_repos/permissive/90330506/verilog/src/wavetable.v:36: Cannot find file containing module: 'square_wave'\n square_wave square_wave\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 308,575 | module | module wavetable(
input wire i_clk,
input wire i_reset,
input wire [9:0] i_phase,
input wire [3:0] i_wave_select,
input wire [7:0] i_voice_index,
input wire [1:0] i_pipeline_state,
output reg [7:0] o_voice_index_next,
output reg signed [15:0] o_sample
);
wire signed [15:0] square_sample;
wire signed [15:0] sine_sample;
sine_table sine_table
(
.theta(i_phase),
.sine_sample(sine_sample)
);
square_wave square_wave
(
.theta(i_phase),
.square_sample(square_sample)
);
always @(posedge i_clk) begin
case (i_pipeline_state)
0: begin
o_voice_index_next <= i_voice_index;
end
1: begin
case (i_wave_select)
4'd0: begin
o_sample <= sine_sample;
end
4'd1: begin
o_sample <= square_sample;
end
4'd2: begin
o_sample <= square_sample;
end
4'd3: begin
o_sample <= square_sample;
end
default: begin
o_sample <= square_sample;
end
endcase
end
2: begin
end
endcase
end
endmodule | module wavetable(
input wire i_clk,
input wire i_reset,
input wire [9:0] i_phase,
input wire [3:0] i_wave_select,
input wire [7:0] i_voice_index,
input wire [1:0] i_pipeline_state,
output reg [7:0] o_voice_index_next,
output reg signed [15:0] o_sample
); |
wire signed [15:0] square_sample;
wire signed [15:0] sine_sample;
sine_table sine_table
(
.theta(i_phase),
.sine_sample(sine_sample)
);
square_wave square_wave
(
.theta(i_phase),
.square_sample(square_sample)
);
always @(posedge i_clk) begin
case (i_pipeline_state)
0: begin
o_voice_index_next <= i_voice_index;
end
1: begin
case (i_wave_select)
4'd0: begin
o_sample <= sine_sample;
end
4'd1: begin
o_sample <= square_sample;
end
4'd2: begin
o_sample <= square_sample;
end
4'd3: begin
o_sample <= square_sample;
end
default: begin
o_sample <= square_sample;
end
endcase
end
2: begin
end
endcase
end
endmodule | 3 |
140,486 | data/full_repos/permissive/90330506/verilog/src/debugging/dds_impl.v | 90,330,506 | dds_impl.v | v | 129 | 248 | [] | [] | [] | [(2, 128)] | null | null | 1: b'%Error: data/full_repos/permissive/90330506/verilog/src/debugging/dds_impl.v:27: Cannot find file containing module: \'dds\'\n dds dds (.i_clk(ref_clk),\n ^~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/src/debugging,data/full_repos/permissive/90330506/dds\n data/full_repos/permissive/90330506/verilog/src/debugging,data/full_repos/permissive/90330506/dds.v\n data/full_repos/permissive/90330506/verilog/src/debugging,data/full_repos/permissive/90330506/dds.sv\n dds\n dds.v\n dds.sv\n obj_dir/dds\n obj_dir/dds.v\n obj_dir/dds.sv\n%Error: data/full_repos/permissive/90330506/verilog/src/debugging/dds_impl.v:44: Cannot find file containing module: \'wavetable\'\n wavetable wavetable(.i_clk(ref_clk),.i_reset(reset),.i_phase(o_phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));\n ^~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/src/debugging/dds_impl.v:121: Operator ASSIGNDLY expects 25 bits on the Assign RHS, but Assign RHS\'s CONST \'24\'h0\' generates 24 bits.\n : ... In instance top_dds\n ledcounter <= 24\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 308,576 | module | module top_dds(
input wire ref_clk,
input wire button,
output reg signed [15:0] dac_out,
output wire [7:0] leds_0_b,
output reg [7:0] leds_1_b,
output reg [7:0] leds_2_b
);
wire reset;
assign reset = ~button;
reg [1:0] pipeline_state;
reg [7:0] voice_index;
wire [9:0] o_phase;
reg SPI_flag;
reg [7:0] SPI_voice_index;
reg [31:0] SPI_tuning_code;
wire [7:0] dds_voice_index_next;
dds dds (.i_clk(ref_clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_tuning_code(SPI_tuning_code),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(o_phase),
.o_voice_index_next(dds_voice_index_next)
);
reg [3:0] wave_select = 4'd1;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(ref_clk),.i_reset(reset),.i_phase(o_phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
always @(posedge ref_clk) begin
if (reset) begin
voice_index <= 8'd0;
end
else begin
if (pipeline_state == 2'd0)
voice_index <= voice_index + 1'b1;
end
end
always @(posedge ref_clk) begin
if (reset) begin
pipeline_state <= 2'b0;
end
else begin
if (pipeline_state < 2'd3)
pipeline_state <= pipeline_state + 1'b1;
else
pipeline_state <= 2'd0;
end
end
reg signed [15:0] phase_mem [7:0];
always @(posedge ref_clk) begin
if (pipeline_state == 2'd2) begin
phase_mem[voice_index-2]<= wavetable_output;
end
end
always @(posedge ref_clk) begin
if (voice_index == 8'd7 & pipeline_state == 2'd3) begin
dac_out <= phase_mem[5] + 16'd32768;
end
end
reg [23:0] counter;
always @(posedge ref_clk) begin
if (reset) begin
counter <= 24'd0;
SPI_flag <= 1'b0;
SPI_tuning_code <= 32'd0;
end
else begin
if (counter == 24'd12000000) begin
SPI_flag <=1'b1;
SPI_tuning_code <= 32'd100000000;
SPI_voice_index <= 8'd5;
end
else begin
SPI_flag <= 1'b0;
counter <= counter + 1'b1;
end
end
end
always @(posedge ref_clk) begin
if (SPI_flag)
leds_2_b <= 8'b1;
else
leds_2_b <= 8'b0;
end
reg [24:0] ledcounter;
always @(posedge ref_clk) begin
if (reset)
ledcounter <= 24'd0;
else begin
ledcounter <= ledcounter +1'b1;
leds_1_b <= ledcounter[24:17];
end
end
endmodule | module top_dds(
input wire ref_clk,
input wire button,
output reg signed [15:0] dac_out,
output wire [7:0] leds_0_b,
output reg [7:0] leds_1_b,
output reg [7:0] leds_2_b
); |
wire reset;
assign reset = ~button;
reg [1:0] pipeline_state;
reg [7:0] voice_index;
wire [9:0] o_phase;
reg SPI_flag;
reg [7:0] SPI_voice_index;
reg [31:0] SPI_tuning_code;
wire [7:0] dds_voice_index_next;
dds dds (.i_clk(ref_clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_tuning_code(SPI_tuning_code),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(o_phase),
.o_voice_index_next(dds_voice_index_next)
);
reg [3:0] wave_select = 4'd1;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(ref_clk),.i_reset(reset),.i_phase(o_phase),.i_wave_select(wave_select),.i_voice_index(dds_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
always @(posedge ref_clk) begin
if (reset) begin
voice_index <= 8'd0;
end
else begin
if (pipeline_state == 2'd0)
voice_index <= voice_index + 1'b1;
end
end
always @(posedge ref_clk) begin
if (reset) begin
pipeline_state <= 2'b0;
end
else begin
if (pipeline_state < 2'd3)
pipeline_state <= pipeline_state + 1'b1;
else
pipeline_state <= 2'd0;
end
end
reg signed [15:0] phase_mem [7:0];
always @(posedge ref_clk) begin
if (pipeline_state == 2'd2) begin
phase_mem[voice_index-2]<= wavetable_output;
end
end
always @(posedge ref_clk) begin
if (voice_index == 8'd7 & pipeline_state == 2'd3) begin
dac_out <= phase_mem[5] + 16'd32768;
end
end
reg [23:0] counter;
always @(posedge ref_clk) begin
if (reset) begin
counter <= 24'd0;
SPI_flag <= 1'b0;
SPI_tuning_code <= 32'd0;
end
else begin
if (counter == 24'd12000000) begin
SPI_flag <=1'b1;
SPI_tuning_code <= 32'd100000000;
SPI_voice_index <= 8'd5;
end
else begin
SPI_flag <= 1'b0;
counter <= counter + 1'b1;
end
end
end
always @(posedge ref_clk) begin
if (SPI_flag)
leds_2_b <= 8'b1;
else
leds_2_b <= 8'b0;
end
reg [24:0] ledcounter;
always @(posedge ref_clk) begin
if (reset)
ledcounter <= 24'd0;
else begin
ledcounter <= ledcounter +1'b1;
leds_1_b <= ledcounter[24:17];
end
end
endmodule | 3 |
140,487 | data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v | 90,330,506 | adsr_tb.v | v | 100 | 46 | [] | [] | [] | [(3, 99)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #4 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 1;\n ^\n%Error: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:22: Cannot find file containing module: \'dds\'\n dds dds1 (.clk(clk),\n ^~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds.v\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds.sv\n dds\n dds.v\n dds.sv\n obj_dir/dds\n obj_dir/dds.v\n obj_dir/dds.sv\n%Error: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:30: Cannot find file containing module: \'square_wave\'\n square_wave square_wave\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/tb/adsr_tb.v:37: Cannot find file containing module: \'ADSR\'\n ADSR ADSR1 (.clk(clk),\n ^~~~\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,577 | module | module adsr_tb;
reg clk;
reg reset;
wire [15:0] attack_amt;
wire [15:0] decay_amt;
wire [15:0] sustain_amt;
wire [15:0] rel_amt;
reg key_state;
reg [7:0] voice_index = 0;
wire signed [15:0] input_sample;
wire signed [15:0] output_sample;
wire [9:0] dds_phase;
dds dds1 (.clk(clk),
.reset(reset),
.delta_phase(100000000),
.voice_index(voice_index),
.output_phase(dds_phase)
);
square_wave square_wave
(.clk(clk),
.theta(dds_phase),
.square_sample(input_sample)
);
ADSR ADSR1 (.clk(clk),
.reset(reset),
.voice_index(voice_index),
.attack_amt(attack_amt),
.decay_amt(decay_amt),
.sustain_amt(sustain_amt),
.rel_amt(rel_amt),
.key_state(key_state),
.input_sample(input_sample),
.output_sample(output_sample)
);
reg [10-1:0] mem_phase [(1<<8)-1:0];
reg signed [16-1:0] mem_input [(1<<8)-1:0];
reg signed [16-1:0] mem_output [(1<<8)-1:0];
always begin
#1 clk = !clk;
end
always begin
#4
voice_index = voice_index + 1;
mem_output[voice_index]=output_sample;
mem_input[voice_index]=input_sample;
mem_phase[voice_index]=dds_phase;
if (voice_index == 254)
key_state = 1;
else
key_state = 0;
end
assign attack_amt = 400;
assign decay_amt = 200;
assign sustain_amt = 20000;
assign rel_amt = 100;
initial
begin
clk = 1;
key_state = 0;
reset = 0;
#10 reset = 1;
end
endmodule | module adsr_tb; |
reg clk;
reg reset;
wire [15:0] attack_amt;
wire [15:0] decay_amt;
wire [15:0] sustain_amt;
wire [15:0] rel_amt;
reg key_state;
reg [7:0] voice_index = 0;
wire signed [15:0] input_sample;
wire signed [15:0] output_sample;
wire [9:0] dds_phase;
dds dds1 (.clk(clk),
.reset(reset),
.delta_phase(100000000),
.voice_index(voice_index),
.output_phase(dds_phase)
);
square_wave square_wave
(.clk(clk),
.theta(dds_phase),
.square_sample(input_sample)
);
ADSR ADSR1 (.clk(clk),
.reset(reset),
.voice_index(voice_index),
.attack_amt(attack_amt),
.decay_amt(decay_amt),
.sustain_amt(sustain_amt),
.rel_amt(rel_amt),
.key_state(key_state),
.input_sample(input_sample),
.output_sample(output_sample)
);
reg [10-1:0] mem_phase [(1<<8)-1:0];
reg signed [16-1:0] mem_input [(1<<8)-1:0];
reg signed [16-1:0] mem_output [(1<<8)-1:0];
always begin
#1 clk = !clk;
end
always begin
#4
voice_index = voice_index + 1;
mem_output[voice_index]=output_sample;
mem_input[voice_index]=input_sample;
mem_phase[voice_index]=dds_phase;
if (voice_index == 254)
key_state = 1;
else
key_state = 0;
end
assign attack_amt = 400;
assign decay_amt = 200;
assign sustain_amt = 20000;
assign rel_amt = 100;
initial
begin
clk = 1;
key_state = 0;
reset = 0;
#10 reset = 1;
end
endmodule | 3 |
140,488 | data/full_repos/permissive/90330506/verilog/tb/dds_tb.v | 90,330,506 | dds_tb.v | v | 146 | 240 | [] | [] | [] | [(3, 145)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:118: Unsupported: Ignoring delay on this delayed statement.\n #10 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #4\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:126: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #10000000\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:132: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:19: Cannot find file containing module: \'dds\'\n dds dds (.i_clk(clk),\n ^~~\n ... Looked in:\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds.v\n data/full_repos/permissive/90330506/verilog/tb,data/full_repos/permissive/90330506/dds.sv\n dds\n dds.v\n dds.sv\n obj_dir/dds\n obj_dir/dds.v\n obj_dir/dds.sv\n%Error: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:33: Cannot find file containing module: \'wavetable\'\n wavetable wavetable(.i_clk(clk),.i_reset(reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(o_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:37: Cannot find file containing module: \'ADSR\'\n ADSR ADSR (\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:80: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h0\' generates 4 bits.\n : ... In instance dds_tb\n pipeline_state = 4\'d0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:82: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h1\' generates 4 bits.\n : ... In instance dds_tb\n pipeline_state = 4\'d1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:84: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'4\'h2\' generates 4 bits.\n : ... In instance dds_tb\n pipeline_state = 4\'d2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:91: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'voice_chain_output\' generates 16 bits.\n : ... In instance dds_tb\n output_sample <= mixer_buffer + voice_chain_output; \n ^\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:95: Operator ADD expects 24 bits on the RHS, but RHS\'s VARREF \'voice_chain_output\' generates 16 bits.\n : ... In instance dds_tb\n mixer_buffer <= mixer_buffer + voice_chain_output;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90330506/verilog/tb/dds_tb.v:102: Operator EQ expects 4 bits on the LHS, but LHS\'s VARREF \'pipeline_state\' generates 2 bits.\n : ... In instance dds_tb\n if (pipeline_state == 4\'d0)\n ^~\n%Error: Exiting due to 3 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,578 | module | module dds_tb;
reg clk;
reg reset;
reg [7:0] voice_index = 0;
reg SPI_flag;
reg [31:0] SPI_tuning_code;
reg [7:0] SPI_voice_index;
wire [9:0] phase;
wire [7:0] o_voice_index_next;
reg [1:0] pipeline_state ;
dds dds (.i_clk(clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_tuning_code(SPI_tuning_code),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(phase),
.o_voice_index_next(o_voice_index_next)
);
reg [3:0] wave_select = 4'd1;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(clk),.i_reset(reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(o_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
wire signed [15:0] voice_chain_output;
reg SPI_note_status;
ADSR ADSR (
.i_clk(clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_note_status(SPI_note_status),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(wavetable_voice_index_next),
.i_pipeline_state(pipeline_state),
.i_sample(wavetable_output),
.i_attack_amt(16'd10000),
.i_decay_amt(16'd10000),
.i_sustain_amt(16'd10000),
.i_rel_amt(16'd1000),
.o_sample(voice_chain_output)
);
reg [10-1:0] mem_phase [(1<<8)-1:0];
reg signed [16-1:0] mem_input [(1<<8)-1:0];
reg signed [16-1:0] mem_output [(1<<8)-1:0];
always begin
#1 clk = !clk;
end
reg signed [23:0] output_sample;
reg signed [23:0] mixer_buffer;
always begin
#2
pipeline_state = 4'd0;
#2
pipeline_state = 4'd1;
#2
pipeline_state = 4'd2;
mem_phase[voice_index]=phase;
mem_input[voice_index]=wavetable_output;
mem_output[voice_index]=voice_chain_output;
if (voice_index == 8'hff) begin
output_sample <= mixer_buffer + voice_chain_output;
mixer_buffer <= 24'sd0;
end
else begin
mixer_buffer <= mixer_buffer + voice_chain_output;
end
end
reg send_SPI;
always @(posedge clk) begin
if (pipeline_state == 4'd0)
voice_index = voice_index + 1;
end
integer lp;
initial
begin
clk = 1;
reset = 1;
send_SPI = 0;
#10 reset = 0;
#4
SPI_flag = 1;
SPI_tuning_code = 20*1000000;
SPI_voice_index = 5;
SPI_note_status = 1'b1;
#2
SPI_flag = 0;
#10000000
SPI_flag = 1;
SPI_voice_index = 5;
SPI_note_status = 1'b0;
#2
SPI_flag = 0;
end
endmodule | module dds_tb; |
reg clk;
reg reset;
reg [7:0] voice_index = 0;
reg SPI_flag;
reg [31:0] SPI_tuning_code;
reg [7:0] SPI_voice_index;
wire [9:0] phase;
wire [7:0] o_voice_index_next;
reg [1:0] pipeline_state ;
dds dds (.i_clk(clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_tuning_code(SPI_tuning_code),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(voice_index),
.i_pipeline_state(pipeline_state),
.o_phase(phase),
.o_voice_index_next(o_voice_index_next)
);
reg [3:0] wave_select = 4'd1;
wire signed [15:0] wavetable_output;
wire [7:0] wavetable_voice_index_next;
wavetable wavetable(.i_clk(clk),.i_reset(reset),.i_phase(phase),.i_wave_select(wave_select),.i_voice_index(o_voice_index_next),.i_pipeline_state(pipeline_state),.o_voice_index_next(wavetable_voice_index_next),.o_sample(wavetable_output));
wire signed [15:0] voice_chain_output;
reg SPI_note_status;
ADSR ADSR (
.i_clk(clk),
.i_reset(reset),
.i_SPI_flag(SPI_flag),
.i_SPI_note_status(SPI_note_status),
.i_SPI_voice_index(SPI_voice_index),
.i_voice_index(wavetable_voice_index_next),
.i_pipeline_state(pipeline_state),
.i_sample(wavetable_output),
.i_attack_amt(16'd10000),
.i_decay_amt(16'd10000),
.i_sustain_amt(16'd10000),
.i_rel_amt(16'd1000),
.o_sample(voice_chain_output)
);
reg [10-1:0] mem_phase [(1<<8)-1:0];
reg signed [16-1:0] mem_input [(1<<8)-1:0];
reg signed [16-1:0] mem_output [(1<<8)-1:0];
always begin
#1 clk = !clk;
end
reg signed [23:0] output_sample;
reg signed [23:0] mixer_buffer;
always begin
#2
pipeline_state = 4'd0;
#2
pipeline_state = 4'd1;
#2
pipeline_state = 4'd2;
mem_phase[voice_index]=phase;
mem_input[voice_index]=wavetable_output;
mem_output[voice_index]=voice_chain_output;
if (voice_index == 8'hff) begin
output_sample <= mixer_buffer + voice_chain_output;
mixer_buffer <= 24'sd0;
end
else begin
mixer_buffer <= mixer_buffer + voice_chain_output;
end
end
reg send_SPI;
always @(posedge clk) begin
if (pipeline_state == 4'd0)
voice_index = voice_index + 1;
end
integer lp;
initial
begin
clk = 1;
reset = 1;
send_SPI = 0;
#10 reset = 0;
#4
SPI_flag = 1;
SPI_tuning_code = 20*1000000;
SPI_voice_index = 5;
SPI_note_status = 1'b1;
#2
SPI_flag = 0;
#10000000
SPI_flag = 1;
SPI_voice_index = 5;
SPI_note_status = 1'b0;
#2
SPI_flag = 0;
end
endmodule | 3 |
140,491 | data/full_repos/permissive/90331782/adders/full-adder/Fulladder.v | 90,331,782 | Fulladder.v | v | 17 | 44 | [] | [] | [] | [(7, 16)] | null | data/verilator_xmls/42ac77f3-0138-49b1-ba8f-c3f06839662f.xml | null | 308,581 | module | module Fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire c1,c2,c3;
xor x1(sum,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,a,cin);
or o1(cout,c1,c2,c3);
endmodule | module Fulladder(a,b,cin,sum,cout); |
input a,b,cin;
output sum,cout;
wire c1,c2,c3;
xor x1(sum,a,b,cin);
and a1(c1,a,b);
and a2(c2,b,cin);
and a3(c3,a,cin);
or o1(cout,c1,c2,c3);
endmodule | 1 |
140,492 | data/full_repos/permissive/90331782/adders/full-adder-using-half-adder/Fulladder.v | 90,331,782 | Fulladder.v | v | 15 | 44 | [] | [] | [] | [(7, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/90331782/adders/full-adder-using-half-adder/Fulladder.v:11: Cannot find file containing module: 'Halfadder'\nHalfadder h1(a,b,s1,c1);\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90331782/adders/full-adder-using-half-adder,data/full_repos/permissive/90331782/Halfadder\n data/full_repos/permissive/90331782/adders/full-adder-using-half-adder,data/full_repos/permissive/90331782/Halfadder.v\n data/full_repos/permissive/90331782/adders/full-adder-using-half-adder,data/full_repos/permissive/90331782/Halfadder.sv\n Halfadder\n Halfadder.v\n Halfadder.sv\n obj_dir/Halfadder\n obj_dir/Halfadder.v\n obj_dir/Halfadder.sv\n%Error: data/full_repos/permissive/90331782/adders/full-adder-using-half-adder/Fulladder.v:12: Cannot find file containing module: 'Halfadder'\nHalfadder h2(s1,cin,sum,c2);\n^~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 308,582 | module | module Fulladder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,c1,c2;
Halfadder h1(a,b,s1,c1);
Halfadder h2(s1,cin,sum,c2);
or o1(cout,c1,c2);
endmodule | module Fulladder(a,b,cin,sum,cout); |
input a,b,cin;
output sum,cout;
wire s1,c1,c2;
Halfadder h1(a,b,s1,c1);
Halfadder h2(s1,cin,sum,c2);
or o1(cout,c1,c2);
endmodule | 1 |
Subsets and Splits