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140,493 | data/full_repos/permissive/90331782/adders/full-adder-using-half-adder/Halfadder.v | 90,331,782 | Halfadder.v | v | 13 | 44 | [] | [] | [] | [(7, 12)] | null | data/verilator_xmls/5948d992-7635-4e17-9b39-39d6e59e95a1.xml | null | 308,583 | module | module Halfadder(a,b,sum,cout);
input a,b;
output sum,cout;
xor x1(sum,a,b);
and a1(cout,a,b);
endmodule | module Halfadder(a,b,sum,cout); |
input a,b;
output sum,cout;
xor x1(sum,a,b);
and a1(cout,a,b);
endmodule | 1 |
140,496 | data/full_repos/permissive/90331782/counters/mod-10/dff.v | 90,331,782 | dff.v | v | 10 | 28 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/6df187c7-ea2c-481f-a22d-8014a7ea1f0c.xml | null | 308,589 | module | module dff(clock,d,q,qbar);
input clock,d;
output wire q,qbar;
wire d1,d2;
nand n1 (d1,clock,d);
nand n2 (d2,clock,(~d));
nand n3 (q,qbar,d1);
nand n4 (qbar,q,d2);
endmodule | module dff(clock,d,q,qbar); |
input clock,d;
output wire q,qbar;
wire d1,d2;
nand n1 (d1,clock,d);
nand n2 (d2,clock,(~d));
nand n3 (q,qbar,d1);
nand n4 (qbar,q,d2);
endmodule | 1 |
140,498 | data/full_repos/permissive/90331782/dividers/Division.v | 90,331,782 | Division.v | v | 58 | 30 | [] | [] | [] | [(1, 57)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90331782/dividers/Division.v:46: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance Division\n if((a==3\'b000)|(b==3\'b000))\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90331782/dividers/Division.v:46: Operator EQ expects 4 bits on the RHS, but RHS\'s CONST \'3\'h0\' generates 3 bits.\n : ... In instance Division\n if((a==3\'b000)|(b==3\'b000))\n ^~\n%Error: Exiting due to 2 warning(s)\n' | 308,591 | module | module Division(q,r,a,b);
output reg[3:0]q,r;
input [3:0]a,b;
reg[3:0] A;
reg[3:0] Q;
reg[3:0] M;
reg[7:0] K;
integer i;
integer count;
always @ (a or b)
begin
A = 4'b0000;
count = 0;
Q = a;
M = b;
K = {A,Q};
for(i=0;i<4;i=i+1)
begin
if(A[3] == 1)
begin
K = K<<1;
A = K[7:4] + M;
Q = K[3:0];
if(A[3] == 1) Q[0] = 0;
else Q[0] = 1;
end
else
begin
K = K<<1;
A = K[7:4] - M;
Q = K[3:0];
if(A[3] == 1) Q[0] = 0;
else Q[0] = 1;
end
count = count + 1;
K = {A,Q};
end
if(count == 4)
begin
if(A[3] == 1)
A = K[7:4] + M;
end
if((a==3'b000)|(b==3'b000))
begin
q = 0;
r = 0;
end
else
begin
q = Q;
r = A;
end
end
endmodule | module Division(q,r,a,b); |
output reg[3:0]q,r;
input [3:0]a,b;
reg[3:0] A;
reg[3:0] Q;
reg[3:0] M;
reg[7:0] K;
integer i;
integer count;
always @ (a or b)
begin
A = 4'b0000;
count = 0;
Q = a;
M = b;
K = {A,Q};
for(i=0;i<4;i=i+1)
begin
if(A[3] == 1)
begin
K = K<<1;
A = K[7:4] + M;
Q = K[3:0];
if(A[3] == 1) Q[0] = 0;
else Q[0] = 1;
end
else
begin
K = K<<1;
A = K[7:4] - M;
Q = K[3:0];
if(A[3] == 1) Q[0] = 0;
else Q[0] = 1;
end
count = count + 1;
K = {A,Q};
end
if(count == 4)
begin
if(A[3] == 1)
A = K[7:4] + M;
end
if((a==3'b000)|(b==3'b000))
begin
q = 0;
r = 0;
end
else
begin
q = Q;
r = A;
end
end
endmodule | 1 |
140,499 | data/full_repos/permissive/90331782/finite-state-machine/moore-machine/Moore_Machine.v | 90,331,782 | Moore_Machine.v | v | 56 | 44 | [] | [] | [] | [(7, 55)] | null | data/verilator_xmls/cbfc6dc6-8e77-4393-9f88-24293ddfffa7.xml | null | 308,593 | module | module Moore_Machine(clock,reset,x,y);
input clock,reset,x;
output reg y;
reg [1:0]state;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @ (posedge clock)
begin
if(reset)
state = S0;
else
case (state)
S0:
if(x)
state = S0;
else
state = S1;
S1:
if(x)
state = S2;
else
state = S1;
S2:
if(x)
state = S0;
else
state = S3;
S3:
if(x)
state = S2;
else
state = S1;
endcase
end
always @ (*)
begin
if(reset)
y = 0;
else if (state == S3)
y = 1;
else
y = 0;
end
endmodule | module Moore_Machine(clock,reset,x,y); |
input clock,reset,x;
output reg y;
reg [1:0]state;
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
always @ (posedge clock)
begin
if(reset)
state = S0;
else
case (state)
S0:
if(x)
state = S0;
else
state = S1;
S1:
if(x)
state = S2;
else
state = S1;
S2:
if(x)
state = S0;
else
state = S3;
S3:
if(x)
state = S2;
else
state = S1;
endcase
end
always @ (*)
begin
if(reset)
y = 0;
else if (state == S3)
y = 1;
else
y = 0;
end
endmodule | 1 |
140,500 | data/full_repos/permissive/90331782/finite-state-machine/sequence-detector/Sequence_Detector.v | 90,331,782 | Sequence_Detector.v | v | 93 | 49 | [] | [] | [] | [(7, 92)] | null | data/verilator_xmls/5acb4207-6ba0-4913-90fa-fef085914f89.xml | null | 308,594 | module | module Sequence_Detector(clock,reset,x,y);
input clock,reset,x;
output reg y;
reg [2:0]state;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
always @ (posedge clock)
begin
if(reset)
state = S0;
else
case (state)
S0:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S0;
y = 0;
end
end
S1:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S2;
y = 0;
end
end
S2:
begin
if(x)
begin
state = S3;
y = 0;
end
else
begin
state = S0;
y = 0;
end
end
S3:
begin
if(x)
begin
state = S4;
y = 1;
end
else
begin
state = S2;
y = 0;
end
end
S4:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S2;
y = 0;
end
end
endcase
end
endmodule | module Sequence_Detector(clock,reset,x,y); |
input clock,reset,x;
output reg y;
reg [2:0]state;
parameter S0 = 3'b000;
parameter S1 = 3'b001;
parameter S2 = 3'b010;
parameter S3 = 3'b011;
parameter S4 = 3'b100;
always @ (posedge clock)
begin
if(reset)
state = S0;
else
case (state)
S0:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S0;
y = 0;
end
end
S1:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S2;
y = 0;
end
end
S2:
begin
if(x)
begin
state = S3;
y = 0;
end
else
begin
state = S0;
y = 0;
end
end
S3:
begin
if(x)
begin
state = S4;
y = 1;
end
else
begin
state = S2;
y = 0;
end
end
S4:
begin
if(x)
begin
state = S1;
y = 0;
end
else
begin
state = S2;
y = 0;
end
end
endcase
end
endmodule | 1 |
140,501 | data/full_repos/permissive/90331782/flipflops/d-ff/behavioral/dflipflop.v | 90,331,782 | dflipflop.v | v | 18 | 44 | [] | [] | [] | [(7, 17)] | null | data/verilator_xmls/aba1bca1-e22f-4346-bab3-bafa86130a2e.xml | null | 308,595 | module | module dflipflop(clock,reset,d,q);
input clock, reset, d;
output reg q;
always @ (posedge clock)
begin
if(reset)
q = 0;
else
q = d;
end
endmodule | module dflipflop(clock,reset,d,q); |
input clock, reset, d;
output reg q;
always @ (posedge clock)
begin
if(reset)
q = 0;
else
q = d;
end
endmodule | 1 |
140,503 | data/full_repos/permissive/90331782/flipflops/jk-ff/behavioral/JKflipflop.v | 90,331,782 | JKflipflop.v | v | 49 | 44 | [] | [] | [] | [(7, 48)] | null | data/verilator_xmls/c60d1a54-fa45-44f5-8dcb-b6fb0448786e.xml | null | 308,597 | module | module JKflipflop(clock,reset,j,k,q,qbar);
input clock,reset,j,k;
output reg q,qbar;
initial
begin
q = 1'b0;
qbar = 1'b1;
end
always @ (posedge clock)
begin
if (reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
case({j,k})
2'b00:
begin
q = q;
qbar = qbar;
end
2'b01:
begin
q = 1'b0;
qbar = 1'b1;
end
2'b10:
begin
q = 1'b1;
qbar = 1'b0;
end
2'b11:
begin
q = qbar;
qbar = q;
end
endcase
end
end
endmodule | module JKflipflop(clock,reset,j,k,q,qbar); |
input clock,reset,j,k;
output reg q,qbar;
initial
begin
q = 1'b0;
qbar = 1'b1;
end
always @ (posedge clock)
begin
if (reset)
begin
q = 1'b0;
qbar = 1'b1;
end
else
begin
case({j,k})
2'b00:
begin
q = q;
qbar = qbar;
end
2'b01:
begin
q = 1'b0;
qbar = 1'b1;
end
2'b10:
begin
q = 1'b1;
qbar = 1'b0;
end
2'b11:
begin
q = qbar;
qbar = q;
end
endcase
end
end
endmodule | 1 |
140,504 | data/full_repos/permissive/90331782/flipflops/sr-ff/behavioral/SRflipflop.v | 90,331,782 | SRflipflop.v | v | 49 | 44 | [] | [] | [] | [(7, 48)] | null | data/verilator_xmls/17f025bc-f2e1-4aa4-a600-ef4674ef126b.xml | null | 308,598 | module | module SRflipflop(clock,reset,s,r,q,qbar);
input clock,reset,s,r;
output reg q,qbar;
initial
begin
q = 1'b1;
qbar = 1'b0;
end
always @ (posedge clock)
begin
if(reset)
begin
q = 0;
qbar = 1'b1;
end
else
begin
case({s,r})
2'b00:
begin
q = q;
qbar = qbar;
end
2'b01:
begin
q = 1'b0;
qbar = 1'b1;
end
2'b10:
begin
q = 1'b1;
qbar = 1'b0;
end
2'b11:
begin
q = 1'bx;
qbar = 1'bx;
end
endcase
end
end
endmodule | module SRflipflop(clock,reset,s,r,q,qbar); |
input clock,reset,s,r;
output reg q,qbar;
initial
begin
q = 1'b1;
qbar = 1'b0;
end
always @ (posedge clock)
begin
if(reset)
begin
q = 0;
qbar = 1'b1;
end
else
begin
case({s,r})
2'b00:
begin
q = q;
qbar = qbar;
end
2'b01:
begin
q = 1'b0;
qbar = 1'b1;
end
2'b10:
begin
q = 1'b1;
qbar = 1'b0;
end
2'b11:
begin
q = 1'bx;
qbar = 1'bx;
end
endcase
end
end
endmodule | 1 |
140,505 | data/full_repos/permissive/90331782/flipflops/sr-ff/structural/SRflipflop.v | 90,331,782 | SRflipflop.v | v | 16 | 44 | [] | [] | [] | [(7, 15)] | null | data/verilator_xmls/0846b23f-550e-4caa-ae15-31e6db85cd72.xml | null | 308,599 | module | module SRflipflop(clock,reset,s,r,q,qbar);
input clock,reset,s,r;
output q,qbar;
wire d1,d2;
nand n1(d1,clock,s,reset);
nand n2(d2,clock,r,reset);
nand n3(q,qbar,d1);
nand n4(qbar,q,d2);
endmodule | module SRflipflop(clock,reset,s,r,q,qbar); |
input clock,reset,s,r;
output q,qbar;
wire d1,d2;
nand n1(d1,clock,s,reset);
nand n2(d2,clock,r,reset);
nand n3(q,qbar,d1);
nand n4(qbar,q,d2);
endmodule | 1 |
140,506 | data/full_repos/permissive/90331782/flipflops/sr-latch/NandLatch.v | 90,331,782 | NandLatch.v | v | 13 | 44 | [] | [] | [] | [(7, 12)] | null | data/verilator_xmls/ae612b04-e686-494c-8180-0cd05462829b.xml | null | 308,600 | module | module NandLatch(s,r,q,qbar);
input s,r;
output q,qbar;
nand n1 (q,qbar,s);
nand n2 (qbar,q,r);
endmodule | module NandLatch(s,r,q,qbar); |
input s,r;
output q,qbar;
nand n1 (q,qbar,s);
nand n2 (qbar,q,r);
endmodule | 1 |
140,507 | data/full_repos/permissive/90331782/flipflops/sr-latch/NorLatch.v | 90,331,782 | NorLatch.v | v | 13 | 44 | [] | [] | [] | [(7, 12)] | null | data/verilator_xmls/b77e5c28-67d8-4e9a-addd-f1d2b6a97f1e.xml | null | 308,601 | module | module NorLatch(s,r,q,qbar);
input s,r;
output q,qbar;
nor n1 (q,qbar,r);
nor n2 (qbar,q,s);
endmodule | module NorLatch(s,r,q,qbar); |
input s,r;
output q,qbar;
nor n1 (q,qbar,r);
nor n2 (qbar,q,s);
endmodule | 1 |
140,508 | data/full_repos/permissive/90331782/flipflops/t-ff/behavioral/Tflipflop.v | 90,331,782 | Tflipflop.v | v | 18 | 44 | [] | [] | [] | [(7, 17)] | null | data/verilator_xmls/ea261207-4364-4d6d-8cfb-55c320f9e814.xml | null | 308,602 | module | module Tflipflop(clock,reset,t,q);
input clock,reset,t;
output reg q;
always @ (posedge clock)
begin
if(reset)
q = 0;
else
q = ~t;
end
endmodule | module Tflipflop(clock,reset,t,q); |
input clock,reset,t;
output reg q;
always @ (posedge clock)
begin
if(reset)
q = 0;
else
q = ~t;
end
endmodule | 1 |
140,509 | data/full_repos/permissive/90331782/flipflops/t-ff/structural/Tflipflop.v | 90,331,782 | Tflipflop.v | v | 15 | 44 | [] | [] | [] | [(7, 15)] | null | data/verilator_xmls/f9c3967d-ccfe-46bb-98f8-b200889ce2ee.xml | null | 308,603 | module | module Tflipflop(clock,t,q,qbar);
input clock,t;
output q,qbar;
wire t1,t2;
nand n1 (t1,clock,t,q);
nand n2 (t2,clock,t,qbar);
nand n3 (q,qbar,t1);
nand n4 (qbar,q,t2);
endmodule | module Tflipflop(clock,t,q,qbar); |
input clock,t;
output q,qbar;
wire t1,t2;
nand n1 (t1,clock,t,q);
nand n2 (t2,clock,t,qbar);
nand n3 (q,qbar,t1);
nand n4 (qbar,q,t2);
endmodule | 1 |
140,510 | data/full_repos/permissive/90331782/multiplexers/2x1/Mux.v | 90,331,782 | Mux.v | v | 16 | 44 | [] | [] | [] | [(7, 15)] | null | data/verilator_xmls/046ac7ba-6b4d-456c-841d-0a64c49fd286.xml | null | 308,604 | module | module Mux(out,in1,in2,select);
input in1,in2,select;
output out;
wire s1,s2,selectbar;
not(selectbar,select);
and(s1,selectbar,in1);
and(s2,select,in2);
or(out,s1,s2);
endmodule | module Mux(out,in1,in2,select); |
input in1,in2,select;
output out;
wire s1,s2,selectbar;
not(selectbar,select);
and(s1,selectbar,in1);
and(s2,select,in2);
or(out,s1,s2);
endmodule | 1 |
140,511 | data/full_repos/permissive/90331782/multiplexers/4x1/Mux.v | 90,331,782 | Mux.v | v | 12 | 90 | [] | [] | [] | null | line:12: before: "software" | data/verilator_xmls/ce65fbda-2219-4a46-ae9d-134c315e9248.xml | null | 308,605 | module | module Mux(y,s0,s1,in1,in2,in3,in4);
input in1,in2,in3,in4,s0,s1;
output y;
assign y = ((~s1)&(~s0)& in1) | ((~s1)&(s0)& in2) | ((s1)&(~s0)& in3) | ((s1)&(s0)& in4);
endmodule | module Mux(y,s0,s1,in1,in2,in3,in4); |
input in1,in2,in3,in4,s0,s1;
output y;
assign y = ((~s1)&(~s0)& in1) | ((~s1)&(s0)& in2) | ((s1)&(~s0)& in3) | ((s1)&(s0)& in4);
endmodule | 1 |
140,513 | data/full_repos/permissive/90331782/multiplexers/4x1-using-2x1/Mux1.v | 90,331,782 | Mux1.v | v | 12 | 44 | [] | [] | [] | [(7, 11)] | null | data/verilator_xmls/a852fdb0-1f64-4332-ad70-7c8b15c79535.xml | null | 308,607 | module | module Mux1(y,s,a,b);
input a,b,s;
output y;
assign y = ((~s)&a) | (s&b);
endmodule | module Mux1(y,s,a,b); |
input a,b,s;
output y;
assign y = ((~s)&a) | (s&b);
endmodule | 1 |
140,514 | data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux/Full_Adder.v | 90,331,782 | Full_Adder.v | v | 13 | 49 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux/Full_Adder.v:10: Cannot find file containing module: 'Mux'\nMux m1(sum,a,b,cin,~cin,~cin,cin);\n^~~\n ... Looked in:\n data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux,data/full_repos/permissive/90331782/Mux\n data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux,data/full_repos/permissive/90331782/Mux.v\n data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux,data/full_repos/permissive/90331782/Mux.sv\n Mux\n Mux.v\n Mux.sv\n obj_dir/Mux\n obj_dir/Mux.v\n obj_dir/Mux.sv\n%Error: data/full_repos/permissive/90331782/multiplexers/full-adder-using-mux/Full_Adder.v:11: Cannot find file containing module: 'Mux'\nMux m2(cout,a,b,0,cin,cin,1);\n^~~\n%Error: Exiting due to 2 error(s)\n" | 308,608 | module | module Full_Adder(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
Mux m1(sum,a,b,cin,~cin,~cin,cin);
Mux m2(cout,a,b,0,cin,cin,1);
endmodule | module Full_Adder(sum,cout,a,b,cin); |
input a,b,cin;
output sum,cout;
Mux m1(sum,a,b,cin,~cin,~cin,cin);
Mux m2(cout,a,b,0,cin,cin,1);
endmodule | 1 |
140,515 | data/full_repos/permissive/90331782/multipliers/shift-and-add/Multiply.v | 90,331,782 | Multiply.v | v | 48 | 79 | [] | [] | [] | [(18, 47)] | null | data/verilator_xmls/b91938a3-5178-4137-9b69-c8e0fa95b988.xml | null | 308,611 | module | module Multiply(y,a,b);
input [7:0]a,b;
output reg [15:0]y;
reg [7:0]A, M, Q;
reg [15:0]K;
integer i;
integer count;
always @(*)
begin
M = a;
Q = b;
A = 0;
K = {A,Q};
count = 1;
for (i=1;i<=8;i=i+1)
begin
if(Q[0]==1'b1)
A = A + M;
K = {A,Q} >> 1;
A = K[15:8];
Q = K[7:0];
K = {A,Q};
count = count + 1;
end
y = K;
end
endmodule | module Multiply(y,a,b); |
input [7:0]a,b;
output reg [15:0]y;
reg [7:0]A, M, Q;
reg [15:0]K;
integer i;
integer count;
always @(*)
begin
M = a;
Q = b;
A = 0;
K = {A,Q};
count = 1;
for (i=1;i<=8;i=i+1)
begin
if(Q[0]==1'b1)
A = A + M;
K = {A,Q} >> 1;
A = K[15:8];
Q = K[7:0];
K = {A,Q};
count = count + 1;
end
y = K;
end
endmodule | 1 |
140,517 | data/full_repos/permissive/90331782/shift-registers/pipo/Usr.v | 90,331,782 | Usr.v | v | 31 | 68 | [] | [] | [] | [(7, 30)] | null | data/verilator_xmls/af62044c-fb58-439d-b2bb-35a81b8395c3.xml | null | 308,614 | module | module Usr(in,out,msb_in,lsb_in,msb_out,lsb_out,s1,s0,clock,reset);
input s1,s0,clock,reset,msb_in,lsb_in;
output msb_out,lsb_out;
input [3:0]in;
output reg [3:0]out;
assign msb_out = out[3];
assign lsb_out = out[0];
always @ (posedge clock)
begin
if(reset)
out = 0;
else
begin
case ({s1,s0})
2'b00: out = out;
2'b01: out = {msb_in,out[3:1]};
2'b10: out = {out[2:0],lsb_in};
2'b11: out = in;
endcase
end
end
endmodule | module Usr(in,out,msb_in,lsb_in,msb_out,lsb_out,s1,s0,clock,reset); |
input s1,s0,clock,reset,msb_in,lsb_in;
output msb_out,lsb_out;
input [3:0]in;
output reg [3:0]out;
assign msb_out = out[3];
assign lsb_out = out[0];
always @ (posedge clock)
begin
if(reset)
out = 0;
else
begin
case ({s1,s0})
2'b00: out = out;
2'b01: out = {msb_in,out[3:1]};
2'b10: out = {out[2:0],lsb_in};
2'b11: out = in;
endcase
end
end
endmodule | 1 |
140,520 | data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v | 90,331,782 | Rbs.v | v | 22 | 56 | [] | [] | [] | [(7, 21)] | null | null | 1: b"%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:13: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs1(a[0],b[0],c,difference[0],b1);\n^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor,data/full_repos/permissive/90331782/Full_Subtractor\n data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor,data/full_repos/permissive/90331782/Full_Subtractor.v\n data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor,data/full_repos/permissive/90331782/Full_Subtractor.sv\n Full_Subtractor\n Full_Subtractor.v\n Full_Subtractor.sv\n obj_dir/Full_Subtractor\n obj_dir/Full_Subtractor.v\n obj_dir/Full_Subtractor.sv\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:14: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs2(a[1],b[1],b1,difference[1],b2);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:15: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs3(a[2],b[2],b2,difference[2],b3);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:16: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs4(a[3],b[3],b3,difference[3],b4);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:17: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs5(a[4],b[4],b4,difference[4],b5);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:18: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs6(a[5],b[5],b5,difference[5],b6);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:19: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs7(a[6],b[6],b6,difference[6],b7);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90331782/subtractors/ripple-borrow-subtractor/Rbs.v:20: Cannot find file containing module: 'Full_Subtractor'\nFull_Subtractor fs8(a[7],b[7],b7,difference[7],borrow);\n^~~~~~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 308,619 | module | module Rbs(a,b,c,difference,borrow);
input [7:0]a,b;
input c;
output [7:0]difference;
output borrow;
wire b1,b2,b3,b4,b5,b6,b7;
Full_Subtractor fs1(a[0],b[0],c,difference[0],b1);
Full_Subtractor fs2(a[1],b[1],b1,difference[1],b2);
Full_Subtractor fs3(a[2],b[2],b2,difference[2],b3);
Full_Subtractor fs4(a[3],b[3],b3,difference[3],b4);
Full_Subtractor fs5(a[4],b[4],b4,difference[4],b5);
Full_Subtractor fs6(a[5],b[5],b5,difference[5],b6);
Full_Subtractor fs7(a[6],b[6],b6,difference[6],b7);
Full_Subtractor fs8(a[7],b[7],b7,difference[7],borrow);
endmodule | module Rbs(a,b,c,difference,borrow); |
input [7:0]a,b;
input c;
output [7:0]difference;
output borrow;
wire b1,b2,b3,b4,b5,b6,b7;
Full_Subtractor fs1(a[0],b[0],c,difference[0],b1);
Full_Subtractor fs2(a[1],b[1],b1,difference[1],b2);
Full_Subtractor fs3(a[2],b[2],b2,difference[2],b3);
Full_Subtractor fs4(a[3],b[3],b3,difference[3],b4);
Full_Subtractor fs5(a[4],b[4],b4,difference[4],b5);
Full_Subtractor fs6(a[5],b[5],b5,difference[5],b6);
Full_Subtractor fs7(a[6],b[6],b6,difference[6],b7);
Full_Subtractor fs8(a[7],b[7],b7,difference[7],borrow);
endmodule | 1 |
140,527 | data/full_repos/permissive/90403445/src/axi4_read_write_merge.v | 90,403,445 | axi4_read_write_merge.v | v | 244 | 72 | [] | [] | [] | [(18, 243)] | null | data/verilator_xmls/960d4542-16c5-4994-970c-13b948f0b576.xml | null | 308,623 | module | module axi4_read_write_merge #
(
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_BURST_LEN = 4,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 1,
parameter integer C_M_AXI_ARUSER_WIDTH = 1,
parameter integer C_M_AXI_WUSER_WIDTH = 1,
parameter integer C_M_AXI_RUSER_WIDTH = 1,
parameter integer C_M_AXI_BUSER_WIDTH = 1
)
(
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_AWID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_READ_AWADDR,
input wire [7 : 0] S_AXI_READ_AWLEN,
input wire [2 : 0] S_AXI_READ_AWSIZE,
input wire [1 : 0] S_AXI_READ_AWBURST,
input wire S_AXI_READ_AWLOCK,
input wire [3 : 0] S_AXI_READ_AWCACHE,
input wire [2 : 0] S_AXI_READ_AWPROT,
input wire [3 : 0] S_AXI_READ_AWQOS,
input wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S_AXI_READ_AWUSER,
input wire S_AXI_READ_AWVALID,
output wire S_AXI_READ_AWREADY,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_READ_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1 : 0] S_AXI_READ_WSTRB,
input wire S_AXI_READ_WLAST,
input wire [C_M_AXI_WUSER_WIDTH-1 : 0] S_AXI_READ_WUSER,
input wire S_AXI_READ_WVALID,
output wire S_AXI_READ_WREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_BID,
output wire [1 : 0] S_AXI_READ_BRESP,
output wire [C_M_AXI_BUSER_WIDTH-1 : 0] S_AXI_READ_BUSER,
output wire S_AXI_READ_BVALID,
input wire S_AXI_READ_BREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_ARID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_READ_ARADDR,
input wire [7 : 0] S_AXI_READ_ARLEN,
input wire [2 : 0] S_AXI_READ_ARSIZE,
input wire [1 : 0] S_AXI_READ_ARBURST,
input wire S_AXI_READ_ARLOCK,
input wire [3 : 0] S_AXI_READ_ARCACHE,
input wire [2 : 0] S_AXI_READ_ARPROT,
input wire [3 : 0] S_AXI_READ_ARQOS,
input wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S_AXI_READ_ARUSER,
input wire S_AXI_READ_ARVALID,
output wire S_AXI_READ_ARREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_RID,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_READ_RDATA,
output wire [1 : 0] S_AXI_READ_RRESP,
output wire S_AXI_READ_RLAST,
output wire [C_M_AXI_RUSER_WIDTH-1 : 0] S_AXI_READ_RUSER,
output wire S_AXI_READ_RVALID,
input wire S_AXI_READ_RREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_AWID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_WRITE_AWADDR,
input wire [7 : 0] S_AXI_WRITE_AWLEN,
input wire [2 : 0] S_AXI_WRITE_AWSIZE,
input wire [1 : 0] S_AXI_WRITE_AWBURST,
input wire S_AXI_WRITE_AWLOCK,
input wire [3 : 0] S_AXI_WRITE_AWCACHE,
input wire [2 : 0] S_AXI_WRITE_AWPROT,
input wire [3 : 0] S_AXI_WRITE_AWQOS,
input wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S_AXI_WRITE_AWUSER,
input wire S_AXI_WRITE_AWVALID,
output wire S_AXI_WRITE_AWREADY,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_WRITE_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WRITE_WSTRB,
input wire S_AXI_WRITE_WLAST,
input wire [C_M_AXI_WUSER_WIDTH-1 : 0] S_AXI_WRITE_WUSER,
input wire S_AXI_WRITE_WVALID,
output wire S_AXI_WRITE_WREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_BID,
output wire [1 : 0] S_AXI_WRITE_BRESP,
output wire [C_M_AXI_BUSER_WIDTH-1 : 0] S_AXI_WRITE_BUSER,
output wire S_AXI_WRITE_BVALID,
input wire S_AXI_WRITE_BREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_ARID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_WRITE_ARADDR,
input wire [7 : 0] S_AXI_WRITE_ARLEN,
input wire [2 : 0] S_AXI_WRITE_ARSIZE,
input wire [1 : 0] S_AXI_WRITE_ARBURST,
input wire S_AXI_WRITE_ARLOCK,
input wire [3 : 0] S_AXI_WRITE_ARCACHE,
input wire [2 : 0] S_AXI_WRITE_ARPROT,
input wire [3 : 0] S_AXI_WRITE_ARQOS,
input wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S_AXI_WRITE_ARUSER,
input wire S_AXI_WRITE_ARVALID,
output wire S_AXI_WRITE_ARREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_RID,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_WRITE_RDATA,
output wire [1 : 0] S_AXI_WRITE_RRESP,
output wire S_AXI_WRITE_RLAST,
output wire [C_M_AXI_RUSER_WIDTH-1 : 0] S_AXI_WRITE_RUSER,
output wire S_AXI_WRITE_RVALID,
input wire S_AXI_WRITE_RREADY,
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
assign M_AXI_AWID = S_AXI_WRITE_AWID;
assign M_AXI_AWADDR = S_AXI_WRITE_AWADDR;
assign M_AXI_AWLEN = S_AXI_WRITE_AWLEN;
assign M_AXI_AWSIZE = S_AXI_WRITE_AWSIZE;
assign M_AXI_AWBURST = S_AXI_WRITE_AWBURST;
assign M_AXI_AWLOCK = S_AXI_WRITE_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_WRITE_AWCACHE;
assign M_AXI_AWPROT = S_AXI_WRITE_AWPROT;
assign M_AXI_AWQOS = S_AXI_WRITE_AWQOS;
assign M_AXI_AWUSER = S_AXI_WRITE_AWUSER;
assign M_AXI_AWVALID = S_AXI_WRITE_AWVALID;
assign S_AXI_WRITE_AWREADY = M_AXI_AWREADY;
assign M_AXI_WDATA = S_AXI_WRITE_WDATA;
assign M_AXI_WSTRB = S_AXI_WRITE_WSTRB;
assign M_AXI_WLAST = S_AXI_WRITE_WLAST;
assign M_AXI_WUSER = S_AXI_WRITE_WUSER;
assign M_AXI_WVALID = S_AXI_WRITE_WVALID;
assign S_AXI_WRITE_WREADY = M_AXI_WREADY;
assign S_AXI_WRITE_BID = M_AXI_BID;
assign S_AXI_WRITE_BRESP = M_AXI_BRESP;
assign S_AXI_WRITE_BUSER = M_AXI_BUSER;
assign S_AXI_WRITE_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = S_AXI_WRITE_BREADY;
assign S_AXI_WRITE_ARREADY = 0;
assign S_AXI_WRITE_RID = 0;
assign S_AXI_WRITE_RDATA = 0;
assign S_AXI_WRITE_RRESP = 0;
assign S_AXI_WRITE_RLAST = 0;
assign S_AXI_WRITE_RUSER = 0;
assign S_AXI_WRITE_RVALID = 0;
assign S_AXI_READ_AWREADY = 0;
assign S_AXI_READ_WREADY = 0;
assign S_AXI_READ_BID = 0;
assign S_AXI_READ_BRESP = 0;
assign S_AXI_READ_BUSER = 0;
assign S_AXI_READ_BVALID = 0;
assign M_AXI_ARID = S_AXI_READ_ARID;
assign M_AXI_ARADDR = S_AXI_READ_ARADDR;
assign M_AXI_ARLEN = S_AXI_READ_ARLEN;
assign M_AXI_ARSIZE = S_AXI_READ_ARSIZE;
assign M_AXI_ARBURST = S_AXI_READ_ARBURST;
assign M_AXI_ARLOCK = S_AXI_READ_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_READ_ARCACHE;
assign M_AXI_ARPROT = S_AXI_READ_ARPROT;
assign M_AXI_ARQOS = S_AXI_READ_ARQOS;
assign M_AXI_ARUSER = S_AXI_READ_ARUSER;
assign M_AXI_ARVALID = S_AXI_READ_ARVALID;
assign S_AXI_READ_ARREADY = M_AXI_ARREADY;
assign S_AXI_READ_RID = M_AXI_RID;
assign S_AXI_READ_RDATA = M_AXI_RDATA;
assign S_AXI_READ_RRESP = M_AXI_RRESP;
assign S_AXI_READ_RLAST = M_AXI_RLAST;
assign S_AXI_READ_RUSER = M_AXI_RUSER;
assign S_AXI_READ_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_READ_RREADY;
endmodule | module axi4_read_write_merge #
(
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_BURST_LEN = 4,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 1,
parameter integer C_M_AXI_ARUSER_WIDTH = 1,
parameter integer C_M_AXI_WUSER_WIDTH = 1,
parameter integer C_M_AXI_RUSER_WIDTH = 1,
parameter integer C_M_AXI_BUSER_WIDTH = 1
)
(
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_AWID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_READ_AWADDR,
input wire [7 : 0] S_AXI_READ_AWLEN,
input wire [2 : 0] S_AXI_READ_AWSIZE,
input wire [1 : 0] S_AXI_READ_AWBURST,
input wire S_AXI_READ_AWLOCK,
input wire [3 : 0] S_AXI_READ_AWCACHE,
input wire [2 : 0] S_AXI_READ_AWPROT,
input wire [3 : 0] S_AXI_READ_AWQOS,
input wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S_AXI_READ_AWUSER,
input wire S_AXI_READ_AWVALID,
output wire S_AXI_READ_AWREADY,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_READ_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1 : 0] S_AXI_READ_WSTRB,
input wire S_AXI_READ_WLAST,
input wire [C_M_AXI_WUSER_WIDTH-1 : 0] S_AXI_READ_WUSER,
input wire S_AXI_READ_WVALID,
output wire S_AXI_READ_WREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_BID,
output wire [1 : 0] S_AXI_READ_BRESP,
output wire [C_M_AXI_BUSER_WIDTH-1 : 0] S_AXI_READ_BUSER,
output wire S_AXI_READ_BVALID,
input wire S_AXI_READ_BREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_ARID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_READ_ARADDR,
input wire [7 : 0] S_AXI_READ_ARLEN,
input wire [2 : 0] S_AXI_READ_ARSIZE,
input wire [1 : 0] S_AXI_READ_ARBURST,
input wire S_AXI_READ_ARLOCK,
input wire [3 : 0] S_AXI_READ_ARCACHE,
input wire [2 : 0] S_AXI_READ_ARPROT,
input wire [3 : 0] S_AXI_READ_ARQOS,
input wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S_AXI_READ_ARUSER,
input wire S_AXI_READ_ARVALID,
output wire S_AXI_READ_ARREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_READ_RID,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_READ_RDATA,
output wire [1 : 0] S_AXI_READ_RRESP,
output wire S_AXI_READ_RLAST,
output wire [C_M_AXI_RUSER_WIDTH-1 : 0] S_AXI_READ_RUSER,
output wire S_AXI_READ_RVALID,
input wire S_AXI_READ_RREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_AWID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_WRITE_AWADDR,
input wire [7 : 0] S_AXI_WRITE_AWLEN,
input wire [2 : 0] S_AXI_WRITE_AWSIZE,
input wire [1 : 0] S_AXI_WRITE_AWBURST,
input wire S_AXI_WRITE_AWLOCK,
input wire [3 : 0] S_AXI_WRITE_AWCACHE,
input wire [2 : 0] S_AXI_WRITE_AWPROT,
input wire [3 : 0] S_AXI_WRITE_AWQOS,
input wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S_AXI_WRITE_AWUSER,
input wire S_AXI_WRITE_AWVALID,
output wire S_AXI_WRITE_AWREADY,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_WRITE_WDATA,
input wire [C_M_AXI_DATA_WIDTH/8-1 : 0] S_AXI_WRITE_WSTRB,
input wire S_AXI_WRITE_WLAST,
input wire [C_M_AXI_WUSER_WIDTH-1 : 0] S_AXI_WRITE_WUSER,
input wire S_AXI_WRITE_WVALID,
output wire S_AXI_WRITE_WREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_BID,
output wire [1 : 0] S_AXI_WRITE_BRESP,
output wire [C_M_AXI_BUSER_WIDTH-1 : 0] S_AXI_WRITE_BUSER,
output wire S_AXI_WRITE_BVALID,
input wire S_AXI_WRITE_BREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_ARID,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] S_AXI_WRITE_ARADDR,
input wire [7 : 0] S_AXI_WRITE_ARLEN,
input wire [2 : 0] S_AXI_WRITE_ARSIZE,
input wire [1 : 0] S_AXI_WRITE_ARBURST,
input wire S_AXI_WRITE_ARLOCK,
input wire [3 : 0] S_AXI_WRITE_ARCACHE,
input wire [2 : 0] S_AXI_WRITE_ARPROT,
input wire [3 : 0] S_AXI_WRITE_ARQOS,
input wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S_AXI_WRITE_ARUSER,
input wire S_AXI_WRITE_ARVALID,
output wire S_AXI_WRITE_ARREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] S_AXI_WRITE_RID,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] S_AXI_WRITE_RDATA,
output wire [1 : 0] S_AXI_WRITE_RRESP,
output wire S_AXI_WRITE_RLAST,
output wire [C_M_AXI_RUSER_WIDTH-1 : 0] S_AXI_WRITE_RUSER,
output wire S_AXI_WRITE_RVALID,
input wire S_AXI_WRITE_RREADY,
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
); |
assign M_AXI_AWID = S_AXI_WRITE_AWID;
assign M_AXI_AWADDR = S_AXI_WRITE_AWADDR;
assign M_AXI_AWLEN = S_AXI_WRITE_AWLEN;
assign M_AXI_AWSIZE = S_AXI_WRITE_AWSIZE;
assign M_AXI_AWBURST = S_AXI_WRITE_AWBURST;
assign M_AXI_AWLOCK = S_AXI_WRITE_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_WRITE_AWCACHE;
assign M_AXI_AWPROT = S_AXI_WRITE_AWPROT;
assign M_AXI_AWQOS = S_AXI_WRITE_AWQOS;
assign M_AXI_AWUSER = S_AXI_WRITE_AWUSER;
assign M_AXI_AWVALID = S_AXI_WRITE_AWVALID;
assign S_AXI_WRITE_AWREADY = M_AXI_AWREADY;
assign M_AXI_WDATA = S_AXI_WRITE_WDATA;
assign M_AXI_WSTRB = S_AXI_WRITE_WSTRB;
assign M_AXI_WLAST = S_AXI_WRITE_WLAST;
assign M_AXI_WUSER = S_AXI_WRITE_WUSER;
assign M_AXI_WVALID = S_AXI_WRITE_WVALID;
assign S_AXI_WRITE_WREADY = M_AXI_WREADY;
assign S_AXI_WRITE_BID = M_AXI_BID;
assign S_AXI_WRITE_BRESP = M_AXI_BRESP;
assign S_AXI_WRITE_BUSER = M_AXI_BUSER;
assign S_AXI_WRITE_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = S_AXI_WRITE_BREADY;
assign S_AXI_WRITE_ARREADY = 0;
assign S_AXI_WRITE_RID = 0;
assign S_AXI_WRITE_RDATA = 0;
assign S_AXI_WRITE_RRESP = 0;
assign S_AXI_WRITE_RLAST = 0;
assign S_AXI_WRITE_RUSER = 0;
assign S_AXI_WRITE_RVALID = 0;
assign S_AXI_READ_AWREADY = 0;
assign S_AXI_READ_WREADY = 0;
assign S_AXI_READ_BID = 0;
assign S_AXI_READ_BRESP = 0;
assign S_AXI_READ_BUSER = 0;
assign S_AXI_READ_BVALID = 0;
assign M_AXI_ARID = S_AXI_READ_ARID;
assign M_AXI_ARADDR = S_AXI_READ_ARADDR;
assign M_AXI_ARLEN = S_AXI_READ_ARLEN;
assign M_AXI_ARSIZE = S_AXI_READ_ARSIZE;
assign M_AXI_ARBURST = S_AXI_READ_ARBURST;
assign M_AXI_ARLOCK = S_AXI_READ_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_READ_ARCACHE;
assign M_AXI_ARPROT = S_AXI_READ_ARPROT;
assign M_AXI_ARQOS = S_AXI_READ_ARQOS;
assign M_AXI_ARUSER = S_AXI_READ_ARUSER;
assign M_AXI_ARVALID = S_AXI_READ_ARVALID;
assign S_AXI_READ_ARREADY = M_AXI_ARREADY;
assign S_AXI_READ_RID = M_AXI_RID;
assign S_AXI_READ_RDATA = M_AXI_RDATA;
assign S_AXI_READ_RRESP = M_AXI_RRESP;
assign S_AXI_READ_RLAST = M_AXI_RLAST;
assign S_AXI_READ_RUSER = M_AXI_RUSER;
assign S_AXI_READ_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_READ_RREADY;
endmodule | 5 |
140,529 | data/full_repos/permissive/90403445/src/axi4_stream_to_full.v | 90,403,445 | axi4_stream_to_full.v | v | 295 | 83 | [] | [] | [] | null | line:96: before: "(" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:142: Signal definition not found, creating implicitly: \'axi_mm_read_address\'\n : ... Suggested alternative: \'axi_mm_write_address\'\n assign axi_mm_read_address = 0;\n ^~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:143: Signal definition not found, creating implicitly: \'axi_mm_start_read\'\n : ... Suggested alternative: \'axi_mm_write_ready\'\n assign axi_mm_start_read = 0;\n ^~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:61: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:67: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:72: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:84: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:91: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,\n ^\n%Error: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:108: Cannot find file containing module: \'axi4_stream_reader\'\n axi4_stream_reader #\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader.v\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader.sv\n axi4_stream_reader\n axi4_stream_reader.v\n axi4_stream_reader.sv\n obj_dir/axi4_stream_reader\n obj_dir/axi4_stream_reader.v\n obj_dir/axi4_stream_reader.sv\n%Error: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:155: Cannot find file containing module: \'axi4_full_master_rw\'\n axi4_full_master_rw #\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n' | 308,625 | module | module axi4_stream_to_full #
(
parameter integer C_AXI_DATA_WIDTH = 32,
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 0,
parameter integer C_M_AXI_ARUSER_WIDTH = 0,
parameter integer C_M_AXI_WUSER_WIDTH = 0,
parameter integer C_M_AXI_RUSER_WIDTH = 0,
parameter integer C_M_AXI_BUSER_WIDTH = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire sw_reset,
output reg sw_reset_ok,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] write_address,
input wire write_start,
output wire output_idle,
output reg [C_AXI_DATA_WIDTH-1:0] debug_data_sum,
output wire S_AXIS_TREADY,
input wire [C_AXI_DATA_WIDTH-1 : 0] S_AXIS_TDATA,
input wire [(C_AXI_DATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
input wire S_AXIS_TLAST,
input wire S_AXIS_TVALID,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
wire axi_stream_enabled;
wire axi_stream_data_valid;
wire [C_AXI_DATA_WIDTH-1:0] axi_stream_data;
axi4_stream_reader #
(
.C_S_AXIS_TDATA_WIDTH(C_AXI_DATA_WIDTH)
)
axi_stream_i
(
.S_AXIS_ACLK(ACLK),
.S_AXIS_ARESETN(ARESETN),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TSTRB(S_AXIS_TSTRB),
.S_AXIS_TLAST(S_AXIS_TLAST),
.S_AXIS_TVALID(S_AXIS_TVALID),
.ready(axi_stream_enabled),
.data_valid(axi_stream_data_valid),
.data(axi_stream_data)
);
reg [C_M_AXI_ADDR_WIDTH-1:0] axi_mm_write_address;
wire [C_AXI_DATA_WIDTH-1:0] axi_mm_write_data;
wire axi_mm_write_data_valid;
reg axi_mm_write_enabled;
wire axi_mm_write_start;
wire axi_mm_write_end;
wire axi_mm_write_ready;
wire axi_mm_output_idle;
wire axi_mm_output_error;
assign axi_mm_read_address = 0;
assign axi_mm_start_read = 0;
reg axi_mm_write_enabled_prev;
always @(posedge ACLK) begin
axi_mm_write_enabled_prev <= axi_mm_write_enabled;
end
assign axi_mm_write_start = (~axi_mm_write_enabled_prev & axi_mm_write_enabled);
axi4_full_master_rw #
(
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
axi_mm_i
(
.write_address(axi_mm_write_address),
.write_data(axi_mm_write_data),
.write_data_valid(axi_mm_write_data_valid),
.write_start(axi_mm_write_start),
.write_ready(axi_mm_write_ready),
.write_end(axi_mm_write_end),
.write_data_last(),
.read_address(0),
.read_start(1'b0),
.read_data(),
.read_data_valid(),
.read_data_last(),
.read_ready(1'b0),
.read_end(),
.output_idle(axi_mm_output_idle),
.output_error(axi_mm_output_error),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_AWID),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.M_AXI_AWLOCK(M_AXI_AWLOCK),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(M_AXI_AWQOS),
.M_AXI_AWUSER(M_AXI_AWUSER),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WUSER(M_AXI_WUSER),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(M_AXI_BID),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(M_AXI_BUSER),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(M_AXI_ARID),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.M_AXI_ARLOCK(M_AXI_ARLOCK),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(M_AXI_ARQOS),
.M_AXI_ARUSER(M_AXI_ARUSER),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(M_AXI_RID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_RUSER(M_AXI_RUSER),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
assign axi_stream_enabled = axi_mm_write_ready && axi_mm_write_enabled;
assign axi_mm_write_data = axi_stream_data;
assign axi_mm_write_data_valid = axi_stream_data_valid || sw_reset;
reg [3:0] state;
assign output_idle = (state == 0);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
debug_data_sum <= 0;
state <= 0;
axi_mm_write_enabled <= 0;
axi_mm_write_address <= 0;
sw_reset_ok <= 0;
end else if (sw_reset) begin
if (axi_mm_output_idle) begin
sw_reset_ok <= 1;
end
end else begin
sw_reset_ok <= 0;
case (state)
0: begin
if (write_start) begin
$display("write start, write_address: %x", write_address);
axi_mm_write_address <= write_address;
axi_mm_write_enabled <= 1;
$display("axi4_s2mm state <= 1");
state <= 1;
end
end
1: begin
if (M_AXI_WVALID && M_AXI_WREADY) begin
debug_data_sum <= debug_data_sum + M_AXI_WDATA;
end
if (M_AXI_WLAST) begin
axi_mm_write_enabled <= 0;
state <= 2;
$display("axi4_s2mm state <= 2");
end
end
2: begin
if (axi_mm_write_end) begin
state <= 0;
$display("axi4_s2mm state <= 0");
end
end
endcase
end
end
endmodule | module axi4_stream_to_full #
(
parameter integer C_AXI_DATA_WIDTH = 32,
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 0,
parameter integer C_M_AXI_ARUSER_WIDTH = 0,
parameter integer C_M_AXI_WUSER_WIDTH = 0,
parameter integer C_M_AXI_RUSER_WIDTH = 0,
parameter integer C_M_AXI_BUSER_WIDTH = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire sw_reset,
output reg sw_reset_ok,
input wire [C_M_AXI_ADDR_WIDTH-1 : 0] write_address,
input wire write_start,
output wire output_idle,
output reg [C_AXI_DATA_WIDTH-1:0] debug_data_sum,
output wire S_AXIS_TREADY,
input wire [C_AXI_DATA_WIDTH-1 : 0] S_AXIS_TDATA,
input wire [(C_AXI_DATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
input wire S_AXIS_TLAST,
input wire S_AXIS_TVALID,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
); |
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
wire axi_stream_enabled;
wire axi_stream_data_valid;
wire [C_AXI_DATA_WIDTH-1:0] axi_stream_data;
axi4_stream_reader #
(
.C_S_AXIS_TDATA_WIDTH(C_AXI_DATA_WIDTH)
)
axi_stream_i
(
.S_AXIS_ACLK(ACLK),
.S_AXIS_ARESETN(ARESETN),
.S_AXIS_TREADY(S_AXIS_TREADY),
.S_AXIS_TDATA(S_AXIS_TDATA),
.S_AXIS_TSTRB(S_AXIS_TSTRB),
.S_AXIS_TLAST(S_AXIS_TLAST),
.S_AXIS_TVALID(S_AXIS_TVALID),
.ready(axi_stream_enabled),
.data_valid(axi_stream_data_valid),
.data(axi_stream_data)
);
reg [C_M_AXI_ADDR_WIDTH-1:0] axi_mm_write_address;
wire [C_AXI_DATA_WIDTH-1:0] axi_mm_write_data;
wire axi_mm_write_data_valid;
reg axi_mm_write_enabled;
wire axi_mm_write_start;
wire axi_mm_write_end;
wire axi_mm_write_ready;
wire axi_mm_output_idle;
wire axi_mm_output_error;
assign axi_mm_read_address = 0;
assign axi_mm_start_read = 0;
reg axi_mm_write_enabled_prev;
always @(posedge ACLK) begin
axi_mm_write_enabled_prev <= axi_mm_write_enabled;
end
assign axi_mm_write_start = (~axi_mm_write_enabled_prev & axi_mm_write_enabled);
axi4_full_master_rw #
(
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
axi_mm_i
(
.write_address(axi_mm_write_address),
.write_data(axi_mm_write_data),
.write_data_valid(axi_mm_write_data_valid),
.write_start(axi_mm_write_start),
.write_ready(axi_mm_write_ready),
.write_end(axi_mm_write_end),
.write_data_last(),
.read_address(0),
.read_start(1'b0),
.read_data(),
.read_data_valid(),
.read_data_last(),
.read_ready(1'b0),
.read_end(),
.output_idle(axi_mm_output_idle),
.output_error(axi_mm_output_error),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_AWID),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.M_AXI_AWLOCK(M_AXI_AWLOCK),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(M_AXI_AWQOS),
.M_AXI_AWUSER(M_AXI_AWUSER),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WUSER(M_AXI_WUSER),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(M_AXI_BID),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(M_AXI_BUSER),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(M_AXI_ARID),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.M_AXI_ARLOCK(M_AXI_ARLOCK),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(M_AXI_ARQOS),
.M_AXI_ARUSER(M_AXI_ARUSER),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(M_AXI_RID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_RUSER(M_AXI_RUSER),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY)
);
assign axi_stream_enabled = axi_mm_write_ready && axi_mm_write_enabled;
assign axi_mm_write_data = axi_stream_data;
assign axi_mm_write_data_valid = axi_stream_data_valid || sw_reset;
reg [3:0] state;
assign output_idle = (state == 0);
always @(posedge ACLK) begin
if (ARESETN == 0) begin
debug_data_sum <= 0;
state <= 0;
axi_mm_write_enabled <= 0;
axi_mm_write_address <= 0;
sw_reset_ok <= 0;
end else if (sw_reset) begin
if (axi_mm_output_idle) begin
sw_reset_ok <= 1;
end
end else begin
sw_reset_ok <= 0;
case (state)
0: begin
if (write_start) begin
$display("write start, write_address: %x", write_address);
axi_mm_write_address <= write_address;
axi_mm_write_enabled <= 1;
$display("axi4_s2mm state <= 1");
state <= 1;
end
end
1: begin
if (M_AXI_WVALID && M_AXI_WREADY) begin
debug_data_sum <= debug_data_sum + M_AXI_WDATA;
end
if (M_AXI_WLAST) begin
axi_mm_write_enabled <= 0;
state <= 2;
$display("axi4_s2mm state <= 2");
end
end
2: begin
if (axi_mm_write_end) begin
state <= 0;
$display("axi4_s2mm state <= 0");
end
end
endcase
end
end
endmodule | 5 |
140,530 | data/full_repos/permissive/90403445/src/axi4_stream_to_full.v | 90,403,445 | axi4_stream_to_full.v | v | 295 | 83 | [] | [] | [] | null | line:96: before: "(" | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:142: Signal definition not found, creating implicitly: \'axi_mm_read_address\'\n : ... Suggested alternative: \'axi_mm_write_address\'\n assign axi_mm_read_address = 0;\n ^~~~~~~~~~~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:143: Signal definition not found, creating implicitly: \'axi_mm_start_read\'\n : ... Suggested alternative: \'axi_mm_write_ready\'\n assign axi_mm_start_read = 0;\n ^~~~~~~~~~~~~~~~~\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:61: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:67: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:72: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:84: Little bit endian vector: MSB < LSB of bit range: -1:0\n output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,\n ^\n%Warning-LITENDIAN: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:91: Little bit endian vector: MSB < LSB of bit range: -1:0\n input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,\n ^\n%Error: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:108: Cannot find file containing module: \'axi4_stream_reader\'\n axi4_stream_reader #\n ^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader.v\n data/full_repos/permissive/90403445/src,data/full_repos/permissive/90403445/axi4_stream_reader.sv\n axi4_stream_reader\n axi4_stream_reader.v\n axi4_stream_reader.sv\n obj_dir/axi4_stream_reader\n obj_dir/axi4_stream_reader.v\n obj_dir/axi4_stream_reader.sv\n%Error: data/full_repos/permissive/90403445/src/axi4_stream_to_full.v:155: Cannot find file containing module: \'axi4_full_master_rw\'\n axi4_full_master_rw #\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n' | 308,625 | function | function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction | function integer clogb2 (input integer bit_depth); |
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction | 5 |
140,531 | data/full_repos/permissive/90403445/src/axi4_stream_writer.v | 90,403,445 | axi4_stream_writer.v | v | 50 | 72 | [] | [] | [] | [(20, 49)] | null | data/verilator_xmls/cbe4f920-363c-42a2-8ee5-af34431fad5d.xml | null | 308,626 | module | module axi_stream_writer #
(
parameter integer C_M_AXIS_TDATA_WIDTH = 32
)
(
input wire start,
input wire [C_M_AXIS_TDATA_WIDTH-1:0] data,
input wire data_valid,
input wire data_last,
output wire ready,
input wire M_AXIS_ACLK,
input wire M_AXIS_ARESETN,
output wire M_AXIS_TVALID,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
output wire M_AXIS_TLAST,
input wire M_AXIS_TREADY
);
assign M_AXIS_TVALID = data_valid;
assign M_AXIS_TDATA = data;
assign M_AXIS_TLAST = data_last;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
assign ready = M_AXIS_TREADY;
endmodule | module axi_stream_writer #
(
parameter integer C_M_AXIS_TDATA_WIDTH = 32
)
(
input wire start,
input wire [C_M_AXIS_TDATA_WIDTH-1:0] data,
input wire data_valid,
input wire data_last,
output wire ready,
input wire M_AXIS_ACLK,
input wire M_AXIS_ARESETN,
output wire M_AXIS_TVALID,
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
output wire M_AXIS_TLAST,
input wire M_AXIS_TREADY
); |
assign M_AXIS_TVALID = data_valid;
assign M_AXIS_TDATA = data;
assign M_AXIS_TLAST = data_last;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
assign ready = M_AXIS_TREADY;
endmodule | 5 |
140,532 | data/full_repos/permissive/90403445/src/dualport_ram.v | 90,403,445 | dualport_ram.v | v | 47 | 124 | [] | [] | [] | [(18, 46)] | null | data/verilator_xmls/af10e85b-c478-47d3-a5fe-e1a52eb319a1.xml | null | 308,627 | module | module dualport_ram #
(
parameter integer C_DATA_WIDTH = 64,
parameter integer C_ADDR_SIZE = 9
)
(
input clk,
input wea,
input reb,
input [C_ADDR_SIZE-1:0] addra,
input [C_ADDR_SIZE-1:0] addrb,
input [C_DATA_WIDTH-1:0] dia,
output reg [C_DATA_WIDTH-1:0] dob
);
localparam C_COUNT = (1<<C_ADDR_SIZE);
reg [C_DATA_WIDTH-1:0] ram [C_COUNT-1:0];
always @ (posedge clk) begin
if (wea)
ram[addra] <= dia;
if (reb) begin
dob <= ram[addrb];
end
end
endmodule | module dualport_ram #
(
parameter integer C_DATA_WIDTH = 64,
parameter integer C_ADDR_SIZE = 9
)
(
input clk,
input wea,
input reb,
input [C_ADDR_SIZE-1:0] addra,
input [C_ADDR_SIZE-1:0] addrb,
input [C_DATA_WIDTH-1:0] dia,
output reg [C_DATA_WIDTH-1:0] dob
); |
localparam C_COUNT = (1<<C_ADDR_SIZE);
reg [C_DATA_WIDTH-1:0] ram [C_COUNT-1:0];
always @ (posedge clk) begin
if (wea)
ram[addra] <= dia;
if (reb) begin
dob <= ram[addrb];
end
end
endmodule | 5 |
140,534 | data/full_repos/permissive/90403445/src/streamif_s2mem.v | 90,403,445 | streamif_s2mem.v | v | 833 | 94 | [] | [] | [] | [(18, 832)] | null | null | 1: b"%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:795: Assigning to input/const variable: 'M_AXI_AWREADY'\n assign M_AXI_AWREADY = M_AXI_MERGE_AWREADY;\n ^~~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:801: Assigning to input/const variable: 'M_AXI_WREADY'\n assign M_AXI_WREADY = M_AXI_MERGE_WREADY;\n ^~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:802: Assigning to input/const variable: 'M_AXI_BID'\n assign M_AXI_BID = M_AXI_MERGE_BID;\n ^~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:803: Assigning to input/const variable: 'M_AXI_BRESP'\n assign M_AXI_BRESP = M_AXI_MERGE_BRESP;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:804: Assigning to input/const variable: 'M_AXI_BUSER'\n assign M_AXI_BUSER = M_AXI_MERGE_BUSER;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:805: Assigning to input/const variable: 'M_AXI_BVALID'\n assign M_AXI_BVALID = M_AXI_MERGE_BVALID;\n ^~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:818: Assigning to input/const variable: 'M_AXI_ARREADY'\n assign M_AXI_ARREADY = M_AXI_MERGE_ARREADY;\n ^~~~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:819: Assigning to input/const variable: 'M_AXI_RID'\n assign M_AXI_RID = M_AXI_MERGE_RID;\n ^~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:820: Assigning to input/const variable: 'M_AXI_RDATA'\n assign M_AXI_RDATA = M_AXI_MERGE_RDATA;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:821: Assigning to input/const variable: 'M_AXI_RRESP'\n assign M_AXI_RRESP = M_AXI_MERGE_RRESP;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:822: Assigning to input/const variable: 'M_AXI_RLAST'\n assign M_AXI_RLAST = M_AXI_MERGE_RLAST;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:823: Assigning to input/const variable: 'M_AXI_RUSER'\n assign M_AXI_RUSER = M_AXI_MERGE_RUSER;\n ^~~~~~~~~~~\n%Error-ASSIGNIN: data/full_repos/permissive/90403445/src/streamif_s2mem.v:824: Assigning to input/const variable: 'M_AXI_RVALID'\n assign M_AXI_RVALID = M_AXI_MERGE_RVALID;\n ^~~~~~~~~~~~\n%Error: Exiting due to 13 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,629 | module | module streamif_s2mem #
(
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 1,
parameter integer C_M_AXI_ARUSER_WIDTH = 1,
parameter integer C_M_AXI_WUSER_WIDTH = 1,
parameter integer C_M_AXI_RUSER_WIDTH = 1,
parameter integer C_M_AXI_BUSER_WIDTH = 1
)
(
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
input wire [31:0] MM2S_CTRL_Addr,
input wire MM2S_CTRL_Start,
input wire MM2S_CTRL_Enabled,
output wire MM2S_CTRL_Idle,
output wire MM2S_CTRL_Last,
input wire [31:0] STREAMIF_CTRL_mm2s_Addr,
input wire STREAMIF_CTRL_mm2s_AddrValid,
input wire STREAMIF_CTRL_mm2s_Start,
output wire STREAMIF_CTRL_mm2s_Idle,
input wire STREAMIF_CTRL_mm2s_Reset,
output wire STREAMIF_CTRL_mm2s_ResetOK,
input wire MM2S_AXIS_TREADY,
output wire [31 : 0] MM2S_AXIS_TDATA,
output wire [(32/8)-1 : 0] MM2S_AXIS_TSTRB,
output wire MM2S_AXIS_TLAST,
output wire MM2S_AXIS_TVALID,
input wire [31:0] S2MM_CTRL_Addr,
input wire S2MM_CTRL_Start,
input wire S2MM_CTRL_Enabled,
output wire S2MM_CTRL_Idle,
output wire S2MM_CTRL_Last,
input wire [31:0] STREAMIF_CTRL_s2mm_Addr,
input wire STREAMIF_CTRL_s2mm_AddrValid,
input wire STREAMIF_CTRL_s2mm_Start,
output wire STREAMIF_CTRL_s2mm_Idle,
input wire STREAMIF_CTRL_s2mm_Reset,
output wire STREAMIF_CTRL_s2mm_ResetOK,
output wire S2MM_AXIS_TREADY,
input wire [31 : 0] S2MM_AXIS_TDATA,
input wire [(32/8)-1 : 0] S2MM_AXIS_TSTRB,
input wire S2MM_AXIS_TLAST,
input wire S2MM_AXIS_TVALID,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire ACLK, ARESETN;
assign ACLK = M_AXI_ACLK;
assign ARESETN = M_AXI_ARESETN;
localparam C_MM2S_DATA_WIDTH = 32;
localparam C_MM2S_BURST_LEN = 256;
localparam C_S2MM_DATA_WIDTH = 32;
localparam C_S2MM_BURST_LEN = 256;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] MM2S_AXI_AWADDR;
wire [7 : 0] MM2S_AXI_AWLEN;
wire [2 : 0] MM2S_AXI_AWSIZE;
wire [1 : 0] MM2S_AXI_AWBURST;
wire MM2S_AXI_AWLOCK;
wire [3 : 0] MM2S_AXI_AWCACHE;
wire [2 : 0] MM2S_AXI_AWPROT;
wire [3 : 0] MM2S_AXI_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] MM2S_AXI_AWUSER;
wire MM2S_AXI_AWVALID;
wire MM2S_AXI_AWREADY;
wire [C_MM2S_DATA_WIDTH-1 : 0] MM2S_AXI_WDATA;
wire [C_MM2S_DATA_WIDTH/8-1 : 0] MM2S_AXI_WSTRB;
wire MM2S_AXI_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] MM2S_AXI_WUSER;
wire MM2S_AXI_WVALID;
wire MM2S_AXI_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_BID;
wire [1 : 0] MM2S_AXI_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] MM2S_AXI_BUSER;
wire MM2S_AXI_BVALID;
wire MM2S_AXI_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] MM2S_AXI_ARADDR;
wire [7 : 0] MM2S_AXI_ARLEN;
wire [2 : 0] MM2S_AXI_ARSIZE;
wire [1 : 0] MM2S_AXI_ARBURST;
wire MM2S_AXI_ARLOCK;
wire [3 : 0] MM2S_AXI_ARCACHE;
wire [2 : 0] MM2S_AXI_ARPROT;
wire [3 : 0] MM2S_AXI_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] MM2S_AXI_ARUSER;
wire MM2S_AXI_ARVALID;
wire MM2S_AXI_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_RID;
wire [C_MM2S_DATA_WIDTH-1 : 0] MM2S_AXI_RDATA;
wire [1 : 0] MM2S_AXI_RRESP;
wire MM2S_AXI_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] MM2S_AXI_RUSER;
wire MM2S_AXI_RVALID;
wire MM2S_AXI_RREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] S2MM_AXI_AWADDR;
wire [7 : 0] S2MM_AXI_AWLEN;
wire [2 : 0] S2MM_AXI_AWSIZE;
wire [1 : 0] S2MM_AXI_AWBURST;
wire S2MM_AXI_AWLOCK;
wire [3 : 0] S2MM_AXI_AWCACHE;
wire [2 : 0] S2MM_AXI_AWPROT;
wire [3 : 0] S2MM_AXI_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S2MM_AXI_AWUSER;
wire S2MM_AXI_AWVALID;
wire S2MM_AXI_AWREADY;
wire [C_S2MM_DATA_WIDTH-1 : 0] S2MM_AXI_WDATA;
wire [C_S2MM_DATA_WIDTH/8-1 : 0] S2MM_AXI_WSTRB;
wire S2MM_AXI_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] S2MM_AXI_WUSER;
wire S2MM_AXI_WVALID;
wire S2MM_AXI_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_BID;
wire [1 : 0] S2MM_AXI_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] S2MM_AXI_BUSER;
wire S2MM_AXI_BVALID;
wire S2MM_AXI_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] S2MM_AXI_ARADDR;
wire [7 : 0] S2MM_AXI_ARLEN;
wire [2 : 0] S2MM_AXI_ARSIZE;
wire [1 : 0] S2MM_AXI_ARBURST;
wire S2MM_AXI_ARLOCK;
wire [3 : 0] S2MM_AXI_ARCACHE;
wire [2 : 0] S2MM_AXI_ARPROT;
wire [3 : 0] S2MM_AXI_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S2MM_AXI_ARUSER;
wire S2MM_AXI_ARVALID;
wire S2MM_AXI_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_RID;
wire [C_S2MM_DATA_WIDTH-1 : 0] S2MM_AXI_RDATA;
wire [1 : 0] S2MM_AXI_RRESP;
wire S2MM_AXI_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] S2MM_AXI_RUSER;
wire S2MM_AXI_RVALID;
wire S2MM_AXI_RREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_MERGE_AWADDR;
wire [7 : 0] M_AXI_MERGE_AWLEN;
wire [2 : 0] M_AXI_MERGE_AWSIZE;
wire [1 : 0] M_AXI_MERGE_AWBURST;
wire M_AXI_MERGE_AWLOCK;
wire [3 : 0] M_AXI_MERGE_AWCACHE;
wire [2 : 0] M_AXI_MERGE_AWPROT;
wire [3 : 0] M_AXI_MERGE_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_MERGE_AWUSER;
wire M_AXI_MERGE_AWVALID;
wire M_AXI_MERGE_AWREADY;
wire [C_S2MM_DATA_WIDTH-1 : 0] M_AXI_MERGE_WDATA;
wire [C_S2MM_DATA_WIDTH/8-1 : 0] M_AXI_MERGE_WSTRB;
wire M_AXI_MERGE_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_MERGE_WUSER;
wire M_AXI_MERGE_WVALID;
wire M_AXI_MERGE_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_BID;
wire [1 : 0] M_AXI_MERGE_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_MERGE_BUSER;
wire M_AXI_MERGE_BVALID;
wire M_AXI_MERGE_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_MERGE_ARADDR;
wire [7 : 0] M_AXI_MERGE_ARLEN;
wire [2 : 0] M_AXI_MERGE_ARSIZE;
wire [1 : 0] M_AXI_MERGE_ARBURST;
wire M_AXI_MERGE_ARLOCK;
wire [3 : 0] M_AXI_MERGE_ARCACHE;
wire [2 : 0] M_AXI_MERGE_ARPROT;
wire [3 : 0] M_AXI_MERGE_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_MERGE_ARUSER;
wire M_AXI_MERGE_ARVALID;
wire M_AXI_MERGE_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_RID;
wire [C_S2MM_DATA_WIDTH-1 : 0] M_AXI_MERGE_RDATA;
wire [1 : 0] M_AXI_MERGE_RRESP;
wire M_AXI_MERGE_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_MERGE_RUSER;
wire M_AXI_MERGE_RVALID;
wire M_AXI_MERGE_RREADY;
assign MM2S_CTRL_Last = MM2S_AXI_RLAST && MM2S_AXI_RVALID;
reg [31:0] mm2s_read_address;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
mm2s_read_address <= 0;
end else begin
if (MM2S_CTRL_Enabled)
mm2s_read_address <= MM2S_CTRL_Addr;
else if (STREAMIF_CTRL_mm2s_AddrValid)
mm2s_read_address <= STREAMIF_CTRL_mm2s_Addr;
else
mm2s_read_address <= mm2s_read_address;
end
end
wire mm2s_idle;
assign STREAMIF_CTRL_mm2s_Idle = mm2s_idle;
assign MM2S_CTRL_Idle = mm2s_idle;
wire mm2s_start_input;
assign mm2s_start_input = (MM2S_CTRL_Enabled) ? MM2S_CTRL_Start : STREAMIF_CTRL_mm2s_Start;
reg mm2s_start_input_old;
wire mm2s_start_signal;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
mm2s_start_input_old <= 0;
end else begin
mm2s_start_input_old <= mm2s_start_input;
end
end
assign mm2s_start_signal = (~mm2s_start_input_old & mm2s_start_input);
reg mm2s_start_signal_d;
always @(posedge ACLK) begin
if (ARESETN == 0)
mm2s_start_signal_d <= 0;
else
mm2s_start_signal_d <= mm2s_start_signal;
end
axi4_full_to_stream #
(
.C_M_AXI_BURST_LEN(C_MM2S_BURST_LEN),
.C_AXI_DATA_WIDTH(C_MM2S_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
mm2s
(
.ACLK(ACLK),
.ARESETN(ARESETN),
.sw_reset(STREAMIF_CTRL_mm2s_Reset),
.sw_reset_ok(STREAMIF_CTRL_mm2s_ResetOK),
.read_address(mm2s_read_address),
.start_read(mm2s_start_signal_d),
.output_idle(mm2s_idle),
.M_AXI_AWID(MM2S_AXI_AWID),
.M_AXI_AWADDR(MM2S_AXI_AWADDR),
.M_AXI_AWLEN(MM2S_AXI_AWLEN),
.M_AXI_AWSIZE(MM2S_AXI_AWSIZE),
.M_AXI_AWBURST(MM2S_AXI_AWBURST),
.M_AXI_AWLOCK(MM2S_AXI_AWLOCK),
.M_AXI_AWCACHE(MM2S_AXI_AWCACHE),
.M_AXI_AWPROT(MM2S_AXI_AWPROT),
.M_AXI_AWQOS(MM2S_AXI_AWQOS),
.M_AXI_AWUSER(MM2S_AXI_AWUSER),
.M_AXI_AWVALID(MM2S_AXI_AWVALID),
.M_AXI_AWREADY(MM2S_AXI_AWREADY),
.M_AXI_WDATA(MM2S_AXI_WDATA),
.M_AXI_WSTRB(MM2S_AXI_WSTRB),
.M_AXI_WLAST(MM2S_AXI_WLAST),
.M_AXI_WUSER(MM2S_AXI_WUSER),
.M_AXI_WVALID(MM2S_AXI_WVALID),
.M_AXI_WREADY(MM2S_AXI_WREADY),
.M_AXI_BID(MM2S_AXI_BID),
.M_AXI_BRESP(MM2S_AXI_BRESP),
.M_AXI_BUSER(MM2S_AXI_BUSER),
.M_AXI_BVALID(MM2S_AXI_BVALID),
.M_AXI_BREADY(MM2S_AXI_BREADY),
.M_AXI_ARID(MM2S_AXI_ARID),
.M_AXI_ARADDR(MM2S_AXI_ARADDR),
.M_AXI_ARLEN(MM2S_AXI_ARLEN),
.M_AXI_ARSIZE(MM2S_AXI_ARSIZE),
.M_AXI_ARBURST(MM2S_AXI_ARBURST),
.M_AXI_ARLOCK(MM2S_AXI_ARLOCK),
.M_AXI_ARCACHE(MM2S_AXI_ARCACHE),
.M_AXI_ARPROT(MM2S_AXI_ARPROT),
.M_AXI_ARQOS(MM2S_AXI_ARQOS),
.M_AXI_ARUSER(MM2S_AXI_ARUSER),
.M_AXI_ARVALID(MM2S_AXI_ARVALID),
.M_AXI_ARREADY(MM2S_AXI_ARREADY),
.M_AXI_RID(MM2S_AXI_RID),
.M_AXI_RDATA(MM2S_AXI_RDATA),
.M_AXI_RRESP(MM2S_AXI_RRESP),
.M_AXI_RLAST(MM2S_AXI_RLAST),
.M_AXI_RUSER(MM2S_AXI_RUSER),
.M_AXI_RVALID(MM2S_AXI_RVALID),
.M_AXI_RREADY(MM2S_AXI_RREADY),
.M_AXIS_TVALID(MM2S_AXIS_TVALID),
.M_AXIS_TDATA(MM2S_AXIS_TDATA),
.M_AXIS_TSTRB(MM2S_AXIS_TSTRB),
.M_AXIS_TLAST(MM2S_AXIS_TLAST),
.M_AXIS_TREADY(MM2S_AXIS_TREADY)
);
assign S2MM_CTRL_Last = S2MM_AXI_WLAST && S2MM_AXI_WVALID;
reg [31:0] s2mm_write_address;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
s2mm_write_address <= 0;
end else begin
if (S2MM_CTRL_Enabled)
s2mm_write_address <= S2MM_CTRL_Addr;
else if (STREAMIF_CTRL_s2mm_AddrValid)
s2mm_write_address <= STREAMIF_CTRL_s2mm_Addr;
else
s2mm_write_address <= s2mm_write_address;
end
end
wire s2mm_idle;
assign STREAMIF_CTRL_s2mm_Idle = s2mm_idle;
assign S2MM_CTRL_Idle = s2mm_idle;
wire s2mm_start_input;
assign s2mm_start_input = (S2MM_CTRL_Enabled) ? S2MM_CTRL_Start : STREAMIF_CTRL_s2mm_Start;
reg s2mm_start_input_old;
wire s2mm_start_signal;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
s2mm_start_input_old <= 0;
end else begin
s2mm_start_input_old <= s2mm_start_input;
end
end
assign s2mm_start_signal = (~s2mm_start_input_old & s2mm_start_input);
reg s2mm_start_signal_d;
always @(posedge ACLK) begin
if (ARESETN == 0)
s2mm_start_signal_d <= 0;
else
s2mm_start_signal_d <= s2mm_start_signal;
end
axi4_stream_to_full #
(
.C_AXI_DATA_WIDTH(C_S2MM_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_S2MM_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
s2mm
(
.ACLK(ACLK),
.ARESETN(ARESETN),
.sw_reset(STREAMIF_CTRL_s2mm_Reset),
.sw_reset_ok(STREAMIF_CTRL_s2mm_ResetOK),
.write_address(s2mm_write_address),
.write_start(s2mm_start_signal_d),
.output_idle(s2mm_idle),
.debug_data_sum(),
.S_AXIS_TREADY(S2MM_AXIS_TREADY),
.S_AXIS_TDATA(S2MM_AXIS_TDATA),
.S_AXIS_TSTRB(S2MM_AXIS_TSTRB),
.S_AXIS_TLAST(S2MM_AXIS_TLAST),
.S_AXIS_TVALID(S2MM_AXIS_TVALID),
.M_AXI_AWID(S2MM_AXI_AWID),
.M_AXI_AWADDR(S2MM_AXI_AWADDR),
.M_AXI_AWLEN(S2MM_AXI_AWLEN),
.M_AXI_AWSIZE(S2MM_AXI_AWSIZE),
.M_AXI_AWBURST(S2MM_AXI_AWBURST),
.M_AXI_AWLOCK(S2MM_AXI_AWLOCK),
.M_AXI_AWCACHE(S2MM_AXI_AWCACHE),
.M_AXI_AWPROT(S2MM_AXI_AWPROT),
.M_AXI_AWQOS(S2MM_AXI_AWQOS),
.M_AXI_AWUSER(S2MM_AXI_AWUSER),
.M_AXI_AWVALID(S2MM_AXI_AWVALID),
.M_AXI_AWREADY(S2MM_AXI_AWREADY),
.M_AXI_WDATA(S2MM_AXI_WDATA),
.M_AXI_WSTRB(S2MM_AXI_WSTRB),
.M_AXI_WLAST(S2MM_AXI_WLAST),
.M_AXI_WUSER(S2MM_AXI_WUSER),
.M_AXI_WVALID(S2MM_AXI_WVALID),
.M_AXI_WREADY(S2MM_AXI_WREADY),
.M_AXI_BID(S2MM_AXI_BID),
.M_AXI_BRESP(S2MM_AXI_BRESP),
.M_AXI_BUSER(S2MM_AXI_BUSER),
.M_AXI_BVALID(S2MM_AXI_BVALID),
.M_AXI_BREADY(S2MM_AXI_BREADY),
.M_AXI_ARID(S2MM_AXI_ARID),
.M_AXI_ARADDR(S2MM_AXI_ARADDR),
.M_AXI_ARLEN(S2MM_AXI_ARLEN),
.M_AXI_ARSIZE(S2MM_AXI_ARSIZE),
.M_AXI_ARBURST(S2MM_AXI_ARBURST),
.M_AXI_ARLOCK(S2MM_AXI_ARLOCK),
.M_AXI_ARCACHE(S2MM_AXI_ARCACHE),
.M_AXI_ARPROT(S2MM_AXI_ARPROT),
.M_AXI_ARQOS(S2MM_AXI_ARQOS),
.M_AXI_ARUSER(S2MM_AXI_ARUSER),
.M_AXI_ARVALID(S2MM_AXI_ARVALID),
.M_AXI_ARREADY(S2MM_AXI_ARREADY),
.M_AXI_RID(S2MM_AXI_RID),
.M_AXI_RDATA(S2MM_AXI_RDATA),
.M_AXI_RRESP(S2MM_AXI_RRESP),
.M_AXI_RLAST(S2MM_AXI_RLAST),
.M_AXI_RUSER(S2MM_AXI_RUSER),
.M_AXI_RVALID(S2MM_AXI_RVALID),
.M_AXI_RREADY(S2MM_AXI_RREADY)
);
axi4_read_write_merge #
(
.C_M_AXI_BURST_LEN(C_S2MM_BURST_LEN),
.C_M_AXI_DATA_WIDTH(C_S2MM_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
merge
(
.S_AXI_READ_AWID(MM2S_AXI_AWID),
.S_AXI_READ_AWADDR(MM2S_AXI_AWADDR),
.S_AXI_READ_AWLEN(MM2S_AXI_AWLEN),
.S_AXI_READ_AWSIZE(MM2S_AXI_AWSIZE),
.S_AXI_READ_AWBURST(MM2S_AXI_AWBURST),
.S_AXI_READ_AWLOCK(MM2S_AXI_AWLOCK),
.S_AXI_READ_AWCACHE(MM2S_AXI_AWCACHE),
.S_AXI_READ_AWPROT(MM2S_AXI_AWPROT),
.S_AXI_READ_AWQOS(MM2S_AXI_AWQOS),
.S_AXI_READ_AWUSER(MM2S_AXI_AWUSER),
.S_AXI_READ_AWVALID(MM2S_AXI_AWVALID),
.S_AXI_READ_AWREADY(MM2S_AXI_AWREADY),
.S_AXI_READ_WDATA(MM2S_AXI_WDATA),
.S_AXI_READ_WSTRB(MM2S_AXI_WSTRB),
.S_AXI_READ_WLAST(MM2S_AXI_WLAST),
.S_AXI_READ_WUSER(MM2S_AXI_WUSER),
.S_AXI_READ_WVALID(MM2S_AXI_WVALID),
.S_AXI_READ_WREADY(MM2S_AXI_WREADY),
.S_AXI_READ_BID(MM2S_AXI_BID),
.S_AXI_READ_BRESP(MM2S_AXI_BRESP),
.S_AXI_READ_BUSER(MM2S_AXI_BUSER),
.S_AXI_READ_BVALID(MM2S_AXI_BVALID),
.S_AXI_READ_BREADY(MM2S_AXI_BREADY),
.S_AXI_READ_ARID(MM2S_AXI_ARID),
.S_AXI_READ_ARADDR(MM2S_AXI_ARADDR),
.S_AXI_READ_ARLEN(MM2S_AXI_ARLEN),
.S_AXI_READ_ARSIZE(MM2S_AXI_ARSIZE),
.S_AXI_READ_ARBURST(MM2S_AXI_ARBURST),
.S_AXI_READ_ARLOCK(MM2S_AXI_ARLOCK),
.S_AXI_READ_ARCACHE(MM2S_AXI_ARCACHE),
.S_AXI_READ_ARPROT(MM2S_AXI_ARPROT),
.S_AXI_READ_ARQOS(MM2S_AXI_ARQOS),
.S_AXI_READ_ARUSER(MM2S_AXI_ARUSER),
.S_AXI_READ_ARVALID(MM2S_AXI_ARVALID),
.S_AXI_READ_ARREADY(MM2S_AXI_ARREADY),
.S_AXI_READ_RID(MM2S_AXI_RID),
.S_AXI_READ_RDATA(MM2S_AXI_RDATA),
.S_AXI_READ_RRESP(MM2S_AXI_RRESP),
.S_AXI_READ_RLAST(MM2S_AXI_RLAST),
.S_AXI_READ_RUSER(MM2S_AXI_RUSER),
.S_AXI_READ_RVALID(MM2S_AXI_RVALID),
.S_AXI_READ_RREADY(MM2S_AXI_RREADY),
.S_AXI_WRITE_AWID(S2MM_AXI_AWID),
.S_AXI_WRITE_AWADDR(S2MM_AXI_AWADDR),
.S_AXI_WRITE_AWLEN(S2MM_AXI_AWLEN),
.S_AXI_WRITE_AWSIZE(S2MM_AXI_AWSIZE),
.S_AXI_WRITE_AWBURST(S2MM_AXI_AWBURST),
.S_AXI_WRITE_AWLOCK(S2MM_AXI_AWLOCK),
.S_AXI_WRITE_AWCACHE(S2MM_AXI_AWCACHE),
.S_AXI_WRITE_AWPROT(S2MM_AXI_AWPROT),
.S_AXI_WRITE_AWQOS(S2MM_AXI_AWQOS),
.S_AXI_WRITE_AWUSER(S2MM_AXI_AWUSER),
.S_AXI_WRITE_AWVALID(S2MM_AXI_AWVALID),
.S_AXI_WRITE_AWREADY(S2MM_AXI_AWREADY),
.S_AXI_WRITE_WDATA(S2MM_AXI_WDATA),
.S_AXI_WRITE_WSTRB(S2MM_AXI_WSTRB),
.S_AXI_WRITE_WLAST(S2MM_AXI_WLAST),
.S_AXI_WRITE_WUSER(S2MM_AXI_WUSER),
.S_AXI_WRITE_WVALID(S2MM_AXI_WVALID),
.S_AXI_WRITE_WREADY(S2MM_AXI_WREADY),
.S_AXI_WRITE_BID(S2MM_AXI_BID),
.S_AXI_WRITE_BRESP(S2MM_AXI_BRESP),
.S_AXI_WRITE_BUSER(S2MM_AXI_BUSER),
.S_AXI_WRITE_BVALID(S2MM_AXI_BVALID),
.S_AXI_WRITE_BREADY(S2MM_AXI_BREADY),
.S_AXI_WRITE_ARID(S2MM_AXI_ARID),
.S_AXI_WRITE_ARADDR(S2MM_AXI_ARADDR),
.S_AXI_WRITE_ARLEN(S2MM_AXI_ARLEN),
.S_AXI_WRITE_ARSIZE(S2MM_AXI_ARSIZE),
.S_AXI_WRITE_ARBURST(S2MM_AXI_ARBURST),
.S_AXI_WRITE_ARLOCK(S2MM_AXI_ARLOCK),
.S_AXI_WRITE_ARCACHE(S2MM_AXI_ARCACHE),
.S_AXI_WRITE_ARPROT(S2MM_AXI_ARPROT),
.S_AXI_WRITE_ARQOS(S2MM_AXI_ARQOS),
.S_AXI_WRITE_ARUSER(S2MM_AXI_ARUSER),
.S_AXI_WRITE_ARVALID(S2MM_AXI_ARVALID),
.S_AXI_WRITE_ARREADY(S2MM_AXI_ARREADY),
.S_AXI_WRITE_RID(S2MM_AXI_RID),
.S_AXI_WRITE_RDATA(S2MM_AXI_RDATA),
.S_AXI_WRITE_RRESP(S2MM_AXI_RRESP),
.S_AXI_WRITE_RLAST(S2MM_AXI_RLAST),
.S_AXI_WRITE_RUSER(S2MM_AXI_RUSER),
.S_AXI_WRITE_RVALID(S2MM_AXI_RVALID),
.S_AXI_WRITE_RREADY(S2MM_AXI_RREADY),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_MERGE_AWID),
.M_AXI_AWADDR(M_AXI_MERGE_AWADDR),
.M_AXI_AWLEN(M_AXI_MERGE_AWLEN),
.M_AXI_AWSIZE(M_AXI_MERGE_AWSIZE),
.M_AXI_AWBURST(M_AXI_MERGE_AWBURST),
.M_AXI_AWLOCK(M_AXI_MERGE_AWLOCK),
.M_AXI_AWCACHE(M_AXI_MERGE_AWCACHE),
.M_AXI_AWPROT(M_AXI_MERGE_AWPROT),
.M_AXI_AWQOS(M_AXI_MERGE_AWQOS),
.M_AXI_AWUSER(M_AXI_MERGE_AWUSER),
.M_AXI_AWVALID(M_AXI_MERGE_AWVALID),
.M_AXI_AWREADY(M_AXI_MERGE_AWREADY),
.M_AXI_WDATA(M_AXI_MERGE_WDATA),
.M_AXI_WSTRB(M_AXI_MERGE_WSTRB),
.M_AXI_WLAST(M_AXI_MERGE_WLAST),
.M_AXI_WUSER(M_AXI_MERGE_WUSER),
.M_AXI_WVALID(M_AXI_MERGE_WVALID),
.M_AXI_WREADY(M_AXI_MERGE_WREADY),
.M_AXI_BID(M_AXI_MERGE_BID),
.M_AXI_BRESP(M_AXI_MERGE_BRESP),
.M_AXI_BUSER(M_AXI_MERGE_BUSER),
.M_AXI_BVALID(M_AXI_MERGE_BVALID),
.M_AXI_BREADY(M_AXI_MERGE_BREADY),
.M_AXI_ARID(M_AXI_MERGE_ARID),
.M_AXI_ARADDR(M_AXI_MERGE_ARADDR),
.M_AXI_ARLEN(M_AXI_MERGE_ARLEN),
.M_AXI_ARSIZE(M_AXI_MERGE_ARSIZE),
.M_AXI_ARBURST(M_AXI_MERGE_ARBURST),
.M_AXI_ARLOCK(M_AXI_MERGE_ARLOCK),
.M_AXI_ARCACHE(M_AXI_MERGE_ARCACHE),
.M_AXI_ARPROT(M_AXI_MERGE_ARPROT),
.M_AXI_ARQOS(M_AXI_MERGE_ARQOS),
.M_AXI_ARUSER(M_AXI_MERGE_ARUSER),
.M_AXI_ARVALID(M_AXI_MERGE_ARVALID),
.M_AXI_ARREADY(M_AXI_MERGE_ARREADY),
.M_AXI_RID(M_AXI_MERGE_RID),
.M_AXI_RDATA(M_AXI_MERGE_RDATA),
.M_AXI_RRESP(M_AXI_MERGE_RRESP),
.M_AXI_RLAST(M_AXI_MERGE_RLAST),
.M_AXI_RUSER(M_AXI_MERGE_RUSER),
.M_AXI_RVALID(M_AXI_MERGE_RVALID),
.M_AXI_RREADY(M_AXI_MERGE_RREADY)
);
generate
if (C_M_AXI_DATA_WIDTH == 64 && C_M_AXI_BURST_LEN == 128)
begin
axi4_32bit_to_64bit #
(
.C_S_AXI_BURST_LEN(256),
.C_S_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH),
.C_M_AXI_BURST_LEN(128),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
datawidth_converter
(
.debug_read(),
.debug_write(),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_AWID),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.M_AXI_AWLOCK(M_AXI_AWLOCK),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(M_AXI_AWQOS),
.M_AXI_AWUSER(M_AXI_AWUSER),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WUSER(M_AXI_WUSER),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(M_AXI_BID),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(M_AXI_BUSER),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(M_AXI_ARID),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.M_AXI_ARLOCK(M_AXI_ARLOCK),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(M_AXI_ARQOS),
.M_AXI_ARUSER(M_AXI_ARUSER),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(M_AXI_RID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_RUSER(M_AXI_RUSER),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.S_AXI_ACLK(ACLK),
.S_AXI_ARESETN(ARESETN),
.S_AXI_AWID(M_AXI_MERGE_AWID),
.S_AXI_AWADDR(M_AXI_MERGE_AWADDR),
.S_AXI_AWLEN(M_AXI_MERGE_AWLEN),
.S_AXI_AWSIZE(M_AXI_MERGE_AWSIZE),
.S_AXI_AWBURST(M_AXI_MERGE_AWBURST),
.S_AXI_AWLOCK(M_AXI_MERGE_AWLOCK),
.S_AXI_AWCACHE(M_AXI_MERGE_AWCACHE),
.S_AXI_AWPROT(M_AXI_MERGE_AWPROT),
.S_AXI_AWQOS(M_AXI_MERGE_AWQOS),
.S_AXI_AWUSER(M_AXI_MERGE_AWUSER),
.S_AXI_AWVALID(M_AXI_MERGE_AWVALID),
.S_AXI_AWREADY(M_AXI_MERGE_AWREADY),
.S_AXI_WDATA(M_AXI_MERGE_WDATA),
.S_AXI_WSTRB(M_AXI_MERGE_WSTRB),
.S_AXI_WLAST(M_AXI_MERGE_WLAST),
.S_AXI_WUSER(M_AXI_MERGE_WUSER),
.S_AXI_WVALID(M_AXI_MERGE_WVALID),
.S_AXI_WREADY(M_AXI_MERGE_WREADY),
.S_AXI_BID(M_AXI_MERGE_BID),
.S_AXI_BRESP(M_AXI_MERGE_BRESP),
.S_AXI_BUSER(M_AXI_MERGE_BUSER),
.S_AXI_BVALID(M_AXI_MERGE_BVALID),
.S_AXI_BREADY(M_AXI_MERGE_BREADY),
.S_AXI_ARID(M_AXI_MERGE_ARID),
.S_AXI_ARADDR(M_AXI_MERGE_ARADDR),
.S_AXI_ARLEN(M_AXI_MERGE_ARLEN),
.S_AXI_ARSIZE(M_AXI_MERGE_ARSIZE),
.S_AXI_ARBURST(M_AXI_MERGE_ARBURST),
.S_AXI_ARLOCK(M_AXI_MERGE_ARLOCK),
.S_AXI_ARCACHE(M_AXI_MERGE_ARCACHE),
.S_AXI_ARPROT(M_AXI_MERGE_ARPROT),
.S_AXI_ARQOS(M_AXI_MERGE_ARQOS),
.S_AXI_ARUSER(M_AXI_MERGE_ARUSER),
.S_AXI_ARVALID(M_AXI_MERGE_ARVALID),
.S_AXI_ARREADY(M_AXI_MERGE_ARREADY),
.S_AXI_RID(M_AXI_MERGE_RID),
.S_AXI_RDATA(M_AXI_MERGE_RDATA),
.S_AXI_RRESP(M_AXI_MERGE_RRESP),
.S_AXI_RLAST(M_AXI_MERGE_RLAST),
.S_AXI_RUSER(M_AXI_MERGE_RUSER),
.S_AXI_RVALID(M_AXI_MERGE_RVALID),
.S_AXI_RREADY(M_AXI_MERGE_RREADY)
);
end
if (C_M_AXI_DATA_WIDTH == 32 && C_M_AXI_BURST_LEN == 256) begin
assign M_AXI_AWID = M_AXI_MERGE_AWID;
assign M_AXI_AWADDR = M_AXI_MERGE_AWADDR;
assign M_AXI_AWLEN = M_AXI_MERGE_AWLEN;
assign M_AXI_AWSIZE = M_AXI_MERGE_AWSIZE;
assign M_AXI_AWBURST = M_AXI_MERGE_AWBURST;
assign M_AXI_AWLOCK = M_AXI_MERGE_AWLOCK;
assign M_AXI_AWCACHE = M_AXI_MERGE_AWCACHE;
assign M_AXI_AWPROT = M_AXI_MERGE_AWPROT;
assign M_AXI_AWQOS = M_AXI_MERGE_AWQOS;
assign M_AXI_AWUSER = M_AXI_MERGE_AWUSER;
assign M_AXI_AWVALID = M_AXI_MERGE_AWVALID;
assign M_AXI_AWREADY = M_AXI_MERGE_AWREADY;
assign M_AXI_WDATA = M_AXI_MERGE_WDATA;
assign M_AXI_WSTRB = M_AXI_MERGE_WSTRB;
assign M_AXI_WLAST = M_AXI_MERGE_WLAST;
assign M_AXI_WUSER = M_AXI_MERGE_WUSER;
assign M_AXI_WVALID = M_AXI_MERGE_WVALID;
assign M_AXI_WREADY = M_AXI_MERGE_WREADY;
assign M_AXI_BID = M_AXI_MERGE_BID;
assign M_AXI_BRESP = M_AXI_MERGE_BRESP;
assign M_AXI_BUSER = M_AXI_MERGE_BUSER;
assign M_AXI_BVALID = M_AXI_MERGE_BVALID;
assign M_AXI_BREADY = M_AXI_MERGE_BREADY;
assign M_AXI_ARID = M_AXI_MERGE_ARID;
assign M_AXI_ARADDR = M_AXI_MERGE_ARADDR;
assign M_AXI_ARLEN = M_AXI_MERGE_ARLEN;
assign M_AXI_ARSIZE = M_AXI_MERGE_ARSIZE;
assign M_AXI_ARBURST = M_AXI_MERGE_ARBURST;
assign M_AXI_ARLOCK = M_AXI_MERGE_ARLOCK;
assign M_AXI_ARCACHE = M_AXI_MERGE_ARCACHE;
assign M_AXI_ARPROT = M_AXI_MERGE_ARPROT;
assign M_AXI_ARQOS = M_AXI_MERGE_ARQOS;
assign M_AXI_ARUSER = M_AXI_MERGE_ARUSER;
assign M_AXI_ARVALID = M_AXI_MERGE_ARVALID;
assign M_AXI_ARREADY = M_AXI_MERGE_ARREADY;
assign M_AXI_RID = M_AXI_MERGE_RID;
assign M_AXI_RDATA = M_AXI_MERGE_RDATA;
assign M_AXI_RRESP = M_AXI_MERGE_RRESP;
assign M_AXI_RLAST = M_AXI_MERGE_RLAST;
assign M_AXI_RUSER = M_AXI_MERGE_RUSER;
assign M_AXI_RVALID = M_AXI_MERGE_RVALID;
assign M_AXI_RREADY = M_AXI_MERGE_RREADY;
end
endgenerate
endmodule | module streamif_s2mem #
(
parameter integer C_M_AXI_DATA_WIDTH = 32,
parameter integer C_M_AXI_BURST_LEN = 256,
parameter C_M_TARGET_SLAVE_BASE_ADDR = 32'h00000000,
parameter integer C_M_AXI_ID_WIDTH = 1,
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_AWUSER_WIDTH = 1,
parameter integer C_M_AXI_ARUSER_WIDTH = 1,
parameter integer C_M_AXI_WUSER_WIDTH = 1,
parameter integer C_M_AXI_RUSER_WIDTH = 1,
parameter integer C_M_AXI_BUSER_WIDTH = 1
)
(
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
input wire [31:0] MM2S_CTRL_Addr,
input wire MM2S_CTRL_Start,
input wire MM2S_CTRL_Enabled,
output wire MM2S_CTRL_Idle,
output wire MM2S_CTRL_Last,
input wire [31:0] STREAMIF_CTRL_mm2s_Addr,
input wire STREAMIF_CTRL_mm2s_AddrValid,
input wire STREAMIF_CTRL_mm2s_Start,
output wire STREAMIF_CTRL_mm2s_Idle,
input wire STREAMIF_CTRL_mm2s_Reset,
output wire STREAMIF_CTRL_mm2s_ResetOK,
input wire MM2S_AXIS_TREADY,
output wire [31 : 0] MM2S_AXIS_TDATA,
output wire [(32/8)-1 : 0] MM2S_AXIS_TSTRB,
output wire MM2S_AXIS_TLAST,
output wire MM2S_AXIS_TVALID,
input wire [31:0] S2MM_CTRL_Addr,
input wire S2MM_CTRL_Start,
input wire S2MM_CTRL_Enabled,
output wire S2MM_CTRL_Idle,
output wire S2MM_CTRL_Last,
input wire [31:0] STREAMIF_CTRL_s2mm_Addr,
input wire STREAMIF_CTRL_s2mm_AddrValid,
input wire STREAMIF_CTRL_s2mm_Start,
output wire STREAMIF_CTRL_s2mm_Idle,
input wire STREAMIF_CTRL_s2mm_Reset,
output wire STREAMIF_CTRL_s2mm_ResetOK,
output wire S2MM_AXIS_TREADY,
input wire [31 : 0] S2MM_AXIS_TDATA,
input wire [(32/8)-1 : 0] S2MM_AXIS_TSTRB,
input wire S2MM_AXIS_TLAST,
input wire S2MM_AXIS_TVALID,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_AWID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
output wire [7 : 0] M_AXI_AWLEN,
output wire [2 : 0] M_AXI_AWSIZE,
output wire [1 : 0] M_AXI_AWBURST,
output wire M_AXI_AWLOCK,
output wire [3 : 0] M_AXI_AWCACHE,
output wire [2 : 0] M_AXI_AWPROT,
output wire [3 : 0] M_AXI_AWQOS,
output wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1 : 0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_BID,
input wire [1 : 0] M_AXI_BRESP,
input wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
output wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_ARID,
output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_ARADDR,
output wire [7 : 0] M_AXI_ARLEN,
output wire [2 : 0] M_AXI_ARSIZE,
output wire [1 : 0] M_AXI_ARBURST,
output wire M_AXI_ARLOCK,
output wire [3 : 0] M_AXI_ARCACHE,
output wire [2 : 0] M_AXI_ARPROT,
output wire [3 : 0] M_AXI_ARQOS,
output wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
input wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_RID,
input wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_RDATA,
input wire [1 : 0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
); |
wire ACLK, ARESETN;
assign ACLK = M_AXI_ACLK;
assign ARESETN = M_AXI_ARESETN;
localparam C_MM2S_DATA_WIDTH = 32;
localparam C_MM2S_BURST_LEN = 256;
localparam C_S2MM_DATA_WIDTH = 32;
localparam C_S2MM_BURST_LEN = 256;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] MM2S_AXI_AWADDR;
wire [7 : 0] MM2S_AXI_AWLEN;
wire [2 : 0] MM2S_AXI_AWSIZE;
wire [1 : 0] MM2S_AXI_AWBURST;
wire MM2S_AXI_AWLOCK;
wire [3 : 0] MM2S_AXI_AWCACHE;
wire [2 : 0] MM2S_AXI_AWPROT;
wire [3 : 0] MM2S_AXI_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] MM2S_AXI_AWUSER;
wire MM2S_AXI_AWVALID;
wire MM2S_AXI_AWREADY;
wire [C_MM2S_DATA_WIDTH-1 : 0] MM2S_AXI_WDATA;
wire [C_MM2S_DATA_WIDTH/8-1 : 0] MM2S_AXI_WSTRB;
wire MM2S_AXI_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] MM2S_AXI_WUSER;
wire MM2S_AXI_WVALID;
wire MM2S_AXI_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_BID;
wire [1 : 0] MM2S_AXI_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] MM2S_AXI_BUSER;
wire MM2S_AXI_BVALID;
wire MM2S_AXI_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] MM2S_AXI_ARADDR;
wire [7 : 0] MM2S_AXI_ARLEN;
wire [2 : 0] MM2S_AXI_ARSIZE;
wire [1 : 0] MM2S_AXI_ARBURST;
wire MM2S_AXI_ARLOCK;
wire [3 : 0] MM2S_AXI_ARCACHE;
wire [2 : 0] MM2S_AXI_ARPROT;
wire [3 : 0] MM2S_AXI_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] MM2S_AXI_ARUSER;
wire MM2S_AXI_ARVALID;
wire MM2S_AXI_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] MM2S_AXI_RID;
wire [C_MM2S_DATA_WIDTH-1 : 0] MM2S_AXI_RDATA;
wire [1 : 0] MM2S_AXI_RRESP;
wire MM2S_AXI_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] MM2S_AXI_RUSER;
wire MM2S_AXI_RVALID;
wire MM2S_AXI_RREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] S2MM_AXI_AWADDR;
wire [7 : 0] S2MM_AXI_AWLEN;
wire [2 : 0] S2MM_AXI_AWSIZE;
wire [1 : 0] S2MM_AXI_AWBURST;
wire S2MM_AXI_AWLOCK;
wire [3 : 0] S2MM_AXI_AWCACHE;
wire [2 : 0] S2MM_AXI_AWPROT;
wire [3 : 0] S2MM_AXI_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] S2MM_AXI_AWUSER;
wire S2MM_AXI_AWVALID;
wire S2MM_AXI_AWREADY;
wire [C_S2MM_DATA_WIDTH-1 : 0] S2MM_AXI_WDATA;
wire [C_S2MM_DATA_WIDTH/8-1 : 0] S2MM_AXI_WSTRB;
wire S2MM_AXI_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] S2MM_AXI_WUSER;
wire S2MM_AXI_WVALID;
wire S2MM_AXI_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_BID;
wire [1 : 0] S2MM_AXI_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] S2MM_AXI_BUSER;
wire S2MM_AXI_BVALID;
wire S2MM_AXI_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] S2MM_AXI_ARADDR;
wire [7 : 0] S2MM_AXI_ARLEN;
wire [2 : 0] S2MM_AXI_ARSIZE;
wire [1 : 0] S2MM_AXI_ARBURST;
wire S2MM_AXI_ARLOCK;
wire [3 : 0] S2MM_AXI_ARCACHE;
wire [2 : 0] S2MM_AXI_ARPROT;
wire [3 : 0] S2MM_AXI_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] S2MM_AXI_ARUSER;
wire S2MM_AXI_ARVALID;
wire S2MM_AXI_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] S2MM_AXI_RID;
wire [C_S2MM_DATA_WIDTH-1 : 0] S2MM_AXI_RDATA;
wire [1 : 0] S2MM_AXI_RRESP;
wire S2MM_AXI_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] S2MM_AXI_RUSER;
wire S2MM_AXI_RVALID;
wire S2MM_AXI_RREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_AWID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_MERGE_AWADDR;
wire [7 : 0] M_AXI_MERGE_AWLEN;
wire [2 : 0] M_AXI_MERGE_AWSIZE;
wire [1 : 0] M_AXI_MERGE_AWBURST;
wire M_AXI_MERGE_AWLOCK;
wire [3 : 0] M_AXI_MERGE_AWCACHE;
wire [2 : 0] M_AXI_MERGE_AWPROT;
wire [3 : 0] M_AXI_MERGE_AWQOS;
wire [C_M_AXI_AWUSER_WIDTH-1 : 0] M_AXI_MERGE_AWUSER;
wire M_AXI_MERGE_AWVALID;
wire M_AXI_MERGE_AWREADY;
wire [C_S2MM_DATA_WIDTH-1 : 0] M_AXI_MERGE_WDATA;
wire [C_S2MM_DATA_WIDTH/8-1 : 0] M_AXI_MERGE_WSTRB;
wire M_AXI_MERGE_WLAST;
wire [C_M_AXI_WUSER_WIDTH-1 : 0] M_AXI_MERGE_WUSER;
wire M_AXI_MERGE_WVALID;
wire M_AXI_MERGE_WREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_BID;
wire [1 : 0] M_AXI_MERGE_BRESP;
wire [C_M_AXI_BUSER_WIDTH-1 : 0] M_AXI_MERGE_BUSER;
wire M_AXI_MERGE_BVALID;
wire M_AXI_MERGE_BREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_ARID;
wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_MERGE_ARADDR;
wire [7 : 0] M_AXI_MERGE_ARLEN;
wire [2 : 0] M_AXI_MERGE_ARSIZE;
wire [1 : 0] M_AXI_MERGE_ARBURST;
wire M_AXI_MERGE_ARLOCK;
wire [3 : 0] M_AXI_MERGE_ARCACHE;
wire [2 : 0] M_AXI_MERGE_ARPROT;
wire [3 : 0] M_AXI_MERGE_ARQOS;
wire [C_M_AXI_ARUSER_WIDTH-1 : 0] M_AXI_MERGE_ARUSER;
wire M_AXI_MERGE_ARVALID;
wire M_AXI_MERGE_ARREADY;
wire [C_M_AXI_ID_WIDTH-1 : 0] M_AXI_MERGE_RID;
wire [C_S2MM_DATA_WIDTH-1 : 0] M_AXI_MERGE_RDATA;
wire [1 : 0] M_AXI_MERGE_RRESP;
wire M_AXI_MERGE_RLAST;
wire [C_M_AXI_RUSER_WIDTH-1 : 0] M_AXI_MERGE_RUSER;
wire M_AXI_MERGE_RVALID;
wire M_AXI_MERGE_RREADY;
assign MM2S_CTRL_Last = MM2S_AXI_RLAST && MM2S_AXI_RVALID;
reg [31:0] mm2s_read_address;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
mm2s_read_address <= 0;
end else begin
if (MM2S_CTRL_Enabled)
mm2s_read_address <= MM2S_CTRL_Addr;
else if (STREAMIF_CTRL_mm2s_AddrValid)
mm2s_read_address <= STREAMIF_CTRL_mm2s_Addr;
else
mm2s_read_address <= mm2s_read_address;
end
end
wire mm2s_idle;
assign STREAMIF_CTRL_mm2s_Idle = mm2s_idle;
assign MM2S_CTRL_Idle = mm2s_idle;
wire mm2s_start_input;
assign mm2s_start_input = (MM2S_CTRL_Enabled) ? MM2S_CTRL_Start : STREAMIF_CTRL_mm2s_Start;
reg mm2s_start_input_old;
wire mm2s_start_signal;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
mm2s_start_input_old <= 0;
end else begin
mm2s_start_input_old <= mm2s_start_input;
end
end
assign mm2s_start_signal = (~mm2s_start_input_old & mm2s_start_input);
reg mm2s_start_signal_d;
always @(posedge ACLK) begin
if (ARESETN == 0)
mm2s_start_signal_d <= 0;
else
mm2s_start_signal_d <= mm2s_start_signal;
end
axi4_full_to_stream #
(
.C_M_AXI_BURST_LEN(C_MM2S_BURST_LEN),
.C_AXI_DATA_WIDTH(C_MM2S_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
mm2s
(
.ACLK(ACLK),
.ARESETN(ARESETN),
.sw_reset(STREAMIF_CTRL_mm2s_Reset),
.sw_reset_ok(STREAMIF_CTRL_mm2s_ResetOK),
.read_address(mm2s_read_address),
.start_read(mm2s_start_signal_d),
.output_idle(mm2s_idle),
.M_AXI_AWID(MM2S_AXI_AWID),
.M_AXI_AWADDR(MM2S_AXI_AWADDR),
.M_AXI_AWLEN(MM2S_AXI_AWLEN),
.M_AXI_AWSIZE(MM2S_AXI_AWSIZE),
.M_AXI_AWBURST(MM2S_AXI_AWBURST),
.M_AXI_AWLOCK(MM2S_AXI_AWLOCK),
.M_AXI_AWCACHE(MM2S_AXI_AWCACHE),
.M_AXI_AWPROT(MM2S_AXI_AWPROT),
.M_AXI_AWQOS(MM2S_AXI_AWQOS),
.M_AXI_AWUSER(MM2S_AXI_AWUSER),
.M_AXI_AWVALID(MM2S_AXI_AWVALID),
.M_AXI_AWREADY(MM2S_AXI_AWREADY),
.M_AXI_WDATA(MM2S_AXI_WDATA),
.M_AXI_WSTRB(MM2S_AXI_WSTRB),
.M_AXI_WLAST(MM2S_AXI_WLAST),
.M_AXI_WUSER(MM2S_AXI_WUSER),
.M_AXI_WVALID(MM2S_AXI_WVALID),
.M_AXI_WREADY(MM2S_AXI_WREADY),
.M_AXI_BID(MM2S_AXI_BID),
.M_AXI_BRESP(MM2S_AXI_BRESP),
.M_AXI_BUSER(MM2S_AXI_BUSER),
.M_AXI_BVALID(MM2S_AXI_BVALID),
.M_AXI_BREADY(MM2S_AXI_BREADY),
.M_AXI_ARID(MM2S_AXI_ARID),
.M_AXI_ARADDR(MM2S_AXI_ARADDR),
.M_AXI_ARLEN(MM2S_AXI_ARLEN),
.M_AXI_ARSIZE(MM2S_AXI_ARSIZE),
.M_AXI_ARBURST(MM2S_AXI_ARBURST),
.M_AXI_ARLOCK(MM2S_AXI_ARLOCK),
.M_AXI_ARCACHE(MM2S_AXI_ARCACHE),
.M_AXI_ARPROT(MM2S_AXI_ARPROT),
.M_AXI_ARQOS(MM2S_AXI_ARQOS),
.M_AXI_ARUSER(MM2S_AXI_ARUSER),
.M_AXI_ARVALID(MM2S_AXI_ARVALID),
.M_AXI_ARREADY(MM2S_AXI_ARREADY),
.M_AXI_RID(MM2S_AXI_RID),
.M_AXI_RDATA(MM2S_AXI_RDATA),
.M_AXI_RRESP(MM2S_AXI_RRESP),
.M_AXI_RLAST(MM2S_AXI_RLAST),
.M_AXI_RUSER(MM2S_AXI_RUSER),
.M_AXI_RVALID(MM2S_AXI_RVALID),
.M_AXI_RREADY(MM2S_AXI_RREADY),
.M_AXIS_TVALID(MM2S_AXIS_TVALID),
.M_AXIS_TDATA(MM2S_AXIS_TDATA),
.M_AXIS_TSTRB(MM2S_AXIS_TSTRB),
.M_AXIS_TLAST(MM2S_AXIS_TLAST),
.M_AXIS_TREADY(MM2S_AXIS_TREADY)
);
assign S2MM_CTRL_Last = S2MM_AXI_WLAST && S2MM_AXI_WVALID;
reg [31:0] s2mm_write_address;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
s2mm_write_address <= 0;
end else begin
if (S2MM_CTRL_Enabled)
s2mm_write_address <= S2MM_CTRL_Addr;
else if (STREAMIF_CTRL_s2mm_AddrValid)
s2mm_write_address <= STREAMIF_CTRL_s2mm_Addr;
else
s2mm_write_address <= s2mm_write_address;
end
end
wire s2mm_idle;
assign STREAMIF_CTRL_s2mm_Idle = s2mm_idle;
assign S2MM_CTRL_Idle = s2mm_idle;
wire s2mm_start_input;
assign s2mm_start_input = (S2MM_CTRL_Enabled) ? S2MM_CTRL_Start : STREAMIF_CTRL_s2mm_Start;
reg s2mm_start_input_old;
wire s2mm_start_signal;
always @(posedge ACLK) begin
if (ARESETN == 0) begin
s2mm_start_input_old <= 0;
end else begin
s2mm_start_input_old <= s2mm_start_input;
end
end
assign s2mm_start_signal = (~s2mm_start_input_old & s2mm_start_input);
reg s2mm_start_signal_d;
always @(posedge ACLK) begin
if (ARESETN == 0)
s2mm_start_signal_d <= 0;
else
s2mm_start_signal_d <= s2mm_start_signal;
end
axi4_stream_to_full #
(
.C_AXI_DATA_WIDTH(C_S2MM_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_S2MM_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
s2mm
(
.ACLK(ACLK),
.ARESETN(ARESETN),
.sw_reset(STREAMIF_CTRL_s2mm_Reset),
.sw_reset_ok(STREAMIF_CTRL_s2mm_ResetOK),
.write_address(s2mm_write_address),
.write_start(s2mm_start_signal_d),
.output_idle(s2mm_idle),
.debug_data_sum(),
.S_AXIS_TREADY(S2MM_AXIS_TREADY),
.S_AXIS_TDATA(S2MM_AXIS_TDATA),
.S_AXIS_TSTRB(S2MM_AXIS_TSTRB),
.S_AXIS_TLAST(S2MM_AXIS_TLAST),
.S_AXIS_TVALID(S2MM_AXIS_TVALID),
.M_AXI_AWID(S2MM_AXI_AWID),
.M_AXI_AWADDR(S2MM_AXI_AWADDR),
.M_AXI_AWLEN(S2MM_AXI_AWLEN),
.M_AXI_AWSIZE(S2MM_AXI_AWSIZE),
.M_AXI_AWBURST(S2MM_AXI_AWBURST),
.M_AXI_AWLOCK(S2MM_AXI_AWLOCK),
.M_AXI_AWCACHE(S2MM_AXI_AWCACHE),
.M_AXI_AWPROT(S2MM_AXI_AWPROT),
.M_AXI_AWQOS(S2MM_AXI_AWQOS),
.M_AXI_AWUSER(S2MM_AXI_AWUSER),
.M_AXI_AWVALID(S2MM_AXI_AWVALID),
.M_AXI_AWREADY(S2MM_AXI_AWREADY),
.M_AXI_WDATA(S2MM_AXI_WDATA),
.M_AXI_WSTRB(S2MM_AXI_WSTRB),
.M_AXI_WLAST(S2MM_AXI_WLAST),
.M_AXI_WUSER(S2MM_AXI_WUSER),
.M_AXI_WVALID(S2MM_AXI_WVALID),
.M_AXI_WREADY(S2MM_AXI_WREADY),
.M_AXI_BID(S2MM_AXI_BID),
.M_AXI_BRESP(S2MM_AXI_BRESP),
.M_AXI_BUSER(S2MM_AXI_BUSER),
.M_AXI_BVALID(S2MM_AXI_BVALID),
.M_AXI_BREADY(S2MM_AXI_BREADY),
.M_AXI_ARID(S2MM_AXI_ARID),
.M_AXI_ARADDR(S2MM_AXI_ARADDR),
.M_AXI_ARLEN(S2MM_AXI_ARLEN),
.M_AXI_ARSIZE(S2MM_AXI_ARSIZE),
.M_AXI_ARBURST(S2MM_AXI_ARBURST),
.M_AXI_ARLOCK(S2MM_AXI_ARLOCK),
.M_AXI_ARCACHE(S2MM_AXI_ARCACHE),
.M_AXI_ARPROT(S2MM_AXI_ARPROT),
.M_AXI_ARQOS(S2MM_AXI_ARQOS),
.M_AXI_ARUSER(S2MM_AXI_ARUSER),
.M_AXI_ARVALID(S2MM_AXI_ARVALID),
.M_AXI_ARREADY(S2MM_AXI_ARREADY),
.M_AXI_RID(S2MM_AXI_RID),
.M_AXI_RDATA(S2MM_AXI_RDATA),
.M_AXI_RRESP(S2MM_AXI_RRESP),
.M_AXI_RLAST(S2MM_AXI_RLAST),
.M_AXI_RUSER(S2MM_AXI_RUSER),
.M_AXI_RVALID(S2MM_AXI_RVALID),
.M_AXI_RREADY(S2MM_AXI_RREADY)
);
axi4_read_write_merge #
(
.C_M_AXI_BURST_LEN(C_S2MM_BURST_LEN),
.C_M_AXI_DATA_WIDTH(C_S2MM_DATA_WIDTH),
.C_M_TARGET_SLAVE_BASE_ADDR(C_M_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
merge
(
.S_AXI_READ_AWID(MM2S_AXI_AWID),
.S_AXI_READ_AWADDR(MM2S_AXI_AWADDR),
.S_AXI_READ_AWLEN(MM2S_AXI_AWLEN),
.S_AXI_READ_AWSIZE(MM2S_AXI_AWSIZE),
.S_AXI_READ_AWBURST(MM2S_AXI_AWBURST),
.S_AXI_READ_AWLOCK(MM2S_AXI_AWLOCK),
.S_AXI_READ_AWCACHE(MM2S_AXI_AWCACHE),
.S_AXI_READ_AWPROT(MM2S_AXI_AWPROT),
.S_AXI_READ_AWQOS(MM2S_AXI_AWQOS),
.S_AXI_READ_AWUSER(MM2S_AXI_AWUSER),
.S_AXI_READ_AWVALID(MM2S_AXI_AWVALID),
.S_AXI_READ_AWREADY(MM2S_AXI_AWREADY),
.S_AXI_READ_WDATA(MM2S_AXI_WDATA),
.S_AXI_READ_WSTRB(MM2S_AXI_WSTRB),
.S_AXI_READ_WLAST(MM2S_AXI_WLAST),
.S_AXI_READ_WUSER(MM2S_AXI_WUSER),
.S_AXI_READ_WVALID(MM2S_AXI_WVALID),
.S_AXI_READ_WREADY(MM2S_AXI_WREADY),
.S_AXI_READ_BID(MM2S_AXI_BID),
.S_AXI_READ_BRESP(MM2S_AXI_BRESP),
.S_AXI_READ_BUSER(MM2S_AXI_BUSER),
.S_AXI_READ_BVALID(MM2S_AXI_BVALID),
.S_AXI_READ_BREADY(MM2S_AXI_BREADY),
.S_AXI_READ_ARID(MM2S_AXI_ARID),
.S_AXI_READ_ARADDR(MM2S_AXI_ARADDR),
.S_AXI_READ_ARLEN(MM2S_AXI_ARLEN),
.S_AXI_READ_ARSIZE(MM2S_AXI_ARSIZE),
.S_AXI_READ_ARBURST(MM2S_AXI_ARBURST),
.S_AXI_READ_ARLOCK(MM2S_AXI_ARLOCK),
.S_AXI_READ_ARCACHE(MM2S_AXI_ARCACHE),
.S_AXI_READ_ARPROT(MM2S_AXI_ARPROT),
.S_AXI_READ_ARQOS(MM2S_AXI_ARQOS),
.S_AXI_READ_ARUSER(MM2S_AXI_ARUSER),
.S_AXI_READ_ARVALID(MM2S_AXI_ARVALID),
.S_AXI_READ_ARREADY(MM2S_AXI_ARREADY),
.S_AXI_READ_RID(MM2S_AXI_RID),
.S_AXI_READ_RDATA(MM2S_AXI_RDATA),
.S_AXI_READ_RRESP(MM2S_AXI_RRESP),
.S_AXI_READ_RLAST(MM2S_AXI_RLAST),
.S_AXI_READ_RUSER(MM2S_AXI_RUSER),
.S_AXI_READ_RVALID(MM2S_AXI_RVALID),
.S_AXI_READ_RREADY(MM2S_AXI_RREADY),
.S_AXI_WRITE_AWID(S2MM_AXI_AWID),
.S_AXI_WRITE_AWADDR(S2MM_AXI_AWADDR),
.S_AXI_WRITE_AWLEN(S2MM_AXI_AWLEN),
.S_AXI_WRITE_AWSIZE(S2MM_AXI_AWSIZE),
.S_AXI_WRITE_AWBURST(S2MM_AXI_AWBURST),
.S_AXI_WRITE_AWLOCK(S2MM_AXI_AWLOCK),
.S_AXI_WRITE_AWCACHE(S2MM_AXI_AWCACHE),
.S_AXI_WRITE_AWPROT(S2MM_AXI_AWPROT),
.S_AXI_WRITE_AWQOS(S2MM_AXI_AWQOS),
.S_AXI_WRITE_AWUSER(S2MM_AXI_AWUSER),
.S_AXI_WRITE_AWVALID(S2MM_AXI_AWVALID),
.S_AXI_WRITE_AWREADY(S2MM_AXI_AWREADY),
.S_AXI_WRITE_WDATA(S2MM_AXI_WDATA),
.S_AXI_WRITE_WSTRB(S2MM_AXI_WSTRB),
.S_AXI_WRITE_WLAST(S2MM_AXI_WLAST),
.S_AXI_WRITE_WUSER(S2MM_AXI_WUSER),
.S_AXI_WRITE_WVALID(S2MM_AXI_WVALID),
.S_AXI_WRITE_WREADY(S2MM_AXI_WREADY),
.S_AXI_WRITE_BID(S2MM_AXI_BID),
.S_AXI_WRITE_BRESP(S2MM_AXI_BRESP),
.S_AXI_WRITE_BUSER(S2MM_AXI_BUSER),
.S_AXI_WRITE_BVALID(S2MM_AXI_BVALID),
.S_AXI_WRITE_BREADY(S2MM_AXI_BREADY),
.S_AXI_WRITE_ARID(S2MM_AXI_ARID),
.S_AXI_WRITE_ARADDR(S2MM_AXI_ARADDR),
.S_AXI_WRITE_ARLEN(S2MM_AXI_ARLEN),
.S_AXI_WRITE_ARSIZE(S2MM_AXI_ARSIZE),
.S_AXI_WRITE_ARBURST(S2MM_AXI_ARBURST),
.S_AXI_WRITE_ARLOCK(S2MM_AXI_ARLOCK),
.S_AXI_WRITE_ARCACHE(S2MM_AXI_ARCACHE),
.S_AXI_WRITE_ARPROT(S2MM_AXI_ARPROT),
.S_AXI_WRITE_ARQOS(S2MM_AXI_ARQOS),
.S_AXI_WRITE_ARUSER(S2MM_AXI_ARUSER),
.S_AXI_WRITE_ARVALID(S2MM_AXI_ARVALID),
.S_AXI_WRITE_ARREADY(S2MM_AXI_ARREADY),
.S_AXI_WRITE_RID(S2MM_AXI_RID),
.S_AXI_WRITE_RDATA(S2MM_AXI_RDATA),
.S_AXI_WRITE_RRESP(S2MM_AXI_RRESP),
.S_AXI_WRITE_RLAST(S2MM_AXI_RLAST),
.S_AXI_WRITE_RUSER(S2MM_AXI_RUSER),
.S_AXI_WRITE_RVALID(S2MM_AXI_RVALID),
.S_AXI_WRITE_RREADY(S2MM_AXI_RREADY),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_MERGE_AWID),
.M_AXI_AWADDR(M_AXI_MERGE_AWADDR),
.M_AXI_AWLEN(M_AXI_MERGE_AWLEN),
.M_AXI_AWSIZE(M_AXI_MERGE_AWSIZE),
.M_AXI_AWBURST(M_AXI_MERGE_AWBURST),
.M_AXI_AWLOCK(M_AXI_MERGE_AWLOCK),
.M_AXI_AWCACHE(M_AXI_MERGE_AWCACHE),
.M_AXI_AWPROT(M_AXI_MERGE_AWPROT),
.M_AXI_AWQOS(M_AXI_MERGE_AWQOS),
.M_AXI_AWUSER(M_AXI_MERGE_AWUSER),
.M_AXI_AWVALID(M_AXI_MERGE_AWVALID),
.M_AXI_AWREADY(M_AXI_MERGE_AWREADY),
.M_AXI_WDATA(M_AXI_MERGE_WDATA),
.M_AXI_WSTRB(M_AXI_MERGE_WSTRB),
.M_AXI_WLAST(M_AXI_MERGE_WLAST),
.M_AXI_WUSER(M_AXI_MERGE_WUSER),
.M_AXI_WVALID(M_AXI_MERGE_WVALID),
.M_AXI_WREADY(M_AXI_MERGE_WREADY),
.M_AXI_BID(M_AXI_MERGE_BID),
.M_AXI_BRESP(M_AXI_MERGE_BRESP),
.M_AXI_BUSER(M_AXI_MERGE_BUSER),
.M_AXI_BVALID(M_AXI_MERGE_BVALID),
.M_AXI_BREADY(M_AXI_MERGE_BREADY),
.M_AXI_ARID(M_AXI_MERGE_ARID),
.M_AXI_ARADDR(M_AXI_MERGE_ARADDR),
.M_AXI_ARLEN(M_AXI_MERGE_ARLEN),
.M_AXI_ARSIZE(M_AXI_MERGE_ARSIZE),
.M_AXI_ARBURST(M_AXI_MERGE_ARBURST),
.M_AXI_ARLOCK(M_AXI_MERGE_ARLOCK),
.M_AXI_ARCACHE(M_AXI_MERGE_ARCACHE),
.M_AXI_ARPROT(M_AXI_MERGE_ARPROT),
.M_AXI_ARQOS(M_AXI_MERGE_ARQOS),
.M_AXI_ARUSER(M_AXI_MERGE_ARUSER),
.M_AXI_ARVALID(M_AXI_MERGE_ARVALID),
.M_AXI_ARREADY(M_AXI_MERGE_ARREADY),
.M_AXI_RID(M_AXI_MERGE_RID),
.M_AXI_RDATA(M_AXI_MERGE_RDATA),
.M_AXI_RRESP(M_AXI_MERGE_RRESP),
.M_AXI_RLAST(M_AXI_MERGE_RLAST),
.M_AXI_RUSER(M_AXI_MERGE_RUSER),
.M_AXI_RVALID(M_AXI_MERGE_RVALID),
.M_AXI_RREADY(M_AXI_MERGE_RREADY)
);
generate
if (C_M_AXI_DATA_WIDTH == 64 && C_M_AXI_BURST_LEN == 128)
begin
axi4_32bit_to_64bit #
(
.C_S_AXI_BURST_LEN(256),
.C_S_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_S_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_S_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_S_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_S_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_S_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH),
.C_M_AXI_BURST_LEN(128),
.C_M_AXI_ID_WIDTH(C_M_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M_AXI_ADDR_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M_AXI_BUSER_WIDTH)
)
datawidth_converter
(
.debug_read(),
.debug_write(),
.M_AXI_ACLK(ACLK),
.M_AXI_ARESETN(ARESETN),
.M_AXI_AWID(M_AXI_AWID),
.M_AXI_AWADDR(M_AXI_AWADDR),
.M_AXI_AWLEN(M_AXI_AWLEN),
.M_AXI_AWSIZE(M_AXI_AWSIZE),
.M_AXI_AWBURST(M_AXI_AWBURST),
.M_AXI_AWLOCK(M_AXI_AWLOCK),
.M_AXI_AWCACHE(M_AXI_AWCACHE),
.M_AXI_AWPROT(M_AXI_AWPROT),
.M_AXI_AWQOS(M_AXI_AWQOS),
.M_AXI_AWUSER(M_AXI_AWUSER),
.M_AXI_AWVALID(M_AXI_AWVALID),
.M_AXI_AWREADY(M_AXI_AWREADY),
.M_AXI_WDATA(M_AXI_WDATA),
.M_AXI_WSTRB(M_AXI_WSTRB),
.M_AXI_WLAST(M_AXI_WLAST),
.M_AXI_WUSER(M_AXI_WUSER),
.M_AXI_WVALID(M_AXI_WVALID),
.M_AXI_WREADY(M_AXI_WREADY),
.M_AXI_BID(M_AXI_BID),
.M_AXI_BRESP(M_AXI_BRESP),
.M_AXI_BUSER(M_AXI_BUSER),
.M_AXI_BVALID(M_AXI_BVALID),
.M_AXI_BREADY(M_AXI_BREADY),
.M_AXI_ARID(M_AXI_ARID),
.M_AXI_ARADDR(M_AXI_ARADDR),
.M_AXI_ARLEN(M_AXI_ARLEN),
.M_AXI_ARSIZE(M_AXI_ARSIZE),
.M_AXI_ARBURST(M_AXI_ARBURST),
.M_AXI_ARLOCK(M_AXI_ARLOCK),
.M_AXI_ARCACHE(M_AXI_ARCACHE),
.M_AXI_ARPROT(M_AXI_ARPROT),
.M_AXI_ARQOS(M_AXI_ARQOS),
.M_AXI_ARUSER(M_AXI_ARUSER),
.M_AXI_ARVALID(M_AXI_ARVALID),
.M_AXI_ARREADY(M_AXI_ARREADY),
.M_AXI_RID(M_AXI_RID),
.M_AXI_RDATA(M_AXI_RDATA),
.M_AXI_RRESP(M_AXI_RRESP),
.M_AXI_RLAST(M_AXI_RLAST),
.M_AXI_RUSER(M_AXI_RUSER),
.M_AXI_RVALID(M_AXI_RVALID),
.M_AXI_RREADY(M_AXI_RREADY),
.S_AXI_ACLK(ACLK),
.S_AXI_ARESETN(ARESETN),
.S_AXI_AWID(M_AXI_MERGE_AWID),
.S_AXI_AWADDR(M_AXI_MERGE_AWADDR),
.S_AXI_AWLEN(M_AXI_MERGE_AWLEN),
.S_AXI_AWSIZE(M_AXI_MERGE_AWSIZE),
.S_AXI_AWBURST(M_AXI_MERGE_AWBURST),
.S_AXI_AWLOCK(M_AXI_MERGE_AWLOCK),
.S_AXI_AWCACHE(M_AXI_MERGE_AWCACHE),
.S_AXI_AWPROT(M_AXI_MERGE_AWPROT),
.S_AXI_AWQOS(M_AXI_MERGE_AWQOS),
.S_AXI_AWUSER(M_AXI_MERGE_AWUSER),
.S_AXI_AWVALID(M_AXI_MERGE_AWVALID),
.S_AXI_AWREADY(M_AXI_MERGE_AWREADY),
.S_AXI_WDATA(M_AXI_MERGE_WDATA),
.S_AXI_WSTRB(M_AXI_MERGE_WSTRB),
.S_AXI_WLAST(M_AXI_MERGE_WLAST),
.S_AXI_WUSER(M_AXI_MERGE_WUSER),
.S_AXI_WVALID(M_AXI_MERGE_WVALID),
.S_AXI_WREADY(M_AXI_MERGE_WREADY),
.S_AXI_BID(M_AXI_MERGE_BID),
.S_AXI_BRESP(M_AXI_MERGE_BRESP),
.S_AXI_BUSER(M_AXI_MERGE_BUSER),
.S_AXI_BVALID(M_AXI_MERGE_BVALID),
.S_AXI_BREADY(M_AXI_MERGE_BREADY),
.S_AXI_ARID(M_AXI_MERGE_ARID),
.S_AXI_ARADDR(M_AXI_MERGE_ARADDR),
.S_AXI_ARLEN(M_AXI_MERGE_ARLEN),
.S_AXI_ARSIZE(M_AXI_MERGE_ARSIZE),
.S_AXI_ARBURST(M_AXI_MERGE_ARBURST),
.S_AXI_ARLOCK(M_AXI_MERGE_ARLOCK),
.S_AXI_ARCACHE(M_AXI_MERGE_ARCACHE),
.S_AXI_ARPROT(M_AXI_MERGE_ARPROT),
.S_AXI_ARQOS(M_AXI_MERGE_ARQOS),
.S_AXI_ARUSER(M_AXI_MERGE_ARUSER),
.S_AXI_ARVALID(M_AXI_MERGE_ARVALID),
.S_AXI_ARREADY(M_AXI_MERGE_ARREADY),
.S_AXI_RID(M_AXI_MERGE_RID),
.S_AXI_RDATA(M_AXI_MERGE_RDATA),
.S_AXI_RRESP(M_AXI_MERGE_RRESP),
.S_AXI_RLAST(M_AXI_MERGE_RLAST),
.S_AXI_RUSER(M_AXI_MERGE_RUSER),
.S_AXI_RVALID(M_AXI_MERGE_RVALID),
.S_AXI_RREADY(M_AXI_MERGE_RREADY)
);
end
if (C_M_AXI_DATA_WIDTH == 32 && C_M_AXI_BURST_LEN == 256) begin
assign M_AXI_AWID = M_AXI_MERGE_AWID;
assign M_AXI_AWADDR = M_AXI_MERGE_AWADDR;
assign M_AXI_AWLEN = M_AXI_MERGE_AWLEN;
assign M_AXI_AWSIZE = M_AXI_MERGE_AWSIZE;
assign M_AXI_AWBURST = M_AXI_MERGE_AWBURST;
assign M_AXI_AWLOCK = M_AXI_MERGE_AWLOCK;
assign M_AXI_AWCACHE = M_AXI_MERGE_AWCACHE;
assign M_AXI_AWPROT = M_AXI_MERGE_AWPROT;
assign M_AXI_AWQOS = M_AXI_MERGE_AWQOS;
assign M_AXI_AWUSER = M_AXI_MERGE_AWUSER;
assign M_AXI_AWVALID = M_AXI_MERGE_AWVALID;
assign M_AXI_AWREADY = M_AXI_MERGE_AWREADY;
assign M_AXI_WDATA = M_AXI_MERGE_WDATA;
assign M_AXI_WSTRB = M_AXI_MERGE_WSTRB;
assign M_AXI_WLAST = M_AXI_MERGE_WLAST;
assign M_AXI_WUSER = M_AXI_MERGE_WUSER;
assign M_AXI_WVALID = M_AXI_MERGE_WVALID;
assign M_AXI_WREADY = M_AXI_MERGE_WREADY;
assign M_AXI_BID = M_AXI_MERGE_BID;
assign M_AXI_BRESP = M_AXI_MERGE_BRESP;
assign M_AXI_BUSER = M_AXI_MERGE_BUSER;
assign M_AXI_BVALID = M_AXI_MERGE_BVALID;
assign M_AXI_BREADY = M_AXI_MERGE_BREADY;
assign M_AXI_ARID = M_AXI_MERGE_ARID;
assign M_AXI_ARADDR = M_AXI_MERGE_ARADDR;
assign M_AXI_ARLEN = M_AXI_MERGE_ARLEN;
assign M_AXI_ARSIZE = M_AXI_MERGE_ARSIZE;
assign M_AXI_ARBURST = M_AXI_MERGE_ARBURST;
assign M_AXI_ARLOCK = M_AXI_MERGE_ARLOCK;
assign M_AXI_ARCACHE = M_AXI_MERGE_ARCACHE;
assign M_AXI_ARPROT = M_AXI_MERGE_ARPROT;
assign M_AXI_ARQOS = M_AXI_MERGE_ARQOS;
assign M_AXI_ARUSER = M_AXI_MERGE_ARUSER;
assign M_AXI_ARVALID = M_AXI_MERGE_ARVALID;
assign M_AXI_ARREADY = M_AXI_MERGE_ARREADY;
assign M_AXI_RID = M_AXI_MERGE_RID;
assign M_AXI_RDATA = M_AXI_MERGE_RDATA;
assign M_AXI_RRESP = M_AXI_MERGE_RRESP;
assign M_AXI_RLAST = M_AXI_MERGE_RLAST;
assign M_AXI_RUSER = M_AXI_MERGE_RUSER;
assign M_AXI_RVALID = M_AXI_MERGE_RVALID;
assign M_AXI_RREADY = M_AXI_MERGE_RREADY;
end
endgenerate
endmodule | 5 |
140,535 | data/full_repos/permissive/90474316/fpga-rtl/OC_Can_av_wrapper.v | 90,474,316 | OC_Can_av_wrapper.v | v | 55 | 51 | [] | [] | [] | [(1, 55)] | null | null | 1: b"%Error: data/full_repos/permissive/90474316/fpga-rtl/OC_Can_av_wrapper.v:35: Cannot find file containing module: 'can_top'\ncan_top wishbone_can_inst\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl,data/full_repos/permissive/90474316/can_top\n data/full_repos/permissive/90474316/fpga-rtl,data/full_repos/permissive/90474316/can_top.v\n data/full_repos/permissive/90474316/fpga-rtl,data/full_repos/permissive/90474316/can_top.sv\n can_top\n can_top.v\n can_top.sv\n obj_dir/can_top\n obj_dir/can_top.v\n obj_dir/can_top.sv\n%Error: Exiting due to 1 error(s)\n" | 308,631 | module | module OC_Can_av_wrapper(
input av_clk,
input av_reset,
input [7:0] av_address,
input av_chipselect,
input av_write,
input av_read,
input [31:0] av_writedata,
output [31:0] av_readdata,
input [3:0] av_byteenable,
output av_waitrequest_n,
input CAN_clk,
input CAN_reset,
input CAN_rx,
output CAN_tx,
output CAN_bus_off,
output CAN_irq,
output CAN_clkout
);
wire wb_ack_o;
assign av_waitrequest_n = wb_ack_o;
assign av_readdata[31:8] = 24'hz;
`define CAN_WISHBONE_IF
can_top wishbone_can_inst
(
.wb_clk_i(av_clk),
.wb_rst_i(av_reset | CAN_reset),
.wb_dat_i(av_writedata[7:0]),
.wb_dat_o(av_readdata[7:0]),
.wb_cyc_i(av_write | av_read),
.wb_stb_i(av_chipselect & (av_write | av_read)),
.wb_we_i(av_write & ~av_read),
.wb_adr_i({av_address[7:0]}),
.wb_ack_o(wb_ack_o),
.clk_i(CAN_clk),
.rx_i(CAN_rx),
.tx_o(CAN_tx),
.bus_off_on(CAN_bus_off),
.irq_on(CAN_irq),
.clkout_o(CAN_clkout)
);
endmodule | module OC_Can_av_wrapper(
input av_clk,
input av_reset,
input [7:0] av_address,
input av_chipselect,
input av_write,
input av_read,
input [31:0] av_writedata,
output [31:0] av_readdata,
input [3:0] av_byteenable,
output av_waitrequest_n,
input CAN_clk,
input CAN_reset,
input CAN_rx,
output CAN_tx,
output CAN_bus_off,
output CAN_irq,
output CAN_clkout
); |
wire wb_ack_o;
assign av_waitrequest_n = wb_ack_o;
assign av_readdata[31:8] = 24'hz;
`define CAN_WISHBONE_IF
can_top wishbone_can_inst
(
.wb_clk_i(av_clk),
.wb_rst_i(av_reset | CAN_reset),
.wb_dat_i(av_writedata[7:0]),
.wb_dat_o(av_readdata[7:0]),
.wb_cyc_i(av_write | av_read),
.wb_stb_i(av_chipselect & (av_write | av_read)),
.wb_we_i(av_write & ~av_read),
.wb_adr_i({av_address[7:0]}),
.wb_ack_o(wb_ack_o),
.clk_i(CAN_clk),
.rx_i(CAN_rx),
.tx_o(CAN_tx),
.bus_off_on(CAN_bus_off),
.irq_on(CAN_irq),
.clkout_o(CAN_clkout)
);
endmodule | 2 |
140,536 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_crc.v | 90,474,316 | can_crc.v | v | 108 | 73 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_crc.v:69: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: Exiting due to 1 error(s)\n' | 308,636 | module | module can_crc (clk, data, enable, initialize, crc);
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
always @ (posedge clk)
begin
if(initialize)
crc <= #Tp 15'h0;
else if (enable)
begin
if (crc_next)
crc <= #Tp crc_tmp ^ 15'h4599;
else
crc <= #Tp crc_tmp;
end
end
endmodule | module can_crc (clk, data, enable, initialize, crc); |
parameter Tp = 1;
input clk;
input data;
input enable;
input initialize;
output [14:0] crc;
reg [14:0] crc;
wire crc_next;
wire [14:0] crc_tmp;
assign crc_next = data ^ crc[14];
assign crc_tmp = {crc[13:0], 1'b0};
always @ (posedge clk)
begin
if(initialize)
crc <= #Tp 15'h0;
else if (enable)
begin
if (crc_next)
crc <= #Tp crc_tmp ^ 15'h4599;
else
crc <= #Tp crc_tmp;
end
end
endmodule | 2 |
140,537 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_fifo.v | 90,474,316 | can_fifo.v | v | 746 | 105 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_fifo.v:132: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_fifo.v:134: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,638 | module | module can_fifo
(
clk,
rst,
wr,
data_in,
addr,
data_out,
fifo_selected,
reset_mode,
release_buffer,
extended_mode,
overrun,
info_empty,
info_cnt
`ifdef CAN_BIST
,
mbist_si_i,
mbist_so_o,
mbist_ctrl_i
`endif
);
parameter Tp = 1;
input clk;
input rst;
input wr;
input [7:0] data_in;
input [5:0] addr;
input reset_mode;
input release_buffer;
input extended_mode;
input fifo_selected;
output [7:0] data_out;
output overrun;
output info_empty;
output [6:0] info_cnt;
`ifdef CAN_BIST
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
wire mbist_s_0;
`endif
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
reg overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
reg overrun_info[0:63];
`else
reg [7:0] fifo [0:63];
reg [3:0] length_fifo[0:63];
reg overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
reg [5:0] rd_pointer;
reg [5:0] wr_pointer;
reg [5:0] read_address;
reg [5:0] wr_info_pointer;
reg [5:0] rd_info_pointer;
reg wr_q;
reg [3:0] len_cnt;
reg [6:0] fifo_cnt;
reg [6:0] info_cnt;
reg latch_overrun;
reg initialize_memories;
wire [3:0] length_info;
wire write_length_info;
wire fifo_empty;
wire fifo_full;
wire info_full;
assign write_length_info = (~wr) & wr_q;
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_q <=#Tp 1'b0;
else if (reset_mode)
wr_q <=#Tp 1'b0;
else
wr_q <=#Tp wr;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
len_cnt <= 4'h0;
else if (reset_mode | write_length_info)
len_cnt <=#Tp 4'h0;
else if (wr & (~fifo_full))
len_cnt <=#Tp len_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_info_pointer <= 6'h0;
else if (write_length_info & (~info_full) | initialize_memories)
wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
else if (reset_mode)
wr_info_pointer <=#Tp 6'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_info_pointer <= 6'h0;
else if (reset_mode)
rd_info_pointer <=#Tp 6'h0;
else if (release_buffer & (~fifo_empty))
rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_pointer <= 5'h0;
else if (release_buffer & (~fifo_empty))
rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
else if (reset_mode)
rd_pointer <=#Tp 5'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_pointer <= 5'h0;
else if (wr & (~fifo_full))
wr_pointer <=#Tp wr_pointer + 1'b1;
else if (reset_mode)
wr_pointer <=#Tp 5'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
latch_overrun <= 1'b0;
else if (reset_mode | write_length_info)
latch_overrun <=#Tp 1'b0;
else if (wr & fifo_full)
latch_overrun <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_cnt <= 7'h0;
else if (wr & (~release_buffer) & (~fifo_full))
fifo_cnt <=#Tp fifo_cnt + 1'b1;
else if ((~wr) & release_buffer & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
else if (reset_mode)
fifo_cnt <=#Tp 7'h0;
end
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
always @ (posedge clk or posedge rst)
begin
if (rst)
info_cnt <=#Tp 7'h0;
else if (reset_mode)
info_cnt <=#Tp 7'h0;
else if (write_length_info ^ release_buffer)
begin
if (release_buffer & (~info_empty))
info_cnt <=#Tp info_cnt - 1'b1;
else if (write_length_info & (~info_full))
info_cnt <=#Tp info_cnt + 1'b1;
end
end
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
always @ (extended_mode or rd_pointer or addr)
begin
if (extended_mode)
read_address = rd_pointer + (addr - 6'd16);
else
read_address = rd_pointer + (addr - 6'd20);
end
always @ (posedge clk or posedge rst)
begin
if (rst)
initialize_memories <= 1'b1;
else if (&wr_info_pointer)
initialize_memories <=#Tp 1'b0;
end
`ifdef ALTERA_RAM
lpm_ram_dp fifo
(
.q (data_out),
.rdclock (clk),
.wrclock (clk),
.data (data_in),
.wren (~(wr & (~fifo_full))),
.rden (~fifo_selected),
.wraddress (wr_pointer),
.rdaddress (read_address)
);
defparam fifo.lpm_width = 8;
defparam fifo.lpm_widthad = 6;
lpm_ram_dp info_fifo
(
.q (length_info),
.rdclock (clk),
.wrclock (clk),
.data (len_cnt & {4{~initialize_memories}}),
.wren (~(write_length_info & (~info_full) | initialize_memories)),
.rden (1'b0),
.wraddress (wr_info_pointer),
.rdaddress (rd_info_pointer)
);
defparam info_fifo.lpm_width = 4;
defparam info_fifo.lpm_widthad = 6;
lpm_ram_dp overrun_fifo
(
.q (overrun),
.rdclock (clk),
.wrclock (clk),
.data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.wren (~(write_length_info & (~info_full) | initialize_memories)),
.rden (1'b0),
.wraddress (wr_info_pointer),
.rdaddress (rd_info_pointer)
);
defparam overrun_fifo.lpm_width = 1;
defparam overrun_fifo.lpm_widthad = 6;
`else
`ifdef ACTEL_APA_RAM
actel_ram_64x8_sync fifo
(
.DO (data_out),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (data_in),
.PO (),
.WRB (~(wr & (~fifo_full))),
.RDB (~fifo_selected),
.WADDR (wr_pointer),
.RADDR (read_address)
);
actel_ram_64x4_sync info_fifo
(
.DO (length_info),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (len_cnt & {4{~initialize_memories}}),
.PO (),
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0),
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
actel_ram_64x1_sync overrun_fifo
(
.DO (overrun),
.RCLOCK (clk),
.WCLOCK (clk),
.DI ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.PO (),
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0),
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
`else
`ifdef XILINX_RAM
RAMB4_S8_S8 fifo
(
.DOA(),
.DOB(data_out),
.ADDRA({3'h0, wr_pointer}),
.CLKA(clk),
.DIA(data_in),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(wr & (~fifo_full)),
.ADDRB({3'h0, read_address}),
.CLKB(clk),
.DIB(8'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S4_S4 info_fifo
(
.DOA(),
.DOB(length_info),
.ADDRA({4'h0, wr_info_pointer}),
.CLKA(clk),
.DIA(len_cnt & {4{~initialize_memories}}),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({4'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(4'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S1_S1 overrun_fifo
(
.DOA(),
.DOB(overrun),
.ADDRA({6'h0, wr_info_pointer}),
.CLKA(clk),
.DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({6'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(1'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
`else
`ifdef VIRTUALSILICON_RAM
`ifdef CAN_BIST
vs_hdtp_64x8_bist fifo
`else
vs_hdtp_64x8 fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (read_address),
.WADR (wr_pointer),
.DI (data_in),
.DOUT (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full)))
`ifdef CAN_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`ifdef CAN_BIST
vs_hdtp_64x4_bist info_fifo
`else
vs_hdtp_64x4 info_fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (rd_info_pointer),
.WADR (wr_info_pointer),
.DI (len_cnt & {4{~initialize_memories}}),
.DOUT (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories))
`ifdef CAN_BIST
,
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`else
`ifdef ARTISAN_RAM
`ifdef CAN_BIST
art_hstp_64x8_bist fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (read_address),
.AW (wr_pointer),
.D (data_in),
.Q (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full))),
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
);
art_hstp_64x4_bist info_fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (rd_info_pointer),
.AW (wr_info_pointer),
.D (len_cnt & {4{~initialize_memories}}),
.Q (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories)),
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x8 fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (read_address),
.AB (wr_pointer),
.DA (8'h00),
.DB (data_in),
.QA (data_out),
.QB (),
.OENA (~fifo_selected),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(wr & (~fifo_full)))
);
art_hsdp_64x4 info_fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (rd_info_pointer),
.AB (wr_info_pointer),
.DA (4'h0),
.DB (len_cnt & {4{~initialize_memories}}),
.QA (length_info),
.QB (),
.OENA (1'b0),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(write_length_info & (~info_full) | initialize_memories))
);
`endif
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`else
always @ (posedge clk)
begin
if (wr & (~fifo_full))
fifo[wr_pointer] <=#Tp data_in;
end
assign data_out = fifo[read_address];
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
end
assign length_info = length_fifo[rd_info_pointer];
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`endif
`endif
`endif
`endif
`endif
endmodule | module can_fifo
(
clk,
rst,
wr,
data_in,
addr,
data_out,
fifo_selected,
reset_mode,
release_buffer,
extended_mode,
overrun,
info_empty,
info_cnt
`ifdef CAN_BIST
,
mbist_si_i,
mbist_so_o,
mbist_ctrl_i
`endif
); |
parameter Tp = 1;
input clk;
input rst;
input wr;
input [7:0] data_in;
input [5:0] addr;
input reset_mode;
input release_buffer;
input extended_mode;
input fifo_selected;
output [7:0] data_out;
output overrun;
output info_empty;
output [6:0] info_cnt;
`ifdef CAN_BIST
input mbist_si_i;
output mbist_so_o;
input [`CAN_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
wire mbist_s_0;
`endif
`ifdef ALTERA_RAM
`else
`ifdef ACTEL_APA_RAM
`else
`ifdef XILINX_RAM
`else
`ifdef ARTISAN_RAM
reg overrun_info[0:63];
`else
`ifdef VIRTUALSILICON_RAM
reg overrun_info[0:63];
`else
reg [7:0] fifo [0:63];
reg [3:0] length_fifo[0:63];
reg overrun_info[0:63];
`endif
`endif
`endif
`endif
`endif
reg [5:0] rd_pointer;
reg [5:0] wr_pointer;
reg [5:0] read_address;
reg [5:0] wr_info_pointer;
reg [5:0] rd_info_pointer;
reg wr_q;
reg [3:0] len_cnt;
reg [6:0] fifo_cnt;
reg [6:0] info_cnt;
reg latch_overrun;
reg initialize_memories;
wire [3:0] length_info;
wire write_length_info;
wire fifo_empty;
wire fifo_full;
wire info_full;
assign write_length_info = (~wr) & wr_q;
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_q <=#Tp 1'b0;
else if (reset_mode)
wr_q <=#Tp 1'b0;
else
wr_q <=#Tp wr;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
len_cnt <= 4'h0;
else if (reset_mode | write_length_info)
len_cnt <=#Tp 4'h0;
else if (wr & (~fifo_full))
len_cnt <=#Tp len_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_info_pointer <= 6'h0;
else if (write_length_info & (~info_full) | initialize_memories)
wr_info_pointer <=#Tp wr_info_pointer + 1'b1;
else if (reset_mode)
wr_info_pointer <=#Tp 6'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_info_pointer <= 6'h0;
else if (reset_mode)
rd_info_pointer <=#Tp 6'h0;
else if (release_buffer & (~fifo_empty))
rd_info_pointer <=#Tp rd_info_pointer + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
rd_pointer <= 5'h0;
else if (release_buffer & (~fifo_empty))
rd_pointer <=#Tp rd_pointer + {2'h0, length_info};
else if (reset_mode)
rd_pointer <=#Tp 5'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
wr_pointer <= 5'h0;
else if (wr & (~fifo_full))
wr_pointer <=#Tp wr_pointer + 1'b1;
else if (reset_mode)
wr_pointer <=#Tp 5'h0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
latch_overrun <= 1'b0;
else if (reset_mode | write_length_info)
latch_overrun <=#Tp 1'b0;
else if (wr & fifo_full)
latch_overrun <=#Tp 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
fifo_cnt <= 7'h0;
else if (wr & (~release_buffer) & (~fifo_full))
fifo_cnt <=#Tp fifo_cnt + 1'b1;
else if ((~wr) & release_buffer & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info};
else if (wr & release_buffer & (~fifo_full) & (~fifo_empty))
fifo_cnt <=#Tp fifo_cnt - {3'h0, length_info} + 1'b1;
else if (reset_mode)
fifo_cnt <=#Tp 7'h0;
end
assign fifo_full = fifo_cnt == 7'd64;
assign fifo_empty = fifo_cnt == 7'd0;
always @ (posedge clk or posedge rst)
begin
if (rst)
info_cnt <=#Tp 7'h0;
else if (reset_mode)
info_cnt <=#Tp 7'h0;
else if (write_length_info ^ release_buffer)
begin
if (release_buffer & (~info_empty))
info_cnt <=#Tp info_cnt - 1'b1;
else if (write_length_info & (~info_full))
info_cnt <=#Tp info_cnt + 1'b1;
end
end
assign info_full = info_cnt == 7'd64;
assign info_empty = info_cnt == 7'd0;
always @ (extended_mode or rd_pointer or addr)
begin
if (extended_mode)
read_address = rd_pointer + (addr - 6'd16);
else
read_address = rd_pointer + (addr - 6'd20);
end
always @ (posedge clk or posedge rst)
begin
if (rst)
initialize_memories <= 1'b1;
else if (&wr_info_pointer)
initialize_memories <=#Tp 1'b0;
end
`ifdef ALTERA_RAM
lpm_ram_dp fifo
(
.q (data_out),
.rdclock (clk),
.wrclock (clk),
.data (data_in),
.wren (~(wr & (~fifo_full))),
.rden (~fifo_selected),
.wraddress (wr_pointer),
.rdaddress (read_address)
);
defparam fifo.lpm_width = 8;
defparam fifo.lpm_widthad = 6;
lpm_ram_dp info_fifo
(
.q (length_info),
.rdclock (clk),
.wrclock (clk),
.data (len_cnt & {4{~initialize_memories}}),
.wren (~(write_length_info & (~info_full) | initialize_memories)),
.rden (1'b0),
.wraddress (wr_info_pointer),
.rdaddress (rd_info_pointer)
);
defparam info_fifo.lpm_width = 4;
defparam info_fifo.lpm_widthad = 6;
lpm_ram_dp overrun_fifo
(
.q (overrun),
.rdclock (clk),
.wrclock (clk),
.data ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.wren (~(write_length_info & (~info_full) | initialize_memories)),
.rden (1'b0),
.wraddress (wr_info_pointer),
.rdaddress (rd_info_pointer)
);
defparam overrun_fifo.lpm_width = 1;
defparam overrun_fifo.lpm_widthad = 6;
`else
`ifdef ACTEL_APA_RAM
actel_ram_64x8_sync fifo
(
.DO (data_out),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (data_in),
.PO (),
.WRB (~(wr & (~fifo_full))),
.RDB (~fifo_selected),
.WADDR (wr_pointer),
.RADDR (read_address)
);
actel_ram_64x4_sync info_fifo
(
.DO (length_info),
.RCLOCK (clk),
.WCLOCK (clk),
.DI (len_cnt & {4{~initialize_memories}}),
.PO (),
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0),
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
actel_ram_64x1_sync overrun_fifo
(
.DO (overrun),
.RCLOCK (clk),
.WCLOCK (clk),
.DI ((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.PO (),
.WRB (~(write_length_info & (~info_full) | initialize_memories)),
.RDB (1'b0),
.WADDR (wr_info_pointer),
.RADDR (rd_info_pointer)
);
`else
`ifdef XILINX_RAM
RAMB4_S8_S8 fifo
(
.DOA(),
.DOB(data_out),
.ADDRA({3'h0, wr_pointer}),
.CLKA(clk),
.DIA(data_in),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(wr & (~fifo_full)),
.ADDRB({3'h0, read_address}),
.CLKB(clk),
.DIB(8'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S4_S4 info_fifo
(
.DOA(),
.DOB(length_info),
.ADDRA({4'h0, wr_info_pointer}),
.CLKA(clk),
.DIA(len_cnt & {4{~initialize_memories}}),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({4'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(4'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
RAMB4_S1_S1 overrun_fifo
(
.DOA(),
.DOB(overrun),
.ADDRA({6'h0, wr_info_pointer}),
.CLKA(clk),
.DIA((latch_overrun | (wr & fifo_full)) & (~initialize_memories)),
.ENA(1'b1),
.RSTA(1'b0),
.WEA(write_length_info & (~info_full) | initialize_memories),
.ADDRB({6'h0, rd_info_pointer}),
.CLKB(clk),
.DIB(1'h0),
.ENB(1'b1),
.RSTB(1'b0),
.WEB(1'b0)
);
`else
`ifdef VIRTUALSILICON_RAM
`ifdef CAN_BIST
vs_hdtp_64x8_bist fifo
`else
vs_hdtp_64x8 fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (read_address),
.WADR (wr_pointer),
.DI (data_in),
.DOUT (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full)))
`ifdef CAN_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`ifdef CAN_BIST
vs_hdtp_64x4_bist info_fifo
`else
vs_hdtp_64x4 info_fifo
`endif
(
.RCK (clk),
.WCK (clk),
.RADR (rd_info_pointer),
.WADR (wr_info_pointer),
.DI (len_cnt & {4{~initialize_memories}}),
.DOUT (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories))
`ifdef CAN_BIST
,
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`else
`ifdef ARTISAN_RAM
`ifdef CAN_BIST
art_hstp_64x8_bist fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (read_address),
.AW (wr_pointer),
.D (data_in),
.Q (data_out),
.REN (~fifo_selected),
.WEN (~(wr & (~fifo_full))),
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_s_0),
.mbist_ctrl_i (mbist_ctrl_i)
);
art_hstp_64x4_bist info_fifo
(
.CLKR (clk),
.CLKW (clk),
.AR (rd_info_pointer),
.AW (wr_info_pointer),
.D (len_cnt & {4{~initialize_memories}}),
.Q (length_info),
.REN (1'b0),
.WEN (~(write_length_info & (~info_full) | initialize_memories)),
.mbist_si_i (mbist_s_0),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x8 fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (read_address),
.AB (wr_pointer),
.DA (8'h00),
.DB (data_in),
.QA (data_out),
.QB (),
.OENA (~fifo_selected),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(wr & (~fifo_full)))
);
art_hsdp_64x4 info_fifo
(
.CENA (1'b0),
.CENB (1'b0),
.CLKA (clk),
.CLKB (clk),
.AA (rd_info_pointer),
.AB (wr_info_pointer),
.DA (4'h0),
.DB (len_cnt & {4{~initialize_memories}}),
.QA (length_info),
.QB (),
.OENA (1'b0),
.OENB (1'b1),
.WENA (1'b1),
.WENB (~(write_length_info & (~info_full) | initialize_memories))
);
`endif
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`else
always @ (posedge clk)
begin
if (wr & (~fifo_full))
fifo[wr_pointer] <=#Tp data_in;
end
assign data_out = fifo[read_address];
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
length_fifo[wr_info_pointer] <=#Tp len_cnt & {4{~initialize_memories}};
end
assign length_info = length_fifo[rd_info_pointer];
always @ (posedge clk)
begin
if (write_length_info & (~info_full) | initialize_memories)
overrun_info[wr_info_pointer] <=#Tp (latch_overrun | (wr & fifo_full)) & (~initialize_memories);
end
assign overrun = overrun_info[rd_info_pointer];
`endif
`endif
`endif
`endif
`endif
endmodule | 2 |
140,538 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_ibo.v | 90,474,316 | can_ibo.v | v | 81 | 71 | [] | ['general public license', 'free software foundation'] | [] | [(62, 80)] | null | null | 1: b"%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_ibo.v:65: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n do\n ^~\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_ibo.v:69: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\noutput [7:0] do;\n ^~\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/asyst_2/rtl/verilog/can_ibo.v:71: syntax error, unexpected do, expecting TYPE-IDENTIFIER\nassign do[0] = di[7];\n ^~\n%Error: Exiting due to 3 error(s)\n" | 308,639 | module | module can_ibo
(
di,
do
);
input [7:0] di;
output [7:0] do;
assign do[0] = di[7];
assign do[1] = di[6];
assign do[2] = di[5];
assign do[3] = di[4];
assign do[4] = di[3];
assign do[5] = di[2];
assign do[6] = di[1];
assign do[7] = di[0];
endmodule | module can_ibo
(
di,
do
); |
input [7:0] di;
output [7:0] do;
assign do[0] = di[7];
assign do[1] = di[6];
assign do[2] = di[5];
assign do[3] = di[4];
assign do[4] = di[3];
assign do[5] = di[2];
assign do[6] = di[1];
assign do[7] = di[0];
endmodule | 2 |
140,542 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_bitstuff.v | 90,474,316 | can_bitstuff.v | v | 138 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_bitstuff.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_bitstuff.v:54: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,677 | module | module can_bitstuff
( clk,
rst,
enable,
data_in,
data_out
);
parameter Tp = 1;
input clk;
input rst;
input enable;
input [30:0]arbitration;
output data_out;
reg [2:0] bit_cnt;
reg data_in_q;
always @ (posedge clk or posedge rst)
begin
if(rst)
data_in_q <= 0;
else if (enable)
data_in_q <= data_in;
else
data_in_q <= ~data_in;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
bit_cnt <= 0;
else if (enable)
begin
if(data_in ^ data_in_q)
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1'b1;
end
else
bit_cnt <= 0;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
data_out <= 0;
else if (enable)
data_in_q <= data_in;
else
data_in_q <= ~data_in;
end
wire go_idle;
always @ (posedge clk or posedge rst)
begin
if(rst)
cnt <= 0;
else if(data_in)
cnt <= cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
idle <= 1'b0;
else if(go_idle)
idle <= 1'b1;
end
endmodule | module can_bitstuff
( clk,
rst,
enable,
data_in,
data_out
); |
parameter Tp = 1;
input clk;
input rst;
input enable;
input [30:0]arbitration;
output data_out;
reg [2:0] bit_cnt;
reg data_in_q;
always @ (posedge clk or posedge rst)
begin
if(rst)
data_in_q <= 0;
else if (enable)
data_in_q <= data_in;
else
data_in_q <= ~data_in;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
bit_cnt <= 0;
else if (enable)
begin
if(data_in ^ data_in_q)
bit_cnt <= 0;
else
bit_cnt <= bit_cnt + 1'b1;
end
else
bit_cnt <= 0;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
data_out <= 0;
else if (enable)
data_in_q <= data_in;
else
data_in_q <= ~data_in;
end
wire go_idle;
always @ (posedge clk or posedge rst)
begin
if(rst)
cnt <= 0;
else if(data_in)
cnt <= cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if(rst)
idle <= 1'b0;
else if(go_idle)
idle <= 1'b1;
end
endmodule | 2 |
140,544 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v | 90,474,316 | can_btl.v | v | 248 | 142 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v:54: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v:206: syntax error, unexpected IDENTIFIER\n reseti clock to 0 so we start with new bit sooner\n ^~~~~\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v:206: Unsupported: SystemVerilog 2005 reserved word not implemented: \'with\'\n reseti clock to 0 so we start with new bit sooner\n ^~~~\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_btl.v:226: syntax error, unexpected wire\nwire sample_time = \n^~~~\n%Error: Cannot continue\n' | 308,679 | module | module can_btl
(
clk,
rst,
rx,
reset_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling,
take_sample,
clk_en,
idle,
sync_mode
);
parameter Tp = 1;
input clk;
input rst;
input rx;
input reset_mode;
input [5:0] baud_r_presc;
input [1:0] sync_jump_width;
input [3:0] time_segment1;
input [2:0] time_segment2;
input triple_sampling;
output take_sample;
output clk_en;
input idle;
input sync_mode;
reg [8:0] clk_cnt;
reg clk_en;
reg hard_sync_blocked;
reg resync_blocked;
reg monitored_bit;
always @ (posedge clk or posedge rst)
begin
if (rst)
monitored_bit <= 1'b0;
else if(clk_en)
monitored_bit <=#Tp rx;
end
reg sampled_bit;
reg [7:0] quant_cnt;
wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1;
wire hard_sync = idle & (~monitored_bit) & sampled_bit & (~hard_sync_blocked);
wire resync = (~idle) & (~monitored_bit) & sampled_bit & (~resync_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
clk_cnt <= 0;
clk_en <= 1'b0;
end
else if (clk_cnt == (preset_cnt-1))
begin
clk_cnt <=#Tp 0;
clk_en <=#Tp 1'b1;
end
else
begin
clk_cnt <=#Tp clk_cnt + 1;
clk_en <=#Tp 1'b0;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
quant_cnt <=#Tp 0;
hard_sync_blocked <=#Tp 1'b0;
end
else if (clk_en)
begin
if (hard_sync || (quant_cnt == (time_segment1 + time_segment2 + 2)))
begin
quant_cnt <=#Tp 0;
hard_sync_blocked <=#Tp hard_sync;
end
else
begin
quant_cnt <=#Tp quant_cnt + 1;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
resync_blocked <=#Tp 1'b0;
end
else if (clk_en)
begin
if (resync)
begin
if (quant_cnt == (time_segment1 + time_segment2 + 2))
dodatek = 0;
else if (sample_point_passed)
dodatek = quant_cnt;
else
reseti clock to 0 so we start with new bit sooner
reg sample_point_passed;
always @ (posedge clk)
begin
if (clk_en & (quant_cnt == (time_segment1 + time_segment2 + 2)))
begin
if(rx)
sample_point_passed <=#Tp 1'b0;
else
sample_point_passed <=#Tp 1'b1;
end
end
wire sample_time =
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
sampled_bit <= 1;
end
else if (clk_en & (quant_cnt == time_segment1))
begin
sampled_bit <=#Tp rx;
end
end
Detect phase error and change the above flip-flop
endmodule | module can_btl
(
clk,
rst,
rx,
reset_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling,
take_sample,
clk_en,
idle,
sync_mode
); |
parameter Tp = 1;
input clk;
input rst;
input rx;
input reset_mode;
input [5:0] baud_r_presc;
input [1:0] sync_jump_width;
input [3:0] time_segment1;
input [2:0] time_segment2;
input triple_sampling;
output take_sample;
output clk_en;
input idle;
input sync_mode;
reg [8:0] clk_cnt;
reg clk_en;
reg hard_sync_blocked;
reg resync_blocked;
reg monitored_bit;
always @ (posedge clk or posedge rst)
begin
if (rst)
monitored_bit <= 1'b0;
else if(clk_en)
monitored_bit <=#Tp rx;
end
reg sampled_bit;
reg [7:0] quant_cnt;
wire [8:0] preset_cnt = (baud_r_presc + 1'b1)<<1;
wire hard_sync = idle & (~monitored_bit) & sampled_bit & (~hard_sync_blocked);
wire resync = (~idle) & (~monitored_bit) & sampled_bit & (~resync_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
clk_cnt <= 0;
clk_en <= 1'b0;
end
else if (clk_cnt == (preset_cnt-1))
begin
clk_cnt <=#Tp 0;
clk_en <=#Tp 1'b1;
end
else
begin
clk_cnt <=#Tp clk_cnt + 1;
clk_en <=#Tp 1'b0;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
quant_cnt <=#Tp 0;
hard_sync_blocked <=#Tp 1'b0;
end
else if (clk_en)
begin
if (hard_sync || (quant_cnt == (time_segment1 + time_segment2 + 2)))
begin
quant_cnt <=#Tp 0;
hard_sync_blocked <=#Tp hard_sync;
end
else
begin
quant_cnt <=#Tp quant_cnt + 1;
end
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
resync_blocked <=#Tp 1'b0;
end
else if (clk_en)
begin
if (resync)
begin
if (quant_cnt == (time_segment1 + time_segment2 + 2))
dodatek = 0;
else if (sample_point_passed)
dodatek = quant_cnt;
else
reseti clock to 0 so we start with new bit sooner
reg sample_point_passed;
always @ (posedge clk)
begin
if (clk_en & (quant_cnt == (time_segment1 + time_segment2 + 2)))
begin
if(rx)
sample_point_passed <=#Tp 1'b0;
else
sample_point_passed <=#Tp 1'b1;
end
end
wire sample_time =
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
sampled_bit <= 1;
end
else if (clk_en & (quant_cnt == time_segment1))
begin
sampled_bit <=#Tp rx;
end
end
Detect phase error and change the above flip-flop
endmodule | 2 |
140,545 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_registers.v | 90,474,316 | can_registers.v | v | 212 | 71 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_registers.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_registers.v:54: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,682 | module | module can_registers
(
clk,
rst,
cs,
rw,
addr,
data_in,
data_out,
reset_mode,
listen_only_mode,
acceptance_filter_mode,
sleep_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling
);
parameter Tp = 1;
input clk;
input rst;
input cs;
input rw;
input [7:0] addr;
input [7:0] data_in;
output [7:0] data_out;
reg [7:0] data_out;
output reset_mode;
output listen_only_mode;
output acceptance_filter_mode;
output sleep_mode;
output [5:0] baud_r_presc;
output [1:0] sync_jump_width;
output [3:0] time_segment1;
output [2:0] time_segment2;
output triple_sampling;
wire we_mode = cs & (~rw) & (addr == 8'h0);
wire we_bus_timing_0 = cs & (~rw) & (addr == 8'h6) & reset_mode;
wire we_bus_timing_1 = cs & (~rw) & (addr == 8'h7) & reset_mode;
wire read = cs & rw;
wire [7:0] mode;
can_register_asyn #(8, 8'h1) MODE_REG
( .data_in(data_in),
.data_out(mode),
.we(we_mode),
.clk(clk),
.rst(rst)
);
assign reset_mode = mode[0];
assign listen_only_mode = mode[1];
assign acceptance_filter_mode = mode[3];
assign sleep_mode = mode[4];
wire [7:0] bus_timing_0;
can_register #(8) BUS_TIMING_0_REG
( .data_in(data_in),
.data_out(bus_timing_0),
.we(we_bus_timing_0),
.clk(clk)
);
assign baud_r_presc = bus_timing_0[5:0];
assign sync_jump_width = bus_timing_0[7:6];
wire [7:0] bus_timing_1;
can_register #(8) BUS_TIMING_1_REG
( .data_in(data_in),
.data_out(bus_timing_1),
.we(we_bus_timing_1),
.clk(clk)
);
assign time_segment1 = bus_timing_1[3:0];
assign time_segment2 = bus_timing_1[6:4];
assign triple_sampling = bus_timing_1[7];
always @ ( addr or read or mode or bus_timing_0 or bus_timing_1
)
begin
if(read)
begin
case(addr)
8'h0 : data_out <= mode;
8'h6 : data_out <= bus_timing_0;
8'h7 : data_out <= bus_timing_1;
default: data_out <= 8'h0;
endcase
end
else
data_out <= 8'h0;
end
endmodule | module can_registers
(
clk,
rst,
cs,
rw,
addr,
data_in,
data_out,
reset_mode,
listen_only_mode,
acceptance_filter_mode,
sleep_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling
); |
parameter Tp = 1;
input clk;
input rst;
input cs;
input rw;
input [7:0] addr;
input [7:0] data_in;
output [7:0] data_out;
reg [7:0] data_out;
output reset_mode;
output listen_only_mode;
output acceptance_filter_mode;
output sleep_mode;
output [5:0] baud_r_presc;
output [1:0] sync_jump_width;
output [3:0] time_segment1;
output [2:0] time_segment2;
output triple_sampling;
wire we_mode = cs & (~rw) & (addr == 8'h0);
wire we_bus_timing_0 = cs & (~rw) & (addr == 8'h6) & reset_mode;
wire we_bus_timing_1 = cs & (~rw) & (addr == 8'h7) & reset_mode;
wire read = cs & rw;
wire [7:0] mode;
can_register_asyn #(8, 8'h1) MODE_REG
( .data_in(data_in),
.data_out(mode),
.we(we_mode),
.clk(clk),
.rst(rst)
);
assign reset_mode = mode[0];
assign listen_only_mode = mode[1];
assign acceptance_filter_mode = mode[3];
assign sleep_mode = mode[4];
wire [7:0] bus_timing_0;
can_register #(8) BUS_TIMING_0_REG
( .data_in(data_in),
.data_out(bus_timing_0),
.we(we_bus_timing_0),
.clk(clk)
);
assign baud_r_presc = bus_timing_0[5:0];
assign sync_jump_width = bus_timing_0[7:6];
wire [7:0] bus_timing_1;
can_register #(8) BUS_TIMING_1_REG
( .data_in(data_in),
.data_out(bus_timing_1),
.we(we_bus_timing_1),
.clk(clk)
);
assign time_segment1 = bus_timing_1[3:0];
assign time_segment2 = bus_timing_1[6:4];
assign triple_sampling = bus_timing_1[7];
always @ ( addr or read or mode or bus_timing_0 or bus_timing_1
)
begin
if(read)
begin
case(addr)
8'h0 : data_out <= mode;
8'h6 : data_out <= bus_timing_0;
8'h7 : data_out <= bus_timing_1;
default: data_out <= 8'h0;
endcase
end
else
data_out <= 8'h0;
end
endmodule | 2 |
140,546 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_top.v | 90,474,316 | can_top.v | v | 182 | 78 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_top.v:52: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/initial/rtl/verilog/can_top.v:54: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,686 | module | module can_top
(
clk,
rst,
data_in,
data_out,
cs, rw, addr,
rx,
idle
);
parameter Tp = 1;
input clk;
input rst;
input [7:0] data_in;
output [7:0] data_out;
input cs, rw;
input [7:0] addr;
input rx;
input idle;
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire sleep_mode;
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
can_registers i_can_registers
(
.clk(clk),
.rst(rst),
.cs(cs),
.rw(rw),
.addr(addr),
.data_in(data_in),
.data_out(data_out),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.sleep_mode(sleep_mode),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling)
);
wire take_sample;
wire clk_en;
wire sync_mode;
can_btl i_can_btl
(
.clk(clk),
.rst(rst),
.rx(rx),
.reset_mode(reset_mode),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.take_sample(take_sample),
.clk_en(clk_en),
.idle(idle),
.sync_mode(sync_mode)
);
can_bsp i_can_bsp
(
.clk(clk),
.rst(rst),
.sync_mode(sync_mode)
);
endmodule | module can_top
(
clk,
rst,
data_in,
data_out,
cs, rw, addr,
rx,
idle
); |
parameter Tp = 1;
input clk;
input rst;
input [7:0] data_in;
output [7:0] data_out;
input cs, rw;
input [7:0] addr;
input rx;
input idle;
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire sleep_mode;
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
can_registers i_can_registers
(
.clk(clk),
.rst(rst),
.cs(cs),
.rw(rw),
.addr(addr),
.data_in(data_in),
.data_out(data_out),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.sleep_mode(sleep_mode),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling)
);
wire take_sample;
wire clk_en;
wire sync_mode;
can_btl i_can_btl
(
.clk(clk),
.rst(rst),
.rx(rx),
.reset_mode(reset_mode),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.take_sample(take_sample),
.clk_en(clk_en),
.idle(idle),
.sync_mode(sync_mode)
);
can_bsp i_can_bsp
(
.clk(clk),
.rst(rst),
.sync_mode(sync_mode)
);
endmodule | 2 |
140,552 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog/can_top.v | 90,474,316 | can_top.v | v | 825 | 145 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog/can_top.v:193: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_15/rtl/verilog/can_top.v:195: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,795 | module | module can_top
(
`ifdef CAN_WISHBONE_IF
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_adr_i,
wb_ack_o,
`else
rst_i,
ale_i,
rd_i,
wr_i,
port_0_io,
cs_can_i,
`endif
clk_i,
rx_i,
tx_o,
tx_oen_o,
irq_on,
clkout_o
`ifdef CAN_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
);
parameter Tp = 1;
`ifdef CAN_WISHBONE_IF
input wb_clk_i;
input wb_rst_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
input [7:0] wb_adr_i;
output wb_ack_o;
reg wb_ack_o;
reg cs_sync1;
reg cs_sync2;
reg cs_sync3;
reg cs_ack1;
reg cs_ack2;
reg cs_ack3;
reg cs_sync_rst1;
reg cs_sync_rst2;
wire cs_can_i;
`else
input rst_i;
input ale_i;
input rd_i;
input wr_i;
inout [7:0] port_0_io;
input cs_can_i;
reg [7:0] addr_latched;
reg wr_i_q;
reg rd_i_q;
`endif
input clk_i;
input rx_i;
output tx_o;
output tx_oen_o;
output irq_on;
output clkout_o;
`ifdef CAN_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
reg data_out_fifo_selected;
wire irq_o;
wire [7:0] data_out_fifo;
wire [7:0] data_out_regs;
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire self_test_mode;
wire release_buffer;
wire tx_request;
wire abort_tx;
wire self_rx_request;
wire single_shot_transmission;
wire tx_state;
wire tx_state_q;
wire read_arbitration_lost_capture_reg;
wire read_error_code_capture_reg;
wire [7:0] error_capture_code;
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
wire [7:0] error_warning_limit;
wire we_rx_err_cnt;
wire we_tx_err_cnt;
wire extended_mode;
wire [7:0] acceptance_code_0;
wire [7:0] acceptance_mask_0;
wire [7:0] acceptance_code_1;
wire [7:0] acceptance_code_2;
wire [7:0] acceptance_code_3;
wire [7:0] acceptance_mask_1;
wire [7:0] acceptance_mask_2;
wire [7:0] acceptance_mask_3;
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
wire cs;
wire sample_point;
wire sampled_bit;
wire sampled_bit_q;
wire tx_point;
wire hard_sync;
wire rx_idle;
wire transmitting;
wire not_first_bit_of_inter;
wire set_reset_mode;
wire node_bus_off;
wire error_status;
wire [7:0] rx_err_cnt;
wire [7:0] tx_err_cnt;
wire rx_err_cnt_dummy;
wire tx_err_cnt_dummy;
wire transmit_status;
wire receive_status;
wire tx_successful;
wire need_to_tx;
wire overrun;
wire info_empty;
wire set_bus_error_irq;
wire set_arbitration_lost_irq;
wire [4:0] arbitration_lost_capture;
wire node_error_passive;
wire node_error_active;
wire [6:0] rx_message_counter;
wire rst;
wire we;
wire [7:0] addr;
wire [7:0] data_in;
reg [7:0] data_out;
reg rx_registered;
can_registers i_can_registers
(
.clk(clk_i),
.rst(rst),
.cs(cs),
.we(we),
.addr(addr),
.data_in(data_in),
.data_out(data_out_regs),
.irq(irq_o),
.sample_point(sample_point),
.transmitting(transmitting),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt(rx_err_cnt),
.tx_err_cnt(tx_err_cnt),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(abort_tx),
.tx_request(tx_request),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.error_warning_limit(error_warning_limit),
.we_rx_err_cnt(we_rx_err_cnt),
.we_tx_err_cnt(we_tx_err_cnt),
.extended_mode(extended_mode),
.clkout(clkout_o),
.acceptance_code_0(acceptance_code_0),
.acceptance_mask_0(acceptance_mask_0),
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12)
);
assign irq_on = ~irq_o;
can_btl i_can_btl
(
.clk(clk_i),
.rst(rst),
.rx(rx_registered),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.rx_idle(rx_idle),
.not_first_bit_of_inter(not_first_bit_of_inter),
.transmitting(transmitting)
);
can_bsp i_can_bsp
(
.clk(clk_i),
.rst(rst),
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.addr(addr),
.data_in(data_in),
.data_out(data_out_fifo),
.fifo_selected(data_out_fifo_selected),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
.release_buffer(release_buffer),
.tx_request(tx_request),
.abort_tx(abort_tx),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
.error_warning_limit(error_warning_limit),
.we_rx_err_cnt(we_rx_err_cnt),
.we_tx_err_cnt(we_tx_err_cnt),
.extended_mode(extended_mode),
.rx_idle(rx_idle),
.transmitting(transmitting),
.go_rx_inter(go_rx_inter),
.not_first_bit_of_inter(not_first_bit_of_inter),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),
.tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
.acceptance_code_0(acceptance_code_0),
.acceptance_mask_0(acceptance_mask_0),
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12),
.tx(tx_o),
.tx_oen(tx_oen_o)
`ifdef CAN_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
always @ (extended_mode or addr or reset_mode)
begin
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
data_out_fifo_selected = 1'b1;
else
data_out_fifo_selected = 1'b0;
end
always @ (posedge clk_i)
begin
if (cs & (~we))
begin
if (data_out_fifo_selected)
data_out <=#Tp data_out_fifo;
else
data_out <=#Tp data_out_regs;
end
end
always @ (posedge clk_i or posedge rst)
begin
if (rst)
rx_registered <= 1'b1;
else
rx_registered <=#Tp rx_i;
end
`ifdef CAN_WISHBONE_IF
assign cs_can_i = 1'b1;
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
cs_sync1 <= 1'b0;
cs_sync2 <= 1'b0;
cs_sync3 <= 1'b0;
cs_sync_rst1 <= 1'b0;
cs_sync_rst2 <= 1'b0;
end
else
begin
cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
cs_sync_rst1 <=#Tp cs_ack3;
cs_sync_rst2 <=#Tp cs_sync_rst1;
end
end
assign cs = cs_sync2 & (~cs_sync3);
always @ (posedge wb_clk_i)
begin
cs_ack1 <=#Tp cs_sync3;
cs_ack2 <=#Tp cs_ack1;
cs_ack3 <=#Tp cs_ack2;
end
always @ (posedge wb_clk_i)
begin
wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
end
assign rst = wb_rst_i;
assign we = wb_we_i;
assign addr = wb_adr_i;
assign data_in = wb_dat_i;
assign wb_dat_o = data_out;
`else
always @ (negedge clk_i or posedge rst)
begin
if (rst)
addr_latched <= 8'h0;
else if (ale_i)
addr_latched <=#Tp port_0_io;
end
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
wr_i_q <= 1'b0;
rd_i_q <= 1'b0;
end
else
begin
wr_i_q <=#Tp wr_i;
rd_i_q <=#Tp rd_i;
end
end
assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
assign rst = rst_i;
assign we = wr_i;
assign addr = addr_latched;
assign data_in = port_0_io;
assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;
`endif
endmodule | module can_top
(
`ifdef CAN_WISHBONE_IF
wb_clk_i,
wb_rst_i,
wb_dat_i,
wb_dat_o,
wb_cyc_i,
wb_stb_i,
wb_we_i,
wb_adr_i,
wb_ack_o,
`else
rst_i,
ale_i,
rd_i,
wr_i,
port_0_io,
cs_can_i,
`endif
clk_i,
rx_i,
tx_o,
tx_oen_o,
irq_on,
clkout_o
`ifdef CAN_BIST
,
scanb_rst,
scanb_clk,
scanb_si,
scanb_so,
scanb_en
`endif
); |
parameter Tp = 1;
`ifdef CAN_WISHBONE_IF
input wb_clk_i;
input wb_rst_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
input [7:0] wb_adr_i;
output wb_ack_o;
reg wb_ack_o;
reg cs_sync1;
reg cs_sync2;
reg cs_sync3;
reg cs_ack1;
reg cs_ack2;
reg cs_ack3;
reg cs_sync_rst1;
reg cs_sync_rst2;
wire cs_can_i;
`else
input rst_i;
input ale_i;
input rd_i;
input wr_i;
inout [7:0] port_0_io;
input cs_can_i;
reg [7:0] addr_latched;
reg wr_i_q;
reg rd_i_q;
`endif
input clk_i;
input rx_i;
output tx_o;
output tx_oen_o;
output irq_on;
output clkout_o;
`ifdef CAN_BIST
input scanb_rst;
input scanb_clk;
input scanb_si;
output scanb_so;
input scanb_en;
`endif
reg data_out_fifo_selected;
wire irq_o;
wire [7:0] data_out_fifo;
wire [7:0] data_out_regs;
wire reset_mode;
wire listen_only_mode;
wire acceptance_filter_mode;
wire self_test_mode;
wire release_buffer;
wire tx_request;
wire abort_tx;
wire self_rx_request;
wire single_shot_transmission;
wire tx_state;
wire tx_state_q;
wire read_arbitration_lost_capture_reg;
wire read_error_code_capture_reg;
wire [7:0] error_capture_code;
wire [5:0] baud_r_presc;
wire [1:0] sync_jump_width;
wire [3:0] time_segment1;
wire [2:0] time_segment2;
wire triple_sampling;
wire [7:0] error_warning_limit;
wire we_rx_err_cnt;
wire we_tx_err_cnt;
wire extended_mode;
wire [7:0] acceptance_code_0;
wire [7:0] acceptance_mask_0;
wire [7:0] acceptance_code_1;
wire [7:0] acceptance_code_2;
wire [7:0] acceptance_code_3;
wire [7:0] acceptance_mask_1;
wire [7:0] acceptance_mask_2;
wire [7:0] acceptance_mask_3;
wire [7:0] tx_data_0;
wire [7:0] tx_data_1;
wire [7:0] tx_data_2;
wire [7:0] tx_data_3;
wire [7:0] tx_data_4;
wire [7:0] tx_data_5;
wire [7:0] tx_data_6;
wire [7:0] tx_data_7;
wire [7:0] tx_data_8;
wire [7:0] tx_data_9;
wire [7:0] tx_data_10;
wire [7:0] tx_data_11;
wire [7:0] tx_data_12;
wire cs;
wire sample_point;
wire sampled_bit;
wire sampled_bit_q;
wire tx_point;
wire hard_sync;
wire rx_idle;
wire transmitting;
wire not_first_bit_of_inter;
wire set_reset_mode;
wire node_bus_off;
wire error_status;
wire [7:0] rx_err_cnt;
wire [7:0] tx_err_cnt;
wire rx_err_cnt_dummy;
wire tx_err_cnt_dummy;
wire transmit_status;
wire receive_status;
wire tx_successful;
wire need_to_tx;
wire overrun;
wire info_empty;
wire set_bus_error_irq;
wire set_arbitration_lost_irq;
wire [4:0] arbitration_lost_capture;
wire node_error_passive;
wire node_error_active;
wire [6:0] rx_message_counter;
wire rst;
wire we;
wire [7:0] addr;
wire [7:0] data_in;
reg [7:0] data_out;
reg rx_registered;
can_registers i_can_registers
(
.clk(clk_i),
.rst(rst),
.cs(cs),
.we(we),
.addr(addr),
.data_in(data_in),
.data_out(data_out_regs),
.irq(irq_o),
.sample_point(sample_point),
.transmitting(transmitting),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt(rx_err_cnt),
.tx_err_cnt(tx_err_cnt),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
.clear_data_overrun(),
.release_buffer(release_buffer),
.abort_tx(abort_tx),
.tx_request(tx_request),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.error_warning_limit(error_warning_limit),
.we_rx_err_cnt(we_rx_err_cnt),
.we_tx_err_cnt(we_tx_err_cnt),
.extended_mode(extended_mode),
.clkout(clkout_o),
.acceptance_code_0(acceptance_code_0),
.acceptance_mask_0(acceptance_mask_0),
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12)
);
assign irq_on = ~irq_o;
can_btl i_can_btl
(
.clk(clk_i),
.rst(rst),
.rx(rx_registered),
.baud_r_presc(baud_r_presc),
.sync_jump_width(sync_jump_width),
.time_segment1(time_segment1),
.time_segment2(time_segment2),
.triple_sampling(triple_sampling),
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.rx_idle(rx_idle),
.not_first_bit_of_inter(not_first_bit_of_inter),
.transmitting(transmitting)
);
can_bsp i_can_bsp
(
.clk(clk_i),
.rst(rst),
.sample_point(sample_point),
.sampled_bit(sampled_bit),
.sampled_bit_q(sampled_bit_q),
.tx_point(tx_point),
.hard_sync(hard_sync),
.addr(addr),
.data_in(data_in),
.data_out(data_out_fifo),
.fifo_selected(data_out_fifo_selected),
.reset_mode(reset_mode),
.listen_only_mode(listen_only_mode),
.acceptance_filter_mode(acceptance_filter_mode),
.self_test_mode(self_test_mode),
.release_buffer(release_buffer),
.tx_request(tx_request),
.abort_tx(abort_tx),
.self_rx_request(self_rx_request),
.single_shot_transmission(single_shot_transmission),
.tx_state(tx_state),
.tx_state_q(tx_state_q),
.read_arbitration_lost_capture_reg(read_arbitration_lost_capture_reg),
.read_error_code_capture_reg(read_error_code_capture_reg),
.error_capture_code(error_capture_code),
.error_warning_limit(error_warning_limit),
.we_rx_err_cnt(we_rx_err_cnt),
.we_tx_err_cnt(we_tx_err_cnt),
.extended_mode(extended_mode),
.rx_idle(rx_idle),
.transmitting(transmitting),
.go_rx_inter(go_rx_inter),
.not_first_bit_of_inter(not_first_bit_of_inter),
.set_reset_mode(set_reset_mode),
.node_bus_off(node_bus_off),
.error_status(error_status),
.rx_err_cnt({rx_err_cnt_dummy, rx_err_cnt[7:0]}),
.tx_err_cnt({tx_err_cnt_dummy, tx_err_cnt[7:0]}),
.transmit_status(transmit_status),
.receive_status(receive_status),
.tx_successful(tx_successful),
.need_to_tx(need_to_tx),
.overrun(overrun),
.info_empty(info_empty),
.set_bus_error_irq(set_bus_error_irq),
.set_arbitration_lost_irq(set_arbitration_lost_irq),
.arbitration_lost_capture(arbitration_lost_capture),
.node_error_passive(node_error_passive),
.node_error_active(node_error_active),
.rx_message_counter(rx_message_counter),
.acceptance_code_0(acceptance_code_0),
.acceptance_mask_0(acceptance_mask_0),
.acceptance_code_1(acceptance_code_1),
.acceptance_code_2(acceptance_code_2),
.acceptance_code_3(acceptance_code_3),
.acceptance_mask_1(acceptance_mask_1),
.acceptance_mask_2(acceptance_mask_2),
.acceptance_mask_3(acceptance_mask_3),
.tx_data_0(tx_data_0),
.tx_data_1(tx_data_1),
.tx_data_2(tx_data_2),
.tx_data_3(tx_data_3),
.tx_data_4(tx_data_4),
.tx_data_5(tx_data_5),
.tx_data_6(tx_data_6),
.tx_data_7(tx_data_7),
.tx_data_8(tx_data_8),
.tx_data_9(tx_data_9),
.tx_data_10(tx_data_10),
.tx_data_11(tx_data_11),
.tx_data_12(tx_data_12),
.tx(tx_o),
.tx_oen(tx_oen_o)
`ifdef CAN_BIST
,
.scanb_rst(scanb_rst),
.scanb_clk(scanb_clk),
.scanb_si(scanb_si),
.scanb_so(scanb_so),
.scanb_en(scanb_en)
`endif
);
always @ (extended_mode or addr or reset_mode)
begin
if (extended_mode & (~reset_mode) & ((addr >= 8'd16) && (addr <= 8'd28)) | (~extended_mode) & ((addr >= 8'd20) && (addr <= 8'd29)))
data_out_fifo_selected = 1'b1;
else
data_out_fifo_selected = 1'b0;
end
always @ (posedge clk_i)
begin
if (cs & (~we))
begin
if (data_out_fifo_selected)
data_out <=#Tp data_out_fifo;
else
data_out <=#Tp data_out_regs;
end
end
always @ (posedge clk_i or posedge rst)
begin
if (rst)
rx_registered <= 1'b1;
else
rx_registered <=#Tp rx_i;
end
`ifdef CAN_WISHBONE_IF
assign cs_can_i = 1'b1;
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
cs_sync1 <= 1'b0;
cs_sync2 <= 1'b0;
cs_sync3 <= 1'b0;
cs_sync_rst1 <= 1'b0;
cs_sync_rst2 <= 1'b0;
end
else
begin
cs_sync1 <=#Tp wb_cyc_i & wb_stb_i & (~cs_sync_rst2) & cs_can_i;
cs_sync2 <=#Tp cs_sync1 & (~cs_sync_rst2);
cs_sync3 <=#Tp cs_sync2 & (~cs_sync_rst2);
cs_sync_rst1 <=#Tp cs_ack3;
cs_sync_rst2 <=#Tp cs_sync_rst1;
end
end
assign cs = cs_sync2 & (~cs_sync3);
always @ (posedge wb_clk_i)
begin
cs_ack1 <=#Tp cs_sync3;
cs_ack2 <=#Tp cs_ack1;
cs_ack3 <=#Tp cs_ack2;
end
always @ (posedge wb_clk_i)
begin
wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));
end
assign rst = wb_rst_i;
assign we = wb_we_i;
assign addr = wb_adr_i;
assign data_in = wb_dat_i;
assign wb_dat_o = data_out;
`else
always @ (negedge clk_i or posedge rst)
begin
if (rst)
addr_latched <= 8'h0;
else if (ale_i)
addr_latched <=#Tp port_0_io;
end
always @ (posedge clk_i or posedge rst)
begin
if (rst)
begin
wr_i_q <= 1'b0;
rd_i_q <= 1'b0;
end
else
begin
wr_i_q <=#Tp wr_i;
rd_i_q <=#Tp rd_i;
end
end
assign cs = ((wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q))) & cs_can_i;
assign rst = rst_i;
assign we = wr_i;
assign addr = addr_latched;
assign data_in = port_0_io;
assign port_0_io = (cs_can_i & rd_i)? data_out : 8'hz;
`endif
endmodule | 2 |
140,554 | data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog/can_btl.v | 90,474,316 | can_btl.v | v | 421 | 137 | [] | ['general public license', 'free software foundation'] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog/can_btl.v:118: Cannot find include file: timescale.v\n`include "timescale.v" \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog,data/full_repos/permissive/90474316/timescale.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.v\n data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog,data/full_repos/permissive/90474316/timescale.v.sv\n timescale.v\n timescale.v.v\n timescale.v.sv\n obj_dir/timescale.v\n obj_dir/timescale.v.v\n obj_dir/timescale.v.sv\n%Error: data/full_repos/permissive/90474316/fpga-rtl/can/tags/rel_5/rtl/verilog/can_btl.v:120: Cannot find include file: can_defines.v\n`include "can_defines.v" \n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n' | 308,981 | module | module can_btl
(
clk,
rst,
rx,
reset_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling,
sample_point,
sampled_bit,
sampled_bit_q,
tx_point,
hard_sync,
rx_idle,
last_bit_of_inter
);
parameter Tp = 1;
input clk;
input rst;
input rx;
input reset_mode;
input [5:0] baud_r_presc;
input [1:0] sync_jump_width;
input [3:0] time_segment1;
input [2:0] time_segment2;
input triple_sampling;
input rx_idle;
input last_bit_of_inter;
output sample_point;
output sampled_bit;
output sampled_bit_q;
output tx_point;
output hard_sync;
reg [6:0] clk_cnt;
reg clk_en;
reg clk_en_q;
reg sync_blocked;
reg resync_blocked;
reg sampled_bit;
reg sampled_bit_q;
reg [4:0] quant_cnt;
reg [3:0] delay;
reg sync;
reg seg1;
reg seg2;
reg resync_latched;
reg sample_point;
reg [1:0] sample;
reg go_sync;
wire go_sync_unregistered;
wire go_seg1;
wire go_seg2;
wire [8:0] preset_cnt;
wire sync_window;
wire resync;
wire quant_cnt_rst;
assign preset_cnt = (baud_r_presc + 1'b1)<<1;
assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked);
assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_cnt <= 0;
else if (clk_cnt >= (preset_cnt-1'b1))
clk_cnt <=#Tp 0;
else
clk_cnt <=#Tp clk_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en <= 1'b0;
else if (clk_cnt == (preset_cnt-1'b1))
clk_en <=#Tp 1'b1;
else
clk_en <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en_q <= 1'b0;
else
clk_en_q <=#Tp clk_en;
end
assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
assign go_seg1 = clk_en_q & ((sync & (~seg1)) | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
always @ (posedge clk or posedge rst)
begin
if (rst)
go_sync <= 1'b0;
else
go_sync <=#Tp go_sync_unregistered;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
resync_latched <= 1'b0;
else if (resync & seg2 & (~sync_window))
resync_latched <=#Tp 1'b1;
else if (go_seg1)
resync_latched <= 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
sync <= 0;
else if (go_sync)
sync <=#Tp 1'b1;
else if (clk_en_q)
sync <=#Tp 1'b0;
end
assign tx_point = go_sync;
always @ (posedge clk or posedge rst)
begin
if (rst)
seg1 <= 1;
else if (go_seg1)
seg1 <=#Tp 1'b1;
else if (go_seg2)
seg1 <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
seg2 <= 0;
else if (go_seg2)
seg2 <=#Tp 1'b1;
else if (go_sync | go_seg1)
seg2 <=#Tp 1'b0;
end
assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
always @ (posedge clk or posedge rst)
begin
if (rst)
quant_cnt <= 0;
else if (quant_cnt_rst)
quant_cnt <=#Tp 0;
else if (clk_en_q)
quant_cnt <=#Tp quant_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
delay <= 0;
else if (clk_en_q & resync & seg1)
delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
else if (go_sync | go_seg1)
delay <=#Tp 0;
end
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
always @ (posedge clk or posedge rst)
begin
if (rst)
sample <= 2'b11;
else if (clk_en_q)
sample <= {sample[0], rx};
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
sampled_bit <= 1;
sampled_bit_q <= 1;
sample_point <= 0;
end
else if (clk_en_q & (~hard_sync))
begin
if (seg1 & (quant_cnt == (time_segment1 + delay)))
begin
sample_point <=#Tp 1;
sampled_bit_q <=#Tp sampled_bit;
if (triple_sampling)
sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
else
sampled_bit <=#Tp rx;
end
end
else
sample_point <=#Tp 0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
sync_blocked <=#Tp 1'b0;
else if (clk_en_q)
begin
if (hard_sync | resync)
sync_blocked <=#Tp 1'b1;
else if (seg2 & (quant_cnt[2:0] == time_segment2))
sync_blocked <=#Tp 1'b0;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
resync_blocked <=#Tp 1'b1;
else if (reset_mode)
resync_blocked <=#Tp 1'b1;
else if (hard_sync)
resync_blocked <=#Tp 1'b0;
end
endmodule | module can_btl
(
clk,
rst,
rx,
reset_mode,
baud_r_presc,
sync_jump_width,
time_segment1,
time_segment2,
triple_sampling,
sample_point,
sampled_bit,
sampled_bit_q,
tx_point,
hard_sync,
rx_idle,
last_bit_of_inter
); |
parameter Tp = 1;
input clk;
input rst;
input rx;
input reset_mode;
input [5:0] baud_r_presc;
input [1:0] sync_jump_width;
input [3:0] time_segment1;
input [2:0] time_segment2;
input triple_sampling;
input rx_idle;
input last_bit_of_inter;
output sample_point;
output sampled_bit;
output sampled_bit_q;
output tx_point;
output hard_sync;
reg [6:0] clk_cnt;
reg clk_en;
reg clk_en_q;
reg sync_blocked;
reg resync_blocked;
reg sampled_bit;
reg sampled_bit_q;
reg [4:0] quant_cnt;
reg [3:0] delay;
reg sync;
reg seg1;
reg seg2;
reg resync_latched;
reg sample_point;
reg [1:0] sample;
reg go_sync;
wire go_sync_unregistered;
wire go_seg1;
wire go_seg2;
wire [8:0] preset_cnt;
wire sync_window;
wire resync;
wire quant_cnt_rst;
assign preset_cnt = (baud_r_presc + 1'b1)<<1;
assign hard_sync = (rx_idle | last_bit_of_inter) & (~rx) & sampled_bit & (~sync_blocked);
assign resync = (~rx_idle) & (~rx) & sampled_bit & (~sync_blocked) & (~resync_blocked);
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_cnt <= 0;
else if (clk_cnt >= (preset_cnt-1'b1))
clk_cnt <=#Tp 0;
else
clk_cnt <=#Tp clk_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en <= 1'b0;
else if (clk_cnt == (preset_cnt-1'b1))
clk_en <=#Tp 1'b1;
else
clk_en <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
clk_en_q <= 1'b0;
else
clk_en_q <=#Tp clk_en;
end
assign go_sync_unregistered = clk_en & (seg2 & (~hard_sync) & (~resync) & ((quant_cnt[2:0] == time_segment2)));
assign go_seg1 = clk_en_q & ((sync & (~seg1)) | hard_sync | (resync & seg2 & sync_window) | (resync_latched & sync_window));
assign go_seg2 = clk_en_q & (seg1 & (~hard_sync) & (quant_cnt == (time_segment1 + delay)));
always @ (posedge clk or posedge rst)
begin
if (rst)
go_sync <= 1'b0;
else
go_sync <=#Tp go_sync_unregistered;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
resync_latched <= 1'b0;
else if (resync & seg2 & (~sync_window))
resync_latched <=#Tp 1'b1;
else if (go_seg1)
resync_latched <= 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
sync <= 0;
else if (go_sync)
sync <=#Tp 1'b1;
else if (clk_en_q)
sync <=#Tp 1'b0;
end
assign tx_point = go_sync;
always @ (posedge clk or posedge rst)
begin
if (rst)
seg1 <= 1;
else if (go_seg1)
seg1 <=#Tp 1'b1;
else if (go_seg2)
seg1 <=#Tp 1'b0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
seg2 <= 0;
else if (go_seg2)
seg2 <=#Tp 1'b1;
else if (go_sync | go_seg1)
seg2 <=#Tp 1'b0;
end
assign quant_cnt_rst = go_sync | go_seg1 | go_seg2;
always @ (posedge clk or posedge rst)
begin
if (rst)
quant_cnt <= 0;
else if (quant_cnt_rst)
quant_cnt <=#Tp 0;
else if (clk_en_q)
quant_cnt <=#Tp quant_cnt + 1'b1;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
delay <= 0;
else if (clk_en_q & resync & seg1)
delay <=#Tp (quant_cnt > {3'h0, sync_jump_width})? (sync_jump_width + 1'b1) : (quant_cnt + 1'b1);
else if (go_sync | go_seg1)
delay <=#Tp 0;
end
assign sync_window = ((time_segment2 - quant_cnt[2:0]) < ( sync_jump_width + 1'b1));
always @ (posedge clk or posedge rst)
begin
if (rst)
sample <= 2'b11;
else if (clk_en_q)
sample <= {sample[0], rx};
end
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
sampled_bit <= 1;
sampled_bit_q <= 1;
sample_point <= 0;
end
else if (clk_en_q & (~hard_sync))
begin
if (seg1 & (quant_cnt == (time_segment1 + delay)))
begin
sample_point <=#Tp 1;
sampled_bit_q <=#Tp sampled_bit;
if (triple_sampling)
sampled_bit <=#Tp (sample[0] & sample[1]) | ( sample[0] & rx) | (sample[1] & rx);
else
sampled_bit <=#Tp rx;
end
end
else
sample_point <=#Tp 0;
end
always @ (posedge clk or posedge rst)
begin
if (rst)
sync_blocked <=#Tp 1'b0;
else if (clk_en_q)
begin
if (hard_sync | resync)
sync_blocked <=#Tp 1'b1;
else if (seg2 & (quant_cnt[2:0] == time_segment2))
sync_blocked <=#Tp 1'b0;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst)
resync_blocked <=#Tp 1'b1;
else if (reset_mode)
resync_blocked <=#Tp 1'b1;
else if (hard_sync)
resync_blocked <=#Tp 1'b0;
end
endmodule | 2 |
140,555 | data/full_repos/permissive/90508365/alu.v | 90,508,365 | alu.v | v | 40 | 66 | [] | [] | [] | [(1, 39)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90508365/alu.v:27: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'sr1\' generates 16 bits.\n : ... In instance alu\n q <= (sr1) ? pc : imm + pc;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90508365/alu.v:35: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS\'s VARREF \'sr1\' generates 16 bits.\n : ... In instance alu\n q <= (!sr1) ? pc : imm + pc; \n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,300 | module | module alu (
output reg [15:0] q,
input [15:0] sr1,
input [15:0] sr2,
input [15:0] pc,
input [15:0] ir,
input CLK,
input RSTN
);
wire [15:0] imm = {{8{ir[7]}},ir[7:0]};
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
casex (ir)
16'b11_xxx_xxx_xxxxxxxx:
q <= sr1 + imm;
16'b00_xxx_xxx_xxx_00100:
q <= (sr1>sr2) ? 16'b1111111111111111 : 16'b0000000000000000;
16'b00_xxx_xxx_xxx_00101:
q <= sr1 * sr2;
16'b10_010_xxx_xxxxxxxx:
q <= (sr1) ? pc : imm + pc;
16'b00_xxx_xxx_xxx_00010:
q <= sr1 + sr2;
16'b01_xxx_000_xxxxxxxx:
q <= imm;
16'b10_000_000_xxxxxxxx:
q <= pc + imm;
16'b10_001_xxx_xxxxxxxx:
q <= (!sr1) ? pc : imm + pc;
endcase
end
end
endmodule | module alu (
output reg [15:0] q,
input [15:0] sr1,
input [15:0] sr2,
input [15:0] pc,
input [15:0] ir,
input CLK,
input RSTN
); |
wire [15:0] imm = {{8{ir[7]}},ir[7:0]};
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
casex (ir)
16'b11_xxx_xxx_xxxxxxxx:
q <= sr1 + imm;
16'b00_xxx_xxx_xxx_00100:
q <= (sr1>sr2) ? 16'b1111111111111111 : 16'b0000000000000000;
16'b00_xxx_xxx_xxx_00101:
q <= sr1 * sr2;
16'b10_010_xxx_xxxxxxxx:
q <= (sr1) ? pc : imm + pc;
16'b00_xxx_xxx_xxx_00010:
q <= sr1 + sr2;
16'b01_xxx_000_xxxxxxxx:
q <= imm;
16'b10_000_000_xxxxxxxx:
q <= pc + imm;
16'b10_001_xxx_xxxxxxxx:
q <= (!sr1) ? pc : imm + pc;
endcase
end
end
endmodule | 0 |
140,556 | data/full_repos/permissive/90508365/alu_tb.v | 90,508,365 | alu_tb.v | v | 40 | 87 | [] | [] | [] | null | line:38: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:31: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/alu_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: data/full_repos/permissive/90508365/alu_tb.v:6: Cannot find file containing module: \'alu\'\n alu alu (.q(w_alu), .sr1(sr1), .sr2(sr2), .pc(pc), .ir(ir), .CLK(CLK), .RSTN(RSTN));\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/alu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/alu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,301 | module | module alu_tb;
wire [15:0] w_alu;
reg [15:0] sr1, sr2, pc, ir;
reg CLK, RSTN;
alu alu (.q(w_alu), .sr1(sr1), .sr2(sr2), .pc(pc), .ir(ir), .CLK(CLK), .RSTN(RSTN));
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
RSTN = 0;
pc = 8;
#20
RSTN = 1;
ir = 16'b01_110_000_00000001;
sr1 = 0; sr2 = 0;
#20
ir = 16'b01_101_000_11111111;
sr1 = 0; sr2 = 7;
#20
ir = 16'b00_100_010_011_00010;
sr1 = 2; sr2 = 3;
#20
ir = 16'b10_001_000_00000100;
sr1 = 0; sr2 = 0;
#20
ir = 16'b10_001_001_11111101;
sr1 = 1; sr2 = 7;
#20
ir = 16'b10_000_000_11111010;
sr1 = 0; sr2 = 7;
#20
$finish;
end
endmodule | module alu_tb; |
wire [15:0] w_alu;
reg [15:0] sr1, sr2, pc, ir;
reg CLK, RSTN;
alu alu (.q(w_alu), .sr1(sr1), .sr2(sr2), .pc(pc), .ir(ir), .CLK(CLK), .RSTN(RSTN));
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
RSTN = 0;
pc = 8;
#20
RSTN = 1;
ir = 16'b01_110_000_00000001;
sr1 = 0; sr2 = 0;
#20
ir = 16'b01_101_000_11111111;
sr1 = 0; sr2 = 7;
#20
ir = 16'b00_100_010_011_00010;
sr1 = 2; sr2 = 3;
#20
ir = 16'b10_001_000_00000100;
sr1 = 0; sr2 = 0;
#20
ir = 16'b10_001_001_11111101;
sr1 = 1; sr2 = 7;
#20
ir = 16'b10_000_000_11111010;
sr1 = 0; sr2 = 7;
#20
$finish;
end
endmodule | 0 |
140,557 | data/full_repos/permissive/90508365/count16rle_tb.v | 90,508,365 | count16rle_tb.v | v | 51 | 88 | [] | [] | [] | null | line:20: before: "while" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:35: Unsupported: Ignoring delay on this delayed statement.\n #160;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #320\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/count16rle_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #700\n ^\n%Error: data/full_repos/permissive/90508365/count16rle_tb.v:48: Cannot find file containing module: \'count16rle\'\n count16rle count16rle (.q(q), .d(d), .load(load), .inc(inc), .CLK(CLK), .RSTN(RSTN));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/count16rle\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/count16rle.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/count16rle.sv\n count16rle\n count16rle.v\n count16rle.sv\n obj_dir/count16rle\n obj_dir/count16rle.v\n obj_dir/count16rle.sv\n%Error: Exiting due to 1 error(s), 9 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,303 | module | module count16rle_tb;
wire [15:0] q;
reg [15:0] d;
reg load;
reg inc;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
inc = 0;
#40
while (1) begin
inc = 1;
#20
inc = 0;
#40;
end
end
initial begin
load = 0;
#320
while (1) begin
load = 1;
#20
load = 0;
#160;
end
end
initial begin
RSTN = 0;
d = 16'h0003;
#20
RSTN = 1;
#700
$finish;
end
count16rle count16rle (.q(q), .d(d), .load(load), .inc(inc), .CLK(CLK), .RSTN(RSTN));
endmodule | module count16rle_tb; |
wire [15:0] q;
reg [15:0] d;
reg load;
reg inc;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
inc = 0;
#40
while (1) begin
inc = 1;
#20
inc = 0;
#40;
end
end
initial begin
load = 0;
#320
while (1) begin
load = 1;
#20
load = 0;
#160;
end
end
initial begin
RSTN = 0;
d = 16'h0003;
#20
RSTN = 1;
#700
$finish;
end
count16rle count16rle (.q(q), .d(d), .load(load), .inc(inc), .CLK(CLK), .RSTN(RSTN));
endmodule | 0 |
140,558 | data/full_repos/permissive/90508365/cpu.v | 90,508,365 | cpu.v | v | 559 | 95 | [] | [] | [] | [(1, 558)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cpu.v:172: Cannot find file containing module: 'imem'\n imem imem ( \n ^~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem.sv\n imem\n imem.v\n imem.sv\n obj_dir/imem\n obj_dir/imem.v\n obj_dir/imem.sv\n%Error: data/full_repos/permissive/90508365/cpu.v:178: Cannot find file containing module: 'dmem'\n dmem dmem ( \n ^~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:186: Cannot find file containing module: 'sm'\n sm sm0 (\n ^~\n%Error: data/full_repos/permissive/90508365/cpu.v:195: Cannot find file containing module: 'sm'\n sm sm1 (\n ^~\n%Error: data/full_repos/permissive/90508365/cpu.v:204: Cannot find file containing module: 'sm'\n sm sm2 (\n ^~\n%Error: data/full_repos/permissive/90508365/cpu.v:213: Cannot find file containing module: 'sm'\n sm sm3 (\n ^~\n%Error: data/full_repos/permissive/90508365/cpu.v:222: Cannot find file containing module: 'count16rle'\n count16rle pc0 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:232: Cannot find file containing module: 'count16rle'\n count16rle pc1 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:242: Cannot find file containing module: 'count16rle'\n count16rle pc2 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:252: Cannot find file containing module: 'count16rle'\n count16rle pc3 (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:262: Cannot find file containing module: 'reg16'\n reg16 ir0 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:270: Cannot find file containing module: 'reg16'\n reg16 ir1 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:278: Cannot find file containing module: 'reg16'\n reg16 ir2 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:286: Cannot find file containing module: 'reg16'\n reg16 ir3 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:294: Cannot find file containing module: 'regfile'\n regfile regfile0 (\n ^~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:310: Cannot find file containing module: 'regfile'\n regfile regfile1 (\n ^~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:326: Cannot find file containing module: 'regfile'\n regfile regfile2 (\n ^~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:342: Cannot find file containing module: 'regfile'\n regfile regfile3 (\n ^~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:358: Cannot find file containing module: 'muxreg16'\n muxreg16 sr1_0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:374: Cannot find file containing module: 'muxreg16'\n muxreg16 sr1_1 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:390: Cannot find file containing module: 'muxreg16'\n muxreg16 sr1_2 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:406: Cannot find file containing module: 'muxreg16'\n muxreg16 sr1_3 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:422: Cannot find file containing module: 'muxreg16'\n muxreg16 sr2_0 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:438: Cannot find file containing module: 'muxreg16'\n muxreg16 sr2_1 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:454: Cannot find file containing module: 'muxreg16'\n muxreg16 sr2_2 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:470: Cannot find file containing module: 'muxreg16'\n muxreg16 sr2_3 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:486: Cannot find file containing module: 'alu'\n alu alu0 (\n ^~~\n%Error: data/full_repos/permissive/90508365/cpu.v:496: Cannot find file containing module: 'alu'\n alu alu1 (\n ^~~\n%Error: data/full_repos/permissive/90508365/cpu.v:506: Cannot find file containing module: 'alu'\n alu alu2 (\n ^~~\n%Error: data/full_repos/permissive/90508365/cpu.v:516: Cannot find file containing module: 'alu'\n alu alu3 (\n ^~~\n%Error: data/full_repos/permissive/90508365/cpu.v:526: Cannot find file containing module: 'reg16'\n reg16 dr0 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:534: Cannot find file containing module: 'reg16'\n reg16 dr1 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:542: Cannot find file containing module: 'reg16'\n reg16 dr2 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508365/cpu.v:550: Cannot find file containing module: 'reg16'\n reg16 dr3 ( \n ^~~~~\n%Error: Exiting due to 34 error(s)\n" | 309,304 | module | module cpu (
output [7:0] led,
output [15:0] seg0,
output [15:0] seg1,
output [15:0] seg2,
output [15:0] seg3,
output [15:0] seg4,
output [15:0] seg5,
output [15:0] seg6,
output [15:0] seg7,
output [15:0] seg8,
output [15:0] seg9,
output [15:0] sega,
output [15:0] segb,
output [15:0] segc,
output [15:0] segd,
output [15:0] sege,
output [15:0] segf,
input start,
input stop,
input CLK,
input RSTN
);
wire [3:0] ph0;
wire [15:0] w_imem0;
wire [15:0] w_dmem0;
wire [15:0] w_pc0, w_ir0, w_sr1_0, w_sr2_0, w_alu0, w_dr0;
wire [15:0] r0_0, r1_0, r2_0, r3_0, r4_0, r5_0, r6_0, r7_0;
wire write_dr0, write_dmem0, write_pc0, write_reg0;
wire [15:0] w_d0;
wire [3:0] ph1;
wire [15:0] w_imem1;
wire [15:0] w_dmem1;
wire [15:0] w_pc1, w_ir1, w_sr1_1, w_sr2_1, w_alu1, w_dr1;
wire [15:0] r0_1, r1_1, r2_1, r3_1, r4_1, r5_1, r6_1, r7_1;
wire write_dr1, write_dmem1, write_pc1, write_reg1;
wire [15:0] w_d1;
wire [3:0] ph2;
wire [15:0] w_imem2;
wire [15:0] w_dmem2;
wire [15:0] w_pc2, w_ir2, w_sr1_2, w_sr2_2, w_alu2, w_dr2;
wire [15:0] r0_2, r1_2, r2_2, r3_2, r4_2, r5_2, r6_2, r7_2;
wire write_dr2, write_dmem2, write_pc2, write_reg2;
wire [15:0] w_d2;
wire [3:0] ph3;
wire [15:0] w_imem3;
wire [15:0] w_dmem3;
wire [15:0] w_pc3, w_ir3, w_sr1_3, w_sr2_3, w_alu3, w_dr3;
wire [15:0] r0_3, r1_3, r2_3, r3_3, r4_3, r5_3, r6_3, r7_3;
wire write_dr3, write_dmem3, write_pc3, write_reg3;
wire [15:0] w_d3;
assign led = {4'b0000, ph3[3:0]};
assign seg0 = r0_3;
assign seg1 = r1_3;
assign seg2 = r2_3;
assign seg3 = r3_3;
assign seg4 = r4_3;
assign seg5 = r5_3;
assign seg6 = r6_3;
assign seg7 = r7_3;
assign seg8 = w_pc3;
assign seg9 = w_ir3;
assign sega = w_sr1_3;
assign segb = w_sr2_3;
assign segc = w_alu3;
assign segd = w_d3;
assign sege = 16'h0000;
assign segf = 16'h0000;
assign write_dr0 = ph0[2] &&
(w_ir0[15:14]==2'b00) && (w_ir0[7:0]==8'b00000001);
assign write_dmem0 = ph0[2] &&
(w_ir0[15:11]==5'b00000) && (w_ir0[4:0]==5'b00000);
assign write_pc0 = ph0[3] &&
((w_ir0[15:8]==8'b10000000)
|| (w_ir0[15:11]==5'b10010)
|| (w_ir0[15:11]==5'b10001));
assign write_reg0 = ph0[3] && (
((w_ir0[15:14]==2'b00) && (w_ir0[7:0]==8'b00000001))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00010))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00100))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00101))
|| (w_ir0[15:14]==2'b11)
|| ((w_ir0[15:14]==2'b01) && (w_ir0[10:8]==3'b000)));
assign w_d0 = ((w_ir0[15:14]==2'b00) &&
(w_ir0[7:0]==8'b00000001)) ? w_dr0 : w_alu0;
assign write_dr1 = ph1[2] && (w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001);
assign write_dmem1 = ph1[2] && (w_ir1[15:11]==5'b00000) && (w_ir1[4:0]==5'b00000);
assign write_pc1 = ph1[3] && ((w_ir1[15:8]==8'b10000000)
|| (w_ir1[15:11]==5'b10010)
|| (w_ir1[15:11]==5'b10001));
assign write_reg1 = ph1[3] && (
((w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00010))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00100))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00101))
|| (w_ir1[15:14]==2'b11)
|| ((w_ir1[15:14]==2'b01) && (w_ir1[10:8]==3'b000)));
assign w_d1 = ((w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001)) ? w_dr1 : w_alu1;
assign write_dr2 = ph2[2] && (w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001);
assign write_dmem2 = ph2[2] && (w_ir2[15:11]==5'b00000) && (w_ir2[4:0]==5'b00000);
assign write_pc2 = ph2[3] && ((w_ir2[15:8]==8'b10000000)
|| (w_ir2[15:11]==5'b10010)
|| (w_ir2[15:11]==5'b10001));
assign write_reg2 = ph2[3] && (
((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00010))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00100))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00101))
|| (w_ir2[15:14]==2'b11)
|| ((w_ir2[15:14]==2'b01) && (w_ir2[10:8]==3'b000)));
assign w_d2 = ((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001)) ? w_dr2 : w_alu2;
assign write_dr3 = ph3[2] && (w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001);
assign write_dmem3 = ph3[2] && (w_ir3[15:11]==5'b00000) && (w_ir3[4:0]==5'b00000);
assign write_pc3 = ph3[3] && ((w_ir3[15:8]==8'b10000000)
|| (w_ir3[15:11]==5'b10010)
|| (w_ir3[15:11]==5'b10001));
assign write_reg3 = ph3[3] && (
((w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00010))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00100))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00101))
|| (w_ir3[15:14]==2'b11)
|| ((w_ir3[15:14]==2'b01) && (w_ir3[10:8]==3'b000)));
assign w_d3 = ((w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001)) ? w_dr3 : w_alu3;
wire [15:0] w_pc;
wire [15:0] w_imem;
wire [15:0] w_sr1,w_sr2;
wire [15:0] w_dmem;
wire write_dmem;
assign w_pc = (ph0[0]) ? w_pc0 :
(ph1[0]) ? w_pc1 :
(ph2[0]) ?
w_pc2 : w_pc3;
assign write_dmem = (write_dmem0) ||
(write_dmem1) ||
(write_dmem2) ||
(write_dmem3);
assign w_sr1 = (write_dmem0) ? w_sr1_0 :
(write_dmem1) ? w_sr1_1 :
(write_dmem2) ?
w_sr1_2 : w_sr1_3;
assign w_sr2 = (write_dmem0) ? w_sr2_0 :
(write_dmem1) ? w_sr2_1 :
(write_dmem2) ?
w_sr2_2 : w_sr2_3;
imem imem (
.address(w_pc),
.clock(~CLK),
.q(w_imem)
);
dmem dmem (
.address(w_sr1),
.clock(~CLK),
.data(w_sr2),
.wren(write_dmem),
.q(w_dmem)
);
sm sm0 (
.q(ph0),
.d(4'b0000),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm1 (
.q(ph1),
.d(4'b1000),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm2 (
.q(ph2),
.d(4'b0100),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm3 (
.q(ph3),
.d(4'b0010),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc0 (
.q(w_pc0),
.def(16'b0000000000001000),
.load(write_pc0),
.inc(ph0[0]),
.d(w_alu0),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc1 (
.q(w_pc1),
.def(16'b0000000000010000),
.load(write_pc1),
.inc(ph1[0]),
.d(w_alu1),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc2 (
.q(w_pc2),
.def(16'b0000000000011000),
.load(write_pc2),
.inc(ph2[0]),
.d(w_alu2),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc3 (
.q(w_pc3),
.def(16'b0000000000000000),
.load(write_pc3),
.inc(ph3[0]),
.d(w_alu3),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir0 (
.q(w_ir0),
.load(ph0[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir1 (
.q(w_ir1),
.load(ph1[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir2 (
.q(w_ir2),
.load(ph2[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir3 (
.q(w_ir3),
.load(ph3[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile0 (
.q0(r0_0),
.q1(r1_0),
.q2(r2_0),
.q3(r3_0),
.q4(r4_0),
.q5(r5_0),
.q6(r6_0),
.q7(r7_0),
.load(write_reg0),
.wsel(w_ir0[13:11]),
.d(w_d0),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile1 (
.q0(r0_1),
.q1(r1_1),
.q2(r2_1),
.q3(r3_1),
.q4(r4_1),
.q5(r5_1),
.q6(r6_1),
.q7(r7_1),
.load(write_reg1),
.wsel(w_ir1[13:11]),
.d(w_d1),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile2 (
.q0(r0_2),
.q1(r1_2),
.q2(r2_2),
.q3(r3_2),
.q4(r4_2),
.q5(r5_2),
.q6(r6_2),
.q7(r7_2),
.load(write_reg2),
.wsel(w_ir2[13:11]),
.d(w_d2),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile3 (
.q0(r0_3),
.q1(r1_3),
.q2(r2_3),
.q3(r3_3),
.q4(r4_3),
.q5(r5_3),
.q6(r6_3),
.q7(r7_3),
.load(write_reg3),
.wsel(w_ir3[13:11]),
.d(w_d3),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_0 (
.q(w_sr1_0),
.load(ph0[1]),
.d0(r0_0),
.d1(r1_0),
.d2(r2_0),
.d3(r3_0),
.d4(r4_0),
.d5(r5_0),
.d6(r6_0),
.d7(r7_0),
.sel(w_ir0[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_1 (
.q(w_sr1_1),
.load(ph1[1]),
.d0(r0_1),
.d1(r1_1),
.d2(r2_1),
.d3(r3_1),
.d4(r4_1),
.d5(r5_1),
.d6(r6_1),
.d7(r7_1),
.sel(w_ir1[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_2 (
.q(w_sr1_2),
.load(ph2[1]),
.d0(r0_2),
.d1(r1_2),
.d2(r2_2),
.d3(r3_2),
.d4(r4_2),
.d5(r5_2),
.d6(r6_2),
.d7(r7_2),
.sel(w_ir2[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_3 (
.q(w_sr1_3),
.load(ph3[1]),
.d0(r0_3),
.d1(r1_3),
.d2(r2_3),
.d3(r3_3),
.d4(r4_3),
.d5(r5_3),
.d6(r6_3),
.d7(r7_3),
.sel(w_ir3[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_0 (
.q(w_sr2_0),
.load(ph0[1]),
.d0(r0_0),
.d1(r1_0),
.d2(r2_0),
.d3(r3_0),
.d4(r4_0),
.d5(r5_0),
.d6(r6_0),
.d7(r7_0),
.sel(w_ir0[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_1 (
.q(w_sr2_1),
.load(ph1[1]),
.d0(r0_1),
.d1(r1_1),
.d2(r2_1),
.d3(r3_1),
.d4(r4_1),
.d5(r5_1),
.d6(r6_1),
.d7(r7_1),
.sel(w_ir1[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_2 (
.q(w_sr2_2),
.load(ph2[1]),
.d0(r0_2),
.d1(r1_2),
.d2(r2_2),
.d3(r3_2),
.d4(r4_2),
.d5(r5_2),
.d6(r6_2),
.d7(r7_2),
.sel(w_ir2[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_3 (
.q(w_sr2_3),
.load(ph3[1]),
.d0(r0_3),
.d1(r1_3),
.d2(r2_3),
.d3(r3_3),
.d4(r4_3),
.d5(r5_3),
.d6(r6_3),
.d7(r7_3),
.sel(w_ir3[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu0 (
.q(w_alu0),
.sr1(w_sr1_0),
.sr2(w_sr2_0),
.pc(w_pc0),
.ir(w_ir0),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu1 (
.q(w_alu1),
.sr1(w_sr1_1),
.sr2(w_sr2_1),
.pc(w_pc1),
.ir(w_ir1),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu2 (
.q(w_alu2),
.sr1(w_sr1_2),
.sr2(w_sr2_2),
.pc(w_pc2),
.ir(w_ir2),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu3 (
.q(w_alu3),
.sr1(w_sr1_3),
.sr2(w_sr2_3),
.pc(w_pc3),
.ir(w_ir3),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr0 (
.q(w_dr0),
.load(write_dr0),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr1 (
.q(w_dr1),
.load(write_dr1),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr2 (
.q(w_dr2),
.load(write_dr2),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr3 (
.q(w_dr3),
.load(write_dr3),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | module cpu (
output [7:0] led,
output [15:0] seg0,
output [15:0] seg1,
output [15:0] seg2,
output [15:0] seg3,
output [15:0] seg4,
output [15:0] seg5,
output [15:0] seg6,
output [15:0] seg7,
output [15:0] seg8,
output [15:0] seg9,
output [15:0] sega,
output [15:0] segb,
output [15:0] segc,
output [15:0] segd,
output [15:0] sege,
output [15:0] segf,
input start,
input stop,
input CLK,
input RSTN
); |
wire [3:0] ph0;
wire [15:0] w_imem0;
wire [15:0] w_dmem0;
wire [15:0] w_pc0, w_ir0, w_sr1_0, w_sr2_0, w_alu0, w_dr0;
wire [15:0] r0_0, r1_0, r2_0, r3_0, r4_0, r5_0, r6_0, r7_0;
wire write_dr0, write_dmem0, write_pc0, write_reg0;
wire [15:0] w_d0;
wire [3:0] ph1;
wire [15:0] w_imem1;
wire [15:0] w_dmem1;
wire [15:0] w_pc1, w_ir1, w_sr1_1, w_sr2_1, w_alu1, w_dr1;
wire [15:0] r0_1, r1_1, r2_1, r3_1, r4_1, r5_1, r6_1, r7_1;
wire write_dr1, write_dmem1, write_pc1, write_reg1;
wire [15:0] w_d1;
wire [3:0] ph2;
wire [15:0] w_imem2;
wire [15:0] w_dmem2;
wire [15:0] w_pc2, w_ir2, w_sr1_2, w_sr2_2, w_alu2, w_dr2;
wire [15:0] r0_2, r1_2, r2_2, r3_2, r4_2, r5_2, r6_2, r7_2;
wire write_dr2, write_dmem2, write_pc2, write_reg2;
wire [15:0] w_d2;
wire [3:0] ph3;
wire [15:0] w_imem3;
wire [15:0] w_dmem3;
wire [15:0] w_pc3, w_ir3, w_sr1_3, w_sr2_3, w_alu3, w_dr3;
wire [15:0] r0_3, r1_3, r2_3, r3_3, r4_3, r5_3, r6_3, r7_3;
wire write_dr3, write_dmem3, write_pc3, write_reg3;
wire [15:0] w_d3;
assign led = {4'b0000, ph3[3:0]};
assign seg0 = r0_3;
assign seg1 = r1_3;
assign seg2 = r2_3;
assign seg3 = r3_3;
assign seg4 = r4_3;
assign seg5 = r5_3;
assign seg6 = r6_3;
assign seg7 = r7_3;
assign seg8 = w_pc3;
assign seg9 = w_ir3;
assign sega = w_sr1_3;
assign segb = w_sr2_3;
assign segc = w_alu3;
assign segd = w_d3;
assign sege = 16'h0000;
assign segf = 16'h0000;
assign write_dr0 = ph0[2] &&
(w_ir0[15:14]==2'b00) && (w_ir0[7:0]==8'b00000001);
assign write_dmem0 = ph0[2] &&
(w_ir0[15:11]==5'b00000) && (w_ir0[4:0]==5'b00000);
assign write_pc0 = ph0[3] &&
((w_ir0[15:8]==8'b10000000)
|| (w_ir0[15:11]==5'b10010)
|| (w_ir0[15:11]==5'b10001));
assign write_reg0 = ph0[3] && (
((w_ir0[15:14]==2'b00) && (w_ir0[7:0]==8'b00000001))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00010))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00100))
|| ((w_ir0[15:14]==2'b00) && (w_ir0[4:0]==5'b00101))
|| (w_ir0[15:14]==2'b11)
|| ((w_ir0[15:14]==2'b01) && (w_ir0[10:8]==3'b000)));
assign w_d0 = ((w_ir0[15:14]==2'b00) &&
(w_ir0[7:0]==8'b00000001)) ? w_dr0 : w_alu0;
assign write_dr1 = ph1[2] && (w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001);
assign write_dmem1 = ph1[2] && (w_ir1[15:11]==5'b00000) && (w_ir1[4:0]==5'b00000);
assign write_pc1 = ph1[3] && ((w_ir1[15:8]==8'b10000000)
|| (w_ir1[15:11]==5'b10010)
|| (w_ir1[15:11]==5'b10001));
assign write_reg1 = ph1[3] && (
((w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00010))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00100))
|| ((w_ir1[15:14]==2'b00) && (w_ir1[4:0]==5'b00101))
|| (w_ir1[15:14]==2'b11)
|| ((w_ir1[15:14]==2'b01) && (w_ir1[10:8]==3'b000)));
assign w_d1 = ((w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001)) ? w_dr1 : w_alu1;
assign write_dr2 = ph2[2] && (w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001);
assign write_dmem2 = ph2[2] && (w_ir2[15:11]==5'b00000) && (w_ir2[4:0]==5'b00000);
assign write_pc2 = ph2[3] && ((w_ir2[15:8]==8'b10000000)
|| (w_ir2[15:11]==5'b10010)
|| (w_ir2[15:11]==5'b10001));
assign write_reg2 = ph2[3] && (
((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00010))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00100))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00101))
|| (w_ir2[15:14]==2'b11)
|| ((w_ir2[15:14]==2'b01) && (w_ir2[10:8]==3'b000)));
assign w_d2 = ((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001)) ? w_dr2 : w_alu2;
assign write_dr3 = ph3[2] && (w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001);
assign write_dmem3 = ph3[2] && (w_ir3[15:11]==5'b00000) && (w_ir3[4:0]==5'b00000);
assign write_pc3 = ph3[3] && ((w_ir3[15:8]==8'b10000000)
|| (w_ir3[15:11]==5'b10010)
|| (w_ir3[15:11]==5'b10001));
assign write_reg3 = ph3[3] && (
((w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00010))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00100))
|| ((w_ir3[15:14]==2'b00) && (w_ir3[4:0]==5'b00101))
|| (w_ir3[15:14]==2'b11)
|| ((w_ir3[15:14]==2'b01) && (w_ir3[10:8]==3'b000)));
assign w_d3 = ((w_ir3[15:14]==2'b00) && (w_ir3[7:0]==8'b00000001)) ? w_dr3 : w_alu3;
wire [15:0] w_pc;
wire [15:0] w_imem;
wire [15:0] w_sr1,w_sr2;
wire [15:0] w_dmem;
wire write_dmem;
assign w_pc = (ph0[0]) ? w_pc0 :
(ph1[0]) ? w_pc1 :
(ph2[0]) ?
w_pc2 : w_pc3;
assign write_dmem = (write_dmem0) ||
(write_dmem1) ||
(write_dmem2) ||
(write_dmem3);
assign w_sr1 = (write_dmem0) ? w_sr1_0 :
(write_dmem1) ? w_sr1_1 :
(write_dmem2) ?
w_sr1_2 : w_sr1_3;
assign w_sr2 = (write_dmem0) ? w_sr2_0 :
(write_dmem1) ? w_sr2_1 :
(write_dmem2) ?
w_sr2_2 : w_sr2_3;
imem imem (
.address(w_pc),
.clock(~CLK),
.q(w_imem)
);
dmem dmem (
.address(w_sr1),
.clock(~CLK),
.data(w_sr2),
.wren(write_dmem),
.q(w_dmem)
);
sm sm0 (
.q(ph0),
.d(4'b0000),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm1 (
.q(ph1),
.d(4'b1000),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm2 (
.q(ph2),
.d(4'b0100),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
sm sm3 (
.q(ph3),
.d(4'b0010),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc0 (
.q(w_pc0),
.def(16'b0000000000001000),
.load(write_pc0),
.inc(ph0[0]),
.d(w_alu0),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc1 (
.q(w_pc1),
.def(16'b0000000000010000),
.load(write_pc1),
.inc(ph1[0]),
.d(w_alu1),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc2 (
.q(w_pc2),
.def(16'b0000000000011000),
.load(write_pc2),
.inc(ph2[0]),
.d(w_alu2),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc3 (
.q(w_pc3),
.def(16'b0000000000000000),
.load(write_pc3),
.inc(ph3[0]),
.d(w_alu3),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir0 (
.q(w_ir0),
.load(ph0[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir1 (
.q(w_ir1),
.load(ph1[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir2 (
.q(w_ir2),
.load(ph2[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 ir3 (
.q(w_ir3),
.load(ph3[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile0 (
.q0(r0_0),
.q1(r1_0),
.q2(r2_0),
.q3(r3_0),
.q4(r4_0),
.q5(r5_0),
.q6(r6_0),
.q7(r7_0),
.load(write_reg0),
.wsel(w_ir0[13:11]),
.d(w_d0),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile1 (
.q0(r0_1),
.q1(r1_1),
.q2(r2_1),
.q3(r3_1),
.q4(r4_1),
.q5(r5_1),
.q6(r6_1),
.q7(r7_1),
.load(write_reg1),
.wsel(w_ir1[13:11]),
.d(w_d1),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile2 (
.q0(r0_2),
.q1(r1_2),
.q2(r2_2),
.q3(r3_2),
.q4(r4_2),
.q5(r5_2),
.q6(r6_2),
.q7(r7_2),
.load(write_reg2),
.wsel(w_ir2[13:11]),
.d(w_d2),
.CLK(CLK),
.RSTN(RSTN)
);
regfile regfile3 (
.q0(r0_3),
.q1(r1_3),
.q2(r2_3),
.q3(r3_3),
.q4(r4_3),
.q5(r5_3),
.q6(r6_3),
.q7(r7_3),
.load(write_reg3),
.wsel(w_ir3[13:11]),
.d(w_d3),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_0 (
.q(w_sr1_0),
.load(ph0[1]),
.d0(r0_0),
.d1(r1_0),
.d2(r2_0),
.d3(r3_0),
.d4(r4_0),
.d5(r5_0),
.d6(r6_0),
.d7(r7_0),
.sel(w_ir0[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_1 (
.q(w_sr1_1),
.load(ph1[1]),
.d0(r0_1),
.d1(r1_1),
.d2(r2_1),
.d3(r3_1),
.d4(r4_1),
.d5(r5_1),
.d6(r6_1),
.d7(r7_1),
.sel(w_ir1[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_2 (
.q(w_sr1_2),
.load(ph2[1]),
.d0(r0_2),
.d1(r1_2),
.d2(r2_2),
.d3(r3_2),
.d4(r4_2),
.d5(r5_2),
.d6(r6_2),
.d7(r7_2),
.sel(w_ir2[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1_3 (
.q(w_sr1_3),
.load(ph3[1]),
.d0(r0_3),
.d1(r1_3),
.d2(r2_3),
.d3(r3_3),
.d4(r4_3),
.d5(r5_3),
.d6(r6_3),
.d7(r7_3),
.sel(w_ir3[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_0 (
.q(w_sr2_0),
.load(ph0[1]),
.d0(r0_0),
.d1(r1_0),
.d2(r2_0),
.d3(r3_0),
.d4(r4_0),
.d5(r5_0),
.d6(r6_0),
.d7(r7_0),
.sel(w_ir0[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_1 (
.q(w_sr2_1),
.load(ph1[1]),
.d0(r0_1),
.d1(r1_1),
.d2(r2_1),
.d3(r3_1),
.d4(r4_1),
.d5(r5_1),
.d6(r6_1),
.d7(r7_1),
.sel(w_ir1[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_2 (
.q(w_sr2_2),
.load(ph2[1]),
.d0(r0_2),
.d1(r1_2),
.d2(r2_2),
.d3(r3_2),
.d4(r4_2),
.d5(r5_2),
.d6(r6_2),
.d7(r7_2),
.sel(w_ir2[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2_3 (
.q(w_sr2_3),
.load(ph3[1]),
.d0(r0_3),
.d1(r1_3),
.d2(r2_3),
.d3(r3_3),
.d4(r4_3),
.d5(r5_3),
.d6(r6_3),
.d7(r7_3),
.sel(w_ir3[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu0 (
.q(w_alu0),
.sr1(w_sr1_0),
.sr2(w_sr2_0),
.pc(w_pc0),
.ir(w_ir0),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu1 (
.q(w_alu1),
.sr1(w_sr1_1),
.sr2(w_sr2_1),
.pc(w_pc1),
.ir(w_ir1),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu2 (
.q(w_alu2),
.sr1(w_sr1_2),
.sr2(w_sr2_2),
.pc(w_pc2),
.ir(w_ir2),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu3 (
.q(w_alu3),
.sr1(w_sr1_3),
.sr2(w_sr2_3),
.pc(w_pc3),
.ir(w_ir3),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr0 (
.q(w_dr0),
.load(write_dr0),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr1 (
.q(w_dr1),
.load(write_dr1),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr2 (
.q(w_dr2),
.load(write_dr2),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
reg16 dr3 (
.q(w_dr3),
.load(write_dr3),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | 0 |
140,559 | data/full_repos/permissive/90508365/cpu2_tb.v | 90,508,365 | cpu2_tb.v | v | 61 | 62 | [] | [] | [] | null | line:33: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/cpu2_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/cpu2_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/cpu2_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #60\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/cpu2_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/cpu2_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #103000\n ^\n%Error: data/full_repos/permissive/90508365/cpu2_tb.v:36: Cannot find file containing module: \'cpu\'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,305 | module | module cpu_tb;
wire [7:0] led;
wire [15:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
wire [15:0] seg8, seg9, sega, segb, segc, segd, sege, segf;
reg start;
reg stop;
reg CLK;
reg RSTN;
initial
begin
CLK = 0;
while (1)
begin
#10
CLK = ~CLK;
end
end
initial
begin
RSTN = 0;
start = 0;
stop = 0;
#40
RSTN = 1;
#60
start = 1;
#20
start = 0;
#103000
$finish;
end
cpu cpu (
.led(led),
.seg0(seg0),
.seg1(seg1),
.seg2(seg2),
.seg3(seg3),
.seg4(seg4),
.seg5(seg5),
.seg6(seg6),
.seg7(seg7),
.seg8(seg8),
.seg9(seg9),
.sega(sega),
.segb(segb),
.segc(segc),
.segd(segd),
.sege(sege),
.segf(segf),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | module cpu_tb; |
wire [7:0] led;
wire [15:0] seg0, seg1, seg2, seg3, seg4, seg5, seg6, seg7;
wire [15:0] seg8, seg9, sega, segb, segc, segd, sege, segf;
reg start;
reg stop;
reg CLK;
reg RSTN;
initial
begin
CLK = 0;
while (1)
begin
#10
CLK = ~CLK;
end
end
initial
begin
RSTN = 0;
start = 0;
stop = 0;
#40
RSTN = 1;
#60
start = 1;
#20
start = 0;
#103000
$finish;
end
cpu cpu (
.led(led),
.seg0(seg0),
.seg1(seg1),
.seg2(seg2),
.seg3(seg3),
.seg4(seg4),
.seg5(seg5),
.seg6(seg6),
.seg7(seg7),
.seg8(seg8),
.seg9(seg9),
.sega(sega),
.segb(segb),
.segc(segc),
.segd(segd),
.sege(sege),
.segf(segf),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | 0 |
140,560 | data/full_repos/permissive/90508365/cputop.v | 90,508,365 | cputop.v | v | 304 | 84 | [] | [] | [] | [(1, 95), (98, 229), (231, 303)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cputop.v:34: Cannot find file containing module: 'cpu'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,306 | module | module cputop(
output [7:0] SEGX_A,
output [7:0] SEGX_B,
output [7:0] SEGX_C,
output [7:0] SEGX_D,
output [7:0] SEGX_E,
output [7:0] SEGX_F,
output [7:0] SEGX_G,
output [7:0] SEGX_H,
output [8:0] SEGX_SEL,
output [7:0] SEG_A,
output [7:0] SEG_B,
output [3:0] SEG_SELA,
output [3:0] SEG_SELB,
output [7:0] LED,
output BZ,
input PSW_D0,
input PSW_D1,
input CLK,
input CLK20MHZ,
input RSTN
);
wire [15:0] DATA0, DATA1, DATA2, DATA3;
wire [15:0] DATA4, DATA5, DATA6, DATA7;
wire [15:0] DATAP, DATAQ, DATAR, DATAS;
wire [15:0] DATAT, DATAU, DATAV, DATAW;
assign SEG_A = 8'b01101110;
assign SEG_B = 8'b00011100;
assign SEG_SELA = 4'b1111;
assign SEG_SELB = 4'b1111;
cpu cpu (
.led(LED[7:0]),
.seg8(DATAP),
.seg9(DATAQ),
.sega(DATAR),
.segb(DATAS),
.segc(DATAT),
.segd(DATAU),
.sege(DATAV),
.segf(DATAW),
.seg0(DATA0),
.seg1(DATA1),
.seg2(DATA2),
.seg3(DATA3),
.seg4(DATA4),
.seg5(DATA5),
.seg6(DATA6),
.seg7(DATA7),
.start(~PSW_D0),
.stop(~PSW_D1),
.CLK(CLK),
.RSTN(RSTN)
);
sevenseg sevenseg (
.SEGX_SEL(SEGX_SEL),
.SEGX_A(SEGX_A),
.SEGX_B(SEGX_B),
.SEGX_C(SEGX_C),
.SEGX_D(SEGX_D),
.SEGX_E(SEGX_E),
.SEGX_F(SEGX_F),
.SEGX_G(SEGX_G),
.SEGX_H(SEGX_H),
.LEDX(64'b0),
.DATA0(DATA0),
.DATA1(DATA1),
.DATA2(DATA2),
.DATA3(DATA3),
.DATA4(DATA4),
.DATA5(DATA5),
.DATA6(DATA6),
.DATA7(DATA7),
.DATAP(DATAP),
.DATAQ(DATAQ),
.DATAR(DATAR),
.DATAS(DATAS),
.DATAT(DATAT),
.DATAU(DATAU),
.DATAV(DATAV),
.DATAW(DATAW),
.CLK(CLK20MHZ),
.RSTN(RSTN)
);
sound sound (
.BZ(BZ),
.data(DATA0),
.CLK(CLK20MHZ),
.RSTN(RSTN)
);
endmodule | module cputop(
output [7:0] SEGX_A,
output [7:0] SEGX_B,
output [7:0] SEGX_C,
output [7:0] SEGX_D,
output [7:0] SEGX_E,
output [7:0] SEGX_F,
output [7:0] SEGX_G,
output [7:0] SEGX_H,
output [8:0] SEGX_SEL,
output [7:0] SEG_A,
output [7:0] SEG_B,
output [3:0] SEG_SELA,
output [3:0] SEG_SELB,
output [7:0] LED,
output BZ,
input PSW_D0,
input PSW_D1,
input CLK,
input CLK20MHZ,
input RSTN
); |
wire [15:0] DATA0, DATA1, DATA2, DATA3;
wire [15:0] DATA4, DATA5, DATA6, DATA7;
wire [15:0] DATAP, DATAQ, DATAR, DATAS;
wire [15:0] DATAT, DATAU, DATAV, DATAW;
assign SEG_A = 8'b01101110;
assign SEG_B = 8'b00011100;
assign SEG_SELA = 4'b1111;
assign SEG_SELB = 4'b1111;
cpu cpu (
.led(LED[7:0]),
.seg8(DATAP),
.seg9(DATAQ),
.sega(DATAR),
.segb(DATAS),
.segc(DATAT),
.segd(DATAU),
.sege(DATAV),
.segf(DATAW),
.seg0(DATA0),
.seg1(DATA1),
.seg2(DATA2),
.seg3(DATA3),
.seg4(DATA4),
.seg5(DATA5),
.seg6(DATA6),
.seg7(DATA7),
.start(~PSW_D0),
.stop(~PSW_D1),
.CLK(CLK),
.RSTN(RSTN)
);
sevenseg sevenseg (
.SEGX_SEL(SEGX_SEL),
.SEGX_A(SEGX_A),
.SEGX_B(SEGX_B),
.SEGX_C(SEGX_C),
.SEGX_D(SEGX_D),
.SEGX_E(SEGX_E),
.SEGX_F(SEGX_F),
.SEGX_G(SEGX_G),
.SEGX_H(SEGX_H),
.LEDX(64'b0),
.DATA0(DATA0),
.DATA1(DATA1),
.DATA2(DATA2),
.DATA3(DATA3),
.DATA4(DATA4),
.DATA5(DATA5),
.DATA6(DATA6),
.DATA7(DATA7),
.DATAP(DATAP),
.DATAQ(DATAQ),
.DATAR(DATAR),
.DATAS(DATAS),
.DATAT(DATAT),
.DATAU(DATAU),
.DATAV(DATAV),
.DATAW(DATAW),
.CLK(CLK20MHZ),
.RSTN(RSTN)
);
sound sound (
.BZ(BZ),
.data(DATA0),
.CLK(CLK20MHZ),
.RSTN(RSTN)
);
endmodule | 0 |
140,561 | data/full_repos/permissive/90508365/cputop.v | 90,508,365 | cputop.v | v | 304 | 84 | [] | [] | [] | [(1, 95), (98, 229), (231, 303)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cputop.v:34: Cannot find file containing module: 'cpu'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,306 | module | module sevenseg (
output [8:0] SEGX_SEL,
output [7:0] SEGX_A,
output [7:0] SEGX_B,
output [7:0] SEGX_C,
output [7:0] SEGX_D,
output [7:0] SEGX_E,
output [7:0] SEGX_F,
output [7:0] SEGX_G,
output [7:0] SEGX_H,
input [63:0] LEDX,
input [15:0] DATA0,
input [15:0] DATA1,
input [15:0] DATA2,
input [15:0] DATA3,
input [15:0] DATA4,
input [15:0] DATA5,
input [15:0] DATA6,
input [15:0] DATA7,
input [15:0] DATAP,
input [15:0] DATAQ,
input [15:0] DATAR,
input [15:0] DATAS,
input [15:0] DATAT,
input [15:0] DATAU,
input [15:0] DATAV,
input [15:0] DATAW,
input CLK,
input RSTN
);
reg [`SEG_DIVIDER-1:0] count0;
reg [3:0] count1;
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN)
begin
count0 <= `SEG_DIVIDER'd0;
end
else
begin
count0 <= count0+`SEG_DIVIDER'd1;
end
end
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN)
begin
count1 <= 4'd0;
end
else if (count0 == (1<<`SEG_DIVIDER)-1)
begin
if (count1 == 4'd8)
begin
count1 <= 4'd0;
end
else
begin
count1 <= count1+4'd1;
end
end
end
assign SEGX_SEL[0] = (count1==0 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[1] = (count1==1 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[2] = (count1==2 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[3] = (count1==3 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[4] = (count1==4 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[5] = (count1==5 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[6] = (count1==6 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[7] = (count1==7 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[8] = (count1==8 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_A = leddec(count1,DATA0[15:12],DATA2[15:12],DATA4[15:12],DATA6[15:12],
DATAP[15:12],DATAR[15:12],DATAT[15:12],DATAV[15:12],LEDX[63:56]);
assign SEGX_B = leddec(count1,DATA0[11: 8],DATA2[11: 8],DATA4[11: 8],DATA6[11: 8],
DATAP[11: 8],DATAR[11: 8],DATAT[11: 8],DATAV[11: 8],LEDX[55:48]);
assign SEGX_C = leddec(count1,DATA0[ 7: 4],DATA2[ 7: 4],DATA4[ 7: 4],DATA6[ 7: 4],
DATAP[ 7: 4],DATAR[ 7: 4],DATAT[ 7: 4],DATAV[ 7: 4],LEDX[47:40]);
assign SEGX_D = leddec(count1,DATA0[ 3: 0],DATA2[ 3: 0],DATA4[ 3: 0],DATA6[ 3: 0],
DATAP[ 3: 0],DATAR[ 3: 0],DATAT[ 3: 0],DATAV[ 3: 0],LEDX[39:32]);
assign SEGX_E = leddec(count1,DATA1[15:12],DATA3[15:12],DATA5[15:12],DATA7[15:12],
DATAQ[15:12],DATAS[15:12],DATAU[15:12],DATAW[15:12],LEDX[31:24]);
assign SEGX_F = leddec(count1,DATA1[11: 8],DATA3[11: 8],DATA5[11: 8],DATA7[11: 8],
DATAQ[11: 8],DATAS[11: 8],DATAU[11: 8],DATAW[11: 8],LEDX[23:16]);
assign SEGX_G = leddec(count1,DATA1[ 7: 4],DATA3[ 7: 4],DATA5[ 7: 4],DATA7[ 7: 4],
DATAQ[ 7: 4],DATAS[ 7: 4],DATAU[ 7: 4],DATAW[ 7: 4],LEDX[15: 8]);
assign SEGX_H = leddec(count1,DATA1[ 3: 0],DATA3[ 3: 0],DATA5[ 3: 0],DATA7[ 3: 0],
DATAQ[ 3: 0],DATAS[ 3: 0],DATAU[ 3: 0],DATAW[ 3: 0],LEDX[ 7: 0]);
function [7:0] leddec;
input [3:0] count1;
input [3:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [7:0] led;
case (count1)
0: leddec = bintoled(d0);
1: leddec = bintoled(d1);
2: leddec = bintoled(d2);
3: leddec = bintoled(d3);
4: leddec = bintoled(d4);
5: leddec = bintoled(d5);
6: leddec = bintoled(d6);
7: leddec = bintoled(d7);
default:leddec = {led[0],led[1],led[2],led[3],led[4],led[5],led[6],led[7]};
endcase
endfunction
function [7:0] bintoled;
input [3:0] data;
case (data)
4'h0: bintoled = 8'b11111100;
4'h1: bintoled = 8'b01100000;
4'h2: bintoled = 8'b11011010;
4'h3: bintoled = 8'b11110010;
4'h4: bintoled = 8'b01100110;
4'h5: bintoled = 8'b10110110;
4'h6: bintoled = 8'b10111110;
4'h7: bintoled = 8'b11100000;
4'h8: bintoled = 8'b11111110;
4'h9: bintoled = 8'b11110110;
4'ha: bintoled = 8'b11101110;
4'hb: bintoled = 8'b00111110;
4'hc: bintoled = 8'b00011010;
4'hd: bintoled = 8'b01111010;
4'he: bintoled = 8'b10011110;
4'hf: bintoled = 8'b10001110;
endcase
endfunction
endmodule | module sevenseg (
output [8:0] SEGX_SEL,
output [7:0] SEGX_A,
output [7:0] SEGX_B,
output [7:0] SEGX_C,
output [7:0] SEGX_D,
output [7:0] SEGX_E,
output [7:0] SEGX_F,
output [7:0] SEGX_G,
output [7:0] SEGX_H,
input [63:0] LEDX,
input [15:0] DATA0,
input [15:0] DATA1,
input [15:0] DATA2,
input [15:0] DATA3,
input [15:0] DATA4,
input [15:0] DATA5,
input [15:0] DATA6,
input [15:0] DATA7,
input [15:0] DATAP,
input [15:0] DATAQ,
input [15:0] DATAR,
input [15:0] DATAS,
input [15:0] DATAT,
input [15:0] DATAU,
input [15:0] DATAV,
input [15:0] DATAW,
input CLK,
input RSTN
); |
reg [`SEG_DIVIDER-1:0] count0;
reg [3:0] count1;
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN)
begin
count0 <= `SEG_DIVIDER'd0;
end
else
begin
count0 <= count0+`SEG_DIVIDER'd1;
end
end
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN)
begin
count1 <= 4'd0;
end
else if (count0 == (1<<`SEG_DIVIDER)-1)
begin
if (count1 == 4'd8)
begin
count1 <= 4'd0;
end
else
begin
count1 <= count1+4'd1;
end
end
end
assign SEGX_SEL[0] = (count1==0 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[1] = (count1==1 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[2] = (count1==2 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[3] = (count1==3 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[4] = (count1==4 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[5] = (count1==5 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[6] = (count1==6 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[7] = (count1==7 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_SEL[8] = (count1==8 && count0==1) ? 1'b1 : 1'b0;
assign SEGX_A = leddec(count1,DATA0[15:12],DATA2[15:12],DATA4[15:12],DATA6[15:12],
DATAP[15:12],DATAR[15:12],DATAT[15:12],DATAV[15:12],LEDX[63:56]);
assign SEGX_B = leddec(count1,DATA0[11: 8],DATA2[11: 8],DATA4[11: 8],DATA6[11: 8],
DATAP[11: 8],DATAR[11: 8],DATAT[11: 8],DATAV[11: 8],LEDX[55:48]);
assign SEGX_C = leddec(count1,DATA0[ 7: 4],DATA2[ 7: 4],DATA4[ 7: 4],DATA6[ 7: 4],
DATAP[ 7: 4],DATAR[ 7: 4],DATAT[ 7: 4],DATAV[ 7: 4],LEDX[47:40]);
assign SEGX_D = leddec(count1,DATA0[ 3: 0],DATA2[ 3: 0],DATA4[ 3: 0],DATA6[ 3: 0],
DATAP[ 3: 0],DATAR[ 3: 0],DATAT[ 3: 0],DATAV[ 3: 0],LEDX[39:32]);
assign SEGX_E = leddec(count1,DATA1[15:12],DATA3[15:12],DATA5[15:12],DATA7[15:12],
DATAQ[15:12],DATAS[15:12],DATAU[15:12],DATAW[15:12],LEDX[31:24]);
assign SEGX_F = leddec(count1,DATA1[11: 8],DATA3[11: 8],DATA5[11: 8],DATA7[11: 8],
DATAQ[11: 8],DATAS[11: 8],DATAU[11: 8],DATAW[11: 8],LEDX[23:16]);
assign SEGX_G = leddec(count1,DATA1[ 7: 4],DATA3[ 7: 4],DATA5[ 7: 4],DATA7[ 7: 4],
DATAQ[ 7: 4],DATAS[ 7: 4],DATAU[ 7: 4],DATAW[ 7: 4],LEDX[15: 8]);
assign SEGX_H = leddec(count1,DATA1[ 3: 0],DATA3[ 3: 0],DATA5[ 3: 0],DATA7[ 3: 0],
DATAQ[ 3: 0],DATAS[ 3: 0],DATAU[ 3: 0],DATAW[ 3: 0],LEDX[ 7: 0]);
function [7:0] leddec;
input [3:0] count1;
input [3:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [7:0] led;
case (count1)
0: leddec = bintoled(d0);
1: leddec = bintoled(d1);
2: leddec = bintoled(d2);
3: leddec = bintoled(d3);
4: leddec = bintoled(d4);
5: leddec = bintoled(d5);
6: leddec = bintoled(d6);
7: leddec = bintoled(d7);
default:leddec = {led[0],led[1],led[2],led[3],led[4],led[5],led[6],led[7]};
endcase
endfunction
function [7:0] bintoled;
input [3:0] data;
case (data)
4'h0: bintoled = 8'b11111100;
4'h1: bintoled = 8'b01100000;
4'h2: bintoled = 8'b11011010;
4'h3: bintoled = 8'b11110010;
4'h4: bintoled = 8'b01100110;
4'h5: bintoled = 8'b10110110;
4'h6: bintoled = 8'b10111110;
4'h7: bintoled = 8'b11100000;
4'h8: bintoled = 8'b11111110;
4'h9: bintoled = 8'b11110110;
4'ha: bintoled = 8'b11101110;
4'hb: bintoled = 8'b00111110;
4'hc: bintoled = 8'b00011010;
4'hd: bintoled = 8'b01111010;
4'he: bintoled = 8'b10011110;
4'hf: bintoled = 8'b10001110;
endcase
endfunction
endmodule | 0 |
140,562 | data/full_repos/permissive/90508365/cputop.v | 90,508,365 | cputop.v | v | 304 | 84 | [] | [] | [] | [(1, 95), (98, 229), (231, 303)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cputop.v:34: Cannot find file containing module: 'cpu'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,306 | module | module sound (output BZ, input [15:0] data, input CLK, input RSTN);
reg [16:0] count;
reg [16:0] counter;
always @* begin
case (data)
1: count = 17'd90909;
2: count = 17'd85806;
3: count = 17'd80990;
4: count = 17'd76445;
5: count = 17'd72154;
6: count = 17'd68104;
7: count = 17'd64282;
8: count = 17'd60674;
9: count = 17'd57269;
10: count = 17'd54054;
11: count = 17'd51021;
12: count = 17'd48157;
13: count = 17'd45454;
14: count = 17'd42903;
15: count = 17'd40495;
16: count = 17'd38222;
17: count = 17'd36077;
18: count = 17'd34052;
19: count = 17'd32141;
20: count = 17'd30337;
21: count = 17'd28634;
22: count = 17'd27027;
23: count = 17'd25510;
24: count = 17'd24078;
25: count = 17'd22727;
26: count = 17'd21451;
27: count = 17'd20247;
28: count = 17'd19111;
29: count = 17'd18038;
30: count = 17'd17026;
31: count = 17'd16070;
32: count = 17'd15168;
33: count = 17'd14317;
34: count = 17'd13513;
35: count = 17'd12755;
36: count = 17'd12039;
37: count = 17'd11363;
38: count = 17'd10725;
39: count = 17'd10123;
40: count = 17'd9555;
41: count = 17'd9019;
42: count = 17'd8513;
43: count = 17'd8035;
44: count = 17'd7584;
45: count = 17'd7158;
46: count = 17'd6756;
47: count = 17'd6377;
48: count = 17'd6019;
49: count = 17'd5681;
50: count = 17'd5362;
51: count = 17'd5061;
52: count = 17'd4777;
default: count = 17'd0;
endcase
end
always @(posedge CLK or negedge RSTN) begin
if (!RSTN) begin
counter <= 17'd0;
end
else begin
if (counter == 0) counter <= count;
else counter <= counter - 17'd1;
end
end
assign BZ = (counter>(count>>1));
endmodule | module sound (output BZ, input [15:0] data, input CLK, input RSTN); |
reg [16:0] count;
reg [16:0] counter;
always @* begin
case (data)
1: count = 17'd90909;
2: count = 17'd85806;
3: count = 17'd80990;
4: count = 17'd76445;
5: count = 17'd72154;
6: count = 17'd68104;
7: count = 17'd64282;
8: count = 17'd60674;
9: count = 17'd57269;
10: count = 17'd54054;
11: count = 17'd51021;
12: count = 17'd48157;
13: count = 17'd45454;
14: count = 17'd42903;
15: count = 17'd40495;
16: count = 17'd38222;
17: count = 17'd36077;
18: count = 17'd34052;
19: count = 17'd32141;
20: count = 17'd30337;
21: count = 17'd28634;
22: count = 17'd27027;
23: count = 17'd25510;
24: count = 17'd24078;
25: count = 17'd22727;
26: count = 17'd21451;
27: count = 17'd20247;
28: count = 17'd19111;
29: count = 17'd18038;
30: count = 17'd17026;
31: count = 17'd16070;
32: count = 17'd15168;
33: count = 17'd14317;
34: count = 17'd13513;
35: count = 17'd12755;
36: count = 17'd12039;
37: count = 17'd11363;
38: count = 17'd10725;
39: count = 17'd10123;
40: count = 17'd9555;
41: count = 17'd9019;
42: count = 17'd8513;
43: count = 17'd8035;
44: count = 17'd7584;
45: count = 17'd7158;
46: count = 17'd6756;
47: count = 17'd6377;
48: count = 17'd6019;
49: count = 17'd5681;
50: count = 17'd5362;
51: count = 17'd5061;
52: count = 17'd4777;
default: count = 17'd0;
endcase
end
always @(posedge CLK or negedge RSTN) begin
if (!RSTN) begin
counter <= 17'd0;
end
else begin
if (counter == 0) counter <= count;
else counter <= counter - 17'd1;
end
end
assign BZ = (counter>(count>>1));
endmodule | 0 |
140,563 | data/full_repos/permissive/90508365/cputop.v | 90,508,365 | cputop.v | v | 304 | 84 | [] | [] | [] | [(1, 95), (98, 229), (231, 303)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cputop.v:34: Cannot find file containing module: 'cpu'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,306 | function | function [7:0] leddec;
input [3:0] count1;
input [3:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [7:0] led;
case (count1)
0: leddec = bintoled(d0);
1: leddec = bintoled(d1);
2: leddec = bintoled(d2);
3: leddec = bintoled(d3);
4: leddec = bintoled(d4);
5: leddec = bintoled(d5);
6: leddec = bintoled(d6);
7: leddec = bintoled(d7);
default:leddec = {led[0],led[1],led[2],led[3],led[4],led[5],led[6],led[7]};
endcase
endfunction | function [7:0] leddec; |
input [3:0] count1;
input [3:0] d0,d1,d2,d3,d4,d5,d6,d7;
input [7:0] led;
case (count1)
0: leddec = bintoled(d0);
1: leddec = bintoled(d1);
2: leddec = bintoled(d2);
3: leddec = bintoled(d3);
4: leddec = bintoled(d4);
5: leddec = bintoled(d5);
6: leddec = bintoled(d6);
7: leddec = bintoled(d7);
default:leddec = {led[0],led[1],led[2],led[3],led[4],led[5],led[6],led[7]};
endcase
endfunction | 0 |
140,564 | data/full_repos/permissive/90508365/cputop.v | 90,508,365 | cputop.v | v | 304 | 84 | [] | [] | [] | [(1, 95), (98, 229), (231, 303)] | null | null | 1: b"%Error: data/full_repos/permissive/90508365/cputop.v:34: Cannot find file containing module: 'cpu'\n cpu cpu (\n ^~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/cpu.sv\n cpu\n cpu.v\n cpu.sv\n obj_dir/cpu\n obj_dir/cpu.v\n obj_dir/cpu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,306 | function | function [7:0] bintoled;
input [3:0] data;
case (data)
4'h0: bintoled = 8'b11111100;
4'h1: bintoled = 8'b01100000;
4'h2: bintoled = 8'b11011010;
4'h3: bintoled = 8'b11110010;
4'h4: bintoled = 8'b01100110;
4'h5: bintoled = 8'b10110110;
4'h6: bintoled = 8'b10111110;
4'h7: bintoled = 8'b11100000;
4'h8: bintoled = 8'b11111110;
4'h9: bintoled = 8'b11110110;
4'ha: bintoled = 8'b11101110;
4'hb: bintoled = 8'b00111110;
4'hc: bintoled = 8'b00011010;
4'hd: bintoled = 8'b01111010;
4'he: bintoled = 8'b10011110;
4'hf: bintoled = 8'b10001110;
endcase
endfunction | function [7:0] bintoled; |
input [3:0] data;
case (data)
4'h0: bintoled = 8'b11111100;
4'h1: bintoled = 8'b01100000;
4'h2: bintoled = 8'b11011010;
4'h3: bintoled = 8'b11110010;
4'h4: bintoled = 8'b01100110;
4'h5: bintoled = 8'b10110110;
4'h6: bintoled = 8'b10111110;
4'h7: bintoled = 8'b11100000;
4'h8: bintoled = 8'b11111110;
4'h9: bintoled = 8'b11110110;
4'ha: bintoled = 8'b11101110;
4'hb: bintoled = 8'b00111110;
4'hc: bintoled = 8'b00011010;
4'hd: bintoled = 8'b01111010;
4'he: bintoled = 8'b10011110;
4'hf: bintoled = 8'b10001110;
endcase
endfunction | 0 |
140,565 | data/full_repos/permissive/90508365/dmem_tb.v | 90,508,365 | dmem_tb.v | v | 72 | 39 | [] | [] | [] | null | line:53: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Error: data/full_repos/permissive/90508365/dmem_tb.v:13: Cannot find file containing module: \'dmem\'\n dmem dmem (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem.sv\n dmem\n dmem.v\n dmem.sv\n obj_dir/dmem\n obj_dir/dmem.v\n obj_dir/dmem.sv\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n adr = i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:36: Operator FUNCREF \'reverse\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n dat = reverse(i);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:45: Operator FUNCREF \'reverse\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n adr = reverse(i);\n ^~~~~~~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,310 | module | module dmem_tb;
reg CLK;
reg wren;
reg [15:0] adr;
reg [15:0] dat;
wire [15:0] w_dmem;
reg [15:0] dr;
integer i;
reg read;
dmem dmem (
.address(adr),
.data(dat),
.wren(wren),
.clock(~CLK),
.q(w_dmem)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
read = 0;
wren = 0;
adr = -1;
dat = -1;
for (i=0;i<(1<<`ADDR);i=i+1) begin
#10
adr = i;
dat = reverse(i);
wren = 1;
#20
wren = 0;
dat = ~dat;
#10;
end
for (i=0;i<(1<<`ADDR);i=i+1) begin
#10
adr = reverse(i);
#10
read = 1;
#10
adr = -1;
#10
read = 0;
end
#20 $finish;
end
always @(posedge CLK) begin
if (read) dr <= w_dmem;
end
function [15:0] reverse;
input [15:0] d;
integer i;
begin
reverse = 0;
for (i=0;i<`ADDR;i=i+1) begin
reverse[i] = d[`ADDR-1-i];
end
end
endfunction
endmodule | module dmem_tb; |
reg CLK;
reg wren;
reg [15:0] adr;
reg [15:0] dat;
wire [15:0] w_dmem;
reg [15:0] dr;
integer i;
reg read;
dmem dmem (
.address(adr),
.data(dat),
.wren(wren),
.clock(~CLK),
.q(w_dmem)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
read = 0;
wren = 0;
adr = -1;
dat = -1;
for (i=0;i<(1<<`ADDR);i=i+1) begin
#10
adr = i;
dat = reverse(i);
wren = 1;
#20
wren = 0;
dat = ~dat;
#10;
end
for (i=0;i<(1<<`ADDR);i=i+1) begin
#10
adr = reverse(i);
#10
read = 1;
#10
adr = -1;
#10
read = 0;
end
#20 $finish;
end
always @(posedge CLK) begin
if (read) dr <= w_dmem;
end
function [15:0] reverse;
input [15:0] d;
integer i;
begin
reverse = 0;
for (i=0;i<`ADDR;i=i+1) begin
reverse[i] = d[`ADDR-1-i];
end
end
endfunction
endmodule | 0 |
140,566 | data/full_repos/permissive/90508365/dmem_tb.v | 90,508,365 | dmem_tb.v | v | 72 | 39 | [] | [] | [] | null | line:53: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #10 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/dmem_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #20 $finish;\n ^\n%Error: data/full_repos/permissive/90508365/dmem_tb.v:13: Cannot find file containing module: \'dmem\'\n dmem dmem (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/dmem.sv\n dmem\n dmem.v\n dmem.sv\n obj_dir/dmem\n obj_dir/dmem.v\n obj_dir/dmem.sv\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n adr = i;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:36: Operator FUNCREF \'reverse\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n dat = reverse(i);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/90508365/dmem_tb.v:45: Operator FUNCREF \'reverse\' expects 16 bits on the Function Argument, but Function Argument\'s VARREF \'i\' generates 32 bits.\n : ... In instance dmem_tb\n adr = reverse(i);\n ^~~~~~~\n%Error: Exiting due to 1 error(s), 12 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,310 | function | function [15:0] reverse;
input [15:0] d;
integer i;
begin
reverse = 0;
for (i=0;i<`ADDR;i=i+1) begin
reverse[i] = d[`ADDR-1-i];
end
end
endfunction | function [15:0] reverse; |
input [15:0] d;
integer i;
begin
reverse = 0;
for (i=0;i<`ADDR;i=i+1) begin
reverse[i] = d[`ADDR-1-i];
end
end
endfunction | 0 |
140,567 | data/full_repos/permissive/90508365/imem_tb.v | 90,508,365 | imem_tb.v | v | 37 | 38 | [] | [] | [] | [(21, 29)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/imem_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n #10 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/imem_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/imem_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #80 adr = (adr==5) ? 3 : adr+1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/imem_tb.v:33: Unsupported: Ignoring delay on this delayed statement.\n #1200\n ^\n%Error: data/full_repos/permissive/90508365/imem_tb.v:7: Cannot find file containing module: \'imem\'\n imem imem (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/imem.sv\n imem\n imem.v\n imem.sv\n obj_dir/imem\n obj_dir/imem.v\n obj_dir/imem.sv\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,313 | module | module imem_tb;
reg CLK;
reg [15:0] adr;
reg [15:0] ir;
wire [15:0] w_imem;
imem imem (
.address(adr),
.clock(~CLK),
.q(w_imem)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
adr = 0;
#10;
while (1) begin
#80 adr = (adr==5) ? 3 : adr+1;
end
end
always @(posedge CLK) begin
ir <= w_imem;
end
initial begin
#1200
$finish;
end
endmodule | module imem_tb; |
reg CLK;
reg [15:0] adr;
reg [15:0] ir;
wire [15:0] w_imem;
imem imem (
.address(adr),
.clock(~CLK),
.q(w_imem)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
adr = 0;
#10;
while (1) begin
#80 adr = (adr==5) ? 3 : adr+1;
end
end
always @(posedge CLK) begin
ir <= w_imem;
end
initial begin
#1200
$finish;
end
endmodule | 0 |
140,568 | data/full_repos/permissive/90508365/muxreg16 (1).v | 90,508,365 | muxreg16 (1).v | v | 35 | 40 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b'%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s)\n' | 309,314 | module | module muxreg16 (
output reg [15:0] q,
input [15:0] d0,
input [15:0] d1,
input [15:0] d2,
input [15:0] d3,
input [15:0] d4,
input [15:0] d5,
input [15:0] d6,
input [15:0] d7,
input load,
input [2:0] sel,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else if (load) begin
case (sel)
3'b000 : q <= d0;
3'b001 : q <= d1;
3'b010 : q <= d2;
3'b011 : q <= d3;
3'b100 : q <= d4;
3'b101 : q <= d5;
3'b110 : q <= d6;
3'b111 : q <= d7;
endcase
end
end
endmodule | module muxreg16 (
output reg [15:0] q,
input [15:0] d0,
input [15:0] d1,
input [15:0] d2,
input [15:0] d3,
input [15:0] d4,
input [15:0] d5,
input [15:0] d6,
input [15:0] d7,
input load,
input [2:0] sel,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else if (load) begin
case (sel)
3'b000 : q <= d0;
3'b001 : q <= d1;
3'b010 : q <= d2;
3'b011 : q <= d3;
3'b100 : q <= d4;
3'b101 : q <= d5;
3'b110 : q <= d6;
3'b111 : q <= d7;
endcase
end
end
endmodule | 0 |
140,569 | data/full_repos/permissive/90508365/muxreg16_tb.v | 90,508,365 | muxreg16_tb.v | v | 58 | 51 | [] | [] | [] | null | line:20: before: "while" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:12: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/muxreg16_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #700\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d0 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:32: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d1 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:33: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d2 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:34: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d3 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:35: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d4 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:36: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d5 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d6 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:38: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n d7 = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/muxreg16_tb.v:39: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance muxreg16_tb\n sel = $random;\n ^\n%Error: data/full_repos/permissive/90508365/muxreg16_tb.v:51: Cannot find file containing module: \'muxreg16\'\n muxreg16 muxreg16 (\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/muxreg16\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/muxreg16.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/muxreg16.sv\n muxreg16\n muxreg16.v\n muxreg16.sv\n obj_dir/muxreg16\n obj_dir/muxreg16.v\n obj_dir/muxreg16.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,316 | module | module muxreg16_tb;
wire [15:0] q;
reg [15:0] d0, d1, d2, d3, d4, d5, d6, d7;
reg load;
reg [2:0] sel;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
load = 0;
#40
while (1) begin
load = 1;
#20
load = 0;
#40;
end
end
initial begin
while (1) begin
#20
d0 = $random;
d1 = $random;
d2 = $random;
d3 = $random;
d4 = $random;
d5 = $random;
d6 = $random;
d7 = $random;
sel = $random;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#700
$finish;
end
muxreg16 muxreg16 (
.q(q),
.d0(d0), .d1(d1), .d2(d2), .d3(d3),
.d4(d4), .d5(d5), .d6(d6), .d7(d7),
.load(load), .sel(sel), .CLK(CLK), .RSTN(RSTN));
endmodule | module muxreg16_tb; |
wire [15:0] q;
reg [15:0] d0, d1, d2, d3, d4, d5, d6, d7;
reg load;
reg [2:0] sel;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
load = 0;
#40
while (1) begin
load = 1;
#20
load = 0;
#40;
end
end
initial begin
while (1) begin
#20
d0 = $random;
d1 = $random;
d2 = $random;
d3 = $random;
d4 = $random;
d5 = $random;
d6 = $random;
d7 = $random;
sel = $random;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#700
$finish;
end
muxreg16 muxreg16 (
.q(q),
.d0(d0), .d1(d1), .d2(d2), .d3(d3),
.d4(d4), .d5(d5), .d6(d6), .d7(d7),
.load(load), .sel(sel), .CLK(CLK), .RSTN(RSTN));
endmodule | 0 |
140,570 | data/full_repos/permissive/90508365/reg16.v | 90,508,365 | reg16.v | v | 18 | 40 | [] | [] | [] | [(1, 17)] | null | data/verilator_xmls/39062e48-7950-4871-a8f2-37fb7a473681.xml | null | 309,317 | module | module reg16 (
output reg [15:0] q,
input [15:0] d,
input load,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else if (load) begin
q <= d;
end
end
endmodule | module reg16 (
output reg [15:0] q,
input [15:0] d,
input load,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else if (load) begin
q <= d;
end
end
endmodule | 0 |
140,571 | data/full_repos/permissive/90508365/reg16_tb (1).v | 90,508,365 | reg16_tb (1).v | v | 46 | 67 | [] | [] | [] | [(21, 46)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:21: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:23: Unsupported: Ignoring delay on this delayed statement.\n #40;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #40\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:37: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/reg16_tb.v:39: Unsupported: Ignoring delay on this delayed statement.\n #700\n ^\n%Error: Cannot find file containing module: (1).v\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/(1).v.sv\n (1).v\n (1).v.v\n (1).v.sv\n obj_dir/(1).v\n obj_dir/(1).v.v\n obj_dir/(1).v.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,318 | module | module reg16_tb;
wire [15:0] q;
reg [15:0] d;
reg load;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
load = 0;
#40
while (1) begin
load = 1;
#20
load = 0;
#40;
end
end
initial begin
d = 0;
while (1) begin
#20
d = $random;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#700
$finish;
end
reg16 reg16 (.q(q), .d(d), .load(load), .CLK(CLK), .RSTN(RSTN));
endmodule | module reg16_tb; |
wire [15:0] q;
reg [15:0] d;
reg load;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
load = 0;
#40
while (1) begin
load = 1;
#20
load = 0;
#40;
end
end
initial begin
d = 0;
while (1) begin
#20
d = $random;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#700
$finish;
end
reg16 reg16 (.q(q), .d(d), .load(load), .CLK(CLK), .RSTN(RSTN));
endmodule | 0 |
140,572 | data/full_repos/permissive/90508365/regfile.v | 90,508,365 | regfile.v | v | 35 | 43 | [] | [] | [] | [(1, 34)] | null | data/verilator_xmls/558571d1-1d14-4f1c-b2ec-496855370e6e.xml | null | 309,320 | module | module regfile (
output reg [15:0] q0,
output reg [15:0] q1,
output reg [15:0] q2,
output reg [15:0] q3,
output reg [15:0] q4,
output reg [15:0] q5,
output reg [15:0] q6,
output reg [15:0] q7,
input [15:0] d,
input load,
input [2:0] wsel,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
{q0,q1,q2,q3,q4,q5,q6,q7} <= 128'b0;
end
else if (load) begin
case (wsel)
3'b000 : q0 <= d;
3'b001 : q1 <= d;
3'b010 : q2 <= d;
3'b011 : q3 <= d;
3'b100 : q4 <= d;
3'b101 : q5 <= d;
3'b110 : q6 <= d;
3'b111 : q7 <= d;
endcase
end
end
endmodule | module regfile (
output reg [15:0] q0,
output reg [15:0] q1,
output reg [15:0] q2,
output reg [15:0] q3,
output reg [15:0] q4,
output reg [15:0] q5,
output reg [15:0] q6,
output reg [15:0] q7,
input [15:0] d,
input load,
input [2:0] wsel,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
{q0,q1,q2,q3,q4,q5,q6,q7} <= 128'b0;
end
else if (load) begin
case (wsel)
3'b000 : q0 <= d;
3'b001 : q1 <= d;
3'b010 : q2 <= d;
3'b011 : q3 <= d;
3'b100 : q4 <= d;
3'b101 : q5 <= d;
3'b110 : q6 <= d;
3'b111 : q7 <= d;
endcase
end
end
endmodule | 0 |
140,573 | data/full_repos/permissive/90508365/regfile_tb.v | 90,508,365 | regfile_tb.v | v | 40 | 46 | [] | [] | [] | null | line:37: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/regfile_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #10 CLK = ~CLK;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/regfile_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #20;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/regfile_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/regfile_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #400\n ^\n%Error: data/full_repos/permissive/90508365/regfile_tb.v:9: Cannot find file containing module: \'regfile\'\n regfile regfile (\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/regfile\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/regfile.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/regfile.sv\n regfile\n regfile.v\n regfile.sv\n obj_dir/regfile\n obj_dir/regfile.v\n obj_dir/regfile.sv\n%Warning-WIDTH: data/full_repos/permissive/90508365/regfile_tb.v:25: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance regfile_tb\n d = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/regfile_tb.v:26: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance regfile_tb\n load = $random;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90508365/regfile_tb.v:27: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS\'s RAND generates 32 bits.\n : ... In instance regfile_tb\n wsel = $random;\n ^\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,321 | module | module regfile_tb;
wire [15:0] q0, q1, q2, q3, q4, q5, q6, q7;
reg [15:0] d;
reg load;
reg [2:0] wsel;
reg CLK;
reg RSTN;
regfile regfile (
.q0(q0), .q1(q1), .q2(q2), .q3(q3),
.q4(q4), .q5(q5), .q6(q6), .q7(q7),
.d(d), .load(load), .wsel(wsel),
.CLK(CLK), .RSTN(RSTN)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
while (1) begin
d = $random;
load = $random;
wsel = $random;
#20;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#400
$finish;
end
endmodule | module regfile_tb; |
wire [15:0] q0, q1, q2, q3, q4, q5, q6, q7;
reg [15:0] d;
reg load;
reg [2:0] wsel;
reg CLK;
reg RSTN;
regfile regfile (
.q0(q0), .q1(q1), .q2(q2), .q3(q3),
.q4(q4), .q5(q5), .q6(q6), .q7(q7),
.d(d), .load(load), .wsel(wsel),
.CLK(CLK), .RSTN(RSTN)
);
initial begin
CLK = 0;
while (1) begin
#10 CLK = ~CLK;
end
end
initial begin
while (1) begin
d = $random;
load = $random;
wsel = $random;
#20;
end
end
initial begin
RSTN = 0;
#20
RSTN = 1;
#400
$finish;
end
endmodule | 0 |
140,574 | data/full_repos/permissive/90508365/sm.v | 90,508,365 | sm.v | v | 26 | 51 | [] | [] | [] | [(1, 25)] | null | data/verilator_xmls/366aec83-08ca-43bb-a66a-a2f72acecf90.xml | null | 309,322 | module | module sm (
output reg [3:0] q,
input [3:0] d,
input start,
input stop,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= d;
end
else begin
casex ({q,start,stop})
6'b0000_1_x: q <= 4'b0001;
6'b0001_x_x: q <= 4'b0010;
6'b0010_x_x: q <= 4'b0100;
6'b0100_x_x: q <= 4'b1000;
6'b1000_x_0: q <= 4'b0001;
6'b1000_x_1: q <= 4'b0000;
endcase
end
end
endmodule | module sm (
output reg [3:0] q,
input [3:0] d,
input start,
input stop,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= d;
end
else begin
casex ({q,start,stop})
6'b0000_1_x: q <= 4'b0001;
6'b0001_x_x: q <= 4'b0010;
6'b0010_x_x: q <= 4'b0100;
6'b0100_x_x: q <= 4'b1000;
6'b1000_x_0: q <= 4'b0001;
6'b1000_x_1: q <= 4'b0000;
endcase
end
end
endmodule | 0 |
140,575 | data/full_repos/permissive/90508365/sm_tb.v | 90,508,365 | sm_tb.v | v | 37 | 70 | [] | [] | [] | null | line:31: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #80\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #80\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #200\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #100\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90508365/sm_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #50\n ^\n%Error: data/full_repos/permissive/90508365/sm_tb.v:34: Cannot find file containing module: \'sm\'\n sm sm (.q(ph), .start(start), .stop(stop), .CLK(CLK), .RSTN(RSTN));\n ^~\n ... Looked in:\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/sm\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/sm.v\n data/full_repos/permissive/90508365,data/full_repos/permissive/90508365/sm.sv\n sm\n sm.v\n sm.sv\n obj_dir/sm\n obj_dir/sm.v\n obj_dir/sm.sv\n%Error: Exiting due to 1 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,323 | module | module sm_tb;
wire [3:0] ph;
reg start;
reg stop;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
RSTN = 0;
start = 0;
stop = 0;
#100
RSTN = 1;
#80
start = 1;
#80
start = 0;
#200
stop = 1;
#100
stop = 0;
#50
$finish;
end
sm sm (.q(ph), .start(start), .stop(stop), .CLK(CLK), .RSTN(RSTN));
endmodule | module sm_tb; |
wire [3:0] ph;
reg start;
reg stop;
reg CLK;
reg RSTN;
initial begin
CLK = 0;
while(1) begin
#10
CLK = ~CLK;
end
end
initial begin
RSTN = 0;
start = 0;
stop = 0;
#100
RSTN = 1;
#80
start = 1;
#80
start = 0;
#200
stop = 1;
#100
stop = 0;
#50
$finish;
end
sm sm (.q(ph), .start(start), .stop(stop), .CLK(CLK), .RSTN(RSTN));
endmodule | 0 |
140,576 | data/full_repos/permissive/90508539/count16rle.v | 90,508,539 | count16rle.v | v | 24 | 40 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/5a8b9ef3-6899-424a-a25f-b060a7481007.xml | null | 309,326 | module | module count16rle(
output reg [15:0] q,
input [15:0] d,
input load,
input inc,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
if (load) begin
q <= d;
end
else if (inc) begin
q <= q + 1;
end
end
end
endmodule | module count16rle(
output reg [15:0] q,
input [15:0] d,
input load,
input inc,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
if (load) begin
q <= d;
end
else if (inc) begin
q <= q + 1;
end
end
end
endmodule | 0 |
140,577 | data/full_repos/permissive/90508539/cpu.v | 90,508,539 | cpu.v | v | 235 | 69 | [] | [] | [] | [(1, 234)] | null | null | 1: b"%Error: data/full_repos/permissive/90508539/cpu.v:101: Cannot find file containing module: 'sm'\n sm sm (\n ^~\n ... Looked in:\n data/full_repos/permissive/90508539,data/full_repos/permissive/90508539/sm\n data/full_repos/permissive/90508539,data/full_repos/permissive/90508539/sm.v\n data/full_repos/permissive/90508539,data/full_repos/permissive/90508539/sm.sv\n sm\n sm.v\n sm.sv\n obj_dir/sm\n obj_dir/sm.v\n obj_dir/sm.sv\n%Error: data/full_repos/permissive/90508539/cpu.v:109: Cannot find file containing module: 'count16rle'\n count16rle pc (\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:118: Cannot find file containing module: 'count16rle'\n count16rle pc1 ( \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:127: Cannot find file containing module: 'imem'\n imem imem (\n ^~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:133: Cannot find file containing module: 'reg16'\n reg16 ir ( \n ^~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:142: Cannot find file containing module: 'reg16'\n reg16 ir1 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:151: Cannot find file containing module: 'reg16'\n reg16 ir2 ( \n ^~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:160: Cannot find file containing module: 'regfile'\n regfile regfile (\n ^~~~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:176: Cannot find file containing module: 'muxreg16'\n muxreg16 sr1 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:192: Cannot find file containing module: 'muxreg16'\n muxreg16 sr2 (\n ^~~~~~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:208: Cannot find file containing module: 'alu'\n alu alu (\n ^~~\n%Error: data/full_repos/permissive/90508539/cpu.v:218: Cannot find file containing module: 'dmem'\n dmem dmem (\n ^~~~\n%Error: data/full_repos/permissive/90508539/cpu.v:226: Cannot find file containing module: 'reg16'\n reg16 dr ( \n ^~~~~\n%Error: Exiting due to 13 error(s)\n" | 309,328 | module | module cpu (
output [7:0] led,
output [15:0] seg0,
output [15:0] seg1,
output [15:0] seg2,
output [15:0] seg3,
output [15:0] seg4,
output [15:0] seg5,
output [15:0] seg6,
output [15:0] seg7,
output [15:0] seg8,
output [15:0] seg9,
output [15:0] sega,
output [15:0] segb,
output [15:0] segc,
output [15:0] segd,
output [15:0] sege,
output [15:0] segf,
input start,
input stop,
input CLK,
input RSTN
);
wire [3:0] ph;
wire [15:0] w_imem, w_dmem;
wire [15:0] w_pc, w_ir, w_sr1, w_sr2, w_alu, w_dr;
wire [15:0] r0, r1, r2, r3, r4, r5, r6, r7;
wire write_dr, write_dmem, write_pc, write_reg;
wire [15:0] w_d;
wire [15:0] w_ir1, w_ir2;
wire [15:0] w_pc1;
wire [15:0] whichr0;
wire [15:0] whichr1;
wire [15:0] whichr2;
wire [15:0] whichr3;
wire [15:0] whichr4;
wire [15:0] whichr5;
wire [15:0] whichr6;
wire [15:0] whichr7;
assign whichr0 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r0;
assign whichr1 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r1;
assign whichr2 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r2;
assign whichr3 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r3;
assign whichr4 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r4;
assign whichr5 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r5;
assign whichr6 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r6;
assign whichr7 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r7;
wire [15:0] whichf1r;
assign whichf1r = ((w_ir2[13:11] == w_ir1[10:8]))
? w_d : w_sr1;
assign led = {4'b0000, ph[3:0]};
assign seg0 = r0;
assign seg1 = r1;
assign seg2 = r2;
assign seg3 = r3;
assign seg4 = r4;
assign seg5 = r5;
assign seg6 = r6;
assign seg7 = r7;
assign seg8 = w_pc;
assign seg9 = w_ir;
assign sega = w_sr1;
assign segb = w_sr2;
assign segc = w_alu;
assign segd = w_dr;
assign sege = 16'h0000;
assign segf = 16'h0000;
assign write_dr = ph[2] &&
(w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001);
assign write_dmem = ph[2] &&
(w_ir1[15:11]==5'b00000) && (w_ir1[4:0]==5'b00000);
assign write_pc = ph[3] &&
((w_ir2[15:8]==8'b10000000)
|| (w_ir2[15:11]==5'b10010)
|| (w_ir2[15:11]==5'b10001));
assign write_reg = ph[3] && (
((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00010))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00100))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00101))
|| (w_ir2[15:14]==2'b11)
|| ((w_ir2[15:14]==2'b01) && (w_ir2[10:8]==3'b000)));
assign w_d = ((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
? w_dr : w_alu;
sm sm (
.q(ph),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc (
.q(w_pc),
.load(write_pc),
.inc(ph[0]),
.d(w_alu),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc1 (
.q(w_pc1),
.load(ph[1]),
.inc(1'b0),
.d(w_pc),
.CLK(CLK),
.RSTN(RSTN)
);
imem imem (
.address(w_pc),
.clock(~CLK),
.q(w_imem)
);
reg16 ir (
.q(w_ir),
.load(ph[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
reg16 ir1 (
.q(w_ir1),
.load(ph[1]),
.d(w_ir),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
reg16 ir2 (
.q(w_ir2),
.load(ph[2]),
.d(w_ir1),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
regfile regfile (
.q0(r0),
.q1(r1),
.q2(r2),
.q3(r3),
.q4(r4),
.q5(r5),
.q6(r6),
.q7(r7),
.load(write_reg),
.wsel(w_ir2[13:11]),
.d(w_d),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1 (
.q(w_sr1),
.load(ph[1]),
.d0(whichr0),
.d1(whichr1),
.d2(whichr2),
.d3(whichr3),
.d4(whichr4),
.d5(whichr5),
.d6(whichr6),
.d7(whichr7),
.sel(w_ir[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2 (
.q(w_sr2),
.load(ph[1]),
.d0(r0),
.d1(r1),
.d2(r2),
.d3(r3),
.d4(r4),
.d5(r5),
.d6(r6),
.d7(r7),
.sel(w_ir[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu (
.q(w_alu),
.sr1(whichf1r),
.sr2(w_sr2),
.pc(w_pc1),
.ir(w_ir1),
.CLK(CLK),
.RSTN(RSTN)
);
dmem dmem (
.address(whichf1r),
.clock(~CLK),
.data(w_sr2),
.wren(write_dmem),
.q(w_dmem)
);
reg16 dr (
.q(w_dr),
.load(write_dr),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | module cpu (
output [7:0] led,
output [15:0] seg0,
output [15:0] seg1,
output [15:0] seg2,
output [15:0] seg3,
output [15:0] seg4,
output [15:0] seg5,
output [15:0] seg6,
output [15:0] seg7,
output [15:0] seg8,
output [15:0] seg9,
output [15:0] sega,
output [15:0] segb,
output [15:0] segc,
output [15:0] segd,
output [15:0] sege,
output [15:0] segf,
input start,
input stop,
input CLK,
input RSTN
); |
wire [3:0] ph;
wire [15:0] w_imem, w_dmem;
wire [15:0] w_pc, w_ir, w_sr1, w_sr2, w_alu, w_dr;
wire [15:0] r0, r1, r2, r3, r4, r5, r6, r7;
wire write_dr, write_dmem, write_pc, write_reg;
wire [15:0] w_d;
wire [15:0] w_ir1, w_ir2;
wire [15:0] w_pc1;
wire [15:0] whichr0;
wire [15:0] whichr1;
wire [15:0] whichr2;
wire [15:0] whichr3;
wire [15:0] whichr4;
wire [15:0] whichr5;
wire [15:0] whichr6;
wire [15:0] whichr7;
assign whichr0 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r0;
assign whichr1 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r1;
assign whichr2 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r2;
assign whichr3 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r3;
assign whichr4 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r4;
assign whichr5 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r5;
assign whichr6 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r6;
assign whichr7 = (w_ir2[13:11] == w_ir[10:8]) ? w_d : r7;
wire [15:0] whichf1r;
assign whichf1r = ((w_ir2[13:11] == w_ir1[10:8]))
? w_d : w_sr1;
assign led = {4'b0000, ph[3:0]};
assign seg0 = r0;
assign seg1 = r1;
assign seg2 = r2;
assign seg3 = r3;
assign seg4 = r4;
assign seg5 = r5;
assign seg6 = r6;
assign seg7 = r7;
assign seg8 = w_pc;
assign seg9 = w_ir;
assign sega = w_sr1;
assign segb = w_sr2;
assign segc = w_alu;
assign segd = w_dr;
assign sege = 16'h0000;
assign segf = 16'h0000;
assign write_dr = ph[2] &&
(w_ir1[15:14]==2'b00) && (w_ir1[7:0]==8'b00000001);
assign write_dmem = ph[2] &&
(w_ir1[15:11]==5'b00000) && (w_ir1[4:0]==5'b00000);
assign write_pc = ph[3] &&
((w_ir2[15:8]==8'b10000000)
|| (w_ir2[15:11]==5'b10010)
|| (w_ir2[15:11]==5'b10001));
assign write_reg = ph[3] && (
((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00010))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00100))
|| ((w_ir2[15:14]==2'b00) && (w_ir2[4:0]==5'b00101))
|| (w_ir2[15:14]==2'b11)
|| ((w_ir2[15:14]==2'b01) && (w_ir2[10:8]==3'b000)));
assign w_d = ((w_ir2[15:14]==2'b00) && (w_ir2[7:0]==8'b00000001))
? w_dr : w_alu;
sm sm (
.q(ph),
.start(start),
.stop(stop),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc (
.q(w_pc),
.load(write_pc),
.inc(ph[0]),
.d(w_alu),
.CLK(CLK),
.RSTN(RSTN)
);
count16rle pc1 (
.q(w_pc1),
.load(ph[1]),
.inc(1'b0),
.d(w_pc),
.CLK(CLK),
.RSTN(RSTN)
);
imem imem (
.address(w_pc),
.clock(~CLK),
.q(w_imem)
);
reg16 ir (
.q(w_ir),
.load(ph[0]),
.d(w_imem),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
reg16 ir1 (
.q(w_ir1),
.load(ph[1]),
.d(w_ir),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
reg16 ir2 (
.q(w_ir2),
.load(ph[2]),
.d(w_ir1),
.CLK(CLK),
.RSTN(RSTN),
.Bjudge(write_pc)
);
regfile regfile (
.q0(r0),
.q1(r1),
.q2(r2),
.q3(r3),
.q4(r4),
.q5(r5),
.q6(r6),
.q7(r7),
.load(write_reg),
.wsel(w_ir2[13:11]),
.d(w_d),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr1 (
.q(w_sr1),
.load(ph[1]),
.d0(whichr0),
.d1(whichr1),
.d2(whichr2),
.d3(whichr3),
.d4(whichr4),
.d5(whichr5),
.d6(whichr6),
.d7(whichr7),
.sel(w_ir[10:8]),
.CLK(CLK),
.RSTN(RSTN)
);
muxreg16 sr2 (
.q(w_sr2),
.load(ph[1]),
.d0(r0),
.d1(r1),
.d2(r2),
.d3(r3),
.d4(r4),
.d5(r5),
.d6(r6),
.d7(r7),
.sel(w_ir[7:5]),
.CLK(CLK),
.RSTN(RSTN)
);
alu alu (
.q(w_alu),
.sr1(whichf1r),
.sr2(w_sr2),
.pc(w_pc1),
.ir(w_ir1),
.CLK(CLK),
.RSTN(RSTN)
);
dmem dmem (
.address(whichf1r),
.clock(~CLK),
.data(w_sr2),
.wren(write_dmem),
.q(w_dmem)
);
reg16 dr (
.q(w_dr),
.load(write_dr),
.d(w_dmem),
.CLK(CLK),
.RSTN(RSTN)
);
endmodule | 0 |
140,578 | data/full_repos/permissive/90508539/sm.v | 90,508,539 | sm.v | v | 28 | 54 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/23ac7791-e32d-4b09-a44c-ca344830cec8.xml | null | 309,346 | module | module sm (
output reg [3:0] q,
input start,
input stop,
input CLK,
input RSTN
);
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
casex ({q,start,stop})
6'b0000_1_x: q <= 4'b0001;
6'b0001_x_x: q <= 4'b0011;
6'b0011_x_x: q <= 4'b0111;
6'b0111_x_x: q <= 4'b1111;
6'b1111_x_0: q <= 4'b1111;
6'b1111_x_1: q <= 4'b1110;
6'b1110_x_x: q <= 4'b1100;
6'b1100_x_x: q <= 4'b1000;
6'b1000_x_x: q <= 4'b0000;
endcase
end
end
endmodule | module sm (
output reg [3:0] q,
input start,
input stop,
input CLK,
input RSTN
); |
always @(posedge CLK or negedge RSTN)
begin
if (!RSTN) begin
q <= 0;
end
else begin
casex ({q,start,stop})
6'b0000_1_x: q <= 4'b0001;
6'b0001_x_x: q <= 4'b0011;
6'b0011_x_x: q <= 4'b0111;
6'b0111_x_x: q <= 4'b1111;
6'b1111_x_0: q <= 4'b1111;
6'b1111_x_1: q <= 4'b1110;
6'b1110_x_x: q <= 4'b1100;
6'b1100_x_x: q <= 4'b1000;
6'b1000_x_x: q <= 4'b0000;
endcase
end
end
endmodule | 0 |
140,579 | data/full_repos/permissive/90611392/keccak_chi_iota.v | 90,611,392 | keccak_chi_iota.v | v | 260 | 136 | [] | [] | [] | null | line:21: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:103: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.sv\n keccak_sbox\n keccak_sbox.v\n keccak_sbox.sv\n obj_dir/keccak_sbox\n obj_dir/keccak_sbox.v\n obj_dir/keccak_sbox.sv\n%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:119: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,348 | module | module keccak_chi_iota #(
parameter SHARES = 2,
parameter SLICES = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter LESS_RAND = 0,
parameter DOM_PIPELINE = 0
)
(
input wire ClkxCI,
input wire EnablexSI,
input wire RstxRBI,
input wire[SHARES*25*SLICES-1:0] SlicesxDI,
input wire[(SHARES*SHARES-SHARES)/2*25*SLICES-1:0] ZxDI,
input wire[SLICES-1:0] IotaRCxDI,
output reg[SHARES*25*SLICES-1:0] SlicesxDO
);
localparam W = SLICES;
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction
generate
if(SHARES == 1) begin
always @(*) begin : CHI_UNPROTECTED_COMB
integer x0, x1, x2, y;
reg[25*W-1:0] S, result;
S = SlicesxDI;
result = {25*W{1'b0}};
for(x0=0; x0 < 5; x0=x0+1) begin : SBOX_LOOP
x1 = (x0 + 1) % 5;
x2 = (x0 + 2) % 5;
for(y=0; y < 5; y=y+1) begin
result[Idx(x0,y) +: W] = S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
if(x0 == 0 && y == 0) begin
result[0 +: W] = result[0 +: W] ^ IotaRCxDI;
end
end
end
SlicesxDO = result;
end
end else if (1) begin
genvar y, z;
function integer RowIdx(input integer share_nr, input integer idx_x, input integer idx_y);
RowIdx = share_nr*25*SLICES + (5*idx_x + idx_y)*SLICES;
endfunction
for(z = 0; z < SLICES; z=z+1) begin : GEN_SLICES
for (y = 0; y < 5; y=y+1) begin : GEN_ROWS
reg[SHARES*5-1 : 0] RowsInxD;
wire[SHARES*5-1 : 0] RowsOutxD;
reg[5*(SHARES*SHARES-SHARES)/2-1 : 0] RowsRandxD;
always @(*) begin : ROW_SEL_IN
integer i;
for (i = 0; i < SHARES; i=i+1) begin
RowsInxD[i*5 + 0] = SlicesxDI[RowIdx(i,0,y) + z];
RowsInxD[i*5 + 1] = SlicesxDI[RowIdx(i,1,y) + z];
RowsInxD[i*5 + 2] = SlicesxDI[RowIdx(i,2,y) + z];
RowsInxD[i*5 + 3] = SlicesxDI[RowIdx(i,3,y) + z];
RowsInxD[i*5 + 4] = SlicesxDI[RowIdx(i,4,y) + z];
end
RowsRandxD = ZxDI[25*z + 5*y +: 5*(SHARES*SHARES - SHARES)/2];
end
always @(*) begin : ROW_SEL_OUT
integer i;
for (i = 0; i < SHARES; i=i+1) begin
SlicesxDO[RowIdx(i,0,y) + z] = RowsOutxD[i*5 + 0];
SlicesxDO[RowIdx(i,1,y) + z] = RowsOutxD[i*5 + 1];
SlicesxDO[RowIdx(i,2,y) + z] = RowsOutxD[i*5 + 2];
SlicesxDO[RowIdx(i,3,y) + z] = RowsOutxD[i*5 + 3];
SlicesxDO[RowIdx(i,4,y) + z] = RowsOutxD[i*5 + 4];
end
end
if (y == 0) begin
keccak_sbox
#(.SHARES(SHARES)
, .CHI_DOUBLE_CLK(CHI_DOUBLE_CLK)
, .LESS_RAND(LESS_RAND)
, .DOM_PIPELINE(DOM_PIPELINE)
, .IOTA_XOR(1)
) sbox
( .ClkxCI(ClkxCI)
, .RstxRBI(RstxRBI)
, .EnablexSI(EnablexSI)
, .IotaRCxDI(IotaRCxDI[z])
, .InputxDI(RowsInxD)
, .ZxDI(RowsRandxD)
, .OutputxDO(RowsOutxD)
);
end else begin
keccak_sbox
#(.SHARES(SHARES)
, .CHI_DOUBLE_CLK(CHI_DOUBLE_CLK)
, .LESS_RAND(LESS_RAND)
, .DOM_PIPELINE(DOM_PIPELINE)
, .IOTA_XOR(0)
) sbox
( .ClkxCI(ClkxCI)
, .RstxRBI(RstxRBI)
, .EnablexSI(EnablexSI)
, .IotaRCxDI(1'b0)
, .InputxDI(RowsInxD)
, .ZxDI(RowsRandxD)
, .OutputxDO(RowsOutxD)
);
end
end
end
end
else begin
localparam NUM_FF = DOM_PIPELINE ? (SHARES*SHARES)*25*W
: (SHARES*SHARES - SHARES)*25*W;
reg[NUM_FF-1:0] FFxDN, FFxDP;
if(CHI_DOUBLE_CLK) begin
always @(negedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) FFxDP <= {NUM_FF{1'b0}};
else if(EnablexSI) FFxDP <= FFxDN;
end
end
else begin
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) FFxDP <= {NUM_FF{1'b0}};
else if(EnablexSI) FFxDP <= FFxDN;
end
end
always @(*) begin : SBOXES
integer i, j, x0, x1, x2, y, ff_idx;
reg[W-1:0] result;
reg[25*W-1:0] S, T;
reg[SHARES*25*W-1:0] SlicesxD;
FFxDN = {NUM_FF{1'b0}};
for(x0=0; x0 < 5; x0=x0+1) begin
x1 = (x0 + 1) % 5;
x2 = (x0 + 2) % 5;
for(y=0; y < 5; y=y+1) begin
for(i=0; i < SHARES; i=i+1) begin
result = {W{1'b0}};
S = SlicesxDI[i*25*W +: 25*W];
for(j=0; j < SHARES; j=j+1) begin
T = SlicesxDI[j*25*W +: 25*W];
if(i==j) begin
if(DOM_PIPELINE) begin
ff_idx = i*SHARES+i;
if(LESS_RAND && i >= SHARES-2) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
end
else begin
if(LESS_RAND && i >= SHARES-2) begin
result = result ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
else begin
result = result ^ S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
end
end
else if(i < j) begin
if(DOM_PIPELINE)
ff_idx = i*SHARES + j;
else
ff_idx = i*(SHARES-1) + j-1;
if(LESS_RAND && (i + j*(j-1)/2) == (SHARES*SHARES-SHARES)/2-1) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W]) ^ S[Idx(x0,y) +: W];
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W])
^ ZxDI[(i + j*(j-1)/2)*25*W + Idx(x0,y) +: W];
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
if(i == 0 && x0 == 0 && y == 0 && (i + j*(j-1)/2)==0) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = IotaRCxDI ^ FFxDN[ff_idx*25*W + Idx(x0,y) +: W];
end
end
else if(i > j) begin
if(DOM_PIPELINE)
ff_idx = i*SHARES + j;
else
ff_idx = i*(SHARES-1) + j;
if(LESS_RAND && (j + i*(i-1)/2) == (SHARES*SHARES-SHARES)/2-1) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W]) ^ S[Idx(x0,y) +: W];
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W])
^ ZxDI[(j + i*(i-1)/2)*25*W + Idx(x0,y) +: W];
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
end
end
SlicesxDO[i*25*W + Idx(x0,y) +: W] = result;
end
end
end
end
end
endgenerate
endmodule | module keccak_chi_iota #(
parameter SHARES = 2,
parameter SLICES = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter LESS_RAND = 0,
parameter DOM_PIPELINE = 0
)
(
input wire ClkxCI,
input wire EnablexSI,
input wire RstxRBI,
input wire[SHARES*25*SLICES-1:0] SlicesxDI,
input wire[(SHARES*SHARES-SHARES)/2*25*SLICES-1:0] ZxDI,
input wire[SLICES-1:0] IotaRCxDI,
output reg[SHARES*25*SLICES-1:0] SlicesxDO
); |
localparam W = SLICES;
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction
generate
if(SHARES == 1) begin
always @(*) begin : CHI_UNPROTECTED_COMB
integer x0, x1, x2, y;
reg[25*W-1:0] S, result;
S = SlicesxDI;
result = {25*W{1'b0}};
for(x0=0; x0 < 5; x0=x0+1) begin : SBOX_LOOP
x1 = (x0 + 1) % 5;
x2 = (x0 + 2) % 5;
for(y=0; y < 5; y=y+1) begin
result[Idx(x0,y) +: W] = S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
if(x0 == 0 && y == 0) begin
result[0 +: W] = result[0 +: W] ^ IotaRCxDI;
end
end
end
SlicesxDO = result;
end
end else if (1) begin
genvar y, z;
function integer RowIdx(input integer share_nr, input integer idx_x, input integer idx_y);
RowIdx = share_nr*25*SLICES + (5*idx_x + idx_y)*SLICES;
endfunction
for(z = 0; z < SLICES; z=z+1) begin : GEN_SLICES
for (y = 0; y < 5; y=y+1) begin : GEN_ROWS
reg[SHARES*5-1 : 0] RowsInxD;
wire[SHARES*5-1 : 0] RowsOutxD;
reg[5*(SHARES*SHARES-SHARES)/2-1 : 0] RowsRandxD;
always @(*) begin : ROW_SEL_IN
integer i;
for (i = 0; i < SHARES; i=i+1) begin
RowsInxD[i*5 + 0] = SlicesxDI[RowIdx(i,0,y) + z];
RowsInxD[i*5 + 1] = SlicesxDI[RowIdx(i,1,y) + z];
RowsInxD[i*5 + 2] = SlicesxDI[RowIdx(i,2,y) + z];
RowsInxD[i*5 + 3] = SlicesxDI[RowIdx(i,3,y) + z];
RowsInxD[i*5 + 4] = SlicesxDI[RowIdx(i,4,y) + z];
end
RowsRandxD = ZxDI[25*z + 5*y +: 5*(SHARES*SHARES - SHARES)/2];
end
always @(*) begin : ROW_SEL_OUT
integer i;
for (i = 0; i < SHARES; i=i+1) begin
SlicesxDO[RowIdx(i,0,y) + z] = RowsOutxD[i*5 + 0];
SlicesxDO[RowIdx(i,1,y) + z] = RowsOutxD[i*5 + 1];
SlicesxDO[RowIdx(i,2,y) + z] = RowsOutxD[i*5 + 2];
SlicesxDO[RowIdx(i,3,y) + z] = RowsOutxD[i*5 + 3];
SlicesxDO[RowIdx(i,4,y) + z] = RowsOutxD[i*5 + 4];
end
end
if (y == 0) begin
keccak_sbox
#(.SHARES(SHARES)
, .CHI_DOUBLE_CLK(CHI_DOUBLE_CLK)
, .LESS_RAND(LESS_RAND)
, .DOM_PIPELINE(DOM_PIPELINE)
, .IOTA_XOR(1)
) sbox
( .ClkxCI(ClkxCI)
, .RstxRBI(RstxRBI)
, .EnablexSI(EnablexSI)
, .IotaRCxDI(IotaRCxDI[z])
, .InputxDI(RowsInxD)
, .ZxDI(RowsRandxD)
, .OutputxDO(RowsOutxD)
);
end else begin
keccak_sbox
#(.SHARES(SHARES)
, .CHI_DOUBLE_CLK(CHI_DOUBLE_CLK)
, .LESS_RAND(LESS_RAND)
, .DOM_PIPELINE(DOM_PIPELINE)
, .IOTA_XOR(0)
) sbox
( .ClkxCI(ClkxCI)
, .RstxRBI(RstxRBI)
, .EnablexSI(EnablexSI)
, .IotaRCxDI(1'b0)
, .InputxDI(RowsInxD)
, .ZxDI(RowsRandxD)
, .OutputxDO(RowsOutxD)
);
end
end
end
end
else begin
localparam NUM_FF = DOM_PIPELINE ? (SHARES*SHARES)*25*W
: (SHARES*SHARES - SHARES)*25*W;
reg[NUM_FF-1:0] FFxDN, FFxDP;
if(CHI_DOUBLE_CLK) begin
always @(negedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) FFxDP <= {NUM_FF{1'b0}};
else if(EnablexSI) FFxDP <= FFxDN;
end
end
else begin
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) FFxDP <= {NUM_FF{1'b0}};
else if(EnablexSI) FFxDP <= FFxDN;
end
end
always @(*) begin : SBOXES
integer i, j, x0, x1, x2, y, ff_idx;
reg[W-1:0] result;
reg[25*W-1:0] S, T;
reg[SHARES*25*W-1:0] SlicesxD;
FFxDN = {NUM_FF{1'b0}};
for(x0=0; x0 < 5; x0=x0+1) begin
x1 = (x0 + 1) % 5;
x2 = (x0 + 2) % 5;
for(y=0; y < 5; y=y+1) begin
for(i=0; i < SHARES; i=i+1) begin
result = {W{1'b0}};
S = SlicesxDI[i*25*W +: 25*W];
for(j=0; j < SHARES; j=j+1) begin
T = SlicesxDI[j*25*W +: 25*W];
if(i==j) begin
if(DOM_PIPELINE) begin
ff_idx = i*SHARES+i;
if(LESS_RAND && i >= SHARES-2) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
end
else begin
if(LESS_RAND && i >= SHARES-2) begin
result = result ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
else begin
result = result ^ S[Idx(x0,y) +: W] ^ (~S[Idx(x1,y) +: W] & S[Idx(x2,y) +: W]);
end
end
end
else if(i < j) begin
if(DOM_PIPELINE)
ff_idx = i*SHARES + j;
else
ff_idx = i*(SHARES-1) + j-1;
if(LESS_RAND && (i + j*(j-1)/2) == (SHARES*SHARES-SHARES)/2-1) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W]) ^ S[Idx(x0,y) +: W];
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W])
^ ZxDI[(i + j*(j-1)/2)*25*W + Idx(x0,y) +: W];
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
if(i == 0 && x0 == 0 && y == 0 && (i + j*(j-1)/2)==0) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W] = IotaRCxDI ^ FFxDN[ff_idx*25*W + Idx(x0,y) +: W];
end
end
else if(i > j) begin
if(DOM_PIPELINE)
ff_idx = i*SHARES + j;
else
ff_idx = i*(SHARES-1) + j;
if(LESS_RAND && (j + i*(i-1)/2) == (SHARES*SHARES-SHARES)/2-1) begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W]) ^ S[Idx(x0,y) +: W];
end
else begin
FFxDN[ff_idx*25*W + Idx(x0,y) +: W]
= (S[Idx(x1,y) +: W] & T[Idx(x2,y) +: W])
^ ZxDI[(j + i*(i-1)/2)*25*W + Idx(x0,y) +: W];
end
result = result ^ FFxDP[ff_idx*25*W + Idx(x0,y) +: W];
end
end
SlicesxDO[i*25*W + Idx(x0,y) +: W] = result;
end
end
end
end
end
endgenerate
endmodule | 0 |
140,580 | data/full_repos/permissive/90611392/keccak_chi_iota.v | 90,611,392 | keccak_chi_iota.v | v | 260 | 136 | [] | [] | [] | null | line:21: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:103: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.sv\n keccak_sbox\n keccak_sbox.v\n keccak_sbox.sv\n obj_dir/keccak_sbox\n obj_dir/keccak_sbox.v\n obj_dir/keccak_sbox.sv\n%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:119: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,348 | function | function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction | function integer Idx(input integer x, input integer y); |
Idx = (5*x+y)*W;
endfunction | 0 |
140,581 | data/full_repos/permissive/90611392/keccak_chi_iota.v | 90,611,392 | keccak_chi_iota.v | v | 260 | 136 | [] | [] | [] | null | line:21: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:103: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_sbox.sv\n keccak_sbox\n keccak_sbox.v\n keccak_sbox.sv\n obj_dir/keccak_sbox\n obj_dir/keccak_sbox.v\n obj_dir/keccak_sbox.sv\n%Error: data/full_repos/permissive/90611392/keccak_chi_iota.v:119: Cannot find file containing module: 'keccak_sbox'\n keccak_sbox\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,348 | function | function integer RowIdx(input integer share_nr, input integer idx_x, input integer idx_y);
RowIdx = share_nr*25*SLICES + (5*idx_x + idx_y)*SLICES;
endfunction | function integer RowIdx(input integer share_nr, input integer idx_x, input integer idx_y); |
RowIdx = share_nr*25*SLICES + (5*idx_x + idx_y)*SLICES;
endfunction | 0 |
140,582 | data/full_repos/permissive/90611392/keccak_control.v | 90,611,392 | keccak_control.v | v | 430 | 111 | [] | [] | [] | null | line:15 column:2: Illegal character '\x00' | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_control.v:77: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:137: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_control\n == (l_cnt / ABSORB_LANES));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:200: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP == ABSORBCNT_MAX) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:267: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:386: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDN\' generates 5 bits.\n : ... In instance keccak_control\n RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:391: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDP\' generates 5 bits.\n : ... In instance keccak_control\nwire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));\n ^~\n%Error: data/full_repos/permissive/90611392/keccak_control.v:409: Cannot find file containing module: \'keccak_roundconstant\'\nkeccak_roundconstant #(\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.sv\n keccak_roundconstant\n keccak_roundconstant.v\n keccak_roundconstant.sv\n obj_dir/keccak_roundconstant\n obj_dir/keccak_roundconstant.v\n obj_dir/keccak_roundconstant.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 309,349 | module | module keccak_control #(
parameter RATE = 128,
parameter W = 16,
parameter SHARES = 2,
parameter ABSORB_LANES = RATE/W,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 0,
parameter THETA_ITERATIVE = 0,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter SLICES_PARALLEL = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter DOM_PIPELINE = 1,
parameter ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W,
parameter THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES,
parameter CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W,
parameter CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_SLICES) ? 1 : 0
)(
input wire ClkxCI,
input wire RstxRBI,
input wire StartAbsorbxSI,
input wire StartSqueezexSI,
input wire RandomnessAvailablexSI,
output wire[CHI_SLICES-1:0] IotaRCxDO,
output wire[33:0] StateCtrlxSO,
output reg ReadyxSO
);
function integer clog2(input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer max(input integer first, input integer second);
max = first > second ? first : second;
endfunction
localparam USE_LAMBDA_STEPS = (SHARES > 1 || CHI_IOTA_ITERATIVE);
localparam SBOX_1CYCLE = (SHARES==1 || CHI_DOUBLE_CLK);
localparam ROUNDS = 12 + 2 * clog2(W);
localparam CHICNT_BITWIDTH = SBOX_1CYCLE ? clog2(W/CHI_SLICES) : clog2(2*W/CHI_SLICES);
localparam CHICNT_RST = DOM_PIPELINE ? (W/CHI_SLICES) :
(SBOX_1CYCLE ? (W/CHI_SLICES - 1) : (2*W/CHI_SLICES - 1));
localparam THETACNT_BITWIDTH = clog2(W/THETA_SLICES);
localparam THETACNT_RST = W/THETA_SLICES - 1;
localparam ABSORBCNT_BITWIDTH = clog2( (RATE/W)/ABSORB_LANES * W/ABSORB_SLICES);
localparam ABSORBCNT_BITWIDTH_SLICES = clog2(W/ABSORB_SLICES);
localparam ABSORBCNT_MAX = (RATE/W)/ABSORB_LANES * W/ABSORB_SLICES - 1;
localparam RHOCNT_BITWIDTH = RHO_PI_ITERATIVE ? clog2(W) : 0;
localparam RSTCNT_BITWIDTH = RESET_ITERATIVE ? clog2(W) : 0;
localparam RSTCNT_MAX = W-1;
localparam MAXCNT_BITWIDTH = max(max(max(max(ABSORBCNT_BITWIDTH,
THETACNT_BITWIDTH), RHOCNT_BITWIDTH), CHICNT_BITWIDTH),
RSTCNT_BITWIDTH);
localparam [0:25*8-1] ROTATION_OFFSETS = {
8'd00, 8'd36, 8'd03, 8'd41, 8'd18,
8'd01, 8'd44, 8'd10, 8'd45, 8'd02,
8'd62, 8'd06, 8'd43, 8'd15, 8'd61,
8'd28, 8'd55, 8'd25, 8'd21, 8'd56,
8'd27, 8'd20, 8'd39, 8'd08, 8'd14
};
localparam
RESET = 7'h01,
IDLE = 7'h02,
RHOPI = 7'h04,
THETA_CHI_IOTA = 7'h08,
THETA = 7'h10,
LAMBDA = 7'h20,
CHI_IOTA = 7'h40;
reg[MAXCNT_BITWIDTH:0] CounterxDP, CounterxDN;
reg[6:0] CtrlStatexDP, CtrlStatexDN;
reg[4:0] RoundCountxDP, RoundCountxDN;
reg RoundCountLastxDP;
reg enableRoundCountxS;
reg SetInitialAbsorbDonexS;
reg[24:0] ctrl_enable_lane;
reg ctrl_enable_absorb;
reg ctrl_enable_lambda;
reg ctrl_enable_theta;
reg ctrl_enable_rhopi;
reg ctrl_enable_chi_iota;
reg ctrl_theta_last;
reg ctrl_enable_absorb_theta;
reg ctrl_enable_DOM_ff;
reg ctrl_reset_state;
assign StateCtrlxSO = { ctrl_enable_lane,
ctrl_enable_absorb,
ctrl_enable_lambda,
ctrl_enable_theta,
ctrl_enable_rhopi,
ctrl_enable_chi_iota,
ctrl_theta_last,
ctrl_enable_absorb_theta,
ctrl_enable_DOM_ff,
ctrl_reset_state};
task enable_absorb_lanes; begin : ENABLE_ABSORB_LANES
integer y, x, l_cnt, l_nr;
for(y = 0; y < 5; y=y+1) begin
for(x = 0; x < 5; x=x+1) begin
l_cnt = x + 5*y;
l_nr = getLaneNr(x,y);
ctrl_enable_lane[l_nr] =
(CounterxDP[ABSORBCNT_BITWIDTH:ABSORBCNT_BITWIDTH_SLICES]
== (l_cnt / ABSORB_LANES));
end
end
end endtask
task control_theta; begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_theta = 1;
CounterxDN = CounterxDP + 1;
if(CounterxDP == THETACNT_RST) begin
ctrl_theta_last = 1;
CounterxDN = 0;
if(CHI_IOTA_ITERATIVE)
CtrlStatexDN = RHOPI;
else
CtrlStatexDN = CHI_IOTA;
end
end endtask
always @(*) begin : FSM
CtrlStatexDN = CtrlStatexDP;
CounterxDN = CounterxDP;
ctrl_enable_lane = 25'b0;
ctrl_enable_absorb = 0;
ctrl_enable_lambda = 0;
ctrl_enable_theta = 0;
ctrl_enable_rhopi = 0;
ctrl_enable_chi_iota = 0;
ctrl_theta_last = 0;
ctrl_enable_absorb_theta = 0;
ctrl_enable_DOM_ff = 0;
ctrl_reset_state = 0;
enableRoundCountxS = 0;
ReadyxSO = 0;
SetInitialAbsorbDonexS = 0;
case(CtrlStatexDP)
RESET: begin
ctrl_reset_state = 1;
ctrl_enable_lane = {25{1'b1}};
CounterxDN = CounterxDP + 1;
if(CounterxDP == RSTCNT_MAX) begin
CounterxDN = 0;
CtrlStatexDN = IDLE;
end
end
IDLE: begin
ReadyxSO = 1;
if(StartAbsorbxSI) begin
ctrl_enable_absorb = 1;
enable_absorb_lanes;
if(ABSORB_LANES != RATE/W) begin
CounterxDN = CounterxDP + 1;
if(CounterxDP == ABSORBCNT_MAX) begin
CounterxDN = 0;
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE)
CtrlStatexDN = THETA;
else if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
else if(ABSORB_ITERATIVE) begin
ctrl_enable_absorb = 0;
ctrl_enable_absorb_theta = 1;
control_theta;
end
else if(THETA_ITERATIVE || RHO_PI_ITERATIVE) begin
CtrlStatexDN = THETA;
end
else begin
if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
else if(StartSqueezexSI) begin
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE) begin
CtrlStatexDN = THETA;
end
else begin
if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
end
LAMBDA: begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_lambda = 1;
CtrlStatexDN = CHI_IOTA;
end
THETA: begin
control_theta;
end
RHOPI: begin
if(RHO_PI_ITERATIVE) begin : RHO
integer i;
ctrl_enable_rhopi = 1;
CounterxDN = CounterxDP + 1;
for(i=0; i<25; i=i+1) begin
if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin
ctrl_enable_lane[i] = 1'b1;
end
end
if(CounterxDP == W-1) begin
CounterxDN = 0;
if(CONNECT_ABSORB_CHI)begin
SetInitialAbsorbDonexS = 1;
CtrlStatexDN = THETA_CHI_IOTA;
end
else begin
CtrlStatexDN = CHI_IOTA;
end
end
end
else begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_rhopi = 1;
CtrlStatexDN = CHI_IOTA;
if(CONNECT_ABSORB_CHI)begin
SetInitialAbsorbDonexS = 1;
CtrlStatexDN = THETA_CHI_IOTA;
end
end
end
THETA_CHI_IOTA: begin
if(CONNECT_ABSORB_CHI) begin
if(DOM_PIPELINE) begin
if(RoundCountLastxDP && StartAbsorbxSI && (CounterxDP != 0)) begin
ReadyxSO = 1;
end
end
else if(SBOX_1CYCLE) begin
if(RoundCountLastxDP)
ReadyxSO = 1;
end
else begin
if(RoundCountLastxDP && CounterxDP[0])
ReadyxSO = 1;
end
if((ReadyxSO && StartAbsorbxSI)
|| !RoundCountLastxDP
|| (!SBOX_1CYCLE && !CounterxDP[0])
|| (DOM_PIPELINE && (CounterxDP == 0))) begin
CounterxDN = CounterxDP + 1;
ctrl_enable_DOM_ff = 1;
if((CounterxDP[0] == 1) || SBOX_1CYCLE || DOM_PIPELINE) begin
ctrl_enable_chi_iota = 1;
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_theta = 1;
ctrl_enable_absorb_theta = ReadyxSO;
if(DOM_PIPELINE) begin : pippi
reg delay;
delay = (CounterxDP != 0);
ctrl_enable_theta = delay;
ctrl_enable_absorb_theta = delay && ReadyxSO;
end
end
if(CounterxDP == CHICNT_RST) begin
CounterxDN = 0;
enableRoundCountxS = 1;
ctrl_theta_last = 1;
CtrlStatexDN = RHOPI;
end
end
end
end
CHI_IOTA: begin
CounterxDN = CounterxDP + 1;
ctrl_enable_DOM_ff = 1;
if(CounterxDP % 2 == 1 || SBOX_1CYCLE || DOM_PIPELINE) begin
ctrl_enable_chi_iota = 1;
ctrl_enable_lane = {25{1'b1}};
end
if(CounterxDP == CHICNT_RST) begin
CounterxDN = 0;
enableRoundCountxS = 1;
if(RoundCountLastxDP) begin
CtrlStatexDN = IDLE;
end
else begin
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE)
CtrlStatexDN = THETA;
else if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
end
endcase
end
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) begin
CtrlStatexDP <= RESET_ITERATIVE ? RESET : IDLE;
RoundCountxDP <= 0;
RoundCountLastxDP <= 0;
CounterxDP <= 0;
end
else begin
CtrlStatexDP <= CtrlStatexDN;
RoundCountxDP <= RoundCountxDN;
RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);
CounterxDP <= CounterxDN;
end
end
wire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));
always @(*) begin
RoundCountxDN = RoundCountxDP;
if(resetRoundCountxS) RoundCountxDN = 0;
else if(enableRoundCountxS) RoundCountxDN = RoundCountxDP + 1;
end
reg InitialAbsorbDonexDP;
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) InitialAbsorbDonexDP <= 1'b0;
else if(SetInitialAbsorbDonexS) InitialAbsorbDonexDP <= 1'b1;
end
wire[CHI_SLICES-1:0] RCxD;
keccak_roundconstant #(
.W(W),
.SLICES_PARALLEL(CHI_SLICES),
.COUNTER_BITWIDTH(MAXCNT_BITWIDTH),
.DOM_PIPELINE(DOM_PIPELINE),
.SBOX_1CYCLE(SBOX_1CYCLE)
) RC_GEN (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.RoundNrxDI(RoundCountxDP),
.SliceNrxDI(CounterxDP),
.NextSliceNrxDI(CounterxDN),
.ResetRCxSI(resetRoundCountxS),
.EnableRCxSI(ctrl_enable_chi_iota),
.RCxDO(RCxD)
);
assign IotaRCxDO = RCxD & {CHI_SLICES{(!CONNECT_ABSORB_CHI || InitialAbsorbDonexDP)}};
endmodule | module keccak_control #(
parameter RATE = 128,
parameter W = 16,
parameter SHARES = 2,
parameter ABSORB_LANES = RATE/W,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 0,
parameter THETA_ITERATIVE = 0,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter SLICES_PARALLEL = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter DOM_PIPELINE = 1,
parameter ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W,
parameter THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES,
parameter CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W,
parameter CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_SLICES) ? 1 : 0
)(
input wire ClkxCI,
input wire RstxRBI,
input wire StartAbsorbxSI,
input wire StartSqueezexSI,
input wire RandomnessAvailablexSI,
output wire[CHI_SLICES-1:0] IotaRCxDO,
output wire[33:0] StateCtrlxSO,
output reg ReadyxSO
); |
function integer clog2(input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer max(input integer first, input integer second);
max = first > second ? first : second;
endfunction
localparam USE_LAMBDA_STEPS = (SHARES > 1 || CHI_IOTA_ITERATIVE);
localparam SBOX_1CYCLE = (SHARES==1 || CHI_DOUBLE_CLK);
localparam ROUNDS = 12 + 2 * clog2(W);
localparam CHICNT_BITWIDTH = SBOX_1CYCLE ? clog2(W/CHI_SLICES) : clog2(2*W/CHI_SLICES);
localparam CHICNT_RST = DOM_PIPELINE ? (W/CHI_SLICES) :
(SBOX_1CYCLE ? (W/CHI_SLICES - 1) : (2*W/CHI_SLICES - 1));
localparam THETACNT_BITWIDTH = clog2(W/THETA_SLICES);
localparam THETACNT_RST = W/THETA_SLICES - 1;
localparam ABSORBCNT_BITWIDTH = clog2( (RATE/W)/ABSORB_LANES * W/ABSORB_SLICES);
localparam ABSORBCNT_BITWIDTH_SLICES = clog2(W/ABSORB_SLICES);
localparam ABSORBCNT_MAX = (RATE/W)/ABSORB_LANES * W/ABSORB_SLICES - 1;
localparam RHOCNT_BITWIDTH = RHO_PI_ITERATIVE ? clog2(W) : 0;
localparam RSTCNT_BITWIDTH = RESET_ITERATIVE ? clog2(W) : 0;
localparam RSTCNT_MAX = W-1;
localparam MAXCNT_BITWIDTH = max(max(max(max(ABSORBCNT_BITWIDTH,
THETACNT_BITWIDTH), RHOCNT_BITWIDTH), CHICNT_BITWIDTH),
RSTCNT_BITWIDTH);
localparam [0:25*8-1] ROTATION_OFFSETS = {
8'd00, 8'd36, 8'd03, 8'd41, 8'd18,
8'd01, 8'd44, 8'd10, 8'd45, 8'd02,
8'd62, 8'd06, 8'd43, 8'd15, 8'd61,
8'd28, 8'd55, 8'd25, 8'd21, 8'd56,
8'd27, 8'd20, 8'd39, 8'd08, 8'd14
};
localparam
RESET = 7'h01,
IDLE = 7'h02,
RHOPI = 7'h04,
THETA_CHI_IOTA = 7'h08,
THETA = 7'h10,
LAMBDA = 7'h20,
CHI_IOTA = 7'h40;
reg[MAXCNT_BITWIDTH:0] CounterxDP, CounterxDN;
reg[6:0] CtrlStatexDP, CtrlStatexDN;
reg[4:0] RoundCountxDP, RoundCountxDN;
reg RoundCountLastxDP;
reg enableRoundCountxS;
reg SetInitialAbsorbDonexS;
reg[24:0] ctrl_enable_lane;
reg ctrl_enable_absorb;
reg ctrl_enable_lambda;
reg ctrl_enable_theta;
reg ctrl_enable_rhopi;
reg ctrl_enable_chi_iota;
reg ctrl_theta_last;
reg ctrl_enable_absorb_theta;
reg ctrl_enable_DOM_ff;
reg ctrl_reset_state;
assign StateCtrlxSO = { ctrl_enable_lane,
ctrl_enable_absorb,
ctrl_enable_lambda,
ctrl_enable_theta,
ctrl_enable_rhopi,
ctrl_enable_chi_iota,
ctrl_theta_last,
ctrl_enable_absorb_theta,
ctrl_enable_DOM_ff,
ctrl_reset_state};
task enable_absorb_lanes; begin : ENABLE_ABSORB_LANES
integer y, x, l_cnt, l_nr;
for(y = 0; y < 5; y=y+1) begin
for(x = 0; x < 5; x=x+1) begin
l_cnt = x + 5*y;
l_nr = getLaneNr(x,y);
ctrl_enable_lane[l_nr] =
(CounterxDP[ABSORBCNT_BITWIDTH:ABSORBCNT_BITWIDTH_SLICES]
== (l_cnt / ABSORB_LANES));
end
end
end endtask
task control_theta; begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_theta = 1;
CounterxDN = CounterxDP + 1;
if(CounterxDP == THETACNT_RST) begin
ctrl_theta_last = 1;
CounterxDN = 0;
if(CHI_IOTA_ITERATIVE)
CtrlStatexDN = RHOPI;
else
CtrlStatexDN = CHI_IOTA;
end
end endtask
always @(*) begin : FSM
CtrlStatexDN = CtrlStatexDP;
CounterxDN = CounterxDP;
ctrl_enable_lane = 25'b0;
ctrl_enable_absorb = 0;
ctrl_enable_lambda = 0;
ctrl_enable_theta = 0;
ctrl_enable_rhopi = 0;
ctrl_enable_chi_iota = 0;
ctrl_theta_last = 0;
ctrl_enable_absorb_theta = 0;
ctrl_enable_DOM_ff = 0;
ctrl_reset_state = 0;
enableRoundCountxS = 0;
ReadyxSO = 0;
SetInitialAbsorbDonexS = 0;
case(CtrlStatexDP)
RESET: begin
ctrl_reset_state = 1;
ctrl_enable_lane = {25{1'b1}};
CounterxDN = CounterxDP + 1;
if(CounterxDP == RSTCNT_MAX) begin
CounterxDN = 0;
CtrlStatexDN = IDLE;
end
end
IDLE: begin
ReadyxSO = 1;
if(StartAbsorbxSI) begin
ctrl_enable_absorb = 1;
enable_absorb_lanes;
if(ABSORB_LANES != RATE/W) begin
CounterxDN = CounterxDP + 1;
if(CounterxDP == ABSORBCNT_MAX) begin
CounterxDN = 0;
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE)
CtrlStatexDN = THETA;
else if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
else if(ABSORB_ITERATIVE) begin
ctrl_enable_absorb = 0;
ctrl_enable_absorb_theta = 1;
control_theta;
end
else if(THETA_ITERATIVE || RHO_PI_ITERATIVE) begin
CtrlStatexDN = THETA;
end
else begin
if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
else if(StartSqueezexSI) begin
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE) begin
CtrlStatexDN = THETA;
end
else begin
if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
end
LAMBDA: begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_lambda = 1;
CtrlStatexDN = CHI_IOTA;
end
THETA: begin
control_theta;
end
RHOPI: begin
if(RHO_PI_ITERATIVE) begin : RHO
integer i;
ctrl_enable_rhopi = 1;
CounterxDN = CounterxDP + 1;
for(i=0; i<25; i=i+1) begin
if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin
ctrl_enable_lane[i] = 1'b1;
end
end
if(CounterxDP == W-1) begin
CounterxDN = 0;
if(CONNECT_ABSORB_CHI)begin
SetInitialAbsorbDonexS = 1;
CtrlStatexDN = THETA_CHI_IOTA;
end
else begin
CtrlStatexDN = CHI_IOTA;
end
end
end
else begin
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_rhopi = 1;
CtrlStatexDN = CHI_IOTA;
if(CONNECT_ABSORB_CHI)begin
SetInitialAbsorbDonexS = 1;
CtrlStatexDN = THETA_CHI_IOTA;
end
end
end
THETA_CHI_IOTA: begin
if(CONNECT_ABSORB_CHI) begin
if(DOM_PIPELINE) begin
if(RoundCountLastxDP && StartAbsorbxSI && (CounterxDP != 0)) begin
ReadyxSO = 1;
end
end
else if(SBOX_1CYCLE) begin
if(RoundCountLastxDP)
ReadyxSO = 1;
end
else begin
if(RoundCountLastxDP && CounterxDP[0])
ReadyxSO = 1;
end
if((ReadyxSO && StartAbsorbxSI)
|| !RoundCountLastxDP
|| (!SBOX_1CYCLE && !CounterxDP[0])
|| (DOM_PIPELINE && (CounterxDP == 0))) begin
CounterxDN = CounterxDP + 1;
ctrl_enable_DOM_ff = 1;
if((CounterxDP[0] == 1) || SBOX_1CYCLE || DOM_PIPELINE) begin
ctrl_enable_chi_iota = 1;
ctrl_enable_lane = {25{1'b1}};
ctrl_enable_theta = 1;
ctrl_enable_absorb_theta = ReadyxSO;
if(DOM_PIPELINE) begin : pippi
reg delay;
delay = (CounterxDP != 0);
ctrl_enable_theta = delay;
ctrl_enable_absorb_theta = delay && ReadyxSO;
end
end
if(CounterxDP == CHICNT_RST) begin
CounterxDN = 0;
enableRoundCountxS = 1;
ctrl_theta_last = 1;
CtrlStatexDN = RHOPI;
end
end
end
end
CHI_IOTA: begin
CounterxDN = CounterxDP + 1;
ctrl_enable_DOM_ff = 1;
if(CounterxDP % 2 == 1 || SBOX_1CYCLE || DOM_PIPELINE) begin
ctrl_enable_chi_iota = 1;
ctrl_enable_lane = {25{1'b1}};
end
if(CounterxDP == CHICNT_RST) begin
CounterxDN = 0;
enableRoundCountxS = 1;
if(RoundCountLastxDP) begin
CtrlStatexDN = IDLE;
end
else begin
if(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE)
CtrlStatexDN = THETA;
else if(USE_LAMBDA_STEPS)
CtrlStatexDN = LAMBDA;
else
CtrlStatexDN = CHI_IOTA;
end
end
end
endcase
end
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) begin
CtrlStatexDP <= RESET_ITERATIVE ? RESET : IDLE;
RoundCountxDP <= 0;
RoundCountLastxDP <= 0;
CounterxDP <= 0;
end
else begin
CtrlStatexDP <= CtrlStatexDN;
RoundCountxDP <= RoundCountxDN;
RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);
CounterxDP <= CounterxDN;
end
end
wire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));
always @(*) begin
RoundCountxDN = RoundCountxDP;
if(resetRoundCountxS) RoundCountxDN = 0;
else if(enableRoundCountxS) RoundCountxDN = RoundCountxDP + 1;
end
reg InitialAbsorbDonexDP;
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) InitialAbsorbDonexDP <= 1'b0;
else if(SetInitialAbsorbDonexS) InitialAbsorbDonexDP <= 1'b1;
end
wire[CHI_SLICES-1:0] RCxD;
keccak_roundconstant #(
.W(W),
.SLICES_PARALLEL(CHI_SLICES),
.COUNTER_BITWIDTH(MAXCNT_BITWIDTH),
.DOM_PIPELINE(DOM_PIPELINE),
.SBOX_1CYCLE(SBOX_1CYCLE)
) RC_GEN (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.RoundNrxDI(RoundCountxDP),
.SliceNrxDI(CounterxDP),
.NextSliceNrxDI(CounterxDN),
.ResetRCxSI(resetRoundCountxS),
.EnableRCxSI(ctrl_enable_chi_iota),
.RCxDO(RCxD)
);
assign IotaRCxDO = RCxD & {CHI_SLICES{(!CONNECT_ABSORB_CHI || InitialAbsorbDonexDP)}};
endmodule | 0 |
140,583 | data/full_repos/permissive/90611392/keccak_control.v | 90,611,392 | keccak_control.v | v | 430 | 111 | [] | [] | [] | null | line:15 column:2: Illegal character '\x00' | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_control.v:77: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:137: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_control\n == (l_cnt / ABSORB_LANES));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:200: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP == ABSORBCNT_MAX) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:267: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:386: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDN\' generates 5 bits.\n : ... In instance keccak_control\n RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:391: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDP\' generates 5 bits.\n : ... In instance keccak_control\nwire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));\n ^~\n%Error: data/full_repos/permissive/90611392/keccak_control.v:409: Cannot find file containing module: \'keccak_roundconstant\'\nkeccak_roundconstant #(\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.sv\n keccak_roundconstant\n keccak_roundconstant.v\n keccak_roundconstant.sv\n obj_dir/keccak_roundconstant\n obj_dir/keccak_roundconstant.v\n obj_dir/keccak_roundconstant.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 309,349 | function | function integer clog2(input integer value); begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction | function integer clog2(input integer value); | begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end endfunction | 0 |
140,584 | data/full_repos/permissive/90611392/keccak_control.v | 90,611,392 | keccak_control.v | v | 430 | 111 | [] | [] | [] | null | line:15 column:2: Illegal character '\x00' | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_control.v:77: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:137: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_control\n == (l_cnt / ABSORB_LANES));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:200: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP == ABSORBCNT_MAX) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:267: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:386: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDN\' generates 5 bits.\n : ... In instance keccak_control\n RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:391: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDP\' generates 5 bits.\n : ... In instance keccak_control\nwire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));\n ^~\n%Error: data/full_repos/permissive/90611392/keccak_control.v:409: Cannot find file containing module: \'keccak_roundconstant\'\nkeccak_roundconstant #(\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.sv\n keccak_roundconstant\n keccak_roundconstant.v\n keccak_roundconstant.sv\n obj_dir/keccak_roundconstant\n obj_dir/keccak_roundconstant.v\n obj_dir/keccak_roundconstant.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 309,349 | function | function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction | function integer getLaneNr(input integer x_coord, input integer y_coord); |
getLaneNr = 5*x_coord + y_coord;
endfunction | 0 |
140,585 | data/full_repos/permissive/90611392/keccak_control.v | 90,611,392 | keccak_control.v | v | 430 | 111 | [] | [] | [] | null | line:15 column:2: Illegal character '\x00' | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_control.v:77: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:137: Operator EQ expects 32 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_control\n == (l_cnt / ABSORB_LANES));\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:200: Operator EQ expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP == ABSORBCNT_MAX) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:267: Operator LT expects 32 or 8 bits on the LHS, but LHS\'s VARREF \'CounterxDP\' generates 5 bits.\n : ... In instance keccak_control\n if(CounterxDP < (W - (ROTATION_OFFSETS[i*8 +: 8] % W))) begin\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:386: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDN\' generates 5 bits.\n : ... In instance keccak_control\n RoundCountLastxDP <= (RoundCountxDN == ROUNDS - 1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_control.v:391: Operator EQ expects 32 bits on the LHS, but LHS\'s VARREF \'RoundCountxDP\' generates 5 bits.\n : ... In instance keccak_control\nwire resetRoundCountxS = (enableRoundCountxS & (RoundCountxDP == ROUNDS - 1));\n ^~\n%Error: data/full_repos/permissive/90611392/keccak_control.v:409: Cannot find file containing module: \'keccak_roundconstant\'\nkeccak_roundconstant #(\n^~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.v\n data/full_repos/permissive/90611392,data/full_repos/permissive/90611392/keccak_roundconstant.sv\n keccak_roundconstant\n keccak_roundconstant.v\n keccak_roundconstant.sv\n obj_dir/keccak_roundconstant\n obj_dir/keccak_roundconstant.v\n obj_dir/keccak_roundconstant.sv\n%Error: Exiting due to 1 error(s), 6 warning(s)\n' | 309,349 | function | function integer max(input integer first, input integer second);
max = first > second ? first : second;
endfunction | function integer max(input integer first, input integer second); |
max = first > second ? first : second;
endfunction | 0 |
140,586 | data/full_repos/permissive/90611392/keccak_pi.v | 90,611,392 | keccak_pi.v | v | 35 | 61 | [] | [] | [] | null | line:14: before: "(" | data/verilator_xmls/3c0c9008-8860-4a85-b3eb-f3f2dbc8140d.xml | null | 309,350 | module | module keccak_pi #(
parameter SLICES_PARALLEL = 1
)(
input wire ClkxCI,
input wire RstxRBI,
input wire[25*SLICES_PARALLEL-1 : 0] SlicesxDI,
output reg[25*SLICES_PARALLEL-1 : 0] SlicesxDO
);
localparam SP = SLICES_PARALLEL;
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction
always @(*) begin : RHO_PI_COMB
reg[25*SP-1:0] A;
reg[25*SP-1:0] B;
integer x, y;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
B[Idx(y,(2*x+3*y)%5) +: SP] = A[Idx(x,y) +: SP];
end
end
SlicesxDO = B;
end
endmodule | module keccak_pi #(
parameter SLICES_PARALLEL = 1
)(
input wire ClkxCI,
input wire RstxRBI,
input wire[25*SLICES_PARALLEL-1 : 0] SlicesxDI,
output reg[25*SLICES_PARALLEL-1 : 0] SlicesxDO
); |
localparam SP = SLICES_PARALLEL;
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction
always @(*) begin : RHO_PI_COMB
reg[25*SP-1:0] A;
reg[25*SP-1:0] B;
integer x, y;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
B[Idx(y,(2*x+3*y)%5) +: SP] = A[Idx(x,y) +: SP];
end
end
SlicesxDO = B;
end
endmodule | 0 |
140,587 | data/full_repos/permissive/90611392/keccak_pi.v | 90,611,392 | keccak_pi.v | v | 35 | 61 | [] | [] | [] | null | line:14: before: "(" | data/verilator_xmls/3c0c9008-8860-4a85-b3eb-f3f2dbc8140d.xml | null | 309,350 | function | function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction | function integer Idx(input integer x, input integer y); |
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction | 0 |
140,588 | data/full_repos/permissive/90611392/keccak_rhopi.v | 90,611,392 | keccak_rhopi.v | v | 39 | 104 | [] | [] | [] | null | line:10: before: "(" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_rhopi.v:14: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_rhopi.v:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance keccak_rhopi\n RHO[Idx(x,y) +: W] = {2{A[Idx(x,y) +: W]}} >> (W - (ROTATION_OFFSETS[(5*x+y)*8 +: 8] % W));\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,351 | module | module keccak_rhopi #(
parameter W = 16
)(
input wire[25*W-1:0] StatexDI,
output reg[25*W-1:0] StatexDO
);
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction
localparam [0:25*8-1] ROTATION_OFFSETS = {
8'd00, 8'd36, 8'd03, 8'd41, 8'd18,
8'd01, 8'd44, 8'd10, 8'd45, 8'd02,
8'd62, 8'd06, 8'd43, 8'd15, 8'd61,
8'd28, 8'd55, 8'd25, 8'd21, 8'd56,
8'd27, 8'd20, 8'd39, 8'd08, 8'd14
};
reg[25*W-1:0] RHO;
always @(*) begin : RHO_PI_COMB
reg[25*W-1:0] A;
reg[25*W-1:0] B;
integer x, y;
A = StatexDI;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
RHO[Idx(x,y) +: W] = {2{A[Idx(x,y) +: W]}} >> (W - (ROTATION_OFFSETS[(5*x+y)*8 +: 8] % W));
B[Idx(y,(2*x+3*y)%5) +: W] = RHO[Idx(x,y) +: W];
end
end
StatexDO = B;
end
endmodule | module keccak_rhopi #(
parameter W = 16
)(
input wire[25*W-1:0] StatexDI,
output reg[25*W-1:0] StatexDO
); |
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction
localparam [0:25*8-1] ROTATION_OFFSETS = {
8'd00, 8'd36, 8'd03, 8'd41, 8'd18,
8'd01, 8'd44, 8'd10, 8'd45, 8'd02,
8'd62, 8'd06, 8'd43, 8'd15, 8'd61,
8'd28, 8'd55, 8'd25, 8'd21, 8'd56,
8'd27, 8'd20, 8'd39, 8'd08, 8'd14
};
reg[25*W-1:0] RHO;
always @(*) begin : RHO_PI_COMB
reg[25*W-1:0] A;
reg[25*W-1:0] B;
integer x, y;
A = StatexDI;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
RHO[Idx(x,y) +: W] = {2{A[Idx(x,y) +: W]}} >> (W - (ROTATION_OFFSETS[(5*x+y)*8 +: 8] % W));
B[Idx(y,(2*x+3*y)%5) +: W] = RHO[Idx(x,y) +: W];
end
end
StatexDO = B;
end
endmodule | 0 |
140,589 | data/full_repos/permissive/90611392/keccak_rhopi.v | 90,611,392 | keccak_rhopi.v | v | 39 | 104 | [] | [] | [] | null | line:10: before: "(" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_rhopi.v:14: Little bit endian vector: MSB < LSB of bit range: 0:199\nlocalparam [0:25*8-1] ROTATION_OFFSETS = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_rhopi.v:31: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance keccak_rhopi\n RHO[Idx(x,y) +: W] = {2{A[Idx(x,y) +: W]}} >> (W - (ROTATION_OFFSETS[(5*x+y)*8 +: 8] % W));\n ^\n%Error: Exiting due to 2 warning(s)\n' | 309,351 | function | function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*W;
endfunction | function integer Idx(input integer x, input integer y); |
Idx = (5*x+y)*W;
endfunction | 0 |
140,590 | data/full_repos/permissive/90611392/keccak_roundconstant.v | 90,611,392 | keccak_roundconstant.v | v | 98 | 141 | [] | [] | [] | null | line:22: before: "begin" | null | 1: b'%Warning-LITENDIAN: data/full_repos/permissive/90611392/keccak_roundconstant.v:72: Little bit endian vector: MSB < LSB of bit range: 0:1535\n wire[0:24*64-1] RC = {\n ^\n ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_roundconstant.v:84: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SliceNrxDI\' generates 5 bits.\n : ... In instance keccak_roundconstant\n i = SliceNrxDI;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_roundconstant.v:86: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'SliceNrxDI\' generates 5 bits.\n : ... In instance keccak_roundconstant\n i = SliceNrxDI;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_roundconstant.v:90: Operator COND expects 64 bits on the Conditional True, but Conditional True\'s SEL generates 1 bits.\n : ... In instance keccak_roundconstant\n RCxDO = EnableRCxSI ? current_rc[i*SLICES_PARALLEL +: SLICES_PARALLEL] : 64\'h0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_roundconstant.v:90: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 64 bits.\n : ... In instance keccak_roundconstant\n RCxDO = EnableRCxSI ? current_rc[i*SLICES_PARALLEL +: SLICES_PARALLEL] : 64\'h0;\n ^\n%Error: Exiting due to 5 warning(s)\n' | 309,352 | module | module keccak_roundconstant #(
parameter W = 16,
parameter COUNTER_BITWIDTH = 4,
parameter SLICES_PARALLEL = 1,
parameter DOM_PIPELINE = 1,
parameter SBOX_1CYCLE = 0
)
(
input wire ClkxCI,
input wire RstxRBI,
input wire[4:0] RoundNrxDI,
input wire[COUNTER_BITWIDTH:0] SliceNrxDI,
input wire[COUNTER_BITWIDTH:0] NextSliceNrxDI,
input wire ResetRCxSI,
input wire EnableRCxSI,
output reg[SLICES_PARALLEL-1:0] RCxDO
);
generate begin
if(0 && SLICES_PARALLEL == 1 && W == 64) begin
reg[7:0] RC_LFSRxDP, RC_LFSRxDN;
reg RC_ZeroxSP, RC_ZeroxSN;
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) begin
RC_LFSRxDP <= 8'h01;
RC_ZeroxSP <= 0;
end
else begin
RC_LFSRxDP <= RC_LFSRxDN;
RC_ZeroxSP <= RC_ZeroxSN;
end
end
always @(*) begin : LFSR_UPDATE
reg[7:0] r;
reg[COUNTER_BITWIDTH:0] tmp;
tmp = {COUNTER_BITWIDTH{1'b0}};
if(DOM_PIPELINE)
tmp = (SliceNrxDI == 0) ? 0 : (SliceNrxDI - 1);
else if(!SBOX_1CYCLE)
tmp = NextSliceNrxDI >> 1;
else
tmp = NextSliceNrxDI;
RC_ZeroxSN = (tmp == 0) | (tmp == 1) | (tmp == 3) | (tmp == 7) | (tmp == 15)
| (tmp == 31) | (tmp == 63);
r = RC_LFSRxDP;
RC_LFSRxDN = RC_LFSRxDP;
if(ResetRCxSI) begin
RC_LFSRxDN = 8'h01;
end
else if(EnableRCxSI) begin
if (RC_ZeroxSP) begin
RC_LFSRxDN[7] = r[6] ^ r[5] ^ r[4] ^ r[0];
RC_LFSRxDN[6:0] = r[7:1];
end
end
RCxDO[0] = RC_LFSRxDP[0] & RC_ZeroxSP;
end
end
else begin
wire[0:24*64-1] RC = {
64'h0000000000000001, 64'h0000000000008082, 64'h800000000000808A, 64'h8000000080008000,
64'h000000000000808B, 64'h0000000080000001, 64'h8000000080008081, 64'h8000000000008009,
64'h000000000000008A, 64'h0000000000000088, 64'h0000000080008009, 64'h000000008000000A,
64'h000000008000808B, 64'h800000000000008B, 64'h8000000000008089, 64'h8000000000008003,
64'h8000000000008002, 64'h8000000000000080, 64'h000000000000800A, 64'h800000008000000A,
64'h8000000080008081, 64'h8000000000008080, 64'h0000000080000001, 64'h8000000080008008
};
always @(*) begin : SELECT_ROUND_CONSTANT
integer i;
reg[63:0] current_rc;
i = SliceNrxDI;
if(DOM_PIPELINE)
i = SliceNrxDI;
else if(!SBOX_1CYCLE)
i = i >> 1;
current_rc = RC[RoundNrxDI*64 +: 64];
RCxDO = EnableRCxSI ? current_rc[i*SLICES_PARALLEL +: SLICES_PARALLEL] : 64'h0;
end
end
end endgenerate
endmodule | module keccak_roundconstant #(
parameter W = 16,
parameter COUNTER_BITWIDTH = 4,
parameter SLICES_PARALLEL = 1,
parameter DOM_PIPELINE = 1,
parameter SBOX_1CYCLE = 0
)
(
input wire ClkxCI,
input wire RstxRBI,
input wire[4:0] RoundNrxDI,
input wire[COUNTER_BITWIDTH:0] SliceNrxDI,
input wire[COUNTER_BITWIDTH:0] NextSliceNrxDI,
input wire ResetRCxSI,
input wire EnableRCxSI,
output reg[SLICES_PARALLEL-1:0] RCxDO
); |
generate begin
if(0 && SLICES_PARALLEL == 1 && W == 64) begin
reg[7:0] RC_LFSRxDP, RC_LFSRxDN;
reg RC_ZeroxSP, RC_ZeroxSN;
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) begin
RC_LFSRxDP <= 8'h01;
RC_ZeroxSP <= 0;
end
else begin
RC_LFSRxDP <= RC_LFSRxDN;
RC_ZeroxSP <= RC_ZeroxSN;
end
end
always @(*) begin : LFSR_UPDATE
reg[7:0] r;
reg[COUNTER_BITWIDTH:0] tmp;
tmp = {COUNTER_BITWIDTH{1'b0}};
if(DOM_PIPELINE)
tmp = (SliceNrxDI == 0) ? 0 : (SliceNrxDI - 1);
else if(!SBOX_1CYCLE)
tmp = NextSliceNrxDI >> 1;
else
tmp = NextSliceNrxDI;
RC_ZeroxSN = (tmp == 0) | (tmp == 1) | (tmp == 3) | (tmp == 7) | (tmp == 15)
| (tmp == 31) | (tmp == 63);
r = RC_LFSRxDP;
RC_LFSRxDN = RC_LFSRxDP;
if(ResetRCxSI) begin
RC_LFSRxDN = 8'h01;
end
else if(EnableRCxSI) begin
if (RC_ZeroxSP) begin
RC_LFSRxDN[7] = r[6] ^ r[5] ^ r[4] ^ r[0];
RC_LFSRxDN[6:0] = r[7:1];
end
end
RCxDO[0] = RC_LFSRxDP[0] & RC_ZeroxSP;
end
end
else begin
wire[0:24*64-1] RC = {
64'h0000000000000001, 64'h0000000000008082, 64'h800000000000808A, 64'h8000000080008000,
64'h000000000000808B, 64'h0000000080000001, 64'h8000000080008081, 64'h8000000000008009,
64'h000000000000008A, 64'h0000000000000088, 64'h0000000080008009, 64'h000000008000000A,
64'h000000008000808B, 64'h800000000000008B, 64'h8000000000008089, 64'h8000000000008003,
64'h8000000000008002, 64'h8000000000000080, 64'h000000000000800A, 64'h800000008000000A,
64'h8000000080008081, 64'h8000000000008080, 64'h0000000080000001, 64'h8000000080008008
};
always @(*) begin : SELECT_ROUND_CONSTANT
integer i;
reg[63:0] current_rc;
i = SliceNrxDI;
if(DOM_PIPELINE)
i = SliceNrxDI;
else if(!SBOX_1CYCLE)
i = i >> 1;
current_rc = RC[RoundNrxDI*64 +: 64];
RCxDO = EnableRCxSI ? current_rc[i*SLICES_PARALLEL +: SLICES_PARALLEL] : 64'h0;
end
end
end endgenerate
endmodule | 0 |
140,591 | data/full_repos/permissive/90611392/keccak_state.v | 90,611,392 | keccak_state.v | v | 196 | 95 | [] | [] | [] | null | line:40: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:89: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:93: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:100: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:111: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:119: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:134: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:141: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:153: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Error: Exiting due to 8 warning(s)\n' | 309,354 | module | module keccak_state #(
parameter RATE = 128,
parameter W = 16,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 1,
parameter THETA_ITERATIVE = 1,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter CONNECT_ABSORB_CHI = 1,
parameter SLICES_PARALLEL = 1,
parameter THETA_SLICES = 1,
parameter CHI_SLICES = 1,
parameter ABSORB_LANES = RATE/W,
parameter ABSORB_SLICES = W
)(
input wire ClkxCI,
input wire RstxRBI,
input wire[24:0] EnableLanexSI,
input wire ctrl_reset_state,
input wire ctrl_enable_rhopi,
input wire ctrl_enable_theta,
input wire ctrl_theta_last,
input wire ctrl_enable_lambda,
input wire ctrl_enable_absorb,
input wire[(ABSORB_LANES*ABSORB_SLICES)-1:0] AbsorbSlicesxDI,
input wire[24:0] SliceZ0FromThetaxDI,
input wire[25*THETA_SLICES-1:0] SlicesFromThetaxDI,
input wire[25*W-1:0] StateFromRhoPixDI,
input wire[25*CHI_SLICES-1:0] SlicesFromChixDI,
output wire[25*W-1:0] StatexDO
);
localparam STATE_SIZE = 5*5*W;
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer Idx(input integer x,
input integer y,
input integer len);
Idx = getLaneNr(x,y)*len;
endfunction
`define QUEUE2(target_state, slices, slice_len, shift) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
target_state[Idx(x,y,W) +: W] = { \
slices[Idx(x,y,slice_len) +: shift], \
StatexDP[Idx(x,y,W) +: W] } >> shift; \
end \
end
`define CON_SLICES2(dst, dst_len, src, src_len, start_slice, amount) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
dst[Idx(x,y,dst_len) +: amount] \
= src[Idx(x,y,src_len) + start_slice +: amount]; \
end \
end
`define CON_ABSORB_XOR2(dst, dst_len, src, src_len, amount) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
if(x+5*y < RATE/W) begin \
dst[Idx(x,y, dst_len) +: amount] \
= AbsorbSlicesxDI[((x+5*y)%ABSORB_LANES)*ABSORB_SLICES +: ABSORB_SLICES] \
^ src[Idx(x,y,src_len) +: amount]; \
end \
end \
end
reg[STATE_SIZE-1:0] SlicesToStatexD;
reg[STATE_SIZE-1:0] StatexDP;
always @(*) begin : STATE_CONNECT
integer x, y;
reg[STATE_SIZE-1:0] tmp;
if(CONNECT_ABSORB_CHI) begin
if(RESET_ITERATIVE && ctrl_reset_state) begin
tmp = {STATE_SIZE{1'b0}};
`QUEUE2(SlicesToStatexD, tmp, W, THETA_SLICES)
end
else if(ctrl_enable_rhopi) begin
if (RHO_PI_ITERATIVE) begin
`QUEUE2(SlicesToStatexD, StatexDP, W, 1)
end
else begin
SlicesToStatexD = StateFromRhoPixDI;
end
end
else begin
`QUEUE2(SlicesToStatexD, SlicesFromThetaxDI, THETA_SLICES, THETA_SLICES)
if(ctrl_theta_last) begin
`CON_SLICES2(SlicesToStatexD, W, SliceZ0FromThetaxDI, 1, 0, 1)
end
end
end
else begin
case(1'b1)
RESET_ITERATIVE && ctrl_reset_state: begin
tmp = {STATE_SIZE{1'b0}};
`QUEUE2(SlicesToStatexD, tmp, W, THETA_SLICES)
end
ctrl_enable_absorb: begin
if(!ABSORB_ITERATIVE) begin
`CON_ABSORB_XOR2(SlicesToStatexD, W, StatexDP, W, W)
end
else if(W!=ABSORB_SLICES && ABSORB_LANES < RATE/W) begin
`CON_ABSORB_XOR2(tmp, W, StatexDP, W, W)
`QUEUE2(SlicesToStatexD, tmp, W, ABSORB_SLICES)
end
else begin
$fatal(1, "stop");
SlicesToStatexD = 42;
end
end
ctrl_enable_lambda: begin
SlicesToStatexD = StateFromRhoPixDI;
end
ctrl_enable_rhopi: begin
if (RHO_PI_ITERATIVE) begin
`QUEUE2(SlicesToStatexD, StatexDP, W, 1)
end
else begin
SlicesToStatexD = StateFromRhoPixDI;
end
end
ctrl_enable_theta: begin
`QUEUE2(SlicesToStatexD, SlicesFromThetaxDI, THETA_SLICES, THETA_SLICES)
if((ABSORB_ITERATIVE || THETA_ITERATIVE) && ctrl_theta_last) begin
`CON_SLICES2(SlicesToStatexD, W, SliceZ0FromThetaxDI, 1, 0, 1)
end
end
default: begin
`QUEUE2(SlicesToStatexD, SlicesFromChixDI, CHI_SLICES, CHI_SLICES)
end
endcase
end
end
generate begin
if(!RESET_ITERATIVE) begin
always @(posedge ClkxCI or negedge RstxRBI) begin : STATE
integer regcnt;
if(~RstxRBI) begin
StatexDP <= {STATE_SIZE{1'b0}};
end
else begin
for(regcnt=0; regcnt < 25; regcnt=regcnt+1) begin
if (EnableLanexSI[regcnt]) begin
StatexDP[regcnt*W +: W] <= SlicesToStatexD[regcnt*W +: W];
end
end
end
end
end
else begin
always @(posedge ClkxCI) begin : STATE
integer regcnt;
for(regcnt=0; regcnt < 25; regcnt=regcnt+1) begin
if (EnableLanexSI[regcnt]) begin
StatexDP[regcnt*W +: W] <= SlicesToStatexD[regcnt*W +: W];
end
end
end
end
assign StatexDO = StatexDP;
end endgenerate
endmodule | module keccak_state #(
parameter RATE = 128,
parameter W = 16,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 1,
parameter THETA_ITERATIVE = 1,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter CONNECT_ABSORB_CHI = 1,
parameter SLICES_PARALLEL = 1,
parameter THETA_SLICES = 1,
parameter CHI_SLICES = 1,
parameter ABSORB_LANES = RATE/W,
parameter ABSORB_SLICES = W
)(
input wire ClkxCI,
input wire RstxRBI,
input wire[24:0] EnableLanexSI,
input wire ctrl_reset_state,
input wire ctrl_enable_rhopi,
input wire ctrl_enable_theta,
input wire ctrl_theta_last,
input wire ctrl_enable_lambda,
input wire ctrl_enable_absorb,
input wire[(ABSORB_LANES*ABSORB_SLICES)-1:0] AbsorbSlicesxDI,
input wire[24:0] SliceZ0FromThetaxDI,
input wire[25*THETA_SLICES-1:0] SlicesFromThetaxDI,
input wire[25*W-1:0] StateFromRhoPixDI,
input wire[25*CHI_SLICES-1:0] SlicesFromChixDI,
output wire[25*W-1:0] StatexDO
); |
localparam STATE_SIZE = 5*5*W;
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer Idx(input integer x,
input integer y,
input integer len);
Idx = getLaneNr(x,y)*len;
endfunction
`define QUEUE2(target_state, slices, slice_len, shift) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
target_state[Idx(x,y,W) +: W] = { \
slices[Idx(x,y,slice_len) +: shift], \
StatexDP[Idx(x,y,W) +: W] } >> shift; \
end \
end
`define CON_SLICES2(dst, dst_len, src, src_len, start_slice, amount) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
dst[Idx(x,y,dst_len) +: amount] \
= src[Idx(x,y,src_len) + start_slice +: amount]; \
end \
end
`define CON_ABSORB_XOR2(dst, dst_len, src, src_len, amount) \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
if(x+5*y < RATE/W) begin \
dst[Idx(x,y, dst_len) +: amount] \
= AbsorbSlicesxDI[((x+5*y)%ABSORB_LANES)*ABSORB_SLICES +: ABSORB_SLICES] \
^ src[Idx(x,y,src_len) +: amount]; \
end \
end \
end
reg[STATE_SIZE-1:0] SlicesToStatexD;
reg[STATE_SIZE-1:0] StatexDP;
always @(*) begin : STATE_CONNECT
integer x, y;
reg[STATE_SIZE-1:0] tmp;
if(CONNECT_ABSORB_CHI) begin
if(RESET_ITERATIVE && ctrl_reset_state) begin
tmp = {STATE_SIZE{1'b0}};
`QUEUE2(SlicesToStatexD, tmp, W, THETA_SLICES)
end
else if(ctrl_enable_rhopi) begin
if (RHO_PI_ITERATIVE) begin
`QUEUE2(SlicesToStatexD, StatexDP, W, 1)
end
else begin
SlicesToStatexD = StateFromRhoPixDI;
end
end
else begin
`QUEUE2(SlicesToStatexD, SlicesFromThetaxDI, THETA_SLICES, THETA_SLICES)
if(ctrl_theta_last) begin
`CON_SLICES2(SlicesToStatexD, W, SliceZ0FromThetaxDI, 1, 0, 1)
end
end
end
else begin
case(1'b1)
RESET_ITERATIVE && ctrl_reset_state: begin
tmp = {STATE_SIZE{1'b0}};
`QUEUE2(SlicesToStatexD, tmp, W, THETA_SLICES)
end
ctrl_enable_absorb: begin
if(!ABSORB_ITERATIVE) begin
`CON_ABSORB_XOR2(SlicesToStatexD, W, StatexDP, W, W)
end
else if(W!=ABSORB_SLICES && ABSORB_LANES < RATE/W) begin
`CON_ABSORB_XOR2(tmp, W, StatexDP, W, W)
`QUEUE2(SlicesToStatexD, tmp, W, ABSORB_SLICES)
end
else begin
$fatal(1, "stop");
SlicesToStatexD = 42;
end
end
ctrl_enable_lambda: begin
SlicesToStatexD = StateFromRhoPixDI;
end
ctrl_enable_rhopi: begin
if (RHO_PI_ITERATIVE) begin
`QUEUE2(SlicesToStatexD, StatexDP, W, 1)
end
else begin
SlicesToStatexD = StateFromRhoPixDI;
end
end
ctrl_enable_theta: begin
`QUEUE2(SlicesToStatexD, SlicesFromThetaxDI, THETA_SLICES, THETA_SLICES)
if((ABSORB_ITERATIVE || THETA_ITERATIVE) && ctrl_theta_last) begin
`CON_SLICES2(SlicesToStatexD, W, SliceZ0FromThetaxDI, 1, 0, 1)
end
end
default: begin
`QUEUE2(SlicesToStatexD, SlicesFromChixDI, CHI_SLICES, CHI_SLICES)
end
endcase
end
end
generate begin
if(!RESET_ITERATIVE) begin
always @(posedge ClkxCI or negedge RstxRBI) begin : STATE
integer regcnt;
if(~RstxRBI) begin
StatexDP <= {STATE_SIZE{1'b0}};
end
else begin
for(regcnt=0; regcnt < 25; regcnt=regcnt+1) begin
if (EnableLanexSI[regcnt]) begin
StatexDP[regcnt*W +: W] <= SlicesToStatexD[regcnt*W +: W];
end
end
end
end
end
else begin
always @(posedge ClkxCI) begin : STATE
integer regcnt;
for(regcnt=0; regcnt < 25; regcnt=regcnt+1) begin
if (EnableLanexSI[regcnt]) begin
StatexDP[regcnt*W +: W] <= SlicesToStatexD[regcnt*W +: W];
end
end
end
end
assign StatexDO = StatexDP;
end endgenerate
endmodule | 0 |
140,592 | data/full_repos/permissive/90611392/keccak_state.v | 90,611,392 | keccak_state.v | v | 196 | 95 | [] | [] | [] | null | line:40: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:89: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:93: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:100: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:111: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:119: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:134: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:141: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:153: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Error: Exiting due to 8 warning(s)\n' | 309,354 | function | function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction | function integer getLaneNr(input integer x_coord, input integer y_coord); |
getLaneNr = 5*x_coord + y_coord;
endfunction | 0 |
140,593 | data/full_repos/permissive/90611392/keccak_state.v | 90,611,392 | keccak_state.v | v | 196 | 95 | [] | [] | [] | null | line:40: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:89: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:93: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:100: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:111: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:119: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 32 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:134: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:141: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_state.v:153: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 17 bits.\n : ... In instance keccak_state\n SlicesToStatexD[Idx(x,y,W) +: W] = { \n ^\n%Error: Exiting due to 8 warning(s)\n' | 309,354 | function | function integer Idx(input integer x,
input integer y,
input integer len);
Idx = getLaneNr(x,y)*len;
endfunction | function integer Idx(input integer x,
input integer y,
input integer len); |
Idx = getLaneNr(x,y)*len;
endfunction | 0 |
140,594 | data/full_repos/permissive/90611392/keccak_tb.sv | 90,611,392 | keccak_tb.sv | sv | 253 | 150 | [] | [] | [] | null | line:4: before: ")" | null | 1: b'%Error: data/full_repos/permissive/90611392/keccak_tb.sv:1: Unsupported: `default_nettype of other than none or wire: `default_nettype uwire\n`default_nettype uwire\n^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\nalways #5 ClkxCI = ~ClkxCI;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:109: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:134: Unsupported: Static in this context\n static int state_nr = 0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:135: Unsupported: Static in this context\n static string state_name = "";\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:136: Unsupported: Static in this context\n static State2D_t state_data = \'0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:137: Unsupported: Static in this context\n static State2D_t received = \'0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:138: Unsupported: Static in this context\n static int assigns = 0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:147: syntax error, unexpected \'@\'\n repeat(2) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:149: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:181: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:183: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:184: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:184: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:202: syntax error, unexpected \'@\'\n wait(ReadyxSO == 1) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:202: Unsupported: wait statements\n wait(ReadyxSO == 1) @(posedge ClkxCI) #1;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:214: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:214: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:221: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:221: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:223: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.RHOPI);\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:237: syntax error, unexpected \'@\'\n wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:237: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;\n ^~~~\n%Error: Exiting due to 18 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,355 | module | module keccak_tb #(
) ( );
timeunit 1ns;
timeprecision 1ns;
parameter int RATE = 128;
parameter int W = 16;
parameter int SHARES = 2;
parameter string TEST_FILE = "keccak_r128_c272_s2.ref";
parameter int ABSORB_LANES = RATE/W;
parameter int RESET_ITERATIVE = 0;
parameter int ABSORB_ITERATIVE = 1;
parameter int THETA_ITERATIVE = 1;
parameter int RHO_PI_ITERATIVE = 0;
parameter int CHI_IOTA_ITERATIVE = 1;
parameter int SLICES_PARALLEL = 1;
parameter int CHI_DOUBLE_CLK = 0;
parameter int LESS_RAND = 1;
parameter int DOM_PIPELINE = 1;
localparam ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W;
localparam THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES;
localparam CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W;
localparam CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_LANES) ? 1 : 0;
localparam DATAOUT_SIZE = CONNECT_ABSORB_CHI ? 25*SLICES_PARALLEL : RATE;
typedef logic[4:0][4:0][W-1:0] State3D_t;
typedef logic[24:0][W-1:0] State2D_t;
typedef bit[(SHARES*SHARES-SHARES)/2 - 1:0][4:0][4:0][CHI_SLICES-1:0] Rand_t;
logic ClkxCI;
always #5 ClkxCI = ~ClkxCI;
logic RstxRBI;
logic StartAbsorbxSI;
logic StartSqueezexSI;
logic[SHARES-1:0][4:0][4:0][W-1:0] AbsorbStatexD;
logic[SHARES-1:0][ABSORB_LANES-1:0][ABSORB_SLICES-1:0] AbsorbSlicesxDI;
Rand_t ZxDI;
logic[SHARES*DATAOUT_SIZE-1:0] DataxDO;
logic ReadyxSO;
integer data_file;
integer STDERR = 32'h8000_0002;
keccak_top #(
.RATE(RATE),
.W(W),
.SHARES(SHARES),
.SLICES_PARALLEL(SLICES_PARALLEL),
.ABSORB_LANES(ABSORB_LANES),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.LESS_RAND(LESS_RAND),
.DOM_PIPELINE(DOM_PIPELINE)
)
DUT (
.ClkxCI,
.RstxRBI,
.RandomnessAvailablexSI(1'b1),
.StartAbsorbxSI,
.StartSqueezexSI,
.ReadyxSO,
.AbsorbSlicesxDI,
.ZxDI,
.DataxDO
);
task choose_absorb_data (input int lane_nr, input int slice_nr);
for(int i = 0; i < SHARES; i++) begin
for(int j = 0; j < ABSORB_LANES; j++) begin
automatic int x = (lane_nr + j) % 5;
automatic int y = (lane_nr + j) / 5;
assert(lane_nr + j < RATE/W) else $fatal(1, "Testbench error");
AbsorbSlicesxDI[i][(lane_nr + j)%ABSORB_LANES] = AbsorbStatexD[i][x][y][slice_nr +: ABSORB_SLICES];
end
end
endtask
task check(
input State2D_t expected,
input State2D_t[SHARES-1:0] to_check
);
automatic State2D_t received = '0;
for (int i = 0; i < SHARES; i++) begin
received ^= to_check[i];
end
if(received !== expected)begin
#3;
$fdisplay(STDERR, "Expected: %h", expected);
$fdisplay(STDERR, "Received: %h", received);
$fatal(1, "State check failed");
end
endtask
function Rand_t random_vec();
automatic Rand_t result;
for(int i=0; i<(SHARES*SHARES-SHARES)/2; i++)
for(int x=0; x<5; x++)
for(int y=0; y<5; y++)
for(int z=0; z<(W/32+1); z++)
result[i][x][y] = {result[i][x][y], $random()};
return result;
endfunction
Rand_t ZxDP;
always @(posedge ClkxCI) begin
ZxDP <= random_vec();
end
assign ZxDI = ZxDP;
initial begin
static int state_nr = 0;
static string state_name = "";
static State2D_t state_data = '0;
static State2D_t received = '0;
static int assigns = 0;
AbsorbStatexD = '0;
StartAbsorbxSI = 0;
StartSqueezexSI = 0;
ClkxCI = 0;
RstxRBI = 0;
repeat(2) @(posedge ClkxCI) #1;
RstxRBI = 1;
@(posedge ClkxCI) #1;
data_file = $fopen(TEST_FILE, "r");
if (data_file == 0) begin
$fatal(1, "[ERROR] data_file handle was NULL");
end
$display("Configuration");
$display("RATE = %4d", RATE);
$display("W = %2d", W);
$display("SHARES = %2d", SHARES);
$display("ABSORB_LANES = %2d", ABSORB_LANES);
$display("RESET_ITERATIVE = %1d", RESET_ITERATIVE);
$display("ABSORB_ITERATIVE = %1d", ABSORB_ITERATIVE);
$display("THETA_ITERATIVE = %1d", THETA_ITERATIVE);
$display("RHO_PI_ITERATIVE = %1d", RHO_PI_ITERATIVE);
$display("CHI_IOTA_ITERATIVE = %1d", CHI_IOTA_ITERATIVE);
$display("SLICES_PARALLEL = %1d", SLICES_PARALLEL);
$display("CHI_DOUBLE_CLK = %1d", CHI_DOUBLE_CLK);
$display("LESS_RAND = %1d", LESS_RAND);
$display("DOM_PIPELINE = 1%d", DOM_PIPELINE);
while (!$feof(data_file)) begin
assigns = $fscanf(data_file, "%s %h %d\n", state_name, state_data, state_nr);
if(assigns < 1)begin
$fdisplay(STDERR, "%s %h %d", state_name, state_data, state_nr);
$fatal(1, "Couldn't read input");
end
case(state_name)
"reset": begin
$display("reset");
RstxRBI = 0;
@(posedge ClkxCI) #1;
RstxRBI = 1;
@(posedge ClkxCI) #1;
wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;
end
"inputshare": begin
for(int lane_nr=0; lane_nr < RATE/W; lane_nr++) begin
AbsorbStatexD[state_nr][lane_nr%5][lane_nr/5] = state_data[RATE/W - 1 - lane_nr];
end
$display("inputshare %0d: %h", state_nr, AbsorbStatexD[state_nr]);
end
"absorb": begin
for(int lane_nr = 0; lane_nr < (RATE/W); lane_nr+=ABSORB_LANES) begin
for(int slice_nr = 0; slice_nr < W; slice_nr+=ABSORB_SLICES) begin
choose_absorb_data(lane_nr, slice_nr);
StartAbsorbxSI = 1;
wait(ReadyxSO == 1) @(posedge ClkxCI) #1;
StartAbsorbxSI = 0;
AbsorbSlicesxDI = $random();
end
end
ReadyCheck: assert(ReadyxSO == 0) else $fatal(1, "[ERROR] Still ready...");
StartAbsorbxSI = 0;
AbsorbStatexD = '0;
if(!CONNECT_ABSORB_CHI && !ABSORB_ITERATIVE) begin
$display("absorb: %h", state_data);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;
check(state_data, DUT.StatexD);
end
end
"theta": begin
if(CONNECT_ABSORB_CHI) begin
$display("theta: %h", state_data);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;
check(state_data, DUT.StatexD);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.RHOPI);
end
end
"rho_pi": begin
end
"chi": begin
end
"iota": begin
if(!CONNECT_ABSORB_CHI) begin
$display("iota: %h", state_data);
wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;
check(state_data, DUT.StatexD);
end
end
default: begin
$fatal(1, "[ERROR] unknown state '%s'", state_name);
end
endcase;
end
$fdisplay(STDERR, "[SUCCESS] Done! All tests passed");
$finish();
end
endmodule | module keccak_tb #(
) ( ); |
timeunit 1ns;
timeprecision 1ns;
parameter int RATE = 128;
parameter int W = 16;
parameter int SHARES = 2;
parameter string TEST_FILE = "keccak_r128_c272_s2.ref";
parameter int ABSORB_LANES = RATE/W;
parameter int RESET_ITERATIVE = 0;
parameter int ABSORB_ITERATIVE = 1;
parameter int THETA_ITERATIVE = 1;
parameter int RHO_PI_ITERATIVE = 0;
parameter int CHI_IOTA_ITERATIVE = 1;
parameter int SLICES_PARALLEL = 1;
parameter int CHI_DOUBLE_CLK = 0;
parameter int LESS_RAND = 1;
parameter int DOM_PIPELINE = 1;
localparam ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W;
localparam THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES;
localparam CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W;
localparam CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_LANES) ? 1 : 0;
localparam DATAOUT_SIZE = CONNECT_ABSORB_CHI ? 25*SLICES_PARALLEL : RATE;
typedef logic[4:0][4:0][W-1:0] State3D_t;
typedef logic[24:0][W-1:0] State2D_t;
typedef bit[(SHARES*SHARES-SHARES)/2 - 1:0][4:0][4:0][CHI_SLICES-1:0] Rand_t;
logic ClkxCI;
always #5 ClkxCI = ~ClkxCI;
logic RstxRBI;
logic StartAbsorbxSI;
logic StartSqueezexSI;
logic[SHARES-1:0][4:0][4:0][W-1:0] AbsorbStatexD;
logic[SHARES-1:0][ABSORB_LANES-1:0][ABSORB_SLICES-1:0] AbsorbSlicesxDI;
Rand_t ZxDI;
logic[SHARES*DATAOUT_SIZE-1:0] DataxDO;
logic ReadyxSO;
integer data_file;
integer STDERR = 32'h8000_0002;
keccak_top #(
.RATE(RATE),
.W(W),
.SHARES(SHARES),
.SLICES_PARALLEL(SLICES_PARALLEL),
.ABSORB_LANES(ABSORB_LANES),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.LESS_RAND(LESS_RAND),
.DOM_PIPELINE(DOM_PIPELINE)
)
DUT (
.ClkxCI,
.RstxRBI,
.RandomnessAvailablexSI(1'b1),
.StartAbsorbxSI,
.StartSqueezexSI,
.ReadyxSO,
.AbsorbSlicesxDI,
.ZxDI,
.DataxDO
);
task choose_absorb_data (input int lane_nr, input int slice_nr);
for(int i = 0; i < SHARES; i++) begin
for(int j = 0; j < ABSORB_LANES; j++) begin
automatic int x = (lane_nr + j) % 5;
automatic int y = (lane_nr + j) / 5;
assert(lane_nr + j < RATE/W) else $fatal(1, "Testbench error");
AbsorbSlicesxDI[i][(lane_nr + j)%ABSORB_LANES] = AbsorbStatexD[i][x][y][slice_nr +: ABSORB_SLICES];
end
end
endtask
task check(
input State2D_t expected,
input State2D_t[SHARES-1:0] to_check
);
automatic State2D_t received = '0;
for (int i = 0; i < SHARES; i++) begin
received ^= to_check[i];
end
if(received !== expected)begin
#3;
$fdisplay(STDERR, "Expected: %h", expected);
$fdisplay(STDERR, "Received: %h", received);
$fatal(1, "State check failed");
end
endtask
function Rand_t random_vec();
automatic Rand_t result;
for(int i=0; i<(SHARES*SHARES-SHARES)/2; i++)
for(int x=0; x<5; x++)
for(int y=0; y<5; y++)
for(int z=0; z<(W/32+1); z++)
result[i][x][y] = {result[i][x][y], $random()};
return result;
endfunction
Rand_t ZxDP;
always @(posedge ClkxCI) begin
ZxDP <= random_vec();
end
assign ZxDI = ZxDP;
initial begin
static int state_nr = 0;
static string state_name = "";
static State2D_t state_data = '0;
static State2D_t received = '0;
static int assigns = 0;
AbsorbStatexD = '0;
StartAbsorbxSI = 0;
StartSqueezexSI = 0;
ClkxCI = 0;
RstxRBI = 0;
repeat(2) @(posedge ClkxCI) #1;
RstxRBI = 1;
@(posedge ClkxCI) #1;
data_file = $fopen(TEST_FILE, "r");
if (data_file == 0) begin
$fatal(1, "[ERROR] data_file handle was NULL");
end
$display("Configuration");
$display("RATE = %4d", RATE);
$display("W = %2d", W);
$display("SHARES = %2d", SHARES);
$display("ABSORB_LANES = %2d", ABSORB_LANES);
$display("RESET_ITERATIVE = %1d", RESET_ITERATIVE);
$display("ABSORB_ITERATIVE = %1d", ABSORB_ITERATIVE);
$display("THETA_ITERATIVE = %1d", THETA_ITERATIVE);
$display("RHO_PI_ITERATIVE = %1d", RHO_PI_ITERATIVE);
$display("CHI_IOTA_ITERATIVE = %1d", CHI_IOTA_ITERATIVE);
$display("SLICES_PARALLEL = %1d", SLICES_PARALLEL);
$display("CHI_DOUBLE_CLK = %1d", CHI_DOUBLE_CLK);
$display("LESS_RAND = %1d", LESS_RAND);
$display("DOM_PIPELINE = 1%d", DOM_PIPELINE);
while (!$feof(data_file)) begin
assigns = $fscanf(data_file, "%s %h %d\n", state_name, state_data, state_nr);
if(assigns < 1)begin
$fdisplay(STDERR, "%s %h %d", state_name, state_data, state_nr);
$fatal(1, "Couldn't read input");
end
case(state_name)
"reset": begin
$display("reset");
RstxRBI = 0;
@(posedge ClkxCI) #1;
RstxRBI = 1;
@(posedge ClkxCI) #1;
wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;
end
"inputshare": begin
for(int lane_nr=0; lane_nr < RATE/W; lane_nr++) begin
AbsorbStatexD[state_nr][lane_nr%5][lane_nr/5] = state_data[RATE/W - 1 - lane_nr];
end
$display("inputshare %0d: %h", state_nr, AbsorbStatexD[state_nr]);
end
"absorb": begin
for(int lane_nr = 0; lane_nr < (RATE/W); lane_nr+=ABSORB_LANES) begin
for(int slice_nr = 0; slice_nr < W; slice_nr+=ABSORB_SLICES) begin
choose_absorb_data(lane_nr, slice_nr);
StartAbsorbxSI = 1;
wait(ReadyxSO == 1) @(posedge ClkxCI) #1;
StartAbsorbxSI = 0;
AbsorbSlicesxDI = $random();
end
end
ReadyCheck: assert(ReadyxSO == 0) else $fatal(1, "[ERROR] Still ready...");
StartAbsorbxSI = 0;
AbsorbStatexD = '0;
if(!CONNECT_ABSORB_CHI && !ABSORB_ITERATIVE) begin
$display("absorb: %h", state_data);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;
check(state_data, DUT.StatexD);
end
end
"theta": begin
if(CONNECT_ABSORB_CHI) begin
$display("theta: %h", state_data);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;
check(state_data, DUT.StatexD);
wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.RHOPI);
end
end
"rho_pi": begin
end
"chi": begin
end
"iota": begin
if(!CONNECT_ABSORB_CHI) begin
$display("iota: %h", state_data);
wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;
check(state_data, DUT.StatexD);
end
end
default: begin
$fatal(1, "[ERROR] unknown state '%s'", state_name);
end
endcase;
end
$fdisplay(STDERR, "[SUCCESS] Done! All tests passed");
$finish();
end
endmodule | 0 |
140,595 | data/full_repos/permissive/90611392/keccak_tb.sv | 90,611,392 | keccak_tb.sv | sv | 253 | 150 | [] | [] | [] | null | line:4: before: ")" | null | 1: b'%Error: data/full_repos/permissive/90611392/keccak_tb.sv:1: Unsupported: `default_nettype of other than none or wire: `default_nettype uwire\n`default_nettype uwire\n^~~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:42: Unsupported: Ignoring delay on this delayed statement.\nalways #5 ClkxCI = ~ClkxCI;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:109: Unsupported: Ignoring delay on this delayed statement.\n #3;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:134: Unsupported: Static in this context\n static int state_nr = 0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:135: Unsupported: Static in this context\n static string state_name = "";\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:136: Unsupported: Static in this context\n static State2D_t state_data = \'0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:137: Unsupported: Static in this context\n static State2D_t received = \'0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:138: Unsupported: Static in this context\n static int assigns = 0;\n ^~~~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:147: syntax error, unexpected \'@\'\n repeat(2) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:149: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:181: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:183: syntax error, unexpected \'@\'\n @(posedge ClkxCI) #1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:184: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:184: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.IDLE) #1;\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:202: syntax error, unexpected \'@\'\n wait(ReadyxSO == 1) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:202: Unsupported: wait statements\n wait(ReadyxSO == 1) @(posedge ClkxCI) #1;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:214: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:214: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.IDLE) #1;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/90611392/keccak_tb.sv:221: Unsupported: Ignoring delay on this delayed statement.\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:221: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP === DUT.KECCAK_CONTROL.RHOPI) #1;\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:223: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.CtrlStatexDP !== DUT.KECCAK_CONTROL.RHOPI);\n ^~~~\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:237: syntax error, unexpected \'@\'\n wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;\n ^\n%Error: data/full_repos/permissive/90611392/keccak_tb.sv:237: Unsupported: wait statements\n wait(DUT.KECCAK_CONTROL.enableRoundCountxS) @(posedge ClkxCI) #1;\n ^~~~\n%Error: Exiting due to 18 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,355 | function | function Rand_t random_vec();
automatic Rand_t result;
for(int i=0; i<(SHARES*SHARES-SHARES)/2; i++)
for(int x=0; x<5; x++)
for(int y=0; y<5; y++)
for(int z=0; z<(W/32+1); z++)
result[i][x][y] = {result[i][x][y], $random()};
return result;
endfunction | function Rand_t random_vec(); |
automatic Rand_t result;
for(int i=0; i<(SHARES*SHARES-SHARES)/2; i++)
for(int x=0; x<5; x++)
for(int y=0; y<5; y++)
for(int z=0; z<(W/32+1); z++)
result[i][x][y] = {result[i][x][y], $random()};
return result;
endfunction | 0 |
140,596 | data/full_repos/permissive/90611392/keccak_theta.v | 90,611,392 | keccak_theta.v | v | 99 | 93 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:65: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance keccak_theta\n C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator XOR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator XOR expects 2 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Error: Exiting due to 4 warning(s)\n' | 309,356 | module | module keccak_theta #(
parameter W = 16,
parameter SLICES_PARALLEL = 1
)(
input wire ClkxCI,
input wire RstxRBI,
input wire RstSyncxRI,
input wire EnablexSI,
input wire[25*SLICES_PARALLEL-1:0] SlicesxDI,
input wire[24:0] SliceZ0xDI,
output reg[25*SLICES_PARALLEL-1:0] SlicesxDO,
output reg[24:0] SliceZ0xDO
);
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction
generate begin
reg[5*SLICES_PARALLEL-1:0] C, C_rot;
reg[25*SLICES_PARALLEL-1:0] A, D;
localparam SP = SLICES_PARALLEL;
if(W==SLICES_PARALLEL) begin
always @(*) begin : THETA_PARALLEL
integer x, y;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
C[x*SP +: SP] = A[Idx(x,0) +: SP] ^ A[Idx(x,1) +: SP] ^ A[Idx(x,2) +: SP]
^ A[Idx(x,3) +: SP] ^ A[Idx(x,4) +: SP];
C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);
end
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP]
^ C[(((x-1)+5) % 5)*SP +: SP] ^ C_rot[((x+1) % 5)*SP +: SP];
end
end
SlicesxDO = D;
end
end
else begin
reg[4:0] TmpStoragexDP, TmpStoragexDN;
always @(*) begin : THETA_ITERATIVE
integer x, y;
TmpStoragexDN = TmpStoragexDP;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
C[x*SP +: SP] = A[Idx(x,0) +: SP] ^ A[Idx(x,1) +: SP] ^ A[Idx(x,2) +: SP]
^ A[Idx(x,3) +: SP] ^ A[Idx(x,4) +: SP];
C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);
TmpStoragexDN[x] = C[x*SP + SP - 1];
end
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]
^ {C_rot[((x+1)%5)*SP +: SP] >> 1, TmpStoragexDP[(x+1)%5]};
end
end
SlicesxDO = D;
end
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) TmpStoragexDP <= {5{1'b0}};
else if(RstSyncxRI) TmpStoragexDP <= {5{1'b0}};
else if(EnablexSI) TmpStoragexDP <= TmpStoragexDN;
end
always @(*) begin : LAST_SLICE
integer x, y;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
SliceZ0xDO[5*x+y] = SliceZ0xDI[5*x+y] ^ TmpStoragexDN[(x+1)%5];
end
end
end
end
end
endgenerate
endmodule | module keccak_theta #(
parameter W = 16,
parameter SLICES_PARALLEL = 1
)(
input wire ClkxCI,
input wire RstxRBI,
input wire RstSyncxRI,
input wire EnablexSI,
input wire[25*SLICES_PARALLEL-1:0] SlicesxDI,
input wire[24:0] SliceZ0xDI,
output reg[25*SLICES_PARALLEL-1:0] SlicesxDO,
output reg[24:0] SliceZ0xDO
); |
function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction
generate begin
reg[5*SLICES_PARALLEL-1:0] C, C_rot;
reg[25*SLICES_PARALLEL-1:0] A, D;
localparam SP = SLICES_PARALLEL;
if(W==SLICES_PARALLEL) begin
always @(*) begin : THETA_PARALLEL
integer x, y;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
C[x*SP +: SP] = A[Idx(x,0) +: SP] ^ A[Idx(x,1) +: SP] ^ A[Idx(x,2) +: SP]
^ A[Idx(x,3) +: SP] ^ A[Idx(x,4) +: SP];
C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);
end
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP]
^ C[(((x-1)+5) % 5)*SP +: SP] ^ C_rot[((x+1) % 5)*SP +: SP];
end
end
SlicesxDO = D;
end
end
else begin
reg[4:0] TmpStoragexDP, TmpStoragexDN;
always @(*) begin : THETA_ITERATIVE
integer x, y;
TmpStoragexDN = TmpStoragexDP;
A = SlicesxDI;
for(x=0; x < 5; x=x+1) begin
C[x*SP +: SP] = A[Idx(x,0) +: SP] ^ A[Idx(x,1) +: SP] ^ A[Idx(x,2) +: SP]
^ A[Idx(x,3) +: SP] ^ A[Idx(x,4) +: SP];
C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);
TmpStoragexDN[x] = C[x*SP + SP - 1];
end
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]
^ {C_rot[((x+1)%5)*SP +: SP] >> 1, TmpStoragexDP[(x+1)%5]};
end
end
SlicesxDO = D;
end
always @(posedge ClkxCI or negedge RstxRBI) begin
if(~RstxRBI) TmpStoragexDP <= {5{1'b0}};
else if(RstSyncxRI) TmpStoragexDP <= {5{1'b0}};
else if(EnablexSI) TmpStoragexDP <= TmpStoragexDN;
end
always @(*) begin : LAST_SLICE
integer x, y;
for(x=0; x < 5; x=x+1) begin
for(y=0; y < 5; y=y+1) begin
SliceZ0xDO[5*x+y] = SliceZ0xDI[5*x+y] ^ TmpStoragexDN[(x+1)%5];
end
end
end
end
end
endgenerate
endmodule | 0 |
140,597 | data/full_repos/permissive/90611392/keccak_theta.v | 90,611,392 | keccak_theta.v | v | 99 | 93 | [] | [] | [] | null | line:17: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:65: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s SHIFTR generates 2 bits.\n : ... In instance keccak_theta\n C_rot[x*SP +: SP] = {2{C[x*SP +: SP]}} >> (SP-1);\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator XOR expects 2 bits on the LHS, but LHS\'s SEL generates 1 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator XOR expects 2 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Warning-WIDTH: data/full_repos/permissive/90611392/keccak_theta.v:70: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS\'s XOR generates 2 bits.\n : ... In instance keccak_theta\n D[Idx(x,y) +: SP] = A[Idx(x,y) +: SP] ^ C[(((x-1)+5) % 5)*SP +: SP]\n ^\n%Error: Exiting due to 4 warning(s)\n' | 309,356 | function | function integer Idx(input integer x, input integer y);
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction | function integer Idx(input integer x, input integer y); |
Idx = (5*x+y)*SLICES_PARALLEL;
endfunction | 0 |
140,598 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | module | module keccak_top #(
parameter RATE = 1088,
parameter W = 64,
parameter SHARES = 1,
parameter ABSORB_LANES = RATE/W,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 1,
parameter THETA_ITERATIVE = 1,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter SLICES_PARALLEL = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter LESS_RAND = 1,
parameter DOM_PIPELINE = 1,
parameter ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W,
parameter THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES,
parameter CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W,
parameter CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_LANES) ? 1 : 0,
parameter DATAOUT_SIZE = (CONNECT_ABSORB_CHI) ? 25*SLICES_PARALLEL : RATE
)(
input wire ClkxCI,
input wire RstxRBI,
input wire RandomnessAvailablexSI,
input wire StartAbsorbxSI,
input wire StartSqueezexSI,
output wire ReadyxSO,
input wire[SHARES*(ABSORB_LANES*ABSORB_SLICES)-1:0] AbsorbSlicesxDI,
input wire[(SHARES*SHARES-SHARES)/2 * 25 * CHI_SLICES - 1:0] ZxDI,
output reg[SHARES*DATAOUT_SIZE-1:0] DataxDO
);
localparam STATE_SIZE = 5*5*W;
localparam THETA_SLICES_SIZE = 5*5*THETA_SLICES;
localparam CHI_SLICES_SIZE = 5*5*CHI_SLICES;
localparam PI_SLICES = SLICES_PARALLEL;
localparam PI_SLICES_SIZE = 5*5*PI_SLICES;
localparam ABSORB_SLICES_SIZE = ABSORB_SLICES * ABSORB_LANES;
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer getXCoord(input integer lane_nr);
getXCoord = lane_nr / 5;
endfunction
function integer getYCoord(input integer lane_nr);
getYCoord = lane_nr % 5;
endfunction
function integer Idx(input integer s,
input integer x,
input integer y,
input integer len);
Idx = s*25*len + getLaneNr(x,y)*len;
endfunction
function integer StateIdx(input integer s, input integer x, input integer y);
StateIdx = s*STATE_SIZE + getLaneNr(x,y)*W;
endfunction
`define QUEUE(target_state, slices, slice_len, shift) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
target_state[StateIdx(i,x,y) +: W] = { \
slices[Idx(i,x,y,slice_len) +: shift], \
StatexD[StateIdx(i,x,y) +: W] } >> shift; \
end \
end \
end
`define CON_SLICES(dst, dst_len, src, src_len, start_slice, amount) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
dst[Idx(i,x,y,dst_len) +: amount] \
= src[Idx(i,x,y,src_len) + start_slice +: amount]; \
end \
end \
end
`define CON_ABSORB_XOR(dst, dst_len, src, src_len, amount) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
if(x+5*y < RATE/W) begin \
dst[Idx(i,x,y, dst_len) +: amount] \
= AbsorbSlicesxDI[i*(ABSORB_LANES*ABSORB_SLICES) + ((x+5*y)%ABSORB_LANES)*ABSORB_SLICES +: ABSORB_SLICES] \
^ src[Idx(i,x,y,src_len) +: amount]; \
end \
end \
end \
end
generate begin
if(RATE % W || RATE > 25*W)
_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();
else if(SLICES_PARALLEL > W)
_SLICES_PARALLEL__must_be_smaller_or_equal_to_the_lane_length__W_ DONT_COMPILE();
else if(!(W == 1 || W == 2 || W == 4 || W == 8 || W == 16 || W == 32 || W == 64))
The_lane_length__W__must_be_a_power_of_2 DONT_COMPILE();
else if( (W==SLICES_PARALLEL) && (ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE || CHI_IOTA_ITERATIVE) )
W_eq_SLICES_PARALLEL_but_at_least_one_step_should_be_iterative_according_to_a_xxITERATIVE_parameter DONT_COMPILE();
else if( (W!=SLICES_PARALLEL) && !(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE || CHI_IOTA_ITERATIVE) )
W_neq_SLICES_PARALLEL_but_no_iterative_step DONT_COMPILE();
else if( W==SLICES_PARALLEL && SHARES > 1 ) begin
end
else if( ABSORB_LANES < 1 || ABSORB_LANES > RATE/W || (RATE/W) % ABSORB_LANES != 0)
Allowed_range_is_1_le_ABSORB_LANES_le_RATE_over_W___Further_restriction_is_RATE_over_W_mod_ABSORB_LANES_eq_0 DONT_COMPILE();
else if(RHO_PI_ITERATIVE && !CHI_IOTA_ITERATIVE)
Not_useful_because_Rho_and_pi_will_take_W_cycles_each_Set_CHI_IOTA_ITERATIVE_so_that_the_Pi_step_is_done_concurrently_with_Chi DONT_COMPILE();
else if(RHO_PI_ITERATIVE && SLICES_PARALLEL != 1)
The_iterative_Rho_step_is_done_by_shifting_the_lanes_Thus_we_need_W_cycles_and_not_W_over_SLICES_PARALLEL DONT_COMPILE();
else if(CHI_DOUBLE_CLK && DOM_PIPELINE)
CHI_DOUBLE_CLK_and_DOM_PIPELINE_cannot_both_be_true DONT_COMPILE();
end endgenerate
wire[SHARES*STATE_SIZE-1:0] StatexD;
reg[SHARES*5*5*THETA_SLICES-1:0] SlicesToThetaxD;
wire[SHARES*5*5*THETA_SLICES-1:0] SlicesFromThetaxD;
reg[SHARES*5*5-1:0] SliceZ0ToThetaxD;
wire[SHARES*5*5-1:0] SliceZ0FromThetaxD;
wire[SHARES*5*5*SLICES_PARALLEL-1:0] SlicesFromPixD;
reg[SHARES*5*5*SLICES_PARALLEL-1:0] SlicesToPixD;
wire[SHARES*STATE_SIZE-1:0] StateFromRhoPixD;
reg[SHARES*STATE_SIZE-1:0] StateToRhoPixD;
reg[SHARES*5*5*CHI_SLICES-1:0] SlicesToChixD;
wire[SHARES*5*5*CHI_SLICES-1:0] SlicesFromChixD;
wire[24:0] ctrl_enable_lane;
wire ctrl_enable_absorb;
wire ctrl_enable_lambda;
wire ctrl_enable_theta;
wire ctrl_enable_rhopi;
wire ctrl_enable_chi_iota;
wire ctrl_theta_last;
wire ctrl_enable_absorb_theta;
wire ctrl_enable_DOM_ff;
wire ctrl_reset_state;
genvar i;
generate begin
for(i = 0; i < SHARES; i=i+1) begin : gen_linear_steps
keccak_state #(
.RATE(RATE),
.W(W),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.CONNECT_ABSORB_CHI(CONNECT_ABSORB_CHI),
.SLICES_PARALLEL(SLICES_PARALLEL),
.THETA_SLICES(THETA_SLICES),
.CHI_SLICES(CHI_SLICES),
.ABSORB_LANES(ABSORB_LANES),
.ABSORB_SLICES(ABSORB_SLICES)
) SHARE(
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.EnableLanexSI (ctrl_enable_lane ),
.ctrl_reset_state (ctrl_reset_state ),
.ctrl_enable_rhopi (ctrl_enable_rhopi ),
.ctrl_enable_theta (ctrl_enable_theta ),
.ctrl_theta_last (ctrl_theta_last ),
.ctrl_enable_lambda(ctrl_enable_lambda),
.ctrl_enable_absorb(ctrl_enable_absorb),
.AbsorbSlicesxDI(AbsorbSlicesxDI[i*(ABSORB_LANES*ABSORB_SLICES) +: (ABSORB_LANES*ABSORB_SLICES)]),
.SliceZ0FromThetaxDI(SliceZ0FromThetaxD[i*25 +: 25]),
.SlicesFromThetaxDI(SlicesFromThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.StateFromRhoPixDI(StateFromRhoPixD[i*STATE_SIZE +: STATE_SIZE]),
.SlicesFromChixDI(SlicesFromChixD[i*CHI_SLICES_SIZE +: CHI_SLICES_SIZE]),
.StatexDO(StatexD[i*STATE_SIZE +: STATE_SIZE])
);
keccak_theta #(.W(W), .SLICES_PARALLEL(THETA_SLICES)) THETA(
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.RstSyncxRI(ctrl_theta_last),
.EnablexSI(ctrl_enable_theta),
.SlicesxDI(SlicesToThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.SliceZ0xDI(SliceZ0ToThetaxD[i*25 +: 25]),
.SlicesxDO(SlicesFromThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.SliceZ0xDO(SliceZ0FromThetaxD[i*25 +: 25])
);
if(RHO_PI_ITERATIVE) begin
keccak_pi #(
.SLICES_PARALLEL(PI_SLICES)
) PI (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.SlicesxDI(SlicesToPixD[i*PI_SLICES_SIZE +: PI_SLICES_SIZE]),
.SlicesxDO(SlicesFromPixD[i*PI_SLICES_SIZE +: PI_SLICES_SIZE])
);
end
else begin
keccak_rhopi #(.W(W)) RHOPI(
.StatexDI(StateToRhoPixD[i*STATE_SIZE +: STATE_SIZE]),
.StatexDO(StateFromRhoPixD[i*STATE_SIZE +: STATE_SIZE])
);
end
end
end
endgenerate
wire[CHI_SLICES-1:0] IotaRCxD;
keccak_chi_iota #(
.SHARES(SHARES),
.SLICES(CHI_SLICES),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.LESS_RAND(LESS_RAND),
.DOM_PIPELINE(DOM_PIPELINE)
) CHI(
.ClkxCI(ClkxCI),
.EnablexSI(ctrl_enable_DOM_ff),
.RstxRBI(RstxRBI),
.SlicesxDI(SlicesToChixD),
.ZxDI(ZxDI),
.IotaRCxDI(IotaRCxD),
.SlicesxDO(SlicesFromChixD)
);
always @(*) begin : OUTPUT_CONNECT
integer i, x, y;
if(CONNECT_ABSORB_CHI) begin
DataxDO = SlicesFromChixD;
end
else begin
for(i=0; i < SHARES; i=i+1)
for(x=0; x < 5; x=x+1)
for(y=0; y < 5; y=y+1)
if(x+5*y < RATE/W)
DataxDO[i*RATE + (x+5*y)*W +: W] = StatexD[StateIdx(i,x,y) +: W];
end
end
always @(*) begin : THETA_CONNECT
integer i, x, y;
if(THETA_ITERATIVE || ABSORB_ITERATIVE) begin
`CON_SLICES(SliceZ0ToThetaxD, 1, StatexD, W, THETA_SLICES, 1)
end
else begin
SliceZ0ToThetaxD = {SHARES*25{1'b0}};
end
if(CONNECT_ABSORB_CHI) begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, SlicesFromChixD, CHI_SLICES, 0, THETA_SLICES)
if(ctrl_enable_absorb_theta) begin
`CON_ABSORB_XOR(SlicesToThetaxD, THETA_SLICES, SlicesFromChixD, CHI_SLICES, THETA_SLICES)
end
end
else if(ABSORB_ITERATIVE) begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, StatexD, W, 0, THETA_SLICES)
if(ctrl_enable_absorb_theta) begin
`CON_ABSORB_XOR(SlicesToThetaxD, THETA_SLICES, StatexD, W, THETA_SLICES)
end
end
else begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, StatexD, W, 0, THETA_SLICES)
end
end
always @(*) begin : RHO_PI_CONNECT
integer i, x, y;
if(RHO_PI_ITERATIVE) begin
`CON_SLICES(SlicesToPixD, PI_SLICES, StatexD, W, 0, PI_SLICES)
end
else if(!RHO_PI_ITERATIVE && !THETA_ITERATIVE && !ABSORB_ITERATIVE) begin
`CON_SLICES(StateToRhoPixD, W, SlicesFromThetaxD, W, 0, W)
end
else begin
StateToRhoPixD = StatexD;
end
end
always @(*) begin : CHI_CONNECT
integer i, x, y;
if(CHI_IOTA_ITERATIVE || (SHARES > 1)) begin
if(RHO_PI_ITERATIVE) begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, SlicesFromPixD, PI_SLICES, 0, CHI_SLICES)
end
else begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, StatexD, W, 0, CHI_SLICES)
end
end
else begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, StateFromRhoPixD, W, 0, CHI_SLICES)
end
end
keccak_control #(
.RATE(RATE),
.W(W),
.SHARES(SHARES),
.ABSORB_LANES(ABSORB_LANES),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.SLICES_PARALLEL(SLICES_PARALLEL),
.ABSORB_SLICES(ABSORB_SLICES),
.THETA_SLICES(THETA_SLICES),
.CHI_SLICES(CHI_SLICES),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.CONNECT_ABSORB_CHI(CONNECT_ABSORB_CHI),
.DOM_PIPELINE(DOM_PIPELINE)
) KECCAK_CONTROL (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.StartAbsorbxSI(StartAbsorbxSI),
.StartSqueezexSI(StartSqueezexSI),
.RandomnessAvailablexSI(RandomnessAvailablexSI),
.ReadyxSO(ReadyxSO),
.IotaRCxDO(IotaRCxD),
.StateCtrlxSO( {ctrl_enable_lane,
ctrl_enable_absorb,
ctrl_enable_lambda,
ctrl_enable_theta,
ctrl_enable_rhopi,
ctrl_enable_chi_iota,
ctrl_theta_last,
ctrl_enable_absorb_theta,
ctrl_enable_DOM_ff,
ctrl_reset_state } )
);
endmodule | module keccak_top #(
parameter RATE = 1088,
parameter W = 64,
parameter SHARES = 1,
parameter ABSORB_LANES = RATE/W,
parameter RESET_ITERATIVE = 1,
parameter ABSORB_ITERATIVE = 1,
parameter THETA_ITERATIVE = 1,
parameter RHO_PI_ITERATIVE = 0,
parameter CHI_IOTA_ITERATIVE = 1,
parameter SLICES_PARALLEL = 1,
parameter CHI_DOUBLE_CLK = 1,
parameter LESS_RAND = 1,
parameter DOM_PIPELINE = 1,
parameter ABSORB_SLICES = ABSORB_ITERATIVE ? SLICES_PARALLEL : W,
parameter THETA_SLICES = THETA_ITERATIVE ? SLICES_PARALLEL : ABSORB_SLICES,
parameter CHI_SLICES = CHI_IOTA_ITERATIVE ? SLICES_PARALLEL : W,
parameter CONNECT_ABSORB_CHI = (ABSORB_ITERATIVE && CHI_IOTA_ITERATIVE && RATE/W == ABSORB_LANES) ? 1 : 0,
parameter DATAOUT_SIZE = (CONNECT_ABSORB_CHI) ? 25*SLICES_PARALLEL : RATE
)(
input wire ClkxCI,
input wire RstxRBI,
input wire RandomnessAvailablexSI,
input wire StartAbsorbxSI,
input wire StartSqueezexSI,
output wire ReadyxSO,
input wire[SHARES*(ABSORB_LANES*ABSORB_SLICES)-1:0] AbsorbSlicesxDI,
input wire[(SHARES*SHARES-SHARES)/2 * 25 * CHI_SLICES - 1:0] ZxDI,
output reg[SHARES*DATAOUT_SIZE-1:0] DataxDO
); |
localparam STATE_SIZE = 5*5*W;
localparam THETA_SLICES_SIZE = 5*5*THETA_SLICES;
localparam CHI_SLICES_SIZE = 5*5*CHI_SLICES;
localparam PI_SLICES = SLICES_PARALLEL;
localparam PI_SLICES_SIZE = 5*5*PI_SLICES;
localparam ABSORB_SLICES_SIZE = ABSORB_SLICES * ABSORB_LANES;
function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction
function integer getXCoord(input integer lane_nr);
getXCoord = lane_nr / 5;
endfunction
function integer getYCoord(input integer lane_nr);
getYCoord = lane_nr % 5;
endfunction
function integer Idx(input integer s,
input integer x,
input integer y,
input integer len);
Idx = s*25*len + getLaneNr(x,y)*len;
endfunction
function integer StateIdx(input integer s, input integer x, input integer y);
StateIdx = s*STATE_SIZE + getLaneNr(x,y)*W;
endfunction
`define QUEUE(target_state, slices, slice_len, shift) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
target_state[StateIdx(i,x,y) +: W] = { \
slices[Idx(i,x,y,slice_len) +: shift], \
StatexD[StateIdx(i,x,y) +: W] } >> shift; \
end \
end \
end
`define CON_SLICES(dst, dst_len, src, src_len, start_slice, amount) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
dst[Idx(i,x,y,dst_len) +: amount] \
= src[Idx(i,x,y,src_len) + start_slice +: amount]; \
end \
end \
end
`define CON_ABSORB_XOR(dst, dst_len, src, src_len, amount) \
for(i=0; i < SHARES; i=i+1) begin \
for(x=0; x < 5; x=x+1) begin \
for(y=0; y < 5; y=y+1) begin \
if(x+5*y < RATE/W) begin \
dst[Idx(i,x,y, dst_len) +: amount] \
= AbsorbSlicesxDI[i*(ABSORB_LANES*ABSORB_SLICES) + ((x+5*y)%ABSORB_LANES)*ABSORB_SLICES +: ABSORB_SLICES] \
^ src[Idx(i,x,y,src_len) +: amount]; \
end \
end \
end \
end
generate begin
if(RATE % W || RATE > 25*W)
_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();
else if(SLICES_PARALLEL > W)
_SLICES_PARALLEL__must_be_smaller_or_equal_to_the_lane_length__W_ DONT_COMPILE();
else if(!(W == 1 || W == 2 || W == 4 || W == 8 || W == 16 || W == 32 || W == 64))
The_lane_length__W__must_be_a_power_of_2 DONT_COMPILE();
else if( (W==SLICES_PARALLEL) && (ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE || CHI_IOTA_ITERATIVE) )
W_eq_SLICES_PARALLEL_but_at_least_one_step_should_be_iterative_according_to_a_xxITERATIVE_parameter DONT_COMPILE();
else if( (W!=SLICES_PARALLEL) && !(ABSORB_ITERATIVE || THETA_ITERATIVE || RHO_PI_ITERATIVE || CHI_IOTA_ITERATIVE) )
W_neq_SLICES_PARALLEL_but_no_iterative_step DONT_COMPILE();
else if( W==SLICES_PARALLEL && SHARES > 1 ) begin
end
else if( ABSORB_LANES < 1 || ABSORB_LANES > RATE/W || (RATE/W) % ABSORB_LANES != 0)
Allowed_range_is_1_le_ABSORB_LANES_le_RATE_over_W___Further_restriction_is_RATE_over_W_mod_ABSORB_LANES_eq_0 DONT_COMPILE();
else if(RHO_PI_ITERATIVE && !CHI_IOTA_ITERATIVE)
Not_useful_because_Rho_and_pi_will_take_W_cycles_each_Set_CHI_IOTA_ITERATIVE_so_that_the_Pi_step_is_done_concurrently_with_Chi DONT_COMPILE();
else if(RHO_PI_ITERATIVE && SLICES_PARALLEL != 1)
The_iterative_Rho_step_is_done_by_shifting_the_lanes_Thus_we_need_W_cycles_and_not_W_over_SLICES_PARALLEL DONT_COMPILE();
else if(CHI_DOUBLE_CLK && DOM_PIPELINE)
CHI_DOUBLE_CLK_and_DOM_PIPELINE_cannot_both_be_true DONT_COMPILE();
end endgenerate
wire[SHARES*STATE_SIZE-1:0] StatexD;
reg[SHARES*5*5*THETA_SLICES-1:0] SlicesToThetaxD;
wire[SHARES*5*5*THETA_SLICES-1:0] SlicesFromThetaxD;
reg[SHARES*5*5-1:0] SliceZ0ToThetaxD;
wire[SHARES*5*5-1:0] SliceZ0FromThetaxD;
wire[SHARES*5*5*SLICES_PARALLEL-1:0] SlicesFromPixD;
reg[SHARES*5*5*SLICES_PARALLEL-1:0] SlicesToPixD;
wire[SHARES*STATE_SIZE-1:0] StateFromRhoPixD;
reg[SHARES*STATE_SIZE-1:0] StateToRhoPixD;
reg[SHARES*5*5*CHI_SLICES-1:0] SlicesToChixD;
wire[SHARES*5*5*CHI_SLICES-1:0] SlicesFromChixD;
wire[24:0] ctrl_enable_lane;
wire ctrl_enable_absorb;
wire ctrl_enable_lambda;
wire ctrl_enable_theta;
wire ctrl_enable_rhopi;
wire ctrl_enable_chi_iota;
wire ctrl_theta_last;
wire ctrl_enable_absorb_theta;
wire ctrl_enable_DOM_ff;
wire ctrl_reset_state;
genvar i;
generate begin
for(i = 0; i < SHARES; i=i+1) begin : gen_linear_steps
keccak_state #(
.RATE(RATE),
.W(W),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.CONNECT_ABSORB_CHI(CONNECT_ABSORB_CHI),
.SLICES_PARALLEL(SLICES_PARALLEL),
.THETA_SLICES(THETA_SLICES),
.CHI_SLICES(CHI_SLICES),
.ABSORB_LANES(ABSORB_LANES),
.ABSORB_SLICES(ABSORB_SLICES)
) SHARE(
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.EnableLanexSI (ctrl_enable_lane ),
.ctrl_reset_state (ctrl_reset_state ),
.ctrl_enable_rhopi (ctrl_enable_rhopi ),
.ctrl_enable_theta (ctrl_enable_theta ),
.ctrl_theta_last (ctrl_theta_last ),
.ctrl_enable_lambda(ctrl_enable_lambda),
.ctrl_enable_absorb(ctrl_enable_absorb),
.AbsorbSlicesxDI(AbsorbSlicesxDI[i*(ABSORB_LANES*ABSORB_SLICES) +: (ABSORB_LANES*ABSORB_SLICES)]),
.SliceZ0FromThetaxDI(SliceZ0FromThetaxD[i*25 +: 25]),
.SlicesFromThetaxDI(SlicesFromThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.StateFromRhoPixDI(StateFromRhoPixD[i*STATE_SIZE +: STATE_SIZE]),
.SlicesFromChixDI(SlicesFromChixD[i*CHI_SLICES_SIZE +: CHI_SLICES_SIZE]),
.StatexDO(StatexD[i*STATE_SIZE +: STATE_SIZE])
);
keccak_theta #(.W(W), .SLICES_PARALLEL(THETA_SLICES)) THETA(
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.RstSyncxRI(ctrl_theta_last),
.EnablexSI(ctrl_enable_theta),
.SlicesxDI(SlicesToThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.SliceZ0xDI(SliceZ0ToThetaxD[i*25 +: 25]),
.SlicesxDO(SlicesFromThetaxD[i*THETA_SLICES_SIZE +: THETA_SLICES_SIZE]),
.SliceZ0xDO(SliceZ0FromThetaxD[i*25 +: 25])
);
if(RHO_PI_ITERATIVE) begin
keccak_pi #(
.SLICES_PARALLEL(PI_SLICES)
) PI (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.SlicesxDI(SlicesToPixD[i*PI_SLICES_SIZE +: PI_SLICES_SIZE]),
.SlicesxDO(SlicesFromPixD[i*PI_SLICES_SIZE +: PI_SLICES_SIZE])
);
end
else begin
keccak_rhopi #(.W(W)) RHOPI(
.StatexDI(StateToRhoPixD[i*STATE_SIZE +: STATE_SIZE]),
.StatexDO(StateFromRhoPixD[i*STATE_SIZE +: STATE_SIZE])
);
end
end
end
endgenerate
wire[CHI_SLICES-1:0] IotaRCxD;
keccak_chi_iota #(
.SHARES(SHARES),
.SLICES(CHI_SLICES),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.LESS_RAND(LESS_RAND),
.DOM_PIPELINE(DOM_PIPELINE)
) CHI(
.ClkxCI(ClkxCI),
.EnablexSI(ctrl_enable_DOM_ff),
.RstxRBI(RstxRBI),
.SlicesxDI(SlicesToChixD),
.ZxDI(ZxDI),
.IotaRCxDI(IotaRCxD),
.SlicesxDO(SlicesFromChixD)
);
always @(*) begin : OUTPUT_CONNECT
integer i, x, y;
if(CONNECT_ABSORB_CHI) begin
DataxDO = SlicesFromChixD;
end
else begin
for(i=0; i < SHARES; i=i+1)
for(x=0; x < 5; x=x+1)
for(y=0; y < 5; y=y+1)
if(x+5*y < RATE/W)
DataxDO[i*RATE + (x+5*y)*W +: W] = StatexD[StateIdx(i,x,y) +: W];
end
end
always @(*) begin : THETA_CONNECT
integer i, x, y;
if(THETA_ITERATIVE || ABSORB_ITERATIVE) begin
`CON_SLICES(SliceZ0ToThetaxD, 1, StatexD, W, THETA_SLICES, 1)
end
else begin
SliceZ0ToThetaxD = {SHARES*25{1'b0}};
end
if(CONNECT_ABSORB_CHI) begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, SlicesFromChixD, CHI_SLICES, 0, THETA_SLICES)
if(ctrl_enable_absorb_theta) begin
`CON_ABSORB_XOR(SlicesToThetaxD, THETA_SLICES, SlicesFromChixD, CHI_SLICES, THETA_SLICES)
end
end
else if(ABSORB_ITERATIVE) begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, StatexD, W, 0, THETA_SLICES)
if(ctrl_enable_absorb_theta) begin
`CON_ABSORB_XOR(SlicesToThetaxD, THETA_SLICES, StatexD, W, THETA_SLICES)
end
end
else begin
`CON_SLICES(SlicesToThetaxD, THETA_SLICES, StatexD, W, 0, THETA_SLICES)
end
end
always @(*) begin : RHO_PI_CONNECT
integer i, x, y;
if(RHO_PI_ITERATIVE) begin
`CON_SLICES(SlicesToPixD, PI_SLICES, StatexD, W, 0, PI_SLICES)
end
else if(!RHO_PI_ITERATIVE && !THETA_ITERATIVE && !ABSORB_ITERATIVE) begin
`CON_SLICES(StateToRhoPixD, W, SlicesFromThetaxD, W, 0, W)
end
else begin
StateToRhoPixD = StatexD;
end
end
always @(*) begin : CHI_CONNECT
integer i, x, y;
if(CHI_IOTA_ITERATIVE || (SHARES > 1)) begin
if(RHO_PI_ITERATIVE) begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, SlicesFromPixD, PI_SLICES, 0, CHI_SLICES)
end
else begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, StatexD, W, 0, CHI_SLICES)
end
end
else begin
`CON_SLICES(SlicesToChixD, CHI_SLICES, StateFromRhoPixD, W, 0, CHI_SLICES)
end
end
keccak_control #(
.RATE(RATE),
.W(W),
.SHARES(SHARES),
.ABSORB_LANES(ABSORB_LANES),
.RESET_ITERATIVE(RESET_ITERATIVE),
.ABSORB_ITERATIVE(ABSORB_ITERATIVE),
.THETA_ITERATIVE(THETA_ITERATIVE),
.RHO_PI_ITERATIVE(RHO_PI_ITERATIVE),
.CHI_IOTA_ITERATIVE(CHI_IOTA_ITERATIVE),
.SLICES_PARALLEL(SLICES_PARALLEL),
.ABSORB_SLICES(ABSORB_SLICES),
.THETA_SLICES(THETA_SLICES),
.CHI_SLICES(CHI_SLICES),
.CHI_DOUBLE_CLK(CHI_DOUBLE_CLK),
.CONNECT_ABSORB_CHI(CONNECT_ABSORB_CHI),
.DOM_PIPELINE(DOM_PIPELINE)
) KECCAK_CONTROL (
.ClkxCI(ClkxCI),
.RstxRBI(RstxRBI),
.StartAbsorbxSI(StartAbsorbxSI),
.StartSqueezexSI(StartSqueezexSI),
.RandomnessAvailablexSI(RandomnessAvailablexSI),
.ReadyxSO(ReadyxSO),
.IotaRCxDO(IotaRCxD),
.StateCtrlxSO( {ctrl_enable_lane,
ctrl_enable_absorb,
ctrl_enable_lambda,
ctrl_enable_theta,
ctrl_enable_rhopi,
ctrl_enable_chi_iota,
ctrl_theta_last,
ctrl_enable_absorb_theta,
ctrl_enable_DOM_ff,
ctrl_reset_state } )
);
endmodule | 0 |
140,599 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | function | function integer getLaneNr(input integer x_coord, input integer y_coord);
getLaneNr = 5*x_coord + y_coord;
endfunction | function integer getLaneNr(input integer x_coord, input integer y_coord); |
getLaneNr = 5*x_coord + y_coord;
endfunction | 0 |
140,600 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | function | function integer getXCoord(input integer lane_nr);
getXCoord = lane_nr / 5;
endfunction | function integer getXCoord(input integer lane_nr); |
getXCoord = lane_nr / 5;
endfunction | 0 |
140,601 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | function | function integer getYCoord(input integer lane_nr);
getYCoord = lane_nr % 5;
endfunction | function integer getYCoord(input integer lane_nr); |
getYCoord = lane_nr % 5;
endfunction | 0 |
140,602 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | function | function integer Idx(input integer s,
input integer x,
input integer y,
input integer len);
Idx = s*25*len + getLaneNr(x,y)*len;
endfunction | function integer Idx(input integer s,
input integer x,
input integer y,
input integer len); |
Idx = s*25*len + getLaneNr(x,y)*len;
endfunction | 0 |
140,603 | data/full_repos/permissive/90611392/keccak_top.v | 90,611,392 | keccak_top.v | v | 435 | 150 | [] | [] | [] | null | line:104: before: "(" | null | 1: b"%Error: data/full_repos/permissive/90611392/keccak_top.v:165: Can't resolve module reference: '_RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W'\n _RATE__must_be_a_multiple_of_the_lane_length__W__and_smaller_or_equal_to_25W DONT_COMPILE();\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,357 | function | function integer StateIdx(input integer s, input integer x, input integer y);
StateIdx = s*STATE_SIZE + getLaneNr(x,y)*W;
endfunction | function integer StateIdx(input integer s, input integer x, input integer y); |
StateIdx = s*STATE_SIZE + getLaneNr(x,y)*W;
endfunction | 0 |
140,605 | data/full_repos/permissive/90852660/Exp 1/a/and2gate_tb.v | 90,852,660 | and2gate_tb.v | v | 11 | 21 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: 1/a,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.sv\n 1/a,data/full_repos/permissive/90852660\n 1/a,data/full_repos/permissive/90852660.v\n 1/a,data/full_repos/permissive/90852660.sv\n obj_dir/1/a,data/full_repos/permissive/90852660\n obj_dir/1/a,data/full_repos/permissive/90852660.v\n obj_dir/1/a,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/a/and2gate_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,359 | module | module and2gate_tb;
reg a,b;
wire c;
and2gate a1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | module and2gate_tb; |
reg a,b;
wire c;
and2gate a1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | 3 |
140,606 | data/full_repos/permissive/90852660/Exp 1/a/notgate.v | 90,852,660 | notgate.v | v | 6 | 21 | [] | [] | [] | [(1, 5)] | null | null | 1: b'%Error: Cannot find file containing module: 1/a,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.sv\n 1/a,data/full_repos/permissive/90852660\n 1/a,data/full_repos/permissive/90852660.v\n 1/a,data/full_repos/permissive/90852660.sv\n obj_dir/1/a,data/full_repos/permissive/90852660\n obj_dir/1/a,data/full_repos/permissive/90852660.v\n obj_dir/1/a,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/a/notgate.v\n%Error: Exiting due to 3 error(s)\n' | 309,360 | module | module notgate(A,B);
input A;
output B;
assign A=!B;
endmodule | module notgate(A,B); |
input A;
output B;
assign A=!B;
endmodule | 3 |
140,607 | data/full_repos/permissive/90852660/Exp 1/a/notgate_tb.v | 90,852,660 | notgate_tb.v | v | 9 | 19 | [] | [] | [] | [(1, 9)] | null | null | 1: b'%Error: Cannot find file containing module: 1/a,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.sv\n 1/a,data/full_repos/permissive/90852660\n 1/a,data/full_repos/permissive/90852660.v\n 1/a,data/full_repos/permissive/90852660.sv\n obj_dir/1/a,data/full_repos/permissive/90852660\n obj_dir/1/a,data/full_repos/permissive/90852660.v\n obj_dir/1/a,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/a/notgate_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,361 | module | module notgate_tb;
reg a;
wire b;
notgate n1(a,b);
initial begin
a=0; #100;
a=0; #100;
end
endmodule | module notgate_tb; |
reg a;
wire b;
notgate n1(a,b);
initial begin
a=0; #100;
a=0; #100;
end
endmodule | 3 |
140,608 | data/full_repos/permissive/90852660/Exp 1/a/or2gate.v | 90,852,660 | or2gate.v | v | 6 | 23 | [] | [] | [] | [(1, 5)] | null | null | 1: b'%Error: Cannot find file containing module: 1/a,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/a,data/full_repos/permissive/90852660.sv\n 1/a,data/full_repos/permissive/90852660\n 1/a,data/full_repos/permissive/90852660.v\n 1/a,data/full_repos/permissive/90852660.sv\n obj_dir/1/a,data/full_repos/permissive/90852660\n obj_dir/1/a,data/full_repos/permissive/90852660.v\n obj_dir/1/a,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/a/or2gate.v\n%Error: Exiting due to 3 error(s)\n' | 309,362 | module | module or2gate(A,B,C);
input A,B;
output C;
assign C = A|B;
endmodule | module or2gate(A,B,C); |
input A,B;
output C;
assign C = A|B;
endmodule | 3 |
140,610 | data/full_repos/permissive/90852660/Exp 1/b/nand2gate.v | 90,852,660 | nand2gate.v | v | 7 | 25 | [] | [] | [] | [(2, 6)] | null | null | 1: b'%Error: Cannot find file containing module: 1/b,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.sv\n 1/b,data/full_repos/permissive/90852660\n 1/b,data/full_repos/permissive/90852660.v\n 1/b,data/full_repos/permissive/90852660.sv\n obj_dir/1/b,data/full_repos/permissive/90852660\n obj_dir/1/b,data/full_repos/permissive/90852660.v\n obj_dir/1/b,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/b/nand2gate.v\n%Error: Exiting due to 3 error(s)\n' | 309,364 | module | module nand2gate(A,B,C);
input A,B;
output C;
assign C = !(A&B);
endmodule | module nand2gate(A,B,C); |
input A,B;
output C;
assign C = !(A&B);
endmodule | 3 |
140,611 | data/full_repos/permissive/90852660/Exp 1/b/nand2gate_tb.v | 90,852,660 | nand2gate_tb.v | v | 11 | 22 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: 1/b,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.sv\n 1/b,data/full_repos/permissive/90852660\n 1/b,data/full_repos/permissive/90852660.v\n 1/b,data/full_repos/permissive/90852660.sv\n obj_dir/1/b,data/full_repos/permissive/90852660\n obj_dir/1/b,data/full_repos/permissive/90852660.v\n obj_dir/1/b,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/b/nand2gate_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,365 | module | module nand2gate_tb;
reg a,b;
wire c;
nand2gate n1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | module nand2gate_tb; |
reg a,b;
wire c;
nand2gate n1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | 3 |
140,612 | data/full_repos/permissive/90852660/Exp 1/b/nor2gate.v | 90,852,660 | nor2gate.v | v | 6 | 24 | [] | [] | [] | [(1, 5)] | null | null | 1: b'%Error: Cannot find file containing module: 1/b,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.sv\n 1/b,data/full_repos/permissive/90852660\n 1/b,data/full_repos/permissive/90852660.v\n 1/b,data/full_repos/permissive/90852660.sv\n obj_dir/1/b,data/full_repos/permissive/90852660\n obj_dir/1/b,data/full_repos/permissive/90852660.v\n obj_dir/1/b,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/b/nor2gate.v\n%Error: Exiting due to 3 error(s)\n' | 309,366 | module | module nor2gate(A,B,C);
input A,B;
output C;
assign C = !(A|B);
endmodule | module nor2gate(A,B,C); |
input A,B;
output C;
assign C = !(A|B);
endmodule | 3 |
140,613 | data/full_repos/permissive/90852660/Exp 1/b/nor2gate_tb.v | 90,852,660 | nor2gate_tb.v | v | 11 | 21 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: 1/b,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/b,data/full_repos/permissive/90852660.sv\n 1/b,data/full_repos/permissive/90852660\n 1/b,data/full_repos/permissive/90852660.v\n 1/b,data/full_repos/permissive/90852660.sv\n obj_dir/1/b,data/full_repos/permissive/90852660\n obj_dir/1/b,data/full_repos/permissive/90852660.v\n obj_dir/1/b,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/b/nor2gate_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,367 | module | module nor2gate_tb;
reg a,b;
wire c;
nor2gate n1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | module nor2gate_tb; |
reg a,b;
wire c;
nor2gate n1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | 3 |
140,614 | data/full_repos/permissive/90852660/Exp 1/c/1/xnor_direct_tb.v | 90,852,660 | xnor_direct_tb.v | v | 11 | 24 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: 1/c/1,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660.sv\n 1/c/1,data/full_repos/permissive/90852660\n 1/c/1,data/full_repos/permissive/90852660.v\n 1/c/1,data/full_repos/permissive/90852660.sv\n obj_dir/1/c/1,data/full_repos/permissive/90852660\n obj_dir/1/c/1,data/full_repos/permissive/90852660.v\n obj_dir/1/c/1,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/c/1/xnor_direct_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,369 | module | module xnor_direct_tb;
reg a,b;
wire c;
xnor_direct x1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | module xnor_direct_tb; |
reg a,b;
wire c;
xnor_direct x1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | 3 |
140,616 | data/full_repos/permissive/90852660/Exp 1/c/1/xor_direct_tb.v | 90,852,660 | xor_direct_tb.v | v | 11 | 23 | [] | [] | [] | [(1, 11)] | null | null | 1: b'%Error: Cannot find file containing module: 1/c/1,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/1/c/1,data/full_repos/permissive/90852660.sv\n 1/c/1,data/full_repos/permissive/90852660\n 1/c/1,data/full_repos/permissive/90852660.v\n 1/c/1,data/full_repos/permissive/90852660.sv\n obj_dir/1/c/1,data/full_repos/permissive/90852660\n obj_dir/1/c/1,data/full_repos/permissive/90852660.v\n obj_dir/1/c/1,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 1/c/1/xor_direct_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,371 | module | module xor_direct_tb;
reg a,b;
wire c;
xor_direct x1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | module xor_direct_tb; |
reg a,b;
wire c;
xor_direct x1(a,b,c);
initial begin
a=0; b=0; #100;
a=0; b=1; #100;
a=1; b=0; #100;
a=1; b=1; #100;
end
endmodule | 3 |
140,621 | data/full_repos/permissive/90852660/Exp 10/pipo.v | 90,852,660 | pipo.v | v | 13 | 34 | [] | [] | [] | [(1, 13)] | null | null | 1: b'%Error: Cannot find file containing module: 10,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.sv\n 10,data/full_repos/permissive/90852660\n 10,data/full_repos/permissive/90852660.v\n 10,data/full_repos/permissive/90852660.sv\n obj_dir/10,data/full_repos/permissive/90852660\n obj_dir/10,data/full_repos/permissive/90852660.v\n obj_dir/10,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 10/pipo.v\n%Error: Exiting due to 3 error(s)\n' | 309,376 | module | module pipo(clk,rst,a,q);
input clk,rst;
input[3:0]a;
output[3:0]q;
reg[3:0]q;
always@(posedge clk,posedge rst)
begin
if (rst==1'b1)
q<=4'b0000;
else
q<=a;
end
endmodule | module pipo(clk,rst,a,q); |
input clk,rst;
input[3:0]a;
output[3:0]q;
reg[3:0]q;
always@(posedge clk,posedge rst)
begin
if (rst==1'b1)
q<=4'b0000;
else
q<=a;
end
endmodule | 3 |
140,622 | data/full_repos/permissive/90852660/Exp 10/pipo_tb.v | 90,852,660 | pipo_tb.v | v | 17 | 26 | [] | [] | [] | null | line:71: before: "assign" | null | 1: b'%Error: Cannot find file containing module: 10,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.sv\n 10,data/full_repos/permissive/90852660\n 10,data/full_repos/permissive/90852660.v\n 10,data/full_repos/permissive/90852660.sv\n obj_dir/10,data/full_repos/permissive/90852660\n obj_dir/10,data/full_repos/permissive/90852660.v\n obj_dir/10,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 10/pipo_tb.v\n%Error: Exiting due to 3 error(s)\n' | 309,377 | module | module pipo_tb;
reg clk, rst;
reg [3:0]a;
wire [3:0]q;
initial clk='b1;
pipo p1(clk, rst, a, q);
always #10 clk=~clk;
initial begin
a=4'b1101;rst=1'b1;
#100 rst=1'b0;
#100 a=4'b1000;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial #600 $stop;
endmodule | module pipo_tb; |
reg clk, rst;
reg [3:0]a;
wire [3:0]q;
initial clk='b1;
pipo p1(clk, rst, a, q);
always #10 clk=~clk;
initial begin
a=4'b1101;rst=1'b1;
#100 rst=1'b0;
#100 a=4'b1000;
#100 rst=1'b1;
#100 rst=1'b0;
end
initial #600 $stop;
endmodule | 3 |
140,623 | data/full_repos/permissive/90852660/Exp 10/piso.v | 90,852,660 | piso.v | v | 21 | 34 | [] | [] | [] | [(1, 20)] | null | null | 1: b'%Error: Cannot find file containing module: 10,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.sv\n 10,data/full_repos/permissive/90852660\n 10,data/full_repos/permissive/90852660.v\n 10,data/full_repos/permissive/90852660.sv\n obj_dir/10,data/full_repos/permissive/90852660\n obj_dir/10,data/full_repos/permissive/90852660.v\n obj_dir/10,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 10/piso.v\n%Error: Exiting due to 3 error(s)\n' | 309,378 | module | module piso(clk,rst,a,q);
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1)
begin
q<=0;
temp<=a;
end
else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule | module piso(clk,rst,a,q); |
input clk,rst;
input [3:0]a;
output q;
reg q;
reg [3:0]temp;
always@(posedge clk,posedge rst)
begin
if(rst==1)
begin
q<=0;
temp<=a;
end
else
begin
q<=temp[0];
temp <= temp>>1'b1;
end
end
endmodule | 3 |
140,625 | data/full_repos/permissive/90852660/Exp 10/sipo.v | 90,852,660 | sipo.v | v | 19 | 34 | [] | [] | [] | [(1, 18)] | null | null | 1: b'%Error: Cannot find file containing module: 10,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.sv\n 10,data/full_repos/permissive/90852660\n 10,data/full_repos/permissive/90852660.v\n 10,data/full_repos/permissive/90852660.sv\n obj_dir/10,data/full_repos/permissive/90852660\n obj_dir/10,data/full_repos/permissive/90852660.v\n obj_dir/10,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 10/sipo.v\n%Error: Exiting due to 3 error(s)\n' | 309,380 | module | module sipo(clk,rst,a,q);
input a;
input clk,rst;
output [3:0]q;
wire [3:0]q;
reg [3:0]tmp;
always@(posedge clk,posedge rst)
begin
if (rst==1)
tmp=0;
else
begin
tmp=tmp<<1;
tmp[0]=a;
end
end
assign q=tmp;
endmodule | module sipo(clk,rst,a,q); |
input a;
input clk,rst;
output [3:0]q;
wire [3:0]q;
reg [3:0]tmp;
always@(posedge clk,posedge rst)
begin
if (rst==1)
tmp=0;
else
begin
tmp=tmp<<1;
tmp[0]=a;
end
end
assign q=tmp;
endmodule | 3 |
140,627 | data/full_repos/permissive/90852660/Exp 10/siso.v | 90,852,660 | siso.v | v | 24 | 28 | [] | [] | [] | [(1, 23)] | null | null | 1: b'%Error: Cannot find file containing module: 10,data/full_repos/permissive/90852660\n ... Looked in:\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.v\n data/full_repos/permissive/90852660/Exp/10,data/full_repos/permissive/90852660.sv\n 10,data/full_repos/permissive/90852660\n 10,data/full_repos/permissive/90852660.v\n 10,data/full_repos/permissive/90852660.sv\n obj_dir/10,data/full_repos/permissive/90852660\n obj_dir/10,data/full_repos/permissive/90852660.v\n obj_dir/10,data/full_repos/permissive/90852660.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/90852660/Exp\n%Error: Cannot find file containing module: 10/siso.v\n%Error: Exiting due to 3 error(s)\n' | 309,382 | module | module siso(
input in,
output out,
input rst,
input clk
);
reg [3:0] d;
reg out;
initial begin
d = 4'b0000;
end
always@(posedge clk) begin
if(rst == 1'b1) begin
d = 4'b0000;
out = 0;
end
else begin
out = d[0];
d = d >> 1;
d[3] = in;
end
end
endmodule | module siso(
input in,
output out,
input rst,
input clk
); |
reg [3:0] d;
reg out;
initial begin
d = 4'b0000;
end
always@(posedge clk) begin
if(rst == 1'b1) begin
d = 4'b0000;
out = 0;
end
else begin
out = d[0];
d = d >> 1;
d[3] = in;
end
end
endmodule | 3 |
Subsets and Splits