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140,283 | data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv | 90,320,290 | apb_write_read_word_seq.sv | sv | 45 | 81 | [] | [] | [] | null | line:4: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:4: Unsupported: classes\nclass apb_write_read_word_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:4: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_write_read_word_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_start_addr { start_addr[1:0] == 2\'b00; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:8: syntax error, unexpected IDENTIFIER\n constraint c_start_addr { start_addr[1:0] == 2\'b00; }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:11: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_write_read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:13: Unsupported: new constructor\n function new(string name="apb_write_read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:14: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:14: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:14: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:17: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:20: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence:",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:23: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:23: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:25: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { req.addr == start_addr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:26: syntax error, unexpected \';\'\n req.direction == APB_WRITE; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:28: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { req.addr == start_addr;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:29: syntax error, unexpected \';\'\n req.direction == APB_READ; })\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/apb_write_read_word_seq.sv:44: syntax error, unexpected endclass\nendclass : apb_write_read_word_seq\n^~~~~~~~\n%Error: Exiting due to 18 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,405 | function | function new(string name="apb_write_read_word_seq");
super.new(name);
endfunction | function new(string name="apb_write_read_word_seq"); |
super.new(name);
endfunction | 0 |
140,284 | data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv | 90,320,290 | multi_apb_transfer_seq.sv | sv | 32 | 81 | [] | [] | [] | null | line:4: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:4: Unsupported: classes\nclass multi_apb_transfer_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:4: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass multi_apb_transfer_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_seq { num_seq inside {[1:10]}; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:7: syntax error, unexpected IDENTIFIER\n constraint c_num_seq { num_seq inside {[1:10]}; }\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:10: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(multi_apb_transfer_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:11: Unsupported: new constructor\n function new(string name="multi_apb_transfer_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:15: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:16: syntax error, unexpected IDENTIFIER\n apb_transfer_seq apb_seq; \n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:19: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence:",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:24: Define or directive not defined: \'`uvm_do\'\n `uvm_do(apb_seq)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/multi_apb_transfer_seq.sv:27: syntax error, unexpected if\n if (starting_phase != null)\n ^~\n%Error: Exiting due to 14 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,406 | function | function new(string name="multi_apb_transfer_seq");
super.new(name);
endfunction | function new(string name="multi_apb_transfer_seq"); |
super.new(name);
endfunction | 0 |
140,285 | data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv | 90,320,290 | mydut_seq_lib.sv | sv | 23 | 81 | [] | [] | [] | null | line:4: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:4: Unsupported: classes\nclass mydut_seq_lib extends uvm_sequence_library #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:4: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass mydut_seq_lib extends uvm_sequence_library #(apb_transfer);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:6: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(mydut_seq_lib)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:7: Define or directive not defined: \'`uvm_sequence_library_utils\'\n `uvm_sequence_library_utils(mydut_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:9: Unsupported: new constructor\n function new(string name="mydut_seq_lib");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:10: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:10: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:10: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:15: syntax error, unexpected ::, expecting \')\'\n add_sequence(apb_transfer_seq::get_type());\n ^~\n : ... Perhaps \'apb_transfer_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:16: syntax error, unexpected ::, expecting \')\'\n add_sequence(multi_apb_transfer_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:17: syntax error, unexpected ::, expecting \')\'\n add_sequence(apb_write_read_word_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:18: syntax error, unexpected ::, expecting \')\'\n add_sequence(apb_traffic_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/5_interface_uvcs/sv/mydut_seq_lib.sv:22: syntax error, unexpected endclass\nendclass : mydut_seq_lib\n^~~~~~~~\n%Error: Exiting due to 13 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,407 | function | function new(string name="mydut_seq_lib");
super.new(name);
min_random_count = 1;
max_random_count = 5;
add_sequence(apb_transfer_seq::get_type());
add_sequence(multi_apb_transfer_seq::get_type());
add_sequence(apb_write_read_word_seq::get_type());
add_sequence(apb_traffic_seq::get_type());
init_sequence_library();
endfunction | function new(string name="mydut_seq_lib"); |
super.new(name);
min_random_count = 1;
max_random_count = 5;
add_sequence(apb_transfer_seq::get_type());
add_sequence(multi_apb_transfer_seq::get_type());
add_sequence(apb_write_read_word_seq::get_type());
add_sequence(apb_traffic_seq::get_type());
init_sequence_library();
endfunction | 0 |
140,286 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv | 90,320,290 | ex7-10_uart_ctrl_override_test.sv | sv | 36 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: Unsupported: classes\nclass short_delay_frame extends uart_frame;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_frame extends uart_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_test1_txmit_delay {transmit_delay < 10;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:10: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(short_delay_frame)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:11: Unsupported: new constructor\n function new(string name="short_delay_frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:14: syntax error, unexpected endclass\nendclass: short_delay_frame\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: Unsupported: classes\nclass short_delay_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:19: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(short_delay_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,408 | function | function new(string name="short_delay_frame");
super.new(name);
endfunction | function new(string name="short_delay_frame"); |
super.new(name);
endfunction | 0 |
140,287 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv | 90,320,290 | ex7-10_uart_ctrl_override_test.sv | sv | 36 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: Unsupported: classes\nclass short_delay_frame extends uart_frame;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_frame extends uart_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_test1_txmit_delay {transmit_delay < 10;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:10: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(short_delay_frame)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:11: Unsupported: new constructor\n function new(string name="short_delay_frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:14: syntax error, unexpected endclass\nendclass: short_delay_frame\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: Unsupported: classes\nclass short_delay_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:19: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(short_delay_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,408 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,288 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv | 90,320,290 | ex7-10_uart_ctrl_override_test.sv | sv | 36 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: Unsupported: classes\nclass short_delay_frame extends uart_frame;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_frame extends uart_frame;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_test1_txmit_delay {transmit_delay < 10;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:10: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(short_delay_frame)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:11: Unsupported: new constructor\n function new(string name="short_delay_frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:12: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:14: syntax error, unexpected endclass\nendclass: short_delay_frame\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: Unsupported: classes\nclass short_delay_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass short_delay_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:19: Define or directive not defined: \'`uvm_component_utils\'\n`uvm_component_utils(short_delay_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-10_uart_ctrl_override_test.sv:24: syntax error, unexpected IDENTIFIER, expecting \')\'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 15 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,408 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
factory.set_type_override_by_type(uart_frame::get_type(),
short_delay_frame::get_type());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
factory.set_type_override_by_type(uart_frame::get_type(),
short_delay_frame::get_type());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | 0 |
140,289 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv | 90,320,290 | ex7-11_retry_seq.sv | sv | 41 | 82 | [] | [] | [] | null | line:7: before: "16" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:7: Cannot find include file: uart_if.sv\n`include "uart_if.sv" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.sv\n uart_if.sv\n uart_if.sv.v\n uart_if.sv.sv\n obj_dir/uart_if.sv\n obj_dir/uart_if.sv.v\n obj_dir/uart_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:10: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:16: Unsupported: classes\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:20: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:20: syntax error, unexpected \'(\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:21: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:24: Unsupported: new constructor\n function new(string name="uart_retry_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:25: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:25: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:25: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:28: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:29: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RETRY_SEQ", {"Executing sequence: ", get_type_name()}, UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:29: syntax error, unexpected \',\'\n `uvm_info("RETRY_SEQ", {"Executing sequence: ", get_type_name()}, UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload; parity_type == uart_pkg::BAD_PARITY;})\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, { payload == pload; parity_type == uart_pkg::BAD_PARITY;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:33: syntax error, unexpected ::\n `uvm_do_with(req, { payload == pload; parity_type == uart_pkg::BAD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:35: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload; parity_type == uart_pkg::GOOD_PARITY;})\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:35: syntax error, unexpected ::\n `uvm_do_with(req, { payload == pload; parity_type == uart_pkg::GOOD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-11_retry_seq.sv:40: syntax error, unexpected endclass\nendclass : uart_retry_seq\n^~~~~~~~\n%Error: Exiting due to 21 error(s)\n' | 308,409 | function | function new(string name="uart_retry_seq");
super.new(name);
endfunction | function new(string name="uart_retry_seq"); |
super.new(name);
endfunction | 0 |
140,290 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv | 90,320,290 | ex7-12_rand_retry_seq.sv | sv | 72 | 73 | [] | [] | [] | null | line:7: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:7: Cannot find include file: uart_if.sv\n`include "uart_if.sv" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.sv\n uart_if.sv\n uart_if.sv.v\n uart_if.sv.sv\n obj_dir/uart_if.sv\n obj_dir/uart_if.sv.v\n obj_dir/uart_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:15: Unsupported: classes\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:19: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:19: syntax error, unexpected \'(\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:20: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:22: Unsupported: new constructor\n function new(string name="uart_retry_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:26: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:28: Unsupported: this\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:29: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RETRY_SEQ", "Executing.", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:29: syntax error, unexpected \',\'\n `uvm_info("RETRY_SEQ", "Executing.", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:31: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:32: syntax error, unexpected ::\n parity_type == uart_pkg::BAD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:34: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:35: syntax error, unexpected ::\n parity_type == uart_pkg::GOOD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:39: syntax error, unexpected endclass\nendclass : uart_retry_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:44: Unsupported: classes\nclass rand_retry_seq extends uvm_sequence #(uart_frame);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:44: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass rand_retry_seq extends uvm_sequence #(uart_frame);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:47: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(rand_retry_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:50: Unsupported: new constructor\n function new(string name="rand_retry_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:57: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:59: Unsupported: this\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:60: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RAND_RETRY_SEQ", "Executing.", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:60: syntax error, unexpected \',\'\n `uvm_info("RAND_RETRY_SEQ", "Executing.", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:62: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:64: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(retry_seq, { pload inside {[0:31]};})\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:66: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: Exiting due to 35 error(s)\n' | 308,410 | function | function new(string name="uart_retry_seq");
super.new(name);
endfunction | function new(string name="uart_retry_seq"); |
super.new(name);
endfunction | 0 |
140,291 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv | 90,320,290 | ex7-12_rand_retry_seq.sv | sv | 72 | 73 | [] | [] | [] | null | line:7: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:7: Cannot find include file: uart_if.sv\n`include "uart_if.sv" \n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uart_if.sv.sv\n uart_if.sv\n uart_if.sv.v\n uart_if.sv.sv\n obj_dir/uart_if.sv\n obj_dir/uart_if.sv.v\n obj_dir/uart_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:9: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:15: Unsupported: classes\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_retry_seq extends uvm_sequence #(uart_frame);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:19: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:19: syntax error, unexpected \'(\'\n `uvm_object_utils(uart_retry_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:20: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:22: Unsupported: new constructor\n function new(string name="uart_retry_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:23: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:26: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:28: Unsupported: this\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:29: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RETRY_SEQ", "Executing.", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:29: syntax error, unexpected \',\'\n `uvm_info("RETRY_SEQ", "Executing.", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:31: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:32: syntax error, unexpected ::\n parity_type == uart_pkg::BAD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:34: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, { payload == pload;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:35: syntax error, unexpected ::\n parity_type == uart_pkg::GOOD_PARITY;})\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:39: syntax error, unexpected endclass\nendclass : uart_retry_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:44: Unsupported: classes\nclass rand_retry_seq extends uvm_sequence #(uart_frame);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:44: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass rand_retry_seq extends uvm_sequence #(uart_frame);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:47: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(rand_retry_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:50: Unsupported: new constructor\n function new(string name="rand_retry_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:57: syntax error, unexpected virtual\n virtual task body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:59: Unsupported: this\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:60: Define or directive not defined: \'`uvm_info\'\n `uvm_info("RAND_RETRY_SEQ", "Executing.", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:60: syntax error, unexpected \',\'\n `uvm_info("RAND_RETRY_SEQ", "Executing.", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:62: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:64: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(retry_seq, { pload inside {[0:31]};})\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-12_rand_retry_seq.sv:66: Define or directive not defined: \'`uvm_do\'\n `uvm_do(req)\n ^~~~~~~\n%Error: Exiting due to 35 error(s)\n' | 308,410 | function | function new(string name="rand_retry_seq");
super.new(name);
endfunction | function new(string name="rand_retry_seq"); |
super.new(name);
endfunction | 0 |
140,292 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv | 90,320,290 | ex7-13_directed_test.sv | sv | 96 | 100 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:23: Cannot find include file: tb/uart_ctrl_simple_tb.sv\n `include "tb/uart_ctrl_simple_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:25: Cannot find include file: tb/test_lib.sv\n `include "tb/test_lib.sv" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: Unsupported: classes\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:47: syntax error, unexpected super\n super.run_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:48: syntax error, unexpected \'(\', expecting IDENTIFIER\n phase.raise_objection(this, "Test: config_uart_ctrl_test");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:53: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:54: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h83;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:55: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.direction = APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.transmit_delay = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:57: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:59: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:61: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:63: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:65: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:69: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:83: Unsupported: Ignoring delay on this delayed statement.\n #51 reset <= 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:85: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:89: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'config_uart_ctrl_test\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,411 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
`include "tb/uart_ctrl_simple_tb.sv"
`include "tb/test_lib.sv"
class config_uart_ctrl_test extends uart_ctrl_base_test;
`uvm_component_utils(config_uart_ctrl_test)
function new(string name="config_uart_ctrl_test", uvm_component parent=null);
super.new(name, parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
apb_transfer transfer;
super.run_phase(phase);
phase.raise_objection(this, "Test: config_uart_ctrl_test");
transfer = apb_transfer::type_id::create("transfer", this);
#100
$finish;
transfer.addr = 8'h03;
transfer.data = 8'h83;
transfer.direction = APB_WRITE;
transfer.transmit_delay = 1;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h00;
transfer.data = 8'h01;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h01;
transfer.data = 8'h00;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h03;
transfer.data = 8'h03;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
#300
phase.drop_objection(this, "Test: config_uart_ctrl_test");
endtask : run_phase
endclass : config_uart_ctrl_test
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
reset <= 1'b0;
clk <= 1'b0;
#51 reset <= 1'b1;
end
always #5 clk = ~clk;
initial begin
uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "uvm_test_top.uart_ctrl_tb0.uart0*", "vif", uart_if0);
run_test("config_uart_ctrl_test");
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
`include "tb/uart_ctrl_simple_tb.sv"
`include "tb/test_lib.sv"
class config_uart_ctrl_test extends uart_ctrl_base_test;
`uvm_component_utils(config_uart_ctrl_test)
function new(string name="config_uart_ctrl_test", uvm_component parent=null);
super.new(name, parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
apb_transfer transfer;
super.run_phase(phase);
phase.raise_objection(this, "Test: config_uart_ctrl_test");
transfer = apb_transfer::type_id::create("transfer", this);
#100
$finish;
transfer.addr = 8'h03;
transfer.data = 8'h83;
transfer.direction = APB_WRITE;
transfer.transmit_delay = 1;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h00;
transfer.data = 8'h01;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h01;
transfer.data = 8'h00;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
transfer.addr = 8'h03;
transfer.data = 8'h03;
uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);
#300
phase.drop_objection(this, "Test: config_uart_ctrl_test");
endtask : run_phase
endclass : config_uart_ctrl_test
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
reset <= 1'b0;
clk <= 1'b0;
#51 reset <= 1'b1;
end
always #5 clk = ~clk;
initial begin
uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "uvm_test_top.uart_ctrl_tb0.uart0*", "vif", uart_if0);
run_test("config_uart_ctrl_test");
end
endmodule | 0 |
140,293 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv | 90,320,290 | ex7-13_directed_test.sv | sv | 96 | 100 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:23: Cannot find include file: tb/uart_ctrl_simple_tb.sv\n `include "tb/uart_ctrl_simple_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:25: Cannot find include file: tb/test_lib.sv\n `include "tb/test_lib.sv" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: Unsupported: classes\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:47: syntax error, unexpected super\n super.run_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:48: syntax error, unexpected \'(\', expecting IDENTIFIER\n phase.raise_objection(this, "Test: config_uart_ctrl_test");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:53: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:54: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h83;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:55: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.direction = APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.transmit_delay = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:57: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:59: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:61: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:63: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:65: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:69: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:83: Unsupported: Ignoring delay on this delayed statement.\n #51 reset <= 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:85: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:89: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'config_uart_ctrl_test\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,411 | function | function new(string name="config_uart_ctrl_test", uvm_component parent=null);
super.new(name, parent);
endfunction | function new(string name="config_uart_ctrl_test", uvm_component parent=null); |
super.new(name, parent);
endfunction | 0 |
140,294 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv | 90,320,290 | ex7-13_directed_test.sv | sv | 96 | 100 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:23: Cannot find include file: tb/uart_ctrl_simple_tb.sv\n `include "tb/uart_ctrl_simple_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:25: Cannot find include file: tb/test_lib.sv\n `include "tb/test_lib.sv" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: Unsupported: classes\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass config_uart_ctrl_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:47: syntax error, unexpected super\n super.run_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:48: syntax error, unexpected \'(\', expecting IDENTIFIER\n phase.raise_objection(this, "Test: config_uart_ctrl_test");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:53: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:54: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h83;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:55: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.direction = APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.transmit_delay = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:57: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:59: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:61: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:63: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h01;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h00;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:65: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.addr = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n transfer.data = 8\'h03;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:69: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart_ctrl_tb0.apb0.master.sequencer.execute_item(transfer);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:83: Unsupported: Ignoring delay on this delayed statement.\n #51 reset <= 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:85: Unsupported: Ignoring delay on this delayed statement.\nalways #5 clk = ~clk;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:89: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "uvm_test_top.uart_ctrl_tb0.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-13_directed_test.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'config_uart_ctrl_test\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,411 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
endfunction | 0 |
140,295 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv | 90,320,290 | ex7-14_base_virtual_sequence.sv | sv | 26 | 67 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:7: Unsupported: classes\nclass base_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass base_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:9: Unsupported: new constructor\n function new(string name="base_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:10: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:10: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:10: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:13: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(base_vseq) \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:13: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(base_vseq) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:14: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:18: Unsupported: this\n starting_phase.raise_objection(this, "Running sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:21: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:23: Unsupported: this\n starting_phase.drop_objection(this, "Completed sequence");\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-14_base_virtual_sequence.sv:25: syntax error, unexpected endclass\nendclass : base_vseq\n^~~~~~~~\n%Error: Exiting due to 13 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,412 | function | function new(string name="base_vseq");
super.new(name);
endfunction | function new(string name="base_vseq"); |
super.new(name);
endfunction | 0 |
140,296 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv | 90,320,290 | ex7-15_virtual_sequence.sv | sv | 33 | 66 | [] | [] | [] | null | line:7: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:7: Unsupported: classes\nclass u2a_a2u_vseq extends base_vseq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_a2u_vseq extends base_vseq;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:9: Unsupported: new constructor\n function new(string name="u2a_a2u_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:10: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:10: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:10: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:13: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(u2a_a2u_vseq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:13: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_object_utils(u2a_a2u_vseq)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:23: Define or directive not defined: \'`uvm_info\'\n `uvm_info("U2A_A2U_VSEQ", "Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:23: syntax error, unexpected \',\'\n `uvm_info("U2A_A2U_VSEQ", "Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:25: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(config_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:28: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(u2a_seq, p_sequencer.uart_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-15_virtual_sequence.sv:29: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(a2u_seq, p_sequencer.apb_seqr)\n ^~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,413 | function | function new(string name="u2a_a2u_vseq");
super.new(name);
endfunction | function new(string name="u2a_a2u_vseq"); |
super.new(name);
endfunction | 0 |
140,297 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv | 90,320,290 | ex7-1_uart_ctrl_tb.sv | sv | 108 | 96 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:92: Cannot find include file: tb/simple_test.sv\n `include "tb/simple_test.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: syntax error, unexpected \'(\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n apb_cfg = apb_config::type_id::create("apb_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:57: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:58: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_slave("slave0", 32\'h00000000, 32\'h81FFFFFF, 0, UVM_PASSIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:61: syntax error, unexpected \'=\', expecting IDENTIFIER\n uart_cfg = uart_config::type_id::create("uart_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:63: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:64: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:65: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:66: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:79: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:80: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:81: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:82: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:85: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.apb_seqr = apb0.master.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:87: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.uart_seqr = uart0.Tx.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:101: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_ctrl_tb\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,414 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
class uart_ctrl_tb extends uvm_env;
apb_pkg::apb_env apb0;
uart_pkg::uart_env uart0;
uart_ctrl_tx_scbd tx_scbd;
uart_ctrl_rx_scbd rx_scbd;
uart_ctrl_virtual_sequencer virtual_sequencer;
apb_config apb_cfg;
uart_config uart_cfg;
`uvm_component_utils(uart_ctrl_tb)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction : build_phase
function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction : connect_phase
`include "tb/simple_test.sv"
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "*.my_tb.uart0*", "vif", uart_if0);
run_test("simple_test");
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
import uart_pkg::*;
`include "sv/uart_ctrl_defines.svh"
`include "sv/uart_ctrl_config.sv"
`include "sv/uart_ctrl_virtual_sequencer.sv"
`include "sv/uart_ctrl_scoreboard.sv"
class uart_ctrl_tb extends uvm_env;
apb_pkg::apb_env apb0;
uart_pkg::uart_env uart0;
uart_ctrl_tx_scbd tx_scbd;
uart_ctrl_rx_scbd rx_scbd;
uart_ctrl_virtual_sequencer virtual_sequencer;
apb_config apb_cfg;
uart_config uart_cfg;
`uvm_component_utils(uart_ctrl_tb)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
extern virtual function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction : build_phase
function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction : connect_phase
`include "tb/simple_test.sv"
bit clk, reset;
apb_if apb_if0(clk, reset);
uart_if uart_if0(clk, reset);
initial begin
uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);
uvm_config_db#(virtual uart_if)::set(null, "*.my_tb.uart0*", "vif", uart_if0);
run_test("simple_test");
end
endmodule | 0 |
140,298 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv | 90,320,290 | ex7-1_uart_ctrl_tb.sv | sv | 108 | 96 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:92: Cannot find include file: tb/simple_test.sv\n `include "tb/simple_test.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: syntax error, unexpected \'(\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n apb_cfg = apb_config::type_id::create("apb_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:57: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:58: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_slave("slave0", 32\'h00000000, 32\'h81FFFFFF, 0, UVM_PASSIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:61: syntax error, unexpected \'=\', expecting IDENTIFIER\n uart_cfg = uart_config::type_id::create("uart_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:63: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:64: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:65: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:66: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:79: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:80: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:81: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:82: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:85: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.apb_seqr = apb0.master.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:87: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.uart_seqr = uart0.Tx.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:101: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_ctrl_tb\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,414 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,299 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv | 90,320,290 | ex7-1_uart_ctrl_tb.sv | sv | 108 | 96 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:92: Cannot find include file: tb/simple_test.sv\n `include "tb/simple_test.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: syntax error, unexpected \'(\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n apb_cfg = apb_config::type_id::create("apb_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:57: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:58: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_slave("slave0", 32\'h00000000, 32\'h81FFFFFF, 0, UVM_PASSIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:61: syntax error, unexpected \'=\', expecting IDENTIFIER\n uart_cfg = uart_config::type_id::create("uart_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:63: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:64: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:65: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:66: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:79: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:80: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:81: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:82: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:85: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.apb_seqr = apb0.master.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:87: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.uart_seqr = uart0.Tx.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:101: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_ctrl_tb\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,414 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
endclass : uart_ctrl_tb
function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | 0 |
140,300 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv | 90,320,290 | ex7-1_uart_ctrl_tb.sv | sv | 108 | 96 | [] | [] | [] | null | line:9: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:10: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:17: Cannot find include file: sv/uart_ctrl_defines.svh\n `include "sv/uart_ctrl_defines.svh" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:18: Cannot find include file: sv/uart_ctrl_config.sv\n `include "sv/uart_ctrl_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:19: Cannot find include file: sv/uart_ctrl_virtual_sequencer.sv\n `include "sv/uart_ctrl_virtual_sequencer.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:20: Cannot find include file: sv/uart_ctrl_scoreboard.sv\n `include "sv/uart_ctrl_scoreboard.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:92: Cannot find include file: tb/simple_test.sv\n `include "tb/simple_test.sv" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:9: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: Unsupported: classes\nclass uart_ctrl_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:22: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:40: syntax error, unexpected \'(\'\n `uvm_component_utils(uart_ctrl_tb)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:56: syntax error, unexpected \'=\', expecting IDENTIFIER\n apb_cfg = apb_config::type_id::create("apb_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:57: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:58: syntax error, unexpected \'(\', expecting IDENTIFIER\n apb_cfg.add_slave("slave0", 32\'h00000000, 32\'h81FFFFFF, 0, UVM_PASSIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:61: syntax error, unexpected \'=\', expecting IDENTIFIER\n uart_cfg = uart_config::type_id::create("uart_cfg", this);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:63: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:64: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:65: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:66: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:79: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:80: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:81: syntax error, unexpected \'.\', expecting IDENTIFIER\n uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:82: syntax error, unexpected \'.\', expecting IDENTIFIER\n apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:85: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.apb_seqr = apb0.master.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:87: syntax error, unexpected \'=\', expecting IDENTIFIER\n virtual_sequencer.uart_seqr = uart0.Tx.sequencer;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:101: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.my_tb.apb0*", "vif", apb_if0);\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-1_uart_ctrl_tb.sv:7: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_ctrl_tb\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,414 | function | function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | function void uart_ctrl_tb::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | 0 |
140,301 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-2_tb_build_phase.sv | 90,320,290 | ex7-2_tb_build_phase.sv | sv | 36 | 96 | [] | [] | [] | null | line:9: before: "function" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-2_tb_build_phase.sv:9: syntax error, unexpected ::, expecting '(' or ';'\nfunction void uart_ctrl_tb::build_phase(uvm_phase phase);\n ^~\n : ... Perhaps 'uart_ctrl_tb' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Exiting due to 1 error(s)\n" | 308,415 | function | function void uart_ctrl_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | function void uart_ctrl_tb::build_phase(uvm_phase phase); |
super.build_phase(phase);
if (apb_cfg == null) begin
apb_cfg = apb_config::type_id::create("apb_cfg", this);
apb_cfg.add_master("master", UVM_ACTIVE);
apb_cfg.add_slave("slave0", 32'h00000000, 32'h81FFFFFF, 0, UVM_PASSIVE);
end
if (uart_cfg == null) begin
uart_cfg = uart_config::type_id::create("uart_cfg", this);
end
uvm_config_db#(apb_config)::set(this, "apb0*", "cfg", apb_cfg);
uvm_config_db#(uart_config)::set(this, "uart0*", "cfg", uart_cfg);
uvm_config_db#(uart_config)::set(this, "*scbd*", "uart_cfg", uart_cfg);
uvm_config_db#(apb_slave_config)::set(this, "*scbd*", "slave_cfg", apb_cfg.slave_configs[0]);
apb0 = apb_env::type_id::create("apb0", this);
uart0 = uart_env::type_id::create("uart0", this);
virtual_sequencer = uart_ctrl_virtual_sequencer::type_id::create("virtual_sequencer", this);
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd", this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd", this);
endfunction | 0 |
140,302 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-3_tb_connect_phase.sv | 90,320,290 | ex7-3_tb_connect_phase.sv | sv | 23 | 69 | [] | [] | [] | null | line:9: before: "function" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-3_tb_connect_phase.sv:9: syntax error, unexpected ::, expecting '(' or ';'\nfunction void uart_ctrl_tb::connect_phase(uvm_phase phase);\n ^~\n : ... Perhaps 'uart_ctrl_tb' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Exiting due to 1 error(s)\n" | 308,416 | function | function void uart_ctrl_tb::connect_phase(uvm_phase phase);
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | function void uart_ctrl_tb::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
uart0.Rx.monitor.frame_collected_port.connect(rx_scbd.uart_match);
apb0.bus_monitor.item_collected_port.connect(rx_scbd.apb_add);
uart0.Tx.monitor.frame_collected_port.connect(tx_scbd.uart_add);
apb0.bus_monitor.item_collected_port.connect(tx_scbd.apb_match);
virtual_sequencer.apb_seqr = apb0.master.sequencer;
if (uart0.Tx.get_is_active() == UVM_ACTIVE)
virtual_sequencer.uart_seqr = uart0.Tx.sequencer;
endfunction | 0 |
140,303 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv | 90,320,290 | ex7-4_virtual_sequencer.sv | sv | 28 | 76 | [] | [] | [] | null | line:16: before: "class" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv:16: Unsupported: classes\nclass uart_ctrl_virtual_sequencer extends uvm_sequencer;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_virtual_sequencer extends uvm_sequencer;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv:21: Unsupported: new constructor\n function new (input string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv:21: syntax error, unexpected IDENTIFIER, expecting ')'\n function new (input string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-4_virtual_sequencer.sv:25: Define or directive not defined: '`uvm_component_utils'\n `uvm_component_utils(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,417 | function | function new (input string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (input string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,304 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv | 90,320,290 | ex7-6_uart_config.sv | sv | 128 | 80 | [] | [] | [] | null | line:8: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:9: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: Unsupported: classes\nclass uart_config extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_config extends uvm_object;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_tx_active = UVM_ACTIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:19: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_rx_active = UVM_PASSIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: syntax error, unexpected \'{\', expecting IDENTIFIER\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_tx_en { tx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rx_en { rx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rts_en { rts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_cts_en { cts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_ua_chmode { ua_chmode == 2\'b00;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:65: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_config)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:66: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:67: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:68: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:69: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:70: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(char_length, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:71: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(nbstop, UVM_DEFAULT ) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:72: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_en, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:75: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_mode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:78: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_chmode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:86: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : char_len_val = 5;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:102: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : char_len_val = 6;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b10 : char_len_val = 7;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b11 : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:105: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:112: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : stop_bit_val = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:114: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: Hierarchical class references\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: scoped class reference\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:115: Unsupported: scoped class reference\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: syntax error, unexpected ::, expecting \';\'\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n : ... Perhaps \'type_id\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:6: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_config\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,419 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
class uart_config extends uvm_object;
uvm_active_passive_enum is_tx_active = UVM_ACTIVE;
uvm_active_passive_enum is_rx_active = UVM_PASSIVE;
rand bit [7:0] baud_rate_gen;
rand bit [7:0] baud_rate_div;
rand bit [1:0] char_length = 2;
rand bit nbstop=1;
rand bit parity_en ;
rand bit parity_even;
rand bit parity_stick;
rand bit [1:0] parity_mode=1;
rand bit break_ctl;
rand bit dl_access;
rand bit [1:0] ua_chmode;
rand bit rx_en = 1'b1;
rand bit tx_en = 1'b1;
rand bit cts_en ;
rand bit rts_en ;
rand bit [10:0] ua_ier;
rand bit [10:0] ua_idr;
rand bit [4:0] ua_rtrig;
byte unsigned char_len_val;
byte unsigned stop_bit_val;
constraint c_num_stop_bits { nbstop inside {[0:2]};}
constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}
constraint c_tx_en { tx_en == 1;}
constraint c_rx_en { rx_en == 1;}
constraint c_rts_en { rts_en == 0;}
constraint c_cts_en { cts_en == 0;}
constraint c_ua_chmode { ua_chmode == 2'b00;}
`uvm_object_utils_begin(uart_config)
`uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)
`uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)
`uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)
`uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)
`uvm_field_int(char_length, UVM_DEFAULT)
`uvm_field_int(nbstop, UVM_DEFAULT )
`uvm_field_int(parity_en, UVM_DEFAULT)
`uvm_field_int(parity_mode, UVM_DEFAULT)
`uvm_field_int(ua_chmode, UVM_DEFAULT)
`uvm_object_utils_end
function new(string name = "uart_config");
super.new(name);
endfunction
function void post_randomize();
ConvToIntChrl();
ConvToIntStpBt();
endfunction
function void ConvToIntChrl();
case(char_length)
2'b00 : char_len_val = 5;
2'b01 : char_len_val = 6;
2'b10 : char_len_val = 7;
2'b11 : char_len_val = 8;
default : char_len_val = 8;
endcase
endfunction : ConvToIntChrl
function void ConvToIntStpBt();
case(nbstop)
2'b00 : stop_bit_val = 1;
2'b01 : stop_bit_val = 2;
default : stop_bit_val = 2;
endcase
endfunction : ConvToIntStpBt
endclass
uart_config uart_cfg;
initial begin
uart_cfg = uart_config::type_id::create("uart_cfg");
uart_cfg.print();
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
class uart_config extends uvm_object;
uvm_active_passive_enum is_tx_active = UVM_ACTIVE;
uvm_active_passive_enum is_rx_active = UVM_PASSIVE;
rand bit [7:0] baud_rate_gen;
rand bit [7:0] baud_rate_div;
rand bit [1:0] char_length = 2;
rand bit nbstop=1;
rand bit parity_en ;
rand bit parity_even;
rand bit parity_stick;
rand bit [1:0] parity_mode=1;
rand bit break_ctl;
rand bit dl_access;
rand bit [1:0] ua_chmode;
rand bit rx_en = 1'b1;
rand bit tx_en = 1'b1;
rand bit cts_en ;
rand bit rts_en ;
rand bit [10:0] ua_ier;
rand bit [10:0] ua_idr;
rand bit [4:0] ua_rtrig;
byte unsigned char_len_val;
byte unsigned stop_bit_val;
constraint c_num_stop_bits { nbstop inside {[0:2]};}
constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}
constraint c_tx_en { tx_en == 1;}
constraint c_rx_en { rx_en == 1;}
constraint c_rts_en { rts_en == 0;}
constraint c_cts_en { cts_en == 0;}
constraint c_ua_chmode { ua_chmode == 2'b00;}
`uvm_object_utils_begin(uart_config)
`uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)
`uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)
`uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)
`uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)
`uvm_field_int(char_length, UVM_DEFAULT)
`uvm_field_int(nbstop, UVM_DEFAULT )
`uvm_field_int(parity_en, UVM_DEFAULT)
`uvm_field_int(parity_mode, UVM_DEFAULT)
`uvm_field_int(ua_chmode, UVM_DEFAULT)
`uvm_object_utils_end
function new(string name = "uart_config");
super.new(name);
endfunction
function void post_randomize();
ConvToIntChrl();
ConvToIntStpBt();
endfunction
function void ConvToIntChrl();
case(char_length)
2'b00 : char_len_val = 5;
2'b01 : char_len_val = 6;
2'b10 : char_len_val = 7;
2'b11 : char_len_val = 8;
default : char_len_val = 8;
endcase
endfunction : ConvToIntChrl
function void ConvToIntStpBt();
case(nbstop)
2'b00 : stop_bit_val = 1;
2'b01 : stop_bit_val = 2;
default : stop_bit_val = 2;
endcase
endfunction : ConvToIntStpBt
endclass
uart_config uart_cfg;
initial begin
uart_cfg = uart_config::type_id::create("uart_cfg");
uart_cfg.print();
end
endmodule | 0 |
140,305 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv | 90,320,290 | ex7-6_uart_config.sv | sv | 128 | 80 | [] | [] | [] | null | line:8: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:9: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: Unsupported: classes\nclass uart_config extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_config extends uvm_object;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_tx_active = UVM_ACTIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:19: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_rx_active = UVM_PASSIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: syntax error, unexpected \'{\', expecting IDENTIFIER\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_tx_en { tx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rx_en { rx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rts_en { rts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_cts_en { cts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_ua_chmode { ua_chmode == 2\'b00;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:65: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_config)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:66: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:67: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:68: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:69: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:70: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(char_length, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:71: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(nbstop, UVM_DEFAULT ) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:72: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_en, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:75: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_mode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:78: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_chmode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:86: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : char_len_val = 5;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:102: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : char_len_val = 6;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b10 : char_len_val = 7;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b11 : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:105: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:112: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : stop_bit_val = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:114: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: Hierarchical class references\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: scoped class reference\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:115: Unsupported: scoped class reference\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: syntax error, unexpected ::, expecting \';\'\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n : ... Perhaps \'type_id\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:6: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_config\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,419 | function | function new(string name = "uart_config");
super.new(name);
endfunction | function new(string name = "uart_config"); |
super.new(name);
endfunction | 0 |
140,306 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv | 90,320,290 | ex7-6_uart_config.sv | sv | 128 | 80 | [] | [] | [] | null | line:8: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:9: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: Unsupported: classes\nclass uart_config extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_config extends uvm_object;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_tx_active = UVM_ACTIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:19: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_rx_active = UVM_PASSIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: syntax error, unexpected \'{\', expecting IDENTIFIER\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_tx_en { tx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rx_en { rx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rts_en { rts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_cts_en { cts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_ua_chmode { ua_chmode == 2\'b00;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:65: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_config)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:66: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:67: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:68: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:69: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:70: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(char_length, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:71: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(nbstop, UVM_DEFAULT ) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:72: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_en, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:75: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_mode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:78: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_chmode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:86: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : char_len_val = 5;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:102: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : char_len_val = 6;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b10 : char_len_val = 7;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b11 : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:105: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:112: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : stop_bit_val = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:114: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: Hierarchical class references\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: scoped class reference\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:115: Unsupported: scoped class reference\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: syntax error, unexpected ::, expecting \';\'\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n : ... Perhaps \'type_id\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:6: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_config\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,419 | function | function void post_randomize();
ConvToIntChrl();
ConvToIntStpBt();
endfunction | function void post_randomize(); |
ConvToIntChrl();
ConvToIntStpBt();
endfunction | 0 |
140,307 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv | 90,320,290 | ex7-6_uart_config.sv | sv | 128 | 80 | [] | [] | [] | null | line:8: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:9: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: Unsupported: classes\nclass uart_config extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_config extends uvm_object;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_tx_active = UVM_ACTIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:19: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_rx_active = UVM_PASSIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: syntax error, unexpected \'{\', expecting IDENTIFIER\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_tx_en { tx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rx_en { rx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rts_en { rts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_cts_en { cts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_ua_chmode { ua_chmode == 2\'b00;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:65: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_config)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:66: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:67: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:68: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:69: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:70: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(char_length, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:71: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(nbstop, UVM_DEFAULT ) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:72: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_en, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:75: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_mode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:78: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_chmode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:86: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : char_len_val = 5;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:102: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : char_len_val = 6;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b10 : char_len_val = 7;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b11 : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:105: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:112: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : stop_bit_val = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:114: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: Hierarchical class references\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: scoped class reference\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:115: Unsupported: scoped class reference\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: syntax error, unexpected ::, expecting \';\'\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n : ... Perhaps \'type_id\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:6: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_config\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,419 | function | function void ConvToIntChrl();
case(char_length)
2'b00 : char_len_val = 5;
2'b01 : char_len_val = 6;
2'b10 : char_len_val = 7;
2'b11 : char_len_val = 8;
default : char_len_val = 8;
endcase
endfunction | function void ConvToIntChrl(); |
case(char_length)
2'b00 : char_len_val = 5;
2'b01 : char_len_val = 6;
2'b10 : char_len_val = 7;
2'b11 : char_len_val = 8;
default : char_len_val = 8;
endcase
endfunction | 0 |
140,308 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv | 90,320,290 | ex7-6_uart_config.sv | sv | 128 | 80 | [] | [] | [] | null | line:8: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:9: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:8: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: Unsupported: classes\nclass uart_config extends uvm_object;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:16: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_config extends uvm_object;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:18: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_tx_active = UVM_ACTIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:19: syntax error, unexpected \'=\', expecting \',\' or \';\'\n uvm_active_passive_enum is_rx_active = UVM_PASSIVE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:55: syntax error, unexpected \'{\', expecting IDENTIFIER\n constraint c_num_stop_bits { nbstop inside {[0:2]};}\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:56: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_parity_mode { parity_mode == {parity_stick, parity_even};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:57: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_tx_en { tx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:58: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rx_en { rx_en == 1;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:59: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_rts_en { rts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_cts_en { cts_en == 0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_ua_chmode { ua_chmode == 2\'b00;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:65: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_config)\n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:66: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_tx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:67: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_rx_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:68: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_gen, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:69: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(baud_rate_div, UVM_DEFAULT + UVM_DEC)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:70: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(char_length, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:71: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(nbstop, UVM_DEFAULT ) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:72: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_en, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:75: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity_mode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:78: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(ua_chmode, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:86: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:101: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : char_len_val = 5;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:102: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : char_len_val = 6;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:103: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b10 : char_len_val = 7;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:104: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b11 : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:105: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : char_len_val = 8;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:112: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b00 : stop_bit_val = 1;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:113: syntax error, unexpected \'=\', expecting IDENTIFIER\n 2\'b01 : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:114: syntax error, unexpected \'=\', expecting IDENTIFIER\n default : stop_bit_val = 2;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: Hierarchical class references\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: Unsupported: scoped class reference\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:115: Unsupported: scoped class reference\n endcase\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:123: syntax error, unexpected ::, expecting \';\'\n uart_cfg = uart_config::type_id::create("uart_cfg");\n ^~\n : ... Perhaps \'type_id\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-6_uart_config.sv:6: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_config\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,419 | function | function void ConvToIntStpBt();
case(nbstop)
2'b00 : stop_bit_val = 1;
2'b01 : stop_bit_val = 2;
default : stop_bit_val = 2;
endcase
endfunction | function void ConvToIntStpBt(); |
case(nbstop)
2'b00 : stop_bit_val = 1;
2'b01 : stop_bit_val = 2;
default : stop_bit_val = 2;
endcase
endfunction | 0 |
140,309 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv | 90,320,290 | ex7-7_uart_ctrl_base_test.sv | sv | 27 | 76 | [] | [] | [] | null | line:7: before: "class" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:7: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:11: Define or directive not defined: '`uvm_component_utils'\n `uvm_component_utils(uart_ctrl_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:13: Unsupported: new constructor\n function new(input string name, input uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:13: syntax error, unexpected IDENTIFIER, expecting ')'\n function new(input string name, input uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:17: syntax error, unexpected IDENTIFIER, expecting ')'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:22: syntax error, unexpected IDENTIFIER, expecting ')'\n virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 7 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,420 | function | function new(input string name, input uvm_component parent = null);
super.new(name, parent);
endfunction | function new(input string name, input uvm_component parent = null); |
super.new(name, parent);
endfunction | 0 |
140,310 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv | 90,320,290 | ex7-7_uart_ctrl_base_test.sv | sv | 27 | 76 | [] | [] | [] | null | line:7: before: "class" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:7: Unsupported: classes\nclass uart_ctrl_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:11: Define or directive not defined: '`uvm_component_utils'\n `uvm_component_utils(uart_ctrl_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:13: Unsupported: new constructor\n function new(input string name, input uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:13: syntax error, unexpected IDENTIFIER, expecting ')'\n function new(input string name, input uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:17: syntax error, unexpected IDENTIFIER, expecting ')'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-7_uart_ctrl_base_test.sv:22: syntax error, unexpected IDENTIFIER, expecting ')'\n virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 7 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,420 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uart_ctrl_tb0 = uart_ctrl_tb::type_id::create("uart_ctrl_tb0", this);
endfunction | 0 |
140,311 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv | 90,320,290 | ex7-8_uart_ctrl_test.sv | sv | 24 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:7: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:9: Define or directive not defined: '`uvm_component_utils'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:11: syntax error, unexpected IDENTIFIER, expecting ')'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:19: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:19: syntax error, unexpected IDENTIFIER, expecting ')'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: Exiting due to 6 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,421 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
uvm_config_wrapper::set(this, "uart_ctrl_tb0.apb0.master.sequencer.run_phase",
"default_sequence", apb_write_to_uart_seq::type_id::get());
uvm_config_wrapper::set(this, "uart_ctrl_tb0.uart0.Tx.sequencer.run_phase",
"default_sequence", uart_write_to_apb_seq::type_id::get());
endfunction | 0 |
140,312 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv | 90,320,290 | ex7-8_uart_ctrl_test.sv | sv | 24 | 81 | [] | [] | [] | null | line:7: before: "class" | null | 1: b"%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:7: Unsupported: classes\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_a2u_rand_test extends uart_ctrl_base_test;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:9: Define or directive not defined: '`uvm_component_utils'\n`uvm_component_utils(u2a_a2u_rand_test)\n^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:11: syntax error, unexpected IDENTIFIER, expecting ')'\nvirtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:19: Unsupported: new constructor\nfunction new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-8_uart_ctrl_test.sv:19: syntax error, unexpected IDENTIFIER, expecting ')'\nfunction new(string name, uvm_component parent);\n ^~~~~~\n%Error: Exiting due to 6 error(s)\n ... See the manual and https://verilator.org for more assistance.\n" | 308,421 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,313 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv | 90,320,290 | ex7-9_uart_frame.sv | sv | 101 | 88 | [] | [] | [] | null | line:10: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:11: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:10: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: Unsupported: classes\nclass uart_frame extends uvm_sequence_item; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_frame extends uvm_sequence_item; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:27: syntax error, unexpected rand\n rand int transmit_delay;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:31: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_error_bits { error_bits != 4\'b0000;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_start_bit { start_bit == 1\'b0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_stop_bits { stop_bits == 2\'b11;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:39: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_frame) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:40: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(start_bit, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:41: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(payload, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(stop_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:44: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(error_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:45: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE) \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:46: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:47: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[5:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:62: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[6:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:72: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = ~ParityMode[0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:75: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:77: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:83: syntax error, unexpected \'=\', expecting IDENTIFIER\n parity = ~calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n else parity = calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:93: Unsupported: new with arguments\n frame = new("frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: syntax error, unexpected \'(\'\n void\'(frame.randomize());\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:9: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_frame\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,422 | module | module test;
import uvm_pkg::*;
`include "uvm_macros.svh"
typedef enum bit {GOOD_PARITY, BAD_PARITY} parity_e;
class uart_frame extends uvm_sequence_item;
rand bit start_bit;
rand bit [7:0] payload;
rand bit [1:0] stop_bits;
rand bit [3:0] error_bits;
bit parity;
rand int transmit_delay;
rand parity_e parity_type;
constraint default_error_bits { error_bits != 4'b0000;}
constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}
constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}
constraint default_start_bit { start_bit == 1'b0;}
constraint default_stop_bits { stop_bits == 2'b11;}
`uvm_object_utils_begin(uart_frame)
`uvm_field_int(start_bit, UVM_DEFAULT)
`uvm_field_int(payload, UVM_DEFAULT)
`uvm_field_int(parity, UVM_DEFAULT)
`uvm_field_int(stop_bits, UVM_DEFAULT)
`uvm_field_int(error_bits, UVM_DEFAULT)
`uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE)
`uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)
`uvm_object_utils_end
function new(string name = "uart_frame");
super.new(name);
endfunction
function bit calc_parity(int unsigned num_of_data_bits=8,
bit[1:0] ParityMode=0);
bit temp_parity;
if (num_of_data_bits == 6)
temp_parity = ^payload[5:0];
else if (num_of_data_bits == 7)
temp_parity = ^payload[6:0];
else
temp_parity = ^payload;
case(ParityMode[0])
0: temp_parity = ~temp_parity;
1: temp_parity = temp_parity;
endcase
case(ParityMode[1])
0: temp_parity = temp_parity;
1: temp_parity = ~ParityMode[0];
endcase
if (parity_type == BAD_PARITY)
calc_parity = ~temp_parity;
else
calc_parity = temp_parity;
endfunction
function void post_randomize();
if (parity_type == BAD_PARITY)
parity = ~calc_parity();
else parity = calc_parity();
endfunction : post_randomize
endclass : uart_frame
uart_frame frame;
initial begin
frame = new("frame");
repeat (3) begin
void'(frame.randomize());
frame.print();
end
end
endmodule | module test; |
import uvm_pkg::*;
`include "uvm_macros.svh"
typedef enum bit {GOOD_PARITY, BAD_PARITY} parity_e;
class uart_frame extends uvm_sequence_item;
rand bit start_bit;
rand bit [7:0] payload;
rand bit [1:0] stop_bits;
rand bit [3:0] error_bits;
bit parity;
rand int transmit_delay;
rand parity_e parity_type;
constraint default_error_bits { error_bits != 4'b0000;}
constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}
constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}
constraint default_start_bit { start_bit == 1'b0;}
constraint default_stop_bits { stop_bits == 2'b11;}
`uvm_object_utils_begin(uart_frame)
`uvm_field_int(start_bit, UVM_DEFAULT)
`uvm_field_int(payload, UVM_DEFAULT)
`uvm_field_int(parity, UVM_DEFAULT)
`uvm_field_int(stop_bits, UVM_DEFAULT)
`uvm_field_int(error_bits, UVM_DEFAULT)
`uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE)
`uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)
`uvm_object_utils_end
function new(string name = "uart_frame");
super.new(name);
endfunction
function bit calc_parity(int unsigned num_of_data_bits=8,
bit[1:0] ParityMode=0);
bit temp_parity;
if (num_of_data_bits == 6)
temp_parity = ^payload[5:0];
else if (num_of_data_bits == 7)
temp_parity = ^payload[6:0];
else
temp_parity = ^payload;
case(ParityMode[0])
0: temp_parity = ~temp_parity;
1: temp_parity = temp_parity;
endcase
case(ParityMode[1])
0: temp_parity = temp_parity;
1: temp_parity = ~ParityMode[0];
endcase
if (parity_type == BAD_PARITY)
calc_parity = ~temp_parity;
else
calc_parity = temp_parity;
endfunction
function void post_randomize();
if (parity_type == BAD_PARITY)
parity = ~calc_parity();
else parity = calc_parity();
endfunction : post_randomize
endclass : uart_frame
uart_frame frame;
initial begin
frame = new("frame");
repeat (3) begin
void'(frame.randomize());
frame.print();
end
end
endmodule | 0 |
140,314 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv | 90,320,290 | ex7-9_uart_frame.sv | sv | 101 | 88 | [] | [] | [] | null | line:10: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:11: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:10: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: Unsupported: classes\nclass uart_frame extends uvm_sequence_item; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_frame extends uvm_sequence_item; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:27: syntax error, unexpected rand\n rand int transmit_delay;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:31: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_error_bits { error_bits != 4\'b0000;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_start_bit { start_bit == 1\'b0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_stop_bits { stop_bits == 2\'b11;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:39: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_frame) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:40: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(start_bit, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:41: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(payload, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(stop_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:44: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(error_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:45: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE) \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:46: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:47: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[5:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:62: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[6:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:72: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = ~ParityMode[0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:75: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:77: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:83: syntax error, unexpected \'=\', expecting IDENTIFIER\n parity = ~calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n else parity = calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:93: Unsupported: new with arguments\n frame = new("frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: syntax error, unexpected \'(\'\n void\'(frame.randomize());\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:9: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_frame\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,422 | function | function new(string name = "uart_frame");
super.new(name);
endfunction | function new(string name = "uart_frame"); |
super.new(name);
endfunction | 0 |
140,315 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv | 90,320,290 | ex7-9_uart_frame.sv | sv | 101 | 88 | [] | [] | [] | null | line:10: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:11: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:10: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: Unsupported: classes\nclass uart_frame extends uvm_sequence_item; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_frame extends uvm_sequence_item; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:27: syntax error, unexpected rand\n rand int transmit_delay;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:31: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_error_bits { error_bits != 4\'b0000;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_start_bit { start_bit == 1\'b0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_stop_bits { stop_bits == 2\'b11;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:39: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_frame) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:40: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(start_bit, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:41: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(payload, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(stop_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:44: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(error_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:45: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE) \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:46: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:47: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[5:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:62: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[6:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:72: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = ~ParityMode[0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:75: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:77: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:83: syntax error, unexpected \'=\', expecting IDENTIFIER\n parity = ~calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n else parity = calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:93: Unsupported: new with arguments\n frame = new("frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: syntax error, unexpected \'(\'\n void\'(frame.randomize());\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:9: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_frame\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,422 | function | function bit calc_parity(int unsigned num_of_data_bits=8,
bit[1:0] ParityMode=0);
bit temp_parity;
if (num_of_data_bits == 6)
temp_parity = ^payload[5:0];
else if (num_of_data_bits == 7)
temp_parity = ^payload[6:0];
else
temp_parity = ^payload;
case(ParityMode[0])
0: temp_parity = ~temp_parity;
1: temp_parity = temp_parity;
endcase
case(ParityMode[1])
0: temp_parity = temp_parity;
1: temp_parity = ~ParityMode[0];
endcase
if (parity_type == BAD_PARITY)
calc_parity = ~temp_parity;
else
calc_parity = temp_parity;
endfunction | function bit calc_parity(int unsigned num_of_data_bits=8,
bit[1:0] ParityMode=0); |
bit temp_parity;
if (num_of_data_bits == 6)
temp_parity = ^payload[5:0];
else if (num_of_data_bits == 7)
temp_parity = ^payload[6:0];
else
temp_parity = ^payload;
case(ParityMode[0])
0: temp_parity = ~temp_parity;
1: temp_parity = temp_parity;
endcase
case(ParityMode[1])
0: temp_parity = temp_parity;
1: temp_parity = ~ParityMode[0];
endcase
if (parity_type == BAD_PARITY)
calc_parity = ~temp_parity;
else
calc_parity = temp_parity;
endfunction | 0 |
140,316 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv | 90,320,290 | ex7-9_uart_frame.sv | sv | 101 | 88 | [] | [] | [] | null | line:10: before: ":" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:11: Cannot find include file: uvm_macros.svh\n`include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration,data/full_repos/permissive/90320290/uvm_macros.svh.sv\n uvm_macros.svh\n uvm_macros.svh.v\n uvm_macros.svh.sv\n obj_dir/uvm_macros.svh\n obj_dir/uvm_macros.svh.v\n obj_dir/uvm_macros.svh.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:10: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\nimport uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: Unsupported: classes\nclass uart_frame extends uvm_sequence_item; \n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_frame extends uvm_sequence_item; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:27: syntax error, unexpected rand\n rand int transmit_delay;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:31: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_error_bits { error_bits != 4\'b0000;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:32: Unsupported: SystemVerilog 2005 reserved word not implemented: \'dist\'\n constraint default_parity_type { parity_type dist {GOOD_PARITY:=90, BAD_PARITY:=10};}\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_txmit_delay {transmit_delay >= 0; transmit_delay < 20;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_start_bit { start_bit == 1\'b0;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:35: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint default_stop_bits { stop_bits == 2\'b11;}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:39: Define or directive not defined: \'`uvm_object_utils_begin\'\n `uvm_object_utils_begin(uart_frame) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:40: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(start_bit, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:41: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(payload, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:42: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(parity, UVM_DEFAULT) \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:43: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(stop_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:44: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(error_bits, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:45: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(parity_e,parity_type, UVM_DEFAULT + UVM_NOCOMPARE) \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:46: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(transmit_delay, UVM_DEFAULT + UVM_DEC + UVM_NOCOMPARE + UVM_NOCOPY)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:47: Define or directive not defined: \'`uvm_object_utils_end\'\n `uvm_object_utils_end\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:60: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[5:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:62: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload[6:0]; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:64: syntax error, unexpected \'=\', expecting IDENTIFIER\n temp_parity = ^payload; \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:67: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:68: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:71: syntax error, unexpected \'=\', expecting IDENTIFIER\n 0: temp_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:72: syntax error, unexpected \'=\', expecting IDENTIFIER\n 1: temp_parity = ~ParityMode[0];\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:75: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = ~temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:77: syntax error, unexpected \'=\', expecting IDENTIFIER\n calc_parity = temp_parity;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:83: syntax error, unexpected \'=\', expecting IDENTIFIER\n parity = ~calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:84: syntax error, unexpected \'=\', expecting IDENTIFIER\n else parity = calc_parity();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:93: Unsupported: new with arguments\n frame = new("frame");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: Unsupported: SystemVerilog 2005 reserved word not implemented: \'randomize\'\n void\'(frame.randomize());\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:95: syntax error, unexpected \'(\'\n void\'(frame.randomize());\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/ex7-9_uart_frame.sv:9: ../V3ParseSym.h:114: Symbols suggest ending CLASS \'uart_frame\' but parser thinks ending MODULE \'test\'\nmodule test;\n ^~~~\n' | 308,422 | function | function void post_randomize();
if (parity_type == BAD_PARITY)
parity = ~calc_parity();
else parity = calc_parity();
endfunction | function void post_randomize(); |
if (parity_type == BAD_PARITY)
parity = ~calc_parity();
else parity = calc_parity();
endfunction | 0 |
140,317 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv | 90,320,290 | demo_seq_lib.sv | sv | 91 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:36: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:36: Unsupported: classes\nclass demo_seq_lib extends uvm_sequence_library #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:36: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_seq_lib extends uvm_sequence_library #(apb_transfer);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:38: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(demo_seq_lib)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:39: Define or directive not defined: \'`uvm_sequence_library_utils\'\n `uvm_sequence_library_utils(demo_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:41: Unsupported: new constructor\n function new(string name="demo_seq_lib");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:47: syntax error, unexpected ::, expecting \')\'\n add_sequence(write_byte_seq::get_type());\n ^~\n : ... Perhaps \'write_byte_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:48: syntax error, unexpected ::, expecting \')\'\n add_sequence(read_byte_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:49: syntax error, unexpected ::, expecting \')\'\n add_sequence(read_after_write_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:50: syntax error, unexpected ::, expecting \')\'\n add_sequence(multiple_read_after_write_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:59: Unsupported: this\n this.print();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:60: Unsupported: super\n super.body();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:61: Unsupported: this\n this.print();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:64: syntax error, unexpected endclass\nendclass : demo_seq_lib\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:66: Unsupported: classes\nclass demo_seq_lib2 extends demo_seq_lib;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:66: Unsupported: extends\nclass demo_seq_lib2 extends demo_seq_lib;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:68: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:68: syntax error, unexpected \'(\'\n `uvm_object_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:69: Define or directive not defined: \'`uvm_sequence_library_utils\'\n `uvm_sequence_library_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,425 | function | function new(string name="demo_seq_lib");
super.new(name);
min_random_count = 1;
max_random_count = 5;
add_sequence(write_byte_seq::get_type());
add_sequence(read_byte_seq::get_type());
add_sequence(read_after_write_seq::get_type());
add_sequence(multiple_read_after_write_seq::get_type());
init_sequence_library();
endfunction | function new(string name="demo_seq_lib"); |
super.new(name);
min_random_count = 1;
max_random_count = 5;
add_sequence(write_byte_seq::get_type());
add_sequence(read_byte_seq::get_type());
add_sequence(read_after_write_seq::get_type());
add_sequence(multiple_read_after_write_seq::get_type());
init_sequence_library();
endfunction | 0 |
140,318 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv | 90,320,290 | demo_seq_lib.sv | sv | 91 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:36: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:36: Unsupported: classes\nclass demo_seq_lib extends uvm_sequence_library #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:36: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_seq_lib extends uvm_sequence_library #(apb_transfer);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:38: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(demo_seq_lib)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:39: Define or directive not defined: \'`uvm_sequence_library_utils\'\n `uvm_sequence_library_utils(demo_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:41: Unsupported: new constructor\n function new(string name="demo_seq_lib");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:42: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:47: syntax error, unexpected ::, expecting \')\'\n add_sequence(write_byte_seq::get_type());\n ^~\n : ... Perhaps \'write_byte_seq\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:48: syntax error, unexpected ::, expecting \')\'\n add_sequence(read_byte_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:49: syntax error, unexpected ::, expecting \')\'\n add_sequence(read_after_write_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:50: syntax error, unexpected ::, expecting \')\'\n add_sequence(multiple_read_after_write_seq::get_type());\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:59: Unsupported: this\n this.print();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:60: Unsupported: super\n super.body();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:61: Unsupported: this\n this.print();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:64: syntax error, unexpected endclass\nendclass : demo_seq_lib\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:66: Unsupported: classes\nclass demo_seq_lib2 extends demo_seq_lib;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:66: Unsupported: extends\nclass demo_seq_lib2 extends demo_seq_lib;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:68: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:68: syntax error, unexpected \'(\'\n `uvm_object_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_seq_lib.sv:69: Define or directive not defined: \'`uvm_sequence_library_utils\'\n `uvm_sequence_library_utils(demo_seq_lib2)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 308,425 | function | function new(string name="demo_seq_lib2");
super.new(name);
min_random_count = 3;
max_random_count = 8;
remove_sequence(multiple_read_after_write_seq::get_type());
endfunction | function new(string name="demo_seq_lib2"); |
super.new(name);
min_random_count = 3;
max_random_count = 8;
remove_sequence(multiple_read_after_write_seq::get_type());
endfunction | 0 |
140,319 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv | 90,320,290 | demo_tb.sv | sv | 69 | 90 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:15: Cannot find include file: ./examples/demo_config.sv\n`include "./examples/demo_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.sv\n ./examples/demo_config.sv\n ./examples/demo_config.sv.v\n ./examples/demo_config.sv.sv\n obj_dir/./examples/demo_config.sv\n obj_dir/./examples/demo_config.sv.v\n obj_dir/./examples/demo_config.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:16: Cannot find include file: ./sv/apb_master_seq_lib.sv\n`include "./sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:17: Cannot find include file: ./sv/apb_slave_seq_lib.sv\n`include "./sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:18: Cannot find include file: ./examples/demo_seq_lib.sv\n`include "./examples/demo_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: Unsupported: classes\nclass demo_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:27: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Hierarchical class references\n function void demo_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: scoped class reference\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: Hierarchical class references\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: scoped class reference\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Out of class block function declaration\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 19 error(s)\n' | 308,426 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,320 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv | 90,320,290 | demo_tb.sv | sv | 69 | 90 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:15: Cannot find include file: ./examples/demo_config.sv\n`include "./examples/demo_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.sv\n ./examples/demo_config.sv\n ./examples/demo_config.sv.v\n ./examples/demo_config.sv.sv\n obj_dir/./examples/demo_config.sv\n obj_dir/./examples/demo_config.sv.v\n obj_dir/./examples/demo_config.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:16: Cannot find include file: ./sv/apb_master_seq_lib.sv\n`include "./sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:17: Cannot find include file: ./sv/apb_slave_seq_lib.sv\n`include "./sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:18: Cannot find include file: ./examples/demo_seq_lib.sv\n`include "./examples/demo_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: Unsupported: classes\nclass demo_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:27: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Hierarchical class references\n function void demo_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: scoped class reference\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: Hierarchical class references\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: scoped class reference\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Out of class block function declaration\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 19 error(s)\n' | 308,426 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
endclass : demo_tb
function void demo_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
demo_cfg = demo_config::type_id::create("demo_cfg");
uvm_config_object::set(this, "apb0*", "cfg", demo_cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", demo_cfg.slave_configs[0]);
uvm_config_object::set(this, "apb0.slave[1]*", "cfg", demo_cfg.slave_configs[1]);
apb0 = apb_env::type_id::create("apb0", this);
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
endclass : demo_tb
function void demo_tb::build_phase(uvm_phase phase);
super.build_phase(phase);
demo_cfg = demo_config::type_id::create("demo_cfg");
uvm_config_object::set(this, "apb0*", "cfg", demo_cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", demo_cfg.slave_configs[0]);
uvm_config_object::set(this, "apb0.slave[1]*", "cfg", demo_cfg.slave_configs[1]);
apb0 = apb_env::type_id::create("apb0", this);
endfunction | 0 |
140,321 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv | 90,320,290 | demo_tb.sv | sv | 69 | 90 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:15: Cannot find include file: ./examples/demo_config.sv\n`include "./examples/demo_config.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_config.sv.sv\n ./examples/demo_config.sv\n ./examples/demo_config.sv.v\n ./examples/demo_config.sv.sv\n obj_dir/./examples/demo_config.sv\n obj_dir/./examples/demo_config.sv.v\n obj_dir/./examples/demo_config.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:16: Cannot find include file: ./sv/apb_master_seq_lib.sv\n`include "./sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:17: Cannot find include file: ./sv/apb_slave_seq_lib.sv\n`include "./sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:18: Cannot find include file: ./examples/demo_seq_lib.sv\n`include "./examples/demo_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: Unsupported: classes\nclass demo_tb extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:24: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_tb extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:27: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_tb)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:39: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:44: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Hierarchical class references\n function void demo_tb::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: scoped class reference\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:45: Unsupported: Out of class block function declaration\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: Hierarchical class references\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: Unsupported: scoped class reference\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:50: Unsupported: Out of class block function declaration\n function void demo_tb::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/demo_tb.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void demo_tb::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to 19 error(s)\n' | 308,426 | function | function void demo_tb::connect_phase(uvm_phase phase);
endfunction | function void demo_tb::connect_phase(uvm_phase phase); |
endfunction | 0 |
140,322 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/dut_dummy.v | 90,320,290 | dut_dummy.v | v | 6 | 68 | [] | [] | [] | null | line:3: before: "apb_if" | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/dut_dummy.v:3: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'dut_dummy\'\nmodule dut_dummy( input apb_clock, input apb_reset, apb_if apb_if);\n ^~~~~~~~~\n : ... Top module \'apb_if\'\nmodule dut_dummy( input apb_clock, input apb_reset, apb_if apb_if);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/dut_dummy.v:3: Unsupported: Interfaced port on top level module\nmodule dut_dummy( input apb_clock, input apb_reset, apb_if apb_if);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/dut_dummy.v:3: Cannot find file containing interface: \'apb_if\'\nmodule dut_dummy( input apb_clock, input apb_reset, apb_if apb_if);\n ^~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 308,428 | module | module dut_dummy( input apb_clock, input apb_reset, apb_if apb_if);
endmodule | module dut_dummy( input apb_clock, input apb_reset, apb_if apb_if); |
endmodule | 0 |
140,323 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv | 90,320,290 | simple_top.sv | sv | 97 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:12: Cannot find include file: sv/apb_if.sv\n`include "sv/apb_if.sv" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.sv\n sv/apb_if.sv\n sv/apb_if.sv.v\n sv/apb_if.sv.sv\n obj_dir/sv/apb_if.sv\n obj_dir/sv/apb_if.sv.v\n obj_dir/sv/apb_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:13: Cannot find include file: sv/apb_pkg.sv\n`include "sv/apb_pkg.sv" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:18: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:24: Cannot find include file: sv/apb_master_seq_lib.sv\n `include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:25: Cannot find include file: sv/apb_slave_seq_lib.sv\n `include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:17: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: Unsupported: classes\n class simple_test extends uvm_test;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n class simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:49: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_slave("slave[0]", 32\'h0000_0000, 32\'hFFFF_FFFF, 0, UVM_ACTIVE);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:50: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:56: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:60: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:72: syntax error, unexpected \'.\', expecting IDENTIFIER\n phase.phase_done.set_drain_time(this, 200);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:83: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.apb0*", "vif", apb_if_0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:91: Unsupported: Ignoring delay on this delayed statement.\n #51 reset = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:94: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock = ~clock;\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:14: ../V3ParseSym.h:114: Symbols suggest ending FUNC \'new\' but parser thinks ending MODULE \'simple_top\'\nmodule simple_top;\n ^~~~~~~~~~\n' | 308,431 | module | module simple_top;
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
`include "sv/apb_master_seq_lib.sv"
`include "sv/apb_slave_seq_lib.sv"
class simple_test extends uvm_test;
`uvm_component_utils(simple_test)
apb_env apb0;
apb_config cfg;
function new(string name = "simple_test", uvm_component parent);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
apb0 = apb_env::type_id::create("apb0", this);
endfunction : build_phase
task run_phase(uvm_phase phase);
this.print();
phase.phase_done.set_drain_time(this, 200);
endtask : run_phase
endclass : simple_test
reg clock;
reg reset;
apb_if apb_if_0(clock, reset);
initial begin
uvm_config_db#(virtual apb_if)::set(null, "*.apb0*", "vif", apb_if_0);
run_test();
end
initial begin
reset <= 1'b0;
clock <= 1'b0;
#51 reset = 1'b1;
end
always #5 clock = ~clock;
endmodule | module simple_top; |
import uvm_pkg::*;
`include "uvm_macros.svh"
import apb_pkg::*;
`include "sv/apb_master_seq_lib.sv"
`include "sv/apb_slave_seq_lib.sv"
class simple_test extends uvm_test;
`uvm_component_utils(simple_test)
apb_env apb0;
apb_config cfg;
function new(string name = "simple_test", uvm_component parent);
super.new(name,parent);
endfunction : new
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
apb0 = apb_env::type_id::create("apb0", this);
endfunction : build_phase
task run_phase(uvm_phase phase);
this.print();
phase.phase_done.set_drain_time(this, 200);
endtask : run_phase
endclass : simple_test
reg clock;
reg reset;
apb_if apb_if_0(clock, reset);
initial begin
uvm_config_db#(virtual apb_if)::set(null, "*.apb0*", "vif", apb_if_0);
run_test();
end
initial begin
reset <= 1'b0;
clock <= 1'b0;
#51 reset = 1'b1;
end
always #5 clock = ~clock;
endmodule | 0 |
140,324 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv | 90,320,290 | simple_top.sv | sv | 97 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:12: Cannot find include file: sv/apb_if.sv\n`include "sv/apb_if.sv" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.sv\n sv/apb_if.sv\n sv/apb_if.sv.v\n sv/apb_if.sv.sv\n obj_dir/sv/apb_if.sv\n obj_dir/sv/apb_if.sv.v\n obj_dir/sv/apb_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:13: Cannot find include file: sv/apb_pkg.sv\n`include "sv/apb_pkg.sv" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:18: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:24: Cannot find include file: sv/apb_master_seq_lib.sv\n `include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:25: Cannot find include file: sv/apb_slave_seq_lib.sv\n `include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:17: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: Unsupported: classes\n class simple_test extends uvm_test;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n class simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:49: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_slave("slave[0]", 32\'h0000_0000, 32\'hFFFF_FFFF, 0, UVM_ACTIVE);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:50: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:56: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:60: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:72: syntax error, unexpected \'.\', expecting IDENTIFIER\n phase.phase_done.set_drain_time(this, 200);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:83: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.apb0*", "vif", apb_if_0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:91: Unsupported: Ignoring delay on this delayed statement.\n #51 reset = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:94: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock = ~clock;\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:14: ../V3ParseSym.h:114: Symbols suggest ending FUNC \'new\' but parser thinks ending MODULE \'simple_top\'\nmodule simple_top;\n ^~~~~~~~~~\n' | 308,431 | function | function new(string name = "simple_test", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "simple_test", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,325 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv | 90,320,290 | simple_top.sv | sv | 97 | 83 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:12: Cannot find include file: sv/apb_if.sv\n`include "sv/apb_if.sv" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/sv/apb_if.sv.sv\n sv/apb_if.sv\n sv/apb_if.sv.v\n sv/apb_if.sv.sv\n obj_dir/sv/apb_if.sv\n obj_dir/sv/apb_if.sv.v\n obj_dir/sv/apb_if.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:13: Cannot find include file: sv/apb_pkg.sv\n`include "sv/apb_pkg.sv" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:18: Cannot find include file: uvm_macros.svh\n `include "uvm_macros.svh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:24: Cannot find include file: sv/apb_master_seq_lib.sv\n `include "sv/apb_master_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:25: Cannot find include file: sv/apb_slave_seq_lib.sv\n `include "sv/apb_slave_seq_lib.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:17: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING\n import uvm_pkg::*;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: Unsupported: classes\n class simple_test extends uvm_test;\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:28: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\n class simple_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:30: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(simple_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: Unsupported: new constructor\n function new(string name = "simple_test", uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:38: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name = "simple_test", uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:49: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_slave("slave[0]", 32\'h0000_0000, 32\'hFFFF_FFFF, 0, UVM_ACTIVE);\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:50: syntax error, unexpected \'(\', expecting IDENTIFIER\n cfg.add_master("master", UVM_ACTIVE);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:56: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:60: syntax error, unexpected ::, expecting IDENTIFIER\n uvm_config_db#(uvm_object_wrapper)::set(this,\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:72: syntax error, unexpected \'.\', expecting IDENTIFIER\n phase.phase_done.set_drain_time(this, 200);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:83: syntax error, unexpected \'#\'\n uvm_config_db#(virtual apb_if)::set(null, "*.apb0*", "vif", apb_if_0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:91: Unsupported: Ignoring delay on this delayed statement.\n #51 reset = 1\'b1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:94: Unsupported: Ignoring delay on this delayed statement.\n always #5 clock = ~clock;\n ^\n%Error: Internal Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/simple_top.sv:14: ../V3ParseSym.h:114: Symbols suggest ending FUNC \'new\' but parser thinks ending MODULE \'simple_top\'\nmodule simple_top;\n ^~~~~~~~~~\n' | 308,431 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
apb0 = apb_env::type_id::create("apb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
cfg = apb_config::type_id::create("cfg");
cfg.add_slave("slave[0]", 32'h0000_0000, 32'hFFFF_FFFF, 0, UVM_ACTIVE);
cfg.add_master("master", UVM_ACTIVE);
uvm_config_object::set(this, "apb0*", "cfg", cfg);
uvm_config_object::set(this, "apb0.slave[0]*", "cfg", cfg.slave_configs[0]);
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.master.sequencer.run_phase",
"default_sequence",
multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"apb0.slave[0].sequencer.run_phase",
"default_sequence",
mem_response_seq::type_id::get());
apb0 = apb_env::type_id::create("apb0", this);
endfunction | 0 |
140,326 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "demo_base_test",
uvm_component parent);
super.new(name,parent);
printer = new();
endfunction | function new(string name = "demo_base_test",
uvm_component parent); |
super.new(name,parent);
printer = new();
endfunction | 0 |
140,327 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
set_config_int("*", "recording_detail", UVM_FULL);
demo_tb0 = demo_tb::type_id::create("demo_tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
set_config_int("*", "recording_detail", UVM_FULL);
demo_tb0 = demo_tb::type_id::create("demo_tb0", this);
endfunction | 0 |
140,328 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void connect_phase(uvm_phase phase);
endfunction | function void connect_phase(uvm_phase phase); |
endfunction | 0 |
140,329 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "test_read_after_write", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "test_read_after_write", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,330 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
uvm_config_db #(uvm_object_wrapper)::set(this,
"demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | function void build_phase(uvm_phase phase); |
uvm_config_db #(uvm_object_wrapper)::set(this,
"demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,
"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | 0 |
140,331 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "test_seq_lib", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "test_seq_lib", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,332 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
uvm_sequence_library_cfg seqlib_cfg;
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", demo_seq_lib2::type_id::get());
seqlib_cfg = new("seqlib_cfg", UVM_SEQ_LIB_RAND, 10, 10);
uvm_config_db #(uvm_sequence_library_cfg)::set(this,
"demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence.config", seqlib_cfg);
uvm_config_db#(uvm_object_wrapper)::set(this,"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | function void build_phase(uvm_phase phase); |
uvm_sequence_library_cfg seqlib_cfg;
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", demo_seq_lib2::type_id::get());
seqlib_cfg = new("seqlib_cfg", UVM_SEQ_LIB_RAND, 10, 10);
uvm_config_db #(uvm_sequence_library_cfg)::set(this,
"demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence.config", seqlib_cfg);
uvm_config_db#(uvm_object_wrapper)::set(this,"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | 0 |
140,333 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "test_multiple_read_after_write", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "test_multiple_read_after_write", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,334 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | function void build_phase(uvm_phase phase); |
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase",
"default_sequence", multiple_read_after_write_seq::type_id::get());
uvm_config_db#(uvm_object_wrapper)::set(this,"demo_tb0.apb0.slave[0].sequencer.run_phase",
"default_sequence", mem_response_seq::type_id::get());
super.build_phase(phase);
endfunction | 0 |
140,335 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "test_048_write_read", uvm_component parent);
super.new(name,parent);
endfunction | function new(string name = "test_048_write_read", uvm_component parent); |
super.new(name,parent);
endfunction | 0 |
140,336 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
begin
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase","default_sequence", multiple_read_after_write_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[0].sequencer.run_phase","default_sequence", mem_response_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[1].sequencer.run_phase","default_sequence", mem_response_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[2].sequencer.run_phase","default_sequence", simple_response_seq::type_id::get());
super.build_phase(phase);
end
endfunction | function void build_phase(uvm_phase phase); |
begin
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.master.sequencer.run_phase","default_sequence", multiple_read_after_write_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[0].sequencer.run_phase","default_sequence", mem_response_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[1].sequencer.run_phase","default_sequence", mem_response_seq::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(this, "demo_tb0.apb0.slave[2].sequencer.run_phase","default_sequence", simple_response_seq::type_id::get());
super.build_phase(phase);
end
endfunction | 0 |
140,337 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function new(string name = "config_uart_ctrl_test",
uvm_component parent);
super.new(name,parent);
printer = new();
endfunction | function new(string name = "config_uart_ctrl_test",
uvm_component parent); |
super.new(name,parent);
printer = new();
endfunction | 0 |
140,338 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv | 90,320,290 | test_lib.sv | sv | 238 | 162 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:11: Cannot find include file: ./examples/demo_tb.sv\n`include "./examples/demo_tb.sv" \n ^~~~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.v\n data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples,data/full_repos/permissive/90320290/./examples/demo_tb.sv.sv\n ./examples/demo_tb.sv\n ./examples/demo_tb.sv.v\n ./examples/demo_tb.sv.sv\n obj_dir/./examples/demo_tb.sv\n obj_dir/./examples/demo_tb.sv.v\n obj_dir/./examples/demo_tb.sv.sv\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: Unsupported: classes\nclass demo_base_test extends uvm_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:18: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass demo_base_test extends uvm_test;\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:20: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(demo_base_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:25: Unsupported: new constructor\n function new(string name = "demo_base_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:26: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:31: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:43: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: classes\nclass test_read_after_write extends demo_base_test;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:64: Unsupported: extends\nclass test_read_after_write extends demo_base_test;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:66: syntax error, unexpected \'(\'\n `uvm_component_utils(test_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:91: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_seq_lib)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:132: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_multiple_read_after_write)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:156: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(test_048_write_read)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:181: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(config_uart_ctrl_test)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:186: Unsupported: new constructor\n function new(string name = "config_uart_ctrl_test", \n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/examples/test_lib.sv:187: syntax error, unexpected IDENTIFIER, expecting \')\'\n uvm_component parent);\n ^~~~~~\n%Error: Cannot continue\n' | 308,432 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
set_config_int("*", "recording_detail", UVM_FULL);
demo_tb0 = demo_tb::type_id::create("demo_tb0", this);
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
set_config_int("*", "recording_detail", UVM_FULL);
demo_tb0 = demo_tb::type_id::create("demo_tb0", this);
endfunction | 0 |
140,339 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv | 90,320,290 | apb_env.sv | sv | 159 | 87 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: Unsupported: classes\nclass apb_env extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_env extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:34: Unsupported: virtual interface\n protected virtual interface apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:37: syntax error, unexpected IDENTIFIER\n apb_config cfg; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:45: syntax error, unexpected IDENTIFIER\n apb_monitor bus_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:51: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:52: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:53: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:54: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:64: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:65: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:67: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:70: syntax error, unexpected endclass\nendclass : apb_env\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:74: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:77: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:78: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:79: Unsupported or unknown PLI call: $cast\n $cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:87: syntax error, unexpected ::\n uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:90: syntax error, unexpected ::, expecting \';\'\n bus_monitor = apb_monitor::type_id::create("bus_monitor",this);\n ^~\n : ... Perhaps \'apb_monitor\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:91: syntax error, unexpected ::, expecting \';\'\n bus_collector = apb_collector::type_id::create("bus_collector",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:92: syntax error, unexpected ::, expecting \';\'\n master = apb_master_agent::type_id::create(cfg.master_config.name,this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:93: Unsupported: Dynamic array new\n slaves = new[cfg.slave_configs.size()];\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:95: syntax error, unexpected ::, expecting \';\'\n slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Hierarchical class references\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: scoped class reference\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:68: Unsupported: Out of class block function declaration\n extern virtual task update_vif_enables();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:104: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:105: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Hierarchical class references\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: scoped class reference\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Out of class block function declaration\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Hierarchical class references\nfunction void apb_env::update_config(apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: scoped class reference\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Out of class block function declaration\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Hierarchical class references\ntask apb_env::update_vif_enables();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: scoped class reference\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Out of class block function declaration\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:145: syntax error, unexpected \'@\'\n @(checks_enable || coverage_enable);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: Hierarchical class references\ntask apb_env::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: scoped class reference\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Out of class block function declaration\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,436 | function | function new(string name, uvm_component parent);
super.new(name, parent);
endfunction | function new(string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,340 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv | 90,320,290 | apb_env.sv | sv | 159 | 87 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: Unsupported: classes\nclass apb_env extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_env extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:34: Unsupported: virtual interface\n protected virtual interface apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:37: syntax error, unexpected IDENTIFIER\n apb_config cfg; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:45: syntax error, unexpected IDENTIFIER\n apb_monitor bus_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:51: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:52: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:53: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:54: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:64: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:65: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:67: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:70: syntax error, unexpected endclass\nendclass : apb_env\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:74: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:77: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:78: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:79: Unsupported or unknown PLI call: $cast\n $cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:87: syntax error, unexpected ::\n uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:90: syntax error, unexpected ::, expecting \';\'\n bus_monitor = apb_monitor::type_id::create("bus_monitor",this);\n ^~\n : ... Perhaps \'apb_monitor\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:91: syntax error, unexpected ::, expecting \';\'\n bus_collector = apb_collector::type_id::create("bus_collector",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:92: syntax error, unexpected ::, expecting \';\'\n master = apb_master_agent::type_id::create(cfg.master_config.name,this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:93: Unsupported: Dynamic array new\n slaves = new[cfg.slave_configs.size()];\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:95: syntax error, unexpected ::, expecting \';\'\n slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Hierarchical class references\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: scoped class reference\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:68: Unsupported: Out of class block function declaration\n extern virtual task update_vif_enables();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:104: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:105: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Hierarchical class references\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: scoped class reference\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Out of class block function declaration\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Hierarchical class references\nfunction void apb_env::update_config(apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: scoped class reference\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Out of class block function declaration\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Hierarchical class references\ntask apb_env::update_vif_enables();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: scoped class reference\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Out of class block function declaration\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:145: syntax error, unexpected \'@\'\n @(checks_enable || coverage_enable);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: Hierarchical class references\ntask apb_env::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: scoped class reference\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Out of class block function declaration\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,436 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual function void start_of_simulation_phase(uvm_phase phase);
extern virtual function void update_config(apb_config cfg);
extern virtual task run_phase(uvm_phase phase);
extern virtual task update_vif_enables();
endclass : apb_env
function void apb_env::build_phase(uvm_phase phase);
super.build_phase(phase);
if(cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)
$cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));
end
uvm_config_object::set(this, "*", "cfg", cfg);
foreach(cfg.slave_configs[i]) begin
string sname;
sname = $sformatf("slave[%0d]*", i);
uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);
end
bus_monitor = apb_monitor::type_id::create("bus_monitor",this);
bus_collector = apb_collector::type_id::create("bus_collector",this);
master = apb_master_agent::type_id::create(cfg.master_config.name,this);
slaves = new[cfg.slave_configs.size()];
for(int i = 0; i < cfg.slave_configs.size(); i++) begin
slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);
end
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual function void start_of_simulation_phase(uvm_phase phase);
extern virtual function void update_config(apb_config cfg);
extern virtual task run_phase(uvm_phase phase);
extern virtual task update_vif_enables();
endclass : apb_env
function void apb_env::build_phase(uvm_phase phase);
super.build_phase(phase);
if(cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin
`uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)
$cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));
end
uvm_config_object::set(this, "*", "cfg", cfg);
foreach(cfg.slave_configs[i]) begin
string sname;
sname = $sformatf("slave[%0d]*", i);
uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);
end
bus_monitor = apb_monitor::type_id::create("bus_monitor",this);
bus_collector = apb_collector::type_id::create("bus_collector",this);
master = apb_master_agent::type_id::create(cfg.master_config.name,this);
slaves = new[cfg.slave_configs.size()];
for(int i = 0; i < cfg.slave_configs.size(); i++) begin
slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);
end
endfunction | 0 |
140,341 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv | 90,320,290 | apb_env.sv | sv | 159 | 87 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: Unsupported: classes\nclass apb_env extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_env extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:34: Unsupported: virtual interface\n protected virtual interface apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:37: syntax error, unexpected IDENTIFIER\n apb_config cfg; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:45: syntax error, unexpected IDENTIFIER\n apb_monitor bus_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:51: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:52: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:53: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:54: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:64: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:65: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:67: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:70: syntax error, unexpected endclass\nendclass : apb_env\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:74: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:77: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:78: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:79: Unsupported or unknown PLI call: $cast\n $cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:87: syntax error, unexpected ::\n uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:90: syntax error, unexpected ::, expecting \';\'\n bus_monitor = apb_monitor::type_id::create("bus_monitor",this);\n ^~\n : ... Perhaps \'apb_monitor\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:91: syntax error, unexpected ::, expecting \';\'\n bus_collector = apb_collector::type_id::create("bus_collector",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:92: syntax error, unexpected ::, expecting \';\'\n master = apb_master_agent::type_id::create(cfg.master_config.name,this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:93: Unsupported: Dynamic array new\n slaves = new[cfg.slave_configs.size()];\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:95: syntax error, unexpected ::, expecting \';\'\n slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Hierarchical class references\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: scoped class reference\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:68: Unsupported: Out of class block function declaration\n extern virtual task update_vif_enables();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:104: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:105: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Hierarchical class references\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: scoped class reference\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Out of class block function declaration\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Hierarchical class references\nfunction void apb_env::update_config(apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: scoped class reference\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Out of class block function declaration\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Hierarchical class references\ntask apb_env::update_vif_enables();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: scoped class reference\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Out of class block function declaration\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:145: syntax error, unexpected \'@\'\n @(checks_enable || coverage_enable);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: Hierarchical class references\ntask apb_env::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: scoped class reference\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Out of class block function declaration\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,436 | function | function void apb_env::connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
bus_collector.item_collected_port.connect(bus_monitor.coll_mon_port);
bus_monitor.addr_trans_port.connect(bus_collector.addr_trans_export);
master.monitor.set_report_verbosity_level(UVM_NONE);
master.collector.set_report_verbosity_level(UVM_NONE);
foreach(slaves[i]) begin
slaves[i].monitor.set_report_verbosity_level(UVM_NONE);
slaves[i].collector.set_report_verbosity_level(UVM_NONE);
if (slaves[i].is_active == UVM_ACTIVE)
slaves[i].sequencer.addr_trans_port.connect(bus_monitor.addr_trans_export);
end
endfunction | function void apb_env::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})
bus_collector.item_collected_port.connect(bus_monitor.coll_mon_port);
bus_monitor.addr_trans_port.connect(bus_collector.addr_trans_export);
master.monitor.set_report_verbosity_level(UVM_NONE);
master.collector.set_report_verbosity_level(UVM_NONE);
foreach(slaves[i]) begin
slaves[i].monitor.set_report_verbosity_level(UVM_NONE);
slaves[i].collector.set_report_verbosity_level(UVM_NONE);
if (slaves[i].is_active == UVM_ACTIVE)
slaves[i].sequencer.addr_trans_port.connect(bus_monitor.addr_trans_export);
end
endfunction | 0 |
140,342 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv | 90,320,290 | apb_env.sv | sv | 159 | 87 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: Unsupported: classes\nclass apb_env extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_env extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:34: Unsupported: virtual interface\n protected virtual interface apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:37: syntax error, unexpected IDENTIFIER\n apb_config cfg; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:45: syntax error, unexpected IDENTIFIER\n apb_monitor bus_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:51: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:52: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:53: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:54: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:64: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:65: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:67: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:70: syntax error, unexpected endclass\nendclass : apb_env\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:74: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:77: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:78: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:79: Unsupported or unknown PLI call: $cast\n $cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:87: syntax error, unexpected ::\n uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:90: syntax error, unexpected ::, expecting \';\'\n bus_monitor = apb_monitor::type_id::create("bus_monitor",this);\n ^~\n : ... Perhaps \'apb_monitor\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:91: syntax error, unexpected ::, expecting \';\'\n bus_collector = apb_collector::type_id::create("bus_collector",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:92: syntax error, unexpected ::, expecting \';\'\n master = apb_master_agent::type_id::create(cfg.master_config.name,this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:93: Unsupported: Dynamic array new\n slaves = new[cfg.slave_configs.size()];\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:95: syntax error, unexpected ::, expecting \';\'\n slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Hierarchical class references\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: scoped class reference\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:68: Unsupported: Out of class block function declaration\n extern virtual task update_vif_enables();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:104: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:105: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Hierarchical class references\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: scoped class reference\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Out of class block function declaration\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Hierarchical class references\nfunction void apb_env::update_config(apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: scoped class reference\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Out of class block function declaration\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Hierarchical class references\ntask apb_env::update_vif_enables();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: scoped class reference\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Out of class block function declaration\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:145: syntax error, unexpected \'@\'\n @(checks_enable || coverage_enable);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: Hierarchical class references\ntask apb_env::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: scoped class reference\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Out of class block function declaration\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,436 | function | function void apb_env::start_of_simulation_phase(uvm_phase phase);
set_report_id_action_hier("CFGOVR", UVM_DISPLAY);
set_report_id_action_hier("CFGSET", UVM_DISPLAY);
check_config_usage();
endfunction | function void apb_env::start_of_simulation_phase(uvm_phase phase); |
set_report_id_action_hier("CFGOVR", UVM_DISPLAY);
set_report_id_action_hier("CFGSET", UVM_DISPLAY);
check_config_usage();
endfunction | 0 |
140,343 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv | 90,320,290 | apb_env.sv | sv | 159 | 87 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: Unsupported: classes\nclass apb_env extends uvm_env;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_env extends uvm_env;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:34: Unsupported: virtual interface\n protected virtual interface apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:37: syntax error, unexpected IDENTIFIER\n apb_config cfg; \n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:45: syntax error, unexpected IDENTIFIER\n apb_monitor bus_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:51: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_env)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:52: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:53: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(checks_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:54: Define or directive not defined: \'`uvm_field_int\'\n `uvm_field_int(coverage_enable, UVM_DEFAULT)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:55: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: Unsupported: new constructor\n function new(string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new(string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:63: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:64: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:65: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:66: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:67: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual task run_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:70: syntax error, unexpected endclass\nendclass : apb_env\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:74: Unsupported: super\n super.build_phase(phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:77: syntax error, unexpected \'#\'\n if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg)) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:78: Define or directive not defined: \'`uvm_info\'\n `uvm_info("NOCONFIG", "Using default_apb_config", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:79: Unsupported or unknown PLI call: $cast\n $cast(cfg, factory.create_object_by_name("default_apb_config","cfg"));\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:87: syntax error, unexpected ::\n uvm_config_object::set(this, sname, "cfg", cfg.slave_configs[i]);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:90: syntax error, unexpected ::, expecting \';\'\n bus_monitor = apb_monitor::type_id::create("bus_monitor",this);\n ^~\n : ... Perhaps \'apb_monitor\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:91: syntax error, unexpected ::, expecting \';\'\n bus_collector = apb_collector::type_id::create("bus_collector",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:92: syntax error, unexpected ::, expecting \';\'\n master = apb_master_agent::type_id::create(cfg.master_config.name,this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:93: Unsupported: Dynamic array new\n slaves = new[cfg.slave_configs.size()];\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:95: syntax error, unexpected ::, expecting \';\'\n slaves[i] = apb_slave_agent::type_id::create($sformatf("slave[%0d]", i), this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Hierarchical class references\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: scoped class reference\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:68: Unsupported: Out of class block function declaration\n extern virtual task update_vif_enables();\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:104: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:105: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Hierarchical class references\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: scoped class reference\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:101: Unsupported: Out of class block function declaration\nfunction void apb_env::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Hierarchical class references\nfunction void apb_env::update_config(apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: scoped class reference\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:125: Unsupported: Out of class block function declaration\nfunction void apb_env::start_of_simulation_phase(uvm_phase phase);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_env::update_config(apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Hierarchical class references\ntask apb_env::update_vif_enables();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: scoped class reference\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:132: Unsupported: Out of class block function declaration\nfunction void apb_env::update_config(apb_config cfg);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:145: syntax error, unexpected \'@\'\n @(checks_enable || coverage_enable);\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: Hierarchical class references\ntask apb_env::run_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: Unsupported: scoped class reference\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:141: Unsupported: Out of class block function declaration\ntask apb_env::update_vif_enables();\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_env.sv:152: syntax error, unexpected IDENTIFIER, expecting \')\'\ntask apb_env::run_phase(uvm_phase phase);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,436 | function | function void apb_env::update_config(apb_config cfg);
bus_monitor.cfg = cfg;
bus_collector.cfg = cfg;
master.update_config(cfg);
foreach(slaves[i])
slaves[i].update_config(cfg.slave_configs[i]);
endfunction | function void apb_env::update_config(apb_config cfg); |
bus_monitor.cfg = cfg;
bus_collector.cfg = cfg;
master.update_config(cfg);
foreach(slaves[i])
slaves[i].update_config(cfg.slave_configs[i]);
endfunction | 0 |
140,344 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv | 90,320,290 | apb_master_agent.sv | sv | 96 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:26: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: Unsupported: classes\nclass apb_master_agent extends uvm_agent;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_agent extends uvm_agent;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:40: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_agent)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:41: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:42: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:43: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(input apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Hierarchical class references\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: scoped class reference\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: Unsupported: Out of class block function declaration\n extern virtual function void update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:63: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Hierarchical class references\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: scoped class reference\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: Hierarchical class references\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: scoped class reference\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,438 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,345 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv | 90,320,290 | apb_master_agent.sv | sv | 96 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:26: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: Unsupported: classes\nclass apb_master_agent extends uvm_agent;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_agent extends uvm_agent;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:40: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_agent)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:41: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:42: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:43: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(input apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Hierarchical class references\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: scoped class reference\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: Unsupported: Out of class block function declaration\n extern virtual function void update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:63: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Hierarchical class references\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: scoped class reference\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: Hierarchical class references\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: scoped class reference\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,438 | function | function void build_phase(uvm_phase phase);
extern virtual function void connect_phase(uvm_phase phase);
extern virtual function void update_config(input apb_config cfg);
endclass : apb_master_agent
function void apb_master_agent::build_phase(uvm_phase phase);
uvm_object config_obj;
super.build_phase(phase);
if (cfg == null) begin
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_warning("NOCONFIG",
"Config not set for master agent, using default is_active field")
end
else is_active = cfg.master_config.is_active;
monitor = apb_monitor::type_id::create("monitor",this);
collector = apb_collector::type_id::create("collector",this);
if(is_active == UVM_ACTIVE) begin
sequencer = apb_master_sequencer::type_id::create("sequencer",this);
driver = apb_master_driver::type_id::create("driver",this);
end
endfunction | function void build_phase(uvm_phase phase); |
extern virtual function void connect_phase(uvm_phase phase);
extern virtual function void update_config(input apb_config cfg);
endclass : apb_master_agent
function void apb_master_agent::build_phase(uvm_phase phase);
uvm_object config_obj;
super.build_phase(phase);
if (cfg == null) begin
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_warning("NOCONFIG",
"Config not set for master agent, using default is_active field")
end
else is_active = cfg.master_config.is_active;
monitor = apb_monitor::type_id::create("monitor",this);
collector = apb_collector::type_id::create("collector",this);
if(is_active == UVM_ACTIVE) begin
sequencer = apb_master_sequencer::type_id::create("sequencer",this);
driver = apb_master_driver::type_id::create("driver",this);
end
endfunction | 0 |
140,346 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv | 90,320,290 | apb_master_agent.sv | sv | 96 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:26: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: Unsupported: classes\nclass apb_master_agent extends uvm_agent;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_agent extends uvm_agent;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:40: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_agent)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:41: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:42: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:43: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(input apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Hierarchical class references\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: scoped class reference\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: Unsupported: Out of class block function declaration\n extern virtual function void update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:63: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Hierarchical class references\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: scoped class reference\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: Hierarchical class references\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: scoped class reference\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,438 | function | function void apb_master_agent::connect_phase(uvm_phase phase);
super.connect_phase(phase);
collector.item_collected_port.connect(monitor.coll_mon_port);
monitor.addr_trans_port.connect(collector.addr_trans_export);
if (is_active == UVM_ACTIVE) begin
driver.seq_item_port.connect(sequencer.seq_item_export);
end
endfunction | function void apb_master_agent::connect_phase(uvm_phase phase); |
super.connect_phase(phase);
collector.item_collected_port.connect(monitor.coll_mon_port);
monitor.addr_trans_port.connect(collector.addr_trans_export);
if (is_active == UVM_ACTIVE) begin
driver.seq_item_port.connect(sequencer.seq_item_export);
end
endfunction | 0 |
140,347 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv | 90,320,290 | apb_master_agent.sv | sv | 96 | 81 | [] | ['apache license'] | ['all rights reserved'] | null | line:26: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: Unsupported: classes\nclass apb_master_agent extends uvm_agent;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:26: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_agent extends uvm_agent;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:40: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_agent)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:41: Define or directive not defined: \'`uvm_field_enum\'\n `uvm_field_enum(uvm_active_passive_enum, is_active, UVM_DEFAULT)\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:42: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:43: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:46: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:51: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: syntax error, unexpected IDENTIFIER, expecting \')\'\n extern virtual function void update_config(input apb_config cfg);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Hierarchical class references\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: scoped class reference\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:53: Unsupported: Out of class block function declaration\n extern virtual function void update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:63: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Hierarchical class references\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: scoped class reference\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:58: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::build_phase(uvm_phase phase);\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: Hierarchical class references\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: Unsupported: scoped class reference\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:78: Unsupported: Out of class block function declaration\nfunction void apb_master_agent::connect_phase(uvm_phase phase);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_agent.sv:90: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void apb_master_agent::update_config(input apb_config cfg);\n ^~~\n%Error: Exiting due to 24 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,438 | function | function void apb_master_agent::update_config(input apb_config cfg);
if (is_active == UVM_ACTIVE) begin
sequencer.cfg = cfg;
driver.cfg = cfg;
end
endfunction | function void apb_master_agent::update_config(input apb_config cfg); |
if (is_active == UVM_ACTIVE) begin
sequencer.cfg = cfg;
driver.cfg = cfg;
end
endfunction | 0 |
140,348 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv | 90,320,290 | apb_master_sequencer.sv | sv | 63 | 91 | [] | ['apache license'] | ['all rights reserved'] | null | line:27: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:38: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:39: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:47: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:51: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:57: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:58: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,443 | function | function new (string name, uvm_component parent);
super.new(name, parent);
endfunction | function new (string name, uvm_component parent); |
super.new(name, parent);
endfunction | 0 |
140,349 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv | 90,320,290 | apb_master_sequencer.sv | sv | 63 | 91 | [] | ['apache license'] | ['all rights reserved'] | null | line:27: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:38: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:39: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:47: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:51: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:57: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:58: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,443 | function | function void build_phase(uvm_phase phase);
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_warning("NOCONFIG", "apb_config not set for this component")
endfunction | function void build_phase(uvm_phase phase); |
super.build_phase(phase);
if (cfg == null)
if (!uvm_config_db#(apb_config)::get(this, "", "cfg", cfg))
`uvm_warning("NOCONFIG", "apb_config not set for this component")
endfunction | 0 |
140,350 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv | 90,320,290 | apb_master_sequencer.sv | sv | 63 | 91 | [] | ['apache license'] | ['all rights reserved'] | null | line:27: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: Unsupported: classes\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:27: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_sequencer extends uvm_sequencer #(apb_transfer);\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:33: Unsupported: virtual data type\n virtual apb_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:37: syntax error, unexpected \'(\'\n `uvm_component_utils_begin(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:38: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT|UVM_REFERENCE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:39: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: Unsupported: new constructor\n function new (string name, uvm_component parent);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:42: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name, uvm_component parent);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:47: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void build_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:51: Define or directive not defined: \'`uvm_warning\'\n `uvm_warning("NOCONFIG", "apb_config not set for this component")\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:55: syntax error, unexpected IDENTIFIER, expecting \')\'\n virtual function void connect_phase(uvm_phase phase);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:57: Unsupported: virtual data type\n if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_sequencer.sv:58: Define or directive not defined: \'`uvm_error\'\n : ... Suggested alternative: \'`error\'\n `uvm_error("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"})\n ^~~~~~~~~~\n%Error: Exiting due to 14 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,443 | function | function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | function void connect_phase(uvm_phase phase); |
super.connect_phase(phase);
if (!uvm_config_db#(virtual apb_if)::get(this, "", "vif", vif))
`uvm_error("NOVIF", {"virtual interface must be set for: ",get_full_name(),".vif"})
endfunction | 0 |
140,351 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="apb_master_base_seq");
super.new(name);
endfunction | function new(string name="apb_master_base_seq"); |
super.new(name);
endfunction | 0 |
140,352 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="read_byte_seq");
super.new(name);
endfunction | function new(string name="read_byte_seq"); |
super.new(name);
endfunction | 0 |
140,353 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="write_byte_seq");
super.new(name);
endfunction | function new(string name="write_byte_seq"); |
super.new(name);
endfunction | 0 |
140,354 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="read_word_seq");
super.new(name);
endfunction | function new(string name="read_word_seq"); |
super.new(name);
endfunction | 0 |
140,355 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="write_word_seq");
super.new(name);
endfunction | function new(string name="write_word_seq"); |
super.new(name);
endfunction | 0 |
140,356 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="read_after_write_seq");
super.new(name);
endfunction | function new(string name="read_after_write_seq"); |
super.new(name);
endfunction | 0 |
140,357 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv | 90,320,290 | apb_master_seq_lib.sv | sv | 222 | 82 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: Unsupported: classes\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_master_base_seq extends uvm_sequence #(apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:31: Unsupported: new constructor\n function new(string name="apb_master_base_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:32: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:35: syntax error, unexpected \'(\'\n `uvm_object_utils(apb_master_base_seq)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:36: Define or directive not defined: \'`uvm_declare_p_sequencer\'\n `uvm_declare_p_sequencer(apb_master_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:41: Unsupported: this\n starting_phase.raise_objection(this, {"Running sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:45: syntax error, unexpected virtual\n virtual task post_body();\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:47: Unsupported: this\n starting_phase.drop_objection(this, {"Completed sequence \'",\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:50: syntax error, unexpected endclass\nendclass : apb_master_base_seq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: classes\nclass read_byte_seq extends apb_master_base_seq;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:55: Unsupported: extends\nclass read_byte_seq extends apb_master_base_seq;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:59: Unsupported: new constructor\n function new(string name="read_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:60: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:63: syntax error, unexpected \'(\'\n `uvm_object_utils(read_byte_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:65: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:69: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:74: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:87: Unsupported: new constructor\n function new(string name="write_byte_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:88: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:91: syntax error, unexpected \'(\'\n `uvm_object_utils(write_byte_seq)\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:93: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:96: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:102: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("addr = \'h%0h, data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:114: Unsupported: new constructor\n function new(string name="read_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:115: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: Define or directive not defined: \'`uvm_object_utils\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:118: syntax error, unexpected \'(\'\n `uvm_object_utils(read_word_seq)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:120: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:121: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:124: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_HIGH)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:125: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:130: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("req_addr = \'h%0h, req_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:132: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("rsp_addr = \'h%0h, rsp_data = \'h%0h", \n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:143: Unsupported: new constructor\n function new(string name="write_word_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/apb_master_seq_lib.sv:144: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,444 | function | function new(string name="multiple_read_after_write_seq");
super.new(name);
endfunction | function new(string name="multiple_read_after_write_seq"); |
super.new(name);
endfunction | 0 |
140,358 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv | 90,320,290 | reg_to_apb_adapter.sv | sv | 67 | 79 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: Unsupported: classes\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:31: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(reg_to_apb_adapter)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:33: Unsupported: new constructor\n function new(string name="reg_to_apb_adapter");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:43: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:54: Unsupported or unknown PLI call: $cast\n if (!$cast(transfer, bus_item)) begin\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:55: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("NOT_REG_TYPE",\n ^~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,455 | function | function new(string name="reg_to_apb_adapter");
super.new(name);
endfunction | function new(string name="reg_to_apb_adapter"); |
super.new(name);
endfunction | 0 |
140,359 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv | 90,320,290 | reg_to_apb_adapter.sv | sv | 67 | 79 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: Unsupported: classes\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:31: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(reg_to_apb_adapter)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:33: Unsupported: new constructor\n function new(string name="reg_to_apb_adapter");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:43: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:54: Unsupported or unknown PLI call: $cast\n if (!$cast(transfer, bus_item)) begin\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:55: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("NOT_REG_TYPE",\n ^~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,455 | function | function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
apb_transfer transfer;
transfer = apb_transfer::type_id::create("transfer");
transfer.addr = rw.addr;
transfer.data = rw.data;
transfer.direction = (rw.kind == UVM_READ) ? APB_READ : APB_WRITE;
return (transfer);
endfunction | function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); |
apb_transfer transfer;
transfer = apb_transfer::type_id::create("transfer");
transfer.addr = rw.addr;
transfer.data = rw.data;
transfer.direction = (rw.kind == UVM_READ) ? APB_READ : APB_WRITE;
return (transfer);
endfunction | 0 |
140,360 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv | 90,320,290 | reg_to_apb_adapter.sv | sv | 67 | 79 | [] | ['apache license'] | ['all rights reserved'] | null | line:29: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: Unsupported: classes\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:29: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass reg_to_apb_adapter extends uvm_reg_adapter;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:31: Define or directive not defined: \'`uvm_object_utils\'\n`uvm_object_utils(reg_to_apb_adapter)\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:33: Unsupported: new constructor\n function new(string name="reg_to_apb_adapter");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:34: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:43: syntax error, unexpected IDENTIFIER, expecting \'(\' or \';\'\n function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:52: syntax error, unexpected IDENTIFIER, expecting \')\'\n function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:54: Unsupported or unknown PLI call: $cast\n if (!$cast(transfer, bus_item)) begin\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/apb/sv/reg_to_apb_adapter.sv:55: Define or directive not defined: \'`uvm_fatal\'\n `uvm_fatal("NOT_REG_TYPE",\n ^~~~~~~~~~\n%Error: Exiting due to 11 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,455 | function | function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
apb_transfer transfer;
if (!$cast(transfer, bus_item)) begin
`uvm_fatal("NOT_REG_TYPE",
"Provided bus_item is not of the correct type. Expecting apb_transfer")
return;
end
rw.kind = (transfer.direction == APB_READ) ? UVM_READ : UVM_WRITE;
rw.addr = transfer.addr;
rw.data = transfer.data;
rw.status = UVM_IS_OK;
endfunction | function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); |
apb_transfer transfer;
if (!$cast(transfer, bus_item)) begin
`uvm_fatal("NOT_REG_TYPE",
"Provided bus_item is not of the correct type. Expecting apb_transfer")
return;
end
rw.kind = (transfer.direction == APB_READ) ? UVM_READ : UVM_WRITE;
rw.addr = transfer.addr;
rw.data = transfer.data;
rw.status = UVM_IS_OK;
endfunction | 0 |
140,361 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function new (string name = "", uvm_component parent = null);
super.new(name, parent);
create_tlm_ports();
endfunction | function new (string name = "", uvm_component parent = null); |
super.new(name, parent);
create_tlm_ports();
endfunction | 0 |
140,362 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void create_tlm_ports();
extern virtual function void build();
extern virtual function void connect();
extern virtual function void write_rx(uart_frame frame);
extern virtual function void write_tx(uart_frame frame);
extern virtual function void write_apb(apb_transfer transfer);
extern virtual function void write_cfg(uart_config uart_cfg);
extern virtual function void update_config(uart_ctrl_config uart_ctrl_cfg);
extern virtual function void set_slave_config(apb_slave_config slave_cfg);
extern virtual function void set_uart_config(uart_config uart_cfg);
endclass : uart_ctrl_monitor
function void uart_ctrl_monitor::create_tlm_ports();
apb_in = new("apb_in", this);
apb_out = new("apb_out", this);
uart_rx_in = new("uart_rx_in", this);
uart_rx_out = new("uart_rx_out", this);
uart_tx_in = new("uart_tx_in", this);
uart_tx_out = new("uart_tx_out", this);
endfunction | function void create_tlm_ports(); |
extern virtual function void build();
extern virtual function void connect();
extern virtual function void write_rx(uart_frame frame);
extern virtual function void write_tx(uart_frame frame);
extern virtual function void write_apb(apb_transfer transfer);
extern virtual function void write_cfg(uart_config uart_cfg);
extern virtual function void update_config(uart_ctrl_config uart_ctrl_cfg);
extern virtual function void set_slave_config(apb_slave_config slave_cfg);
extern virtual function void set_uart_config(uart_config uart_cfg);
endclass : uart_ctrl_monitor
function void uart_ctrl_monitor::create_tlm_ports();
apb_in = new("apb_in", this);
apb_out = new("apb_out", this);
uart_rx_in = new("uart_rx_in", this);
uart_rx_out = new("uart_rx_out", this);
uart_tx_in = new("uart_tx_in", this);
uart_tx_out = new("uart_tx_out", this);
endfunction | 0 |
140,363 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::build();
super.build();
uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);
if (cfg == null) begin
`uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)
cfg = uart_ctrl_config::type_id::create("cfg", this);
set_config_object("tx_scbd", "cfg", cfg);
set_config_object("rx_scbd", "cfg", cfg);
end
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);
endfunction | function void uart_ctrl_monitor::build(); |
super.build();
uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);
if (cfg == null) begin
`uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)
cfg = uart_ctrl_config::type_id::create("cfg", this);
set_config_object("tx_scbd", "cfg", cfg);
set_config_object("rx_scbd", "cfg", cfg);
end
tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);
rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);
endfunction | 0 |
140,364 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::connect();
super.connect();
apb_out.connect(tx_scbd.apb_match);
uart_tx_out.connect(tx_scbd.uart_add);
apb_out.connect(rx_scbd.apb_add);
uart_rx_out.connect(rx_scbd.uart_match);
endfunction | function void uart_ctrl_monitor::connect(); |
super.connect();
apb_out.connect(tx_scbd.apb_match);
uart_tx_out.connect(tx_scbd.uart_add);
apb_out.connect(rx_scbd.apb_add);
uart_rx_out.connect(rx_scbd.uart_match);
endfunction | 0 |
140,365 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::write_rx(uart_frame frame);
uart_rx_out.write(frame);
rx_time_q.push_front($time);
endfunction | function void uart_ctrl_monitor::write_rx(uart_frame frame); |
uart_rx_out.write(frame);
rx_time_q.push_front($time);
endfunction | 0 |
140,366 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::write_tx(uart_frame frame);
uart_tx_out.write(frame);
tx_time_in = tx_time_q.pop_back();
tx_time_out = ($time-tx_time_in)/clk_period;
endfunction | function void uart_ctrl_monitor::write_tx(uart_frame frame); |
uart_tx_out.write(frame);
tx_time_in = tx_time_q.pop_back();
tx_time_out = ($time-tx_time_in)/clk_period;
endfunction | 0 |
140,367 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);
set_uart_config(uart_cfg);
endfunction | function void uart_ctrl_monitor::write_cfg(uart_config uart_cfg); |
set_uart_config(uart_cfg);
endfunction | 0 |
140,368 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::write_apb(apb_transfer transfer);
apb_out.write(transfer);
if ((transfer.direction == APB_READ) && (transfer.addr == `RX_FIFO_REG))
begin
rx_time_in = rx_time_q.pop_back();
rx_time_out = ($time-rx_time_in)/clk_period;
end
else if ((transfer.direction == APB_WRITE) && (transfer.addr == `TX_FIFO_REG))
begin
tx_time_q.push_front($time);
end
endfunction | function void uart_ctrl_monitor::write_apb(apb_transfer transfer); |
apb_out.write(transfer);
if ((transfer.direction == APB_READ) && (transfer.addr == `RX_FIFO_REG))
begin
rx_time_in = rx_time_q.pop_back();
rx_time_out = ($time-rx_time_in)/clk_period;
end
else if ((transfer.direction == APB_WRITE) && (transfer.addr == `TX_FIFO_REG))
begin
tx_time_q.push_front($time);
end
endfunction | 0 |
140,369 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::update_config(uart_ctrl_config uart_ctrl_cfg);
`uvm_info(get_type_name(), {"Updating Config\n", uart_ctrl_cfg.sprint}, UVM_HIGH)
cfg = uart_ctrl_cfg;
tx_scbd.slave_cfg = uart_ctrl_cfg.apb_cfg.slave_configs[0];
tx_scbd.uart_cfg = uart_ctrl_cfg.uart_cfg;
rx_scbd.slave_cfg = uart_ctrl_cfg.apb_cfg.slave_configs[0];
rx_scbd.uart_cfg = uart_ctrl_cfg.uart_cfg;
endfunction | function void uart_ctrl_monitor::update_config(uart_ctrl_config uart_ctrl_cfg); |
`uvm_info(get_type_name(), {"Updating Config\n", uart_ctrl_cfg.sprint}, UVM_HIGH)
cfg = uart_ctrl_cfg;
tx_scbd.slave_cfg = uart_ctrl_cfg.apb_cfg.slave_configs[0];
tx_scbd.uart_cfg = uart_ctrl_cfg.uart_cfg;
rx_scbd.slave_cfg = uart_ctrl_cfg.apb_cfg.slave_configs[0];
rx_scbd.uart_cfg = uart_ctrl_cfg.uart_cfg;
endfunction | 0 |
140,370 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::set_slave_config(apb_slave_config slave_cfg);
cfg.apb_cfg.slave_configs[0] = slave_cfg;
tx_scbd.slave_cfg = slave_cfg;
rx_scbd.slave_cfg = slave_cfg;
endfunction | function void uart_ctrl_monitor::set_slave_config(apb_slave_config slave_cfg); |
cfg.apb_cfg.slave_configs[0] = slave_cfg;
tx_scbd.slave_cfg = slave_cfg;
rx_scbd.slave_cfg = slave_cfg;
endfunction | 0 |
140,371 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv | 90,320,290 | uart_ctrl_monitor.sv | sv | 162 | 87 | [] | [] | [] | null | line:12: before: "_rx" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_rx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:12: syntax error, unexpected \'(\'\n`uvm_analysis_imp_decl(_rx)\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:13: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_tx)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:14: Define or directive not defined: \'`uvm_analysis_imp_decl\'\n`uvm_analysis_imp_decl(_cfg)\n^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: Unsupported: classes\nclass uart_ctrl_monitor extends uvm_monitor;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:17: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_monitor extends uvm_monitor;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:20: Unsupported: virtual interface\n virtual interface uart_ctrl_internal_if vif;\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:27: syntax error, unexpected IDENTIFIER\n uart_ctrl_config cfg;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:48: Define or directive not defined: \'`uvm_component_utils\'\n `uvm_component_utils(uart_ctrl_monitor)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: Unsupported: new constructor\n function new (string name = "", uvm_component parent = null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:50: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (string name = "", uvm_component parent = null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:56: syntax error, unexpected \'@\'\n @(posedge vif.clock) clk_period = $time;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: syntax error, unexpected virtual, expecting interface or module or program\n extern virtual function void create_tlm_ports();\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:62: syntax error, unexpected extern\n extern virtual function void build();\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: this\n apb_in = new("apb_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:75: Unsupported: new with arguments\n apb_in = new("apb_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: this\n apb_out = new("apb_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:76: Unsupported: new with arguments\n apb_out = new("apb_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: this\n uart_rx_in = new("uart_rx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:77: Unsupported: new with arguments\n uart_rx_in = new("uart_rx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: this\n uart_rx_out = new("uart_rx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:78: Unsupported: new with arguments\n uart_rx_out = new("uart_rx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: this\n uart_tx_in = new("uart_tx_in", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:79: Unsupported: new with arguments\n uart_tx_in = new("uart_tx_in", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: this\n uart_tx_out = new("uart_tx_out", this);\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:80: Unsupported: new with arguments\n uart_tx_out = new("uart_tx_out", this);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::build();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:61: Unsupported: Out of class block function declaration\n extern virtual function void create_tlm_ports();\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:84: Unsupported: super\n super.build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:85: syntax error, unexpected ::, expecting \';\'\n uart_cover = uart_ctrl_cover::type_id::create("uart_cover",this);\n ^~\n : ... Perhaps \'uart_ctrl_cover\' is a package which needs to be predeclared? (IEEE 1800-2017 26.3)\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:87: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "cfg is null...creating ", UVM_MEDIUM)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:92: syntax error, unexpected ::, expecting \';\'\n tx_scbd = uart_ctrl_tx_scbd::type_id::create("tx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:93: syntax error, unexpected ::, expecting \';\'\n rx_scbd = uart_ctrl_rx_scbd::type_id::create("rx_scbd",this);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::connect();\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:83: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::build();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:101: Unsupported: super\n super.connect();\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:100: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::connect();\n ^~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:109: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_rx(uart_frame frame);\n ^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: syntax error, unexpected IDENTIFIER, expecting \')\'\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: Hierarchical class references\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:122: Unsupported: scoped class reference\nfunction void uart_ctrl_monitor::write_cfg(uart_config uart_cfg);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_monitor.sv:115: Unsupported: Out of class block function declaration\nfunction void uart_ctrl_monitor::write_tx(uart_frame frame);\n ^~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 308,459 | function | function void uart_ctrl_monitor::set_uart_config(uart_config uart_cfg);
cfg.uart_cfg = uart_cfg;
tx_scbd.uart_cfg = uart_cfg;
rx_scbd.uart_cfg = uart_cfg;
endfunction | function void uart_ctrl_monitor::set_uart_config(uart_config uart_cfg); |
cfg.uart_cfg = uart_cfg;
tx_scbd.uart_cfg = uart_cfg;
rx_scbd.uart_cfg = uart_cfg;
endfunction | 0 |
140,372 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv | 90,320,290 | uart_ctrl_virtual_sequencer.sv | sv | 29 | 101 | [] | [] | [] | null | line:12: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:12: Unsupported: classes\nclass uart_ctrl_virtual_sequencer extends uvm_sequencer;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:12: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass uart_ctrl_virtual_sequencer extends uvm_sequencer;\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:20: Unsupported: new constructor\n function new (input string name="uart_ctrl_virtual_sequencer", input uvm_component parent=null);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:20: syntax error, unexpected IDENTIFIER, expecting \')\'\n function new (input string name="uart_ctrl_virtual_sequencer", input uvm_component parent=null);\n ^~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:24: Define or directive not defined: \'`uvm_component_utils_begin\'\n `uvm_component_utils_begin(uart_ctrl_virtual_sequencer)\n ^~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:25: Define or directive not defined: \'`uvm_field_object\'\n `uvm_field_object(cfg, UVM_DEFAULT | UVM_NOPRINT)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/uart_ctrl_virtual_sequencer.sv:26: Define or directive not defined: \'`uvm_component_utils_end\'\n `uvm_component_utils_end\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 7 error(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 308,461 | function | function new (input string name="uart_ctrl_virtual_sequencer", input uvm_component parent=null);
super.new(name, parent);
endfunction | function new (input string name="uart_ctrl_virtual_sequencer", input uvm_component parent=null); |
super.new(name, parent);
endfunction | 0 |
140,373 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv | 90,320,290 | simple_seq_lib.sv | sv | 114 | 89 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: Unsupported: classes\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="program_dut_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:21: syntax error, unexpected rand\n rand uart_pkg::uart_config cfg;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:24: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(program_dut_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:28: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: syntax error, unexpected IDENTIFIER\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `LINE_CTRL;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:39: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:40: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:41: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:43: Define or directive not defined: \'`DIVD_LATCH1\'\n start_addr = `DIVD_LATCH1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:46: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:47: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:49: Define or directive not defined: \'`DIVD_LATCH2\'\n start_addr = `DIVD_LATCH2;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:52: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:53: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:55: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:59: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:60: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:61: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:70: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:73: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(read_rx_fifo_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:76: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:77: syntax error, unexpected rand\n rand int unsigned num_of_rd;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: syntax error, unexpected IDENTIFIER\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(read_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:85: Define or directive not defined: \'`RX_FIFO_REG\'\n read_addr = `RX_FIFO_REG; \n ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,462 | function | function new(string name="program_dut_seq");
super.new(name);
endfunction | function new(string name="program_dut_seq"); |
super.new(name);
endfunction | 0 |
140,374 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv | 90,320,290 | simple_seq_lib.sv | sv | 114 | 89 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: Unsupported: classes\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="program_dut_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:21: syntax error, unexpected rand\n rand uart_pkg::uart_config cfg;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:24: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(program_dut_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:28: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: syntax error, unexpected IDENTIFIER\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `LINE_CTRL;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:39: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:40: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:41: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:43: Define or directive not defined: \'`DIVD_LATCH1\'\n start_addr = `DIVD_LATCH1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:46: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:47: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:49: Define or directive not defined: \'`DIVD_LATCH2\'\n start_addr = `DIVD_LATCH2;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:52: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:53: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:55: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:59: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:60: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:61: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:70: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:73: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(read_rx_fifo_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:76: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:77: syntax error, unexpected rand\n rand int unsigned num_of_rd;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: syntax error, unexpected IDENTIFIER\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(read_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:85: Define or directive not defined: \'`RX_FIFO_REG\'\n read_addr = `RX_FIFO_REG; \n ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,462 | function | function new(string name="read_rx_fifo_seq");
super.new(name);
endfunction | function new(string name="read_rx_fifo_seq"); |
super.new(name);
endfunction | 0 |
140,375 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv | 90,320,290 | simple_seq_lib.sv | sv | 114 | 89 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: Unsupported: classes\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass program_dut_seq extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="program_dut_seq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:21: syntax error, unexpected rand\n rand uart_pkg::uart_config cfg;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:24: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(program_dut_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:28: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:29: syntax error, unexpected IDENTIFIER\n constraint c_transmit_del { transmit_del <= 8; }\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:32: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:35: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `LINE_CTRL;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:37: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:39: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:40: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:41: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:43: Define or directive not defined: \'`DIVD_LATCH1\'\n start_addr = `DIVD_LATCH1;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:46: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:47: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:49: Define or directive not defined: \'`DIVD_LATCH2\'\n start_addr = `DIVD_LATCH2;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:50: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:52: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:53: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:55: Define or directive not defined: \'`LINE_CTRL\'\n start_addr = `LINE_CTRL;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:57: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:59: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:60: syntax error, unexpected \';\'\n req.data == write_data;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:61: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:69: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:70: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:73: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(read_rx_fifo_seq, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:76: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:77: syntax error, unexpected rand\n rand int unsigned num_of_rd;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:78: syntax error, unexpected IDENTIFIER\n constraint num_of_rd_ct { (num_of_rd <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:79: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(read_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:83: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Starting %0d Reads...", num_of_rd), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/simple_seq_lib.sv:85: Define or directive not defined: \'`RX_FIFO_REG\'\n read_addr = `RX_FIFO_REG; \n ^~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,462 | function | function new(string name="uart_tx_seq");
super.new(name);
endfunction | function new(string name="uart_tx_seq"); |
super.new(name);
endfunction | 0 |
140,376 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv | 90,320,290 | uart_ctrl_seq_lib.sv | sv | 222 | 157 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: Unsupported: classes\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="apb_to_uart_rd_after_wr");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: syntax error, unexpected \'(\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:25: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: syntax error, unexpected IDENTIFIER\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:35: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:36: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:38: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:41: syntax error, unexpected \';\'\n req.direction == APB_READ;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:42: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:52: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:55: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_wr, apb_rgm_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:58: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:59: syntax error, unexpected rand\n rand int unsigned num_of_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \')\', expecting \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: syntax error, unexpected \',\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:78: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:79: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:83: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:94: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,463 | function | function new(string name="apb_to_uart_rd_after_wr");
super.new(name);
endfunction | function new(string name="apb_to_uart_rd_after_wr"); |
super.new(name);
endfunction | 0 |
140,377 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv | 90,320,290 | uart_ctrl_seq_lib.sv | sv | 222 | 157 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: Unsupported: classes\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="apb_to_uart_rd_after_wr");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: syntax error, unexpected \'(\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:25: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: syntax error, unexpected IDENTIFIER\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:35: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:36: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:38: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:41: syntax error, unexpected \';\'\n req.direction == APB_READ;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:42: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:52: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:55: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_wr, apb_rgm_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:58: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:59: syntax error, unexpected rand\n rand int unsigned num_of_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \')\', expecting \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: syntax error, unexpected \',\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:78: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:79: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:83: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:94: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,463 | function | function new(string name="apb_to_uart_wr");
super.new(name);
endfunction | function new(string name="apb_to_uart_wr"); |
super.new(name);
endfunction | 0 |
140,378 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv | 90,320,290 | uart_ctrl_seq_lib.sv | sv | 222 | 157 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: Unsupported: classes\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="apb_to_uart_rd_after_wr");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: syntax error, unexpected \'(\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:25: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: syntax error, unexpected IDENTIFIER\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:35: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:36: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:38: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:41: syntax error, unexpected \';\'\n req.direction == APB_READ;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:42: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:52: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:55: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_wr, apb_rgm_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:58: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:59: syntax error, unexpected rand\n rand int unsigned num_of_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \')\', expecting \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: syntax error, unexpected \',\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:78: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:79: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:83: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:94: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,463 | function | function new(string name="program_dut_seq");
super.new(name);
endfunction | function new(string name="program_dut_seq"); |
super.new(name);
endfunction | 0 |
140,379 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv | 90,320,290 | uart_ctrl_seq_lib.sv | sv | 222 | 157 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: Unsupported: classes\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="apb_to_uart_rd_after_wr");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: syntax error, unexpected \'(\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:25: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: syntax error, unexpected IDENTIFIER\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:35: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:36: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:38: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:41: syntax error, unexpected \';\'\n req.direction == APB_READ;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:42: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:52: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:55: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_wr, apb_rgm_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:58: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:59: syntax error, unexpected rand\n rand int unsigned num_of_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \')\', expecting \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: syntax error, unexpected \',\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:78: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:79: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:83: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:94: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,463 | function | function new(string name="read_rx_fifo_seq");
super.new(name);
endfunction | function new(string name="read_rx_fifo_seq"); |
super.new(name);
endfunction | 0 |
140,380 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv | 90,320,290 | uart_ctrl_seq_lib.sv | sv | 222 | 157 | [] | [] | [] | null | line:15: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: Unsupported: classes\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:15: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass apb_to_uart_rd_after_wr extends uvm_sequence #(apb_pkg::apb_transfer);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:17: Unsupported: new constructor\n function new(string name="apb_to_uart_rd_after_wr");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:18: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:22: syntax error, unexpected \'(\'\n `uvm_sequence_utils(apb_to_uart_rd_after_wr, apb_pkg::apb_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:25: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:26: syntax error, unexpected IDENTIFIER\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:30: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "APB RGM Sequencer Starting...", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:32: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:33: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:35: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:36: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:38: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:39: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:41: syntax error, unexpected \';\'\n req.direction == APB_READ;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:42: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:51: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:52: syntax error, unexpected endfunction, expecting endtask\n endfunction\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:55: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(apb_to_uart_wr, apb_rgm_master_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:58: syntax error, unexpected rand\n rand int unsigned transmit_del = 0;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:59: syntax error, unexpected rand\n rand int unsigned num_of_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:60: syntax error, unexpected IDENTIFIER\n constraint num_of_wr_ct { (num_of_wr <= 150); }\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:61: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint transmit_del_ct { (transmit_del <= 10); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:62: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint addr_ct {(start_addr[1:0] == 0); }\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: Define or directive not defined: \'`TX_FIFO_REG\'\n start_addr = `TX_FIFO_REG;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:66: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n start_addr = `TX_FIFO_REG;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:68: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("APB RGM Sequencer Starting %0d Writes...", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:69: syntax error, unexpected \')\', expecting \';\'\n for (int i = 0; i < num_of_wr; i++) begin\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: Define or directive not defined: \'`uvm_info\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:72: syntax error, unexpected \',\'\n `uvm_info("UART_APB_SEQLIB", $sformatf("Breaking from apb_to_uart_wr since tfifo is not empty yet, pending num_of_wr = %d", num_of_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: Define or directive not defined: \'`uvm_do_with\'\n `uvm_do_with(req, \n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:76: syntax error, unexpected \',\'\n `uvm_do_with(req, \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:78: syntax error, unexpected \';\'\n req.direction == APB_WRITE;\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:79: syntax error, unexpected \';\'\n req.transmit_delay == transmit_del; } )\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:83: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_seq_lib.sv:94: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,463 | function | function new(string name="apb_interrupt_from_uart");
super.new(name);
endfunction | function new(string name="apb_interrupt_from_uart"); |
super.new(name);
endfunction | 0 |
140,381 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv | 90,320,290 | uart_ctrl_virtual_seq_lib.sv | sv | 313 | 124 | [] | [] | [] | null | line:21: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: Unsupported: classes\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:24: syntax error, unexpected rand\n rand int unsigned num_u2a_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:26: Unsupported: new constructor\n function new(string name="concurrent_u2a_a2u_rand_trans_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr <= 6);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr <= 9);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:52: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:56: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(raw_seq, p_sequencer.apb_seqr, {num_of_wr == num_a2u_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {num_of_tx == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: syntax error, unexpected \',\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:66: syntax error, unexpected endclass\nendclass : concurrent_u2a_a2u_rand_trans_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: Unsupported: classes\nclass u2a_incr_payload_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_incr_payload_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:71: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:73: Unsupported: new constructor\n function new(string name="u2a_incr_payload_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr > 2) && (num_u2a_wr <= 10);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr == 0);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:93: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:99: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {cnt == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:100: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:105: syntax error, unexpected endclass\nendclass : u2a_incr_payload_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: Unsupported: classes\nclass u2a_bad_parity_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_bad_parity_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:110: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:112: Unsupported: new constructor\n function new(string name="u2a_bad_parity_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,464 | function | function new(string name="concurrent_u2a_a2u_rand_trans_vseq");
super.new(name);
endfunction | function new(string name="concurrent_u2a_a2u_rand_trans_vseq"); |
super.new(name);
endfunction | 0 |
140,382 | data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv | 90,320,290 | uart_ctrl_virtual_seq_lib.sv | sv | 313 | 124 | [] | [] | [] | null | line:21: before: "class" | null | 1: b'%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: Unsupported: classes\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:21: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass concurrent_u2a_a2u_rand_trans_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:24: syntax error, unexpected rand\n rand int unsigned num_u2a_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:26: Unsupported: new constructor\n function new(string name="concurrent_u2a_a2u_rand_trans_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:27: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:31: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(concurrent_u2a_a2u_rand_trans_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:33: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr <= 6);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr <= 9);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:44: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:47: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:48: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:49: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:52: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:56: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(raw_seq, p_sequencer.apb_seqr, {num_of_wr == num_a2u_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:57: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {num_of_tx == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:61: syntax error, unexpected \',\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:66: syntax error, unexpected endclass\nendclass : concurrent_u2a_a2u_rand_trans_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: Unsupported: classes\nclass u2a_incr_payload_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:68: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_incr_payload_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:71: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:73: Unsupported: new constructor\n function new(string name="u2a_incr_payload_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:74: Unsupported: dotted new\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: Define or directive not defined: \'`uvm_sequence_utils\'\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:78: syntax error, unexpected new-then-paren, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `uvm_sequence_utils(u2a_incr_payload_vseq, uart_ctrl_virtual_sequencer) \n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:80: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_u2a_wr_ct {(num_u2a_wr > 2) && (num_u2a_wr <= 10);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:81: Unsupported: SystemVerilog 2005 reserved word not implemented: \'constraint\'\n constraint num_a2u_wr_ct {(num_a2u_wr == 0);}\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:89: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), "UART Controller Virtual Sequencer Executing", UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:92: syntax error, unexpected \',\'\n `uvm_info(get_type_name(), $sformatf("Number of APB->UART Transaction = %0d", num_a2u_wr), UVM_LOW)\n ^\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:93: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Number of UART->APB Transaction = %0d", num_u2a_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:94: Define or directive not defined: \'`uvm_info\'\n `uvm_info(get_type_name(), $sformatf("Total Number of APB<->UART Transaction = %0d", num_u2a_wr + num_a2u_wr), UVM_LOW)\n ^~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:97: Define or directive not defined: \'`uvm_do_on\'\n `uvm_do_on(uart_cfg_dut_seq, p_sequencer.rgm_seqr)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:99: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(uart_seq, p_sequencer.uart_seqr, {cnt == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:100: Define or directive not defined: \'`uvm_do_on_with\'\n `uvm_do_on_with(rd_rx_fifo, p_sequencer.apb_seqr, {num_of_rd == num_u2a_wr;})\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:105: syntax error, unexpected endclass\nendclass : u2a_incr_payload_vseq\n^~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: Unsupported: classes\nclass u2a_bad_parity_vseq extends uvm_sequence;\n^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:107: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER\nclass u2a_bad_parity_vseq extends uvm_sequence;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:110: syntax error, unexpected rand\n rand int unsigned num_a2u_wr;\n ^~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:112: Unsupported: new constructor\n function new(string name="u2a_bad_parity_vseq");\n ^~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: super\n super.new(name);\n ^~~~~\n%Error: data/full_repos/permissive/90320290/uvm_book/examples_lib/7_simple_testbench_integration/sv/sequence_lib/uart_ctrl_virtual_seq_lib.sv:113: Unsupported: new with arguments\n super.new(name);\n ^~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n ... See the manual and https://verilator.org for more assistance.\n' | 308,464 | function | function new(string name="u2a_incr_payload_vseq");
super.new(name);
endfunction | function new(string name="u2a_incr_payload_vseq"); |
super.new(name);
endfunction | 0 |
Subsets and Splits