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140,792 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module fulladder (
input a, b, c_in,
output sum, c_out
);
wire s1, c1, c2;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a, b);
and g4(c2, s1, c_in);
or g5(c_out, c2, c1);
endmodule | module fulladder (
input a, b, c_in,
output sum, c_out
); |
wire s1, c1, c2;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a, b);
and g4(c2, s1, c_in);
or g5(c_out, c2, c1);
endmodule | 0 |
140,793 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module not4 (input [3:0] x, output [3:0] y);
assign y = ~x;
endmodule | module not4 (input [3:0] x, output [3:0] y); |
assign y = ~x;
endmodule | 0 |
140,794 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module xor4 (input [3:0] a, input [3:0] b, output [3:0] y);
assign y = a ^ b;
endmodule | module xor4 (input [3:0] a, input [3:0] b, output [3:0] y); |
assign y = a ^ b;
endmodule | 0 |
140,795 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module add4 (
input c_in,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
);
wire [3:0] c;
fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ;
fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ;
fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ;
fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ;
endmodule | module add4 (
input c_in,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
); |
wire [3:0] c;
fulladder fa1(a[0],b[0], c_in, sum[0], c[1]) ;
fulladder fa2(a[1],b[1], c[1], sum[1], c[2]) ;
fulladder fa3(a[2],b[2], c[2], sum[2], c[3]) ;
fulladder fa4(a[3],b[3], c[3], sum[3], c_out) ;
endmodule | 0 |
140,796 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module sub4 (
input op,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
);
wire [3:0] bnot;
not4 n1(b, bnot);
add4 a1(op, a, bnot, sum, c_out);
endmodule | module sub4 (
input op,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
); |
wire [3:0] bnot;
not4 n1(b, bnot);
add4 a1(op, a, bnot, sum, c_out);
endmodule | 0 |
140,797 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module addSub4 (
input op,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
);
wire [3:0] bop;
xor4 x1(b, {op, op, op, op}, bop);
add4 a1(op, a, bop, sum, c_out);
endmodule | module addSub4 (
input op,
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output c_out
); |
wire [3:0] bop;
xor4 x1(b, {op, op, op, op}, bop);
add4 a1(op, a, bop, sum, c_out);
endmodule | 0 |
140,798 | data/full_repos/permissive/91778934/FullAddr/fulladdr.v | 91,778,934 | fulladdr.v | v | 91 | 77 | [] | [] | [] | null | line:80: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:76: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("fulladder.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:77: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:82: Unsupported or unknown PLI call: $monitor\n $monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);\n ^~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:80: Unsupported: Ignoring delay on this delayed statement.\n always #1600 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:85: Unsupported: Ignoring delay on this delayed statement.\n always #100 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/FullAddr/fulladdr.v:89: Unsupported: Ignoring delay on this delayed statement.\n initial #3000 $finish;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,709 | module | module main;
reg signed [3:0] a;
reg signed [3:0] b;
wire signed [3:0] sum;
reg op;
wire c_out;
addSub4 as(op, a, b, sum, c_out);
initial begin
a = 4'b0101;
b = 4'b0000;
op = 1'b0;
$dumpfile("fulladder.vcd");
$dumpvars;
end
always #1600 begin
op = op + 1;
$monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);
end
always #100 begin
b = b + 1;
end
initial #3000 $finish;
endmodule | module main; |
reg signed [3:0] a;
reg signed [3:0] b;
wire signed [3:0] sum;
reg op;
wire c_out;
addSub4 as(op, a, b, sum, c_out);
initial begin
a = 4'b0101;
b = 4'b0000;
op = 1'b0;
$dumpfile("fulladder.vcd");
$dumpvars;
end
always #1600 begin
op = op + 1;
$monitor("%dns monitor: op=%d a=%d b=%d sum=%d", $stime, op, a, b, sum);
end
always #100 begin
b = b + 1;
end
initial #3000 $finish;
endmodule | 0 |
140,799 | data/full_repos/permissive/91778934/Mux4_1/mux4_1.v | 91,778,934 | mux4_1.v | v | 52 | 40 | [] | [] | [] | null | line:43: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 sel = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:39: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:40: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:41: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:42: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:43: Unsupported: Ignoring delay on this delayed statement.\n #40 $finish;\n ^\n%Error: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:47: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mux4_1.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:48: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,710 | module | module mux4_1(
input [3:0] in,
input [1:0] sel,
output out
);
assign out = in[sel];
endmodule | module mux4_1(
input [3:0] in,
input [1:0] sel,
output out
); |
assign out = in[sel];
endmodule | 0 |
140,800 | data/full_repos/permissive/91778934/Mux4_1/mux4_1.v | 91,778,934 | mux4_1.v | v | 52 | 40 | [] | [] | [] | null | line:43: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:33: Unsupported: Ignoring delay on this delayed statement.\n #10;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:38: Unsupported: Ignoring delay on this delayed statement.\n #0 sel = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:39: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b01;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:40: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:41: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:42: Unsupported: Ignoring delay on this delayed statement.\n #40 sel = 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:43: Unsupported: Ignoring delay on this delayed statement.\n #40 $finish;\n ^\n%Error: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:47: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("mux4_1.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/Mux4_1/mux4_1.v:48: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Error: Exiting due to 2 error(s), 7 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,710 | module | module main;
output out;
reg [3:0] in;
reg [1:0] sel;
mux4_1 m41(in, sel, out);
integer i;
initial begin
for(i = 0; i < 20; i = i + 1) begin
in = i;
#10;
end
end
initial begin
#0 sel = 2'b00;
#40 sel = 2'b01;
#40 sel = 2'b10;
#40 sel = 2'b11;
#40 sel = 2'b00;
#40 $finish;
end
initial begin
$dumpfile("mux4_1.vcd");
$dumpvars;
end
endmodule | module main; |
output out;
reg [3:0] in;
reg [1:0] sel;
mux4_1 m41(in, sel, out);
integer i;
initial begin
for(i = 0; i < 20; i = i + 1) begin
in = i;
#10;
end
end
initial begin
#0 sel = 2'b00;
#40 sel = 2'b01;
#40 sel = 2'b10;
#40 sel = 2'b11;
#40 sel = 2'b00;
#40 $finish;
end
initial begin
$dumpfile("mux4_1.vcd");
$dumpvars;
end
endmodule | 0 |
140,801 | data/full_repos/permissive/91778934/SRLatch/srlatch.v | 91,778,934 | srlatch.v | v | 46 | 39 | [] | [] | [] | null | line:36: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("srlatch.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:40: Unsupported: Ignoring delay on this delayed statement.\n always #300 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:44: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,711 | module | module nor_latch(
input S,
input R,
output Q,
output Qb
);
nor n1(Q, S, Qb);
nor n2(Qb, R, Q);
endmodule | module nor_latch(
input S,
input R,
output Q,
output Qb
); |
nor n1(Q, S, Qb);
nor n2(Qb, R, Q);
endmodule | 0 |
140,802 | data/full_repos/permissive/91778934/SRLatch/srlatch.v | 91,778,934 | srlatch.v | v | 46 | 39 | [] | [] | [] | null | line:36: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("srlatch.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:40: Unsupported: Ignoring delay on this delayed statement.\n always #300 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:44: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,711 | module | module nand_latch(
input S,
input R,
output Q,
output Qb
);
nand n1(Q, S, Qb);
nand n2(Qb, R, Q);
endmodule | module nand_latch(
input S,
input R,
output Q,
output Qb
); |
nand n1(Q, S, Qb);
nand n2(Qb, R, Q);
endmodule | 0 |
140,803 | data/full_repos/permissive/91778934/SRLatch/srlatch.v | 91,778,934 | srlatch.v | v | 46 | 39 | [] | [] | [] | null | line:36: before: "begin" | null | 1: b'%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:32: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("srlatch.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91778934/SRLatch/srlatch.v:33: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:36: Unsupported: Ignoring delay on this delayed statement.\n always #50 begin\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:40: Unsupported: Ignoring delay on this delayed statement.\n always #300 begin\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91778934/SRLatch/srlatch.v:44: Unsupported: Ignoring delay on this delayed statement.\n initial #1000 $finish;\n ^\n%Error: Exiting due to 2 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,711 | module | module main;
reg S, R;
wire Q, Qb;
nand_latch nand_latch(S, R, Q, Qb);
initial begin
S = 0;
R = 0;
$dumpfile("srlatch.vcd");
$dumpvars;
end
always #50 begin
S = S + 1;
end
always #300 begin
R = R + 1;
end
initial #1000 $finish;
endmodule | module main; |
reg S, R;
wire Q, Qb;
nand_latch nand_latch(S, R, Q, Qb);
initial begin
S = 0;
R = 0;
$dumpfile("srlatch.vcd");
$dumpvars;
end
always #50 begin
S = S + 1;
end
always #300 begin
R = R + 1;
end
initial #1000 $finish;
endmodule | 0 |
140,804 | data/full_repos/permissive/91855037/src/data_port.v | 91,855,037 | data_port.v | v | 35 | 32 | [] | [] | [] | [(1, 34)] | null | data/verilator_xmls/481ba4dd-4b3b-4a93-babb-d3401a07e6b9.xml | null | 309,716 | module | module data_port (
input clk,
output [7:0] data_out,
input input_pin_0,
input input_pin_1,
input input_pin_2,
input input_pin_3,
input input_pin_4,
input input_pin_5,
input input_pin_6,
input input_pin_7);
wire [7:0] data;
assign data[0] = input_pin_0;
assign data[1] = input_pin_1;
assign data[2] = input_pin_2;
assign data[3] = input_pin_3;
assign data[4] = input_pin_4;
assign data[5] = input_pin_5;
assign data[6] = input_pin_6;
assign data[7] = input_pin_7;
reg [7:0] data_q;
assign data_out = data_q;
always @(posedge clk) begin
data_q <= data;
end
endmodule | module data_port (
input clk,
output [7:0] data_out,
input input_pin_0,
input input_pin_1,
input input_pin_2,
input input_pin_3,
input input_pin_4,
input input_pin_5,
input input_pin_6,
input input_pin_7); |
wire [7:0] data;
assign data[0] = input_pin_0;
assign data[1] = input_pin_1;
assign data[2] = input_pin_2;
assign data[3] = input_pin_3;
assign data[4] = input_pin_4;
assign data[5] = input_pin_5;
assign data[6] = input_pin_6;
assign data[7] = input_pin_7;
reg [7:0] data_q;
assign data_out = data_q;
always @(posedge clk) begin
data_q <= data;
end
endmodule | 7 |
140,806 | data/full_repos/permissive/91855037/src/gravity_simulator.v | 91,855,037 | gravity_simulator.v | v | 264 | 69 | [] | [] | [] | null | line:257: before: "to_scope_reg" | null | 1: b"%Error: data/full_repos/permissive/91855037/src/gravity_simulator.v:257: syntax error, unexpected IDENTIFIER\n to_scope_reg = {2'b0, y_pos_object};\n ^~~~~~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,718 | module | module gravity_simulator (
output [7:0] to_scope,
input clock,
input reset);
reg [6:0] x_pos_all [7:0];
reg [5:0] y_pos_all [7:0];
reg [13:0] x_vel_all [7:0];
reg [13:0] y_vel_all [7:0];
reg [26:0] clock_counter;
reg [2:0] object_select;
always @(posedge clock) begin
if (reset) begin
clock_counter = 27'b0;
object_select = 3'b0;
x_pos_all[0] = 7'd10;
y_pos_all[0] = 6'd10;
x_pos_all[1] = 7'd10;
y_pos_all[1] = 6'd20;
x_pos_all[2] = 7'd20;
y_pos_all[2] = 6'd20;
x_pos_all[3] = 7'd20;
y_pos_all[3] = 6'd10;
x_pos_all[4] = 7'd50;
y_pos_all[4] = 6'd50;
x_pos_all[5] = 7'd30;
y_pos_all[5] = 6'd30;
x_pos_all[6] = 7'd40;
y_pos_all[6] = 6'd40;
x_pos_all[7] = 7'd40;
y_pos_all[7] = 6'd50;
x_vel_all[0] = 14'b0;
y_vel_all[0] = 14'b0;
x_vel_all[1] = 14'b0;
y_vel_all[1] = 14'b0;
x_vel_all[2] = 14'b0;
y_vel_all[2] = 14'b0;
x_vel_all[3] = 14'b0;
y_vel_all[3] = 14'b0;
x_vel_all[4] = 14'b0;
y_vel_all[4] = 14'b0;
x_vel_all[5] = 14'b0;
y_vel_all[5] = 14'b0;
x_vel_all[6] = 14'b0;
y_vel_all[6] = 14'b0;
x_vel_all[7] = 14'b0;
y_vel_all[7] = 14'b0;
end
else begin
clock_counter = clock_counter + 1;
if (clock_counter[22:0] == 23'b0) begin
x_pos_all[object_select] = new_x_position;
y_pos_all[object_select] = new_y_position;
x_vel_all[object_select] = new_x_velocity;
y_vel_all[object_select] = new_y_velocity;
object_select = object_select + 1;
end
end
end
wire [6:0] x_pos_object;
wire [5:0] y_pos_object;
wire [13:0] x_vel_object;
wire [13:0] y_vel_object;
assign x_pos_object = x_pos_all[object_select];
assign y_pos_object = y_pos_all[object_select];
assign x_vel_object = x_vel_all[object_select];
assign y_vel_object = y_vel_all[object_select];
wire [6:0] x_pos_0;
wire [6:0] x_pos_1;
wire [6:0] x_pos_2;
wire [6:0] x_pos_3;
wire [6:0] x_pos_4;
wire [6:0] x_pos_5;
wire [6:0] x_pos_6;
wire [6:0] x_pos_7;
assign x_pos_0 = x_pos_all[0];
assign x_pos_1 = x_pos_all[1];
assign x_pos_2 = x_pos_all[2];
assign x_pos_3 = x_pos_all[3];
assign x_pos_4 = x_pos_all[4];
assign x_pos_5 = x_pos_all[5];
assign x_pos_6 = x_pos_all[6];
assign x_pos_7 = x_pos_all[7];
wire [5:0] y_pos_0;
wire [5:0] y_pos_1;
wire [5:0] y_pos_2;
wire [5:0] y_pos_3;
wire [5:0] y_pos_4;
wire [5:0] y_pos_5;
wire [5:0] y_pos_6;
wire [5:0] y_pos_7;
assign y_pos_0 = y_pos_all[0];
assign y_pos_1 = y_pos_all[1];
assign y_pos_2 = y_pos_all[2];
assign y_pos_3 = y_pos_all[3];
assign y_pos_4 = y_pos_all[4];
assign y_pos_5 = y_pos_all[5];
assign y_pos_6 = y_pos_all[6];
assign y_pos_7 = y_pos_all[7];
wire [13:0] x_force_0;
wire [13:0] x_force_1;
wire [13:0] x_force_2;
wire [13:0] x_force_3;
wire [13:0] x_force_4;
wire [13:0] x_force_5;
wire [13:0] x_force_6;
wire [13:0] x_force_7;
wire [13:0] y_force_0;
wire [13:0] y_force_1;
wire [13:0] y_force_2;
wire [13:0] y_force_3;
wire [13:0] y_force_4;
wire [13:0] y_force_5;
wire [13:0] y_force_6;
wire [13:0] y_force_7;
force_calculator force_calculator_0 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_0),
.y_pos_other(y_pos_0),
.x_force(x_force_0),
.y_force(y_force_0)
);
force_calculator force_calculator_1 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_1),
.y_pos_other(y_pos_1),
.x_force(x_force_1),
.y_force(y_force_1)
);
force_calculator force_calculator_2 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_2),
.y_pos_other(y_pos_2),
.x_force(x_force_2),
.y_force(y_force_2)
);
force_calculator force_calculator_3 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_3),
.y_pos_other(y_pos_3),
.x_force(x_force_3),
.y_force(y_force_3)
);
force_calculator force_calculator_4 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_4),
.y_pos_other(y_pos_4),
.x_force(x_force_4),
.y_force(y_force_4)
);
force_calculator force_calculator_5 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_5),
.y_pos_other(y_pos_5),
.x_force(x_force_5),
.y_force(y_force_5)
);
force_calculator force_calculator_6 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_6),
.y_pos_other(y_pos_6),
.x_force(x_force_6),
.y_force(y_force_6)
);
force_calculator force_calculator_7 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_7),
.y_pos_other(y_pos_7),
.x_force(x_force_7),
.y_force(y_force_7)
);
wire [13:0] x_total_force;
wire [13:0] y_total_force;
assign x_total_force =
x_force_0 + x_force_1 + x_force_2 + x_force_3 +
x_force_4 + x_force_5 + x_force_6 + x_force_7;
assign y_total_force =
y_force_0 + y_force_1 + y_force_2 + y_force_3 +
y_force_4 + y_force_5 + y_force_6 + y_force_7;
wire [13:0] new_x_velocity;
wire [13:0] new_y_velocity;
assign new_x_velocity = x_vel_object+x_total_force;
assign new_y_velocity = y_vel_object+y_total_force;
reg [6:0] new_x_position;
reg [5:0] new_y_position;
always @(*) begin
if (new_x_velocity[13] == 1'b0)
new_x_position = x_pos_object + {3'b000, x_vel_object[12:10]};
else
new_x_position = x_pos_object + {2'b11, x_vel_object[13:10]};
end
always @(*) begin
if (new_y_velocity[13] == 1'b0)
new_y_position = y_pos_object + {3'b000, y_vel_object[12:10]};
else
new_y_position = y_pos_object + {2'b11, y_vel_object[13:10]};
end
reg [7:0] to_scope_reg;
assign to_scope = to_scope_reg;
always @(posedge clock) begin
if (clock_counter[22:20] == 3'b000)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b001)
to_scope_reg = {5'b0, object_select};
else if (clock_counter[22:20] == 3'b010)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b011)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b100)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b101)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b110)f
to_scope_reg = {2'b0, y_pos_object};
else if (clock_counter[22:20] == 3'b111)
to_scope_reg = {1'b0, x_pos_object};
end
endmodule | module gravity_simulator (
output [7:0] to_scope,
input clock,
input reset); |
reg [6:0] x_pos_all [7:0];
reg [5:0] y_pos_all [7:0];
reg [13:0] x_vel_all [7:0];
reg [13:0] y_vel_all [7:0];
reg [26:0] clock_counter;
reg [2:0] object_select;
always @(posedge clock) begin
if (reset) begin
clock_counter = 27'b0;
object_select = 3'b0;
x_pos_all[0] = 7'd10;
y_pos_all[0] = 6'd10;
x_pos_all[1] = 7'd10;
y_pos_all[1] = 6'd20;
x_pos_all[2] = 7'd20;
y_pos_all[2] = 6'd20;
x_pos_all[3] = 7'd20;
y_pos_all[3] = 6'd10;
x_pos_all[4] = 7'd50;
y_pos_all[4] = 6'd50;
x_pos_all[5] = 7'd30;
y_pos_all[5] = 6'd30;
x_pos_all[6] = 7'd40;
y_pos_all[6] = 6'd40;
x_pos_all[7] = 7'd40;
y_pos_all[7] = 6'd50;
x_vel_all[0] = 14'b0;
y_vel_all[0] = 14'b0;
x_vel_all[1] = 14'b0;
y_vel_all[1] = 14'b0;
x_vel_all[2] = 14'b0;
y_vel_all[2] = 14'b0;
x_vel_all[3] = 14'b0;
y_vel_all[3] = 14'b0;
x_vel_all[4] = 14'b0;
y_vel_all[4] = 14'b0;
x_vel_all[5] = 14'b0;
y_vel_all[5] = 14'b0;
x_vel_all[6] = 14'b0;
y_vel_all[6] = 14'b0;
x_vel_all[7] = 14'b0;
y_vel_all[7] = 14'b0;
end
else begin
clock_counter = clock_counter + 1;
if (clock_counter[22:0] == 23'b0) begin
x_pos_all[object_select] = new_x_position;
y_pos_all[object_select] = new_y_position;
x_vel_all[object_select] = new_x_velocity;
y_vel_all[object_select] = new_y_velocity;
object_select = object_select + 1;
end
end
end
wire [6:0] x_pos_object;
wire [5:0] y_pos_object;
wire [13:0] x_vel_object;
wire [13:0] y_vel_object;
assign x_pos_object = x_pos_all[object_select];
assign y_pos_object = y_pos_all[object_select];
assign x_vel_object = x_vel_all[object_select];
assign y_vel_object = y_vel_all[object_select];
wire [6:0] x_pos_0;
wire [6:0] x_pos_1;
wire [6:0] x_pos_2;
wire [6:0] x_pos_3;
wire [6:0] x_pos_4;
wire [6:0] x_pos_5;
wire [6:0] x_pos_6;
wire [6:0] x_pos_7;
assign x_pos_0 = x_pos_all[0];
assign x_pos_1 = x_pos_all[1];
assign x_pos_2 = x_pos_all[2];
assign x_pos_3 = x_pos_all[3];
assign x_pos_4 = x_pos_all[4];
assign x_pos_5 = x_pos_all[5];
assign x_pos_6 = x_pos_all[6];
assign x_pos_7 = x_pos_all[7];
wire [5:0] y_pos_0;
wire [5:0] y_pos_1;
wire [5:0] y_pos_2;
wire [5:0] y_pos_3;
wire [5:0] y_pos_4;
wire [5:0] y_pos_5;
wire [5:0] y_pos_6;
wire [5:0] y_pos_7;
assign y_pos_0 = y_pos_all[0];
assign y_pos_1 = y_pos_all[1];
assign y_pos_2 = y_pos_all[2];
assign y_pos_3 = y_pos_all[3];
assign y_pos_4 = y_pos_all[4];
assign y_pos_5 = y_pos_all[5];
assign y_pos_6 = y_pos_all[6];
assign y_pos_7 = y_pos_all[7];
wire [13:0] x_force_0;
wire [13:0] x_force_1;
wire [13:0] x_force_2;
wire [13:0] x_force_3;
wire [13:0] x_force_4;
wire [13:0] x_force_5;
wire [13:0] x_force_6;
wire [13:0] x_force_7;
wire [13:0] y_force_0;
wire [13:0] y_force_1;
wire [13:0] y_force_2;
wire [13:0] y_force_3;
wire [13:0] y_force_4;
wire [13:0] y_force_5;
wire [13:0] y_force_6;
wire [13:0] y_force_7;
force_calculator force_calculator_0 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_0),
.y_pos_other(y_pos_0),
.x_force(x_force_0),
.y_force(y_force_0)
);
force_calculator force_calculator_1 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_1),
.y_pos_other(y_pos_1),
.x_force(x_force_1),
.y_force(y_force_1)
);
force_calculator force_calculator_2 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_2),
.y_pos_other(y_pos_2),
.x_force(x_force_2),
.y_force(y_force_2)
);
force_calculator force_calculator_3 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_3),
.y_pos_other(y_pos_3),
.x_force(x_force_3),
.y_force(y_force_3)
);
force_calculator force_calculator_4 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_4),
.y_pos_other(y_pos_4),
.x_force(x_force_4),
.y_force(y_force_4)
);
force_calculator force_calculator_5 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_5),
.y_pos_other(y_pos_5),
.x_force(x_force_5),
.y_force(y_force_5)
);
force_calculator force_calculator_6 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_6),
.y_pos_other(y_pos_6),
.x_force(x_force_6),
.y_force(y_force_6)
);
force_calculator force_calculator_7 (
.x_pos_object(x_pos_object),
.y_pos_object(y_pos_object),
.x_pos_other(x_pos_7),
.y_pos_other(y_pos_7),
.x_force(x_force_7),
.y_force(y_force_7)
);
wire [13:0] x_total_force;
wire [13:0] y_total_force;
assign x_total_force =
x_force_0 + x_force_1 + x_force_2 + x_force_3 +
x_force_4 + x_force_5 + x_force_6 + x_force_7;
assign y_total_force =
y_force_0 + y_force_1 + y_force_2 + y_force_3 +
y_force_4 + y_force_5 + y_force_6 + y_force_7;
wire [13:0] new_x_velocity;
wire [13:0] new_y_velocity;
assign new_x_velocity = x_vel_object+x_total_force;
assign new_y_velocity = y_vel_object+y_total_force;
reg [6:0] new_x_position;
reg [5:0] new_y_position;
always @(*) begin
if (new_x_velocity[13] == 1'b0)
new_x_position = x_pos_object + {3'b000, x_vel_object[12:10]};
else
new_x_position = x_pos_object + {2'b11, x_vel_object[13:10]};
end
always @(*) begin
if (new_y_velocity[13] == 1'b0)
new_y_position = y_pos_object + {3'b000, y_vel_object[12:10]};
else
new_y_position = y_pos_object + {2'b11, y_vel_object[13:10]};
end
reg [7:0] to_scope_reg;
assign to_scope = to_scope_reg;
always @(posedge clock) begin
if (clock_counter[22:20] == 3'b000)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b001)
to_scope_reg = {5'b0, object_select};
else if (clock_counter[22:20] == 3'b010)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b011)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b100)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b101)
to_scope_reg = 8'b11111111;
else if (clock_counter[22:20] == 3'b110)f
to_scope_reg = {2'b0, y_pos_object};
else if (clock_counter[22:20] == 3'b111)
to_scope_reg = {1'b0, x_pos_object};
end
endmodule | 7 |
140,807 | data/full_repos/permissive/91855037/src/inv_calculator.v | 91,855,037 | inv_calculator.v | v | 143 | 58 | [] | [] | [] | [(1, 142)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91855037/src/inv_calculator.v:140: Bit extraction of array[10:0] requires 4 bit index, not 7 bits.\n : ... In instance inv_calculator\n output_buffer = pre_calculated[x_dist][y_dist];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91855037/src/inv_calculator.v:140: Bit extraction of array[10:0] requires 4 bit index, not 6 bits.\n : ... In instance inv_calculator\n output_buffer = pre_calculated[x_dist][y_dist];\n ^\n%Warning-WIDTH: data/full_repos/permissive/91855037/src/inv_calculator.v:137: Operator GT expects 20 bits on the LHS, but LHS\'s VARREF \'x_dist\' generates 7 bits.\n : ... In instance inv_calculator\n if ((x_dist>20\'b1011)|(y_dist>20\'b1011))\n ^\n%Warning-WIDTH: data/full_repos/permissive/91855037/src/inv_calculator.v:137: Operator GT expects 20 bits on the LHS, but LHS\'s VARREF \'y_dist\' generates 6 bits.\n : ... In instance inv_calculator\n if ((x_dist>20\'b1011)|(y_dist>20\'b1011))\n ^\n%Error: Exiting due to 4 warning(s)\n' | 309,719 | module | module inv_calculator (
input [6:0] x_dist,
input [5:0] y_dist,
output [19:0] inv_distance_cube);
reg [19:0] output_buffer;
assign inv_distance_cube = output_buffer;
wire [19:0] pre_calculated [10:0][10:0];
assign pre_calculated[0][0] = 20'b0;
assign pre_calculated[0][1] = 20'b11111111111111111111;
assign pre_calculated[0][2] = 20'b11111111111111111111;
assign pre_calculated[0][3] = 20'b111000111000111000;
assign pre_calculated[0][4] = 20'b100000000000000000;
assign pre_calculated[0][5] = 20'b10100011110101110;
assign pre_calculated[0][6] = 20'b1110001110001110;
assign pre_calculated[0][7] = 20'b1010011100101111;
assign pre_calculated[0][8] = 20'b1000000000000000;
assign pre_calculated[0][9] = 20'b110010100100010;
assign pre_calculated[0][10] = 20'b101000111101011;
assign pre_calculated[1][0] = 20'b11111111111111111111;
assign pre_calculated[1][1] = 20'b11111111111111111111;
assign pre_calculated[1][2] = 20'b1100110011001100110;
assign pre_calculated[1][3] = 20'b110011001100110011;
assign pre_calculated[1][4] = 20'b11110000111100001;
assign pre_calculated[1][5] = 20'b10011101100010011;
assign pre_calculated[1][6] = 20'b1101110101100111;
assign pre_calculated[1][7] = 20'b1010001111010111;
assign pre_calculated[1][8] = 20'b111111000000111;
assign pre_calculated[1][9] = 20'b110001111100111;
assign pre_calculated[1][10] = 20'b101000100011011;
assign pre_calculated[2][0] = 20'b10000000000000000000;
assign pre_calculated[2][1] = 20'b1100110011001100110;
assign pre_calculated[2][2] = 20'b1000000000000000000;
assign pre_calculated[2][3] = 20'b100111011000100111;
assign pre_calculated[2][4] = 20'b11001100110011001;
assign pre_calculated[2][5] = 20'b10001101001111011;
assign pre_calculated[2][6] = 20'b1100110011001100;
assign pre_calculated[2][7] = 20'b1001101010010000;
assign pre_calculated[2][8] = 20'b111100001111000;
assign pre_calculated[2][9] = 20'b110000001100000;
assign pre_calculated[2][10] = 20'b100111011000100;
assign pre_calculated[3][0] = 20'b111000111000111000;
assign pre_calculated[3][1] = 20'b110011001100110011;
assign pre_calculated[3][2] = 20'b100111011000100111;
assign pre_calculated[3][3] = 20'b11100011100011100;
assign pre_calculated[3][4] = 20'b10100011110101110;
assign pre_calculated[3][5] = 20'b1111000011110000;
assign pre_calculated[3][6] = 20'b1011011000001011;
assign pre_calculated[3][7] = 20'b1000110100111101;
assign pre_calculated[3][8] = 20'b111000000111000;
assign pre_calculated[3][9] = 20'b101101100000101;
assign pre_calculated[3][10] = 20'b100101100100111;
assign pre_calculated[4][0] = 20'b100000000000000000;
assign pre_calculated[4][1] = 20'b11110000111100001;
assign pre_calculated[4][2] = 20'b11001100110011001;
assign pre_calculated[4][3] = 20'b10100011110101110;
assign pre_calculated[4][4] = 20'b10000000000000000;
assign pre_calculated[4][5] = 20'b1100011111001110;
assign pre_calculated[4][6] = 20'b1001110110001001;
assign pre_calculated[4][7] = 20'b111111000000111;
assign pre_calculated[4][8] = 20'b110011001100110;
assign pre_calculated[4][9] = 20'b101010001110100;
assign pre_calculated[4][10] = 20'b100011010011110;
assign pre_calculated[5][0] = 20'b10100011110101110;
assign pre_calculated[5][1] = 20'b10011101100010011;
assign pre_calculated[5][2] = 20'b10001101001111011;
assign pre_calculated[5][3] = 20'b1111000011110000;
assign pre_calculated[5][4] = 20'b1100011111001110;
assign pre_calculated[5][5] = 20'b1010001111010111;
assign pre_calculated[5][6] = 20'b1000011001001011;
assign pre_calculated[5][7] = 20'b110111010110011;
assign pre_calculated[5][8] = 20'b101110000001011;
assign pre_calculated[5][9] = 20'b100110101001000;
assign pre_calculated[5][10] = 20'b100000110001001;
assign pre_calculated[6][0] = 20'b1110001110001110;
assign pre_calculated[6][1] = 20'b1101110101100111;
assign pre_calculated[6][2] = 20'b1100110011001100;
assign pre_calculated[6][3] = 20'b1011011000001011;
assign pre_calculated[6][4] = 20'b1001110110001001;
assign pre_calculated[6][5] = 20'b1000011001001011;
assign pre_calculated[6][6] = 20'b111000111000111;
assign pre_calculated[6][7] = 20'b110000001100000;
assign pre_calculated[6][8] = 20'b101000111101011;
assign pre_calculated[6][9] = 20'b100011000000100;
assign pre_calculated[6][10] = 20'b11110000111100;
assign pre_calculated[7][0] = 20'b1010011100101111;
assign pre_calculated[7][1] = 20'b1010001111010111;
assign pre_calculated[7][2] = 20'b1001101010010000;
assign pre_calculated[7][3] = 20'b1000110100111101;
assign pre_calculated[7][4] = 20'b111111000000111;
assign pre_calculated[7][5] = 20'b110111010110011;
assign pre_calculated[7][6] = 20'b110000001100000;
assign pre_calculated[7][7] = 20'b101001110010111;
assign pre_calculated[7][8] = 20'b100100001111110;
assign pre_calculated[7][9] = 20'b11111100000011;
assign pre_calculated[7][10] = 20'b11011011111010;
assign pre_calculated[8][0] = 20'b1000000000000000;
assign pre_calculated[8][1] = 20'b111111000000111;
assign pre_calculated[8][2] = 20'b111100001111000;
assign pre_calculated[8][3] = 20'b111000000111000;
assign pre_calculated[8][4] = 20'b110011001100110;
assign pre_calculated[8][5] = 20'b101110000001011;
assign pre_calculated[8][6] = 20'b101000111101011;
assign pre_calculated[8][7] = 20'b100100001111110;
assign pre_calculated[8][8] = 20'b100000000000000;
assign pre_calculated[8][9] = 20'b11100001111111;
assign pre_calculated[8][10] = 20'b11000111110011;
assign pre_calculated[9][0] = 20'b110010100100010;
assign pre_calculated[9][1] = 20'b110001111100111;
assign pre_calculated[9][2] = 20'b110000001100000;
assign pre_calculated[9][3] = 20'b101101100000101;
assign pre_calculated[9][4] = 20'b101010001110100;
assign pre_calculated[9][5] = 20'b100110101001000;
assign pre_calculated[9][6] = 20'b100011000000100;
assign pre_calculated[9][7] = 20'b11111100000011;
assign pre_calculated[9][8] = 20'b11100001111111;
assign pre_calculated[9][9] = 20'b11001010010001;
assign pre_calculated[9][10] = 20'b10110101000010;
assign pre_calculated[10][0] = 20'b101000111101011;
assign pre_calculated[10][1] = 20'b101000100011011;
assign pre_calculated[10][2] = 20'b100111011000100;
assign pre_calculated[10][3] = 20'b100101100100111;
assign pre_calculated[10][4] = 20'b100011010011110;
assign pre_calculated[10][5] = 20'b100000110001001;
assign pre_calculated[10][6] = 20'b11110000111100;
assign pre_calculated[10][7] = 20'b11011011111010;
assign pre_calculated[10][8] = 20'b11000111110011;
assign pre_calculated[10][9] = 20'b10110101000010;
assign pre_calculated[10][10] = 20'b10100011110101;
always @(*) begin
if ((x_dist>20'b1011)|(y_dist>20'b1011))
output_buffer = 20'b0;
else
output_buffer = pre_calculated[x_dist][y_dist];
end
endmodule | module inv_calculator (
input [6:0] x_dist,
input [5:0] y_dist,
output [19:0] inv_distance_cube); |
reg [19:0] output_buffer;
assign inv_distance_cube = output_buffer;
wire [19:0] pre_calculated [10:0][10:0];
assign pre_calculated[0][0] = 20'b0;
assign pre_calculated[0][1] = 20'b11111111111111111111;
assign pre_calculated[0][2] = 20'b11111111111111111111;
assign pre_calculated[0][3] = 20'b111000111000111000;
assign pre_calculated[0][4] = 20'b100000000000000000;
assign pre_calculated[0][5] = 20'b10100011110101110;
assign pre_calculated[0][6] = 20'b1110001110001110;
assign pre_calculated[0][7] = 20'b1010011100101111;
assign pre_calculated[0][8] = 20'b1000000000000000;
assign pre_calculated[0][9] = 20'b110010100100010;
assign pre_calculated[0][10] = 20'b101000111101011;
assign pre_calculated[1][0] = 20'b11111111111111111111;
assign pre_calculated[1][1] = 20'b11111111111111111111;
assign pre_calculated[1][2] = 20'b1100110011001100110;
assign pre_calculated[1][3] = 20'b110011001100110011;
assign pre_calculated[1][4] = 20'b11110000111100001;
assign pre_calculated[1][5] = 20'b10011101100010011;
assign pre_calculated[1][6] = 20'b1101110101100111;
assign pre_calculated[1][7] = 20'b1010001111010111;
assign pre_calculated[1][8] = 20'b111111000000111;
assign pre_calculated[1][9] = 20'b110001111100111;
assign pre_calculated[1][10] = 20'b101000100011011;
assign pre_calculated[2][0] = 20'b10000000000000000000;
assign pre_calculated[2][1] = 20'b1100110011001100110;
assign pre_calculated[2][2] = 20'b1000000000000000000;
assign pre_calculated[2][3] = 20'b100111011000100111;
assign pre_calculated[2][4] = 20'b11001100110011001;
assign pre_calculated[2][5] = 20'b10001101001111011;
assign pre_calculated[2][6] = 20'b1100110011001100;
assign pre_calculated[2][7] = 20'b1001101010010000;
assign pre_calculated[2][8] = 20'b111100001111000;
assign pre_calculated[2][9] = 20'b110000001100000;
assign pre_calculated[2][10] = 20'b100111011000100;
assign pre_calculated[3][0] = 20'b111000111000111000;
assign pre_calculated[3][1] = 20'b110011001100110011;
assign pre_calculated[3][2] = 20'b100111011000100111;
assign pre_calculated[3][3] = 20'b11100011100011100;
assign pre_calculated[3][4] = 20'b10100011110101110;
assign pre_calculated[3][5] = 20'b1111000011110000;
assign pre_calculated[3][6] = 20'b1011011000001011;
assign pre_calculated[3][7] = 20'b1000110100111101;
assign pre_calculated[3][8] = 20'b111000000111000;
assign pre_calculated[3][9] = 20'b101101100000101;
assign pre_calculated[3][10] = 20'b100101100100111;
assign pre_calculated[4][0] = 20'b100000000000000000;
assign pre_calculated[4][1] = 20'b11110000111100001;
assign pre_calculated[4][2] = 20'b11001100110011001;
assign pre_calculated[4][3] = 20'b10100011110101110;
assign pre_calculated[4][4] = 20'b10000000000000000;
assign pre_calculated[4][5] = 20'b1100011111001110;
assign pre_calculated[4][6] = 20'b1001110110001001;
assign pre_calculated[4][7] = 20'b111111000000111;
assign pre_calculated[4][8] = 20'b110011001100110;
assign pre_calculated[4][9] = 20'b101010001110100;
assign pre_calculated[4][10] = 20'b100011010011110;
assign pre_calculated[5][0] = 20'b10100011110101110;
assign pre_calculated[5][1] = 20'b10011101100010011;
assign pre_calculated[5][2] = 20'b10001101001111011;
assign pre_calculated[5][3] = 20'b1111000011110000;
assign pre_calculated[5][4] = 20'b1100011111001110;
assign pre_calculated[5][5] = 20'b1010001111010111;
assign pre_calculated[5][6] = 20'b1000011001001011;
assign pre_calculated[5][7] = 20'b110111010110011;
assign pre_calculated[5][8] = 20'b101110000001011;
assign pre_calculated[5][9] = 20'b100110101001000;
assign pre_calculated[5][10] = 20'b100000110001001;
assign pre_calculated[6][0] = 20'b1110001110001110;
assign pre_calculated[6][1] = 20'b1101110101100111;
assign pre_calculated[6][2] = 20'b1100110011001100;
assign pre_calculated[6][3] = 20'b1011011000001011;
assign pre_calculated[6][4] = 20'b1001110110001001;
assign pre_calculated[6][5] = 20'b1000011001001011;
assign pre_calculated[6][6] = 20'b111000111000111;
assign pre_calculated[6][7] = 20'b110000001100000;
assign pre_calculated[6][8] = 20'b101000111101011;
assign pre_calculated[6][9] = 20'b100011000000100;
assign pre_calculated[6][10] = 20'b11110000111100;
assign pre_calculated[7][0] = 20'b1010011100101111;
assign pre_calculated[7][1] = 20'b1010001111010111;
assign pre_calculated[7][2] = 20'b1001101010010000;
assign pre_calculated[7][3] = 20'b1000110100111101;
assign pre_calculated[7][4] = 20'b111111000000111;
assign pre_calculated[7][5] = 20'b110111010110011;
assign pre_calculated[7][6] = 20'b110000001100000;
assign pre_calculated[7][7] = 20'b101001110010111;
assign pre_calculated[7][8] = 20'b100100001111110;
assign pre_calculated[7][9] = 20'b11111100000011;
assign pre_calculated[7][10] = 20'b11011011111010;
assign pre_calculated[8][0] = 20'b1000000000000000;
assign pre_calculated[8][1] = 20'b111111000000111;
assign pre_calculated[8][2] = 20'b111100001111000;
assign pre_calculated[8][3] = 20'b111000000111000;
assign pre_calculated[8][4] = 20'b110011001100110;
assign pre_calculated[8][5] = 20'b101110000001011;
assign pre_calculated[8][6] = 20'b101000111101011;
assign pre_calculated[8][7] = 20'b100100001111110;
assign pre_calculated[8][8] = 20'b100000000000000;
assign pre_calculated[8][9] = 20'b11100001111111;
assign pre_calculated[8][10] = 20'b11000111110011;
assign pre_calculated[9][0] = 20'b110010100100010;
assign pre_calculated[9][1] = 20'b110001111100111;
assign pre_calculated[9][2] = 20'b110000001100000;
assign pre_calculated[9][3] = 20'b101101100000101;
assign pre_calculated[9][4] = 20'b101010001110100;
assign pre_calculated[9][5] = 20'b100110101001000;
assign pre_calculated[9][6] = 20'b100011000000100;
assign pre_calculated[9][7] = 20'b11111100000011;
assign pre_calculated[9][8] = 20'b11100001111111;
assign pre_calculated[9][9] = 20'b11001010010001;
assign pre_calculated[9][10] = 20'b10110101000010;
assign pre_calculated[10][0] = 20'b101000111101011;
assign pre_calculated[10][1] = 20'b101000100011011;
assign pre_calculated[10][2] = 20'b100111011000100;
assign pre_calculated[10][3] = 20'b100101100100111;
assign pre_calculated[10][4] = 20'b100011010011110;
assign pre_calculated[10][5] = 20'b100000110001001;
assign pre_calculated[10][6] = 20'b11110000111100;
assign pre_calculated[10][7] = 20'b11011011111010;
assign pre_calculated[10][8] = 20'b11000111110011;
assign pre_calculated[10][9] = 20'b10110101000010;
assign pre_calculated[10][10] = 20'b10100011110101;
always @(*) begin
if ((x_dist>20'b1011)|(y_dist>20'b1011))
output_buffer = 20'b0;
else
output_buffer = pre_calculated[x_dist][y_dist];
end
endmodule | 7 |
140,809 | data/full_repos/permissive/91855037/src/oscilloscope.v | 91,855,037 | oscilloscope.v | v | 75 | 52 | [] | [] | [] | [(1, 74)] | null | null | 1: b"%Error: data/full_repos/permissive/91855037/src/oscilloscope.v:28: Cannot find file containing module: 'data_port'\n data_port data_port (\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91855037/src,data/full_repos/permissive/91855037/data_port\n data/full_repos/permissive/91855037/src,data/full_repos/permissive/91855037/data_port.v\n data/full_repos/permissive/91855037/src,data/full_repos/permissive/91855037/data_port.sv\n data_port\n data_port.v\n data_port.sv\n obj_dir/data_port\n obj_dir/data_port.v\n obj_dir/data_port.sv\n%Error: Exiting due to 1 error(s)\n" | 309,721 | module | module oscilloscope (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data,
input input_pin_0,
input input_pin_1,
input input_pin_2,
input input_pin_3,
input input_pin_4,
input input_pin_5,
input input_pin_6,
input input_pin_7);
localparam STATE_SIZE = 1;
localparam IDLE = 0,
PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 1;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
data_port data_port (
.clk(clk),
.data_out(tx_data),
.input_pin_0(input_pin_0),
.input_pin_1(input_pin_1),
.input_pin_2(input_pin_2),
.input_pin_3(input_pin_3),
.input_pin_4(input_pin_4),
.input_pin_5(input_pin_5),
.input_pin_6(input_pin_6),
.input_pin_7(input_pin_7)
);
always @(*) begin
state_d = state_q;
addr_d = addr_q;
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'd0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule | module oscilloscope (
input clk,
input rst,
output [7:0] tx_data,
output reg new_tx_data,
input tx_busy,
input [7:0] rx_data,
input new_rx_data,
input input_pin_0,
input input_pin_1,
input input_pin_2,
input input_pin_3,
input input_pin_4,
input input_pin_5,
input input_pin_6,
input input_pin_7); |
localparam STATE_SIZE = 1;
localparam IDLE = 0,
PRINT_MESSAGE = 1;
localparam MESSAGE_LEN = 1;
reg [STATE_SIZE-1:0] state_d, state_q;
reg [3:0] addr_d, addr_q;
data_port data_port (
.clk(clk),
.data_out(tx_data),
.input_pin_0(input_pin_0),
.input_pin_1(input_pin_1),
.input_pin_2(input_pin_2),
.input_pin_3(input_pin_3),
.input_pin_4(input_pin_4),
.input_pin_5(input_pin_5),
.input_pin_6(input_pin_6),
.input_pin_7(input_pin_7)
);
always @(*) begin
state_d = state_q;
addr_d = addr_q;
new_tx_data = 1'b0;
case (state_q)
IDLE: begin
addr_d = 4'd0;
if (new_rx_data && rx_data == "h")
state_d = PRINT_MESSAGE;
end
PRINT_MESSAGE: begin
if (!tx_busy) begin
new_tx_data = 1'b1;
addr_d = addr_q + 1'b1;
if (addr_q == MESSAGE_LEN-1)
state_d = IDLE;
end
end
default: state_d = IDLE;
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
end else begin
state_q <= state_d;
end
addr_q <= addr_d;
end
endmodule | 7 |
140,810 | data/full_repos/permissive/91894717/001_led/led.v | 91,894,717 | led.v | v | 13 | 35 | [] | [] | [] | null | line:9: before: "(" | data/verilator_xmls/695e799e-7b6a-4e3f-ad03-8decaf83054e.xml | null | 309,725 | module | module led (led1,led2,clk,btn);
input clk;
input btn;
output led1;
output led2;
reg[24:0] count;
assign led1 = count[24];
assign led2 = btn;
always @(posedge(clk)) begin
if(btn == 0) count <= count + 1;
end
endmodule | module led (led1,led2,clk,btn); |
input clk;
input btn;
output led1;
output led2;
reg[24:0] count;
assign led1 = count[24];
assign led2 = btn;
always @(posedge(clk)) begin
if(btn == 0) count <= count + 1;
end
endmodule | 0 |
140,811 | data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v | 91,894,717 | led7seg.v | v | 67 | 47 | [] | [] | [] | null | line:31: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:38: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b00: decodev = decode(v0);\n ^~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:39: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b01: decodev = decode(v1);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:40: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b10: decodev = decode(v2);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:41: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b11: decodev = decode(v3);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n' | 309,727 | module | module LED7Seg(clk, seg, segsel, data);
output [7:0] seg;
output [3:0] segsel;
input clk;
input [15:0] data;
reg [18:0] counter;
wire [3:0] v0, v1, v2, v3;
assign v0 = data[3:0];
assign v1 = data[7:4];
assign v2 = data[11:8];
assign v3 = data[15:12];
wire [1:0] dsel = counter[18:17];
assign segsel = ~(4'b1 << dsel);
assign seg = ~decodev(dsel, v0, v1, v2, v3);
always @ (posedge clk) begin
counter = counter + 1'b1;
end
function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3);
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction
function [7:0] decode (input [3:0] n);
case (n)
4'h0: decode = 8'b00111111;
4'h1: decode = 8'b00000110;
4'h2: decode = 8'b01011011;
4'h3: decode = 8'b01001111;
4'h4: decode = 8'b01100110;
4'h5: decode = 8'b01101101;
4'h6: decode = 8'b01111101;
4'h7: decode = 8'b00000111;
4'h8: decode = 8'b01111111;
4'h9: decode = 8'b01101111;
4'hA: decode = 8'b01110111;
4'hb: decode = 8'b01111100;
4'hC: decode = 8'b00111001;
4'hd: decode = 8'b01011110;
4'hE: decode = 8'b01111001;
4'hF: decode = 8'b01110001;
endcase
endfunction
endmodule | module LED7Seg(clk, seg, segsel, data); |
output [7:0] seg;
output [3:0] segsel;
input clk;
input [15:0] data;
reg [18:0] counter;
wire [3:0] v0, v1, v2, v3;
assign v0 = data[3:0];
assign v1 = data[7:4];
assign v2 = data[11:8];
assign v3 = data[15:12];
wire [1:0] dsel = counter[18:17];
assign segsel = ~(4'b1 << dsel);
assign seg = ~decodev(dsel, v0, v1, v2, v3);
always @ (posedge clk) begin
counter = counter + 1'b1;
end
function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3);
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction
function [7:0] decode (input [3:0] n);
case (n)
4'h0: decode = 8'b00111111;
4'h1: decode = 8'b00000110;
4'h2: decode = 8'b01011011;
4'h3: decode = 8'b01001111;
4'h4: decode = 8'b01100110;
4'h5: decode = 8'b01101101;
4'h6: decode = 8'b01111101;
4'h7: decode = 8'b00000111;
4'h8: decode = 8'b01111111;
4'h9: decode = 8'b01101111;
4'hA: decode = 8'b01110111;
4'hb: decode = 8'b01111100;
4'hC: decode = 8'b00111001;
4'hd: decode = 8'b01011110;
4'hE: decode = 8'b01111001;
4'hF: decode = 8'b01110001;
endcase
endfunction
endmodule | 0 |
140,812 | data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v | 91,894,717 | led7seg.v | v | 67 | 47 | [] | [] | [] | null | line:31: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:38: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b00: decodev = decode(v0);\n ^~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:39: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b01: decodev = decode(v1);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:40: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b10: decodev = decode(v2);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:41: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b11: decodev = decode(v3);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n' | 309,727 | function | function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3);
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction | function [7:0] decodev (
input [1:0] vsel,
input [4:0] v0,
input [4:0] v1,
input [4:0] v2,
input [4:0] v3); |
case (vsel)
2'b00: decodev = decode(v0);
2'b01: decodev = decode(v1);
2'b10: decodev = decode(v2);
2'b11: decodev = decode(v3);
endcase
endfunction | 0 |
140,813 | data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v | 91,894,717 | led7seg.v | v | 67 | 47 | [] | [] | [] | null | line:31: before: "(" | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:38: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b00: decodev = decode(v0);\n ^~~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:39: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b01: decodev = decode(v1);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:40: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b10: decodev = decode(v2);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:41: Operator FUNCREF \'decode\' expects 4 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 5 bits.\n : ... In instance LED7Seg\n 2\'b11: decodev = decode(v3);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v0\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v1\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v2\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/91894717/002_1_too_fast_counter/led7seg.v:25: Operator FUNCREF \'decodev\' expects 5 bits on the Function Argument, but Function Argument\'s VARREF \'v3\' generates 4 bits.\n : ... In instance LED7Seg\n assign seg = ~decodev(dsel, v0, v1, v2, v3);\n ^~~~~~~\n%Error: Exiting due to 8 warning(s)\n' | 309,727 | function | function [7:0] decode (input [3:0] n);
case (n)
4'h0: decode = 8'b00111111;
4'h1: decode = 8'b00000110;
4'h2: decode = 8'b01011011;
4'h3: decode = 8'b01001111;
4'h4: decode = 8'b01100110;
4'h5: decode = 8'b01101101;
4'h6: decode = 8'b01111101;
4'h7: decode = 8'b00000111;
4'h8: decode = 8'b01111111;
4'h9: decode = 8'b01101111;
4'hA: decode = 8'b01110111;
4'hb: decode = 8'b01111100;
4'hC: decode = 8'b00111001;
4'hd: decode = 8'b01011110;
4'hE: decode = 8'b01111001;
4'hF: decode = 8'b01110001;
endcase
endfunction | function [7:0] decode (input [3:0] n); |
case (n)
4'h0: decode = 8'b00111111;
4'h1: decode = 8'b00000110;
4'h2: decode = 8'b01011011;
4'h3: decode = 8'b01001111;
4'h4: decode = 8'b01100110;
4'h5: decode = 8'b01101101;
4'h6: decode = 8'b01111101;
4'h7: decode = 8'b00000111;
4'h8: decode = 8'b01111111;
4'h9: decode = 8'b01101111;
4'hA: decode = 8'b01110111;
4'hb: decode = 8'b01111100;
4'hC: decode = 8'b00111001;
4'hd: decode = 8'b01011110;
4'hE: decode = 8'b01111001;
4'hF: decode = 8'b01110001;
endcase
endfunction | 0 |
140,814 | data/full_repos/permissive/91894717/002_1_too_fast_counter/RZEasyTop.v | 91,894,717 | RZEasyTop.v | v | 16 | 41 | [] | [] | [] | [(1, 16)] | null | null | 1: b"%Error: data/full_repos/permissive/91894717/002_1_too_fast_counter/RZEasyTop.v:10: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, counter);\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/002_1_too_fast_counter,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/002_1_too_fast_counter,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/002_1_too_fast_counter,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: Exiting due to 1 error(s)\n" | 309,728 | module | module RZEasyTop(clk, seg, segsel);
input clk;
output [7:0] seg;
output [3:0] segsel;
reg [15:0] counter;
wire [15:0] next_counter;
assign next_counter = counter + 1;
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
counter = next_counter;
end
endmodule | module RZEasyTop(clk, seg, segsel); |
input clk;
output [7:0] seg;
output [3:0] segsel;
reg [15:0] counter;
wire [15:0] next_counter;
assign next_counter = counter + 1;
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
counter = next_counter;
end
endmodule | 0 |
140,815 | data/full_repos/permissive/91894717/002_2_simple_counter/RZEasyTop.v | 91,894,717 | RZEasyTop.v | v | 23 | 41 | [] | [] | [] | [(1, 22)] | null | null | 1: b"%Error: data/full_repos/permissive/91894717/002_2_simple_counter/RZEasyTop.v:10: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, counter);\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/002_2_simple_counter,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/002_2_simple_counter,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/002_2_simple_counter,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: Exiting due to 1 error(s)\n" | 309,731 | module | module RZEasyTop(clk, seg, segsel);
input clk;
output [7:0] seg;
output [3:0] segsel;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
if(timeout) begin
counter = counter + 1;
timer = 0;
end
else begin
timer = timer + 1;
end
end
endmodule | module RZEasyTop(clk, seg, segsel); |
input clk;
output [7:0] seg;
output [3:0] segsel;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
if(timeout) begin
counter = counter + 1;
timer = 0;
end
else begin
timer = timer + 1;
end
end
endmodule | 0 |
140,816 | data/full_repos/permissive/91894717/003_1_updown_toggle/RZEasyTop.v | 91,894,717 | RZEasyTop.v | v | 31 | 44 | [] | [] | [] | [(1, 30)] | null | null | 1: b"%Error: data/full_repos/permissive/91894717/003_1_updown_toggle/RZEasyTop.v:13: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, counter);\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/003_1_updown_toggle,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/003_1_updown_toggle,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/003_1_updown_toggle,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: Exiting due to 1 error(s)\n" | 309,734 | module | module RZEasyTop(clk, seg, segsel, nbtn);
input clk;
input [3:0] nbtn;
output [7:0] seg;
output [3:0] segsel;
wire [3:0] btn = ~nbtn;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
LED7Seg led7(clk, seg, segsel, counter);
reg toggle = 0;
always @(posedge btn[0]) toggle = ~toggle;
always @(posedge clk) begin
if(timeout) begin
if(toggle) counter = counter + 1'd1;
else counter = counter - 1'd1;
timer = 0;
end
else begin
timer = timer + 1;
end
end
endmodule | module RZEasyTop(clk, seg, segsel, nbtn); |
input clk;
input [3:0] nbtn;
output [7:0] seg;
output [3:0] segsel;
wire [3:0] btn = ~nbtn;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
LED7Seg led7(clk, seg, segsel, counter);
reg toggle = 0;
always @(posedge btn[0]) toggle = ~toggle;
always @(posedge clk) begin
if(timeout) begin
if(toggle) counter = counter + 1'd1;
else counter = counter - 1'd1;
timer = 0;
end
else begin
timer = timer + 1;
end
end
endmodule | 0 |
140,817 | data/full_repos/permissive/91894717/004_kitchen_timer/RZEasyTop.v | 91,894,717 | RZEasyTop.v | v | 50 | 55 | [] | [] | [] | [(1, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/91894717/004_kitchen_timer/RZEasyTop.v:24: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, counter);\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/004_kitchen_timer,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/004_kitchen_timer,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/004_kitchen_timer,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: Exiting due to 1 error(s)\n" | 309,740 | module | module RZEasyTop(clk, seg, segsel, nbtn);
input clk;
input [3:0] nbtn;
output [7:0] seg;
output [3:0] segsel;
wire [3:0] btn = ~nbtn;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
reg [1:0] state = 0;
reg [1:0] next_state;
always begin
case(state)
2'd0: next_state = (btn[2] ? 2'd1 : 2'd0);
2'd1: next_state = (counter == 16'd0 ? 2'd2 : 2'd1);
default: next_state = (btn[2] ? 2'd0 : 2'd2);
endcase
end
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
state = next_state;
if(timeout) timer = 0;
else timer = timer + 1;
end
always @(posedge clk) begin
if(timeout) begin
case(state)
2'd0: begin
case(btn[1:0])
2'b01: counter = counter + 1'd1;
2'b10: counter = counter - 1'd1;
default: counter = counter;
endcase
end
2'd1: counter = counter - 1'd1;
default: counter = counter;
endcase
end
else counter = counter;
end
endmodule | module RZEasyTop(clk, seg, segsel, nbtn); |
input clk;
input [3:0] nbtn;
output [7:0] seg;
output [3:0] segsel;
wire [3:0] btn = ~nbtn;
reg [31:0] timer = 0;
wire timeout = timer > 50_000_000;
reg [15:0] counter;
reg [1:0] state = 0;
reg [1:0] next_state;
always begin
case(state)
2'd0: next_state = (btn[2] ? 2'd1 : 2'd0);
2'd1: next_state = (counter == 16'd0 ? 2'd2 : 2'd1);
default: next_state = (btn[2] ? 2'd0 : 2'd2);
endcase
end
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) begin
state = next_state;
if(timeout) timer = 0;
else timer = timer + 1;
end
always @(posedge clk) begin
if(timeout) begin
case(state)
2'd0: begin
case(btn[1:0])
2'b01: counter = counter + 1'd1;
2'b10: counter = counter - 1'd1;
default: counter = counter;
endcase
end
2'd1: counter = counter - 1'd1;
default: counter = counter;
endcase
end
else counter = counter;
end
endmodule | 0 |
140,818 | data/full_repos/permissive/91894717/006_1_blockram_test/beep.v | 91,894,717 | beep.v | v | 24 | 35 | [] | [] | [] | null | line:11: before: "&&" | data/verilator_xmls/e0bf1a01-3a0a-403a-8987-166e263b3a18.xml | null | 309,744 | module | module Beep(clk, cycle, sw, beep);
input clk;
input [31:0]cycle;
input sw;
output reg beep;
reg [31:0]count = 0;
always @ (posedge clk && sw) begin
if(count > cycle) begin
count = 0;
beep = ~beep;
end
else begin
count = count + 1;
beep = beep;
end
end
endmodule | module Beep(clk, cycle, sw, beep); |
input clk;
input [31:0]cycle;
input sw;
output reg beep;
reg [31:0]count = 0;
always @ (posedge clk && sw) begin
if(count > cycle) begin
count = 0;
beep = ~beep;
end
else begin
count = count + 1;
beep = beep;
end
end
endmodule | 0 |
140,819 | data/full_repos/permissive/91894717/006_1_blockram_test/blockram.v | 91,894,717 | blockram.v | v | 26 | 45 | [] | [] | [] | [(3, 24)] | null | data/verilator_xmls/7c2d4bab-d19e-440c-9e5f-61b4b7081a14.xml | null | 309,745 | module | module BlockRAM(clk, addr, wdata, we, data);
parameter DataWidth = 8;
parameter AddrWidth = 8;
input clk;
input [AddrWidth-1:0] addr;
input [DataWidth-1:0] wdata;
input we;
output [DataWidth-1:0] data;
reg [AddrWidth-1:0] addr_buf = 0;
reg [DataWidth-1:0] ram [2**AddrWidth-1:0];
assign data = ram[addr_buf];
always@(posedge clk) begin
addr_buf = addr;
if(we) begin
ram[addr_buf] = wdata;
end
end
endmodule | module BlockRAM(clk, addr, wdata, we, data); |
parameter DataWidth = 8;
parameter AddrWidth = 8;
input clk;
input [AddrWidth-1:0] addr;
input [DataWidth-1:0] wdata;
input we;
output [DataWidth-1:0] data;
reg [AddrWidth-1:0] addr_buf = 0;
reg [DataWidth-1:0] ram [2**AddrWidth-1:0];
assign data = ram[addr_buf];
always@(posedge clk) begin
addr_buf = addr;
if(we) begin
ram[addr_buf] = wdata;
end
end
endmodule | 0 |
140,820 | data/full_repos/permissive/91894717/006_1_blockram_test/btnlatch.v | 91,894,717 | btnlatch.v | v | 24 | 47 | [] | [] | [] | null | line:22: before: "." | null | 1: b"%Error: data/full_repos/permissive/91894717/006_1_blockram_test/btnlatch.v:21: Cannot find file containing module: 'RemoveChattering'\n RemoveChattering rmchat0(clk, in, in_nochat);\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/RemoveChattering\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/RemoveChattering.v\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/RemoveChattering.sv\n RemoveChattering\n RemoveChattering.v\n RemoveChattering.sv\n obj_dir/RemoveChattering\n obj_dir/RemoveChattering.v\n obj_dir/RemoveChattering.sv\n%Error: Exiting due to 1 error(s)\n" | 309,746 | module | module ButtonLatch(clk, in, out);
parameter PortWidth = 1;
input clk;
input [PortWidth-1:0] in;
output [PortWidth-1:0] out;
reg [PortWidth-1:0] buffer;
wire [PortWidth-1:0] in_nochat;
assign out = in_nochat & ~buffer;
always@(posedge clk) begin
buffer = in_nochat;
end
RemoveChattering rmchat0(clk, in, in_nochat);
defparam rmchat0.PortWidth = PortWidth;
endmodule | module ButtonLatch(clk, in, out); |
parameter PortWidth = 1;
input clk;
input [PortWidth-1:0] in;
output [PortWidth-1:0] out;
reg [PortWidth-1:0] buffer;
wire [PortWidth-1:0] in_nochat;
assign out = in_nochat & ~buffer;
always@(posedge clk) begin
buffer = in_nochat;
end
RemoveChattering rmchat0(clk, in, in_nochat);
defparam rmchat0.PortWidth = PortWidth;
endmodule | 0 |
140,821 | data/full_repos/permissive/91894717/006_1_blockram_test/rmchat.v | 91,894,717 | rmchat.v | v | 22 | 39 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/588beabb-5c47-4af7-a171-aa6c31eea1f7.xml | null | 309,748 | module | module RemoveChattering(clk, in, out);
parameter PortWidth = 1;
parameter CounterWidth = 16;
input clk;
input [PortWidth-1:0] in;
output reg [PortWidth-1:0] out;
reg [CounterWidth-1:0] counter = 0;
reg [PortWidth-1:0] buffer;
always@(posedge clk) begin
counter = counter + 1'd1;
if(counter == 0) begin
buffer <= in;
out <= buffer;
end
end
endmodule | module RemoveChattering(clk, in, out); |
parameter PortWidth = 1;
parameter CounterWidth = 16;
input clk;
input [PortWidth-1:0] in;
output reg [PortWidth-1:0] out;
reg [CounterWidth-1:0] counter = 0;
reg [PortWidth-1:0] buffer;
always@(posedge clk) begin
counter = counter + 1'd1;
if(counter == 0) begin
buffer <= in;
out <= buffer;
end
end
endmodule | 0 |
140,822 | data/full_repos/permissive/91894717/006_1_blockram_test/top.v | 91,894,717 | top.v | v | 51 | 55 | [] | [] | [] | null | line:46: before: "." | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91894717/006_1_blockram_test/top.v:20: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'8\'h0\' generates 8 bits.\n : ... In instance top\nreg [11:0] addr = 8\'h00;\n ^~~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/91894717/006_1_blockram_test/top.v:44: Cannot find file containing module: \'LED7Seg\'\nLED7Seg led7(clk, seg, segsel, {addr, mem_data});\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/006_1_blockram_test,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: data/full_repos/permissive/91894717/006_1_blockram_test/top.v:45: Cannot find file containing module: \'ButtonLatch\'\nButtonLatch btnlatch(clk, ~nbtn, btn_down);\n^~~~~~~~~~~\n%Error: data/full_repos/permissive/91894717/006_1_blockram_test/top.v:47: Cannot find file containing module: \'BlockRAM\'\nBlockRAM blockram(clk, addr, mem_wdata, we, mem_data);\n^~~~~~~~\n%Error: Exiting due to 3 error(s), 1 warning(s)\n' | 309,749 | module | module top(reset, clk, nled, nbtn, beep, seg, segsel);
input reset;
input clk;
output [3:0]nled;
input [3:0] nbtn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [3:0] led;
assign nled = ~led;
wire [3:0] btn_down;
wire [7:0] mem_data;
reg [7:0] mem_wdata;
reg we;
reg [11:0] addr = 8'h00;
always @(posedge clk) begin
case(btn_down[1:0])
2'b01: addr = addr + 1'd1;
2'b10: addr = addr - 1'd1;
default: addr = addr;
endcase
case(btn_down[3:2])
2'b01: begin
mem_wdata = mem_data + 1'd1;
we = 1'd1;
end
2'b10: begin
mem_wdata = mem_data - 1'd1;
we = 1'd1;
end
default: begin
we = 1'd0;
end
endcase
end
LED7Seg led7(clk, seg, segsel, {addr, mem_data});
ButtonLatch btnlatch(clk, ~nbtn, btn_down);
defparam btnlatch.PortWidth = 4;
BlockRAM blockram(clk, addr, mem_wdata, we, mem_data);
defparam blockram.AddrWidth = 12;
endmodule | module top(reset, clk, nled, nbtn, beep, seg, segsel); |
input reset;
input clk;
output [3:0]nled;
input [3:0] nbtn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [3:0] led;
assign nled = ~led;
wire [3:0] btn_down;
wire [7:0] mem_data;
reg [7:0] mem_wdata;
reg we;
reg [11:0] addr = 8'h00;
always @(posedge clk) begin
case(btn_down[1:0])
2'b01: addr = addr + 1'd1;
2'b10: addr = addr - 1'd1;
default: addr = addr;
endcase
case(btn_down[3:2])
2'b01: begin
mem_wdata = mem_data + 1'd1;
we = 1'd1;
end
2'b10: begin
mem_wdata = mem_data - 1'd1;
we = 1'd1;
end
default: begin
we = 1'd0;
end
endcase
end
LED7Seg led7(clk, seg, segsel, {addr, mem_data});
ButtonLatch btnlatch(clk, ~nbtn, btn_down);
defparam btnlatch.PortWidth = 4;
BlockRAM blockram(clk, addr, mem_wdata, we, mem_data);
defparam blockram.AddrWidth = 12;
endmodule | 0 |
140,823 | data/full_repos/permissive/91894717/006_regfile_test/top.v | 91,894,717 | top.v | v | 45 | 55 | [] | [] | [] | null | line:42: before: "." | null | 1: b"%Error: data/full_repos/permissive/91894717/006_regfile_test/top.v:40: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, {addr, memdata});\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/006_regfile_test,data/full_repos/permissive/91894717/LED7Seg\n data/full_repos/permissive/91894717/006_regfile_test,data/full_repos/permissive/91894717/LED7Seg.v\n data/full_repos/permissive/91894717/006_regfile_test,data/full_repos/permissive/91894717/LED7Seg.sv\n LED7Seg\n LED7Seg.v\n LED7Seg.sv\n obj_dir/LED7Seg\n obj_dir/LED7Seg.v\n obj_dir/LED7Seg.sv\n%Error: data/full_repos/permissive/91894717/006_regfile_test/top.v:41: Cannot find file containing module: 'ButtonLatch'\nButtonLatch btnlatch(clk, ~nbtn, btn_down);\n^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,754 | module | module top(reset, clk, nled, nbtn, beep, seg, segsel);
input reset;
input clk;
output [3:0]nled;
input [3:0] nbtn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [3:0] led;
assign nled = ~led;
wire [3:0] btn_down;
reg [7:0] addr = 8'h00;
wire [7:0] memdata = mem[addr];
reg [7:0] mem [255:0];
initial begin
$readmemh("ram.txt", mem);
end
always @(posedge clk) begin
case(btn_down[1:0])
2'b01: addr = addr + 1'd1;
2'b10: addr = addr - 1'd1;
default: addr = addr;
endcase
case(btn_down[3:2])
2'b01: mem[addr] = mem[addr] + 1'd1;
2'b10: mem[addr] = mem[addr] - 1'd1;
endcase
end
LED7Seg led7(clk, seg, segsel, {addr, memdata});
ButtonLatch btnlatch(clk, ~nbtn, btn_down);
defparam btnlatch.PortWidth = 4;
endmodule | module top(reset, clk, nled, nbtn, beep, seg, segsel); |
input reset;
input clk;
output [3:0]nled;
input [3:0] nbtn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [3:0] led;
assign nled = ~led;
wire [3:0] btn_down;
reg [7:0] addr = 8'h00;
wire [7:0] memdata = mem[addr];
reg [7:0] mem [255:0];
initial begin
$readmemh("ram.txt", mem);
end
always @(posedge clk) begin
case(btn_down[1:0])
2'b01: addr = addr + 1'd1;
2'b10: addr = addr - 1'd1;
default: addr = addr;
endcase
case(btn_down[3:2])
2'b01: mem[addr] = mem[addr] + 1'd1;
2'b10: mem[addr] = mem[addr] - 1'd1;
endcase
end
LED7Seg led7(clk, seg, segsel, {addr, memdata});
ButtonLatch btnlatch(clk, ~nbtn, btn_down);
defparam btnlatch.PortWidth = 4;
endmodule | 0 |
140,824 | data/full_repos/permissive/91894717/100_uart_send/rs232c_tb.v | 91,894,717 | rs232c_tb.v | v | 47 | 53 | [] | [] | [] | [(4, 45)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91894717/100_uart_send/rs232c_tb.v:27: Unsupported: Ignoring delay on this delayed statement.\nforever #20 clk = !clk; \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91894717/100_uart_send/rs232c_tb.v:41: Unsupported: Ignoring delay on this delayed statement.\n #(20 * wait_time * 4 + wait_time / 3) rst_n = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91894717/100_uart_send/rs232c_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #(20 * wait_time * 15) rst_n = 1;\n ^\n%Error: data/full_repos/permissive/91894717/100_uart_send/rs232c_tb.v:17: Cannot find file containing module: \'rs232c\'\nrs232c top (\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/rs232c\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/rs232c.v\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/rs232c.sv\n rs232c\n rs232c.v\n rs232c.sv\n obj_dir/rs232c\n obj_dir/rs232c.v\n obj_dir/rs232c.sv\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,755 | module | module rs232c_tb ();
parameter clock = 50_000_000;
parameter baudrate = 9600;
parameter wait_time = clock / baudrate;
reg clk = 1'b0;
reg rst_n = 1'b1;
wire tx;
reg rs232c_unit = 1'b0;
integer wait_count = 0;
rs232c top (
.clk (clk),
.rst_n (rst_n),
.tx (tx)
);
initial
begin
$display("Running testbench");
forever #20 clk = !clk;
end
always @(posedge clk) begin
if (wait_count == wait_time) begin
rs232c_unit <= !rs232c_unit;
wait_count <= 0;
end
else
wait_count <= wait_count + 1;
end
always begin
#(20 * wait_time * 4 + wait_time / 3) rst_n = 0;
#(20 * wait_time * 15) rst_n = 1;
end
endmodule | module rs232c_tb (); |
parameter clock = 50_000_000;
parameter baudrate = 9600;
parameter wait_time = clock / baudrate;
reg clk = 1'b0;
reg rst_n = 1'b1;
wire tx;
reg rs232c_unit = 1'b0;
integer wait_count = 0;
rs232c top (
.clk (clk),
.rst_n (rst_n),
.tx (tx)
);
initial
begin
$display("Running testbench");
forever #20 clk = !clk;
end
always @(posedge clk) begin
if (wait_count == wait_time) begin
rs232c_unit <= !rs232c_unit;
wait_count <= 0;
end
else
wait_count <= wait_count + 1;
end
always begin
#(20 * wait_time * 4 + wait_time / 3) rst_n = 0;
#(20 * wait_time * 15) rst_n = 1;
end
endmodule | 0 |
140,825 | data/full_repos/permissive/91894717/100_uart_send/top.v | 91,894,717 | top.v | v | 52 | 111 | [] | [] | [] | null | line:10: before: "," | null | 1: b"%Error: data/full_repos/permissive/91894717/100_uart_send/top.v:18: Cannot find file containing module: 'uart_sender'\nuart_sender #(.baudrate(9600))\n^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/uart_sender\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/uart_sender.v\n data/full_repos/permissive/91894717/100_uart_send,data/full_repos/permissive/91894717/uart_sender.sv\n uart_sender\n uart_sender.v\n uart_sender.sv\n obj_dir/uart_sender\n obj_dir/uart_sender.v\n obj_dir/uart_sender.sv\n%Error: Exiting due to 1 error(s)\n" | 309,756 | module | module top (
input clk,
output tx,
input rst_n
);
parameter message = "Hello, World!\r\n",
message_len = 15;
reg go = 1'b0,
go_next = 1'b0;
reg [8 * message_len - 1 : 0] mes_buf = message,
mes_buf_next = message;
wire [7:0] data;
wire ready;
uart_sender #(.baudrate(9600))
sender (
.clk (clk),
.go (go),
.data (data),
.tx (tx),
.ready(ready)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
go <= 0;
mes_buf <= message;
end
else begin
go <= go_next;
mes_buf <= mes_buf_next;
end
end
always @(*) begin
mes_buf_next = mes_buf;
if (ready && !go) begin
go_next = 1;
mes_buf_next = {mes_buf[8 * message_len - 9 : 0], mes_buf[8 * message_len - 1 : 8 * message_len - 8]};
end
else begin
go_next = 0;
end
end
assign data = mes_buf[8 * message_len - 1: 8 * message_len - 8];
endmodule | module top (
input clk,
output tx,
input rst_n
); |
parameter message = "Hello, World!\r\n",
message_len = 15;
reg go = 1'b0,
go_next = 1'b0;
reg [8 * message_len - 1 : 0] mes_buf = message,
mes_buf_next = message;
wire [7:0] data;
wire ready;
uart_sender #(.baudrate(9600))
sender (
.clk (clk),
.go (go),
.data (data),
.tx (tx),
.ready(ready)
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
go <= 0;
mes_buf <= message;
end
else begin
go <= go_next;
mes_buf <= mes_buf_next;
end
end
always @(*) begin
mes_buf_next = mes_buf;
if (ready && !go) begin
go_next = 1;
mes_buf_next = {mes_buf[8 * message_len - 9 : 0], mes_buf[8 * message_len - 1 : 8 * message_len - 8]};
end
else begin
go_next = 0;
end
end
assign data = mes_buf[8 * message_len - 1: 8 * message_len - 8];
endmodule | 0 |
140,826 | data/full_repos/permissive/91894717/100_uart_send/uart_sender.v | 91,894,717 | uart_sender.v | v | 63 | 55 | [] | [] | [] | null | line:18: before: "," | data/verilator_xmls/398e310a-ebd6-463c-9a17-d55bbb10b051.xml | null | 309,757 | module | module uart_sender #(
parameter clock = 50_000_000,
parameter baudrate = 9600
) (
input clk,
input go,
input [7:0] data,
output tx,
output ready
);
parameter wait_time = clock / baudrate;
parameter send_ready = 10'b0000000000,
send_start = 10'b0000000001,
send_stop = 10'b1000000000;
reg [31:0] wait_count = wait_time,
wait_count_next = wait_time;
reg [9:0] state = send_ready,
state_next = send_ready;
reg [8:0] send_buf = 9'b111111111,
send_buf_next = 9'b111111111;
always @(posedge clk) begin
state <= state_next;
wait_count <= wait_count_next;
send_buf <= send_buf_next;
end
always @(*) begin
state_next = state;
wait_count_next = wait_count;
send_buf_next = send_buf;
case (state)
send_ready: begin
if (go == 1) begin
state_next = send_start;
wait_count_next = wait_time;
send_buf_next = {data, 1'b0};
end
end
default: begin
if (wait_count == 0) begin
if (state == send_stop)
state_next = send_ready;
else
state_next = {state[8:0], 1'b0};
wait_count_next = wait_time;
send_buf_next = {1'b1, send_buf[8:1]};
end
else begin
wait_count_next = wait_count - 1;
end
end
endcase
end
assign tx = send_buf[0];
assign ready = state == send_ready;
endmodule | module uart_sender #(
parameter clock = 50_000_000,
parameter baudrate = 9600
) (
input clk,
input go,
input [7:0] data,
output tx,
output ready
); |
parameter wait_time = clock / baudrate;
parameter send_ready = 10'b0000000000,
send_start = 10'b0000000001,
send_stop = 10'b1000000000;
reg [31:0] wait_count = wait_time,
wait_count_next = wait_time;
reg [9:0] state = send_ready,
state_next = send_ready;
reg [8:0] send_buf = 9'b111111111,
send_buf_next = 9'b111111111;
always @(posedge clk) begin
state <= state_next;
wait_count <= wait_count_next;
send_buf <= send_buf_next;
end
always @(*) begin
state_next = state;
wait_count_next = wait_count;
send_buf_next = send_buf;
case (state)
send_ready: begin
if (go == 1) begin
state_next = send_start;
wait_count_next = wait_time;
send_buf_next = {data, 1'b0};
end
end
default: begin
if (wait_count == 0) begin
if (state == send_stop)
state_next = send_ready;
else
state_next = {state[8:0], 1'b0};
wait_count_next = wait_time;
send_buf_next = {1'b1, send_buf[8:1]};
end
else begin
wait_count_next = wait_count - 1;
end
end
endcase
end
assign tx = send_buf[0];
assign ready = state == send_ready;
endmodule | 0 |
140,827 | data/full_repos/permissive/91894717/RZEasyTop/RZEasyTop.v | 91,894,717 | RZEasyTop.v | v | 25 | 59 | [] | [] | [] | [(1, 25)] | null | null | 1: b"%Error: data/full_repos/permissive/91894717/RZEasyTop/RZEasyTop.v:14: Cannot find file containing module: 'Beep'\nBeep bp(clk, 32'd56818, ~btn[0], beep);\n^~~~\n ... Looked in:\n data/full_repos/permissive/91894717/RZEasyTop,data/full_repos/permissive/91894717/Beep\n data/full_repos/permissive/91894717/RZEasyTop,data/full_repos/permissive/91894717/Beep.v\n data/full_repos/permissive/91894717/RZEasyTop,data/full_repos/permissive/91894717/Beep.sv\n Beep\n Beep.v\n Beep.sv\n obj_dir/Beep\n obj_dir/Beep.v\n obj_dir/Beep.sv\n%Error: data/full_repos/permissive/91894717/RZEasyTop/RZEasyTop.v:15: Cannot find file containing module: 'LED7Seg'\nLED7Seg led7(clk, seg, segsel, counter);\n^~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,760 | module | module RZEasyTop(reset, clk, led, btn, beep, seg, segsel);
input reset;
input clk;
output [3:0]led;
input [3:0]btn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [31:0] clkcounter = 0;
reg [15:0] counter = 16'h05ec;
Beep bp(clk, 32'd56818, ~btn[0], beep);
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) clkcounter = clkcounter + 1'd1;
always @(posedge clkcounter[21]) begin
if(btn[2] && ~btn[3]) counter = counter + 1'd1;
else if(btn[3] && ~btn[2]) counter = counter - 1'd1;
else counter = counter;
end
endmodule | module RZEasyTop(reset, clk, led, btn, beep, seg, segsel); |
input reset;
input clk;
output [3:0]led;
input [3:0]btn;
output beep;
output [7:0] seg;
output [3:0] segsel;
reg [31:0] clkcounter = 0;
reg [15:0] counter = 16'h05ec;
Beep bp(clk, 32'd56818, ~btn[0], beep);
LED7Seg led7(clk, seg, segsel, counter);
always @(posedge clk) clkcounter = clkcounter + 1'd1;
always @(posedge clkcounter[21]) begin
if(btn[2] && ~btn[3]) counter = counter + 1'd1;
else if(btn[3] && ~btn[2]) counter = counter - 1'd1;
else counter = counter;
end
endmodule | 0 |
140,828 | data/full_repos/permissive/91901094/ff_calc.v | 91,901,094 | ff_calc.v | v | 131 | 89 | [] | [] | [] | [(16, 130)] | null | null | 1: b"%Error: data/full_repos/permissive/91901094/ff_calc.v:124: Duplicate declaration of signal: 'answer'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg [3:0] answer = 4'd0;\n ^~~~~~\n data/full_repos/permissive/91901094/ff_calc.v:23: ... Location of original declaration\n output [3:0] answer \n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,764 | module | module ffCalc (
input clk,
input strobe,
input [3:0] token,
output ready,
output [3:0] answer
);
parameter token_ADD = 4'hA;
parameter token_SUB = 4'hB;
parameter token_MUL = 4'hC;
parameter token_DIV = 4'hD;
parameter token_EQU = 4'hE;
parameter token_CLR = 4'hF;
parameter fsm_IDLE = 3'd0;
parameter fsm_WAIT = 3'd1;
parameter fsm_CALC = 3'd2;
parameter fsm_PUSH_NUMBER = 3'd3;
parameter fsm_EXECUTE = 3'd4;
wire rd_en;
wire shunt_yard_ready;
wire [3:0] output_queue;
ShuntingYard shunt_yard(
.clk(clk),
.rd_en(rd_en),
.wr_en(strobe),
.token(token),
.ready(shunt_yard_ready),
.output_queue(output_queue)
);
wire clear = strobe & (token_CLR==token);
wire is_equal = (token_EQU==token);
wire is_number = (output_queue < 4'hA);
wire is_finished = (token_EQU==output_queue);
reg [2:0] state = fsm_IDLE;
reg [2:0] next_state = fsm_IDLE;
always @(posedge clk) begin
if (clear) state <= fsm_IDLE;
else state <= next_state;
end
always @* begin
case (state)
fsm_IDLE : if (strobe) next_state = fsm_WAIT;
else next_state = fsm_IDLE;
fsm_WAIT : if (shunt_yard_ready) next_state = is_equal ? fsm_CALC : fsm_IDLE;
else next_state = fsm_WAIT;
fsm_CALC : if (is_number) next_state = fsm_PUSH_NUMBER;
else next_state = is_finished ? fsm_IDLE : fsm_EXECUTE;
fsm_PUSH_NUMBER : next_state = fsm_CALC;
fsm_EXECUTE : next_state = fsm_CALC;
default: next_state = fsm_IDLE;
endcase
end
assign ready = (fsm_IDLE==state);
assign rd_en = (fsm_PUSH_NUMBER==state) | (fsm_EXECUTE==state);
reg [3:0] stack[0:7];
always @(posedge clk) begin
if (fsm_PUSH_NUMBER==state) stack[stack_pointer] <= output_queue;
else if (fsm_EXECUTE==state) stack[stack_pointer-2] <= accumulator;
end
reg [2:0] stack_pointer = 3'd0;
always @(posedge clk) begin
if (clear) stack_pointer <= 3'd0;
else if (fsm_PUSH_NUMBER==state) stack_pointer <= stack_pointer + 1'd1;
else if (fsm_EXECUTE==state) stack_pointer <= stack_pointer - 1'd1;
end
reg [3:0] accumulator;
always @* begin
case (output_queue)
token_ADD : accumulator = stack[stack_pointer-2] + stack[stack_pointer-1];
token_SUB : accumulator = stack[stack_pointer-2] - stack[stack_pointer-1];
token_MUL : accumulator = stack[stack_pointer-2] * stack[stack_pointer-1];
token_DIV : accumulator = stack[stack_pointer-2] / stack[stack_pointer-1];
default : accumulator = 4'd0;
endcase
end
reg [3:0] answer = 4'd0;
always @(posedge clk) begin
if (clear) answer <= 4'd0;
else if (fsm_EXECUTE==state) answer <= accumulator;
end
endmodule | module ffCalc (
input clk,
input strobe,
input [3:0] token,
output ready,
output [3:0] answer
); |
parameter token_ADD = 4'hA;
parameter token_SUB = 4'hB;
parameter token_MUL = 4'hC;
parameter token_DIV = 4'hD;
parameter token_EQU = 4'hE;
parameter token_CLR = 4'hF;
parameter fsm_IDLE = 3'd0;
parameter fsm_WAIT = 3'd1;
parameter fsm_CALC = 3'd2;
parameter fsm_PUSH_NUMBER = 3'd3;
parameter fsm_EXECUTE = 3'd4;
wire rd_en;
wire shunt_yard_ready;
wire [3:0] output_queue;
ShuntingYard shunt_yard(
.clk(clk),
.rd_en(rd_en),
.wr_en(strobe),
.token(token),
.ready(shunt_yard_ready),
.output_queue(output_queue)
);
wire clear = strobe & (token_CLR==token);
wire is_equal = (token_EQU==token);
wire is_number = (output_queue < 4'hA);
wire is_finished = (token_EQU==output_queue);
reg [2:0] state = fsm_IDLE;
reg [2:0] next_state = fsm_IDLE;
always @(posedge clk) begin
if (clear) state <= fsm_IDLE;
else state <= next_state;
end
always @* begin
case (state)
fsm_IDLE : if (strobe) next_state = fsm_WAIT;
else next_state = fsm_IDLE;
fsm_WAIT : if (shunt_yard_ready) next_state = is_equal ? fsm_CALC : fsm_IDLE;
else next_state = fsm_WAIT;
fsm_CALC : if (is_number) next_state = fsm_PUSH_NUMBER;
else next_state = is_finished ? fsm_IDLE : fsm_EXECUTE;
fsm_PUSH_NUMBER : next_state = fsm_CALC;
fsm_EXECUTE : next_state = fsm_CALC;
default: next_state = fsm_IDLE;
endcase
end
assign ready = (fsm_IDLE==state);
assign rd_en = (fsm_PUSH_NUMBER==state) | (fsm_EXECUTE==state);
reg [3:0] stack[0:7];
always @(posedge clk) begin
if (fsm_PUSH_NUMBER==state) stack[stack_pointer] <= output_queue;
else if (fsm_EXECUTE==state) stack[stack_pointer-2] <= accumulator;
end
reg [2:0] stack_pointer = 3'd0;
always @(posedge clk) begin
if (clear) stack_pointer <= 3'd0;
else if (fsm_PUSH_NUMBER==state) stack_pointer <= stack_pointer + 1'd1;
else if (fsm_EXECUTE==state) stack_pointer <= stack_pointer - 1'd1;
end
reg [3:0] accumulator;
always @* begin
case (output_queue)
token_ADD : accumulator = stack[stack_pointer-2] + stack[stack_pointer-1];
token_SUB : accumulator = stack[stack_pointer-2] - stack[stack_pointer-1];
token_MUL : accumulator = stack[stack_pointer-2] * stack[stack_pointer-1];
token_DIV : accumulator = stack[stack_pointer-2] / stack[stack_pointer-1];
default : accumulator = 4'd0;
endcase
end
reg [3:0] answer = 4'd0;
always @(posedge clk) begin
if (clear) answer <= 4'd0;
else if (fsm_EXECUTE==state) answer <= accumulator;
end
endmodule | 0 |
140,829 | data/full_repos/permissive/91901094/ff_calc_tb.v | 91,901,094 | ff_calc_tb.v | v | 84 | 38 | [] | [] | [] | null | line:40: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:25: Unsupported: Ignoring delay on this delayed statement.\n #12 clk = 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #13 clk = 1;\n ^\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:31: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("ff_calc.lxt");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:32: Unsupported or unknown PLI call: $dumpvars\n $dumpvars;\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #100 $display("finished");\n ^\n%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n wait(!clk) #1 token = value;\n ^\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:74: Unsupported: wait statements\n wait(!clk) #1 token = value;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n wait(clk) #1 strobe = 1;\n ^\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:75: Unsupported: wait statements\n wait(clk) #1 strobe = 1;\n ^~~~\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:76: Unsupported: wait statements\n wait(!clk);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/91901094/ff_calc_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n wait(clk) #1 strobe = 0;\n ^\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:77: Unsupported: wait statements\n wait(clk) #1 strobe = 0;\n ^~~~\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:78: Unsupported: wait statements\n wait(!clk);\n ^~~~\n%Error: data/full_repos/permissive/91901094/ff_calc_tb.v:79: Unsupported: wait statements\n wait(ready);\n ^~~~\n%Error: Exiting due to 8 error(s), 6 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,765 | module | module ffCalc_tb;
reg clk;
reg strobe;
reg [3:0] token;
wire ready;
wire [3:0] answer;
ffCalc ff_calc(
.clk(clk),
.strobe(strobe),
.token(token),
.ready(ready),
.answer(answer)
);
always begin
#12 clk = 0;
#13 clk = 1;
end
initial begin
$dumpfile("ff_calc.lxt");
$dumpvars;
clk = 1;
strobe = 0;
token = 4'h0;
puttok(4'hF);
puttok(4'h3);
puttok(4'hA);
puttok(4'h4);
puttok(4'hE);
puttok(4'hF);
puttok(4'h7);
puttok(4'hB);
puttok(4'h8);
puttok(4'hD);
puttok(4'h4);
puttok(4'hE);
puttok(4'hF);
puttok(4'h3);
puttok(4'hA);
puttok(4'h4);
puttok(4'hC);
puttok(4'h2);
puttok(4'hB);
puttok(4'h1);
puttok(4'hE);
#100 $display("finished");
$finish;
end
task puttok;
input [3:0] value;
begin
wait(!clk) #1 token = value;
wait(clk) #1 strobe = 1;
wait(!clk);
wait(clk) #1 strobe = 0;
wait(!clk);
wait(ready);
end
endtask
endmodule | module ffCalc_tb; |
reg clk;
reg strobe;
reg [3:0] token;
wire ready;
wire [3:0] answer;
ffCalc ff_calc(
.clk(clk),
.strobe(strobe),
.token(token),
.ready(ready),
.answer(answer)
);
always begin
#12 clk = 0;
#13 clk = 1;
end
initial begin
$dumpfile("ff_calc.lxt");
$dumpvars;
clk = 1;
strobe = 0;
token = 4'h0;
puttok(4'hF);
puttok(4'h3);
puttok(4'hA);
puttok(4'h4);
puttok(4'hE);
puttok(4'hF);
puttok(4'h7);
puttok(4'hB);
puttok(4'h8);
puttok(4'hD);
puttok(4'h4);
puttok(4'hE);
puttok(4'hF);
puttok(4'h3);
puttok(4'hA);
puttok(4'h4);
puttok(4'hC);
puttok(4'h2);
puttok(4'hB);
puttok(4'h1);
puttok(4'hE);
#100 $display("finished");
$finish;
end
task puttok;
input [3:0] value;
begin
wait(!clk) #1 token = value;
wait(clk) #1 strobe = 1;
wait(!clk);
wait(clk) #1 strobe = 0;
wait(!clk);
wait(ready);
end
endtask
endmodule | 0 |
140,830 | data/full_repos/permissive/91901094/shunt_yard.v | 91,901,094 | shunt_yard.v | v | 135 | 130 | [] | [] | [] | [(27, 134)] | null | data/verilator_xmls/2d072a4e-e160-4534-86b7-b023118a1224.xml | null | 309,766 | module | module ShuntingYard (
input clk,
input rd_en,
input wr_en,
input [3:0] token,
output ready,
output [3:0] output_queue
);
parameter token_ADD = 4'hA;
parameter token_SUB = 4'hB;
parameter token_MUL = 4'hC;
parameter token_DIV = 4'hD;
parameter token_EQU = 4'hE;
parameter token_CLR = 4'hF;
parameter fsm_IDLE = 3'd0;
parameter fsm_PUSH_NUMBER = 3'd1;
parameter fsm_OPERATOR = 3'd2;
parameter fsm_PUSH_FUNCTION = 3'd3;
parameter fsm_POP_FUNCTION = 3'd4;
wire clear = wr_en & (token_CLR==token);
wire is_number = (token < 4'hA);
wire is_equal = (token_EQU==token);
wire pop = (stack_pointer>0) && (
(token_ADD==token) ||
(token_SUB==token) ||
((token_MUL[3:1]==token[3:1]) && (token_MUL[3:1]==stack[stack_pointer-1][3:1])) ||
(token_EQU==token)
);
reg [2:0] state = fsm_IDLE;
reg [2:0] next_state = fsm_IDLE;
always @(posedge clk) begin
if (clear) state <= fsm_IDLE;
else state <= next_state;
end
always @* begin
case (state)
fsm_IDLE :
if (wr_en) next_state = is_number ? fsm_PUSH_NUMBER : fsm_OPERATOR;
else next_state = fsm_IDLE;
fsm_PUSH_NUMBER :
next_state = fsm_IDLE;
fsm_OPERATOR :
if (pop) next_state = fsm_POP_FUNCTION;
else next_state = is_equal ? fsm_PUSH_NUMBER : fsm_PUSH_FUNCTION;
fsm_POP_FUNCTION : next_state = fsm_OPERATOR;
fsm_PUSH_FUNCTION : next_state = fsm_IDLE;
default: next_state = fsm_IDLE;
endcase
end
assign ready = (fsm_IDLE==state);
reg [3:0] queue[0:15];
always @(posedge clk) begin
if (fsm_PUSH_NUMBER==state) queue[wr_index] <= token;
else if (fsm_POP_FUNCTION==state) queue[wr_index] <= stack[stack_pointer-1];
end
reg [3:0] wr_index = 4'd0;
always @(posedge clk) begin
if (clear) wr_index <= 4'd0;
else if ((fsm_PUSH_NUMBER==state) || (fsm_POP_FUNCTION==state)) wr_index <= wr_index + 1'd1;
end
reg [3:0] rd_index = 4'd0;
always @(posedge clk) begin
if (clear) rd_index <= 4'd0;
else if (rd_en) rd_index <= rd_index + 1'd1;
end
assign output_queue = queue[rd_index];
reg [3:0] stack[0:7];
always @(posedge clk) begin
if (fsm_PUSH_FUNCTION==state) stack[stack_pointer] <= token;
end
reg [2:0] stack_pointer = 3'd0;
always @(posedge clk) begin
if (clear) stack_pointer <= 3'd0;
else if (fsm_PUSH_FUNCTION==state) stack_pointer <= stack_pointer + 1'd1;
else if (fsm_POP_FUNCTION==state) stack_pointer <= stack_pointer - 1'd1;
end
endmodule | module ShuntingYard (
input clk,
input rd_en,
input wr_en,
input [3:0] token,
output ready,
output [3:0] output_queue
); |
parameter token_ADD = 4'hA;
parameter token_SUB = 4'hB;
parameter token_MUL = 4'hC;
parameter token_DIV = 4'hD;
parameter token_EQU = 4'hE;
parameter token_CLR = 4'hF;
parameter fsm_IDLE = 3'd0;
parameter fsm_PUSH_NUMBER = 3'd1;
parameter fsm_OPERATOR = 3'd2;
parameter fsm_PUSH_FUNCTION = 3'd3;
parameter fsm_POP_FUNCTION = 3'd4;
wire clear = wr_en & (token_CLR==token);
wire is_number = (token < 4'hA);
wire is_equal = (token_EQU==token);
wire pop = (stack_pointer>0) && (
(token_ADD==token) ||
(token_SUB==token) ||
((token_MUL[3:1]==token[3:1]) && (token_MUL[3:1]==stack[stack_pointer-1][3:1])) ||
(token_EQU==token)
);
reg [2:0] state = fsm_IDLE;
reg [2:0] next_state = fsm_IDLE;
always @(posedge clk) begin
if (clear) state <= fsm_IDLE;
else state <= next_state;
end
always @* begin
case (state)
fsm_IDLE :
if (wr_en) next_state = is_number ? fsm_PUSH_NUMBER : fsm_OPERATOR;
else next_state = fsm_IDLE;
fsm_PUSH_NUMBER :
next_state = fsm_IDLE;
fsm_OPERATOR :
if (pop) next_state = fsm_POP_FUNCTION;
else next_state = is_equal ? fsm_PUSH_NUMBER : fsm_PUSH_FUNCTION;
fsm_POP_FUNCTION : next_state = fsm_OPERATOR;
fsm_PUSH_FUNCTION : next_state = fsm_IDLE;
default: next_state = fsm_IDLE;
endcase
end
assign ready = (fsm_IDLE==state);
reg [3:0] queue[0:15];
always @(posedge clk) begin
if (fsm_PUSH_NUMBER==state) queue[wr_index] <= token;
else if (fsm_POP_FUNCTION==state) queue[wr_index] <= stack[stack_pointer-1];
end
reg [3:0] wr_index = 4'd0;
always @(posedge clk) begin
if (clear) wr_index <= 4'd0;
else if ((fsm_PUSH_NUMBER==state) || (fsm_POP_FUNCTION==state)) wr_index <= wr_index + 1'd1;
end
reg [3:0] rd_index = 4'd0;
always @(posedge clk) begin
if (clear) rd_index <= 4'd0;
else if (rd_en) rd_index <= rd_index + 1'd1;
end
assign output_queue = queue[rd_index];
reg [3:0] stack[0:7];
always @(posedge clk) begin
if (fsm_PUSH_FUNCTION==state) stack[stack_pointer] <= token;
end
reg [2:0] stack_pointer = 3'd0;
always @(posedge clk) begin
if (clear) stack_pointer <= 3'd0;
else if (fsm_PUSH_FUNCTION==state) stack_pointer <= stack_pointer + 1'd1;
else if (fsm_POP_FUNCTION==state) stack_pointer <= stack_pointer - 1'd1;
end
endmodule | 0 |
140,831 | data/full_repos/permissive/91985180/counter.v | 91,985,180 | counter.v | v | 13 | 47 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/91985180/counter.v:2: Duplicate declaration of signal: 'clk'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\nwire clk;\n ^~~\n data/full_repos/permissive/91985180/counter.v:1: ... Location of original declaration\nmodule counter(input clk, output [25:0] data);\n ^~~\n%Error: data/full_repos/permissive/91985180/counter.v:5: Duplicate declaration of signal: 'data'\nreg [127:0] data = 0;\n ^~~~\n data/full_repos/permissive/91985180/counter.v:1: ... Location of original declaration\nmodule counter(input clk, output [25:0] data);\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 309,767 | module | module counter(input clk, output [25:0] data);
wire clk;
reg [127:0] data = 0;
always @(posedge clk) begin
data <= data + 1;
end
endmodule | module counter(input clk, output [25:0] data); |
wire clk;
reg [127:0] data = 0;
always @(posedge clk) begin
data <= data + 1;
end
endmodule | 0 |
140,832 | data/full_repos/permissive/91985180/div.v | 91,985,180 | div.v | v | 43 | 43 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/91985180/div.v:19: Operator CASE expects 32 or 7 bits on the Case expression, but Case expression\'s VARREF \'scaler\' generates 3 bits.\n : ... In instance div\n case (scaler)\n ^~~~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 309,768 | module | module div(clk_out,scaler,clk_in);
input wire [2:0]scaler;
input clk_in;
output clk_out;
reg clk1=0;
reg [17:0] Do4 = 191113;
reg [17:0] Re4 = 170263;
reg [17:0] Mi4 = 151687;
reg [17:0] Fa4 = 143173;
reg [17:0] Sol4 = 127553;
reg [17:0] La4 = 113637;
reg [17:0] Si4 = 101239;
reg[17:0] Do5 = 95557;
reg [17:0] N ;
reg [17:0] divcounter;
always @(posedge clk_in)
begin
case (scaler)
000:N<=Do4;
001:N<=Re4;
010:N<=Mi4;
011:N<=Fa4;
100:N<=Sol4;
101:N<=La4;
110:N<=Si4;
111:N<=Do5;
endcase
if (divcounter == N - 1)
begin
clk1 <= ~clk1;
divcounter <= 0;
end
else
divcounter <= divcounter + 1;
end
assign clk_out = clk1;
endmodule | module div(clk_out,scaler,clk_in); |
input wire [2:0]scaler;
input clk_in;
output clk_out;
reg clk1=0;
reg [17:0] Do4 = 191113;
reg [17:0] Re4 = 170263;
reg [17:0] Mi4 = 151687;
reg [17:0] Fa4 = 143173;
reg [17:0] Sol4 = 127553;
reg [17:0] La4 = 113637;
reg [17:0] Si4 = 101239;
reg[17:0] Do5 = 95557;
reg [17:0] N ;
reg [17:0] divcounter;
always @(posedge clk_in)
begin
case (scaler)
000:N<=Do4;
001:N<=Re4;
010:N<=Mi4;
011:N<=Fa4;
100:N<=Sol4;
101:N<=La4;
110:N<=Si4;
111:N<=Do5;
endcase
if (divcounter == N - 1)
begin
clk1 <= ~clk1;
divcounter <= 0;
end
else
divcounter <= divcounter + 1;
end
assign clk_out = clk1;
endmodule | 0 |
140,833 | data/full_repos/permissive/91985180/divfreq.v | 91,985,180 | divfreq.v | v | 37 | 39 | [] | [] | [] | [(1, 36)] | null | null | 1: b"%Error: data/full_repos/permissive/91985180/divfreq.v:27: Cannot find file containing module: 'div'\n div div0(notes[0],m0,clk);\n ^~~\n ... Looked in:\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/div\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/div.v\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/div.sv\n div\n div.v\n div.sv\n obj_dir/div\n obj_dir/div.v\n obj_dir/div.sv\n%Error: data/full_repos/permissive/91985180/divfreq.v:28: Cannot find file containing module: 'div'\n div div1(notes[1],m1,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:29: Cannot find file containing module: 'div'\n div div2(notes[2],m2,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:30: Cannot find file containing module: 'div'\n div div3(notes[3],m3,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:31: Cannot find file containing module: 'div'\n div div4(notes[4],m4,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:32: Cannot find file containing module: 'div'\n div div5(notes[5],m5,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:33: Cannot find file containing module: 'div'\n div div6(notes[6],m6,clk);\n ^~~\n%Error: data/full_repos/permissive/91985180/divfreq.v:34: Cannot find file containing module: 'div'\n div div7(notes[7],m7,clk);\n ^~~\n%Error: Exiting due to 8 error(s)\n" | 309,769 | module | module divfreq(freq,chord,clk);
output wire[7:0] freq;
input wire [7:0] chord;
input clk;
reg [2:0] n0=3'b000;
wire [2:0] n1=3'b001;
wire [2:0] n2=3'b010;
wire [2:0] n3=3'b011;
wire [2:0] n4=3'b100;
wire [2:0] n5=3'b101;
wire [2:0] n6=3'b110;
wire [2:0] n7=3'b111;
wire [7:0] notes;
wire[2:0] m0,m1,m2,m3,m4,m5,m6,m7;
assign m0=n0*chord[0];
assign m1=n1*chord[1];
assign m2=n2*chord[2];
assign m3=n3*chord[3];
assign m4=n4*chord[4];
assign m5=n5*chord[5];
assign m6=n6*chord[6];
assign m7=n7*chord[7];
assign notes= freq;
div div0(notes[0],m0,clk);
div div1(notes[1],m1,clk);
div div2(notes[2],m2,clk);
div div3(notes[3],m3,clk);
div div4(notes[4],m4,clk);
div div5(notes[5],m5,clk);
div div6(notes[6],m6,clk);
div div7(notes[7],m7,clk);
assign freq= notes;
endmodule | module divfreq(freq,chord,clk); |
output wire[7:0] freq;
input wire [7:0] chord;
input clk;
reg [2:0] n0=3'b000;
wire [2:0] n1=3'b001;
wire [2:0] n2=3'b010;
wire [2:0] n3=3'b011;
wire [2:0] n4=3'b100;
wire [2:0] n5=3'b101;
wire [2:0] n6=3'b110;
wire [2:0] n7=3'b111;
wire [7:0] notes;
wire[2:0] m0,m1,m2,m3,m4,m5,m6,m7;
assign m0=n0*chord[0];
assign m1=n1*chord[1];
assign m2=n2*chord[2];
assign m3=n3*chord[3];
assign m4=n4*chord[4];
assign m5=n5*chord[5];
assign m6=n6*chord[6];
assign m7=n7*chord[7];
assign notes= freq;
div div0(notes[0],m0,clk);
div div1(notes[1],m1,clk);
div div2(notes[2],m2,clk);
div div3(notes[3],m3,clk);
div div4(notes[4],m4,clk);
div div5(notes[5],m5,clk);
div div6(notes[6],m6,clk);
div div7(notes[7],m7,clk);
assign freq= notes;
endmodule | 0 |
140,834 | data/full_repos/permissive/91985180/piano.v | 91,985,180 | piano.v | v | 50 | 66 | [] | [] | [] | [(2, 49)] | null | null | 1: b'%Error: data/full_repos/permissive/91985180/piano.v:24: Cannot find file containing module: \'divfreq\'\n divfreq note0(freq,Chord,clk);\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/divfreq\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/divfreq.v\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/divfreq.sv\n divfreq\n divfreq.v\n divfreq.sv\n obj_dir/divfreq\n obj_dir/divfreq.v\n obj_dir/divfreq.sv\n%Error: data/full_repos/permissive/91985180/piano.v:26: Cannot find file containing module: \'rom\'\n rom n0(clks[0],wave0);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:27: Cannot find file containing module: \'rom\'\n rom n1(clks[1],wave1);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:28: Cannot find file containing module: \'rom\'\n rom n2(clks[2],wave2);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:29: Cannot find file containing module: \'rom\'\n rom n3(clks[3],wave3);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:30: Cannot find file containing module: \'rom\'\n rom n4(clks[4],wave4);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:31: Cannot find file containing module: \'rom\'\n rom n5(clks[5],wave5);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:32: Cannot find file containing module: \'rom\'\n rom n6(clks[6],wave6);\n ^~~\n%Error: data/full_repos/permissive/91985180/piano.v:33: Cannot find file containing module: \'rom\'\n rom n7(clks[7],wave7);\n ^~~\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the LHS, but LHS\'s VARREF \'wave0\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave1\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave2\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave3\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave4\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave5\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave6\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:34: Operator ADD expects 16 bits on the RHS, but RHS\'s VARREF \'wave7\' generates 8 bits.\n : ... In instance piano\n assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7; \n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the LHS, but LHS\'s VARREF \'t0\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t1\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t2\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t3\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t4\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t5\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t6\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:35: Operator ADD expects 4 bits on the RHS, but RHS\'s VARREF \'t7\' generates 1 bits.\n : ... In instance piano\n assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;\n ^\n%Warning-WIDTH: data/full_repos/permissive/91985180/piano.v:45: Operator COND expects 32 or 8 bits on the Conditional False, but Conditional False\'s SEL generates 1 bits.\n : ... In instance piano\n (sim==8) ? wavef[14:7]:\n ^\n%Error: Exiting due to 9 error(s), 17 warning(s)\n' | 309,770 | module | module piano(sound, t0,t1,t2,t3,t4,t5,t6,t7,clk);
output wire[7:0] sound;
input t0,t1,t2,t3,t4,t5,t6,t7,clk;
wire [7:0] Chord;
wire [7:0] freq;
wire[3:0] sim,n;
wire [7:0] wave1,wave2,wave3,wave4,wave5,wave6,wave0,wave7;
wire ci0,ci1,ci2,ci3,ci4,ci5;
wire [7:0]clks;
wire [15:0]wavef;
assign Chord[0]=t0;
assign Chord[1]=t1;
assign Chord[2]=t2;
assign Chord[3]=t3;
assign Chord[4]=t4;
assign Chord[5]=t5;
assign Chord[6]=t6;
assign Chord[7]=t7;
divfreq note0(freq,Chord,clk);
assign clks = freq;
rom n0(clks[0],wave0);
rom n1(clks[1],wave1);
rom n2(clks[2],wave2);
rom n3(clks[3],wave3);
rom n4(clks[4],wave4);
rom n5(clks[5],wave5);
rom n6(clks[6],wave6);
rom n7(clks[7],wave7);
assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7;
assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;
assign sound = (sim==0) ? 0:
(sim==1) ? wavef[7:0]:
(sim==2) ? wavef[8:1]:
(sim==3) ? wavef[9:2]:
(sim==4) ? wavef[10:3]:
(sim==5) ? wavef[11:4]:
(sim==6) ? wavef[12:5]:
(sim==7) ? wavef[13:6]:
(sim==8) ? wavef[14:7]:
wavef[15];
endmodule | module piano(sound, t0,t1,t2,t3,t4,t5,t6,t7,clk); |
output wire[7:0] sound;
input t0,t1,t2,t3,t4,t5,t6,t7,clk;
wire [7:0] Chord;
wire [7:0] freq;
wire[3:0] sim,n;
wire [7:0] wave1,wave2,wave3,wave4,wave5,wave6,wave0,wave7;
wire ci0,ci1,ci2,ci3,ci4,ci5;
wire [7:0]clks;
wire [15:0]wavef;
assign Chord[0]=t0;
assign Chord[1]=t1;
assign Chord[2]=t2;
assign Chord[3]=t3;
assign Chord[4]=t4;
assign Chord[5]=t5;
assign Chord[6]=t6;
assign Chord[7]=t7;
divfreq note0(freq,Chord,clk);
assign clks = freq;
rom n0(clks[0],wave0);
rom n1(clks[1],wave1);
rom n2(clks[2],wave2);
rom n3(clks[3],wave3);
rom n4(clks[4],wave4);
rom n5(clks[5],wave5);
rom n6(clks[6],wave6);
rom n7(clks[7],wave7);
assign wavef= wave0+wave1+wave2+wave3+wave4+wave5+wave6+wave7;
assign sim = t0 + t1 + t2 + t3 + t4 + t5 + t6 + t7;
assign sound = (sim==0) ? 0:
(sim==1) ? wavef[7:0]:
(sim==2) ? wavef[8:1]:
(sim==3) ? wavef[9:2]:
(sim==4) ? wavef[10:3]:
(sim==5) ? wavef[11:4]:
(sim==6) ? wavef[12:5]:
(sim==7) ? wavef[13:6]:
(sim==8) ? wavef[14:7]:
wavef[15];
endmodule | 0 |
140,835 | data/full_repos/permissive/91985180/rom.v | 91,985,180 | rom.v | v | 9 | 35 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/bc9df1bf-4099-42e8-bb4b-d7807d2a9005.xml | null | 309,771 | module | module rom(input clk,
output reg [7:0] addr);
always @(negedge clk)
begin
addr <= addr + 1;
end
endmodule | module rom(input clk,
output reg [7:0] addr); |
always @(negedge clk)
begin
addr <= addr + 1;
end
endmodule | 0 |
140,836 | data/full_repos/permissive/91985180/sum.v | 91,985,180 | sum.v | v | 16 | 32 | [] | [] | [] | [(2, 15)] | null | data/verilator_xmls/ab37f3a8-5e6a-42e2-bd0c-e9b61e497abc.xml | null | 309,772 | module | module sum(s,co,a,b,ci
);
output s,co;
input a,b,ci;
wire r,su,t;
xor xor1(r,a,b);
and and1(su,a,b);
xor xor2(s,r,ci);
and and2(t,r,ci);
or or1(co,su,t);
endmodule | module sum(s,co,a,b,ci
); |
output s,co;
input a,b,ci;
wire r,su,t;
xor xor1(r,a,b);
and and1(su,a,b);
xor xor2(s,r,ci);
and and2(t,r,ci);
or or1(co,su,t);
endmodule | 0 |
140,837 | data/full_repos/permissive/91985180/sumres.v | 91,985,180 | sumres.v | v | 29 | 54 | [] | [] | [] | [(1, 28)] | null | null | 1: b"%Error: data/full_repos/permissive/91985180/sumres.v:10: Cannot find file containing module: 'sum'\nsum sum1(.s(s1),.co(co1),.a(a[0]),.b(b[0]),.ci(co));\n^~~\n ... Looked in:\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/sum\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/sum.v\n data/full_repos/permissive/91985180,data/full_repos/permissive/91985180/sum.sv\n sum\n sum.v\n sum.sv\n obj_dir/sum\n obj_dir/sum.v\n obj_dir/sum.sv\n%Error: data/full_repos/permissive/91985180/sumres.v:11: Cannot find file containing module: 'sum'\nsum sum2(.s(s2),.co(co2),.a(a[1]),.b(b[1]),.ci(co1));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:12: Cannot find file containing module: 'sum'\nsum sum3(.s(s3),.co(co3),.a(a[2]),.b(b[2]),.ci(co2));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:13: Cannot find file containing module: 'sum'\nsum sum4(.s(s4),.co(co4),.a(a[3]),.b(b[3]),.ci(co3));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:14: Cannot find file containing module: 'sum'\nsum sum5(.s(s5),.co(co5),.a(a[4]),.b(b[4]),.ci(co4));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:15: Cannot find file containing module: 'sum'\nsum sum6(.s(s6),.co(co6),.a(a[5]),.b(b[5]),.ci(co5));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:16: Cannot find file containing module: 'sum'\nsum sum7(.s(s7),.co(co7),.a(a[6]),.b(b[6]),.ci(co6));\n^~~\n%Error: data/full_repos/permissive/91985180/sumres.v:17: Cannot find file containing module: 'sum'\nsum sum8(.s(s8),.co(co8),.a(a[7]),.b(b[7]),.ci(co7));\n^~~\n%Error: Exiting due to 8 error(s)\n" | 309,773 | module | module sumres(res,a,b,ci
);
output wire [7:0] res;
output ci;
input wire [7:0] a;
input wire [7:0] b;
wire co= 0;
wire co1,co2,co3,co4,co5,co6,co7,co8;
wire s1,s2,s3,s4,s5,s6,s7,s8;
sum sum1(.s(s1),.co(co1),.a(a[0]),.b(b[0]),.ci(co));
sum sum2(.s(s2),.co(co2),.a(a[1]),.b(b[1]),.ci(co1));
sum sum3(.s(s3),.co(co3),.a(a[2]),.b(b[2]),.ci(co2));
sum sum4(.s(s4),.co(co4),.a(a[3]),.b(b[3]),.ci(co3));
sum sum5(.s(s5),.co(co5),.a(a[4]),.b(b[4]),.ci(co4));
sum sum6(.s(s6),.co(co6),.a(a[5]),.b(b[5]),.ci(co5));
sum sum7(.s(s7),.co(co7),.a(a[6]),.b(b[6]),.ci(co6));
sum sum8(.s(s8),.co(co8),.a(a[7]),.b(b[7]),.ci(co7));
assign res[0]=s1;
assign res[1]=s2;
assign res[2]=s3;
assign res[3]=s4;
assign res[4]=s5;
assign res[5]=s6;
assign res[6]=s7;
assign res[7]=s8;
endmodule | module sumres(res,a,b,ci
); |
output wire [7:0] res;
output ci;
input wire [7:0] a;
input wire [7:0] b;
wire co= 0;
wire co1,co2,co3,co4,co5,co6,co7,co8;
wire s1,s2,s3,s4,s5,s6,s7,s8;
sum sum1(.s(s1),.co(co1),.a(a[0]),.b(b[0]),.ci(co));
sum sum2(.s(s2),.co(co2),.a(a[1]),.b(b[1]),.ci(co1));
sum sum3(.s(s3),.co(co3),.a(a[2]),.b(b[2]),.ci(co2));
sum sum4(.s(s4),.co(co4),.a(a[3]),.b(b[3]),.ci(co3));
sum sum5(.s(s5),.co(co5),.a(a[4]),.b(b[4]),.ci(co4));
sum sum6(.s(s6),.co(co6),.a(a[5]),.b(b[5]),.ci(co5));
sum sum7(.s(s7),.co(co7),.a(a[6]),.b(b[6]),.ci(co6));
sum sum8(.s(s8),.co(co8),.a(a[7]),.b(b[7]),.ci(co7));
assign res[0]=s1;
assign res[1]=s2;
assign res[2]=s3;
assign res[3]=s4;
assign res[4]=s5;
assign res[5]=s6;
assign res[6]=s7;
assign res[7]=s8;
endmodule | 0 |
140,839 | data/full_repos/permissive/92018771/dejitter.v | 92,018,771 | dejitter.v | v | 45 | 72 | [] | [] | [] | [(22, 44)] | null | data/verilator_xmls/8a1870ef-d977-4e3d-9eac-8e46d3efd019.xml | null | 309,775 | module | module dejitter(
input wire clk,
input wire btn,
output reg btn_out
);
reg [31:0] count = 0;
initial
btn_out = 0;
always @(posedge clk) begin
if(btn != btn_out)
count = count + 1;
else
count = 0;
if(count == 5000000) begin
btn_out = btn;
count = 0;
end
end
endmodule | module dejitter(
input wire clk,
input wire btn,
output reg btn_out
); |
reg [31:0] count = 0;
initial
btn_out = 0;
always @(posedge clk) begin
if(btn != btn_out)
count = count + 1;
else
count = 0;
if(count == 5000000) begin
btn_out = btn;
count = 0;
end
end
endmodule | 1 |
140,841 | data/full_repos/permissive/92018771/inst_execute.v | 92,018,771 | inst_execute.v | v | 303 | 72 | [] | [] | [] | [(22, 302)] | null | null | 1: b'%Error: data/full_repos/permissive/92018771/inst_execute.v:86: Cannot find file containing module: \'alu\'\nalu alu(\n^~~\n ... Looked in:\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/alu\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/alu.v\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:99: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:106: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:109: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0} & 32\'hf0000000;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:109: Unsized numbers/parameters not allowed in replications.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0} & 32\'hf0000000;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:113: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:118: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:118: Unsized numbers/parameters not allowed in replications.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:119: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 28 bits.\n : ... In instance inst_execute\n alu_b = $signed({immed, 2\'h0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:122: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:126: Unsized numbers/parameters not allowed in concatenations.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0};\n ^\n%Warning-WIDTHCONCAT: data/full_repos/permissive/92018771/inst_execute.v:126: Unsized numbers/parameters not allowed in replications.\n : ... In instance inst_execute\n alu_a = {pc_in + 1, 2\'h0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:127: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 28 bits.\n : ... In instance inst_execute\n alu_b = $signed({immed, 2\'h0});\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:130: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:135: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 26 bits.\n : ... In instance inst_execute\n alu_b = $signed(immed);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:138: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:143: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance inst_execute\n alu_b = $unsigned(immed[15:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:146: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:151: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 26 bits.\n : ... In instance inst_execute\n alu_b = $signed(immed);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:154: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:159: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance inst_execute\n alu_b = $unsigned(immed[15:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:162: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:167: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance inst_execute\n alu_b = $unsigned(immed[15:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:170: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:175: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance inst_execute\n alu_b = $unsigned(immed[15:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:178: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:183: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 16 bits.\n : ... In instance inst_execute\n alu_b = $unsigned(immed[15:0]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:186: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:194: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:199: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 26 bits.\n : ... In instance inst_execute\n alu_b = $signed(immed);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:208: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 26 bits.\n : ... In instance inst_execute\n alu_b = $signed(immed);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:220: Operator ASSIGN expects 30 bits on the Assign RHS, but Assign RHS\'s CONST \'32\'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance inst_execute\n mem_addr = 32\'hzzzzzzzz; mem_din = 32\'hzzzzzzzz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:248: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'pc_in\' generates 30 bits.\n : ... In instance inst_execute\n rd_out = 5\'h1f; rd_val = (pc_in << 2) + 8;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/92018771/inst_execute.v:289: Operator SHIFTL expects 32 bits on the LHS, but LHS\'s VARREF \'pc_in\' generates 30 bits.\n : ... In instance inst_execute\n rd_out = 5\'h1f; rd_val = (pc_in << 2) + 8;\n ^~\n%Error: Exiting due to 1 error(s), 33 warning(s)\n' | 309,777 | module | module inst_execute(
input wire clk,
input wire rst,
input wire [31:2] pc_in,
input wire [31:0] inst,
input wire [5:0] opcode,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] rd,
input wire [4:0] shamt,
input wire [5:0] funct,
input wire [25:0] immed,
output wire [4:0] reg_addr_a,
input wire [31:0] reg_dout_a,
output wire [4:0] reg_addr_b,
input wire [31:0] reg_dout_b,
output reg [31:2] mem_addr,
output reg [31:0] mem_din,
output reg mem_en,
output reg mem_we,
input wire [4:0] mem_rd,
input wire [31:0] mem_rd_val,
output reg [31:2] pc_out,
output reg [31:0] inst_out,
output reg jump,
output reg [31:2] jump_pc,
output reg load,
output reg store,
output reg [4:0] rd_out,
output reg [31:0] rd_val
);
initial begin
pc_out = 0; inst_out = 32'hzzzzzzzz;
mem_addr = 30'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
end
reg [4:0] last_rd = 0;
reg [31:0] last_rd_val = 0;
assign reg_addr_a = rs;
assign reg_addr_b = opcode == 6'h00 ? rt : rd;
wire [31:0] reg_data_a =
reg_addr_a == last_rd ? last_rd_val :
reg_addr_a == mem_rd ? mem_rd_val : reg_dout_a;
wire [31:0] reg_data_b =
reg_addr_b == last_rd ? last_rd_val :
reg_addr_b == mem_rd ? mem_rd_val : reg_dout_b;
reg [31:0] alu_a;
reg [31:0] alu_b;
reg [4:0] alu_shamt;
reg [5:0] alu_op;
wire [31:0] alu_out;
alu alu(
.a(alu_a), .b(alu_b), .shamt(alu_shamt),
.alu_op(alu_op), .out(alu_out)
);
reg [1:0] flush_counter = 0;
always @(*) begin
if(flush_counter == 1) begin
alu_a = 0;
alu_b = 0;
alu_shamt = 0;
alu_op = 0;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else if(opcode == 6'h00) begin
alu_a = reg_data_a;
alu_b = reg_data_b;
alu_shamt = shamt;
alu_op = funct;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else if(opcode == 6'h02 || opcode == 6'h03) begin
alu_a = {pc_in + 1, 2'h0} & 32'hf0000000;
alu_b = {4'h0, immed, 2'h0};
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else
case(opcode)
6'h04: begin
alu_a = {pc_in + 1, 2'h0};
alu_b = $signed({immed, 2'h0});
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h05: begin
alu_a = {pc_in + 1, 2'h0};
alu_b = $signed({immed, 2'h0});
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h08: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h09: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0a: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h2a;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0b: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h2b;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0c: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h24;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0d: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0e: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h26;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0f: begin
alu_a = 0;
alu_b = {immed[15:0], 16'h0000};
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h23: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = alu_out[31:2];
mem_din = 32'hzzzzzzzz;
mem_en = 1; mem_we = 0;
end
6'h2b: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = alu_out[31:2];
mem_din = reg_data_b;
mem_en = 1; mem_we = 1;
end
default: begin
alu_a = 32'hzzzzzzzz;
alu_b = 32'hzzzzzzzz;
alu_shamt = 5'hxx;
alu_op = 6'hxx;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
endcase
end
always @(posedge clk, posedge rst) begin
if(rst) begin
pc_out = 0; inst_out = 32'hzzzzzzzz;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 0;
end else if(flush_counter == 1) begin
pc_out = pc_in; inst_out = 32'h00000000;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 0;
end else begin
flush_counter = flush_counter == 0 ? 0 : flush_counter - 1;
if(opcode == 6'h02 || opcode == 6'h03) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = alu_out[31:2];
load = 0; store = 0;
if(opcode == 6'h03) begin
rd_out = 5'h1f; rd_val = (pc_in << 2) + 8;
end else begin
rd_out = 0; rd_val = 0;
end
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
flush_counter = 2;
end else if(opcode == 6'h04 || opcode == 6'h05) begin
pc_out = pc_in; inst_out = inst;
if(opcode == 6'h04)
jump = reg_data_a == reg_data_b;
else
jump = reg_data_a != reg_data_b;
jump_pc = alu_out[31:2];
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
if(jump)
flush_counter = 2;
end else if(opcode == 6'h23) begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 1; store = 0;
rd_out = rd; rd_val = reg_data_b;
last_rd = 0; last_rd_val = 0;
end else if(opcode == 6'h2b) begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 0; store = 1;
rd_out = rd; rd_val = reg_data_b;
last_rd = 0; last_rd_val = 0;
end else if(opcode == 6'h00 && funct == 6'h08) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = reg_data_a[31:2];
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 2;
end else if(opcode == 6'h00 && funct == 6'h09) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = reg_data_a[31:2];
load = 0; store = 0;
rd_out = 5'h1f; rd_val = (pc_in << 2) + 8;
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
flush_counter = 2;
end else begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = rd; rd_val = alu_out;
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
end
end
end
endmodule | module inst_execute(
input wire clk,
input wire rst,
input wire [31:2] pc_in,
input wire [31:0] inst,
input wire [5:0] opcode,
input wire [4:0] rs,
input wire [4:0] rt,
input wire [4:0] rd,
input wire [4:0] shamt,
input wire [5:0] funct,
input wire [25:0] immed,
output wire [4:0] reg_addr_a,
input wire [31:0] reg_dout_a,
output wire [4:0] reg_addr_b,
input wire [31:0] reg_dout_b,
output reg [31:2] mem_addr,
output reg [31:0] mem_din,
output reg mem_en,
output reg mem_we,
input wire [4:0] mem_rd,
input wire [31:0] mem_rd_val,
output reg [31:2] pc_out,
output reg [31:0] inst_out,
output reg jump,
output reg [31:2] jump_pc,
output reg load,
output reg store,
output reg [4:0] rd_out,
output reg [31:0] rd_val
); |
initial begin
pc_out = 0; inst_out = 32'hzzzzzzzz;
mem_addr = 30'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
end
reg [4:0] last_rd = 0;
reg [31:0] last_rd_val = 0;
assign reg_addr_a = rs;
assign reg_addr_b = opcode == 6'h00 ? rt : rd;
wire [31:0] reg_data_a =
reg_addr_a == last_rd ? last_rd_val :
reg_addr_a == mem_rd ? mem_rd_val : reg_dout_a;
wire [31:0] reg_data_b =
reg_addr_b == last_rd ? last_rd_val :
reg_addr_b == mem_rd ? mem_rd_val : reg_dout_b;
reg [31:0] alu_a;
reg [31:0] alu_b;
reg [4:0] alu_shamt;
reg [5:0] alu_op;
wire [31:0] alu_out;
alu alu(
.a(alu_a), .b(alu_b), .shamt(alu_shamt),
.alu_op(alu_op), .out(alu_out)
);
reg [1:0] flush_counter = 0;
always @(*) begin
if(flush_counter == 1) begin
alu_a = 0;
alu_b = 0;
alu_shamt = 0;
alu_op = 0;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else if(opcode == 6'h00) begin
alu_a = reg_data_a;
alu_b = reg_data_b;
alu_shamt = shamt;
alu_op = funct;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else if(opcode == 6'h02 || opcode == 6'h03) begin
alu_a = {pc_in + 1, 2'h0} & 32'hf0000000;
alu_b = {4'h0, immed, 2'h0};
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end else
case(opcode)
6'h04: begin
alu_a = {pc_in + 1, 2'h0};
alu_b = $signed({immed, 2'h0});
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h05: begin
alu_a = {pc_in + 1, 2'h0};
alu_b = $signed({immed, 2'h0});
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h08: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h20;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h09: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0a: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h2a;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0b: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h2b;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0c: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h24;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0d: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0e: begin
alu_a = reg_data_a;
alu_b = $unsigned(immed[15:0]);
alu_shamt = 0;
alu_op = 6'h26;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h0f: begin
alu_a = 0;
alu_b = {immed[15:0], 16'h0000};
alu_shamt = 0;
alu_op = 6'h25;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
6'h23: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = alu_out[31:2];
mem_din = 32'hzzzzzzzz;
mem_en = 1; mem_we = 0;
end
6'h2b: begin
alu_a = reg_data_a;
alu_b = $signed(immed);
alu_shamt = 0;
alu_op = 6'h21;
mem_addr = alu_out[31:2];
mem_din = reg_data_b;
mem_en = 1; mem_we = 1;
end
default: begin
alu_a = 32'hzzzzzzzz;
alu_b = 32'hzzzzzzzz;
alu_shamt = 5'hxx;
alu_op = 6'hxx;
mem_addr = 32'hzzzzzzzz; mem_din = 32'hzzzzzzzz;
mem_en = 0; mem_we = 0;
end
endcase
end
always @(posedge clk, posedge rst) begin
if(rst) begin
pc_out = 0; inst_out = 32'hzzzzzzzz;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 0;
end else if(flush_counter == 1) begin
pc_out = pc_in; inst_out = 32'h00000000;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 0;
end else begin
flush_counter = flush_counter == 0 ? 0 : flush_counter - 1;
if(opcode == 6'h02 || opcode == 6'h03) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = alu_out[31:2];
load = 0; store = 0;
if(opcode == 6'h03) begin
rd_out = 5'h1f; rd_val = (pc_in << 2) + 8;
end else begin
rd_out = 0; rd_val = 0;
end
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
flush_counter = 2;
end else if(opcode == 6'h04 || opcode == 6'h05) begin
pc_out = pc_in; inst_out = inst;
if(opcode == 6'h04)
jump = reg_data_a == reg_data_b;
else
jump = reg_data_a != reg_data_b;
jump_pc = alu_out[31:2];
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
if(jump)
flush_counter = 2;
end else if(opcode == 6'h23) begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 1; store = 0;
rd_out = rd; rd_val = reg_data_b;
last_rd = 0; last_rd_val = 0;
end else if(opcode == 6'h2b) begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 0; store = 1;
rd_out = rd; rd_val = reg_data_b;
last_rd = 0; last_rd_val = 0;
end else if(opcode == 6'h00 && funct == 6'h08) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = reg_data_a[31:2];
load = 0; store = 0;
rd_out = 0; rd_val = 0;
last_rd = 0; last_rd_val = 0;
flush_counter = 2;
end else if(opcode == 6'h00 && funct == 6'h09) begin
pc_out = pc_in; inst_out = inst;
jump = 1; jump_pc = reg_data_a[31:2];
load = 0; store = 0;
rd_out = 5'h1f; rd_val = (pc_in << 2) + 8;
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
flush_counter = 2;
end else begin
pc_out = pc_in; inst_out = inst;
jump = 0; jump_pc = 0;
load = 0; store = 0;
rd_out = rd; rd_val = alu_out;
last_rd = rd_out; last_rd_val = rd_out != 0 ? rd_val : 0;
end
end
end
endmodule | 1 |
140,842 | data/full_repos/permissive/92018771/inst_fetch.v | 92,018,771 | inst_fetch.v | v | 61 | 72 | [] | [] | [] | [(22, 60)] | null | data/verilator_xmls/2219b785-4a42-417d-b3f0-0fd878889579.xml | null | 309,778 | module | module inst_fetch(
input wire clk,
input wire rst,
output wire [31:2] mem_addr,
input wire [31:0] mem_dout,
output wire mem_en,
input wire stall,
input wire jump,
input wire [31:2] jump_pc,
output wire [31:0] inst,
output reg [31:2] pc
);
reg ready = 0;
reg [31:2] next_pc = 0;
assign mem_addr = jump ? jump_pc : next_pc;
assign mem_en = 1;
assign inst = ready ? mem_dout : 0;
initial begin
pc = 0;
end
always @(posedge clk, posedge rst)
if(rst) begin
pc = 0;
next_pc = 0;
ready = 0;
end else begin
pc = mem_addr;
next_pc = pc + 1;
ready = 1;
end
endmodule | module inst_fetch(
input wire clk,
input wire rst,
output wire [31:2] mem_addr,
input wire [31:0] mem_dout,
output wire mem_en,
input wire stall,
input wire jump,
input wire [31:2] jump_pc,
output wire [31:0] inst,
output reg [31:2] pc
); |
reg ready = 0;
reg [31:2] next_pc = 0;
assign mem_addr = jump ? jump_pc : next_pc;
assign mem_en = 1;
assign inst = ready ? mem_dout : 0;
initial begin
pc = 0;
end
always @(posedge clk, posedge rst)
if(rst) begin
pc = 0;
next_pc = 0;
ready = 0;
end else begin
pc = mem_addr;
next_pc = pc + 1;
ready = 1;
end
endmodule | 1 |
140,844 | data/full_repos/permissive/92018771/inst_writeback.v | 92,018,771 | inst_writeback.v | v | 55 | 72 | [] | [] | [] | [(22, 54)] | null | data/verilator_xmls/f53cd73f-1f5d-40e6-84d0-9044d7ee29a6.xml | null | 309,780 | module | module inst_writeback(
input wire clk,
input wire rst,
input wire [31:2] pc_in,
input wire [31:0] inst,
input wire [4:0] rd,
input wire [31:0] rd_val,
output wire [4:0] reg_addr,
output wire [31:0] reg_din,
output wire reg_we,
output reg [31:2] pc_out,
output reg [31:0] inst_out
);
initial begin
pc_out = 0; inst_out = 32'hxxxxxxxx;
end
assign reg_addr = rd;
assign reg_din = rd_val;
assign reg_we = rd != 5'h00;
always @(posedge clk, posedge rst)
if(rst) begin
pc_out = 0; inst_out = 32'hxxxxxxxx;
end else begin
pc_out = pc_in; inst_out = inst;
end
endmodule | module inst_writeback(
input wire clk,
input wire rst,
input wire [31:2] pc_in,
input wire [31:0] inst,
input wire [4:0] rd,
input wire [31:0] rd_val,
output wire [4:0] reg_addr,
output wire [31:0] reg_din,
output wire reg_we,
output reg [31:2] pc_out,
output reg [31:0] inst_out
); |
initial begin
pc_out = 0; inst_out = 32'hxxxxxxxx;
end
assign reg_addr = rd;
assign reg_din = rd_val;
assign reg_we = rd != 5'h00;
always @(posedge clk, posedge rst)
if(rst) begin
pc_out = 0; inst_out = 32'hxxxxxxxx;
end else begin
pc_out = pc_in; inst_out = inst;
end
endmodule | 1 |
140,845 | data/full_repos/permissive/92018771/led_drv.v | 92,018,771 | led_drv.v | v | 71 | 72 | [] | [] | [] | [(22, 70)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92018771/led_drv.v:35: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s SEL generates 2 bits.\n : ... In instance led_drv\nwire [2:0] digit_idx = clk_div[19:18];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 309,781 | module | module led_drv(
input wire clk,
input wire [15:0] value,
output reg [7:0] digit_led,
output wire [3:0] digit_sel
);
reg [19:0] clk_div;
initial
clk_div = 0;
always @(posedge clk)
clk_div = clk_div + 1;
wire [2:0] digit_idx = clk_div[19:18];
reg [3:0] digit;
always @(posedge clk) begin
case (digit_idx)
3: digit = value[15:12];
2: digit = value[11:8];
1: digit = value[7:4];
0: digit = value[3:0];
endcase
case (digit)
4'h0: digit_led = 8'b00000011;
4'h1: digit_led = 8'b10011111;
4'h2: digit_led = 8'b00100101;
4'h3: digit_led = 8'b00001101;
4'h4: digit_led = 8'b10011001;
4'h5: digit_led = 8'b01001001;
4'h6: digit_led = 8'b01000001;
4'h7: digit_led = 8'b00011111;
4'h8: digit_led = 8'b00000001;
4'h9: digit_led = 8'b00001001;
4'ha: digit_led = 8'b00010001;
4'hb: digit_led = 8'b11000001;
4'hc: digit_led = 8'b01100011;
4'hd: digit_led = 8'b10000101;
4'he: digit_led = 8'b01100001;
4'hf: digit_led = 8'b01110001;
endcase
end
assign digit_sel[3] = digit_idx != 0;
assign digit_sel[2] = digit_idx != 1;
assign digit_sel[1] = digit_idx != 2;
assign digit_sel[0] = digit_idx != 3;
endmodule | module led_drv(
input wire clk,
input wire [15:0] value,
output reg [7:0] digit_led,
output wire [3:0] digit_sel
); |
reg [19:0] clk_div;
initial
clk_div = 0;
always @(posedge clk)
clk_div = clk_div + 1;
wire [2:0] digit_idx = clk_div[19:18];
reg [3:0] digit;
always @(posedge clk) begin
case (digit_idx)
3: digit = value[15:12];
2: digit = value[11:8];
1: digit = value[7:4];
0: digit = value[3:0];
endcase
case (digit)
4'h0: digit_led = 8'b00000011;
4'h1: digit_led = 8'b10011111;
4'h2: digit_led = 8'b00100101;
4'h3: digit_led = 8'b00001101;
4'h4: digit_led = 8'b10011001;
4'h5: digit_led = 8'b01001001;
4'h6: digit_led = 8'b01000001;
4'h7: digit_led = 8'b00011111;
4'h8: digit_led = 8'b00000001;
4'h9: digit_led = 8'b00001001;
4'ha: digit_led = 8'b00010001;
4'hb: digit_led = 8'b11000001;
4'hc: digit_led = 8'b01100011;
4'hd: digit_led = 8'b10000101;
4'he: digit_led = 8'b01100001;
4'hf: digit_led = 8'b01110001;
endcase
end
assign digit_sel[3] = digit_idx != 0;
assign digit_sel[2] = digit_idx != 1;
assign digit_sel[1] = digit_idx != 2;
assign digit_sel[0] = digit_idx != 3;
endmodule | 1 |
140,849 | data/full_repos/permissive/92018771/top_bench.v | 92,018,771 | top_bench.v | v | 63 | 72 | [] | [] | [] | null | line:53: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92018771/top_bench.v:50: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92018771/top_bench.v:56: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n%Error: data/full_repos/permissive/92018771/top_bench.v:34: Cannot find file containing module: \'top\'\n top uut (\n ^~~\n ... Looked in:\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/top\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/top.v\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/top.sv\n top\n top.v\n top.sv\n obj_dir/top\n obj_dir/top.v\n obj_dir/top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,785 | module | module top_bench;
reg clk;
reg gclk;
reg rst;
reg [7:0] led_sel;
wire [11:0] led;
top uut (
.clk(clk),
.gclk(gclk),
.rst(rst),
.led_sel(led_sel),
.led(led)
);
initial begin
clk = 0;
gclk = 0;
rst = 0;
led_sel = 0;
#100;
repeat(500) begin
clk = ~clk;
gclk = ~gclk;
#100;
end
end
endmodule | module top_bench; |
reg clk;
reg gclk;
reg rst;
reg [7:0] led_sel;
wire [11:0] led;
top uut (
.clk(clk),
.gclk(gclk),
.rst(rst),
.led_sel(led_sel),
.led(led)
);
initial begin
clk = 0;
gclk = 0;
rst = 0;
led_sel = 0;
#100;
repeat(500) begin
clk = ~clk;
gclk = ~gclk;
#100;
end
end
endmodule | 1 |
140,850 | data/full_repos/permissive/92018771/top_impl.v | 92,018,771 | top_impl.v | v | 42 | 72 | [] | [] | [] | [(22, 41)] | null | null | 1: b"%Error: data/full_repos/permissive/92018771/top_impl.v:31: Cannot find file containing module: 'dejitter'\ndejitter dejitter(\n^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/dejitter\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/dejitter.v\n data/full_repos/permissive/92018771,data/full_repos/permissive/92018771/dejitter.sv\n dejitter\n dejitter.v\n dejitter.sv\n obj_dir/dejitter\n obj_dir/dejitter.v\n obj_dir/dejitter.sv\n%Error: data/full_repos/permissive/92018771/top_impl.v:36: Cannot find file containing module: 'top'\ntop top(\n^~~\n%Error: Exiting due to 2 error(s)\n" | 309,786 | module | module top_impl(
input wire btn,
input wire gclk,
input wire rst,
input wire [7:0] led_sel,
output wire [11:0] led
);
wire clk;
dejitter dejitter(
.clk(gclk), .btn(btn),
.btn_out(clk)
);
top top(
.clk(clk), .gclk(gclk), .rst(rst),
.led_sel(led_sel), .led(led)
);
endmodule | module top_impl(
input wire btn,
input wire gclk,
input wire rst,
input wire [7:0] led_sel,
output wire [11:0] led
); |
wire clk;
dejitter dejitter(
.clk(gclk), .btn(btn),
.btn_out(clk)
);
top top(
.clk(clk), .gclk(gclk), .rst(rst),
.led_sel(led_sel), .led(led)
);
endmodule | 1 |
140,851 | data/full_repos/permissive/92094463/clockDiv.v | 92,094,463 | clockDiv.v | v | 21 | 102 | [] | [] | [] | [(6, 20)] | null | data/verilator_xmls/a21b6849-4e0e-4bb0-a7c2-d0db0410ac68.xml | null | 309,787 | module | module clockDiv(
input clk,
output out
);
parameter scale = 5;
reg [scale:0] r;
initial r = 0;
assign out = r[scale];
always @ (posedge clk) begin
r = r + 1;
end
endmodule | module clockDiv(
input clk,
output out
); |
parameter scale = 5;
reg [scale:0] r;
initial r = 0;
assign out = r[scale];
always @ (posedge clk) begin
r = r + 1;
end
endmodule | 1 |
140,852 | data/full_repos/permissive/92094463/counter.v | 92,094,463 | counter.v | v | 40 | 102 | [] | [] | [] | [(19, 39)] | null | data/verilator_xmls/e8a416eb-c3a5-49a4-bd7b-33cdf2b61b3e.xml | null | 309,788 | module | module counter(
clk,
reset,
out,
overflow
);
input clk, reset;
parameter bitSize = 8;
output reg [bitSize-1:0] out = 0;
output wire overflow;
parameter [bitSize-1:0] clearVal = {bitSize{1'b1}};
assign overflow = &out;
always @ (posedge clk) begin
if (reset) out = 0;
else if (out == clearVal) out = 0;
else out = out + 1;
end
endmodule | module counter(
clk,
reset,
out,
overflow
); |
input clk, reset;
parameter bitSize = 8;
output reg [bitSize-1:0] out = 0;
output wire overflow;
parameter [bitSize-1:0] clearVal = {bitSize{1'b1}};
assign overflow = &out;
always @ (posedge clk) begin
if (reset) out = 0;
else if (out == clearVal) out = 0;
else out = out + 1;
end
endmodule | 1 |
140,853 | data/full_repos/permissive/92094463/crcGenerator.v | 92,094,463 | crcGenerator.v | v | 47 | 102 | [] | [] | [] | null | line:79: before: "x" | data/verilator_xmls/d06653b1-128b-4aed-a381-619f0b4fca42.xml | null | 309,789 | module | module crcGenerator
#(parameter LEN = 7)(
input inputBit,
input clk,
input clear,
input enable,
input [LEN:0] generator,
output reg [LEN - 1:0] crc
);
wire invert;
assign invert = inputBit ^ crc[LEN - 1];
integer _i = 0;
always @ (posedge clk) begin
if (clear) begin
crc = 0;
end
else if (enable) begin
for (_i = LEN - 1; _i > 0; _i = _i - 1) begin
crc[_i] = crc[_i - 1] ^ (invert & generator[_i]);
end
crc[0] = invert;
end
end
endmodule | module crcGenerator
#(parameter LEN = 7)(
input inputBit,
input clk,
input clear,
input enable,
input [LEN:0] generator,
output reg [LEN - 1:0] crc
); |
wire invert;
assign invert = inputBit ^ crc[LEN - 1];
integer _i = 0;
always @ (posedge clk) begin
if (clear) begin
crc = 0;
end
else if (enable) begin
for (_i = LEN - 1; _i > 0; _i = _i - 1) begin
crc[_i] = crc[_i - 1] ^ (invert & generator[_i]);
end
crc[0] = invert;
end
end
endmodule | 1 |
140,855 | data/full_repos/permissive/92094463/main.v | 92,094,463 | main.v | v | 691 | 120 | [] | [] | [] | null | line:116: before: "," | null | 1: b'%Error: data/full_repos/permissive/92094463/main.v:106: Cannot find file containing module: \'spiCommMaster\'\nspiCommMaster CMM (cpuClock, CM_EN, CM_RST, cmSpiClkEn, CMClkBS,\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92094463,data/full_repos/permissive/92094463/spiCommMaster\n data/full_repos/permissive/92094463,data/full_repos/permissive/92094463/spiCommMaster.v\n data/full_repos/permissive/92094463,data/full_repos/permissive/92094463/spiCommMaster.sv\n spiCommMaster\n spiCommMaster.v\n spiCommMaster.sv\n obj_dir/spiCommMaster\n obj_dir/spiCommMaster.v\n obj_dir/spiCommMaster.sv\n%Error: data/full_repos/permissive/92094463/main.v:120: Cannot find file containing module: \'counter\'\ncounter #(10) INTLTM (CM_SCLK, INTLTM_RST, INTLTM_OUT, INTLTM_OV);\n^~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:155: Cannot find file containing module: \'spiRead\'\nspiRead #(1) INTLRSM (CM_SCLK, INTLRS_ST, SD_MISO, INTLRS_FIN, INTLRS_OUT, INTLRS_WFBI);\n^~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:163: Cannot find file containing module: \'spiRead\'\nspiRead #(2) INTLRDM (CM_SCLK, INTLRD_ST, SD_MISO, INTLRD_FIN, INTLRD_OUT, INTLRD_WFBI);\n^~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:171: Cannot find file containing module: \'spiRead\'\nspiRead #(4) INTLRQM (CM_SCLK, INTLRQ_ST, SD_MISO, INTLRQ_FIN, INTLRQ_OUT, INTLRQ_WFBI);\n^~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:180: Cannot find file containing module: \'crcGenerator\'\ncrcGenerator #(.LEN(16)) CRCDM (CRCD_IN, CM_SCLK, CRCD_CLR, CRCD_EN, 17\'b1_00010000_00100001, CRCD_OUT);\n^~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/92094463/main.v:668: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s REPLICATE generates 8 bits.\n : ... In instance main\nassign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92094463/main.v:668: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 7 bits.\n : ... In instance main\nassign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];\n ^\n%Error: data/full_repos/permissive/92094463/main.v:670: Cannot find file containing module: \'clockDiv\'\nclockDiv #(10) seg0 (cpuClock, segClock);\n^~~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:671: Cannot find file containing module: \'segMaster\'\nsegMaster seg1 (segClock, numSegment, aen, seg, an, dp); \n^~~~~~~~~\n%Error: data/full_repos/permissive/92094463/main.v:688: Cannot find file containing module: \'clockDiv\'\nclockDiv #(12) d0 (cpuClock, cl0);\n^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/92094463/main.v:689: Operator COND expects 16 bits on the Conditional True, but Conditional True\'s SEL generates 15 bits.\n : ... In instance main\nassign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);\n ^\n%Warning-WIDTH: data/full_repos/permissive/92094463/main.v:689: Operator COND expects 16 bits on the Conditional False, but Conditional False\'s SEL generates 15 bits.\n : ... In instance main\nassign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);\n ^\n%Error: Exiting due to 9 error(s), 4 warning(s)\n' | 309,791 | module | module main(
input _cpuClock,
input [15:0] sw,
input btnC,
input btnU,
input btnD,
input btnL,
input btnR,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
input SD_MISO, SD_CD, SD_WP,
output SD_CLK, SD_MOSI, SD_CS
,
input [31:0] UBDI,
output [31:0] UBDO,
output UBEO,
output UBRRI,
input UBRRA,
input UBRM,
input UBWM,
input [31:0] UBADDR
);
localparam PRESCALE = 8;
wire cpuClock;
assign cpuClock = _cpuClock;
wire globalReset;
assign globalReset = btnU || btnC;
reg [7:0] _errorState = 0;
wire _errorNoti;
reg [5:0] CMD_INDEX;
reg [31:0] CMD_ARG;
reg CMD_TRANSMIT;
reg CM_EN = 0;
reg CM_RST = 1;
reg cmSpiClkEn = 1;
reg CMClkBS = 0;
wire CM_EINT;
wire [3:0] CM_ETYPE;
wire [3:0] CM_EST;
reg [1:0] CM_RM = 2'b00;
wire [39:0] CM_RR;
reg CM_STA = 0;
wire CM_FIN;
wire CM_MISO, CM_CD, CM_WP;
wire CM_SCLK, CM_MOSI, CM_CS;
spiCommMaster CMM (cpuClock, CM_EN, CM_RST, cmSpiClkEn, CMClkBS,
CM_EINT, CM_ETYPE, CM_EST,
CMD_TRANSMIT, CMD_INDEX, CMD_ARG,
CM_RM, CM_RR,
CM_STA, CM_FIN,
CM_MISO, CM_CD, CM_WP, CM_SCLK, CM_MOSI, CM_CS);
reg spiClockEn = 0;
reg INTL_MOSI = 1, INTL_CS = 1;
reg INTLTM_RST = 1;
wire [9:0] INTLTM_OUT;
wire INTLTM_OV;
counter #(10) INTLTM (CM_SCLK, INTLTM_RST, INTLTM_OUT, INTLTM_OV);
reg [39:0] INTL_RR = 0;
reg trySDv1 = 1;
assign CM_MISO = SD_MISO;
assign CM_CD = SD_CD;
assign CM_WP = SD_WP;
assign SD_CLK = (spiClockEn ? CM_SCLK : 1'b1) ;
assign SD_MOSI = (CM_EN ? CM_MOSI : INTL_MOSI);
assign SD_CS = (CM_EN ? CM_CS : INTL_CS);
reg [6:0] _yb = 0;
reg INTLRS_ST = 0;
wire INTLRS_FIN;
reg [7:0] INTLRS_BUFF;
wire [7:0] INTLRS_OUT;
reg INTLRS_WFBI = 1;
spiRead #(1) INTLRSM (CM_SCLK, INTLRS_ST, SD_MISO, INTLRS_FIN, INTLRS_OUT, INTLRS_WFBI);
reg INTLRD_ST = 0;
wire INTLRD_FIN;
reg [15:0] INTLRD_BUFF;
wire [15:0] INTLRD_OUT;
reg INTLRD_WFBI = 0;
spiRead #(2) INTLRDM (CM_SCLK, INTLRD_ST, SD_MISO, INTLRD_FIN, INTLRD_OUT, INTLRD_WFBI);
reg INTLRQ_ST = 0;
wire INTLRQ_FIN;
reg [31:0] INTLRQ_BUFF;
wire [31:0] INTLRQ_OUT;
reg INTLRQ_WFBI = 0;
spiRead #(4) INTLRQM (CM_SCLK, INTLRQ_ST, SD_MISO, INTLRQ_FIN, INTLRQ_OUT, INTLRQ_WFBI);
wire CRCD_IN;
reg CRCD_CLR = 1;
reg CRCD_EN = 0;
wire [15:0] CRCD_OUT;
reg [15:0] CRCD_OUT_BUFF;
crcGenerator #(.LEN(16)) CRCDM (CRCD_IN, CM_SCLK, CRCD_CLR, CRCD_EN, 17'b1_00010000_00100001, CRCD_OUT);
assign CRCD_IN = SD_MISO;
reg DR_DRI = 0;
wire DR_DACK;
reg DREO = 0;
wire [31:0] DR_OUT;
assign DR_OUT = (DR_DRI) ? INTLRQ_BUFF : 32'bZ;
assign UBDO = DR_OUT;
assign UBEO = DREO;
assign UBRRI = DR_DRI;
assign DR_DACK = UBRRA;
reg [7:0] state = 8'h10;
reg [7:0] nstate = 8'h10;
assign _errorNoti = state[7:4] == 4'b0;
always @ (negedge cpuClock) begin
if(globalReset) begin
_errorState <= 8'h0;
nstate <= 8'h10;
INTLTM_RST <= 1;
CM_RST <= 1;
DREO <= 0;
end else begin
case (state)
8'h07: begin
if (SD_WP) begin
nstate <= 8'h10;
end
end
8'h10: begin
CM_RST <= 0;
CM_EN <= 0;
if (!SD_CD) begin
INTLTM_RST <= 0;
nstate <= 8'h11;
end
end
8'h11: begin
if (INTLTM_OUT > 200) begin
spiClockEn <= 1;
INTL_CS <= 1;
INTLTM_RST <= 1;
nstate <= 8'h12;
end
end
8'h12: begin
if (INTLTM_OUT == 0) begin
INTLTM_RST <= 0;
nstate <= 8'h13;
end
end
8'h13: begin
if (INTLTM_OUT > 74) begin
CM_EN <= 1;
nstate <= 8'h14;
end
end
8'h14: begin
INTLTM_RST <= 1;
CMD_INDEX <= 0;
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h15;
end
8'h15: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR = CM_RR;
nstate <= 8'h16;
end
end
8'h16: begin
if (INTL_RR[7:0] == 8'b1) nstate <= 8'h20;
else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h20: begin
nstate <= 8'h24;
end
8'h24: begin
CMD_INDEX <= 6'h08;
CMD_ARG <= {24'h000001, 8'hAA};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h25;
end
8'h25: begin
if (CM_EINT) begin
if(CM_ETYPE == 4'b0010) begin
trySDv1 <= 0;
CM_RST <= 1;
nstate <= 8'h28;
end else begin
nstate <= 8'h05;
end
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h26;
end
end
8'h26: begin
if (INTL_RR[11:0] == 12'h1AA) begin
nstate <= 8'h28;
end else if(INTL_RR[39:32] == 8'h05) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
_errorState = state;
nstate <= 8'h03;
end
end
8'h28: begin
CMD_INDEX <= 55;
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h29;
end
8'h29: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2A;
end
end
8'h2A: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h2C;
end else if (INTL_RR[7:0] == 8'h05) begin
if (trySDv1) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
nstate <= 8'h03;
end
end else begin
_errorState <= state;
nstate <= 8'h03;
end
end
8'h2C: begin
CMD_INDEX <= 41;
CMD_ARG <= {(trySDv1 ? 4'h4 : 4'h0), 28'h0};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h2D;
end
8'h2D: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2E;
end
end
8'h2E: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h28;
end else if (INTL_RR[7:0] == 8'h00) begin
if (trySDv1) begin
nstate <= 8'h30;
end else begin
nstate <= 8'h38;
end
end else if (INTL_RR[7:0] == 8'h05) begin
if (trySDv1) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
_errorState = state;
nstate <= 8'h03;
end
end else begin
_errorState = state;
nstate <= 8'h03;
end
end
8'h30: begin
CMD_INDEX <= 58;
CMD_ARG <= 32'h0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h31;
end
8'h31: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h32;
end
end
8'h32: begin
if (INTL_RR[30] == 1) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h34;
end
end
8'h34: begin
CMD_INDEX <= 16;
CMD_ARG <= 32'h00000200;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h35;
end
8'h35: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h36;
end
end
8'h36: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h02;
_errorState <= state;
end
end
8'h40: begin
if (SD_CD) begin
nstate <= 8'h10;
end
if (UBRM) begin
nstate <= 8'h60;
end else if (UBWM) begin
nstate <= 8'hA0;
end
end
8'h60: begin
CMD_INDEX <= 17;
CMD_ARG <= UBADDR;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h61;
end
8'h61: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h62;
end
end
8'h62: begin
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0;
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h64;
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h64: begin
if (INTLRS_FIN == 0) begin
INTLRS_ST <= 1;
INTLRS_WFBI <= 0;
spiClockEn <= 1;
nstate <= 8'h65;
end
end
8'h65: begin
if (INTLRS_FIN) begin
nstate <= 8'h66;
INTLRS_ST <= 0;
INTLRS_WFBI <= 1;
INTLRS_BUFF <= INTLRS_OUT;
end
end
8'h66: begin
if (INTLRS_BUFF == 8'hFE) begin
INTLTM_RST <= 1;
nstate <= 8'h67;
end else if (INTLRS_BUFF == 8'hFC) begin
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFD) begin
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFF) begin
if (INTLTM_OUT > 200) begin
INTLTM_RST <= 1;
_errorState <= state;
nstate <= 8'h01;
end else begin
spiClockEn <= 0;
nstate <= 8'h64;
end
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h67: begin
_yb <= 0;
CRCD_CLR <= 0;
nstate <= 8'h68;
end
8'h68: begin
INTLRQ_ST <= 1;
spiClockEn <= 1;
DR_DRI <= 0;
CRCD_EN <= 1;
nstate <= 8'h69;
end
8'h69: begin
if (INTLRQ_FIN) begin
spiClockEn <= 0;
INTLRQ_BUFF <= INTLRQ_OUT;
INTLRQ_ST <= 0;
DR_DRI <= 1;
CRCD_OUT_BUFF <= CRCD_OUT;
CRCD_EN <= 0;
nstate <= 8'h6A;
end else begin
spiClockEn <= 1;
end
end
8'h6A: begin
if (!INTLRQ_FIN && DR_DACK) begin
if (_yb == 7'h7F) begin
_yb <= 0;
nstate <= 8'h70;
end else begin
_yb <= _yb + 1;
nstate <= 8'h68;
end
end
end
8'h70: begin
INTLRD_ST <= 1;
spiClockEn <= 1;
nstate <= 8'h71;
end
8'h71: begin
if (INTLRD_FIN) begin
INTLRD_BUFF <= INTLRD_OUT;
INTLRD_ST <= 0;
nstate <= 8'h72;
end
end
8'h72: begin
if (INTLRD_BUFF == CRCD_OUT_BUFF) begin
DREO <= 0;
nstate <= 8'h74;
end else begin
DREO <= 1;
nstate <= 8'h08;
end
end
8'h74: begin
CM_EN <= 1;
nstate <= 8'h40;
end
8'h80: begin
CMD_INDEX <= 18;
CMD_ARG <= UBADDR;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h81;
end
8'h81: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h82;
end
end
8'h82: begin
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0;
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h84;
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h84: begin
end
8'hA0: begin
end
default: begin
if(state[7:4] != 4'b0) begin
_errorState = state;
nstate = 8'h04;
end
end
endcase
end
end
always @ (posedge cpuClock) begin
if (nstate != state && nstate != state + 1 && nstate[1:0] != 2'b00 && nstate[7:4] != 4'h0) begin
state <= 8'h06;
end else begin
state <= nstate;
end
end
reg [63:0] history = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
history = 0;
end else if (nstate != state) begin
history = {history[55:0], nstate};
end
end
wire [2:0] historySel;
assign historySel = sw[10:8];
wire [15:0] numSegment;
wire segClock;
wire [3:0] aen;
assign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];
assign aen = ~sw[15:12];
clockDiv #(10) seg0 (cpuClock, segClock);
segMaster seg1 (segClock, numSegment, aen, seg, an, dp);
reg [255:0] historyBuff = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
historyBuff = 0;
end else if (INTLRQ_BUFF != historyBuff[31:0]) begin
historyBuff = {historyBuff[223:0], INTLRQ_BUFF};
end
end
wire [1:0] layer;
assign layer = sw[1:0];
wire cl0, cl1, cl2;
clockDiv #(12) d0 (cpuClock, cl0);
assign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);
endmodule | module main(
input _cpuClock,
input [15:0] sw,
input btnC,
input btnU,
input btnD,
input btnL,
input btnR,
output [15:0] led,
output [6:0] seg,
output dp,
output [3:0] an,
input SD_MISO, SD_CD, SD_WP,
output SD_CLK, SD_MOSI, SD_CS
,
input [31:0] UBDI,
output [31:0] UBDO,
output UBEO,
output UBRRI,
input UBRRA,
input UBRM,
input UBWM,
input [31:0] UBADDR
); |
localparam PRESCALE = 8;
wire cpuClock;
assign cpuClock = _cpuClock;
wire globalReset;
assign globalReset = btnU || btnC;
reg [7:0] _errorState = 0;
wire _errorNoti;
reg [5:0] CMD_INDEX;
reg [31:0] CMD_ARG;
reg CMD_TRANSMIT;
reg CM_EN = 0;
reg CM_RST = 1;
reg cmSpiClkEn = 1;
reg CMClkBS = 0;
wire CM_EINT;
wire [3:0] CM_ETYPE;
wire [3:0] CM_EST;
reg [1:0] CM_RM = 2'b00;
wire [39:0] CM_RR;
reg CM_STA = 0;
wire CM_FIN;
wire CM_MISO, CM_CD, CM_WP;
wire CM_SCLK, CM_MOSI, CM_CS;
spiCommMaster CMM (cpuClock, CM_EN, CM_RST, cmSpiClkEn, CMClkBS,
CM_EINT, CM_ETYPE, CM_EST,
CMD_TRANSMIT, CMD_INDEX, CMD_ARG,
CM_RM, CM_RR,
CM_STA, CM_FIN,
CM_MISO, CM_CD, CM_WP, CM_SCLK, CM_MOSI, CM_CS);
reg spiClockEn = 0;
reg INTL_MOSI = 1, INTL_CS = 1;
reg INTLTM_RST = 1;
wire [9:0] INTLTM_OUT;
wire INTLTM_OV;
counter #(10) INTLTM (CM_SCLK, INTLTM_RST, INTLTM_OUT, INTLTM_OV);
reg [39:0] INTL_RR = 0;
reg trySDv1 = 1;
assign CM_MISO = SD_MISO;
assign CM_CD = SD_CD;
assign CM_WP = SD_WP;
assign SD_CLK = (spiClockEn ? CM_SCLK : 1'b1) ;
assign SD_MOSI = (CM_EN ? CM_MOSI : INTL_MOSI);
assign SD_CS = (CM_EN ? CM_CS : INTL_CS);
reg [6:0] _yb = 0;
reg INTLRS_ST = 0;
wire INTLRS_FIN;
reg [7:0] INTLRS_BUFF;
wire [7:0] INTLRS_OUT;
reg INTLRS_WFBI = 1;
spiRead #(1) INTLRSM (CM_SCLK, INTLRS_ST, SD_MISO, INTLRS_FIN, INTLRS_OUT, INTLRS_WFBI);
reg INTLRD_ST = 0;
wire INTLRD_FIN;
reg [15:0] INTLRD_BUFF;
wire [15:0] INTLRD_OUT;
reg INTLRD_WFBI = 0;
spiRead #(2) INTLRDM (CM_SCLK, INTLRD_ST, SD_MISO, INTLRD_FIN, INTLRD_OUT, INTLRD_WFBI);
reg INTLRQ_ST = 0;
wire INTLRQ_FIN;
reg [31:0] INTLRQ_BUFF;
wire [31:0] INTLRQ_OUT;
reg INTLRQ_WFBI = 0;
spiRead #(4) INTLRQM (CM_SCLK, INTLRQ_ST, SD_MISO, INTLRQ_FIN, INTLRQ_OUT, INTLRQ_WFBI);
wire CRCD_IN;
reg CRCD_CLR = 1;
reg CRCD_EN = 0;
wire [15:0] CRCD_OUT;
reg [15:0] CRCD_OUT_BUFF;
crcGenerator #(.LEN(16)) CRCDM (CRCD_IN, CM_SCLK, CRCD_CLR, CRCD_EN, 17'b1_00010000_00100001, CRCD_OUT);
assign CRCD_IN = SD_MISO;
reg DR_DRI = 0;
wire DR_DACK;
reg DREO = 0;
wire [31:0] DR_OUT;
assign DR_OUT = (DR_DRI) ? INTLRQ_BUFF : 32'bZ;
assign UBDO = DR_OUT;
assign UBEO = DREO;
assign UBRRI = DR_DRI;
assign DR_DACK = UBRRA;
reg [7:0] state = 8'h10;
reg [7:0] nstate = 8'h10;
assign _errorNoti = state[7:4] == 4'b0;
always @ (negedge cpuClock) begin
if(globalReset) begin
_errorState <= 8'h0;
nstate <= 8'h10;
INTLTM_RST <= 1;
CM_RST <= 1;
DREO <= 0;
end else begin
case (state)
8'h07: begin
if (SD_WP) begin
nstate <= 8'h10;
end
end
8'h10: begin
CM_RST <= 0;
CM_EN <= 0;
if (!SD_CD) begin
INTLTM_RST <= 0;
nstate <= 8'h11;
end
end
8'h11: begin
if (INTLTM_OUT > 200) begin
spiClockEn <= 1;
INTL_CS <= 1;
INTLTM_RST <= 1;
nstate <= 8'h12;
end
end
8'h12: begin
if (INTLTM_OUT == 0) begin
INTLTM_RST <= 0;
nstate <= 8'h13;
end
end
8'h13: begin
if (INTLTM_OUT > 74) begin
CM_EN <= 1;
nstate <= 8'h14;
end
end
8'h14: begin
INTLTM_RST <= 1;
CMD_INDEX <= 0;
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h15;
end
8'h15: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR = CM_RR;
nstate <= 8'h16;
end
end
8'h16: begin
if (INTL_RR[7:0] == 8'b1) nstate <= 8'h20;
else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h20: begin
nstate <= 8'h24;
end
8'h24: begin
CMD_INDEX <= 6'h08;
CMD_ARG <= {24'h000001, 8'hAA};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h25;
end
8'h25: begin
if (CM_EINT) begin
if(CM_ETYPE == 4'b0010) begin
trySDv1 <= 0;
CM_RST <= 1;
nstate <= 8'h28;
end else begin
nstate <= 8'h05;
end
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h26;
end
end
8'h26: begin
if (INTL_RR[11:0] == 12'h1AA) begin
nstate <= 8'h28;
end else if(INTL_RR[39:32] == 8'h05) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
_errorState = state;
nstate <= 8'h03;
end
end
8'h28: begin
CMD_INDEX <= 55;
CMD_ARG <= 0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h29;
end
8'h29: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2A;
end
end
8'h2A: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h2C;
end else if (INTL_RR[7:0] == 8'h05) begin
if (trySDv1) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
nstate <= 8'h03;
end
end else begin
_errorState <= state;
nstate <= 8'h03;
end
end
8'h2C: begin
CMD_INDEX <= 41;
CMD_ARG <= {(trySDv1 ? 4'h4 : 4'h0), 28'h0};
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h2D;
end
8'h2D: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h2E;
end
end
8'h2E: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h28;
end else if (INTL_RR[7:0] == 8'h00) begin
if (trySDv1) begin
nstate <= 8'h30;
end else begin
nstate <= 8'h38;
end
end else if (INTL_RR[7:0] == 8'h05) begin
if (trySDv1) begin
trySDv1 <= 0;
nstate <= 8'h28;
end else begin
_errorState = state;
nstate <= 8'h03;
end
end else begin
_errorState = state;
nstate <= 8'h03;
end
end
8'h30: begin
CMD_INDEX <= 58;
CMD_ARG <= 32'h0;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 2;
nstate <= 8'h31;
end
8'h31: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h32;
end
end
8'h32: begin
if (INTL_RR[30] == 1) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h34;
end
end
8'h34: begin
CMD_INDEX <= 16;
CMD_ARG <= 32'h00000200;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h35;
end
8'h35: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h36;
end
end
8'h36: begin
if (INTL_RR[7:0] == 8'h01) begin
nstate <= 8'h40;
end else begin
nstate <= 8'h02;
_errorState <= state;
end
end
8'h40: begin
if (SD_CD) begin
nstate <= 8'h10;
end
if (UBRM) begin
nstate <= 8'h60;
end else if (UBWM) begin
nstate <= 8'hA0;
end
end
8'h60: begin
CMD_INDEX <= 17;
CMD_ARG <= UBADDR;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h61;
end
8'h61: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h62;
end
end
8'h62: begin
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0;
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h64;
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h64: begin
if (INTLRS_FIN == 0) begin
INTLRS_ST <= 1;
INTLRS_WFBI <= 0;
spiClockEn <= 1;
nstate <= 8'h65;
end
end
8'h65: begin
if (INTLRS_FIN) begin
nstate <= 8'h66;
INTLRS_ST <= 0;
INTLRS_WFBI <= 1;
INTLRS_BUFF <= INTLRS_OUT;
end
end
8'h66: begin
if (INTLRS_BUFF == 8'hFE) begin
INTLTM_RST <= 1;
nstate <= 8'h67;
end else if (INTLRS_BUFF == 8'hFC) begin
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFD) begin
_errorState <= state;
nstate <= 8'h02;
end else if (INTLRS_BUFF == 8'hFF) begin
if (INTLTM_OUT > 200) begin
INTLTM_RST <= 1;
_errorState <= state;
nstate <= 8'h01;
end else begin
spiClockEn <= 0;
nstate <= 8'h64;
end
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h67: begin
_yb <= 0;
CRCD_CLR <= 0;
nstate <= 8'h68;
end
8'h68: begin
INTLRQ_ST <= 1;
spiClockEn <= 1;
DR_DRI <= 0;
CRCD_EN <= 1;
nstate <= 8'h69;
end
8'h69: begin
if (INTLRQ_FIN) begin
spiClockEn <= 0;
INTLRQ_BUFF <= INTLRQ_OUT;
INTLRQ_ST <= 0;
DR_DRI <= 1;
CRCD_OUT_BUFF <= CRCD_OUT;
CRCD_EN <= 0;
nstate <= 8'h6A;
end else begin
spiClockEn <= 1;
end
end
8'h6A: begin
if (!INTLRQ_FIN && DR_DACK) begin
if (_yb == 7'h7F) begin
_yb <= 0;
nstate <= 8'h70;
end else begin
_yb <= _yb + 1;
nstate <= 8'h68;
end
end
end
8'h70: begin
INTLRD_ST <= 1;
spiClockEn <= 1;
nstate <= 8'h71;
end
8'h71: begin
if (INTLRD_FIN) begin
INTLRD_BUFF <= INTLRD_OUT;
INTLRD_ST <= 0;
nstate <= 8'h72;
end
end
8'h72: begin
if (INTLRD_BUFF == CRCD_OUT_BUFF) begin
DREO <= 0;
nstate <= 8'h74;
end else begin
DREO <= 1;
nstate <= 8'h08;
end
end
8'h74: begin
CM_EN <= 1;
nstate <= 8'h40;
end
8'h80: begin
CMD_INDEX <= 18;
CMD_ARG <= UBADDR;
CMD_TRANSMIT <= 1;
CM_STA <= 1;
CM_RST <= 0;
CM_RM <= 0;
nstate <= 8'h81;
end
8'h81: begin
if (CM_EINT) begin
_errorState <= state;
nstate <= 8'h05;
end else if (CM_FIN) begin
CM_STA <= 0;
INTL_RR <= CM_RR;
nstate <= 8'h82;
end
end
8'h82: begin
if (INTL_RR[7:0] == 8'h00) begin
CM_EN <= 0;
INTL_MOSI <= 1;
INTL_CS <= 0;
INTLTM_RST <= 0;
spiClockEn <= 0;
nstate <= 8'h84;
end else begin
_errorState <= state;
nstate <= 8'h02;
end
end
8'h84: begin
end
8'hA0: begin
end
default: begin
if(state[7:4] != 4'b0) begin
_errorState = state;
nstate = 8'h04;
end
end
endcase
end
end
always @ (posedge cpuClock) begin
if (nstate != state && nstate != state + 1 && nstate[1:0] != 2'b00 && nstate[7:4] != 4'h0) begin
state <= 8'h06;
end else begin
state <= nstate;
end
end
reg [63:0] history = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
history = 0;
end else if (nstate != state) begin
history = {history[55:0], nstate};
end
end
wire [2:0] historySel;
assign historySel = sw[10:8];
wire [15:0] numSegment;
wire segClock;
wire [3:0] aen;
assign numSegment = sw[11] ? {CM_EST, CM_ETYPE} : historySel == 0 ? {_errorState, state} : history[historySel * 8 +:7];
assign aen = ~sw[15:12];
clockDiv #(10) seg0 (cpuClock, segClock);
segMaster seg1 (segClock, numSegment, aen, seg, an, dp);
reg [255:0] historyBuff = 0;
always @ (posedge cpuClock) begin
if (globalReset)begin
historyBuff = 0;
end else if (INTLRQ_BUFF != historyBuff[31:0]) begin
historyBuff = {historyBuff[223:0], INTLRQ_BUFF};
end
end
wire [1:0] layer;
assign layer = sw[1:0];
wire cl0, cl1, cl2;
clockDiv #(12) d0 (cpuClock, cl0);
assign led = (sw[1] ? historyBuff[historySel * 32 + 16 +:15] : historyBuff[historySel * 32 +:15]);
endmodule | 1 |
140,860 | data/full_repos/permissive/92618161/rtl/ccs.v | 92,618,161 | ccs.v | v | 241 | 122 | [] | [] | [] | [(10, 240)] | null | data/verilator_xmls/e97a619a-436c-4d0b-8960-4f22b88631ec.xml | null | 309,796 | module | module ccs
(
input wire clk,
input wire credit_in,
input wire [PORTS-1:0] port_rqs,
output wire [PORTS-1:0] arb_ack,
output wire [PORTS-1:0] xbar_cfg_vector
);
genvar index;
localparam PORTS = 5;
localparam CREDITS = 4;
localparam IDLE = 2'b00;
localparam NEW = 2'b01;
localparam PULL = 2'b10;
localparam ZERO = 2'b00;
localparam HOLD = 2'b01;
localparam NEXT = 2'b10;
localparam FULL = 2'b11;
wire any_crd;
wire [2:0] crd_next;
reg [2:0] crd_reg = CREDITS;
wire [PORTS-1:0] grant_vector_next;
wire [PORTS-1:0] p_next;
reg [PORTS-1:0] p_reg = 1;
wire [PORTS-1:0] arb1_grant;
wire [PORTS-1:0] arb2_grant;
wire [PORTS-1:0] arb1_cc;
wire [PORTS-1:0] arb2_cc;
wire any_grant;
wire any_rqs;
wire arb_grant;
reg [1:0] fsm_cnt_reg = 2'b00;
wire [1:0] fsm_cnt_next;
wire [1:0] fsm_mux_cfg;
reg [1:0] state_reg = IDLE;
reg [1:0] state_next;
wire [PORTS-1:0] cfg_vector_next;
reg [PORTS-1:0] cfg_vector_reg = 0;
always @(posedge clk)
crd_reg <= crd_next;
assign crd_next = (credit_in) ? crd_reg + 1'b1 :
(state_reg == IDLE && state_next == NEW) ? crd_reg - 1'b1 :
(state_reg == PULL && state_next == NEW) ? crd_reg - 1'b1 :
crd_reg;
assign any_crd = |crd_reg;
always @(posedge clk)
p_reg <= p_next;
assign p_next = (state_reg == NEW && state_next == PULL) ? {cfg_vector_reg[PORTS-2:0], cfg_vector_reg[PORTS-1]} :
p_reg;
generate
for(index=0; index<PORTS; index=index+1)
begin: arb1_grant_slice
assign arb1_grant[index] = (p_reg[index] | arb1_cc[index]) & port_rqs[index];
end
endgenerate
assign arb1_cc[0] = 1'b0;
generate
for (index=1; index<PORTS; index=index+1)
begin: arb1_cc_slice
assign arb1_cc[index] = (p_reg[index-1] | arb1_cc[index-1]) & ~port_rqs[index-1];
end
endgenerate
generate
for(index=0; index<PORTS; index=index+1)
begin: arb2_grant_slice
assign arb2_grant[index] = (p_reg[index] | arb2_cc[index]) & port_rqs[index];
end
endgenerate
assign arb2_cc[0] = arb1_cc[PORTS-1];
generate
for (index=1; index<PORTS; index=index+1)
begin: arb2_cc_slice
assign arb2_cc[index] = (p_reg[index-1] | arb2_cc[index-1]) & ~port_rqs[index-1];
end
endgenerate
assign grant_vector_next = arb1_grant | arb2_grant;
assign any_rqs = |port_rqs;
assign any_grant = |cfg_vector_reg;
always @(posedge clk)
state_reg <= state_next;
always @(*) begin
state_next = IDLE;
case (state_reg)
IDLE:
if (any_rqs && any_crd)
state_next = NEW;
else
state_next = IDLE;
NEW:
state_next = PULL;
PULL:
if (|fsm_cnt_reg)
state_next = PULL;
else if (~|fsm_cnt_reg && any_rqs && any_crd)
state_next = NEW;
else
state_next = IDLE;
endcase
end
assign fsm_mux_cfg = (state_reg == IDLE && state_next == NEW) ? NEXT :
(state_reg == PULL && state_next == NEW) ? NEXT :
(state_reg == NEW && state_next == PULL) ? HOLD :
(state_reg == PULL && state_next == PULL) ? HOLD :
ZERO;
assign arb_grant = (state_reg == NEW && state_next == PULL) ? 1'b1 :
(state_reg == PULL && state_next == NEW) ? 1'b1 :
1'b0;
assign arb_ack = {5{arb_grant}} & cfg_vector_reg;
always @(posedge clk)
fsm_cnt_reg <= fsm_cnt_next;
assign fsm_cnt_next = (state_reg == IDLE && state_next == NEW) ? FULL :
(state_reg == PULL && state_next == NEW) ? FULL :
(state_reg == NEW && state_next == PULL) ? fsm_cnt_reg - 1'b1 :
(state_reg == PULL && state_next == PULL) ? fsm_cnt_reg - 1'b1 :
fsm_cnt_reg;
generate
for (index=0; index<PORTS;index=index+1)
begin: hold_slice
assign cfg_vector_next[index] = (fsm_mux_cfg == NEXT) ? grant_vector_next[index] :
(fsm_mux_cfg == HOLD) ? cfg_vector_reg [index] :
1'b0;
always @(posedge clk)
cfg_vector_reg[index] <= cfg_vector_next[index];
end
endgenerate
assign xbar_cfg_vector = cfg_vector_reg;
endmodule | module ccs
(
input wire clk,
input wire credit_in,
input wire [PORTS-1:0] port_rqs,
output wire [PORTS-1:0] arb_ack,
output wire [PORTS-1:0] xbar_cfg_vector
); |
genvar index;
localparam PORTS = 5;
localparam CREDITS = 4;
localparam IDLE = 2'b00;
localparam NEW = 2'b01;
localparam PULL = 2'b10;
localparam ZERO = 2'b00;
localparam HOLD = 2'b01;
localparam NEXT = 2'b10;
localparam FULL = 2'b11;
wire any_crd;
wire [2:0] crd_next;
reg [2:0] crd_reg = CREDITS;
wire [PORTS-1:0] grant_vector_next;
wire [PORTS-1:0] p_next;
reg [PORTS-1:0] p_reg = 1;
wire [PORTS-1:0] arb1_grant;
wire [PORTS-1:0] arb2_grant;
wire [PORTS-1:0] arb1_cc;
wire [PORTS-1:0] arb2_cc;
wire any_grant;
wire any_rqs;
wire arb_grant;
reg [1:0] fsm_cnt_reg = 2'b00;
wire [1:0] fsm_cnt_next;
wire [1:0] fsm_mux_cfg;
reg [1:0] state_reg = IDLE;
reg [1:0] state_next;
wire [PORTS-1:0] cfg_vector_next;
reg [PORTS-1:0] cfg_vector_reg = 0;
always @(posedge clk)
crd_reg <= crd_next;
assign crd_next = (credit_in) ? crd_reg + 1'b1 :
(state_reg == IDLE && state_next == NEW) ? crd_reg - 1'b1 :
(state_reg == PULL && state_next == NEW) ? crd_reg - 1'b1 :
crd_reg;
assign any_crd = |crd_reg;
always @(posedge clk)
p_reg <= p_next;
assign p_next = (state_reg == NEW && state_next == PULL) ? {cfg_vector_reg[PORTS-2:0], cfg_vector_reg[PORTS-1]} :
p_reg;
generate
for(index=0; index<PORTS; index=index+1)
begin: arb1_grant_slice
assign arb1_grant[index] = (p_reg[index] | arb1_cc[index]) & port_rqs[index];
end
endgenerate
assign arb1_cc[0] = 1'b0;
generate
for (index=1; index<PORTS; index=index+1)
begin: arb1_cc_slice
assign arb1_cc[index] = (p_reg[index-1] | arb1_cc[index-1]) & ~port_rqs[index-1];
end
endgenerate
generate
for(index=0; index<PORTS; index=index+1)
begin: arb2_grant_slice
assign arb2_grant[index] = (p_reg[index] | arb2_cc[index]) & port_rqs[index];
end
endgenerate
assign arb2_cc[0] = arb1_cc[PORTS-1];
generate
for (index=1; index<PORTS; index=index+1)
begin: arb2_cc_slice
assign arb2_cc[index] = (p_reg[index-1] | arb2_cc[index-1]) & ~port_rqs[index-1];
end
endgenerate
assign grant_vector_next = arb1_grant | arb2_grant;
assign any_rqs = |port_rqs;
assign any_grant = |cfg_vector_reg;
always @(posedge clk)
state_reg <= state_next;
always @(*) begin
state_next = IDLE;
case (state_reg)
IDLE:
if (any_rqs && any_crd)
state_next = NEW;
else
state_next = IDLE;
NEW:
state_next = PULL;
PULL:
if (|fsm_cnt_reg)
state_next = PULL;
else if (~|fsm_cnt_reg && any_rqs && any_crd)
state_next = NEW;
else
state_next = IDLE;
endcase
end
assign fsm_mux_cfg = (state_reg == IDLE && state_next == NEW) ? NEXT :
(state_reg == PULL && state_next == NEW) ? NEXT :
(state_reg == NEW && state_next == PULL) ? HOLD :
(state_reg == PULL && state_next == PULL) ? HOLD :
ZERO;
assign arb_grant = (state_reg == NEW && state_next == PULL) ? 1'b1 :
(state_reg == PULL && state_next == NEW) ? 1'b1 :
1'b0;
assign arb_ack = {5{arb_grant}} & cfg_vector_reg;
always @(posedge clk)
fsm_cnt_reg <= fsm_cnt_next;
assign fsm_cnt_next = (state_reg == IDLE && state_next == NEW) ? FULL :
(state_reg == PULL && state_next == NEW) ? FULL :
(state_reg == NEW && state_next == PULL) ? fsm_cnt_reg - 1'b1 :
(state_reg == PULL && state_next == PULL) ? fsm_cnt_reg - 1'b1 :
fsm_cnt_reg;
generate
for (index=0; index<PORTS;index=index+1)
begin: hold_slice
assign cfg_vector_next[index] = (fsm_mux_cfg == NEXT) ? grant_vector_next[index] :
(fsm_mux_cfg == HOLD) ? cfg_vector_reg [index] :
1'b0;
always @(posedge clk)
cfg_vector_reg[index] <= cfg_vector_next[index];
end
endgenerate
assign xbar_cfg_vector = cfg_vector_reg;
endmodule | 0 |
140,861 | data/full_repos/permissive/92618161/rtl/fifo.v | 92,618,161 | fifo.v | v | 95 | 81 | [] | [] | [] | null | line:82: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/fifo.v:46: Cannot find file containing module: 'fifo_controller'\n fifo_controller #(.DWIDTH(DWIDTH), .FDEPTH(FDEPTH)) fifo_controller\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller.v\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller.sv\n fifo_controller\n fifo_controller.v\n fifo_controller.sv\n obj_dir/fifo_controller\n obj_dir/fifo_controller.v\n obj_dir/fifo_controller.sv\n%Error: Exiting due to 1 error(s)\n" | 309,797 | module | module fifo #(parameter DWIDTH=32,
FDEPTH=16)
(
input wire clk,
input wire rst,
input wire wr_strobe,
input wire rd_strobe,
input wire [DWIDTH-1:0] wr_data,
output wire [DWIDTH-1:0] rd_data
);
localparam AWIDTH=clog2(FDEPTH-1);
wire full;
wire empty;
wire [AWIDTH-1:0] rd_addr;
wire [AWIDTH-1:0] wr_addr;
reg [DWIDTH-1:0] REG_FILE [0:FDEPTH-1];
wire push;
integer rf_index;
fifo_controller #(.DWIDTH(DWIDTH), .FDEPTH(FDEPTH)) fifo_controller
(
.clk(clk),
.rst(rst),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.full(full),
.empty(empty),
.rd_addr(rd_addr),
.wr_addr(wr_addr)
);
assign push = wr_strobe & ~full;
always @(posedge clk)
if (push)
REG_FILE[wr_addr] <= wr_data;
assign rd_data = REG_FILE[rd_addr];
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
initial
for (rf_index = 0; rf_index < FDEPTH; rf_index = rf_index + 1)
REG_FILE[rf_index] = {DWIDTH{1'b0}};
endmodule | module fifo #(parameter DWIDTH=32,
FDEPTH=16)
(
input wire clk,
input wire rst,
input wire wr_strobe,
input wire rd_strobe,
input wire [DWIDTH-1:0] wr_data,
output wire [DWIDTH-1:0] rd_data
); |
localparam AWIDTH=clog2(FDEPTH-1);
wire full;
wire empty;
wire [AWIDTH-1:0] rd_addr;
wire [AWIDTH-1:0] wr_addr;
reg [DWIDTH-1:0] REG_FILE [0:FDEPTH-1];
wire push;
integer rf_index;
fifo_controller #(.DWIDTH(DWIDTH), .FDEPTH(FDEPTH)) fifo_controller
(
.clk(clk),
.rst(rst),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.full(full),
.empty(empty),
.rd_addr(rd_addr),
.wr_addr(wr_addr)
);
assign push = wr_strobe & ~full;
always @(posedge clk)
if (push)
REG_FILE[wr_addr] <= wr_data;
assign rd_data = REG_FILE[rd_addr];
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
initial
for (rf_index = 0; rf_index < FDEPTH; rf_index = rf_index + 1)
REG_FILE[rf_index] = {DWIDTH{1'b0}};
endmodule | 0 |
140,862 | data/full_repos/permissive/92618161/rtl/fifo.v | 92,618,161 | fifo.v | v | 95 | 81 | [] | [] | [] | null | line:82: before: "integer" | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/fifo.v:46: Cannot find file containing module: 'fifo_controller'\n fifo_controller #(.DWIDTH(DWIDTH), .FDEPTH(FDEPTH)) fifo_controller\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller.v\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/fifo_controller.sv\n fifo_controller\n fifo_controller.v\n fifo_controller.sv\n obj_dir/fifo_controller\n obj_dir/fifo_controller.v\n obj_dir/fifo_controller.sv\n%Error: Exiting due to 1 error(s)\n" | 309,797 | function | function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | function integer clog2; |
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | 0 |
140,863 | data/full_repos/permissive/92618161/rtl/fifo_controller.v | 92,618,161 | fifo_controller.v | v | 136 | 46 | [] | [] | [] | null | line:129: before: "integer" | data/verilator_xmls/f8b1abb7-29e1-4b03-adce-f656fc191a0e.xml | null | 309,798 | module | module fifo_controller #(parameter DWIDTH=32,
FDEPTH=16)
(
input wire clk,
input wire rst,
input wire wr_strobe,
input wire rd_strobe,
output wire full,
output wire empty,
output wire [AWIDTH-1:0] rd_addr,
output wire [AWIDTH-1:0] wr_addr
);
localparam AWIDTH=clog2(FDEPTH-1);
reg [AWIDTH-1:0] wr_ptr_reg;
reg [AWIDTH-1:0] wr_ptr_next;
reg [AWIDTH-1:0] wr_ptr_succ;
reg [AWIDTH-1:0] rd_ptr_reg;
reg [AWIDTH-1:0] rd_ptr_next;
reg [AWIDTH-1:0] rd_ptr_succ;
reg full_reg;
reg full_next;
reg empty_reg;
reg empty_next;
always @(posedge clk)
if (rst)
begin
full_reg <= 1'b0;
empty_reg <= 1'b1;
wr_ptr_reg <= {AWIDTH{1'b0}};
rd_ptr_reg <= {AWIDTH{1'b0}};
end
else
begin
full_reg <= full_next;
empty_reg <= empty_next;
wr_ptr_reg <= wr_ptr_next;
rd_ptr_reg <= rd_ptr_next;
end
always @(*) begin
wr_ptr_succ = wr_ptr_reg + 1'b1;
rd_ptr_succ = rd_ptr_reg + 1'b1;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr_strobe, rd_strobe})
2'b00: begin
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
end
2'b01: begin
if(~empty_reg) begin
rd_ptr_next = rd_ptr_succ;
full_next = 1'b0;
if (rd_ptr_succ == wr_ptr_reg)
empty_next = 1'b1;
end
end
2'b10: begin
if(~full_reg) begin
wr_ptr_next = wr_ptr_succ;
empty_next = 1'b0;
if (wr_ptr_succ == rd_ptr_reg)
full_next = 1'b1;
end
end
2'b11: begin
wr_ptr_next = wr_ptr_succ;
rd_ptr_next = rd_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign wr_addr = wr_ptr_reg;
assign rd_addr = rd_ptr_reg;
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | module fifo_controller #(parameter DWIDTH=32,
FDEPTH=16)
(
input wire clk,
input wire rst,
input wire wr_strobe,
input wire rd_strobe,
output wire full,
output wire empty,
output wire [AWIDTH-1:0] rd_addr,
output wire [AWIDTH-1:0] wr_addr
); |
localparam AWIDTH=clog2(FDEPTH-1);
reg [AWIDTH-1:0] wr_ptr_reg;
reg [AWIDTH-1:0] wr_ptr_next;
reg [AWIDTH-1:0] wr_ptr_succ;
reg [AWIDTH-1:0] rd_ptr_reg;
reg [AWIDTH-1:0] rd_ptr_next;
reg [AWIDTH-1:0] rd_ptr_succ;
reg full_reg;
reg full_next;
reg empty_reg;
reg empty_next;
always @(posedge clk)
if (rst)
begin
full_reg <= 1'b0;
empty_reg <= 1'b1;
wr_ptr_reg <= {AWIDTH{1'b0}};
rd_ptr_reg <= {AWIDTH{1'b0}};
end
else
begin
full_reg <= full_next;
empty_reg <= empty_next;
wr_ptr_reg <= wr_ptr_next;
rd_ptr_reg <= rd_ptr_next;
end
always @(*) begin
wr_ptr_succ = wr_ptr_reg + 1'b1;
rd_ptr_succ = rd_ptr_reg + 1'b1;
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
case ({wr_strobe, rd_strobe})
2'b00: begin
wr_ptr_next = wr_ptr_reg;
rd_ptr_next = rd_ptr_reg;
full_next = full_reg;
empty_next = empty_reg;
end
2'b01: begin
if(~empty_reg) begin
rd_ptr_next = rd_ptr_succ;
full_next = 1'b0;
if (rd_ptr_succ == wr_ptr_reg)
empty_next = 1'b1;
end
end
2'b10: begin
if(~full_reg) begin
wr_ptr_next = wr_ptr_succ;
empty_next = 1'b0;
if (wr_ptr_succ == rd_ptr_reg)
full_next = 1'b1;
end
end
2'b11: begin
wr_ptr_next = wr_ptr_succ;
rd_ptr_next = rd_ptr_succ;
end
endcase
end
assign full = full_reg;
assign empty = empty_reg;
assign wr_addr = wr_ptr_reg;
assign rd_addr = rd_ptr_reg;
function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction
endmodule | 0 |
140,864 | data/full_repos/permissive/92618161/rtl/fifo_controller.v | 92,618,161 | fifo_controller.v | v | 136 | 46 | [] | [] | [] | null | line:129: before: "integer" | data/verilator_xmls/f8b1abb7-29e1-4b03-adce-f656fc191a0e.xml | null | 309,798 | function | function integer clog2;
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | function integer clog2; |
input integer depth;
for (clog2=0; depth>0; clog2=clog2+1)
depth = depth >> 1;
endfunction | 0 |
140,865 | data/full_repos/permissive/92618161/rtl/hexa.v | 92,618,161 | hexa.v | v | 197 | 96 | [] | [] | [] | [(7, 196)] | null | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/hexa.v:77: Cannot find file containing module: 'inport'\n inport #(.XCOR(XCOR), .YCOR(YCOR)) \n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/inport\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/inport.v\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/inport.sv\n inport\n inport.v\n inport.sv\n obj_dir/inport\n obj_dir/inport.v\n obj_dir/inport.sv\n%Error: data/full_repos/permissive/92618161/rtl/hexa.v:115: Cannot find file containing module: 'ccs'\n ccs ccs (\n ^~~\n%Error: data/full_repos/permissive/92618161/rtl/hexa.v:142: Cannot find file containing module: 'switch_fabric'\n switch_fabric switch_fabric (\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/hexa.v:168: Cannot find file containing module: 'outport'\n outport outport (\n ^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 309,799 | module | module hexa #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire [PORTS-1:0] diff_pair_pi,
input wire [PORTS-1:0] diff_pair_ni,
input wire [PORTS-1:0] crt_in,
input wire [(32*PORTS)-1:0] input_channels,
output wire [PORTS-1:0] diff_pair_po,
output wire [PORTS-1:0] diff_pair_no,
output wire [PORTS-1:0] crt_out,
output wire [(32*PORTS)-1:0] output_channels
);
genvar index;
localparam PORTS = 5;
wire [31:0] inport_data [PORTS-1:0];
wire [PORTS-1:0] port_rqs [PORTS-1:0];
wire pe_rqs [PORTS-1:0];
wire arb_ack [PORTS-1:0];
wire [PORTS-1:0] rqs2arbiters [PORTS-1:0];
wire [PORTS-1:0] xbar_cfg_vector [PORTS-1:0];
wire [PORTS-1:0] arb_ackf [PORTS-1:0];
wire [31:0] xbar_data [PORTS-1:0];
wire [PORTS-1:0] ack2inports;
wire [31:0] output_channel [PORTS-1:0];
wire [31:0] input_data [PORTS-1:0];
generate
for(index=0; index<PORTS; index=index+1)
begin
assign input_data[index] = input_channels[(index*32)+31:index*32];
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: inport_inst
inport #(.XCOR(XCOR), .YCOR(YCOR))
inport (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_pi[index]),
.diff_pair_n(diff_pair_ni[index]),
.arb_ack(ack2inports[index]),
.input_channel(input_data[index]),
.channel_data(inport_data[index]),
.crt_out(crt_out[index]),
.port_rqs(port_rqs[index])
);
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: rqs2arbiters_inst
assign rqs2arbiters[index] = { port_rqs[0][index],
port_rqs[1][index],
port_rqs[2][index],
port_rqs[3][index],
port_rqs[4][index]
};
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: ccs_inst
ccs ccs (
.clk(clk),
.credit_in(crt_in [index]),
.port_rqs(rqs2arbiters[index]),
.arb_ack(arb_ackf[index]),
.xbar_cfg_vector(xbar_cfg_vector[index])
);
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: ack2inports_inst
assign ack2inports[index] = arb_ackf[0][index] |
arb_ackf[1][index] |
arb_ackf[2][index] |
arb_ackf[3][index] |
arb_ackf[4][index];
end
endgenerate
switch_fabric switch_fabric (
.dinA(inport_data[0]),
.dinB(inport_data[1]),
.dinC(inport_data[2]),
.dinD(inport_data[3]),
.dinE(inport_data[4]),
.sf_cfg_vecA(xbar_cfg_vector[0]),
.sf_cfg_vecB(xbar_cfg_vector[1]),
.sf_cfg_vecC(xbar_cfg_vector[2]),
.sf_cfg_vecD(xbar_cfg_vector[3]),
.sf_cfg_vecE(xbar_cfg_vector[4]),
.doutA(xbar_data[0]),
.doutB(xbar_data[1]),
.doutC(xbar_data[2]),
.doutD(xbar_data[3]),
.doutE(xbar_data[4])
);
generate
for (index=0; index<PORTS; index=index+1)
begin: outport_inst
outport outport (
.clk(clk),
.rst(rst),
.arb_ack(ack2inports[index]),
.xbar_data(xbar_data[index]),
.diff_pair_p(diff_pair_po[index]),
.diff_pair_n(diff_pair_no[index]),
.output_channel(output_channel[index])
);
end
endgenerate
assign output_channels = { output_channel[4],
output_channel[3],
output_channel[2],
output_channel[1],
output_channel[0]
};
endmodule | module hexa #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire [PORTS-1:0] diff_pair_pi,
input wire [PORTS-1:0] diff_pair_ni,
input wire [PORTS-1:0] crt_in,
input wire [(32*PORTS)-1:0] input_channels,
output wire [PORTS-1:0] diff_pair_po,
output wire [PORTS-1:0] diff_pair_no,
output wire [PORTS-1:0] crt_out,
output wire [(32*PORTS)-1:0] output_channels
); |
genvar index;
localparam PORTS = 5;
wire [31:0] inport_data [PORTS-1:0];
wire [PORTS-1:0] port_rqs [PORTS-1:0];
wire pe_rqs [PORTS-1:0];
wire arb_ack [PORTS-1:0];
wire [PORTS-1:0] rqs2arbiters [PORTS-1:0];
wire [PORTS-1:0] xbar_cfg_vector [PORTS-1:0];
wire [PORTS-1:0] arb_ackf [PORTS-1:0];
wire [31:0] xbar_data [PORTS-1:0];
wire [PORTS-1:0] ack2inports;
wire [31:0] output_channel [PORTS-1:0];
wire [31:0] input_data [PORTS-1:0];
generate
for(index=0; index<PORTS; index=index+1)
begin
assign input_data[index] = input_channels[(index*32)+31:index*32];
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: inport_inst
inport #(.XCOR(XCOR), .YCOR(YCOR))
inport (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_pi[index]),
.diff_pair_n(diff_pair_ni[index]),
.arb_ack(ack2inports[index]),
.input_channel(input_data[index]),
.channel_data(inport_data[index]),
.crt_out(crt_out[index]),
.port_rqs(port_rqs[index])
);
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: rqs2arbiters_inst
assign rqs2arbiters[index] = { port_rqs[0][index],
port_rqs[1][index],
port_rqs[2][index],
port_rqs[3][index],
port_rqs[4][index]
};
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: ccs_inst
ccs ccs (
.clk(clk),
.credit_in(crt_in [index]),
.port_rqs(rqs2arbiters[index]),
.arb_ack(arb_ackf[index]),
.xbar_cfg_vector(xbar_cfg_vector[index])
);
end
endgenerate
generate
for (index=0; index<PORTS; index=index+1)
begin: ack2inports_inst
assign ack2inports[index] = arb_ackf[0][index] |
arb_ackf[1][index] |
arb_ackf[2][index] |
arb_ackf[3][index] |
arb_ackf[4][index];
end
endgenerate
switch_fabric switch_fabric (
.dinA(inport_data[0]),
.dinB(inport_data[1]),
.dinC(inport_data[2]),
.dinD(inport_data[3]),
.dinE(inport_data[4]),
.sf_cfg_vecA(xbar_cfg_vector[0]),
.sf_cfg_vecB(xbar_cfg_vector[1]),
.sf_cfg_vecC(xbar_cfg_vector[2]),
.sf_cfg_vecD(xbar_cfg_vector[3]),
.sf_cfg_vecE(xbar_cfg_vector[4]),
.doutA(xbar_data[0]),
.doutB(xbar_data[1]),
.doutC(xbar_data[2]),
.doutD(xbar_data[3]),
.doutE(xbar_data[4])
);
generate
for (index=0; index<PORTS; index=index+1)
begin: outport_inst
outport outport (
.clk(clk),
.rst(rst),
.arb_ack(ack2inports[index]),
.xbar_data(xbar_data[index]),
.diff_pair_p(diff_pair_po[index]),
.diff_pair_n(diff_pair_no[index]),
.output_channel(output_channel[index])
);
end
endgenerate
assign output_channels = { output_channel[4],
output_channel[3],
output_channel[2],
output_channel[1],
output_channel[0]
};
endmodule | 0 |
140,866 | data/full_repos/permissive/92618161/rtl/inport.v | 92,618,161 | inport.v | v | 126 | 81 | [] | [] | [] | [(7, 125)] | null | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/inport.v:51: Cannot find file containing module: 'iphu'\n iphu iphu\n ^~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/iphu\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/iphu.v\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/iphu.sv\n iphu\n iphu.v\n iphu.sv\n obj_dir/iphu\n obj_dir/iphu.v\n obj_dir/iphu.sv\n%Error: data/full_repos/permissive/92618161/rtl/inport.v:70: Cannot find file containing module: 'ipcu'\n ipcu ipcu \n ^~~~\n%Error: data/full_repos/permissive/92618161/rtl/inport.v:90: Cannot find file containing module: 'fifo'\n fifo fifo \n ^~~~\n%Error: data/full_repos/permissive/92618161/rtl/inport.v:111: Cannot find file containing module: 'rgu'\n rgu #(.XCOR(XCOR), .YCOR(YCOR)) \n ^~~\n%Error: Exiting due to 4 error(s)\n" | 309,800 | module | module inport #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire diff_pair_p,
input wire diff_pair_n,
input wire arb_ack,
input wire [31:0] input_channel,
output wire [31:0] channel_data,
output wire crt_out,
output wire [PORTS-1:0] port_rqs
);
localparam PORTS = 5;
wire pipe_en;
wire wr_strobe;
wire rd_strobe;
wire addr_src;
wire rqs_strobe;
wire [31:0] rd_data;
iphu iphu
(
.clk(clk),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.pipe_en(pipe_en)
);
ipcu ipcu
(
.clk(clk),
.rst(rst),
.arb_ack(arb_ack),
.pipe_en(pipe_en),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rqs_strobe(rqs_strobe),
.crt_out(crt_out)
);
fifo fifo
(
.clk(clk),
.rst(rst),
.wr_data(input_channel),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rd_data(channel_data)
);
rgu #(.XCOR(XCOR), .YCOR(YCOR))
rgu
(
.clk(clk),
.rst(rst),
.rqs_strobe(rqs_strobe),
.arb_ack(arb_ack),
.addr(channel_data[31:24]),
.rqs_vector(port_rqs)
);
endmodule | module inport #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire diff_pair_p,
input wire diff_pair_n,
input wire arb_ack,
input wire [31:0] input_channel,
output wire [31:0] channel_data,
output wire crt_out,
output wire [PORTS-1:0] port_rqs
); |
localparam PORTS = 5;
wire pipe_en;
wire wr_strobe;
wire rd_strobe;
wire addr_src;
wire rqs_strobe;
wire [31:0] rd_data;
iphu iphu
(
.clk(clk),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.pipe_en(pipe_en)
);
ipcu ipcu
(
.clk(clk),
.rst(rst),
.arb_ack(arb_ack),
.pipe_en(pipe_en),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rqs_strobe(rqs_strobe),
.crt_out(crt_out)
);
fifo fifo
(
.clk(clk),
.rst(rst),
.wr_data(input_channel),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rd_data(channel_data)
);
rgu #(.XCOR(XCOR), .YCOR(YCOR))
rgu
(
.clk(clk),
.rst(rst),
.rqs_strobe(rqs_strobe),
.arb_ack(arb_ack),
.addr(channel_data[31:24]),
.rqs_vector(port_rqs)
);
endmodule | 0 |
140,867 | data/full_repos/permissive/92618161/rtl/ipcu.v | 92,618,161 | ipcu.v | v | 222 | 73 | [] | [] | [] | [(9, 221)] | null | data/verilator_xmls/45f809b8-91f8-44dd-877b-d9bb42d1c7c5.xml | null | 309,801 | module | module ipcu
(
input wire clk,
input wire rst,
input wire arb_ack,
input wire pipe_en,
output wire wr_strobe,
output wire rd_strobe,
output wire rqs_strobe,
output wire crt_out
);
localparam IDLE=2'b00;
localparam NEW =2'b01;
localparam ACK =2'b01;
localparam PUSH=2'b10;
localparam PULL=2'b10;
reg [1:0] istate_next;
reg [1:0] istate_reg;
reg [1:0] ostate_next;
reg [1:0] ostate_reg;
wire icntr_sub;
wire icntr_rst;
reg [1:0] icntr_reg=2'b11;
wire ocntr_sub;
wire ocntr_rst;
reg [1:0] ocntr_reg=2'b11;
wire fcntr_inc;
wire fcntr_sub;
wire fcntr_rst;
reg [2:0] fcntr_reg =3'b000;
reg [2:0] fcntr_next=3'b000;
always @(posedge clk)
if (icntr_rst)
icntr_reg<=2'b11;
else if (icntr_sub)
icntr_reg<=icntr_reg-1'b1;
else
icntr_reg<=icntr_reg;
assign icntr_rst =(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
assign icntr_sub =(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==PUSH) ? 1'b1 :
1'b0;
always @(posedge clk)
if (rst)
istate_reg<=IDLE;
else
istate_reg<=istate_next;
always @(*) begin
istate_next=istate_reg;
case (istate_reg)
IDLE:
if (pipe_en)
istate_next=NEW;
NEW:
istate_next=PUSH;
PUSH:
if (~|icntr_reg && ~pipe_en)
istate_next=IDLE;
else if (~|icntr_reg && pipe_en)
istate_next=NEW;
else
istate_next=PUSH;
endcase
end
assign wr_strobe=(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
always @(posedge clk)
if (ocntr_rst)
ocntr_reg<=2'b11;
else if (ocntr_sub)
ocntr_reg<=ocntr_reg-1'b1;
else
ocntr_reg<=ocntr_reg;
assign ocntr_rst=(ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
assign ocntr_sub=(ostate_reg==ACK && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==PULL) ? 1'b1 :
1'b0;
always @(posedge clk)
if (rst)
ostate_reg<=IDLE;
else
ostate_reg<=ostate_next;
always @(*) begin
ostate_next=ostate_reg;
case (ostate_reg)
IDLE:
if (arb_ack)
ostate_next=ACK;
ACK:
ostate_next=PULL;
PULL:
if (~|ocntr_reg && ~arb_ack)
ostate_next=IDLE;
else if (~|ocntr_reg && arb_ack)
ostate_next=ACK;
else
ostate_next=PULL;
endcase
end
assign crt_out = (ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
assign rd_strobe = (ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==ACK && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
always @(posedge clk)
fcntr_reg<=fcntr_next;
assign fcntr_inc=(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
assign fcntr_sub=(ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
always @(*)
case({fcntr_inc, fcntr_sub})
2'b00:
fcntr_next = fcntr_reg;
2'b01:
fcntr_next = fcntr_reg - 1'b1;
2'b10:
fcntr_next = fcntr_reg + 1'b1;
2'b11:
fcntr_next = fcntr_reg;
endcase
assign rqs_strobe=(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(~|ocntr_reg && |fcntr_reg) ? 1'b1 :
1'b0;
endmodule | module ipcu
(
input wire clk,
input wire rst,
input wire arb_ack,
input wire pipe_en,
output wire wr_strobe,
output wire rd_strobe,
output wire rqs_strobe,
output wire crt_out
); |
localparam IDLE=2'b00;
localparam NEW =2'b01;
localparam ACK =2'b01;
localparam PUSH=2'b10;
localparam PULL=2'b10;
reg [1:0] istate_next;
reg [1:0] istate_reg;
reg [1:0] ostate_next;
reg [1:0] ostate_reg;
wire icntr_sub;
wire icntr_rst;
reg [1:0] icntr_reg=2'b11;
wire ocntr_sub;
wire ocntr_rst;
reg [1:0] ocntr_reg=2'b11;
wire fcntr_inc;
wire fcntr_sub;
wire fcntr_rst;
reg [2:0] fcntr_reg =3'b000;
reg [2:0] fcntr_next=3'b000;
always @(posedge clk)
if (icntr_rst)
icntr_reg<=2'b11;
else if (icntr_sub)
icntr_reg<=icntr_reg-1'b1;
else
icntr_reg<=icntr_reg;
assign icntr_rst =(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
assign icntr_sub =(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==PUSH) ? 1'b1 :
1'b0;
always @(posedge clk)
if (rst)
istate_reg<=IDLE;
else
istate_reg<=istate_next;
always @(*) begin
istate_next=istate_reg;
case (istate_reg)
IDLE:
if (pipe_en)
istate_next=NEW;
NEW:
istate_next=PUSH;
PUSH:
if (~|icntr_reg && ~pipe_en)
istate_next=IDLE;
else if (~|icntr_reg && pipe_en)
istate_next=NEW;
else
istate_next=PUSH;
endcase
end
assign wr_strobe=(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==PUSH) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
always @(posedge clk)
if (ocntr_rst)
ocntr_reg<=2'b11;
else if (ocntr_sub)
ocntr_reg<=ocntr_reg-1'b1;
else
ocntr_reg<=ocntr_reg;
assign ocntr_rst=(ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
assign ocntr_sub=(ostate_reg==ACK && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==PULL) ? 1'b1 :
1'b0;
always @(posedge clk)
if (rst)
ostate_reg<=IDLE;
else
ostate_reg<=ostate_next;
always @(*) begin
ostate_next=ostate_reg;
case (ostate_reg)
IDLE:
if (arb_ack)
ostate_next=ACK;
ACK:
ostate_next=PULL;
PULL:
if (~|ocntr_reg && ~arb_ack)
ostate_next=IDLE;
else if (~|ocntr_reg && arb_ack)
ostate_next=ACK;
else
ostate_next=PULL;
endcase
end
assign crt_out = (ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
assign rd_strobe = (ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==ACK && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==PULL) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
always @(posedge clk)
fcntr_reg<=fcntr_next;
assign fcntr_inc=(istate_reg==IDLE && istate_next==NEW) ? 1'b1 :
(istate_reg==PUSH && istate_next==NEW) ? 1'b1 :
1'b0;
assign fcntr_sub=(ostate_reg==IDLE && ostate_next==ACK) ? 1'b1 :
(ostate_reg==PULL && ostate_next==ACK) ? 1'b1 :
1'b0;
always @(*)
case({fcntr_inc, fcntr_sub})
2'b00:
fcntr_next = fcntr_reg;
2'b01:
fcntr_next = fcntr_reg - 1'b1;
2'b10:
fcntr_next = fcntr_reg + 1'b1;
2'b11:
fcntr_next = fcntr_reg;
endcase
assign rqs_strobe=(istate_reg==NEW && istate_next==PUSH) ? 1'b1 :
(~|ocntr_reg && |fcntr_reg) ? 1'b1 :
1'b0;
endmodule | 0 |
140,868 | data/full_repos/permissive/92618161/rtl/iphu.v | 92,618,161 | iphu.v | v | 42 | 109 | [] | [] | [] | [(8, 41)] | null | data/verilator_xmls/46ead019-894b-4973-af8a-0a2ba4e3037d.xml | null | 309,802 | module | module iphu
(
input wire clk,
input wire diff_pair_p,
input wire diff_pair_n,
output wire pipe_en
);
reg diff_pair_p_reg = 1'b1;
reg diff_pair_n_reg = 1'b0;
wire pipe_enable;
always @(posedge clk)
if (pipe_enable)
begin
diff_pair_p_reg <= ~diff_pair_p_reg;
diff_pair_n_reg <= ~diff_pair_n_reg;
end
assign pipe_enable = ((diff_pair_p ^ diff_pair_p_reg) & (diff_pair_n ^ diff_pair_n_reg)) ? 1'b1 : 1'b0;
assign pipe_en = pipe_enable;
endmodule | module iphu
(
input wire clk,
input wire diff_pair_p,
input wire diff_pair_n,
output wire pipe_en
); |
reg diff_pair_p_reg = 1'b1;
reg diff_pair_n_reg = 1'b0;
wire pipe_enable;
always @(posedge clk)
if (pipe_enable)
begin
diff_pair_p_reg <= ~diff_pair_p_reg;
diff_pair_n_reg <= ~diff_pair_n_reg;
end
assign pipe_enable = ((diff_pair_p ^ diff_pair_p_reg) & (diff_pair_n ^ diff_pair_n_reg)) ? 1'b1 : 1'b0;
assign pipe_en = pipe_enable;
endmodule | 0 |
140,869 | data/full_repos/permissive/92618161/rtl/ophu.v | 92,618,161 | ophu.v | v | 47 | 50 | [] | [] | [] | [(10, 46)] | null | data/verilator_xmls/0f1a0670-7b7d-4618-a67d-8919fbd6cf0c.xml | null | 309,803 | module | module ophu
(
input wire clk,
input wire arb_ack,
output wire diff_pair_p,
output wire diff_pair_n
);
reg diff_pair_p_reg = 1'b1;
reg diff_pair_n_reg = 1'b0;
always @(posedge clk)
if (arb_ack)
begin
diff_pair_p_reg <= ~diff_pair_p_reg;
diff_pair_n_reg <= ~diff_pair_n_reg;
end
else
begin
diff_pair_p_reg <= diff_pair_p_reg;
diff_pair_n_reg <= diff_pair_n_reg;
end
assign diff_pair_p = diff_pair_p_reg;
assign diff_pair_n = diff_pair_n_reg;
endmodule | module ophu
(
input wire clk,
input wire arb_ack,
output wire diff_pair_p,
output wire diff_pair_n
); |
reg diff_pair_p_reg = 1'b1;
reg diff_pair_n_reg = 1'b0;
always @(posedge clk)
if (arb_ack)
begin
diff_pair_p_reg <= ~diff_pair_p_reg;
diff_pair_n_reg <= ~diff_pair_n_reg;
end
else
begin
diff_pair_p_reg <= diff_pair_p_reg;
diff_pair_n_reg <= diff_pair_n_reg;
end
assign diff_pair_p = diff_pair_p_reg;
assign diff_pair_n = diff_pair_n_reg;
endmodule | 0 |
140,870 | data/full_repos/permissive/92618161/rtl/outport.v | 92,618,161 | outport.v | v | 50 | 43 | [] | [] | [] | [(8, 49)] | null | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/outport.v:31: Cannot find file containing module: 'ophu'\nophu ophu (\n^~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/ophu\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/ophu.v\n data/full_repos/permissive/92618161/rtl,data/full_repos/permissive/92618161/ophu.sv\n ophu\n ophu.v\n ophu.sv\n obj_dir/ophu\n obj_dir/ophu.v\n obj_dir/ophu.sv\n%Error: Exiting due to 1 error(s)\n" | 309,804 | module | module outport
(
input wire clk,
input wire rst,
input wire arb_ack,
input wire [31:0] xbar_data,
output wire diff_pair_p,
output wire diff_pair_n,
output wire [31:0] output_channel
);
reg [31:0] xbar_data_reg;
ophu ophu (
.clk(clk),
.arb_ack(arb_ack),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n)
);
always @(posedge clk)
xbar_data_reg <= xbar_data;
assign output_channel = xbar_data_reg;
endmodule | module outport
(
input wire clk,
input wire rst,
input wire arb_ack,
input wire [31:0] xbar_data,
output wire diff_pair_p,
output wire diff_pair_n,
output wire [31:0] output_channel
); |
reg [31:0] xbar_data_reg;
ophu ophu (
.clk(clk),
.arb_ack(arb_ack),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n)
);
always @(posedge clk)
xbar_data_reg <= xbar_data;
assign output_channel = xbar_data_reg;
endmodule | 0 |
140,871 | data/full_repos/permissive/92618161/rtl/rgu.v | 92,618,161 | rgu.v | v | 96 | 73 | [] | [] | [] | [(9, 95)] | null | data/verilator_xmls/4213392f-709f-4a74-9cf9-3c50802ac103.xml | null | 309,805 | module | module rgu #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire rqs_strobe,
input wire arb_ack,
input wire [7:0] addr,
output wire [4:0] rqs_vector
);
localparam NONE = 5'b00000;
localparam XPOS = 5'b00001;
localparam XNEG = 5'b00010;
localparam YPOS = 5'b00100;
localparam YNEG = 5'b01000;
localparam PE = 5'b10000;
wire [4:0] sub_x;
wire [4:0] sub_y;
wire zero_x;
wire zero_y;
reg [4:0] rqs_next;
reg [4:0] rqs_reg = 5'b00000;
assign sub_x = addr[7:4] - XCOR;
assign sub_y = addr[3:0] - YCOR;
assign zero_x = ~|sub_x;
assign zero_y = ~|sub_y;
always @(*) begin
rqs_next = NONE;
case({zero_x, zero_y, sub_x[4], sub_y[4]})
4'b1100:
rqs_next = PE;
4'b0000:
rqs_next = XPOS;
4'b0001:
rqs_next = XPOS;
4'b0100:
rqs_next = XPOS;
4'b0010:
rqs_next = XNEG;
4'b0011:
rqs_next = XNEG;
4'b0110:
rqs_next = XNEG;
4'b1000:
rqs_next = YPOS;
4'b1001:
rqs_next = YNEG;
default:
rqs_next = NONE;
endcase
end
always @(posedge clk)
if (arb_ack)
rqs_reg = 5'b00000;
else if (rqs_strobe)
rqs_reg = rqs_next;
assign rqs_vector = rqs_reg;
endmodule | module rgu #( parameter XCOR = 2,
parameter YCOR = 2
)
(
input wire clk,
input wire rst,
input wire rqs_strobe,
input wire arb_ack,
input wire [7:0] addr,
output wire [4:0] rqs_vector
); |
localparam NONE = 5'b00000;
localparam XPOS = 5'b00001;
localparam XNEG = 5'b00010;
localparam YPOS = 5'b00100;
localparam YNEG = 5'b01000;
localparam PE = 5'b10000;
wire [4:0] sub_x;
wire [4:0] sub_y;
wire zero_x;
wire zero_y;
reg [4:0] rqs_next;
reg [4:0] rqs_reg = 5'b00000;
assign sub_x = addr[7:4] - XCOR;
assign sub_y = addr[3:0] - YCOR;
assign zero_x = ~|sub_x;
assign zero_y = ~|sub_y;
always @(*) begin
rqs_next = NONE;
case({zero_x, zero_y, sub_x[4], sub_y[4]})
4'b1100:
rqs_next = PE;
4'b0000:
rqs_next = XPOS;
4'b0001:
rqs_next = XPOS;
4'b0100:
rqs_next = XPOS;
4'b0010:
rqs_next = XNEG;
4'b0011:
rqs_next = XNEG;
4'b0110:
rqs_next = XNEG;
4'b1000:
rqs_next = YPOS;
4'b1001:
rqs_next = YNEG;
default:
rqs_next = NONE;
endcase
end
always @(posedge clk)
if (arb_ack)
rqs_reg = 5'b00000;
else if (rqs_strobe)
rqs_reg = rqs_next;
assign rqs_vector = rqs_reg;
endmodule | 0 |
140,872 | data/full_repos/permissive/92618161/rtl/switch_fabric.v | 92,618,161 | switch_fabric.v | v | 109 | 39 | [] | [] | [] | [(8, 108)] | null | data/verilator_xmls/2d030152-d75c-498f-a37e-d47a979d4b91.xml | null | 309,806 | module | module switch_fabric
(
input wire [31:0] dinA,
input wire [31:0] dinB,
input wire [31:0] dinC,
input wire [31:0] dinD,
input wire [31:0] dinE,
input wire [4:0] sf_cfg_vecA,
input wire [4:0] sf_cfg_vecB,
input wire [4:0] sf_cfg_vecC,
input wire [4:0] sf_cfg_vecD,
input wire [4:0] sf_cfg_vecE,
output reg [31:0] doutA,
output reg [31:0] doutB,
output reg [31:0] doutC,
output reg [31:0] doutD,
output reg [31:0] doutE
);
localparam RQS0 = 5'b00001;
localparam RQS1 = 5'b00010;
localparam RQS2 = 5'b00100;
localparam RQS3 = 5'b01000;
localparam RQS4 = 5'b10000;
always @(*) begin
doutA = {32{1'b0}};
case (sf_cfg_vecA)
RQS0: doutA = dinA;
RQS1: doutA = dinB;
RQS2: doutA = dinC;
RQS3: doutA = dinD;
RQS4: doutA = dinE;
endcase
end
always @(*) begin
doutB = {32{1'b0}};
case (sf_cfg_vecB)
RQS0: doutB = dinA;
RQS1: doutB = dinB;
RQS2: doutB = dinC;
RQS3: doutB = dinD;
RQS4: doutB = dinE;
endcase
end
always @(*) begin
doutC = {32{1'b0}};
case (sf_cfg_vecC)
RQS0: doutC = dinA;
RQS1: doutC = dinB;
RQS2: doutC = dinC;
RQS3: doutC = dinD;
RQS4: doutC = dinE;
endcase
end
always @(*) begin
doutD = {32{1'b0}};
case (sf_cfg_vecD)
RQS0: doutD = dinA;
RQS1: doutD = dinB;
RQS2: doutD = dinC;
RQS3: doutD = dinD;
RQS4: doutD = dinE;
endcase
end
always @(*) begin
doutE = {32{1'b0}};
case (sf_cfg_vecE)
RQS0: doutE = dinA;
RQS1: doutE = dinB;
RQS2: doutE = dinC;
RQS3: doutE = dinD;
RQS4: doutE = dinE;
endcase
end
endmodule | module switch_fabric
(
input wire [31:0] dinA,
input wire [31:0] dinB,
input wire [31:0] dinC,
input wire [31:0] dinD,
input wire [31:0] dinE,
input wire [4:0] sf_cfg_vecA,
input wire [4:0] sf_cfg_vecB,
input wire [4:0] sf_cfg_vecC,
input wire [4:0] sf_cfg_vecD,
input wire [4:0] sf_cfg_vecE,
output reg [31:0] doutA,
output reg [31:0] doutB,
output reg [31:0] doutC,
output reg [31:0] doutD,
output reg [31:0] doutE
); |
localparam RQS0 = 5'b00001;
localparam RQS1 = 5'b00010;
localparam RQS2 = 5'b00100;
localparam RQS3 = 5'b01000;
localparam RQS4 = 5'b10000;
always @(*) begin
doutA = {32{1'b0}};
case (sf_cfg_vecA)
RQS0: doutA = dinA;
RQS1: doutA = dinB;
RQS2: doutA = dinC;
RQS3: doutA = dinD;
RQS4: doutA = dinE;
endcase
end
always @(*) begin
doutB = {32{1'b0}};
case (sf_cfg_vecB)
RQS0: doutB = dinA;
RQS1: doutB = dinB;
RQS2: doutB = dinC;
RQS3: doutB = dinD;
RQS4: doutB = dinE;
endcase
end
always @(*) begin
doutC = {32{1'b0}};
case (sf_cfg_vecC)
RQS0: doutC = dinA;
RQS1: doutC = dinB;
RQS2: doutC = dinC;
RQS3: doutC = dinD;
RQS4: doutC = dinE;
endcase
end
always @(*) begin
doutD = {32{1'b0}};
case (sf_cfg_vecD)
RQS0: doutD = dinA;
RQS1: doutD = dinB;
RQS2: doutD = dinC;
RQS3: doutD = dinD;
RQS4: doutD = dinE;
endcase
end
always @(*) begin
doutE = {32{1'b0}};
case (sf_cfg_vecE)
RQS0: doutE = dinA;
RQS1: doutE = dinB;
RQS2: doutE = dinC;
RQS3: doutE = dinD;
RQS4: doutE = dinE;
endcase
end
endmodule | 0 |
140,873 | data/full_repos/permissive/92618161/rtl/tests/arbiter_tb.v | 92,618,161 | arbiter_tb.v | v | 38 | 41 | [] | [] | [] | null | line:31: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/arbiter_tb.v:18: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/arbiter_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/arbiter_tb.v:33: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,807 | module | module arbiter_tb();
reg clk;
reg credit_in;
arbiter UUT (
.clk(clk),
.credit_in(credit_in)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
credit_in = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module arbiter_tb(); |
reg clk;
reg credit_in;
arbiter UUT (
.clk(clk),
.credit_in(credit_in)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
credit_in = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,874 | data/full_repos/permissive/92618161/rtl/tests/fifo_tb.v | 92,618,161 | fifo_tb.v | v | 48 | 41 | [] | [] | [] | null | line:41: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/fifo_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/fifo_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/fifo_tb.v:43: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,808 | module | module fifo_tb();
reg clk;
reg rst;
reg wr_strobe;
reg rd_strobe;
wire full;
wire empty;
fifo UUT (
.clk(clk),
.rst(rst),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.full(full),
.empty(empty)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
wr_strobe = 0;
rd_strobe = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module fifo_tb(); |
reg clk;
reg rst;
reg wr_strobe;
reg rd_strobe;
wire full;
wire empty;
fifo UUT (
.clk(clk),
.rst(rst),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.full(full),
.empty(empty)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
wr_strobe = 0;
rd_strobe = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,875 | data/full_repos/permissive/92618161/rtl/tests/inOut_port.v | 92,618,161 | inOut_port.v | v | 71 | 41 | [] | [] | [] | [(3, 69)] | null | null | 1: b"%Error: data/full_repos/permissive/92618161/rtl/tests/inOut_port.v:29: Cannot find file containing module: 'inport'\ninport inport (\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/inport\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/inport.v\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/inport.sv\n inport\n inport.v\n inport.sv\n obj_dir/inport\n obj_dir/inport.v\n obj_dir/inport.sv\n%Error: data/full_repos/permissive/92618161/rtl/tests/inOut_port.v:42: Cannot find file containing module: 'arbiter'\narbiter arbiter\n^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/tests/inOut_port.v:55: Cannot find file containing module: 'outport'\noutport outport (\n^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 309,810 | module | module inOut_port
(
input wire clk,
input wire rst,
input wire diff_pair_p_in,
input wire diff_pair_n_in,
input wire [31:0] input_channel,
input wire credit_in,
output wire [31:0] data_out,
output wire crt_out,
output wire diff_pair_p_out,
output wire diff_pair_n_out,
output wire [3:0] xbar_cfg_vector
);
wire [3:0] arb_ack;
wire [31:0] channel_data;
wire [31:0] xbar_data;
wire [3:0] port_rqs;
wire pe_rqs;
wire ack;
inport inport (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_p_in),
.diff_pair_n(diff_pair_n_in),
.arb_ack(ack),
.input_channel(input_channel),
.channel_data(xbar_data),
.crt_out(crt_out),
.port_rqs(port_rqs),
.pe_rqs(pe_rqs)
);
arbiter arbiter
(
.clk(clk),
.credit_in(credit_in),
.port_rqs(port_rqs),
.arb_ack(arb_ack),
.xbar_cfg_vector(xbar_cfg_vector)
);
outport outport (
.clk(clk),
.rst(rst),
.arb_ack(ack),
.xbar_data(xbar_data),
.diff_pair_p(diff_pair_p_out),
.diff_pair_n(diff_pair_n_out),
.output_channel(data_out)
);
assign ack = |arb_ack;
endmodule | module inOut_port
(
input wire clk,
input wire rst,
input wire diff_pair_p_in,
input wire diff_pair_n_in,
input wire [31:0] input_channel,
input wire credit_in,
output wire [31:0] data_out,
output wire crt_out,
output wire diff_pair_p_out,
output wire diff_pair_n_out,
output wire [3:0] xbar_cfg_vector
); |
wire [3:0] arb_ack;
wire [31:0] channel_data;
wire [31:0] xbar_data;
wire [3:0] port_rqs;
wire pe_rqs;
wire ack;
inport inport (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_p_in),
.diff_pair_n(diff_pair_n_in),
.arb_ack(ack),
.input_channel(input_channel),
.channel_data(xbar_data),
.crt_out(crt_out),
.port_rqs(port_rqs),
.pe_rqs(pe_rqs)
);
arbiter arbiter
(
.clk(clk),
.credit_in(credit_in),
.port_rqs(port_rqs),
.arb_ack(arb_ack),
.xbar_cfg_vector(xbar_cfg_vector)
);
outport outport (
.clk(clk),
.rst(rst),
.arb_ack(ack),
.xbar_data(xbar_data),
.diff_pair_p(diff_pair_p_out),
.diff_pair_n(diff_pair_n_out),
.output_channel(data_out)
);
assign ack = |arb_ack;
endmodule | 0 |
140,876 | data/full_repos/permissive/92618161/rtl/tests/inOut_port_tb.v | 92,618,161 | inOut_port_tb.v | v | 89 | 44 | [] | [] | [] | null | line:50: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inOut_port_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inOut_port_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inOut_port_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #(2000)\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/inOut_port_tb.v:83: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,811 | module | module inOut_port_tb();
reg clk;
reg rst;
reg diff_pair_p_in;
reg diff_pair_n_in;
reg [31:0] input_channel;
wire [31:0] data_out;
reg credit_in;
wire crt_out;
wire diff_pair_p_out;
wire diff_pair_n_out;
wire [3:0] xbar_cfg_vector;
inOut_port UUT (
.clk(clk),
.rst(rst),
.diff_pair_p_in(diff_pair_p_in),
.diff_pair_n_in(diff_pair_n_in),
.input_channel(input_channel),
.data_out(data_out),
.credit_in(credit_in),
.diff_pair_p_out(diff_pair_p_out),
.diff_pair_n_out(diff_pair_n_out),
.crt_out(crt_out),
.xbar_cfg_vector(xbar_cfg_vector)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 1;
diff_pair_p_in = 1;
diff_pair_n_in = 0;
input_channel = 0;
credit_in = 0;
repeat(20)
posEdge();
rst = 0;
repeat(4)
posEdge();
diff_pair_p_in=~diff_pair_p_in;
diff_pair_n_in=~diff_pair_n_in;
input_channel = 32'h11000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
repeat(20)
posEdge();
credit_in = 1;
posEdge();
credit_in = 0;
#(2000)
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module inOut_port_tb(); |
reg clk;
reg rst;
reg diff_pair_p_in;
reg diff_pair_n_in;
reg [31:0] input_channel;
wire [31:0] data_out;
reg credit_in;
wire crt_out;
wire diff_pair_p_out;
wire diff_pair_n_out;
wire [3:0] xbar_cfg_vector;
inOut_port UUT (
.clk(clk),
.rst(rst),
.diff_pair_p_in(diff_pair_p_in),
.diff_pair_n_in(diff_pair_n_in),
.input_channel(input_channel),
.data_out(data_out),
.credit_in(credit_in),
.diff_pair_p_out(diff_pair_p_out),
.diff_pair_n_out(diff_pair_n_out),
.crt_out(crt_out),
.xbar_cfg_vector(xbar_cfg_vector)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 1;
diff_pair_p_in = 1;
diff_pair_n_in = 0;
input_channel = 0;
credit_in = 0;
repeat(20)
posEdge();
rst = 0;
repeat(4)
posEdge();
diff_pair_p_in=~diff_pair_p_in;
diff_pair_n_in=~diff_pair_n_in;
input_channel = 32'h11000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
repeat(20)
posEdge();
credit_in = 1;
posEdge();
credit_in = 0;
#(2000)
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,877 | data/full_repos/permissive/92618161/rtl/tests/inport_tb.v | 92,618,161 | inport_tb.v | v | 193 | 81 | [] | [] | [] | null | line:47: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inport_tb.v:34: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inport_tb.v:36: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/inport_tb.v:164: Unsupported: Ignoring delay on this delayed statement.\n #(200)\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/inport_tb.v:171: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/inport_tb.v:176: syntax error, unexpected package, expecting TYPE-IDENTIFIER\ntask package();\n ^~~~~~~\n%Error: Cannot continue\n ... See the manual and https://verilator.org for more assistance.\n' | 309,812 | module | module inport_tb();
reg clk;
reg rst;
reg diff_pair_p;
reg diff_pair_n;
reg arb_ack;
reg [31:0] input_channel;
wire [31:0] channel_data;
wire crt_out;
wire [3:0] port_rqs;
wire pe_rqs;
inport UUT (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.arb_ack(arb_ack),
.input_channel(input_channel),
.channel_data(channel_data),
.crt_out(crt_out),
.port_rqs(port_rqs),
.pe_rqs(pe_rqs)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 1;
diff_pair_p = 1;
diff_pair_n = 0;
arb_ack = 0;
input_channel = 0;
repeat(20)
posEdge();
rst = 0;
repeat(4)
posEdge();
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'h33000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
arb_ack = 1;
input_channel = 32'h000000FF;
posEdge();
arb_ack = 0;
input_channel = 32'h00000000;
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'h11000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
#(200)
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
task package();
begin
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'hFF000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
end
endtask
endmodule | module inport_tb(); |
reg clk;
reg rst;
reg diff_pair_p;
reg diff_pair_n;
reg arb_ack;
reg [31:0] input_channel;
wire [31:0] channel_data;
wire crt_out;
wire [3:0] port_rqs;
wire pe_rqs;
inport UUT (
.clk(clk),
.rst(rst),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.arb_ack(arb_ack),
.input_channel(input_channel),
.channel_data(channel_data),
.crt_out(crt_out),
.port_rqs(port_rqs),
.pe_rqs(pe_rqs)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 1;
diff_pair_p = 1;
diff_pair_n = 0;
arb_ack = 0;
input_channel = 0;
repeat(20)
posEdge();
rst = 0;
repeat(4)
posEdge();
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'h33000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
arb_ack = 1;
input_channel = 32'h000000FF;
posEdge();
arb_ack = 0;
input_channel = 32'h00000000;
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'h11000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
#(200)
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
task package();
begin
diff_pair_p=~diff_pair_p;
diff_pair_n=~diff_pair_n;
input_channel = 32'hFF000000;
posEdge();
input_channel = 32'h00FF0000;
posEdge();
input_channel = 32'h0000FF00;
posEdge();
input_channel = 32'h000000FF;
posEdge();
input_channel = 32'h00000000;
end
endtask
endmodule | 0 |
140,878 | data/full_repos/permissive/92618161/rtl/tests/ipcu_tb.v | 92,618,161 | ipcu_tb.v | v | 52 | 41 | [] | [] | [] | null | line:45: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/ipcu_tb.v:30: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/ipcu_tb.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/ipcu_tb.v:47: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,813 | module | module ipcu_tb();
reg clk;
reg rst;
reg arb_ack;
reg pipe_en;
wire wr_strobe;
wire rd_strobe;
wire rqs_strobe;
wire crt_out;
ipcu UUT (
.clk(clk),
.rst(rst),
.arb_ack(arb_ack),
.pipe_en(pipe_en),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rqs_strobe(rqs_strobe),
.crt_out(crt_out)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
arb_ack = 0;
pipe_en = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module ipcu_tb(); |
reg clk;
reg rst;
reg arb_ack;
reg pipe_en;
wire wr_strobe;
wire rd_strobe;
wire rqs_strobe;
wire crt_out;
ipcu UUT (
.clk(clk),
.rst(rst),
.arb_ack(arb_ack),
.pipe_en(pipe_en),
.wr_strobe(wr_strobe),
.rd_strobe(rd_strobe),
.rqs_strobe(rqs_strobe),
.crt_out(crt_out)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
arb_ack = 0;
pipe_en = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,879 | data/full_repos/permissive/92618161/rtl/tests/iphu_tb.v | 92,618,161 | iphu_tb.v | v | 43 | 41 | [] | [] | [] | null | line:36: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/iphu_tb.v:22: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/iphu_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/iphu_tb.v:38: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,814 | module | module iphu_tb();
reg clk;
reg diff_pair_p;
reg diff_pair_n;
wire pipe_en;
iphu UUT (
.clk(clk),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.pipe_en(pipe_en)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
diff_pair_p = 0;
diff_pair_n = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module iphu_tb(); |
reg clk;
reg diff_pair_p;
reg diff_pair_n;
wire pipe_en;
iphu UUT (
.clk(clk),
.diff_pair_p(diff_pair_p),
.diff_pair_n(diff_pair_n),
.pipe_en(pipe_en)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
diff_pair_p = 0;
diff_pair_n = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,880 | data/full_repos/permissive/92618161/rtl/tests/rgu_tb.v | 92,618,161 | rgu_tb.v | v | 49 | 41 | [] | [] | [] | null | line:42: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/rgu_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/rgu_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #(10);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/rgu_tb.v:44: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,815 | module | module rgu_tb();
reg clk;
reg rst;
reg rqs_strobe;
reg arb_ack;
reg [7:0] addr;
wire [4:0] rqs_vector;
rgu UUT (
.clk(clk),
.rst(rst),
.rqs_strobe(rqs_strobe),
.arb_ack(arb_ack),
.addr(addr),
.rqs_vector(rqs_vector)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
rqs_strobe = 0;
arb_ack = 0;
addr = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | module rgu_tb(); |
reg clk;
reg rst;
reg rqs_strobe;
reg arb_ack;
reg [7:0] addr;
wire [4:0] rqs_vector;
rgu UUT (
.clk(clk),
.rst(rst),
.rqs_strobe(rqs_strobe),
.arb_ack(arb_ack),
.addr(addr),
.rqs_vector(rqs_vector)
);
always begin
clk = 1'b0;
#(10);
clk = 1'b1;
#(10);
end
initial begin
clk = 0;
rst = 0;
rqs_strobe = 0;
arb_ack = 0;
addr = 0;
$stop;
end
task posEdge();
begin
@(posedge clk)
#(2);
end
endtask
endmodule | 0 |
140,881 | data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v | 92,618,161 | switch_fabric_tb.v | v | 142 | 41 | [] | [] | [] | null | line:129: before: "$" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #(60);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:115: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:117: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:119: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:121: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:123: Unsupported: Ignoring delay on this delayed statement.\n #(20); \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:128: Unsupported: Ignoring delay on this delayed statement.\n #(500)\n ^\n%Error: data/full_repos/permissive/92618161/rtl/tests/switch_fabric_tb.v:23: Cannot find file containing module: \'switch_fabric\'\nswitch_fabric UUT (\n^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/switch_fabric\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/switch_fabric.v\n data/full_repos/permissive/92618161/rtl/tests,data/full_repos/permissive/92618161/switch_fabric.sv\n switch_fabric\n switch_fabric.v\n switch_fabric.sv\n obj_dir/switch_fabric\n obj_dir/switch_fabric.v\n obj_dir/switch_fabric.sv\n%Error: Exiting due to 1 error(s), 27 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,816 | module | module switch_fabric_tb();
reg [31:0] dinA;
reg [31:0] dinB;
reg [31:0] dinC;
reg [31:0] dinD;
reg [31:0] dinE;
reg [3:0] sf_cfg_vecA;
reg [3:0] sf_cfg_vecB;
reg [3:0] sf_cfg_vecC;
reg [3:0] sf_cfg_vecD;
reg [3:0] sf_cfg_vecE;
wire [31:0] doutA;
wire [31:0] doutB;
wire [31:0] doutC;
wire [31:0] doutD;
wire [31:0] doutE;
switch_fabric UUT (
.dinA(dinA),
.dinB(dinB),
.dinC(dinC),
.dinD(dinD),
.dinE(dinE),
.sf_cfg_vecA(sf_cfg_vecA),
.sf_cfg_vecB(sf_cfg_vecB),
.sf_cfg_vecC(sf_cfg_vecC),
.sf_cfg_vecD(sf_cfg_vecD),
.sf_cfg_vecE(sf_cfg_vecE),
.doutA(doutA),
.doutB(doutB),
.doutC(doutC),
.doutD(doutD),
.doutE(doutE)
);
initial begin
sf_cfg_vecA = 0;
sf_cfg_vecB = 0;
sf_cfg_vecC = 0;
sf_cfg_vecD = 0;
sf_cfg_vecE = 0;
dinA = 1;
dinB = 2;
dinC = 3;
dinD = 4;
dinE = 5;
#(60);
sf_cfg_vecA = 4'b0001;
#(20);
sf_cfg_vecA = 4'b0010;
#(20);
sf_cfg_vecA = 4'b0100;
#(20);
sf_cfg_vecA = 4'b1000;
#(20);
sf_cfg_vecA = 4'b0000;
#(20);
sf_cfg_vecB = 4'b0001;
#(20);
sf_cfg_vecB = 4'b0010;
#(20);
sf_cfg_vecB = 4'b0100;
#(20);
sf_cfg_vecB = 4'b1000;
#(20);
sf_cfg_vecB = 4'b0000;
#(20);
sf_cfg_vecC = 4'b0001;
#(20);
sf_cfg_vecC = 4'b0010;
#(20);
sf_cfg_vecC = 4'b0100;
#(20);
sf_cfg_vecC = 4'b1000;
#(20);
sf_cfg_vecC = 4'b0000;
#(20);
sf_cfg_vecD = 4'b0001;
#(20);
sf_cfg_vecD = 4'b0010;
#(20);
sf_cfg_vecD = 4'b0100;
#(20);
sf_cfg_vecD = 4'b1000;
#(20);
sf_cfg_vecD = 4'b0000;
#(20);
sf_cfg_vecE = 4'b0001;
#(20);
sf_cfg_vecE = 4'b0010;
#(20);
sf_cfg_vecE = 4'b0100;
#(20);
sf_cfg_vecE = 4'b1000;
#(20);
sf_cfg_vecE = 4'b0000;
#(20);
#(500)
$stop;
end
endmodule | module switch_fabric_tb(); |
reg [31:0] dinA;
reg [31:0] dinB;
reg [31:0] dinC;
reg [31:0] dinD;
reg [31:0] dinE;
reg [3:0] sf_cfg_vecA;
reg [3:0] sf_cfg_vecB;
reg [3:0] sf_cfg_vecC;
reg [3:0] sf_cfg_vecD;
reg [3:0] sf_cfg_vecE;
wire [31:0] doutA;
wire [31:0] doutB;
wire [31:0] doutC;
wire [31:0] doutD;
wire [31:0] doutE;
switch_fabric UUT (
.dinA(dinA),
.dinB(dinB),
.dinC(dinC),
.dinD(dinD),
.dinE(dinE),
.sf_cfg_vecA(sf_cfg_vecA),
.sf_cfg_vecB(sf_cfg_vecB),
.sf_cfg_vecC(sf_cfg_vecC),
.sf_cfg_vecD(sf_cfg_vecD),
.sf_cfg_vecE(sf_cfg_vecE),
.doutA(doutA),
.doutB(doutB),
.doutC(doutC),
.doutD(doutD),
.doutE(doutE)
);
initial begin
sf_cfg_vecA = 0;
sf_cfg_vecB = 0;
sf_cfg_vecC = 0;
sf_cfg_vecD = 0;
sf_cfg_vecE = 0;
dinA = 1;
dinB = 2;
dinC = 3;
dinD = 4;
dinE = 5;
#(60);
sf_cfg_vecA = 4'b0001;
#(20);
sf_cfg_vecA = 4'b0010;
#(20);
sf_cfg_vecA = 4'b0100;
#(20);
sf_cfg_vecA = 4'b1000;
#(20);
sf_cfg_vecA = 4'b0000;
#(20);
sf_cfg_vecB = 4'b0001;
#(20);
sf_cfg_vecB = 4'b0010;
#(20);
sf_cfg_vecB = 4'b0100;
#(20);
sf_cfg_vecB = 4'b1000;
#(20);
sf_cfg_vecB = 4'b0000;
#(20);
sf_cfg_vecC = 4'b0001;
#(20);
sf_cfg_vecC = 4'b0010;
#(20);
sf_cfg_vecC = 4'b0100;
#(20);
sf_cfg_vecC = 4'b1000;
#(20);
sf_cfg_vecC = 4'b0000;
#(20);
sf_cfg_vecD = 4'b0001;
#(20);
sf_cfg_vecD = 4'b0010;
#(20);
sf_cfg_vecD = 4'b0100;
#(20);
sf_cfg_vecD = 4'b1000;
#(20);
sf_cfg_vecD = 4'b0000;
#(20);
sf_cfg_vecE = 4'b0001;
#(20);
sf_cfg_vecE = 4'b0010;
#(20);
sf_cfg_vecE = 4'b0100;
#(20);
sf_cfg_vecE = 4'b1000;
#(20);
sf_cfg_vecE = 4'b0000;
#(20);
#(500)
$stop;
end
endmodule | 0 |
140,882 | data/full_repos/permissive/92618161/rtl/verif/hexa_harness.v | 92,618,161 | hexa_harness.v | v | 253 | 138 | [] | [] | [] | null | line:240: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/verif/hexa_harness.v:229: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE/2) clk = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/verif/hexa_harness.v:230: Unsupported: Ignoring delay on this delayed statement.\n #(CYCLE/2) clk = 1\'b1;\n ^\n%Error: data/full_repos/permissive/92618161/rtl/verif/hexa_harness.v:242: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/verif/hexa_harness.v:243: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,817 | module | module hexa_harness();
parameter XCOR = 2,
YCOR = 2,
CYCLE = 100,
Tsetup = 15,
Thold = 5,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
reg clk;
reg rst;
wire diff_pair_pi [4:0];
wire diff_pair_ni [4:0];
wire crt_in [4:0];
wire [31:0] input_channels [4:0];
wire diff_pair_po [4:0];
wire diff_pair_no [4:0];
wire crt_out [4:0];
wire [31:0] output_channels [4:0];
hexa
#(.XCOR(XCOR), .YCOR(YCOR))
hexa
(
.clk(clk),
.rst(rst),
.diff_pair_pi({diff_pair_pi[4], diff_pair_pi[3], diff_pair_pi[2], diff_pair_pi[1], diff_pair_pi[0]}),
.diff_pair_ni({diff_pair_ni[4], diff_pair_ni[3], diff_pair_ni[2], diff_pair_ni[1], diff_pair_ni[0]}),
.crt_in({crt_in[4], crt_in[3], crt_in[2], crt_in[1], crt_in[0]}),
.input_channels({input_channels[4], input_channels[3], input_channels[2], input_channels[1], input_channels[0]}),
.diff_pair_po({diff_pair_po[4], diff_pair_po[3], diff_pair_po[2], diff_pair_po[1], diff_pair_po[0]}),
.diff_pair_no({diff_pair_no[4], diff_pair_no[3], diff_pair_no[2], diff_pair_no[1], diff_pair_no[0]}),
.crt_out({crt_out[4], crt_out[3], crt_out[2], crt_out[1], crt_out[0]}),
.output_channels({output_channels[4], output_channels[3], output_channels[2], output_channels[1], output_channels[0]})
);
source
#(
.Thold(Thold),
.PORT(XPOS)
)
xpos_in_channel
(
.clk (clk),
.credit_in (crt_out[0]),
.channel_out(input_channels[0]),
.diff_pair_out({diff_pair_pi[0], diff_pair_ni[0]})
);
sink
#(
.Thold(Thold)
)
xpos_out_channel
(
.clk (clk),
.channel_in (output_channels[0]),
.credit_out (crt_in[0]),
.diff_pair_in({diff_pair_po[0], diff_pair_no[0]})
);
source
#(
.Thold(Thold),
.PORT(XNEG)
)
xneg_in_channel
(
.clk (clk),
.credit_in (crt_out[1]),
.channel_out(input_channels[1]),
.diff_pair_out({diff_pair_pi[1], diff_pair_ni[1]})
);
sink
#(
.Thold(Thold)
)
xneg_out_channel
(
.clk (clk),
.channel_in (output_channels[1]),
.credit_out (crt_in[1]),
.diff_pair_in({diff_pair_po[1], diff_pair_no[1]})
);
source
#(
.Thold(Thold),
.PORT(YPOS)
)
ypos_in_channel
(
.clk (clk),
.credit_in (crt_out[2]),
.channel_out(input_channels[2]),
.diff_pair_out({diff_pair_pi[2], diff_pair_ni[2]})
);
sink
#(
.Thold(Thold)
)
ypos_out_channel
(
.clk (clk),
.channel_in (output_channels[2]),
.credit_out (crt_in[2]),
.diff_pair_in({diff_pair_po[2], diff_pair_no[2]})
);
source
#(
.Thold(Thold),
.PORT(YNEG)
)
yneg_in_channel
(
.clk (clk),
.credit_in (crt_out[3]),
.channel_out(input_channels[3]),
.diff_pair_out({diff_pair_pi[3], diff_pair_ni[3]})
);
sink
#(
.Thold(Thold)
)
yneg_out_channel
(
.clk (clk),
.channel_in (output_channels[3]),
.credit_out (crt_in[3]),
.diff_pair_in({diff_pair_po[3], diff_pair_no[3]})
);
source
#(
.Thold(Thold),
.PORT(PE)
)
pe_in_channel
(
.clk (clk),
.credit_in (crt_out[4]),
.channel_out(input_channels[4]),
.diff_pair_out({diff_pair_pi[4], diff_pair_ni[4]})
);
sink
#(
.Thold(Thold)
)
pe_out_channel
(
.clk (clk),
.channel_in (output_channels[4]),
.credit_out (crt_in[4]),
.diff_pair_in({diff_pair_po[4], diff_pair_no[4]})
);
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule | module hexa_harness(); |
parameter XCOR = 2,
YCOR = 2,
CYCLE = 100,
Tsetup = 15,
Thold = 5,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
reg clk;
reg rst;
wire diff_pair_pi [4:0];
wire diff_pair_ni [4:0];
wire crt_in [4:0];
wire [31:0] input_channels [4:0];
wire diff_pair_po [4:0];
wire diff_pair_no [4:0];
wire crt_out [4:0];
wire [31:0] output_channels [4:0];
hexa
#(.XCOR(XCOR), .YCOR(YCOR))
hexa
(
.clk(clk),
.rst(rst),
.diff_pair_pi({diff_pair_pi[4], diff_pair_pi[3], diff_pair_pi[2], diff_pair_pi[1], diff_pair_pi[0]}),
.diff_pair_ni({diff_pair_ni[4], diff_pair_ni[3], diff_pair_ni[2], diff_pair_ni[1], diff_pair_ni[0]}),
.crt_in({crt_in[4], crt_in[3], crt_in[2], crt_in[1], crt_in[0]}),
.input_channels({input_channels[4], input_channels[3], input_channels[2], input_channels[1], input_channels[0]}),
.diff_pair_po({diff_pair_po[4], diff_pair_po[3], diff_pair_po[2], diff_pair_po[1], diff_pair_po[0]}),
.diff_pair_no({diff_pair_no[4], diff_pair_no[3], diff_pair_no[2], diff_pair_no[1], diff_pair_no[0]}),
.crt_out({crt_out[4], crt_out[3], crt_out[2], crt_out[1], crt_out[0]}),
.output_channels({output_channels[4], output_channels[3], output_channels[2], output_channels[1], output_channels[0]})
);
source
#(
.Thold(Thold),
.PORT(XPOS)
)
xpos_in_channel
(
.clk (clk),
.credit_in (crt_out[0]),
.channel_out(input_channels[0]),
.diff_pair_out({diff_pair_pi[0], diff_pair_ni[0]})
);
sink
#(
.Thold(Thold)
)
xpos_out_channel
(
.clk (clk),
.channel_in (output_channels[0]),
.credit_out (crt_in[0]),
.diff_pair_in({diff_pair_po[0], diff_pair_no[0]})
);
source
#(
.Thold(Thold),
.PORT(XNEG)
)
xneg_in_channel
(
.clk (clk),
.credit_in (crt_out[1]),
.channel_out(input_channels[1]),
.diff_pair_out({diff_pair_pi[1], diff_pair_ni[1]})
);
sink
#(
.Thold(Thold)
)
xneg_out_channel
(
.clk (clk),
.channel_in (output_channels[1]),
.credit_out (crt_in[1]),
.diff_pair_in({diff_pair_po[1], diff_pair_no[1]})
);
source
#(
.Thold(Thold),
.PORT(YPOS)
)
ypos_in_channel
(
.clk (clk),
.credit_in (crt_out[2]),
.channel_out(input_channels[2]),
.diff_pair_out({diff_pair_pi[2], diff_pair_ni[2]})
);
sink
#(
.Thold(Thold)
)
ypos_out_channel
(
.clk (clk),
.channel_in (output_channels[2]),
.credit_out (crt_in[2]),
.diff_pair_in({diff_pair_po[2], diff_pair_no[2]})
);
source
#(
.Thold(Thold),
.PORT(YNEG)
)
yneg_in_channel
(
.clk (clk),
.credit_in (crt_out[3]),
.channel_out(input_channels[3]),
.diff_pair_out({diff_pair_pi[3], diff_pair_ni[3]})
);
sink
#(
.Thold(Thold)
)
yneg_out_channel
(
.clk (clk),
.channel_in (output_channels[3]),
.credit_out (crt_in[3]),
.diff_pair_in({diff_pair_po[3], diff_pair_no[3]})
);
source
#(
.Thold(Thold),
.PORT(PE)
)
pe_in_channel
(
.clk (clk),
.credit_in (crt_out[4]),
.channel_out(input_channels[4]),
.diff_pair_out({diff_pair_pi[4], diff_pair_ni[4]})
);
sink
#(
.Thold(Thold)
)
pe_out_channel
(
.clk (clk),
.channel_in (output_channels[4]),
.credit_out (crt_in[4]),
.diff_pair_in({diff_pair_po[4], diff_pair_no[4]})
);
always
begin
#(CYCLE/2) clk = 1'b0;
#(CYCLE/2) clk = 1'b1;
end
task sync_reset;
begin
reset <= 1'b1;
repeat(4)
begin
@(posedge clk);
#(Thold);
end
reset <= 1'b0;
end
endtask : sync_reset
endmodule | 0 |
140,883 | data/full_repos/permissive/92618161/rtl/verif/packet_generator.v | 92,618,161 | packet_generator.v | v | 518 | 73 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:43: Cannot find include file: packet_type.vh\n`include "packet_type.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/packet_type.vh\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/packet_type.vh.v\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/packet_type.vh.sv\n packet_type.vh\n packet_type.vh.v\n packet_type.vh.sv\n obj_dir/packet_type.vh\n obj_dir/packet_type.vh.v\n obj_dir/packet_type.vh.sv\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:44: Cannot find include file: system.vh\n`include "system.vh" \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:80: Define or directive not defined: \'`PACKET_TYPE\'\n reg `PACKET_TYPE packet;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:109: Define or directive not defined: \'`ID_HEAD\'\n packet `ID_HEAD = 1\'b1;\n ^~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:110: Define or directive not defined: \'`TESTIGO\'\n packet `TESTIGO = 1\'b0;\n ^~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:112: Define or directive not defined: \'`DESTINO\'\n packet `DESTINO = {x_dest, y_dest};\n ^~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:113: Define or directive not defined: \'`PUERTA\'\n packet `PUERTA = {x_gate, y_gate};\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:114: Define or directive not defined: \'`EXTENDED_SERIAL\'\n packet `EXTENDED_SERIAL = extended_serial; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:118: Define or directive not defined: \'`DATA_0\'\n packet `DATA_0 = "x+ ";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:120: Define or directive not defined: \'`DATA_0\'\n packet `DATA_0 = "x- ";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:122: Define or directive not defined: \'`DATA_0\'\n packet `DATA_0 = "y+ ";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:124: Define or directive not defined: \'`DATA_0\'\n packet `DATA_0 = "y- ";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:126: Define or directive not defined: \'`DATA_0\'\n packet `DATA_0 = "pe ";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:130: Define or directive not defined: \'`DATA_1\'\n packet `DATA_1 = {"x =",ascii};\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:133: Define or directive not defined: \'`DATA_2\'\n packet `DATA_2 = {"y =",ascii};\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:135: Define or directive not defined: \'`DATA_3\'\n packet `DATA_3 = "NTST";\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:201: Unsupported: Seeding $random doesn\'t map to C++, use $c("srand")\n x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));\n ^~~~~~~\n%Error: Internal Error: data/full_repos/permissive/92618161/rtl/verif/packet_generator.v:201: ../V3Ast.cpp:358: Null item passed to setOp1p\n x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));\n ^\n' | 309,818 | module | module packet_generator #(
parameter PORT = 0,
parameter PE_RQS = 5,
parameter X_LOCAL = 1,
parameter Y_LOCAL = 1,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)();
reg `PACKET_TYPE packet;
reg [2:0] x_dest_addr = 3'b000;
reg [2:0] y_dest_addr = 3'b000;
reg [2:0] x_gate_addr = 3'b000;
reg [2:0] y_gate_addr = 3'b000;
integer random_number = 0;
reg [7:0] ascii;
task network_directed_packet;
input [2 :0] x_dest = 0;
input [2 :0] y_dest = 0;
input [2 :0] x_gate = 0;
input [2 :0] y_gate = 0;
input [17:0] extended_serial = 0;
begin: directed_packet
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DESTINO = {x_dest, y_dest};
packet `PUERTA = {x_gate, y_gate};
packet `EXTENDED_SERIAL = extended_serial;
if (PORT == 0)
packet `DATA_0 = "x+ ";
else if (PORT == 1)
packet `DATA_0 = "x- ";
else if (PORT == 2)
packet `DATA_0 = "y+ ";
else if (PORT == 3)
packet `DATA_0 = "y- ";
else if (PORT == 4)
packet `DATA_0 = "pe ";
bin2ascii(x_gate);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_gate);
packet `DATA_2 = {"y =",ascii};
packet `DATA_3 = "NTST";
end
endtask
task random_packet_router;
input [11:0] serial = 0;
input [31:0] seed = 0;
begin: random_packet
if (PORT == 0)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr > X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else if (PORT == 1)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr < X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == 2)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr > Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (PORT == 3)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr < Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
random_number = {$random(seed)} % 4;
if (random_number == 0)
begin
x_gate_addr = X_WIDTH + 1;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (random_number == 2)
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
else if (random_number == 1)
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = 0;
end
packet `ID_HEAD = 1'b1;
if ($unsigned($random(seed))%10 < PE_RQS)
begin
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
end
else
begin
packet `TESTIGO = 1'b1;
packet `DATA_3 = "TST ";
end
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_packet_router
task random_performance_packet;
input [17:0] serial = 0;
input [31:0] seed = 0;
begin: random_dn_packet
if (PORT == `X_POS)
x_dest_addr = 0;
else if (PORT == `X_NEG)
x_dest_addr = X_WIDTH + 1;
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == `Y_POS)
y_dest_addr = 0;
else if (PORT == `Y_NEG)
y_dest_addr = Y_WIDTH + 1;
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
random_number = {$random(seed)} % 10;
if (random_number < 6)
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = serial[17:12];
packet `SERIAL = serial[11:0];
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_performance_packet
task custom_packet;
input testigo;
input [5:0] destino;
input [5:0] puerta;
input [11:0] serial;
input [31:0] dato1;
input [31:0] dato2;
input [31:0] dato3;
input [31:0] dato4;
begin
packet `ID_HEAD = 1'b1;
packet `TESTIGO = testigo;
packet `DESTINO = destino;
packet `PUERTA = puerta;
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
packet `DATA_0 = dato1;
packet `DATA_1 = dato2;
packet `DATA_2 = dato3;
packet `DATA_3 = dato4;
end
endtask : custom_packet
task null_packet;
begin
packet `ID_HEAD = 1'b0;
packet `TESTIGO = 1'b0;
packet `DESTINO = {6{1'b0}};
packet `PUERTA = {6{1'b0}};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = 11'b000_0000_0000;
packet `DATA_0 = "_NULL";
packet `DATA_1 = "_NULL";
packet `DATA_2 = "_NULL";
packet `DATA_3 = "_NULL";
end
endtask : null_packet
task bin2ascii;
input [2:0] bin;
begin
if(bin == 3'b000)
ascii = "0";
else if(bin == 3'b001)
ascii = "1";
else if(bin == 3'b010)
ascii = "2";
else if(bin == 3'b011)
ascii = "3";
else if(bin == 3'b100)
ascii = "4";
else if(bin == 3'b101)
ascii = "5";
else if(bin == 3'b110)
ascii = "6";
else
ascii = "7";
end
endtask : bin2ascii
endmodule | module packet_generator #(
parameter PORT = 0,
parameter PE_RQS = 5,
parameter X_LOCAL = 1,
parameter Y_LOCAL = 1,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)(); |
reg `PACKET_TYPE packet;
reg [2:0] x_dest_addr = 3'b000;
reg [2:0] y_dest_addr = 3'b000;
reg [2:0] x_gate_addr = 3'b000;
reg [2:0] y_gate_addr = 3'b000;
integer random_number = 0;
reg [7:0] ascii;
task network_directed_packet;
input [2 :0] x_dest = 0;
input [2 :0] y_dest = 0;
input [2 :0] x_gate = 0;
input [2 :0] y_gate = 0;
input [17:0] extended_serial = 0;
begin: directed_packet
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DESTINO = {x_dest, y_dest};
packet `PUERTA = {x_gate, y_gate};
packet `EXTENDED_SERIAL = extended_serial;
if (PORT == 0)
packet `DATA_0 = "x+ ";
else if (PORT == 1)
packet `DATA_0 = "x- ";
else if (PORT == 2)
packet `DATA_0 = "y+ ";
else if (PORT == 3)
packet `DATA_0 = "y- ";
else if (PORT == 4)
packet `DATA_0 = "pe ";
bin2ascii(x_gate);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_gate);
packet `DATA_2 = {"y =",ascii};
packet `DATA_3 = "NTST";
end
endtask
task random_packet_router;
input [11:0] serial = 0;
input [31:0] seed = 0;
begin: random_packet
if (PORT == 0)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr > X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else if (PORT == 1)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr < X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == 2)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr > Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (PORT == 3)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr < Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
random_number = {$random(seed)} % 4;
if (random_number == 0)
begin
x_gate_addr = X_WIDTH + 1;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (random_number == 2)
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
else if (random_number == 1)
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = 0;
end
packet `ID_HEAD = 1'b1;
if ($unsigned($random(seed))%10 < PE_RQS)
begin
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
end
else
begin
packet `TESTIGO = 1'b1;
packet `DATA_3 = "TST ";
end
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_packet_router
task random_performance_packet;
input [17:0] serial = 0;
input [31:0] seed = 0;
begin: random_dn_packet
if (PORT == `X_POS)
x_dest_addr = 0;
else if (PORT == `X_NEG)
x_dest_addr = X_WIDTH + 1;
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == `Y_POS)
y_dest_addr = 0;
else if (PORT == `Y_NEG)
y_dest_addr = Y_WIDTH + 1;
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
random_number = {$random(seed)} % 10;
if (random_number < 6)
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = serial[17:12];
packet `SERIAL = serial[11:0];
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_performance_packet
task custom_packet;
input testigo;
input [5:0] destino;
input [5:0] puerta;
input [11:0] serial;
input [31:0] dato1;
input [31:0] dato2;
input [31:0] dato3;
input [31:0] dato4;
begin
packet `ID_HEAD = 1'b1;
packet `TESTIGO = testigo;
packet `DESTINO = destino;
packet `PUERTA = puerta;
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
packet `DATA_0 = dato1;
packet `DATA_1 = dato2;
packet `DATA_2 = dato3;
packet `DATA_3 = dato4;
end
endtask : custom_packet
task null_packet;
begin
packet `ID_HEAD = 1'b0;
packet `TESTIGO = 1'b0;
packet `DESTINO = {6{1'b0}};
packet `PUERTA = {6{1'b0}};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = 11'b000_0000_0000;
packet `DATA_0 = "_NULL";
packet `DATA_1 = "_NULL";
packet `DATA_2 = "_NULL";
packet `DATA_3 = "_NULL";
end
endtask : null_packet
task bin2ascii;
input [2:0] bin;
begin
if(bin == 3'b000)
ascii = "0";
else if(bin == 3'b001)
ascii = "1";
else if(bin == 3'b010)
ascii = "2";
else if(bin == 3'b011)
ascii = "3";
else if(bin == 3'b100)
ascii = "4";
else if(bin == 3'b101)
ascii = "5";
else if(bin == 3'b110)
ascii = "6";
else
ascii = "7";
end
endtask : bin2ascii
endmodule | 0 |
140,884 | data/full_repos/permissive/92618161/rtl/verif/sink.v | 92,618,161 | sink.v | v | 246 | 170 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/92618161/rtl/verif/sink.v:32: Cannot find include file: system.vh\n`include "system.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh.v\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh.sv\n system.vh\n system.vh.v\n system.vh.sv\n obj_dir/system.vh\n obj_dir/system.vh.v\n obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/92618161/rtl/verif/sink.v:33: Cannot find include file: packet_type.vh\n`include "packet_type.vh" \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/sink.v:88: Define or directive not defined: \'`PACKET_TYPE\'\n reg `PACKET_TYPE paquete;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/sink.v:174: syntax error, unexpected \'@\'\n @(posedge clk)\n ^\n%Error: Exiting due to 4 error(s)\n' | 309,820 | module | module sink #(
parameter Thold = 5,
parameter PORT = XNEG,
parameter ID = 0
)
(
input wire clk,
input wire [1:0] diff_pair_out,
input wire [31:0] channel_in,
output reg credit_out
);
localparam A_ASCII = 65,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
reg [12*8:0] file_name;
reg [4*8:0] port_name;
reg `PACKET_TYPE paquete;
reg [17:0] extended_serial_field;
reg [11:0] field_serial;
reg [31:0] dato1_flit;
reg [31:0] dato2_flit;
reg [31:0] dato3_flit;
reg [31:0] dato4_flit;
integer fp;
integer packet_count;
integer packet_tick;
integer i;
reg [7:0] file_id;
initial
begin
file_name = "";
file_id = A_ASCII + ID;
paquete = 0;
if (PORT == X_NEG)
port_name = "XNEG";
else if (PORT == X_POS)
port_name = "XPOS";
else if (PORT == Y_NEG)
port_name = "YNEG";
else if (PORT == Y_POS)
port_name = "YPOS";
else
port_name = "PE__";
extended_serial_field = 0;
field_serial = 0;
dato1_flit = 0;
dato2_flit = 0;
dato3_flit = 0;
dato4_flit = 0;
fp = 0;
packet_count = 0;
packet_tick = 0;
i = 0;
credit_out = 0;
end
always @(channel_in)
begin
if (channel_in !== {32{1'b0}} && channel_in !== {32{1'bx}})
begin
for (i = 0; i < 5; i = i+1)
begin
if(i == 4)
begin
packet_count = packet_count + 1;
credit_out <= 1;
end
paquete = {paquete[159:32], channel_in};
@(posedge clk)
#(Thold);
if (i < 4)
paquete = paquete << 32;
end
i = 0;
extended_serial_field = paquete[145:128];
dato1_flit = paquete[127:96];
dato2_flit = paquete[95:64];
dato3_flit = paquete[63:32];
dato4_flit = paquete[31:0];
packet_tick = $time();
$fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
credit_out <= 0;
end
end
task open_observer;
begin
file_name = {port_name, "_RX", file_id, ".dat"};
$display("%s", file_name);
fp = $fopen(file_name, "w");
if(!fp)
$display("Could not open %s", file_name);
else
$display("Success opening %s", file_name);
end
endtask : open_observer
task close_observer;
begin
file_name = {port_name, "_RX", file_id, ".dat"};
$fclose(fp);
$display("%s se cerro de manera exitosa", file_name);
end
endtask : close_observer
endmodule | module sink #(
parameter Thold = 5,
parameter PORT = XNEG,
parameter ID = 0
)
(
input wire clk,
input wire [1:0] diff_pair_out,
input wire [31:0] channel_in,
output reg credit_out
); |
localparam A_ASCII = 65,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
reg [12*8:0] file_name;
reg [4*8:0] port_name;
reg `PACKET_TYPE paquete;
reg [17:0] extended_serial_field;
reg [11:0] field_serial;
reg [31:0] dato1_flit;
reg [31:0] dato2_flit;
reg [31:0] dato3_flit;
reg [31:0] dato4_flit;
integer fp;
integer packet_count;
integer packet_tick;
integer i;
reg [7:0] file_id;
initial
begin
file_name = "";
file_id = A_ASCII + ID;
paquete = 0;
if (PORT == X_NEG)
port_name = "XNEG";
else if (PORT == X_POS)
port_name = "XPOS";
else if (PORT == Y_NEG)
port_name = "YNEG";
else if (PORT == Y_POS)
port_name = "YPOS";
else
port_name = "PE__";
extended_serial_field = 0;
field_serial = 0;
dato1_flit = 0;
dato2_flit = 0;
dato3_flit = 0;
dato4_flit = 0;
fp = 0;
packet_count = 0;
packet_tick = 0;
i = 0;
credit_out = 0;
end
always @(channel_in)
begin
if (channel_in !== {32{1'b0}} && channel_in !== {32{1'bx}})
begin
for (i = 0; i < 5; i = i+1)
begin
if(i == 4)
begin
packet_count = packet_count + 1;
credit_out <= 1;
end
paquete = {paquete[159:32], channel_in};
@(posedge clk)
#(Thold);
if (i < 4)
paquete = paquete << 32;
end
i = 0;
extended_serial_field = paquete[145:128];
dato1_flit = paquete[127:96];
dato2_flit = paquete[95:64];
dato3_flit = paquete[63:32];
dato4_flit = paquete[31:0];
packet_tick = $time();
$fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
credit_out <= 0;
end
end
task open_observer;
begin
file_name = {port_name, "_RX", file_id, ".dat"};
$display("%s", file_name);
fp = $fopen(file_name, "w");
if(!fp)
$display("Could not open %s", file_name);
else
$display("Success opening %s", file_name);
end
endtask : open_observer
task close_observer;
begin
file_name = {port_name, "_RX", file_id, ".dat"};
$fclose(fp);
$display("%s se cerro de manera exitosa", file_name);
end
endtask : close_observer
endmodule | 0 |
140,885 | data/full_repos/permissive/92618161/rtl/verif/source.v | 92,618,161 | source.v | v | 252 | 157 | [] | [] | [] | null | None: at end of input | null | 1: b'%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:34: Cannot find include file: system.vh\n`include "system.vh" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh.v\n data/full_repos/permissive/92618161/rtl/verif,data/full_repos/permissive/92618161/system.vh.sv\n system.vh\n system.vh.v\n system.vh.sv\n obj_dir/system.vh\n obj_dir/system.vh.v\n obj_dir/system.vh.sv\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:35: Cannot find include file: packet_type.vh\n`include "packet_type.vh" \n ^~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/verif/source.v:160: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:177: Define or directive not defined: \'`PACKET_TYPE\'\n input `PACKET_TYPE pkt;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:186: Define or directive not defined: \'`EXTENDED_SERIAL\'\n extended_serial_field = pkt `EXTENDED_SERIAL;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:187: Define or directive not defined: \'`DATA_0\'\n dato1_flit = pkt `DATA_0;\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:188: Define or directive not defined: \'`DATA_1\'\n dato2_flit = pkt `DATA_1;\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:189: Define or directive not defined: \'`DATA_2\'\n dato3_flit = pkt `DATA_2;\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:190: Define or directive not defined: \'`DATA_3\'\n dato4_flit = pkt `DATA_3;\n ^~~~~~~\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:198: syntax error, unexpected \'@\'\n @(creditos > 0);\n ^\n%Error: data/full_repos/permissive/92618161/rtl/verif/source.v:205: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92618161/rtl/verif/source.v:206: Unsupported: Ignoring delay on this delayed statement.\n #(Thold);\n ^\n%Error: Exiting due to 10 error(s), 2 warning(s)\n' | 309,821 | module | module source #(
parameter Thold = 5,
parameter PORT = 0,
parameter CREDITS = 4,
parameter ID = 0
)
(
input wire clk,
input wire credit_in,
output reg [1:0] diff_pair_out,
output reg [32:0] channel_out
);
localparam A_ASCII = 65,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
integer creditos;
integer packet_tick;
integer packet_count;
integer fp;
reg [12*8:0] file_name;
reg [4*8:0] port_name;
reg [7:0] file_id;
reg [17:0] extended_serial_field;
reg [11:0] field_serial;
reg [31:0] dato1_flit;
reg [31:0] dato2_flit;
reg [31:0] dato3_flit;
reg [31:0] dato4_flit;
reg [1:0] diff_pair;
initial
begin
fp = 0;
file_name = "";
file_id = A_ASCII + ID;
if (PORT == XPOS)
port_name = "XPOS";
else if (PORT == XNEG)
port_name = "XNEG";
else if (PORT == YPOS)
port_name = "YPOS";
else if (PORT == YNEG)
port_name = "YNEG";
else
port_name = "PE__";
channel_out = {32{1'b0}};
creditos = CREDITS;
extended_serial_field = 0;
field_serial = 0;
dato1_flit = 0;
dato2_flit = 0;
dato3_flit = 0;
dato4_flit = 0;
packet_tick = 0;
packet_count = 0;
diff_pair = 2'b10;
end
always @(posedge clk)
if (credit_in == 1)
begin
#(Thold);
creditos = creditos + 1;
end
task send_packet;
input `PACKET_TYPE pkt;
integer i;
begin
packet_tick = $time();
extended_serial_field = pkt `EXTENDED_SERIAL;
dato1_flit = pkt `DATA_0;
dato2_flit = pkt `DATA_1;
dato3_flit = pkt `DATA_2;
dato4_flit = pkt `DATA_3;
$fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
if (creditos < 1)
@(creditos > 0);
diff_pair = ~diff_pair;
for (i = 0; i < 5; i = i+1)
begin
channel_out <= pkt[31:0];
@(posedge clk);
#(Thold);
if (i == 0)
creditos = creditos - 1;
pkt = pkt >> 32;
end
packet_count = packet_count + 1;
channel_out = {32{1'bx}};
end
endtask : send_packet
task open_observer;
begin
file_name = {port_name, "_TX", file_id, ".dat"};
$display("%s", file_name);
fp = $fopen(file_name, "w");
if(!fp)
$display("Could not open %s", file_name);
else
$display("Success opening %s", file_name);
end
endtask : open_observer
task close_observer;
begin
$fclose(fp);
$display("%s se cerro de manera exitosa", file_name);
end
endtask : close_observer
endmodule | module source #(
parameter Thold = 5,
parameter PORT = 0,
parameter CREDITS = 4,
parameter ID = 0
)
(
input wire clk,
input wire credit_in,
output reg [1:0] diff_pair_out,
output reg [32:0] channel_out
); |
localparam A_ASCII = 65,
XPOS = 0,
XNEG = 1,
YPOS = 2,
YNEG = 3,
PE = 4;
integer creditos;
integer packet_tick;
integer packet_count;
integer fp;
reg [12*8:0] file_name;
reg [4*8:0] port_name;
reg [7:0] file_id;
reg [17:0] extended_serial_field;
reg [11:0] field_serial;
reg [31:0] dato1_flit;
reg [31:0] dato2_flit;
reg [31:0] dato3_flit;
reg [31:0] dato4_flit;
reg [1:0] diff_pair;
initial
begin
fp = 0;
file_name = "";
file_id = A_ASCII + ID;
if (PORT == XPOS)
port_name = "XPOS";
else if (PORT == XNEG)
port_name = "XNEG";
else if (PORT == YPOS)
port_name = "YPOS";
else if (PORT == YNEG)
port_name = "YNEG";
else
port_name = "PE__";
channel_out = {32{1'b0}};
creditos = CREDITS;
extended_serial_field = 0;
field_serial = 0;
dato1_flit = 0;
dato2_flit = 0;
dato3_flit = 0;
dato4_flit = 0;
packet_tick = 0;
packet_count = 0;
diff_pair = 2'b10;
end
always @(posedge clk)
if (credit_in == 1)
begin
#(Thold);
creditos = creditos + 1;
end
task send_packet;
input `PACKET_TYPE pkt;
integer i;
begin
packet_tick = $time();
extended_serial_field = pkt `EXTENDED_SERIAL;
dato1_flit = pkt `DATA_0;
dato2_flit = pkt `DATA_1;
dato3_flit = pkt `DATA_2;
dato4_flit = pkt `DATA_3;
$fdisplay(fp, "%d, %d", extended_serial_field, packet_tick);
if (creditos < 1)
@(creditos > 0);
diff_pair = ~diff_pair;
for (i = 0; i < 5; i = i+1)
begin
channel_out <= pkt[31:0];
@(posedge clk);
#(Thold);
if (i == 0)
creditos = creditos - 1;
pkt = pkt >> 32;
end
packet_count = packet_count + 1;
channel_out = {32{1'bx}};
end
endtask : send_packet
task open_observer;
begin
file_name = {port_name, "_TX", file_id, ".dat"};
$display("%s", file_name);
fp = $fopen(file_name, "w");
if(!fp)
$display("Could not open %s", file_name);
else
$display("Success opening %s", file_name);
end
endtask : open_observer
task close_observer;
begin
$fclose(fp);
$display("%s se cerro de manera exitosa", file_name);
end
endtask : close_observer
endmodule | 0 |
140,886 | data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v | 92,634,379 | inst_rom.v | v | 56 | 92 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 1820: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:33: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v\n data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v.v\n data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:39: Define or directive not defined: \'`InstAddrBus\'\n input wire[`InstAddrBus] addr,\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:39: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n input wire[`InstAddrBus] addr,\n ^\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:40: Define or directive not defined: \'`InstBus\'\n output reg[`InstBus] inst\n ^~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:44: Define or directive not defined: \'`InstBus\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:44: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:44: Define or directive not defined: \'`InstMemNum\'\n reg[`InstBus] inst_mem[0:`InstMemNum-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:49: Define or directive not defined: \'`ChipDisable\'\n if (ce == `ChipDisable) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:50: Define or directive not defined: \'`ZeroWord\'\n inst <= `ZeroWord;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/inst_rom.v:52: Define or directive not defined: \'`InstMemNumLog2\'\n inst <= inst_mem[addr[`InstMemNumLog2+1:2]];\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 10 error(s)\n' | 309,836 | module | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
);
reg[`InstBus] inst_mem[0:`InstMemNum-1];
initial $readmemh ( "D:/Computer Architecture/My-CPU/ROMSource/inst_rom.data", inst_mem );
always @ (*) begin
if (ce == `ChipDisable) begin
inst <= `ZeroWord;
end else begin
inst <= inst_mem[addr[`InstMemNumLog2+1:2]];
end
end
endmodule | module inst_rom(
input wire ce,
input wire[`InstAddrBus] addr,
output reg[`InstBus] inst
); |
reg[`InstBus] inst_mem[0:`InstMemNum-1];
initial $readmemh ( "D:/Computer Architecture/My-CPU/ROMSource/inst_rom.data", inst_mem );
always @ (*) begin
if (ce == `ChipDisable) begin
inst <= `ZeroWord;
end else begin
inst <= inst_mem[addr[`InstMemNumLog2+1:2]];
end
end
endmodule | 4 |
140,888 | data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/new/clk_div.v | 92,634,379 | clk_div.v | v | 38 | 83 | [] | [] | [] | [(23, 37)] | null | null | 1: b"%Error: data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/new/clk_div.v:27: Duplicate declaration of signal: 'clkout'\n : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)\n reg clkout;\n ^~~~~~\n data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/new/clk_div.v:25: ... Location of original declaration\n output clkout);\n ^~~~~~\n%Error: Exiting due to 1 error(s)\n" | 309,845 | module | module clk_div(
input clkin,
output clkout);
reg clkout;
reg[2:0] temp;
always @(posedge clkin) begin
temp<=temp+1;
if(temp==1) begin
clkout<=~clkout;
temp<=0;
end else
clkout<=clkout;
end
endmodule | module clk_div(
input clkin,
output clkout); |
reg clkout;
reg[2:0] temp;
always @(posedge clkin) begin
temp<=temp+1;
if(temp==1) begin
clkout<=~clkout;
temp<=0;
end else
clkout<=clkout;
end
endmodule | 4 |
140,889 | data/full_repos/permissive/92634379/Final/Final.srcs/sources_1/imports/sources_1/new/io_sel.v | 92,634,379 | io_sel.v | v | 31 | 83 | [] | [] | [] | [(23, 30)] | null | data/verilator_xmls/81e0c589-4c73-4c86-8b19-f0ad42844e11.xml | null | 309,846 | module | module io_sel(
input [31:0] addr,
input cs,
output seg7_cs
);
assign seg7_cs = (addr == 32'h10010000 && cs == 1) ? 1 : 0;
endmodule | module io_sel(
input [31:0] addr,
input cs,
output seg7_cs
); |
assign seg7_cs = (addr == 32'h10010000 && cs == 1) ? 1 : 0;
endmodule | 4 |
140,891 | data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v | 92,634,379 | openmips_min_sopc_tb.v | v | 64 | 93 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 4: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:1: Cannot find include file: defines.v\n`include "defines.v" \n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v.v\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11,data/full_repos/permissive/92634379/defines.v.sv\n defines.v\n defines.v.v\n defines.v.sv\n obj_dir/defines.v\n obj_dir/defines.v.v\n obj_dir/defines.v.sv\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:12: Unsupported: $fopen with multichannel descriptor. Add ,"w" as second argument to open a file descriptor.\n file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");\n ^~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:14: Unsupported: Ignoring delay on this delayed statement.\n forever #10 CLOCK_50 = ~CLOCK_50;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:18: Define or directive not defined: \'`RstEnable\'\n rst = `RstEnable;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:18: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n rst = `RstEnable;\n ^\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:19: Define or directive not defined: \'`RstDisable\'\n #195 rst= `RstDisable;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:19: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n #195 rst= `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:19: Unsupported: Ignoring delay on this delayed statement.\n #195 rst= `RstDisable;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/imports/Chapter11/openmips_min_sopc_tb.v:20: Unsupported: Ignoring delay on this delayed statement.\n #100000 $stop;\n ^\n%Error: Exiting due to 6 error(s), 3 warning(s)\n' | 309,868 | module | module openmips_min_sopc_tb();
reg CLOCK_50;
reg rst;
integer file_output;
initial begin
file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#100000 $stop;
end
openmips_min_sopc openmips_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
always@(posedge CLOCK_50) begin
$fdisplay(file_output,"pc = %h", openmips_min_sopc0.openmips0.id0.pc_i);
$fdisplay(file_output,"instr = %h", openmips_min_sopc0.openmips0.id0.inst_i);
$fdisplay(file_output,"regfiles0 = %h", openmips_min_sopc0.openmips0.regfile1.regs[0]);
$fdisplay(file_output,"regfiles1 = %h", openmips_min_sopc0.openmips0.regfile1.regs[1]);
$fdisplay(file_output,"regfiles2 = %h", openmips_min_sopc0.openmips0.regfile1.regs[2]);
$fdisplay(file_output,"regfiles3 = %h", openmips_min_sopc0.openmips0.regfile1.regs[3]);
$fdisplay(file_output,"regfiles4 = %h", openmips_min_sopc0.openmips0.regfile1.regs[4]);
$fdisplay(file_output,"regfiles5 = %h", openmips_min_sopc0.openmips0.regfile1.regs[5]);
$fdisplay(file_output,"regfiles6 = %h", openmips_min_sopc0.openmips0.regfile1.regs[6]);
$fdisplay(file_output,"regfiles7 = %h", openmips_min_sopc0.openmips0.regfile1.regs[7]);
$fdisplay(file_output,"regfiles8 = %h", openmips_min_sopc0.openmips0.regfile1.regs[8]);
$fdisplay(file_output,"regfiles9 = %h", openmips_min_sopc0.openmips0.regfile1.regs[9]);
$fdisplay(file_output,"regfiles10 = %h", openmips_min_sopc0.openmips0.regfile1.regs[10]);
$fdisplay(file_output,"regfiles11 = %h", openmips_min_sopc0.openmips0.regfile1.regs[11]);
$fdisplay(file_output,"regfiles12 = %h", openmips_min_sopc0.openmips0.regfile1.regs[12]);
$fdisplay(file_output,"regfiles13 = %h", openmips_min_sopc0.openmips0.regfile1.regs[13]);
$fdisplay(file_output,"regfiles14 = %h", openmips_min_sopc0.openmips0.regfile1.regs[14]);
$fdisplay(file_output,"regfiles15 = %h", openmips_min_sopc0.openmips0.regfile1.regs[15]);
$fdisplay(file_output,"regfiles16 = %h", openmips_min_sopc0.openmips0.regfile1.regs[16]);
$fdisplay(file_output,"regfiles17 = %h", openmips_min_sopc0.openmips0.regfile1.regs[17]);
$fdisplay(file_output,"regfiles18 = %h", openmips_min_sopc0.openmips0.regfile1.regs[18]);
$fdisplay(file_output,"regfiles19 = %h", openmips_min_sopc0.openmips0.regfile1.regs[19]);
$fdisplay(file_output,"regfiles20 = %h", openmips_min_sopc0.openmips0.regfile1.regs[20]);
$fdisplay(file_output,"regfiles21 = %h", openmips_min_sopc0.openmips0.regfile1.regs[21]);
$fdisplay(file_output,"regfiles22 = %h", openmips_min_sopc0.openmips0.regfile1.regs[22]);
$fdisplay(file_output,"regfiles23 = %h", openmips_min_sopc0.openmips0.regfile1.regs[23]);
$fdisplay(file_output,"regfiles24 = %h", openmips_min_sopc0.openmips0.regfile1.regs[24]);
$fdisplay(file_output,"regfiles25 = %h", openmips_min_sopc0.openmips0.regfile1.regs[25]);
$fdisplay(file_output,"regfiles26 = %h", openmips_min_sopc0.openmips0.regfile1.regs[26]);
$fdisplay(file_output,"regfiles27 = %h", openmips_min_sopc0.openmips0.regfile1.regs[27]);
$fdisplay(file_output,"regfiles28 = %h", openmips_min_sopc0.openmips0.regfile1.regs[28]);
$fdisplay(file_output,"regfiles29 = %h", openmips_min_sopc0.openmips0.regfile1.regs[29]);
$fdisplay(file_output,"regfiles30 = %h", openmips_min_sopc0.openmips0.regfile1.regs[30]);
$fdisplay(file_output,"regfiles31 = %h", openmips_min_sopc0.openmips0.regfile1.regs[31]);
end
endmodule | module openmips_min_sopc_tb(); |
reg CLOCK_50;
reg rst;
integer file_output;
initial begin
file_output = $fopen("D:/Computer Architecture/My-CPU/TestResult/beq.txt");
CLOCK_50 = 1'b0;
forever #10 CLOCK_50 = ~CLOCK_50;
end
initial begin
rst = `RstEnable;
#195 rst= `RstDisable;
#100000 $stop;
end
openmips_min_sopc openmips_min_sopc0(
.clk(CLOCK_50),
.rst(rst)
);
always@(posedge CLOCK_50) begin
$fdisplay(file_output,"pc = %h", openmips_min_sopc0.openmips0.id0.pc_i);
$fdisplay(file_output,"instr = %h", openmips_min_sopc0.openmips0.id0.inst_i);
$fdisplay(file_output,"regfiles0 = %h", openmips_min_sopc0.openmips0.regfile1.regs[0]);
$fdisplay(file_output,"regfiles1 = %h", openmips_min_sopc0.openmips0.regfile1.regs[1]);
$fdisplay(file_output,"regfiles2 = %h", openmips_min_sopc0.openmips0.regfile1.regs[2]);
$fdisplay(file_output,"regfiles3 = %h", openmips_min_sopc0.openmips0.regfile1.regs[3]);
$fdisplay(file_output,"regfiles4 = %h", openmips_min_sopc0.openmips0.regfile1.regs[4]);
$fdisplay(file_output,"regfiles5 = %h", openmips_min_sopc0.openmips0.regfile1.regs[5]);
$fdisplay(file_output,"regfiles6 = %h", openmips_min_sopc0.openmips0.regfile1.regs[6]);
$fdisplay(file_output,"regfiles7 = %h", openmips_min_sopc0.openmips0.regfile1.regs[7]);
$fdisplay(file_output,"regfiles8 = %h", openmips_min_sopc0.openmips0.regfile1.regs[8]);
$fdisplay(file_output,"regfiles9 = %h", openmips_min_sopc0.openmips0.regfile1.regs[9]);
$fdisplay(file_output,"regfiles10 = %h", openmips_min_sopc0.openmips0.regfile1.regs[10]);
$fdisplay(file_output,"regfiles11 = %h", openmips_min_sopc0.openmips0.regfile1.regs[11]);
$fdisplay(file_output,"regfiles12 = %h", openmips_min_sopc0.openmips0.regfile1.regs[12]);
$fdisplay(file_output,"regfiles13 = %h", openmips_min_sopc0.openmips0.regfile1.regs[13]);
$fdisplay(file_output,"regfiles14 = %h", openmips_min_sopc0.openmips0.regfile1.regs[14]);
$fdisplay(file_output,"regfiles15 = %h", openmips_min_sopc0.openmips0.regfile1.regs[15]);
$fdisplay(file_output,"regfiles16 = %h", openmips_min_sopc0.openmips0.regfile1.regs[16]);
$fdisplay(file_output,"regfiles17 = %h", openmips_min_sopc0.openmips0.regfile1.regs[17]);
$fdisplay(file_output,"regfiles18 = %h", openmips_min_sopc0.openmips0.regfile1.regs[18]);
$fdisplay(file_output,"regfiles19 = %h", openmips_min_sopc0.openmips0.regfile1.regs[19]);
$fdisplay(file_output,"regfiles20 = %h", openmips_min_sopc0.openmips0.regfile1.regs[20]);
$fdisplay(file_output,"regfiles21 = %h", openmips_min_sopc0.openmips0.regfile1.regs[21]);
$fdisplay(file_output,"regfiles22 = %h", openmips_min_sopc0.openmips0.regfile1.regs[22]);
$fdisplay(file_output,"regfiles23 = %h", openmips_min_sopc0.openmips0.regfile1.regs[23]);
$fdisplay(file_output,"regfiles24 = %h", openmips_min_sopc0.openmips0.regfile1.regs[24]);
$fdisplay(file_output,"regfiles25 = %h", openmips_min_sopc0.openmips0.regfile1.regs[25]);
$fdisplay(file_output,"regfiles26 = %h", openmips_min_sopc0.openmips0.regfile1.regs[26]);
$fdisplay(file_output,"regfiles27 = %h", openmips_min_sopc0.openmips0.regfile1.regs[27]);
$fdisplay(file_output,"regfiles28 = %h", openmips_min_sopc0.openmips0.regfile1.regs[28]);
$fdisplay(file_output,"regfiles29 = %h", openmips_min_sopc0.openmips0.regfile1.regs[29]);
$fdisplay(file_output,"regfiles30 = %h", openmips_min_sopc0.openmips0.regfile1.regs[30]);
$fdisplay(file_output,"regfiles31 = %h", openmips_min_sopc0.openmips0.regfile1.regs[31]);
end
endmodule | 4 |
140,893 | data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new/top.v | 92,634,379 | top.v | v | 58 | 83 | [] | [] | [] | [(22, 57)] | null | null | 1: b"%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new/top.v:32: Cannot find file containing module: 'clk_div'\nclk_div clk_div0(\n^~~~~~~\n ... Looked in:\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_div\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_div.v\n data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_div.sv\n clk_div\n clk_div.v\n clk_div.sv\n obj_dir/clk_div\n obj_dir/clk_div.v\n obj_dir/clk_div.sv\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new/top.v:37: Cannot find file containing module: 'io_sel'\nio_sel io_sel1(\n^~~~~~\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new/top.v:43: Cannot find file containing module: 'openmips_min_sopc'\nopenmips_min_sopc openmips_min_sopc1(\n^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/project_4/project_4.srcs/sources_1/new/top.v:49: Cannot find file containing module: 'seg7x16'\nseg7x16 seg7x16_1(\n^~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 309,874 | module | module top(
input clk,
input rst,
output[7:0] o_seg,
output[7:0] o_sel
);
wire clk50;
wire seg7_cs;
wire[31:0] addr;
clk_div clk_div0(
.clkin(clk),
.rst(rst),
.clkout(clk50));
io_sel io_sel1(
.addr(32'h10010000),
.cs(1),
.seg7_cs(seg7_cs)
);
openmips_min_sopc openmips_min_sopc1(
.clk(clk),
.rst(rst),
.data0(addr)
);
seg7x16 seg7x16_1(
.clk(clk),
.reset(rst),
.cs(1),
.i_data(addr),
.o_seg(o_seg),
.o_sel(o_sel));
endmodule | module top(
input clk,
input rst,
output[7:0] o_seg,
output[7:0] o_sel
); |
wire clk50;
wire seg7_cs;
wire[31:0] addr;
clk_div clk_div0(
.clkin(clk),
.rst(rst),
.clkout(clk50));
io_sel io_sel1(
.addr(32'h10010000),
.cs(1),
.seg7_cs(seg7_cs)
);
openmips_min_sopc openmips_min_sopc1(
.clk(clk),
.rst(rst),
.data0(addr)
);
seg7x16 seg7x16_1(
.clk(clk),
.reset(rst),
.cs(1),
.i_data(addr),
.o_seg(o_seg),
.o_sel(o_sel));
endmodule | 4 |
140,897 | data/full_repos/permissive/92634379/Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/openmips_min_sopc.v | 92,634,379 | openmips_min_sopc.v | v | 81 | 60 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbe in position 4: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Program/Small\n ... Looked in:\n data/full_repos/permissive/92634379/Small/Program/Small\n data/full_repos/permissive/92634379/Small/Program/Small.v\n data/full_repos/permissive/92634379/Small/Program/Small.sv\n Program/Small\n Program/Small.v\n Program/Small.sv\n obj_dir/Program/Small\n obj_dir/Program/Small.v\n obj_dir/Program/Small.sv\n%Error: Cannot find file containing module: Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11,data/full_repos/permissive/92634379\n%Error: Cannot find file containing module: data/full_repos/permissive/92634379/Small\n%Error: Cannot find file containing module: Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/openmips_min_sopc.v\n%Error: Exiting due to 4 error(s)\n' | 309,893 | module | module openmips_min_sopc(
input wire clk,
input wire rst,
output wire[`DataBus] data0,
input wire[7:0] direction,
output wire signal,
output wire[15:0] point,
input wire[7:0] AppleX,
input wire[7:0] AppleY,
output wire[7:0] snake,
inout wire[1:0] gamestatus
);
wire[`InstAddrBus] inst_addr;
wire[`InstBus] inst;
wire rom_ce;
wire mem_we_i;
wire[`RegBus] mem_addr_i;
wire[`RegBus] mem_data_i;
wire[`RegBus] mem_data_o;
wire[3:0] mem_sel_i;
wire mem_ce_i;
wire[5:0] int;
wire timer_int;
assign int = {5'b00000, timer_int};
openmips openmips0(
.clk(clk),
.rst(rst),
.rom_addr_o(inst_addr),
.rom_data_i(inst),
.rom_ce_o(rom_ce),
.int_i(int),
.ram_we_o(mem_we_i),
.ram_addr_o(mem_addr_i),
.ram_sel_o(mem_sel_i),
.ram_data_o(mem_data_i),
.ram_data_i(mem_data_o),
.ram_ce_o(mem_ce_i),
.timer_int_o(timer_int)
);
inst_rom inst_rom0(
.ce(rom_ce),
.addr(inst_addr),
.inst(inst)
);
data_ram data_ram0(
.clk(clk),
.ce(mem_ce_i),
.we(mem_we_i),
.addr(mem_addr_i),
.sel(mem_sel_i),
.data_i(mem_data_i),
.data_o(mem_data_o),
.check(data0),
.direction(direction),
.signal(signal),
.point(point),
.AppleX(AppleX),
.AppleY(AppleY),
.snake(snake),
.gamestatus(gamestatus)
);
endmodule | module openmips_min_sopc(
input wire clk,
input wire rst,
output wire[`DataBus] data0,
input wire[7:0] direction,
output wire signal,
output wire[15:0] point,
input wire[7:0] AppleX,
input wire[7:0] AppleY,
output wire[7:0] snake,
inout wire[1:0] gamestatus
); |
wire[`InstAddrBus] inst_addr;
wire[`InstBus] inst;
wire rom_ce;
wire mem_we_i;
wire[`RegBus] mem_addr_i;
wire[`RegBus] mem_data_i;
wire[`RegBus] mem_data_o;
wire[3:0] mem_sel_i;
wire mem_ce_i;
wire[5:0] int;
wire timer_int;
assign int = {5'b00000, timer_int};
openmips openmips0(
.clk(clk),
.rst(rst),
.rom_addr_o(inst_addr),
.rom_data_i(inst),
.rom_ce_o(rom_ce),
.int_i(int),
.ram_we_o(mem_we_i),
.ram_addr_o(mem_addr_i),
.ram_sel_o(mem_sel_i),
.ram_data_o(mem_data_i),
.ram_data_i(mem_data_o),
.ram_ce_o(mem_ce_i),
.timer_int_o(timer_int)
);
inst_rom inst_rom0(
.ce(rom_ce),
.addr(inst_addr),
.inst(inst)
);
data_ram data_ram0(
.clk(clk),
.ce(mem_ce_i),
.we(mem_we_i),
.addr(mem_addr_i),
.sel(mem_sel_i),
.data_i(mem_data_i),
.data_o(mem_data_o),
.check(data0),
.direction(direction),
.signal(signal),
.point(point),
.AppleX(AppleX),
.AppleY(AppleY),
.snake(snake),
.gamestatus(gamestatus)
);
endmodule | 4 |
140,899 | data/full_repos/permissive/92634379/Small Program/Small Program.srcs/sources_1/imports/new/VGA_Control.v | 92,634,379 | VGA_Control.v | v | 90 | 82 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xbf in position 6: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Program/Small\n ... Looked in:\n data/full_repos/permissive/92634379/Small/Program/Small\n data/full_repos/permissive/92634379/Small/Program/Small.v\n data/full_repos/permissive/92634379/Small/Program/Small.sv\n Program/Small\n Program/Small.v\n Program/Small.sv\n obj_dir/Program/Small\n obj_dir/Program/Small.v\n obj_dir/Program/Small.sv\n%Error: Cannot find file containing module: Program.srcs/sources_1/imports/new,data/full_repos/permissive/92634379\n%Error: Cannot find file containing module: data/full_repos/permissive/92634379/Small\n%Error: Cannot find file containing module: Program.srcs/sources_1/imports/new/VGA_Control.v\n%Error: Exiting due to 4 error(s)\n' | 309,899 | module | module VGA_Control
(
input clk,
input rst,
input [7:0]snake,
input [7:0]apple_x,
input [7:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
);
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 7'b0000_000;
localparam HEAD = 7'b0000_001;
localparam BODY = 7'b0000_010;
localparam WALL = 7'b0000_011;
localparam HEAD_COLOR = 12'b0000_1111_0000;
localparam BODY_COLOR = 12'b0000_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or posedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule | module VGA_Control
(
input clk,
input rst,
input [7:0]snake,
input [7:0]apple_x,
input [7:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
); |
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 7'b0000_000;
localparam HEAD = 7'b0000_001;
localparam BODY = 7'b0000_010;
localparam WALL = 7'b0000_011;
localparam HEAD_COLOR = 12'b0000_1111_0000;
localparam BODY_COLOR = 12'b0000_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or posedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule | 4 |
140,900 | data/full_repos/permissive/92634379/Small Program/Small Program.srcs/sources_1/new/Apple.v | 92,634,379 | Apple.v | v | 55 | 139 | [] | [] | [] | [(23, 54)] | null | null | 1: b'%Error: Cannot find file containing module: Program/Small\n ... Looked in:\n data/full_repos/permissive/92634379/Small/Program/Small\n data/full_repos/permissive/92634379/Small/Program/Small.v\n data/full_repos/permissive/92634379/Small/Program/Small.sv\n Program/Small\n Program/Small.v\n Program/Small.sv\n obj_dir/Program/Small\n obj_dir/Program/Small.v\n obj_dir/Program/Small.sv\n%Error: Cannot find file containing module: Program.srcs/sources_1/new,data/full_repos/permissive/92634379\n%Error: Cannot find file containing module: data/full_repos/permissive/92634379/Small\n%Error: Cannot find file containing module: Program.srcs/sources_1/new/Apple.v\n%Error: Exiting due to 4 error(s)\n' | 309,901 | module | module Apple(
input clk,
input rst,
input signal,
output reg[7:0] apple_x,
output reg[7:0] apple_y
);
reg [31:0]clk_cnt;
reg [10:0]random_num;
always@(posedge clk)
random_num <= random_num + 999;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
apple_x <= 24;
apple_y <= 10;
end
else begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 250_000) begin
clk_cnt <= 0;
if(signal) begin
apple_x <= (random_num[10:5] > 38) ? (random_num[10:5] - 25) : (random_num[10:5] == 0) ? 1 : random_num[10:5];
apple_y <= (random_num[4:0] > 28) ? (random_num[4:0] - 3) : (random_num[4:0] == 0) ? 1:random_num[4:0];
end
end
end
end
endmodule | module Apple(
input clk,
input rst,
input signal,
output reg[7:0] apple_x,
output reg[7:0] apple_y
); |
reg [31:0]clk_cnt;
reg [10:0]random_num;
always@(posedge clk)
random_num <= random_num + 999;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
apple_x <= 24;
apple_y <= 10;
end
else begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 250_000) begin
clk_cnt <= 0;
if(signal) begin
apple_x <= (random_num[10:5] > 38) ? (random_num[10:5] - 25) : (random_num[10:5] == 0) ? 1 : random_num[10:5];
apple_y <= (random_num[4:0] > 28) ? (random_num[4:0] - 3) : (random_num[4:0] == 0) ? 1:random_num[4:0];
end
end
end
end
endmodule | 4 |
140,901 | data/full_repos/permissive/92634379/Small Program/Small Program.srcs/sources_1/new/Key.v | 92,634,379 | Key.v | v | 76 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb0 in position 471: invalid start byte | null | 1: b'%Error: Cannot find file containing module: Program/Small\n ... Looked in:\n data/full_repos/permissive/92634379/Small/Program/Small\n data/full_repos/permissive/92634379/Small/Program/Small.v\n data/full_repos/permissive/92634379/Small/Program/Small.sv\n Program/Small\n Program/Small.v\n Program/Small.sv\n obj_dir/Program/Small\n obj_dir/Program/Small.v\n obj_dir/Program/Small.sv\n%Error: Cannot find file containing module: Program.srcs/sources_1/new,data/full_repos/permissive/92634379\n%Error: Cannot find file containing module: data/full_repos/permissive/92634379/Small\n%Error: Cannot find file containing module: Program.srcs/sources_1/new/Key.v\n%Error: Exiting due to 4 error(s)\n' | 309,902 | module | module Key
( input clk,
input rst,
input left,
input right,
input up,
input down,
output reg[7:0] direction
);
reg [31:0]clk_cnt;
reg left_key_last;
reg right_key_last;
reg up_key_last;
reg down_key_last;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
direction <= 8'b0;
left_key_last <= 0;
right_key_last <= 0;
up_key_last <= 0;
down_key_last <= 0;
end
else begin
if(clk_cnt == 5_0000) begin
clk_cnt <= 0;
left_key_last <= left;
right_key_last <= right;
up_key_last <= up;
down_key_last <= down;
if(left_key_last == 0 && left == 1)
direction <= 8'b0000_0001;
if(right_key_last == 0 && right == 1)
direction <= 8'b0000_0010;
if(up_key_last == 0 && up == 1)
direction <= 8'b0000_0011;
if(down_key_last == 0 && down == 1)
direction <= 8'b0000_0100;
end
else begin
clk_cnt <= clk_cnt + 1;
direction <= 8'b0000_0000;
end
end
end
endmodule | module Key
( input clk,
input rst,
input left,
input right,
input up,
input down,
output reg[7:0] direction
); |
reg [31:0]clk_cnt;
reg left_key_last;
reg right_key_last;
reg up_key_last;
reg down_key_last;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
direction <= 8'b0;
left_key_last <= 0;
right_key_last <= 0;
up_key_last <= 0;
down_key_last <= 0;
end
else begin
if(clk_cnt == 5_0000) begin
clk_cnt <= 0;
left_key_last <= left;
right_key_last <= right;
up_key_last <= up;
down_key_last <= down;
if(left_key_last == 0 && left == 1)
direction <= 8'b0000_0001;
if(right_key_last == 0 && right == 1)
direction <= 8'b0000_0010;
if(up_key_last == 0 && up == 1)
direction <= 8'b0000_0011;
if(down_key_last == 0 && down == 1)
direction <= 8'b0000_0100;
end
else begin
clk_cnt <= clk_cnt + 1;
direction <= 8'b0000_0000;
end
end
end
endmodule | 4 |
140,902 | data/full_repos/permissive/92634379/Small Program/Small Program.srcs/sources_1/new/Small Program Top.v | 92,634,379 | Small Program Top.v | v | 110 | 83 | [] | [] | [] | [(23, 109)] | null | null | 1: b'%Error: Cannot find file containing module: Program/Small\n ... Looked in:\n data/full_repos/permissive/92634379/Small/Program/Small\n data/full_repos/permissive/92634379/Small/Program/Small.v\n data/full_repos/permissive/92634379/Small/Program/Small.sv\n Program/Small\n Program/Small.v\n Program/Small.sv\n obj_dir/Program/Small\n obj_dir/Program/Small.v\n obj_dir/Program/Small.sv\n%Error: Cannot find file containing module: Program.srcs/sources_1/new,data/full_repos/permissive/92634379\n%Error: Cannot find file containing module: data/full_repos/permissive/92634379/Small\n%Error: Cannot find file containing module: Program.srcs/sources_1/new/Small\n%Error: Cannot find file containing module: Program\n%Error: Cannot find file containing module: Top.v\n%Error: Exiting due to 6 error(s)\n' | 309,903 | module | module Small_Program_Top(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
);
wire[7:0] direction;
wire[7:0] appleX;
wire[7:0] appleY;
wire[15:0] point;
wire[1:0] game_status;
wire[7:0] snake;
wire[9:0] pos_x;
wire[9:0] pos_y;
wire clk0;
wire clk1;
clk_div clk_div0(
.clkin(clk),
.clkout(clk0));
clk_div clk_div1(
.clkin(clk0),
.clkout(clk1));
Key key0(
.clk(clk0),
.rst(rst),
.left(left),
.right(right),
.up(up),
.down(down),
.direction(direction));
Apple apple0(
.clk(clk0),
.rst(rst),
.signal(signal),
.apple_x(appleX),
.apple_y(appleY));
openmips_min_sopc openmips_min_sopc0(
.clk(clk0),
.rst(rst),
.direction(direction),
.signal(signal),
.point(point),
.AppleX(appleX),
.AppleY(appleY),
.snake(snake),
.gamestatus(game_status)
);
Seg_Display seg_display0
(
.clk(clk0),
.rst(rst),
.add_cube(signal),
.game_status(game_status),
.point(point),
.seg_out(seg_out),
.sel(sel)
);
VGA_Control vga1(
.clk(clk1),
.rst(rst),
.snake(snake),
.apple_x(appleX),
.apple_y(appleY),
.x_pos(pos_x),
.y_pos(pos_y),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out));
endmodule | module Small_Program_Top(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
); |
wire[7:0] direction;
wire[7:0] appleX;
wire[7:0] appleY;
wire[15:0] point;
wire[1:0] game_status;
wire[7:0] snake;
wire[9:0] pos_x;
wire[9:0] pos_y;
wire clk0;
wire clk1;
clk_div clk_div0(
.clkin(clk),
.clkout(clk0));
clk_div clk_div1(
.clkin(clk0),
.clkout(clk1));
Key key0(
.clk(clk0),
.rst(rst),
.left(left),
.right(right),
.up(up),
.down(down),
.direction(direction));
Apple apple0(
.clk(clk0),
.rst(rst),
.signal(signal),
.apple_x(appleX),
.apple_y(appleY));
openmips_min_sopc openmips_min_sopc0(
.clk(clk0),
.rst(rst),
.direction(direction),
.signal(signal),
.point(point),
.AppleX(appleX),
.AppleY(appleY),
.snake(snake),
.gamestatus(game_status)
);
Seg_Display seg_display0
(
.clk(clk0),
.rst(rst),
.add_cube(signal),
.game_status(game_status),
.point(point),
.seg_out(seg_out),
.sel(sel)
);
VGA_Control vga1(
.clk(clk1),
.rst(rst),
.snake(snake),
.apple_x(appleX),
.apple_y(appleY),
.x_pos(pos_x),
.y_pos(pos_y),
.hsync(hsync),
.vsync(vsync),
.color_out(color_out));
endmodule | 4 |
140,904 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/Game_Ctrl_Unit.v | 92,634,379 | Game_Ctrl_Unit.v | v | 65 | 60 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd3 in position 582: invalid continuation byte | data/verilator_xmls/a37fcc73-3c3a-47d6-969a-972206741fd1.xml | null | 309,908 | module | module Game_Ctrl_Unit
(
input clk,
input rst,
input key1_press,
input key2_press,
input key3_press,
input key4_press,
output reg [1:0]game_status,
input hit_wall,
input hit_body,
output reg die_flash,
output reg restart
);
localparam RESTART = 2'b00;
localparam START = 2'b01;
localparam PLAY = 2'b10;
localparam DIE = 2'b11;
reg[31:0]clk_cnt;
always@(posedge clk or negedge rst)
begin
if(!rst) begin
game_status <= START;
clk_cnt <= 0;
die_flash <= 1;
restart <= 0;
end
else begin
case(game_status)
RESTART:begin
if(clk_cnt <= 5) begin
clk_cnt <= clk_cnt + 1;
restart <= 1;
end
else begin
game_status <= START;
clk_cnt <= 0;
restart <= 0;
end
end
START:begin
if (key1_press | key2_press | key3_press | key4_press)
game_status <= PLAY;
else
game_status <= START;
end
PLAY:begin
if(hit_wall | hit_body)
game_status <= DIE;
else
game_status <= PLAY;
end
DIE:begin
die_flash <= 1;
clk_cnt <= 0;
game_status <= RESTART;
end
endcase
end
end
endmodule | module Game_Ctrl_Unit
(
input clk,
input rst,
input key1_press,
input key2_press,
input key3_press,
input key4_press,
output reg [1:0]game_status,
input hit_wall,
input hit_body,
output reg die_flash,
output reg restart
); |
localparam RESTART = 2'b00;
localparam START = 2'b01;
localparam PLAY = 2'b10;
localparam DIE = 2'b11;
reg[31:0]clk_cnt;
always@(posedge clk or negedge rst)
begin
if(!rst) begin
game_status <= START;
clk_cnt <= 0;
die_flash <= 1;
restart <= 0;
end
else begin
case(game_status)
RESTART:begin
if(clk_cnt <= 5) begin
clk_cnt <= clk_cnt + 1;
restart <= 1;
end
else begin
game_status <= START;
clk_cnt <= 0;
restart <= 0;
end
end
START:begin
if (key1_press | key2_press | key3_press | key4_press)
game_status <= PLAY;
else
game_status <= START;
end
PLAY:begin
if(hit_wall | hit_body)
game_status <= DIE;
else
game_status <= PLAY;
end
DIE:begin
die_flash <= 1;
clk_cnt <= 0;
game_status <= RESTART;
end
endcase
end
end
endmodule | 4 |
140,906 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/Seg_Display.v | 92,634,379 | Seg_Display.v | v | 163 | 50 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xca in position 2: invalid continuation byte | data/verilator_xmls/c51b6542-ec89-4b7d-9f0e-f3fd505cc335.xml | null | 309,910 | module | module Seg_Display
(
input clk,
input rst,
input add_cube,
inout [1:0]game_status,
output reg[15:0]point,
output reg[7:0]seg_out,
output reg[3:0]sel
);
localparam RESTART = 2'b00;
reg[31:0]clk_cnt;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else if (game_status == RESTART) begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else
begin
if(clk_cnt <= 20_0000)
begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 5_0000)
begin
sel <= 4'b1110;
case(point[3:0])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 10_0000)
begin
sel <= 4'b1101;
case(point[7:4])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 15_0000)
begin
sel <= 4'b1011;
case(point[11:8])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 20_0000)
begin
sel <= 4'b0111;
case(point[15:12])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
end
else
clk_cnt <= 0;
end
end
reg addcube_state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
point <= 0;
addcube_state <= 0;
end
else if (game_status == RESTART) begin
point <= 0;
addcube_state <= 0;
end
else begin
case(addcube_state)
0: begin
if(add_cube) begin
if(point[3:0] < 9)
point[3:0] <= point[3:0] + 1;
else begin
point[3:0] <= 0;
if(point[7:4] < 9)
point[7:4] <= point[7:4] + 1;
else begin
point[7:4] <= 0;
if(point[11:8] < 9)
point[11:8] <= point[11:8] + 1;
else begin
point[11:8] <= 0;
point[15:12] <= point[15:12] + 1;
end
end
end
addcube_state <= 1;
end
end
1: begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
endmodule | module Seg_Display
(
input clk,
input rst,
input add_cube,
inout [1:0]game_status,
output reg[15:0]point,
output reg[7:0]seg_out,
output reg[3:0]sel
); |
localparam RESTART = 2'b00;
reg[31:0]clk_cnt;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else if (game_status == RESTART) begin
seg_out <= 0;
clk_cnt <= 0;
sel <= 0;
end
else
begin
if(clk_cnt <= 20_0000)
begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 5_0000)
begin
sel <= 4'b1110;
case(point[3:0])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 10_0000)
begin
sel <= 4'b1101;
case(point[7:4])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 15_0000)
begin
sel <= 4'b1011;
case(point[11:8])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
else if(clk_cnt == 20_0000)
begin
sel <= 4'b0111;
case(point[15:12])
4'b0000:seg_out <= 8'b1100_0000;
4'b0001:seg_out <= 8'b1111_1001;
4'b0010:seg_out <= 8'b1010_0100;
4'b0011:seg_out <= 8'b1011_0000;
4'b0100:seg_out <= 8'b1001_1001;
4'b0101:seg_out <= 8'b1001_0010;
4'b0110:seg_out <= 8'b1000_0010;
4'b0111:seg_out <= 8'b1111_1000;
4'b1000:seg_out <= 8'b1000_0000;
4'b1001:seg_out <= 8'b1001_0000;
default;
endcase
end
end
else
clk_cnt <= 0;
end
end
reg addcube_state;
always@(posedge clk or negedge rst)
begin
if(!rst)
begin
point <= 0;
addcube_state <= 0;
end
else if (game_status == RESTART) begin
point <= 0;
addcube_state <= 0;
end
else begin
case(addcube_state)
0: begin
if(add_cube) begin
if(point[3:0] < 9)
point[3:0] <= point[3:0] + 1;
else begin
point[3:0] <= 0;
if(point[7:4] < 9)
point[7:4] <= point[7:4] + 1;
else begin
point[7:4] <= 0;
if(point[11:8] < 9)
point[11:8] <= point[11:8] + 1;
else begin
point[11:8] <= 0;
point[15:12] <= point[15:12] + 1;
end
end
end
addcube_state <= 1;
end
end
1: begin
if(!add_cube)
addcube_state <= 0;
end
endcase
end
end
endmodule | 4 |
140,907 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/Snake_Eating_Apple.v | 92,634,379 | Snake_Eating_Apple.v | v | 45 | 116 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb9 in position 4: invalid start byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/Snake_Eating_Apple.v:34: Operator EQ expects 6 bits on the LHS, but LHS\'s VARREF \'apple_y\' generates 5 bits.\n : ... In instance Snake_Eatting_Apple\n if(apple_x == head_x && apple_y == head_y) begin\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 309,912 | module | module Snake_Eatting_Apple
(
input clk,
input rst,
input [5:0]head_x,
input [5:0]head_y,
output reg [5:0]apple_x,
output reg [4:0]apple_y,
output reg add_cube
);
reg [31:0]clk_cnt;
reg [10:0]random_num;
always@(posedge clk)
random_num <= random_num + 999;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
apple_x <= 24;
apple_y <= 10;
add_cube <= 0;
end
else begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 250_000) begin
clk_cnt <= 0;
if(apple_x == head_x && apple_y == head_y) begin
add_cube <= 1;
apple_x <= (random_num[10:5] > 38) ? (random_num[10:5] - 25) : (random_num[10:5] == 0) ? 1 : random_num[10:5];
apple_y <= (random_num[4:0] > 28) ? (random_num[4:0] - 3) : (random_num[4:0] == 0) ? 1:random_num[4:0];
end
else
add_cube <= 0;
end
end
end
endmodule | module Snake_Eatting_Apple
(
input clk,
input rst,
input [5:0]head_x,
input [5:0]head_y,
output reg [5:0]apple_x,
output reg [4:0]apple_y,
output reg add_cube
); |
reg [31:0]clk_cnt;
reg [10:0]random_num;
always@(posedge clk)
random_num <= random_num + 999;
always@(posedge clk or negedge rst) begin
if(!rst) begin
clk_cnt <= 0;
apple_x <= 24;
apple_y <= 10;
add_cube <= 0;
end
else begin
clk_cnt <= clk_cnt+1;
if(clk_cnt == 250_000) begin
clk_cnt <= 0;
if(apple_x == head_x && apple_y == head_y) begin
add_cube <= 1;
apple_x <= (random_num[10:5] > 38) ? (random_num[10:5] - 25) : (random_num[10:5] == 0) ? 1 : random_num[10:5];
apple_y <= (random_num[4:0] > 28) ? (random_num[4:0] - 3) : (random_num[4:0] == 0) ? 1:random_num[4:0];
end
else
add_cube <= 0;
end
end
end
endmodule | 4 |
140,909 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v | 92,634,379 | top_greedy_snake.v | v | 125 | 37 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xb6 in position 2: invalid start byte | null | 1: b"%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:44: Cannot find file containing module: 'Game_Ctrl_Unit'\n Game_Ctrl_Unit U1 (\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/Game_Ctrl_Unit\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/Game_Ctrl_Unit.v\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/Game_Ctrl_Unit.sv\n Game_Ctrl_Unit\n Game_Ctrl_Unit.v\n Game_Ctrl_Unit.sv\n obj_dir/Game_Ctrl_Unit\n obj_dir/Game_Ctrl_Unit.v\n obj_dir/Game_Ctrl_Unit.sv\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:58: Cannot find file containing module: 'Snake_Eatting_Apple'\n Snake_Eatting_Apple U2 (\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:68: Cannot find file containing module: 'Snake'\n Snake U3 (\n ^~~~~\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:89: Cannot find file containing module: 'VGA_top'\n VGA_top U4 (\n ^~~~~~~\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:102: Cannot find file containing module: 'Key'\n Key U5 (\n ^~~\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/top_greedy_snake.v:115: Cannot find file containing module: 'Seg_Display'\n Seg_Display U6 (\n ^~~~~~~~~~~\n%Error: Exiting due to 6 error(s)\n" | 309,914 | module | module top_greedy_snake
(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
);
wire left_key_press;
wire right_key_press;
wire up_key_press;
wire down_key_press;
wire [1:0]snake;
wire [9:0]x_pos;
wire [9:0]y_pos;
wire [5:0]apple_x;
wire [4:0]apple_y;
wire [5:0]head_x;
wire [5:0]head_y;
wire add_cube;
wire[1:0]game_status;
wire hit_wall;
wire hit_body;
wire die_flash;
wire restart;
wire [6:0]cube_num;
wire rst_n;
wire [15:0] point;
assign rst_n = ~rst;
Game_Ctrl_Unit U1 (
.clk(clk),
.rst(rst_n),
.key1_press(left_key_press),
.key2_press(right_key_press),
.key3_press(up_key_press),
.key4_press(down_key_press),
.game_status(game_status),
.hit_wall(hit_wall),
.hit_body(hit_body),
.die_flash(die_flash),
.restart(restart)
);
Snake_Eatting_Apple U2 (
.clk(clk),
.rst(rst_n),
.apple_x(apple_x),
.apple_y(apple_y),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube)
);
Snake U3 (
.clk(clk),
.rst(rst_n),
.left_press(left_key_press),
.right_press(right_key_press),
.up_press(up_key_press),
.down_press(down_key_press),
.snake(snake),
.x_pos(x_pos),
.y_pos(y_pos),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube),
.game_status(game_status),
.cube_num(cube_num),
.hit_body(hit_body),
.hit_wall(hit_wall),
.die_flash(die_flash),
.point(point)
);
VGA_top U4 (
.clk(clk),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
Key U5 (
.clk(clk),
.rst(rst_n),
.left(left),
.right(right),
.up(up),
.down(down),
.left_key_press(left_key_press),
.right_key_press(right_key_press),
.up_key_press(up_key_press),
.down_key_press(down_key_press)
);
Seg_Display U6 (
.clk(clk),
.rst(rst_n),
.add_cube(add_cube),
.game_status(game_status),
.seg_out(seg_out),
.sel(sel),
.point(point)
);
endmodule | module top_greedy_snake
(
input clk,
input rst,
input left,
input right,
input up,
input down,
output hsync,
output vsync,
output [11:0]color_out,
output [7:0]seg_out,
output [3:0]sel
); |
wire left_key_press;
wire right_key_press;
wire up_key_press;
wire down_key_press;
wire [1:0]snake;
wire [9:0]x_pos;
wire [9:0]y_pos;
wire [5:0]apple_x;
wire [4:0]apple_y;
wire [5:0]head_x;
wire [5:0]head_y;
wire add_cube;
wire[1:0]game_status;
wire hit_wall;
wire hit_body;
wire die_flash;
wire restart;
wire [6:0]cube_num;
wire rst_n;
wire [15:0] point;
assign rst_n = ~rst;
Game_Ctrl_Unit U1 (
.clk(clk),
.rst(rst_n),
.key1_press(left_key_press),
.key2_press(right_key_press),
.key3_press(up_key_press),
.key4_press(down_key_press),
.game_status(game_status),
.hit_wall(hit_wall),
.hit_body(hit_body),
.die_flash(die_flash),
.restart(restart)
);
Snake_Eatting_Apple U2 (
.clk(clk),
.rst(rst_n),
.apple_x(apple_x),
.apple_y(apple_y),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube)
);
Snake U3 (
.clk(clk),
.rst(rst_n),
.left_press(left_key_press),
.right_press(right_key_press),
.up_press(up_key_press),
.down_press(down_key_press),
.snake(snake),
.x_pos(x_pos),
.y_pos(y_pos),
.head_x(head_x),
.head_y(head_y),
.add_cube(add_cube),
.game_status(game_status),
.cube_num(cube_num),
.hit_body(hit_body),
.hit_wall(hit_wall),
.die_flash(die_flash),
.point(point)
);
VGA_top U4 (
.clk(clk),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
Key U5 (
.clk(clk),
.rst(rst_n),
.left(left),
.right(right),
.up(up),
.down(down),
.left_key_press(left_key_press),
.right_key_press(right_key_press),
.up_key_press(up_key_press),
.down_key_press(down_key_press)
);
Seg_Display U6 (
.clk(clk),
.rst(rst_n),
.add_cube(add_cube),
.game_status(game_status),
.seg_out(seg_out),
.sel(sel),
.point(point)
);
endmodule | 4 |
140,910 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v | 92,634,379 | VGA_Control.v | v | 90 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v:41: Operator ASSIGNDLY expects 10 bits on the Assign RHS, but Assign RHS\'s SUB generates 32 or 20 bits.\n : ... In instance VGA_Control\n x_pos <= clk_cnt - 144;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v:78: Operator ASSIGN expects 12 bits on the Assign RHS, but Assign RHS\'s CONST \'3\'h5\' generates 3 bits.\n : ... In instance VGA_Control\n color_out = 3\'b101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v:70: Operator EQ expects 6 bits on the RHS, but RHS\'s VARREF \'apple_y\' generates 5 bits.\n : ... In instance VGA_Control\n if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v:67: Comparison is constant due to unsigned arithmetic\n : ... In instance VGA_Control\n if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin\n ^~\n%Warning-UNSIGNED: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_Control.v:67: Comparison is constant due to unsigned arithmetic\n : ... In instance VGA_Control\n if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin\n ^~\n%Error: Exiting due to 5 warning(s)\n' | 309,915 | module | module VGA_Control
(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
);
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 2'b00;
localparam HEAD = 2'b01;
localparam BODY = 2'b10;
localparam WALL = 2'b11;
localparam HEAD_COLOR = 12'b1010_1111_0000;
localparam BODY_COLOR = 12'b0001_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or negedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule | module VGA_Control
(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
); |
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 2'b00;
localparam HEAD = 2'b01;
localparam BODY = 2'b10;
localparam WALL = 2'b11;
localparam HEAD_COLOR = 12'b1010_1111_0000;
localparam BODY_COLOR = 12'b0001_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or negedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule | 4 |
140,911 | data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_top.v | 92,634,379 | VGA_top.v | v | 60 | 83 | [] | [] | [] | [(23, 59)] | null | null | 1: b"%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_top.v:39: Cannot find file containing module: 'clk_unit'\n clk_unit myclk(\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_unit\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_unit.v\n data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new,data/full_repos/permissive/92634379/clk_unit.sv\n clk_unit\n clk_unit.v\n clk_unit.sv\n obj_dir/clk_unit\n obj_dir/clk_unit.v\n obj_dir/clk_unit.sv\n%Error: data/full_repos/permissive/92634379/Snake/Snake.srcs/sources_1/new/VGA_top.v:46: Cannot find file containing module: 'VGA_Control'\n VGA_Control VGA\n ^~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,916 | module | module VGA_top(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output [9:0]x_pos,
output [9:0]y_pos,
output hsync,
output vsync,
output [11:0] color_out
);
wire clk_n;
clk_unit myclk(
.clk(clk),
.rst(rst),
.clk_n(clk_n)
);
VGA_Control VGA
(
.clk(clk_n),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
endmodule | module VGA_top(
input clk,
input rst,
input [1:0]snake,
input [5:0]apple_x,
input [4:0]apple_y,
output [9:0]x_pos,
output [9:0]y_pos,
output hsync,
output vsync,
output [11:0] color_out
); |
wire clk_n;
clk_unit myclk(
.clk(clk),
.rst(rst),
.clk_n(clk_n)
);
VGA_Control VGA
(
.clk(clk_n),
.rst(rst),
.hsync(hsync),
.vsync(vsync),
.snake(snake),
.color_out(color_out),
.x_pos(x_pos),
.y_pos(y_pos),
.apple_x(apple_x),
.apple_y(apple_y)
);
endmodule | 4 |
140,912 | data/full_repos/permissive/92697978/audioX_tb.v | 92,697,978 | audioX_tb.v | v | 34 | 42 | [] | [] | [] | null | line:6: before: "," | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92697978/audioX_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audioX_tb.v:24: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audioX_tb.v:26: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audioX_tb.v:29: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 255 * 100)\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audioX_tb.v:28: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Error: data/full_repos/permissive/92697978/audioX_tb.v:12: Cannot find file containing module: \'audioX\'\n audioX MUT\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audioX\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audioX.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audioX.sv\n audioX\n audioX.v\n audioX.sv\n obj_dir/audioX\n obj_dir/audioX.v\n obj_dir/audioX.sv\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,919 | module | module audioX_tb();
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0, aclr = 0;
wire pll_locked, fifo_full, right, left;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
audioX MUT
(
.sys_clock(clk),
.reset_(aclr),
.pll_locked(pll_locked),
.audio_fifo_full(fifo_full),
.audio_right(right),
.audio_left(left)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
#(CLOCK_PERIOD_NS * 255 * 100)
$finish;
end
endmodule | module audioX_tb(); |
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0, aclr = 0;
wire pll_locked, fifo_full, right, left;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
audioX MUT
(
.sys_clock(clk),
.reset_(aclr),
.pll_locked(pll_locked),
.audio_fifo_full(fifo_full),
.audio_right(right),
.audio_left(left)
);
initial
begin
#CLOCK_PERIOD_NS
aclr <= 1;
#CLOCK_PERIOD_NS
aclr <= 0;
#CLOCK_PERIOD_NS
#(CLOCK_PERIOD_NS * 255 * 100)
$finish;
end
endmodule | 0 |
140,913 | data/full_repos/permissive/92697978/audio_44_1kHz.v | 92,697,978 | audio_44_1kHz.v | v | 115 | 97 | [] | ['mit license'] | [] | null | line:16: before: "=" | null | 1: b"%Error: data/full_repos/permissive/92697978/audio_44_1kHz.v:31: Cannot find file containing module: 'pll_12bit_44_1kHz'\n pll_12bit_44_1kHz AUDIO_PLL (\n ^~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/pll_12bit_44_1kHz.sv\n pll_12bit_44_1kHz\n pll_12bit_44_1kHz.v\n pll_12bit_44_1kHz.sv\n obj_dir/pll_12bit_44_1kHz\n obj_dir/pll_12bit_44_1kHz.v\n obj_dir/pll_12bit_44_1kHz.sv\n%Error: data/full_repos/permissive/92697978/audio_44_1kHz.v:40: Cannot find file containing module: 'dsm_stereo'\n dsm_stereo #(AUDIO_BITS) AUDIO_DSM (\n ^~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 309,920 | module | module audio_44_1kHz
#(parameter AUDIO_BITS = 12)
(
input clk,
input aclr_,
input wreq,
input [(2*AUDIO_BITS)-1:0] sample,
output wire left_out,
output wire right_out,
output wire pll_locked,
output reg ready = 0,
output wire clk_audio
);
reg [(2*AUDIO_BITS)-1:0] sample_buf = 0;
reg [AUDIO_BITS-1:0] left_pcm = 0;
reg [AUDIO_BITS-1:0] right_pcm = 0;
reg [AUDIO_BITS-1:0] sample_clock = 0;
wire aclr;
assign aclr = !aclr_;
pll_12bit_44_1kHz AUDIO_PLL (
.areset(aclr),
.inclk0(clk),
.c0(clk_audio),
.locked(pll_locked)
);
dsm_stereo #(AUDIO_BITS) AUDIO_DSM (
.clk(clk_audio),
.aclr(aclr),
.left_pcm(left_pcm),
.right_pcm(right_pcm),
.left_out(left_out),
.right_out(right_out)
);
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
sample_buf <= 0;
else
if (wreq)
sample_buf <= sample;
else
sample_buf <= sample_buf;
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
ready <= 1;
else
if (wreq)
ready <= 0;
else if (sample_clock == 0)
ready <= 1;
else
ready <= ready;
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
begin
left_pcm <= 0;
right_pcm <= 0;
end
else
begin
if (sample_clock == 0 && !ready)
begin
left_pcm <= sample_buf[(AUDIO_BITS * 2)-1:AUDIO_BITS];
right_pcm <= sample_buf[AUDIO_BITS-1:0];
end
else if (sample_clock == 0 && ready)
begin
left_pcm <= 0;
right_pcm <= 0;
end
else
begin
left_pcm <= left_pcm;
right_pcm <= right_pcm;
end
end
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
sample_clock <= 0;
else
sample_clock <= sample_clock + 1;
end
endmodule | module audio_44_1kHz
#(parameter AUDIO_BITS = 12)
(
input clk,
input aclr_,
input wreq,
input [(2*AUDIO_BITS)-1:0] sample,
output wire left_out,
output wire right_out,
output wire pll_locked,
output reg ready = 0,
output wire clk_audio
); |
reg [(2*AUDIO_BITS)-1:0] sample_buf = 0;
reg [AUDIO_BITS-1:0] left_pcm = 0;
reg [AUDIO_BITS-1:0] right_pcm = 0;
reg [AUDIO_BITS-1:0] sample_clock = 0;
wire aclr;
assign aclr = !aclr_;
pll_12bit_44_1kHz AUDIO_PLL (
.areset(aclr),
.inclk0(clk),
.c0(clk_audio),
.locked(pll_locked)
);
dsm_stereo #(AUDIO_BITS) AUDIO_DSM (
.clk(clk_audio),
.aclr(aclr),
.left_pcm(left_pcm),
.right_pcm(right_pcm),
.left_out(left_out),
.right_out(right_out)
);
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
sample_buf <= 0;
else
if (wreq)
sample_buf <= sample;
else
sample_buf <= sample_buf;
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
ready <= 1;
else
if (wreq)
ready <= 0;
else if (sample_clock == 0)
ready <= 1;
else
ready <= ready;
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
begin
left_pcm <= 0;
right_pcm <= 0;
end
else
begin
if (sample_clock == 0 && !ready)
begin
left_pcm <= sample_buf[(AUDIO_BITS * 2)-1:AUDIO_BITS];
right_pcm <= sample_buf[AUDIO_BITS-1:0];
end
else if (sample_clock == 0 && ready)
begin
left_pcm <= 0;
right_pcm <= 0;
end
else
begin
left_pcm <= left_pcm;
right_pcm <= right_pcm;
end
end
end
always @(posedge clk_audio or posedge aclr or negedge pll_locked)
begin
if (aclr || !pll_locked)
sample_clock <= 0;
else
sample_clock <= sample_clock + 1;
end
endmodule | 0 |
140,914 | data/full_repos/permissive/92697978/audio_44_1kHz_tb.v | 92,697,978 | audio_44_1kHz_tb.v | v | 57 | 249 | [] | ['mit license'] | [] | null | line:46: before: "#" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:16: Unsupported: Ignoring delay on this delayed statement.\n always #(CLOCK_PERIOD_NS/2) clk <= !clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:38: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #150 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #CLOCK_PERIOD_NS\n ^\n%Warning-STMTDLY: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #(CLOCK_PERIOD_NS * 2 * 1150) \n ^\n%Error: data/full_repos/permissive/92697978/audio_44_1kHz_tb.v:24: Cannot find file containing module: \'audio_44_1kHz\'\n audio_44_1kHz #(AUDIO_BITS) MUT\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz.v\n data/full_repos/permissive/92697978,data/full_repos/permissive/92697978/audio_44_1kHz.sv\n audio_44_1kHz\n audio_44_1kHz.v\n audio_44_1kHz.sv\n obj_dir/audio_44_1kHz\n obj_dir/audio_44_1kHz.v\n obj_dir/audio_44_1kHz.sv\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 309,921 | module | module audio_44_1kHz_tb #(parameter AUDIO_BITS = 12) ();
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr_ = 1;
reg wreq = 0;
reg [(AUDIO_BITS*2)-1:0] sample = 0;
wire status, ready, pll_locked;
wire left_out, right_out;
audio_44_1kHz #(AUDIO_BITS) MUT
(
.clk(clk),
.aclr_(aclr_),
.wreq(wreq),
.sample(sample),
.left_out(left_out),
.right_out(right_out),
.pll_locked(pll_locked),
.ready(ready)
);
initial
begin
#CLOCK_PERIOD_NS
aclr_ <= 0;
#CLOCK_PERIOD_NS
aclr_ <= 1;
#CLOCK_PERIOD_NS
sample[(AUDIO_BITS*2)-1:AUDIO_BITS] <= 1024;
sample[AUDIO_BITS-1:0] <= 4000;
#150
#CLOCK_PERIOD_NS
wreq <= 1;
#CLOCK_PERIOD_NS
wreq <= 0;
#(CLOCK_PERIOD_NS * 2 * 1150)
$finish;
end
endmodule | module audio_44_1kHz_tb #(parameter AUDIO_BITS = 12) (); |
localparam CLOCK_PERIOD_NS = 20;
reg clk = 0;
always #(CLOCK_PERIOD_NS/2) clk <= !clk;
reg aclr_ = 1;
reg wreq = 0;
reg [(AUDIO_BITS*2)-1:0] sample = 0;
wire status, ready, pll_locked;
wire left_out, right_out;
audio_44_1kHz #(AUDIO_BITS) MUT
(
.clk(clk),
.aclr_(aclr_),
.wreq(wreq),
.sample(sample),
.left_out(left_out),
.right_out(right_out),
.pll_locked(pll_locked),
.ready(ready)
);
initial
begin
#CLOCK_PERIOD_NS
aclr_ <= 0;
#CLOCK_PERIOD_NS
aclr_ <= 1;
#CLOCK_PERIOD_NS
sample[(AUDIO_BITS*2)-1:AUDIO_BITS] <= 1024;
sample[AUDIO_BITS-1:0] <= 4000;
#150
#CLOCK_PERIOD_NS
wreq <= 1;
#CLOCK_PERIOD_NS
wreq <= 0;
#(CLOCK_PERIOD_NS * 2 * 1150)
$finish;
end
endmodule | 0 |
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