Unnamed: 0
int64 1
143k
| directory
stringlengths 39
203
| repo_id
float64 143k
552M
| file_name
stringlengths 3
107
| extension
stringclasses 6
values | no_lines
int64 5
304k
| max_line_len
int64 15
21.6k
| generation_keywords
stringclasses 3
values | license_whitelist_keywords
stringclasses 16
values | license_blacklist_keywords
stringclasses 4
values | icarus_module_spans
stringlengths 8
6.16k
⌀ | icarus_exception
stringlengths 12
124
⌀ | verilator_xml_output_path
stringlengths 60
60
⌀ | verilator_exception
stringlengths 33
1.53M
⌀ | file_index
int64 0
315k
| snippet_type
stringclasses 2
values | snippet
stringlengths 21
9.27M
| snippet_def
stringlengths 9
30.3k
| snippet_body
stringlengths 10
9.27M
| gh_stars
int64 0
1.61k
|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
141,057 | data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier.v | 93,424,147 | premier.v | v | 48 | 49 | [] | [] | [] | null | line:48: before: "endmodule" | null | 1: b"%Error: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier.v:48: syntax error, unexpected endmodule, expecting ',' or ';'\nendmodule\n^~~~~~~~~\n%Error: Cannot continue\n" | 310,859 | module | module blink #(parameter speed=32'd16499999)
(
input wire CLK,
output reg led
);
reg [31:0] cnt;
always @(posedge CLK)
begin
if (nct != speed)
cnt <= cnt + 1'd1;
else
cnt <= 32'd0;
end
wire clign;
always @(posedge clk)
begin
if (clign)
led <= ~led;
end
assign clign= (cnt == speed)
endmodule | module blink #(parameter speed=32'd16499999)
(
input wire CLK,
output reg led
); |
reg [31:0] cnt;
always @(posedge CLK)
begin
if (nct != speed)
cnt <= cnt + 1'd1;
else
cnt <= 32'd0;
end
wire clign;
always @(posedge clk)
begin
if (clign)
led <= ~led;
end
assign clign= (cnt == speed)
endmodule | 0 |
141,058 | data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier_tb.v | 93,424,147 | premier_tb.v | v | 23 | 45 | [] | [] | [] | null | line:13: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier_tb.v:10: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("premier.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier_tb.v:11: Unsupported or unknown PLI call: $dumpvars\n $dumpvars(0,premier_tb);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier_tb.v:14: syntax error, unexpected end, expecting \';\'\nend\n^~~\n%Warning-STMTDLY: data/full_repos/permissive/93424147/Icarus/OpenSolicium08/premier_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\n #40000 $finish\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 3 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,860 | module | module premier_tb;
output reg clock;
wire iled1;
wire iled2;
wire iled3;
initial
begin
$dumpfile("premier.vcd");
$dumpvars(0,premier_tb);
clock=0;
#40000 $finish
end
always
begin
#1 clock = !clock;
end
Premier premtb (clock, iled1, iled2, iled3);
endmodule | module premier_tb; |
output reg clock;
wire iled1;
wire iled2;
wire iled3;
initial
begin
$dumpfile("premier.vcd");
$dumpvars(0,premier_tb);
clock=0;
#40000 $finish
end
always
begin
#1 clock = !clock;
end
Premier premtb (clock, iled1, iled2, iled3);
endmodule | 0 |
141,059 | data/full_repos/permissive/93424147/ProgrammingFPGAs-LogiPi/chapter4/data_selector.v | 93,424,147 | data_selector.v | v | 34 | 92 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/1c5c3b2e-723c-4192-ad55-136b5c84b0b8.xml | null | 310,861 | module | module data_selector(
input A,
input B,
input SEL,
output reg Q
);
initial
begin
$display("RUN starting ...");
end
always @(A or B or SEL)
begin
if (SEL)
Q = A;
else
Q = B;
end
endmodule | module data_selector(
input A,
input B,
input SEL,
output reg Q
); |
initial
begin
$display("RUN starting ...");
end
always @(A or B or SEL)
begin
if (SEL)
Q = A;
else
Q = B;
end
endmodule | 0 |
141,060 | data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v | 93,530,040 | my_bram_tb.v | v | 117 | 83 | [] | [] | [] | null | line:114: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:29: Unexpected \'do\': \'do\' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\nwire [31:0]do;\n ^~\n%Error: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:30: syntax error, unexpected do, expecting \')\'\nmy_bram MB1(clk,en,we,re,addr,di,do);\n ^~\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:40: Unsupported: Ignoring delay on this delayed statement.\n #5 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:42: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:43: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:44: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "abcd";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:45: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:46: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:47: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:48: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "efgh";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:49: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:50: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:51: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:52: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:53: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "ijkl";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:55: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:56: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:57: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "mnop";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:58: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:59: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:60: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:61: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:62: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "qrst";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:63: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:64: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:65: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:66: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "uvwx";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:67: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:68: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 6;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:71: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "yzAB";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:72: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:73: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:74: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 7;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:75: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "CDEF";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:76: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:77: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:78: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 8;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:79: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "GHIJ";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:80: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:81: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:82: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:83: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "KLMN";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:84: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:85: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:86: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:87: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:88: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "OPQR";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:89: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:90: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:91: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 11;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:92: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "STUV";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:93: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:94: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:95: Unsupported: Ignoring delay on this delayed statement.\n #10 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:96: Unsupported: Ignoring delay on this delayed statement.\n #5 addr = 12;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:97: Unsupported: Ignoring delay on this delayed statement.\n #5 di = "WXYZ";\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:98: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:99: Unsupported: Ignoring delay on this delayed statement.\n #5 we = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:100: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:101: Unsupported: Ignoring delay on this delayed statement.\n #5 re = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:102: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:103: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 2; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:104: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 3; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 4; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:106: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 5; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:107: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 6; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:108: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 7; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:109: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 8; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:110: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 9;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:111: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 10; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:112: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 11; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:113: Unsupported: Ignoring delay on this delayed statement.\n #10 addr = 12; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93530040/my_bram.srcs/sim_1/new/my_bram_tb.v:114: Unsupported: Ignoring delay on this delayed statement.\n #100 $stop;\n ^\n%Error: Exiting due to 2 error(s), 74 warning(s)\n' | 310,864 | module | module my_bram_tb(
);
reg clk,we,re,en;
reg [4:0]addr;
reg [31:0]di;
wire [31:0]do;
my_bram MB1(clk,en,we,re,addr,di,do);
initial begin
clk = 0;
we = 0;
re = 0;
en = 0;
addr = 0;
di = 0;
end
always
#5 clk = ~clk;
always begin
#10 en = 1;
#5 addr = 0;
#5 di = "abcd";
#5 we = 1;
#5 we = 0;
#5 addr = 1;
#5 di = "efgh";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 2;
#5 di = "ijkl";
#5 we = 1;
#5 we = 0;
#5 addr = 3;
#5 di = "mnop";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 4;
#5 di = "qrst";
#5 we = 1;
#5 we = 0;
#5 addr = 5;
#5 di = "uvwx";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 6;
#5 di = "yzAB";
#5 we = 1;
#5 we = 0;
#5 addr = 7;
#5 di = "CDEF";
#5 we = 1;
#5 we = 0;
#5 addr = 8;
#5 di = "GHIJ";
#5 we = 1;
#5 we = 0;
#5 addr = 9;
#5 di = "KLMN";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 10;
#5 di = "OPQR";
#5 we = 1;
#5 we = 0;
#5 addr = 11;
#5 di = "STUV";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 12;
#5 di = "WXYZ";
#5 we = 1;
#5 we = 0;
#10 addr = 0;
#5 re = 1;
#10 addr = 1;
#10 addr = 2;
#10 addr = 3;
#10 addr = 4;
#10 addr = 5;
#10 addr = 6;
#10 addr = 7;
#10 addr = 8;
#10 addr = 9;
#10 addr = 10;
#10 addr = 11;
#10 addr = 12;
#100 $stop;
end
endmodule | module my_bram_tb(
); |
reg clk,we,re,en;
reg [4:0]addr;
reg [31:0]di;
wire [31:0]do;
my_bram MB1(clk,en,we,re,addr,di,do);
initial begin
clk = 0;
we = 0;
re = 0;
en = 0;
addr = 0;
di = 0;
end
always
#5 clk = ~clk;
always begin
#10 en = 1;
#5 addr = 0;
#5 di = "abcd";
#5 we = 1;
#5 we = 0;
#5 addr = 1;
#5 di = "efgh";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 2;
#5 di = "ijkl";
#5 we = 1;
#5 we = 0;
#5 addr = 3;
#5 di = "mnop";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 4;
#5 di = "qrst";
#5 we = 1;
#5 we = 0;
#5 addr = 5;
#5 di = "uvwx";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 6;
#5 di = "yzAB";
#5 we = 1;
#5 we = 0;
#5 addr = 7;
#5 di = "CDEF";
#5 we = 1;
#5 we = 0;
#5 addr = 8;
#5 di = "GHIJ";
#5 we = 1;
#5 we = 0;
#5 addr = 9;
#5 di = "KLMN";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 10;
#5 di = "OPQR";
#5 we = 1;
#5 we = 0;
#5 addr = 11;
#5 di = "STUV";
#5 we = 1;
#5 we = 0;
#10 en = 1;
#5 addr = 12;
#5 di = "WXYZ";
#5 we = 1;
#5 we = 0;
#10 addr = 0;
#5 re = 1;
#10 addr = 1;
#10 addr = 2;
#10 addr = 3;
#10 addr = 4;
#10 addr = 5;
#10 addr = 6;
#10 addr = 7;
#10 addr = 8;
#10 addr = 9;
#10 addr = 10;
#10 addr = 11;
#10 addr = 12;
#100 $stop;
end
endmodule | 0 |
141,061 | data/full_repos/permissive/93530040/my_bram.srcs/sources_1/new/my_bram.v | 93,530,040 | my_bram.v | v | 48 | 83 | [] | [] | [] | [(23, 47)] | null | null | 1: b"%Error: data/full_repos/permissive/93530040/my_bram.srcs/sources_1/new/my_bram.v:29: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.\n ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.\n output [31:0]do);\n ^~\n%Error: data/full_repos/permissive/93530040/my_bram.srcs/sources_1/new/my_bram.v:46: syntax error, unexpected do, expecting TYPE-IDENTIFIER\nassign do = RAM[read_addr];\n ^~\n%Error: Exiting due to 2 error(s)\n" | 310,865 | module | module my_bram(input clk,
input en,
input we,
input re,
input [3:0]addr,
input [31:0]di,
output [31:0]do);
reg [31:0] RAM [15:0];
reg [3:0] read_addr;
always @(posedge clk)begin
if (en)begin
if (we)
RAM[addr] <= di;
else if (re)
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule | module my_bram(input clk,
input en,
input we,
input re,
input [3:0]addr,
input [31:0]di,
output [31:0]do); |
reg [31:0] RAM [15:0];
reg [3:0] read_addr;
always @(posedge clk)begin
if (en)begin
if (we)
RAM[addr] <= di;
else if (re)
read_addr <= addr;
end
end
assign do = RAM[read_addr];
endmodule | 0 |
141,062 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | module alu32 (d, Cout, V, a, b, Cin, S); |
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | 0 |
141,063 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,064 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,065 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,066 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,067 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,068 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,069 | data/full_repos/permissive/93595154/assignment_1/alu32.v | 93,595,154 | alu32.v | v | 260 | 109 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5f1021fd-b2f6-486d-8ef8-b58b201bbb20.xml | null | 310,866 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,070 | data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v | 93,595,154 | alupipe_testbench.v | v | 132 | 164 | [] | [] | [] | [(2, 128)] | null | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:8: syntax error, unexpected ref, expecting IDENTIFIER or \'=\' or do or final\nreg [31:0] dontcare, str[0:33], ref[0:33], stma[0:33], stmb[0:33];\n ^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:23: syntax error, unexpected ref\nref[0] = 32\'h00000000; Vref[0] = 0; Coutref[0] = 0; Stm[0] = 3\'b100; stma[0] = 32\'h00000000; stmb[0] = 32\'h00000000; Cinstm[0] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:24: syntax error, unexpected ref\nref[1] = 32\'h00000000; Vref[1] = 0; Coutref[1] = 0; Stm[1] = 3\'b100; stma[1] = 32\'h00000000; stmb[1] = 32\'h00000000; Cinstm[1] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:25: syntax error, unexpected ref\nref[2] = 32\'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0; Stm[2] = 3\'b010; stma[2] = 32\'hFFFFFFFF; stmb[2] = 32\'h00000000; Cinstm[2] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:26: syntax error, unexpected ref\nref[3] = 32\'h00000000; Vref[3] = 0; Coutref[3] = 1; Stm[3] = 3\'b010; stma[3] = 32\'hFFFFFFFF; stmb[3] = 32\'h00000000; Cinstm[3] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:27: syntax error, unexpected ref\nref[4] = 32\'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; Stm[4] = 3\'b010; stma[4] = 32\'h7FFFFFFF; stmb[4] = 32\'h00000000; Cinstm[4] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:28: syntax error, unexpected ref\nref[5] = 32\'h80000000; Vref[5] = 1; Coutref[5] = 0; Stm[5] = 3\'b010; stma[5] = 32\'h7FFFFFFF; stmb[5] = 32\'h00000000; Cinstm[5] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:29: syntax error, unexpected ref\nref[6] = 32\'h00100166; Vref[6] = 1\'bx; Coutref[6] = 1\'bx; Stm[6] = 3\'b000; stma[6] = 32\'hF01010CA; stmb[6] = 32\'hF00011AC; Cinstm[6] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:30: syntax error, unexpected ref\nref[7] = 32\'h0EEF9997; Vref[7] = 1\'bx; Coutref[7] = 1\'bx; Stm[7] = 3\'b001; stma[7] = 32\'hF101CBA9; stmb[7] = 32\'h0011ADC1; Cinstm[7] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:31: syntax error, unexpected ref\nref[8] = 32\'h0000FFFF; Vref[8] = 1\'bx; Coutref[8] = 1\'bx; Stm[8] = 3\'b110; stma[8] = 32\'hFFFFFFFF; stmb[8] = 32\'h0000FFFF; Cinstm[8] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:32: syntax error, unexpected ref\nref[9] = 32\'hF111EFE9; Vref[9] = 1\'bx; Coutref[9] = 1\'bx; Stm[9] = 3\'b100; stma[9] = 32\'hF101CBA9; stmb[9] = 32\'h0011ADC1; Cinstm[9] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:33: syntax error, unexpected ref\nref[10] = 32\'h64424220; Vref[10] = 1\'bx; Coutref[10] = 1\'bx; Stm[10] = 3\'b010; stma[10] = 32\'h31312020; stmb[10] = 32\'h33112200; Cinstm[10] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:34: syntax error, unexpected ref\nref[11] = 32\'h64424221; Vref[11] = 1\'bx; Coutref[11] = 1\'bx; Stm[11] = 3\'b011; stma[11] = 32\'h31312020; stmb[11] = 32\'hCCEEDDFF; Cinstm[11] = 1; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:35: syntax error, unexpected ref\nref[12] = 32\'h00000001; Vref[12] = 1\'bx; Coutref[12] = 1\'bx; Stm[12] = 3\'b010; stma[12] = 32\'h00000000; stmb[12] = 32\'h00000000; Cinstm[12] = 1; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:36: syntax error, unexpected ref\nref[13] = 32\'h0000000F; Vref[13] = 1\'bx; Coutref[13] = 1\'bx; Stm[13] = 3\'b010; stma[13] = 32\'h0000000F; stmb[13] = 32\'h00000000; Cinstm[13] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:37: syntax error, unexpected ref\nref[14] = 32\'h00000010; Vref[14] = 1\'bx; Coutref[14] = 1\'bx; Stm[14] = 3\'b010; stma[14] = 32\'h0000000F; stmb[14] = 32\'h00000000; Cinstm[14] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:38: syntax error, unexpected ref\nref[15] = 32\'h000000FF; Vref[15] = 1\'bx; Coutref[15] = 1\'bx; Stm[15] = 3\'b010; stma[15] = 32\'h000000FF; stmb[15] = 32\'h00000000; Cinstm[15] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:39: syntax error, unexpected ref\nref[16] = 32\'h00000100; Vref[16] = 1\'bx; Coutref[16] = 1\'bx; Stm[16] = 3\'b010; stma[16] = 32\'h000000FF; stmb[16] = 32\'h00000000; Cinstm[16] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:40: syntax error, unexpected ref\nref[17] = 32\'h00000FFF; Vref[17] = 1\'bx; Coutref[17] = 1\'bx; Stm[17] = 3\'b010; stma[17] = 32\'h00000FFF; stmb[17] = 32\'h00000000; Cinstm[17] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:41: syntax error, unexpected ref\nref[18] = 32\'h00001000; Vref[18] = 1\'bx; Coutref[18] = 1\'bx; Stm[18] = 3\'b010; stma[18] = 32\'h00000FFF; stmb[18] = 32\'h00000000; Cinstm[18] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:42: syntax error, unexpected ref\nref[19] = 32\'h0000FFFF; Vref[19] = 1\'bx; Coutref[19] = 1\'bx; Stm[19] = 3\'b010; stma[19] = 32\'h0000FFFF; stmb[19] = 32\'h00000000; Cinstm[19] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:43: syntax error, unexpected ref\nref[20] = 32\'h00010000; Vref[20] = 1\'bx; Coutref[20] = 1\'bx; Stm[20] = 3\'b010; stma[20] = 32\'h0000FFFF; stmb[20] = 32\'h00000000; Cinstm[20] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:44: syntax error, unexpected ref\nref[21] = 32\'h000FFFFF; Vref[21] = 1\'bx; Coutref[21] = 1\'bx; Stm[21] = 3\'b010; stma[21] = 32\'h000FFFFF; stmb[21] = 32\'h00000000; Cinstm[21] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:45: syntax error, unexpected ref\nref[22] = 32\'h00100000; Vref[22] = 1\'bx; Coutref[22] = 1\'bx; Stm[22] = 3\'b010; stma[22] = 32\'h000FFFFF; stmb[22] = 32\'h00000000; Cinstm[22] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:46: syntax error, unexpected ref\nref[23] = 32\'h00FFFFFF; Vref[23] = 1\'bx; Coutref[23] = 1\'bx; Stm[23] = 3\'b010; stma[23] = 32\'h00FFFFFF; stmb[23] = 32\'h00000000; Cinstm[23] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:47: syntax error, unexpected ref\nref[24] = 32\'h01000000; Vref[24] = 1\'bx; Coutref[24] = 1\'bx; Stm[24] = 3\'b010; stma[24] = 32\'h00FFFFFF; stmb[24] = 32\'h00000000; Cinstm[24] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:48: syntax error, unexpected ref\nref[25] = 32\'h0FFFFFFF; Vref[25] = 1\'bx; Coutref[25] = 1\'bx; Stm[25] = 3\'b010; stma[25] = 32\'h0FFFFFFF; stmb[25] = 32\'h00000000; Cinstm[25] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:49: syntax error, unexpected ref\nref[26] = 32\'h10000000; Vref[26] = 1\'bx; Coutref[26] = 1\'bx; Stm[26] = 3\'b010; stma[26] = 32\'h0FFFFFFF; stmb[26] = 32\'h00000000; Cinstm[26] = 1;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:50: syntax error, unexpected ref\nref[27] = 32\'h00000000; Vref[27] = 1\'bx; Coutref[27] = 1\'bx; Stm[27] = 3\'b101; stma[27] = 32\'hFFFFFFFF; stmb[27] = 32\'h0000FFFF; Cinstm[27] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:51: syntax error, unexpected ref\nref[28] = 32\'hx; Vref[28] = 0; Coutref[28] = 0; Stm[28] = 3\'b010; stma[28] = 32\'h00000000; stmb[28] = 32\'h00000000; Cinstm[28] = 0; \n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:52: syntax error, unexpected ref\nref[29] = 32\'hx; Vref[29] = 0; Coutref[29] = 1; Stm[29] = 3\'b010; stma[29] = 32\'hFFFFFFFF; stmb[29] = 32\'hFFFFFFFF; Cinstm[29] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:53: syntax error, unexpected ref\nref[30] = 32\'hx; Vref[30] = 1; Coutref[30] = 1; Stm[30] = 3\'b010; stma[30] = 32\'h80000000; stmb[30] = 32\'h80000000; Cinstm[30] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:54: syntax error, unexpected ref\nref[31] = 32\'hx; Vref[31] = 1; Coutref[31] = 0; Stm[31] = 3\'b010; stma[31] = 32\'h40000000; stmb[31] = 32\'h40000000; Cinstm[31] = 0;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:55: syntax error, unexpected ref\nref[32] = 32\'hx; Vref[32] = 1\'bx; Coutref[32] =1\'bx; Stm[32] = 3\'hx; stma[32] = 32\'hx; stmb[32] = 32\'hx; Cinstm[32] =1\'bx;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:56: syntax error, unexpected ref\nref[33] = 32\'hx; Vref[33] =1\'bx; Coutref[33] =1\'bx; Stm[33] = 3\'hx; stma[33] = 32\'hx; stmb[33] = 32\'hx; Cinstm[33] =1\'bx;\n^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:60: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:73: Unsupported: Ignoring delay on this delayed statement.\n #12.5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:104: syntax error, unexpected ref, expecting TYPE-IDENTIFIER\n $display ("Time=%t \\n S=%b \\n Cin=%b \\n a=%b \\n b=%b \\n d=%b \\n ref=%b \\n",$realtime, Stm[k-2], Cinstm[k-2], stma[k-2], stmb[k-2], d, ref[k-2]);\n ^~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:109: syntax error, unexpected ref, expecting TYPE-IDENTIFIER\n if (( (ref[k-2] !== d) && (ref[k-2] !== dontcare) ) )\n ^~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:116: Unsupported: Ignoring delay on this delayed statement.\n #12.5 ;\n ^\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:120: syntax error, unexpected $display\n $display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");\n ^~~~~~~~\n%Error: data/full_repos/permissive/93595154/assignment_2/alupipe_testbench.v:123: syntax error, unexpected $display\n $display("---------------ERRORS. Mismatches Have Occured------------------");\n ^~~~~~~~\n%Error: Cannot continue\n' | 310,869 | module | module alupipe_testbench();
reg [31:0] a, b;
wire [31:0] d;
reg [2:0] S, Stm[0:33];
reg Cin, clk;
reg [31:0] dontcare, str[0:33], ref[0:33], stma[0:33], stmb[0:33];
reg Vstr[0:33], Vref[0:33], Coutstr[0:33], Coutref[0:33], Cinstm[0:33];
integer ntests, error, k, i;
alupipe dut(.abus(a), .bbus(b), .dbus(d), .Cin(Cin), .S(S), .clk(clk));
initial begin
ref[0] = 32'h00000000; Vref[0] = 0; Coutref[0] = 0; Stm[0] = 3'b100; stma[0] = 32'h00000000; stmb[0] = 32'h00000000; Cinstm[0] = 0;
ref[1] = 32'h00000000; Vref[1] = 0; Coutref[1] = 0; Stm[1] = 3'b100; stma[1] = 32'h00000000; stmb[1] = 32'h00000000; Cinstm[1] = 0;
ref[2] = 32'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0; Stm[2] = 3'b010; stma[2] = 32'hFFFFFFFF; stmb[2] = 32'h00000000; Cinstm[2] = 0;
ref[3] = 32'h00000000; Vref[3] = 0; Coutref[3] = 1; Stm[3] = 3'b010; stma[3] = 32'hFFFFFFFF; stmb[3] = 32'h00000000; Cinstm[3] = 1;
ref[4] = 32'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; Stm[4] = 3'b010; stma[4] = 32'h7FFFFFFF; stmb[4] = 32'h00000000; Cinstm[4] = 0;
ref[5] = 32'h80000000; Vref[5] = 1; Coutref[5] = 0; Stm[5] = 3'b010; stma[5] = 32'h7FFFFFFF; stmb[5] = 32'h00000000; Cinstm[5] = 1;
ref[6] = 32'h00100166; Vref[6] = 1'bx; Coutref[6] = 1'bx; Stm[6] = 3'b000; stma[6] = 32'hF01010CA; stmb[6] = 32'hF00011AC; Cinstm[6] = 0;
ref[7] = 32'h0EEF9997; Vref[7] = 1'bx; Coutref[7] = 1'bx; Stm[7] = 3'b001; stma[7] = 32'hF101CBA9; stmb[7] = 32'h0011ADC1; Cinstm[7] = 0;
ref[8] = 32'h0000FFFF; Vref[8] = 1'bx; Coutref[8] = 1'bx; Stm[8] = 3'b110; stma[8] = 32'hFFFFFFFF; stmb[8] = 32'h0000FFFF; Cinstm[8] = 0;
ref[9] = 32'hF111EFE9; Vref[9] = 1'bx; Coutref[9] = 1'bx; Stm[9] = 3'b100; stma[9] = 32'hF101CBA9; stmb[9] = 32'h0011ADC1; Cinstm[9] = 0;
ref[10] = 32'h64424220; Vref[10] = 1'bx; Coutref[10] = 1'bx; Stm[10] = 3'b010; stma[10] = 32'h31312020; stmb[10] = 32'h33112200; Cinstm[10] = 0;
ref[11] = 32'h64424221; Vref[11] = 1'bx; Coutref[11] = 1'bx; Stm[11] = 3'b011; stma[11] = 32'h31312020; stmb[11] = 32'hCCEEDDFF; Cinstm[11] = 1;
ref[12] = 32'h00000001; Vref[12] = 1'bx; Coutref[12] = 1'bx; Stm[12] = 3'b010; stma[12] = 32'h00000000; stmb[12] = 32'h00000000; Cinstm[12] = 1;
ref[13] = 32'h0000000F; Vref[13] = 1'bx; Coutref[13] = 1'bx; Stm[13] = 3'b010; stma[13] = 32'h0000000F; stmb[13] = 32'h00000000; Cinstm[13] = 0;
ref[14] = 32'h00000010; Vref[14] = 1'bx; Coutref[14] = 1'bx; Stm[14] = 3'b010; stma[14] = 32'h0000000F; stmb[14] = 32'h00000000; Cinstm[14] = 1;
ref[15] = 32'h000000FF; Vref[15] = 1'bx; Coutref[15] = 1'bx; Stm[15] = 3'b010; stma[15] = 32'h000000FF; stmb[15] = 32'h00000000; Cinstm[15] = 0;
ref[16] = 32'h00000100; Vref[16] = 1'bx; Coutref[16] = 1'bx; Stm[16] = 3'b010; stma[16] = 32'h000000FF; stmb[16] = 32'h00000000; Cinstm[16] = 1;
ref[17] = 32'h00000FFF; Vref[17] = 1'bx; Coutref[17] = 1'bx; Stm[17] = 3'b010; stma[17] = 32'h00000FFF; stmb[17] = 32'h00000000; Cinstm[17] = 0;
ref[18] = 32'h00001000; Vref[18] = 1'bx; Coutref[18] = 1'bx; Stm[18] = 3'b010; stma[18] = 32'h00000FFF; stmb[18] = 32'h00000000; Cinstm[18] = 1;
ref[19] = 32'h0000FFFF; Vref[19] = 1'bx; Coutref[19] = 1'bx; Stm[19] = 3'b010; stma[19] = 32'h0000FFFF; stmb[19] = 32'h00000000; Cinstm[19] = 0;
ref[20] = 32'h00010000; Vref[20] = 1'bx; Coutref[20] = 1'bx; Stm[20] = 3'b010; stma[20] = 32'h0000FFFF; stmb[20] = 32'h00000000; Cinstm[20] = 1;
ref[21] = 32'h000FFFFF; Vref[21] = 1'bx; Coutref[21] = 1'bx; Stm[21] = 3'b010; stma[21] = 32'h000FFFFF; stmb[21] = 32'h00000000; Cinstm[21] = 0;
ref[22] = 32'h00100000; Vref[22] = 1'bx; Coutref[22] = 1'bx; Stm[22] = 3'b010; stma[22] = 32'h000FFFFF; stmb[22] = 32'h00000000; Cinstm[22] = 1;
ref[23] = 32'h00FFFFFF; Vref[23] = 1'bx; Coutref[23] = 1'bx; Stm[23] = 3'b010; stma[23] = 32'h00FFFFFF; stmb[23] = 32'h00000000; Cinstm[23] = 0;
ref[24] = 32'h01000000; Vref[24] = 1'bx; Coutref[24] = 1'bx; Stm[24] = 3'b010; stma[24] = 32'h00FFFFFF; stmb[24] = 32'h00000000; Cinstm[24] = 1;
ref[25] = 32'h0FFFFFFF; Vref[25] = 1'bx; Coutref[25] = 1'bx; Stm[25] = 3'b010; stma[25] = 32'h0FFFFFFF; stmb[25] = 32'h00000000; Cinstm[25] = 0;
ref[26] = 32'h10000000; Vref[26] = 1'bx; Coutref[26] = 1'bx; Stm[26] = 3'b010; stma[26] = 32'h0FFFFFFF; stmb[26] = 32'h00000000; Cinstm[26] = 1;
ref[27] = 32'h00000000; Vref[27] = 1'bx; Coutref[27] = 1'bx; Stm[27] = 3'b101; stma[27] = 32'hFFFFFFFF; stmb[27] = 32'h0000FFFF; Cinstm[27] = 0;
ref[28] = 32'hx; Vref[28] = 0; Coutref[28] = 0; Stm[28] = 3'b010; stma[28] = 32'h00000000; stmb[28] = 32'h00000000; Cinstm[28] = 0;
ref[29] = 32'hx; Vref[29] = 0; Coutref[29] = 1; Stm[29] = 3'b010; stma[29] = 32'hFFFFFFFF; stmb[29] = 32'hFFFFFFFF; Cinstm[29] = 0;
ref[30] = 32'hx; Vref[30] = 1; Coutref[30] = 1; Stm[30] = 3'b010; stma[30] = 32'h80000000; stmb[30] = 32'h80000000; Cinstm[30] = 0;
ref[31] = 32'hx; Vref[31] = 1; Coutref[31] = 0; Stm[31] = 3'b010; stma[31] = 32'h40000000; stmb[31] = 32'h40000000; Cinstm[31] = 0;
ref[32] = 32'hx; Vref[32] = 1'bx; Coutref[32] =1'bx; Stm[32] = 3'hx; stma[32] = 32'hx; stmb[32] = 32'hx; Cinstm[32] =1'bx;
ref[33] = 32'hx; Vref[33] =1'bx; Coutref[33] =1'bx; Stm[33] = 3'hx; stma[33] = 32'hx; stmb[33] = 32'hx; Cinstm[33] =1'bx;
dontcare = 32'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= ntests+1; k=k+1)
begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#12.5
clk=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
a = stma[k] ; b = stmb[k];
if (k >= 1) begin
S = Stm[k-1]; Cin = Cinstm[k-1];
end
if (k >=2) begin
if ( Stm[k-2] == 3'b000 )
$display ("----- TEST FOR A XOR B -----");
if ( Stm[k-2] == 3'b001 )
$display ("----- TEST FOR A XNOR B -----");
if ( Stm[k-2] == 3'b010 )
$display ("----- TEST FOR A + B/ CARRY CHAIN -----");
if ( Stm[k-2] == 3'b011 )
$display ("----- TEST FOR A - B -----");
if ( Stm[k-2] == 3'b100 )
$display ("----- TEST FOR A OR B -----");
if ( Stm[k-2] == 3'b101 )
$display ("----- TEST FOR A NOR B -----");
if ( Stm[k-2] == 3'b110 )
$display ("----- TEST FOR A AND B -----");
$display ("Time=%t \n S=%b \n Cin=%b \n a=%b \n b=%b \n d=%b \n ref=%b \n",$realtime, Stm[k-2], Cinstm[k-2], stma[k-2], stmb[k-2], d, ref[k-2]);
if (( (ref[k-2] !== d) && (ref[k-2] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
#12.5 ;
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
if ( error != 0)
$display("---------------ERRORS. Mismatches Have Occured------------------");
end
endmodule | module alupipe_testbench(); |
reg [31:0] a, b;
wire [31:0] d;
reg [2:0] S, Stm[0:33];
reg Cin, clk;
reg [31:0] dontcare, str[0:33], ref[0:33], stma[0:33], stmb[0:33];
reg Vstr[0:33], Vref[0:33], Coutstr[0:33], Coutref[0:33], Cinstm[0:33];
integer ntests, error, k, i;
alupipe dut(.abus(a), .bbus(b), .dbus(d), .Cin(Cin), .S(S), .clk(clk));
initial begin
ref[0] = 32'h00000000; Vref[0] = 0; Coutref[0] = 0; Stm[0] = 3'b100; stma[0] = 32'h00000000; stmb[0] = 32'h00000000; Cinstm[0] = 0;
ref[1] = 32'h00000000; Vref[1] = 0; Coutref[1] = 0; Stm[1] = 3'b100; stma[1] = 32'h00000000; stmb[1] = 32'h00000000; Cinstm[1] = 0;
ref[2] = 32'hFFFFFFFF; Vref[2] = 0; Coutref[2] = 0; Stm[2] = 3'b010; stma[2] = 32'hFFFFFFFF; stmb[2] = 32'h00000000; Cinstm[2] = 0;
ref[3] = 32'h00000000; Vref[3] = 0; Coutref[3] = 1; Stm[3] = 3'b010; stma[3] = 32'hFFFFFFFF; stmb[3] = 32'h00000000; Cinstm[3] = 1;
ref[4] = 32'h7FFFFFFF; Vref[4] = 0; Coutref[4] = 0; Stm[4] = 3'b010; stma[4] = 32'h7FFFFFFF; stmb[4] = 32'h00000000; Cinstm[4] = 0;
ref[5] = 32'h80000000; Vref[5] = 1; Coutref[5] = 0; Stm[5] = 3'b010; stma[5] = 32'h7FFFFFFF; stmb[5] = 32'h00000000; Cinstm[5] = 1;
ref[6] = 32'h00100166; Vref[6] = 1'bx; Coutref[6] = 1'bx; Stm[6] = 3'b000; stma[6] = 32'hF01010CA; stmb[6] = 32'hF00011AC; Cinstm[6] = 0;
ref[7] = 32'h0EEF9997; Vref[7] = 1'bx; Coutref[7] = 1'bx; Stm[7] = 3'b001; stma[7] = 32'hF101CBA9; stmb[7] = 32'h0011ADC1; Cinstm[7] = 0;
ref[8] = 32'h0000FFFF; Vref[8] = 1'bx; Coutref[8] = 1'bx; Stm[8] = 3'b110; stma[8] = 32'hFFFFFFFF; stmb[8] = 32'h0000FFFF; Cinstm[8] = 0;
ref[9] = 32'hF111EFE9; Vref[9] = 1'bx; Coutref[9] = 1'bx; Stm[9] = 3'b100; stma[9] = 32'hF101CBA9; stmb[9] = 32'h0011ADC1; Cinstm[9] = 0;
ref[10] = 32'h64424220; Vref[10] = 1'bx; Coutref[10] = 1'bx; Stm[10] = 3'b010; stma[10] = 32'h31312020; stmb[10] = 32'h33112200; Cinstm[10] = 0;
ref[11] = 32'h64424221; Vref[11] = 1'bx; Coutref[11] = 1'bx; Stm[11] = 3'b011; stma[11] = 32'h31312020; stmb[11] = 32'hCCEEDDFF; Cinstm[11] = 1;
ref[12] = 32'h00000001; Vref[12] = 1'bx; Coutref[12] = 1'bx; Stm[12] = 3'b010; stma[12] = 32'h00000000; stmb[12] = 32'h00000000; Cinstm[12] = 1;
ref[13] = 32'h0000000F; Vref[13] = 1'bx; Coutref[13] = 1'bx; Stm[13] = 3'b010; stma[13] = 32'h0000000F; stmb[13] = 32'h00000000; Cinstm[13] = 0;
ref[14] = 32'h00000010; Vref[14] = 1'bx; Coutref[14] = 1'bx; Stm[14] = 3'b010; stma[14] = 32'h0000000F; stmb[14] = 32'h00000000; Cinstm[14] = 1;
ref[15] = 32'h000000FF; Vref[15] = 1'bx; Coutref[15] = 1'bx; Stm[15] = 3'b010; stma[15] = 32'h000000FF; stmb[15] = 32'h00000000; Cinstm[15] = 0;
ref[16] = 32'h00000100; Vref[16] = 1'bx; Coutref[16] = 1'bx; Stm[16] = 3'b010; stma[16] = 32'h000000FF; stmb[16] = 32'h00000000; Cinstm[16] = 1;
ref[17] = 32'h00000FFF; Vref[17] = 1'bx; Coutref[17] = 1'bx; Stm[17] = 3'b010; stma[17] = 32'h00000FFF; stmb[17] = 32'h00000000; Cinstm[17] = 0;
ref[18] = 32'h00001000; Vref[18] = 1'bx; Coutref[18] = 1'bx; Stm[18] = 3'b010; stma[18] = 32'h00000FFF; stmb[18] = 32'h00000000; Cinstm[18] = 1;
ref[19] = 32'h0000FFFF; Vref[19] = 1'bx; Coutref[19] = 1'bx; Stm[19] = 3'b010; stma[19] = 32'h0000FFFF; stmb[19] = 32'h00000000; Cinstm[19] = 0;
ref[20] = 32'h00010000; Vref[20] = 1'bx; Coutref[20] = 1'bx; Stm[20] = 3'b010; stma[20] = 32'h0000FFFF; stmb[20] = 32'h00000000; Cinstm[20] = 1;
ref[21] = 32'h000FFFFF; Vref[21] = 1'bx; Coutref[21] = 1'bx; Stm[21] = 3'b010; stma[21] = 32'h000FFFFF; stmb[21] = 32'h00000000; Cinstm[21] = 0;
ref[22] = 32'h00100000; Vref[22] = 1'bx; Coutref[22] = 1'bx; Stm[22] = 3'b010; stma[22] = 32'h000FFFFF; stmb[22] = 32'h00000000; Cinstm[22] = 1;
ref[23] = 32'h00FFFFFF; Vref[23] = 1'bx; Coutref[23] = 1'bx; Stm[23] = 3'b010; stma[23] = 32'h00FFFFFF; stmb[23] = 32'h00000000; Cinstm[23] = 0;
ref[24] = 32'h01000000; Vref[24] = 1'bx; Coutref[24] = 1'bx; Stm[24] = 3'b010; stma[24] = 32'h00FFFFFF; stmb[24] = 32'h00000000; Cinstm[24] = 1;
ref[25] = 32'h0FFFFFFF; Vref[25] = 1'bx; Coutref[25] = 1'bx; Stm[25] = 3'b010; stma[25] = 32'h0FFFFFFF; stmb[25] = 32'h00000000; Cinstm[25] = 0;
ref[26] = 32'h10000000; Vref[26] = 1'bx; Coutref[26] = 1'bx; Stm[26] = 3'b010; stma[26] = 32'h0FFFFFFF; stmb[26] = 32'h00000000; Cinstm[26] = 1;
ref[27] = 32'h00000000; Vref[27] = 1'bx; Coutref[27] = 1'bx; Stm[27] = 3'b101; stma[27] = 32'hFFFFFFFF; stmb[27] = 32'h0000FFFF; Cinstm[27] = 0;
ref[28] = 32'hx; Vref[28] = 0; Coutref[28] = 0; Stm[28] = 3'b010; stma[28] = 32'h00000000; stmb[28] = 32'h00000000; Cinstm[28] = 0;
ref[29] = 32'hx; Vref[29] = 0; Coutref[29] = 1; Stm[29] = 3'b010; stma[29] = 32'hFFFFFFFF; stmb[29] = 32'hFFFFFFFF; Cinstm[29] = 0;
ref[30] = 32'hx; Vref[30] = 1; Coutref[30] = 1; Stm[30] = 3'b010; stma[30] = 32'h80000000; stmb[30] = 32'h80000000; Cinstm[30] = 0;
ref[31] = 32'hx; Vref[31] = 1; Coutref[31] = 0; Stm[31] = 3'b010; stma[31] = 32'h40000000; stmb[31] = 32'h40000000; Cinstm[31] = 0;
ref[32] = 32'hx; Vref[32] = 1'bx; Coutref[32] =1'bx; Stm[32] = 3'hx; stma[32] = 32'hx; stmb[32] = 32'hx; Cinstm[32] =1'bx;
ref[33] = 32'hx; Vref[33] =1'bx; Coutref[33] =1'bx; Stm[33] = 3'hx; stma[33] = 32'hx; stmb[33] = 32'hx; Cinstm[33] =1'bx;
dontcare = 32'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= ntests+1; k=k+1)
begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#12.5
clk=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
a = stma[k] ; b = stmb[k];
if (k >= 1) begin
S = Stm[k-1]; Cin = Cinstm[k-1];
end
if (k >=2) begin
if ( Stm[k-2] == 3'b000 )
$display ("----- TEST FOR A XOR B -----");
if ( Stm[k-2] == 3'b001 )
$display ("----- TEST FOR A XNOR B -----");
if ( Stm[k-2] == 3'b010 )
$display ("----- TEST FOR A + B/ CARRY CHAIN -----");
if ( Stm[k-2] == 3'b011 )
$display ("----- TEST FOR A - B -----");
if ( Stm[k-2] == 3'b100 )
$display ("----- TEST FOR A OR B -----");
if ( Stm[k-2] == 3'b101 )
$display ("----- TEST FOR A NOR B -----");
if ( Stm[k-2] == 3'b110 )
$display ("----- TEST FOR A AND B -----");
$display ("Time=%t \n S=%b \n Cin=%b \n a=%b \n b=%b \n d=%b \n ref=%b \n",$realtime, Stm[k-2], Cinstm[k-2], stma[k-2], stmb[k-2], d, ref[k-2]);
if (( (ref[k-2] !== d) && (ref[k-2] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
#12.5 ;
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
if ( error != 0)
$display("---------------ERRORS. Mismatches Have Occured------------------");
end
endmodule | 0 |
141,071 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;
wire [31:0] bInput;
wire [31:0] dInput;
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule | module alupipe(S, abus, bbus, clk, Cin, dbus); |
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;
wire [31:0] bInput;
wire [31:0] dInput;
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule | 0 |
141,072 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule | module DflipFlop(dataIn, clk, dataOut); |
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule | 0 |
141,073 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | module alu32 (d, Cout, V, a, b, Cin, S); |
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | 0 |
141,074 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,075 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,076 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,077 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,078 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,079 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,080 | data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v | 93,595,154 | alupipe.v | v | 290 | 109 | [] | [] | [] | [(10, 26), (28, 36), (41, 81), (84, 116), (119, 125), (128, 141), (144, 178), (181, 215), (218, 252), (255, 289)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_2/assignment_2.srcs/sources_1/new/alupipe.v:21: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Error: Exiting due to 2 warning(s)\n' | 310,871 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,081 | data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v | 93,595,154 | regfil_testbench.v | v | 185 | 166 | [] | [] | [] | null | line:149: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v:125: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12); \n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v:135: Unsupported: Ignoring delay on this delayed statement.\n #25 ;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v:147: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v:155: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_3/regfil_testbench.v:168: Unsupported: Ignoring delay on this delayed statement.\n #5 ;\n ^\n%Error: Exiting due to 1 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,872 | module | module regfil_testbench();
reg [31:0] Aselect, Bselect, Dselect;
reg [31:0] dbus;
wire [31:0] abus,bbus;
reg clk;
reg [31:0] dontcare, ref_abus[0:31], ref_bbus[0:31], stm_dbus[0:31], stm_asel[0:31], stm_bsel[0:31], stm_dsel[0:31];
integer error, i, k, ntests;
regfile dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .abus(abus), .bbus(bbus), .dbus(dbus), .clk(clk));
initial begin
stm_dsel[0] = 32'h02000000; stm_dbus[0] = 32'h76543210;
ref_abus[0] = 32'h76543210; ref_bbus[0] = 32'h00000000; stm_asel[0] = 32'h02000000; stm_bsel[0] = 32'h00000001;
stm_dsel[1] = 32'h00001000; stm_dbus[1] = 32'hF4820000;
ref_abus[1] = 32'hF4820000; ref_bbus[1] = 32'h76543210; stm_asel[1] = 32'h00001000; stm_bsel[1] = 32'h02000000;
stm_dsel[2] = 32'h00000001; stm_dbus[2] = 32'h00001111;
ref_abus[2] = 32'h00000000; ref_bbus[2] = 32'h76543210; stm_asel[2] = 32'h00000001; stm_bsel[2] = 32'h02000000;
stm_dsel[3] = 32'h00000040; stm_dbus[3] = 32'h80876263;
ref_abus[3] = 32'hF4820000; ref_bbus[3] = 32'h80876263; stm_asel[3] = 32'h00001000; stm_bsel[3] = 32'h00000040;
stm_dsel[4] = 32'h00040000; stm_dbus[4] = 32'h10101010;
ref_abus[4] = 32'h10101010; ref_bbus[4] = 32'h10101010; stm_asel[4] = 32'h00040000; stm_bsel[4] = 32'h00040000;
stm_dsel[5] = 32'h80000000; stm_dbus[5] = 32'h33333333;
ref_abus[5] = 32'hF4820000; ref_bbus[5] = 32'h76543210; stm_asel[5] = 32'h00001000; stm_bsel[5] = 32'h02000000;
stm_dsel[6] = 32'h00000800; stm_dbus[6] = 32'h000062DE;
ref_abus[6] = 32'h000062DE; ref_bbus[6] = 32'h33333333; stm_asel[6] = 32'h00000800; stm_bsel[6] = 32'h80000000;
stm_dsel[7] = 32'h00800000; stm_dbus[7] = 32'h83848586;
ref_abus[7] = 32'h80876263; ref_bbus[7] = 32'h00000000; stm_asel[7] = 32'h00000040; stm_bsel[7] = 32'h00000001;
stm_dsel[8] = 32'h00000010; stm_dbus[8] = 32'h80000000;
ref_abus[8] = 32'h00000000; ref_bbus[8] = 32'h83848586; stm_asel[8] = 32'h00000001; stm_bsel[8] = 32'h00800000;
stm_dsel[9] = 32'h04000000; stm_dbus[9] = 32'hFFFFCCCC;
ref_abus[9] = 32'hFFFFCCCC; ref_bbus[9] = 32'h80000000; stm_asel[9] = 32'h04000000; stm_bsel[9] = 32'h00000010;
stm_dsel[10] = 32'h00004000; stm_dbus[10] = 32'hF393F393;
ref_abus[10] = 32'h76543210; ref_bbus[10] = 32'h10101010; stm_asel[10] = 32'h02000000; stm_bsel[10] = 32'h00040000;
stm_dsel[11] = 32'h00000020; stm_dbus[11] = 32'h0FEFEFEF;
ref_abus[11] = 32'h0FEFEFEF; ref_bbus[11] = 32'hF393F393; stm_asel[11] = 32'h00000020; stm_bsel[11] = 32'h00004000;
stm_dsel[12] = 32'h20000000; stm_dbus[12] = 32'h09876543;
ref_abus[12] = 32'h33333333; ref_bbus[12] = 32'hFFFFCCCC; stm_asel[12] = 32'h80000000; stm_bsel[12] = 32'h04000000;
stm_dsel[13] = 32'h01000000; stm_dbus[13] = 32'h01234567;
ref_abus[13] = 32'h000062DE; ref_bbus[13] = 32'h0FEFEFEF; stm_asel[13] = 32'h00000800; stm_bsel[13] = 32'h00000020;
stm_dsel[14] = 32'h00200000; stm_dbus[14] = 32'h00000008;
ref_abus[14] = 32'h09876543; ref_bbus[14] = 32'h01234567; stm_asel[14] = 32'h20000000; stm_bsel[14] = 32'h01000000;
stm_dsel[15] = 32'h00000100; stm_dbus[15] = 32'hFFFF0000;
ref_abus[15] = 32'h80876263; ref_bbus[15] = 32'h00000008; stm_asel[15] = 32'h00000040; stm_bsel[15] = 32'h00200000;
stm_dsel[16] = 32'h00000008; stm_dbus[16] = 32'hFFFFFFFF;
ref_abus[16] = 32'hFFFFFFFF; ref_bbus[16] = 32'hFFFF0000; stm_asel[16] = 32'h00000008; stm_bsel[16] = 32'h00000100;
stm_dsel[17] = 32'h00010000; stm_dbus[17] = 32'h0000FEAB;
ref_abus[17] = 32'h83848586; ref_bbus[17] = 32'hFFFFFFFF; stm_asel[17] = 32'h00800000; stm_bsel[17] = 32'h00000008;
stm_dsel[18] = 32'h10000000; stm_dbus[18] = 32'h50600000;
ref_abus[18] = 32'h0000FEAB; ref_bbus[18] = 32'h50600000; stm_asel[18] = 32'h00010000; stm_bsel[18] = 32'h10000000;
stm_dsel[19] = 32'h00020000; stm_dbus[19] = 32'h88887777;
ref_abus[19] = 32'h88887777; ref_bbus[19] = 32'h00000000; stm_asel[19] = 32'h00020000; stm_bsel[19] = 32'h00000001;
stm_dsel[20] = 32'h00080000; stm_dbus[20] = 32'hF0E0D0C0;
ref_abus[20] = 32'h00000000; ref_bbus[20] = 32'h00000000; stm_asel[20] = 32'h00000001; stm_bsel[20] = 32'h00000001;
stm_dsel[21] = 32'h00008000; stm_dbus[21] = 32'hAAAAAAAA;
ref_abus[21] = 32'h88887777; ref_bbus[21] = 32'hF0E0D0C0; stm_asel[21] = 32'h00020000; stm_bsel[21] = 32'h00080000;
stm_dsel[22] = 32'h40000000; stm_dbus[22] = 32'hFDFEFFFF;
ref_abus[22] = 32'hFDFEFFFF; ref_bbus[22] = 32'hAAAAAAAA; stm_asel[22] = 32'h40000000; stm_bsel[22] = 32'h00008000;
stm_dsel[23] = 32'h00100000; stm_dbus[23] = 32'hCCCCFFFF;
ref_abus[23] = 32'h00000000; ref_bbus[23] = 32'h00000000; stm_asel[23] = 32'h00000001; stm_bsel[23] = 32'h00000001;
stm_dsel[24] = 32'h00000002; stm_dbus[24] = 32'hF0F0F0F0;
ref_abus[24] = 32'hF0F0F0F0; ref_bbus[24] = 32'hCCCCFFFF; stm_asel[24] = 32'h00000002; stm_bsel[24] = 32'h00100000;
stm_dsel[25] = 32'h00000400; stm_dbus[25] = 32'hAAAAFFFF;
ref_abus[25] = 32'hCCCCFFFF; ref_bbus[25] = 32'hF0F0F0F0; stm_asel[25] = 32'h00100000; stm_bsel[25] = 32'h00000002;
stm_dsel[26] = 32'h08000000; stm_dbus[26] = 32'hDDDDECFA;
ref_abus[26] = 32'hDDDDECFA; ref_bbus[26] = 32'hAAAAFFFF; stm_asel[26] = 32'h08000000; stm_bsel[26] = 32'h00000400;
stm_dsel[27] = 32'h00000004; stm_dbus[27] = 32'h66666666;
ref_abus[27] = 32'hFDFEFFFF; ref_bbus[27] = 32'hF0F0F0F0; stm_asel[27] = 32'h40000000; stm_bsel[27] = 32'h00000002;
stm_dsel[28] = 32'h00000080; stm_dbus[28] = 32'h0999FFFF;
ref_abus[28] = 32'h66666666; ref_bbus[28] = 32'hDDDDECFA; stm_asel[28] = 32'h00000004; stm_bsel[28] = 32'h08000000;
stm_dsel[29] = 32'h00000200; stm_dbus[29] = 32'hEEEABDCE;
ref_abus[29] = 32'hF393F393; ref_bbus[29] = 32'hFFFFFFFF; stm_asel[29] = 32'h00004000; stm_bsel[29] = 32'h00000008;
stm_dsel[30] = 32'h00002000; stm_dbus[30] = 32'h80808080;
ref_abus[30] = 32'h0999FFFF; ref_bbus[30] = 32'hEEEABDCE; stm_asel[30] = 32'h00000080; stm_bsel[30] = 32'h00000200;
stm_dsel[31] = 32'h00400000; stm_dbus[31] = 32'hABCDEF90;
ref_abus[31] = 32'hABCDEF90; ref_bbus[31] = 32'h80808080; stm_asel[31] = 32'h00400000; stm_bsel[31] = 32'h00002000;
dontcare = 32'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk = 0;
#25 ;
for (k=0; k<= 31; k=k+1)
begin
$display("ASSIGNING VALUE TO THE DBUS AND SELECTING DSEL REGISTER TO WRITE VALUE OF DBUS");
clk = 1;
Dselect = stm_dsel[k];
dbus = stm_dbus[k];
$display ("Time=%t \n clk =%b \n Dselect=%b \n dbus=%b \n",$realtime, clk, Dselect, dbus);
#25
$display("TEST READ OPERATION");
clk = 0;
Aselect = stm_asel[k]; Bselect = stm_bsel[k];
$display ("Time=%t \n clk =%b \n Aselect=%b \n Bselect=%b \n",$realtime, clk, Aselect, Bselect);
#20
$display ("Time=%t \n clk =%b \n your abus=%b \n correct abus=%b \n your bbus=%b \n correct bbus=%b \n ",$realtime, clk, abus, ref_abus[k], bbus, ref_bbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k+1] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
$display("END TEST READ OPERATION");
#5 ;
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module regfil_testbench(); |
reg [31:0] Aselect, Bselect, Dselect;
reg [31:0] dbus;
wire [31:0] abus,bbus;
reg clk;
reg [31:0] dontcare, ref_abus[0:31], ref_bbus[0:31], stm_dbus[0:31], stm_asel[0:31], stm_bsel[0:31], stm_dsel[0:31];
integer error, i, k, ntests;
regfile dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .abus(abus), .bbus(bbus), .dbus(dbus), .clk(clk));
initial begin
stm_dsel[0] = 32'h02000000; stm_dbus[0] = 32'h76543210;
ref_abus[0] = 32'h76543210; ref_bbus[0] = 32'h00000000; stm_asel[0] = 32'h02000000; stm_bsel[0] = 32'h00000001;
stm_dsel[1] = 32'h00001000; stm_dbus[1] = 32'hF4820000;
ref_abus[1] = 32'hF4820000; ref_bbus[1] = 32'h76543210; stm_asel[1] = 32'h00001000; stm_bsel[1] = 32'h02000000;
stm_dsel[2] = 32'h00000001; stm_dbus[2] = 32'h00001111;
ref_abus[2] = 32'h00000000; ref_bbus[2] = 32'h76543210; stm_asel[2] = 32'h00000001; stm_bsel[2] = 32'h02000000;
stm_dsel[3] = 32'h00000040; stm_dbus[3] = 32'h80876263;
ref_abus[3] = 32'hF4820000; ref_bbus[3] = 32'h80876263; stm_asel[3] = 32'h00001000; stm_bsel[3] = 32'h00000040;
stm_dsel[4] = 32'h00040000; stm_dbus[4] = 32'h10101010;
ref_abus[4] = 32'h10101010; ref_bbus[4] = 32'h10101010; stm_asel[4] = 32'h00040000; stm_bsel[4] = 32'h00040000;
stm_dsel[5] = 32'h80000000; stm_dbus[5] = 32'h33333333;
ref_abus[5] = 32'hF4820000; ref_bbus[5] = 32'h76543210; stm_asel[5] = 32'h00001000; stm_bsel[5] = 32'h02000000;
stm_dsel[6] = 32'h00000800; stm_dbus[6] = 32'h000062DE;
ref_abus[6] = 32'h000062DE; ref_bbus[6] = 32'h33333333; stm_asel[6] = 32'h00000800; stm_bsel[6] = 32'h80000000;
stm_dsel[7] = 32'h00800000; stm_dbus[7] = 32'h83848586;
ref_abus[7] = 32'h80876263; ref_bbus[7] = 32'h00000000; stm_asel[7] = 32'h00000040; stm_bsel[7] = 32'h00000001;
stm_dsel[8] = 32'h00000010; stm_dbus[8] = 32'h80000000;
ref_abus[8] = 32'h00000000; ref_bbus[8] = 32'h83848586; stm_asel[8] = 32'h00000001; stm_bsel[8] = 32'h00800000;
stm_dsel[9] = 32'h04000000; stm_dbus[9] = 32'hFFFFCCCC;
ref_abus[9] = 32'hFFFFCCCC; ref_bbus[9] = 32'h80000000; stm_asel[9] = 32'h04000000; stm_bsel[9] = 32'h00000010;
stm_dsel[10] = 32'h00004000; stm_dbus[10] = 32'hF393F393;
ref_abus[10] = 32'h76543210; ref_bbus[10] = 32'h10101010; stm_asel[10] = 32'h02000000; stm_bsel[10] = 32'h00040000;
stm_dsel[11] = 32'h00000020; stm_dbus[11] = 32'h0FEFEFEF;
ref_abus[11] = 32'h0FEFEFEF; ref_bbus[11] = 32'hF393F393; stm_asel[11] = 32'h00000020; stm_bsel[11] = 32'h00004000;
stm_dsel[12] = 32'h20000000; stm_dbus[12] = 32'h09876543;
ref_abus[12] = 32'h33333333; ref_bbus[12] = 32'hFFFFCCCC; stm_asel[12] = 32'h80000000; stm_bsel[12] = 32'h04000000;
stm_dsel[13] = 32'h01000000; stm_dbus[13] = 32'h01234567;
ref_abus[13] = 32'h000062DE; ref_bbus[13] = 32'h0FEFEFEF; stm_asel[13] = 32'h00000800; stm_bsel[13] = 32'h00000020;
stm_dsel[14] = 32'h00200000; stm_dbus[14] = 32'h00000008;
ref_abus[14] = 32'h09876543; ref_bbus[14] = 32'h01234567; stm_asel[14] = 32'h20000000; stm_bsel[14] = 32'h01000000;
stm_dsel[15] = 32'h00000100; stm_dbus[15] = 32'hFFFF0000;
ref_abus[15] = 32'h80876263; ref_bbus[15] = 32'h00000008; stm_asel[15] = 32'h00000040; stm_bsel[15] = 32'h00200000;
stm_dsel[16] = 32'h00000008; stm_dbus[16] = 32'hFFFFFFFF;
ref_abus[16] = 32'hFFFFFFFF; ref_bbus[16] = 32'hFFFF0000; stm_asel[16] = 32'h00000008; stm_bsel[16] = 32'h00000100;
stm_dsel[17] = 32'h00010000; stm_dbus[17] = 32'h0000FEAB;
ref_abus[17] = 32'h83848586; ref_bbus[17] = 32'hFFFFFFFF; stm_asel[17] = 32'h00800000; stm_bsel[17] = 32'h00000008;
stm_dsel[18] = 32'h10000000; stm_dbus[18] = 32'h50600000;
ref_abus[18] = 32'h0000FEAB; ref_bbus[18] = 32'h50600000; stm_asel[18] = 32'h00010000; stm_bsel[18] = 32'h10000000;
stm_dsel[19] = 32'h00020000; stm_dbus[19] = 32'h88887777;
ref_abus[19] = 32'h88887777; ref_bbus[19] = 32'h00000000; stm_asel[19] = 32'h00020000; stm_bsel[19] = 32'h00000001;
stm_dsel[20] = 32'h00080000; stm_dbus[20] = 32'hF0E0D0C0;
ref_abus[20] = 32'h00000000; ref_bbus[20] = 32'h00000000; stm_asel[20] = 32'h00000001; stm_bsel[20] = 32'h00000001;
stm_dsel[21] = 32'h00008000; stm_dbus[21] = 32'hAAAAAAAA;
ref_abus[21] = 32'h88887777; ref_bbus[21] = 32'hF0E0D0C0; stm_asel[21] = 32'h00020000; stm_bsel[21] = 32'h00080000;
stm_dsel[22] = 32'h40000000; stm_dbus[22] = 32'hFDFEFFFF;
ref_abus[22] = 32'hFDFEFFFF; ref_bbus[22] = 32'hAAAAAAAA; stm_asel[22] = 32'h40000000; stm_bsel[22] = 32'h00008000;
stm_dsel[23] = 32'h00100000; stm_dbus[23] = 32'hCCCCFFFF;
ref_abus[23] = 32'h00000000; ref_bbus[23] = 32'h00000000; stm_asel[23] = 32'h00000001; stm_bsel[23] = 32'h00000001;
stm_dsel[24] = 32'h00000002; stm_dbus[24] = 32'hF0F0F0F0;
ref_abus[24] = 32'hF0F0F0F0; ref_bbus[24] = 32'hCCCCFFFF; stm_asel[24] = 32'h00000002; stm_bsel[24] = 32'h00100000;
stm_dsel[25] = 32'h00000400; stm_dbus[25] = 32'hAAAAFFFF;
ref_abus[25] = 32'hCCCCFFFF; ref_bbus[25] = 32'hF0F0F0F0; stm_asel[25] = 32'h00100000; stm_bsel[25] = 32'h00000002;
stm_dsel[26] = 32'h08000000; stm_dbus[26] = 32'hDDDDECFA;
ref_abus[26] = 32'hDDDDECFA; ref_bbus[26] = 32'hAAAAFFFF; stm_asel[26] = 32'h08000000; stm_bsel[26] = 32'h00000400;
stm_dsel[27] = 32'h00000004; stm_dbus[27] = 32'h66666666;
ref_abus[27] = 32'hFDFEFFFF; ref_bbus[27] = 32'hF0F0F0F0; stm_asel[27] = 32'h40000000; stm_bsel[27] = 32'h00000002;
stm_dsel[28] = 32'h00000080; stm_dbus[28] = 32'h0999FFFF;
ref_abus[28] = 32'h66666666; ref_bbus[28] = 32'hDDDDECFA; stm_asel[28] = 32'h00000004; stm_bsel[28] = 32'h08000000;
stm_dsel[29] = 32'h00000200; stm_dbus[29] = 32'hEEEABDCE;
ref_abus[29] = 32'hF393F393; ref_bbus[29] = 32'hFFFFFFFF; stm_asel[29] = 32'h00004000; stm_bsel[29] = 32'h00000008;
stm_dsel[30] = 32'h00002000; stm_dbus[30] = 32'h80808080;
ref_abus[30] = 32'h0999FFFF; ref_bbus[30] = 32'hEEEABDCE; stm_asel[30] = 32'h00000080; stm_bsel[30] = 32'h00000200;
stm_dsel[31] = 32'h00400000; stm_dbus[31] = 32'hABCDEF90;
ref_abus[31] = 32'hABCDEF90; ref_bbus[31] = 32'h80808080; stm_asel[31] = 32'h00400000; stm_bsel[31] = 32'h00002000;
dontcare = 32'hx;
ntests = 32;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk = 0;
#25 ;
for (k=0; k<= 31; k=k+1)
begin
$display("ASSIGNING VALUE TO THE DBUS AND SELECTING DSEL REGISTER TO WRITE VALUE OF DBUS");
clk = 1;
Dselect = stm_dsel[k];
dbus = stm_dbus[k];
$display ("Time=%t \n clk =%b \n Dselect=%b \n dbus=%b \n",$realtime, clk, Dselect, dbus);
#25
$display("TEST READ OPERATION");
clk = 0;
Aselect = stm_asel[k]; Bselect = stm_bsel[k];
$display ("Time=%t \n clk =%b \n Aselect=%b \n Bselect=%b \n",$realtime, clk, Aselect, Bselect);
#20
$display ("Time=%t \n clk =%b \n your abus=%b \n correct abus=%b \n your bbus=%b \n correct bbus=%b \n ",$realtime, clk, abus, ref_abus[k], bbus, ref_bbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k+1] !== dontcare) ) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
$display("END TEST READ OPERATION");
#5 ;
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,082 | data/full_repos/permissive/93595154/assignment_3/assignment_3.srcs/sources_1/new/regfile.v | 93,595,154 | regfile.v | v | 54 | 83 | [] | [] | [] | [(3, 35), (37, 53)] | null | data/verilator_xmls/c7359728-0f9e-44b0-9dfb-032e30888750.xml | null | 310,874 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
); |
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,083 | data/full_repos/permissive/93595154/assignment_3/assignment_3.srcs/sources_1/new/regfile.v | 93,595,154 | regfile.v | v | 54 | 83 | [] | [] | [] | [(3, 35), (37, 53)] | null | data/verilator_xmls/c7359728-0f9e-44b0-9dfb-032e30888750.xml | null | 310,874 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
reg [31:0] data;
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
reg [31:0] data;
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | 0 |
141,084 | data/full_repos/permissive/93595154/assignment_4/regalu_testbench.v | 93,595,154 | regalu_testbench.v | v | 411 | 299 | [] | [] | [] | [(2, 409)] | null | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_4/regalu_testbench.v:356: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12); \n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_4/regalu_testbench.v:368: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,876 | module | module regalu_testbench();
reg [31:0] Aselect, Bselect, Dselect;
reg [2:0] S, stm_S[0:29];
reg Cin, clk, stm_CL[0:29], stm_Cin[0:29];
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg [31:0] dontcare, ref_abus[0:29], ref_bbus[0:29], ref_dbus[0:29], asel[0:29], bsel[0:29], dsel[0:29];
integer error, i, k, ntests;
regalu dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus), .S(S), .Cin(Cin));
initial begin
stm_CL[0]=0;
stm_Cin[0]=0;
stm_S[0] =3'b001;
asel[0]= 32'h00000001;
bsel[0]=32'h00000001;
dsel[0]=32'h00000001;
ref_abus[0]=32'h00000000;
ref_bbus[0]=32'h00000000;
ref_dbus[0]=32'hxxxxxxxx;
stm_CL[1]=1;
stm_Cin[1]=0;
stm_S[1]=3'b001;
asel[1]= 32'h00000001;
bsel[1]=32'h00000001;
dsel[1]=32'h00000001;
ref_abus[1]=32'hxxxxxxxx;
ref_bbus[1]=32'hxxxxxxxx;
ref_dbus[1]=32'hxxxxxxxx;
stm_CL[2]=0;
stm_Cin[2]=0;
stm_S[2]=3'b001;
asel[2]= 32'h00000001;
bsel[2]=32'h00000001;
dsel[2]=32'h00000001;
ref_abus[2]=32'h00000000;
ref_bbus[2]=32'h00000000;
ref_dbus[2]=32'hxxxxxxxx;
stm_CL[3]=1;
stm_Cin[3]=0;
stm_S[3]=3'b110;
asel[3]= 32'h00000001;
bsel[3]= 32'h00000001;
dsel[3]=32'h00000002;
ref_abus[3]=32'hxxxxxxxx;
ref_bbus[3]=32'hxxxxxxxx;
ref_dbus[3]=32'hFFFFFFFF;
stm_CL[4]=0;
stm_Cin[4]=0;
stm_S[4]=3'b001;
asel[4]=32'h00000001;
bsel[4]=32'h00000002;
dsel[4]=32'h00000001;
ref_abus[4]=32'h00000000;
ref_bbus[4]=32'hFFFFFFFF;
ref_dbus[4]=32'hxxxxxxxx;
stm_CL[5]=1;
stm_Cin[5]=0;
stm_S[5]=3'b100;
asel[5]=32'h00000001;
bsel[5]=32'h00000001;
dsel[5]=32'h00000004;
ref_abus[5]=32'hxxxxxxxx;
ref_bbus[5]=32'hxxxxxxxx;
ref_dbus[5]=32'hFFFFFFFF;
stm_CL[6]=0;
stm_Cin[6]=0;
stm_S[6]=3'b100;
asel[6]=32'h00000004;
bsel[6]=32'h00000002;
dsel[6]=32'h00000001;
ref_abus[6]=32'hFFFFFFFF;
ref_bbus[6]=32'hFFFFFFFF;
ref_dbus[6]=32'hxxxxxxxx;
stm_CL[7]=1;
stm_Cin[7]=0;
stm_S[7]=3'b000;
asel[7]=32'h00000001;
bsel[7]=32'h00000001;
dsel[7]=32'h00000008;
ref_abus[7]=32'hxxxxxxxx;
ref_bbus[7]=32'hxxxxxxxx;
ref_dbus[7]=32'hFFFFFFFF;
stm_CL[8]=0;
stm_Cin[8]=0;
stm_S[8]=3'b000;
asel[8]=32'h00000008;
bsel[8]=32'h00000004;
dsel[8]=32'h00000000;
ref_abus[8]=32'hFFFFFFFF;
ref_bbus[8]=32'hFFFFFFFF;
ref_dbus[8]=32'hxxxxxxxx;
stm_CL[9]=1;
stm_Cin[9]=0;
stm_S[9]=3'b001;
asel[9]=32'h00000001;
bsel[9]=32'h00000001;
dsel[9]=32'h00000010;
ref_abus[9]=32'hxxxxxxxx;
ref_bbus[9]=32'hxxxxxxxx;
ref_dbus[9]=32'h00000000;
stm_CL[10]=0;
stm_Cin[10]=0;
stm_S[10]=3'b001;
asel[10]=32'h00000008;
bsel[10]=32'h00000010;
dsel[10]=32'h00000000;
ref_abus[10]=32'hFFFFFFFF;
ref_bbus[10]=32'h00000000;
ref_dbus[10]=32'hxxxxxxxx;
stm_CL[11]=1;
stm_Cin[11]=0;
stm_S[11]=3'b101;
asel[11]=32'h00000001;
bsel[11]=32'h00000001;
dsel[11]=32'h00000020;
ref_abus[11]=32'hxxxxxxxx;
ref_bbus[11]=32'hxxxxxxxx;
ref_dbus[11]=32'hFFFFFFFF;
stm_CL[12]=0;
stm_Cin[12]=0;
stm_S[12]=3'b101;
asel[12]=32'h00000010;
bsel[12]=32'h00000020;
dsel[12]=32'h00000000;
ref_abus[12]=32'h00000000;
ref_bbus[12]=32'hFFFFFFFF;
ref_dbus[12]=32'hxxxxxxxx;
stm_CL[13]=1;
stm_Cin[13]=0;
stm_S[13]=3'b010;
asel[13]=32'h00000001;
bsel[13]=32'h00000001;
dsel[13]=32'h00000040;
ref_abus[13]=32'hxxxxxxxx;
ref_bbus[13]=32'hxxxxxxxx;
ref_dbus[13]=32'h00000000;
stm_CL[14]=0;
stm_Cin[14]=0;
stm_S[14]=3'b010;
asel[14]=32'h00000020;
bsel[14]=32'h00000040;
dsel[14]=32'h00000000;
ref_abus[14]=32'hFFFFFFFF;
ref_bbus[14]=32'h00000000;
ref_dbus[14]=32'hxxxxxxxx;
stm_CL[15]=1;
stm_Cin[15]=0;
stm_S[15]=3'b000;
asel[15]=32'h00000001;
bsel[15]=32'h00000001;
dsel[15]=32'h00000080;
ref_abus[15]=32'hxxxxxxxx;
ref_bbus[15]=32'hxxxxxxxx;
ref_dbus[15]=32'hFFFFFFFF;
stm_CL[16]=0;
stm_Cin[16]=0;
stm_S[16]=3'b000;
asel[16]=32'h00000040;
bsel[16]=32'h00000080;
dsel[16]=32'h00000000;
ref_abus[16]=32'h00000000;
ref_bbus[16]=32'hFFFFFFFF;
ref_dbus[16]=32'hxxxxxxxx;
stm_CL[17]=1;
stm_Cin[17]=0;
stm_S[17]=3'b001;
asel[17]=32'h00000001;
bsel[17]=32'h00000001;
dsel[17]=32'h00000100;
ref_abus[17]=32'hxxxxxxxx;
ref_bbus[17]=32'hxxxxxxxx;
ref_dbus[17]=32'hFFFFFFFF;
stm_CL[18]=0;
stm_Cin[18]=0;
stm_S[18]=3'b001;
asel[18]=32'h00000080;
bsel[18]=32'h00000100;
dsel[18]=32'h00000100;
ref_abus[18]=32'hFFFFFFFF;
ref_bbus[18]=32'hFFFFFFFF;
ref_dbus[18]=32'hxxxxxxxx;
stm_CL[19]=1;
stm_Cin[19]=0;
stm_S[19]=3'b100;
asel[19]=32'h00000001;
bsel[19]=32'h00000001;
dsel[19]=32'h00000200;
ref_abus[19]=32'hxxxxxxxx;
ref_bbus[19]=32'hxxxxxxxx;
ref_dbus[19]=32'h00000000;
stm_CL[20]=0;
stm_Cin[20]=0;
stm_S[20]=3'b100;
asel[20]=32'h00000100;
bsel[20]=32'h00000200;
dsel[20]=32'h00000000;
ref_abus[20]=32'hFFFFFFFF;
ref_bbus[20]=32'h00000000;
ref_dbus[20]=32'hxxxxxxxx;
stm_CL[21]=1;
stm_Cin[21]=0;
stm_S[21]=3'b101;
asel[21]=32'h00000001;
bsel[21]=32'h00000001;
dsel[21]=32'h00000400;
ref_abus[21]=32'hxxxxxxxx;
ref_bbus[21]=32'hxxxxxxxx;
ref_dbus[21]=32'hFFFFFFFF;
stm_CL[22]=0;
stm_Cin[22]=0;
stm_S[22]=3'b101;
asel[22]=32'h00000200;
bsel[22]=32'h00000400;
dsel[22]=32'h00000000;
ref_abus[22]=32'h00000000;
ref_bbus[22]=32'hFFFFFFFF;
ref_dbus[22]=32'hxxxxxxxx;
stm_CL[23]=1;
stm_Cin[23]=0;
stm_S[23]=3'b110;
asel[23]=32'h0000001;
bsel[23]=32'h0000001;
dsel[23]=32'h0000800;
ref_abus[23]=32'hxxxxxxxx;
ref_bbus[23]=32'hxxxxxxxx;
ref_dbus[23]=32'h00000000;
stm_CL[24]=0;
stm_Cin[24]=0;
stm_S[24]=3'b110;
asel[24]=32'h00000400;
bsel[24]=32'h00000800;
dsel[24]=32'h00000000;
ref_abus[24]=32'hFFFFFFFF;
ref_bbus[24]=32'h00000000;
ref_dbus[24]=32'hxxxxxxxx;
stm_CL[25]=1;
stm_Cin[25]=0;
stm_S[25]=3'b000;
asel[25]=32'h00000001;
bsel[25]=32'h00000001;
dsel[25]=32'h00001000;
ref_abus[25]=32'hxxxxxxxx;
ref_bbus[25]=32'hxxxxxxxx;
ref_dbus[25]=32'h00000000;
stm_CL[26]=0;
stm_Cin[26]=0;
stm_S[26]=3'b000;
asel[26]=32'h00000800;
bsel[26]=32'h00001000;
dsel[26]=32'h00000000;
ref_abus[26]=32'h00000000;
ref_bbus[26]=32'h00000000;
ref_dbus[26]=32'hxxxxxxxx;
stm_CL[27]=1;
stm_Cin[27]=0;
stm_S[27]=3'b001;
asel[27]=32'h00000001;
bsel[27]=32'h00000001;
dsel[27]=32'h00002000;
ref_abus[27]=32'hxxxxxxxx;
ref_bbus[27]=32'hxxxxxxxx;
ref_dbus[27]=32'hFFFFFFFF;
stm_CL[28]=0;
stm_Cin[28]=0;
stm_S[28]=3'b001;
asel[28]=32'h00001000;
bsel[28]=32'h00002000;
dsel[28]=32'h00000000;
ref_abus[28]=32'h00000000;
ref_bbus[28]=32'hFFFFFFFF;
ref_dbus[28]=32'hxxxxxxxx;
stm_CL[29]=1;
stm_Cin[29]=1;
stm_S[29]=3'b110;
asel[29]=32'h00000001;
bsel[29]=32'h00000001;
dsel[29]=32'h00004000;
ref_abus[29]=32'hxxxxxxxx;
ref_bbus[29]=32'hxxxxxxxx;
ref_dbus[29]=32'hFFFFFFFF;
dontcare = 32'hxxxxxxxx;
ntests = 30;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= 29; k=k+1)
begin
Aselect=asel[k]; Bselect=bsel[k]; Dselect=dsel[k]; clk=stm_CL[k]; S=stm_S[k]; Cin=stm_Cin[k];
#25
if ( k >= 3) begin
if ( stm_S[k-2] == 3'b000 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XOR B -----");
if ( stm_S[k-2] == 3'b001 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XNOR B -----");
if ( stm_S[k-2] == 3'b010 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A + B // CARRY CHAIN -----");
if ( stm_S[k-2] == 3'b100 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A OR B -----");
if ( stm_S[k-2] == 3'b011 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A - B -----");
if ( stm_S[k-2] == 3'b101 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A NOR B -----");
if ( stm_S[k-2] == 3'b110 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A AND B -----");
end
$display ("Test=%d \n Time=%t \n Clk=%b \n S=%b \n Cin=%b \n Aselect=%b \n Bselect=%b \n Dselect=%b \n abus=%b \n ref_abus=%b \n bbus=%b \n ref_bbus=%b \n dbus=%b \n ref_dbus=%b \n ", k, $realtime, clk, S, Cin, Aselect, Bselect, Dselect, abus, ref_abus[k], bbus, ref_bbus[k], dbus, ref_dbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k] !== dontcare)) || ( (ref_dbus[k] !== dbus) && (ref_dbus[k] !== dontcare)) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module regalu_testbench(); |
reg [31:0] Aselect, Bselect, Dselect;
reg [2:0] S, stm_S[0:29];
reg Cin, clk, stm_CL[0:29], stm_Cin[0:29];
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg [31:0] dontcare, ref_abus[0:29], ref_bbus[0:29], ref_dbus[0:29], asel[0:29], bsel[0:29], dsel[0:29];
integer error, i, k, ntests;
regalu dut(.Aselect(Aselect), .Bselect(Bselect), .Dselect(Dselect), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus), .S(S), .Cin(Cin));
initial begin
stm_CL[0]=0;
stm_Cin[0]=0;
stm_S[0] =3'b001;
asel[0]= 32'h00000001;
bsel[0]=32'h00000001;
dsel[0]=32'h00000001;
ref_abus[0]=32'h00000000;
ref_bbus[0]=32'h00000000;
ref_dbus[0]=32'hxxxxxxxx;
stm_CL[1]=1;
stm_Cin[1]=0;
stm_S[1]=3'b001;
asel[1]= 32'h00000001;
bsel[1]=32'h00000001;
dsel[1]=32'h00000001;
ref_abus[1]=32'hxxxxxxxx;
ref_bbus[1]=32'hxxxxxxxx;
ref_dbus[1]=32'hxxxxxxxx;
stm_CL[2]=0;
stm_Cin[2]=0;
stm_S[2]=3'b001;
asel[2]= 32'h00000001;
bsel[2]=32'h00000001;
dsel[2]=32'h00000001;
ref_abus[2]=32'h00000000;
ref_bbus[2]=32'h00000000;
ref_dbus[2]=32'hxxxxxxxx;
stm_CL[3]=1;
stm_Cin[3]=0;
stm_S[3]=3'b110;
asel[3]= 32'h00000001;
bsel[3]= 32'h00000001;
dsel[3]=32'h00000002;
ref_abus[3]=32'hxxxxxxxx;
ref_bbus[3]=32'hxxxxxxxx;
ref_dbus[3]=32'hFFFFFFFF;
stm_CL[4]=0;
stm_Cin[4]=0;
stm_S[4]=3'b001;
asel[4]=32'h00000001;
bsel[4]=32'h00000002;
dsel[4]=32'h00000001;
ref_abus[4]=32'h00000000;
ref_bbus[4]=32'hFFFFFFFF;
ref_dbus[4]=32'hxxxxxxxx;
stm_CL[5]=1;
stm_Cin[5]=0;
stm_S[5]=3'b100;
asel[5]=32'h00000001;
bsel[5]=32'h00000001;
dsel[5]=32'h00000004;
ref_abus[5]=32'hxxxxxxxx;
ref_bbus[5]=32'hxxxxxxxx;
ref_dbus[5]=32'hFFFFFFFF;
stm_CL[6]=0;
stm_Cin[6]=0;
stm_S[6]=3'b100;
asel[6]=32'h00000004;
bsel[6]=32'h00000002;
dsel[6]=32'h00000001;
ref_abus[6]=32'hFFFFFFFF;
ref_bbus[6]=32'hFFFFFFFF;
ref_dbus[6]=32'hxxxxxxxx;
stm_CL[7]=1;
stm_Cin[7]=0;
stm_S[7]=3'b000;
asel[7]=32'h00000001;
bsel[7]=32'h00000001;
dsel[7]=32'h00000008;
ref_abus[7]=32'hxxxxxxxx;
ref_bbus[7]=32'hxxxxxxxx;
ref_dbus[7]=32'hFFFFFFFF;
stm_CL[8]=0;
stm_Cin[8]=0;
stm_S[8]=3'b000;
asel[8]=32'h00000008;
bsel[8]=32'h00000004;
dsel[8]=32'h00000000;
ref_abus[8]=32'hFFFFFFFF;
ref_bbus[8]=32'hFFFFFFFF;
ref_dbus[8]=32'hxxxxxxxx;
stm_CL[9]=1;
stm_Cin[9]=0;
stm_S[9]=3'b001;
asel[9]=32'h00000001;
bsel[9]=32'h00000001;
dsel[9]=32'h00000010;
ref_abus[9]=32'hxxxxxxxx;
ref_bbus[9]=32'hxxxxxxxx;
ref_dbus[9]=32'h00000000;
stm_CL[10]=0;
stm_Cin[10]=0;
stm_S[10]=3'b001;
asel[10]=32'h00000008;
bsel[10]=32'h00000010;
dsel[10]=32'h00000000;
ref_abus[10]=32'hFFFFFFFF;
ref_bbus[10]=32'h00000000;
ref_dbus[10]=32'hxxxxxxxx;
stm_CL[11]=1;
stm_Cin[11]=0;
stm_S[11]=3'b101;
asel[11]=32'h00000001;
bsel[11]=32'h00000001;
dsel[11]=32'h00000020;
ref_abus[11]=32'hxxxxxxxx;
ref_bbus[11]=32'hxxxxxxxx;
ref_dbus[11]=32'hFFFFFFFF;
stm_CL[12]=0;
stm_Cin[12]=0;
stm_S[12]=3'b101;
asel[12]=32'h00000010;
bsel[12]=32'h00000020;
dsel[12]=32'h00000000;
ref_abus[12]=32'h00000000;
ref_bbus[12]=32'hFFFFFFFF;
ref_dbus[12]=32'hxxxxxxxx;
stm_CL[13]=1;
stm_Cin[13]=0;
stm_S[13]=3'b010;
asel[13]=32'h00000001;
bsel[13]=32'h00000001;
dsel[13]=32'h00000040;
ref_abus[13]=32'hxxxxxxxx;
ref_bbus[13]=32'hxxxxxxxx;
ref_dbus[13]=32'h00000000;
stm_CL[14]=0;
stm_Cin[14]=0;
stm_S[14]=3'b010;
asel[14]=32'h00000020;
bsel[14]=32'h00000040;
dsel[14]=32'h00000000;
ref_abus[14]=32'hFFFFFFFF;
ref_bbus[14]=32'h00000000;
ref_dbus[14]=32'hxxxxxxxx;
stm_CL[15]=1;
stm_Cin[15]=0;
stm_S[15]=3'b000;
asel[15]=32'h00000001;
bsel[15]=32'h00000001;
dsel[15]=32'h00000080;
ref_abus[15]=32'hxxxxxxxx;
ref_bbus[15]=32'hxxxxxxxx;
ref_dbus[15]=32'hFFFFFFFF;
stm_CL[16]=0;
stm_Cin[16]=0;
stm_S[16]=3'b000;
asel[16]=32'h00000040;
bsel[16]=32'h00000080;
dsel[16]=32'h00000000;
ref_abus[16]=32'h00000000;
ref_bbus[16]=32'hFFFFFFFF;
ref_dbus[16]=32'hxxxxxxxx;
stm_CL[17]=1;
stm_Cin[17]=0;
stm_S[17]=3'b001;
asel[17]=32'h00000001;
bsel[17]=32'h00000001;
dsel[17]=32'h00000100;
ref_abus[17]=32'hxxxxxxxx;
ref_bbus[17]=32'hxxxxxxxx;
ref_dbus[17]=32'hFFFFFFFF;
stm_CL[18]=0;
stm_Cin[18]=0;
stm_S[18]=3'b001;
asel[18]=32'h00000080;
bsel[18]=32'h00000100;
dsel[18]=32'h00000100;
ref_abus[18]=32'hFFFFFFFF;
ref_bbus[18]=32'hFFFFFFFF;
ref_dbus[18]=32'hxxxxxxxx;
stm_CL[19]=1;
stm_Cin[19]=0;
stm_S[19]=3'b100;
asel[19]=32'h00000001;
bsel[19]=32'h00000001;
dsel[19]=32'h00000200;
ref_abus[19]=32'hxxxxxxxx;
ref_bbus[19]=32'hxxxxxxxx;
ref_dbus[19]=32'h00000000;
stm_CL[20]=0;
stm_Cin[20]=0;
stm_S[20]=3'b100;
asel[20]=32'h00000100;
bsel[20]=32'h00000200;
dsel[20]=32'h00000000;
ref_abus[20]=32'hFFFFFFFF;
ref_bbus[20]=32'h00000000;
ref_dbus[20]=32'hxxxxxxxx;
stm_CL[21]=1;
stm_Cin[21]=0;
stm_S[21]=3'b101;
asel[21]=32'h00000001;
bsel[21]=32'h00000001;
dsel[21]=32'h00000400;
ref_abus[21]=32'hxxxxxxxx;
ref_bbus[21]=32'hxxxxxxxx;
ref_dbus[21]=32'hFFFFFFFF;
stm_CL[22]=0;
stm_Cin[22]=0;
stm_S[22]=3'b101;
asel[22]=32'h00000200;
bsel[22]=32'h00000400;
dsel[22]=32'h00000000;
ref_abus[22]=32'h00000000;
ref_bbus[22]=32'hFFFFFFFF;
ref_dbus[22]=32'hxxxxxxxx;
stm_CL[23]=1;
stm_Cin[23]=0;
stm_S[23]=3'b110;
asel[23]=32'h0000001;
bsel[23]=32'h0000001;
dsel[23]=32'h0000800;
ref_abus[23]=32'hxxxxxxxx;
ref_bbus[23]=32'hxxxxxxxx;
ref_dbus[23]=32'h00000000;
stm_CL[24]=0;
stm_Cin[24]=0;
stm_S[24]=3'b110;
asel[24]=32'h00000400;
bsel[24]=32'h00000800;
dsel[24]=32'h00000000;
ref_abus[24]=32'hFFFFFFFF;
ref_bbus[24]=32'h00000000;
ref_dbus[24]=32'hxxxxxxxx;
stm_CL[25]=1;
stm_Cin[25]=0;
stm_S[25]=3'b000;
asel[25]=32'h00000001;
bsel[25]=32'h00000001;
dsel[25]=32'h00001000;
ref_abus[25]=32'hxxxxxxxx;
ref_bbus[25]=32'hxxxxxxxx;
ref_dbus[25]=32'h00000000;
stm_CL[26]=0;
stm_Cin[26]=0;
stm_S[26]=3'b000;
asel[26]=32'h00000800;
bsel[26]=32'h00001000;
dsel[26]=32'h00000000;
ref_abus[26]=32'h00000000;
ref_bbus[26]=32'h00000000;
ref_dbus[26]=32'hxxxxxxxx;
stm_CL[27]=1;
stm_Cin[27]=0;
stm_S[27]=3'b001;
asel[27]=32'h00000001;
bsel[27]=32'h00000001;
dsel[27]=32'h00002000;
ref_abus[27]=32'hxxxxxxxx;
ref_bbus[27]=32'hxxxxxxxx;
ref_dbus[27]=32'hFFFFFFFF;
stm_CL[28]=0;
stm_Cin[28]=0;
stm_S[28]=3'b001;
asel[28]=32'h00001000;
bsel[28]=32'h00002000;
dsel[28]=32'h00000000;
ref_abus[28]=32'h00000000;
ref_bbus[28]=32'hFFFFFFFF;
ref_dbus[28]=32'hxxxxxxxx;
stm_CL[29]=1;
stm_Cin[29]=1;
stm_S[29]=3'b110;
asel[29]=32'h00000001;
bsel[29]=32'h00000001;
dsel[29]=32'h00004000;
ref_abus[29]=32'hxxxxxxxx;
ref_bbus[29]=32'hxxxxxxxx;
ref_dbus[29]=32'hFFFFFFFF;
dontcare = 32'hxxxxxxxx;
ntests = 30;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
for (k=0; k<= 29; k=k+1)
begin
Aselect=asel[k]; Bselect=bsel[k]; Dselect=dsel[k]; clk=stm_CL[k]; S=stm_S[k]; Cin=stm_Cin[k];
#25
if ( k >= 3) begin
if ( stm_S[k-2] == 3'b000 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XOR B -----");
if ( stm_S[k-2] == 3'b001 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A XNOR B -----");
if ( stm_S[k-2] == 3'b010 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A + B // CARRY CHAIN -----");
if ( stm_S[k-2] == 3'b100 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A OR B -----");
if ( stm_S[k-2] == 3'b011 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A - B -----");
if ( stm_S[k-2] == 3'b101 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A NOR B -----");
if ( stm_S[k-2] == 3'b110 && (k== 3 || k== 5 || k== 7 || k== 9 || k== 11 || k== 13 || k== 15 || k== 17 || k== 19 || k== 21 || k== 23 || k== 25 || k== 27 || k== 29))
$display ("----- TEST FOR A AND B -----");
end
$display ("Test=%d \n Time=%t \n Clk=%b \n S=%b \n Cin=%b \n Aselect=%b \n Bselect=%b \n Dselect=%b \n abus=%b \n ref_abus=%b \n bbus=%b \n ref_bbus=%b \n dbus=%b \n ref_dbus=%b \n ", k, $realtime, clk, S, Cin, Aselect, Bselect, Dselect, abus, ref_abus[k], bbus, ref_bbus[k], dbus, ref_dbus[k]);
if ( ( (ref_bbus[k] !== bbus) && (ref_bbus[k] !== dontcare) ) || ( (ref_abus[k] !== abus) && (ref_abus[k] !== dontcare)) || ( (ref_dbus[k] !== dbus) && (ref_dbus[k] !== dontcare)) )
begin
$display ("-------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( error !== 0)
begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,085 | data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v | 93,595,154 | regalu.v | v | 88 | 83 | [] | [] | [] | [(9, 38), (40, 67), (69, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v:30: Cannot find file containing module: 'alupipe'\n alupipe alup(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.v\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.sv\n alupipe\n alupipe.v\n alupipe.sv\n obj_dir/alupipe\n obj_dir/alupipe.v\n obj_dir/alupipe.sv\n%Error: Exiting due to 1 error(s)\n" | 310,878 | module | module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule | module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus); |
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule | 0 |
141,086 | data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v | 93,595,154 | regalu.v | v | 88 | 83 | [] | [] | [] | [(9, 38), (40, 67), (69, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v:30: Cannot find file containing module: 'alupipe'\n alupipe alup(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.v\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.sv\n alupipe\n alupipe.v\n alupipe.sv\n obj_dir/alupipe\n obj_dir/alupipe.v\n obj_dir/alupipe.sv\n%Error: Exiting due to 1 error(s)\n" | 310,878 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
); |
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,087 | data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v | 93,595,154 | regalu.v | v | 88 | 83 | [] | [] | [] | [(9, 38), (40, 67), (69, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new/regalu.v:30: Cannot find file containing module: 'alupipe'\n alupipe alup(\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.v\n data/full_repos/permissive/93595154/assignment_4/assignment_4.srcs/sources_1/new,data/full_repos/permissive/93595154/alupipe.sv\n alupipe\n alupipe.v\n alupipe.sv\n obj_dir/alupipe\n obj_dir/alupipe.v\n obj_dir/alupipe.sv\n%Error: Exiting due to 1 error(s)\n" | 310,878 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
always @(negedge wireclk) begin
data = dbus;
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
always @(negedge wireclk) begin
data = dbus;
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | 0 |
141,088 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);
input [31:0] ibus;
input clk;
output [31:0] Aselect;
output [31:0] Bselect;
output [31:0] Dselect;
output [2:0] S;
output Imm;
output Cin;
reg immHolder;
reg [2:0] S_holder;
reg Cin_holder;
wire [31:0] IF_ID_OUT;
wire [31:0] ID_EX_IN;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [5:0] opCode;
wire [5:0] funktion;
wire [5:0] opCodeThing;
wire [5:0] opCodeThing2;
wire [31:0] EX_MEM_IN;
wire [4:0] muxOut;
DflipFlop IFID(.dataIn(ibus), .clk(clk), .dataOut(IF_ID_OUT));
assign opCode = IF_ID_OUT[31:26];
assign rs = IF_ID_OUT[25:21];
assign rt = IF_ID_OUT[20:16];
assign rd = IF_ID_OUT[15:11];
assign funktion = IF_ID_OUT[5:0];
assign Aselect = 1 << rs;
initial begin
immHolder = 1'bx;
Cin_holder = 1'bx;
S_holder = 3'bxxx;
end
always @(IF_ID_OUT) begin
immHolder = 1;
Cin_holder = 0;
case (opCode)
6'b000011: begin
S_holder = 3'b010;
end
6'b000010: begin
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
S_holder = 3'b000;
end
6'b001111: begin
S_holder = 3'b110;
end
6'b001100: begin
S_holder = 3'b100;
end
6'b000000: begin
immHolder= 0;
case (funktion)
6'b000011: begin
S_holder = 3'b010;
end
6'b000010: begin
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
S_holder = 3'b000;
end
6'b000111: begin
S_holder = 3'b110;
end
6'b000100: begin
S_holder = 3'b100;
end
endcase
end
endcase
end
assign Bselect = immHolder? 32'bx: 1 << rt;
assign muxOut = immHolder? rt:rd;
assign ID_EX_IN = 1 << muxOut;
assign opCodeThing = {immHolder,S_holder,Cin_holder};
DflipFlop2 ID_EX(.dataIn(ID_EX_IN),.clk(clk),.dataOut(EX_MEM_IN),.opCodeThingIn(opCodeThing),.opCodeThingOut(opCodeThing2));
assign Imm = opCodeThing2[4];
assign S = opCodeThing2[3:1];
assign Cin = opCodeThing2[0];
DflipFlop EXMEMm(.dataIn(EX_MEM_IN),.clk(clk),.dataOut(Dselect));
endmodule | module controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect); |
input [31:0] ibus;
input clk;
output [31:0] Aselect;
output [31:0] Bselect;
output [31:0] Dselect;
output [2:0] S;
output Imm;
output Cin;
reg immHolder;
reg [2:0] S_holder;
reg Cin_holder;
wire [31:0] IF_ID_OUT;
wire [31:0] ID_EX_IN;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [5:0] opCode;
wire [5:0] funktion;
wire [5:0] opCodeThing;
wire [5:0] opCodeThing2;
wire [31:0] EX_MEM_IN;
wire [4:0] muxOut;
DflipFlop IFID(.dataIn(ibus), .clk(clk), .dataOut(IF_ID_OUT));
assign opCode = IF_ID_OUT[31:26];
assign rs = IF_ID_OUT[25:21];
assign rt = IF_ID_OUT[20:16];
assign rd = IF_ID_OUT[15:11];
assign funktion = IF_ID_OUT[5:0];
assign Aselect = 1 << rs;
initial begin
immHolder = 1'bx;
Cin_holder = 1'bx;
S_holder = 3'bxxx;
end
always @(IF_ID_OUT) begin
immHolder = 1;
Cin_holder = 0;
case (opCode)
6'b000011: begin
S_holder = 3'b010;
end
6'b000010: begin
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
S_holder = 3'b000;
end
6'b001111: begin
S_holder = 3'b110;
end
6'b001100: begin
S_holder = 3'b100;
end
6'b000000: begin
immHolder= 0;
case (funktion)
6'b000011: begin
S_holder = 3'b010;
end
6'b000010: begin
S_holder = 3'b011;
Cin_holder = 1;
end
6'b000001: begin
S_holder = 3'b000;
end
6'b000111: begin
S_holder = 3'b110;
end
6'b000100: begin
S_holder = 3'b100;
end
endcase
end
endcase
end
assign Bselect = immHolder? 32'bx: 1 << rt;
assign muxOut = immHolder? rt:rd;
assign ID_EX_IN = 1 << muxOut;
assign opCodeThing = {immHolder,S_holder,Cin_holder};
DflipFlop2 ID_EX(.dataIn(ID_EX_IN),.clk(clk),.dataOut(EX_MEM_IN),.opCodeThingIn(opCodeThing),.opCodeThingOut(opCodeThing2));
assign Imm = opCodeThing2[4];
assign S = opCodeThing2[3:1];
assign Cin = opCodeThing2[0];
DflipFlop EXMEMm(.dataIn(EX_MEM_IN),.clk(clk),.dataOut(Dselect));
endmodule | 0 |
141,089 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module mux(rtIn, rdIn, imSwitch, out);
input [4:0] rtIn;
input [4:0] rdIn;
input imSwitch;
output [31:0] out;
wire [4:0] whichIn;
assign whichIn = imSwitch? rtIn : rdIn;
signExtend outExtend(.in(whichIn),.out(out));
endmodule | module mux(rtIn, rdIn, imSwitch, out); |
input [4:0] rtIn;
input [4:0] rdIn;
input imSwitch;
output [31:0] out;
wire [4:0] whichIn;
assign whichIn = imSwitch? rtIn : rdIn;
signExtend outExtend(.in(whichIn),.out(out));
endmodule | 0 |
141,090 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);
input [5:0] opcode;
input [5:0] funct;
output [11:0] opCodeOutputThing;
assign opCodeOutputThing= {opcode,funct};
output immFlag;
assign immFlag = opcode? 1'b1 : 1'b0;
endmodule | module opFunctDecode(opcode,funct,immFlag, opCodeOutputThing); |
input [5:0] opcode;
input [5:0] funct;
output [11:0] opCodeOutputThing;
assign opCodeOutputThing= {opcode,funct};
output immFlag;
assign immFlag = opcode? 1'b1 : 1'b0;
endmodule | 0 |
141,091 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module signExtend(in,out);
input [4:0] in;
output [31:0] out;
assign out = in[4]? {27'b0, in}: {27'b1, in};
endmodule | module signExtend(in,out); |
input [4:0] in;
output [31:0] out;
assign out = in[4]? {27'b0, in}: {27'b1, in};
endmodule | 0 |
141,092 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module DflipFlop(dataIn, clk, dataOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule | module DflipFlop(dataIn, clk, dataOut); |
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
always @(posedge clk) begin
dataOut = dataIn;
end
endmodule | 0 |
141,093 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module DflipFlop2(dataIn, clk, dataOut, opCodeThingIn, opCodeThingOut);
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
input [5:0] opCodeThingIn;
output [5:0] opCodeThingOut;
reg [5:0] opCodeThingOut;
always @(posedge clk) begin
dataOut = dataIn;
opCodeThingOut = opCodeThingIn;
end
endmodule | module DflipFlop2(dataIn, clk, dataOut, opCodeThingIn, opCodeThingOut); |
input [31:0] dataIn;
input clk;
output [31:0] dataOut;
reg [31:0] dataOut;
input [5:0] opCodeThingIn;
output [5:0] opCodeThingOut;
reg [5:0] opCodeThingOut;
always @(posedge clk) begin
dataOut = dataIn;
opCodeThingOut = opCodeThingIn;
end
endmodule | 0 |
141,094 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule | module regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus); |
input [31:0] Aselect;
input [31:0] Bselect;
input [31:0] Dselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
output [31:0] dbus;
input [2:0] S;
input Cin;
regfile reggie(
.Aselect(Aselect),
.Bselect(Bselect),
.Dselect(Dselect),
.dbus(dbus),
.bbus(bbus),
.abus(abus),
.clk(clk)
);
alupipe alup(
.S(S),
.Cin(Cin),
.clk(clk),
.abus(abus),
.bbus(bbus),
.dbus(dbus)
);
endmodule | 0 |
141,095 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
); |
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,096 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
always @(negedge wireclk) begin
data = dbus;
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
always @(negedge wireclk) begin
data = dbus;
end
assign abus = Aselect ? data : 32'bz;
assign bbus = Bselect ? data : 32'bz;
endmodule | 0 |
141,097 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module alupipe(S, abus, bbus, clk, Cin, dbus);
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;
wire [31:0] bInput;
wire [31:0] dInput;
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule | module alupipe(S, abus, bbus, clk, Cin, dbus); |
input [31:0] abus;
input [31:0] bbus;
input clk;
input [2:0] S;
input Cin;
output [31:0] dbus;
wire [31:0] aInput;
wire [31:0] bInput;
wire [31:0] dInput;
alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));
DflipFlop AFF(.dataIn(abus), .dataOut(aInput), .clk(clk));
DflipFlop BFF(.dataIn(bbus), .dataOut(bInput), .clk(clk));
DflipFlop DFF(.dataIn(dInput), .dataOut(dbus), .clk(clk));
endmodule | 0 |
141,099 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | module alu32 (d, Cout, V, a, b, Cin, S); |
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | 0 |
141,100 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,101 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,102 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,103 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,104 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,105 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,106 | data/full_repos/permissive/93595154/assignment_5/controller.v | 93,595,154 | controller.v | v | 544 | 127 | [] | [] | [] | [(8, 125), (128, 137), (140, 147), (150, 154), (157, 165), (168, 180), (182, 216), (219, 240), (242, 260), (264, 280), (282, 290), (295, 335), (338, 370), (373, 379), (382, 395), (398, 432), (435, 469), (472, 506), (509, 543)] | null | null | 1: b'%Warning-MODDUP: data/full_repos/permissive/93595154/assignment_5/controller.v:282: Duplicate declaration of module: \'DflipFlop\'\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n data/full_repos/permissive/93595154/assignment_5/controller.v:157: ... Location of original declaration\nmodule DflipFlop(dataIn, clk, dataOut);\n ^~~~~~~~~\n ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'Cout\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_5/controller.v:275: Cell has missing pin: \'V\'\n alu32 ALU(.a(aInput), .b(bInput), .Cin(Cin), .d(dInput), .S(S));\n ^~~\n%Warning-MULTITOP: data/full_repos/permissive/93595154/assignment_5/controller.v:128: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'controller\'\nmodule controller(ibus, clk, Cin, Imm, S, Aselect, Bselect, Dselect);\n ^~~~~~~~~~\n : ... Top module \'mux\'\nmodule mux(rtIn, rdIn, imSwitch, out);\n ^~~\n : ... Top module \'opFunctDecode\'\nmodule opFunctDecode(opcode,funct,immFlag, opCodeOutputThing);\n ^~~~~~~~~~~~~\n : ... Top module \'regalu\'\nmodule regalu(Aselect, Bselect, Dselect, clk, Cin, S, abus, bbus, dbus);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:113: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 5 bits.\n : ... In instance controller\n assign opCodeThing = {immHolder,S_holder,Cin_holder};\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_5/controller.v:146: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'opcode\' generates 6 bits.\n : ... In instance opFunctDecode\n assign immFlag = opcode? 1\'b1 : 1\'b0;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 310,879 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,107 | data/full_repos/permissive/93595154/assignment_5/controller_testbench.v | 93,595,154 | controller_testbench.v | v | 596 | 128 | [] | [] | [] | null | line:565: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:495: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12); \n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:507: Unsupported: Ignoring delay on this delayed statement.\n #25;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:514: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:556: Unsupported: Ignoring delay on this delayed statement.\n #20 \n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:563: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_5/controller_testbench.v:582: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,880 | module | module controller_testbench();
reg [31:0] ibustm[0:31], ibus, Ref_Aselect[0:31], Ref_Bselect[0:31],Ref_Dselect[0:31];
reg clk, Ref_Imm[0:31], Ref_Cin[0:31];
reg [2:0] Ref_S[0:31];
wire [2:0] S;
wire Cin,Imm;
wire [31:0] Aselect,Bselect, Dselect;
reg [31:0] dontcare;
reg neglect;
reg [2:0] neg;
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SADD = 3'b010;
parameter SSUB = 3'b011;
parameter SXOR = 3'b000;
parameter SAND = 3'b110;
parameter SOR = 3'b100;
controller dut(.ibus(ibus), .clk(clk), .Cin(Cin), .Imm(Imm), .S(S) , .Aselect(Aselect) , .Bselect(Bselect), .Dselect(Dselect));
initial begin
dontcare = 32'hxxxxxxxx;
neglect = 1'bx;
neg = 3'bxxx;
ibustm[0]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
ibustm[1]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
Ref_Aselect[1] = 32'b00000000000000000000000000000001;
Ref_Bselect[1] = 32'b00000000000000000000000000000001;
Ref_Dselect[1] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[1] =1'bx;
Ref_Cin[1] =1'bx;
Ref_S[1] = 3'bxxx;
ibustm[2]={ADDI, 5'b00000, 5'b00001, 16'hFFFF};
Ref_Aselect[2] = 32'b00000000000000000000000000000001;
Ref_Bselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[2] =1'b0;
Ref_Cin[2] =1'b1;
Ref_S[2] = SSUB;
ibustm[3]={ADDI, 5'b00000, 5'b00000, 16'hFFFF};
Ref_Aselect[3] = 32'b0000000000000000000000000000001;
Ref_Bselect[3] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[3] = 32'b0000000000000000010000000000000;
Ref_Imm[3] =1'b1;
Ref_Cin[3] =1'b0;
Ref_S[3] = SADD;
ibustm[4]={ADDI, 5'b00001, 5'b11110, 16'hAFC0};
Ref_Aselect[4] = 32'b00000000000000000000000000000010;
Ref_Bselect[4] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[4] = 32'b00000000000000000000000000000010;
Ref_Imm[4] =1'b1;
Ref_Cin[4] =1'b0;
Ref_S[4] = SADD;
ibustm[5]={Rformat, 5'b00000, 5'b00000, 5'b00000, 5'b00000, SUB};
Ref_Aselect[5] = 32'b0000000000000000000000000000001;
Ref_Bselect[5] = 32'b0000000000000000000000000000001;
Ref_Dselect[5] = 32'b0000000000000000000000000000001;
Ref_Imm[5] =1'b1;
Ref_Cin[5] =1'b0;
Ref_S[5] = SADD;
ibustm[6]={XORI, 5'b00000, 5'b00011, 16'h8CCB};
Ref_Aselect[6] = 32'b00000000000000000000000000000001;
Ref_Bselect[6] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[6] = 32'b01000000000000000000000000000000;
Ref_Imm[6] =1'b0;
Ref_Cin[6] =1'b1;
Ref_S[6] = SSUB;
ibustm[7]={ORI, 5'b00000, 5'b10101, 16'hF98B};
Ref_Aselect[7] = 32'b00000000000000000000000000000001;
Ref_Bselect[7] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[7] = 32'b00000000000000000000000000000001;
Ref_Imm[7] =1'b1;
Ref_Cin[7] =1'b0;
Ref_S[7] = SXOR;
ibustm[8]={Rformat, 5'b00001, 5'b00011, 5'b10000, 5'b00000, XOR};
Ref_Aselect[8] = 32'b00000000000000000000000000000010;
Ref_Bselect[8] = 32'b00000000000000000000000000001000;
Ref_Dselect[8] = 32'b00000000000000000000000000001000;
Ref_Imm[8] =1'b1;
Ref_Cin[8] =1'b0;
Ref_S[8] = SOR;
ibustm[9]={SUBI, 5'b10101, 5'b11111, 16'h0030};
Ref_Aselect[9] = 32'b00000000001000000000000000000000;
Ref_Bselect[9] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[9] = 32'b00000000001000000000000000000000;
Ref_Imm[9] =1'b0;
Ref_Cin[9] =1'b0;
Ref_S[9] = SXOR;
ibustm[10]={Rformat, 5'b10000, 5'b10101, 5'b00101, 5'b00000, XOR};
Ref_Aselect[10] = 32'b00000000000000010000000000000000;
Ref_Bselect[10] = 32'b00000000001000000000000000000000;
Ref_Dselect[10] = 32'b00000000000000010000000000000000;
Ref_Imm[10] =1'b1;
Ref_Cin[10] =1'b1;
Ref_S[10] = SSUB;
ibustm[11]={ORI, 5'b00000, 5'b01010, 16'h34FB};
Ref_Aselect[11] = 32'b00000000000000000000000000000001;
Ref_Bselect[11] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[11] = 32'b10000000000000000000000000000000;
Ref_Imm[11] =1'b0;
Ref_Cin[11] =1'b0;
Ref_S[11] = SXOR;
ibustm[12]={XORI, 5'b00001, 5'b10010, 16'h0B31};
Ref_Aselect[12] = 32'b00000000000000000000000000000010;
Ref_Bselect[12] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[12] = 32'b00000000000000000000000000100000;
Ref_Imm[12] =1'b1;
Ref_Cin[12] =1'b0;
Ref_S[12] = SOR;
ibustm[13]={Rformat, 5'b10000, 5'b00011, 5'b11000, 5'b00000, ADD};
Ref_Aselect[13] = 32'b00000000000000010000000000000000;
Ref_Bselect[13] = 32'b00000000000000000000000000001000;
Ref_Dselect[13] = 32'b00000000000000000000010000000000;
Ref_Imm[13] =1'b1;
Ref_Cin[13] =1'b0;
Ref_S[13] = SXOR;
ibustm[14]={Rformat, 5'b01010, 5'b01010, 5'b00111, 5'b00000, OR};
Ref_Aselect[14] = 32'b00000000000000000000010000000000;
Ref_Bselect[14] = 32'b00000000000000000000010000000000;
Ref_Dselect[14] = 32'b00000000000001000000000000000000;
Ref_Imm[14] =1'b0;
Ref_Cin[14] =1'b0;
Ref_S[14] = SADD;
ibustm[15]={XORI, 5'b10101, 5'b01100, 16'h00F0};
Ref_Aselect[15] = 32'b00000000001000000000000000000000;
Ref_Bselect[15] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[15] = 32'b00000001000000000000000000000000;
Ref_Imm[15] =1'b0;
Ref_Cin[15] =1'b0;
Ref_S[15] = SOR;
ibustm[16]={SUBI, 5'b11111, 5'b11010, 16'h0111};
Ref_Aselect[16] = 32'b10000000000000000000000000000000;
Ref_Bselect[16] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[16] = 32'b00000000000000000000000010000000;
Ref_Imm[16] =1'b1;
Ref_Cin[16] =1'b0;
Ref_S[16] = SXOR;
ibustm[17]={Rformat, 5'b00011, 5'b10101, 5'b10001, 5'b00000, ADD};
Ref_Aselect[17] = 32'b00000000000000000000000000001000;
Ref_Bselect[17] = 32'b00000000001000000000000000000000;
Ref_Dselect[17] = 32'b00000000000000000001000000000000;
Ref_Imm[17] =1'b1;
Ref_Cin[17] =1'b1;
Ref_S[17] = SSUB;
ibustm[18]={Rformat, 5'b00111, 5'b10101, 5'b01111, 5'b00000, XOR};
Ref_Aselect[18] = 32'b00000000000000000000000010000000;
Ref_Bselect[18] = 32'b00000000001000000000000000000000;
Ref_Dselect[18] = 32'b00000100000000000000000000000000;
Ref_Imm[18] =1'b0;
Ref_Cin[18] =1'b0;
Ref_S[18] = SADD;
ibustm[19]={ADDI, 5'b01101, 5'b01101, 16'hFFFF};
Ref_Aselect[19] = 32'b00000000000000000010000000000000;
Ref_Bselect[19] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[19] = 32'b00000000000000100000000000000000;
Ref_Imm[19] =1'b0;
Ref_Cin[19] =1'b0;
Ref_S[19] = SXOR;
ibustm[20]={ADDI, 5'b00001, 5'b10111, 16'hAFC0};
Ref_Aselect[20] = 32'b00000000000000000000000000000010;
Ref_Bselect[20] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[20] = 32'b00000000000000001000000000000000;
Ref_Imm[20] =1'b1;
Ref_Cin[20] =1'b0;
Ref_S[20] = SADD;
ibustm[21]={Rformat, 5'b00001, 5'b00001, 5'b10100, 5'b00000, SUB};
Ref_Aselect[21] = 32'b00000000000000000000000000000010;
Ref_Bselect[21] = 32'b00000000000000000000000000000010;
Ref_Dselect[21] = 32'b00000000000000000010000000000000;
Ref_Imm[21] =1'b1;
Ref_Cin[21] =1'b0;
Ref_S[21] = SADD;
ibustm[22]={XORI, 5'b00000, 5'b10011, 16'h8CCB};
Ref_Aselect[22] = 32'b00000000000000000000000000000001;
Ref_Bselect[22] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[22] = 32'b00000000100000000000000000000000;
Ref_Imm[22] =1'b0;
Ref_Cin[22] =1'b1;
Ref_S[22] = SSUB;
ibustm[23]={ORI, 5'b10100, 5'b01001, 16'hF98B};
Ref_Aselect[23] = 32'b00000000000100000000000000000000;
Ref_Bselect[23] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[23] = 32'b00000000000100000000000000000000;
Ref_Imm[23] =1'b1;
Ref_Cin[23] =1'b0;
Ref_S[23] = SXOR;
ibustm[24]={Rformat, 5'b01101, 5'b10011, 5'b00010, 5'b00000, XOR};
Ref_Aselect[24] = 32'b00000000000000000010000000000000;
Ref_Bselect[24] = 32'b00000000000010000000000000000000;
Ref_Dselect[24] = 32'b00000000000010000000000000000000;
Ref_Imm[24] =1'b1;
Ref_Cin[24] =1'b0;
Ref_S[24] = SOR;
ibustm[25]={SUBI, 5'b01001, 5'b11010, 16'h0030};
Ref_Aselect[25] = 32'b00000000000000000000001000000000;
Ref_Bselect[25] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[25] = 32'b00000000000000000000001000000000;
Ref_Imm[25] =1'b0;
Ref_Cin[25] =1'b0;
Ref_S[25] = SXOR;
ibustm[26]={Rformat, 5'b00010, 5'b01001, 5'b11001, 5'b00000, XOR};
Ref_Aselect[26] = 32'b00000000000000000000000000000100;
Ref_Bselect[26] = 32'b00000000000000000000001000000000;
Ref_Dselect[26] = 32'b00000000000000000000000000000100;
Ref_Imm[26] =1'b1;
Ref_Cin[26] =1'b1;
Ref_S[26] = SSUB;
ibustm[27]={ORI, 5'b10100, 5'b01000, 16'h34FB};
Ref_Aselect[27] = 32'b00000000000100000000000000000000;
Ref_Bselect[27] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[27] = 32'b00000100000000000000000000000000;
Ref_Imm[27] =1'b0;
Ref_Cin[27] =1'b0;
Ref_S[27] = SXOR;
ibustm[28]={XORI, 5'b01101, 5'b11011, 16'h0B31};
Ref_Aselect[28] = 32'b00000000000000000010000000000000;
Ref_Bselect[28] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[28] = 32'b00000010000000000000000000000000;
Ref_Imm[28] =1'b1;
Ref_Cin[28] =1'b0;
Ref_S[28] = SOR;
ibustm[29]={Rformat, 5'b00010, 5'b10011, 5'b01110, 5'b00000, ADD};
Ref_Aselect[29] = 32'b00000000000000000000000000000100;
Ref_Bselect[29] = 32'b00000000000010000000000000000000;
Ref_Dselect[29] = 32'b00000000000000000000000100000000;
Ref_Imm[29] =1'b1;
Ref_Cin[29] =1'b0;
Ref_S[29] = SXOR;
ibustm[30]={Rformat, 5'b01000, 5'b01000, 5'b00100, 5'b00000, OR};
Ref_Aselect[30] = 32'b00000000000000000000000100000000;
Ref_Bselect[30] = 32'b00000000000000000000000100000000;
Ref_Dselect[30] = 32'b00001000000000000000000000000000;
Ref_Imm[30] =1'b0;
Ref_Cin[30] =1'b0;
Ref_S[30] = SADD;
ibustm[31]={XORI, 5'b10101, 5'b01100, 16'h5555};
Ref_Aselect[31] = 32'b00000000001000000000000000000000;
Ref_Bselect[31] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[31] = 32'b00000000000000000100000000000000;
Ref_Imm[31] =1'b0;
Ref_Cin[31] =1'b0;
Ref_S[31] = SOR;
ntests = 180;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
$display("-------------------------------");
$display("Time=%t Instruction Number: 0 ",$realtime);
$display("-------------------------------");
ibus = ibustm[0];
#25;
for (k=1; k<= 31; k=k+1) begin
$display("-------------------------------");
$display("Time=%t Instruction Number: %d ",$realtime,k);
$display("-------------------------------");
clk=1;
#5
if (k>=1) begin
$display (" Testing Immediate, Cin and S for instruction %d", k-1);
$display (" Your Imm = %b", Imm);
$display (" Correct Imm = %b", Ref_Imm[k]);
if ( (Imm !== Ref_Imm[k]) && (Ref_Imm[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your Cin = %b", Cin);
$display (" Correct Cin = %b", Ref_Cin[k]);
if ( (Cin !== Ref_Cin[k]) && (Ref_Cin[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your S = %b", S);
$display (" Correct S = %b", Ref_S[k]);
if ( (S !== Ref_S[k]) && (Ref_S[k] !== 3'bxxx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
if (k>=2) begin
$display (" Testing Destination Registers for instruction %d", k-2);
$display (" Your Dselect = %b", Dselect);
$display (" Correct Dselect = %b", Ref_Dselect[k]);
if ( (Dselect !== Ref_Dselect[k]) && (Ref_Dselect[k] !== dontcare) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
#20
clk = 0;
$display ("-------------------------------");
$display (" Time=%t ",$realtime);
$display ("-------------------------------");
ibus = ibustm[k+1];
#5
$display (" Testing Source Registers for instruction %d", k);
$display (" Your Aselect = %b", Aselect);
$display (" Correct Aselect = %b", Ref_Aselect[k]);
if ( (Aselect !== Ref_Aselect[k]) && (Ref_Aselect[k]) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
$display (" Your Bselect = %b", Bselect);
$display (" Correct Bselect = %b", Ref_Bselect[k]);
if ( (Bselect !== Ref_Bselect[k]) && (Ref_Bselect[k] !== dontcare) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
#20
clk = 0;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----------YOU DID IT :-) !!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module controller_testbench(); |
reg [31:0] ibustm[0:31], ibus, Ref_Aselect[0:31], Ref_Bselect[0:31],Ref_Dselect[0:31];
reg clk, Ref_Imm[0:31], Ref_Cin[0:31];
reg [2:0] Ref_S[0:31];
wire [2:0] S;
wire Cin,Imm;
wire [31:0] Aselect,Bselect, Dselect;
reg [31:0] dontcare;
reg neglect;
reg [2:0] neg;
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SADD = 3'b010;
parameter SSUB = 3'b011;
parameter SXOR = 3'b000;
parameter SAND = 3'b110;
parameter SOR = 3'b100;
controller dut(.ibus(ibus), .clk(clk), .Cin(Cin), .Imm(Imm), .S(S) , .Aselect(Aselect) , .Bselect(Bselect), .Dselect(Dselect));
initial begin
dontcare = 32'hxxxxxxxx;
neglect = 1'bx;
neg = 3'bxxx;
ibustm[0]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
ibustm[1]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
Ref_Aselect[1] = 32'b00000000000000000000000000000001;
Ref_Bselect[1] = 32'b00000000000000000000000000000001;
Ref_Dselect[1] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[1] =1'bx;
Ref_Cin[1] =1'bx;
Ref_S[1] = 3'bxxx;
ibustm[2]={ADDI, 5'b00000, 5'b00001, 16'hFFFF};
Ref_Aselect[2] = 32'b00000000000000000000000000000001;
Ref_Bselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[2] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Imm[2] =1'b0;
Ref_Cin[2] =1'b1;
Ref_S[2] = SSUB;
ibustm[3]={ADDI, 5'b00000, 5'b00000, 16'hFFFF};
Ref_Aselect[3] = 32'b0000000000000000000000000000001;
Ref_Bselect[3] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[3] = 32'b0000000000000000010000000000000;
Ref_Imm[3] =1'b1;
Ref_Cin[3] =1'b0;
Ref_S[3] = SADD;
ibustm[4]={ADDI, 5'b00001, 5'b11110, 16'hAFC0};
Ref_Aselect[4] = 32'b00000000000000000000000000000010;
Ref_Bselect[4] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[4] = 32'b00000000000000000000000000000010;
Ref_Imm[4] =1'b1;
Ref_Cin[4] =1'b0;
Ref_S[4] = SADD;
ibustm[5]={Rformat, 5'b00000, 5'b00000, 5'b00000, 5'b00000, SUB};
Ref_Aselect[5] = 32'b0000000000000000000000000000001;
Ref_Bselect[5] = 32'b0000000000000000000000000000001;
Ref_Dselect[5] = 32'b0000000000000000000000000000001;
Ref_Imm[5] =1'b1;
Ref_Cin[5] =1'b0;
Ref_S[5] = SADD;
ibustm[6]={XORI, 5'b00000, 5'b00011, 16'h8CCB};
Ref_Aselect[6] = 32'b00000000000000000000000000000001;
Ref_Bselect[6] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[6] = 32'b01000000000000000000000000000000;
Ref_Imm[6] =1'b0;
Ref_Cin[6] =1'b1;
Ref_S[6] = SSUB;
ibustm[7]={ORI, 5'b00000, 5'b10101, 16'hF98B};
Ref_Aselect[7] = 32'b00000000000000000000000000000001;
Ref_Bselect[7] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[7] = 32'b00000000000000000000000000000001;
Ref_Imm[7] =1'b1;
Ref_Cin[7] =1'b0;
Ref_S[7] = SXOR;
ibustm[8]={Rformat, 5'b00001, 5'b00011, 5'b10000, 5'b00000, XOR};
Ref_Aselect[8] = 32'b00000000000000000000000000000010;
Ref_Bselect[8] = 32'b00000000000000000000000000001000;
Ref_Dselect[8] = 32'b00000000000000000000000000001000;
Ref_Imm[8] =1'b1;
Ref_Cin[8] =1'b0;
Ref_S[8] = SOR;
ibustm[9]={SUBI, 5'b10101, 5'b11111, 16'h0030};
Ref_Aselect[9] = 32'b00000000001000000000000000000000;
Ref_Bselect[9] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[9] = 32'b00000000001000000000000000000000;
Ref_Imm[9] =1'b0;
Ref_Cin[9] =1'b0;
Ref_S[9] = SXOR;
ibustm[10]={Rformat, 5'b10000, 5'b10101, 5'b00101, 5'b00000, XOR};
Ref_Aselect[10] = 32'b00000000000000010000000000000000;
Ref_Bselect[10] = 32'b00000000001000000000000000000000;
Ref_Dselect[10] = 32'b00000000000000010000000000000000;
Ref_Imm[10] =1'b1;
Ref_Cin[10] =1'b1;
Ref_S[10] = SSUB;
ibustm[11]={ORI, 5'b00000, 5'b01010, 16'h34FB};
Ref_Aselect[11] = 32'b00000000000000000000000000000001;
Ref_Bselect[11] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[11] = 32'b10000000000000000000000000000000;
Ref_Imm[11] =1'b0;
Ref_Cin[11] =1'b0;
Ref_S[11] = SXOR;
ibustm[12]={XORI, 5'b00001, 5'b10010, 16'h0B31};
Ref_Aselect[12] = 32'b00000000000000000000000000000010;
Ref_Bselect[12] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[12] = 32'b00000000000000000000000000100000;
Ref_Imm[12] =1'b1;
Ref_Cin[12] =1'b0;
Ref_S[12] = SOR;
ibustm[13]={Rformat, 5'b10000, 5'b00011, 5'b11000, 5'b00000, ADD};
Ref_Aselect[13] = 32'b00000000000000010000000000000000;
Ref_Bselect[13] = 32'b00000000000000000000000000001000;
Ref_Dselect[13] = 32'b00000000000000000000010000000000;
Ref_Imm[13] =1'b1;
Ref_Cin[13] =1'b0;
Ref_S[13] = SXOR;
ibustm[14]={Rformat, 5'b01010, 5'b01010, 5'b00111, 5'b00000, OR};
Ref_Aselect[14] = 32'b00000000000000000000010000000000;
Ref_Bselect[14] = 32'b00000000000000000000010000000000;
Ref_Dselect[14] = 32'b00000000000001000000000000000000;
Ref_Imm[14] =1'b0;
Ref_Cin[14] =1'b0;
Ref_S[14] = SADD;
ibustm[15]={XORI, 5'b10101, 5'b01100, 16'h00F0};
Ref_Aselect[15] = 32'b00000000001000000000000000000000;
Ref_Bselect[15] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[15] = 32'b00000001000000000000000000000000;
Ref_Imm[15] =1'b0;
Ref_Cin[15] =1'b0;
Ref_S[15] = SOR;
ibustm[16]={SUBI, 5'b11111, 5'b11010, 16'h0111};
Ref_Aselect[16] = 32'b10000000000000000000000000000000;
Ref_Bselect[16] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[16] = 32'b00000000000000000000000010000000;
Ref_Imm[16] =1'b1;
Ref_Cin[16] =1'b0;
Ref_S[16] = SXOR;
ibustm[17]={Rformat, 5'b00011, 5'b10101, 5'b10001, 5'b00000, ADD};
Ref_Aselect[17] = 32'b00000000000000000000000000001000;
Ref_Bselect[17] = 32'b00000000001000000000000000000000;
Ref_Dselect[17] = 32'b00000000000000000001000000000000;
Ref_Imm[17] =1'b1;
Ref_Cin[17] =1'b1;
Ref_S[17] = SSUB;
ibustm[18]={Rformat, 5'b00111, 5'b10101, 5'b01111, 5'b00000, XOR};
Ref_Aselect[18] = 32'b00000000000000000000000010000000;
Ref_Bselect[18] = 32'b00000000001000000000000000000000;
Ref_Dselect[18] = 32'b00000100000000000000000000000000;
Ref_Imm[18] =1'b0;
Ref_Cin[18] =1'b0;
Ref_S[18] = SADD;
ibustm[19]={ADDI, 5'b01101, 5'b01101, 16'hFFFF};
Ref_Aselect[19] = 32'b00000000000000000010000000000000;
Ref_Bselect[19] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[19] = 32'b00000000000000100000000000000000;
Ref_Imm[19] =1'b0;
Ref_Cin[19] =1'b0;
Ref_S[19] = SXOR;
ibustm[20]={ADDI, 5'b00001, 5'b10111, 16'hAFC0};
Ref_Aselect[20] = 32'b00000000000000000000000000000010;
Ref_Bselect[20] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[20] = 32'b00000000000000001000000000000000;
Ref_Imm[20] =1'b1;
Ref_Cin[20] =1'b0;
Ref_S[20] = SADD;
ibustm[21]={Rformat, 5'b00001, 5'b00001, 5'b10100, 5'b00000, SUB};
Ref_Aselect[21] = 32'b00000000000000000000000000000010;
Ref_Bselect[21] = 32'b00000000000000000000000000000010;
Ref_Dselect[21] = 32'b00000000000000000010000000000000;
Ref_Imm[21] =1'b1;
Ref_Cin[21] =1'b0;
Ref_S[21] = SADD;
ibustm[22]={XORI, 5'b00000, 5'b10011, 16'h8CCB};
Ref_Aselect[22] = 32'b00000000000000000000000000000001;
Ref_Bselect[22] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[22] = 32'b00000000100000000000000000000000;
Ref_Imm[22] =1'b0;
Ref_Cin[22] =1'b1;
Ref_S[22] = SSUB;
ibustm[23]={ORI, 5'b10100, 5'b01001, 16'hF98B};
Ref_Aselect[23] = 32'b00000000000100000000000000000000;
Ref_Bselect[23] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[23] = 32'b00000000000100000000000000000000;
Ref_Imm[23] =1'b1;
Ref_Cin[23] =1'b0;
Ref_S[23] = SXOR;
ibustm[24]={Rformat, 5'b01101, 5'b10011, 5'b00010, 5'b00000, XOR};
Ref_Aselect[24] = 32'b00000000000000000010000000000000;
Ref_Bselect[24] = 32'b00000000000010000000000000000000;
Ref_Dselect[24] = 32'b00000000000010000000000000000000;
Ref_Imm[24] =1'b1;
Ref_Cin[24] =1'b0;
Ref_S[24] = SOR;
ibustm[25]={SUBI, 5'b01001, 5'b11010, 16'h0030};
Ref_Aselect[25] = 32'b00000000000000000000001000000000;
Ref_Bselect[25] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[25] = 32'b00000000000000000000001000000000;
Ref_Imm[25] =1'b0;
Ref_Cin[25] =1'b0;
Ref_S[25] = SXOR;
ibustm[26]={Rformat, 5'b00010, 5'b01001, 5'b11001, 5'b00000, XOR};
Ref_Aselect[26] = 32'b00000000000000000000000000000100;
Ref_Bselect[26] = 32'b00000000000000000000001000000000;
Ref_Dselect[26] = 32'b00000000000000000000000000000100;
Ref_Imm[26] =1'b1;
Ref_Cin[26] =1'b1;
Ref_S[26] = SSUB;
ibustm[27]={ORI, 5'b10100, 5'b01000, 16'h34FB};
Ref_Aselect[27] = 32'b00000000000100000000000000000000;
Ref_Bselect[27] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[27] = 32'b00000100000000000000000000000000;
Ref_Imm[27] =1'b0;
Ref_Cin[27] =1'b0;
Ref_S[27] = SXOR;
ibustm[28]={XORI, 5'b01101, 5'b11011, 16'h0B31};
Ref_Aselect[28] = 32'b00000000000000000010000000000000;
Ref_Bselect[28] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[28] = 32'b00000010000000000000000000000000;
Ref_Imm[28] =1'b1;
Ref_Cin[28] =1'b0;
Ref_S[28] = SOR;
ibustm[29]={Rformat, 5'b00010, 5'b10011, 5'b01110, 5'b00000, ADD};
Ref_Aselect[29] = 32'b00000000000000000000000000000100;
Ref_Bselect[29] = 32'b00000000000010000000000000000000;
Ref_Dselect[29] = 32'b00000000000000000000000100000000;
Ref_Imm[29] =1'b1;
Ref_Cin[29] =1'b0;
Ref_S[29] = SXOR;
ibustm[30]={Rformat, 5'b01000, 5'b01000, 5'b00100, 5'b00000, OR};
Ref_Aselect[30] = 32'b00000000000000000000000100000000;
Ref_Bselect[30] = 32'b00000000000000000000000100000000;
Ref_Dselect[30] = 32'b00001000000000000000000000000000;
Ref_Imm[30] =1'b0;
Ref_Cin[30] =1'b0;
Ref_S[30] = SADD;
ibustm[31]={XORI, 5'b10101, 5'b01100, 16'h5555};
Ref_Aselect[31] = 32'b00000000001000000000000000000000;
Ref_Bselect[31] = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
Ref_Dselect[31] = 32'b00000000000000000100000000000000;
Ref_Imm[31] =1'b0;
Ref_Cin[31] =1'b0;
Ref_S[31] = SOR;
ntests = 180;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
$display("-------------------------------");
$display("Time=%t Instruction Number: 0 ",$realtime);
$display("-------------------------------");
ibus = ibustm[0];
#25;
for (k=1; k<= 31; k=k+1) begin
$display("-------------------------------");
$display("Time=%t Instruction Number: %d ",$realtime,k);
$display("-------------------------------");
clk=1;
#5
if (k>=1) begin
$display (" Testing Immediate, Cin and S for instruction %d", k-1);
$display (" Your Imm = %b", Imm);
$display (" Correct Imm = %b", Ref_Imm[k]);
if ( (Imm !== Ref_Imm[k]) && (Ref_Imm[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your Cin = %b", Cin);
$display (" Correct Cin = %b", Ref_Cin[k]);
if ( (Cin !== Ref_Cin[k]) && (Ref_Cin[k] !== 1'bx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
$display (" Your S = %b", S);
$display (" Correct S = %b", Ref_S[k]);
if ( (S !== Ref_S[k]) && (Ref_S[k] !== 3'bxxx) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
if (k>=2) begin
$display (" Testing Destination Registers for instruction %d", k-2);
$display (" Your Dselect = %b", Dselect);
$display (" Correct Dselect = %b", Ref_Dselect[k]);
if ( (Dselect !== Ref_Dselect[k]) && (Ref_Dselect[k] !== dontcare) ) begin
error = error+1;
$display("-------ERROR. Mismatch Has Occured--------");
end
end
#20
clk = 0;
$display ("-------------------------------");
$display (" Time=%t ",$realtime);
$display ("-------------------------------");
ibus = ibustm[k+1];
#5
$display (" Testing Source Registers for instruction %d", k);
$display (" Your Aselect = %b", Aselect);
$display (" Correct Aselect = %b", Ref_Aselect[k]);
if ( (Aselect !== Ref_Aselect[k]) && (Ref_Aselect[k]) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
$display (" Your Bselect = %b", Bselect);
$display (" Correct Bselect = %b", Ref_Bselect[k]);
if ( (Bselect !== Ref_Bselect[k]) && (Ref_Bselect[k] !== dontcare) ) begin
error = error+1;
$display("-------------ERROR. Mismatch Has Occured---------------");
end
#20
clk = 0;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----------YOU DID IT :-) !!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,108 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module cpu3(ibus,clk,abus,bbus,dbus);
input clk;
wire [5:0] opCode;
wire [5:0] funktion;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [5:0] rs;
wire [31:0] BselectWire;
wire [5:0] rt;
reg immBit1;
wire immBit2;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
output [31:0] abus;
wire [31:0] abusWire1;
wire [31:0] abusWire2;
output [31:0] bbus;
wire [31:0] bbusWire1;
wire [31:0] bbusWire2;
output [31:0] dbus;
wire [31:0] dbusWire1;
wire [31:0] dbusWire2;
wire [31:0] mux2Out;
wire [31:0] immWire1;
wire [31:0] immWire2;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
end
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire));
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
always @(ibusWire) begin
immBit1 = 1;
CinWire1 = 0;
case (opCode)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b001111: begin
SWire1 = 3'b110;
end
6'b001100: begin
SWire1 = 3'b100;
end
6'b000000: begin
immBit1= 0;
case (funktion)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b000111: begin
SWire1 = 3'b110;
end
6'b000100: begin
SWire1 = 3'b100;
end
endcase
end
endcase
end
assign AselectWire = 1 << rs;
assign BselectWire = 1 << rt;
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire3),.abus(abusWire1),.bbus(bbusWire1),.dbus(dbusWire2));
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),.CinWire1(CinWire1),.immBit1(immBit1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2);
assign abus = abusWire2;
assign mux2Out = immBit2? immWire2: bbusWire2;
assign bbus = mux2Out;
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1),.DselectWire2(DselectWire2),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3));
assign dbus = dbusWire2;
endmodule | module cpu3(ibus,clk,abus,bbus,dbus); |
input clk;
wire [5:0] opCode;
wire [5:0] funktion;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [5:0] rs;
wire [31:0] BselectWire;
wire [5:0] rt;
reg immBit1;
wire immBit2;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
output [31:0] abus;
wire [31:0] abusWire1;
wire [31:0] abusWire2;
output [31:0] bbus;
wire [31:0] bbusWire1;
wire [31:0] bbusWire2;
output [31:0] dbus;
wire [31:0] dbusWire1;
wire [31:0] dbusWire2;
wire [31:0] mux2Out;
wire [31:0] immWire1;
wire [31:0] immWire2;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
end
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire));
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
always @(ibusWire) begin
immBit1 = 1;
CinWire1 = 0;
case (opCode)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b001111: begin
SWire1 = 3'b110;
end
6'b001100: begin
SWire1 = 3'b100;
end
6'b000000: begin
immBit1= 0;
case (funktion)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b000111: begin
SWire1 = 3'b110;
end
6'b000100: begin
SWire1 = 3'b100;
end
endcase
end
endcase
end
assign AselectWire = 1 << rs;
assign BselectWire = 1 << rt;
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire3),.abus(abusWire1),.bbus(bbusWire1),.dbus(dbusWire2));
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),.CinWire1(CinWire1),.immBit1(immBit1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2);
assign abus = abusWire2;
assign mux2Out = immBit2? immWire2: bbusWire2;
assign bbus = mux2Out;
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1),.DselectWire2(DselectWire2),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3));
assign dbus = dbusWire2;
endmodule | 0 |
141,109 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module pipeline_1_latch(clk, ibus, ibusWire);
input [31:0] ibus;
input clk;
output [31:0] ibusWire;
reg [31:0] ibusWire;
always @(posedge clk) begin
ibusWire = ibus;
end
endmodule | module pipeline_1_latch(clk, ibus, ibusWire); |
input [31:0] ibus;
input clk;
output [31:0] ibusWire;
reg [31:0] ibusWire;
always @(posedge clk) begin
ibusWire = ibus;
end
endmodule | 0 |
141,110 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
end
endmodule | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2); |
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
end
endmodule | 0 |
141,111 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module pipeline_3_latch(clk, dbusWire1, DselectWire2, dbusWire2, DselectWire3);
input clk;
input [31:0] dbusWire1, DselectWire2;
output [31:0] dbusWire2, DselectWire3;
reg [31:0] dbusWire2, DselectWire3;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
end
endmodule | module pipeline_3_latch(clk, dbusWire1, DselectWire2, dbusWire2, DselectWire3); |
input clk;
input [31:0] dbusWire1, DselectWire2;
output [31:0] dbusWire2, DselectWire3;
reg [31:0] dbusWire2, DselectWire3;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
end
endmodule | 0 |
141,112 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
); |
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,113 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge wireclk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge wireclk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule | 0 |
141,114 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | module alu32 (d, Cout, V, a, b, Cin, S); |
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | 0 |
141,115 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,116 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,117 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,118 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,119 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,120 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,121 | data/full_repos/permissive/93595154/assignment_6/cpu3.v | 93,595,154 | cpu3.v | v | 518 | 321 | [] | [] | [] | null | line:154: before: ")" | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'Cout\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_6/cpu3.v:165: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2));\n ^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:65: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:66: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_6/cpu3.v:67: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu3\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 5 warning(s)\n' | 310,882 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,122 | data/full_repos/permissive/93595154/assignment_6/cpu3_testbench.v | 93,595,154 | cpu3_testbench.v | v | 430 | 126 | [] | [] | [] | null | line:399: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_6/cpu3_testbench.v:367: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12); \n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_6/cpu3_testbench.v:395: Unsupported: Ignoring delay on this delayed statement.\n #25 \n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_6/cpu3_testbench.v:416: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,883 | module | module cpu3_testbench();
reg [31:0] ibustm[0:30], ibus;
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg clk;
reg [31:0] dontcare, abusin[0:30], bbusin[0:30], dbusout[0:30];
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
cpu3 dut(.ibus(ibus), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus));
initial begin
ibustm[0]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
abusin[0]=32'h00000000;
bbusin[0]=32'h00000000;
dbusout[0]=32'h00000000;
ibustm[1]={ADDI, 5'b00000, 5'b00001, 16'h0000};
abusin[1]=32'h00000000;
bbusin[1]=32'h00000000;
dbusout[1]=32'h00000000;
ibustm[2]={ADDI, 5'b00000, 5'b00000, 16'hFFFF};
abusin[2]=32'h00000000;
bbusin[2]=32'hFFFFFFFF;
dbusout[2]=32'hFFFFFFFF;
ibustm[3]={ADDI, 5'b00001, 5'b11110, 16'hAFC0};
abusin[3]=32'h00000000;
bbusin[3]=32'hFFFFAFC0;
dbusout[3]=32'hFFFFAFC0;
ibustm[4]={Rformat, 5'b00000, 5'b00000, 5'b00000, 5'b00000, SUB};
abusin[4]=32'h00000000;
bbusin[4]=32'h00000000;
dbusout[4]=32'h00000000;
ibustm[5]={ORI, 5'b00001, 5'b00011, 16'h7334};
abusin[5]=32'h00000000;
bbusin[5]=32'h00007334;
dbusout[5]=32'h00007334;
ibustm[6]={ORI, 5'b00001, 5'b10101, 16'hF98B};
abusin[6]=32'h00000000;
bbusin[6]=32'hFFFFF98B;
dbusout[6]=32'hFFFFF98B;
ibustm[7]={Rformat, 5'b00001, 5'b00011, 5'b10000, 5'b00000, XOR};
abusin[7]=32'h00000000;
bbusin[7]=32'h00007334;
dbusout[7]=32'h00007334;
ibustm[8]={SUBI, 5'b10101, 5'b11111, 16'h0030};
abusin[8]=32'hFFFFF98B;
bbusin[8]=32'h00000030;
dbusout[8]=32'hFFFFF95B;
ibustm[9]={ORI, 5'b00001, 5'b00101, 16'h8ABF};
abusin[9]=32'h00000000;
bbusin[9]=32'hFFFF8ABF;
dbusout[9]=32'hFFFF8ABF;
ibustm[10]={ORI, 5'b00001, 5'b01010, 16'h34FB};
abusin[10]=32'h00000000;
bbusin[10]=32'h000034FB;
dbusout[10]=32'h000034FB;
ibustm[11]={XORI, 5'b00001, 5'b10010, 16'h0B31};
abusin[11]=32'h00000000;
bbusin[11]=32'h00000B31;
dbusout[11]=32'h00000B31;
ibustm[12]={Rformat, 5'b10000, 5'b00011, 5'b11000, 5'b00000, ADD};
abusin[12]=32'h00007334;
bbusin[12]=32'h00007334;
dbusout[12]=32'h0000E668;
ibustm[13]={Rformat, 5'b01010, 5'b01010, 5'b00111, 5'b00000, OR};
abusin[13]=32'h000034FB;
bbusin[13]=32'h000034FB;
dbusout[13]=32'h000034FB;
ibustm[14]={XORI, 5'b10101, 5'b01100, 16'h00F0};
abusin[14]=32'hFFFFF98B;
bbusin[14]=32'h000000F0;
dbusout[14]=32'hFFFFF97B;
ibustm[15]={SUBI, 5'b11111, 5'b11100, 16'h0111};
abusin[15]=32'hFFFFF95B;
bbusin[15]=32'h00000111;
dbusout[15]=32'hFFFFF84A;
ibustm[16]={Rformat, 5'b00011, 5'b10101, 5'b10001, 5'b00000, ADD};
abusin[16]=32'h00007334;
bbusin[16]=32'hFFFFF98B;
dbusout[16]=32'h00006CBF;
ibustm[17]={ORI, 5'b00001, 5'b01111, 16'h328F};
abusin[17]=32'h00000000;
bbusin[17]=32'h0000328F;
dbusout[17]=32'h0000328F;
ibustm[18]={ADDI, 5'b01101, 5'b01101, 16'hFFFF};
abusin[18]=32'h00000000;
bbusin[18]=32'hFFFFFFFF;
dbusout[18]=32'hFFFFFFFF;
ibustm[19]={ADDI, 5'b00001, 5'b10111, 16'hAFC0};
abusin[19]=32'h00000000;
bbusin[19]=32'hFFFFAFC0;
dbusout[19]=32'hFFFFAFC0;
ibustm[20]={Rformat, 5'b00001, 5'b00001, 5'b10100, 5'b00000, SUB};
abusin[20]=32'h00000000;
bbusin[20]=32'h00000000;
dbusout[20]=32'h00000000;
ibustm[21]={ORI, 5'b00001, 5'b10011, 16'h7334};
abusin[21]=32'h00000000;
bbusin[21]=32'h00007334;
dbusout[21]=32'h00007334;
ibustm[22]={ORI, 5'b01101, 5'b01001, 16'hF98B};
abusin[22]=32'hFFFFFFFF;
bbusin[22]=32'hFFFFF98B;
dbusout[22]=32'hFFFFFFFF;
ibustm[23]={Rformat, 5'b01101, 5'b10011, 5'b00010, 5'b00000, XOR};
abusin[23]=32'hFFFFFFFF;
bbusin[23]=32'h00007334;
dbusout[23]=32'hFFFF8CCB;
ibustm[24]={SUBI, 5'b01001, 5'b11010, 16'h0030};
abusin[24]=32'hFFFFFFFF;
bbusin[24]=32'h00000030;
dbusout[24]=32'hFFFFFFCF;
ibustm[25]={ORI, 5'b00001, 5'b11001, 16'h8ABF};
abusin[25]=32'h00000000;
bbusin[25]=32'hFFFF8ABF;
dbusout[25]=32'hFFFF8ABF;
ibustm[26]={ORI, 5'b01101, 5'b01000, 16'h34FB};
abusin[26]=32'hFFFFFFFF;
bbusin[26]=32'h000034FB;
dbusout[26]=32'hFFFFFFFF;
ibustm[27]={XORI, 5'b01101, 5'b11011, 16'h0B31};
abusin[27]=32'hFFFFFFFF;
bbusin[27]=32'h00000B31;
dbusout[27]=32'hFFFFF4CE;
ibustm[28]={Rformat, 5'b00010, 5'b10011, 5'b01110, 5'b00000, ADD};
abusin[28]=32'hFFFF8CCB;
bbusin[28]=32'h00007334;
dbusout[28]=32'hFFFFFFFF;
ibustm[29]={Rformat, 5'b01000, 5'b01000, 5'b00100, 5'b00000, OR};
abusin[29]=32'hFFFFFFFF;
bbusin[29]=32'hFFFFFFFF;
dbusout[29]=32'hFFFFFFFF;
ibustm[30]={XORI, 5'b10101, 5'b01100, 16'h5555};
abusin[30]=32'hFFFFF98B;
bbusin[30]=32'h00005555;
dbusout[30]=32'hFFFFACDE;
ntests = 62;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
for (k=0; k<= 30; k=k+1) begin
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing input operands for instruction %d", k-3);
$display (" Your abus = %b", abus);
$display (" Correct abus = %b", abusin[k-3]);
$display (" Your bbus = %b", bbus);
$display (" Correct bbus = %b", bbusin[k-3]);
if ((abusin[k-3] !== abus) ||(bbusin[k-3] !== bbus)) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk=1;
#25
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing output operand for instruction %d", k-3);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-3]);
if (dbusout[k-3] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
ibus=ibustm[k];
$display (" ibus=%b %b %b %b %b for instruction %d", ibus[31:26], ibus[25:21], ibus[20:16], ibus[15:11], ibus[10:0], k);
clk = 0;
#25
error = error;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module cpu3_testbench(); |
reg [31:0] ibustm[0:30], ibus;
wire [31:0] abus;
wire [31:0] bbus;
wire [31:0] dbus;
reg clk;
reg [31:0] dontcare, abusin[0:30], bbusin[0:30], dbusout[0:30];
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
cpu3 dut(.ibus(ibus), .clk(clk), .abus(abus), .bbus(bbus), .dbus(dbus));
initial begin
ibustm[0]={Rformat, 5'b00000, 5'b00000, 5'b01101, 5'b00000, SUB};
abusin[0]=32'h00000000;
bbusin[0]=32'h00000000;
dbusout[0]=32'h00000000;
ibustm[1]={ADDI, 5'b00000, 5'b00001, 16'h0000};
abusin[1]=32'h00000000;
bbusin[1]=32'h00000000;
dbusout[1]=32'h00000000;
ibustm[2]={ADDI, 5'b00000, 5'b00000, 16'hFFFF};
abusin[2]=32'h00000000;
bbusin[2]=32'hFFFFFFFF;
dbusout[2]=32'hFFFFFFFF;
ibustm[3]={ADDI, 5'b00001, 5'b11110, 16'hAFC0};
abusin[3]=32'h00000000;
bbusin[3]=32'hFFFFAFC0;
dbusout[3]=32'hFFFFAFC0;
ibustm[4]={Rformat, 5'b00000, 5'b00000, 5'b00000, 5'b00000, SUB};
abusin[4]=32'h00000000;
bbusin[4]=32'h00000000;
dbusout[4]=32'h00000000;
ibustm[5]={ORI, 5'b00001, 5'b00011, 16'h7334};
abusin[5]=32'h00000000;
bbusin[5]=32'h00007334;
dbusout[5]=32'h00007334;
ibustm[6]={ORI, 5'b00001, 5'b10101, 16'hF98B};
abusin[6]=32'h00000000;
bbusin[6]=32'hFFFFF98B;
dbusout[6]=32'hFFFFF98B;
ibustm[7]={Rformat, 5'b00001, 5'b00011, 5'b10000, 5'b00000, XOR};
abusin[7]=32'h00000000;
bbusin[7]=32'h00007334;
dbusout[7]=32'h00007334;
ibustm[8]={SUBI, 5'b10101, 5'b11111, 16'h0030};
abusin[8]=32'hFFFFF98B;
bbusin[8]=32'h00000030;
dbusout[8]=32'hFFFFF95B;
ibustm[9]={ORI, 5'b00001, 5'b00101, 16'h8ABF};
abusin[9]=32'h00000000;
bbusin[9]=32'hFFFF8ABF;
dbusout[9]=32'hFFFF8ABF;
ibustm[10]={ORI, 5'b00001, 5'b01010, 16'h34FB};
abusin[10]=32'h00000000;
bbusin[10]=32'h000034FB;
dbusout[10]=32'h000034FB;
ibustm[11]={XORI, 5'b00001, 5'b10010, 16'h0B31};
abusin[11]=32'h00000000;
bbusin[11]=32'h00000B31;
dbusout[11]=32'h00000B31;
ibustm[12]={Rformat, 5'b10000, 5'b00011, 5'b11000, 5'b00000, ADD};
abusin[12]=32'h00007334;
bbusin[12]=32'h00007334;
dbusout[12]=32'h0000E668;
ibustm[13]={Rformat, 5'b01010, 5'b01010, 5'b00111, 5'b00000, OR};
abusin[13]=32'h000034FB;
bbusin[13]=32'h000034FB;
dbusout[13]=32'h000034FB;
ibustm[14]={XORI, 5'b10101, 5'b01100, 16'h00F0};
abusin[14]=32'hFFFFF98B;
bbusin[14]=32'h000000F0;
dbusout[14]=32'hFFFFF97B;
ibustm[15]={SUBI, 5'b11111, 5'b11100, 16'h0111};
abusin[15]=32'hFFFFF95B;
bbusin[15]=32'h00000111;
dbusout[15]=32'hFFFFF84A;
ibustm[16]={Rformat, 5'b00011, 5'b10101, 5'b10001, 5'b00000, ADD};
abusin[16]=32'h00007334;
bbusin[16]=32'hFFFFF98B;
dbusout[16]=32'h00006CBF;
ibustm[17]={ORI, 5'b00001, 5'b01111, 16'h328F};
abusin[17]=32'h00000000;
bbusin[17]=32'h0000328F;
dbusout[17]=32'h0000328F;
ibustm[18]={ADDI, 5'b01101, 5'b01101, 16'hFFFF};
abusin[18]=32'h00000000;
bbusin[18]=32'hFFFFFFFF;
dbusout[18]=32'hFFFFFFFF;
ibustm[19]={ADDI, 5'b00001, 5'b10111, 16'hAFC0};
abusin[19]=32'h00000000;
bbusin[19]=32'hFFFFAFC0;
dbusout[19]=32'hFFFFAFC0;
ibustm[20]={Rformat, 5'b00001, 5'b00001, 5'b10100, 5'b00000, SUB};
abusin[20]=32'h00000000;
bbusin[20]=32'h00000000;
dbusout[20]=32'h00000000;
ibustm[21]={ORI, 5'b00001, 5'b10011, 16'h7334};
abusin[21]=32'h00000000;
bbusin[21]=32'h00007334;
dbusout[21]=32'h00007334;
ibustm[22]={ORI, 5'b01101, 5'b01001, 16'hF98B};
abusin[22]=32'hFFFFFFFF;
bbusin[22]=32'hFFFFF98B;
dbusout[22]=32'hFFFFFFFF;
ibustm[23]={Rformat, 5'b01101, 5'b10011, 5'b00010, 5'b00000, XOR};
abusin[23]=32'hFFFFFFFF;
bbusin[23]=32'h00007334;
dbusout[23]=32'hFFFF8CCB;
ibustm[24]={SUBI, 5'b01001, 5'b11010, 16'h0030};
abusin[24]=32'hFFFFFFFF;
bbusin[24]=32'h00000030;
dbusout[24]=32'hFFFFFFCF;
ibustm[25]={ORI, 5'b00001, 5'b11001, 16'h8ABF};
abusin[25]=32'h00000000;
bbusin[25]=32'hFFFF8ABF;
dbusout[25]=32'hFFFF8ABF;
ibustm[26]={ORI, 5'b01101, 5'b01000, 16'h34FB};
abusin[26]=32'hFFFFFFFF;
bbusin[26]=32'h000034FB;
dbusout[26]=32'hFFFFFFFF;
ibustm[27]={XORI, 5'b01101, 5'b11011, 16'h0B31};
abusin[27]=32'hFFFFFFFF;
bbusin[27]=32'h00000B31;
dbusout[27]=32'hFFFFF4CE;
ibustm[28]={Rformat, 5'b00010, 5'b10011, 5'b01110, 5'b00000, ADD};
abusin[28]=32'hFFFF8CCB;
bbusin[28]=32'h00007334;
dbusout[28]=32'hFFFFFFFF;
ibustm[29]={Rformat, 5'b01000, 5'b01000, 5'b00100, 5'b00000, OR};
abusin[29]=32'hFFFFFFFF;
bbusin[29]=32'hFFFFFFFF;
dbusout[29]=32'hFFFFFFFF;
ibustm[30]={XORI, 5'b10101, 5'b01100, 16'h5555};
abusin[30]=32'hFFFFF98B;
bbusin[30]=32'h00005555;
dbusout[30]=32'hFFFFACDE;
ntests = 62;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clk=0;
for (k=0; k<= 30; k=k+1) begin
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing input operands for instruction %d", k-3);
$display (" Your abus = %b", abus);
$display (" Correct abus = %b", abusin[k-3]);
$display (" Your bbus = %b", bbus);
$display (" Correct bbus = %b", bbusin[k-3]);
if ((abusin[k-3] !== abus) ||(bbusin[k-3] !== bbus)) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk=1;
#25
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >= 3) begin
$display (" Testing output operand for instruction %d", k-3);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-3]);
if (dbusout[k-3] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
ibus=ibustm[k];
$display (" ibus=%b %b %b %b %b for instruction %d", ibus[31:26], ibus[25:21], ibus[20:16], ibus[15:11], ibus[10:0], k);
clk = 0;
#25
error = error;
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,123 | data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v | 93,595,154 | cpu4_testbench.v | v | 333 | 138 | [] | [] | [] | null | line:275: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:257: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:274: Unsupported: Ignoring delay on this delayed statement.\n #25\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:280: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:282: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:319: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_7/cpu4_testbench.v:321: Unsupported: Ignoring delay on this delayed statement.\n #20\n ^\n%Error: Exiting due to 1 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,886 | module | module cpu4_testbench();
reg [0:31] ibus;
reg [0:31] ibusin[0:23];
wire [0:31] daddrbus;
reg [0:31] daddrbusout[0:23];
wire [0:31] databus;
reg [0:31] databusk, databusin[0:23], databusout[0:23];
reg clk;
reg clkd;
reg [0:31] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter LW = 6'b011110;
parameter SW = 6'b011111;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
cpu4 dut(.clk(clk),.ibus(ibus),.daddrbus(daddrbus),.databus(databus));
initial begin
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "NOP";
iname[22] = "NOP";
iname[23] = "NOP";
dontcare = 32'hx;
ibusin[0]={ADDI, 5'b00000, 5'b10100, 16'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
ibusin[1]={ADDI, 5'b00000, 5'b10101, 16'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
ibusin[2]={ADDI, 5'b00000, 5'b10110, 16'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
ibusin[3]={LW, 5'b10100, 5'b11000, 16'h0000};
daddrbusout[3] = 32'hFFFFFFFF;
databusin[3] = 32'hCCCCCCCC;
databusout[3] = dontcare;
ibusin[4]={LW, 5'b10101, 5'b11001, 16'h0000};
daddrbusout[4] = 32'h00000001;
databusin[4] = 32'hAAAAAAAA;
databusout[4] = dontcare;
ibusin[5]={SW, 5'b10110, 5'b10100, 16'h1000};
daddrbusout[5] = 32'h00001002;
databusin[5] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32'hFFFFFFFF;
ibusin[6]={SW, 5'b00000, 5'b10101, 16'h0002};
daddrbusout[6] = 32'h00000002;
databusin[6] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32'h00000001;
ibusin[7]={Rformat, 5'b11000, 5'b11001, 5'b11010, 5'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
ibusin[8]={SUBI, 5'b11000, 5'b10001, 16'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
ibusin[9]={Rformat, 5'b11000, 5'b11001, 5'b11011, 5'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
ibusin[10]={ANDI, 5'b11000, 5'b10010, 16'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
ibusin[11]={Rformat, 5'b11000, 5'b00000, 5'b11100, 5'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
ibusin[12]={XORI, 5'b11000, 5'b10011, 16'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
ibusin[13]={Rformat, 5'b11000, 5'b11001, 5'b11101, 5'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
ibusin[14]={ORI, 5'b11000, 5'b10100, 16'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
ibusin[15]={Rformat, 5'b11000, 5'b11001, 5'b11110, 5'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
ibusin[16]={SW, 5'b11010, 5'b11010, 16'h0000};
daddrbusout[16] = 32'h77777776;
databusin[16] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32'h77777776;
ibusin[17]={SW, 5'b10001, 5'b11011, 16'h0000};
daddrbusout[17] = 32'hCCCC68AC;
databusin[17] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32'h22222222;
ibusin[18]={SW, 5'b10010, 5'b11100, 16'h1000};
daddrbusout[18] = 32'h00001000;
databusin[18] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32'h00000000;
ibusin[19]={SW, 5'b10011, 5'b11101, 16'h0000};
daddrbusout[19] = 32'hCCCCA8EC;
databusin[19] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32'h66666666;
ibusin[20]={SW, 5'b10100, 5'b11110, 16'h0000};
daddrbusout[20] = 32'hCCCCECEC;
databusin[20] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32'hEEEEEEEE;
ibusin[21] = 32'b00000000000000000000000000000000;
daddrbusout[21] = dontcare;
databusin[21] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
ibusin[22] = 32'b00000000000000000000000000000000;
daddrbusout[22] = dontcare;
databusin[22] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
ibusin[23] = 32'b00000000000000000000000000000000;
daddrbusout[23] = dontcare;
databusin[23] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
ntests = 16;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 32'bz : databusk;
initial begin
error = 0;
clkd =0;
clk=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 32'bz;
#25
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 23; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clkd=1;
#20
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >=3)
databusk = databusin[k-3];
ibus=ibusin[k];
$display (" ibus=%b %b %b %b %b for instruction %d: %s", ibus[0:5], ibus[6:10], ibus[11:15], ibus[16:20], ibus[21:31], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clkd = 0;
#20
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module cpu4_testbench(); |
reg [0:31] ibus;
reg [0:31] ibusin[0:23];
wire [0:31] daddrbus;
reg [0:31] daddrbusout[0:23];
wire [0:31] databus;
reg [0:31] databusk, databusin[0:23], databusout[0:23];
reg clk;
reg clkd;
reg [0:31] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter LW = 6'b011110;
parameter SW = 6'b011111;
parameter Rformat = 6'b000000;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
cpu4 dut(.clk(clk),.ibus(ibus),.daddrbus(daddrbus),.databus(databus));
initial begin
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "NOP";
iname[22] = "NOP";
iname[23] = "NOP";
dontcare = 32'hx;
ibusin[0]={ADDI, 5'b00000, 5'b10100, 16'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
ibusin[1]={ADDI, 5'b00000, 5'b10101, 16'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
ibusin[2]={ADDI, 5'b00000, 5'b10110, 16'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
ibusin[3]={LW, 5'b10100, 5'b11000, 16'h0000};
daddrbusout[3] = 32'hFFFFFFFF;
databusin[3] = 32'hCCCCCCCC;
databusout[3] = dontcare;
ibusin[4]={LW, 5'b10101, 5'b11001, 16'h0000};
daddrbusout[4] = 32'h00000001;
databusin[4] = 32'hAAAAAAAA;
databusout[4] = dontcare;
ibusin[5]={SW, 5'b10110, 5'b10100, 16'h1000};
daddrbusout[5] = 32'h00001002;
databusin[5] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32'hFFFFFFFF;
ibusin[6]={SW, 5'b00000, 5'b10101, 16'h0002};
daddrbusout[6] = 32'h00000002;
databusin[6] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32'h00000001;
ibusin[7]={Rformat, 5'b11000, 5'b11001, 5'b11010, 5'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
ibusin[8]={SUBI, 5'b11000, 5'b10001, 16'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
ibusin[9]={Rformat, 5'b11000, 5'b11001, 5'b11011, 5'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
ibusin[10]={ANDI, 5'b11000, 5'b10010, 16'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
ibusin[11]={Rformat, 5'b11000, 5'b00000, 5'b11100, 5'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
ibusin[12]={XORI, 5'b11000, 5'b10011, 16'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
ibusin[13]={Rformat, 5'b11000, 5'b11001, 5'b11101, 5'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
ibusin[14]={ORI, 5'b11000, 5'b10100, 16'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
ibusin[15]={Rformat, 5'b11000, 5'b11001, 5'b11110, 5'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
ibusin[16]={SW, 5'b11010, 5'b11010, 16'h0000};
daddrbusout[16] = 32'h77777776;
databusin[16] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32'h77777776;
ibusin[17]={SW, 5'b10001, 5'b11011, 16'h0000};
daddrbusout[17] = 32'hCCCC68AC;
databusin[17] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32'h22222222;
ibusin[18]={SW, 5'b10010, 5'b11100, 16'h1000};
daddrbusout[18] = 32'h00001000;
databusin[18] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32'h00000000;
ibusin[19]={SW, 5'b10011, 5'b11101, 16'h0000};
daddrbusout[19] = 32'hCCCCA8EC;
databusin[19] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32'h66666666;
ibusin[20]={SW, 5'b10100, 5'b11110, 16'h0000};
daddrbusout[20] = 32'hCCCCECEC;
databusin[20] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32'hEEEEEEEE;
ibusin[21] = 32'b00000000000000000000000000000000;
daddrbusout[21] = dontcare;
databusin[21] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
ibusin[22] = 32'b00000000000000000000000000000000;
daddrbusout[22] = dontcare;
databusin[22] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
ibusin[23] = 32'b00000000000000000000000000000000;
daddrbusout[23] = dontcare;
databusin[23] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
ntests = 16;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 32'bz : databusk;
initial begin
error = 0;
clkd =0;
clk=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 32'bz;
#25
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 23; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clkd=1;
#20
$display ("Time=%t\n clk=%b", $realtime, clk);
if (k >=3)
databusk = databusin[k-3];
ibus=ibusin[k];
$display (" ibus=%b %b %b %b %b for instruction %d: %s", ibus[0:5], ibus[6:10], ibus[11:15], ibus[16:20], ibus[21:31], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clkd = 0;
#20
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,124 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module cpu5(ibus,clk,daddrbus,databus,reset,iaddrbus);
input clk;
input reset;
output [31:0] iaddrbus;
wire [31:0] iaddrbusWire1;
wire [31:0] iaddrbusWire2;
wire [31:0] iaddrbusWire4;
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
wire ZBit;
wire [31:0] potentialSLEBit;
wire [31:0] potentialSLTBit;
wire [31:0] actualSLBit;
wire ALUCoutWire;
reg [1:0] branchControlBit;
wire [1:0] branchControlBitWire1;
wire [1:0] branchControlBitWire2;
wire [1:0] branchControlBitWire3;
wire [31:0] PCWire1;
wire [31:0] branchCalcWire1;
wire [31:0] branchCalcWire2;
output [31:0] daddrbus;
inout [31:0] databus;
wire [5:0] opCode;
wire [5:0] funktion;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [5:0] rs;
wire [31:0] BselectWire;
wire [5:0] rt;
reg immBit1;
wire immBit2;
reg [1:0] lwSwFlag1;
wire [1:0] lwSwFlag2;
wire [1:0] lwSwFlag3;
wire [1:0] lwSwFlag4;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
wire [31:0] DselectWire3_5;
wire [31:0] DselectWire4;
wire [31:0] abusWire1;
wire [31:0] abusWire2;
wire [31:0] bbusWire1;
wire [31:0] bbusWire2;
wire [31:0] bbusWire3;
wire [31:0] bbusWire3_5;
wire [31:0] bbusWire4;
wire [31:0] dbusWire1;
wire [31:0] dbusWire1_5;
wire [31:0] dbusWire2;
wire [31:0] dbusWire3;
wire [31:0] mux3Out;
wire [31:0] mux2Out;
wire mux4Controller;
wire [31:0] immWire1;
wire [31:0] immWire2;
wire [31:0] branchWire;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
branchControlBit = 2'b0;
setControlBits = 2'b00;
end
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
assign iaddrbus = mux4Controller? branchCalcWire2 : iaddrbusWire2;
assign iaddrbusWire4 = iaddrbusWire2;
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
assign branchWire = ibusWire[15]? {14'b11111111111111, ibusWire[15:0], 2'b00} : {14'b00000000000000, ibusWire[15:0], 2'b00};
always @(ibusWire) begin
immBit1 = 1;
CinWire1 = 0;
branchControlBit = 0;
setControlBits = 0;
lwSwFlag1 = 2'b00;
case (opCode)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b001111: begin
SWire1 = 3'b110;
end
6'b001100: begin
SWire1 = 3'b100;
end
6'b011110: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
6'b011111: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
6'b110000: begin
SWire1 = 3'b010;
branchControlBit = 2'b01;
end
6'b110001: begin
SWire1 = 3'b010;
branchControlBit = 2'b10;
end
6'b000000: begin
immBit1= 0;
case (funktion)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b000111: begin
SWire1 = 3'b110;
end
6'b000100: begin
SWire1 = 3'b100;
end
6'b110110: begin
setControlBits = 2'b01;
SWire1 = 3'b011;
end
6'b110111: begin
setControlBits = 2'b10;
SWire1 = 3'b011;
end
endcase
end
endcase
end
assign AselectWire = 1 << rs;
assign BselectWire = 1 << rt;
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
assign mux4Controller = ((!clk) && ((branchControlBit==2'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2'b10) && (abusWire1!=bbusWire1)))? 1: 0;
assign branchCalcWire1 = immWire1 << 2;
assign branchCalcWire2 = branchWire + PCWire1;
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1));
assign mux2Out = immBit2? immWire2: bbusWire2;
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));
assign ZBit = (dbusWire1==0)? 1:0;
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 32'h00000001:32'h00000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 32'h00000001:32'h00000000;
assign actualSLBit = (setControlBitsWire1 == 2'b01)? potentialSLTBit: potentialSLEBit;
assign dbusWire1_5 = (setControlBitsWire1 > 2'b00)? actualSLBit:dbusWire1;
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_5),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2));
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 32'hzzzzzzzz;
assign daddrbus = dbusWire2;
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),
.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),.branchControlBitWire3(branchControlBitWire3));
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = ((lwSwFlag4 == 2'b10) ||(branchControlBitWire3 > 2'b00))? 32'h00000001: DselectWire3_5;
endmodule | module cpu5(ibus,clk,daddrbus,databus,reset,iaddrbus); |
input clk;
input reset;
output [31:0] iaddrbus;
wire [31:0] iaddrbusWire1;
wire [31:0] iaddrbusWire2;
wire [31:0] iaddrbusWire4;
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
wire ZBit;
wire [31:0] potentialSLEBit;
wire [31:0] potentialSLTBit;
wire [31:0] actualSLBit;
wire ALUCoutWire;
reg [1:0] branchControlBit;
wire [1:0] branchControlBitWire1;
wire [1:0] branchControlBitWire2;
wire [1:0] branchControlBitWire3;
wire [31:0] PCWire1;
wire [31:0] branchCalcWire1;
wire [31:0] branchCalcWire2;
output [31:0] daddrbus;
inout [31:0] databus;
wire [5:0] opCode;
wire [5:0] funktion;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [5:0] rs;
wire [31:0] BselectWire;
wire [5:0] rt;
reg immBit1;
wire immBit2;
reg [1:0] lwSwFlag1;
wire [1:0] lwSwFlag2;
wire [1:0] lwSwFlag3;
wire [1:0] lwSwFlag4;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
wire [31:0] DselectWire3_5;
wire [31:0] DselectWire4;
wire [31:0] abusWire1;
wire [31:0] abusWire2;
wire [31:0] bbusWire1;
wire [31:0] bbusWire2;
wire [31:0] bbusWire3;
wire [31:0] bbusWire3_5;
wire [31:0] bbusWire4;
wire [31:0] dbusWire1;
wire [31:0] dbusWire1_5;
wire [31:0] dbusWire2;
wire [31:0] dbusWire3;
wire [31:0] mux3Out;
wire [31:0] mux2Out;
wire mux4Controller;
wire [31:0] immWire1;
wire [31:0] immWire2;
wire [31:0] branchWire;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
branchControlBit = 2'b0;
setControlBits = 2'b00;
end
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
assign iaddrbus = mux4Controller? branchCalcWire2 : iaddrbusWire2;
assign iaddrbusWire4 = iaddrbusWire2;
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
assign opCode = ibusWire[31:26];
assign rs = ibusWire[25:21];
assign rt = ibusWire[20:16];
assign rd = ibusWire[15:11];
assign funktion = ibusWire[5:0];
assign immWire1 = ibusWire[15]? {16'b1111111111111111,ibusWire[15:0]} : {16'b0000000000000000,ibusWire[15:0]};
assign branchWire = ibusWire[15]? {14'b11111111111111, ibusWire[15:0], 2'b00} : {14'b00000000000000, ibusWire[15:0], 2'b00};
always @(ibusWire) begin
immBit1 = 1;
CinWire1 = 0;
branchControlBit = 0;
setControlBits = 0;
lwSwFlag1 = 2'b00;
case (opCode)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b001111: begin
SWire1 = 3'b110;
end
6'b001100: begin
SWire1 = 3'b100;
end
6'b011110: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
6'b011111: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
6'b110000: begin
SWire1 = 3'b010;
branchControlBit = 2'b01;
end
6'b110001: begin
SWire1 = 3'b010;
branchControlBit = 2'b10;
end
6'b000000: begin
immBit1= 0;
case (funktion)
6'b000011: begin
SWire1 = 3'b010;
end
6'b000010: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
6'b000001: begin
SWire1 = 3'b000;
end
6'b000111: begin
SWire1 = 3'b110;
end
6'b000100: begin
SWire1 = 3'b100;
end
6'b110110: begin
setControlBits = 2'b01;
SWire1 = 3'b011;
end
6'b110111: begin
setControlBits = 2'b10;
SWire1 = 3'b011;
end
endcase
end
endcase
end
assign AselectWire = 1 << rs;
assign BselectWire = 1 << rt;
assign DselectWire1 = immBit1? 1<<rt : 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire),.Bselect(BselectWire),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
assign mux4Controller = ((!clk) && ((branchControlBit==2'b01) && (abusWire1 == bbusWire1)) || ((branchControlBit==2'b10) && (abusWire1!=bbusWire1)))? 1: 0;
assign branchCalcWire1 = immWire1 << 2;
assign branchCalcWire2 = branchWire + PCWire1;
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.immWire1(immWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.immWire2(immWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1));
assign mux2Out = immBit2? immWire2: bbusWire2;
alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));
assign ZBit = (dbusWire1==0)? 1:0;
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 32'h00000001:32'h00000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 32'h00000001:32'h00000000;
assign actualSLBit = (setControlBitsWire1 == 2'b01)? potentialSLTBit: potentialSLEBit;
assign dbusWire1_5 = (setControlBitsWire1 > 2'b00)? actualSLBit:dbusWire1;
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_5),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2));
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 32'hzzzzzzzz;
assign daddrbus = dbusWire2;
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),.DselectWire4(DselectWire3_5),
.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),.branchControlBitWire3(branchControlBitWire3));
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = ((lwSwFlag4 == 2'b10) ||(branchControlBitWire3 > 2'b00))? 32'h00000001: DselectWire3_5;
endmodule | 0 |
141,125 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [31:0] iaddrbusWire1;
output [31:0] iaddrbusOut;
reg [31:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule | module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset); |
input clk, reset;
input [31:0] iaddrbusWire1;
output [31:0] iaddrbusOut;
reg [31:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule | 0 |
141,126 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus, PCIn;
input clk;
output [31:0] ibusWire, PCOut;
reg [31:0] ibusWire, PCOut;
always @(posedge clk) begin
ibusWire = ibus;
PCOut = PCIn;
end
endmodule | module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut); |
input [31:0] ibus, PCIn;
input clk;
output [31:0] ibusWire, PCOut;
reg [31:0] ibusWire, PCOut;
always @(posedge clk) begin
ibusWire = ibus;
PCOut = PCIn;
end
endmodule | 0 |
141,127 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1);
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [1:0] branchControlBit;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [1:0] branchControlBitWire1;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [1:0] branchControlBitWire1;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
end
endmodule | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, immWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,immWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1); |
input clk, CinWire1,immBit1;
input [31:0] abusWire1, bbusWire1, DselectWire1, immWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [1:0] branchControlBit;
output CinWire2,immBit2;
output [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [1:0] branchControlBitWire1;
reg CinWire2,immBit2;
reg [31:0] abusWire2, bbusWire2, DselectWire2, immWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [1:0] branchControlBitWire1;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
immWire2 = immWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
end
endmodule | 0 |
141,128 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,branchControlBitWire2);
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
input [1:0] branchControlBitWire1;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
output [1:0] branchControlBitWire2;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
reg [1:0] branchControlBitWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
end
endmodule | module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,branchControlBitWire2); |
input clk;
input [31:0] dbusWire1, DselectWire2, bbusWire2;
input [1:0] lwSwFlag2;
input [1:0] branchControlBitWire1;
output [31:0] dbusWire2, DselectWire3, bbusWire3;
output [1:0] lwSwFlag3;
output [1:0] branchControlBitWire2;
reg [31:0] dbusWire2, DselectWire3, bbusWire3;
reg [1:0] lwSwFlag3;
reg [1:0] branchControlBitWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
end
endmodule | 0 |
141,129 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,branchControlBitWire3);
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
input [1:0] branchControlBitWire2;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
output [1:0] branchControlBitWire3;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
reg [1:0] branchControlBitWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
end
endmodule | module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,branchControlBitWire3); |
input clk;
input [31:0] dbusWire2, DselectWire3, bbusWire3;
input [1:0] lwSwFlag3;
input [1:0] branchControlBitWire2;
output [31:0] dbusWire3, DselectWire4, bbusWire4;
output [1:0] lwSwFlag4;
output [1:0] branchControlBitWire3;
reg [31:0] dbusWire3, DselectWire4, bbusWire4;
reg [1:0] lwSwFlag4;
reg [1:0] branchControlBitWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
end
endmodule | 0 |
141,130 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
);
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [31:0] dbus,
output [31:0] abus,
output [31:0] bbus,
input clk
); |
assign abus = Aselect[0] ? 32'b0 : 32'bz;
assign bbus = Bselect[0] ? 32'b0 : 32'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[31:1]),
.Bselect(Bselect[31:1]),
.Aselect(Aselect[31:1]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,131 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [31:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [31:0] abus;
output [31:0] bbus;
wire wireclk;
reg [31:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 32'h00000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 32'hzzzzzzzz;
assign bbus = Bselect? data : 32'hzzzzzzzz;
endmodule | 0 |
141,132 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module alu32 (d, Cout, V, a, b, Cin, S);
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | module alu32 (d, Cout, V, a, b, Cin, S); |
output[31:0] d;
output Cout, V;
input [31:0] a, b;
input Cin;
input [2:0] S;
wire [31:0] c, g, p;
wire gout, pout;
alu_cell mycell[31:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac5 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[31]),
.Cin(Cin)
);
endmodule | 0 |
141,133 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,134 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,135 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,136 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,137 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module lac3 (c, gout, pout, Cin, g, p);
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac3 (c, gout, pout, Cin, g, p); |
output [7:0] c;
output gout, pout;
input Cin;
input [7:0] g, p;
wire [1:0] cint, gint, pint;
lac2 leaf0(
.c(c[3:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[3:0]),
.p(p[3:0])
);
lac2 leaf1(
.c(c[7:4]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[7:4]),
.p(p[7:4])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,138 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module lac4 (c, gout, pout, Cin, g, p);
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac4 (c, gout, pout, Cin, g, p); |
output [15:0] c;
output gout, pout;
input Cin;
input [15:0] g, p;
wire [1:0] cint, gint, pint;
lac3 leaf0(
.c(c[7:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[7:0]),
.p(p[7:0])
);
lac3 leaf1(
.c(c[15:8]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[15:8]),
.p(p[15:8])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,139 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v | 93,595,154 | cpu5.v | v | 703 | 186 | [] | [] | [] | null | line:257: before: "," | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:265: Cell has missing pin: \'V\'\n alu32 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux2Out),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire));\n ^~~~~~~~~~~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:130: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rs = ibusWire[25:21];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:131: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rt = ibusWire[20:16];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p1/cpu5.v:132: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance cpu5\n assign rd = ibusWire[15:11];\n ^\n%Error: Exiting due to 4 warning(s)\n' | 310,888 | module | module lac5 (c, gout, pout, Cin, g, p);
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac5 (c, gout, pout, Cin, g, p); |
output [31:0] c;
output gout, pout;
input Cin;
input [31:0] g, p;
wire [1:0] cint, gint, pint;
lac4 leaf0(
.c(c[15:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[15:0]),
.p(p[15:0])
);
lac4 leaf1(
.c(c[31:16]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[31:16]),
.p(p[31:16])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
141,140 | data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v | 93,595,154 | cpu5_testbench.v | v | 502 | 164 | [] | [] | [] | null | line:429: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:395: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:415: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:419: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:424: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:428: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:434: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:436: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:487: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p1/cpu5_testbench.v:489: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,889 | module | module cpu5_testbench();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:35];
wire [31:0] iaddrbus, daddrbus;
reg [31:0] iaddrbusout[0:35], daddrbusout[0:35];
wire [31:0] databus;
reg [31:0] databusk, databusin[0:35], databusout[0:35];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:35];
integer error, k, ntests;
parameter Rformat = 6'b000000;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter LW = 6'b011110;
parameter SW = 6'b011111;
parameter BEQ = 6'b110000;
parameter BNE = 6'b110001;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SLT = 6'b110110;
parameter SLE = 6'b110111;
cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "SLT R1, R0, R21";
iname[22] = "ADDI R5, R0, #1";
iname[23] = "ADDI R6, R0, #1";
iname[24] = "BNE R0, R1, #10";
iname[25] = "ADDI R8, R0, #1";
iname[26] = "SLE R2, R0, R0";
iname[27] = "NOP";
iname[28] = "NOP";
iname[29] = "BEQ R0, R2, #25";
iname[30] = "NOP";
iname[31] = "BEQ R2, R2, #10";
iname[32] = "ADDI R20, R0, #1";
iname[33] = "NOP";
iname[34] = "NOP";
iname[35] = "NOP";
dontcare = 32'hx;
iaddrbusout[0] = 32'h00000000;
instrbusin[0]={ADDI, 5'b00000, 5'b10100, 16'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
iaddrbusout[1] = 32'h00000004;
instrbusin[1]={ADDI, 5'b00000, 5'b10101, 16'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
iaddrbusout[2] = 32'h00000008;
instrbusin[2]={ADDI, 5'b00000, 5'b10110, 16'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
iaddrbusout[3] = 32'h0000000C;
instrbusin[3]={LW, 5'b10100, 5'b11000, 16'h0000};
daddrbusout[3] = 32'hFFFFFFFF;
databusin[3] = 32'hCCCCCCCC;
databusout[3] = dontcare;
iaddrbusout[4] = 32'h00000010;
instrbusin[4]={LW, 5'b10101, 5'b11001, 16'h0000};
daddrbusout[4] = 32'h00000001;
databusin[4] = 32'hAAAAAAAA;
databusout[4] = dontcare;
iaddrbusout[5] = 32'h00000014;
instrbusin[5]={SW, 5'b10110, 5'b10100, 16'h1000};
daddrbusout[5] = 32'h00001002;
databusin[5] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32'hFFFFFFFF;
iaddrbusout[6] = 32'h00000018;
instrbusin[6]={SW, 5'b00000, 5'b10101, 16'h0002};
daddrbusout[6] = 32'h00000002;
databusin[6] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32'h00000001;
iaddrbusout[7] = 32'h0000001C;
instrbusin[7]={Rformat, 5'b11000, 5'b11001, 5'b11010, 5'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
iaddrbusout[8] = 32'h00000020;
instrbusin[8]={SUBI, 5'b11000, 5'b10001, 16'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
iaddrbusout[9] = 32'h00000024;
instrbusin[9]={Rformat, 5'b11000, 5'b11001, 5'b11011, 5'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
iaddrbusout[10] = 32'h00000028;
instrbusin[10]={ANDI, 5'b11000, 5'b10010, 16'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
iaddrbusout[11] = 32'h0000002C;
instrbusin[11]={Rformat, 5'b11000, 5'b00000, 5'b11100, 5'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
iaddrbusout[12] = 32'h00000030;
instrbusin[12]={XORI, 5'b11000, 5'b10011, 16'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
iaddrbusout[13] = 32'h00000034;
instrbusin[13]={Rformat, 5'b11000, 5'b11001, 5'b11101, 5'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
iaddrbusout[14] = 32'h00000038;
instrbusin[14]={ORI, 5'b11000, 5'b10100, 16'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
iaddrbusout[15] = 32'h0000003C;
instrbusin[15]={Rformat, 5'b11000, 5'b11001, 5'b11110, 5'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
iaddrbusout[16] = 32'h00000040;
instrbusin[16]={SW, 5'b11010, 5'b11010, 16'h0000};
daddrbusout[16] = 32'h77777776;
databusin[16] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32'h77777776;
iaddrbusout[17] = 32'h00000044;
instrbusin[17]={SW, 5'b10001, 5'b11011, 16'h0000};
daddrbusout[17] = 32'hCCCC68AC;
databusin[17] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32'h22222222;
iaddrbusout[18] = 32'h00000048;
instrbusin[18]={SW, 5'b10010, 5'b11100, 16'h1000};
daddrbusout[18] = 32'h00001000;
databusin[18] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32'h00000000;
iaddrbusout[19] = 32'h0000004C;
instrbusin[19]={SW, 5'b10011, 5'b11101, 16'h0000};
daddrbusout[19] = 32'hCCCCA8EC;
databusin[19] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32'h66666666;
iaddrbusout[20] = 32'h00000050;
instrbusin[20]={SW, 5'b10100, 5'b11110, 16'h0000};
daddrbusout[20] = 32'hCCCCECEC;
databusin[20] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32'hEEEEEEEE;
iaddrbusout[21] = 32'h00000054;
instrbusin[21]={Rformat, 5'b00000, 5'b10101, 5'b00001, 5'b00000, SLT};
daddrbusout[21] = dontcare;
databusin[21] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
iaddrbusout[22] = 32'h00000058;
instrbusin[22]={ADDI, 5'b00000, 5'b00101, 16'h0001};
daddrbusout[22] = dontcare;
databusin[22] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
iaddrbusout[23] = 32'h0000005C;
instrbusin[23]={ADDI, 5'b00000, 5'b00110, 16'h0001};
daddrbusout[23] = dontcare;
databusin[23] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
iaddrbusout[24] = 32'h00000060;
instrbusin[24]={BNE, 5'b00001, 5'b00000, 16'h000A};
daddrbusout[24] = dontcare;
databusin[24] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[24] = dontcare;
iaddrbusout[25] = 32'h00000064;
instrbusin[25]={ADDI, 5'b00000, 5'b01000, 16'h0001};
daddrbusout[25] = dontcare;
databusin[25] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[25] = dontcare;
iaddrbusout[26] = 32'h0000008C;
instrbusin[26]={Rformat, 5'b00000, 5'b00000, 5'b00010, 5'b00000, SLE};
daddrbusout[26] = dontcare;
databusin[26] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[26] = dontcare;
iaddrbusout[27] = 32'h00000090;
instrbusin[27] = 32'b00000000000000000000000000000000;
daddrbusout[27] = dontcare;
databusin[27] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[27] = dontcare;
iaddrbusout[28] = 32'h00000094;
instrbusin[28] = 32'b00000000000000000000000000000000;
daddrbusout[28] = dontcare;
databusin[28] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[28] = dontcare;
iaddrbusout[29] = 32'h00000098;
instrbusin[29]={BEQ, 5'b00010, 5'b00000, 16'h0019};
daddrbusout[29] = dontcare;
databusin[29] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[29] = dontcare;
iaddrbusout[30] = 32'h0000009C;
instrbusin[30] = 32'b00000000000000000000000000000000;
daddrbusout[30] = dontcare;
databusin[30] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[30] = dontcare;
iaddrbusout[31] = 32'h000000A0;
instrbusin[31]={BEQ, 5'b00010, 5'b00010, 16'h000A};
daddrbusout[31] = dontcare;
databusin[31] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[31] = dontcare;
iaddrbusout[32] = 32'h000000A4;
instrbusin[32]={ADDI, 5'b00000, 5'b10100, 16'h0001};
daddrbusout[32] = dontcare;
databusin[32] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[32] = dontcare;
iaddrbusout[33] = 32'h000000CC;
instrbusin[33] = 32'b00000000000000000000000000000000;
daddrbusout[33] = dontcare;
databusin[33] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[33] = dontcare;
iaddrbusout[34] = 32'h000000D0;
instrbusin[34] = 32'b00000000000000000000000000000000;
daddrbusout[34] = dontcare;
databusin[34] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[34] = dontcare;
iaddrbusout[35] = 32'h000000D4;
instrbusin[35] = 32'b00000000000000000000000000000000;
daddrbusout[35] = dontcare;
databusin[35] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[35] = dontcare;
ntests = 51;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 32'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 32'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 35; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module cpu5_testbench(); |
reg [31:0] instrbus;
reg [31:0] instrbusin[0:35];
wire [31:0] iaddrbus, daddrbus;
reg [31:0] iaddrbusout[0:35], daddrbusout[0:35];
wire [31:0] databus;
reg [31:0] databusk, databusin[0:35], databusout[0:35];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:35];
integer error, k, ntests;
parameter Rformat = 6'b000000;
parameter ADDI = 6'b000011;
parameter SUBI = 6'b000010;
parameter XORI = 6'b000001;
parameter ANDI = 6'b001111;
parameter ORI = 6'b001100;
parameter LW = 6'b011110;
parameter SW = 6'b011111;
parameter BEQ = 6'b110000;
parameter BNE = 6'b110001;
parameter ADD = 6'b000011;
parameter SUB = 6'b000010;
parameter XOR = 6'b000001;
parameter AND = 6'b000111;
parameter OR = 6'b000100;
parameter SLT = 6'b110110;
parameter SLE = 6'b110111;
cpu5 dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
iname[0] = "ADDI R20, R0, #-1";
iname[1] = "ADDI R21, R0, #1";
iname[2] = "ADDI R22, R0, #2";
iname[3] = "LW R24, 0(R20)";
iname[4] = "LW R25, 0(R21)";
iname[5] = "SW 1000(R22), R20";
iname[6] = "SW 2(R0), R21";
iname[7] = "ADD R26, R24, R25";
iname[8] = "SUBI R17, R24, 6420";
iname[9] = "SUB R27, R24, R25";
iname[10] = "ANDI R18, R24, #0";
iname[11] = "AND R28, R24, R0";
iname[12] = "XORI R19, R24, 6420";
iname[13] = "XOR R29, R24, R25";
iname[14] = "ORI R20, R24, 6420";
iname[15] = "OR R30, R24, R25";
iname[16] = "SW 0(R26), R26";
iname[17] = "SW 0(R17), R27";
iname[18] = "SW 1000(R18), R28";
iname[19] = "SW 0(R19), R29";
iname[20] = "SW 0(R20), R30";
iname[21] = "SLT R1, R0, R21";
iname[22] = "ADDI R5, R0, #1";
iname[23] = "ADDI R6, R0, #1";
iname[24] = "BNE R0, R1, #10";
iname[25] = "ADDI R8, R0, #1";
iname[26] = "SLE R2, R0, R0";
iname[27] = "NOP";
iname[28] = "NOP";
iname[29] = "BEQ R0, R2, #25";
iname[30] = "NOP";
iname[31] = "BEQ R2, R2, #10";
iname[32] = "ADDI R20, R0, #1";
iname[33] = "NOP";
iname[34] = "NOP";
iname[35] = "NOP";
dontcare = 32'hx;
iaddrbusout[0] = 32'h00000000;
instrbusin[0]={ADDI, 5'b00000, 5'b10100, 16'hFFFF};
daddrbusout[0] = dontcare;
databusin[0] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[0] = dontcare;
iaddrbusout[1] = 32'h00000004;
instrbusin[1]={ADDI, 5'b00000, 5'b10101, 16'h0001};
daddrbusout[1] = dontcare;
databusin[1] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[1] = dontcare;
iaddrbusout[2] = 32'h00000008;
instrbusin[2]={ADDI, 5'b00000, 5'b10110, 16'h0002};
daddrbusout[2] = dontcare;
databusin[2] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[2] = dontcare;
iaddrbusout[3] = 32'h0000000C;
instrbusin[3]={LW, 5'b10100, 5'b11000, 16'h0000};
daddrbusout[3] = 32'hFFFFFFFF;
databusin[3] = 32'hCCCCCCCC;
databusout[3] = dontcare;
iaddrbusout[4] = 32'h00000010;
instrbusin[4]={LW, 5'b10101, 5'b11001, 16'h0000};
daddrbusout[4] = 32'h00000001;
databusin[4] = 32'hAAAAAAAA;
databusout[4] = dontcare;
iaddrbusout[5] = 32'h00000014;
instrbusin[5]={SW, 5'b10110, 5'b10100, 16'h1000};
daddrbusout[5] = 32'h00001002;
databusin[5] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[5] = 32'hFFFFFFFF;
iaddrbusout[6] = 32'h00000018;
instrbusin[6]={SW, 5'b00000, 5'b10101, 16'h0002};
daddrbusout[6] = 32'h00000002;
databusin[6] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[6] = 32'h00000001;
iaddrbusout[7] = 32'h0000001C;
instrbusin[7]={Rformat, 5'b11000, 5'b11001, 5'b11010, 5'b00000, ADD};
daddrbusout[7] = dontcare;
databusin[7] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[7] = dontcare;
iaddrbusout[8] = 32'h00000020;
instrbusin[8]={SUBI, 5'b11000, 5'b10001, 16'h6420};
daddrbusout[8] = dontcare;
databusin[8] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[8] = dontcare;
iaddrbusout[9] = 32'h00000024;
instrbusin[9]={Rformat, 5'b11000, 5'b11001, 5'b11011, 5'b00000, SUB};
daddrbusout[9] = dontcare;
databusin[9] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[9] = dontcare;
iaddrbusout[10] = 32'h00000028;
instrbusin[10]={ANDI, 5'b11000, 5'b10010, 16'h0000};
daddrbusout[10] = dontcare;
databusin[10] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[10] = dontcare;
iaddrbusout[11] = 32'h0000002C;
instrbusin[11]={Rformat, 5'b11000, 5'b00000, 5'b11100, 5'b00000, AND};
daddrbusout[11] = dontcare;
databusin[11] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[11] = dontcare;
iaddrbusout[12] = 32'h00000030;
instrbusin[12]={XORI, 5'b11000, 5'b10011, 16'h6420};
daddrbusout[12] = dontcare;
databusin[12] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[12] = dontcare;
iaddrbusout[13] = 32'h00000034;
instrbusin[13]={Rformat, 5'b11000, 5'b11001, 5'b11101, 5'b00000, XOR};
daddrbusout[13] = dontcare;
databusin[13] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[13] = dontcare;
iaddrbusout[14] = 32'h00000038;
instrbusin[14]={ORI, 5'b11000, 5'b10100, 16'h6420};
daddrbusout[14] = dontcare;
databusin[14] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[14] = dontcare;
iaddrbusout[15] = 32'h0000003C;
instrbusin[15]={Rformat, 5'b11000, 5'b11001, 5'b11110, 5'b00000, OR};
daddrbusout[15] = dontcare;
databusin[15] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[15] = dontcare;
iaddrbusout[16] = 32'h00000040;
instrbusin[16]={SW, 5'b11010, 5'b11010, 16'h0000};
daddrbusout[16] = 32'h77777776;
databusin[16] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[16] = 32'h77777776;
iaddrbusout[17] = 32'h00000044;
instrbusin[17]={SW, 5'b10001, 5'b11011, 16'h0000};
daddrbusout[17] = 32'hCCCC68AC;
databusin[17] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[17] = 32'h22222222;
iaddrbusout[18] = 32'h00000048;
instrbusin[18]={SW, 5'b10010, 5'b11100, 16'h1000};
daddrbusout[18] = 32'h00001000;
databusin[18] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[18] = 32'h00000000;
iaddrbusout[19] = 32'h0000004C;
instrbusin[19]={SW, 5'b10011, 5'b11101, 16'h0000};
daddrbusout[19] = 32'hCCCCA8EC;
databusin[19] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[19] = 32'h66666666;
iaddrbusout[20] = 32'h00000050;
instrbusin[20]={SW, 5'b10100, 5'b11110, 16'h0000};
daddrbusout[20] = 32'hCCCCECEC;
databusin[20] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[20] = 32'hEEEEEEEE;
iaddrbusout[21] = 32'h00000054;
instrbusin[21]={Rformat, 5'b00000, 5'b10101, 5'b00001, 5'b00000, SLT};
daddrbusout[21] = dontcare;
databusin[21] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[21] = dontcare;
iaddrbusout[22] = 32'h00000058;
instrbusin[22]={ADDI, 5'b00000, 5'b00101, 16'h0001};
daddrbusout[22] = dontcare;
databusin[22] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[22] = dontcare;
iaddrbusout[23] = 32'h0000005C;
instrbusin[23]={ADDI, 5'b00000, 5'b00110, 16'h0001};
daddrbusout[23] = dontcare;
databusin[23] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[23] = dontcare;
iaddrbusout[24] = 32'h00000060;
instrbusin[24]={BNE, 5'b00001, 5'b00000, 16'h000A};
daddrbusout[24] = dontcare;
databusin[24] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[24] = dontcare;
iaddrbusout[25] = 32'h00000064;
instrbusin[25]={ADDI, 5'b00000, 5'b01000, 16'h0001};
daddrbusout[25] = dontcare;
databusin[25] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[25] = dontcare;
iaddrbusout[26] = 32'h0000008C;
instrbusin[26]={Rformat, 5'b00000, 5'b00000, 5'b00010, 5'b00000, SLE};
daddrbusout[26] = dontcare;
databusin[26] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[26] = dontcare;
iaddrbusout[27] = 32'h00000090;
instrbusin[27] = 32'b00000000000000000000000000000000;
daddrbusout[27] = dontcare;
databusin[27] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[27] = dontcare;
iaddrbusout[28] = 32'h00000094;
instrbusin[28] = 32'b00000000000000000000000000000000;
daddrbusout[28] = dontcare;
databusin[28] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[28] = dontcare;
iaddrbusout[29] = 32'h00000098;
instrbusin[29]={BEQ, 5'b00010, 5'b00000, 16'h0019};
daddrbusout[29] = dontcare;
databusin[29] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[29] = dontcare;
iaddrbusout[30] = 32'h0000009C;
instrbusin[30] = 32'b00000000000000000000000000000000;
daddrbusout[30] = dontcare;
databusin[30] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[30] = dontcare;
iaddrbusout[31] = 32'h000000A0;
instrbusin[31]={BEQ, 5'b00010, 5'b00010, 16'h000A};
daddrbusout[31] = dontcare;
databusin[31] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[31] = dontcare;
iaddrbusout[32] = 32'h000000A4;
instrbusin[32]={ADDI, 5'b00000, 5'b10100, 16'h0001};
daddrbusout[32] = dontcare;
databusin[32] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[32] = dontcare;
iaddrbusout[33] = 32'h000000CC;
instrbusin[33] = 32'b00000000000000000000000000000000;
daddrbusout[33] = dontcare;
databusin[33] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[33] = dontcare;
iaddrbusout[34] = 32'h000000D0;
instrbusin[34] = 32'b00000000000000000000000000000000;
daddrbusout[34] = dontcare;
databusin[34] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[34] = dontcare;
iaddrbusout[35] = 32'h000000D4;
instrbusin[35] = 32'b00000000000000000000000000000000;
daddrbusout[35] = dontcare;
databusin[35] = 32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
databusout[35] = dontcare;
ntests = 51;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 32'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 32'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 35; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,141 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v | 93,595,154 | ARMStb_phase2_32.v | v | 411 | 160 | [] | [] | [] | null | line:338: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:304: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:324: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:328: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:333: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:337: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:343: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:345: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:396: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase2_32.v:398: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,894 | module | module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:23];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:23], dselectout[0:23];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:23];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
parameter zeroSham = 6'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32'hx;
iname[0] = "ADDI, R20, R31, #AAA";
iaddrbusout[0] = 32'h00000000;
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32'h00000AAA;
iname[1] = "ADDI, R31, R23, #002";
iaddrbusout[1] = 32'h00000004;
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
iname[2] = "ADDI, R0, R23, #002";
iaddrbusout[2] = 32'h00000008;
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32'h00000002;
iname[3] = "ORRI, R21, R24, #001";
iaddrbusout[3] = 32'h0000000C;
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32'h00000001;
iname[4] = "EORI, R22, R20, #000";
iaddrbusout[4] = 32'h00000010;
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32'h00000AAA;
iname[5] = "ANDI, R23, R0, #003";
iaddrbusout[5] = 32'h00000014;
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32'h00000002;
iname[6] = "SUBI, R24, R20, #00A";
iaddrbusout[6] = 32'h00000018;
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32'h00000AA0;
iname[7] = "ADD, R25, R20, R0";
iaddrbusout[7] = 32'h0000001C;
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32'h00000AAC;
iname[8] = "AND, R26, R20, R22";
iaddrbusout[8] = 32'h00000020;
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32'h00000AAA;
iname[9] = "EOR, R27, R23, R21";
iaddrbusout[9] = 32'h00000024;
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32'h00000003;
iname[10] = "ORR, R28, R25, R23";
iaddrbusout[10] = 32'h00000028;
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32'h00000AAE;
iname[11] = "SUB, R29, R20, R22";
iaddrbusout[11] = 32'h0000002C;
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32'h00000000;
iname[12] = "ADDI, R30, R31, #000";
iaddrbusout[12] = 32'h00000030;
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32'h00000000;
iname[13] = "SUBIS,R20, R0, #003";
iaddrbusout[13] = 32'h00000034;
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
iname[14] = "SUBS, R21, R25, R28";
iaddrbusout[14] = 32'h00000038;
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
iname[15] = "ADDIS,R22, R31, #000";
iaddrbusout[15] = 32'h0000003C;
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
iname[16] = "ADDS R23, R20, R23";
iaddrbusout[16] = 32'h00000040;
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
iname[17] = "ANDIS,R24, R20, #002";
iaddrbusout[17] = 32'h00000044;
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
iname[18] = "ANDS, R25, R21, R20";
iaddrbusout[18] = 32'h00000048;
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
iaddrbusout[19] = 32'h0000004C;
instrbusin[19] = 32'b00000000000000000000000000000000;
dselectout[19] = dontcare;
dbusout[19] = dontcare;
iaddrbusout[20] = 32'h00000050;
instrbusin[20] = 32'b00000000000000000000000000000000;
dselectout[20] = dontcare;
dbusout[20] = dontcare;
iaddrbusout[21] = 32'h00000054;
instrbusin[21] = 32'b00000000000000000000000000000000;
dselectout[21] = dontcare;
dbusout[21] = dontcare;
iaddrbusout[22] = 32'h00000058;
instrbusin[22] = 32'b00000000000000000000000000000000;
dselectout[22] = dontcare;
dbusout[22] = dontcare;
iaddrbusout[23] = 32'h0000005C;
instrbusin[23] = 32'b00000000000000000000000000000000;
dselectout[23] = dontcare;
dbusout[23] = dontcare;
ntests = 24;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 26; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=4)
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----SIMULATION INCONCLUSIVE - CHECK YOUR NZVC BIT(S) IN THE SCOPE------");
end
endmodule | module ARMStb(); |
reg [31:0] instrbus;
reg [31:0] instrbusin[0:23];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:23], dselectout[0:23];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:23];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:23];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
parameter zeroSham = 6'b000000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32'hx;
iname[0] = "ADDI, R20, R31, #AAA";
iaddrbusout[0] = 32'h00000000;
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32'h00000AAA;
iname[1] = "ADDI, R31, R23, #002";
iaddrbusout[1] = 32'h00000004;
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
iname[2] = "ADDI, R0, R23, #002";
iaddrbusout[2] = 32'h00000008;
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32'h00000002;
iname[3] = "ORRI, R21, R24, #001";
iaddrbusout[3] = 32'h0000000C;
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32'h00000001;
iname[4] = "EORI, R22, R20, #000";
iaddrbusout[4] = 32'h00000010;
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32'h00000AAA;
iname[5] = "ANDI, R23, R0, #003";
iaddrbusout[5] = 32'h00000014;
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32'h00000002;
iname[6] = "SUBI, R24, R20, #00A";
iaddrbusout[6] = 32'h00000018;
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32'h00000AA0;
iname[7] = "ADD, R25, R20, R0";
iaddrbusout[7] = 32'h0000001C;
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32'h00000AAC;
iname[8] = "AND, R26, R20, R22";
iaddrbusout[8] = 32'h00000020;
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32'h00000AAA;
iname[9] = "EOR, R27, R23, R21";
iaddrbusout[9] = 32'h00000024;
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32'h00000003;
iname[10] = "ORR, R28, R25, R23";
iaddrbusout[10] = 32'h00000028;
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32'h00000AAE;
iname[11] = "SUB, R29, R20, R22";
iaddrbusout[11] = 32'h0000002C;
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32'h00000000;
iname[12] = "ADDI, R30, R31, #000";
iaddrbusout[12] = 32'h00000030;
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32'h00000000;
iname[13] = "SUBIS,R20, R0, #003";
iaddrbusout[13] = 32'h00000034;
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
iname[14] = "SUBS, R21, R25, R28";
iaddrbusout[14] = 32'h00000038;
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
iname[15] = "ADDIS,R22, R31, #000";
iaddrbusout[15] = 32'h0000003C;
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
iname[16] = "ADDS R23, R20, R23";
iaddrbusout[16] = 32'h00000040;
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
iname[17] = "ANDIS,R24, R20, #002";
iaddrbusout[17] = 32'h00000044;
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
iname[18] = "ANDS, R25, R21, R20";
iaddrbusout[18] = 32'h00000048;
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
iaddrbusout[19] = 32'h0000004C;
instrbusin[19] = 32'b00000000000000000000000000000000;
dselectout[19] = dontcare;
dbusout[19] = dontcare;
iaddrbusout[20] = 32'h00000050;
instrbusin[20] = 32'b00000000000000000000000000000000;
dselectout[20] = dontcare;
dbusout[20] = dontcare;
iaddrbusout[21] = 32'h00000054;
instrbusin[21] = 32'b00000000000000000000000000000000;
dselectout[21] = dontcare;
dbusout[21] = dontcare;
iaddrbusout[22] = 32'h00000058;
instrbusin[22] = 32'b00000000000000000000000000000000;
dselectout[22] = dontcare;
dbusout[22] = dontcare;
iaddrbusout[23] = 32'h0000005C;
instrbusin[23] = 32'b00000000000000000000000000000000;
dselectout[23] = dontcare;
dbusout[23] = dontcare;
ntests = 24;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 26; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=4)
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("-----SIMULATION INCONCLUSIVE - CHECK YOUR NZVC BIT(S) IN THE SCOPE------");
end
endmodule | 0 |
141,142 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v | 93,595,154 | ARMStb_phase3_64.v | v | 472 | 160 | [] | [] | [] | null | line:399: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:365: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:385: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:389: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:394: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:398: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:404: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:406: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:457: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase3_64.v:459: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,897 | module | module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [63:0] iaddrbus;
reg [63:0] iaddrbusout[0:29];
wire [31:0] dselect;
reg [31:0] dselectout[0:29];
wire [63:0] dbus;
reg [63:0] dbusout[0:29];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [31:0] dontcare_addr;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R18 = 5'b10010;
parameter R18_dselect = 32'b00000000000001000000000000000000;
parameter R19 = 5'b10011;
parameter R19_dselect = 32'b00000000000010000000000000000000;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 64'hx;
dontcare_addr = 32'hx;
iname[0] = "ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 64'h00000AAA;
iname[1] = "ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
iname[2] = "ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 64'h00000002;
iname[3] = "ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 64'h00000001;
iname[4] = "EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 64'h00000AAA;
iname[5] = "ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 64'h00000002;
iname[6] = "SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 64'h00000AA0;
iname[7] = "ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 64'h00000AAC;
iname[8] = "AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 64'h00000AAA;
iname[9] = "EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 64'h00000003;
iname[10] = "ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 64'h00000AAE;
iname[11] = "SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 64'h00000000;
iname[12] = "ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 64'h00000000;
iname[13] = "SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
iname[14] = "SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
iname[15] = "ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
iname[16] = "ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
iname[17] = "ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
iname[18] = "ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64'h00000007;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64'h00000700;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64'h00000000;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64'h00000000;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64'h00000700;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64'h00000007;
iname[25] = "NOP";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] = 64'b0;
dselectout[25] = dontcare_addr;
dbusout[25] = dontcare;
iname[26] = "NOP";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] = 64'b0;
dselectout[26] = dontcare_addr;
dbusout[26] = dontcare;
iname[27] = "NOP";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] = 64'b0;
dselectout[27] = dontcare_addr;
dbusout[27] = dontcare;
iname[28] = "NOP";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] = 64'b0;
dselectout[28] = dontcare_addr;
dbusout[28] = dontcare;
iname[29] = "NOP";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] = 64'b0;
dselectout[29] = dontcare_addr;
dbusout[29] = dontcare;
ntests = 30;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=4)
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 4) && (dselectout[k-4] !== dontcare_addr) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module ARMStb(); |
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [63:0] iaddrbus;
reg [63:0] iaddrbusout[0:29];
wire [31:0] dselect;
reg [31:0] dselectout[0:29];
wire [63:0] dbus;
reg [63:0] dbusout[0:29];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [31:0] dontcare_addr;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R18 = 5'b10010;
parameter R18_dselect = 32'b00000000000001000000000000000000;
parameter R19 = 5'b10011;
parameter R19_dselect = 32'b00000000000010000000000000000000;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 64'hx;
dontcare_addr = 32'hx;
iname[0] = "ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 64'h00000AAA;
iname[1] = "ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
iname[2] = "ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 64'h00000002;
iname[3] = "ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 64'h00000001;
iname[4] = "EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 64'h00000AAA;
iname[5] = "ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 64'h00000002;
iname[6] = "SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 64'h00000AA0;
iname[7] = "ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 64'h00000AAC;
iname[8] = "AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 64'h00000AAA;
iname[9] = "EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 64'h00000003;
iname[10] = "ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 64'h00000AAE;
iname[11] = "SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 64'h00000000;
iname[12] = "ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 64'h00000000;
iname[13] = "SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
iname[14] = "SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
iname[15] = "ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
iname[16] = "ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
iname[17] = "ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
iname[18] = "ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64'h00000007;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64'h00000700;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64'h00000000;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64'h00000000;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64'h00000700;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64'h00000007;
iname[25] = "NOP";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] = 64'b0;
dselectout[25] = dontcare_addr;
dbusout[25] = dontcare;
iname[26] = "NOP";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] = 64'b0;
dselectout[26] = dontcare_addr;
dbusout[26] = dontcare;
iname[27] = "NOP";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] = 64'b0;
dselectout[27] = dontcare_addr;
dbusout[27] = dontcare;
iname[28] = "NOP";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] = 64'b0;
dselectout[28] = dontcare_addr;
dbusout[28] = dontcare;
iname[29] = "NOP";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] = 64'b0;
dselectout[29] = dontcare_addr;
dbusout[29] = dontcare;
ntests = 30;
$timeformat(-9,1,"ns",12);
end
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=4)
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 4) && (dselectout[k-4] !== dontcare_addr) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,143 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v | 93,595,154 | ARMStb_phase4.v | v | 508 | 164 | [] | [] | [] | null | line:435: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:401: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:421: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:425: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:430: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:434: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:440: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:442: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:493: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase4.v:495: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,898 | module | module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:34];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:34], daddrbusout[0:34];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:34], databusout[0:34];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:34];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
iname[0] ="ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
iname[1] ="ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
iname[2] ="ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
iname[3] ="ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
iname[4] ="EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
iname[5] ="ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
iname[6] ="SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
iname[7] ="ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
iname[8] ="AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
iname[9] ="EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
iname[10] ="ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
iname[11] ="SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
iname[12] ="ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
iname[13] ="SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
iname[14] ="SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
iname[15] ="ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
iname[16] ="ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
iname[17] ="ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
iname[18] ="ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
iname[25] ="LDUR, R22, R31, #1";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;
databusin[25] = 64'h0000000000042069;
databusout[25] = dontcare;
iname[26] ="STUR, R23, #068, R24";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;
iname[27] ="AND, R19, R31, R31";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
iname[28] ="AND, R18, R31, R31";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
iname[29] ="AND, R17, R31, R31";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
iname[30] = "NOP";
iaddrbusout[30] = 64'h00000078;
instrbusin[30] = 64'b0;
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
iname[31] = "NOP";
iaddrbusout[31] = 64'h0000007C;
instrbusin[31] = 64'b0;
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
iname[32] = "NOP";
iaddrbusout[32] = 64'h00000080;
instrbusin[32] = 64'b0;
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
iname[33] = "NOP";
iaddrbusout[33] = 64'h00000084;
instrbusin[33] = 64'b0;
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
iname[34] = "NOP";
iaddrbusout[34] = 64'h00000088;
instrbusin[34] = 64'b0;
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
ntests = 35;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 64'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 34; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module ARMStb(); |
reg [31:0] instrbus;
reg [31:0] instrbusin[0:34];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:34], daddrbusout[0:34];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:34], databusout[0:34];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:34];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
iname[0] ="ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
iname[1] ="ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
iname[2] ="ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
iname[3] ="ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
iname[4] ="EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
iname[5] ="ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
iname[6] ="SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
iname[7] ="ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
iname[8] ="AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
iname[9] ="EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
iname[10] ="ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
iname[11] ="SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
iname[12] ="ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
iname[13] ="SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
iname[14] ="SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
iname[15] ="ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
iname[16] ="ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
iname[17] ="ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
iname[18] ="ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
iname[25] ="LDUR, R22, R31, #1";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;
databusin[25] = 64'h0000000000042069;
databusout[25] = dontcare;
iname[26] ="STUR, R23, #068, R24";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;
iname[27] ="AND, R19, R31, R31";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
iname[28] ="AND, R18, R31, R31";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
iname[29] ="AND, R17, R31, R31";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
iname[30] = "NOP";
iaddrbusout[30] = 64'h00000078;
instrbusin[30] = 64'b0;
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
iname[31] = "NOP";
iaddrbusout[31] = 64'h0000007C;
instrbusin[31] = 64'b0;
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
iname[32] = "NOP";
iaddrbusout[32] = 64'h00000080;
instrbusin[32] = 64'b0;
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
iname[33] = "NOP";
iaddrbusout[33] = 64'h00000084;
instrbusin[33] = 64'b0;
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
iname[34] = "NOP";
iaddrbusout[34] = 64'h00000088;
instrbusin[34] = 64'b0;
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
ntests = 35;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 64'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 34; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,144 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v | 93,595,154 | ARMStb_phase8.v | v | 928 | 164 | [] | [] | [] | null | line:855: before: "$" | null | 1: b'%Error: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:821: Unsupported or unknown PLI call: $timeformat\n$timeformat(-9,1,"ns",12);\n^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:841: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:845: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:850: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:854: Unsupported: Ignoring delay on this delayed statement.\n #5\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:860: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:862: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:913: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMStb_phase8.v:915: Unsupported: Ignoring delay on this delayed statement.\n #3\n ^\n%Error: Exiting due to 1 error(s), 8 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 310,902 | module | module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:81];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:81], daddrbusout[0:81];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:81], databusout[0:81];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:81];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
parameter move_0 = 2'b00;
parameter move_1 = 2'b01;
parameter move_2 = 2'b10;
parameter move_3 = 2'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
iname[0] ="ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
iname[1] ="ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
iname[2] ="ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
iname[3] ="ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
iname[4] ="EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
iname[5] ="ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
iname[6] ="SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
iname[7] ="ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
iname[8] ="AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
iname[9] ="EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
iname[10] ="ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
iname[11] ="SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
iname[12] ="ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
iname[13] ="SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
iname[14] ="SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
iname[15] ="ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
iname[16] ="ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
iname[17] ="ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
iname[18] ="ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
iname[25] ="LDUR, R22, R31, #1";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;
databusin[25] = 64'h0000000000042069;
databusout[25] = dontcare;
iname[26] ="STUR, R23, #068, R24";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;
iname[27] ="AND, R19, R31, R31";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
iname[28] ="AND, R18, R31, R31";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
iname[29] ="AND, R17, R31, R31";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
iname[30] ="B, #EA";
iaddrbusout[30] = 64'h00000078;
instrbusin[30] ={B, 26'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
iname[31] ="AND, R19, R31, R31";
iaddrbusout[31] = 64'h0000007C;
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
iname[32] ="ADD, R20, R21, R20";
iaddrbusout[32] = 64'h00000420;
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
iname[33] ="ADDI, R21, R31, #AAA";
iaddrbusout[33] = 64'h00000424;
instrbusin[33] ={ADDI, 12'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
iname[34] ="ADDI, R22, R31, #AAA";
iaddrbusout[34] = 64'h00000428;
instrbusin[34] ={ADDI, 12'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
iname[35] ="ADDIS,R31, R31, #420";
iaddrbusout[35] = 64'h0000042C;
instrbusin[35] ={ADDIS, 12'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64'bz;
databusout[35] = dontcare;
iname[36] ="B_EQ, #69420, RX";
iaddrbusout[36] = 64'h00000430;
instrbusin[36] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64'bz;
databusout[36] = dontcare;
iname[37] = "NOP";
iaddrbusout[37] = 64'h00000434;
instrbusin[37] = 64'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64'bz;
databusout[37] = dontcare;
iname[38] ="SUBS, R31, R21, R22";
iaddrbusout[38] = 64'h00000438;
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64'bz;
databusout[38] = dontcare;
iname[39] ="B_EQ, #69, RX";
iaddrbusout[39] = 64'h0000043C;
instrbusin[39] ={B_EQ, 19'b0000000000001101001, RX};
daddrbusout[39] = dontcare;
databusin[39] = 64'bz;
databusout[39] = dontcare;
iname[40] = "NOP";
iaddrbusout[40] = 64'h00000440;
instrbusin[40] = 64'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64'bz;
databusout[40] = dontcare;
iname[41] = "NOP";
iaddrbusout[41] = 64'h000005E0;
instrbusin[41] = 64'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64'bz;
databusout[41] = dontcare;
iname[42] ="SUBS, R31, R21, R20";
iaddrbusout[42] = 64'h000005E4;
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64'bz;
databusout[42] = dontcare;
iname[43] ="B_NE, #96, RX";
iaddrbusout[43] = 64'h000005E8;
instrbusin[43] ={B_NE, 19'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64'bz;
databusout[43] = dontcare;
iname[44] = "NOP";
iaddrbusout[44] = 64'h000005EC;
instrbusin[44] = 64'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64'bz;
databusout[44] = dontcare;
iname[45] = "NOP";
iaddrbusout[45] = 64'h00000840;
instrbusin[45] = 64'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64'bz;
databusout[45] = dontcare;
iname[46] ="CBZ, #F, R22";
iaddrbusout[46] = 64'h00000844;
instrbusin[46] ={CBZ, 19'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64'bz;
databusout[46] = dontcare;
iname[47] = "NOP";
iaddrbusout[47] = 64'h00000848;
instrbusin[47] = 64'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64'bz;
databusout[47] = dontcare;
iname[48] = "NOP";
iaddrbusout[48] = 64'h0000084C;
instrbusin[48] = 64'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64'bz;
databusout[48] = dontcare;
iname[49] ="CBZ, #21, R19";
iaddrbusout[49] = 64'h00000850;
instrbusin[49] ={CBZ, 19'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64'bz;
databusout[49] = dontcare;
iname[50] = "NOP";
iaddrbusout[50] = 64'h00000854;
instrbusin[50] = 64'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64'bz;
databusout[50] = dontcare;
iname[51] = "NOP";
iaddrbusout[51] = 64'h000008D4;
instrbusin[51] = 64'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64'bz;
databusout[51] = dontcare;
iname[52] ="CBNZ, #FF, R31";
iaddrbusout[52] = 64'h000008D8;
instrbusin[52] ={CBNZ, 19'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64'bz;
databusout[52] = dontcare;
iname[53] = "NOP";
iaddrbusout[53] = 64'h000008DC;
instrbusin[53] = 64'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64'bz;
databusout[53] = dontcare;
iname[54] = "NOP";
iaddrbusout[54] = 64'h000008E0;
instrbusin[54] = 64'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64'bz;
databusout[54] = dontcare;
iname[55] ="CBNZ, #22, R20";
iaddrbusout[55] = 64'h000008E4;
instrbusin[55] ={CBNZ, 19'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64'bz;
databusout[55] = dontcare;
iname[56] = "NOP";
iaddrbusout[56] = 64'h000008E8;
instrbusin[56] = 64'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64'bz;
databusout[56] = dontcare;
iname[57] = "NOP";
iaddrbusout[57] = 64'h0000096C;
instrbusin[57] = 64'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64'bz;
databusout[57] = dontcare;
iname[58] ="AND, R19, R31, R31";
iaddrbusout[58] = 64'h00000970;
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64'bz;
databusout[58] = dontcare;
iname[59] ="AND, R20, R31, R31";
iaddrbusout[59] = 64'h00000974;
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64'bz;
databusout[59] = dontcare;
iname[60] ="AND, R21, R31, R31";
iaddrbusout[60] = 64'h00000978;
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64'bz;
databusout[60] = dontcare;
iname[61] ="AND, R22, R31, R31";
iaddrbusout[61] = 64'h0000097C;
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64'bz;
databusout[61] = dontcare;
iname[62] ="MOVZ, move_0, #FFFF, R19";
iaddrbusout[62] = 64'h00000980;
instrbusin[62] ={MOVZ, move_0, 16'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64'bz;
databusout[62] = dontcare;
iname[63] ="MOVZ, move_1, #FFFF, R20";
iaddrbusout[63] = 64'h00000984;
instrbusin[63] ={MOVZ, move_1, 16'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64'bz;
databusout[63] = dontcare;
iname[64] ="MOVZ, move_2, #FFFF, R21";
iaddrbusout[64] = 64'h00000988;
instrbusin[64] ={MOVZ, move_2, 16'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64'bz;
databusout[64] = dontcare;
iname[65] ="MOVZ, move_3, #7FFF, R22";
iaddrbusout[65] = 64'h0000098C;
instrbusin[65] ={MOVZ, move_3, 16'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64'bz;
databusout[65] = dontcare;
iname[66] ="ORR, R23, R19, R20";
iaddrbusout[66] = 64'h00000990;
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64'bz;
databusout[66] = dontcare;
iname[67] = "NOP";
iaddrbusout[67] = 64'h00000994;
instrbusin[67] = 64'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64'bz;
databusout[67] = dontcare;
iname[68] ="ORR, R24, R21, R22";
iaddrbusout[68] = 64'h00000998;
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64'bz;
databusout[68] = dontcare;
iname[69] = "NOP";
iaddrbusout[69] = 64'h0000099C;
instrbusin[69] = 64'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64'bz;
databusout[69] = dontcare;
iname[70] = "NOP";
iaddrbusout[70] = 64'h000009A0;
instrbusin[70] = 64'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64'bz;
databusout[70] = dontcare;
iname[71] ="ORR, R25, R23, R24";
iaddrbusout[71] = 64'h000009A4;
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64'bz;
databusout[71] = dontcare;
iname[72] = "NOP";
iaddrbusout[72] = 64'h000009A8;
instrbusin[72] = 64'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64'bz;
databusout[72] = dontcare;
iname[73] = "NOP";
iaddrbusout[73] = 64'h000009AC;
instrbusin[73] = 64'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64'bz;
databusout[73] = dontcare;
iname[74] ="ADDIS,R26, R25, #001";
iaddrbusout[74] = 64'h000009B0;
instrbusin[74] ={ADDIS, 12'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64'bz;
databusout[74] = dontcare;
iname[75] = "NOP";
iaddrbusout[75] = 64'h000009B4;
instrbusin[75] = 64'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64'bz;
databusout[75] = dontcare;
iname[76] = "NOP";
iaddrbusout[76] = 64'h000009B8;
instrbusin[76] = 64'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64'bz;
databusout[76] = dontcare;
iname[77] = "NOP";
iaddrbusout[77] = 64'h000009BC;
instrbusin[77] = 64'b0;
daddrbusout[77] = dontcare;
databusin[77] = 64'bz;
databusout[77] = dontcare;
iname[78] = "NOP";
iaddrbusout[78] = 64'h000009C0;
instrbusin[78] = 64'b0;
daddrbusout[78] = dontcare;
databusin[78] = 64'bz;
databusout[78] = dontcare;
iname[79] = "NOP";
iaddrbusout[79] = 64'h000009C4;
instrbusin[79] = 64'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64'bz;
databusout[79] = dontcare;
iname[80] = "NOP";
iaddrbusout[80] = 64'h000009C8;
instrbusin[80] = 64'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64'bz;
databusout[80] = dontcare;
iname[81] = "NOP";
iaddrbusout[81] = 64'h000009CC;
instrbusin[81] = 64'b0;
daddrbusout[81] = dontcare;
databusin[81] = 64'bz;
databusout[81] = dontcare;
ntests = 82;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 64'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 81; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | module ARMStb(); |
reg [31:0] instrbus;
reg [31:0] instrbusin[0:81];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:81], daddrbusout[0:81];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:81], databusout[0:81];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:81];
integer error, k, ntests;
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
parameter move_0 = 2'b00;
parameter move_1 = 2'b01;
parameter move_2 = 2'b10;
parameter move_3 = 2'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
iname[0] ="ADDI, R20, R31, #AAA";
iaddrbusout[0] = 64'h00000000;
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
iname[1] ="ADDI, R31, R23, #002";
iaddrbusout[1] = 64'h00000004;
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
iname[2] ="ADDI, R0, R23, #002";
iaddrbusout[2] = 64'h00000008;
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
iname[3] ="ORRI, R21, R24, #001";
iaddrbusout[3] = 64'h0000000C;
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
iname[4] ="EORI, R22, R20, #000";
iaddrbusout[4] = 64'h00000010;
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
iname[5] ="ANDI, R23, R0, #003";
iaddrbusout[5] = 64'h00000014;
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
iname[6] ="SUBI, R24, R20, #00A";
iaddrbusout[6] = 64'h00000018;
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
iname[7] ="ADD, R25, R20, R0";
iaddrbusout[7] = 64'h0000001C;
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
iname[8] ="AND, R26, R20, R22";
iaddrbusout[8] = 64'h00000020;
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
iname[9] ="EOR, R27, R23, R21";
iaddrbusout[9] = 64'h00000024;
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
iname[10] ="ORR, R28, R25, R23";
iaddrbusout[10] = 64'h00000028;
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
iname[11] ="SUB, R29, R20, R22";
iaddrbusout[11] = 64'h0000002C;
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
iname[12] ="ADDI, R30, R31, #000";
iaddrbusout[12] = 64'h00000030;
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
iname[13] ="SUBIS,R20, R0, #003";
iaddrbusout[13] = 64'h00000034;
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
iname[14] ="SUBS, R21, R25, R28";
iaddrbusout[14] = 64'h00000038;
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
iname[15] ="ADDIS,R22, R31, #000";
iaddrbusout[15] = 64'h0000003C;
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
iname[16] ="ADDS R23, R20, R23";
iaddrbusout[16] = 64'h00000040;
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
iname[17] ="ANDIS,R24, R20, #002";
iaddrbusout[17] = 64'h00000044;
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
iname[18] ="ANDS, R25, R21, R20";
iaddrbusout[18] = 64'h00000048;
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
iname[19] ="ADDI, R20, R31, #007";
iaddrbusout[19] = 64'h0000004C;
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
iname[20] ="ADDI, R21, R31, #700";
iaddrbusout[20] = 64'h00000050;
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
iname[21] ="AND, R19, R31, R31";
iaddrbusout[21] = 64'h00000054;
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
iname[22] ="AND, R18, R31, R31";
iaddrbusout[22] = 64'h00000058;
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
iname[23] ="LSL, R20, R20, 2";
iaddrbusout[23] = 64'h0000005C;
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
iname[24] ="LSR, R21, R21, 2";
iaddrbusout[24] = 64'h00000060;
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
iname[25] ="LDUR, R22, R31, #1";
iaddrbusout[25] = 64'h00000064;
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;
databusin[25] = 64'h0000000000042069;
databusout[25] = dontcare;
iname[26] ="STUR, R23, #068, R24";
iaddrbusout[26] = 64'h00000068;
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;
iname[27] ="AND, R19, R31, R31";
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
iname[28] ="AND, R18, R31, R31";
iaddrbusout[28] = 64'h00000070;
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
iname[29] ="AND, R17, R31, R31";
iaddrbusout[29] = 64'h00000074;
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
iname[30] ="B, #EA";
iaddrbusout[30] = 64'h00000078;
instrbusin[30] ={B, 26'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
iname[31] ="AND, R19, R31, R31";
iaddrbusout[31] = 64'h0000007C;
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
iname[32] ="ADD, R20, R21, R20";
iaddrbusout[32] = 64'h00000420;
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
iname[33] ="ADDI, R21, R31, #AAA";
iaddrbusout[33] = 64'h00000424;
instrbusin[33] ={ADDI, 12'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
iname[34] ="ADDI, R22, R31, #AAA";
iaddrbusout[34] = 64'h00000428;
instrbusin[34] ={ADDI, 12'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
iname[35] ="ADDIS,R31, R31, #420";
iaddrbusout[35] = 64'h0000042C;
instrbusin[35] ={ADDIS, 12'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64'bz;
databusout[35] = dontcare;
iname[36] ="B_EQ, #69420, RX";
iaddrbusout[36] = 64'h00000430;
instrbusin[36] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64'bz;
databusout[36] = dontcare;
iname[37] = "NOP";
iaddrbusout[37] = 64'h00000434;
instrbusin[37] = 64'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64'bz;
databusout[37] = dontcare;
iname[38] ="SUBS, R31, R21, R22";
iaddrbusout[38] = 64'h00000438;
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64'bz;
databusout[38] = dontcare;
iname[39] ="B_EQ, #69, RX";
iaddrbusout[39] = 64'h0000043C;
instrbusin[39] ={B_EQ, 19'b0000000000001101001, RX};
daddrbusout[39] = dontcare;
databusin[39] = 64'bz;
databusout[39] = dontcare;
iname[40] = "NOP";
iaddrbusout[40] = 64'h00000440;
instrbusin[40] = 64'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64'bz;
databusout[40] = dontcare;
iname[41] = "NOP";
iaddrbusout[41] = 64'h000005E0;
instrbusin[41] = 64'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64'bz;
databusout[41] = dontcare;
iname[42] ="SUBS, R31, R21, R20";
iaddrbusout[42] = 64'h000005E4;
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64'bz;
databusout[42] = dontcare;
iname[43] ="B_NE, #96, RX";
iaddrbusout[43] = 64'h000005E8;
instrbusin[43] ={B_NE, 19'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64'bz;
databusout[43] = dontcare;
iname[44] = "NOP";
iaddrbusout[44] = 64'h000005EC;
instrbusin[44] = 64'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64'bz;
databusout[44] = dontcare;
iname[45] = "NOP";
iaddrbusout[45] = 64'h00000840;
instrbusin[45] = 64'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64'bz;
databusout[45] = dontcare;
iname[46] ="CBZ, #F, R22";
iaddrbusout[46] = 64'h00000844;
instrbusin[46] ={CBZ, 19'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64'bz;
databusout[46] = dontcare;
iname[47] = "NOP";
iaddrbusout[47] = 64'h00000848;
instrbusin[47] = 64'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64'bz;
databusout[47] = dontcare;
iname[48] = "NOP";
iaddrbusout[48] = 64'h0000084C;
instrbusin[48] = 64'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64'bz;
databusout[48] = dontcare;
iname[49] ="CBZ, #21, R19";
iaddrbusout[49] = 64'h00000850;
instrbusin[49] ={CBZ, 19'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64'bz;
databusout[49] = dontcare;
iname[50] = "NOP";
iaddrbusout[50] = 64'h00000854;
instrbusin[50] = 64'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64'bz;
databusout[50] = dontcare;
iname[51] = "NOP";
iaddrbusout[51] = 64'h000008D4;
instrbusin[51] = 64'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64'bz;
databusout[51] = dontcare;
iname[52] ="CBNZ, #FF, R31";
iaddrbusout[52] = 64'h000008D8;
instrbusin[52] ={CBNZ, 19'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64'bz;
databusout[52] = dontcare;
iname[53] = "NOP";
iaddrbusout[53] = 64'h000008DC;
instrbusin[53] = 64'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64'bz;
databusout[53] = dontcare;
iname[54] = "NOP";
iaddrbusout[54] = 64'h000008E0;
instrbusin[54] = 64'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64'bz;
databusout[54] = dontcare;
iname[55] ="CBNZ, #22, R20";
iaddrbusout[55] = 64'h000008E4;
instrbusin[55] ={CBNZ, 19'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64'bz;
databusout[55] = dontcare;
iname[56] = "NOP";
iaddrbusout[56] = 64'h000008E8;
instrbusin[56] = 64'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64'bz;
databusout[56] = dontcare;
iname[57] = "NOP";
iaddrbusout[57] = 64'h0000096C;
instrbusin[57] = 64'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64'bz;
databusout[57] = dontcare;
iname[58] ="AND, R19, R31, R31";
iaddrbusout[58] = 64'h00000970;
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64'bz;
databusout[58] = dontcare;
iname[59] ="AND, R20, R31, R31";
iaddrbusout[59] = 64'h00000974;
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64'bz;
databusout[59] = dontcare;
iname[60] ="AND, R21, R31, R31";
iaddrbusout[60] = 64'h00000978;
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64'bz;
databusout[60] = dontcare;
iname[61] ="AND, R22, R31, R31";
iaddrbusout[61] = 64'h0000097C;
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64'bz;
databusout[61] = dontcare;
iname[62] ="MOVZ, move_0, #FFFF, R19";
iaddrbusout[62] = 64'h00000980;
instrbusin[62] ={MOVZ, move_0, 16'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64'bz;
databusout[62] = dontcare;
iname[63] ="MOVZ, move_1, #FFFF, R20";
iaddrbusout[63] = 64'h00000984;
instrbusin[63] ={MOVZ, move_1, 16'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64'bz;
databusout[63] = dontcare;
iname[64] ="MOVZ, move_2, #FFFF, R21";
iaddrbusout[64] = 64'h00000988;
instrbusin[64] ={MOVZ, move_2, 16'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64'bz;
databusout[64] = dontcare;
iname[65] ="MOVZ, move_3, #7FFF, R22";
iaddrbusout[65] = 64'h0000098C;
instrbusin[65] ={MOVZ, move_3, 16'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64'bz;
databusout[65] = dontcare;
iname[66] ="ORR, R23, R19, R20";
iaddrbusout[66] = 64'h00000990;
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64'bz;
databusout[66] = dontcare;
iname[67] = "NOP";
iaddrbusout[67] = 64'h00000994;
instrbusin[67] = 64'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64'bz;
databusout[67] = dontcare;
iname[68] ="ORR, R24, R21, R22";
iaddrbusout[68] = 64'h00000998;
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64'bz;
databusout[68] = dontcare;
iname[69] = "NOP";
iaddrbusout[69] = 64'h0000099C;
instrbusin[69] = 64'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64'bz;
databusout[69] = dontcare;
iname[70] = "NOP";
iaddrbusout[70] = 64'h000009A0;
instrbusin[70] = 64'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64'bz;
databusout[70] = dontcare;
iname[71] ="ORR, R25, R23, R24";
iaddrbusout[71] = 64'h000009A4;
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64'bz;
databusout[71] = dontcare;
iname[72] = "NOP";
iaddrbusout[72] = 64'h000009A8;
instrbusin[72] = 64'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64'bz;
databusout[72] = dontcare;
iname[73] = "NOP";
iaddrbusout[73] = 64'h000009AC;
instrbusin[73] = 64'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64'bz;
databusout[73] = dontcare;
iname[74] ="ADDIS,R26, R25, #001";
iaddrbusout[74] = 64'h000009B0;
instrbusin[74] ={ADDIS, 12'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64'bz;
databusout[74] = dontcare;
iname[75] = "NOP";
iaddrbusout[75] = 64'h000009B4;
instrbusin[75] = 64'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64'bz;
databusout[75] = dontcare;
iname[76] = "NOP";
iaddrbusout[76] = 64'h000009B8;
instrbusin[76] = 64'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64'bz;
databusout[76] = dontcare;
iname[77] = "NOP";
iaddrbusout[77] = 64'h000009BC;
instrbusin[77] = 64'b0;
daddrbusout[77] = dontcare;
databusin[77] = 64'bz;
databusout[77] = dontcare;
iname[78] = "NOP";
iaddrbusout[78] = 64'h000009C0;
instrbusin[78] = 64'b0;
daddrbusout[78] = dontcare;
databusin[78] = 64'bz;
databusout[78] = dontcare;
iname[79] = "NOP";
iaddrbusout[79] = 64'h000009C4;
instrbusin[79] = 64'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64'bz;
databusout[79] = dontcare;
iname[80] = "NOP";
iaddrbusout[80] = 64'h000009C8;
instrbusin[80] = 64'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64'bz;
databusout[80] = dontcare;
iname[81] = "NOP";
iaddrbusout[81] = 64'h000009CC;
instrbusin[81] = 64'b0;
daddrbusout[81] = dontcare;
databusin[81] = 64'bz;
databusout[81] = dontcare;
ntests = 82;
$timeformat(-9,1,"ns",12);
end
assign databus = clkd ? 64'bz : databusk;
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 81; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
if (k >=3)
databusk = databusin[k-3];
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule | 0 |
141,145 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module ARMS(ibus,clk,daddrbus,databus,reset,iaddrbus);
input clk;
input reset;
output [63:0] iaddrbus;
wire [63:0] iaddrbusWire1;
wire [63:0] iaddrbusWire2;
wire [63:0] iaddrbusWire4;
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
wire ZBit;
wire [63:0] potentialSLEBit;
wire [63:0] potentialSLTBit;
wire [63:0] actualSLBit;
wire ALUCoutWire;
wire overflowWire;
reg [2:0] branchControlBit;
wire [2:0] branchControlBitWire1;
wire [2:0] branchControlBitWire2;
wire [2:0] branchControlBitWire3;
reg takeBranch;
wire takeBranchWire1;
wire takeCondBranchWire1;
wire [63:0] PCWire1;
wire [63:0] branchCalcWire1;
wire [63:0] branchCalcWire2;
output [63:0] daddrbus;
inout [63:0] databus;
wire [10:0] opCode;
reg NOP;
wire NOPWire1;
wire NOPWire2;
wire NOPWire3;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [31:0] AselectWire1;
wire [5:0] rn;
wire [31:0] BselectWire;
wire [31:0] BselectWire1;
wire [31:0] BselectWire2;
wire [5:0] rm;
reg movBit1;
wire movBit2;
wire [5:0] moveImmShftAmt;
wire [5:0] moveImmShftAmtWire1;
reg immBit1;
wire immBit2;
wire [3:0]NZVC;
wire potentialNBit;
wire potentialZBit;
wire potentialVBit;
wire potentialCBit;
reg NZVCSetBit;
wire NZVCSetBitWire1;
reg [1:0] shiftBit1;
wire [1:0] shiftBit2;
wire [63:0] potentialLSLResult;
wire [63:0] potentialLSRResult;
wire [63:0] actualLSResult;
reg [1:0] lwSwFlag1;
wire [1:0] lwSwFlag2;
wire [1:0] lwSwFlag3;
wire [1:0] lwSwFlag4;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
wire [31:0] DselectWire3_5;
wire [31:0] DselectWire4;
wire [63:0] abusWire1;
wire [63:0] abusWire2;
wire [63:0] bbusWire1;
wire [63:0] bbusWire2;
wire [63:0] bbusWire3;
wire [63:0] bbusWire3_5;
wire [63:0] bbusWire4;
wire [63:0] dbusWire1;
wire [63:0] dbusWire1_5;
wire [63:0] dbusWire1_6;
wire [63:0] dbusWire2;
wire [63:0] dbusWire3;
wire [63:0] mux3Out;
wire [63:0] mux2Out;
wire [63:0] mux5;
wire [63:0] mux6;
wire mux4Controller;
wire [63:0] ALUImmWire1;
wire [63:0] ALUImmWire2;
wire [63:0] BranchAddrWire1;
wire [63:0] CondBranchAddrType1Wire1;
wire [63:0] CondBranchAddrType2Wire1;
wire [63:0] MOVImmWire1;
wire [63:0] MOVImmWire2;
wire [5:0] shamt;
wire [5:0] shamtWire1;
wire [63:0] DTAddrWire1;
wire [63:0] DTAddrWire2;
wire [63:0] DTAddrWire3;
wire [63:0] DTAddrWire4;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
movBit1 = 1'bx;
NZVCSetBit = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
branchControlBit = 3'b0;
setControlBits = 2'b00;
shiftBit1 = 2'bxx;
takeBranch = 1'b0;
NOP = 1'bx;
end
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
assign iaddrbusWire4 = iaddrbusWire2;
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
assign iaddrbus = iaddrbusWire1;
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
assign opCode = ibusWire[31:21];
assign rn = ibusWire[9:5];
assign rm = ibusWire[20:16];
assign rd = ibusWire[4:0];
assign shamt = ibusWire[15:10];
assign DTAddrWire1 = ibusWire[20]? {55'b1,ibusWire[20:12]} : {55'b0,ibusWire[20:12]};
assign moveImmShftAmt = ibusWire[22:21] << 4;
assign ALUImmWire1 = {52'b0, ibusWire[21:10]};
assign BranchAddrWire1 = ibusWire[25]? {36'b1111,ibusWire[25:0],2'b00} : {36'b0000,ibusWire[25:0],2'b00};
assign CondBranchAddrType1Wire1 = ibusWire[23]? {43'b11111111111,ibusWire[23:5],2'b00} : {43'b00000000000,ibusWire[23:5],2'b00};
assign MOVImmWire1= {48'b0, ibusWire[20:5]};
always @(ibusWire) begin
immBit1 = 0;
movBit1 = 0;
CinWire1 = 0;
branchControlBit = 3'b000;
setControlBits = 0;
NZVCSetBit = 0;
lwSwFlag1 = 2'b00;
shiftBit1 = 2'b00;
NOP = 1'b0;
casez (opCode)
11'b10001011000: begin
SWire1 = 3'b010;
end
11'b1001000100?: begin
SWire1 = 3'b010;
immBit1 = 1;
end
11'b1011000100?: begin
SWire1 = 3'b010;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b10101011000: begin
SWire1 = 3'b010;
NZVCSetBit = 1;
end
11'b10001010000: begin
SWire1 = 3'b110;
end
11'b1001001000?: begin
SWire1 = 3'b110;
immBit1 = 1;
end
11'b1111001000?: begin
SWire1 = 3'b110;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b11101010000: begin
SWire1 = 3'b110;
NZVCSetBit = 1;
end
11'b10110101???: begin
SWire1 = 3'b010;
branchControlBit = 3'b110;
end
11'b10110100???: begin
SWire1 = 3'b010;
branchControlBit = 3'b111;
end
11'b11001010000: begin
SWire1 = 3'b000;
end
11'b1101001000?: begin
SWire1 = 3'b000;
immBit1 = 1;
end
11'b11111000010: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
11'b11010011011: begin
shiftBit1 = 2'b01;
SWire1 = 3'b010;
end
11'b11010011010: begin
shiftBit1 = 2'b10;
SWire1 = 3'b010;
end
11'b110100101??: begin
movBit1 = 1;
SWire1 = 3'b100;
end
11'b10101010000: begin
SWire1 = 3'b100;
end
11'b1011001000?: begin
SWire1 = 3'b100;
immBit1 = 1;
end
11'b11111000000: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
11'b11001011000: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
11'b1101000100?: begin
SWire1 = 3'b011;
CinWire1 = 1;
immBit1 = 1;
end
11'b1111000100?: begin
SWire1 = 3'b011;
CinWire1 = 1;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b11101011000: begin
SWire1 = 3'b011;
CinWire1 = 1;
NZVCSetBit = 1;
end
11'b000101?????: begin
SWire1 = 3'b010;
branchControlBit = 3'b001;
end
11'b01010101???: begin
SWire1 = 3'b010;
branchControlBit = 3'b010;
end
11'b01010110???: begin
SWire1 = 3'b010;
branchControlBit = 3'b011;
end
11'b01010111???: begin
SWire1 = 3'b010;
branchControlBit = 3'b100;
end
11'b01011000???: begin
SWire1 = 3'b010;
branchControlBit = 3'b101;
end
11'b00000000000: begin
SWire1 = 3'b010;
NOP = 1'b1;
end
endcase
end
always@(negedge clk) begin
takeBranch = 1'b0;
case (branchControlBit)
3'b000: begin
takeBranch = 0;
end
3'b001: begin
takeBranch = 1;
end
3'b010: begin
takeBranch = (NZVC[2] == 1'b1)? 1:0;
end
3'b011: begin
takeBranch = (NZVC[2] == 1'b0)? 1:0;
end
3'b100: begin
takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
3'b101: begin
takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
3'b110: begin
takeBranch = (abusWire1 != 0)? 1:0;
end
3'b111: begin
takeBranch = (abusWire1 == 0)? 1:0;
end
endcase
end
assign AselectWire = ((branchControlBit == 3'b110) || (branchControlBit == 3'b111))? 1<<rd :1 << rn;
assign AselectWire1 = (movBit1)? 32'h80000000 : AselectWire;
assign BselectWire = 1 << rm;
assign BselectWire1 = ((shiftBit1 > 2'b00) || (movBit1))? 32'h80000000:BselectWire;
assign BselectWire2 = (lwSwFlag1 == 2'b10)? 1<<rd:BselectWire1;
assign DselectWire1 = 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire1),.Bselect(BselectWire2),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
assign takeBranchWire1 = takeBranch;
assign mux4Controller = ((!clk) && (branchControlBit > 3'b000) && (takeBranchWire1))? 1 : 0;
assign branchCalcWire1 = (branchControlBit == 3'b001)? BranchAddrWire1:CondBranchAddrType1Wire1;
assign branchCalcWire2 = branchCalcWire1 + PCWire1 - 4;
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.ALUImmWire1(ALUImmWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.ALUImmWire2(ALUImmWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1),.NZVCSetBit(NZVCSetBit),.NZVCSetBitWire1(NZVCSetBitWire1),
.shiftBit1(shiftBit1),.shiftBit2(shiftBit2),.shamt(shamt),.shamtWire1(shamtWire1),.DTAddrWire1(DTAddrWire1),.DTAddrWire2(DTAddrWire2),
.MOVImmWire1(MOVImmWire1),.MOVImmWire2(MOVImmWire2),.movBit1(movBit1),.movBit2(movBit2),.moveImmShftAmt(moveImmShftAmt),
.moveImmShftAmtWire1(moveImmShftAmtWire1),.NOP(NOP),.NOPWire1(NOPWire1));
assign mux2Out = immBit2? ALUImmWire2: bbusWire2;
assign mux5 = (lwSwFlag2 > 2'b00)? DTAddrWire2:mux2Out;
assign mux6 = (movBit2)? MOVImmWire2:mux5;
alu64 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux6),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire),.V(overflowWire));
assign ZBit = (dbusWire1==0)? 1:0;
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 64'h0000000000000001:64'h0000000000000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 64'h0000000000000001:64'h0000000000000000;
assign actualSLBit = (setControlBitsWire1 == 2'b01)? potentialSLTBit: potentialSLEBit;
assign potentialLSLResult = dbusWire1 << shamtWire1;
assign potentialLSRResult = dbusWire1 >> shamtWire1;
assign actualLSResult = (shiftBit2 == 2'b10)? potentialLSRResult:potentialLSLResult;
assign dbusWire1_5 = (shiftBit2 > 2'b00)? actualLSResult:dbusWire1;
assign dbusWire1_6 = (movBit2)? {dbusWire1_5 << moveImmShftAmtWire1}: dbusWire1_5;
assign potentialNBit = (dbusWire1[63] == 1'b1)? 1'b1:1'b0;
assign potentialZBit = (ZBit)? 1'b1:1'b0;
assign potentialVBit = (overflowWire)? 1'b1:1'b0;
assign potentialCBit = (ALUCoutWire)? 1'b1:1'b0;
assign NZVC[3] = (NZVCSetBitWire1)? potentialNBit:1'bz;
assign NZVC[2] = (NZVCSetBitWire1)? potentialZBit:1'bz;
assign NZVC[1] = (NZVCSetBitWire1)? potentialVBit:1'bz;
assign NZVC[0] = (NZVCSetBitWire1)? potentialCBit:1'bz;
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_6),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2),
.NOPWire1(NOPWire1),.NOPWire2(NOPWire2));
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 64'hzzzzzzzz;
assign daddrbus = dbusWire2;
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),
.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),
.branchControlBitWire3(branchControlBitWire3),.NOPWire2(NOPWire2),.NOPWire3(NOPWire3));
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = ((lwSwFlag4 == 2'b10) ||(branchControlBitWire3 > 3'b000) || (NOPWire3 == 1'b1))? 32'h80000000: DselectWire3_5;
endmodule | module ARMS(ibus,clk,daddrbus,databus,reset,iaddrbus); |
input clk;
input reset;
output [63:0] iaddrbus;
wire [63:0] iaddrbusWire1;
wire [63:0] iaddrbusWire2;
wire [63:0] iaddrbusWire4;
reg [1:0] setControlBits;
wire [1:0] setControlBitsWire1;
wire [1:0] setControlBitsWire2;
wire ZBit;
wire [63:0] potentialSLEBit;
wire [63:0] potentialSLTBit;
wire [63:0] actualSLBit;
wire ALUCoutWire;
wire overflowWire;
reg [2:0] branchControlBit;
wire [2:0] branchControlBitWire1;
wire [2:0] branchControlBitWire2;
wire [2:0] branchControlBitWire3;
reg takeBranch;
wire takeBranchWire1;
wire takeCondBranchWire1;
wire [63:0] PCWire1;
wire [63:0] branchCalcWire1;
wire [63:0] branchCalcWire2;
output [63:0] daddrbus;
inout [63:0] databus;
wire [10:0] opCode;
reg NOP;
wire NOPWire1;
wire NOPWire2;
wire NOPWire3;
input [31:0] ibus;
wire [31:0] ibusWire;
wire [31:0] AselectWire;
wire [31:0] AselectWire1;
wire [5:0] rn;
wire [31:0] BselectWire;
wire [31:0] BselectWire1;
wire [31:0] BselectWire2;
wire [5:0] rm;
reg movBit1;
wire movBit2;
wire [5:0] moveImmShftAmt;
wire [5:0] moveImmShftAmtWire1;
reg immBit1;
wire immBit2;
wire [3:0]NZVC;
wire potentialNBit;
wire potentialZBit;
wire potentialVBit;
wire potentialCBit;
reg NZVCSetBit;
wire NZVCSetBitWire1;
reg [1:0] shiftBit1;
wire [1:0] shiftBit2;
wire [63:0] potentialLSLResult;
wire [63:0] potentialLSRResult;
wire [63:0] actualLSResult;
reg [1:0] lwSwFlag1;
wire [1:0] lwSwFlag2;
wire [1:0] lwSwFlag3;
wire [1:0] lwSwFlag4;
wire [31:0] DselectWire1;
wire [5:0] rd;
wire [31:0] DselectWire2;
wire [31:0] DselectWire3;
wire [31:0] DselectWire3_5;
wire [31:0] DselectWire4;
wire [63:0] abusWire1;
wire [63:0] abusWire2;
wire [63:0] bbusWire1;
wire [63:0] bbusWire2;
wire [63:0] bbusWire3;
wire [63:0] bbusWire3_5;
wire [63:0] bbusWire4;
wire [63:0] dbusWire1;
wire [63:0] dbusWire1_5;
wire [63:0] dbusWire1_6;
wire [63:0] dbusWire2;
wire [63:0] dbusWire3;
wire [63:0] mux3Out;
wire [63:0] mux2Out;
wire [63:0] mux5;
wire [63:0] mux6;
wire mux4Controller;
wire [63:0] ALUImmWire1;
wire [63:0] ALUImmWire2;
wire [63:0] BranchAddrWire1;
wire [63:0] CondBranchAddrType1Wire1;
wire [63:0] CondBranchAddrType2Wire1;
wire [63:0] MOVImmWire1;
wire [63:0] MOVImmWire2;
wire [5:0] shamt;
wire [5:0] shamtWire1;
wire [63:0] DTAddrWire1;
wire [63:0] DTAddrWire2;
wire [63:0] DTAddrWire3;
wire [63:0] DTAddrWire4;
reg [2:0] SWire1;
wire [2:0] SWire2;
reg CinWire1;
wire CinWire2;
initial begin
immBit1 = 1'bx;
movBit1 = 1'bx;
NZVCSetBit = 1'bx;
CinWire1 = 1'bx;
SWire1 = 3'bxxx;
lwSwFlag1 = 2'bxx;
branchControlBit = 3'b0;
setControlBits = 2'b00;
shiftBit1 = 2'bxx;
takeBranch = 1'b0;
NOP = 1'bx;
end
pipeline_0_latch PC(.clk(clk),.iaddrbusWire1(iaddrbusWire1),.iaddrbusOut(iaddrbusWire2),.reset(reset));
assign iaddrbusWire4 = iaddrbusWire2;
assign iaddrbusWire1 = mux4Controller? branchCalcWire2 : iaddrbusWire2;
assign iaddrbus = iaddrbusWire1;
pipeline_1_latch IF_ID(.clk(clk),.ibus(ibus),.ibusWire(ibusWire),.PCIn(iaddrbusWire4),.PCOut(PCWire1));
assign opCode = ibusWire[31:21];
assign rn = ibusWire[9:5];
assign rm = ibusWire[20:16];
assign rd = ibusWire[4:0];
assign shamt = ibusWire[15:10];
assign DTAddrWire1 = ibusWire[20]? {55'b1,ibusWire[20:12]} : {55'b0,ibusWire[20:12]};
assign moveImmShftAmt = ibusWire[22:21] << 4;
assign ALUImmWire1 = {52'b0, ibusWire[21:10]};
assign BranchAddrWire1 = ibusWire[25]? {36'b1111,ibusWire[25:0],2'b00} : {36'b0000,ibusWire[25:0],2'b00};
assign CondBranchAddrType1Wire1 = ibusWire[23]? {43'b11111111111,ibusWire[23:5],2'b00} : {43'b00000000000,ibusWire[23:5],2'b00};
assign MOVImmWire1= {48'b0, ibusWire[20:5]};
always @(ibusWire) begin
immBit1 = 0;
movBit1 = 0;
CinWire1 = 0;
branchControlBit = 3'b000;
setControlBits = 0;
NZVCSetBit = 0;
lwSwFlag1 = 2'b00;
shiftBit1 = 2'b00;
NOP = 1'b0;
casez (opCode)
11'b10001011000: begin
SWire1 = 3'b010;
end
11'b1001000100?: begin
SWire1 = 3'b010;
immBit1 = 1;
end
11'b1011000100?: begin
SWire1 = 3'b010;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b10101011000: begin
SWire1 = 3'b010;
NZVCSetBit = 1;
end
11'b10001010000: begin
SWire1 = 3'b110;
end
11'b1001001000?: begin
SWire1 = 3'b110;
immBit1 = 1;
end
11'b1111001000?: begin
SWire1 = 3'b110;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b11101010000: begin
SWire1 = 3'b110;
NZVCSetBit = 1;
end
11'b10110101???: begin
SWire1 = 3'b010;
branchControlBit = 3'b110;
end
11'b10110100???: begin
SWire1 = 3'b010;
branchControlBit = 3'b111;
end
11'b11001010000: begin
SWire1 = 3'b000;
end
11'b1101001000?: begin
SWire1 = 3'b000;
immBit1 = 1;
end
11'b11111000010: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b01;
end
11'b11010011011: begin
shiftBit1 = 2'b01;
SWire1 = 3'b010;
end
11'b11010011010: begin
shiftBit1 = 2'b10;
SWire1 = 3'b010;
end
11'b110100101??: begin
movBit1 = 1;
SWire1 = 3'b100;
end
11'b10101010000: begin
SWire1 = 3'b100;
end
11'b1011001000?: begin
SWire1 = 3'b100;
immBit1 = 1;
end
11'b11111000000: begin
SWire1 = 3'b010;
lwSwFlag1 = 2'b10;
end
11'b11001011000: begin
SWire1 = 3'b011;
CinWire1 = 1;
end
11'b1101000100?: begin
SWire1 = 3'b011;
CinWire1 = 1;
immBit1 = 1;
end
11'b1111000100?: begin
SWire1 = 3'b011;
CinWire1 = 1;
immBit1 = 1;
NZVCSetBit = 1;
end
11'b11101011000: begin
SWire1 = 3'b011;
CinWire1 = 1;
NZVCSetBit = 1;
end
11'b000101?????: begin
SWire1 = 3'b010;
branchControlBit = 3'b001;
end
11'b01010101???: begin
SWire1 = 3'b010;
branchControlBit = 3'b010;
end
11'b01010110???: begin
SWire1 = 3'b010;
branchControlBit = 3'b011;
end
11'b01010111???: begin
SWire1 = 3'b010;
branchControlBit = 3'b100;
end
11'b01011000???: begin
SWire1 = 3'b010;
branchControlBit = 3'b101;
end
11'b00000000000: begin
SWire1 = 3'b010;
NOP = 1'b1;
end
endcase
end
always@(negedge clk) begin
takeBranch = 1'b0;
case (branchControlBit)
3'b000: begin
takeBranch = 0;
end
3'b001: begin
takeBranch = 1;
end
3'b010: begin
takeBranch = (NZVC[2] == 1'b1)? 1:0;
end
3'b011: begin
takeBranch = (NZVC[2] == 1'b0)? 1:0;
end
3'b100: begin
takeBranch = (NZVC[3] != NZVC[1])? 1:0;
end
3'b101: begin
takeBranch = (NZVC[3] == NZVC[1])? 1:0;
end
3'b110: begin
takeBranch = (abusWire1 != 0)? 1:0;
end
3'b111: begin
takeBranch = (abusWire1 == 0)? 1:0;
end
endcase
end
assign AselectWire = ((branchControlBit == 3'b110) || (branchControlBit == 3'b111))? 1<<rd :1 << rn;
assign AselectWire1 = (movBit1)? 32'h80000000 : AselectWire;
assign BselectWire = 1 << rm;
assign BselectWire1 = ((shiftBit1 > 2'b00) || (movBit1))? 32'h80000000:BselectWire;
assign BselectWire2 = (lwSwFlag1 == 2'b10)? 1<<rd:BselectWire1;
assign DselectWire1 = 1<<rd;
regfile Reggie3(.clk(clk),.Aselect(AselectWire1),.Bselect(BselectWire2),.Dselect(DselectWire4),.abus(abusWire1),.bbus(bbusWire1),.dbus(mux3Out));
assign takeBranchWire1 = takeBranch;
assign mux4Controller = ((!clk) && (branchControlBit > 3'b000) && (takeBranchWire1))? 1 : 0;
assign branchCalcWire1 = (branchControlBit == 3'b001)? BranchAddrWire1:CondBranchAddrType1Wire1;
assign branchCalcWire2 = branchCalcWire1 + PCWire1 - 4;
pipeline_2_latch ED_EX(.clk(clk),.abusWire1(abusWire1),.bbusWire1(bbusWire1),.DselectWire1(DselectWire1),.ALUImmWire1(ALUImmWire1),.SWire1(SWire1),
.CinWire1(CinWire1),.immBit1(immBit1),.lwSwFlag1(lwSwFlag1),.abusWire2(abusWire2),.bbusWire2(bbusWire2),.ALUImmWire2(ALUImmWire2),.CinWire2(CinWire2),
.DselectWire2(DselectWire2),.immBit2(immBit2),.SWire2,.lwSwFlag2(lwSwFlag2),.setControlBits(setControlBits),.setControlBitsWire1(setControlBitsWire1),
.branchControlBit(branchControlBit),.branchControlBitWire1(branchControlBitWire1),.NZVCSetBit(NZVCSetBit),.NZVCSetBitWire1(NZVCSetBitWire1),
.shiftBit1(shiftBit1),.shiftBit2(shiftBit2),.shamt(shamt),.shamtWire1(shamtWire1),.DTAddrWire1(DTAddrWire1),.DTAddrWire2(DTAddrWire2),
.MOVImmWire1(MOVImmWire1),.MOVImmWire2(MOVImmWire2),.movBit1(movBit1),.movBit2(movBit2),.moveImmShftAmt(moveImmShftAmt),
.moveImmShftAmtWire1(moveImmShftAmtWire1),.NOP(NOP),.NOPWire1(NOPWire1));
assign mux2Out = immBit2? ALUImmWire2: bbusWire2;
assign mux5 = (lwSwFlag2 > 2'b00)? DTAddrWire2:mux2Out;
assign mux6 = (movBit2)? MOVImmWire2:mux5;
alu64 literallyLogic(.d(dbusWire1),.a(abusWire2),.b(mux6),.Cin(CinWire2),.S(SWire2),.Cout(ALUCoutWire),.V(overflowWire));
assign ZBit = (dbusWire1==0)? 1:0;
assign potentialSLTBit = (!ALUCoutWire && !ZBit)? 64'h0000000000000001:64'h0000000000000000;
assign potentialSLEBit = (!ALUCoutWire || ZBit)? 64'h0000000000000001:64'h0000000000000000;
assign actualSLBit = (setControlBitsWire1 == 2'b01)? potentialSLTBit: potentialSLEBit;
assign potentialLSLResult = dbusWire1 << shamtWire1;
assign potentialLSRResult = dbusWire1 >> shamtWire1;
assign actualLSResult = (shiftBit2 == 2'b10)? potentialLSRResult:potentialLSLResult;
assign dbusWire1_5 = (shiftBit2 > 2'b00)? actualLSResult:dbusWire1;
assign dbusWire1_6 = (movBit2)? {dbusWire1_5 << moveImmShftAmtWire1}: dbusWire1_5;
assign potentialNBit = (dbusWire1[63] == 1'b1)? 1'b1:1'b0;
assign potentialZBit = (ZBit)? 1'b1:1'b0;
assign potentialVBit = (overflowWire)? 1'b1:1'b0;
assign potentialCBit = (ALUCoutWire)? 1'b1:1'b0;
assign NZVC[3] = (NZVCSetBitWire1)? potentialNBit:1'bz;
assign NZVC[2] = (NZVCSetBitWire1)? potentialZBit:1'bz;
assign NZVC[1] = (NZVCSetBitWire1)? potentialVBit:1'bz;
assign NZVC[0] = (NZVCSetBitWire1)? potentialCBit:1'bz;
pipeline_3_latch EX_MEME (.clk(clk),.dbusWire1(dbusWire1_6),.DselectWire2(DselectWire2),.bbusWire2(bbusWire2),.lwSwFlag2(lwSwFlag2),.dbusWire2(dbusWire2),
.DselectWire3(DselectWire3),.bbusWire3(bbusWire3),.lwSwFlag3(lwSwFlag3),.branchControlBitWire1(branchControlBitWire1),.branchControlBitWire2(branchControlBitWire2),
.NOPWire1(NOPWire1),.NOPWire2(NOPWire2));
assign bbusWire3_5 = (lwSwFlag3==2'b01)? databus: bbusWire3;
assign databus = (lwSwFlag3 == 2'b10)? bbusWire3: 64'hzzzzzzzz;
assign daddrbus = dbusWire2;
pipeline_4_latch MEM_WB (.clk(clk),.dbusWire2(dbusWire2),.DselectWire3(DselectWire3),.bbusWire3(bbusWire3_5),.lwSwFlag3(lwSwFlag3),.dbusWire3(dbusWire3),
.DselectWire4(DselectWire3_5),.bbusWire4(bbusWire4),.lwSwFlag4(lwSwFlag4),.branchControlBitWire2(branchControlBitWire2),
.branchControlBitWire3(branchControlBitWire3),.NOPWire2(NOPWire2),.NOPWire3(NOPWire3));
assign mux3Out = (lwSwFlag4 == 2'b01)? bbusWire4:dbusWire3;
assign DselectWire4 = ((lwSwFlag4 == 2'b10) ||(branchControlBitWire3 > 3'b000) || (NOPWire3 == 1'b1))? 32'h80000000: DselectWire3_5;
endmodule | 0 |
141,146 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset);
input clk, reset;
input [63:0] iaddrbusWire1;
output [63:0] iaddrbusOut;
reg [63:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule | module pipeline_0_latch(clk, iaddrbusWire1, iaddrbusOut, reset); |
input clk, reset;
input [63:0] iaddrbusWire1;
output [63:0] iaddrbusOut;
reg [63:0] iaddrbusOut;
reg startBit;
initial begin
startBit = 1;
end
always@(posedge clk) begin
iaddrbusOut = (reset|startBit)? 0:iaddrbusWire1+4;
startBit = 0;
end
endmodule | 0 |
141,147 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut);
input [31:0] ibus;
input [63:0] PCIn;
input clk;
output [31:0] ibusWire;
output [63:0] PCOut;
reg [31:0] ibusWire;
reg [63:0] PCOut;
always @(posedge clk) begin
ibusWire = ibus;
PCOut = PCIn;
end
endmodule | module pipeline_1_latch(clk, ibus, ibusWire, PCIn, PCOut); |
input [31:0] ibus;
input [63:0] PCIn;
input clk;
output [31:0] ibusWire;
output [63:0] PCOut;
reg [31:0] ibusWire;
reg [63:0] PCOut;
always @(posedge clk) begin
ibusWire = ibus;
PCOut = PCIn;
end
endmodule | 0 |
141,148 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, ALUImmWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,ALUImmWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1,NZVCSetBit,NZVCSetBitWire1,shiftBit1,shiftBit2,shamt,shamtWire1,DTAddrWire1,
DTAddrWire2,MOVImmWire1,MOVImmWire2,movBit1,movBit2,moveImmShftAmt,moveImmShftAmtWire1,NOP,NOPWire1);
input clk, CinWire1,immBit1,NOP;
input [63:0] abusWire1, bbusWire1, ALUImmWire1,DTAddrWire1,MOVImmWire1;
input [31:0] DselectWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [2:0] branchControlBit;
input NZVCSetBit;
input [1:0] shiftBit1;
input [5:0] shamt,moveImmShftAmt;
input movBit1;
output CinWire2,immBit2,NOPWire1;
output [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
output [31:0] DselectWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [2:0] branchControlBitWire1;
output NZVCSetBitWire1;
output [1:0] shiftBit2;
output [5:0] shamtWire1,moveImmShftAmtWire1;
output movBit2;
reg CinWire2,immBit2,NOPWire1;
reg [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
reg [31:0] DselectWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [2:0] branchControlBitWire1;
reg NZVCSetBitWire1;
reg [1:0] shiftBit2;
reg [5:0] shamtWire1,moveImmShftAmtWire1;
reg movBit2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
ALUImmWire2 = ALUImmWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
NZVCSetBitWire1 = NZVCSetBit;
shiftBit2 = shiftBit1;
shamtWire1 = shamt;
DTAddrWire2 = DTAddrWire1;
MOVImmWire2 = MOVImmWire1;
movBit2 = movBit1;
moveImmShftAmtWire1 = moveImmShftAmt;
NOPWire1 = NOP;
end
endmodule | module pipeline_2_latch(clk, abusWire1, bbusWire1, DselectWire1, ALUImmWire1, SWire1, CinWire1,immBit1,lwSwFlag1,
abusWire2,bbusWire2,ALUImmWire2,SWire2,CinWire2,DselectWire2,immBit2,lwSwFlag2,setControlBits,setControlBitsWire1,
branchControlBit,branchControlBitWire1,NZVCSetBit,NZVCSetBitWire1,shiftBit1,shiftBit2,shamt,shamtWire1,DTAddrWire1,
DTAddrWire2,MOVImmWire1,MOVImmWire2,movBit1,movBit2,moveImmShftAmt,moveImmShftAmtWire1,NOP,NOPWire1); |
input clk, CinWire1,immBit1,NOP;
input [63:0] abusWire1, bbusWire1, ALUImmWire1,DTAddrWire1,MOVImmWire1;
input [31:0] DselectWire1;
input [2:0] SWire1;
input [1:0] lwSwFlag1;
input [1:0] setControlBits;
input [2:0] branchControlBit;
input NZVCSetBit;
input [1:0] shiftBit1;
input [5:0] shamt,moveImmShftAmt;
input movBit1;
output CinWire2,immBit2,NOPWire1;
output [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
output [31:0] DselectWire2;
output [2:0] SWire2;
output [1:0] lwSwFlag2;
output [1:0] setControlBitsWire1;
output [2:0] branchControlBitWire1;
output NZVCSetBitWire1;
output [1:0] shiftBit2;
output [5:0] shamtWire1,moveImmShftAmtWire1;
output movBit2;
reg CinWire2,immBit2,NOPWire1;
reg [63:0] abusWire2, bbusWire2, ALUImmWire2,DTAddrWire2,MOVImmWire2;
reg [31:0] DselectWire2;
reg [2:0] SWire2;
reg [1:0] lwSwFlag2;
reg [1:0] setControlBitsWire1;
reg [2:0] branchControlBitWire1;
reg NZVCSetBitWire1;
reg [1:0] shiftBit2;
reg [5:0] shamtWire1,moveImmShftAmtWire1;
reg movBit2;
always @(posedge clk) begin
abusWire2 = abusWire1;
bbusWire2 = bbusWire1;
DselectWire2 = DselectWire1;
ALUImmWire2 = ALUImmWire1;
SWire2 = SWire1;
CinWire2 = CinWire1;
immBit2 = immBit1;
lwSwFlag2 = lwSwFlag1;
setControlBitsWire1 = setControlBits;
branchControlBitWire1 = branchControlBit;
NZVCSetBitWire1 = NZVCSetBit;
shiftBit2 = shiftBit1;
shamtWire1 = shamt;
DTAddrWire2 = DTAddrWire1;
MOVImmWire2 = MOVImmWire1;
movBit2 = movBit1;
moveImmShftAmtWire1 = moveImmShftAmt;
NOPWire1 = NOP;
end
endmodule | 0 |
141,149 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,
branchControlBitWire2,NOPWire1,NOPWire2);
input clk;
input [63:0] dbusWire1, bbusWire2;
input [31:0] DselectWire2;
input [1:0] lwSwFlag2;
input [2:0] branchControlBitWire1;
input NOPWire1;
output [63:0] dbusWire2, bbusWire3;
output [31:0] DselectWire3;
output [1:0] lwSwFlag3;
output [2:0] branchControlBitWire2;
output NOPWire2;
reg [63:0] dbusWire2, bbusWire3;
reg [31:0] DselectWire3;
reg [1:0] lwSwFlag3;
reg [2:0] branchControlBitWire2;
reg NOPWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
NOPWire2 = NOPWire1;
end
endmodule | module pipeline_3_latch(clk, dbusWire1, DselectWire2, bbusWire2, lwSwFlag2, dbusWire2, DselectWire3,bbusWire3,lwSwFlag3,branchControlBitWire1,
branchControlBitWire2,NOPWire1,NOPWire2); |
input clk;
input [63:0] dbusWire1, bbusWire2;
input [31:0] DselectWire2;
input [1:0] lwSwFlag2;
input [2:0] branchControlBitWire1;
input NOPWire1;
output [63:0] dbusWire2, bbusWire3;
output [31:0] DselectWire3;
output [1:0] lwSwFlag3;
output [2:0] branchControlBitWire2;
output NOPWire2;
reg [63:0] dbusWire2, bbusWire3;
reg [31:0] DselectWire3;
reg [1:0] lwSwFlag3;
reg [2:0] branchControlBitWire2;
reg NOPWire2;
always @(posedge clk) begin
dbusWire2 = dbusWire1;
DselectWire3 = DselectWire2;
bbusWire3 = bbusWire2;
lwSwFlag3 = lwSwFlag2;
branchControlBitWire2 = branchControlBitWire1;
NOPWire2 = NOPWire1;
end
endmodule | 0 |
141,150 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,
branchControlBitWire3,NOPWire2,NOPWire3);
input clk;
input [63:0] dbusWire2, bbusWire3;
input [31:0] DselectWire3;
input [1:0] lwSwFlag3;
input [2:0] branchControlBitWire2;
input NOPWire2;
output [63:0] dbusWire3, bbusWire4;
output [31:0] DselectWire4;
output [1:0] lwSwFlag4;
output [2:0] branchControlBitWire3;
output NOPWire3;
reg [63:0] dbusWire3, bbusWire4;
reg [31:0] DselectWire4;
reg [1:0] lwSwFlag4;
reg [2:0] branchControlBitWire3;
reg NOPWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
NOPWire3 = NOPWire2;
end
endmodule | module pipeline_4_latch(clk, dbusWire2, DselectWire3, bbusWire3, lwSwFlag3, dbusWire3, DselectWire4,bbusWire4,lwSwFlag4,branchControlBitWire2,
branchControlBitWire3,NOPWire2,NOPWire3); |
input clk;
input [63:0] dbusWire2, bbusWire3;
input [31:0] DselectWire3;
input [1:0] lwSwFlag3;
input [2:0] branchControlBitWire2;
input NOPWire2;
output [63:0] dbusWire3, bbusWire4;
output [31:0] DselectWire4;
output [1:0] lwSwFlag4;
output [2:0] branchControlBitWire3;
output NOPWire3;
reg [63:0] dbusWire3, bbusWire4;
reg [31:0] DselectWire4;
reg [1:0] lwSwFlag4;
reg [2:0] branchControlBitWire3;
reg NOPWire3;
always @(posedge clk) begin
dbusWire3 = dbusWire2;
DselectWire4 = DselectWire3;
bbusWire4 = bbusWire3;
lwSwFlag4 = lwSwFlag3;
branchControlBitWire3 = branchControlBitWire2;
NOPWire3 = NOPWire2;
end
endmodule | 0 |
141,151 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [63:0] dbus,
output [63:0] abus,
output [63:0] bbus,
input clk
);
assign abus = Aselect[31] ? 64'b0 : 64'bz;
assign bbus = Bselect[31] ? 64'b0 : 64'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[30:0]),
.Bselect(Bselect[30:0]),
.Aselect(Aselect[30:0]),
.bbus(bbus),
.clk(clk)
);
endmodule | module regfile(
input [31:0] Aselect,
input [31:0] Bselect,
input [31:0] Dselect,
input [63:0] dbus,
output [63:0] abus,
output [63:0] bbus,
input clk
); |
assign abus = Aselect[31] ? 64'b0 : 64'bz;
assign bbus = Bselect[31] ? 64'b0 : 64'bz;
DNegflipFlop myFlips[30:0](
.dbus(dbus),
.abus(abus),
.Dselect(Dselect[30:0]),
.Bselect(Bselect[30:0]),
.Aselect(Aselect[30:0]),
.bbus(bbus),
.clk(clk)
);
endmodule | 0 |
141,152 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk);
input [63:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [63:0] abus;
output [63:0] bbus;
wire wireclk;
reg [63:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 64'h0000000000000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 64'hzzzzzzzzzzzzzzzz;
assign bbus = Bselect? data : 64'hzzzzzzzzzzzzzzzz;
endmodule | module DNegflipFlop(dbus, abus, Dselect, Bselect, Aselect, bbus, clk); |
input [63:0] dbus;
input Dselect;
input Bselect;
input Aselect;
input clk;
output [63:0] abus;
output [63:0] bbus;
wire wireclk;
reg [63:0] data;
assign wireclk = clk & Dselect;
initial begin
data = 64'h0000000000000000;
end
always @(negedge clk) begin
if(Dselect) begin
data = dbus;
end
end
assign abus = Aselect? data : 64'hzzzzzzzzzzzzzzzz;
assign bbus = Bselect? data : 64'hzzzzzzzzzzzzzzzz;
endmodule | 0 |
141,153 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module alu64 (d, Cout, V, a, b, Cin, S);
output[63:0] d;
output Cout, V;
input [63:0] a, b;
input Cin;
input [2:0] S;
wire [63:0] c, g, p;
wire gout, pout;
alu_cell mycell[63:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac6 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[63]),
.Cin(Cin)
);
endmodule | module alu64 (d, Cout, V, a, b, Cin, S); |
output[63:0] d;
output Cout, V;
input [63:0] a, b;
input Cin;
input [2:0] S;
wire [63:0] c, g, p;
wire gout, pout;
alu_cell mycell[63:0] (
.d(d),
.g(g),
.p(p),
.a(a),
.b(b),
.c(c),
.S(S)
);
lac6 lac(
.c(c),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(g),
.p(p)
);
overflow ov(
.Cout(Cout),
.V(V),
.g(gout),
.p(pout),
.c31(c[63]),
.Cin(Cin)
);
endmodule | 0 |
141,154 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module alu_cell (d, g, p, a, b, c, S);
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | module alu_cell (d, g, p, a, b, c, S); |
output d, g, p;
input a, b, c;
input [2:0] S;
reg g,p,d,cint,bint;
always @(a,b,c,S,p,g) begin
bint = S[0] ^ b;
g = a & bint;
p = a ^ bint;
cint = S[1] & c;
if(S[2]==0)
begin
d = p ^ cint;
end
else if(S[2]==1)
begin
if((S[1]==0) & (S[0]==0)) begin
d = a | b;
end
else if ((S[1]==0) & (S[0]==1)) begin
d = ~(a|b);
end
else if ((S[1]==1) & (S[0]==0)) begin
d = a&b;
end
else
d = 1;
end
end
endmodule | 0 |
141,155 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module overflow (Cout, V, g, p, c31, Cin);
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | module overflow (Cout, V, g, p, c31, Cin); |
output Cout, V;
input g, p, c31, Cin;
assign Cout = g|(p&Cin);
assign V = Cout^c31;
endmodule | 0 |
141,156 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac(c, gout, pout, Cin, g, p);
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | module lac(c, gout, pout, Cin, g, p); |
output [1:0] c;
output gout;
output pout;
input Cin;
input [1:0] g;
input [1:0] p;
assign c[0] = Cin;
assign c[1] = g[0] | ( p[0] & Cin );
assign gout = g[1] | ( p[1] & g[0] );
assign pout = p[1] & p[0];
endmodule | 0 |
141,157 | data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v | 93,595,154 | ARMS_final.v | v | 1,044 | 167 | [] | [] | [] | null | line:489: before: "," | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:199: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rn = ibusWire[9:5]; \n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:200: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rm = ibusWire[20:16]; \n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:201: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS\'s SEL generates 5 bits.\n : ... In instance ARMS\n assign rd = ibusWire[4:0];\n ^\n%Warning-WIDTH: data/full_repos/permissive/93595154/assignment_8_p2_final/ARMS_final.v:204: Operator SHIFTL expects 6 bits on the LHS, but LHS\'s SEL generates 2 bits.\n : ... In instance ARMS\n assign moveImmShftAmt = ibusWire[22:21] << 4;\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 310,904 | module | module lac2 (c, gout, pout, Cin, g, p);
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | module lac2 (c, gout, pout, Cin, g, p); |
output [3:0] c;
output gout, pout;
input Cin;
input [3:0] g, p;
wire [1:0] cint, gint, pint;
lac leaf0(
.c(c[1:0]),
.gout(gint[0]),
.pout(pint[0]),
.Cin(cint[0]),
.g(g[1:0]),
.p(p[1:0])
);
lac leaf1(
.c(c[3:2]),
.gout(gint[1]),
.pout(pint[1]),
.Cin(cint[1]),
.g(g[3:2]),
.p(p[3:2])
);
lac root(
.c(cint),
.gout(gout),
.pout(pout),
.Cin(Cin),
.g(gint),
.p(pint)
);
endmodule | 0 |
Subsets and Splits