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142,108 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_Delay(clk, reset, d, q);
parameter WIDTH=1;
parameter DELAY=1;
input clk;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [(WIDTH*DELAY)-1:0] reg_inputs;
wire [(WIDTH*DELAY)-1:0] reg_outputs;
genvar i;
generate
for (i = 0; i < DELAY; i = i + 1)
begin: DFF_CHAIN
CC_DFlipFlop #(WIDTH) chain_reg(.clk(clk),
.en(1'b1),
.reset(reset),
.d(reg_inputs[(i+1)*WIDTH-1:i*WIDTH]),
.q(reg_outputs[(i+1)*WIDTH-1:i*WIDTH]));
if (i < DELAY - 1) begin
assign reg_inputs[(i+2)*WIDTH-1:(i+1)*WIDTH] =
reg_outputs[(i+1)*WIDTH-1:i*WIDTH];
end
end
endgenerate
assign q = reg_outputs[(DELAY*WIDTH)-1:(DELAY-1)*WIDTH];
assign reg_inputs[WIDTH-1:0] = d;
endmodule | module CC_Delay(clk, reset, d, q); |
parameter WIDTH=1;
parameter DELAY=1;
input clk;
input reset;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [(WIDTH*DELAY)-1:0] reg_inputs;
wire [(WIDTH*DELAY)-1:0] reg_outputs;
genvar i;
generate
for (i = 0; i < DELAY; i = i + 1)
begin: DFF_CHAIN
CC_DFlipFlop #(WIDTH) chain_reg(.clk(clk),
.en(1'b1),
.reset(reset),
.d(reg_inputs[(i+1)*WIDTH-1:i*WIDTH]),
.q(reg_outputs[(i+1)*WIDTH-1:i*WIDTH]));
if (i < DELAY - 1) begin
assign reg_inputs[(i+2)*WIDTH-1:(i+1)*WIDTH] =
reg_outputs[(i+1)*WIDTH-1:i*WIDTH];
end
end
endgenerate
assign q = reg_outputs[(DELAY*WIDTH)-1:(DELAY-1)*WIDTH];
assign reg_inputs[WIDTH-1:0] = d;
endmodule | 0 |
142,109 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_DLatch(en, d, q);
parameter WIDTH=1;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [WIDTH-1:0] reg_out;
CC_DFlipFlop #(WIDTH) r(.clk(~en), .en(1'b1), .reset(0), .d(d), .q(reg_out));
assign q = en ? d : reg_out;
endmodule | module CC_DLatch(en, d, q); |
parameter WIDTH=1;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
wire [WIDTH-1:0] reg_out;
CC_DFlipFlop #(WIDTH) r(.clk(~en), .en(1'b1), .reset(0), .d(d), .q(reg_out));
assign q = en ? d : reg_out;
endmodule | 0 |
142,110 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_Bidir(sel_in, io, in, out);
parameter WIDTH=1;
input sel_in;
inout [WIDTH-1:0] io;
output [WIDTH-1:0] in;
input [WIDTH-1:0] out;
assign in = sel_in ? io : {WIDTH{1'bz}};
assign io = sel_in ? {WIDTH{1'bz}} : out;
endmodule | module CC_Bidir(sel_in, io, in, out); |
parameter WIDTH=1;
input sel_in;
inout [WIDTH-1:0] io;
output [WIDTH-1:0] in;
input [WIDTH-1:0] out;
assign in = sel_in ? io : {WIDTH{1'bz}};
assign io = sel_in ? {WIDTH{1'bz}} : out;
endmodule | 0 |
142,111 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_MuxReg(sel, clk, en, in_a, in_b, out);
parameter WIDTH=8;
input sel;
input clk;
input en;
input [WIDTH-1:0] in_a;
input [WIDTH-1:0] in_b;
output [WIDTH-1:0] out;
wire [WIDTH-1:0] out_a;
wire [WIDTH-1:0] out_b;
CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);
CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);
assign out = sel ? out_a : out_b;
endmodule | module CC_MuxReg(sel, clk, en, in_a, in_b, out); |
parameter WIDTH=8;
input sel;
input clk;
input en;
input [WIDTH-1:0] in_a;
input [WIDTH-1:0] in_b;
output [WIDTH-1:0] out;
wire [WIDTH-1:0] out_a;
wire [WIDTH-1:0] out_b;
CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);
CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);
assign out = sel ? out_a : out_b;
endmodule | 0 |
142,112 | data/full_repos/permissive/9705033/common/basics.v | 9,705,033 | basics.v | v | 134 | 80 | [] | ['general public license', 'free software foundation'] | [] | [(21, 36), (39, 69), (72, 83), (86, 96), (99, 116), (119, 133)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:112: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-PINMISSING: data/full_repos/permissive/9705033/common/basics.v:113: Cell has missing pin: \'q\'\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~~\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics.v:72: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'CC_Delay\'\nmodule CC_Delay(clk, reset, d, q);\n ^~~~~~~~\n : ... Top module \'CC_DLatch\'\nmodule CC_DLatch(en, d, q);\n ^~~~~~~~~\n : ... Top module \'CC_Bidir\'\nmodule CC_Bidir(sel_in, io, in, out);\n ^~~~~~~~\n : ... Top module \'CC_MuxReg\'\nmodule CC_MuxReg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n : ... Top module \'CC_Decoder\'\nmodule CC_Decoder(in, out);\n ^~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:112: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_a\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_a(clk, en, in_a, out_a);\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics.v:113: Input port connection \'reset\' expects 1 bits on the pin connection, but pin connection\'s VARREF \'in_b\' generates 8 bits.\n : ... In instance CC_MuxReg\n CC_DFlipFlop #(WIDTH) reg_b(clk, en, in_b, out_b);\n ^~~~\n%Error: Exiting due to 5 warning(s)\n' | 313,055 | module | module CC_Decoder(in, out);
parameter IN_WIDTH=8;
parameter OUT_WIDTH=(1 << IN_WIDTH);
input [IN_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
genvar i;
generate
for (i = 0; i < OUT_WIDTH; i = i + 1)
begin: SELECT
assign out[i] = (i == in) ? 1'b1 : 1'b0;
end
endgenerate
endmodule | module CC_Decoder(in, out); |
parameter IN_WIDTH=8;
parameter OUT_WIDTH=(1 << IN_WIDTH);
input [IN_WIDTH-1:0] in;
output [OUT_WIDTH-1:0] out;
genvar i;
generate
for (i = 0; i < OUT_WIDTH; i = i + 1)
begin: SELECT
assign out[i] = (i == in) ? 1'b1 : 1'b0;
end
endgenerate
endmodule | 0 |
142,113 | data/full_repos/permissive/9705033/common/basics_test.v | 9,705,033 | basics_test.v | v | 167 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(22, 50), (52, 82), (85, 111), (114, 146), (149, 166)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #3 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n #4 sel_in = ~sel_in;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #7 sel = ~sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n #6 in_a = in_a + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 in_b = in_b + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1 in = in + 1;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics_test.v:52: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'RegLatchTest\'\nmodule RegLatchTest;\n ^~~~~~~~~~~~\n : ... Top module \'RegDelayTest\'\nmodule RegDelayTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_BidirTest\'\nmodule CC_BidirTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_MuxRegTest\'\nmodule CC_MuxRegTest;\n ^~~~~~~~~~~~~\n : ... Top module \'CC_DecoderTest\'\nmodule CC_DecoderTest;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:158: Cannot find file containing module: \'CC_Decoder\'\n CC_Decoder #(WIDTH) decoder(.in(in), .out(out));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.sv\n CC_Decoder\n CC_Decoder.v\n CC_Decoder.sv\n obj_dir/CC_Decoder\n obj_dir/CC_Decoder.v\n obj_dir/CC_Decoder.sv\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:121: Cannot find file containing module: \'CC_MuxReg\'\n CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:89: Cannot find file containing module: \'CC_Bidir\'\n CC_Bidir #(4) bidir(sel_in, port, in, out);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'count_in\' generates 4 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:64: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:65: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:66: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:32: Cannot find file containing module: \'CC_DFlipFlop\'\n CC_DFlipFlop #(4) register(clk, en, data, rout);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:33: Cannot find file containing module: \'CC_DLatch\'\n CC_DLatch #(4) latch(en, data, lout);\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,056 | module | module RegLatchTest;
reg en, clk;
reg [3:0] data;
wire [3:0] rout;
wire [3:0] lout;
CC_DFlipFlop #(4) register(clk, en, data, rout);
CC_DLatch #(4) latch(en, data, lout);
initial begin
en = 0;
data = 'b0;
clk = 0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#2 data = data + 1;
endmodule | module RegLatchTest; |
reg en, clk;
reg [3:0] data;
wire [3:0] rout;
wire [3:0] lout;
CC_DFlipFlop #(4) register(clk, en, data, rout);
CC_DLatch #(4) latch(en, data, lout);
initial begin
en = 0;
data = 'b0;
clk = 0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#2 data = data + 1;
endmodule | 0 |
142,114 | data/full_repos/permissive/9705033/common/basics_test.v | 9,705,033 | basics_test.v | v | 167 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(22, 50), (52, 82), (85, 111), (114, 146), (149, 166)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #3 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n #4 sel_in = ~sel_in;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #7 sel = ~sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n #6 in_a = in_a + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 in_b = in_b + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1 in = in + 1;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics_test.v:52: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'RegLatchTest\'\nmodule RegLatchTest;\n ^~~~~~~~~~~~\n : ... Top module \'RegDelayTest\'\nmodule RegDelayTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_BidirTest\'\nmodule CC_BidirTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_MuxRegTest\'\nmodule CC_MuxRegTest;\n ^~~~~~~~~~~~~\n : ... Top module \'CC_DecoderTest\'\nmodule CC_DecoderTest;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:158: Cannot find file containing module: \'CC_Decoder\'\n CC_Decoder #(WIDTH) decoder(.in(in), .out(out));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.sv\n CC_Decoder\n CC_Decoder.v\n CC_Decoder.sv\n obj_dir/CC_Decoder\n obj_dir/CC_Decoder.v\n obj_dir/CC_Decoder.sv\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:121: Cannot find file containing module: \'CC_MuxReg\'\n CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:89: Cannot find file containing module: \'CC_Bidir\'\n CC_Bidir #(4) bidir(sel_in, port, in, out);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'count_in\' generates 4 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:64: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:65: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:66: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:32: Cannot find file containing module: \'CC_DFlipFlop\'\n CC_DFlipFlop #(4) register(clk, en, data, rout);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:33: Cannot find file containing module: \'CC_DLatch\'\n CC_DLatch #(4) latch(en, data, lout);\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,056 | module | module RegDelayTest;
reg clk;
reg reset;
reg [3:0] data;
wire [3:0] out1;
wire [3:0] out2;
wire [3:0] out3;
CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);
CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);
CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);
initial begin
clk = 0;
reset = 1;
data = 0;
#3 reset = 0;
end
always
#1 clk = ~clk;
always
#2 data = data + 1;
endmodule | module RegDelayTest; |
reg clk;
reg reset;
reg [3:0] data;
wire [3:0] out1;
wire [3:0] out2;
wire [3:0] out3;
CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);
CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);
CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);
initial begin
clk = 0;
reset = 1;
data = 0;
#3 reset = 0;
end
always
#1 clk = ~clk;
always
#2 data = data + 1;
endmodule | 0 |
142,115 | data/full_repos/permissive/9705033/common/basics_test.v | 9,705,033 | basics_test.v | v | 167 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(22, 50), (52, 82), (85, 111), (114, 146), (149, 166)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #3 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n #4 sel_in = ~sel_in;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #7 sel = ~sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n #6 in_a = in_a + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 in_b = in_b + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1 in = in + 1;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics_test.v:52: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'RegLatchTest\'\nmodule RegLatchTest;\n ^~~~~~~~~~~~\n : ... Top module \'RegDelayTest\'\nmodule RegDelayTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_BidirTest\'\nmodule CC_BidirTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_MuxRegTest\'\nmodule CC_MuxRegTest;\n ^~~~~~~~~~~~~\n : ... Top module \'CC_DecoderTest\'\nmodule CC_DecoderTest;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:158: Cannot find file containing module: \'CC_Decoder\'\n CC_Decoder #(WIDTH) decoder(.in(in), .out(out));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.sv\n CC_Decoder\n CC_Decoder.v\n CC_Decoder.sv\n obj_dir/CC_Decoder\n obj_dir/CC_Decoder.v\n obj_dir/CC_Decoder.sv\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:121: Cannot find file containing module: \'CC_MuxReg\'\n CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:89: Cannot find file containing module: \'CC_Bidir\'\n CC_Bidir #(4) bidir(sel_in, port, in, out);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'count_in\' generates 4 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:64: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:65: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:66: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:32: Cannot find file containing module: \'CC_DFlipFlop\'\n CC_DFlipFlop #(4) register(clk, en, data, rout);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:33: Cannot find file containing module: \'CC_DLatch\'\n CC_DLatch #(4) latch(en, data, lout);\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,056 | module | module CC_BidirTest;
reg sel_in;
wire [3:0] port, in, out;
CC_Bidir #(4) bidir(sel_in, port, in, out);
reg [3:0] count_in;
reg [3:0] count_out;
initial begin
sel_in = 0;
count_in = 'b0;
count_out = 'b0;
end
always begin
#1
count_in = count_in + 1;
count_out = count_out - 1;
end
assign port = sel_in ? count_in : 'bz;
assign out = count_out;
always
#4 sel_in = ~sel_in;
endmodule | module CC_BidirTest; |
reg sel_in;
wire [3:0] port, in, out;
CC_Bidir #(4) bidir(sel_in, port, in, out);
reg [3:0] count_in;
reg [3:0] count_out;
initial begin
sel_in = 0;
count_in = 'b0;
count_out = 'b0;
end
always begin
#1
count_in = count_in + 1;
count_out = count_out - 1;
end
assign port = sel_in ? count_in : 'bz;
assign out = count_out;
always
#4 sel_in = ~sel_in;
endmodule | 0 |
142,116 | data/full_repos/permissive/9705033/common/basics_test.v | 9,705,033 | basics_test.v | v | 167 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(22, 50), (52, 82), (85, 111), (114, 146), (149, 166)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #3 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n #4 sel_in = ~sel_in;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #7 sel = ~sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n #6 in_a = in_a + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 in_b = in_b + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1 in = in + 1;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics_test.v:52: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'RegLatchTest\'\nmodule RegLatchTest;\n ^~~~~~~~~~~~\n : ... Top module \'RegDelayTest\'\nmodule RegDelayTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_BidirTest\'\nmodule CC_BidirTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_MuxRegTest\'\nmodule CC_MuxRegTest;\n ^~~~~~~~~~~~~\n : ... Top module \'CC_DecoderTest\'\nmodule CC_DecoderTest;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:158: Cannot find file containing module: \'CC_Decoder\'\n CC_Decoder #(WIDTH) decoder(.in(in), .out(out));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.sv\n CC_Decoder\n CC_Decoder.v\n CC_Decoder.sv\n obj_dir/CC_Decoder\n obj_dir/CC_Decoder.v\n obj_dir/CC_Decoder.sv\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:121: Cannot find file containing module: \'CC_MuxReg\'\n CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:89: Cannot find file containing module: \'CC_Bidir\'\n CC_Bidir #(4) bidir(sel_in, port, in, out);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'count_in\' generates 4 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:64: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:65: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:66: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:32: Cannot find file containing module: \'CC_DFlipFlop\'\n CC_DFlipFlop #(4) register(clk, en, data, rout);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:33: Cannot find file containing module: \'CC_DLatch\'\n CC_DLatch #(4) latch(en, data, lout);\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,056 | module | module CC_MuxRegTest;
reg clk;
reg sel;
reg en;
reg [3:0] in_a, in_b;
wire [3:0] out;
CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);
initial begin
sel = 0;
en = 0;
clk = 0;
in_a = 'b0;
in_b = 'b0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#7 sel = ~sel;
always
#6 in_a = in_a + 1;
always
#10 in_b = in_b + 1;
endmodule | module CC_MuxRegTest; |
reg clk;
reg sel;
reg en;
reg [3:0] in_a, in_b;
wire [3:0] out;
CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);
initial begin
sel = 0;
en = 0;
clk = 0;
in_a = 'b0;
in_b = 'b0;
end
always
#1 clk = ~clk;
always
#4 en = ~en;
always
#7 sel = ~sel;
always
#6 in_a = in_a + 1;
always
#10 in_b = in_b + 1;
endmodule | 0 |
142,117 | data/full_repos/permissive/9705033/common/basics_test.v | 9,705,033 | basics_test.v | v | 167 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(22, 50), (52, 82), (85, 111), (114, 146), (149, 166)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:42: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #3 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #2 data = data + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:109: Unsupported: Ignoring delay on this delayed statement.\n #4 sel_in = ~sel_in;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:135: Unsupported: Ignoring delay on this delayed statement.\n #4 en = ~en;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:138: Unsupported: Ignoring delay on this delayed statement.\n #7 sel = ~sel;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:141: Unsupported: Ignoring delay on this delayed statement.\n #6 in_a = in_a + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #10 in_b = in_b + 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/basics_test.v:164: Unsupported: Ignoring delay on this delayed statement.\n #1 in = in + 1;\n ^\n%Warning-MULTITOP: data/full_repos/permissive/9705033/common/basics_test.v:52: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n : ... Top module \'RegLatchTest\'\nmodule RegLatchTest;\n ^~~~~~~~~~~~\n : ... Top module \'RegDelayTest\'\nmodule RegDelayTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_BidirTest\'\nmodule CC_BidirTest;\n ^~~~~~~~~~~~\n : ... Top module \'CC_MuxRegTest\'\nmodule CC_MuxRegTest;\n ^~~~~~~~~~~~~\n : ... Top module \'CC_DecoderTest\'\nmodule CC_DecoderTest;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:158: Cannot find file containing module: \'CC_Decoder\'\n CC_Decoder #(WIDTH) decoder(.in(in), .out(out));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_Decoder.sv\n CC_Decoder\n CC_Decoder.v\n CC_Decoder.sv\n obj_dir/CC_Decoder\n obj_dir/CC_Decoder.v\n obj_dir/CC_Decoder.sv\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:121: Cannot find file containing module: \'CC_MuxReg\'\n CC_MuxReg #(4) muxreg(sel, clk, en, in_a, in_b, out);\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:89: Cannot find file containing module: \'CC_Bidir\'\n CC_Bidir #(4) bidir(sel_in, port, in, out);\n ^~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'count_in\' generates 4 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/basics_test.v:105: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance CC_BidirTest\n assign port = sel_in ? count_in : \'bz;\n ^\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:64: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(1)) delay1(clk, reset, data, out1);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:65: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(2)) delay2(clk, reset, data, out2);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:66: Cannot find file containing module: \'CC_Delay\'\n CC_Delay #(.WIDTH(4), .DELAY(3)) delay3(clk, reset, data, out3);\n ^~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:32: Cannot find file containing module: \'CC_DFlipFlop\'\n CC_DFlipFlop #(4) register(clk, en, data, rout);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/basics_test.v:33: Cannot find file containing module: \'CC_DLatch\'\n CC_DLatch #(4) latch(en, data, lout);\n ^~~~~~~~~\n%Error: Exiting due to 8 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,056 | module | module CC_DecoderTest;
parameter WIDTH=4;
reg [WIDTH-1:0] in;
wire [(1 << WIDTH)-1:0] out;
CC_Decoder #(WIDTH) decoder(.in(in), .out(out));
initial
in = 0;
always
#1 in = in + 1;
endmodule | module CC_DecoderTest; |
parameter WIDTH=4;
reg [WIDTH-1:0] in;
wire [(1 << WIDTH)-1:0] out;
CC_Decoder #(WIDTH) decoder(.in(in), .out(out));
initial
in = 0;
always
#1 in = in + 1;
endmodule | 0 |
142,118 | data/full_repos/permissive/9705033/common/collision_table.v | 9,705,033 | collision_table.v | v | 88 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(65, 128)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/collision_table.v:20: Cannot find include file: collision.vh\n`include "collision.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.sv\n collision.vh\n collision.vh.v\n collision.vh.sv\n obj_dir/collision.vh\n obj_dir/collision.vh.v\n obj_dir/collision.vh.sv\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:34: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n input [`COLL_ADDR_WIDTH-1:0] table_index; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:35: Define or directive not defined: \'`COLL_DATA_WIDTH\'\n : ... Suggested alternative: \'`MPU_DATA_WIDTH\'\n input [`COLL_DATA_WIDTH-1:0] table_value; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:40: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n input [`COLL_ADDR_WIDTH-1:0] addr; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:49: Define or directive not defined: \'`COLL_REGS_BASE\'\n wire reg_select = (addr >= `COLL_REGS_BASE) &\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:49: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire reg_select = (addr >= `COLL_REGS_BASE) &\n ^\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:50: Define or directive not defined: \'`COLL_REGS_BASE\'\n (addr < `COLL_REGS_BASE + `NUM_COLL_STATUS_REGS);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:50: Define or directive not defined: \'`NUM_COLL_STATUS_REGS\'\n (addr < `COLL_REGS_BASE + `NUM_COLL_STATUS_REGS);\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:51: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:51: Define or directive not defined: \'`COLL_REGS_BASE\'\n wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:51: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;\n ^\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:52: Define or directive not defined: \'`COLL_REGS_CLEAR\'\n wire reg_reset = reset | (wr & (addr == `COLL_REGS_CLEAR));\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:52: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire reg_reset = reset | (wr & (addr == `COLL_REGS_CLEAR));\n ^\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:55: Define or directive not defined: \'`NUM_COLL_STATUS_REGS\'\n reg [16-1:0] status_regs[`NUM_COLL_STATUS_REGS-1:0];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:58: Define or directive not defined: \'`NUM_COLL_STATUS_REGS\'\n for (i = 0; i < `NUM_COLL_STATUS_REGS; i = i + 1) begin : REGS\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:58: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_COLL_STATUS_REGS; i = i + 1) begin : REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:69: Define or directive not defined: \'`COLL_TABLE_BASE\'\n wire table_select = (addr >= `COLL_TABLE_BASE) &\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:70: Define or directive not defined: \'`COLL_TABLE_BASE\'\n (addr < `COLL_TABLE_BASE + `COLL_TABLE_SIZE);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:70: Define or directive not defined: \'`COLL_TABLE_SIZE\'\n (addr < `COLL_TABLE_BASE + `COLL_TABLE_SIZE);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:81: Define or directive not defined: \'`BYTE_WIDTH\'\n .data_a({table_value[`BYTE_WIDTH-1:0], table_value[`BYTE_WIDTH-1:0]}),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:81: Define or directive not defined: \'`BYTE_WIDTH\'\n .data_a({table_value[`BYTE_WIDTH-1:0], table_value[`BYTE_WIDTH-1:0]}),\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:84: Define or directive not defined: \'`COLL_TABLE_BASE\'\n .address_b(addr - `COLL_TABLE_BASE),\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/collision_table.v:84: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n .address_b(addr - `COLL_TABLE_BASE),\n ^\n%Error: Cannot continue\n' | 313,058 | module | module CollisionTable(clk, reset,
write_collision, table_index, table_value,
wr, be, addr, data_in, data_out);
input clk;
input reset;
input write_collision;
input [`COLL_ADDR_WIDTH-1:0] table_index;
input [`COLL_DATA_WIDTH-1:0] table_value;
input wr;
input [1:0] be;
input [`COLL_ADDR_WIDTH-1:0] addr;
input [`MPU_DATA_WIDTH-1:0] data_in;
output [`MPU_DATA_WIDTH-1:0] data_out;
assign data_out = table_select ? table_data_out :
(reg_select ? status_regs[reg_addr] : 0);
wire reg_select = (addr >= `COLL_REGS_BASE) &
(addr < `COLL_REGS_BASE + `NUM_COLL_STATUS_REGS);
wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;
wire reg_reset = reset | (wr & (addr == `COLL_REGS_CLEAR));
reg [`MPU_DATA_WIDTH-1:0] status_regs[`NUM_COLL_STATUS_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_COLL_STATUS_REGS; i = i + 1) begin : REGS
always @ (posedge reg_reset or posedge clk) begin
if (reg_reset)
status_regs[i] <= 0;
else if (write_collision & table_index / `MPU_DATA_WIDTH == i)
status_regs[i][table_index % `MPU_DATA_WIDTH] <= 1;
end
end
endgenerate
wire table_select = (addr >= `COLL_TABLE_BASE) &
(addr < `COLL_TABLE_BASE + `COLL_TABLE_SIZE);
wire [`MPU_DATA_WIDTH-1:0] table_data_out;
collision_table_256x16 collision_table(
.clock(clk),
.wren_a(write_collision),
.byteena_a(table_index[0] ? 'b10 : 'b01),
.address_a(table_index / 2),
.data_a({table_value[`BYTE_WIDTH-1:0], table_value[`BYTE_WIDTH-1:0]}),
.wren_b(0),
.address_b(addr - `COLL_TABLE_BASE),
.q_b(table_data_out));
endmodule | module CollisionTable(clk, reset,
write_collision, table_index, table_value,
wr, be, addr, data_in, data_out); |
input clk;
input reset;
input write_collision;
input [`COLL_ADDR_WIDTH-1:0] table_index;
input [`COLL_DATA_WIDTH-1:0] table_value;
input wr;
input [1:0] be;
input [`COLL_ADDR_WIDTH-1:0] addr;
input [`MPU_DATA_WIDTH-1:0] data_in;
output [`MPU_DATA_WIDTH-1:0] data_out;
assign data_out = table_select ? table_data_out :
(reg_select ? status_regs[reg_addr] : 0);
wire reg_select = (addr >= `COLL_REGS_BASE) &
(addr < `COLL_REGS_BASE + `NUM_COLL_STATUS_REGS);
wire [`COLL_ADDR_WIDTH-1:0] reg_addr = addr - `COLL_REGS_BASE;
wire reg_reset = reset | (wr & (addr == `COLL_REGS_CLEAR));
reg [`MPU_DATA_WIDTH-1:0] status_regs[`NUM_COLL_STATUS_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_COLL_STATUS_REGS; i = i + 1) begin : REGS
always @ (posedge reg_reset or posedge clk) begin
if (reg_reset)
status_regs[i] <= 0;
else if (write_collision & table_index / `MPU_DATA_WIDTH == i)
status_regs[i][table_index % `MPU_DATA_WIDTH] <= 1;
end
end
endgenerate
wire table_select = (addr >= `COLL_TABLE_BASE) &
(addr < `COLL_TABLE_BASE + `COLL_TABLE_SIZE);
wire [`MPU_DATA_WIDTH-1:0] table_data_out;
collision_table_256x16 collision_table(
.clock(clk),
.wren_a(write_collision),
.byteena_a(table_index[0] ? 'b10 : 'b01),
.address_a(table_index / 2),
.data_a({table_value[`BYTE_WIDTH-1:0], table_value[`BYTE_WIDTH-1:0]}),
.wren_b(0),
.address_b(addr - `COLL_TABLE_BASE),
.q_b(table_data_out));
endmodule | 0 |
142,119 | data/full_repos/permissive/9705033/common/core.v | 9,705,033 | core.v | v | 453 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | line:738: before: ")" | null | 1: b'%Error: data/full_repos/permissive/9705033/common/core.v:21: Cannot find include file: collision.vh\n`include "collision.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.sv\n collision.vh\n collision.vh.v\n collision.vh.sv\n obj_dir/collision.vh\n obj_dir/collision.vh.v\n obj_dir/collision.vh.sv\n%Error: data/full_repos/permissive/9705033/common/core.v:22: Cannot find include file: memory_map.vh\n`include "memory_map.vh" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:23: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:24: Cannot find include file: sprite_registers.vh\n`include "sprite_registers.vh" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:25: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:68: Define or directive not defined: \'`VRAM_ADDR_WIDTH\'\n : ... Suggested alternative: \'`VRAM_DATA_WIDTH\'\n output reg [`VRAM_ADDR_WIDTH-1:0] vram_addr; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:81: Define or directive not defined: \'`PAGE_OFFSET_WIDTH\'\n wire [`PAGE_OFFSET_WIDTH-1:0] page_offset =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:82: Define or directive not defined: \'`PAGE_OFFSET_WIDTH\'\n mpu_addr_in[`PAGE_OFFSET_WIDTH-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:83: Define or directive not defined: \'`PAGE_OFFSET_WIDTH\'\n wire [16-`PAGE_OFFSET_WIDTH-1:0] page_index =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:84: Define or directive not defined: \'`PAGE_OFFSET_WIDTH\'\n mpu_addr_in >> `PAGE_OFFSET_WIDTH;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:84: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n mpu_addr_in >> `PAGE_OFFSET_WIDTH;\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:87: Define or directive not defined: \'`INT_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`INT_ADDR_WIDTH-1:0] mpu_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:88: Define or directive not defined: \'`MEM_BANK\'\n wire [7:0] bank_value = reg_array_out[`MEM_BANK];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [7:0] bank_value = reg_array_out[`MEM_BANK];\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:129: Define or directive not defined: \'`COLL_ADDR_BASE\'\n wire collision_select = (mpu_addr >= `COLL_ADDR_BASE) &\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:129: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire collision_select = (mpu_addr >= `COLL_ADDR_BASE) &\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:130: Define or directive not defined: \'`COLL_ADDR_BASE\'\n (mpu_addr < `COLL_ADDR_BASE + `COLL_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:130: Define or directive not defined: \'`COLL_ADDR_LENGTH\'\n (mpu_addr < `COLL_ADDR_BASE + `COLL_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:131: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`COLL_ADDR_WIDTH-1:0] coll_addr = (mpu_addr - `COLL_ADDR_BASE);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:131: Define or directive not defined: \'`COLL_ADDR_BASE\'\n wire [`COLL_ADDR_WIDTH-1:0] coll_addr = (mpu_addr - `COLL_ADDR_BASE);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:131: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire [`COLL_ADDR_WIDTH-1:0] coll_addr = (mpu_addr - `COLL_ADDR_BASE);\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:136: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`COLL_ADDR_WIDTH-1:0] ren_coll_addr;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:137: Define or directive not defined: \'`COLL_DATA_WIDTH\'\n : ... Suggested alternative: \'`MPU_DATA_WIDTH\'\n wire [`COLL_DATA_WIDTH-1:0] ren_coll_data;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:159: Define or directive not defined: \'`PAL_ADDR_BASE\'\n wire palette_select = (mpu_addr >= `PAL_ADDR_BASE) &\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:159: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire palette_select = (mpu_addr >= `PAL_ADDR_BASE) &\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:160: Define or directive not defined: \'`PAL_ADDR_BASE\'\n (mpu_addr < `PAL_ADDR_BASE + `PAL_ADDR_LENGTH);\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:160: Define or directive not defined: \'`PAL_ADDR_LENGTH\'\n (mpu_addr < `PAL_ADDR_BASE + `PAL_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:164: Define or directive not defined: \'`NUM_PAL_CHANNELS\'\n wire [`NUM_PAL_CHANNELS-1:0] pal_byte_en;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:169: Define or directive not defined: \'`NUM_PAL_CHANNELS\'\n wire [`NUM_PAL_CHANNELS*8-1:0] pal_data_out_temp;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:169: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`NUM_PAL_CHANNELS*8-1:0] pal_data_out_temp;\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:175: Define or directive not defined: \'`PAL_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`PAL_ADDR_WIDTH-1:0] ren_pal_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:176: Define or directive not defined: \'`PAL_DATA_WIDTH\'\n : ... Suggested alternative: \'`MPU_DATA_WIDTH\'\n wire [`PAL_DATA_WIDTH-1:0] ren_pal_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:178: Define or directive not defined: \'`NUM_PAL_CHANNELS\'\n Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) palette(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:196: Define or directive not defined: \'`SPRITE_ADDR_BASE\'\n wire sprite_select = (mpu_addr >= `SPRITE_ADDR_BASE) &\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:196: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n wire sprite_select = (mpu_addr >= `SPRITE_ADDR_BASE) &\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:197: Define or directive not defined: \'`SPRITE_ADDR_BASE\'\n (mpu_addr < `SPRITE_ADDR_BASE + `SPRITE_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:197: Define or directive not defined: \'`SPRITE_ADDR_LENGTH\'\n (mpu_addr < `SPRITE_ADDR_BASE + `SPRITE_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:203: Define or directive not defined: \'`SPRITE_XY_ADDR_BASE\'\n (mpu_addr >= `SPRITE_XY_ADDR_BASE) &\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:203: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n (mpu_addr >= `SPRITE_XY_ADDR_BASE) &\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:204: Define or directive not defined: \'`SPRITE_XY_ADDR_BASE\'\n (mpu_addr < `SPRITE_XY_ADDR_BASE + `SPRITE_XY_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:204: Define or directive not defined: \'`SPRITE_XY_ADDR_LENGTH\'\n (mpu_addr < `SPRITE_XY_ADDR_BASE + `SPRITE_XY_ADDR_LENGTH);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:205: Define or directive not defined: \'`SPRITE_XY_ADDR_BASE\'\n wire [16-1:0] sprite_xy_addr = mpu_addr - `SPRITE_XY_ADDR_BASE;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:205: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n wire [16-1:0] sprite_xy_addr = mpu_addr - `SPRITE_XY_ADDR_BASE;\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:209: Define or directive not defined: \'`SPRITE_OFFSET_Y\'\n (sprite_xy_addr % 2) ? `SPRITE_OFFSET_Y : `SPRITE_OFFSET_X;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:209: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n (sprite_xy_addr % 2) ? `SPRITE_OFFSET_Y : `SPRITE_OFFSET_X;\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:209: Define or directive not defined: \'`SPRITE_OFFSET_X\'\n (sprite_xy_addr % 2) ? `SPRITE_OFFSET_Y : `SPRITE_OFFSET_X;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:211: Define or directive not defined: \'`NUM_SPRITE_REGS\'\n sprite_xy_index * `NUM_SPRITE_REGS + sprite_xy_offset;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:215: Define or directive not defined: \'`SPRITE_ADDR_BASE\'\n sprite_select ? (mpu_addr - `SPRITE_ADDR_BASE)\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/core.v:215: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n sprite_select ? (mpu_addr - `SPRITE_ADDR_BASE)\n ^\n%Error: data/full_repos/permissive/9705033/common/core.v:219: Define or directive not defined: \'`SPRITE_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`SPRITE_ADDR_WIDTH-1:0] ren_spr_addr;\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,059 | module | module Core(
clk, reset, _int,
mpu_rd, mpu_wr, mpu_en, mpu_be, mpu_addr_in, mpu_data_in, mpu_data_out,
vram_en, vram_rd, vram_wr, vram_be, vram_addr, vram_data_in, vram_data_out,
vga_vsync, vga_hsync, vga_rgb);
input clk;
input reset;
input _int;
input mpu_en;
input mpu_rd;
input mpu_wr;
input [1:0] mpu_be;
input [`MPU_ADDR_WIDTH-1:0] mpu_addr_in;
input [`MPU_DATA_WIDTH-1:0] mpu_data_in;
output [`MPU_DATA_WIDTH-1:0] mpu_data_out;
output vram_en;
output vram_rd;
output vram_wr;
output [1:0] vram_be;
output reg [`VRAM_ADDR_WIDTH-1:0] vram_addr;
input [`VRAM_DATA_WIDTH-1:0] vram_data_in;
output [`VRAM_DATA_WIDTH-1:0] vram_data_out;
output vga_vsync;
output vga_hsync;
output [`RGB_COLOR_DEPTH-1:0] vga_rgb;
wire [`PAGE_OFFSET_WIDTH-1:0] page_offset =
mpu_addr_in[`PAGE_OFFSET_WIDTH-1:0];
wire [`MPU_ADDR_WIDTH-`PAGE_OFFSET_WIDTH-1:0] page_index =
mpu_addr_in >> `PAGE_OFFSET_WIDTH;
wire [`INT_ADDR_WIDTH-1:0] mpu_addr;
wire [7:0] bank_value = reg_array_out[`MEM_BANK];
assign mpu_addr = { ((page_index == 0) ? {16'b0} : bank_value), page_offset };
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController display(.clk(clk),
.reset(reset),
.h_pos(h_pos),
.v_pos(v_pos));
wire [`MPU_DATA_WIDTH-1:0] pal_data_out;
wire [`MPU_DATA_WIDTH-1:0] reg_data_out;
wire [`MPU_DATA_WIDTH-1:0] low_mem_data_out;
wire [`MPU_DATA_WIDTH-1:0] high_mem_data_out;
wire low_mem_select = mpu_addr < `LOW_MEM_SIZE;
assign mpu_data_out =
(~mpu_rd | ~mpu_en) ? {`MPU_DATA_WIDTH {1'b0}}
: (low_mem_select ? low_mem_data_out
: high_mem_data_out);
assign low_mem_data_out = (main_regs_select ? reg_data_out :
(tile_regs_select ? tile_data_out :
(collision_select ? coll_data_out :
(palette_select ? pal_data_out :
`UNMAPPED_MEMORY_VALUE))));
assign high_mem_data_out = (sprite_select ? sprite_data_out :
(map_select ? map_data_out :
(vram_select ? vram_data_in :
`UNMAPPED_MEMORY_VALUE)));
wire collision_select = (mpu_addr >= `COLL_ADDR_BASE) &
(mpu_addr < `COLL_ADDR_BASE + `COLL_ADDR_LENGTH);
wire [`COLL_ADDR_WIDTH-1:0] coll_addr = (mpu_addr - `COLL_ADDR_BASE);
wire [`MPU_DATA_WIDTH-1:0] coll_data_out;
wire ren_coll_wr;
wire [`COLL_ADDR_WIDTH-1:0] ren_coll_addr;
wire [`COLL_DATA_WIDTH-1:0] ren_coll_data;
CollisionTable collision_table(
.clk(clk),
.reset(master_reset),
.write_collision(ren_coll_wr),
.table_index(ren_coll_addr),
.table_value(ren_coll_data),
.wr(mpu_wr & collision_select),
.be(mpu_be),
.addr(coll_addr),
.data_in(mpu_data_in),
.data_out(coll_data_out),
);
wire palette_select = (mpu_addr >= `PAL_ADDR_BASE) &
(mpu_addr < `PAL_ADDR_BASE + `PAL_ADDR_LENGTH);
wire pal_wr = palette_select & mpu_wr;
wire pal_rd = palette_select & mpu_rd;
wire [`NUM_PAL_CHANNELS-1:0] pal_byte_en;
assign pal_byte_en[0] = (mpu_addr[0] == 0) & mpu_be[0];
assign pal_byte_en[1] = (mpu_addr[0] == 0) & mpu_be[1];
assign pal_byte_en[2] = (mpu_addr[0] == 1) & mpu_be[0];
wire [`NUM_PAL_CHANNELS*8-1:0] pal_data_out_temp;
assign pal_data_out = (mpu_addr[0] == 0) ? pal_data_out_temp[15:0]
: pal_data_out_temp[23:16];
wire ren_pal_clk;
wire [`PAL_ADDR_WIDTH-1:0] ren_pal_addr;
wire [`PAL_DATA_WIDTH-1:0] ren_pal_data;
Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) palette(
.clk_a(clk),
.wr_a(pal_wr),
.rd_a(pal_rd),
.addr_a(mpu_addr >> 1),
.data_in_a({mpu_data_in, mpu_data_in}),
.data_out_a(pal_data_out_temp),
.byte_en_a(pal_byte_en),
.clk_b(ren_pal_clk),
.wr_b(0),
.rd_b(1),
.addr_b(ren_pal_addr),
.data_in_b(0),
.data_out_b(ren_pal_data)
);
wire sprite_select = (mpu_addr >= `SPRITE_ADDR_BASE) &
(mpu_addr < `SPRITE_ADDR_BASE + `SPRITE_ADDR_LENGTH);
wire sprite_xy_select =
(mpu_addr >= `SPRITE_XY_ADDR_BASE) &
(mpu_addr < `SPRITE_XY_ADDR_BASE + `SPRITE_XY_ADDR_LENGTH);
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_addr = mpu_addr - `SPRITE_XY_ADDR_BASE;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_index = sprite_xy_addr / 2;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_offset =
(sprite_xy_addr % 2) ? `SPRITE_OFFSET_Y : `SPRITE_OFFSET_X;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_mapped_addr =
sprite_xy_index * `NUM_SPRITE_REGS + sprite_xy_offset;
wire [`MPU_ADDR_WIDTH-1:0] sprite_addr =
sprite_select ? (mpu_addr - `SPRITE_ADDR_BASE)
: (sprite_xy_select ? sprite_xy_mapped_addr : 0);
wire ren_spr_clk;
wire [`SPRITE_ADDR_WIDTH-1:0] ren_spr_addr;
wire [`SPRITE_DATA_WIDTH-1:0] ren_spr_data;
wire [`SPRITE_DATA_WIDTH-1:0] ren_spr_data_out;
wire [`MPU_DATA_WIDTH-1:0] sprite_data_out;
sprite_ram_4Kx16 sprite_ram(
.clock_a(clk),
.address_a(sprite_addr),
.byteena_a(mpu_be),
.wren_a((sprite_select | sprite_xy_select) & mpu_wr & ~mpu_rd),
.data_a(mpu_data_in),
.q_a(sprite_data_out),
.clock_b(ren_spr_clk),
.address_b(ren_spr_addr),
.data_b('bx),
.wren_b(0),
.q_b(ren_spr_data));
wire map_select = (mpu_addr >= `TILEMAP_ADDR_BASE) &
(mpu_addr < `TILEMAP_ADDR_BASE + `TILEMAP_ADDR_LENGTH);
wire map_wr = map_select & mpu_wr;
wire map_rd = map_select & mpu_rd;
wire [1:0] map_be = mpu_be;
wire [`MPU_DATA_WIDTH-1:0] map_data_out;
wire ren_map_clk;
wire [`TILEMAP_ADDR_WIDTH-1:0] ren_map_addr;
wire [`TILEMAP_DATA_WIDTH-1:0] ren_map_data;
tilemap_ram_4Kx16 tilemap(
.clock_a(clk),
.address_a(mpu_addr),
.byteena_a(map_be),
.rden_a(map_rd),
.wren_a(map_wr),
.data_a(mpu_data_in),
.q_a(map_data_out),
.clock_b(ren_map_clk),
.rden_b(1),
.wren_b(0),
.address_b(ren_map_addr),
.data_b(0),
.q_b(ren_map_data)
);
wire vram_select = (mpu_addr >= `VRAM_ADDR_BASE) &
(mpu_addr < `VRAM_ADDR_BASE + `VRAM_ADDR_LENGTH);
wire vram_uses_mpu = reg_array_out[`SYS_CTRL][`SYS_CTRL_VRAM_ACCESS];
wire vram_en = vram_uses_mpu ? vram_uses_mpu : ren_vram_en;
wire vram_wr = vram_uses_mpu ? mpu_wr : ren_vram_wr;
wire vram_rd = vram_uses_mpu ? mpu_rd : ren_vram_rd;
wire [1:0] vram_be = vram_uses_mpu ? mpu_be : ren_vram_be;
always @ (posedge clk)
vram_addr <= vram_uses_mpu ? (mpu_addr - `VRAM_ADDR_BASE) : ren_vram_addr;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out =
vram_uses_mpu ? mpu_data_in : {`VRAM_DATA_WIDTH {1'b0}};
wire ren_vram_en;
wire ren_vram_rd;
wire ren_vram_wr;
wire [1:0] ren_vram_be;
wire [`VRAM_ADDR_WIDTH-1:0] ren_vram_addr;
reg [`VRAM_DATA_WIDTH-1:0] ren_vram_data;
always @ (posedge clk)
ren_vram_data <= vram_uses_mpu ? 0 : vram_data_in;
Renderer renderer(.clk(clk),
.reset(master_reset),
.reg_values(reg_values_out),
.tile_reg_values(tile_reg_values),
.vram_en(ren_vram_en),
.vram_rd(ren_vram_rd),
.vram_wr(ren_vram_wr),
.vram_be(ren_vram_be),
.vram_addr(ren_vram_addr),
.vram_data(ren_vram_data),
.pal_clk(ren_pal_clk),
.pal_addr(ren_pal_addr),
.pal_data(ren_pal_data),
.map_clk(ren_map_clk),
.map_addr(ren_map_addr),
.map_data(ren_map_data),
.spr_clk(ren_spr_clk),
.spr_addr(ren_spr_addr),
.spr_data(ren_spr_data),
.coll_wr(ren_coll_wr),
.coll_addr(ren_coll_addr),
.coll_data(ren_coll_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(vga_hsync),
.v_sync(vga_vsync),
.rgb_out(vga_rgb));
wire [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values_out;
wire [`REG_DATA_WIDTH-1:0] reg_array_out [`NUM_MAIN_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : OUT_REGS
assign reg_array_out[i] = reg_values_out[`REG_DATA_WIDTH * (i + 1) - 1:
`REG_DATA_WIDTH * i];
end
endgenerate
reg reset_bit;
always @ (posedge clk or posedge reset) begin
if (reset)
reset_bit <= 0;
else
reset_bit <= reg_array_out[`SYS_CTRL][`SYS_CTRL_RESET];
end
wire master_reset = reset | reset_bit;
wire [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values_in;
wire [`REG_DATA_WIDTH-1:0] reg_array_in [`NUM_MAIN_REGS-1:0];
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : IN_REGS
assign reg_values_in[`REG_DATA_WIDTH * (i + 1) - 1: `REG_DATA_WIDTH * i] =
reg_array_in[i];
end
endgenerate
assign reg_array_in[`ID] = `ID_REG_VALUE;
DisplayTiming timing(.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(reg_array_in[`OUTPUT_STATUS][0]),
.v_sync(reg_array_in[`OUTPUT_STATUS][1]),
.h_blank(reg_array_in[`OUTPUT_STATUS][2]),
.v_blank(reg_array_in[`OUTPUT_STATUS][3]),
.h_visible_pos(reg_array_in[`SCAN_X]),
.v_visible_pos(reg_array_in[`SCAN_Y]));
wire main_regs_select = (mpu_addr >= `MAIN_REG_ADDR_BASE) &
(mpu_addr < `MAIN_REG_ADDR_BASE + `NUM_MAIN_REGS);
Registers #(.DATA_WIDTH(`REG_DATA_WIDTH),
.ADDR_WIDTH(`MAIN_REG_ADDR_WIDTH),
.NUM_REGS(`NUM_MAIN_REGS),
.IS_GENERIC(1))
registers(.clk(clk),
.reset(master_reset),
.en(main_regs_select),
.rd(mpu_rd),
.wr(mpu_wr),
.be(mpu_be),
.addr(mpu_addr[`MAIN_REG_ADDR_WIDTH-1:0]),
.data_in(mpu_data_in),
.data_out(reg_data_out),
.values_in(reg_values_in),
.values_out(reg_values_out));
wire tile_regs_select =
(mpu_addr >= `TILE_REG_ADDR_BASE) &
(mpu_addr < `TILE_REG_ADDR_BASE + `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS);
wire [`NUM_TILE_LAYERS-1:0] tile_layer_reg_select;
wire [`REG_DATA_WIDTH-1:0] tile_data_out_array[`NUM_TILE_LAYERS-1:0];
wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]
tile_values_out_array[`NUM_TILE_LAYERS-1:0];
wire [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES
assign tile_reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:
i * `NUM_REG_BITS_PER_TILE_LAYER]
= tile_values_out_array[i];
end
endgenerate
reg [`REG_DATA_WIDTH-1:0] tile_data_out;
wire [1:0] tile_index =
mpu_addr[`TILE_BLOCK_ADDR_WIDTH+1:`TILE_BLOCK_ADDR_WIDTH];
wire [`TILE_BLOCK_ADDR_WIDTH-1:0] tile_reg_addr =
mpu_addr[`TILE_BLOCK_ADDR_WIDTH-1:0];
always @ (*) begin
if (~tile_regs_select) begin
tile_data_out <= 'bx;
end else begin
if (tile_index < `NUM_TILE_REGISTERS)
tile_data_out <= tile_data_out_array[tile_index];
else
tile_data_out <= 0;
end
end
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_SELECT
assign tile_layer_reg_select[i] =
tile_regs_select &
(mpu_addr >= `TILE_REG_ADDR_BASE + i * `TILE_REG_ADDR_STEP) &
(mpu_addr < `TILE_REG_ADDR_BASE +
i * `TILE_REG_ADDR_STEP +
`NUM_TILE_REGISTERS);
Registers #(.DATA_WIDTH(`REG_DATA_WIDTH),
.ADDR_WIDTH(`TILE_REG_ADDR_WIDTH),
.NUM_REGS(`NUM_TILE_REGISTERS),
.IS_GENERIC(0))
tile_registers(.clk(clk),
.reset(master_reset),
.en(tile_layer_reg_select[i]),
.rd(mpu_rd),
.wr(mpu_wr),
.be(mpu_be),
.addr(mpu_addr[`TILE_REG_ADDR_WIDTH-1:0]),
.data_in(mpu_data_in[`REG_DATA_WIDTH-1:0]),
.data_out(tile_data_out_array[i]),
.values_in(0),
.values_out(tile_values_out_array[i]));
end
endgenerate
endmodule | module Core(
clk, reset, _int,
mpu_rd, mpu_wr, mpu_en, mpu_be, mpu_addr_in, mpu_data_in, mpu_data_out,
vram_en, vram_rd, vram_wr, vram_be, vram_addr, vram_data_in, vram_data_out,
vga_vsync, vga_hsync, vga_rgb); |
input clk;
input reset;
input _int;
input mpu_en;
input mpu_rd;
input mpu_wr;
input [1:0] mpu_be;
input [`MPU_ADDR_WIDTH-1:0] mpu_addr_in;
input [`MPU_DATA_WIDTH-1:0] mpu_data_in;
output [`MPU_DATA_WIDTH-1:0] mpu_data_out;
output vram_en;
output vram_rd;
output vram_wr;
output [1:0] vram_be;
output reg [`VRAM_ADDR_WIDTH-1:0] vram_addr;
input [`VRAM_DATA_WIDTH-1:0] vram_data_in;
output [`VRAM_DATA_WIDTH-1:0] vram_data_out;
output vga_vsync;
output vga_hsync;
output [`RGB_COLOR_DEPTH-1:0] vga_rgb;
wire [`PAGE_OFFSET_WIDTH-1:0] page_offset =
mpu_addr_in[`PAGE_OFFSET_WIDTH-1:0];
wire [`MPU_ADDR_WIDTH-`PAGE_OFFSET_WIDTH-1:0] page_index =
mpu_addr_in >> `PAGE_OFFSET_WIDTH;
wire [`INT_ADDR_WIDTH-1:0] mpu_addr;
wire [7:0] bank_value = reg_array_out[`MEM_BANK];
assign mpu_addr = { ((page_index == 0) ? {16'b0} : bank_value), page_offset };
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController display(.clk(clk),
.reset(reset),
.h_pos(h_pos),
.v_pos(v_pos));
wire [`MPU_DATA_WIDTH-1:0] pal_data_out;
wire [`MPU_DATA_WIDTH-1:0] reg_data_out;
wire [`MPU_DATA_WIDTH-1:0] low_mem_data_out;
wire [`MPU_DATA_WIDTH-1:0] high_mem_data_out;
wire low_mem_select = mpu_addr < `LOW_MEM_SIZE;
assign mpu_data_out =
(~mpu_rd | ~mpu_en) ? {`MPU_DATA_WIDTH {1'b0}}
: (low_mem_select ? low_mem_data_out
: high_mem_data_out);
assign low_mem_data_out = (main_regs_select ? reg_data_out :
(tile_regs_select ? tile_data_out :
(collision_select ? coll_data_out :
(palette_select ? pal_data_out :
`UNMAPPED_MEMORY_VALUE))));
assign high_mem_data_out = (sprite_select ? sprite_data_out :
(map_select ? map_data_out :
(vram_select ? vram_data_in :
`UNMAPPED_MEMORY_VALUE)));
wire collision_select = (mpu_addr >= `COLL_ADDR_BASE) &
(mpu_addr < `COLL_ADDR_BASE + `COLL_ADDR_LENGTH);
wire [`COLL_ADDR_WIDTH-1:0] coll_addr = (mpu_addr - `COLL_ADDR_BASE);
wire [`MPU_DATA_WIDTH-1:0] coll_data_out;
wire ren_coll_wr;
wire [`COLL_ADDR_WIDTH-1:0] ren_coll_addr;
wire [`COLL_DATA_WIDTH-1:0] ren_coll_data;
CollisionTable collision_table(
.clk(clk),
.reset(master_reset),
.write_collision(ren_coll_wr),
.table_index(ren_coll_addr),
.table_value(ren_coll_data),
.wr(mpu_wr & collision_select),
.be(mpu_be),
.addr(coll_addr),
.data_in(mpu_data_in),
.data_out(coll_data_out),
);
wire palette_select = (mpu_addr >= `PAL_ADDR_BASE) &
(mpu_addr < `PAL_ADDR_BASE + `PAL_ADDR_LENGTH);
wire pal_wr = palette_select & mpu_wr;
wire pal_rd = palette_select & mpu_rd;
wire [`NUM_PAL_CHANNELS-1:0] pal_byte_en;
assign pal_byte_en[0] = (mpu_addr[0] == 0) & mpu_be[0];
assign pal_byte_en[1] = (mpu_addr[0] == 0) & mpu_be[1];
assign pal_byte_en[2] = (mpu_addr[0] == 1) & mpu_be[0];
wire [`NUM_PAL_CHANNELS*8-1:0] pal_data_out_temp;
assign pal_data_out = (mpu_addr[0] == 0) ? pal_data_out_temp[15:0]
: pal_data_out_temp[23:16];
wire ren_pal_clk;
wire [`PAL_ADDR_WIDTH-1:0] ren_pal_addr;
wire [`PAL_DATA_WIDTH-1:0] ren_pal_data;
Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) palette(
.clk_a(clk),
.wr_a(pal_wr),
.rd_a(pal_rd),
.addr_a(mpu_addr >> 1),
.data_in_a({mpu_data_in, mpu_data_in}),
.data_out_a(pal_data_out_temp),
.byte_en_a(pal_byte_en),
.clk_b(ren_pal_clk),
.wr_b(0),
.rd_b(1),
.addr_b(ren_pal_addr),
.data_in_b(0),
.data_out_b(ren_pal_data)
);
wire sprite_select = (mpu_addr >= `SPRITE_ADDR_BASE) &
(mpu_addr < `SPRITE_ADDR_BASE + `SPRITE_ADDR_LENGTH);
wire sprite_xy_select =
(mpu_addr >= `SPRITE_XY_ADDR_BASE) &
(mpu_addr < `SPRITE_XY_ADDR_BASE + `SPRITE_XY_ADDR_LENGTH);
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_addr = mpu_addr - `SPRITE_XY_ADDR_BASE;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_index = sprite_xy_addr / 2;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_offset =
(sprite_xy_addr % 2) ? `SPRITE_OFFSET_Y : `SPRITE_OFFSET_X;
wire [`MPU_ADDR_WIDTH-1:0] sprite_xy_mapped_addr =
sprite_xy_index * `NUM_SPRITE_REGS + sprite_xy_offset;
wire [`MPU_ADDR_WIDTH-1:0] sprite_addr =
sprite_select ? (mpu_addr - `SPRITE_ADDR_BASE)
: (sprite_xy_select ? sprite_xy_mapped_addr : 0);
wire ren_spr_clk;
wire [`SPRITE_ADDR_WIDTH-1:0] ren_spr_addr;
wire [`SPRITE_DATA_WIDTH-1:0] ren_spr_data;
wire [`SPRITE_DATA_WIDTH-1:0] ren_spr_data_out;
wire [`MPU_DATA_WIDTH-1:0] sprite_data_out;
sprite_ram_4Kx16 sprite_ram(
.clock_a(clk),
.address_a(sprite_addr),
.byteena_a(mpu_be),
.wren_a((sprite_select | sprite_xy_select) & mpu_wr & ~mpu_rd),
.data_a(mpu_data_in),
.q_a(sprite_data_out),
.clock_b(ren_spr_clk),
.address_b(ren_spr_addr),
.data_b('bx),
.wren_b(0),
.q_b(ren_spr_data));
wire map_select = (mpu_addr >= `TILEMAP_ADDR_BASE) &
(mpu_addr < `TILEMAP_ADDR_BASE + `TILEMAP_ADDR_LENGTH);
wire map_wr = map_select & mpu_wr;
wire map_rd = map_select & mpu_rd;
wire [1:0] map_be = mpu_be;
wire [`MPU_DATA_WIDTH-1:0] map_data_out;
wire ren_map_clk;
wire [`TILEMAP_ADDR_WIDTH-1:0] ren_map_addr;
wire [`TILEMAP_DATA_WIDTH-1:0] ren_map_data;
tilemap_ram_4Kx16 tilemap(
.clock_a(clk),
.address_a(mpu_addr),
.byteena_a(map_be),
.rden_a(map_rd),
.wren_a(map_wr),
.data_a(mpu_data_in),
.q_a(map_data_out),
.clock_b(ren_map_clk),
.rden_b(1),
.wren_b(0),
.address_b(ren_map_addr),
.data_b(0),
.q_b(ren_map_data)
);
wire vram_select = (mpu_addr >= `VRAM_ADDR_BASE) &
(mpu_addr < `VRAM_ADDR_BASE + `VRAM_ADDR_LENGTH);
wire vram_uses_mpu = reg_array_out[`SYS_CTRL][`SYS_CTRL_VRAM_ACCESS];
wire vram_en = vram_uses_mpu ? vram_uses_mpu : ren_vram_en;
wire vram_wr = vram_uses_mpu ? mpu_wr : ren_vram_wr;
wire vram_rd = vram_uses_mpu ? mpu_rd : ren_vram_rd;
wire [1:0] vram_be = vram_uses_mpu ? mpu_be : ren_vram_be;
always @ (posedge clk)
vram_addr <= vram_uses_mpu ? (mpu_addr - `VRAM_ADDR_BASE) : ren_vram_addr;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out =
vram_uses_mpu ? mpu_data_in : {`VRAM_DATA_WIDTH {1'b0}};
wire ren_vram_en;
wire ren_vram_rd;
wire ren_vram_wr;
wire [1:0] ren_vram_be;
wire [`VRAM_ADDR_WIDTH-1:0] ren_vram_addr;
reg [`VRAM_DATA_WIDTH-1:0] ren_vram_data;
always @ (posedge clk)
ren_vram_data <= vram_uses_mpu ? 0 : vram_data_in;
Renderer renderer(.clk(clk),
.reset(master_reset),
.reg_values(reg_values_out),
.tile_reg_values(tile_reg_values),
.vram_en(ren_vram_en),
.vram_rd(ren_vram_rd),
.vram_wr(ren_vram_wr),
.vram_be(ren_vram_be),
.vram_addr(ren_vram_addr),
.vram_data(ren_vram_data),
.pal_clk(ren_pal_clk),
.pal_addr(ren_pal_addr),
.pal_data(ren_pal_data),
.map_clk(ren_map_clk),
.map_addr(ren_map_addr),
.map_data(ren_map_data),
.spr_clk(ren_spr_clk),
.spr_addr(ren_spr_addr),
.spr_data(ren_spr_data),
.coll_wr(ren_coll_wr),
.coll_addr(ren_coll_addr),
.coll_data(ren_coll_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(vga_hsync),
.v_sync(vga_vsync),
.rgb_out(vga_rgb));
wire [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values_out;
wire [`REG_DATA_WIDTH-1:0] reg_array_out [`NUM_MAIN_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : OUT_REGS
assign reg_array_out[i] = reg_values_out[`REG_DATA_WIDTH * (i + 1) - 1:
`REG_DATA_WIDTH * i];
end
endgenerate
reg reset_bit;
always @ (posedge clk or posedge reset) begin
if (reset)
reset_bit <= 0;
else
reset_bit <= reg_array_out[`SYS_CTRL][`SYS_CTRL_RESET];
end
wire master_reset = reset | reset_bit;
wire [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values_in;
wire [`REG_DATA_WIDTH-1:0] reg_array_in [`NUM_MAIN_REGS-1:0];
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : IN_REGS
assign reg_values_in[`REG_DATA_WIDTH * (i + 1) - 1: `REG_DATA_WIDTH * i] =
reg_array_in[i];
end
endgenerate
assign reg_array_in[`ID] = `ID_REG_VALUE;
DisplayTiming timing(.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(reg_array_in[`OUTPUT_STATUS][0]),
.v_sync(reg_array_in[`OUTPUT_STATUS][1]),
.h_blank(reg_array_in[`OUTPUT_STATUS][2]),
.v_blank(reg_array_in[`OUTPUT_STATUS][3]),
.h_visible_pos(reg_array_in[`SCAN_X]),
.v_visible_pos(reg_array_in[`SCAN_Y]));
wire main_regs_select = (mpu_addr >= `MAIN_REG_ADDR_BASE) &
(mpu_addr < `MAIN_REG_ADDR_BASE + `NUM_MAIN_REGS);
Registers #(.DATA_WIDTH(`REG_DATA_WIDTH),
.ADDR_WIDTH(`MAIN_REG_ADDR_WIDTH),
.NUM_REGS(`NUM_MAIN_REGS),
.IS_GENERIC(1))
registers(.clk(clk),
.reset(master_reset),
.en(main_regs_select),
.rd(mpu_rd),
.wr(mpu_wr),
.be(mpu_be),
.addr(mpu_addr[`MAIN_REG_ADDR_WIDTH-1:0]),
.data_in(mpu_data_in),
.data_out(reg_data_out),
.values_in(reg_values_in),
.values_out(reg_values_out));
wire tile_regs_select =
(mpu_addr >= `TILE_REG_ADDR_BASE) &
(mpu_addr < `TILE_REG_ADDR_BASE + `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS);
wire [`NUM_TILE_LAYERS-1:0] tile_layer_reg_select;
wire [`REG_DATA_WIDTH-1:0] tile_data_out_array[`NUM_TILE_LAYERS-1:0];
wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]
tile_values_out_array[`NUM_TILE_LAYERS-1:0];
wire [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES
assign tile_reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:
i * `NUM_REG_BITS_PER_TILE_LAYER]
= tile_values_out_array[i];
end
endgenerate
reg [`REG_DATA_WIDTH-1:0] tile_data_out;
wire [1:0] tile_index =
mpu_addr[`TILE_BLOCK_ADDR_WIDTH+1:`TILE_BLOCK_ADDR_WIDTH];
wire [`TILE_BLOCK_ADDR_WIDTH-1:0] tile_reg_addr =
mpu_addr[`TILE_BLOCK_ADDR_WIDTH-1:0];
always @ (*) begin
if (~tile_regs_select) begin
tile_data_out <= 'bx;
end else begin
if (tile_index < `NUM_TILE_REGISTERS)
tile_data_out <= tile_data_out_array[tile_index];
else
tile_data_out <= 0;
end
end
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_SELECT
assign tile_layer_reg_select[i] =
tile_regs_select &
(mpu_addr >= `TILE_REG_ADDR_BASE + i * `TILE_REG_ADDR_STEP) &
(mpu_addr < `TILE_REG_ADDR_BASE +
i * `TILE_REG_ADDR_STEP +
`NUM_TILE_REGISTERS);
Registers #(.DATA_WIDTH(`REG_DATA_WIDTH),
.ADDR_WIDTH(`TILE_REG_ADDR_WIDTH),
.NUM_REGS(`NUM_TILE_REGISTERS),
.IS_GENERIC(0))
tile_registers(.clk(clk),
.reset(master_reset),
.en(tile_layer_reg_select[i]),
.rd(mpu_rd),
.wr(mpu_wr),
.be(mpu_be),
.addr(mpu_addr[`TILE_REG_ADDR_WIDTH-1:0]),
.data_in(mpu_data_in[`REG_DATA_WIDTH-1:0]),
.data_out(tile_data_out_array[i]),
.values_in(0),
.values_out(tile_values_out_array[i]));
end
endgenerate
endmodule | 0 |
142,120 | data/full_repos/permissive/9705033/common/display_controller.v | 9,705,033 | display_controller.v | v | 170 | 82 | [] | ['general public license', 'free software foundation'] | [] | [(104, 147), (150, 219), (221, 279)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/display_controller.v:24: Cannot find include file: video_modes.vh\n`include "video_modes.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.sv\n video_modes.vh\n video_modes.vh.v\n video_modes.vh.sv\n obj_dir/video_modes.vh\n obj_dir/video_modes.vh.v\n obj_dir/video_modes.vh.sv\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:29: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:31: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] h_pos; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:32: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:60: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_pos <= v_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:64: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_pos <= h_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:75: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] h_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:76: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:77: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:85: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] h_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:86: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] v_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:103: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign h_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:104: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:105: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:106: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign v_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:108: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:141: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:145: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:148: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] h_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:149: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] v_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_LENGTH\'\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:152: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_LENGTH\'\n `VGA_640X480_60HZ_H_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:153: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_LENGTH\'\n `VGA_640X480_60HZ_H_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:154: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_LENGTH\'\n `VGA_640X480_60HZ_H_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:155: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_START\'\n `VGA_640X480_60HZ_H_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:156: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_START\'\n `VGA_640X480_60HZ_H_BACK_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:157: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_START\'\n `VGA_640X480_60HZ_H_VISIBLE_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:158: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_START\'\n `VGA_640X480_60HZ_H_FRONT_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:159: Define or directive not defined: \'`VGA_640X480_60HZ_H_TOTAL_LENGTH\'\n `VGA_640X480_60HZ_H_TOTAL_LENGTH };\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: Define or directive not defined: \'`VGA_640X480_60HZ_V_VISIBLE_LENGTH\'\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:161: Define or directive not defined: \'`VGA_640X480_60HZ_V_FRONT_LENGTH\'\n `VGA_640X480_60HZ_V_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:162: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_LENGTH\'\n `VGA_640X480_60HZ_V_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:163: Define or directive not defined: \'`VGA_640X480_60HZ_V_BACK_LENGTH\'\n `VGA_640X480_60HZ_V_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:164: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_START\'\n `VGA_640X480_60HZ_V_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,060 | module | module DisplayController(clk, reset, h_pos, v_pos, mode);
input clk;
input reset;
input [`VIDEO_MODE_WIDTH-1:0] mode;
output reg [`VIDEO_COUNT_WIDTH-1:0] h_pos;
output reg [`VIDEO_COUNT_WIDTH-1:0] v_pos;
wire h_end, v_end;
DisplayTiming timing(.h_pos(h_pos),
.v_pos(v_pos),
.h_end(h_end),
.v_end(v_end),
.mode(mode));
reg clk_25mhz;
always @ (posedge clk or posedge reset)
if (reset)
clk_25mhz <= 0;
else
clk_25mhz <= ~clk_25mhz;
always @ (posedge clk_25mhz or posedge reset)
begin
if (reset) begin
h_pos <= 0;
v_pos <= 0;
end else begin
if (h_end)
begin
if (v_end)
v_pos <= 0;
else
v_pos <= v_pos + `VIDEO_COUNT_WIDTH'b1;
h_pos <= 0;
end else
begin
h_pos <= h_pos + `VIDEO_COUNT_WIDTH'b1;
end
end
end
endmodule | module DisplayController(clk, reset, h_pos, v_pos, mode); |
input clk;
input reset;
input [`VIDEO_MODE_WIDTH-1:0] mode;
output reg [`VIDEO_COUNT_WIDTH-1:0] h_pos;
output reg [`VIDEO_COUNT_WIDTH-1:0] v_pos;
wire h_end, v_end;
DisplayTiming timing(.h_pos(h_pos),
.v_pos(v_pos),
.h_end(h_end),
.v_end(v_end),
.mode(mode));
reg clk_25mhz;
always @ (posedge clk or posedge reset)
if (reset)
clk_25mhz <= 0;
else
clk_25mhz <= ~clk_25mhz;
always @ (posedge clk_25mhz or posedge reset)
begin
if (reset) begin
h_pos <= 0;
v_pos <= 0;
end else begin
if (h_end)
begin
if (v_end)
v_pos <= 0;
else
v_pos <= v_pos + `VIDEO_COUNT_WIDTH'b1;
h_pos <= 0;
end else
begin
h_pos <= h_pos + `VIDEO_COUNT_WIDTH'b1;
end
end
end
endmodule | 0 |
142,121 | data/full_repos/permissive/9705033/common/display_controller.v | 9,705,033 | display_controller.v | v | 170 | 82 | [] | ['general public license', 'free software foundation'] | [] | [(104, 147), (150, 219), (221, 279)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/display_controller.v:24: Cannot find include file: video_modes.vh\n`include "video_modes.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.sv\n video_modes.vh\n video_modes.vh.v\n video_modes.vh.sv\n obj_dir/video_modes.vh\n obj_dir/video_modes.vh.v\n obj_dir/video_modes.vh.sv\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:29: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:31: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] h_pos; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:32: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:60: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_pos <= v_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:64: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_pos <= h_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:75: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] h_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:76: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:77: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:85: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] h_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:86: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] v_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:103: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign h_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:104: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:105: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:106: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign v_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:108: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:141: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:145: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:148: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] h_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:149: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] v_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_LENGTH\'\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:152: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_LENGTH\'\n `VGA_640X480_60HZ_H_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:153: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_LENGTH\'\n `VGA_640X480_60HZ_H_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:154: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_LENGTH\'\n `VGA_640X480_60HZ_H_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:155: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_START\'\n `VGA_640X480_60HZ_H_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:156: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_START\'\n `VGA_640X480_60HZ_H_BACK_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:157: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_START\'\n `VGA_640X480_60HZ_H_VISIBLE_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:158: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_START\'\n `VGA_640X480_60HZ_H_FRONT_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:159: Define or directive not defined: \'`VGA_640X480_60HZ_H_TOTAL_LENGTH\'\n `VGA_640X480_60HZ_H_TOTAL_LENGTH };\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: Define or directive not defined: \'`VGA_640X480_60HZ_V_VISIBLE_LENGTH\'\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:161: Define or directive not defined: \'`VGA_640X480_60HZ_V_FRONT_LENGTH\'\n `VGA_640X480_60HZ_V_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:162: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_LENGTH\'\n `VGA_640X480_60HZ_V_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:163: Define or directive not defined: \'`VGA_640X480_60HZ_V_BACK_LENGTH\'\n `VGA_640X480_60HZ_V_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:164: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_START\'\n `VGA_640X480_60HZ_V_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,060 | module | module DisplayTiming(h_pos, v_pos, h_sync, v_sync, h_blank, v_blank,
h_visible_pos, v_visible_pos, h_end, v_end,
mode);
input [`VIDEO_COUNT_WIDTH-1:0] h_pos;
input [`VIDEO_COUNT_WIDTH-1:0] v_pos;
input [`VIDEO_MODE_WIDTH-1:0] mode;
output h_sync, v_sync;
output h_blank, v_blank;
output [`VIDEO_COUNT_WIDTH-1:0] h_visible_pos;
output [`VIDEO_COUNT_WIDTH-1:0] v_visible_pos;
output h_end, v_end;
wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;
wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;
VideoModeDecoder decoder(mode, h_timing_values_array, v_timing_values_array);
wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];
wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];
genvar i;
generate
for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values
assign h_timing_values[`NUM_TIMING_VALUES - 1 - i] =
h_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:
`VIDEO_COUNT_WIDTH * i];
assign v_timing_values[`NUM_TIMING_VALUES - 1 - i] =
v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:
`VIDEO_COUNT_WIDTH * i];
end
endgenerate
`define H_VISIBLE_LENGTH h_timing_values[0]
`define H_FRONT_LENGTH h_timing_values[1]
`define H_SYNC_LENGTH h_timing_values[2]
`define H_BACK_LENGTH h_timing_values[3]
`define H_SYNC_START h_timing_values[4]
`define H_BACK_START h_timing_values[5]
`define H_VISIBLE_START h_timing_values[6]
`define H_FRONT_START h_timing_values[7]
`define H_TOTAL_LENGTH h_timing_values[8]
`define V_VISIBLE_LENGTH v_timing_values[0]
`define V_FRONT_LENGTH v_timing_values[1]
`define V_SYNC_LENGTH v_timing_values[2]
`define V_BACK_LENGTH v_timing_values[3]
`define V_SYNC_START v_timing_values[4]
`define V_BACK_START v_timing_values[5]
`define V_VISIBLE_START v_timing_values[6]
`define V_FRONT_START v_timing_values[7]
`define V_TOTAL_LENGTH v_timing_values[8]
assign h_sync = ~(h_pos < `H_SYNC_LENGTH);
assign v_sync = ~(v_pos < `V_SYNC_LENGTH);
assign h_blank = (h_pos < `H_VISIBLE_START || h_pos >= `H_FRONT_START);
assign v_blank = (v_pos < `V_VISIBLE_START || v_pos >= `V_FRONT_START);
assign h_visible_pos = h_pos - `H_VISIBLE_START;
assign v_visible_pos = v_pos - `V_VISIBLE_START;
assign h_end = (h_pos == (`H_TOTAL_LENGTH - 1));
assign v_end = (v_pos == (`V_TOTAL_LENGTH - 1));
endmodule | module DisplayTiming(h_pos, v_pos, h_sync, v_sync, h_blank, v_blank,
h_visible_pos, v_visible_pos, h_end, v_end,
mode); |
input [`VIDEO_COUNT_WIDTH-1:0] h_pos;
input [`VIDEO_COUNT_WIDTH-1:0] v_pos;
input [`VIDEO_MODE_WIDTH-1:0] mode;
output h_sync, v_sync;
output h_blank, v_blank;
output [`VIDEO_COUNT_WIDTH-1:0] h_visible_pos;
output [`VIDEO_COUNT_WIDTH-1:0] v_visible_pos;
output h_end, v_end;
wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;
wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;
VideoModeDecoder decoder(mode, h_timing_values_array, v_timing_values_array);
wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];
wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];
genvar i;
generate
for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values
assign h_timing_values[`NUM_TIMING_VALUES - 1 - i] =
h_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:
`VIDEO_COUNT_WIDTH * i];
assign v_timing_values[`NUM_TIMING_VALUES - 1 - i] =
v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:
`VIDEO_COUNT_WIDTH * i];
end
endgenerate
`define H_VISIBLE_LENGTH h_timing_values[0]
`define H_FRONT_LENGTH h_timing_values[1]
`define H_SYNC_LENGTH h_timing_values[2]
`define H_BACK_LENGTH h_timing_values[3]
`define H_SYNC_START h_timing_values[4]
`define H_BACK_START h_timing_values[5]
`define H_VISIBLE_START h_timing_values[6]
`define H_FRONT_START h_timing_values[7]
`define H_TOTAL_LENGTH h_timing_values[8]
`define V_VISIBLE_LENGTH v_timing_values[0]
`define V_FRONT_LENGTH v_timing_values[1]
`define V_SYNC_LENGTH v_timing_values[2]
`define V_BACK_LENGTH v_timing_values[3]
`define V_SYNC_START v_timing_values[4]
`define V_BACK_START v_timing_values[5]
`define V_VISIBLE_START v_timing_values[6]
`define V_FRONT_START v_timing_values[7]
`define V_TOTAL_LENGTH v_timing_values[8]
assign h_sync = ~(h_pos < `H_SYNC_LENGTH);
assign v_sync = ~(v_pos < `V_SYNC_LENGTH);
assign h_blank = (h_pos < `H_VISIBLE_START || h_pos >= `H_FRONT_START);
assign v_blank = (v_pos < `V_VISIBLE_START || v_pos >= `V_FRONT_START);
assign h_visible_pos = h_pos - `H_VISIBLE_START;
assign v_visible_pos = v_pos - `V_VISIBLE_START;
assign h_end = (h_pos == (`H_TOTAL_LENGTH - 1));
assign v_end = (v_pos == (`V_TOTAL_LENGTH - 1));
endmodule | 0 |
142,122 | data/full_repos/permissive/9705033/common/display_controller.v | 9,705,033 | display_controller.v | v | 170 | 82 | [] | ['general public license', 'free software foundation'] | [] | [(104, 147), (150, 219), (221, 279)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/display_controller.v:24: Cannot find include file: video_modes.vh\n`include "video_modes.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.sv\n video_modes.vh\n video_modes.vh.v\n video_modes.vh.sv\n obj_dir/video_modes.vh\n obj_dir/video_modes.vh.v\n obj_dir/video_modes.vh.sv\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:29: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode; \n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:31: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] h_pos; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:32: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output reg [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:60: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_pos <= v_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:64: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_pos <= h_pos + `VIDEO_COUNT_WIDTH\'b1;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:75: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] h_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:76: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n input [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:77: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:85: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] h_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:86: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH-1:0] v_visible_pos;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:90: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] h_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:91: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH * `NUM_TIMING_VALUES - 1:0] v_timing_values_array;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:96: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:97: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_timing_values [`NUM_TIMING_VALUES-1:0];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:100: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_TIMING_VALUES; i = i + 1) begin : timing_values\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:103: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign h_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:104: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n h_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:105: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:106: Define or directive not defined: \'`NUM_TIMING_VALUES\'\n assign v_timing_values[`NUM_TIMING_VALUES - 1 - i] =\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:107: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n v_timing_values_array[`VIDEO_COUNT_WIDTH * (i + 1) - 1:\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:108: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n `VIDEO_COUNT_WIDTH * i];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:141: syntax error, unexpected endmodule\nendmodule\n^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:145: Define or directive not defined: \'`VIDEO_MODE_WIDTH\'\n input [`VIDEO_MODE_WIDTH-1:0] mode;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:148: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] h_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:149: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n output [`VIDEO_COUNT_WIDTH*9-1:0] v_values;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_LENGTH\'\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:151: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:152: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_LENGTH\'\n `VGA_640X480_60HZ_H_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:153: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_LENGTH\'\n `VGA_640X480_60HZ_H_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:154: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_LENGTH\'\n `VGA_640X480_60HZ_H_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:155: Define or directive not defined: \'`VGA_640X480_60HZ_H_SYNC_START\'\n `VGA_640X480_60HZ_H_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:156: Define or directive not defined: \'`VGA_640X480_60HZ_H_BACK_START\'\n `VGA_640X480_60HZ_H_BACK_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:157: Define or directive not defined: \'`VGA_640X480_60HZ_H_VISIBLE_START\'\n `VGA_640X480_60HZ_H_VISIBLE_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:158: Define or directive not defined: \'`VGA_640X480_60HZ_H_FRONT_START\'\n `VGA_640X480_60HZ_H_FRONT_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:159: Define or directive not defined: \'`VGA_640X480_60HZ_H_TOTAL_LENGTH\'\n `VGA_640X480_60HZ_H_TOTAL_LENGTH };\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: Define or directive not defined: \'`VGA_640X480_60HZ_V_VISIBLE_LENGTH\'\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:160: syntax error, unexpected \',\', expecting TYPE-IDENTIFIER\n assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,\n ^\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:161: Define or directive not defined: \'`VGA_640X480_60HZ_V_FRONT_LENGTH\'\n `VGA_640X480_60HZ_V_FRONT_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:162: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_LENGTH\'\n `VGA_640X480_60HZ_V_SYNC_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:163: Define or directive not defined: \'`VGA_640X480_60HZ_V_BACK_LENGTH\'\n `VGA_640X480_60HZ_V_BACK_LENGTH,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller.v:164: Define or directive not defined: \'`VGA_640X480_60HZ_V_SYNC_START\'\n `VGA_640X480_60HZ_V_SYNC_START,\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,060 | module | module VideoModeDecoder(mode, h_values, v_values);
input [`VIDEO_MODE_WIDTH-1:0] mode;
output [`VIDEO_COUNT_WIDTH*9-1:0] h_values;
output [`VIDEO_COUNT_WIDTH*9-1:0] v_values;
assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,
`VGA_640X480_60HZ_H_FRONT_LENGTH,
`VGA_640X480_60HZ_H_SYNC_LENGTH,
`VGA_640X480_60HZ_H_BACK_LENGTH,
`VGA_640X480_60HZ_H_SYNC_START,
`VGA_640X480_60HZ_H_BACK_START,
`VGA_640X480_60HZ_H_VISIBLE_START,
`VGA_640X480_60HZ_H_FRONT_START,
`VGA_640X480_60HZ_H_TOTAL_LENGTH };
assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,
`VGA_640X480_60HZ_V_FRONT_LENGTH,
`VGA_640X480_60HZ_V_SYNC_LENGTH,
`VGA_640X480_60HZ_V_BACK_LENGTH,
`VGA_640X480_60HZ_V_SYNC_START,
`VGA_640X480_60HZ_V_BACK_START,
`VGA_640X480_60HZ_V_VISIBLE_START,
`VGA_640X480_60HZ_V_FRONT_START,
`VGA_640X480_60HZ_V_TOTAL_LENGTH };
endmodule | module VideoModeDecoder(mode, h_values, v_values); |
input [`VIDEO_MODE_WIDTH-1:0] mode;
output [`VIDEO_COUNT_WIDTH*9-1:0] h_values;
output [`VIDEO_COUNT_WIDTH*9-1:0] v_values;
assign h_values = { `VGA_640X480_60HZ_H_VISIBLE_LENGTH,
`VGA_640X480_60HZ_H_FRONT_LENGTH,
`VGA_640X480_60HZ_H_SYNC_LENGTH,
`VGA_640X480_60HZ_H_BACK_LENGTH,
`VGA_640X480_60HZ_H_SYNC_START,
`VGA_640X480_60HZ_H_BACK_START,
`VGA_640X480_60HZ_H_VISIBLE_START,
`VGA_640X480_60HZ_H_FRONT_START,
`VGA_640X480_60HZ_H_TOTAL_LENGTH };
assign v_values = { `VGA_640X480_60HZ_V_VISIBLE_LENGTH,
`VGA_640X480_60HZ_V_FRONT_LENGTH,
`VGA_640X480_60HZ_V_SYNC_LENGTH,
`VGA_640X480_60HZ_V_BACK_LENGTH,
`VGA_640X480_60HZ_V_SYNC_START,
`VGA_640X480_60HZ_V_BACK_START,
`VGA_640X480_60HZ_V_VISIBLE_START,
`VGA_640X480_60HZ_V_FRONT_START,
`VGA_640X480_60HZ_V_TOTAL_LENGTH };
endmodule | 0 |
142,123 | data/full_repos/permissive/9705033/common/display_controller_test.v | 9,705,033 | display_controller_test.v | v | 60 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(103, 137)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/display_controller_test.v:23: Cannot find include file: video_modes.vh\n`include "video_modes.vh" \n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/video_modes.vh.sv\n video_modes.vh\n video_modes.vh.v\n video_modes.vh.sv\n obj_dir/video_modes.vh\n obj_dir/video_modes.vh.v\n obj_dir/video_modes.vh.sv\n%Error: data/full_repos/permissive/9705033/common/display_controller_test.v:30: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] h_pos; \n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/display_controller_test.v:31: Define or directive not defined: \'`VIDEO_COUNT_WIDTH\'\n wire [`VIDEO_COUNT_WIDTH-1:0] v_pos;\n ^~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/display_controller_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/display_controller_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n #200 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/display_controller_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n #10 clk = !clk;\n ^\n%Error: Exiting due to 3 error(s), 3 warning(s)\n' | 313,061 | module | module DisplayController_Test;
reg clk;
reg reset;
wire [`VIDEO_COUNT_WIDTH-1:0] h_pos;
wire [`VIDEO_COUNT_WIDTH-1:0] v_pos;
wire hsync;
wire vsync;
wire hblank;
wire vblank;
DisplayController display_controller(.clk(clk),
.reset(reset),
.h_pos(h_pos),
.v_pos(v_pos));
DisplayTiming display_timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(hsync), .v_sync(vsync),
.h_blank(hblank), .v_blank(vblank));
initial begin
clk = 0;
reset = 0;
#100 reset = 1;
#200 reset = 0;
end
always
#10 clk = !clk;
endmodule | module DisplayController_Test; |
reg clk;
reg reset;
wire [`VIDEO_COUNT_WIDTH-1:0] h_pos;
wire [`VIDEO_COUNT_WIDTH-1:0] v_pos;
wire hsync;
wire vsync;
wire hblank;
wire vblank;
DisplayController display_controller(.clk(clk),
.reset(reset),
.h_pos(h_pos),
.v_pos(v_pos));
DisplayTiming display_timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(hsync), .v_sync(vsync),
.h_blank(hblank), .v_blank(vblank));
initial begin
clk = 0;
reset = 0;
#100 reset = 1;
#200 reset = 0;
end
always
#10 clk = !clk;
endmodule | 0 |
142,124 | data/full_repos/permissive/9705033/common/main_arduino_uno.v | 9,705,033 | main_arduino_uno.v | v | 194 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | Syntax Error | null | 1: b'%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:29: Cannot find include file: spi_memory.vh\n`include "spi_memory.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.sv\n spi_memory.vh\n spi_memory.vh.v\n spi_memory.vh.sv\n obj_dir/spi_memory.vh\n obj_dir/spi_memory.vh.v\n obj_dir/spi_memory.vh.sv\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:85: Define or directive not defined: \'`SPI_MEM_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n wire [`SPI_MEM_ADDR_WIDTH-1:0] spi_addr;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:86: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n : ... Suggested alternative: \'`MPU_DATA_WIDTH\'\n wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_in;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:87: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n : ... Suggested alternative: \'`MPU_DATA_WIDTH\'\n wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_out;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:97: Define or directive not defined: \'`SPI_MEM_ADDR_WIDTH\'\n : ... Suggested alternative: \'`MPU_ADDR_WIDTH\'\n {1\'b0, spi_addr[`SPI_MEM_ADDR_WIDTH-1:1]};\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:109: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_addr[0] ? cc_data_out[`BYTE_WIDTH*2-1:`BYTE_WIDTH]\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:109: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n spi_addr[0] ? cc_data_out[`BYTE_WIDTH*2-1:`BYTE_WIDTH]\n ^\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:109: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_addr[0] ? cc_data_out[`BYTE_WIDTH*2-1:`BYTE_WIDTH]\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_arduino_uno.v:110: Define or directive not defined: \'`BYTE_WIDTH\'\n : cc_data_out[`BYTE_WIDTH-1:0];\n ^~~~~~~~~~~\n%Error: Exiting due to 9 error(s)\n' | 313,062 | module | module MainArduinoUno(
clk, _reset,
_select, sck, mosi, miso,
_alt_select, alt_sck, alt_mosi, alt_miso,
_vram_en, _vram_rd, _vram_wr, _vram_be, vram_addr, vram_data,
vsync, hsync, rgb,
led, audio_l, audio_r);
input clk;
input _reset;
input _select, sck, mosi;
output miso;
input _alt_select, alt_sck, alt_mosi;
output alt_miso;
output _vram_en;
output _vram_rd;
output _vram_wr;
output [1:0] _vram_be;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
inout [`VRAM_DATA_WIDTH-1:0] vram_data;
output vsync;
output hsync;
output [`RGB_COLOR_DEPTH-1:0] rgb;
output led = mem_nss;
output audio_l;
output audio_r;
wire mem_nss, mem_sck, mem_mosi, mem_miso;
wire spi_bus_alt_miso;
SPIBus spi_bus(_select, sck, mosi, miso,
_alt_select, alt_sck, alt_mosi, spi_bus_alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
assign alt_miso = _alt_select ? 'bz : spi_bus_alt_miso;
wire [`SPI_MEM_ADDR_WIDTH-1:0] spi_addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_out;
wire spi_rd, spi_wr;
SPIMemory spi_memory(
._select(mem_nss), .sck(mem_sck), .mosi(mem_mosi), .miso(mem_miso),
.addr(spi_addr), .data_in(spi_data_in), .data_out(spi_data_out),
.rd(spi_rd), .wr(spi_wr));
wire [`MPU_ADDR_WIDTH-1:0] cc_addr =
{1'b0, spi_addr[`SPI_MEM_ADDR_WIDTH-1:1]};
wire [`MPU_DATA_WIDTH-1:0] cc_data_in = {spi_data_out, spi_data_out};
wire [`MPU_DATA_WIDTH-1:0] cc_data_out;
assign spi_data_in =
spi_addr[0] ? cc_data_out[`BYTE_WIDTH*2-1:`BYTE_WIDTH]
: cc_data_out[`BYTE_WIDTH-1:0];
wire [1:0] cc_byte_enable = spi_addr[0] ? 2'b10 : 2'b01;
wire cc_enable = (spi_rd ^ spi_wr);
wire vram_en;
wire vram_rd;
wire vram_wr;
wire [1:0] vram_be;
assign _vram_en = ~vram_en;
assign _vram_rd = ~vram_rd;
assign _vram_wr = ~vram_wr;
assign _vram_be = ~vram_be;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_in;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out;
assign vram_data = (vram_en & vram_wr) ? vram_data_out
: {`VRAM_DATA_WIDTH {1'bz}};
assign vram_data_in = vram_data;
Core core(.clk(clk),
.reset(~_reset),
.mpu_rd(spi_rd),
.mpu_wr(spi_wr),
.mpu_en(cc_enable),
.mpu_be(cc_byte_enable),
.mpu_addr_in(cc_addr),
.mpu_data_in(cc_data_in),
.mpu_data_out(cc_data_out),
.vram_en(vram_en),
.vram_rd(vram_rd),
.vram_wr(vram_wr),
.vram_be(vram_be),
.vram_addr(vram_addr),
.vram_data_in(vram_data_in),
.vram_data_out(vram_data_out),
.vga_vsync(vsync),
.vga_hsync(hsync),
.vga_rgb(rgb)
);
reg [7:0] pwm_counter;
always @ (posedge clk)
pwm_counter <= pwm_counter + 1'b1;
`define SLOW_PERIOD 200
`define FAST_PERIOD 100
reg [7:0] wave_counter_slow;
reg [7:0] wave_counter_fast;
always @ (negedge _reset or posedge clk) begin
if (~_reset) begin
wave_counter_slow <= 0;
wave_counter_fast <= 0;
end else if (pwm_counter == 0) begin
if (wave_counter_slow >= `SLOW_PERIOD - 1)
wave_counter_slow <= 0;
else
wave_counter_slow = wave_counter_slow + 1'b1;
if (wave_counter_fast >= `FAST_PERIOD - 1)
wave_counter_fast <= 0;
else
wave_counter_fast = wave_counter_fast + 1'b1;
end
end
assign audio_l = (wave_counter_slow > `SLOW_PERIOD / 2);
assign audio_r = (wave_counter_fast > `FAST_PERIOD / 2);
endmodule | module MainArduinoUno(
clk, _reset,
_select, sck, mosi, miso,
_alt_select, alt_sck, alt_mosi, alt_miso,
_vram_en, _vram_rd, _vram_wr, _vram_be, vram_addr, vram_data,
vsync, hsync, rgb,
led, audio_l, audio_r); |
input clk;
input _reset;
input _select, sck, mosi;
output miso;
input _alt_select, alt_sck, alt_mosi;
output alt_miso;
output _vram_en;
output _vram_rd;
output _vram_wr;
output [1:0] _vram_be;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
inout [`VRAM_DATA_WIDTH-1:0] vram_data;
output vsync;
output hsync;
output [`RGB_COLOR_DEPTH-1:0] rgb;
output led = mem_nss;
output audio_l;
output audio_r;
wire mem_nss, mem_sck, mem_mosi, mem_miso;
wire spi_bus_alt_miso;
SPIBus spi_bus(_select, sck, mosi, miso,
_alt_select, alt_sck, alt_mosi, spi_bus_alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
assign alt_miso = _alt_select ? 'bz : spi_bus_alt_miso;
wire [`SPI_MEM_ADDR_WIDTH-1:0] spi_addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] spi_data_out;
wire spi_rd, spi_wr;
SPIMemory spi_memory(
._select(mem_nss), .sck(mem_sck), .mosi(mem_mosi), .miso(mem_miso),
.addr(spi_addr), .data_in(spi_data_in), .data_out(spi_data_out),
.rd(spi_rd), .wr(spi_wr));
wire [`MPU_ADDR_WIDTH-1:0] cc_addr =
{1'b0, spi_addr[`SPI_MEM_ADDR_WIDTH-1:1]};
wire [`MPU_DATA_WIDTH-1:0] cc_data_in = {spi_data_out, spi_data_out};
wire [`MPU_DATA_WIDTH-1:0] cc_data_out;
assign spi_data_in =
spi_addr[0] ? cc_data_out[`BYTE_WIDTH*2-1:`BYTE_WIDTH]
: cc_data_out[`BYTE_WIDTH-1:0];
wire [1:0] cc_byte_enable = spi_addr[0] ? 2'b10 : 2'b01;
wire cc_enable = (spi_rd ^ spi_wr);
wire vram_en;
wire vram_rd;
wire vram_wr;
wire [1:0] vram_be;
assign _vram_en = ~vram_en;
assign _vram_rd = ~vram_rd;
assign _vram_wr = ~vram_wr;
assign _vram_be = ~vram_be;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_in;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out;
assign vram_data = (vram_en & vram_wr) ? vram_data_out
: {`VRAM_DATA_WIDTH {1'bz}};
assign vram_data_in = vram_data;
Core core(.clk(clk),
.reset(~_reset),
.mpu_rd(spi_rd),
.mpu_wr(spi_wr),
.mpu_en(cc_enable),
.mpu_be(cc_byte_enable),
.mpu_addr_in(cc_addr),
.mpu_data_in(cc_data_in),
.mpu_data_out(cc_data_out),
.vram_en(vram_en),
.vram_rd(vram_rd),
.vram_wr(vram_wr),
.vram_be(vram_be),
.vram_addr(vram_addr),
.vram_data_in(vram_data_in),
.vram_data_out(vram_data_out),
.vga_vsync(vsync),
.vga_hsync(hsync),
.vga_rgb(rgb)
);
reg [7:0] pwm_counter;
always @ (posedge clk)
pwm_counter <= pwm_counter + 1'b1;
`define SLOW_PERIOD 200
`define FAST_PERIOD 100
reg [7:0] wave_counter_slow;
reg [7:0] wave_counter_fast;
always @ (negedge _reset or posedge clk) begin
if (~_reset) begin
wave_counter_slow <= 0;
wave_counter_fast <= 0;
end else if (pwm_counter == 0) begin
if (wave_counter_slow >= `SLOW_PERIOD - 1)
wave_counter_slow <= 0;
else
wave_counter_slow = wave_counter_slow + 1'b1;
if (wave_counter_fast >= `FAST_PERIOD - 1)
wave_counter_fast <= 0;
else
wave_counter_fast = wave_counter_fast + 1'b1;
end
end
assign audio_l = (wave_counter_slow > `SLOW_PERIOD / 2);
assign audio_r = (wave_counter_fast > `FAST_PERIOD / 2);
endmodule | 0 |
142,125 | data/full_repos/permissive/9705033/common/main_avr.v | 9,705,033 | main_avr.v | v | 149 | 81 | [] | ['general public license', 'free software foundation'] | [] | [(35, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/9705033/common/main_avr.v:77: Cannot find file containing module: 'CC_DLatch'\n CC_DLatch #(8)\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_DLatch\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_DLatch.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/CC_DLatch.sv\n CC_DLatch\n CC_DLatch.v\n CC_DLatch.sv\n obj_dir/CC_DLatch\n obj_dir/CC_DLatch.v\n obj_dir/CC_DLatch.sv\n%Error: data/full_repos/permissive/9705033/common/main_avr.v:125: Cannot find file containing module: 'Core'\n Core core(.clk(clk),\n ^~~~\n%Error: Exiting due to 2 error(s)\n" | 313,063 | module | module MainAVR(clk, _reset,
_mpu_rd, _mpu_wr, mpu_ale, mpu_ah, mpu_ad,
_vram_en, _vram_rd, _vram_wr, _vram_be, vram_addr, vram_data,
vsync, hsync, rgb);
input clk;
input _reset;
input _mpu_rd;
input _mpu_wr;
input mpu_ale;
input [`AVR_MPU_AH_BUS_WIDTH-1:0] mpu_ah;
inout [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_ad;
output _vram_en;
output _vram_rd;
output _vram_wr;
output [1:0] _vram_be;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
inout [`VRAM_DATA_WIDTH-1:0] vram_data;
output vsync;
output hsync;
output [`RGB_COLOR_DEPTH-1:0] rgb;
wire [`AVR_MPU_ADDR_WIDTH-1:0] cc_addr;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_in;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_out;
wire [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_al;
CC_DLatch #(`AVR_MPU_AD_BUS_WIDTH)
address_latch(.en(mpu_ale),
.d(mpu_ad),
.q(mpu_al));
assign cc_addr = {1'b0, mpu_ah, mpu_al[`AVR_MPU_AD_BUS_WIDTH-1:1]};
assign mpu_ad = (~_mpu_rd & _mpu_wr & ~mpu_ale) ? mpu_data_out
: {`AVR_MPU_DATA_WIDTH{1'bz}};
wire [`MPU_DATA_WIDTH-1:0] cc_data_in;
wire [`MPU_DATA_WIDTH-1:0] cc_data_out;
assign cc_data_in = {mpu_ad, mpu_ad};
assign mpu_data_out =
mpu_al[0] ? cc_data_out[`MPU_DATA_WIDTH-1:`AVR_MPU_DATA_WIDTH]
: cc_data_out[`AVR_MPU_DATA_WIDTH-1:0];
wire [1:0] _mpu_be = mpu_al[0] ? 2'b01 : 2'b10;
wire _mpu_en = ~(~_mpu_rd ^ ~_mpu_wr);
wire vram_en;
wire vram_rd;
wire vram_wr;
wire [1:0] vram_be;
assign _vram_en = ~vram_en;
assign _vram_rd = ~vram_rd;
assign _vram_wr = ~vram_wr;
assign _vram_be = ~vram_be;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_in;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out;
assign vram_data = (vram_en & vram_wr) ? vram_data_out
: {`VRAM_DATA_WIDTH {1'bz}};
assign vram_data_in = vram_data;
Core core(.clk(clk),
.reset(~_reset),
.mpu_rd(~_mpu_rd),
.mpu_wr(~_mpu_wr),
.mpu_en(~_mpu_en),
.mpu_be(~_mpu_be),
.mpu_addr_in(cc_addr),
.mpu_data_in(cc_data_in),
.mpu_data_out(cc_data_out),
.vram_en(vram_en),
.vram_rd(vram_rd),
.vram_wr(vram_wr),
.vram_be(vram_be),
.vram_addr(vram_addr),
.vram_data_in(vram_data_in),
.vram_data_out(vram_data_out),
.vga_vsync(vsync),
.vga_hsync(hsync),
.vga_rgb(rgb)
);
endmodule | module MainAVR(clk, _reset,
_mpu_rd, _mpu_wr, mpu_ale, mpu_ah, mpu_ad,
_vram_en, _vram_rd, _vram_wr, _vram_be, vram_addr, vram_data,
vsync, hsync, rgb); |
input clk;
input _reset;
input _mpu_rd;
input _mpu_wr;
input mpu_ale;
input [`AVR_MPU_AH_BUS_WIDTH-1:0] mpu_ah;
inout [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_ad;
output _vram_en;
output _vram_rd;
output _vram_wr;
output [1:0] _vram_be;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
inout [`VRAM_DATA_WIDTH-1:0] vram_data;
output vsync;
output hsync;
output [`RGB_COLOR_DEPTH-1:0] rgb;
wire [`AVR_MPU_ADDR_WIDTH-1:0] cc_addr;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_in;
wire [`AVR_MPU_DATA_WIDTH-1:0] mpu_data_out;
wire [`AVR_MPU_AD_BUS_WIDTH-1:0] mpu_al;
CC_DLatch #(`AVR_MPU_AD_BUS_WIDTH)
address_latch(.en(mpu_ale),
.d(mpu_ad),
.q(mpu_al));
assign cc_addr = {1'b0, mpu_ah, mpu_al[`AVR_MPU_AD_BUS_WIDTH-1:1]};
assign mpu_ad = (~_mpu_rd & _mpu_wr & ~mpu_ale) ? mpu_data_out
: {`AVR_MPU_DATA_WIDTH{1'bz}};
wire [`MPU_DATA_WIDTH-1:0] cc_data_in;
wire [`MPU_DATA_WIDTH-1:0] cc_data_out;
assign cc_data_in = {mpu_ad, mpu_ad};
assign mpu_data_out =
mpu_al[0] ? cc_data_out[`MPU_DATA_WIDTH-1:`AVR_MPU_DATA_WIDTH]
: cc_data_out[`AVR_MPU_DATA_WIDTH-1:0];
wire [1:0] _mpu_be = mpu_al[0] ? 2'b01 : 2'b10;
wire _mpu_en = ~(~_mpu_rd ^ ~_mpu_wr);
wire vram_en;
wire vram_rd;
wire vram_wr;
wire [1:0] vram_be;
assign _vram_en = ~vram_en;
assign _vram_rd = ~vram_rd;
assign _vram_wr = ~vram_wr;
assign _vram_be = ~vram_be;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_in;
wire [`VRAM_DATA_WIDTH-1:0] vram_data_out;
assign vram_data = (vram_en & vram_wr) ? vram_data_out
: {`VRAM_DATA_WIDTH {1'bz}};
assign vram_data_in = vram_data;
Core core(.clk(clk),
.reset(~_reset),
.mpu_rd(~_mpu_rd),
.mpu_wr(~_mpu_wr),
.mpu_en(~_mpu_en),
.mpu_be(~_mpu_be),
.mpu_addr_in(cc_addr),
.mpu_data_in(cc_data_in),
.mpu_data_out(cc_data_out),
.vram_en(vram_en),
.vram_rd(vram_rd),
.vram_wr(vram_wr),
.vram_be(vram_be),
.vram_addr(vram_addr),
.vram_data_in(vram_data_in),
.vram_data_out(vram_data_out),
.vga_vsync(vsync),
.vga_hsync(hsync),
.vga_rgb(rgb)
);
endmodule | 0 |
142,126 | data/full_repos/permissive/9705033/common/main_avr_test.v | 9,705,033 | main_avr_test.v | v | 186 | 79 | [] | ['general public license', 'free software foundation'] | [] | null | line:306: before: "(" | null | 1: b'%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:23: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:24: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:72: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(0, \'hdead);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:79: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(2, \'hbeef);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(4, \'hcafe);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:81: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(8, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(16, \'hbead);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(18, \'hfade);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:84: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(24, \'hdeaf);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(26, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(28, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(30, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:89: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:93: Unsupported: Ignoring delay on this delayed statement.\n #1 read_test();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:95: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:98: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:101: Unsupported: Ignoring delay on this delayed statement.\n #1 write8(i * 2, \'h0000);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:102: Unsupported: Ignoring delay on this delayed statement.\n #1 write8(i * 2 + 1, \'hffff);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:106: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:107: Unsupported: Ignoring delay on this delayed statement.\n #1 read_test();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/main_avr_test.v:110: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 6;\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:111: Define or directive not defined: \'`TILE_REG_ADDR_STEP\'\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:111: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:111: Define or directive not defined: \'`NUM_TILE_LAYERS\'\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:111: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:113: Define or directive not defined: \'`TILE_REG_ADDR_BASE\'\n #1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:117: Define or directive not defined: \'`TILE_REG_ADDR_STEP\'\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:117: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:117: Define or directive not defined: \'`NUM_TILE_LAYERS\'\n for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:119: Define or directive not defined: \'`TILE_REG_ADDR_BASE\'\n #1 read8((`TILE_REG_ADDR_BASE + i) * 2);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:120: Define or directive not defined: \'`TILE_REG_ADDR_BASE\'\n #1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:127: syntax error, unexpected \'#\'\n #1 write16(\'h1000 + i * 2, ~i);\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:133: syntax error, unexpected \'#\'\n #1 read8(\'h1000 + i);\n ^\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:141: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:155: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:164: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/main_avr_test.v:175: syntax error, unexpected begin\n begin\n ^~~~~\n%Error: Cannot continue\n' | 313,064 | module | module Main_Test;
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=8;
reg clk;
reg reset;
reg rd;
reg wr;
reg ale;
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
reg data_valid;
wire [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] ad;
MainAVR main_avr(._reset(~reset), .clk(clk),
._mpu_rd(~rd), ._mpu_wr(~wr), .mpu_ale(ale),
.mpu_ah(addr[ADDR_WIDTH-1:DATA_WIDTH]), .mpu_ad(ad));
assign data_out = (rd & ~wr & ~ale) ? ad : 'bx;
assign ad = ale ? addr[DATA_WIDTH-1:0] : (data_valid ? data_in : 'bz);
always
#1 clk = ~clk;
integer i;
reg [4:0] stage = 0;
initial begin
clk = 0;
reset = 0;
rd = 0;
wr = 0;
addr = 0;
data_in = 0;
data_valid = 0;
#5 stage = 1;
#1 reset = 1;
#5 reset = 0;
#1 addr = 'bx;
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
#5 stage = 4;
for (i = 0; i < 16; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
#5 stage = 5;
#1 read_test();
#5 stage = 6;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);
end
#5 stage = 7;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 read8((`TILE_REG_ADDR_BASE + i) * 2);
#1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);
end
#5 stage = 8;
for (i = 0; i < 16; i = i + 1)
begin
#1 write16('h1000 + i * 2, ~i);
end
#5 stage = 9;
for (i = 0; i < 32; i = i + 1)
begin
#1 read8('h1000 + i);
end
end
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg;
data_in = data_arg;
#2 rd = 0; wr = 0; ale = 1; data_valid = 0;
#2 rd = 0; wr = 1; ale = 0; data_valid = 1;
#2 rd = 0; wr = 0; ale = 0; data_valid = 1;
#2 data_valid = 0;
end
endtask
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH*2-1:0] data_arg;
begin
write8(addr_arg, data_arg[DATA_WIDTH-1:0]);
write8(addr_arg + 1, data_arg[DATA_WIDTH*2-1:DATA_WIDTH]);
end
endtask
task read8;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg;
#2 rd = 0; wr = 0; ale = 1;
#2 rd = 1; wr = 0; ale = 0;
#2 rd = 0; wr = 0; ale = 0;
end
endtask
task read_test;
integer i;
begin
#5
for (i = 0; i < 30; i = i + 1) begin
#1 read8(i);
end
end
endtask
endmodule | module Main_Test; |
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=8;
reg clk;
reg reset;
reg rd;
reg wr;
reg ale;
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
reg data_valid;
wire [DATA_WIDTH-1:0] data_out;
wire [DATA_WIDTH-1:0] ad;
MainAVR main_avr(._reset(~reset), .clk(clk),
._mpu_rd(~rd), ._mpu_wr(~wr), .mpu_ale(ale),
.mpu_ah(addr[ADDR_WIDTH-1:DATA_WIDTH]), .mpu_ad(ad));
assign data_out = (rd & ~wr & ~ale) ? ad : 'bx;
assign ad = ale ? addr[DATA_WIDTH-1:0] : (data_valid ? data_in : 'bz);
always
#1 clk = ~clk;
integer i;
reg [4:0] stage = 0;
initial begin
clk = 0;
reset = 0;
rd = 0;
wr = 0;
addr = 0;
data_in = 0;
data_valid = 0;
#5 stage = 1;
#1 reset = 1;
#5 reset = 0;
#1 addr = 'bx;
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
#5 stage = 4;
for (i = 0; i < 16; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
#5 stage = 5;
#1 read_test();
#5 stage = 6;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 write16((`TILE_REG_ADDR_BASE + i) * 2, ~i);
end
#5 stage = 7;
for (i = 0; i < `TILE_REG_ADDR_STEP * `NUM_TILE_LAYERS; i = i + 1)
begin
#1 read8((`TILE_REG_ADDR_BASE + i) * 2);
#1 read8((`TILE_REG_ADDR_BASE + i) * 2 + 1);
end
#5 stage = 8;
for (i = 0; i < 16; i = i + 1)
begin
#1 write16('h1000 + i * 2, ~i);
end
#5 stage = 9;
for (i = 0; i < 32; i = i + 1)
begin
#1 read8('h1000 + i);
end
end
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg;
data_in = data_arg;
#2 rd = 0; wr = 0; ale = 1; data_valid = 0;
#2 rd = 0; wr = 1; ale = 0; data_valid = 1;
#2 rd = 0; wr = 0; ale = 0; data_valid = 1;
#2 data_valid = 0;
end
endtask
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH*2-1:0] data_arg;
begin
write8(addr_arg, data_arg[DATA_WIDTH-1:0]);
write8(addr_arg + 1, data_arg[DATA_WIDTH*2-1:DATA_WIDTH]);
end
endtask
task read8;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg;
#2 rd = 0; wr = 0; ale = 1;
#2 rd = 1; wr = 0; ale = 0;
#2 rd = 0; wr = 0; ale = 0;
end
endtask
task read_test;
integer i;
begin
#5
for (i = 0; i < 30; i = i + 1) begin
#1 read8(i);
end
end
endtask
endmodule | 0 |
142,127 | data/full_repos/permissive/9705033/common/palette.v | 9,705,033 | palette.v | v | 65 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(21, 64)] | null | null | 1: b"%Error: data/full_repos/permissive/9705033/common/palette.v:48: Cannot find file containing module: 'palette_ram_1Kx8'\n palette_ram_1Kx8 ram(.clock_a(clk_a), .clock_b(clk_b),\n ^~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/palette_ram_1Kx8\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/palette_ram_1Kx8.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/palette_ram_1Kx8.sv\n palette_ram_1Kx8\n palette_ram_1Kx8.v\n palette_ram_1Kx8.sv\n obj_dir/palette_ram_1Kx8\n obj_dir/palette_ram_1Kx8.v\n obj_dir/palette_ram_1Kx8.sv\n%Error: Exiting due to 1 error(s)\n" | 313,066 | module | module Palette(
clk_a, wr_a, rd_a, addr_a, data_in_a, data_out_a, byte_en_a,
clk_b, wr_b, rd_b, addr_b, data_in_b, data_out_b);
parameter NUM_CHANNELS = 3;
localparam BITS_PER_BYTE = 8;
localparam DATA_WIDTH = NUM_CHANNELS * BITS_PER_BYTE;
localparam ADDR_WIDTH = 10;
input clk_a;
input wr_a;
input rd_a;
input [NUM_CHANNELS-1:0] byte_en_a;
input [ADDR_WIDTH-1:0] addr_a;
input [DATA_WIDTH-1:0] data_in_a;
output [DATA_WIDTH-1:0] data_out_a;
input clk_b;
input wr_b;
input rd_b;
input [ADDR_WIDTH-1:0] addr_b;
input [DATA_WIDTH-1:0] data_in_b;
output [DATA_WIDTH-1:0] data_out_b;
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : RAM
palette_ram_1Kx8 ram(.clock_a(clk_a), .clock_b(clk_b),
.address_a(addr_a), .address_b(addr_b),
.wren_a(wr_a), .wren_b(wr_b),
.rden_a(rd_a), .rden_b(rd_b),
.data_a(data_in_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.data_b(data_in_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_a(data_out_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_b(data_out_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.byteena_a(byte_en_a[i]));
end
endgenerate
endmodule | module Palette(
clk_a, wr_a, rd_a, addr_a, data_in_a, data_out_a, byte_en_a,
clk_b, wr_b, rd_b, addr_b, data_in_b, data_out_b); |
parameter NUM_CHANNELS = 3;
localparam BITS_PER_BYTE = 8;
localparam DATA_WIDTH = NUM_CHANNELS * BITS_PER_BYTE;
localparam ADDR_WIDTH = 10;
input clk_a;
input wr_a;
input rd_a;
input [NUM_CHANNELS-1:0] byte_en_a;
input [ADDR_WIDTH-1:0] addr_a;
input [DATA_WIDTH-1:0] data_in_a;
output [DATA_WIDTH-1:0] data_out_a;
input clk_b;
input wr_b;
input rd_b;
input [ADDR_WIDTH-1:0] addr_b;
input [DATA_WIDTH-1:0] data_in_b;
output [DATA_WIDTH-1:0] data_out_b;
genvar i;
generate
for (i = 0; i < NUM_CHANNELS; i = i + 1) begin : RAM
palette_ram_1Kx8 ram(.clock_a(clk_a), .clock_b(clk_b),
.address_a(addr_a), .address_b(addr_b),
.wren_a(wr_a), .wren_b(wr_b),
.rden_a(rd_a), .rden_b(rd_b),
.data_a(data_in_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.data_b(data_in_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_a(data_out_a[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.q_b(data_out_b[(i + 1) * BITS_PER_BYTE - 1 :
i * BITS_PER_BYTE]),
.byteena_a(byte_en_a[i]));
end
endgenerate
endmodule | 0 |
142,128 | data/full_repos/permissive/9705033/common/registers.v | 9,705,033 | registers.v | v | 160 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/9705033/common/registers.v:24: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/registers.v:25: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: Define or directive not defined: \'`REG_RW\'\n parameter TYPE=`REG_RW; \n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter TYPE=`REG_RW; \n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: Define or directive not defined: \'`REG_RW\'\n if (TYPE == `REG_RW) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (TYPE == `REG_RW) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:74: syntax error, unexpected input\n input clk; \n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`ID\'\n `ID: register_type = `REG_RO;\n ^~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: syntax error, unexpected \':\', expecting endcase\n `ID: register_type = `REG_RO;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`REG_RO\'\n `ID: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`OUTPUT_STATUS\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`REG_RO\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`SCAN_X\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`REG_RO\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`SCAN_Y\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`REG_RO\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`SYS_CTRL\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`REG_RW\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`MEM_BANK\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`REG_RW\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`OUTPUT_CTRL\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`REG_RW\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`MODE_CTRL\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`REG_RW\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`SPRITE_Z\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`REG_RW\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`SCROLL_X\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`REG_RW\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`SCROLL_Y\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`REG_RW\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:109: Define or directive not defined: \'`REG_RO\'\n default: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`TILE_CTRL0\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: syntax error, unexpected \':\', expecting endcase\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`REG_RW\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`TILE_DATA_OFFSET\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`REG_RW\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`TILE_NOP_VALUE\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`REG_RW\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`TILE_COLOR_KEY\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`REG_RW\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`TILE_OFFSET_X\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`TILE_OFFSET_Y\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:129: Define or directive not defined: \'`REG_RO\'\n default: tile_reg_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:152: syntax error, unexpected endgenerate\n endgenerate\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 313,067 | module | module Register(reset, clk, en, be, d, q, value_in);
parameter WIDTH=16;
parameter BUS_WIDTH=16;
parameter TYPE=`REG_RW;
input clk;
input reset;
input en;
input [1:0] be;
input [BUS_WIDTH-1:0] d;
output [BUS_WIDTH-1:0] q;
input [BUS_WIDTH-1:0] value_in;
wire byte_lo_en = be[0];
wire byte_hi_en = be[1];
genvar i;
generate
if (TYPE == `REG_RW) begin
for (i = 0; i < BUS_WIDTH; i = i + 1) begin: REG
if (i < WIDTH) begin
CC_DFlipFlop #(1) dff(.clk(clk),
.reset(reset),
.en(en & ((i < 8) ? byte_lo_en : byte_hi_en)),
.d(d[i]),
.q(q[i]));
end else begin
assign q[i] = 1'b0;
end
end
end else begin
assign q = value_in;
end
endgenerate
endmodule | module Register(reset, clk, en, be, d, q, value_in); |
parameter WIDTH=16;
parameter BUS_WIDTH=16;
parameter TYPE=`REG_RW;
input clk;
input reset;
input en;
input [1:0] be;
input [BUS_WIDTH-1:0] d;
output [BUS_WIDTH-1:0] q;
input [BUS_WIDTH-1:0] value_in;
wire byte_lo_en = be[0];
wire byte_hi_en = be[1];
genvar i;
generate
if (TYPE == `REG_RW) begin
for (i = 0; i < BUS_WIDTH; i = i + 1) begin: REG
if (i < WIDTH) begin
CC_DFlipFlop #(1) dff(.clk(clk),
.reset(reset),
.en(en & ((i < 8) ? byte_lo_en : byte_hi_en)),
.d(d[i]),
.q(q[i]));
end else begin
assign q[i] = 1'b0;
end
end
end else begin
assign q = value_in;
end
endgenerate
endmodule | 0 |
142,129 | data/full_repos/permissive/9705033/common/registers.v | 9,705,033 | registers.v | v | 160 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/9705033/common/registers.v:24: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/registers.v:25: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: Define or directive not defined: \'`REG_RW\'\n parameter TYPE=`REG_RW; \n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter TYPE=`REG_RW; \n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: Define or directive not defined: \'`REG_RW\'\n if (TYPE == `REG_RW) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (TYPE == `REG_RW) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:74: syntax error, unexpected input\n input clk; \n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`ID\'\n `ID: register_type = `REG_RO;\n ^~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: syntax error, unexpected \':\', expecting endcase\n `ID: register_type = `REG_RO;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`REG_RO\'\n `ID: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`OUTPUT_STATUS\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`REG_RO\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`SCAN_X\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`REG_RO\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`SCAN_Y\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`REG_RO\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`SYS_CTRL\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`REG_RW\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`MEM_BANK\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`REG_RW\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`OUTPUT_CTRL\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`REG_RW\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`MODE_CTRL\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`REG_RW\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`SPRITE_Z\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`REG_RW\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`SCROLL_X\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`REG_RW\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`SCROLL_Y\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`REG_RW\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:109: Define or directive not defined: \'`REG_RO\'\n default: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`TILE_CTRL0\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: syntax error, unexpected \':\', expecting endcase\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`REG_RW\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`TILE_DATA_OFFSET\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`REG_RW\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`TILE_NOP_VALUE\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`REG_RW\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`TILE_COLOR_KEY\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`REG_RW\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`TILE_OFFSET_X\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`TILE_OFFSET_Y\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:129: Define or directive not defined: \'`REG_RO\'\n default: tile_reg_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:152: syntax error, unexpected endgenerate\n endgenerate\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 313,067 | module | module Registers(clk, reset, en, rd, wr, be, addr, data_in, data_out,
values_in, values_out);
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=16;
parameter NUM_REGS=(1 << ADDR_WIDTH);
parameter IS_GENERIC=1;
input clk;
input reset;
input en;
input rd;
input wr;
input [1:0] be;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output reg [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH * NUM_REGS - 1 : 0] values_in;
output [DATA_WIDTH * NUM_REGS - 1 : 0] values_out;
function integer register_type;
input [31:0] address;
begin
case (address)
`ID: register_type = `REG_RO;
`OUTPUT_STATUS: register_type = `REG_RO;
`SCAN_X: register_type = `REG_RO;
`SCAN_Y: register_type = `REG_RO;
`SYS_CTRL: register_type = `REG_RW;
`MEM_BANK: register_type = `REG_RW;
`OUTPUT_CTRL: register_type = `REG_RW;
`MODE_CTRL: register_type = `REG_RW;
`SPRITE_Z: register_type = `REG_RW;
`SCROLL_X: register_type = `REG_RW;
`SCROLL_Y: register_type = `REG_RW;
default: register_type = `REG_RO;
endcase
end
endfunction
function integer tile_reg_type;
input [31:0] address;
begin
case (address)
`TILE_CTRL0: tile_reg_type = `REG_RW;
`TILE_DATA_OFFSET: tile_reg_type = `REG_RW;
`TILE_NOP_VALUE: tile_reg_type = `REG_RW;
`TILE_COLOR_KEY: tile_reg_type = `REG_RW;
`TILE_OFFSET_X: tile_reg_type = `REG_RW;
`TILE_OFFSET_Y: tile_reg_type = `REG_RW;
default: tile_reg_type = `REG_RO;
endcase
end
endfunction
wire [DATA_WIDTH-1:0] q_array [NUM_REGS - 1:0];
genvar i;
generate
for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS
Register #(.WIDTH(DATA_WIDTH),
.TYPE(IS_GENERIC ? register_type(i) : tile_reg_type(i)))
register(.clk(~wr),
.en(en & ~rd & (i == addr)),
.reset(reset),
.be(be),
.d(data_in),
.q(q_array[i]),
.value_in(values_in[DATA_WIDTH * (i + 1) - 1 :
DATA_WIDTH * i]));
assign values_out[DATA_WIDTH * (i + 1) - 1 : DATA_WIDTH * i] = q_array[i];
end
endgenerate
always @ (posedge clk)
if (en & rd)
data_out <= q_array[addr];
endmodule | module Registers(clk, reset, en, rd, wr, be, addr, data_in, data_out,
values_in, values_out); |
parameter ADDR_WIDTH=16;
parameter DATA_WIDTH=16;
parameter NUM_REGS=(1 << ADDR_WIDTH);
parameter IS_GENERIC=1;
input clk;
input reset;
input en;
input rd;
input wr;
input [1:0] be;
input [ADDR_WIDTH-1:0] addr;
input [DATA_WIDTH-1:0] data_in;
output reg [DATA_WIDTH-1:0] data_out;
input [DATA_WIDTH * NUM_REGS - 1 : 0] values_in;
output [DATA_WIDTH * NUM_REGS - 1 : 0] values_out;
function integer register_type;
input [31:0] address;
begin
case (address)
`ID: register_type = `REG_RO;
`OUTPUT_STATUS: register_type = `REG_RO;
`SCAN_X: register_type = `REG_RO;
`SCAN_Y: register_type = `REG_RO;
`SYS_CTRL: register_type = `REG_RW;
`MEM_BANK: register_type = `REG_RW;
`OUTPUT_CTRL: register_type = `REG_RW;
`MODE_CTRL: register_type = `REG_RW;
`SPRITE_Z: register_type = `REG_RW;
`SCROLL_X: register_type = `REG_RW;
`SCROLL_Y: register_type = `REG_RW;
default: register_type = `REG_RO;
endcase
end
endfunction
function integer tile_reg_type;
input [31:0] address;
begin
case (address)
`TILE_CTRL0: tile_reg_type = `REG_RW;
`TILE_DATA_OFFSET: tile_reg_type = `REG_RW;
`TILE_NOP_VALUE: tile_reg_type = `REG_RW;
`TILE_COLOR_KEY: tile_reg_type = `REG_RW;
`TILE_OFFSET_X: tile_reg_type = `REG_RW;
`TILE_OFFSET_Y: tile_reg_type = `REG_RW;
default: tile_reg_type = `REG_RO;
endcase
end
endfunction
wire [DATA_WIDTH-1:0] q_array [NUM_REGS - 1:0];
genvar i;
generate
for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS
Register #(.WIDTH(DATA_WIDTH),
.TYPE(IS_GENERIC ? register_type(i) : tile_reg_type(i)))
register(.clk(~wr),
.en(en & ~rd & (i == addr)),
.reset(reset),
.be(be),
.d(data_in),
.q(q_array[i]),
.value_in(values_in[DATA_WIDTH * (i + 1) - 1 :
DATA_WIDTH * i]));
assign values_out[DATA_WIDTH * (i + 1) - 1 : DATA_WIDTH * i] = q_array[i];
end
endgenerate
always @ (posedge clk)
if (en & rd)
data_out <= q_array[addr];
endmodule | 0 |
142,130 | data/full_repos/permissive/9705033/common/registers.v | 9,705,033 | registers.v | v | 160 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/9705033/common/registers.v:24: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/registers.v:25: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: Define or directive not defined: \'`REG_RW\'\n parameter TYPE=`REG_RW; \n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter TYPE=`REG_RW; \n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: Define or directive not defined: \'`REG_RW\'\n if (TYPE == `REG_RW) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (TYPE == `REG_RW) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:74: syntax error, unexpected input\n input clk; \n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`ID\'\n `ID: register_type = `REG_RO;\n ^~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: syntax error, unexpected \':\', expecting endcase\n `ID: register_type = `REG_RO;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`REG_RO\'\n `ID: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`OUTPUT_STATUS\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`REG_RO\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`SCAN_X\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`REG_RO\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`SCAN_Y\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`REG_RO\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`SYS_CTRL\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`REG_RW\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`MEM_BANK\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`REG_RW\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`OUTPUT_CTRL\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`REG_RW\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`MODE_CTRL\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`REG_RW\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`SPRITE_Z\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`REG_RW\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`SCROLL_X\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`REG_RW\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`SCROLL_Y\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`REG_RW\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:109: Define or directive not defined: \'`REG_RO\'\n default: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`TILE_CTRL0\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: syntax error, unexpected \':\', expecting endcase\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`REG_RW\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`TILE_DATA_OFFSET\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`REG_RW\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`TILE_NOP_VALUE\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`REG_RW\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`TILE_COLOR_KEY\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`REG_RW\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`TILE_OFFSET_X\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`TILE_OFFSET_Y\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:129: Define or directive not defined: \'`REG_RO\'\n default: tile_reg_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:152: syntax error, unexpected endgenerate\n endgenerate\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 313,067 | function | function integer register_type;
input [31:0] address;
begin
case (address)
`ID: register_type = `REG_RO;
`OUTPUT_STATUS: register_type = `REG_RO;
`SCAN_X: register_type = `REG_RO;
`SCAN_Y: register_type = `REG_RO;
`SYS_CTRL: register_type = `REG_RW;
`MEM_BANK: register_type = `REG_RW;
`OUTPUT_CTRL: register_type = `REG_RW;
`MODE_CTRL: register_type = `REG_RW;
`SPRITE_Z: register_type = `REG_RW;
`SCROLL_X: register_type = `REG_RW;
`SCROLL_Y: register_type = `REG_RW;
default: register_type = `REG_RO;
endcase
end
endfunction | function integer register_type; |
input [31:0] address;
begin
case (address)
`ID: register_type = `REG_RO;
`OUTPUT_STATUS: register_type = `REG_RO;
`SCAN_X: register_type = `REG_RO;
`SCAN_Y: register_type = `REG_RO;
`SYS_CTRL: register_type = `REG_RW;
`MEM_BANK: register_type = `REG_RW;
`OUTPUT_CTRL: register_type = `REG_RW;
`MODE_CTRL: register_type = `REG_RW;
`SPRITE_Z: register_type = `REG_RW;
`SCROLL_X: register_type = `REG_RW;
`SCROLL_Y: register_type = `REG_RW;
default: register_type = `REG_RO;
endcase
end
endfunction | 0 |
142,131 | data/full_repos/permissive/9705033/common/registers.v | 9,705,033 | registers.v | v | 160 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/9705033/common/registers.v:24: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/registers.v:25: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: Define or directive not defined: \'`REG_RW\'\n parameter TYPE=`REG_RW; \n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:30: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n parameter TYPE=`REG_RW; \n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: Define or directive not defined: \'`REG_RW\'\n if (TYPE == `REG_RW) begin\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:46: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (TYPE == `REG_RW) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:74: syntax error, unexpected input\n input clk; \n ^~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`ID\'\n `ID: register_type = `REG_RO;\n ^~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: syntax error, unexpected \':\', expecting endcase\n `ID: register_type = `REG_RO;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:94: Define or directive not defined: \'`REG_RO\'\n `ID: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`OUTPUT_STATUS\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:95: Define or directive not defined: \'`REG_RO\'\n `OUTPUT_STATUS: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`SCAN_X\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:96: Define or directive not defined: \'`REG_RO\'\n `SCAN_X: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`SCAN_Y\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:97: Define or directive not defined: \'`REG_RO\'\n `SCAN_Y: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`SYS_CTRL\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:99: Define or directive not defined: \'`REG_RW\'\n `SYS_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`MEM_BANK\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:100: Define or directive not defined: \'`REG_RW\'\n `MEM_BANK: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`OUTPUT_CTRL\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:101: Define or directive not defined: \'`REG_RW\'\n `OUTPUT_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`MODE_CTRL\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:102: Define or directive not defined: \'`REG_RW\'\n `MODE_CTRL: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`SPRITE_Z\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:104: Define or directive not defined: \'`REG_RW\'\n `SPRITE_Z: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`SCROLL_X\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:106: Define or directive not defined: \'`REG_RW\'\n `SCROLL_X: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`SCROLL_Y\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:107: Define or directive not defined: \'`REG_RW\'\n `SCROLL_Y: register_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:109: Define or directive not defined: \'`REG_RO\'\n default: register_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`TILE_CTRL0\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: syntax error, unexpected \':\', expecting endcase\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:119: Define or directive not defined: \'`REG_RW\'\n `TILE_CTRL0: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`TILE_DATA_OFFSET\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:120: Define or directive not defined: \'`REG_RW\'\n `TILE_DATA_OFFSET: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`TILE_NOP_VALUE\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:122: Define or directive not defined: \'`REG_RW\'\n `TILE_NOP_VALUE: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`TILE_COLOR_KEY\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:124: Define or directive not defined: \'`REG_RW\'\n `TILE_COLOR_KEY: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`TILE_OFFSET_X\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:126: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_X: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`TILE_OFFSET_Y\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:127: Define or directive not defined: \'`REG_RW\'\n `TILE_OFFSET_Y: tile_reg_type = `REG_RW;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:129: Define or directive not defined: \'`REG_RO\'\n default: tile_reg_type = `REG_RO;\n ^~~~~~~\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:139: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < NUM_REGS; i = i + 1) begin: REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/registers.v:152: syntax error, unexpected endgenerate\n endgenerate\n ^~~~~~~~~~~\n%Error: Cannot continue\n' | 313,067 | function | function integer tile_reg_type;
input [31:0] address;
begin
case (address)
`TILE_CTRL0: tile_reg_type = `REG_RW;
`TILE_DATA_OFFSET: tile_reg_type = `REG_RW;
`TILE_NOP_VALUE: tile_reg_type = `REG_RW;
`TILE_COLOR_KEY: tile_reg_type = `REG_RW;
`TILE_OFFSET_X: tile_reg_type = `REG_RW;
`TILE_OFFSET_Y: tile_reg_type = `REG_RW;
default: tile_reg_type = `REG_RO;
endcase
end
endfunction | function integer tile_reg_type; |
input [31:0] address;
begin
case (address)
`TILE_CTRL0: tile_reg_type = `REG_RW;
`TILE_DATA_OFFSET: tile_reg_type = `REG_RW;
`TILE_NOP_VALUE: tile_reg_type = `REG_RW;
`TILE_COLOR_KEY: tile_reg_type = `REG_RW;
`TILE_OFFSET_X: tile_reg_type = `REG_RW;
`TILE_OFFSET_Y: tile_reg_type = `REG_RW;
default: tile_reg_type = `REG_RO;
endcase
end
endfunction | 0 |
142,132 | data/full_repos/permissive/9705033/common/registers_test.v | 9,705,033 | registers_test.v | v | 168 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | line:71: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:67: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:70: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1 read_test();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:73: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:76: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 2;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(0, \'hdead);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(2, \'hbeef);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:79: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(4, \'hcafe);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:80: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(8, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:81: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(16, \'hbead);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(18, \'hfade);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(24, \'hdeaf);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:84: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(26, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:85: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(28, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #1 write16(30, \'hface);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:88: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 3;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:92: Unsupported: Ignoring delay on this delayed statement.\n #1 read_test();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:94: Unsupported: Ignoring delay on this delayed statement.\n #1 addr = \'bx;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:97: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 4;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:100: Unsupported: Ignoring delay on this delayed statement.\n #1 write8(i * 2, \'h0000);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:101: Unsupported: Ignoring delay on this delayed statement.\n #1 write8(i * 2 + 1, \'hffff);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:105: Unsupported: Ignoring delay on this delayed statement.\n #5 stage = 5;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:106: Unsupported: Ignoring delay on this delayed statement.\n #1 read_test();\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:117: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1; rd = 0; wr = 1; byte_lo = 1; byte_hi = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:118: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1; rd = 0; wr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:119: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:130: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1; rd = 0; wr = 1; byte_lo = ~addr_arg[0]; byte_hi = addr_arg[0];\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:131: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1; rd = 0; wr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:132: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:142: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1; rd = 1; wr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:143: Unsupported: Ignoring delay on this delayed statement.\n #3 en = 1; rd = 0; wr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:144: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 0; rd = 0; wr = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:152: Unsupported: Ignoring delay on this delayed statement.\n #5 read(0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:153: Unsupported: Ignoring delay on this delayed statement.\n #1 read(2);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:154: Unsupported: Ignoring delay on this delayed statement.\n #1 read(4);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:155: Unsupported: Ignoring delay on this delayed statement.\n #1 read(8);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:156: Unsupported: Ignoring delay on this delayed statement.\n #1 read(16);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:157: Unsupported: Ignoring delay on this delayed statement.\n #1 read(17);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:158: Unsupported: Ignoring delay on this delayed statement.\n #1 read(18);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:159: Unsupported: Ignoring delay on this delayed statement.\n #1 read(19);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:160: Unsupported: Ignoring delay on this delayed statement.\n #1 read(24);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:161: Unsupported: Ignoring delay on this delayed statement.\n #1 read(25);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:162: Unsupported: Ignoring delay on this delayed statement.\n #1 read(26);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/registers_test.v:163: Unsupported: Ignoring delay on this delayed statement.\n #1 read(27);\n ^\n%Error: data/full_repos/permissive/9705033/common/registers_test.v:39: Cannot find file containing module: \'Registers\'\n Registers #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))\n ^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Registers\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Registers.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Registers.sv\n Registers\n Registers.v\n Registers.sv\n obj_dir/Registers\n obj_dir/Registers.v\n obj_dir/Registers.sv\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:141: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\' generates 32 bits.\n : ... In instance Registers_Test\n data_in = \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:73: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance Registers_Test\n #1 addr = \'bx;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:88: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance Registers_Test\n #1 addr = \'bx;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:94: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\' generates 32 bits.\n : ... In instance Registers_Test\n #1 addr = \'bx;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:100: Operator TASKREF \'write8\' expects 8 bits on the Function Argument, but Function Argument\'s MULS generates 32 bits.\n : ... In instance Registers_Test\n #1 write8(i * 2, \'h0000);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:101: Operator TASKREF \'write8\' expects 8 bits on the Function Argument, but Function Argument\'s ADD generates 32 bits.\n : ... In instance Registers_Test\n #1 write8(i * 2 + 1, \'hffff);\n ^~~~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/registers_test.v:101: Operator TASKREF \'write8\' expects 8 bits on the Function Argument, but Function Argument\'s CONST \'?32?hffff\' generates 32 or 16 bits.\n : ... In instance Registers_Test\n #1 write8(i * 2 + 1, \'hffff);\n ^~~~~~\n%Error: Exiting due to 1 error(s), 54 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,069 | module | module Registers_Test;
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=16;
reg clk;
reg reset;
reg en;
reg rd;
reg wr;
reg byte_lo;
reg byte_hi;
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
Registers #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
registers(.reset(reset),
.en(en),
.rd(rd),
.wr(wr),
.be({byte_hi, byte_lo}),
.addr(addr),
.data_in(data_in),
.data_out(data_out));
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
rd = 0;
wr = 0;
#5 reset = 1;
#1 reset = 0;
#5 stage = 1;
#1 read_test();
#1 addr = 'bx;
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
#5 stage = 4;
for (i = 0; i < 15; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
#5 stage = 5;
#1 read_test();
end
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = data_arg;
#1 en = 1; rd = 0; wr = 1; byte_lo = 1; byte_hi = 1;
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH/2-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = {data_arg, data_arg};
#1 en = 1; rd = 0; wr = 1; byte_lo = ~addr_arg[0]; byte_hi = addr_arg[0];
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
task read;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg >> 1;
data_in = 'bz;
#1 en = 1; rd = 1; wr = 0;
#3 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0;
end
endtask
task read_test;
begin
#5 read(0);
#1 read(2);
#1 read(4);
#1 read(8);
#1 read(16);
#1 read(17);
#1 read(18);
#1 read(19);
#1 read(24);
#1 read(25);
#1 read(26);
#1 read(27);
end
endtask
endmodule | module Registers_Test; |
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=16;
reg clk;
reg reset;
reg en;
reg rd;
reg wr;
reg byte_lo;
reg byte_hi;
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
Registers #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
registers(.reset(reset),
.en(en),
.rd(rd),
.wr(wr),
.be({byte_hi, byte_lo}),
.addr(addr),
.data_in(data_in),
.data_out(data_out));
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
rd = 0;
wr = 0;
#5 reset = 1;
#1 reset = 0;
#5 stage = 1;
#1 read_test();
#1 addr = 'bx;
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
#5 stage = 4;
for (i = 0; i < 15; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
#5 stage = 5;
#1 read_test();
end
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = data_arg;
#1 en = 1; rd = 0; wr = 1; byte_lo = 1; byte_hi = 1;
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH/2-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = {data_arg, data_arg};
#1 en = 1; rd = 0; wr = 1; byte_lo = ~addr_arg[0]; byte_hi = addr_arg[0];
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
task read;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg >> 1;
data_in = 'bz;
#1 en = 1; rd = 1; wr = 0;
#3 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0;
end
endtask
task read_test;
begin
#5 read(0);
#1 read(2);
#1 read(4);
#1 read(8);
#1 read(16);
#1 read(17);
#1 read(18);
#1 read(19);
#1 read(24);
#1 read(25);
#1 read(26);
#1 read(27);
end
endtask
endmodule | 0 |
142,133 | data/full_repos/permissive/9705033/common/register_test.v | 9,705,033 | register_test.v | v | 79 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(21, 78)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:43: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:55: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:57: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hdead;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hbeef;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:60: Unsupported: Ignoring delay on this delayed statement.\n #1 en = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:62: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hdead;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hbeef;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n #1 byte_lo = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:68: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hface;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hcafe;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:71: Unsupported: Ignoring delay on this delayed statement.\n #1 byte_lo = 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:74: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hf00d;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/register_test.v:75: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = \'hbead;\n ^\n%Warning-IMPLICIT: data/full_repos/permissive/9705033/common/register_test.v:33: Signal definition not found, creating implicitly: \'data\'\n : ... Suggested alternative: \'data_in\'\n assign data = data_in;\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/register_test.v:33: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s VARREF \'data_in\' generates 16 bits.\n : ... In instance Register_Test\n assign data = data_in;\n ^\n%Error: data/full_repos/permissive/9705033/common/register_test.v:34: Cannot find file containing module: \'Register\'\n Register register(.reset(reset),\n ^~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Register\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Register.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/Register.sv\n Register\n Register.v\n Register.sv\n obj_dir/Register\n obj_dir/Register.v\n obj_dir/Register.sv\n%Error: Exiting due to 1 error(s), 16 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,070 | module | module Register_Test;
reg clk;
reg reset;
reg en;
reg byte_lo;
reg byte_hi;
reg [15:0] data_in;
wire [15:0] data_out;
assign data = data_in;
Register register(.reset(reset),
.clk(clk),
.en(en),
.be({byte_hi, byte_lo}),
.d(data_in),
.q(data_out));
always
#1 clk = ~clk;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
#5 reset = 1;
#1 reset = 0;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 en = 1;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 byte_lo = 1;
byte_hi = 0;
#4 data_in = 'hface;
#4 data_in = 'hcafe;
#1 byte_lo = 0;
byte_hi = 1;
#4 data_in = 'hf00d;
#4 data_in = 'hbead;
end
endmodule | module Register_Test; |
reg clk;
reg reset;
reg en;
reg byte_lo;
reg byte_hi;
reg [15:0] data_in;
wire [15:0] data_out;
assign data = data_in;
Register register(.reset(reset),
.clk(clk),
.en(en),
.be({byte_hi, byte_lo}),
.d(data_in),
.q(data_out));
always
#1 clk = ~clk;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
#5 reset = 1;
#1 reset = 0;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 en = 1;
#4 data_in = 'hdead;
#4 data_in = 'hbeef;
#1 byte_lo = 1;
byte_hi = 0;
#4 data_in = 'hface;
#4 data_in = 'hcafe;
#1 byte_lo = 0;
byte_hi = 1;
#4 data_in = 'hf00d;
#4 data_in = 'hbead;
end
endmodule | 0 |
142,134 | data/full_repos/permissive/9705033/common/renderer.v | 9,705,033 | renderer.v | v | 778 | 83 | [] | ['general public license', 'free software foundation'] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/9705033/common/renderer.v:20: Cannot find include file: collision.vh\n`include "collision.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/collision.vh.sv\n collision.vh\n collision.vh.v\n collision.vh.sv\n obj_dir/collision.vh\n obj_dir/collision.vh.v\n obj_dir/collision.vh.sv\n%Error: data/full_repos/permissive/9705033/common/renderer.v:21: Cannot find include file: memory_map.vh\n`include "memory_map.vh" \n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:22: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:23: Cannot find include file: sprite_registers.vh\n`include "sprite_registers.vh" \n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:24: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:65: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:65: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:65: Define or directive not defined: \'`NUM_MAIN_REGS\'\n input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:66: Define or directive not defined: \'`NUM_TOTAL_TILE_REG_BITS\'\n input [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:101: Define or directive not defined: \'`PAL_ADDR_WIDTH\'\n output [`PAL_ADDR_WIDTH-1:0] pal_addr;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:102: Define or directive not defined: \'`PAL_DATA_WIDTH\'\n input [`PAL_DATA_WIDTH-1:0] pal_data;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:106: Define or directive not defined: \'`TILEMAP_ADDR_WIDTH\'\n : ... Suggested alternative: \'`LINE_BUF_ADDR_WIDTH\'\n output [`TILEMAP_ADDR_WIDTH-1:0] map_addr;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:107: Define or directive not defined: \'`TILEMAP_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n input [`TILEMAP_DATA_WIDTH-1:0] map_data;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:111: Define or directive not defined: \'`SPRITE_ADDR_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n output [`SPRITE_ADDR_WIDTH-1:0] spr_addr;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:112: Define or directive not defined: \'`SPRITE_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n input [`SPRITE_DATA_WIDTH-1:0] spr_data;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:116: Define or directive not defined: \'`COLL_ADDR_WIDTH\'\n : ... Suggested alternative: \'`WORLD_WIDTH\'\n output [`COLL_ADDR_WIDTH-1:0] coll_addr;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:117: Define or directive not defined: \'`COLL_DATA_WIDTH\'\n : ... Suggested alternative: \'`WORLD_WIDTH\'\n output [`COLL_DATA_WIDTH-1:0] coll_data;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:126: Define or directive not defined: \'`VRAM_ADDR_WIDTH\'\n output [`VRAM_ADDR_WIDTH-1:0] vram_addr; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:127: Define or directive not defined: \'`VRAM_DATA_WIDTH\'\n input [`VRAM_DATA_WIDTH-1:0] vram_data; \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:137: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] reg_array [`NUM_MAIN_REGS-1:0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:137: Define or directive not defined: \'`NUM_MAIN_REGS\'\n wire [`REG_DATA_WIDTH-1:0] reg_array [`NUM_MAIN_REGS-1:0];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:140: Define or directive not defined: \'`NUM_MAIN_REGS\'\n for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : REGS\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:140: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:141: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n assign reg_array[i] = reg_values[`REG_DATA_WIDTH * (i + 1) - 1:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:142: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n `REG_DATA_WIDTH * i];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:147: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_ctrl0;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:148: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_ctrl1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:149: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_nop_value;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:150: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_color_key;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:151: Define or directive not defined: \'`VRAM_DATA_WIDTH\'\n wire [`VRAM_DATA_WIDTH:0] tile_data_offset;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:151: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`VRAM_DATA_WIDTH:0] tile_data_offset;\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:152: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_offset_x;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:153: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] tile_offset_y;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:171: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:172: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] sprite_ctrl1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:173: Define or directive not defined: \'`VRAM_ADDR_WIDTH\'\n wire [`VRAM_ADDR_WIDTH:0] sprite_data_offset;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:173: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [`VRAM_ADDR_WIDTH:0] sprite_data_offset;\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:174: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] sprite_color_key;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:175: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] sprite_offset_x;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:176: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] sprite_offset_y;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:223: Define or directive not defined: \'`SCROLL_X\'\n sprite_enable_scroll ? sprite_offset_x - reg_array[`SCROLL_X]\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:223: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n sprite_enable_scroll ? sprite_offset_x - reg_array[`SCROLL_X]\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:226: Define or directive not defined: \'`SCROLL_Y\'\n sprite_enable_scroll ? sprite_offset_y - reg_array[`SCROLL_Y]\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:226: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n sprite_enable_scroll ? sprite_offset_y - reg_array[`SCROLL_Y]\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:242: Define or directive not defined: \'`SCROLL_Y\'\n wire [SCREEN_Y_WIDTH-2:0] world_y = screen_y + reg_array[`SCROLL_Y];\n ^~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:242: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n wire [SCREEN_Y_WIDTH-2:0] world_y = screen_y + reg_array[`SCROLL_Y];\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:267: Define or directive not defined: \'`NUM_SPRITE_REGS\'\n reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:267: syntax error, unexpected \'*\', expecting TYPE-IDENTIFIER\n reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer.v:267: Define or directive not defined: \'`REG_DATA_WIDTH\'\n : ... Suggested alternative: \'`SPRITE_BUF_DATA_WIDTH\'\n reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer.v:296: Define or directive not defined: \'`SPRITE_Z\'\n if (num_layers_drawn < reg_array[`SPRITE_Z] ||\n ^~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,071 | module | module Renderer(clk, reset, reg_values, tile_reg_values,
h_pos, v_pos, h_sync, v_sync,
pal_clk, pal_addr, pal_data,
map_clk, map_addr, map_data,
spr_clk, spr_addr, spr_data,
vram_en, vram_rd, vram_wr, vram_be,
vram_clk, vram_addr, vram_data,
coll_wr, coll_addr, coll_data,
rgb_out);
parameter RGB_COLOR_DEPTH=18;
localparam SCREEN_X_WIDTH=10;
localparam SCREEN_Y_WIDTH=10;
input clk;
input reset;
input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;
input [SCREEN_X_WIDTH-1:0] h_pos;
input [SCREEN_Y_WIDTH-1:0] v_pos;
output h_sync, v_sync;
wire h_blank, v_blank;
wire h_sync_in, v_sync_in;
wire [SCREEN_X_WIDTH-1:0] h_visible;
wire [SCREEN_X_WIDTH-1:0] v_visible;
DisplayTiming timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(h_sync_in), .v_sync(v_sync_in),
.h_blank(h_blank), .v_blank(v_blank),
.h_visible_pos(h_visible), .v_visible_pos(v_visible));
wire h_blank_delayed;
wire v_blank_delayed;
DisplayTiming v_delay(.h_pos(h_pos),
.v_pos(v_pos - 2),
.v_sync(v_sync),
.v_blank(v_blank_delayed));
CC_Delay #(.WIDTH(2), .DELAY(2)) h_delay(.clk(clk),
.reset(reset),
.d({h_sync_in, h_blank}),
.q({h_sync, h_blank_delayed}));
output pal_clk;
output [`PAL_ADDR_WIDTH-1:0] pal_addr;
input [`PAL_DATA_WIDTH-1:0] pal_data;
output map_clk;
output [`TILEMAP_ADDR_WIDTH-1:0] map_addr;
input [`TILEMAP_DATA_WIDTH-1:0] map_data;
output spr_clk;
output [`SPRITE_ADDR_WIDTH-1:0] spr_addr;
input [`SPRITE_DATA_WIDTH-1:0] spr_data;
output coll_wr;
output [`COLL_ADDR_WIDTH-1:0] coll_addr;
output [`COLL_DATA_WIDTH-1:0] coll_data;
output wire vram_en;
output wire vram_rd;
output wire vram_wr;
output wire [1:0] vram_be;
output vram_clk;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
input [`VRAM_DATA_WIDTH-1:0] vram_data;
output [RGB_COLOR_DEPTH-1:0] rgb_out;
assign vram_wr = 1'b0;
assign vram_rd = 1'b1;
assign vram_en = 1'b1;
assign vram_be = 2'b11;
wire [`REG_DATA_WIDTH-1:0] reg_array [`NUM_MAIN_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : REGS
assign reg_array[i] = reg_values[`REG_DATA_WIDTH * (i + 1) - 1:
`REG_DATA_WIDTH * i];
end
endgenerate
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl1;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value;
wire [`REG_DATA_WIDTH-1:0] tile_color_key;
wire [`VRAM_DATA_WIDTH:0] tile_data_offset;
wire [`REG_DATA_WIDTH-1:0] tile_offset_x;
wire [`REG_DATA_WIDTH-1:0] tile_offset_y;
wire tile_enable_flip;
wire tile_enable_8_bit;
TileRegDecoder tile_reg_decoder(
.current_layer(current_tile_layer),
.reg_values(tile_reg_values),
.ctrl0(tile_ctrl0),
.enable_8bit(tile_enable_8_bit),
.enable_flip(tile_enable_flip),
.ctrl1(tile_ctrl1),
.data_offset(tile_data_offset),
.nop_value(tile_nop_value),
.color_key(tile_color_key),
.offset_x(tile_offset_x),
.offset_y(tile_offset_y));
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0;
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl1;
wire [`VRAM_ADDR_WIDTH:0] sprite_data_offset;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_x;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_y;
wire sprite_enabled;
wire sprite_enable_scroll;
wire sprite_enable_transp;
wire sprite_enable_alpha;
wire sprite_enable_color;
wire sprite_flip_x;
wire sprite_flip_y;
wire sprite_flip_xy;
wire [8:0] sprite_pal_index;
wire [8:0] sprite_width;
wire [8:0] sprite_height;
SpriteRegDecoder sprite_reg_decoder(
.reg_values(sprite_reg_values),
.enabled(sprite_enabled),
.enable_scroll(sprite_enable_scroll),
.enable_transp(sprite_enable_transp),
.enable_alpha(sprite_enable_alpha),
.enable_color(sprite_enable_color),
.flip_x(sprite_flip_x),
.flip_y(sprite_flip_y),
.flip_xy(sprite_flip_xy),
.palette(sprite_pal_index),
.width(sprite_width),
.height(sprite_height),
.ctrl0(sprite_ctrl0),
.ctrl1(sprite_ctrl1),
.data_offset(sprite_data_offset),
.color_key(sprite_color_key),
.offset_x(sprite_offset_x),
.offset_y(sprite_offset_y));
wire [8:0] sprite_render_width = sprite_flip_xy ? sprite_height
: sprite_width;
wire [8:0] sprite_render_height = sprite_flip_xy ? sprite_width
: sprite_height;
wire [SCREEN_X_WIDTH-1:0] sprite_screen_offset_x =
sprite_enable_scroll ? sprite_offset_x - reg_array[`SCROLL_X]
: sprite_offset_x;
wire [SCREEN_Y_WIDTH-1:0] sprite_screen_offset_y =
sprite_enable_scroll ? sprite_offset_y - reg_array[`SCROLL_Y]
: sprite_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_top = sprite_screen_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_bottom =
sprite_screen_offset_y + sprite_render_height;
wire [SCREEN_X_WIDTH-2:0] screen_x = h_visible / 2;
wire [SCREEN_Y_WIDTH-2:0] screen_y = v_visible / 2;
wire [SCREEN_Y_WIDTH-2:0] world_y = screen_y + reg_array[`SCROLL_Y];
assign pal_clk = clk;
assign map_clk = clk;
assign vram_clk = clk;
assign spr_clk = ~clk;
`define STATE_IDLE 0
`define STATE_DECIDE 1
`define STATE_DRAW_LAYER 2
`define STATE_READ_SPRITE 3
`define STATE_DRAW_SPRITE 4
reg [3:0] render_state;
reg [`LINE_BUF_ADDR_WIDTH-2:0] render_x;
reg [4:0] num_layers_drawn;
reg [8:0] num_sprites_drawn;
reg [15:0] num_texels_drawn;
reg [8:0] num_sprite_words_read;
wire [4:0] current_tile_layer = num_layers_drawn;
wire [`BYTE_WIDTH-1:0] current_sprite = num_sprites_drawn[`BYTE_WIDTH-1:0];
assign spr_addr = {current_sprite, num_sprite_words_read[0]};
reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;
always @ (posedge clk or posedge reset) begin
if (reset) begin
render_state <= `STATE_IDLE;
sprite_reg_values <= 0;
end else begin
case (render_state)
`STATE_IDLE:
begin
if (h_pos == 0 && v_blank == 0 && v_visible[0] == 0) begin
render_state <= `STATE_DECIDE;
num_layers_drawn <= 0;
num_sprites_drawn <= 0;
num_texels_drawn <= 0;
num_sprite_words_read <= 0;
end
end
`STATE_DECIDE:
begin
if (num_layers_drawn < reg_array[`SPRITE_Z] ||
(num_layers_drawn < `NUM_TILE_LAYERS && num_sprites_drawn > 0))
begin
if (tile_ctrl0[`TILE_LAYER_ENABLED]) begin
render_state <= `STATE_DRAW_LAYER;
render_x <= 0;
end
else
num_layers_drawn <= num_layers_drawn + 1;
end
else if ((num_layers_drawn == reg_array[`SPRITE_Z] ||
num_layers_drawn == `NUM_TILE_LAYERS) &&
num_sprites_drawn < `NUM_SPRITES)
begin
render_state <= `STATE_READ_SPRITE;
num_sprite_words_read <= 0;
end
else
render_state <= `STATE_IDLE;
end
`STATE_DRAW_LAYER:
begin
if (h_pos + 1 == 800 && v_visible[0] == 1) begin
render_state <= `STATE_IDLE;
end else if (render_x + 1 >= `SCREEN_IMAGE_WIDTH) begin
render_state <= `STATE_DECIDE;
num_layers_drawn <= num_layers_drawn + 1;
end else begin
render_x <= render_x + 1;
end
end
`STATE_READ_SPRITE:
begin
if (num_sprites_drawn >= `NUM_SPRITES) begin
render_state <= `STATE_DECIDE;
end else if (num_sprite_words_read < 2) begin
if (num_sprite_words_read == 0)
sprite_reg_values[`SPRITE_DATA_WIDTH-1:0] <= spr_data;
else if (num_sprite_words_read == 1)
sprite_reg_values[`SPRITE_DATA_WIDTH*2-1:`SPRITE_DATA_WIDTH] <=
spr_data;
num_sprite_words_read <= num_sprite_words_read + 1;
end else begin
if (!sprite_enabled ||
(sprite_top <= sprite_bottom &&
(screen_y < sprite_top || screen_y >= sprite_bottom)) ||
(sprite_top >= sprite_bottom &&
(screen_y >= sprite_bottom && screen_y < sprite_top))
) begin
num_sprite_words_read <= 0;
num_sprites_drawn <= num_sprites_drawn + 1;
end else begin
render_state <= `STATE_DRAW_SPRITE;
render_x <= 0;
end
end
end
`STATE_DRAW_SPRITE:
begin
if (render_x + 1 >= sprite_render_width) begin
render_state <= `STATE_READ_SPRITE;
num_sprites_drawn <= num_sprites_drawn + 1;
num_sprite_words_read <= 0;
end else begin
render_x <= render_x + 1;
end
end
endcase
end
end
wire render_tiles = (render_state == `STATE_DRAW_LAYER);
wire render_sprite = (render_state == `STATE_DRAW_SPRITE);
reg render_tiles_delayed;
reg render_sprite_delayed;
always @ (posedge clk) begin
render_tiles_delayed <= render_tiles;
render_sprite_delayed <= render_sprite;
end
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_x = render_x;
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_y =
screen_y + reg_array[`SCROLL_Y] - tile_offset_y;
wire [`LINE_BUF_ADDR_WIDTH-2:0] sprite_render_x =
(render_x + sprite_screen_offset_x) % `WORLD_WIDTH;
reg [15:0] sprite_x;
reg [15:0] sprite_y;
wire [15:0] sprite_render_y =
(screen_y - sprite_screen_offset_y) % `WORLD_HEIGHT;
wire [15:0] sprite_flipped_x = sprite_render_width - render_x - 1;
wire [15:0] sprite_flipped_y = sprite_render_height - sprite_render_y - 1;
reg [`VRAM_ADDR_WIDTH-1:0] sprite_vram_offset;
always @ (posedge clk) begin
if (~sprite_flip_xy) begin
sprite_x <= sprite_flip_x ? sprite_flipped_x : render_x;
sprite_y <= sprite_flip_y ? sprite_flipped_y : sprite_render_y;
end else begin
sprite_x <= sprite_flip_x ? sprite_flipped_y : sprite_render_y;
sprite_y <= sprite_flip_y ? sprite_flipped_x : render_x;
end
sprite_vram_offset <= sprite_data_offset / 2;
end
wire [15:0] sprite_pixel_offset = sprite_y * sprite_width + sprite_x;
wire [`LINE_BUF_ADDR_WIDTH-2:0] render_x_world =
tile_render_x + reg_array[`SCROLL_X] - tile_offset_x;
wire tile_enable_8x8 = tile_ctrl0[`TILE_ENABLE_8x8];
reg [4:0] map_x;
reg [5:0] map_y;
reg [3:0] tile_x;
reg [3:0] tile_y;
always @ (*) begin
if (tile_enable_8x8) begin
if (tile_enable_8_bit) begin
map_x <= render_x_world[7:3];
map_y <= {tile_render_y[8:3], render_x_world[8]};
end else begin
map_x <= render_x_world[8:3];
map_y <= tile_render_y[8:3];
end
tile_x <= render_x_world[2:0];
tile_y <= tile_render_y[2:0];
end else begin
map_x <= render_x_world[8:4];
map_y <= tile_render_y[8:4];
tile_x <= render_x_world[3:0];
tile_y <= tile_render_y[3:0];
end
end
assign map_addr =
tile_enable_8_bit ? {current_tile_layer, map_y[5:0], map_x[4:1]}
: {current_tile_layer, map_y[4:0], map_x[4:0]};
reg map_data_byte_select;
always @ (posedge clk)
map_data_byte_select <= map_x[0];
wire tile_flip_x = tile_enable_flip & map_data[`TILE_FLIP_X_BIT];
wire tile_flip_y = tile_enable_flip & map_data[`TILE_FLIP_Y_BIT];
wire tile_flip_xy = tile_enable_flip & map_data[`TILE_FLIP_XY_BIT];
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value =
tile_enable_8_bit
? (map_data_byte_select
? map_data[`TILEMAP_DATA_WIDTH-1:`TILEMAP_DATA_WIDTH/2]
: map_data[`TILEMAP_DATA_WIDTH/2-1:0])
: (tile_enable_flip ? (~`TILE_FLIP_BITS_MASK & map_data)
: map_data);
reg [3:0] tile_x_reg;
reg [3:0] tile_y_reg;
always @ (posedge clk) begin
tile_x_reg <= tile_x;
tile_y_reg <= tile_y;
end
reg [3:0] tile_x_flipped;
reg [3:0] tile_y_flipped;
always @ (*)
begin
if (tile_flip_xy) begin
tile_x_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
tile_y_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
end else begin
tile_x_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
tile_y_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
end
end
reg [`VRAM_ADDR_WIDTH-1:0] tile_vram_offset;
always @ (posedge clk)
tile_vram_offset <= tile_data_offset / 2;
wire [`VRAM_ADDR_WIDTH-1:0] tile_vram_addr =
tile_enable_8x8 ? {tile_value, tile_y_flipped[2:0], tile_x_flipped[2:1]}
: {tile_value, tile_y_flipped[3:0], tile_x_flipped[3:1]} +
tile_vram_offset;
wire [`VRAM_ADDR_WIDTH-1:0] sprite_vram_addr =
sprite_pixel_offset[15:1] + sprite_vram_offset;
assign vram_addr = render_tiles_delayed ? tile_vram_addr : sprite_vram_addr;
wire vram_byte_select;
CC_Delay #(.WIDTH(1), .DELAY(2))
vram_byte_select_delay(
.clk(clk),
.reset(reset),
.d(render_tiles_delayed ? tile_x_flipped[0] : sprite_pixel_offset[0]),
.q(vram_byte_select));
`define RENDER_DELAY 5
wire [`TILE_PALETTE_WIDTH-1:0] tile_pal_index =
tile_ctrl0[`TILE_PALETTE_END:`TILE_PALETTE_START];
wire [`TILE_PALETTE_WIDTH-1:0] pal_index_delayed;
CC_Delay #(.WIDTH(`TILE_PALETTE_WIDTH), .DELAY(`RENDER_DELAY-2))
pal_index_delay(.clk(clk),
.reset(reset),
.d(render_tiles ? tile_pal_index : sprite_pal_index),
.q(pal_index_delayed));
assign pal_addr =
{ pal_index_delayed,
(vram_byte_select == 0) ? vram_data[7:0] : vram_data[15:8] };
reg [RGB_COLOR_DEPTH-1:0] rgb_out;
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr;
CC_Delay #(.WIDTH(`LINE_BUF_ADDR_WIDTH), .DELAY(`RENDER_DELAY))
buf_addr_delay(
.clk(clk),
.reset(reset),
.d({screen_y[0],
render_tiles_delayed ? tile_render_x : sprite_render_x}),
.q(buf_addr));
wire [3:0] render_state_delayed;
CC_Delay #(.WIDTH(3), .DELAY(`RENDER_DELAY))
render_state_delay(.clk(clk),
.reset(reset),
.d(render_state),
.q(render_state_delayed));
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key_delayed;
wire [`BYTE_WIDTH-1:0] current_sprite_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_ctrl0_delay(.clk(clk),
.reset(reset),
.d(sprite_ctrl0),
.q(sprite_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_color_key_delay(.clk(clk),
.reset(reset),
.d(sprite_color_key),
.q(sprite_color_key_delayed));
CC_Delay #(.WIDTH(`BYTE_WIDTH), .DELAY(`RENDER_DELAY))
current_sprite_delay(.clk(clk),
.reset(reset),
.d(current_sprite),
.q(current_sprite_delayed));
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_color_key_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_enable_nop_delay(.clk(clk),
.reset(reset),
.d(tile_ctrl0),
.q(tile_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_nop_value_delay(.clk(clk),
.reset(reset),
.d(tile_nop_value[`TILEMAP_DATA_WIDTH-1:0]),
.q(tile_nop_value_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_color_key_delay(.clk(clk),
.reset(reset),
.d(tile_color_key),
.q(tile_color_key_delayed));
CC_Delay #(.WIDTH(`TILEMAP_DATA_WIDTH), .DELAY(`RENDER_DELAY-1))
tile_value_delay(.clk(clk),
.reset(reset),
.d(map_data),
.q(tile_value_delayed));
wire [7:0] pixel_value_delayed;
CC_Delay #(.WIDTH(8), .DELAY(2))
pixel_value_delay(.clk(clk),
.reset(reset),
.d(pal_addr[7:0]),
.q(pixel_value_delayed));
wire tile_buf_wr = (render_state_delayed == `STATE_DRAW_LAYER) &&
!(tile_value_delayed == tile_nop_value_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_NOP]) &&
!(pixel_value_delayed == tile_color_key_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_TRANSP]);
wire sprite_buf_wr = (render_state_delayed == `STATE_DRAW_SPRITE) &&
!(pixel_value_delayed == sprite_color_key_delayed &&
sprite_ctrl0_delayed[`SPRITE_ENABLE_TRANSP]);
Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) line_buffer(
.clk_a(clk),
.wr_a(tile_buf_wr | sprite_buf_wr),
.rd_a(0),
.addr_a(buf_addr),
.data_in_a(pal_data),
.byte_en_a(3'b111),
.clk_b(clk),
.wr_b(h_visible[0] & v_visible[0]),
.rd_b(~(h_blank | v_blank_delayed)),
.addr_b(buf_scanout_addr),
.data_in_b(0),
.data_out_b(buf_scanout_data)
);
wire [`SPRITE_BUF_DATA_WIDTH-1:0] sprite_buffer_out;
collision_buffer_1Kx9 sprite_buffer(
.clock(clk),
.wren_a(sprite_buf_wr),
.address_a(buf_addr),
.data_a({1'b1, current_sprite_delayed}),
.q_a({existing_sprite_pixel_valid, existing_sprite_index}),
.wren_b(h_visible[0] & v_visible[0]),
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(sprite_buffer_out),
);
reg sprite_buf_wr_delayed;
reg [`BYTE_WIDTH-1:0] new_sprite_index;
reg [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr_delayed;
always @ (posedge clk) begin
sprite_buf_wr_delayed <= sprite_buf_wr;
new_sprite_index <= current_sprite_delayed;
buf_addr_delayed <= buf_addr;
end
wire existing_sprite_pixel_valid;
wire [`BYTE_WIDTH-1:0] existing_sprite_index;
wire sprite_collision = sprite_buf_wr_delayed & existing_sprite_pixel_valid;
assign coll_wr = sprite_collision;
assign coll_addr = new_sprite_index;
assign coll_data = existing_sprite_index;
wire [`COLLISION_BUF_DATA_WIDTH-1:0] collision_buffer_out;
collision_buffer_1Kx9 collision_test_buffer(
.clock(clk),
.wren_a(sprite_collision),
.address_a(buf_addr_delayed),
.data_a({`COLLISION_BUF_DATA_WIDTH{1'b1}}),
.wren_b(h_visible[0] & v_visible[0]),
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(collision_buffer_out),
);
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_scanout_addr;
assign buf_scanout_addr = {~screen_y[0], screen_x};
wire [`PAL_DATA_WIDTH-1:0] buf_scanout_data;
reg [7:0] buf_scanout_red;
reg [7:0] buf_scanout_green;
reg [7:0] buf_scanout_blue;
always @ (negedge clk) begin
`ifndef TEST_COLLISION_BUFFER
buf_scanout_red = buf_scanout_data[7:0];
buf_scanout_green = buf_scanout_data[15:8];
buf_scanout_blue = buf_scanout_data[23:16];
`else
`ifndef TEST_COLLISION_REGIONS_ONLY
`define BUFFER_TEST_BIT sprite_buffer_out[`SPRITE_BUF_DATA_WIDTH-1]
`else
`define BUFFER_TEST_BIT collision_buffer_out[`COLL_DATA_WIDTH-1]
`endif
{buf_scanout_red, buf_scanout_green, buf_scanout_blue} =
`BUFFER_TEST_BIT ? 'h7f7f7f : {buf_scanout_data[7:0],
buf_scanout_data[15:8],
buf_scanout_data[23:16]};
`endif
end
always @ (negedge clk) begin
if (h_blank_delayed | v_blank_delayed) begin
rgb_out <= {RGB_COLOR_DEPTH {1'b0}};
end else if (~h_visible[0]) begin
rgb_out <= {buf_scanout_blue[7:2],
buf_scanout_green[7:2],
buf_scanout_red[7:2]};
end
end
endmodule | module Renderer(clk, reset, reg_values, tile_reg_values,
h_pos, v_pos, h_sync, v_sync,
pal_clk, pal_addr, pal_data,
map_clk, map_addr, map_data,
spr_clk, spr_addr, spr_data,
vram_en, vram_rd, vram_wr, vram_be,
vram_clk, vram_addr, vram_data,
coll_wr, coll_addr, coll_data,
rgb_out); |
parameter RGB_COLOR_DEPTH=18;
localparam SCREEN_X_WIDTH=10;
localparam SCREEN_Y_WIDTH=10;
input clk;
input reset;
input [`REG_DATA_WIDTH * `NUM_MAIN_REGS - 1 : 0] reg_values;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] tile_reg_values;
input [SCREEN_X_WIDTH-1:0] h_pos;
input [SCREEN_Y_WIDTH-1:0] v_pos;
output h_sync, v_sync;
wire h_blank, v_blank;
wire h_sync_in, v_sync_in;
wire [SCREEN_X_WIDTH-1:0] h_visible;
wire [SCREEN_X_WIDTH-1:0] v_visible;
DisplayTiming timing(.h_pos(h_pos), .v_pos(v_pos),
.h_sync(h_sync_in), .v_sync(v_sync_in),
.h_blank(h_blank), .v_blank(v_blank),
.h_visible_pos(h_visible), .v_visible_pos(v_visible));
wire h_blank_delayed;
wire v_blank_delayed;
DisplayTiming v_delay(.h_pos(h_pos),
.v_pos(v_pos - 2),
.v_sync(v_sync),
.v_blank(v_blank_delayed));
CC_Delay #(.WIDTH(2), .DELAY(2)) h_delay(.clk(clk),
.reset(reset),
.d({h_sync_in, h_blank}),
.q({h_sync, h_blank_delayed}));
output pal_clk;
output [`PAL_ADDR_WIDTH-1:0] pal_addr;
input [`PAL_DATA_WIDTH-1:0] pal_data;
output map_clk;
output [`TILEMAP_ADDR_WIDTH-1:0] map_addr;
input [`TILEMAP_DATA_WIDTH-1:0] map_data;
output spr_clk;
output [`SPRITE_ADDR_WIDTH-1:0] spr_addr;
input [`SPRITE_DATA_WIDTH-1:0] spr_data;
output coll_wr;
output [`COLL_ADDR_WIDTH-1:0] coll_addr;
output [`COLL_DATA_WIDTH-1:0] coll_data;
output wire vram_en;
output wire vram_rd;
output wire vram_wr;
output wire [1:0] vram_be;
output vram_clk;
output [`VRAM_ADDR_WIDTH-1:0] vram_addr;
input [`VRAM_DATA_WIDTH-1:0] vram_data;
output [RGB_COLOR_DEPTH-1:0] rgb_out;
assign vram_wr = 1'b0;
assign vram_rd = 1'b1;
assign vram_en = 1'b1;
assign vram_be = 2'b11;
wire [`REG_DATA_WIDTH-1:0] reg_array [`NUM_MAIN_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_MAIN_REGS; i = i + 1) begin : REGS
assign reg_array[i] = reg_values[`REG_DATA_WIDTH * (i + 1) - 1:
`REG_DATA_WIDTH * i];
end
endgenerate
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl1;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value;
wire [`REG_DATA_WIDTH-1:0] tile_color_key;
wire [`VRAM_DATA_WIDTH:0] tile_data_offset;
wire [`REG_DATA_WIDTH-1:0] tile_offset_x;
wire [`REG_DATA_WIDTH-1:0] tile_offset_y;
wire tile_enable_flip;
wire tile_enable_8_bit;
TileRegDecoder tile_reg_decoder(
.current_layer(current_tile_layer),
.reg_values(tile_reg_values),
.ctrl0(tile_ctrl0),
.enable_8bit(tile_enable_8_bit),
.enable_flip(tile_enable_flip),
.ctrl1(tile_ctrl1),
.data_offset(tile_data_offset),
.nop_value(tile_nop_value),
.color_key(tile_color_key),
.offset_x(tile_offset_x),
.offset_y(tile_offset_y));
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0;
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl1;
wire [`VRAM_ADDR_WIDTH:0] sprite_data_offset;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_x;
wire [`REG_DATA_WIDTH-1:0] sprite_offset_y;
wire sprite_enabled;
wire sprite_enable_scroll;
wire sprite_enable_transp;
wire sprite_enable_alpha;
wire sprite_enable_color;
wire sprite_flip_x;
wire sprite_flip_y;
wire sprite_flip_xy;
wire [8:0] sprite_pal_index;
wire [8:0] sprite_width;
wire [8:0] sprite_height;
SpriteRegDecoder sprite_reg_decoder(
.reg_values(sprite_reg_values),
.enabled(sprite_enabled),
.enable_scroll(sprite_enable_scroll),
.enable_transp(sprite_enable_transp),
.enable_alpha(sprite_enable_alpha),
.enable_color(sprite_enable_color),
.flip_x(sprite_flip_x),
.flip_y(sprite_flip_y),
.flip_xy(sprite_flip_xy),
.palette(sprite_pal_index),
.width(sprite_width),
.height(sprite_height),
.ctrl0(sprite_ctrl0),
.ctrl1(sprite_ctrl1),
.data_offset(sprite_data_offset),
.color_key(sprite_color_key),
.offset_x(sprite_offset_x),
.offset_y(sprite_offset_y));
wire [8:0] sprite_render_width = sprite_flip_xy ? sprite_height
: sprite_width;
wire [8:0] sprite_render_height = sprite_flip_xy ? sprite_width
: sprite_height;
wire [SCREEN_X_WIDTH-1:0] sprite_screen_offset_x =
sprite_enable_scroll ? sprite_offset_x - reg_array[`SCROLL_X]
: sprite_offset_x;
wire [SCREEN_Y_WIDTH-1:0] sprite_screen_offset_y =
sprite_enable_scroll ? sprite_offset_y - reg_array[`SCROLL_Y]
: sprite_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_top = sprite_screen_offset_y;
wire [SCREEN_Y_WIDTH-2:0] sprite_bottom =
sprite_screen_offset_y + sprite_render_height;
wire [SCREEN_X_WIDTH-2:0] screen_x = h_visible / 2;
wire [SCREEN_Y_WIDTH-2:0] screen_y = v_visible / 2;
wire [SCREEN_Y_WIDTH-2:0] world_y = screen_y + reg_array[`SCROLL_Y];
assign pal_clk = clk;
assign map_clk = clk;
assign vram_clk = clk;
assign spr_clk = ~clk;
`define STATE_IDLE 0
`define STATE_DECIDE 1
`define STATE_DRAW_LAYER 2
`define STATE_READ_SPRITE 3
`define STATE_DRAW_SPRITE 4
reg [3:0] render_state;
reg [`LINE_BUF_ADDR_WIDTH-2:0] render_x;
reg [4:0] num_layers_drawn;
reg [8:0] num_sprites_drawn;
reg [15:0] num_texels_drawn;
reg [8:0] num_sprite_words_read;
wire [4:0] current_tile_layer = num_layers_drawn;
wire [`BYTE_WIDTH-1:0] current_sprite = num_sprites_drawn[`BYTE_WIDTH-1:0];
assign spr_addr = {current_sprite, num_sprite_words_read[0]};
reg [`NUM_SPRITE_REGS * `REG_DATA_WIDTH - 1 : 0] sprite_reg_values;
always @ (posedge clk or posedge reset) begin
if (reset) begin
render_state <= `STATE_IDLE;
sprite_reg_values <= 0;
end else begin
case (render_state)
`STATE_IDLE:
begin
if (h_pos == 0 && v_blank == 0 && v_visible[0] == 0) begin
render_state <= `STATE_DECIDE;
num_layers_drawn <= 0;
num_sprites_drawn <= 0;
num_texels_drawn <= 0;
num_sprite_words_read <= 0;
end
end
`STATE_DECIDE:
begin
if (num_layers_drawn < reg_array[`SPRITE_Z] ||
(num_layers_drawn < `NUM_TILE_LAYERS && num_sprites_drawn > 0))
begin
if (tile_ctrl0[`TILE_LAYER_ENABLED]) begin
render_state <= `STATE_DRAW_LAYER;
render_x <= 0;
end
else
num_layers_drawn <= num_layers_drawn + 1;
end
else if ((num_layers_drawn == reg_array[`SPRITE_Z] ||
num_layers_drawn == `NUM_TILE_LAYERS) &&
num_sprites_drawn < `NUM_SPRITES)
begin
render_state <= `STATE_READ_SPRITE;
num_sprite_words_read <= 0;
end
else
render_state <= `STATE_IDLE;
end
`STATE_DRAW_LAYER:
begin
if (h_pos + 1 == 800 && v_visible[0] == 1) begin
render_state <= `STATE_IDLE;
end else if (render_x + 1 >= `SCREEN_IMAGE_WIDTH) begin
render_state <= `STATE_DECIDE;
num_layers_drawn <= num_layers_drawn + 1;
end else begin
render_x <= render_x + 1;
end
end
`STATE_READ_SPRITE:
begin
if (num_sprites_drawn >= `NUM_SPRITES) begin
render_state <= `STATE_DECIDE;
end else if (num_sprite_words_read < 2) begin
if (num_sprite_words_read == 0)
sprite_reg_values[`SPRITE_DATA_WIDTH-1:0] <= spr_data;
else if (num_sprite_words_read == 1)
sprite_reg_values[`SPRITE_DATA_WIDTH*2-1:`SPRITE_DATA_WIDTH] <=
spr_data;
num_sprite_words_read <= num_sprite_words_read + 1;
end else begin
if (!sprite_enabled ||
(sprite_top <= sprite_bottom &&
(screen_y < sprite_top || screen_y >= sprite_bottom)) ||
(sprite_top >= sprite_bottom &&
(screen_y >= sprite_bottom && screen_y < sprite_top))
) begin
num_sprite_words_read <= 0;
num_sprites_drawn <= num_sprites_drawn + 1;
end else begin
render_state <= `STATE_DRAW_SPRITE;
render_x <= 0;
end
end
end
`STATE_DRAW_SPRITE:
begin
if (render_x + 1 >= sprite_render_width) begin
render_state <= `STATE_READ_SPRITE;
num_sprites_drawn <= num_sprites_drawn + 1;
num_sprite_words_read <= 0;
end else begin
render_x <= render_x + 1;
end
end
endcase
end
end
wire render_tiles = (render_state == `STATE_DRAW_LAYER);
wire render_sprite = (render_state == `STATE_DRAW_SPRITE);
reg render_tiles_delayed;
reg render_sprite_delayed;
always @ (posedge clk) begin
render_tiles_delayed <= render_tiles;
render_sprite_delayed <= render_sprite;
end
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_x = render_x;
wire [`LINE_BUF_ADDR_WIDTH-2:0] tile_render_y =
screen_y + reg_array[`SCROLL_Y] - tile_offset_y;
wire [`LINE_BUF_ADDR_WIDTH-2:0] sprite_render_x =
(render_x + sprite_screen_offset_x) % `WORLD_WIDTH;
reg [15:0] sprite_x;
reg [15:0] sprite_y;
wire [15:0] sprite_render_y =
(screen_y - sprite_screen_offset_y) % `WORLD_HEIGHT;
wire [15:0] sprite_flipped_x = sprite_render_width - render_x - 1;
wire [15:0] sprite_flipped_y = sprite_render_height - sprite_render_y - 1;
reg [`VRAM_ADDR_WIDTH-1:0] sprite_vram_offset;
always @ (posedge clk) begin
if (~sprite_flip_xy) begin
sprite_x <= sprite_flip_x ? sprite_flipped_x : render_x;
sprite_y <= sprite_flip_y ? sprite_flipped_y : sprite_render_y;
end else begin
sprite_x <= sprite_flip_x ? sprite_flipped_y : sprite_render_y;
sprite_y <= sprite_flip_y ? sprite_flipped_x : render_x;
end
sprite_vram_offset <= sprite_data_offset / 2;
end
wire [15:0] sprite_pixel_offset = sprite_y * sprite_width + sprite_x;
wire [`LINE_BUF_ADDR_WIDTH-2:0] render_x_world =
tile_render_x + reg_array[`SCROLL_X] - tile_offset_x;
wire tile_enable_8x8 = tile_ctrl0[`TILE_ENABLE_8x8];
reg [4:0] map_x;
reg [5:0] map_y;
reg [3:0] tile_x;
reg [3:0] tile_y;
always @ (*) begin
if (tile_enable_8x8) begin
if (tile_enable_8_bit) begin
map_x <= render_x_world[7:3];
map_y <= {tile_render_y[8:3], render_x_world[8]};
end else begin
map_x <= render_x_world[8:3];
map_y <= tile_render_y[8:3];
end
tile_x <= render_x_world[2:0];
tile_y <= tile_render_y[2:0];
end else begin
map_x <= render_x_world[8:4];
map_y <= tile_render_y[8:4];
tile_x <= render_x_world[3:0];
tile_y <= tile_render_y[3:0];
end
end
assign map_addr =
tile_enable_8_bit ? {current_tile_layer, map_y[5:0], map_x[4:1]}
: {current_tile_layer, map_y[4:0], map_x[4:0]};
reg map_data_byte_select;
always @ (posedge clk)
map_data_byte_select <= map_x[0];
wire tile_flip_x = tile_enable_flip & map_data[`TILE_FLIP_X_BIT];
wire tile_flip_y = tile_enable_flip & map_data[`TILE_FLIP_Y_BIT];
wire tile_flip_xy = tile_enable_flip & map_data[`TILE_FLIP_XY_BIT];
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value =
tile_enable_8_bit
? (map_data_byte_select
? map_data[`TILEMAP_DATA_WIDTH-1:`TILEMAP_DATA_WIDTH/2]
: map_data[`TILEMAP_DATA_WIDTH/2-1:0])
: (tile_enable_flip ? (~`TILE_FLIP_BITS_MASK & map_data)
: map_data);
reg [3:0] tile_x_reg;
reg [3:0] tile_y_reg;
always @ (posedge clk) begin
tile_x_reg <= tile_x;
tile_y_reg <= tile_y;
end
reg [3:0] tile_x_flipped;
reg [3:0] tile_y_flipped;
always @ (*)
begin
if (tile_flip_xy) begin
tile_x_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
tile_y_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
end else begin
tile_x_flipped <= tile_flip_x ? ~tile_x_reg : tile_x_reg;
tile_y_flipped <= tile_flip_y ? ~tile_y_reg : tile_y_reg;
end
end
reg [`VRAM_ADDR_WIDTH-1:0] tile_vram_offset;
always @ (posedge clk)
tile_vram_offset <= tile_data_offset / 2;
wire [`VRAM_ADDR_WIDTH-1:0] tile_vram_addr =
tile_enable_8x8 ? {tile_value, tile_y_flipped[2:0], tile_x_flipped[2:1]}
: {tile_value, tile_y_flipped[3:0], tile_x_flipped[3:1]} +
tile_vram_offset;
wire [`VRAM_ADDR_WIDTH-1:0] sprite_vram_addr =
sprite_pixel_offset[15:1] + sprite_vram_offset;
assign vram_addr = render_tiles_delayed ? tile_vram_addr : sprite_vram_addr;
wire vram_byte_select;
CC_Delay #(.WIDTH(1), .DELAY(2))
vram_byte_select_delay(
.clk(clk),
.reset(reset),
.d(render_tiles_delayed ? tile_x_flipped[0] : sprite_pixel_offset[0]),
.q(vram_byte_select));
`define RENDER_DELAY 5
wire [`TILE_PALETTE_WIDTH-1:0] tile_pal_index =
tile_ctrl0[`TILE_PALETTE_END:`TILE_PALETTE_START];
wire [`TILE_PALETTE_WIDTH-1:0] pal_index_delayed;
CC_Delay #(.WIDTH(`TILE_PALETTE_WIDTH), .DELAY(`RENDER_DELAY-2))
pal_index_delay(.clk(clk),
.reset(reset),
.d(render_tiles ? tile_pal_index : sprite_pal_index),
.q(pal_index_delayed));
assign pal_addr =
{ pal_index_delayed,
(vram_byte_select == 0) ? vram_data[7:0] : vram_data[15:8] };
reg [RGB_COLOR_DEPTH-1:0] rgb_out;
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr;
CC_Delay #(.WIDTH(`LINE_BUF_ADDR_WIDTH), .DELAY(`RENDER_DELAY))
buf_addr_delay(
.clk(clk),
.reset(reset),
.d({screen_y[0],
render_tiles_delayed ? tile_render_x : sprite_render_x}),
.q(buf_addr));
wire [3:0] render_state_delayed;
CC_Delay #(.WIDTH(3), .DELAY(`RENDER_DELAY))
render_state_delay(.clk(clk),
.reset(reset),
.d(render_state),
.q(render_state_delayed));
wire [`REG_DATA_WIDTH-1:0] sprite_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] sprite_color_key_delayed;
wire [`BYTE_WIDTH-1:0] current_sprite_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_ctrl0_delay(.clk(clk),
.reset(reset),
.d(sprite_ctrl0),
.q(sprite_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
sprite_color_key_delay(.clk(clk),
.reset(reset),
.d(sprite_color_key),
.q(sprite_color_key_delayed));
CC_Delay #(.WIDTH(`BYTE_WIDTH), .DELAY(`RENDER_DELAY))
current_sprite_delay(.clk(clk),
.reset(reset),
.d(current_sprite),
.q(current_sprite_delayed));
wire [`TILEMAP_DATA_WIDTH-1:0] tile_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_ctrl0_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_nop_value_delayed;
wire [`REG_DATA_WIDTH-1:0] tile_color_key_delayed;
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_enable_nop_delay(.clk(clk),
.reset(reset),
.d(tile_ctrl0),
.q(tile_ctrl0_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_nop_value_delay(.clk(clk),
.reset(reset),
.d(tile_nop_value[`TILEMAP_DATA_WIDTH-1:0]),
.q(tile_nop_value_delayed));
CC_Delay #(.WIDTH(`REG_DATA_WIDTH), .DELAY(`RENDER_DELAY))
tile_color_key_delay(.clk(clk),
.reset(reset),
.d(tile_color_key),
.q(tile_color_key_delayed));
CC_Delay #(.WIDTH(`TILEMAP_DATA_WIDTH), .DELAY(`RENDER_DELAY-1))
tile_value_delay(.clk(clk),
.reset(reset),
.d(map_data),
.q(tile_value_delayed));
wire [7:0] pixel_value_delayed;
CC_Delay #(.WIDTH(8), .DELAY(2))
pixel_value_delay(.clk(clk),
.reset(reset),
.d(pal_addr[7:0]),
.q(pixel_value_delayed));
wire tile_buf_wr = (render_state_delayed == `STATE_DRAW_LAYER) &&
!(tile_value_delayed == tile_nop_value_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_NOP]) &&
!(pixel_value_delayed == tile_color_key_delayed &&
tile_ctrl0_delayed[`TILE_ENABLE_TRANSP]);
wire sprite_buf_wr = (render_state_delayed == `STATE_DRAW_SPRITE) &&
!(pixel_value_delayed == sprite_color_key_delayed &&
sprite_ctrl0_delayed[`SPRITE_ENABLE_TRANSP]);
Palette #(.NUM_CHANNELS(`NUM_PAL_CHANNELS)) line_buffer(
.clk_a(clk),
.wr_a(tile_buf_wr | sprite_buf_wr),
.rd_a(0),
.addr_a(buf_addr),
.data_in_a(pal_data),
.byte_en_a(3'b111),
.clk_b(clk),
.wr_b(h_visible[0] & v_visible[0]),
.rd_b(~(h_blank | v_blank_delayed)),
.addr_b(buf_scanout_addr),
.data_in_b(0),
.data_out_b(buf_scanout_data)
);
wire [`SPRITE_BUF_DATA_WIDTH-1:0] sprite_buffer_out;
collision_buffer_1Kx9 sprite_buffer(
.clock(clk),
.wren_a(sprite_buf_wr),
.address_a(buf_addr),
.data_a({1'b1, current_sprite_delayed}),
.q_a({existing_sprite_pixel_valid, existing_sprite_index}),
.wren_b(h_visible[0] & v_visible[0]),
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(sprite_buffer_out),
);
reg sprite_buf_wr_delayed;
reg [`BYTE_WIDTH-1:0] new_sprite_index;
reg [`LINE_BUF_ADDR_WIDTH-1:0] buf_addr_delayed;
always @ (posedge clk) begin
sprite_buf_wr_delayed <= sprite_buf_wr;
new_sprite_index <= current_sprite_delayed;
buf_addr_delayed <= buf_addr;
end
wire existing_sprite_pixel_valid;
wire [`BYTE_WIDTH-1:0] existing_sprite_index;
wire sprite_collision = sprite_buf_wr_delayed & existing_sprite_pixel_valid;
assign coll_wr = sprite_collision;
assign coll_addr = new_sprite_index;
assign coll_data = existing_sprite_index;
wire [`COLLISION_BUF_DATA_WIDTH-1:0] collision_buffer_out;
collision_buffer_1Kx9 collision_test_buffer(
.clock(clk),
.wren_a(sprite_collision),
.address_a(buf_addr_delayed),
.data_a({`COLLISION_BUF_DATA_WIDTH{1'b1}}),
.wren_b(h_visible[0] & v_visible[0]),
.address_b(buf_scanout_addr),
.data_b(0),
.q_b(collision_buffer_out),
);
wire [`LINE_BUF_ADDR_WIDTH-1:0] buf_scanout_addr;
assign buf_scanout_addr = {~screen_y[0], screen_x};
wire [`PAL_DATA_WIDTH-1:0] buf_scanout_data;
reg [7:0] buf_scanout_red;
reg [7:0] buf_scanout_green;
reg [7:0] buf_scanout_blue;
always @ (negedge clk) begin
`ifndef TEST_COLLISION_BUFFER
buf_scanout_red = buf_scanout_data[7:0];
buf_scanout_green = buf_scanout_data[15:8];
buf_scanout_blue = buf_scanout_data[23:16];
`else
`ifndef TEST_COLLISION_REGIONS_ONLY
`define BUFFER_TEST_BIT sprite_buffer_out[`SPRITE_BUF_DATA_WIDTH-1]
`else
`define BUFFER_TEST_BIT collision_buffer_out[`COLL_DATA_WIDTH-1]
`endif
{buf_scanout_red, buf_scanout_green, buf_scanout_blue} =
`BUFFER_TEST_BIT ? 'h7f7f7f : {buf_scanout_data[7:0],
buf_scanout_data[15:8],
buf_scanout_data[23:16]};
`endif
end
always @ (negedge clk) begin
if (h_blank_delayed | v_blank_delayed) begin
rgb_out <= {RGB_COLOR_DEPTH {1'b0}};
end else if (~h_visible[0]) begin
rgb_out <= {buf_scanout_blue[7:2],
buf_scanout_green[7:2],
buf_scanout_red[7:2]};
end
end
endmodule | 0 |
142,135 | data/full_repos/permissive/9705033/common/renderer_test.v | 9,705,033 | renderer_test.v | v | 101 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(485, 557)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/renderer_test.v:21: Cannot find include file: registers.vh\n`include "registers.vh" \n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/registers.vh.sv\n registers.vh\n registers.vh.v\n registers.vh.sv\n obj_dir/registers.vh\n obj_dir/registers.vh.v\n obj_dir/registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:22: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:23: Cannot find include file: sprite_registers.vh\n`include "sprite_registers.vh" \n ^~~~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/renderer_test.v:72: Unsupported: Ignoring delay on this delayed statement.\n #1 clk = ~clk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/renderer_test.v:82: Unsupported: Ignoring delay on this delayed statement.\n #5 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/renderer_test.v:83: Unsupported: Ignoring delay on this delayed statement.\n #1 reset = 0;\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:86: Define or directive not defined: \'`NUM_SPRITES\'\n for (i = 0; i < `NUM_SPRITES; i = i + 1) begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:86: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_SPRITES; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:86: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `NUM_SPRITES; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/renderer_test.v:92: syntax error, unexpected else\n end else begin\n ^~~~\n%Error: Cannot continue\n' | 313,072 | module | module Renderer_Test;
reg clk;
reg reset;
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController #(.HCOUNT_WIDTH(`DISPLAY_HCOUNT_WIDTH),
.VCOUNT_WIDTH(`DISPLAY_VCOUNT_WIDTH))
display(.clk(clk),
.reset(reset),
.v_pos(v_pos),
.h_pos(h_pos));
wire h_sync, v_sync;
reg [127:0] spr_values [255:0];
reg [127:0] spr_data;
reg [127:0] spr_data_reg;
wire [7:0] spr_addr;
wire spr_clk;
always @ (posedge spr_clk)
spr_data <= spr_values[spr_addr];
Renderer renderer(.clk(clk),
.reset(reset),
.reg_values(0),
.tile_reg_values(0),
.spr_clk(spr_clk),
.spr_addr(spr_addr),
.spr_data(spr_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(h_sync),
.v_sync(v_sync));
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
#5 reset = 1;
#1 reset = 0;
for (i = 0; i < `NUM_SPRITES; i = i + 1) begin
if (i < 4) begin
spr_values[i * 2] = 1 | ((15-i)) << 16;
spr_values[i * 2 + 1] = (i * 8) | ((i * 8) << 16);
end else begin
spr_values[i * 2] = 0;
spr_values[i * 2 + 1] = 0;
end
end
end
endmodule | module Renderer_Test; |
reg clk;
reg reset;
wire [`DISPLAY_HCOUNT_WIDTH-1:0] h_pos;
wire [`DISPLAY_VCOUNT_WIDTH-1:0] v_pos;
DisplayController #(.HCOUNT_WIDTH(`DISPLAY_HCOUNT_WIDTH),
.VCOUNT_WIDTH(`DISPLAY_VCOUNT_WIDTH))
display(.clk(clk),
.reset(reset),
.v_pos(v_pos),
.h_pos(h_pos));
wire h_sync, v_sync;
reg [127:0] spr_values [255:0];
reg [127:0] spr_data;
reg [127:0] spr_data_reg;
wire [7:0] spr_addr;
wire spr_clk;
always @ (posedge spr_clk)
spr_data <= spr_values[spr_addr];
Renderer renderer(.clk(clk),
.reset(reset),
.reg_values(0),
.tile_reg_values(0),
.spr_clk(spr_clk),
.spr_addr(spr_addr),
.spr_data(spr_data),
.h_pos(h_pos),
.v_pos(v_pos),
.h_sync(h_sync),
.v_sync(v_sync));
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
#5 reset = 1;
#1 reset = 0;
for (i = 0; i < `NUM_SPRITES; i = i + 1) begin
if (i < 4) begin
spr_values[i * 2] = 1 | ((15-i)) << 16;
spr_values[i * 2 + 1] = (i * 8) | ((i * 8) << 16);
end else begin
spr_values[i * 2] = 0;
spr_values[i * 2 + 1] = 0;
end
end
end
endmodule | 0 |
142,136 | data/full_repos/permissive/9705033/common/spi_bus.v | 9,705,033 | spi_bus.v | v | 75 | 79 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | [(26, 74)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/9705033/common/spi_bus.v:71: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'miso\' generates 1 bits.\n : ... In instance SPIBus\n assign main_miso = (main_nss == \'b0) ? miso : \'bz;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/spi_bus.v:71: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance SPIBus\n assign main_miso = (main_nss == \'b0) ? miso : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/spi_bus.v:72: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'miso\' generates 1 bits.\n : ... In instance SPIBus\n assign alt_miso = (alt_nss == \'b0) ? miso : \'bz;\n ^\n%Warning-WIDTH: data/full_repos/permissive/9705033/common/spi_bus.v:72: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s COND generates 32 bits.\n : ... In instance SPIBus\n assign alt_miso = (alt_nss == \'b0) ? miso : \'bz;\n ^\n%Error: Exiting due to 4 warning(s)\n' | 313,073 | module | module SPIBus(
input main_nss,
input main_sck,
input main_mosi,
output main_miso,
input alt_nss,
input alt_sck,
input alt_mosi,
output alt_miso,
output reg nss,
output reg sck,
output reg mosi,
input miso
);
wire alt_bus_enabled = (alt_nss == 'b0) & (main_nss == 'b1);
wire main_bus_enabled = (alt_nss == 'b1) & (main_nss == 'b0);
always @ (*) begin
if (alt_bus_enabled) begin
nss <= 'b0;
sck <= alt_sck;
mosi <= alt_mosi;
end else if (main_bus_enabled) begin
nss <= 'b0;
sck <= main_sck;
mosi <= main_mosi;
end else begin
nss <= 'b1;
sck <= 0;
mosi <= 0;
end
end
assign main_miso = (main_nss == 'b0) ? miso : 'bz;
assign alt_miso = (alt_nss == 'b0) ? miso : 'bz;
endmodule | module SPIBus(
input main_nss,
input main_sck,
input main_mosi,
output main_miso,
input alt_nss,
input alt_sck,
input alt_mosi,
output alt_miso,
output reg nss,
output reg sck,
output reg mosi,
input miso
); |
wire alt_bus_enabled = (alt_nss == 'b0) & (main_nss == 'b1);
wire main_bus_enabled = (alt_nss == 'b1) & (main_nss == 'b0);
always @ (*) begin
if (alt_bus_enabled) begin
nss <= 'b0;
sck <= alt_sck;
mosi <= alt_mosi;
end else if (main_bus_enabled) begin
nss <= 'b0;
sck <= main_sck;
mosi <= main_mosi;
end else begin
nss <= 'b1;
sck <= 0;
mosi <= 0;
end
end
assign main_miso = (main_nss == 'b0) ? miso : 'bz;
assign alt_miso = (alt_nss == 'b0) ? miso : 'bz;
endmodule | 0 |
142,137 | data/full_repos/permissive/9705033/common/spi_bus_test.v | 9,705,033 | spi_bus_test.v | v | 153 | 81 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | line:71: before: "(" | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:63: Unsupported: Ignoring delay on this delayed statement.\n #1 main_nss = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:65: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:69: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:78: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:86: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:91: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:105: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:115: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:119: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:121: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:124: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:136: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:140: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:142: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_bus_test.v:145: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_bus_test.v:42: Cannot find file containing module: \'SPIBus\'\n SPIBus spi_bus(main_nss, main_sck, main_mosi, main_miso,\n ^~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/SPIBus\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/SPIBus.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/SPIBus.sv\n SPIBus\n SPIBus.v\n SPIBus.sv\n obj_dir/SPIBus\n obj_dir/SPIBus.v\n obj_dir/SPIBus.sv\n%Error: Exiting due to 1 error(s), 15 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,074 | module | module SPIBusTest;
reg main_nss, main_sck, main_mosi;
wire main_miso;
reg alt_nss, alt_sck, alt_mosi;
wire alt_miso;
wire mem_nss, mem_sck, mem_mosi;
reg mem_miso;
SPIBus spi_bus(main_nss, main_sck, main_mosi, main_miso,
alt_nss, alt_sck, alt_mosi, alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
integer stage;
always @ (*)
mem_miso <= ~mem_mosi;
initial begin
main_nss = 0;
main_sck = 0;
main_mosi = 0;
alt_nss = 1;
alt_sck = 0;
alt_mosi = 0;
stage = 0;
#1 main_nss = 1;
#10
stage = 1;
#10
main_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
main_nss = 1;
#10
alt_nss = 0;
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
alt_nss = 1;
#10
stage = 2;
#10
main_nss = 0;
alt_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
main_nss = 1;
alt_nss = 1;
#10
stage = 3;
end
task main_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
main_sck = 0;
#2
main_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
main_mosi = data[`BYTE_WIDTH - 1 - i];
#1
main_sck = 1;
#1
main_sck = 0;
end
#2
main_sck = 0;
main_mosi = 0;
end
endtask
task alt_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
alt_sck = 0;
#2
alt_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
alt_mosi = data[`BYTE_WIDTH - 1 - i];
#1
alt_sck = 1;
#1
alt_sck = 0;
end
#2
alt_sck = 0;
alt_mosi = 0;
end
endtask
endmodule | module SPIBusTest; |
reg main_nss, main_sck, main_mosi;
wire main_miso;
reg alt_nss, alt_sck, alt_mosi;
wire alt_miso;
wire mem_nss, mem_sck, mem_mosi;
reg mem_miso;
SPIBus spi_bus(main_nss, main_sck, main_mosi, main_miso,
alt_nss, alt_sck, alt_mosi, alt_miso,
mem_nss, mem_sck, mem_mosi, mem_miso);
integer stage;
always @ (*)
mem_miso <= ~mem_mosi;
initial begin
main_nss = 0;
main_sck = 0;
main_mosi = 0;
alt_nss = 1;
alt_sck = 0;
alt_mosi = 0;
stage = 0;
#1 main_nss = 1;
#10
stage = 1;
#10
main_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
main_nss = 1;
#10
alt_nss = 0;
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
alt_nss = 1;
#10
stage = 2;
#10
main_nss = 0;
alt_nss = 0;
main_spi_transmit(8'h01);
main_spi_transmit(8'h02);
main_spi_transmit(8'h04);
main_spi_transmit(8'h08);
alt_spi_transmit(8'h11);
alt_spi_transmit(8'h22);
alt_spi_transmit(8'h44);
alt_spi_transmit(8'h88);
main_nss = 1;
alt_nss = 1;
#10
stage = 3;
end
task main_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
main_sck = 0;
#2
main_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
main_mosi = data[`BYTE_WIDTH - 1 - i];
#1
main_sck = 1;
#1
main_sck = 0;
end
#2
main_sck = 0;
main_mosi = 0;
end
endtask
task alt_spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
alt_sck = 0;
#2
alt_sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
alt_mosi = data[`BYTE_WIDTH - 1 - i];
#1
alt_sck = 1;
#1
alt_sck = 0;
end
#2
alt_sck = 0;
alt_mosi = 0;
end
endtask
endmodule | 0 |
142,138 | data/full_repos/permissive/9705033/common/spi_memory.v | 9,705,033 | spi_memory.v | v | 134 | 80 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | line:70: before: ")" | null | 1: b'%Error: data/full_repos/permissive/9705033/common/spi_memory.v:27: Cannot find include file: spi_memory.vh\n`include "spi_memory.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.sv\n spi_memory.vh\n spi_memory.vh.v\n spi_memory.vh.sv\n obj_dir/spi_memory.vh\n obj_dir/spi_memory.vh.v\n obj_dir/spi_memory.vh.sv\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:31: syntax error, unexpected \')\', expecting \'[\'\n );\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:38: Define or directive not defined: \'`SPI_MEM_ADDR_WIDTH\'\n output [`SPI_MEM_ADDR_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:39: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n input [`SPI_MEM_DATA_WIDTH-1:0] data_in;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:40: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n output [`SPI_MEM_DATA_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:43: Define or directive not defined: \'`BYTE_COUNTER_WIDTH\'\n reg [`BYTE_COUNTER_WIDTH-1:0] spi_counter;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:44: Define or directive not defined: \'`BYTE_WIDTH\'\n reg [`BYTE_WIDTH-1:0] spi_data;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:47: Define or directive not defined: \'`BYTE_WIDTH\'\n reg [`BYTE_WIDTH-1:0] spi_addr_0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:48: Define or directive not defined: \'`BYTE_WIDTH\'\n reg [`BYTE_WIDTH-1:0] spi_addr_1;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:51: syntax error, unexpected always\n always @ (posedge sck)\n ^~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:53: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_data <= {spi_data[`BYTE_WIDTH-2:0], mosi};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:56: Define or directive not defined: \'`SPI_MEM_STATE_DATA_READ\'\n assign rd = (spi_counter == 0) & (spi_state == `SPI_MEM_STATE_DATA_READ);\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:58: Define or directive not defined: \'`BYTE_WIDTH\'\n assign wr = (spi_counter == `BYTE_WIDTH-1) &\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:59: Define or directive not defined: \'`SPI_MEM_STATE_DATA_WRITE\'\n (spi_state == `SPI_MEM_STATE_DATA_WRITE);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:66: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n reg [`SPI_MEM_DATA_WIDTH-1:0] read_data;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:67: syntax error, unexpected always\n always @ (posedge sck) \n ^~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:72: Define or directive not defined: \'`BYTE_WIDTH\'\n assign miso = (spi_counter == 0) ? data_in[`BYTE_WIDTH - 1]\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:73: Define or directive not defined: \'`BYTE_WIDTH\'\n : read_data[`BYTE_WIDTH - 1 - spi_counter];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:76: Define or directive not defined: \'`SPI_MEM_STATE_WIDTH\'\n reg [`SPI_MEM_STATE_WIDTH-1:0] spi_state;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:78: Define or directive not defined: \'`SPI_MEM_STATE_WIDTH\'\n reg [`SPI_MEM_STATE_WIDTH-1:0] spi_prev_state;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:83: syntax error, unexpected always\n always @ (posedge _select or negedge sck) begin\n ^~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:87: Define or directive not defined: \'`SPI_MEM_STATE_ADDR_H\'\n spi_state <= `SPI_MEM_STATE_ADDR_H;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:88: Define or directive not defined: \'`SPI_MEM_STATE_ADDR_H\'\n spi_prev_state <= `SPI_MEM_STATE_ADDR_H;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:93: Define or directive not defined: \'`BYTE_WIDTH\'\n if (spi_counter == `BYTE_WIDTH - 1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:95: Define or directive not defined: \'`SPI_MEM_STATE_ADDR_H\'\n `SPI_MEM_STATE_ADDR_H:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:97: Define or directive not defined: \'`SPI_MEM_STATE_ADDR_L\'\n spi_state <= `SPI_MEM_STATE_ADDR_L;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:99: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_addr_1 <= {1\'b0, spi_data[`BYTE_WIDTH-2:0]};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:100: Define or directive not defined: \'`BYTE_WIDTH\'\n write_op <= spi_data[`BYTE_WIDTH-1];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:102: Define or directive not defined: \'`SPI_MEM_STATE_ADDR_L\'\n `SPI_MEM_STATE_ADDR_L:\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:104: Define or directive not defined: \'`SPI_MEM_STATE_DATA_WRITE\'\n spi_state <= write_op ? `SPI_MEM_STATE_DATA_WRITE\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:105: Define or directive not defined: \'`SPI_MEM_STATE_DATA_READ\'\n : `SPI_MEM_STATE_DATA_READ;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:108: Define or directive not defined: \'`SPI_MEM_STATE_DATA_READ\'\n `SPI_MEM_STATE_DATA_READ:\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:113: Define or directive not defined: \'`BYTE_WIDTH\'\n if (spi_addr_0 == {`BYTE_WIDTH{1\'b1}})\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:114: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_addr_1 <= (spi_addr_1 + 1\'b1) & {(`BYTE_WIDTH-1){1\'b1}};\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:120: Define or directive not defined: \'`SPI_MEM_STATE_DATA_WRITE\'\n end else if (spi_counter == 0 & spi_state == `SPI_MEM_STATE_DATA_WRITE &\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:125: Define or directive not defined: \'`BYTE_WIDTH\'\n if (spi_addr_0 == {`BYTE_WIDTH{1\'b1}})\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory.v:126: Define or directive not defined: \'`BYTE_WIDTH\'\n spi_addr_1 <= (spi_addr_1 + 1\'b1) & {(`BYTE_WIDTH-1){1\'b1}};\n ^~~~~~~~~~~\n%Error: Exiting due to 37 error(s)\n' | 313,075 | module | module SPIMemory(_select, sck, mosi, miso,
addr, data_out, data_in, rd, wr,
);
input _select, sck, mosi;
output miso;
output [`SPI_MEM_ADDR_WIDTH-1:0] addr;
input [`SPI_MEM_DATA_WIDTH-1:0] data_in;
output [`SPI_MEM_DATA_WIDTH-1:0] data_out;
output rd, wr;
reg [`BYTE_COUNTER_WIDTH-1:0] spi_counter;
reg [`BYTE_WIDTH-1:0] spi_data;
reg [`BYTE_WIDTH-1:0] spi_addr_0;
reg [`BYTE_WIDTH-1:0] spi_addr_1;
always @ (posedge sck)
if (~_select)
spi_data <= {spi_data[`BYTE_WIDTH-2:0], mosi};
assign rd = (spi_counter == 0) & (spi_state == `SPI_MEM_STATE_DATA_READ);
assign wr = (spi_counter == `BYTE_WIDTH-1) &
(spi_state == `SPI_MEM_STATE_DATA_WRITE);
assign addr = {spi_addr_1, spi_addr_0};
assign data_out = spi_data;
reg [`SPI_MEM_DATA_WIDTH-1:0] read_data;
always @ (posedge sck)
if (spi_counter == 0)
read_data <= data_in;
assign miso = (spi_counter == 0) ? data_in[`BYTE_WIDTH - 1]
: read_data[`BYTE_WIDTH - 1 - spi_counter];
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_state;
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_prev_state;
reg write_op;
always @ (posedge _select or negedge sck) begin
if (_select) begin
spi_state <= `SPI_MEM_STATE_ADDR_H;
spi_prev_state <= `SPI_MEM_STATE_ADDR_H;
spi_counter <= 1'b0;
write_op <= 0;
end else begin
if (spi_counter == `BYTE_WIDTH - 1) begin
case (spi_state)
`SPI_MEM_STATE_ADDR_H:
begin
spi_state <= `SPI_MEM_STATE_ADDR_L;
spi_addr_1 <= {1'b0, spi_data[`BYTE_WIDTH-2:0]};
write_op <= spi_data[`BYTE_WIDTH-1];
end
`SPI_MEM_STATE_ADDR_L:
begin
spi_state <= write_op ? `SPI_MEM_STATE_DATA_WRITE
: `SPI_MEM_STATE_DATA_READ;
spi_addr_0 <= spi_data;
end
`SPI_MEM_STATE_DATA_READ:
begin
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
endcase
spi_prev_state <= spi_state;
end else if (spi_counter == 0 & spi_state == `SPI_MEM_STATE_DATA_WRITE &
spi_prev_state == spi_state) begin
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
spi_counter <= spi_counter + 1'b1;
end
end
endmodule | module SPIMemory(_select, sck, mosi, miso,
addr, data_out, data_in, rd, wr,
); |
input _select, sck, mosi;
output miso;
output [`SPI_MEM_ADDR_WIDTH-1:0] addr;
input [`SPI_MEM_DATA_WIDTH-1:0] data_in;
output [`SPI_MEM_DATA_WIDTH-1:0] data_out;
output rd, wr;
reg [`BYTE_COUNTER_WIDTH-1:0] spi_counter;
reg [`BYTE_WIDTH-1:0] spi_data;
reg [`BYTE_WIDTH-1:0] spi_addr_0;
reg [`BYTE_WIDTH-1:0] spi_addr_1;
always @ (posedge sck)
if (~_select)
spi_data <= {spi_data[`BYTE_WIDTH-2:0], mosi};
assign rd = (spi_counter == 0) & (spi_state == `SPI_MEM_STATE_DATA_READ);
assign wr = (spi_counter == `BYTE_WIDTH-1) &
(spi_state == `SPI_MEM_STATE_DATA_WRITE);
assign addr = {spi_addr_1, spi_addr_0};
assign data_out = spi_data;
reg [`SPI_MEM_DATA_WIDTH-1:0] read_data;
always @ (posedge sck)
if (spi_counter == 0)
read_data <= data_in;
assign miso = (spi_counter == 0) ? data_in[`BYTE_WIDTH - 1]
: read_data[`BYTE_WIDTH - 1 - spi_counter];
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_state;
reg [`SPI_MEM_STATE_WIDTH-1:0] spi_prev_state;
reg write_op;
always @ (posedge _select or negedge sck) begin
if (_select) begin
spi_state <= `SPI_MEM_STATE_ADDR_H;
spi_prev_state <= `SPI_MEM_STATE_ADDR_H;
spi_counter <= 1'b0;
write_op <= 0;
end else begin
if (spi_counter == `BYTE_WIDTH - 1) begin
case (spi_state)
`SPI_MEM_STATE_ADDR_H:
begin
spi_state <= `SPI_MEM_STATE_ADDR_L;
spi_addr_1 <= {1'b0, spi_data[`BYTE_WIDTH-2:0]};
write_op <= spi_data[`BYTE_WIDTH-1];
end
`SPI_MEM_STATE_ADDR_L:
begin
spi_state <= write_op ? `SPI_MEM_STATE_DATA_WRITE
: `SPI_MEM_STATE_DATA_READ;
spi_addr_0 <= spi_data;
end
`SPI_MEM_STATE_DATA_READ:
begin
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
endcase
spi_prev_state <= spi_state;
end else if (spi_counter == 0 & spi_state == `SPI_MEM_STATE_DATA_WRITE &
spi_prev_state == spi_state) begin
spi_addr_0 <= spi_addr_0 + 1'b1;
if (spi_addr_0 == {`BYTE_WIDTH{1'b1}})
spi_addr_1 <= (spi_addr_1 + 1'b1) & {(`BYTE_WIDTH-1){1'b1}};
end
spi_counter <= spi_counter + 1'b1;
end
end
endmodule | 0 |
142,139 | data/full_repos/permissive/9705033/common/spi_memory_test.v | 9,705,033 | spi_memory_test.v | v | 131 | 81 | [] | ['redistribution and use in source and binary forms, with or without modification, are permitted'] | ['all rights reserved'] | null | line:97: before: "(" | null | 1: b'%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:26: Cannot find include file: spi_memory.vh\n`include "spi_memory.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/spi_memory.vh.sv\n spi_memory.vh\n spi_memory.vh.v\n spi_memory.vh.sv\n obj_dir/spi_memory.vh\n obj_dir/spi_memory.vh.v\n obj_dir/spi_memory.vh.sv\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:34: Define or directive not defined: \'`SPI_MEM_ADDR_WIDTH\'\n wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:35: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:36: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:47: Define or directive not defined: \'`SPI_MEM_DATA_WIDTH\'\n assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : \'bx;\n ^~~~~~~~~~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n #1 _select = 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:56: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:66: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:77: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:87: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:97: Unsupported: Ignoring delay on this delayed statement.\n #10\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:111: Define or directive not defined: \'`BYTE_WIDTH\'\n input [`BYTE_WIDTH-1:0] data;\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:115: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:117: Define or directive not defined: \'`BYTE_WIDTH\'\n for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:117: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:117: syntax error, unexpected \')\', expecting \';\'\n for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:118: Define or directive not defined: \'`BYTE_WIDTH\'\n mosi = data[`BYTE_WIDTH - 1 - i];\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:119: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:121: Unsupported: Ignoring delay on this delayed statement.\n #1\n ^\n%Warning-STMTDLY: data/full_repos/permissive/9705033/common/spi_memory_test.v:124: Unsupported: Ignoring delay on this delayed statement.\n #2\n ^\n%Error: data/full_repos/permissive/9705033/common/spi_memory_test.v:126: syntax error, unexpected end\n end\n ^~~\n%Error: Cannot continue\n' | 313,077 | module | module SPIMemoryTest;
reg _select, sck, mosi;
wire miso;
wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;
wire rd, wr;
SPIMemory spi_memory(
._select(_select), .sck(sck), .mosi(mosi), .miso(miso),
.addr(addr), .data_in(data_in), .data_out(data_out), .rd(rd), .wr(wr)
);
assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : 'bx;
initial begin
_select = 0;
sck = 0;
mosi = 0;
#1 _select = 1;
#10
_select = 0;
spi_transmit(8'hde);
spi_transmit(8'had);
spi_transmit(8'h01);
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'hbe);
spi_transmit(8'hef);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'h5a);
spi_transmit(8'hfe);
spi_transmit(8'h01);
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'h7f);
spi_transmit(8'hfe);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'hff);
spi_transmit(8'hfe);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
end
task spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
sck = 0;
#2
sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
mosi = data[`BYTE_WIDTH - 1 - i];
#1
sck = 1;
#1
sck = 0;
end
#2
sck = 0;
end
endtask
endmodule | module SPIMemoryTest; |
reg _select, sck, mosi;
wire miso;
wire [`SPI_MEM_ADDR_WIDTH-1:0] addr;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_in;
wire [`SPI_MEM_DATA_WIDTH-1:0] data_out;
wire rd, wr;
SPIMemory spi_memory(
._select(_select), .sck(sck), .mosi(mosi), .miso(miso),
.addr(addr), .data_in(data_in), .data_out(data_out), .rd(rd), .wr(wr)
);
assign data_in = rd ? addr[`SPI_MEM_DATA_WIDTH-1:0] : 'bx;
initial begin
_select = 0;
sck = 0;
mosi = 0;
#1 _select = 1;
#10
_select = 0;
spi_transmit(8'hde);
spi_transmit(8'had);
spi_transmit(8'h01);
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'hbe);
spi_transmit(8'hef);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'h5a);
spi_transmit(8'hfe);
spi_transmit(8'h01);
spi_transmit(8'h02);
spi_transmit(8'h04);
spi_transmit(8'h08);
_select = 1;
#10
_select = 0;
spi_transmit(8'h7f);
spi_transmit(8'hfe);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
#10
_select = 0;
spi_transmit(8'hff);
spi_transmit(8'hfe);
spi_transmit(8'h11);
spi_transmit(8'h22);
spi_transmit(8'h44);
spi_transmit(8'h88);
_select = 1;
end
task spi_transmit;
input [`BYTE_WIDTH-1:0] data;
integer i;
begin
sck = 0;
#2
sck = 0;
for (i = 0; i < `BYTE_WIDTH; i = i + 1) begin
mosi = data[`BYTE_WIDTH - 1 - i];
#1
sck = 1;
#1
sck = 0;
end
#2
sck = 0;
end
endtask
endmodule | 0 |
142,140 | data/full_repos/permissive/9705033/common/sprite_reg_decoder.v | 9,705,033 | sprite_reg_decoder.v | v | 116 | 81 | [] | ['general public license', 'free software foundation'] | [] | [(254, 344)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:20: Cannot find include file: sprite_registers.vh\n`include "sprite_registers.vh" \n ^~~~~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/sprite_registers.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/sprite_registers.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/sprite_registers.vh.sv\n sprite_registers.vh\n sprite_registers.vh.v\n sprite_registers.vh.sv\n obj_dir/sprite_registers.vh\n obj_dir/sprite_registers.vh.v\n obj_dir/sprite_registers.vh.sv\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:49: Define or directive not defined: \'`NUM_REG_BITS_PER_SPRITE\'\n input [`NUM_REG_BITS_PER_SPRITE-1:0] reg_values;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:61: Define or directive not defined: \'`SPRITE_PALETTE_WIDTH\'\n output [`SPRITE_PALETTE_WIDTH-1:0] palette;\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:68: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] ctrl0;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:69: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] ctrl1;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:70: Define or directive not defined: \'`VRAM_ADDR_WIDTH\'\n output [`VRAM_ADDR_WIDTH:0] data_offset;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:70: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n output [`VRAM_ADDR_WIDTH:0] data_offset;\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:71: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] ref_xy;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:72: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] color_key;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:73: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] offset_x;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:74: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] offset_y;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:77: Define or directive not defined: \'`REG_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] regs [`NUM_SPRITE_REGS-1:0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:77: Define or directive not defined: \'`NUM_SPRITE_REGS\'\n wire [`REG_DATA_WIDTH-1:0] regs [`NUM_SPRITE_REGS-1:0];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:80: Define or directive not defined: \'`NUM_SPRITE_REGS\'\n for (i = 0; i < `NUM_SPRITE_REGS; i = i + 1) begin: SPRITE_REGS\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:80: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_SPRITE_REGS; i = i + 1) begin: SPRITE_REGS\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:81: Define or directive not defined: \'`REG_DATA_WIDTH\'\n assign regs[i] = reg_values[(i+1)*`REG_DATA_WIDTH-1:i*`REG_DATA_WIDTH];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:81: Define or directive not defined: \'`REG_DATA_WIDTH\'\n assign regs[i] = reg_values[(i+1)*`REG_DATA_WIDTH-1:i*`REG_DATA_WIDTH];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:86: Define or directive not defined: \'`SPRITE_ENABLED\'\n assign enabled = ctrl0[`SPRITE_ENABLED];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:87: Define or directive not defined: \'`SPRITE_ENABLE_SCROLL\'\n assign enable_scroll = ctrl0[`SPRITE_ENABLE_SCROLL];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:87: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_scroll = ctrl0[`SPRITE_ENABLE_SCROLL];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:88: Define or directive not defined: \'`SPRITE_ENABLE_TRANSP\'\n assign enable_transp = ctrl0[`SPRITE_ENABLE_TRANSP];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:88: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_transp = ctrl0[`SPRITE_ENABLE_TRANSP];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:89: Define or directive not defined: \'`SPRITE_ENABLE_ALPHA\'\n assign enable_alpha = ctrl0[`SPRITE_ENABLE_ALPHA];\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:89: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_alpha = ctrl0[`SPRITE_ENABLE_ALPHA];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:90: Define or directive not defined: \'`SPRITE_ENABLE_COLOR\'\n assign enable_color = ctrl0[`SPRITE_ENABLE_COLOR];\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:90: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_color = ctrl0[`SPRITE_ENABLE_COLOR];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:91: Define or directive not defined: \'`SPRITE_FLIP_X\'\n assign flip_x = ctrl0[`SPRITE_FLIP_X];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:91: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign flip_x = ctrl0[`SPRITE_FLIP_X];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:92: Define or directive not defined: \'`SPRITE_FLIP_Y\'\n assign flip_y = ctrl0[`SPRITE_FLIP_Y];\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:92: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign flip_y = ctrl0[`SPRITE_FLIP_Y];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:93: Define or directive not defined: \'`SPRITE_FLIP_XY\'\n assign flip_xy = ctrl0[`SPRITE_FLIP_XY];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:93: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign flip_xy = ctrl0[`SPRITE_FLIP_XY];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:94: Define or directive not defined: \'`SPRITE_SHIFT_DATA_OFFSET\'\n assign shift_data_offset = ctrl0[`SPRITE_SHIFT_DATA_OFFSET];\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:94: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign shift_data_offset = ctrl0[`SPRITE_SHIFT_DATA_OFFSET];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:95: Define or directive not defined: \'`SPRITE_PALETTE_END\'\n assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:95: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:95: Define or directive not defined: \'`SPRITE_PALETTE_START\'\n assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];\n ^~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:98: Define or directive not defined: \'`SPRITE_HSIZE_END\'\n wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:98: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:98: Define or directive not defined: \'`SPRITE_HSIZE_START\'\n wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:99: Define or directive not defined: \'`SPRITE_VSIZE_END\'\n wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:99: syntax error, unexpected \':\', expecting TYPE-IDENTIFIER\n wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:99: Define or directive not defined: \'`SPRITE_VSIZE_START\'\n wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:104: Define or directive not defined: \'`SPRITE_CTRL0\'\n assign ctrl0 = regs[`SPRITE_CTRL0];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:104: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ctrl0 = regs[`SPRITE_CTRL0];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:105: Define or directive not defined: \'`SPRITE_CTRL1\'\n assign ctrl1 = regs[`SPRITE_CTRL1];\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:105: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign ctrl1 = regs[`SPRITE_CTRL1];\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:108: Define or directive not defined: \'`SPRITE_DATA_OFFSET\'\n ? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:108: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n ? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)\n ^\n%Error: data/full_repos/permissive/9705033/common/sprite_reg_decoder.v:108: Define or directive not defined: \'`SPRITE_DATA_OFFSET_SHIFT\'\n ? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,079 | module | module SpriteRegDecoder(reg_values,
enabled,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
flip_x,
flip_y,
flip_xy,
shift_data_offset,
palette,
width,
height,
ctrl0,
ctrl1,
data_offset,
ref_xy,
color_key,
offset_x,
offset_y);
input [`NUM_REG_BITS_PER_SPRITE-1:0] reg_values;
output enabled;
output enable_scroll;
output enable_transp;
output enable_alpha;
output enable_color;
output flip_x;
output flip_y;
output flip_xy;
output shift_data_offset;
output [`SPRITE_PALETTE_WIDTH-1:0] palette;
output [31:0] width;
output [31:0] height;
output [`REG_DATA_WIDTH-1:0] ctrl0;
output [`REG_DATA_WIDTH-1:0] ctrl1;
output [`VRAM_ADDR_WIDTH:0] data_offset;
output [`REG_DATA_WIDTH-1:0] ref_xy;
output [`REG_DATA_WIDTH-1:0] color_key;
output [`REG_DATA_WIDTH-1:0] offset_x;
output [`REG_DATA_WIDTH-1:0] offset_y;
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_SPRITE_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_SPRITE_REGS; i = i + 1) begin: SPRITE_REGS
assign regs[i] = reg_values[(i+1)*`REG_DATA_WIDTH-1:i*`REG_DATA_WIDTH];
end
endgenerate
assign enabled = ctrl0[`SPRITE_ENABLED];
assign enable_scroll = ctrl0[`SPRITE_ENABLE_SCROLL];
assign enable_transp = ctrl0[`SPRITE_ENABLE_TRANSP];
assign enable_alpha = ctrl0[`SPRITE_ENABLE_ALPHA];
assign enable_color = ctrl0[`SPRITE_ENABLE_COLOR];
assign flip_x = ctrl0[`SPRITE_FLIP_X];
assign flip_y = ctrl0[`SPRITE_FLIP_Y];
assign flip_xy = ctrl0[`SPRITE_FLIP_XY];
assign shift_data_offset = ctrl0[`SPRITE_SHIFT_DATA_OFFSET];
assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];
wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];
wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];
assign width = (`SPRITE_MIN_SIZE << width_shift);
assign height = (`SPRITE_MIN_SIZE << height_shift);
assign ctrl0 = regs[`SPRITE_CTRL0];
assign ctrl1 = regs[`SPRITE_CTRL1];
assign data_offset =
shift_data_offset
? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)
: regs[`SPRITE_DATA_OFFSET];
assign ref_xy = regs[`SPRITE_REF_XY];
assign color_key = regs[`SPRITE_COLOR_KEY];
assign offset_x = regs[`SPRITE_OFFSET_X];
assign offset_y = regs[`SPRITE_OFFSET_Y];
endmodule | module SpriteRegDecoder(reg_values,
enabled,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
flip_x,
flip_y,
flip_xy,
shift_data_offset,
palette,
width,
height,
ctrl0,
ctrl1,
data_offset,
ref_xy,
color_key,
offset_x,
offset_y); |
input [`NUM_REG_BITS_PER_SPRITE-1:0] reg_values;
output enabled;
output enable_scroll;
output enable_transp;
output enable_alpha;
output enable_color;
output flip_x;
output flip_y;
output flip_xy;
output shift_data_offset;
output [`SPRITE_PALETTE_WIDTH-1:0] palette;
output [31:0] width;
output [31:0] height;
output [`REG_DATA_WIDTH-1:0] ctrl0;
output [`REG_DATA_WIDTH-1:0] ctrl1;
output [`VRAM_ADDR_WIDTH:0] data_offset;
output [`REG_DATA_WIDTH-1:0] ref_xy;
output [`REG_DATA_WIDTH-1:0] color_key;
output [`REG_DATA_WIDTH-1:0] offset_x;
output [`REG_DATA_WIDTH-1:0] offset_y;
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_SPRITE_REGS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_SPRITE_REGS; i = i + 1) begin: SPRITE_REGS
assign regs[i] = reg_values[(i+1)*`REG_DATA_WIDTH-1:i*`REG_DATA_WIDTH];
end
endgenerate
assign enabled = ctrl0[`SPRITE_ENABLED];
assign enable_scroll = ctrl0[`SPRITE_ENABLE_SCROLL];
assign enable_transp = ctrl0[`SPRITE_ENABLE_TRANSP];
assign enable_alpha = ctrl0[`SPRITE_ENABLE_ALPHA];
assign enable_color = ctrl0[`SPRITE_ENABLE_COLOR];
assign flip_x = ctrl0[`SPRITE_FLIP_X];
assign flip_y = ctrl0[`SPRITE_FLIP_Y];
assign flip_xy = ctrl0[`SPRITE_FLIP_XY];
assign shift_data_offset = ctrl0[`SPRITE_SHIFT_DATA_OFFSET];
assign palette = ctrl0[`SPRITE_PALETTE_END:`SPRITE_PALETTE_START];
wire [1:0] width_shift = ctrl1[`SPRITE_HSIZE_END:`SPRITE_HSIZE_START];
wire [1:0] height_shift = ctrl1[`SPRITE_VSIZE_END:`SPRITE_VSIZE_START];
assign width = (`SPRITE_MIN_SIZE << width_shift);
assign height = (`SPRITE_MIN_SIZE << height_shift);
assign ctrl0 = regs[`SPRITE_CTRL0];
assign ctrl1 = regs[`SPRITE_CTRL1];
assign data_offset =
shift_data_offset
? (regs[`SPRITE_DATA_OFFSET] << `SPRITE_DATA_OFFSET_SHIFT)
: regs[`SPRITE_DATA_OFFSET];
assign ref_xy = regs[`SPRITE_REF_XY];
assign color_key = regs[`SPRITE_COLOR_KEY];
assign offset_x = regs[`SPRITE_OFFSET_X];
assign offset_y = regs[`SPRITE_OFFSET_Y];
endmodule | 0 |
142,141 | data/full_repos/permissive/9705033/common/tile_reg_decoder.v | 9,705,033 | tile_reg_decoder.v | v | 120 | 79 | [] | ['general public license', 'free software foundation'] | [] | [(282, 379)] | null | null | 1: b'%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:20: Cannot find include file: memory_map.vh\n`include "memory_map.vh" \n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/memory_map.vh\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/memory_map.vh.v\n data/full_repos/permissive/9705033/common,data/full_repos/permissive/9705033/memory_map.vh.sv\n memory_map.vh\n memory_map.vh.v\n memory_map.vh.sv\n obj_dir/memory_map.vh\n obj_dir/memory_map.vh.v\n obj_dir/memory_map.vh.sv\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:21: Cannot find include file: tile_registers.vh\n`include "tile_registers.vh" \n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:49: Define or directive not defined: \'`NUM_TOTAL_TILE_REG_BITS\'\n input [`NUM_TOTAL_TILE_REG_BITS-1:0] reg_values;\n ^~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:51: Define or directive not defined: \'`NUM_REG_BITS_PER_TILE_LAYER\'\n wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:52: Define or directive not defined: \'`NUM_TILE_LAYERS\'\n reg_values_array[`NUM_TILE_LAYERS-1:0];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:55: Define or directive not defined: \'`NUM_TILE_LAYERS\'\n for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:55: syntax error, unexpected \';\', expecting TYPE-IDENTIFIER\n for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:57: Define or directive not defined: \'`NUM_REG_BITS_PER_TILE_LAYER\'\n reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:58: Define or directive not defined: \'`NUM_REG_BITS_PER_TILE_LAYER\'\n i * `NUM_REG_BITS_PER_TILE_LAYER];\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:62: Define or directive not defined: \'`REG_DATA_WIDTH\'\n wire [`REG_DATA_WIDTH-1:0] regs [`NUM_TILE_REGISTERS-1:0];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:62: Define or directive not defined: \'`NUM_TILE_REGISTERS\'\n wire [`REG_DATA_WIDTH-1:0] regs [`NUM_TILE_REGISTERS-1:0];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:64: Define or directive not defined: \'`NUM_TILE_REGISTERS\'\n for (i = 0; i < `NUM_TILE_REGISTERS; i = i + 1) begin: TILE_REGS\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:66: Define or directive not defined: \'`REG_DATA_WIDTH\'\n reg_values_array[current_layer][(i+1)*`REG_DATA_WIDTH-1:\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:67: Define or directive not defined: \'`REG_DATA_WIDTH\'\n i*`REG_DATA_WIDTH];\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:83: Define or directive not defined: \'`TILE_HSIZE_WIDTH\'\n output [`TILE_HSIZE_WIDTH-1:0] tile_hsize_enum;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:84: Define or directive not defined: \'`TILE_VSIZE_WIDTH\'\n output [`TILE_VSIZE_WIDTH-1:0] tile_vsize_enum;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:86: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] ctrl0 ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:87: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] ctrl1 ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:88: Define or directive not defined: \'`VRAM_ADDR_WIDTH\'\n output [`VRAM_ADDR_WIDTH:0] data_offset ;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:89: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] nop_value ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:90: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] color_key ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:91: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] offset_x ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:92: Define or directive not defined: \'`REG_DATA_WIDTH\'\n output [`REG_DATA_WIDTH-1:0] offset_y ;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:94: Define or directive not defined: \'`TILE_CTRL0\'\n assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:94: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:94: Define or directive not defined: \'`TILE_LAYER_ENABLED\'\n assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:95: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:95: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:95: Define or directive not defined: \'`TILE_ENABLE_8_BIT\'\n assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:96: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:96: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:96: Define or directive not defined: \'`TILE_ENABLE_NOP\'\n assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:97: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:97: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:97: Define or directive not defined: \'`TILE_ENABLE_SCROLL\'\n assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:98: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:98: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:98: Define or directive not defined: \'`TILE_ENABLE_TRANSP\'\n assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:99: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:99: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:99: Define or directive not defined: \'`TILE_ENABLE_ALPHA\'\n assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:100: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:100: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:100: Define or directive not defined: \'`TILE_ENABLE_COLOR\'\n assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:101: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:101: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:101: Define or directive not defined: \'`TILE_ENABLE_WRAP_X\'\n assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:102: Define or directive not defined: \'`TILE_CTRL0\'\n assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:102: syntax error, unexpected \']\', expecting TYPE-IDENTIFIER\n assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];\n ^\n%Error: data/full_repos/permissive/9705033/common/tile_reg_decoder.v:102: Define or directive not defined: \'`TILE_ENABLE_WRAP_Y\'\n assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];\n ^~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,081 | module | module TileRegDecoder(current_layer,
reg_values,
layer_enabled,
enable_8bit,
enable_nop,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
enable_wrap_x,
enable_wrap_y,
enable_flip,
shift_data_offset,
tile_hsize_enum,
tile_vsize_enum,
ctrl0,
ctrl1,
data_offset,
nop_value,
color_key,
offset_x,
offset_y);
input [1:0] current_layer;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] reg_values;
wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]
reg_values_array[`NUM_TILE_LAYERS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES
assign reg_values_array[i] =
reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:
i * `NUM_REG_BITS_PER_TILE_LAYER];
end
endgenerate
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_TILE_REGISTERS-1:0];
generate
for (i = 0; i < `NUM_TILE_REGISTERS; i = i + 1) begin: TILE_REGS
assign regs[i] =
reg_values_array[current_layer][(i+1)*`REG_DATA_WIDTH-1:
i*`REG_DATA_WIDTH];
end
endgenerate
output layer_enabled ;
output enable_8bit ;
output enable_nop ;
output enable_scroll ;
output enable_transp ;
output enable_alpha ;
output enable_color ;
output enable_wrap_x ;
output enable_wrap_y ;
output enable_flip ;
output shift_data_offset;
output [`TILE_HSIZE_WIDTH-1:0] tile_hsize_enum;
output [`TILE_VSIZE_WIDTH-1:0] tile_vsize_enum;
output [`REG_DATA_WIDTH-1:0] ctrl0 ;
output [`REG_DATA_WIDTH-1:0] ctrl1 ;
output [`VRAM_ADDR_WIDTH:0] data_offset ;
output [`REG_DATA_WIDTH-1:0] nop_value ;
output [`REG_DATA_WIDTH-1:0] color_key ;
output [`REG_DATA_WIDTH-1:0] offset_x ;
output [`REG_DATA_WIDTH-1:0] offset_y ;
assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];
assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];
assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];
assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];
assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];
assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];
assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];
assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];
assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];
assign enable_flip = regs[`TILE_CTRL0][`TILE_ENABLE_FLIP];
assign shift_data_offset = regs[`TILE_CTRL0][`TILE_SHIFT_DATA_OFFSET];
assign tile_hsize_enum = regs[`TILE_CTRL1][`TILE_HSIZE_1:`TILE_HSIZE_0];
assign tile_vsize_enum = regs[`TILE_CTRL1][`TILE_VSIZE_1:`TILE_VSIZE_0];
assign ctrl0 = regs[`TILE_CTRL0];
assign ctrl1 = regs[`TILE_CTRL1];
assign data_offset =
shift_data_offset ? (regs[`TILE_DATA_OFFSET] << `TILE_DATA_OFFSET_SHIFT)
: regs[`TILE_DATA_OFFSET];
assign nop_value = regs[`TILE_NOP_VALUE];
assign color_key = regs[`TILE_COLOR_KEY];
assign offset_x = regs[`TILE_OFFSET_X];
assign offset_y = regs[`TILE_OFFSET_Y];
endmodule | module TileRegDecoder(current_layer,
reg_values,
layer_enabled,
enable_8bit,
enable_nop,
enable_scroll,
enable_transp,
enable_alpha,
enable_color,
enable_wrap_x,
enable_wrap_y,
enable_flip,
shift_data_offset,
tile_hsize_enum,
tile_vsize_enum,
ctrl0,
ctrl1,
data_offset,
nop_value,
color_key,
offset_x,
offset_y); |
input [1:0] current_layer;
input [`NUM_TOTAL_TILE_REG_BITS-1:0] reg_values;
wire [`NUM_REG_BITS_PER_TILE_LAYER-1:0]
reg_values_array[`NUM_TILE_LAYERS-1:0];
genvar i;
generate
for (i = 0; i < `NUM_TILE_LAYERS; i = i + 1) begin: TILE_REG_VALUES
assign reg_values_array[i] =
reg_values[(i + 1) * `NUM_REG_BITS_PER_TILE_LAYER - 1:
i * `NUM_REG_BITS_PER_TILE_LAYER];
end
endgenerate
wire [`REG_DATA_WIDTH-1:0] regs [`NUM_TILE_REGISTERS-1:0];
generate
for (i = 0; i < `NUM_TILE_REGISTERS; i = i + 1) begin: TILE_REGS
assign regs[i] =
reg_values_array[current_layer][(i+1)*`REG_DATA_WIDTH-1:
i*`REG_DATA_WIDTH];
end
endgenerate
output layer_enabled ;
output enable_8bit ;
output enable_nop ;
output enable_scroll ;
output enable_transp ;
output enable_alpha ;
output enable_color ;
output enable_wrap_x ;
output enable_wrap_y ;
output enable_flip ;
output shift_data_offset;
output [`TILE_HSIZE_WIDTH-1:0] tile_hsize_enum;
output [`TILE_VSIZE_WIDTH-1:0] tile_vsize_enum;
output [`REG_DATA_WIDTH-1:0] ctrl0 ;
output [`REG_DATA_WIDTH-1:0] ctrl1 ;
output [`VRAM_ADDR_WIDTH:0] data_offset ;
output [`REG_DATA_WIDTH-1:0] nop_value ;
output [`REG_DATA_WIDTH-1:0] color_key ;
output [`REG_DATA_WIDTH-1:0] offset_x ;
output [`REG_DATA_WIDTH-1:0] offset_y ;
assign layer_enabled = regs[`TILE_CTRL0][`TILE_LAYER_ENABLED];
assign enable_8bit = regs[`TILE_CTRL0][`TILE_ENABLE_8_BIT];
assign enable_nop = regs[`TILE_CTRL0][`TILE_ENABLE_NOP];
assign enable_scroll = regs[`TILE_CTRL0][`TILE_ENABLE_SCROLL];
assign enable_transp = regs[`TILE_CTRL0][`TILE_ENABLE_TRANSP];
assign enable_alpha = regs[`TILE_CTRL0][`TILE_ENABLE_ALPHA];
assign enable_color = regs[`TILE_CTRL0][`TILE_ENABLE_COLOR];
assign enable_wrap_x = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_X];
assign enable_wrap_y = regs[`TILE_CTRL0][`TILE_ENABLE_WRAP_Y];
assign enable_flip = regs[`TILE_CTRL0][`TILE_ENABLE_FLIP];
assign shift_data_offset = regs[`TILE_CTRL0][`TILE_SHIFT_DATA_OFFSET];
assign tile_hsize_enum = regs[`TILE_CTRL1][`TILE_HSIZE_1:`TILE_HSIZE_0];
assign tile_vsize_enum = regs[`TILE_CTRL1][`TILE_VSIZE_1:`TILE_VSIZE_0];
assign ctrl0 = regs[`TILE_CTRL0];
assign ctrl1 = regs[`TILE_CTRL1];
assign data_offset =
shift_data_offset ? (regs[`TILE_DATA_OFFSET] << `TILE_DATA_OFFSET_SHIFT)
: regs[`TILE_DATA_OFFSET];
assign nop_value = regs[`TILE_NOP_VALUE];
assign color_key = regs[`TILE_COLOR_KEY];
assign offset_x = regs[`TILE_OFFSET_X];
assign offset_y = regs[`TILE_OFFSET_Y];
endmodule | 0 |
142,142 | data/full_repos/permissive/97070179/multi_cycle_cpu/sim.v | 97,070,179 | sim.v | v | 30 | 44 | [] | [] | [] | [(3, 29)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/97070179/multi_cycle_cpu/sim.v:13: Unsupported: Ignoring delay on this delayed statement.\n # 3\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/97070179/multi_cycle_cpu/sim.v:21: Unsupported: Ignoring delay on this delayed statement.\n # 2 mips_cpu_clk = ~mips_cpu_clk;\n ^\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/sim.v:24: Cannot find file containing module: \'mips_cpu_top\'\n mips_cpu_top u_mips_cpu_top (\n ^~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu,data/full_repos/permissive/97070179/mips_cpu_top\n data/full_repos/permissive/97070179/multi_cycle_cpu,data/full_repos/permissive/97070179/mips_cpu_top.v\n data/full_repos/permissive/97070179/multi_cycle_cpu,data/full_repos/permissive/97070179/mips_cpu_top.sv\n mips_cpu_top\n mips_cpu_top.v\n mips_cpu_top.sv\n obj_dir/mips_cpu_top\n obj_dir/mips_cpu_top.v\n obj_dir/mips_cpu_top.sv\n%Error: Exiting due to 1 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,089 | module | module mips_cpu_test
();
reg mips_cpu_clk;
reg mips_cpu_reset;
initial begin
mips_cpu_clk = 1'b0;
mips_cpu_reset = 1'b1;
# 3
mips_cpu_reset = 1'b0;
end
always begin
# 2 mips_cpu_clk = ~mips_cpu_clk;
end
mips_cpu_top u_mips_cpu_top (
.mips_cpu_clk (mips_cpu_clk),
.mips_cpu_reset (mips_cpu_reset)
);
endmodule | module mips_cpu_test
(); |
reg mips_cpu_clk;
reg mips_cpu_reset;
initial begin
mips_cpu_clk = 1'b0;
mips_cpu_reset = 1'b1;
# 3
mips_cpu_reset = 1'b0;
end
always begin
# 2 mips_cpu_clk = ~mips_cpu_clk;
end
mips_cpu_top u_mips_cpu_top (
.mips_cpu_clk (mips_cpu_clk),
.mips_cpu_reset (mips_cpu_reset)
);
endmodule | 2 |
142,143 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/alu.v | 97,070,179 | alu.v | v | 42 | 95 | [] | [] | [] | [(2, 41)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/alu.v:21: Signal definition not found, creating implicitly: \'Result_SLT\'\n : ... Suggested alternative: \'Result_SLL\'\n 3\'b111: Result<=Result_SLT;\n ^~~~~~~~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/alu.v:21: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'Result_SLT\' generates 1 bits.\n : ... In instance alu\n 3\'b111: Result<=Result_SLT;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/alu.v:32: Operator ADD expects 34 bits on the RHS, but RHS\'s SEL generates 1 bits.\n : ... In instance alu\n assign {CF, OF, Result_PLUS}={A[31], A}+{B_OP[31], B_OP}+ALUop[2];\n ^\n%Warning-WIDTH: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/alu.v:33: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s REPLICATE generates 32 bits.\n : ... In instance alu\n assign Result_SLT={31\'b0, OF};\n ^\n%Error: Exiting due to 4 warning(s)\n' | 313,090 | module | module alu(
input [31:0] A,
input [31:0] B,
input [4:0] shamt,
input [2:0] ALUop,
output Overflow,
output CarryOut,
output Zero,
output reg [31:0] Result
);
wire OF, CF;
wire [31:0] B_OP, Result_AND, Result_OR, Result_PLUS, Result_LUI, Result_SLL, Result_SLTU;
always@(*)
begin
case(ALUop)
3'b000: Result<=Result_AND;
3'b001: Result<=Result_OR;
3'b010, 3'b110: Result<=Result_PLUS;
3'b111: Result<=Result_SLT;
3'b011: Result<=Result_LUI;
3'b100: Result<=Result_SLL;
3'b101: Result<=Result_SLTU;
default: Result<=32'b0;
endcase
end
assign Result_AND=A&B;
assign Result_OR=A|B;
assign B_OP=B^{32{ALUop[2]}};
assign {CF, OF, Result_PLUS}={A[31], A}+{B_OP[31], B_OP}+ALUop[2];
assign Result_SLT={31'b0, OF};
assign Result_LUI={B[15:0], 16'b0};
assign Result_SLL=B<<shamt;
assign Result_SLTU={31'b0, ~CF};
assign Overflow=OF^Result_PLUS[31];
assign CarryOut=CF^ALUop[2];
assign Zero=~|Result_PLUS;
endmodule | module alu(
input [31:0] A,
input [31:0] B,
input [4:0] shamt,
input [2:0] ALUop,
output Overflow,
output CarryOut,
output Zero,
output reg [31:0] Result
); |
wire OF, CF;
wire [31:0] B_OP, Result_AND, Result_OR, Result_PLUS, Result_LUI, Result_SLL, Result_SLTU;
always@(*)
begin
case(ALUop)
3'b000: Result<=Result_AND;
3'b001: Result<=Result_OR;
3'b010, 3'b110: Result<=Result_PLUS;
3'b111: Result<=Result_SLT;
3'b011: Result<=Result_LUI;
3'b100: Result<=Result_SLL;
3'b101: Result<=Result_SLTU;
default: Result<=32'b0;
endcase
end
assign Result_AND=A&B;
assign Result_OR=A|B;
assign B_OP=B^{32{ALUop[2]}};
assign {CF, OF, Result_PLUS}={A[31], A}+{B_OP[31], B_OP}+ALUop[2];
assign Result_SLT={31'b0, OF};
assign Result_LUI={B[15:0], 16'b0};
assign Result_SLL=B<<shamt;
assign Result_SLTU={31'b0, ~CF};
assign Overflow=OF^Result_PLUS[31];
assign CarryOut=CF^ALUop[2];
assign Zero=~|Result_PLUS;
endmodule | 2 |
142,144 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | module | module mips_cpu(
input clk,
input rst,
output reg [31:0] PC,
input [31:0] Instruction,
output [31:0] Address,
output MemWrite,
output [31:0] Write_data,
output MemRead,
input [31:0] Read_data
);
wire [31:0] alu_in_A, alu_in_B;
wire [4:0] alu_in_shamt;
wire [2:0] alu_in_ALUop;
wire alu_out_Overflow, alu_out_CarryOut, alu_out_Zero;
wire [31:0] alu_out_Result;
wire [4:0] rf_in_waddr, rf_in_raddr1, rf_in_raddr2;
wire rf_in_wen;
wire [31:0] rf_in_wdata;
wire [31:0] rf_out_rdata1, rf_out_rdata2;
wire [5:0] cu_in_Opcode;
wire cu_out_RegWrite, cu_out_ALUSrcA, cu_out_MemRead, cu_out_MemWrite, cu_out_IRWrite,
cu_out_PCWrite, cu_out_PCWriteCond, cu_out_ALUCond;
wire [1:0] cu_out_RegDst, cu_out_MemtoReg, cu_out_ALUSrcB, cu_out_PCSource;
wire ac_in_ALUCond;
wire [5:0] ac_in_Opcode, ac_in_Funct;
wire [2:0] ac_out_ALUop;
wire ac_out_PCWrite;
wire [5:0] bc_in_Opcode;
wire [31:0] bc_in_ALUResult;
wire bc_in_Overflow, bc_in_CarryOut, bc_in_Zero;
wire bc_out_Result;
reg [31:0] Instruction_reg, Memory_Data_reg, ALUIn_A, ALUIn_B, ALUOut;
wire PC_control;
wire [31:0] PC_next, Sign_extend;
alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow),
.CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));
reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2),
.wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));
control_unit cu_i(.clk(clk), .rst(rst), .Opcode(cu_in_Opcode), .RegDst(cu_out_RegDst),
.RegWrite(cu_out_RegWrite), .ALUSrcA(cu_out_ALUSrcA), .MemRead(cu_out_MemRead),
.MemWrite(cu_out_MemWrite), .MemtoReg(cu_out_MemtoReg), .IRWrite(cu_out_IRWrite),
.PCWrite(cu_out_PCWrite), .PCWriteCond(cu_out_PCWriteCond), .ALUCond(cu_out_ALUCond),
.ALUSrcB(cu_out_ALUSrcB), .PCSource(cu_out_PCSource));
alu_control ac_i(.ALUCond(ac_in_ALUCond), .Opcode(ac_in_Opcode), .Funct(ac_in_Funct),
.ALUop(ac_out_ALUop), .PCWrite(ac_out_PCWrite));
branch_control bc_i(.Opcode(bc_in_Opcode), .ALUResult(bc_in_ALUResult), .Overflow(bc_in_Overflow),
.CarryOut(bc_in_CarryOut), .Zero(bc_in_Zero), .BranchResult(bc_out_Result));
assign alu_in_A = cu_out_ALUSrcA ? ALUIn_A : PC;
assign alu_in_B = cu_out_ALUSrcB[1] ?
(cu_out_ALUSrcB[0] ? Sign_extend << 2 : Sign_extend) :
(cu_out_ALUSrcB[0] ? 32'd4 : ALUIn_B);
assign alu_in_shamt = Instruction_reg[10:6];
assign alu_in_ALUop = ac_out_ALUop;
assign rf_in_waddr = cu_out_RegDst[1] ? 5'd31 :
(cu_out_RegDst[0] ? Instruction_reg[15:11] : Instruction_reg[20:16]);
assign rf_in_raddr1 = Instruction_reg[25:21];
assign rf_in_raddr2 = Instruction_reg[20:16];
assign rf_in_wen = cu_out_RegWrite;
assign rf_in_wdata = cu_out_MemtoReg[1] ? PC :
(cu_out_MemtoReg[0] ? Memory_Data_reg : ALUOut);
assign cu_in_Opcode = Instruction_reg[31:26];
assign ac_in_ALUCond = cu_out_ALUCond;
assign ac_in_Opcode = Instruction_reg[31:26];
assign ac_in_Funct = Instruction_reg[5:0];
assign bc_in_Opcode = Instruction_reg[31:26];
assign bc_in_ALUResult = alu_out_Result;
assign bc_in_Overflow = alu_out_Overflow;
assign bc_in_CarryOut = alu_out_CarryOut;
assign bc_in_Zero = alu_out_Zero;
assign PC_control = ( bc_out_Result & cu_out_PCWriteCond ) | cu_out_PCWrite | ac_out_PCWrite;
assign PC_next = cu_out_PCSource[1] ? {PC[31:28], Instruction_reg[25:0], 2'b0} :
(cu_out_PCSource[0] ? ALUOut : alu_out_Result);
assign Sign_extend = {{16{Instruction_reg[15]}}, Instruction_reg[15:0]};
assign Address = ALUOut;
assign MemWrite = cu_out_MemWrite;
assign Write_data = ALUIn_B;
assign MemRead = cu_out_MemRead;
always @(posedge clk)
begin
if(rst)
PC <= 32'd0;
else if(PC_control)
PC <= PC_next;
if(cu_out_IRWrite)
Instruction_reg <= Instruction;
Memory_Data_reg <= Read_data;
ALUIn_A <= rf_out_rdata1;
ALUIn_B <= rf_out_rdata2;
ALUOut <= alu_out_Result;
end
endmodule | module mips_cpu(
input clk,
input rst,
output reg [31:0] PC,
input [31:0] Instruction,
output [31:0] Address,
output MemWrite,
output [31:0] Write_data,
output MemRead,
input [31:0] Read_data
); |
wire [31:0] alu_in_A, alu_in_B;
wire [4:0] alu_in_shamt;
wire [2:0] alu_in_ALUop;
wire alu_out_Overflow, alu_out_CarryOut, alu_out_Zero;
wire [31:0] alu_out_Result;
wire [4:0] rf_in_waddr, rf_in_raddr1, rf_in_raddr2;
wire rf_in_wen;
wire [31:0] rf_in_wdata;
wire [31:0] rf_out_rdata1, rf_out_rdata2;
wire [5:0] cu_in_Opcode;
wire cu_out_RegWrite, cu_out_ALUSrcA, cu_out_MemRead, cu_out_MemWrite, cu_out_IRWrite,
cu_out_PCWrite, cu_out_PCWriteCond, cu_out_ALUCond;
wire [1:0] cu_out_RegDst, cu_out_MemtoReg, cu_out_ALUSrcB, cu_out_PCSource;
wire ac_in_ALUCond;
wire [5:0] ac_in_Opcode, ac_in_Funct;
wire [2:0] ac_out_ALUop;
wire ac_out_PCWrite;
wire [5:0] bc_in_Opcode;
wire [31:0] bc_in_ALUResult;
wire bc_in_Overflow, bc_in_CarryOut, bc_in_Zero;
wire bc_out_Result;
reg [31:0] Instruction_reg, Memory_Data_reg, ALUIn_A, ALUIn_B, ALUOut;
wire PC_control;
wire [31:0] PC_next, Sign_extend;
alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow),
.CarryOut(alu_out_CarryOut), .Zero(alu_out_Zero), .Result(alu_out_Result));
reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2),
.wen(rf_in_wen), .wdata(rf_in_wdata), .rdata1(rf_out_rdata1), .rdata2(rf_out_rdata2));
control_unit cu_i(.clk(clk), .rst(rst), .Opcode(cu_in_Opcode), .RegDst(cu_out_RegDst),
.RegWrite(cu_out_RegWrite), .ALUSrcA(cu_out_ALUSrcA), .MemRead(cu_out_MemRead),
.MemWrite(cu_out_MemWrite), .MemtoReg(cu_out_MemtoReg), .IRWrite(cu_out_IRWrite),
.PCWrite(cu_out_PCWrite), .PCWriteCond(cu_out_PCWriteCond), .ALUCond(cu_out_ALUCond),
.ALUSrcB(cu_out_ALUSrcB), .PCSource(cu_out_PCSource));
alu_control ac_i(.ALUCond(ac_in_ALUCond), .Opcode(ac_in_Opcode), .Funct(ac_in_Funct),
.ALUop(ac_out_ALUop), .PCWrite(ac_out_PCWrite));
branch_control bc_i(.Opcode(bc_in_Opcode), .ALUResult(bc_in_ALUResult), .Overflow(bc_in_Overflow),
.CarryOut(bc_in_CarryOut), .Zero(bc_in_Zero), .BranchResult(bc_out_Result));
assign alu_in_A = cu_out_ALUSrcA ? ALUIn_A : PC;
assign alu_in_B = cu_out_ALUSrcB[1] ?
(cu_out_ALUSrcB[0] ? Sign_extend << 2 : Sign_extend) :
(cu_out_ALUSrcB[0] ? 32'd4 : ALUIn_B);
assign alu_in_shamt = Instruction_reg[10:6];
assign alu_in_ALUop = ac_out_ALUop;
assign rf_in_waddr = cu_out_RegDst[1] ? 5'd31 :
(cu_out_RegDst[0] ? Instruction_reg[15:11] : Instruction_reg[20:16]);
assign rf_in_raddr1 = Instruction_reg[25:21];
assign rf_in_raddr2 = Instruction_reg[20:16];
assign rf_in_wen = cu_out_RegWrite;
assign rf_in_wdata = cu_out_MemtoReg[1] ? PC :
(cu_out_MemtoReg[0] ? Memory_Data_reg : ALUOut);
assign cu_in_Opcode = Instruction_reg[31:26];
assign ac_in_ALUCond = cu_out_ALUCond;
assign ac_in_Opcode = Instruction_reg[31:26];
assign ac_in_Funct = Instruction_reg[5:0];
assign bc_in_Opcode = Instruction_reg[31:26];
assign bc_in_ALUResult = alu_out_Result;
assign bc_in_Overflow = alu_out_Overflow;
assign bc_in_CarryOut = alu_out_CarryOut;
assign bc_in_Zero = alu_out_Zero;
assign PC_control = ( bc_out_Result & cu_out_PCWriteCond ) | cu_out_PCWrite | ac_out_PCWrite;
assign PC_next = cu_out_PCSource[1] ? {PC[31:28], Instruction_reg[25:0], 2'b0} :
(cu_out_PCSource[0] ? ALUOut : alu_out_Result);
assign Sign_extend = {{16{Instruction_reg[15]}}, Instruction_reg[15:0]};
assign Address = ALUOut;
assign MemWrite = cu_out_MemWrite;
assign Write_data = ALUIn_B;
assign MemRead = cu_out_MemRead;
always @(posedge clk)
begin
if(rst)
PC <= 32'd0;
else if(PC_control)
PC <= PC_next;
if(cu_out_IRWrite)
Instruction_reg <= Instruction;
Memory_Data_reg <= Read_data;
ALUIn_A <= rf_out_rdata1;
ALUIn_B <= rf_out_rdata2;
ALUOut <= alu_out_Result;
end
endmodule | 2 |
142,145 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | module | module control_unit(
input clk,
input rst,
input [5:0] Opcode,
output [1:0] RegDst,
output RegWrite,
output ALUSrcA,
output MemRead,
output MemWrite,
output [1:0] MemtoReg,
output IRWrite,
output PCWrite,
output PCWriteCond,
output ALUCond,
output [1:0] ALUSrcB,
output [1:0] PCSource
);
reg [3:0] State;
reg [16:0] CtrlResult;
always @(posedge clk)
begin
if(rst)
State <= 0;
else
State <= State_next(State, Opcode);
end
always @(*)
case(State)
4'd0: CtrlResult <= 17'b00001_00001_100_0100;
4'd1: CtrlResult <= 17'b00000_00000_000_1100;
4'd2, 4'd10: CtrlResult <= 17'b00010_00000_000_1000;
4'd3: CtrlResult <= 17'b00001_00010_000_0000;
4'd4: CtrlResult <= 17'b00100_00100_000_0000;
4'd5: CtrlResult <= 17'b00000_10010_000_0000;
4'd6: CtrlResult <= 17'b00010_00000_001_0000;
4'd7: CtrlResult <= 17'b01100_00000_000_0000;
4'd8: CtrlResult <= 17'b00010_00000_011_0001;
4'd9: CtrlResult <= 17'b00000_00000_100_0010;
4'd11: CtrlResult <= 17'b00010_00000_001_1000;
4'd12: CtrlResult <= 17'b00100_00000_000_0000;
4'd13: CtrlResult <= 17'b10100_01000_100_0010;
default: CtrlResult <= 17'b00000_00000_000_0000;
endcase
assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond,
ALUCond, ALUSrcB, PCSource} = CtrlResult;
function [3:0] State_next;
input [3:0] State_now;
input [5:0] Opcode;
begin
case(State_now)
4'd1: State_next = Optype(Opcode);
4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd12, 4'd13: State_next = 4'd0;
4'd10: State_next = 4'd5;
default: State_next = State_now + 1;
endcase
end
endfunction
function [3:0] Optype;
input [5:0] Opcode;
begin
case(Opcode)
6'b100011: Optype=4'd2;
6'b101011: Optype=4'd10;
6'b000000: Optype=4'd6;
6'b000100, 6'b000101: Optype=4'd8;
6'b000010: Optype=4'd9;
6'b000011: Optype=4'd13;
6'b001001, 6'b001111, 6'b001010, 6'b001011: Optype=4'd11;
default: Optype=4'd0;
endcase
end
endfunction
endmodule | module control_unit(
input clk,
input rst,
input [5:0] Opcode,
output [1:0] RegDst,
output RegWrite,
output ALUSrcA,
output MemRead,
output MemWrite,
output [1:0] MemtoReg,
output IRWrite,
output PCWrite,
output PCWriteCond,
output ALUCond,
output [1:0] ALUSrcB,
output [1:0] PCSource
); |
reg [3:0] State;
reg [16:0] CtrlResult;
always @(posedge clk)
begin
if(rst)
State <= 0;
else
State <= State_next(State, Opcode);
end
always @(*)
case(State)
4'd0: CtrlResult <= 17'b00001_00001_100_0100;
4'd1: CtrlResult <= 17'b00000_00000_000_1100;
4'd2, 4'd10: CtrlResult <= 17'b00010_00000_000_1000;
4'd3: CtrlResult <= 17'b00001_00010_000_0000;
4'd4: CtrlResult <= 17'b00100_00100_000_0000;
4'd5: CtrlResult <= 17'b00000_10010_000_0000;
4'd6: CtrlResult <= 17'b00010_00000_001_0000;
4'd7: CtrlResult <= 17'b01100_00000_000_0000;
4'd8: CtrlResult <= 17'b00010_00000_011_0001;
4'd9: CtrlResult <= 17'b00000_00000_100_0010;
4'd11: CtrlResult <= 17'b00010_00000_001_1000;
4'd12: CtrlResult <= 17'b00100_00000_000_0000;
4'd13: CtrlResult <= 17'b10100_01000_100_0010;
default: CtrlResult <= 17'b00000_00000_000_0000;
endcase
assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond,
ALUCond, ALUSrcB, PCSource} = CtrlResult;
function [3:0] State_next;
input [3:0] State_now;
input [5:0] Opcode;
begin
case(State_now)
4'd1: State_next = Optype(Opcode);
4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd12, 4'd13: State_next = 4'd0;
4'd10: State_next = 4'd5;
default: State_next = State_now + 1;
endcase
end
endfunction
function [3:0] Optype;
input [5:0] Opcode;
begin
case(Opcode)
6'b100011: Optype=4'd2;
6'b101011: Optype=4'd10;
6'b000000: Optype=4'd6;
6'b000100, 6'b000101: Optype=4'd8;
6'b000010: Optype=4'd9;
6'b000011: Optype=4'd13;
6'b001001, 6'b001111, 6'b001010, 6'b001011: Optype=4'd11;
default: Optype=4'd0;
endcase
end
endfunction
endmodule | 2 |
142,146 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | module | module alu_control(
input ALUCond,
input [5:0] Opcode,
input [5:0] Funct,
output reg [2:0] ALUop,
output reg PCWrite
);
always @(*)
if(ALUCond)
case(Opcode)
6'b000000:
case(Funct)
6'b001000: {ALUop, PCWrite} <= 4'b010_1;
6'b000000: {ALUop, PCWrite} <= 4'b100_0;
6'b101010: {ALUop, PCWrite} <= 4'b111_0;
default: {ALUop, PCWrite} <= 4'b010_0;
endcase
6'b000100, 6'b000101:
{ALUop, PCWrite} <= 4'b110_0;
6'b001111:
{ALUop, PCWrite} <= 4'b011_0;
6'b001010:
{ALUop, PCWrite} <= 4'b111_0;
6'b001011:
{ALUop, PCWrite} <= 4'b101_0;
default:
{ALUop, PCWrite} <= 4'b010_0;
endcase
else
{ALUop, PCWrite} <= 4'b010_0;
endmodule | module alu_control(
input ALUCond,
input [5:0] Opcode,
input [5:0] Funct,
output reg [2:0] ALUop,
output reg PCWrite
); |
always @(*)
if(ALUCond)
case(Opcode)
6'b000000:
case(Funct)
6'b001000: {ALUop, PCWrite} <= 4'b010_1;
6'b000000: {ALUop, PCWrite} <= 4'b100_0;
6'b101010: {ALUop, PCWrite} <= 4'b111_0;
default: {ALUop, PCWrite} <= 4'b010_0;
endcase
6'b000100, 6'b000101:
{ALUop, PCWrite} <= 4'b110_0;
6'b001111:
{ALUop, PCWrite} <= 4'b011_0;
6'b001010:
{ALUop, PCWrite} <= 4'b111_0;
6'b001011:
{ALUop, PCWrite} <= 4'b101_0;
default:
{ALUop, PCWrite} <= 4'b010_0;
endcase
else
{ALUop, PCWrite} <= 4'b010_0;
endmodule | 2 |
142,147 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | module | module branch_control(
input [5:0] Opcode,
input [31:0] ALUResult,
input Overflow,
input CarryOut,
input Zero,
output reg BranchResult
);
always @(*)
begin
case(Opcode)
6'b000100: BranchResult <= Zero;
6'b000101: BranchResult <= ~Zero;
default: BranchResult <= 1'b0;
endcase
end
endmodule | module branch_control(
input [5:0] Opcode,
input [31:0] ALUResult,
input Overflow,
input CarryOut,
input Zero,
output reg BranchResult
); |
always @(*)
begin
case(Opcode)
6'b000100: BranchResult <= Zero;
6'b000101: BranchResult <= ~Zero;
default: BranchResult <= 1'b0;
endcase
end
endmodule | 2 |
142,148 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | function | function [3:0] State_next;
input [3:0] State_now;
input [5:0] Opcode;
begin
case(State_now)
4'd1: State_next = Optype(Opcode);
4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd12, 4'd13: State_next = 4'd0;
4'd10: State_next = 4'd5;
default: State_next = State_now + 1;
endcase
end
endfunction | function [3:0] State_next; |
input [3:0] State_now;
input [5:0] Opcode;
begin
case(State_now)
4'd1: State_next = Optype(Opcode);
4'd4, 4'd5, 4'd7, 4'd8, 4'd9, 4'd12, 4'd13: State_next = 4'd0;
4'd10: State_next = 4'd5;
default: State_next = State_now + 1;
endcase
end
endfunction | 2 |
142,149 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v | 97,070,179 | mips_cpu.v | v | 247 | 116 | [] | [] | [] | [(1, 114), (116, 195), (197, 227), (229, 246)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:163: Signal definition not found, creating implicitly: \'IorD\'\n assign {RegDst, RegWrite, ALUSrcA, MemRead, MemWrite, MemtoReg, IorD, IRWrite, PCWrite, PCWriteCond, \n ^~~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:42: Cannot find file containing module: \'alu\'\n alu alu_i(.A(alu_in_A), .B(alu_in_B), .shamt(alu_in_shamt), .ALUop(alu_in_ALUop), .Overflow(alu_out_Overflow), \n ^~~\n ... Looked in:\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.v\n data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core,data/full_repos/permissive/97070179/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/mips_cpu.v:45: Cannot find file containing module: \'reg_file\'\n reg_file rf_i(.rst(rst), .clk(clk), .waddr(rf_in_waddr), .raddr1(rf_in_raddr1), .raddr2(rf_in_raddr2), \n ^~~~~~~~\n%Error: Exiting due to 2 error(s), 1 warning(s)\n' | 313,091 | function | function [3:0] Optype;
input [5:0] Opcode;
begin
case(Opcode)
6'b100011: Optype=4'd2;
6'b101011: Optype=4'd10;
6'b000000: Optype=4'd6;
6'b000100, 6'b000101: Optype=4'd8;
6'b000010: Optype=4'd9;
6'b000011: Optype=4'd13;
6'b001001, 6'b001111, 6'b001010, 6'b001011: Optype=4'd11;
default: Optype=4'd0;
endcase
end
endfunction | function [3:0] Optype; |
input [5:0] Opcode;
begin
case(Opcode)
6'b100011: Optype=4'd2;
6'b101011: Optype=4'd10;
6'b000000: Optype=4'd6;
6'b000100, 6'b000101: Optype=4'd8;
6'b000010: Optype=4'd9;
6'b000011: Optype=4'd13;
6'b001001, 6'b001111, 6'b001010, 6'b001011: Optype=4'd11;
default: Optype=4'd0;
endcase
end
endfunction | 2 |
142,150 | data/full_repos/permissive/97070179/multi_cycle_cpu/mips_core/reg_file.v | 97,070,179 | reg_file.v | v | 22 | 45 | [] | [] | [] | [(2, 21)] | null | data/verilator_xmls/38cfde83-0000-4cf0-9f88-a2d5cef385c4.xml | null | 313,092 | module | module reg_file(
input clk,
input rst,
input [4:0] waddr,
input [4:0] raddr1,
input [4:0] raddr2,
input wen,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
);
reg [31:0] mem [0:31];
always@(posedge clk)
if(wen)
mem[waddr]<=wdata;
assign rdata1={32{|raddr1}}&mem[raddr1];
assign rdata2={32{|raddr2}}&mem[raddr2];
endmodule | module reg_file(
input clk,
input rst,
input [4:0] waddr,
input [4:0] raddr1,
input [4:0] raddr2,
input wen,
input [31:0] wdata,
output [31:0] rdata1,
output [31:0] rdata2
); |
reg [31:0] mem [0:31];
always@(posedge clk)
if(wen)
mem[waddr]<=wdata;
assign rdata1={32{|raddr1}}&mem[raddr1];
assign rdata2={32{|raddr2}}&mem[raddr2];
endmodule | 2 |
142,152 | data/full_repos/permissive/97170571/tut.fi/communication.bridge/wb_cpu/1.0/wb_master.v | 97,170,571 | wb_master.v | v | 156 | 220 | [] | [] | [] | [(13, 155)] | null | data/verilator_xmls/03ef3b35-97c3-43a5-bb07-d461217a0142.xml | null | 313,116 | module | module wb_master #(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter BASE_ADDRESS = 'h0F00,
parameter RANGE = 'h0200
) (
input [ADDR_WIDTH-1:0] mem_address_in,
input [DATA_WIDTH-1:0] mem_data_in,
input mem_master_rdy,
input mem_we_in,
output reg [DATA_WIDTH-1:0] mem_data_out,
output reg mem_slave_rdy,
input ack_i,
input [DATA_WIDTH-1:0] dat_i,
input err_i,
output reg [ADDR_WIDTH-1:0] adr_o,
output reg cyc_o,
output reg [DATA_WIDTH-1:0] dat_o,
output reg stb_o,
output reg we_o,
input clk_i,
input rst_i
);
reg [2:0] state;
parameter [2:0]
S_CMD = 3'd0,
S_WRITE_INIT = 3'd1,
S_WAIT_WRITE_ACK = 3'd2,
S_READ_INIT = 3'd3,
S_WAIT_READ_ACK = 3'd4,
S_DEASSERT = 3'd5;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
state <= S_CMD;
dat_o <= 0;
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
adr_o <= 0;
mem_data_out <= 0;
mem_slave_rdy <= 0;
end
else begin
case(state)
S_CMD: begin
if (mem_master_rdy == 1'b1) begin
if (mem_we_in == 1'b1) begin
state <= S_WRITE_INIT;
end
else begin
state <= S_READ_INIT;
end
end
end
S_WRITE_INIT: begin
cyc_o <= 1;
stb_o <= 1;
we_o <= 1;
dat_o <= mem_data_in;
adr_o <= mem_address_in;
state <= S_WAIT_WRITE_ACK;
end
S_WAIT_WRITE_ACK: begin
if (err_i == 1'b1 || ack_i == 1'b1) begin
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
mem_slave_rdy <= 1;
state <= S_DEASSERT;
end
end
S_READ_INIT: begin
cyc_o <= 1;
stb_o <= 1;
we_o <= 0;
adr_o <= mem_address_in;
state <= S_WAIT_READ_ACK;
end
S_WAIT_READ_ACK: begin
if (err_i == 1'b1 || ack_i == 1'b1) begin
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
mem_slave_rdy <= 1;
if (err_i == 1'b1) begin
mem_data_out <= 0;
end
else begin
mem_data_out <= dat_i;
end
state <= S_DEASSERT;
end
end
S_DEASSERT: begin
state <= S_CMD;
mem_slave_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule | module wb_master #(
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter BASE_ADDRESS = 'h0F00,
parameter RANGE = 'h0200
) (
input [ADDR_WIDTH-1:0] mem_address_in,
input [DATA_WIDTH-1:0] mem_data_in,
input mem_master_rdy,
input mem_we_in,
output reg [DATA_WIDTH-1:0] mem_data_out,
output reg mem_slave_rdy,
input ack_i,
input [DATA_WIDTH-1:0] dat_i,
input err_i,
output reg [ADDR_WIDTH-1:0] adr_o,
output reg cyc_o,
output reg [DATA_WIDTH-1:0] dat_o,
output reg stb_o,
output reg we_o,
input clk_i,
input rst_i
); |
reg [2:0] state;
parameter [2:0]
S_CMD = 3'd0,
S_WRITE_INIT = 3'd1,
S_WAIT_WRITE_ACK = 3'd2,
S_READ_INIT = 3'd3,
S_WAIT_READ_ACK = 3'd4,
S_DEASSERT = 3'd5;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
state <= S_CMD;
dat_o <= 0;
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
adr_o <= 0;
mem_data_out <= 0;
mem_slave_rdy <= 0;
end
else begin
case(state)
S_CMD: begin
if (mem_master_rdy == 1'b1) begin
if (mem_we_in == 1'b1) begin
state <= S_WRITE_INIT;
end
else begin
state <= S_READ_INIT;
end
end
end
S_WRITE_INIT: begin
cyc_o <= 1;
stb_o <= 1;
we_o <= 1;
dat_o <= mem_data_in;
adr_o <= mem_address_in;
state <= S_WAIT_WRITE_ACK;
end
S_WAIT_WRITE_ACK: begin
if (err_i == 1'b1 || ack_i == 1'b1) begin
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
mem_slave_rdy <= 1;
state <= S_DEASSERT;
end
end
S_READ_INIT: begin
cyc_o <= 1;
stb_o <= 1;
we_o <= 0;
adr_o <= mem_address_in;
state <= S_WAIT_READ_ACK;
end
S_WAIT_READ_ACK: begin
if (err_i == 1'b1 || ack_i == 1'b1) begin
cyc_o <= 0;
stb_o <= 0;
we_o <= 0;
mem_slave_rdy <= 1;
if (err_i == 1'b1) begin
mem_data_out <= 0;
end
else begin
mem_data_out <= dat_i;
end
state <= S_DEASSERT;
end
end
S_DEASSERT: begin
state <= S_CMD;
mem_slave_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule | 0 |
142,153 | data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.v | 97,170,571 | wb_cpu.setup.v | v | 173 | 125 | [] | [] | [] | [(13, 172)] | null | null | 1: b"%Error: data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.v:112: Cannot find file containing module: 'clock_generator'\n clock_generator clock_generator_0(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0,data/full_repos/permissive/97170571/clock_generator\n data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0,data/full_repos/permissive/97170571/clock_generator.v\n data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0,data/full_repos/permissive/97170571/clock_generator.sv\n clock_generator\n clock_generator.v\n clock_generator.sv\n obj_dir/clock_generator\n obj_dir/clock_generator.v\n obj_dir/clock_generator.sv\n%Error: data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.v:118: Cannot find file containing module: 'wb_slave_mem_master'\n wb_slave_mem_master #(\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/communication.bridge.test/wb_cpu.setup/1.0/wb_cpu.setup.v:145: Cannot find file containing module: 'wb_master'\n wb_master #(\n ^~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,120 | module | module wb_cpu_setup();
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
wire [15:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
wire [31:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms;
wire [31:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
wire wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
wire wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
wire [15:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress;
wire [31:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms;
wire [31:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire wb_cpu_bench_0_ack_o;
wire [15:0] wb_cpu_bench_0_adr_i;
wire wb_cpu_bench_0_clk_i;
wire wb_cpu_bench_0_cyc_i;
wire [31:0] wb_cpu_bench_0_dat_i;
wire [31:0] wb_cpu_bench_0_dat_o;
wire wb_cpu_bench_0_err_o;
wire [15:0] wb_cpu_bench_0_mem_address_o;
wire [31:0] wb_cpu_bench_0_mem_data_i;
wire [31:0] wb_cpu_bench_0_mem_data_o;
wire wb_cpu_bench_0_mem_master_rdy;
wire wb_cpu_bench_0_mem_slave_rdy;
wire wb_cpu_bench_0_mem_we_o;
wire wb_cpu_bench_0_rst_i;
wire wb_cpu_bench_0_stb_i;
wire wb_cpu_bench_0_we_i;
wire wb_cpu_0_ack_i;
wire [15:0] wb_cpu_0_adr_o;
wire wb_cpu_0_clk_i;
wire wb_cpu_0_cyc_o;
wire [31:0] wb_cpu_0_dat_i;
wire [31:0] wb_cpu_0_dat_o;
wire wb_cpu_0_err_i;
wire [15:0] wb_cpu_0_mem_address_in;
wire [31:0] wb_cpu_0_mem_data_in;
wire [31:0] wb_cpu_0_mem_data_out;
wire wb_cpu_0_mem_master_rdy;
wire wb_cpu_0_mem_slave_rdy;
wire wb_cpu_0_mem_we_in;
wire wb_cpu_0_rst_i;
wire wb_cpu_0_stb_o;
wire wb_cpu_0_we_o;
assign wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack = wb_cpu_bench_0_ack_o;
assign wb_cpu_bench_0_adr_i[15:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0];
assign wb_cpu_bench_0_clk_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_cpu_bench_0_cyc_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
assign wb_cpu_bench_0_dat_i[31:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0] = wb_cpu_bench_0_dat_o[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr = wb_cpu_bench_0_err_o;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0] = wb_cpu_bench_0_mem_address_o[15:0];
assign wb_cpu_bench_0_mem_data_i[31:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0] = wb_cpu_bench_0_mem_data_o[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy = wb_cpu_bench_0_mem_master_rdy;
assign wb_cpu_bench_0_mem_slave_rdy = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe = wb_cpu_bench_0_mem_we_o;
assign wb_cpu_bench_0_rst_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_cpu_bench_0_stb_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
assign wb_cpu_bench_0_we_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
assign wb_cpu_0_ack_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0] = wb_cpu_0_adr_o[15:0];
assign wb_cpu_0_clk_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc = wb_cpu_0_cyc_o;
assign wb_cpu_0_dat_i[31:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0] = wb_cpu_0_dat_o[31:0];
assign wb_cpu_0_err_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
assign wb_cpu_0_mem_address_in[15:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0];
assign wb_cpu_0_mem_data_in[31:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0] = wb_cpu_0_mem_data_out[31:0];
assign wb_cpu_0_mem_master_rdy = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy = wb_cpu_0_mem_slave_rdy;
assign wb_cpu_0_mem_we_in = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
assign wb_cpu_0_rst_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb = wb_cpu_0_stb_o;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe = wb_cpu_0_we_o;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
wb_slave_mem_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (3840))
wb_cpu_bench_0(
.mem_data_i (wb_cpu_bench_0_mem_data_i),
.mem_slave_rdy (wb_cpu_bench_0_mem_slave_rdy),
.mem_address_o (wb_cpu_bench_0_mem_address_o),
.mem_data_o (wb_cpu_bench_0_mem_data_o),
.mem_master_rdy (wb_cpu_bench_0_mem_master_rdy),
.mem_we_o (wb_cpu_bench_0_mem_we_o),
.adr_i (wb_cpu_bench_0_adr_i),
.cyc_i (wb_cpu_bench_0_cyc_i),
.dat_i (wb_cpu_bench_0_dat_i),
.stb_i (wb_cpu_bench_0_stb_i),
.we_i (wb_cpu_bench_0_we_i),
.ack_o (wb_cpu_bench_0_ack_o),
.dat_o (wb_cpu_bench_0_dat_o),
.err_o (wb_cpu_bench_0_err_o),
.clk_i (wb_cpu_bench_0_clk_i),
.rst_i (wb_cpu_bench_0_rst_i));
wb_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.BASE_ADDRESS (3840),
.RANGE (512))
wb_cpu_0(
.mem_address_in (wb_cpu_0_mem_address_in),
.mem_data_in (wb_cpu_0_mem_data_in),
.mem_master_rdy (wb_cpu_0_mem_master_rdy),
.mem_we_in (wb_cpu_0_mem_we_in),
.mem_data_out (wb_cpu_0_mem_data_out),
.mem_slave_rdy (wb_cpu_0_mem_slave_rdy),
.ack_i (wb_cpu_0_ack_i),
.dat_i (wb_cpu_0_dat_i),
.err_i (wb_cpu_0_err_i),
.adr_o (wb_cpu_0_adr_o),
.cyc_o (wb_cpu_0_cyc_o),
.dat_o (wb_cpu_0_dat_o),
.stb_o (wb_cpu_0_stb_o),
.we_o (wb_cpu_0_we_o),
.clk_i (wb_cpu_0_clk_i),
.rst_i (wb_cpu_0_rst_i));
endmodule | module wb_cpu_setup(); |
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
wire [15:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
wire [31:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms;
wire [31:0] wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
wire wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
wire wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
wire wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
wire [15:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress;
wire [31:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms;
wire [31:0] wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
wire wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire wb_cpu_bench_0_ack_o;
wire [15:0] wb_cpu_bench_0_adr_i;
wire wb_cpu_bench_0_clk_i;
wire wb_cpu_bench_0_cyc_i;
wire [31:0] wb_cpu_bench_0_dat_i;
wire [31:0] wb_cpu_bench_0_dat_o;
wire wb_cpu_bench_0_err_o;
wire [15:0] wb_cpu_bench_0_mem_address_o;
wire [31:0] wb_cpu_bench_0_mem_data_i;
wire [31:0] wb_cpu_bench_0_mem_data_o;
wire wb_cpu_bench_0_mem_master_rdy;
wire wb_cpu_bench_0_mem_slave_rdy;
wire wb_cpu_bench_0_mem_we_o;
wire wb_cpu_bench_0_rst_i;
wire wb_cpu_bench_0_stb_i;
wire wb_cpu_bench_0_we_i;
wire wb_cpu_0_ack_i;
wire [15:0] wb_cpu_0_adr_o;
wire wb_cpu_0_clk_i;
wire wb_cpu_0_cyc_o;
wire [31:0] wb_cpu_0_dat_i;
wire [31:0] wb_cpu_0_dat_o;
wire wb_cpu_0_err_i;
wire [15:0] wb_cpu_0_mem_address_in;
wire [31:0] wb_cpu_0_mem_data_in;
wire [31:0] wb_cpu_0_mem_data_out;
wire wb_cpu_0_mem_master_rdy;
wire wb_cpu_0_mem_slave_rdy;
wire wb_cpu_0_mem_we_in;
wire wb_cpu_0_rst_i;
wire wb_cpu_0_stb_o;
wire wb_cpu_0_we_o;
assign wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack = wb_cpu_bench_0_ack_o;
assign wb_cpu_bench_0_adr_i[15:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0];
assign wb_cpu_bench_0_clk_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_cpu_bench_0_cyc_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc;
assign wb_cpu_bench_0_dat_i[31:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0] = wb_cpu_bench_0_dat_o[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr = wb_cpu_bench_0_err_o;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0] = wb_cpu_bench_0_mem_address_o[15:0];
assign wb_cpu_bench_0_mem_data_i[31:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0] = wb_cpu_bench_0_mem_data_o[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy = wb_cpu_bench_0_mem_master_rdy;
assign wb_cpu_bench_0_mem_slave_rdy = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe = wb_cpu_bench_0_mem_we_o;
assign wb_cpu_bench_0_rst_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_cpu_bench_0_stb_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb;
assign wb_cpu_bench_0_we_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe;
assign wb_cpu_0_ack_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveack;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveadr[15:0] = wb_cpu_0_adr_o[15:0];
assign wb_cpu_0_clk_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemclk;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavecyc = wb_cpu_0_cyc_o;
assign wb_cpu_0_dat_i[31:0] = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_sm[31:0];
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavedat_ms[31:0] = wb_cpu_0_dat_o[31:0];
assign wb_cpu_0_err_i = wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slaveerr;
assign wb_cpu_0_mem_address_in[15:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceaddress[15:0];
assign wb_cpu_0_mem_data_in[31:0] = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_ms[31:0];
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacedata_sm[31:0] = wb_cpu_0_mem_data_out[31:0];
assign wb_cpu_0_mem_master_rdy = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacemaster_rdy;
assign wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfaceslave_rdy = wb_cpu_0_mem_slave_rdy;
assign wb_cpu_0_mem_we_in = wb_cpu_0_contoller_to_wb_cpu_bench_0_memory_interfacewe;
assign wb_cpu_0_rst_i = wb_cpu_0_wb_system_to_clock_generator_0_wb_systemrst;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavestb = wb_cpu_0_stb_o;
assign wb_cpu_0_wb_master_to_wb_cpu_bench_0_wb_slavewe = wb_cpu_0_we_o;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
wb_slave_mem_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.DATA_COUNT (8),
.BASE_ADDRESS (3840))
wb_cpu_bench_0(
.mem_data_i (wb_cpu_bench_0_mem_data_i),
.mem_slave_rdy (wb_cpu_bench_0_mem_slave_rdy),
.mem_address_o (wb_cpu_bench_0_mem_address_o),
.mem_data_o (wb_cpu_bench_0_mem_data_o),
.mem_master_rdy (wb_cpu_bench_0_mem_master_rdy),
.mem_we_o (wb_cpu_bench_0_mem_we_o),
.adr_i (wb_cpu_bench_0_adr_i),
.cyc_i (wb_cpu_bench_0_cyc_i),
.dat_i (wb_cpu_bench_0_dat_i),
.stb_i (wb_cpu_bench_0_stb_i),
.we_i (wb_cpu_bench_0_we_i),
.ack_o (wb_cpu_bench_0_ack_o),
.dat_o (wb_cpu_bench_0_dat_o),
.err_o (wb_cpu_bench_0_err_o),
.clk_i (wb_cpu_bench_0_clk_i),
.rst_i (wb_cpu_bench_0_rst_i));
wb_master #(
.ADDR_WIDTH (16),
.DATA_WIDTH (32),
.BASE_ADDRESS (3840),
.RANGE (512))
wb_cpu_0(
.mem_address_in (wb_cpu_0_mem_address_in),
.mem_data_in (wb_cpu_0_mem_data_in),
.mem_master_rdy (wb_cpu_0_mem_master_rdy),
.mem_we_in (wb_cpu_0_mem_we_in),
.mem_data_out (wb_cpu_0_mem_data_out),
.mem_slave_rdy (wb_cpu_0_mem_slave_rdy),
.ack_i (wb_cpu_0_ack_i),
.dat_i (wb_cpu_0_dat_i),
.err_i (wb_cpu_0_err_i),
.adr_o (wb_cpu_0_adr_o),
.cyc_o (wb_cpu_0_cyc_o),
.dat_o (wb_cpu_0_dat_o),
.stb_o (wb_cpu_0_stb_o),
.we_o (wb_cpu_0_we_o),
.clk_i (wb_cpu_0_clk_i),
.rst_i (wb_cpu_0_rst_i));
endmodule | 0 |
142,154 | data/full_repos/permissive/97170571/tut.fi/cpu.logic/memory_controller/1.0/memory_controller.v | 97,170,571 | memory_controller.v | v | 163 | 119 | [] | [] | [] | [(13, 162)] | null | data/verilator_xmls/fa65ea1f-0dc1-41bb-9106-a1a676847a50.xml | null | 313,131 | module | module memory_controller #(
parameter DATA_WIDTH = 16,
parameter AUB = 8,
parameter ADDR_WIDTH = 16,
parameter MEMORY_SIZE = 256,
parameter PERIPHERAL_BASE = 128,
parameter REGISTER_COUNT = 8,
parameter DATA_BYTES = DATA_WIDTH/AUB,
parameter CONTROL_RANGE = 'h40
) (
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] address_i,
input mem_active_i,
input [DATA_WIDTH-1:0] register_value_i,
input we_i,
output [DATA_WIDTH-1:0] load_value_o,
output mem_rdy_o,
output mem_read_rdy_o,
input [DATA_WIDTH-1:0] local_read_data,
output [ADDR_WIDTH-1:0] local_address_o,
output [DATA_WIDTH-1:0] local_write_data,
output local_write_o,
input [DATA_WIDTH-1:0] mem_data_i,
input mem_slave_rdy,
output reg [ADDR_WIDTH-1:0] mem_address_o,
output reg [DATA_WIDTH-1:0] mem_data_o,
output reg mem_master_rdy,
output reg mem_we_o
);
wire local_mem_active = mem_active_i && address_i < PERIPHERAL_BASE;
wire periph_mem_active = mem_active_i && address_i >= PERIPHERAL_BASE;
reg periph_mem_rdy;
reg local_mem_rdy;
reg [DATA_WIDTH-1:0] periph_load_value;
reg read_operation;
assign load_value_o = periph_mem_active ? periph_load_value : local_read_data;
assign local_write_data = register_value_i;
assign local_write_o = we_i;
assign local_address_o = address_i;
assign mem_rdy_o = local_mem_rdy | periph_mem_rdy;
assign mem_read_rdy_o = mem_rdy_o && read_operation;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
local_mem_rdy <= 0;
read_operation <= 0;
end
else begin
if (local_mem_active) begin
local_mem_rdy <= 1;
end
else begin
local_mem_rdy <= 0;
end
if (local_mem_active || mem_active_i) begin
read_operation <= ~we_i;
end
else begin
read_operation <= 0;
end
end
end
reg [1:0] state;
parameter [1:0]
S_WAIT = 2'd0,
S_WAIT_WRITE = 2'd1,
S_WAIT_READ = 2'd2,
S_DEASSERT = 2'd3;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
state <= S_WAIT;
periph_mem_rdy <= 0;
periph_load_value <= 0;
mem_address_o <= 0;
mem_data_o <= 0;
mem_master_rdy <= 0;
mem_we_o <= 0;
end
else begin
case(state)
S_WAIT: begin
if (periph_mem_active == 1) begin
if (we_i == 1) begin
mem_we_o <= 1;
mem_data_o <= register_value_i;
state <= S_WAIT_WRITE;
end
else begin
state <= S_WAIT_READ;
end
mem_master_rdy <= 1;
mem_address_o <= address_i - PERIPHERAL_BASE;
end
end
S_WAIT_WRITE: begin
mem_master_rdy <= 0;
if (mem_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_mem_rdy <= 1;
mem_we_o <= 0;
end
end
S_WAIT_READ: begin
mem_master_rdy <= 0;
if (mem_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_load_value <= mem_data_i;
periph_mem_rdy <= 1;
end
end
S_DEASSERT: begin
state <= S_WAIT;
periph_mem_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule | module memory_controller #(
parameter DATA_WIDTH = 16,
parameter AUB = 8,
parameter ADDR_WIDTH = 16,
parameter MEMORY_SIZE = 256,
parameter PERIPHERAL_BASE = 128,
parameter REGISTER_COUNT = 8,
parameter DATA_BYTES = DATA_WIDTH/AUB,
parameter CONTROL_RANGE = 'h40
) (
input clk_i,
input rst_i,
input [ADDR_WIDTH-1:0] address_i,
input mem_active_i,
input [DATA_WIDTH-1:0] register_value_i,
input we_i,
output [DATA_WIDTH-1:0] load_value_o,
output mem_rdy_o,
output mem_read_rdy_o,
input [DATA_WIDTH-1:0] local_read_data,
output [ADDR_WIDTH-1:0] local_address_o,
output [DATA_WIDTH-1:0] local_write_data,
output local_write_o,
input [DATA_WIDTH-1:0] mem_data_i,
input mem_slave_rdy,
output reg [ADDR_WIDTH-1:0] mem_address_o,
output reg [DATA_WIDTH-1:0] mem_data_o,
output reg mem_master_rdy,
output reg mem_we_o
); |
wire local_mem_active = mem_active_i && address_i < PERIPHERAL_BASE;
wire periph_mem_active = mem_active_i && address_i >= PERIPHERAL_BASE;
reg periph_mem_rdy;
reg local_mem_rdy;
reg [DATA_WIDTH-1:0] periph_load_value;
reg read_operation;
assign load_value_o = periph_mem_active ? periph_load_value : local_read_data;
assign local_write_data = register_value_i;
assign local_write_o = we_i;
assign local_address_o = address_i;
assign mem_rdy_o = local_mem_rdy | periph_mem_rdy;
assign mem_read_rdy_o = mem_rdy_o && read_operation;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
local_mem_rdy <= 0;
read_operation <= 0;
end
else begin
if (local_mem_active) begin
local_mem_rdy <= 1;
end
else begin
local_mem_rdy <= 0;
end
if (local_mem_active || mem_active_i) begin
read_operation <= ~we_i;
end
else begin
read_operation <= 0;
end
end
end
reg [1:0] state;
parameter [1:0]
S_WAIT = 2'd0,
S_WAIT_WRITE = 2'd1,
S_WAIT_READ = 2'd2,
S_DEASSERT = 2'd3;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
state <= S_WAIT;
periph_mem_rdy <= 0;
periph_load_value <= 0;
mem_address_o <= 0;
mem_data_o <= 0;
mem_master_rdy <= 0;
mem_we_o <= 0;
end
else begin
case(state)
S_WAIT: begin
if (periph_mem_active == 1) begin
if (we_i == 1) begin
mem_we_o <= 1;
mem_data_o <= register_value_i;
state <= S_WAIT_WRITE;
end
else begin
state <= S_WAIT_READ;
end
mem_master_rdy <= 1;
mem_address_o <= address_i - PERIPHERAL_BASE;
end
end
S_WAIT_WRITE: begin
mem_master_rdy <= 0;
if (mem_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_mem_rdy <= 1;
mem_we_o <= 0;
end
end
S_WAIT_READ: begin
mem_master_rdy <= 0;
if (mem_slave_rdy == 1) begin
state <= S_DEASSERT;
periph_load_value <= mem_data_i;
periph_mem_rdy <= 1;
end
end
S_DEASSERT: begin
state <= S_WAIT;
periph_mem_rdy <= 0;
end
default: begin
$display("ERROR: Unkown state: %d", state);
end
endcase
end
end
endmodule | 0 |
142,155 | data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v | 97,170,571 | core_example_0.v | v | 328 | 125 | [] | [] | [] | [(13, 327)] | null | null | 1: b"%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v:227: Cannot find file containing module: 'alu'\n alu #(\n ^~~\n ... Looked in:\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/alu\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/alu.v\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/alu.sv\n alu\n alu.v\n alu.sv\n obj_dir/alu\n obj_dir/alu.v\n obj_dir/alu.sv\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v:238: Cannot find file containing module: 'clock'\n clock #(\n ^~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v:249: Cannot find file containing module: 'instruction_decoder'\n instruction_decoder #(\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v:274: Cannot find file containing module: 'memory_controller'\n memory_controller #(\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/core_example_0.v:306: Cannot find file containing module: 'register_bank'\n register_bank #(\n ^~~~~~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 313,136 | module | module core_example_0 #(
parameter DATA_WIDTH = 16,
parameter REGISTER_ID_WIDTH = 3,
parameter ADDR_WIDTH = 10,
parameter SUPPORTED_MEMORY = 1024,
parameter REGISTER_COUNT = 8,
parameter PERIPHERAL_BASE = 256,
parameter OP_CODE_WIDTH = 4,
parameter INSTRUCTION_WIDTH = 28,
parameter INSTRUCTION_ADDRESS_WIDTH = 8
) (
input [27:0] instruction_feed,
output [7:0] iaddr_o,
input [15:0] local_read_data,
output [9:0] local_address_o,
output [15:0] local_write_data,
output local_write_o,
input [15:0] mem_data_i,
input mem_slave_rdy,
output [9:0] mem_address_o,
output [15:0] mem_data_o,
output mem_master_rdy,
output mem_we_o,
input clk_i,
input rst_i
);
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemaddress;
wire memory_controller_cpu_system_to_alu_cpu_systemalu_active;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemalu_operation;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_result;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_status;
wire [3:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1;
wire [3:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemload_value;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_active;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_we;
wire memory_controller_cpu_system_to_alu_cpu_systemregister_active;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_input;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_1;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_2;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
wire [9:0] memory_controller_peripheral_access_to_peripheral_accessaddress;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_ms;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_sm;
wire memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
wire memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
wire memory_controller_peripheral_access_to_peripheral_accesswe;
wire [7:0] instruction_decoder_instruction_feed_to_instructionsaddress;
wire [27:0] instruction_decoder_instruction_feed_to_instructionsread_data;
wire [9:0] memory_controller_local_data_to_local_dataaddress;
wire [15:0] memory_controller_local_data_to_local_dataread_data;
wire memory_controller_local_data_to_local_datawrite;
wire [15:0] memory_controller_local_data_to_local_datawrite_data;
wire clock_clk_i_to_clk_i;
wire clock_rst_i_to_rst_i;
wire [2:0] alu_alu_op_i;
wire [15:0] alu_alu_result_o;
wire [15:0] alu_alu_status_o;
wire [15:0] alu_register_value_i1;
wire [15:0] alu_register_value_i2;
wire clock_clk_i;
wire clock_clk_o;
wire clock_rst_i;
wire clock_rst_o;
wire instruction_decoder_alu_active_o;
wire [2:0] instruction_decoder_alu_op_o;
wire [15:0] instruction_decoder_alu_status_i;
wire [3:0] instruction_decoder_choose_reg1_o;
wire [3:0] instruction_decoder_choose_reg2_o;
wire instruction_decoder_clk_i;
wire [7:0] instruction_decoder_iaddr_o;
wire [27:0] instruction_decoder_instruction_feed;
wire [15:0] instruction_decoder_load_value_i;
wire instruction_decoder_mem_active_o;
wire instruction_decoder_mem_rdy_i;
wire instruction_decoder_register_active_o;
wire [15:0] instruction_decoder_register_value_o;
wire instruction_decoder_rst_i;
wire instruction_decoder_we_o;
wire [9:0] memory_controller_address_i;
wire memory_controller_clk_i;
wire [15:0] memory_controller_load_value_o;
wire [9:0] memory_controller_local_address_o;
wire [15:0] memory_controller_local_read_data;
wire [15:0] memory_controller_local_write_data;
wire memory_controller_local_write_o;
wire memory_controller_mem_active_i;
wire [9:0] memory_controller_mem_address_o;
wire [15:0] memory_controller_mem_data_i;
wire [15:0] memory_controller_mem_data_o;
wire memory_controller_mem_master_rdy;
wire memory_controller_mem_rdy_o;
wire memory_controller_mem_read_rdy_o;
wire memory_controller_mem_slave_rdy;
wire memory_controller_mem_we_o;
wire [15:0] memory_controller_register_value_i;
wire memory_controller_rst_i;
wire memory_controller_we_i;
wire register_bank_alu_active_i;
wire [15:0] register_bank_alu_result_i;
wire [2:0] register_bank_choose_register_i1;
wire [2:0] register_bank_choose_register_i2;
wire register_bank_clk_i;
wire [15:0] register_bank_load_value_i;
wire register_bank_mem_read_rdy_i;
wire register_bank_register_active_i;
wire [15:0] register_bank_register_input;
wire [15:0] register_bank_register_output1;
wire [15:0] register_bank_register_output2;
wire register_bank_rst_i;
assign clock_clk_i_to_clk_i = clk_i;
assign iaddr_o[7:0] = instruction_decoder_instruction_feed_to_instructionsaddress[7:0];
assign instruction_decoder_instruction_feed_to_instructionsread_data[27:0] = instruction_feed[27:0];
assign local_address_o[9:0] = memory_controller_local_data_to_local_dataaddress[9:0];
assign memory_controller_local_data_to_local_dataread_data[15:0] = local_read_data[15:0];
assign local_write_data[15:0] = memory_controller_local_data_to_local_datawrite_data[15:0];
assign local_write_o = memory_controller_local_data_to_local_datawrite;
assign mem_address_o[9:0] = memory_controller_peripheral_access_to_peripheral_accessaddress[9:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0] = mem_data_i[15:0];
assign mem_data_o[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0];
assign mem_master_rdy = memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
assign memory_controller_peripheral_access_to_peripheral_accessslave_rdy = mem_slave_rdy;
assign mem_we_o = memory_controller_peripheral_access_to_peripheral_accesswe;
assign clock_rst_i_to_rst_i = rst_i;
assign alu_alu_op_i[2:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0] = alu_alu_result_o[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0] = alu_alu_status_o[15:0];
assign alu_register_value_i1[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign alu_register_value_i2[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0];
assign clock_clk_i = clock_clk_i_to_clk_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk = clock_clk_o;
assign clock_rst_i = clock_rst_i_to_rst_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst = clock_rst_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_active = instruction_decoder_alu_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0] = instruction_decoder_alu_op_o[2:0];
assign instruction_decoder_alu_status_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[3:0] = instruction_decoder_choose_reg1_o[3:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[3:0] = instruction_decoder_choose_reg2_o[3:0];
assign instruction_decoder_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign instruction_decoder_instruction_feed_to_instructionsaddress[7:0] = instruction_decoder_iaddr_o[7:0];
assign instruction_decoder_instruction_feed[27:0] = instruction_decoder_instruction_feed_to_instructionsread_data[27:0];
assign instruction_decoder_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_active = instruction_decoder_mem_active_o;
assign instruction_decoder_mem_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_active = instruction_decoder_register_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0] = instruction_decoder_register_value_o[15:0];
assign instruction_decoder_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_we = instruction_decoder_we_o;
assign memory_controller_address_i[9:0] = memory_controller_cpu_system_to_alu_cpu_systemaddress[9:0];
assign memory_controller_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0] = memory_controller_load_value_o[15:0];
assign memory_controller_local_data_to_local_dataaddress[9:0] = memory_controller_local_address_o[9:0];
assign memory_controller_local_read_data[15:0] = memory_controller_local_data_to_local_dataread_data[15:0];
assign memory_controller_local_data_to_local_datawrite_data[15:0] = memory_controller_local_write_data[15:0];
assign memory_controller_local_data_to_local_datawrite = memory_controller_local_write_o;
assign memory_controller_mem_active_i = memory_controller_cpu_system_to_alu_cpu_systemmem_active;
assign memory_controller_peripheral_access_to_peripheral_accessaddress[9:0] = memory_controller_mem_address_o[9:0];
assign memory_controller_mem_data_i[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0] = memory_controller_mem_data_o[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessmaster_rdy = memory_controller_mem_master_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_rdy = memory_controller_mem_rdy_o;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy = memory_controller_mem_read_rdy_o;
assign memory_controller_mem_slave_rdy = memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
assign memory_controller_peripheral_access_to_peripheral_accesswe = memory_controller_mem_we_o;
assign memory_controller_register_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign memory_controller_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_we_i = memory_controller_cpu_system_to_alu_cpu_systemmem_we;
assign register_bank_alu_active_i = memory_controller_cpu_system_to_alu_cpu_systemalu_active;
assign register_bank_alu_result_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0];
assign register_bank_choose_register_i1[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0];
assign register_bank_choose_register_i2[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0];
assign register_bank_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign register_bank_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign register_bank_mem_read_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
assign register_bank_register_active_i = memory_controller_cpu_system_to_alu_cpu_systemregister_active;
assign register_bank_register_input[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0] = register_bank_register_output1[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemaddress[15:0] = register_bank_register_output2[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0] = register_bank_register_output2[15:0];
assign register_bank_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
alu #(
.DATA_WIDTH (16))
alu(
.alu_op_i (alu_alu_op_i),
.register_value_i1 (alu_register_value_i1),
.register_value_i2 (alu_register_value_i2),
.alu_result_o (alu_alu_result_o),
.alu_status_o (alu_alu_status_o));
clock #(
.SCALE (2))
clock(
.clk_o (clock_clk_o),
.rst_o (clock_rst_o),
.clk_i (clock_clk_i),
.rst_i (clock_rst_i));
instruction_decoder #(
.REGISTER_ID_WIDTH (4),
.DATA_WIDTH (16),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_decoder(
.clk_i (instruction_decoder_clk_i),
.rst_i (instruction_decoder_rst_i),
.alu_status_i (instruction_decoder_alu_status_i),
.load_value_i (instruction_decoder_load_value_i),
.mem_rdy_i (instruction_decoder_mem_rdy_i),
.alu_active_o (instruction_decoder_alu_active_o),
.alu_op_o (instruction_decoder_alu_op_o),
.choose_reg1_o (instruction_decoder_choose_reg1_o),
.choose_reg2_o (instruction_decoder_choose_reg2_o),
.mem_active_o (instruction_decoder_mem_active_o),
.register_active_o (instruction_decoder_register_active_o),
.register_value_o (instruction_decoder_register_value_o),
.we_o (instruction_decoder_we_o),
.instruction_feed (instruction_decoder_instruction_feed),
.iaddr_o (instruction_decoder_iaddr_o));
memory_controller #(
.DATA_WIDTH (16),
.ADDR_WIDTH (10),
.MEMORY_SIZE (1024),
.PERIPHERAL_BASE (256),
.REGISTER_COUNT (8))
memory_controller(
.clk_i (memory_controller_clk_i),
.rst_i (memory_controller_rst_i),
.address_i (memory_controller_address_i),
.mem_active_i (memory_controller_mem_active_i),
.register_value_i (memory_controller_register_value_i),
.we_i (memory_controller_we_i),
.load_value_o (memory_controller_load_value_o),
.mem_rdy_o (memory_controller_mem_rdy_o),
.mem_read_rdy_o (memory_controller_mem_read_rdy_o),
.local_read_data (memory_controller_local_read_data),
.local_address_o (memory_controller_local_address_o),
.local_write_data (memory_controller_local_write_data),
.local_write_o (memory_controller_local_write_o),
.mem_data_i (memory_controller_mem_data_i),
.mem_slave_rdy (memory_controller_mem_slave_rdy),
.mem_address_o (memory_controller_mem_address_o),
.mem_data_o (memory_controller_mem_data_o),
.mem_master_rdy (memory_controller_mem_master_rdy),
.mem_we_o (memory_controller_mem_we_o));
register_bank #(
.DATA_WIDTH (16),
.REGISTER_ID_WIDTH (3),
.REGISTER_COUNT (8))
register_bank(
.clk_i (register_bank_clk_i),
.rst_i (register_bank_rst_i),
.alu_active_i (register_bank_alu_active_i),
.alu_result_i (register_bank_alu_result_i),
.choose_register_i1 (register_bank_choose_register_i1),
.choose_register_i2 (register_bank_choose_register_i2),
.load_value_i (register_bank_load_value_i),
.mem_read_rdy_i (register_bank_mem_read_rdy_i),
.register_active_i (register_bank_register_active_i),
.register_input (register_bank_register_input),
.register_output1 (register_bank_register_output1),
.register_output2 (register_bank_register_output2));
endmodule | module core_example_0 #(
parameter DATA_WIDTH = 16,
parameter REGISTER_ID_WIDTH = 3,
parameter ADDR_WIDTH = 10,
parameter SUPPORTED_MEMORY = 1024,
parameter REGISTER_COUNT = 8,
parameter PERIPHERAL_BASE = 256,
parameter OP_CODE_WIDTH = 4,
parameter INSTRUCTION_WIDTH = 28,
parameter INSTRUCTION_ADDRESS_WIDTH = 8
) (
input [27:0] instruction_feed,
output [7:0] iaddr_o,
input [15:0] local_read_data,
output [9:0] local_address_o,
output [15:0] local_write_data,
output local_write_o,
input [15:0] mem_data_i,
input mem_slave_rdy,
output [9:0] mem_address_o,
output [15:0] mem_data_o,
output mem_master_rdy,
output mem_we_o,
input clk_i,
input rst_i
); |
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemaddress;
wire memory_controller_cpu_system_to_alu_cpu_systemalu_active;
wire [2:0] memory_controller_cpu_system_to_alu_cpu_systemalu_operation;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_result;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemalu_status;
wire [3:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1;
wire [3:0] memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemload_value;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_active;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
wire memory_controller_cpu_system_to_alu_cpu_systemmem_we;
wire memory_controller_cpu_system_to_alu_cpu_systemregister_active;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_input;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_1;
wire [15:0] memory_controller_cpu_system_to_alu_cpu_systemregister_output_2;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
wire clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
wire [9:0] memory_controller_peripheral_access_to_peripheral_accessaddress;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_ms;
wire [15:0] memory_controller_peripheral_access_to_peripheral_accessdata_sm;
wire memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
wire memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
wire memory_controller_peripheral_access_to_peripheral_accesswe;
wire [7:0] instruction_decoder_instruction_feed_to_instructionsaddress;
wire [27:0] instruction_decoder_instruction_feed_to_instructionsread_data;
wire [9:0] memory_controller_local_data_to_local_dataaddress;
wire [15:0] memory_controller_local_data_to_local_dataread_data;
wire memory_controller_local_data_to_local_datawrite;
wire [15:0] memory_controller_local_data_to_local_datawrite_data;
wire clock_clk_i_to_clk_i;
wire clock_rst_i_to_rst_i;
wire [2:0] alu_alu_op_i;
wire [15:0] alu_alu_result_o;
wire [15:0] alu_alu_status_o;
wire [15:0] alu_register_value_i1;
wire [15:0] alu_register_value_i2;
wire clock_clk_i;
wire clock_clk_o;
wire clock_rst_i;
wire clock_rst_o;
wire instruction_decoder_alu_active_o;
wire [2:0] instruction_decoder_alu_op_o;
wire [15:0] instruction_decoder_alu_status_i;
wire [3:0] instruction_decoder_choose_reg1_o;
wire [3:0] instruction_decoder_choose_reg2_o;
wire instruction_decoder_clk_i;
wire [7:0] instruction_decoder_iaddr_o;
wire [27:0] instruction_decoder_instruction_feed;
wire [15:0] instruction_decoder_load_value_i;
wire instruction_decoder_mem_active_o;
wire instruction_decoder_mem_rdy_i;
wire instruction_decoder_register_active_o;
wire [15:0] instruction_decoder_register_value_o;
wire instruction_decoder_rst_i;
wire instruction_decoder_we_o;
wire [9:0] memory_controller_address_i;
wire memory_controller_clk_i;
wire [15:0] memory_controller_load_value_o;
wire [9:0] memory_controller_local_address_o;
wire [15:0] memory_controller_local_read_data;
wire [15:0] memory_controller_local_write_data;
wire memory_controller_local_write_o;
wire memory_controller_mem_active_i;
wire [9:0] memory_controller_mem_address_o;
wire [15:0] memory_controller_mem_data_i;
wire [15:0] memory_controller_mem_data_o;
wire memory_controller_mem_master_rdy;
wire memory_controller_mem_rdy_o;
wire memory_controller_mem_read_rdy_o;
wire memory_controller_mem_slave_rdy;
wire memory_controller_mem_we_o;
wire [15:0] memory_controller_register_value_i;
wire memory_controller_rst_i;
wire memory_controller_we_i;
wire register_bank_alu_active_i;
wire [15:0] register_bank_alu_result_i;
wire [2:0] register_bank_choose_register_i1;
wire [2:0] register_bank_choose_register_i2;
wire register_bank_clk_i;
wire [15:0] register_bank_load_value_i;
wire register_bank_mem_read_rdy_i;
wire register_bank_register_active_i;
wire [15:0] register_bank_register_input;
wire [15:0] register_bank_register_output1;
wire [15:0] register_bank_register_output2;
wire register_bank_rst_i;
assign clock_clk_i_to_clk_i = clk_i;
assign iaddr_o[7:0] = instruction_decoder_instruction_feed_to_instructionsaddress[7:0];
assign instruction_decoder_instruction_feed_to_instructionsread_data[27:0] = instruction_feed[27:0];
assign local_address_o[9:0] = memory_controller_local_data_to_local_dataaddress[9:0];
assign memory_controller_local_data_to_local_dataread_data[15:0] = local_read_data[15:0];
assign local_write_data[15:0] = memory_controller_local_data_to_local_datawrite_data[15:0];
assign local_write_o = memory_controller_local_data_to_local_datawrite;
assign mem_address_o[9:0] = memory_controller_peripheral_access_to_peripheral_accessaddress[9:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0] = mem_data_i[15:0];
assign mem_data_o[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0];
assign mem_master_rdy = memory_controller_peripheral_access_to_peripheral_accessmaster_rdy;
assign memory_controller_peripheral_access_to_peripheral_accessslave_rdy = mem_slave_rdy;
assign mem_we_o = memory_controller_peripheral_access_to_peripheral_accesswe;
assign clock_rst_i_to_rst_i = rst_i;
assign alu_alu_op_i[2:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0] = alu_alu_result_o[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0] = alu_alu_status_o[15:0];
assign alu_register_value_i1[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign alu_register_value_i2[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0];
assign clock_clk_i = clock_clk_i_to_clk_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk = clock_clk_o;
assign clock_rst_i = clock_rst_i_to_rst_i;
assign clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst = clock_rst_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_active = instruction_decoder_alu_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemalu_operation[2:0] = instruction_decoder_alu_op_o[2:0];
assign instruction_decoder_alu_status_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_status[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[3:0] = instruction_decoder_choose_reg1_o[3:0];
assign memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[3:0] = instruction_decoder_choose_reg2_o[3:0];
assign instruction_decoder_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign instruction_decoder_instruction_feed_to_instructionsaddress[7:0] = instruction_decoder_iaddr_o[7:0];
assign instruction_decoder_instruction_feed[27:0] = instruction_decoder_instruction_feed_to_instructionsread_data[27:0];
assign instruction_decoder_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemmem_active = instruction_decoder_mem_active_o;
assign instruction_decoder_mem_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_active = instruction_decoder_register_active_o;
assign memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0] = instruction_decoder_register_value_o[15:0];
assign instruction_decoder_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_we = instruction_decoder_we_o;
assign memory_controller_address_i[9:0] = memory_controller_cpu_system_to_alu_cpu_systemaddress[9:0];
assign memory_controller_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0] = memory_controller_load_value_o[15:0];
assign memory_controller_local_data_to_local_dataaddress[9:0] = memory_controller_local_address_o[9:0];
assign memory_controller_local_read_data[15:0] = memory_controller_local_data_to_local_dataread_data[15:0];
assign memory_controller_local_data_to_local_datawrite_data[15:0] = memory_controller_local_write_data[15:0];
assign memory_controller_local_data_to_local_datawrite = memory_controller_local_write_o;
assign memory_controller_mem_active_i = memory_controller_cpu_system_to_alu_cpu_systemmem_active;
assign memory_controller_peripheral_access_to_peripheral_accessaddress[9:0] = memory_controller_mem_address_o[9:0];
assign memory_controller_mem_data_i[15:0] = memory_controller_peripheral_access_to_peripheral_accessdata_sm[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessdata_ms[15:0] = memory_controller_mem_data_o[15:0];
assign memory_controller_peripheral_access_to_peripheral_accessmaster_rdy = memory_controller_mem_master_rdy;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_rdy = memory_controller_mem_rdy_o;
assign memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy = memory_controller_mem_read_rdy_o;
assign memory_controller_mem_slave_rdy = memory_controller_peripheral_access_to_peripheral_accessslave_rdy;
assign memory_controller_peripheral_access_to_peripheral_accesswe = memory_controller_mem_we_o;
assign memory_controller_register_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0];
assign memory_controller_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
assign memory_controller_we_i = memory_controller_cpu_system_to_alu_cpu_systemmem_we;
assign register_bank_alu_active_i = memory_controller_cpu_system_to_alu_cpu_systemalu_active;
assign register_bank_alu_result_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemalu_result[15:0];
assign register_bank_choose_register_i1[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_1[2:0];
assign register_bank_choose_register_i2[2:0] = memory_controller_cpu_system_to_alu_cpu_systemchoose_register_2[2:0];
assign register_bank_clk_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkclk;
assign register_bank_load_value_i[15:0] = memory_controller_cpu_system_to_alu_cpu_systemload_value[15:0];
assign register_bank_mem_read_rdy_i = memory_controller_cpu_system_to_alu_cpu_systemmem_read_rdy;
assign register_bank_register_active_i = memory_controller_cpu_system_to_alu_cpu_systemregister_active;
assign register_bank_register_input[15:0] = memory_controller_cpu_system_to_alu_cpu_systemregister_input[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_1[15:0] = register_bank_register_output1[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemaddress[15:0] = register_bank_register_output2[15:0];
assign memory_controller_cpu_system_to_alu_cpu_systemregister_output_2[15:0] = register_bank_register_output2[15:0];
assign register_bank_rst_i = clock_cpu_clk_source_to_register_bank_cpu_clk_sinkrst;
alu #(
.DATA_WIDTH (16))
alu(
.alu_op_i (alu_alu_op_i),
.register_value_i1 (alu_register_value_i1),
.register_value_i2 (alu_register_value_i2),
.alu_result_o (alu_alu_result_o),
.alu_status_o (alu_alu_status_o));
clock #(
.SCALE (2))
clock(
.clk_o (clock_clk_o),
.rst_o (clock_rst_o),
.clk_i (clock_clk_i),
.rst_i (clock_rst_i));
instruction_decoder #(
.REGISTER_ID_WIDTH (4),
.DATA_WIDTH (16),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_decoder(
.clk_i (instruction_decoder_clk_i),
.rst_i (instruction_decoder_rst_i),
.alu_status_i (instruction_decoder_alu_status_i),
.load_value_i (instruction_decoder_load_value_i),
.mem_rdy_i (instruction_decoder_mem_rdy_i),
.alu_active_o (instruction_decoder_alu_active_o),
.alu_op_o (instruction_decoder_alu_op_o),
.choose_reg1_o (instruction_decoder_choose_reg1_o),
.choose_reg2_o (instruction_decoder_choose_reg2_o),
.mem_active_o (instruction_decoder_mem_active_o),
.register_active_o (instruction_decoder_register_active_o),
.register_value_o (instruction_decoder_register_value_o),
.we_o (instruction_decoder_we_o),
.instruction_feed (instruction_decoder_instruction_feed),
.iaddr_o (instruction_decoder_iaddr_o));
memory_controller #(
.DATA_WIDTH (16),
.ADDR_WIDTH (10),
.MEMORY_SIZE (1024),
.PERIPHERAL_BASE (256),
.REGISTER_COUNT (8))
memory_controller(
.clk_i (memory_controller_clk_i),
.rst_i (memory_controller_rst_i),
.address_i (memory_controller_address_i),
.mem_active_i (memory_controller_mem_active_i),
.register_value_i (memory_controller_register_value_i),
.we_i (memory_controller_we_i),
.load_value_o (memory_controller_load_value_o),
.mem_rdy_o (memory_controller_mem_rdy_o),
.mem_read_rdy_o (memory_controller_mem_read_rdy_o),
.local_read_data (memory_controller_local_read_data),
.local_address_o (memory_controller_local_address_o),
.local_write_data (memory_controller_local_write_data),
.local_write_o (memory_controller_local_write_o),
.mem_data_i (memory_controller_mem_data_i),
.mem_slave_rdy (memory_controller_mem_slave_rdy),
.mem_address_o (memory_controller_mem_address_o),
.mem_data_o (memory_controller_mem_data_o),
.mem_master_rdy (memory_controller_mem_master_rdy),
.mem_we_o (memory_controller_mem_we_o));
register_bank #(
.DATA_WIDTH (16),
.REGISTER_ID_WIDTH (3),
.REGISTER_COUNT (8))
register_bank(
.clk_i (register_bank_clk_i),
.rst_i (register_bank_rst_i),
.alu_active_i (register_bank_alu_active_i),
.alu_result_i (register_bank_alu_result_i),
.choose_register_i1 (register_bank_choose_register_i1),
.choose_register_i2 (register_bank_choose_register_i2),
.load_value_i (register_bank_load_value_i),
.mem_read_rdy_i (register_bank_mem_read_rdy_i),
.register_active_i (register_bank_register_active_i),
.register_input (register_bank_register_input),
.register_output1 (register_bank_register_output1),
.register_output2 (register_bank_register_output2));
endmodule | 0 |
142,156 | data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v | 97,170,571 | test_setup.v | v | 187 | 128 | [] | [] | [] | [(13, 186)] | null | null | 1: b"%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v:121: Cannot find file containing module: 'clock_generator'\n clock_generator clock_generator_0(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.v\n data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.sv\n clock_generator\n clock_generator.v\n clock_generator.sv\n obj_dir/clock_generator\n obj_dir/clock_generator.v\n obj_dir/clock_generator.sv\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v:127: Cannot find file containing module: 'cpu_example_0'\n cpu_example_0 cpu_example_0(\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v:146: Cannot find file containing module: 'data_memory'\n data_memory #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v:162: Cannot find file containing module: 'instruction_memory'\n instruction_memory #(\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.structure.test/cpu_example.setup/1.0/test_setup.v:174: Cannot find file containing module: 'spi_slave'\n spi_slave #(\n ^~~~~~~~~\n%Error: Exiting due to 5 error(s)\n" | 313,139 | module | module test_setup();
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifSS;
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
wire [7:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress;
wire [27:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data;
wire [9:0] cpu_example_0_local_data_to_data_memory_0_slaveaddress;
wire [15:0] cpu_example_0_local_data_to_data_memory_0_slaveread_data;
wire cpu_example_0_local_data_to_data_memory_0_slavewrite;
wire [15:0] cpu_example_0_local_data_to_data_memory_0_slavewrite_data;
wire spi_slave_0_rst_in_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire clock_generator_0_rst_o_to_cpu_example_0_rst_i;
wire clock_generator_0_clk_o_to_cpu_example_0_clk_i;
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_rst_o_to_data_memory_0_rst_i;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire cpu_example_0_clk_i;
wire cpu_example_0_clk_out;
wire cpu_example_0_data_in;
wire cpu_example_0_data_out;
wire [7:0] cpu_example_0_iaddr_o;
wire [27:0] cpu_example_0_instruction_feed;
wire [9:0] cpu_example_0_local_address_o;
wire [15:0] cpu_example_0_local_read_data;
wire [15:0] cpu_example_0_local_write_data;
wire cpu_example_0_local_write_o;
wire cpu_example_0_rst_i;
wire cpu_example_0_slave_select_out;
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [15:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [15:0] data_memory_0_write_data;
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_o;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
wire spi_slave_0_clk_in;
wire spi_slave_0_data_in;
wire spi_slave_0_data_out;
wire spi_slave_0_rst_in;
wire spi_slave_0_slave_select_in;
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_cpu_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_cpu_example_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_data_memory_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
assign spi_slave_0_rst_in_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign cpu_example_0_clk_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
assign cpu_example_0_clk_i = clock_generator_0_clk_o_to_cpu_example_0_clk_i;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK = cpu_example_0_clk_out;
assign cpu_example_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI = cpu_example_0_data_out;
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0] = cpu_example_0_iaddr_o[7:0];
assign cpu_example_0_instruction_feed[27:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0];
assign cpu_example_0_local_data_to_data_memory_0_slaveaddress[9:0] = cpu_example_0_local_address_o[9:0];
assign cpu_example_0_local_read_data[15:0] = cpu_example_0_local_data_to_data_memory_0_slaveread_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite_data[15:0] = cpu_example_0_local_write_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite = cpu_example_0_local_write_o;
assign cpu_example_0_rst_i = clock_generator_0_rst_o_to_cpu_example_0_rst_i;
assign cpu_example_0_rst_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifSS = cpu_example_0_slave_select_out;
assign data_memory_0_adr_i[8:0] = cpu_example_0_local_data_to_data_memory_0_slaveaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign cpu_example_0_local_data_to_data_memory_0_slaveread_data[15:0] = data_memory_0_read_data[15:0];
assign data_memory_0_rst_i = clock_generator_0_rst_o_to_data_memory_0_rst_i;
assign data_memory_0_write = cpu_example_0_local_data_to_data_memory_0_slavewrite;
assign data_memory_0_write_data[15:0] = cpu_example_0_local_data_to_data_memory_0_slavewrite_data[15:0];
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_o[7:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0];
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
assign spi_slave_0_clk_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK;
assign spi_slave_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO = spi_slave_0_data_out;
assign spi_slave_0_rst_in = spi_slave_0_rst_in_to_clock_generator_0_rst_o;
assign spi_slave_0_slave_select_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifSS;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
cpu_example_0 cpu_example_0(
.instruction_feed (cpu_example_0_instruction_feed),
.iaddr_o (cpu_example_0_iaddr_o),
.local_read_data (cpu_example_0_local_read_data),
.local_address_o (cpu_example_0_local_address_o),
.local_write_data (cpu_example_0_local_write_data),
.local_write_o (cpu_example_0_local_write_o),
.data_in (cpu_example_0_data_in),
.clk_out (cpu_example_0_clk_out),
.data_out (cpu_example_0_data_out),
.slave_select_out (cpu_example_0_slave_select_out),
.clk_i (cpu_example_0_clk_i),
.rst_i (cpu_example_0_rst_i));
data_memory #(
.DATA_WIDTH (16),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
.iaddr_o (instruction_memory_0_iaddr_o),
.instruction_feed (instruction_memory_0_instruction_feed),
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
spi_slave #(
.SLAVE_ID (0))
spi_slave_0(
.clk_in (spi_slave_0_clk_in),
.data_in (spi_slave_0_data_in),
.slave_select_in (spi_slave_0_slave_select_in),
.data_out (spi_slave_0_data_out),
.rst_in (spi_slave_0_rst_in));
endmodule | module test_setup(); |
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK;
wire spi_slave_0_slave_if_to_cpu_example_0_master_ifSS;
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
wire cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
wire [7:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress;
wire [27:0] instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data;
wire [9:0] cpu_example_0_local_data_to_data_memory_0_slaveaddress;
wire [15:0] cpu_example_0_local_data_to_data_memory_0_slaveread_data;
wire cpu_example_0_local_data_to_data_memory_0_slavewrite;
wire [15:0] cpu_example_0_local_data_to_data_memory_0_slavewrite_data;
wire spi_slave_0_rst_in_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire clock_generator_0_rst_o_to_cpu_example_0_rst_i;
wire clock_generator_0_clk_o_to_cpu_example_0_clk_i;
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_rst_o_to_data_memory_0_rst_i;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire cpu_example_0_clk_i;
wire cpu_example_0_clk_out;
wire cpu_example_0_data_in;
wire cpu_example_0_data_out;
wire [7:0] cpu_example_0_iaddr_o;
wire [27:0] cpu_example_0_instruction_feed;
wire [9:0] cpu_example_0_local_address_o;
wire [15:0] cpu_example_0_local_read_data;
wire [15:0] cpu_example_0_local_write_data;
wire cpu_example_0_local_write_o;
wire cpu_example_0_rst_i;
wire cpu_example_0_slave_select_out;
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [15:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [15:0] data_memory_0_write_data;
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_o;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
wire spi_slave_0_clk_in;
wire spi_slave_0_data_in;
wire spi_slave_0_data_out;
wire spi_slave_0_rst_in;
wire spi_slave_0_slave_select_in;
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_cpu_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_cpu_example_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_data_memory_0_rst_i = clock_generator_0_rst_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst = clock_generator_0_rst_o;
assign spi_slave_0_rst_in_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign cpu_example_0_clk_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemclk;
assign cpu_example_0_clk_i = clock_generator_0_clk_o_to_cpu_example_0_clk_i;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK = cpu_example_0_clk_out;
assign cpu_example_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI = cpu_example_0_data_out;
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0] = cpu_example_0_iaddr_o[7:0];
assign cpu_example_0_instruction_feed[27:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0];
assign cpu_example_0_local_data_to_data_memory_0_slaveaddress[9:0] = cpu_example_0_local_address_o[9:0];
assign cpu_example_0_local_read_data[15:0] = cpu_example_0_local_data_to_data_memory_0_slaveread_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite_data[15:0] = cpu_example_0_local_write_data[15:0];
assign cpu_example_0_local_data_to_data_memory_0_slavewrite = cpu_example_0_local_write_o;
assign cpu_example_0_rst_i = clock_generator_0_rst_o_to_cpu_example_0_rst_i;
assign cpu_example_0_rst_i = cpu_example_0_wb_system_to_clock_generator_0_wb_systemrst;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifSS = cpu_example_0_slave_select_out;
assign data_memory_0_adr_i[8:0] = cpu_example_0_local_data_to_data_memory_0_slaveaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign cpu_example_0_local_data_to_data_memory_0_slaveread_data[15:0] = data_memory_0_read_data[15:0];
assign data_memory_0_rst_i = clock_generator_0_rst_o_to_data_memory_0_rst_i;
assign data_memory_0_write = cpu_example_0_local_data_to_data_memory_0_slavewrite;
assign data_memory_0_write_data[15:0] = cpu_example_0_local_data_to_data_memory_0_slavewrite_data[15:0];
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_o[7:0] = instruction_memory_0_slave_to_cpu_example_0_iaddr_oaddress[7:0];
assign instruction_memory_0_slave_to_cpu_example_0_iaddr_oread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
assign spi_slave_0_clk_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifSCLK;
assign spi_slave_0_data_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifMOSI;
assign spi_slave_0_slave_if_to_cpu_example_0_master_ifMISO = spi_slave_0_data_out;
assign spi_slave_0_rst_in = spi_slave_0_rst_in_to_clock_generator_0_rst_o;
assign spi_slave_0_slave_select_in = spi_slave_0_slave_if_to_cpu_example_0_master_ifSS;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
cpu_example_0 cpu_example_0(
.instruction_feed (cpu_example_0_instruction_feed),
.iaddr_o (cpu_example_0_iaddr_o),
.local_read_data (cpu_example_0_local_read_data),
.local_address_o (cpu_example_0_local_address_o),
.local_write_data (cpu_example_0_local_write_data),
.local_write_o (cpu_example_0_local_write_o),
.data_in (cpu_example_0_data_in),
.clk_out (cpu_example_0_clk_out),
.data_out (cpu_example_0_data_out),
.slave_select_out (cpu_example_0_slave_select_out),
.clk_i (cpu_example_0_clk_i),
.rst_i (cpu_example_0_rst_i));
data_memory #(
.DATA_WIDTH (16),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
.iaddr_o (instruction_memory_0_iaddr_o),
.instruction_feed (instruction_memory_0_instruction_feed),
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
spi_slave #(
.SLAVE_ID (0))
spi_slave_0(
.clk_in (spi_slave_0_clk_in),
.data_in (spi_slave_0_data_in),
.slave_select_in (spi_slave_0_slave_select_in),
.data_out (spi_slave_0_data_out),
.rst_in (spi_slave_0_rst_in));
endmodule | 0 |
142,157 | data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0/test_setup.v | 97,170,571 | test_setup.v | v | 150 | 131 | [] | [] | [] | [(13, 149)] | null | null | 1: b"%Error: data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0/test_setup.v:87: Cannot find file containing module: 'clock_generator'\n clock_generator clock_generator_0(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator\n data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.v\n data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.sv\n clock_generator\n clock_generator.v\n clock_generator.sv\n obj_dir/clock_generator\n obj_dir/clock_generator.v\n obj_dir/clock_generator.sv\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0/test_setup.v:93: Cannot find file containing module: 'core_example_0'\n core_example_0 #(\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0/test_setup.v:121: Cannot find file containing module: 'data_memory'\n data_memory #(\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/cpu.subsystem.test/core_example.setup/1.0/test_setup.v:137: Cannot find file containing module: 'instruction_memory'\n instruction_memory #(\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n" | 313,141 | module | module test_setup();
wire [7:0] core_example_0_instructions_to_instruction_memory_0_slaveaddress;
wire [27:0] core_example_0_instructions_to_instruction_memory_0_slaveread_data;
wire [8:0] data_memory_0_slave_to_core_example_0_local_dataaddress;
wire [31:0] data_memory_0_slave_to_core_example_0_local_dataread_data;
wire data_memory_0_slave_to_core_example_0_local_datawrite;
wire [31:0] data_memory_0_slave_to_core_example_0_local_datawrite_data;
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_clk_o_to_core_example_0_clk_i;
wire core_example_0_rst_i_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire data_memory_0_rst_i_to_clock_generator_0_rst_o;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire core_example_0_clk_i;
wire [7:0] core_example_0_iaddr_o;
wire [27:0] core_example_0_instruction_feed;
wire [8:0] core_example_0_local_address_o;
wire [31:0] core_example_0_local_read_data;
wire [31:0] core_example_0_local_write_data;
wire core_example_0_local_write_o;
wire core_example_0_rst_i;
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [31:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [31:0] data_memory_0_write_data;
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_o;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
assign clock_generator_0_clk_o_to_core_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign core_example_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign data_memory_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign core_example_0_clk_i = clock_generator_0_clk_o_to_core_example_0_clk_i;
assign core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0] = core_example_0_iaddr_o[7:0];
assign core_example_0_instruction_feed[27:0] = core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0];
assign data_memory_0_slave_to_core_example_0_local_dataaddress[8:0] = core_example_0_local_address_o[8:0];
assign core_example_0_local_read_data[31:0] = data_memory_0_slave_to_core_example_0_local_dataread_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0] = core_example_0_local_write_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite = core_example_0_local_write_o;
assign core_example_0_rst_i = core_example_0_rst_i_to_clock_generator_0_rst_o;
assign data_memory_0_adr_i[8:0] = data_memory_0_slave_to_core_example_0_local_dataaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign data_memory_0_slave_to_core_example_0_local_dataread_data[31:0] = data_memory_0_read_data[31:0];
assign data_memory_0_rst_i = data_memory_0_rst_i_to_clock_generator_0_rst_o;
assign data_memory_0_write = data_memory_0_slave_to_core_example_0_local_datawrite;
assign data_memory_0_write_data[31:0] = data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0];
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_o[7:0] = core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0];
assign core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
core_example_0 #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.SUPPORTED_MEMORY (512),
.PERIPHERAL_BASE (128),
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
core_example_0(
.instruction_feed (core_example_0_instruction_feed),
.iaddr_o (core_example_0_iaddr_o),
.local_read_data (core_example_0_local_read_data),
.local_address_o (core_example_0_local_address_o),
.local_write_data (core_example_0_local_write_data),
.local_write_o (core_example_0_local_write_o),
.mem_data_i (0),
.mem_slave_rdy (0),
.mem_address_o (),
.mem_data_o (),
.mem_master_rdy (),
.mem_we_o (),
.clk_i (core_example_0_clk_i),
.rst_i (core_example_0_rst_i));
data_memory #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
.iaddr_o (instruction_memory_0_iaddr_o),
.instruction_feed (instruction_memory_0_instruction_feed),
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
endmodule | module test_setup(); |
wire [7:0] core_example_0_instructions_to_instruction_memory_0_slaveaddress;
wire [27:0] core_example_0_instructions_to_instruction_memory_0_slaveread_data;
wire [8:0] data_memory_0_slave_to_core_example_0_local_dataaddress;
wire [31:0] data_memory_0_slave_to_core_example_0_local_dataread_data;
wire data_memory_0_slave_to_core_example_0_local_datawrite;
wire [31:0] data_memory_0_slave_to_core_example_0_local_datawrite_data;
wire clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
wire clock_generator_0_clk_o_to_core_example_0_clk_i;
wire core_example_0_rst_i_to_clock_generator_0_rst_o;
wire clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
wire data_memory_0_rst_i_to_clock_generator_0_rst_o;
wire data_memory_0_clk_i_to_clock_generator_0_clk_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire core_example_0_clk_i;
wire [7:0] core_example_0_iaddr_o;
wire [27:0] core_example_0_instruction_feed;
wire [8:0] core_example_0_local_address_o;
wire [31:0] core_example_0_local_read_data;
wire [31:0] core_example_0_local_write_data;
wire core_example_0_local_write_o;
wire core_example_0_rst_i;
wire [8:0] data_memory_0_adr_i;
wire data_memory_0_clk_i;
wire [31:0] data_memory_0_read_data;
wire data_memory_0_rst_i;
wire data_memory_0_write;
wire [31:0] data_memory_0_write_data;
wire instruction_memory_0_clk_i;
wire [7:0] instruction_memory_0_iaddr_o;
wire [27:0] instruction_memory_0_instruction_feed;
wire instruction_memory_0_rst_i;
assign clock_generator_0_clk_o_to_core_example_0_clk_i = clock_generator_0_clk_o;
assign clock_generator_0_clk_o_to_instruction_memory_0_clk_i = clock_generator_0_clk_o;
assign data_memory_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_rst_o_to_instruction_memory_0_rst_i = clock_generator_0_rst_o;
assign core_example_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign data_memory_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign core_example_0_clk_i = clock_generator_0_clk_o_to_core_example_0_clk_i;
assign core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0] = core_example_0_iaddr_o[7:0];
assign core_example_0_instruction_feed[27:0] = core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0];
assign data_memory_0_slave_to_core_example_0_local_dataaddress[8:0] = core_example_0_local_address_o[8:0];
assign core_example_0_local_read_data[31:0] = data_memory_0_slave_to_core_example_0_local_dataread_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0] = core_example_0_local_write_data[31:0];
assign data_memory_0_slave_to_core_example_0_local_datawrite = core_example_0_local_write_o;
assign core_example_0_rst_i = core_example_0_rst_i_to_clock_generator_0_rst_o;
assign data_memory_0_adr_i[8:0] = data_memory_0_slave_to_core_example_0_local_dataaddress[8:0];
assign data_memory_0_clk_i = data_memory_0_clk_i_to_clock_generator_0_clk_o;
assign data_memory_0_slave_to_core_example_0_local_dataread_data[31:0] = data_memory_0_read_data[31:0];
assign data_memory_0_rst_i = data_memory_0_rst_i_to_clock_generator_0_rst_o;
assign data_memory_0_write = data_memory_0_slave_to_core_example_0_local_datawrite;
assign data_memory_0_write_data[31:0] = data_memory_0_slave_to_core_example_0_local_datawrite_data[31:0];
assign instruction_memory_0_clk_i = clock_generator_0_clk_o_to_instruction_memory_0_clk_i;
assign instruction_memory_0_iaddr_o[7:0] = core_example_0_instructions_to_instruction_memory_0_slaveaddress[7:0];
assign core_example_0_instructions_to_instruction_memory_0_slaveread_data[27:0] = instruction_memory_0_instruction_feed[27:0];
assign instruction_memory_0_rst_i = clock_generator_0_rst_o_to_instruction_memory_0_rst_i;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
core_example_0 #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.SUPPORTED_MEMORY (512),
.PERIPHERAL_BASE (128),
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
core_example_0(
.instruction_feed (core_example_0_instruction_feed),
.iaddr_o (core_example_0_iaddr_o),
.local_read_data (core_example_0_local_read_data),
.local_address_o (core_example_0_local_address_o),
.local_write_data (core_example_0_local_write_data),
.local_write_o (core_example_0_local_write_o),
.mem_data_i (0),
.mem_slave_rdy (0),
.mem_address_o (),
.mem_data_o (),
.mem_master_rdy (),
.mem_we_o (),
.clk_i (core_example_0_clk_i),
.rst_i (core_example_0_rst_i));
data_memory #(
.DATA_WIDTH (32),
.ADDR_WIDTH (9),
.MEMORY_SIZE (128),
.AUB (8))
data_memory_0(
.adr_i (data_memory_0_adr_i),
.write (data_memory_0_write),
.write_data (data_memory_0_write_data),
.read_data (data_memory_0_read_data),
.clk_i (data_memory_0_clk_i),
.rst_i (data_memory_0_rst_i));
instruction_memory #(
.INSTRUCTION_WIDTH (28),
.INSTRUCTION_ADDRESS_WIDTH(8))
instruction_memory_0(
.iaddr_o (instruction_memory_0_iaddr_o),
.instruction_feed (instruction_memory_0_instruction_feed),
.clk_i (instruction_memory_0_clk_i),
.rst_i (instruction_memory_0_rst_i));
endmodule | 0 |
142,158 | data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0/test_setup.v | 97,170,571 | test_setup.v | v | 82 | 128 | [] | [] | [] | [(13, 81)] | null | null | 1: b"%Error: data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0/test_setup.v:56: Cannot find file containing module: 'clock_generator'\n clock_generator clock_generator_0(\n ^~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator\n data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.v\n data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0,data/full_repos/permissive/97170571/clock_generator.sv\n clock_generator\n clock_generator.v\n clock_generator.sv\n obj_dir/clock_generator\n obj_dir/clock_generator.v\n obj_dir/clock_generator.sv\n%Error: data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0/test_setup.v:62: Cannot find file containing module: 'TestInitializer'\n TestInitializer #(\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97170571/tut.fi/other.subsystem.test/wb_example.setup/1.0/test_setup.v:72: Cannot find file containing module: 'wb_example_0'\n wb_example_0 wb_example_0(\n ^~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,144 | module | module test_setup();
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_to_wb_example_bench_0_done;
wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire wb_example_bench_0_clk_i;
wire wb_example_bench_0_done;
wire wb_example_bench_0_rst_i;
wire wb_example_bench_0_start;
wire wb_example_0_clk_i;
wire wb_example_0_done;
wire wb_example_0_rst_i;
wire wb_example_0_start;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done;
assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start;
assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done;
assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
TestInitializer #(
.WAIT_TIME (1200))
wb_example_bench_0(
.clk_i (wb_example_bench_0_clk_i),
.done (wb_example_bench_0_done),
.rst_i (wb_example_bench_0_rst_i),
.start (wb_example_bench_0_start));
wb_example_0 wb_example_0(
.clk_i (wb_example_0_clk_i),
.rst_i (wb_example_0_rst_i),
.start (wb_example_0_start),
.done (wb_example_0_done));
endmodule | module test_setup(); |
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
wire clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
wire wb_example_0_start_to_wb_example_bench_0_start;
wire wb_example_0_done_to_wb_example_bench_0_done;
wire wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
wire wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
wire clock_generator_0_clk_o;
wire clock_generator_0_rst_o;
wire wb_example_bench_0_clk_i;
wire wb_example_bench_0_done;
wire wb_example_bench_0_rst_i;
wire wb_example_bench_0_start;
wire wb_example_0_clk_i;
wire wb_example_0_done;
wire wb_example_0_rst_i;
wire wb_example_0_start;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemclk = clock_generator_0_clk_o;
assign wb_example_bench_0_clk_i_to_clock_generator_0_clk_o = clock_generator_0_clk_o;
assign clock_generator_0_wb_system_to_wb_example_0_wb_systemrst = clock_generator_0_rst_o;
assign wb_example_bench_0_rst_i_to_clock_generator_0_rst_o = clock_generator_0_rst_o;
assign wb_example_bench_0_clk_i = wb_example_bench_0_clk_i_to_clock_generator_0_clk_o;
assign wb_example_bench_0_done = wb_example_0_done_to_wb_example_bench_0_done;
assign wb_example_bench_0_rst_i = wb_example_bench_0_rst_i_to_clock_generator_0_rst_o;
assign wb_example_0_start_to_wb_example_bench_0_start = wb_example_bench_0_start;
assign wb_example_0_clk_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemclk;
assign wb_example_0_done_to_wb_example_bench_0_done = wb_example_0_done;
assign wb_example_0_rst_i = clock_generator_0_wb_system_to_wb_example_0_wb_systemrst;
assign wb_example_0_start = wb_example_0_start_to_wb_example_bench_0_start;
clock_generator clock_generator_0(
.clk_o (clock_generator_0_clk_o),
.rst_o (clock_generator_0_rst_o));
TestInitializer #(
.WAIT_TIME (1200))
wb_example_bench_0(
.clk_i (wb_example_bench_0_clk_i),
.done (wb_example_bench_0_done),
.rst_i (wb_example_bench_0_rst_i),
.start (wb_example_bench_0_start));
wb_example_0 wb_example_0(
.clk_i (wb_example_0_clk_i),
.rst_i (wb_example_0_rst_i),
.start (wb_example_0_start),
.done (wb_example_0_done));
endmodule | 0 |
142,159 | data/full_repos/permissive/97170571/tut.fi/peripheral.logic/sum_buffer/1.0/wb_sum_buffer.v | 97,170,571 | wb_sum_buffer.v | v | 121 | 183 | [] | [] | [] | [(13, 120)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/97170571/tut.fi/peripheral.logic/sum_buffer/1.0/wb_sum_buffer.v:89: Operator LT expects 32 or 5 bits on the LHS, but LHS\'s VARREF \'index\' generates 4 bits.\n : ... In instance wb_sum_buffer\n if (index < BUFFER_SIZE-1) begin\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,147 | module | module wb_sum_buffer #(
parameter BUFFER_SIZE = 16,
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter BASE_ADDRESS = 'h0F00,
parameter BUFFER_INDEX_WIDTH = $clog2(BUFFER_SIZE),
parameter COLUMN_WIDTH = 1
) (
input [ADDR_WIDTH-1:0] adr_i,
input cyc_i,
input [DATA_WIDTH-1:0] dat_i,
input stb_i,
input we_i,
output reg ack_o,
output reg [DATA_WIDTH-1:0] dat_o,
output reg err_o,
input clk_i,
input rst_i
);
reg [DATA_WIDTH-1:0] memory [BUFFER_SIZE-1:0];
reg [DATA_WIDTH-1:0] result;
reg [BUFFER_INDEX_WIDTH-1:0] index;
localparam AUB = 8;
localparam AU_IN_DATA = DATA_WIDTH/AUB;
reg [0:0] state;
integer lastValue;
integer newValue;
integer iterator;
parameter [0:0]
S_WAIT = 1'd0,
S_DEASSERT = 1'd1;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
ack_o <= 0;
dat_o <= 0;
err_o <= 0;
state <= S_WAIT;
result <= 0;
index <= 0;
for (iterator = 0; iterator < BUFFER_SIZE; iterator = iterator +1) begin
memory[iterator] <= 0;
end
end
else begin
if (state == S_WAIT) begin
if ( cyc_i == 1 && stb_i == 1 ) begin
if (adr_i == BUFFER_SIZE+BASE_ADDRESS && we_i == 1) begin
ack_o <= 1;
lastValue = memory[index];
newValue = dat_i * COLUMN_WIDTH;
memory[index] <= newValue;
result <= result - lastValue + newValue;
if (index < BUFFER_SIZE-1) begin
index <= index + 1;
end
else begin
index <= 0;
end
end
else if (adr_i == BUFFER_SIZE+BASE_ADDRESS+AU_IN_DATA && we_i == 0) begin
ack_o <= 1;
dat_o = result;
end
else begin
err_o <= 1;
end
state <= S_DEASSERT;
end
end
else if (state == S_DEASSERT) begin
ack_o <= 0;
err_o <= 0;
state <= S_WAIT;
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule | module wb_sum_buffer #(
parameter BUFFER_SIZE = 16,
parameter ADDR_WIDTH = 16,
parameter DATA_WIDTH = 32,
parameter BASE_ADDRESS = 'h0F00,
parameter BUFFER_INDEX_WIDTH = $clog2(BUFFER_SIZE),
parameter COLUMN_WIDTH = 1
) (
input [ADDR_WIDTH-1:0] adr_i,
input cyc_i,
input [DATA_WIDTH-1:0] dat_i,
input stb_i,
input we_i,
output reg ack_o,
output reg [DATA_WIDTH-1:0] dat_o,
output reg err_o,
input clk_i,
input rst_i
); |
reg [DATA_WIDTH-1:0] memory [BUFFER_SIZE-1:0];
reg [DATA_WIDTH-1:0] result;
reg [BUFFER_INDEX_WIDTH-1:0] index;
localparam AUB = 8;
localparam AU_IN_DATA = DATA_WIDTH/AUB;
reg [0:0] state;
integer lastValue;
integer newValue;
integer iterator;
parameter [0:0]
S_WAIT = 1'd0,
S_DEASSERT = 1'd1;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
ack_o <= 0;
dat_o <= 0;
err_o <= 0;
state <= S_WAIT;
result <= 0;
index <= 0;
for (iterator = 0; iterator < BUFFER_SIZE; iterator = iterator +1) begin
memory[iterator] <= 0;
end
end
else begin
if (state == S_WAIT) begin
if ( cyc_i == 1 && stb_i == 1 ) begin
if (adr_i == BUFFER_SIZE+BASE_ADDRESS && we_i == 1) begin
ack_o <= 1;
lastValue = memory[index];
newValue = dat_i * COLUMN_WIDTH;
memory[index] <= newValue;
result <= result - lastValue + newValue;
if (index < BUFFER_SIZE-1) begin
index <= index + 1;
end
else begin
index <= 0;
end
end
else if (adr_i == BUFFER_SIZE+BASE_ADDRESS+AU_IN_DATA && we_i == 0) begin
ack_o <= 1;
dat_o = result;
end
else begin
err_o <= 1;
end
state <= S_DEASSERT;
end
end
else if (state == S_DEASSERT) begin
ack_o <= 0;
err_o <= 0;
state <= S_WAIT;
end
else
$display("ERROR: Unkown state: %d", state);
end
end
endmodule | 0 |
142,163 | data/full_repos/permissive/97488549/src/IR.v | 97,488,549 | IR.v | v | 39 | 76 | [] | [] | [] | [(156, 186)] | null | null | 1: b'%Error: data/full_repos/permissive/97488549/src/IR.v:7: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/97488549/src/IR.v:12: Define or directive not defined: \'`FE_STATE_BITS\'\n input [`FE_STATE_BITS-1:0] fetchState , \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:13: Define or directive not defined: \'`EX_STATE_BITS\'\n input [`EX_STATE_BITS-1:0] executeState, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:14: Define or directive not defined: \'`INST_WIDTH\'\n input [ `INST_WIDTH-1:0] programMemIn, \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:17: Define or directive not defined: \'`INST_WIDTH\'\n output [ `INST_WIDTH-1:0] IR \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:20: Define or directive not defined: \'`INST_WIDTH\'\nreg [`INST_WIDTH-1:0] rIR;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:26: Define or directive not defined: \'`INST_WIDTH\'\n rIR <= `INST_WIDTH\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:29: Define or directive not defined: \'`FE_Q4\'\n if (fetchState == `FE_Q4) begin\n ^~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:29: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (fetchState == `FE_Q4) begin\n ^\n%Error: data/full_repos/permissive/97488549/src/IR.v:32: Define or directive not defined: \'`EX_Q1\'\n if (executeState == `EX_Q1) begin\n ^~~~~~\n%Error: data/full_repos/permissive/97488549/src/IR.v:32: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\n if (executeState == `EX_Q1) begin\n ^\n%Error: data/full_repos/permissive/97488549/src/IR.v:34: Define or directive not defined: \'`I_NOP_12\'\n rIR <= `I_NOP_12;\n ^~~~~~~~~\n%Error: Cannot continue\n' | 313,155 | module | module IR (
input clk ,
input rst_n ,
input [`FE_STATE_BITS-1:0] fetchState ,
input [`EX_STATE_BITS-1:0] executeState,
input [ `INST_WIDTH-1:0] programMemIn,
input goto ,
input skip ,
output [ `INST_WIDTH-1:0] IR
);
reg [`INST_WIDTH-1:0] rIR;
assign IR = rIR;
always @(posedge clk) begin
if (!rst_n) begin
rIR <= `INST_WIDTH'b0;
end
else begin
if (fetchState == `FE_Q4) begin
rIR <= programMemIn;
end
if (executeState == `EX_Q1) begin
if (skip | goto) begin
rIR <= `I_NOP_12;
end
end
end
end
endmodule | module IR (
input clk ,
input rst_n ,
input [`FE_STATE_BITS-1:0] fetchState ,
input [`EX_STATE_BITS-1:0] executeState,
input [ `INST_WIDTH-1:0] programMemIn,
input goto ,
input skip ,
output [ `INST_WIDTH-1:0] IR
); |
reg [`INST_WIDTH-1:0] rIR;
assign IR = rIR;
always @(posedge clk) begin
if (!rst_n) begin
rIR <= `INST_WIDTH'b0;
end
else begin
if (fetchState == `FE_Q4) begin
rIR <= programMemIn;
end
if (executeState == `EX_Q1) begin
if (skip | goto) begin
rIR <= `I_NOP_12;
end
end
end
end
endmodule | 4 |
142,167 | data/full_repos/permissive/97488549/src/programMem.v | 97,488,549 | programMem.v | v | 25 | 60 | [] | [] | [] | [(156, 171)] | null | null | 1: b'%Error: data/full_repos/permissive/97488549/src/programMem.v:7: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/97488549/src/programMem.v:12: Define or directive not defined: \'`PC_WIDTH\'\n input [`PC_WIDTH-1:0] PCIn,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/programMem.v:13: Define or directive not defined: \'`INST_WIDTH\'\n output [`INST_WIDTH - 1:0] programMemOut \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/programMem.v:16: Define or directive not defined: \'`INST_WIDTH\'\n reg [`INST_WIDTH - 1:0] programMem [511:0];\n ^~~~~~~~~~~\n%Error: Exiting due to 4 error(s)\n' | 313,159 | module | module programMem (
input [`PC_WIDTH-1:0] PCIn,
output [`INST_WIDTH - 1:0] programMemOut
);
reg [`INST_WIDTH - 1:0] programMem [511:0];
assign programMemOut = programMem [PCIn];
initial begin
$readmemh("program.mif", programMem);
$display("Program loaded.");
end
endmodule | module programMem (
input [`PC_WIDTH-1:0] PCIn,
output [`INST_WIDTH - 1:0] programMemOut
); |
reg [`INST_WIDTH - 1:0] programMem [511:0];
assign programMemOut = programMem [PCIn];
initial begin
$readmemh("program.mif", programMem);
$display("Program loaded.");
end
endmodule | 4 |
142,169 | data/full_repos/permissive/97488549/src/RegisterFile.v | 97,488,549 | RegisterFile.v | v | 219 | 73 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:7: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:13: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] writeDataIn ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n input [`DATA_WIDTH-1:0] statusIn ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:15: Define or directive not defined: \'`IO_A_WIDTH\'\n input [`IO_A_WIDTH-1:0] portAIn ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:16: Define or directive not defined: \'`IO_B_WIDTH\'\n input [`IO_B_WIDTH-1:0] portBIn ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:17: Define or directive not defined: \'`IO_C_WIDTH\'\n input [`IO_C_WIDTH-1:0] portCIn ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:18: Define or directive not defined: \'`PC_WIDTH\'\n input [ `PC_WIDTH-1:0] pcIn ,\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:19: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] fsrOut , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:20: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] regfileOut , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:21: Define or directive not defined: \'`DATA_WIDTH\'\n output [`DATA_WIDTH-1:0] statusOut , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:22: Define or directive not defined: \'`IO_A_WIDTH\'\n output [`IO_A_WIDTH-1:0] portAOut ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:23: Define or directive not defined: \'`IO_B_WIDTH\'\n output [`IO_B_WIDTH-1:0] portBOut ,\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:24: Define or directive not defined: \'`IO_C_WIDTH\'\n output [`IO_C_WIDTH-1:0] portCOut\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:28: Define or directive not defined: \'`DATA_WIDTH\'\nreg[`DATA_WIDTH - 1:0] status;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:29: Define or directive not defined: \'`DATA_WIDTH\'\nreg[`DATA_WIDTH - 1:0] FSReg;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:30: Define or directive not defined: \'`IO_A_WIDTH\'\nreg[`IO_A_WIDTH - 1:0] portA;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:31: Define or directive not defined: \'`IO_B_WIDTH\'\nreg[`IO_B_WIDTH - 1:0] portB;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:32: Define or directive not defined: \'`IO_C_WIDTH\'\nreg[`IO_C_WIDTH - 1:0] portC;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:34: Define or directive not defined: \'`DATA_WIDTH\'\nreg[`DATA_WIDTH - 1:0] indirect; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:35: Define or directive not defined: \'`DATA_WIDTH\'\nreg[`DATA_WIDTH - 1:0] direct; \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:38: Define or directive not defined: \'`DATA_WIDTH\'\nreg [`DATA_WIDTH - 1:0] GPR [31:8];\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:42: Define or directive not defined: \'`ADDR_INDF\'\nassign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:42: syntax error, unexpected \')\', expecting TYPE-IDENTIFIER\nassign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;\n ^\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:51: Define or directive not defined: \'`ADDR_INDF\'\n `ADDR_INDF: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:51: syntax error, unexpected \':\', expecting endcase\n `ADDR_INDF: begin\n ^\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:52: Define or directive not defined: \'`DATA_WIDTH\'\n indirect = `DATA_WIDTH\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:54: Define or directive not defined: \'`ADDR_TMR0\'\n `ADDR_TMR0: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:54: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_TMR0: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:55: Define or directive not defined: \'`DATA_WIDTH\'\n indirect = `DATA_WIDTH\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:57: Define or directive not defined: \'`ADDR_PCL\'\n `ADDR_PCL: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:57: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_PCL: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:60: Define or directive not defined: \'`ADDR_STATUS\'\n `ADDR_STATUS: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:60: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_STATUS: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:63: Define or directive not defined: \'`ADDR_FSR\'\n `ADDR_FSR: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:63: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_FSR: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:66: Define or directive not defined: \'`ADDR_PORTA\'\n `ADDR_PORTA: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:66: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_PORTA: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:69: Define or directive not defined: \'`ADDR_PORTB\'\n `ADDR_PORTB: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:69: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_PORTB: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:72: Define or directive not defined: \'`ADDR_PORTC\'\n `ADDR_PORTC: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:72: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `ADDR_PORTC: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:88: Define or directive not defined: \'`ADDR_INDF\'\n `ADDR_INDF: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:89: Define or directive not defined: \'`DATA_WIDTH\'\n direct = `DATA_WIDTH\'bX;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:91: Define or directive not defined: \'`ADDR_TMR0\'\n `ADDR_TMR0: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:92: Define or directive not defined: \'`DATA_WIDTH\'\n direct = `DATA_WIDTH\'bX;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:94: Define or directive not defined: \'`ADDR_PCL\'\n `ADDR_PCL: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:97: Define or directive not defined: \'`ADDR_STATUS\'\n `ADDR_STATUS: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:100: Define or directive not defined: \'`ADDR_FSR\'\n `ADDR_FSR: begin\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:103: Define or directive not defined: \'`ADDR_PORTA\'\n `ADDR_PORTA: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/RegisterFile.v:106: Define or directive not defined: \'`ADDR_PORTB\'\n `ADDR_PORTB: begin\n ^~~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n' | 313,161 | module | module RegisterFile (
input clk ,
input rst ,
input [ 2:0] writeCommand,
input [ 4:0] fileAddr ,
input [`DATA_WIDTH-1:0] writeDataIn ,
input [`DATA_WIDTH-1:0] statusIn ,
input [`IO_A_WIDTH-1:0] portAIn ,
input [`IO_B_WIDTH-1:0] portBIn ,
input [`IO_C_WIDTH-1:0] portCIn ,
input [ `PC_WIDTH-1:0] pcIn ,
output [`DATA_WIDTH-1:0] fsrOut ,
output [`DATA_WIDTH-1:0] regfileOut ,
output [`DATA_WIDTH-1:0] statusOut ,
output [`IO_A_WIDTH-1:0] portAOut ,
output [`IO_B_WIDTH-1:0] portBOut ,
output [`IO_C_WIDTH-1:0] portCOut
);
reg[`DATA_WIDTH - 1:0] status;
reg[`DATA_WIDTH - 1:0] FSReg;
reg[`IO_A_WIDTH - 1:0] portA;
reg[`IO_B_WIDTH - 1:0] portB;
reg[`IO_C_WIDTH - 1:0] portC;
reg[`DATA_WIDTH - 1:0] indirect;
reg[`DATA_WIDTH - 1:0] direct;
reg [`DATA_WIDTH - 1:0] GPR [31:8];
assign fsrOut = FSReg;
assign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;
assign statusOut = status;
assign portAOut = portA;
assign portBOut = portB;
assign portCOut = portC;
always @(*) begin
case (FSReg[4:0])
`ADDR_INDF: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_TMR0: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_PCL: begin
indirect = pcIn[7:0];
end
`ADDR_STATUS: begin
indirect = status;
end
`ADDR_FSR: begin
indirect = FSReg;
end
`ADDR_PORTA: begin
indirect = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
indirect = portBIn;
end
`ADDR_PORTC: begin
indirect = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F:begin
indirect = GPR[FSReg[4:0]];
end
default: ;
endcase
end
always @(*) begin
case (fileAddr)
`ADDR_INDF: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_TMR0: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_PCL: begin
direct = pcIn[7:0];
end
`ADDR_STATUS: begin
direct = status;
end
`ADDR_FSR: begin
direct = FSReg;
end
`ADDR_PORTA: begin
direct = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
direct = portBIn;
end
`ADDR_PORTC: begin
direct = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
direct = GPR[fileAddr];
end
default: ;
endcase
end
integer index;
always@(posedge clk) begin
if(!rst) begin
status <= `DATA_WIDTH'b0001_1xxx;
FSReg <= `DATA_WIDTH'b1xxx_xxxx;
portA <= `IO_A_WIDTH'bxxxx;
portB <= `IO_B_WIDTH'bxxxx_xxxx;
portC <= `IO_C_WIDTH'bxxxx_xxxx;
GPR[8] <= `DATA_WIDTH'b0000_0000;
GPR[9] <= `DATA_WIDTH'b0000_0000;
GPR[10] <= `DATA_WIDTH'b0000_0000;
GPR[11] <= `DATA_WIDTH'b0000_0000;
GPR[12] <= `DATA_WIDTH'b0000_0000;
GPR[13] <= `DATA_WIDTH'b0000_0000;
GPR[14] <= `DATA_WIDTH'b0000_0000;
GPR[15] <= `DATA_WIDTH'b0000_0000;
end
else begin
case (writeCommand)
3'b010,3'b011: begin
if(writeCommand == 3'b011) begin
status <= statusIn;
end
case (fileAddr)
`ADDR_INDF: begin
case(FSReg[4:0])
`ADDR_INDF: begin
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[FSReg[4:0]] <= writeDataIn;
end
default: ;
endcase
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[fileAddr] <= writeDataIn;
end
default :;
endcase
end
3'b001: begin
status <= statusIn;
end
3'b100: begin
FSReg <= writeDataIn;
end
default :;
endcase
end
end
endmodule | module RegisterFile (
input clk ,
input rst ,
input [ 2:0] writeCommand,
input [ 4:0] fileAddr ,
input [`DATA_WIDTH-1:0] writeDataIn ,
input [`DATA_WIDTH-1:0] statusIn ,
input [`IO_A_WIDTH-1:0] portAIn ,
input [`IO_B_WIDTH-1:0] portBIn ,
input [`IO_C_WIDTH-1:0] portCIn ,
input [ `PC_WIDTH-1:0] pcIn ,
output [`DATA_WIDTH-1:0] fsrOut ,
output [`DATA_WIDTH-1:0] regfileOut ,
output [`DATA_WIDTH-1:0] statusOut ,
output [`IO_A_WIDTH-1:0] portAOut ,
output [`IO_B_WIDTH-1:0] portBOut ,
output [`IO_C_WIDTH-1:0] portCOut
); |
reg[`DATA_WIDTH - 1:0] status;
reg[`DATA_WIDTH - 1:0] FSReg;
reg[`IO_A_WIDTH - 1:0] portA;
reg[`IO_B_WIDTH - 1:0] portB;
reg[`IO_C_WIDTH - 1:0] portC;
reg[`DATA_WIDTH - 1:0] indirect;
reg[`DATA_WIDTH - 1:0] direct;
reg [`DATA_WIDTH - 1:0] GPR [31:8];
assign fsrOut = FSReg;
assign regfileOut = (fileAddr == `ADDR_INDF) ? indirect : direct;
assign statusOut = status;
assign portAOut = portA;
assign portBOut = portB;
assign portCOut = portC;
always @(*) begin
case (FSReg[4:0])
`ADDR_INDF: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_TMR0: begin
indirect = `DATA_WIDTH'b0;
end
`ADDR_PCL: begin
indirect = pcIn[7:0];
end
`ADDR_STATUS: begin
indirect = status;
end
`ADDR_FSR: begin
indirect = FSReg;
end
`ADDR_PORTA: begin
indirect = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
indirect = portBIn;
end
`ADDR_PORTC: begin
indirect = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F:begin
indirect = GPR[FSReg[4:0]];
end
default: ;
endcase
end
always @(*) begin
case (fileAddr)
`ADDR_INDF: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_TMR0: begin
direct = `DATA_WIDTH'bX;
end
`ADDR_PCL: begin
direct = pcIn[7:0];
end
`ADDR_STATUS: begin
direct = status;
end
`ADDR_FSR: begin
direct = FSReg;
end
`ADDR_PORTA: begin
direct = {4'b0000, portAIn};
end
`ADDR_PORTB: begin
direct = portBIn;
end
`ADDR_PORTC: begin
direct = portCIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
direct = GPR[fileAddr];
end
default: ;
endcase
end
integer index;
always@(posedge clk) begin
if(!rst) begin
status <= `DATA_WIDTH'b0001_1xxx;
FSReg <= `DATA_WIDTH'b1xxx_xxxx;
portA <= `IO_A_WIDTH'bxxxx;
portB <= `IO_B_WIDTH'bxxxx_xxxx;
portC <= `IO_C_WIDTH'bxxxx_xxxx;
GPR[8] <= `DATA_WIDTH'b0000_0000;
GPR[9] <= `DATA_WIDTH'b0000_0000;
GPR[10] <= `DATA_WIDTH'b0000_0000;
GPR[11] <= `DATA_WIDTH'b0000_0000;
GPR[12] <= `DATA_WIDTH'b0000_0000;
GPR[13] <= `DATA_WIDTH'b0000_0000;
GPR[14] <= `DATA_WIDTH'b0000_0000;
GPR[15] <= `DATA_WIDTH'b0000_0000;
end
else begin
case (writeCommand)
3'b010,3'b011: begin
if(writeCommand == 3'b011) begin
status <= statusIn;
end
case (fileAddr)
`ADDR_INDF: begin
case(FSReg[4:0])
`ADDR_INDF: begin
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[FSReg[4:0]] <= writeDataIn;
end
default: ;
endcase
end
`ADDR_TMR0: begin
end
`ADDR_PCL: begin
end
`ADDR_STATUS: begin
status <= {writeDataIn[7:5],status[4:3],writeDataIn[2:0]};
end
`ADDR_FSR: begin
FSReg <= writeDataIn;
end
`ADDR_PORTA: begin
portA <= writeDataIn[`IO_A_WIDTH - 1:0];
end
`ADDR_PORTB: begin
portB <= writeDataIn;
end
`ADDR_PORTC: begin
portC <= writeDataIn;
end
5'h08, 5'h09, 5'h0A, 5'h0B, 5'h0C,5'h0D,
5'h0E, 5'h0F, 5'h10, 5'h11, 5'h12, 5'h13,
5'h14,5'h15, 5'h16, 5'h17, 5'h18, 5'h19,
5'h1A, 5'h1B, 5'h1C, 5'h1D, 5'h1E, 5'h1F: begin
GPR[fileAddr] <= writeDataIn;
end
default :;
endcase
end
3'b001: begin
status <= statusIn;
end
3'b100: begin
FSReg <= writeDataIn;
end
default :;
endcase
end
end
endmodule | 4 |
142,171 | data/full_repos/permissive/97488549/src/wRegWriteControl.v | 97,488,549 | wRegWriteControl.v | v | 89 | 76 | [] | [] | [] | [(156, 235)] | null | null | 1: b'%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:7: Cannot find include file: define.v\n`include "define.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.v\n data/full_repos/permissive/97488549/src,data/full_repos/permissive/97488549/define.v.sv\n define.v\n define.v.v\n define.v.sv\n obj_dir/define.v\n obj_dir/define.v.v\n obj_dir/define.v.sv\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:13: Define or directive not defined: \'`EX_STATE_BITS\'\n input [`EX_STATE_BITS-1:0] executeState, \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:14: Define or directive not defined: \'`DATA_WIDTH\'\n input [ `DATA_WIDTH-1:0] aluResultIn , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:15: Define or directive not defined: \'`DATA_WIDTH\'\n input [ `DATA_WIDTH-1:0] gprIn , \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:16: Define or directive not defined: \'`DATA_WIDTH\'\n output [ `DATA_WIDTH-1:0] wROut \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:19: Define or directive not defined: \'`DATA_WIDTH\'\nreg [`DATA_WIDTH-1:0] wR;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:25: Define or directive not defined: \'`DATA_WIDTH\'\n wR <= `DATA_WIDTH\'b0;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:29: Define or directive not defined: \'`EX_Q1\'\n `EX_Q1: begin\n ^~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:29: syntax error, unexpected \':\', expecting endcase\n `EX_Q1: begin\n ^\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:31: Define or directive not defined: \'`EX_Q2\'\n `EX_Q2: begin\n ^~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:33: Define or directive not defined: \'`EX_Q3\'\n `EX_Q3: begin\n ^~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:35: Define or directive not defined: \'`EX_Q4_CLRF\'\n `EX_Q4_CLRF: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:37: Define or directive not defined: \'`EX_Q4_CLRW\'\n `EX_Q4_CLRW: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:40: Define or directive not defined: \'`EX_Q4_FSZ\'\n `EX_Q4_FSZ: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:40: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `EX_Q4_FSZ: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:45: Define or directive not defined: \'`EX_Q4_MOVF\'\n `EX_Q4_MOVF: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:45: syntax error, unexpected begin, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER or new\n `EX_Q4_MOVF: begin\n ^~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:50: Define or directive not defined: \'`EX_Q4_MOVWF\'\n `EX_Q4_MOVWF: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:52: Define or directive not defined: \'`EX_Q4_BXF\'\n `EX_Q4_BXF: begin\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:54: Define or directive not defined: \'`EX_Q4_BTFSX\'\n `EX_Q4_BTFSX: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:56: Define or directive not defined: \'`EX_Q4_CALL\'\n `EX_Q4_CALL: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:58: Define or directive not defined: \'`EX_Q4_CLRWDT\'\n `EX_Q4_CLRWDT: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:60: Define or directive not defined: \'`EX_Q4_GOTO\'\n `EX_Q4_GOTO: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:62: Define or directive not defined: \'`EX_Q4_MOVLW\'\n `EX_Q4_MOVLW: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:65: Define or directive not defined: \'`EX_Q4_OPTION\'\n `EX_Q4_OPTION: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:67: Define or directive not defined: \'`EX_Q4_RETLW\'\n `EX_Q4_RETLW: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:70: Define or directive not defined: \'`EX_Q4_SLEEP\'\n `EX_Q4_SLEEP: begin\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:72: Define or directive not defined: \'`EX_Q4_TRIS\'\n `EX_Q4_TRIS: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:74: Define or directive not defined: \'`EX_Q4_ELSE\'\n `EX_Q4_ELSE: begin\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:79: Define or directive not defined: \'`EX_Q4_ALUXLW\'\n `EX_Q4_ALUXLW: begin\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/97488549/src/wRegWriteControl.v:82: Define or directive not defined: \'`EX_Q4_NOP\'\n `EX_Q4_NOP: begin\n ^~~~~~~~~~\n%Error: Cannot continue\n' | 313,163 | module | module wRegWriteControl (
input clk ,
input rst_n ,
input [ 7:0] IR ,
input [`EX_STATE_BITS-1:0] executeState,
input [ `DATA_WIDTH-1:0] aluResultIn ,
input [ `DATA_WIDTH-1:0] gprIn ,
output [ `DATA_WIDTH-1:0] wROut
);
reg [`DATA_WIDTH-1:0] wR;
assign wROut = wR;
always @(posedge clk) begin
if (!rst_n) begin
wR <= `DATA_WIDTH'b0;
end
else begin
case (executeState)
`EX_Q1: begin
end
`EX_Q2: begin
end
`EX_Q3: begin
end
`EX_Q4_CLRF: begin
end
`EX_Q4_CLRW: begin
wR <= 0;
end
`EX_Q4_FSZ: begin
if (!IR[5]) begin
wR <= aluResultIn;
end
end
`EX_Q4_MOVF: begin
if (! IR[5]) begin
wR <= gprIn;
end
end
`EX_Q4_MOVWF: begin
end
`EX_Q4_BXF: begin
end
`EX_Q4_BTFSX: begin
end
`EX_Q4_CALL: begin
end
`EX_Q4_CLRWDT: begin
end
`EX_Q4_GOTO: begin
end
`EX_Q4_MOVLW: begin
wR <= IR[7:0];
end
`EX_Q4_OPTION: begin
end
`EX_Q4_RETLW: begin
wR <= IR[7:0];
end
`EX_Q4_SLEEP: begin
end
`EX_Q4_TRIS: begin
end
`EX_Q4_ELSE: begin
if (!IR[5]) begin
wR <= aluResultIn;
end
end
`EX_Q4_ALUXLW: begin
wR <= aluResultIn;
end
`EX_Q4_NOP: begin
end
default: ;
endcase
end
end
endmodule | module wRegWriteControl (
input clk ,
input rst_n ,
input [ 7:0] IR ,
input [`EX_STATE_BITS-1:0] executeState,
input [ `DATA_WIDTH-1:0] aluResultIn ,
input [ `DATA_WIDTH-1:0] gprIn ,
output [ `DATA_WIDTH-1:0] wROut
); |
reg [`DATA_WIDTH-1:0] wR;
assign wROut = wR;
always @(posedge clk) begin
if (!rst_n) begin
wR <= `DATA_WIDTH'b0;
end
else begin
case (executeState)
`EX_Q1: begin
end
`EX_Q2: begin
end
`EX_Q3: begin
end
`EX_Q4_CLRF: begin
end
`EX_Q4_CLRW: begin
wR <= 0;
end
`EX_Q4_FSZ: begin
if (!IR[5]) begin
wR <= aluResultIn;
end
end
`EX_Q4_MOVF: begin
if (! IR[5]) begin
wR <= gprIn;
end
end
`EX_Q4_MOVWF: begin
end
`EX_Q4_BXF: begin
end
`EX_Q4_BTFSX: begin
end
`EX_Q4_CALL: begin
end
`EX_Q4_CLRWDT: begin
end
`EX_Q4_GOTO: begin
end
`EX_Q4_MOVLW: begin
wR <= IR[7:0];
end
`EX_Q4_OPTION: begin
end
`EX_Q4_RETLW: begin
wR <= IR[7:0];
end
`EX_Q4_SLEEP: begin
end
`EX_Q4_TRIS: begin
end
`EX_Q4_ELSE: begin
if (!IR[5]) begin
wR <= aluResultIn;
end
end
`EX_Q4_ALUXLW: begin
wR <= aluResultIn;
end
`EX_Q4_NOP: begin
end
default: ;
endcase
end
end
endmodule | 4 |
142,173 | data/full_repos/permissive/97630563/b16-eval-usb-test.v | 97,630,563 | b16-eval-usb-test.v | v | 37 | 62 | [] | [] | [] | null | line:31: before: "(" | null | 1: b'%Error: data/full_repos/permissive/97630563/b16-eval-usb-test.v:26: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("b16-eval-usb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97630563/b16-eval-usb-test.v:27: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/97630563/b16-eval-usb-test.v:30: Unsupported: Ignoring delay on this delayed statement.\n #10000 nreset <= 1;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/97630563/b16-eval-usb-test.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 clk <= ~clk;\n ^\n%Error: Exiting due to 2 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,165 | module | module test;
wire [15:0] a0, a1, d0, d1;
wire DP, DN, send0, send1;
reg clk, nreset;
assign { DP, DN } = (send0 | send1) ? 2'bzz : 2'b10;
b16_eval_usb #(16, "master.hex")
core0(clk, nreset, a0, d0, wr_b0, rd_b0, ble_b0, bhe_b0,
DP, DN, dif0, send0, dp0, dn0);
b16_eval_usb #(16, "slave.hex")
core1(clk, nreset, a1, d1, wr_b1, rd_b1, ble_b1, bhe_b1,
DP, DN, dif1, send1, dp1, dn1);
usbphys usbp0(DP, DN, dif0, send0, dp0, dn0);
usbphys usbp1(DP, DN, dif1, send1, dp1, dn1);
initial
begin
$dumpfile("b16-eval-usb.vcd");
$dumpvars();
nreset <= 0;
clk <= 0;
#10000 nreset <= 1;
repeat(10000)
#10 clk <= ~clk;
$finish;
end
endmodule | module test; |
wire [15:0] a0, a1, d0, d1;
wire DP, DN, send0, send1;
reg clk, nreset;
assign { DP, DN } = (send0 | send1) ? 2'bzz : 2'b10;
b16_eval_usb #(16, "master.hex")
core0(clk, nreset, a0, d0, wr_b0, rd_b0, ble_b0, bhe_b0,
DP, DN, dif0, send0, dp0, dn0);
b16_eval_usb #(16, "slave.hex")
core1(clk, nreset, a1, d1, wr_b1, rd_b1, ble_b1, bhe_b1,
DP, DN, dif1, send1, dp1, dn1);
usbphys usbp0(DP, DN, dif0, send0, dp0, dn0);
usbphys usbp1(DP, DN, dif1, send1, dp1, dn1);
initial
begin
$dumpfile("b16-eval-usb.vcd");
$dumpvars();
nreset <= 0;
clk <= 0;
#10000 nreset <= 1;
repeat(10000)
#10 clk <= ~clk;
$finish;
end
endmodule | 2 |
142,181 | data/full_repos/permissive/97630563/ram1024.v | 97,630,563 | ram1024.v | v | 29 | 68 | [] | [] | [] | [(3, 28)] | null | data/verilator_xmls/23d980c7-809c-45d2-82e2-afd66754b4c1.xml | null | 313,170 | module | module ram1024 (address, byteena, clock, data, wren, q);
parameter bootram="b16.hex";
input [9:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
reg [15:0] ram[0:1023];
reg [15:0] q;
wire [15:0] dfetch = ram[address];
wire [15:0] dstore = { byteena[1] ? data[15:8] : dfetch[15:8],
byteena[0] ? data[7:0] : dfetch[7:0] };
always @(posedge clock)
begin
if(wren) ram[address] <= dstore;
q <= #2 dfetch;
end
initial
$readmemh(bootram, ram);
endmodule | module ram1024 (address, byteena, clock, data, wren, q); |
parameter bootram="b16.hex";
input [9:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
reg [15:0] ram[0:1023];
reg [15:0] q;
wire [15:0] dfetch = ram[address];
wire [15:0] dstore = { byteena[1] ? data[15:8] : dfetch[15:8],
byteena[0] ? data[7:0] : dfetch[7:0] };
always @(posedge clock)
begin
if(wren) ram[address] <= dstore;
q <= #2 dfetch;
end
initial
$readmemh(bootram, ram);
endmodule | 2 |
142,183 | data/full_repos/permissive/97630563/usb-test.v | 97,630,563 | usb-test.v | v | 310 | 82 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b'%Error: data/full_repos/permissive/97630563/usb-test.v:67: syntax error, unexpected \'[\', expecting "\'{"\n wire tx = (sendcrc & sendcrcen) ? crcout : byte[0];\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:145: syntax error, unexpected \';\', expecting IDENTIFIER\n input bit;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:148: syntax error, unexpected \';\', expecting "\'{"\n tx <= bit;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:153: Unsupported: Ignoring delay on this delayed statement.\n #(40) usbclk <= 0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:154: Unsupported: Ignoring delay on this delayed statement.\n #(40) usbclk <= 1;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:156: syntax error, unexpected \')\', expecting "\'{"\n if(!bit) begin\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:159: syntax error, unexpected else\n end else bitstuff <= bitstuff + 1;\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:160: Unsupported: Ignoring delay on this delayed statement.\n #(40) usbclk <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:161: Unsupported: Ignoring delay on this delayed statement.\n #(40) usbclk <= 1;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:162: syntax error, unexpected end\n end\n ^~~\n%Error: data/full_repos/permissive/97630563/usb-test.v:170: syntax error, unexpected \'[\', expecting "\'{"\n sendbit(byte[0]);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:190: Unsupported: Ignoring delay on this delayed statement.\n #(40*0) { dp, dn } <= 2\'b00;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:191: Unsupported: Ignoring delay on this delayed statement.\n #(40*4) { dp, dn } <= 2\'b10;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:192: Unsupported: Ignoring delay on this delayed statement.\n #(40*2) { dp, dn } <= 2\'bzz;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:246: syntax error, unexpected \'@\'\n @(posedge usbclk4) sel <= 1;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:251: syntax error, unexpected \'@\'\n @(posedge usbclk4) sel <= 0;\n ^\n%Error: data/full_repos/permissive/97630563/usb-test.v:260: Unsupported or unknown PLI call: $dumpfile\n $dumpfile("usb.vcd");\n ^~~~~~~~~\n%Error: data/full_repos/permissive/97630563/usb-test.v:261: Unsupported or unknown PLI call: $dumpvars\n $dumpvars();\n ^~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:279: Unsupported: Ignoring delay on this delayed statement.\n #100 reset = 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:282: Unsupported: Ignoring delay on this delayed statement.\n #1000 sendtoken(4\'b0101, 6\'h00, 4\'h0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:283: Unsupported: Ignoring delay on this delayed statement.\n #1000 sendtoken(4\'b1101, 6\'h12, 4\'h3);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:286: Unsupported: Ignoring delay on this delayed statement.\n #1000 senddata(0, 3\'h7, 64\'h123456789ABCDEF0);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:287: Unsupported: Ignoring delay on this delayed statement.\n #1000 sendtoken(4\'b0001, 6\'h7F, 4\'hF);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:290: Unsupported: Ignoring delay on this delayed statement.\n #1000 senddata(1, 3\'h7, 64\'hFEDCBA9876543210);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:293: Unsupported: Ignoring delay on this delayed statement.\n #1000 write(1, 16\'h1234);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:296: Unsupported: Ignoring delay on this delayed statement.\n #4000 memory[15\'h2B3C] = 16\'h1234;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:301: Unsupported: Ignoring delay on this delayed statement.\n #10000 write(2, 16\'h5678);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:303: Unsupported: Ignoring delay on this delayed statement.\n #10000 write(0, 16\'h3800);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/97630563/usb-test.v:304: Unsupported: Ignoring delay on this delayed statement.\n #3000 write(0, 16\'h0000);\n ^\n%Error: Exiting due to 11 error(s), 18 warning(s)\n' | 313,172 | module | module usbtest;
reg [15:0] crc;
reg crcen, crc16;
reg [2:0] bitstuff;
reg usbclk;
wire usbclk4;
reg usbclken;
reg sendcrc;
wire dif;
reg olddif, tx;
wire DP, DN;
reg dp, dn;
reg reset;
reg sel, r, ack, intack;
reg [1:0] addr, w;
reg [15:0] din;
wire [15:0] dout, dma;
wire intreq, reqr, reqw;
wire [3:0] pid;
reg [15:0] memory[0:32367];
assign { DP, DN } = { dp, dn };
wire tx = (sendcrc & sendcrcen) ? crcout : byte[0];
assign dif = DP & ~DN;
assign #(`USBBIT/4) usbclk4 = usbclken & ~usbclk4;
always @(posedge usbclk4)
if(ack !== 1'b0) begin
ack <= 1'b0;
if(reqw) memory[dma[15:1]] <= dout;
if(reqw) $display("mem[%x] <= %x", dma, dout);
end else if(reqr | reqw) begin
ack <= 1;
if(reqr) din <= memory[dma[15:1]];
if(reqr) $display("%x <= mem[%x]", memory[dma[15:1]], dma);
end
always @(posedge usbclk4)
if(intreq) begin
intack <= 1;
if(!intack) $display("USB IRQ pid %x", pid);
end else begin
intack <= 0;
end
usbphys usbp0(DP, DN, dif0, send0, dp0, dn0);
usbphys usbp1(DP, DN, dif1, send1, dp1, dn1);
usb #(0) usb0(usbclk4, reset, DP, DN, dif0, send0, dp0, dn0,
sel, addr, r, w, dma, reqr, reqw, ack, din, dout,
pid, intreq, intack);
usb #(1) usb1(usbclk4, reset, DP, DN, dif1, send1, dp1, dn1,
0, 0, 0, 0, , , , 0, 0, , , , 0);
always @(negedge usbclk)
begin
if(crcen && (bitstuff != 6))
crc <= { crc[14:0], ~sendcrc } ^
(~sendcrc ^ tx ^ (crc16 ? crc[15] : crc[4])
? 16'h8005 : 16'h0);
olddif <= dif;
end
reg [4:0] bitcount;
reg [3:0] oversample;
reg [7:0] bytein;
reg [2:0] bits;
reg [3:0] eop;
wire se0;
assign se0 = ~(DP | DN);
always @(posedge usbclk4)
begin
oversample <= { oversample[2:0], dif };
bitcount <= bitcount + ~&bitcount;
if(|bitcount[4:2]) begin
if((oversample[2] ^ oversample[0]) && (bitcount[1:0] != 2'b00))
begin
if(bitcount[4:2] != 3'h7 || bitcount == 5'h1F) begin
bytein <= { 1'b0, bytein[7:1] };
bits <= bits + 1;
end
bitcount <= 5'h02;
end
else if((bitcount[1:0] == 2'b11) && |bitcount[4:2] && ~&bitcount[4:2])
begin
bytein <= { 1'b1, bytein[7:1] };
bits <= bits + 1;
end
end
eop <= se0 ? eop + 1 : 0;
if(eop[2]) begin
bits <= 0;
bitcount <= 5'h1F;
end
end
task sendbit;
input bit;
begin
usbclk <= 1;
tx <= bit;
if(bitstuff == 6) begin
{ dp, dn } <= { dn, dp };
bitstuff <= 0;
#(`USBBIT) usbclk <= 0;
#(`USBBIT) usbclk <= 1;
end
if(!bit) begin
{ dp, dn } <= { dn, dp };
bitstuff <= 0;
end else bitstuff <= bitstuff + 1;
#(`USBBIT) usbclk <= 0;
#(`USBBIT) usbclk <= 1;
end
endtask
task sendbyte;
input [7:0] byte;
begin
repeat(8) begin
sendbit(byte[0]);
byte = byte[7:1];
end
end
endtask
task sendpid;
input [3:0] pid;
begin
crc = 0;
sendcrc = 0;
crcen = 0;
{ dp, dn } = 2'b10;
sendbyte(8'h80);
sendbyte({ ~pid, pid });
end
endtask
task eop;
begin
#(`USBBIT*0) { dp, dn } <= 2'b00;
#(`USBBIT*4) { dp, dn } <= 2'b10;
#(`USBBIT*2) { dp, dn } <= 2'bzz;
end
endtask
task sendtoken;
input [3:0] pid;
input [6:0] addr;
input [3:0] endp;
begin
sendpid(pid);
crcen = 1;
crc16 = 0;
repeat(7) begin
sendbit(addr[0]);
addr <= addr[6:1];
end
repeat(4) begin
sendbit(endp[0]);
endp <= endp[3:1];
end
sendcrc = 1;
repeat(5) begin
sendbit(crc[4]);
end
sendcrc = 0;
eop;
end
endtask
task senddata;
input toggle;
input [2:0] count;
input [63:0] data;
begin
sendpid(toggle ? `DATA1 : `DATA0);
crcen = 1;
crc16 = 1;
repeat(count+1) begin
sendbyte(data[63:56]);
data = { data[55:0], 8'h00 };
end
sendcrc = 1;
repeat(16) begin
sendbit(crc[15]);
end
sendcrc = 0;
eop;
end
endtask
task write;
input [1:0] addrin;
input [15:0] data;
begin
@(posedge usbclk4) sel <= 1;
addr <= addrin;
din <= data;
r <= 1'b0;
w <= 2'b11;
@(posedge usbclk4) sel <= 0;
end
endtask
`define SENDTEST
`define RECEIVETEST
initial
begin
$dumpfile("usb.vcd");
$dumpvars();
reset = 0;
sel = 0;
usbclk = 0;
usbclken = 0;
dp = 1'bz;
dn = 1'bz;
bitstuff = 0;
bitcount = 0;
oversample = 0;
bytein = 0;
bits = 0;
eop = 0;
crcen = 0;
crc16 = 0;
sendcrc = 0;
crc = 0;
#100 reset = 1;
usbclken = 1;
`ifdef SENDTEST
#1000 sendtoken(`SOF, 6'h00, 4'h0);
#1000 sendtoken(`SETUP, 6'h12, 4'h3);
write(2, 16'h2000);
write(0, 16'h000B);
#1000 senddata(0, 3'h7, 64'h123456789ABCDEF0);
#1000 sendtoken(`OUT, 6'h7F, 4'hF);
write(2, 16'h3000);
write(0, 16'h0005);
#1000 senddata(1, 3'h7, 64'hFEDCBA9876543210);
`endif
`ifdef RECEIVETEST
#1000 write(1, 16'h1234);
write(2, 16'h5678);
write(0, 16'h5801);
#4000 memory[15'h2B3C] = 16'h1234;
memory[15'h2B3D] = 16'h5678;
memory[15'h2B3E] = 16'h9ABC;
memory[15'h2B3F] = 16'hDEF0;
write(0, 16'h3809);
#10000 write(2, 16'h5678);
write(0, 16'hB806);
#10000 write(0, 16'h3800);
#3000 write(0, 16'h0000);
`endif
$finish;
end
endmodule | module usbtest; |
reg [15:0] crc;
reg crcen, crc16;
reg [2:0] bitstuff;
reg usbclk;
wire usbclk4;
reg usbclken;
reg sendcrc;
wire dif;
reg olddif, tx;
wire DP, DN;
reg dp, dn;
reg reset;
reg sel, r, ack, intack;
reg [1:0] addr, w;
reg [15:0] din;
wire [15:0] dout, dma;
wire intreq, reqr, reqw;
wire [3:0] pid;
reg [15:0] memory[0:32367];
assign { DP, DN } = { dp, dn };
wire tx = (sendcrc & sendcrcen) ? crcout : byte[0];
assign dif = DP & ~DN;
assign #(`USBBIT/4) usbclk4 = usbclken & ~usbclk4;
always @(posedge usbclk4)
if(ack !== 1'b0) begin
ack <= 1'b0;
if(reqw) memory[dma[15:1]] <= dout;
if(reqw) $display("mem[%x] <= %x", dma, dout);
end else if(reqr | reqw) begin
ack <= 1;
if(reqr) din <= memory[dma[15:1]];
if(reqr) $display("%x <= mem[%x]", memory[dma[15:1]], dma);
end
always @(posedge usbclk4)
if(intreq) begin
intack <= 1;
if(!intack) $display("USB IRQ pid %x", pid);
end else begin
intack <= 0;
end
usbphys usbp0(DP, DN, dif0, send0, dp0, dn0);
usbphys usbp1(DP, DN, dif1, send1, dp1, dn1);
usb #(0) usb0(usbclk4, reset, DP, DN, dif0, send0, dp0, dn0,
sel, addr, r, w, dma, reqr, reqw, ack, din, dout,
pid, intreq, intack);
usb #(1) usb1(usbclk4, reset, DP, DN, dif1, send1, dp1, dn1,
0, 0, 0, 0, , , , 0, 0, , , , 0);
always @(negedge usbclk)
begin
if(crcen && (bitstuff != 6))
crc <= { crc[14:0], ~sendcrc } ^
(~sendcrc ^ tx ^ (crc16 ? crc[15] : crc[4])
? 16'h8005 : 16'h0);
olddif <= dif;
end
reg [4:0] bitcount;
reg [3:0] oversample;
reg [7:0] bytein;
reg [2:0] bits;
reg [3:0] eop;
wire se0;
assign se0 = ~(DP | DN);
always @(posedge usbclk4)
begin
oversample <= { oversample[2:0], dif };
bitcount <= bitcount + ~&bitcount;
if(|bitcount[4:2]) begin
if((oversample[2] ^ oversample[0]) && (bitcount[1:0] != 2'b00))
begin
if(bitcount[4:2] != 3'h7 || bitcount == 5'h1F) begin
bytein <= { 1'b0, bytein[7:1] };
bits <= bits + 1;
end
bitcount <= 5'h02;
end
else if((bitcount[1:0] == 2'b11) && |bitcount[4:2] && ~&bitcount[4:2])
begin
bytein <= { 1'b1, bytein[7:1] };
bits <= bits + 1;
end
end
eop <= se0 ? eop + 1 : 0;
if(eop[2]) begin
bits <= 0;
bitcount <= 5'h1F;
end
end
task sendbit;
input bit;
begin
usbclk <= 1;
tx <= bit;
if(bitstuff == 6) begin
{ dp, dn } <= { dn, dp };
bitstuff <= 0;
#(`USBBIT) usbclk <= 0;
#(`USBBIT) usbclk <= 1;
end
if(!bit) begin
{ dp, dn } <= { dn, dp };
bitstuff <= 0;
end else bitstuff <= bitstuff + 1;
#(`USBBIT) usbclk <= 0;
#(`USBBIT) usbclk <= 1;
end
endtask
task sendbyte;
input [7:0] byte;
begin
repeat(8) begin
sendbit(byte[0]);
byte = byte[7:1];
end
end
endtask
task sendpid;
input [3:0] pid;
begin
crc = 0;
sendcrc = 0;
crcen = 0;
{ dp, dn } = 2'b10;
sendbyte(8'h80);
sendbyte({ ~pid, pid });
end
endtask
task eop;
begin
#(`USBBIT*0) { dp, dn } <= 2'b00;
#(`USBBIT*4) { dp, dn } <= 2'b10;
#(`USBBIT*2) { dp, dn } <= 2'bzz;
end
endtask
task sendtoken;
input [3:0] pid;
input [6:0] addr;
input [3:0] endp;
begin
sendpid(pid);
crcen = 1;
crc16 = 0;
repeat(7) begin
sendbit(addr[0]);
addr <= addr[6:1];
end
repeat(4) begin
sendbit(endp[0]);
endp <= endp[3:1];
end
sendcrc = 1;
repeat(5) begin
sendbit(crc[4]);
end
sendcrc = 0;
eop;
end
endtask
task senddata;
input toggle;
input [2:0] count;
input [63:0] data;
begin
sendpid(toggle ? `DATA1 : `DATA0);
crcen = 1;
crc16 = 1;
repeat(count+1) begin
sendbyte(data[63:56]);
data = { data[55:0], 8'h00 };
end
sendcrc = 1;
repeat(16) begin
sendbit(crc[15]);
end
sendcrc = 0;
eop;
end
endtask
task write;
input [1:0] addrin;
input [15:0] data;
begin
@(posedge usbclk4) sel <= 1;
addr <= addrin;
din <= data;
r <= 1'b0;
w <= 2'b11;
@(posedge usbclk4) sel <= 0;
end
endtask
`define SENDTEST
`define RECEIVETEST
initial
begin
$dumpfile("usb.vcd");
$dumpvars();
reset = 0;
sel = 0;
usbclk = 0;
usbclken = 0;
dp = 1'bz;
dn = 1'bz;
bitstuff = 0;
bitcount = 0;
oversample = 0;
bytein = 0;
bits = 0;
eop = 0;
crcen = 0;
crc16 = 0;
sendcrc = 0;
crc = 0;
#100 reset = 1;
usbclken = 1;
`ifdef SENDTEST
#1000 sendtoken(`SOF, 6'h00, 4'h0);
#1000 sendtoken(`SETUP, 6'h12, 4'h3);
write(2, 16'h2000);
write(0, 16'h000B);
#1000 senddata(0, 3'h7, 64'h123456789ABCDEF0);
#1000 sendtoken(`OUT, 6'h7F, 4'hF);
write(2, 16'h3000);
write(0, 16'h0005);
#1000 senddata(1, 3'h7, 64'hFEDCBA9876543210);
`endif
`ifdef RECEIVETEST
#1000 write(1, 16'h1234);
write(2, 16'h5678);
write(0, 16'h5801);
#4000 memory[15'h2B3C] = 16'h1234;
memory[15'h2B3D] = 16'h5678;
memory[15'h2B3E] = 16'h9ABC;
memory[15'h2B3F] = 16'hDEF0;
write(0, 16'h3809);
#10000 write(2, 16'h5678);
write(0, 16'hB806);
#10000 write(0, 16'h3800);
#3000 write(0, 16'h0000);
`endif
$finish;
end
endmodule | 2 |
142,189 | data/full_repos/permissive/97630563/usbphys.v | 97,630,563 | usbphys.v | v | 12 | 50 | [] | [] | [] | [(3, 11)] | null | data/verilator_xmls/dc284c34-1bf1-42b3-91ce-e78c8ff9c463.xml | null | 313,174 | module | module usbphys(DP, DN, dif, send, dp, dn);
inout DP, DN;
output dif;
input send, dp, dn;
assign dif = DP & ~DN;
assign { DP, DN } = send ? { dp, dn } : 2'bzz;
endmodule | module usbphys(DP, DN, dif, send, dp, dn); |
inout DP, DN;
output dif;
input send, dp, dn;
assign dif = DP & ~DN;
assign { DP, DN } = send ? { dp, dn } : 2'bzz;
endmodule | 2 |
142,191 | data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v | 97,859,536 | Mult_Dadda16.v | v | 547 | 71 | [] | [] | [] | [(3, 547)] | null | null | 1: b"%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:273: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA1 (P[0][13], P[1][12], S[1], Cout[1]);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.v\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.sv\n Half_Adder\n Half_Adder.v\n Half_Adder.sv\n obj_dir/Half_Adder\n obj_dir/Half_Adder.v\n obj_dir/Half_Adder.sv\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:274: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA1 (P[0][14], P[1][13], P[2][12], S[2], Cout[2]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:275: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA2 (P[3][11], P[4][10], S[3], Cout[3]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:276: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA2 (P[0][15], P[1][14], P[2][13], S[4], Cout[4]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:277: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA3 (P[3][12], P[4][11], P[5][10], S[5], Cout[5]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:278: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA3 (P[6][9], P[7][8], S[6], Cout[6]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:279: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA4 (P[1][15], P[2][14], P[3][13], S[7], Cout[7]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:280: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA5 (P[4][12], P[5][11], P[6][10], S[8], Cout[8]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:281: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA4 (P[7][9], P[8][8], S[9], Cout[9]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:282: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA6 (P[2][15], P[3][14], P[4][13], S[10], Cout[10]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:283: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA7 (P[5][12], P[6][11], P[7][10], S[11], Cout[11]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:284: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA8 (P[3][15], P[4][14], P[5][13], S[12], Cout[12]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:285: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA5 (P[0][9], P[1][8], S[13], Cout[13]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:286: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA9 (P[0][10], P[1][9], P[2][8], S[14], Cout[14]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:287: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA6 (P[3][7], P[4][6], S[15], Cout[15]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:288: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA10 (P[0][11], P[1][10], P[2][9], S[16], Cout[16]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:289: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA11 (P[3][8], P[4][7], P[5][6], S[17], Cout[17]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:290: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA7 (P[6][5], P[7][4], S[18], Cout[18]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:291: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA12 (P[0][12], P[1][11], P[2][10], S[19], Cout[19]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:292: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA13 (P[3][9], P[4][8], P[5][7], S[20], Cout[20]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:293: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA14 (P[6][6], P[7][5], P[8][4], S[21], Cout[21]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:294: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA8 (P[9][3], P[10][2], S[22], Cout[22]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:295: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA15 (P[2][11], P[3][10], P[4][9], S[23], Cout[23]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:296: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA16 (P[5][8], P[6][7], P[7][6], S[24], Cout[24]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:297: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA17 (P[8][5], P[9][4], P[10][3], S[25], Cout[25]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:298: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA18 (P[11][2], P[12][1], P[13][0], S[26], Cout[26]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:299: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA19 (P[5][9], P[6][8], P[7][7], S[27], Cout[27]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:300: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA20 (P[8][6], P[9][5], P[10][4], S[28], Cout[28]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:301: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA21 (P[11][3], P[12][2], P[13][1], S[29], Cout[29]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:302: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA22 (P[14][0], Cout[1], S[2], S[30], Cout[30]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:303: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA23 (P[8][7], P[9][6], P[10][5], S[31], Cout[31]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:304: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA24 (P[11][4], P[12][3], P[13][2], S[32], Cout[32]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:305: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA25 (P[14][1], P[15][0], Cout[2], S[33], Cout[33]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:306: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA26 (Cout[3], S[4], S[5], S[34], Cout[34]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:307: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA27 (P[9][7], P[10][6], P[11][5], S[35], Cout[35]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:308: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA28 (P[12][4], P[13][3], P[14][2], S[36], Cout[36]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:309: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA29 (P[15][1], Cout[4], Cout[5], S[37], Cout[37]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:310: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA30 (Cout[6], S[7], S[8], S[38], Cout[38]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:311: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA31 (P[8][9], P[9][8], P[10][7], S[39], Cout[39]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:312: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA32 (P[11][6], P[12][5], P[13][4], S[40], Cout[40]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:313: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA33 (P[14][3], P[15][2], Cout[7], S[41], Cout[41]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:314: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA34 (Cout[8], Cout[9], S[10], S[42], Cout[42]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:315: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA35 (P[6][12], P[7][11], P[8][10], S[43], Cout[43]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:316: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA36 (P[9][9], P[10][8], P[11][7], S[44], Cout[44]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:317: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA37 (P[12][6], P[13][5], P[14][4], S[45], Cout[45]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:318: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA38 (P[15][3], Cout[10], Cout[11], S[46], Cout[46]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:319: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA39 (P[4][15], P[5][14], P[6][13], S[47], Cout[47]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:320: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA40 (P[7][12], P[8][11], P[9][10], S[48], Cout[48]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:321: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA41 (P[10][9], P[11][8], P[12][7], S[49], Cout[49]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda16.v:322: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA42 (P[13][6], P[14][5], P[15][4], S[50], Cout[50]);\n^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 313,181 | module | module Mult_Dadda16 # (
parameter N = 16
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
);
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[0][4] = x[0] & y[4];
assign P[0][5] = x[0] & y[5];
assign P[0][6] = x[0] & y[6];
assign P[0][7] = x[0] & y[7];
assign P[0][8] = x[0] & y[8];
assign P[0][9] = x[0] & y[9];
assign P[0][10] = x[0] & y[10];
assign P[0][11] = x[0] & y[11];
assign P[0][12] = x[0] & y[12];
assign P[0][13] = x[0] & y[13];
assign P[0][14] = x[0] & y[14];
assign P[0][15] = x[0] & y[15];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[1][4] = x[1] & y[4];
assign P[1][5] = x[1] & y[5];
assign P[1][6] = x[1] & y[6];
assign P[1][7] = x[1] & y[7];
assign P[1][8] = x[1] & y[8];
assign P[1][9] = x[1] & y[9];
assign P[1][10] = x[1] & y[10];
assign P[1][11] = x[1] & y[11];
assign P[1][12] = x[1] & y[12];
assign P[1][13] = x[1] & y[13];
assign P[1][14] = x[1] & y[14];
assign P[1][15] = x[1] & y[15];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[2][4] = x[2] & y[4];
assign P[2][5] = x[2] & y[5];
assign P[2][6] = x[2] & y[6];
assign P[2][7] = x[2] & y[7];
assign P[2][8] = x[2] & y[8];
assign P[2][9] = x[2] & y[9];
assign P[2][10] = x[2] & y[10];
assign P[2][11] = x[2] & y[11];
assign P[2][12] = x[2] & y[12];
assign P[2][13] = x[2] & y[13];
assign P[2][14] = x[2] & y[14];
assign P[2][15] = x[2] & y[15];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
assign P[3][4] = x[3] & y[4];
assign P[3][5] = x[3] & y[5];
assign P[3][6] = x[3] & y[6];
assign P[3][7] = x[3] & y[7];
assign P[3][8] = x[3] & y[8];
assign P[3][9] = x[3] & y[9];
assign P[3][10] = x[3] & y[10];
assign P[3][11] = x[3] & y[11];
assign P[3][12] = x[3] & y[12];
assign P[3][13] = x[3] & y[13];
assign P[3][14] = x[3] & y[14];
assign P[3][15] = x[3] & y[15];
assign P[4][0] = x[4] & y[0];
assign P[4][1] = x[4] & y[1];
assign P[4][2] = x[4] & y[2];
assign P[4][3] = x[4] & y[3];
assign P[4][4] = x[4] & y[4];
assign P[4][5] = x[4] & y[5];
assign P[4][6] = x[4] & y[6];
assign P[4][7] = x[4] & y[7];
assign P[4][8] = x[4] & y[8];
assign P[4][9] = x[4] & y[9];
assign P[4][10] = x[4] & y[10];
assign P[4][11] = x[4] & y[11];
assign P[4][12] = x[4] & y[12];
assign P[4][13] = x[4] & y[13];
assign P[4][14] = x[4] & y[14];
assign P[4][15] = x[4] & y[15];
assign P[5][0] = x[5] & y[0];
assign P[5][1] = x[5] & y[1];
assign P[5][2] = x[5] & y[2];
assign P[5][3] = x[5] & y[3];
assign P[5][4] = x[5] & y[4];
assign P[5][5] = x[5] & y[5];
assign P[5][6] = x[5] & y[6];
assign P[5][7] = x[5] & y[7];
assign P[5][8] = x[5] & y[8];
assign P[5][9] = x[5] & y[9];
assign P[5][10] = x[5] & y[10];
assign P[5][11] = x[5] & y[11];
assign P[5][12] = x[5] & y[12];
assign P[5][13] = x[5] & y[13];
assign P[5][14] = x[5] & y[14];
assign P[5][15] = x[5] & y[15];
assign P[6][0] = x[6] & y[0];
assign P[6][1] = x[6] & y[1];
assign P[6][2] = x[6] & y[2];
assign P[6][3] = x[6] & y[3];
assign P[6][4] = x[6] & y[4];
assign P[6][5] = x[6] & y[5];
assign P[6][6] = x[6] & y[6];
assign P[6][7] = x[6] & y[7];
assign P[6][8] = x[6] & y[8];
assign P[6][9] = x[6] & y[9];
assign P[6][10] = x[6] & y[10];
assign P[6][11] = x[6] & y[11];
assign P[6][12] = x[6] & y[12];
assign P[6][13] = x[6] & y[13];
assign P[6][14] = x[6] & y[14];
assign P[6][15] = x[6] & y[15];
assign P[7][0] = x[7] & y[0];
assign P[7][1] = x[7] & y[1];
assign P[7][2] = x[7] & y[2];
assign P[7][3] = x[7] & y[3];
assign P[7][4] = x[7] & y[4];
assign P[7][5] = x[7] & y[5];
assign P[7][6] = x[7] & y[6];
assign P[7][7] = x[7] & y[7];
assign P[7][8] = x[7] & y[8];
assign P[7][9] = x[7] & y[9];
assign P[7][10] = x[7] & y[10];
assign P[7][11] = x[7] & y[11];
assign P[7][12] = x[7] & y[12];
assign P[7][13] = x[7] & y[13];
assign P[7][14] = x[7] & y[14];
assign P[7][15] = x[7] & y[15];
assign P[8][0] = x[8] & y[0];
assign P[8][1] = x[8] & y[1];
assign P[8][2] = x[8] & y[2];
assign P[8][3] = x[8] & y[3];
assign P[8][4] = x[8] & y[4];
assign P[8][5] = x[8] & y[5];
assign P[8][6] = x[8] & y[6];
assign P[8][7] = x[8] & y[7];
assign P[8][8] = x[8] & y[8];
assign P[8][9] = x[8] & y[9];
assign P[8][10] = x[8] & y[10];
assign P[8][11] = x[8] & y[11];
assign P[8][12] = x[8] & y[12];
assign P[8][13] = x[8] & y[13];
assign P[8][14] = x[8] & y[14];
assign P[8][15] = x[8] & y[15];
assign P[9][0] = x[9] & y[0];
assign P[9][1] = x[9] & y[1];
assign P[9][2] = x[9] & y[2];
assign P[9][3] = x[9] & y[3];
assign P[9][4] = x[9] & y[4];
assign P[9][5] = x[9] & y[5];
assign P[9][6] = x[9] & y[6];
assign P[9][7] = x[9] & y[7];
assign P[9][8] = x[9] & y[8];
assign P[9][9] = x[9] & y[9];
assign P[9][10] = x[9] & y[10];
assign P[9][11] = x[9] & y[11];
assign P[9][12] = x[9] & y[12];
assign P[9][13] = x[9] & y[13];
assign P[9][14] = x[9] & y[14];
assign P[9][15] = x[9] & y[15];
assign P[10][0] = x[10] & y[0];
assign P[10][1] = x[10] & y[1];
assign P[10][2] = x[10] & y[2];
assign P[10][3] = x[10] & y[3];
assign P[10][4] = x[10] & y[4];
assign P[10][5] = x[10] & y[5];
assign P[10][6] = x[10] & y[6];
assign P[10][7] = x[10] & y[7];
assign P[10][8] = x[10] & y[8];
assign P[10][9] = x[10] & y[9];
assign P[10][10] = x[10] & y[10];
assign P[10][11] = x[10] & y[11];
assign P[10][12] = x[10] & y[12];
assign P[10][13] = x[10] & y[13];
assign P[10][14] = x[10] & y[14];
assign P[10][15] = x[10] & y[15];
assign P[11][0] = x[11] & y[0];
assign P[11][1] = x[11] & y[1];
assign P[11][2] = x[11] & y[2];
assign P[11][3] = x[11] & y[3];
assign P[11][4] = x[11] & y[4];
assign P[11][5] = x[11] & y[5];
assign P[11][6] = x[11] & y[6];
assign P[11][7] = x[11] & y[7];
assign P[11][8] = x[11] & y[8];
assign P[11][9] = x[11] & y[9];
assign P[11][10] = x[11] & y[10];
assign P[11][11] = x[11] & y[11];
assign P[11][12] = x[11] & y[12];
assign P[11][13] = x[11] & y[13];
assign P[11][14] = x[11] & y[14];
assign P[11][15] = x[11] & y[15];
assign P[12][0] = x[12] & y[0];
assign P[12][1] = x[12] & y[1];
assign P[12][2] = x[12] & y[2];
assign P[12][3] = x[12] & y[3];
assign P[12][4] = x[12] & y[4];
assign P[12][5] = x[12] & y[5];
assign P[12][6] = x[12] & y[6];
assign P[12][7] = x[12] & y[7];
assign P[12][8] = x[12] & y[8];
assign P[12][9] = x[12] & y[9];
assign P[12][10] = x[12] & y[10];
assign P[12][11] = x[12] & y[11];
assign P[12][12] = x[12] & y[12];
assign P[12][13] = x[12] & y[13];
assign P[12][14] = x[12] & y[14];
assign P[12][15] = x[12] & y[15];
assign P[13][0] = x[13] & y[0];
assign P[13][1] = x[13] & y[1];
assign P[13][2] = x[13] & y[2];
assign P[13][3] = x[13] & y[3];
assign P[13][4] = x[13] & y[4];
assign P[13][5] = x[13] & y[5];
assign P[13][6] = x[13] & y[6];
assign P[13][7] = x[13] & y[7];
assign P[13][8] = x[13] & y[8];
assign P[13][9] = x[13] & y[9];
assign P[13][10] = x[13] & y[10];
assign P[13][11] = x[13] & y[11];
assign P[13][12] = x[13] & y[12];
assign P[13][13] = x[13] & y[13];
assign P[13][14] = x[13] & y[14];
assign P[13][15] = x[13] & y[15];
assign P[14][0] = x[14] & y[0];
assign P[14][1] = x[14] & y[1];
assign P[14][2] = x[14] & y[2];
assign P[14][3] = x[14] & y[3];
assign P[14][4] = x[14] & y[4];
assign P[14][5] = x[14] & y[5];
assign P[14][6] = x[14] & y[6];
assign P[14][7] = x[14] & y[7];
assign P[14][8] = x[14] & y[8];
assign P[14][9] = x[14] & y[9];
assign P[14][10] = x[14] & y[10];
assign P[14][11] = x[14] & y[11];
assign P[14][12] = x[14] & y[12];
assign P[14][13] = x[14] & y[13];
assign P[14][14] = x[14] & y[14];
assign P[14][15] = x[14] & y[15];
assign P[15][0] = x[15] & y[0];
assign P[15][1] = x[15] & y[1];
assign P[15][2] = x[15] & y[2];
assign P[15][3] = x[15] & y[3];
assign P[15][4] = x[15] & y[4];
assign P[15][5] = x[15] & y[5];
assign P[15][6] = x[15] & y[6];
assign P[15][7] = x[15] & y[7];
assign P[15][8] = x[15] & y[8];
assign P[15][9] = x[15] & y[9];
assign P[15][10] = x[15] & y[10];
assign P[15][11] = x[15] & y[11];
assign P[15][12] = x[15] & y[12];
assign P[15][13] = x[15] & y[13];
assign P[15][14] = x[15] & y[14];
assign P[15][15] = x[15] & y[15];
wire [240:0] S;
wire [240:0] Cout;
Half_Adder HA1 (P[0][13], P[1][12], S[1], Cout[1]);
Full_Adder FA1 (P[0][14], P[1][13], P[2][12], S[2], Cout[2]);
Half_Adder HA2 (P[3][11], P[4][10], S[3], Cout[3]);
Full_Adder FA2 (P[0][15], P[1][14], P[2][13], S[4], Cout[4]);
Full_Adder FA3 (P[3][12], P[4][11], P[5][10], S[5], Cout[5]);
Half_Adder HA3 (P[6][9], P[7][8], S[6], Cout[6]);
Full_Adder FA4 (P[1][15], P[2][14], P[3][13], S[7], Cout[7]);
Full_Adder FA5 (P[4][12], P[5][11], P[6][10], S[8], Cout[8]);
Half_Adder HA4 (P[7][9], P[8][8], S[9], Cout[9]);
Full_Adder FA6 (P[2][15], P[3][14], P[4][13], S[10], Cout[10]);
Full_Adder FA7 (P[5][12], P[6][11], P[7][10], S[11], Cout[11]);
Full_Adder FA8 (P[3][15], P[4][14], P[5][13], S[12], Cout[12]);
Half_Adder HA5 (P[0][9], P[1][8], S[13], Cout[13]);
Full_Adder FA9 (P[0][10], P[1][9], P[2][8], S[14], Cout[14]);
Half_Adder HA6 (P[3][7], P[4][6], S[15], Cout[15]);
Full_Adder FA10 (P[0][11], P[1][10], P[2][9], S[16], Cout[16]);
Full_Adder FA11 (P[3][8], P[4][7], P[5][6], S[17], Cout[17]);
Half_Adder HA7 (P[6][5], P[7][4], S[18], Cout[18]);
Full_Adder FA12 (P[0][12], P[1][11], P[2][10], S[19], Cout[19]);
Full_Adder FA13 (P[3][9], P[4][8], P[5][7], S[20], Cout[20]);
Full_Adder FA14 (P[6][6], P[7][5], P[8][4], S[21], Cout[21]);
Half_Adder HA8 (P[9][3], P[10][2], S[22], Cout[22]);
Full_Adder FA15 (P[2][11], P[3][10], P[4][9], S[23], Cout[23]);
Full_Adder FA16 (P[5][8], P[6][7], P[7][6], S[24], Cout[24]);
Full_Adder FA17 (P[8][5], P[9][4], P[10][3], S[25], Cout[25]);
Full_Adder FA18 (P[11][2], P[12][1], P[13][0], S[26], Cout[26]);
Full_Adder FA19 (P[5][9], P[6][8], P[7][7], S[27], Cout[27]);
Full_Adder FA20 (P[8][6], P[9][5], P[10][4], S[28], Cout[28]);
Full_Adder FA21 (P[11][3], P[12][2], P[13][1], S[29], Cout[29]);
Full_Adder FA22 (P[14][0], Cout[1], S[2], S[30], Cout[30]);
Full_Adder FA23 (P[8][7], P[9][6], P[10][5], S[31], Cout[31]);
Full_Adder FA24 (P[11][4], P[12][3], P[13][2], S[32], Cout[32]);
Full_Adder FA25 (P[14][1], P[15][0], Cout[2], S[33], Cout[33]);
Full_Adder FA26 (Cout[3], S[4], S[5], S[34], Cout[34]);
Full_Adder FA27 (P[9][7], P[10][6], P[11][5], S[35], Cout[35]);
Full_Adder FA28 (P[12][4], P[13][3], P[14][2], S[36], Cout[36]);
Full_Adder FA29 (P[15][1], Cout[4], Cout[5], S[37], Cout[37]);
Full_Adder FA30 (Cout[6], S[7], S[8], S[38], Cout[38]);
Full_Adder FA31 (P[8][9], P[9][8], P[10][7], S[39], Cout[39]);
Full_Adder FA32 (P[11][6], P[12][5], P[13][4], S[40], Cout[40]);
Full_Adder FA33 (P[14][3], P[15][2], Cout[7], S[41], Cout[41]);
Full_Adder FA34 (Cout[8], Cout[9], S[10], S[42], Cout[42]);
Full_Adder FA35 (P[6][12], P[7][11], P[8][10], S[43], Cout[43]);
Full_Adder FA36 (P[9][9], P[10][8], P[11][7], S[44], Cout[44]);
Full_Adder FA37 (P[12][6], P[13][5], P[14][4], S[45], Cout[45]);
Full_Adder FA38 (P[15][3], Cout[10], Cout[11], S[46], Cout[46]);
Full_Adder FA39 (P[4][15], P[5][14], P[6][13], S[47], Cout[47]);
Full_Adder FA40 (P[7][12], P[8][11], P[9][10], S[48], Cout[48]);
Full_Adder FA41 (P[10][9], P[11][8], P[12][7], S[49], Cout[49]);
Full_Adder FA42 (P[13][6], P[14][5], P[15][4], S[50], Cout[50]);
Full_Adder FA43 (P[5][15], P[6][14], P[7][13], S[51], Cout[51]);
Full_Adder FA44 (P[8][12], P[9][11], P[10][10], S[52], Cout[52]);
Full_Adder FA45 (P[11][9], P[12][8], P[13][7], S[53], Cout[53]);
Full_Adder FA46 (P[6][15], P[7][14], P[8][13], S[54], Cout[54]);
Full_Adder FA47 (P[9][12], P[10][11], P[11][10], S[55], Cout[55]);
Full_Adder FA48 (P[7][15], P[8][14], P[9][13], S[56], Cout[56]);
Half_Adder HA9 (P[0][6], P[1][5], S[57], Cout[57]);
Full_Adder FA49 (P[0][7], P[1][6], P[2][5], S[58], Cout[58]);
Half_Adder HA10 (P[3][4], P[4][3], S[59], Cout[59]);
Full_Adder FA50 (P[0][8], P[1][7], P[2][6], S[60], Cout[60]);
Full_Adder FA51 (P[3][5], P[4][4], P[5][3], S[61], Cout[61]);
Half_Adder HA11 (P[6][2], P[7][1], S[62], Cout[62]);
Full_Adder FA52 (P[2][7], P[3][6], P[4][5], S[63], Cout[63]);
Full_Adder FA53 (P[5][4], P[6][3], P[7][2], S[64], Cout[64]);
Full_Adder FA54 (P[8][1], P[9][0], S[13], S[65], Cout[65]);
Full_Adder FA55 (P[5][5], P[6][4], P[7][3], S[66], Cout[66]);
Full_Adder FA56 (P[8][2], P[9][1], P[10][0], S[67], Cout[67]);
Full_Adder FA57 (Cout[13], S[14], S[15], S[68], Cout[68]);
Full_Adder FA58 (P[8][3], P[9][2], P[10][1], S[69], Cout[69]);
Full_Adder FA59 (P[11][0], Cout[14], Cout[15], S[70], Cout[70]);
Full_Adder FA60 (S[16], S[17], S[18], S[71], Cout[71]);
Full_Adder FA61 (P[11][1], P[12][0], Cout[16], S[72], Cout[72]);
Full_Adder FA62 (Cout[17], Cout[18], S[19], S[73], Cout[73]);
Full_Adder FA63 (S[20], S[21], S[22], S[74], Cout[74]);
Full_Adder FA64 (S[1], Cout[19], Cout[20], S[75], Cout[75]);
Full_Adder FA65 (Cout[21], Cout[22], S[23], S[76], Cout[76]);
Full_Adder FA66 (S[24], S[25], S[26], S[77], Cout[77]);
Full_Adder FA67 (S[3], Cout[23], Cout[24], S[78], Cout[78]);
Full_Adder FA68 (Cout[25], Cout[26], S[27], S[79], Cout[79]);
Full_Adder FA69 (S[28], S[29], S[30], S[80], Cout[80]);
Full_Adder FA70 (S[6], Cout[27], Cout[28], S[81], Cout[81]);
Full_Adder FA71 (Cout[29], Cout[30], S[31], S[82], Cout[82]);
Full_Adder FA72 (S[32], S[33], S[34], S[83], Cout[83]);
Full_Adder FA73 (S[9], Cout[31], Cout[32], S[84], Cout[84]);
Full_Adder FA74 (Cout[33], Cout[34], S[35], S[85], Cout[85]);
Full_Adder FA75 (S[36], S[37], S[38], S[86], Cout[86]);
Full_Adder FA76 (S[11], Cout[35], Cout[36], S[87], Cout[87]);
Full_Adder FA77 (Cout[37], Cout[38], S[39], S[88], Cout[88]);
Full_Adder FA78 (S[40], S[41], S[42], S[89], Cout[89]);
Full_Adder FA79 (S[12], Cout[39], Cout[40], S[90], Cout[90]);
Full_Adder FA80 (Cout[41], Cout[42], S[43], S[91], Cout[91]);
Full_Adder FA81 (S[44], S[45], S[46], S[92], Cout[92]);
Full_Adder FA82 (Cout[12], Cout[43], Cout[44], S[93], Cout[93]);
Full_Adder FA83 (Cout[45], Cout[46], S[47], S[94], Cout[94]);
Full_Adder FA84 (S[48], S[49], S[50], S[95], Cout[95]);
Full_Adder FA85 (P[14][6], P[15][5], Cout[47], S[96], Cout[96]);
Full_Adder FA86 (Cout[48], Cout[49], Cout[50], S[97], Cout[97]);
Full_Adder FA87 (S[51], S[52], S[53], S[98], Cout[98]);
Full_Adder FA88 (P[12][9], P[13][8], P[14][7], S[99], Cout[99]);
Full_Adder FA89 (P[15][6], Cout[51], Cout[52], S[100], Cout[100]);
Full_Adder FA90 (Cout[53], S[54], S[55], S[101], Cout[101]);
Full_Adder FA91 (P[10][12], P[11][11], P[12][10], S[102], Cout[102]);
Full_Adder FA92 (P[13][9], P[14][8], P[15][7], S[103], Cout[103]);
Full_Adder FA93 (Cout[54], Cout[55], S[56], S[104], Cout[104]);
Full_Adder FA94 (P[8][15], P[9][14], P[10][13], S[105], Cout[105]);
Full_Adder FA95 (P[11][12], P[12][11], P[13][10], S[106], Cout[106]);
Full_Adder FA96 (P[14][9], P[15][8], Cout[56], S[107], Cout[107]);
Full_Adder FA97 (P[9][15], P[10][14], P[11][13], S[108], Cout[108]);
Full_Adder FA98 (P[12][12], P[13][11], P[14][10], S[109], Cout[109]);
Full_Adder FA99 (P[10][15], P[11][14], P[12][13], S[110], Cout[110]);
Half_Adder HA12 (P[0][4], P[1][3], S[111], Cout[111]);
Full_Adder FA100 (P[0][5], P[1][4], P[2][3], S[112], Cout[112]);
Half_Adder HA13 (P[3][2], P[4][1], S[113], Cout[113]);
Full_Adder FA101 (P[2][4], P[3][3], P[4][2], S[114], Cout[114]);
Full_Adder FA102 (P[5][1], P[6][0], S[57], S[115], Cout[115]);
Full_Adder FA103 (P[5][2], P[6][1], P[7][0], S[116], Cout[116]);
Full_Adder FA104 (Cout[57], S[58], S[59], S[117], Cout[117]);
Full_Adder FA105 (P[8][0], Cout[58], Cout[59], S[118], Cout[118]);
Full_Adder FA106 (S[60], S[61], S[62], S[119], Cout[119]);
Full_Adder FA107 (Cout[60], Cout[61], Cout[62], S[120], Cout[120]);
Full_Adder FA108 (S[63], S[64], S[65], S[121], Cout[121]);
Full_Adder FA109 (Cout[63], Cout[64], Cout[65], S[122], Cout[122]);
Full_Adder FA110 (S[66], S[67], S[68], S[123], Cout[123]);
Full_Adder FA111 (Cout[66], Cout[67], Cout[68], S[124], Cout[124]);
Full_Adder FA112 (S[69], S[70], S[71], S[125], Cout[125]);
Full_Adder FA113 (Cout[69], Cout[70], Cout[71], S[126], Cout[126]);
Full_Adder FA114 (S[72], S[73], S[74], S[127], Cout[127]);
Full_Adder FA115 (Cout[72], Cout[73], Cout[74], S[128], Cout[128]);
Full_Adder FA116 (S[75], S[76], S[77], S[129], Cout[129]);
Full_Adder FA117 (Cout[75], Cout[76], Cout[77], S[130], Cout[130]);
Full_Adder FA118 (S[78], S[79], S[80], S[131], Cout[131]);
Full_Adder FA119 (Cout[78], Cout[79], Cout[80], S[132], Cout[132]);
Full_Adder FA120 (S[81], S[82], S[83], S[133], Cout[133]);
Full_Adder FA121 (Cout[81], Cout[82], Cout[83], S[134], Cout[134]);
Full_Adder FA122 (S[84], S[85], S[86], S[135], Cout[135]);
Full_Adder FA123 (Cout[84], Cout[85], Cout[86], S[136], Cout[136]);
Full_Adder FA124 (S[87], S[88], S[89], S[137], Cout[137]);
Full_Adder FA125 (Cout[87], Cout[88], Cout[89], S[138], Cout[138]);
Full_Adder FA126 (S[90], S[91], S[92], S[139], Cout[139]);
Full_Adder FA127 (Cout[90], Cout[91], Cout[92], S[140], Cout[140]);
Full_Adder FA128 (S[93], S[94], S[95], S[141], Cout[141]);
Full_Adder FA129 (Cout[93], Cout[94], Cout[95], S[142], Cout[142]);
Full_Adder FA130 (S[96], S[97], S[98], S[143], Cout[143]);
Full_Adder FA131 (Cout[96], Cout[97], Cout[98], S[144], Cout[144]);
Full_Adder FA132 (S[99], S[100], S[101], S[145], Cout[145]);
Full_Adder FA133 (Cout[99], Cout[100], Cout[101], S[146], Cout[146]);
Full_Adder FA134 (S[102], S[103], S[104], S[147], Cout[147]);
Full_Adder FA135 (Cout[102], Cout[103], Cout[104], S[148], Cout[148]);
Full_Adder FA136 (S[105], S[106], S[107], S[149], Cout[149]);
Full_Adder FA137 (P[15][9], Cout[105], Cout[106], S[150], Cout[150]);
Full_Adder FA138 (Cout[107], S[108], S[109], S[151], Cout[151]);
Full_Adder FA139 (P[13][12], P[14][11], P[15][10], S[152], Cout[152]);
Full_Adder FA140 (Cout[108], Cout[109], S[110], S[153], Cout[153]);
Full_Adder FA141 (P[11][15], P[12][14], P[13][13], S[154], Cout[154]);
Full_Adder FA142 (P[14][12], P[15][11], Cout[110], S[155], Cout[155]);
Full_Adder FA143 (P[12][15], P[13][14], P[14][13], S[156], Cout[156]);
Half_Adder HA14 (P[0][3], P[1][2], S[157], Cout[157]);
Full_Adder FA144 (P[2][2], P[3][1], P[4][0], S[158], Cout[158]);
Full_Adder FA145 (P[5][0], Cout[111], S[112], S[159], Cout[159]);
Full_Adder FA146 (Cout[112], Cout[113], S[114], S[160], Cout[160]);
Full_Adder FA147 (Cout[114], Cout[115], S[116], S[161], Cout[161]);
Full_Adder FA148 (Cout[116], Cout[117], S[118], S[162], Cout[162]);
Full_Adder FA149 (Cout[118], Cout[119], S[120], S[163], Cout[163]);
Full_Adder FA150 (Cout[120], Cout[121], S[122], S[164], Cout[164]);
Full_Adder FA151 (Cout[122], Cout[123], S[124], S[165], Cout[165]);
Full_Adder FA152 (Cout[124], Cout[125], S[126], S[166], Cout[166]);
Full_Adder FA153 (Cout[126], Cout[127], S[128], S[167], Cout[167]);
Full_Adder FA154 (Cout[128], Cout[129], S[130], S[168], Cout[168]);
Full_Adder FA155 (Cout[130], Cout[131], S[132], S[169], Cout[169]);
Full_Adder FA156 (Cout[132], Cout[133], S[134], S[170], Cout[170]);
Full_Adder FA157 (Cout[134], Cout[135], S[136], S[171], Cout[171]);
Full_Adder FA158 (Cout[136], Cout[137], S[138], S[172], Cout[172]);
Full_Adder FA159 (Cout[138], Cout[139], S[140], S[173], Cout[173]);
Full_Adder FA160 (Cout[140], Cout[141], S[142], S[174], Cout[174]);
Full_Adder FA161 (Cout[142], Cout[143], S[144], S[175], Cout[175]);
Full_Adder FA162 (Cout[144], Cout[145], S[146], S[176], Cout[176]);
Full_Adder FA163 (Cout[146], Cout[147], S[148], S[177], Cout[177]);
Full_Adder FA164 (Cout[148], Cout[149], S[150], S[178], Cout[178]);
Full_Adder FA165 (Cout[150], Cout[151], S[152], S[179], Cout[179]);
Full_Adder FA166 (Cout[152], Cout[153], S[154], S[180], Cout[180]);
Full_Adder FA167 (P[15][12], Cout[154], Cout[155], S[181], Cout[181]);
Full_Adder FA168 (P[13][15], P[14][14], P[15][13], S[182], Cout[182]);
Half_Adder HA15 (P[0][2], P[1][1], S[183], Cout[183]);
Full_Adder FA169 (P[2][1], P[3][0], S[157], S[184], Cout[184]);
Full_Adder FA170 (S[111], Cout[157], S[158], S[185], Cout[185]);
Full_Adder FA171 (S[113], Cout[158], S[159], S[186], Cout[186]);
Full_Adder FA172 (S[115], Cout[159], S[160], S[187], Cout[187]);
Full_Adder FA173 (S[117], Cout[160], S[161], S[188], Cout[188]);
Full_Adder FA174 (S[119], Cout[161], S[162], S[189], Cout[189]);
Full_Adder FA175 (S[121], Cout[162], S[163], S[190], Cout[190]);
Full_Adder FA176 (S[123], Cout[163], S[164], S[191], Cout[191]);
Full_Adder FA177 (S[125], Cout[164], S[165], S[192], Cout[192]);
Full_Adder FA178 (S[127], Cout[165], S[166], S[193], Cout[193]);
Full_Adder FA179 (S[129], Cout[166], S[167], S[194], Cout[194]);
Full_Adder FA180 (S[131], Cout[167], S[168], S[195], Cout[195]);
Full_Adder FA181 (S[133], Cout[168], S[169], S[196], Cout[196]);
Full_Adder FA182 (S[135], Cout[169], S[170], S[197], Cout[197]);
Full_Adder FA183 (S[137], Cout[170], S[171], S[198], Cout[198]);
Full_Adder FA184 (S[139], Cout[171], S[172], S[199], Cout[199]);
Full_Adder FA185 (S[141], Cout[172], S[173], S[200], Cout[200]);
Full_Adder FA186 (S[143], Cout[173], S[174], S[201], Cout[201]);
Full_Adder FA187 (S[145], Cout[174], S[175], S[202], Cout[202]);
Full_Adder FA188 (S[147], Cout[175], S[176], S[203], Cout[203]);
Full_Adder FA189 (S[149], Cout[176], S[177], S[204], Cout[204]);
Full_Adder FA190 (S[151], Cout[177], S[178], S[205], Cout[205]);
Full_Adder FA191 (S[153], Cout[178], S[179], S[206], Cout[206]);
Full_Adder FA192 (S[155], Cout[179], S[180], S[207], Cout[207]);
Full_Adder FA193 (S[156], Cout[180], S[181], S[208], Cout[208]);
Full_Adder FA194 (Cout[156], Cout[181], S[182], S[209], Cout[209]);
Full_Adder FA195 (P[14][15], P[15][14], Cout[182], S[210], Cout[210]);
Half_Adder HA16 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA196 (P[2][0], S[183], Cout[0], S[211], Cout[211]);
Full_Adder FA197 (Cout[183], S[184], Cout[211], S[212], Cout[212]);
Full_Adder FA198 (Cout[184], S[185], Cout[212], S[213], Cout[213]);
Full_Adder FA199 (Cout[185], S[186], Cout[213], S[214], Cout[214]);
Full_Adder FA200 (Cout[186], S[187], Cout[214], S[215], Cout[215]);
Full_Adder FA201 (Cout[187], S[188], Cout[215], S[216], Cout[216]);
Full_Adder FA202 (Cout[188], S[189], Cout[216], S[217], Cout[217]);
Full_Adder FA203 (Cout[189], S[190], Cout[217], S[218], Cout[218]);
Full_Adder FA204 (Cout[190], S[191], Cout[218], S[219], Cout[219]);
Full_Adder FA205 (Cout[191], S[192], Cout[219], S[220], Cout[220]);
Full_Adder FA206 (Cout[192], S[193], Cout[220], S[221], Cout[221]);
Full_Adder FA207 (Cout[193], S[194], Cout[221], S[222], Cout[222]);
Full_Adder FA208 (Cout[194], S[195], Cout[222], S[223], Cout[223]);
Full_Adder FA209 (Cout[195], S[196], Cout[223], S[224], Cout[224]);
Full_Adder FA210 (Cout[196], S[197], Cout[224], S[225], Cout[225]);
Full_Adder FA211 (Cout[197], S[198], Cout[225], S[226], Cout[226]);
Full_Adder FA212 (Cout[198], S[199], Cout[226], S[227], Cout[227]);
Full_Adder FA213 (Cout[199], S[200], Cout[227], S[228], Cout[228]);
Full_Adder FA214 (Cout[200], S[201], Cout[228], S[229], Cout[229]);
Full_Adder FA215 (Cout[201], S[202], Cout[229], S[230], Cout[230]);
Full_Adder FA216 (Cout[202], S[203], Cout[230], S[231], Cout[231]);
Full_Adder FA217 (Cout[203], S[204], Cout[231], S[232], Cout[232]);
Full_Adder FA218 (Cout[204], S[205], Cout[232], S[233], Cout[233]);
Full_Adder FA219 (Cout[205], S[206], Cout[233], S[234], Cout[234]);
Full_Adder FA220 (Cout[206], S[207], Cout[234], S[235], Cout[235]);
Full_Adder FA221 (Cout[207], S[208], Cout[235], S[236], Cout[236]);
Full_Adder FA222 (Cout[208], S[209], Cout[236], S[237], Cout[237]);
Full_Adder FA223 (Cout[209], S[210], Cout[237], S[238], Cout[238]);
Full_Adder FA224 (P[15][15], Cout[210], Cout[238], S[239], Cout[239]);
assign z[31] = Cout[239];
assign z[30] = S[239];
assign z[29] = S[238];
assign z[28] = S[237];
assign z[27] = S[236];
assign z[26] = S[235];
assign z[25] = S[234];
assign z[24] = S[233];
assign z[23] = S[232];
assign z[22] = S[231];
assign z[21] = S[230];
assign z[20] = S[229];
assign z[19] = S[228];
assign z[18] = S[227];
assign z[17] = S[226];
assign z[16] = S[225];
assign z[15] = S[224];
assign z[14] = S[223];
assign z[13] = S[222];
assign z[12] = S[221];
assign z[11] = S[220];
assign z[10] = S[219];
assign z[9] = S[218];
assign z[8] = S[217];
assign z[7] = S[216];
assign z[6] = S[215];
assign z[5] = S[214];
assign z[4] = S[213];
assign z[3] = S[212];
assign z[2] = S[211];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | module Mult_Dadda16 # (
parameter N = 16
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
); |
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[0][4] = x[0] & y[4];
assign P[0][5] = x[0] & y[5];
assign P[0][6] = x[0] & y[6];
assign P[0][7] = x[0] & y[7];
assign P[0][8] = x[0] & y[8];
assign P[0][9] = x[0] & y[9];
assign P[0][10] = x[0] & y[10];
assign P[0][11] = x[0] & y[11];
assign P[0][12] = x[0] & y[12];
assign P[0][13] = x[0] & y[13];
assign P[0][14] = x[0] & y[14];
assign P[0][15] = x[0] & y[15];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[1][4] = x[1] & y[4];
assign P[1][5] = x[1] & y[5];
assign P[1][6] = x[1] & y[6];
assign P[1][7] = x[1] & y[7];
assign P[1][8] = x[1] & y[8];
assign P[1][9] = x[1] & y[9];
assign P[1][10] = x[1] & y[10];
assign P[1][11] = x[1] & y[11];
assign P[1][12] = x[1] & y[12];
assign P[1][13] = x[1] & y[13];
assign P[1][14] = x[1] & y[14];
assign P[1][15] = x[1] & y[15];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[2][4] = x[2] & y[4];
assign P[2][5] = x[2] & y[5];
assign P[2][6] = x[2] & y[6];
assign P[2][7] = x[2] & y[7];
assign P[2][8] = x[2] & y[8];
assign P[2][9] = x[2] & y[9];
assign P[2][10] = x[2] & y[10];
assign P[2][11] = x[2] & y[11];
assign P[2][12] = x[2] & y[12];
assign P[2][13] = x[2] & y[13];
assign P[2][14] = x[2] & y[14];
assign P[2][15] = x[2] & y[15];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
assign P[3][4] = x[3] & y[4];
assign P[3][5] = x[3] & y[5];
assign P[3][6] = x[3] & y[6];
assign P[3][7] = x[3] & y[7];
assign P[3][8] = x[3] & y[8];
assign P[3][9] = x[3] & y[9];
assign P[3][10] = x[3] & y[10];
assign P[3][11] = x[3] & y[11];
assign P[3][12] = x[3] & y[12];
assign P[3][13] = x[3] & y[13];
assign P[3][14] = x[3] & y[14];
assign P[3][15] = x[3] & y[15];
assign P[4][0] = x[4] & y[0];
assign P[4][1] = x[4] & y[1];
assign P[4][2] = x[4] & y[2];
assign P[4][3] = x[4] & y[3];
assign P[4][4] = x[4] & y[4];
assign P[4][5] = x[4] & y[5];
assign P[4][6] = x[4] & y[6];
assign P[4][7] = x[4] & y[7];
assign P[4][8] = x[4] & y[8];
assign P[4][9] = x[4] & y[9];
assign P[4][10] = x[4] & y[10];
assign P[4][11] = x[4] & y[11];
assign P[4][12] = x[4] & y[12];
assign P[4][13] = x[4] & y[13];
assign P[4][14] = x[4] & y[14];
assign P[4][15] = x[4] & y[15];
assign P[5][0] = x[5] & y[0];
assign P[5][1] = x[5] & y[1];
assign P[5][2] = x[5] & y[2];
assign P[5][3] = x[5] & y[3];
assign P[5][4] = x[5] & y[4];
assign P[5][5] = x[5] & y[5];
assign P[5][6] = x[5] & y[6];
assign P[5][7] = x[5] & y[7];
assign P[5][8] = x[5] & y[8];
assign P[5][9] = x[5] & y[9];
assign P[5][10] = x[5] & y[10];
assign P[5][11] = x[5] & y[11];
assign P[5][12] = x[5] & y[12];
assign P[5][13] = x[5] & y[13];
assign P[5][14] = x[5] & y[14];
assign P[5][15] = x[5] & y[15];
assign P[6][0] = x[6] & y[0];
assign P[6][1] = x[6] & y[1];
assign P[6][2] = x[6] & y[2];
assign P[6][3] = x[6] & y[3];
assign P[6][4] = x[6] & y[4];
assign P[6][5] = x[6] & y[5];
assign P[6][6] = x[6] & y[6];
assign P[6][7] = x[6] & y[7];
assign P[6][8] = x[6] & y[8];
assign P[6][9] = x[6] & y[9];
assign P[6][10] = x[6] & y[10];
assign P[6][11] = x[6] & y[11];
assign P[6][12] = x[6] & y[12];
assign P[6][13] = x[6] & y[13];
assign P[6][14] = x[6] & y[14];
assign P[6][15] = x[6] & y[15];
assign P[7][0] = x[7] & y[0];
assign P[7][1] = x[7] & y[1];
assign P[7][2] = x[7] & y[2];
assign P[7][3] = x[7] & y[3];
assign P[7][4] = x[7] & y[4];
assign P[7][5] = x[7] & y[5];
assign P[7][6] = x[7] & y[6];
assign P[7][7] = x[7] & y[7];
assign P[7][8] = x[7] & y[8];
assign P[7][9] = x[7] & y[9];
assign P[7][10] = x[7] & y[10];
assign P[7][11] = x[7] & y[11];
assign P[7][12] = x[7] & y[12];
assign P[7][13] = x[7] & y[13];
assign P[7][14] = x[7] & y[14];
assign P[7][15] = x[7] & y[15];
assign P[8][0] = x[8] & y[0];
assign P[8][1] = x[8] & y[1];
assign P[8][2] = x[8] & y[2];
assign P[8][3] = x[8] & y[3];
assign P[8][4] = x[8] & y[4];
assign P[8][5] = x[8] & y[5];
assign P[8][6] = x[8] & y[6];
assign P[8][7] = x[8] & y[7];
assign P[8][8] = x[8] & y[8];
assign P[8][9] = x[8] & y[9];
assign P[8][10] = x[8] & y[10];
assign P[8][11] = x[8] & y[11];
assign P[8][12] = x[8] & y[12];
assign P[8][13] = x[8] & y[13];
assign P[8][14] = x[8] & y[14];
assign P[8][15] = x[8] & y[15];
assign P[9][0] = x[9] & y[0];
assign P[9][1] = x[9] & y[1];
assign P[9][2] = x[9] & y[2];
assign P[9][3] = x[9] & y[3];
assign P[9][4] = x[9] & y[4];
assign P[9][5] = x[9] & y[5];
assign P[9][6] = x[9] & y[6];
assign P[9][7] = x[9] & y[7];
assign P[9][8] = x[9] & y[8];
assign P[9][9] = x[9] & y[9];
assign P[9][10] = x[9] & y[10];
assign P[9][11] = x[9] & y[11];
assign P[9][12] = x[9] & y[12];
assign P[9][13] = x[9] & y[13];
assign P[9][14] = x[9] & y[14];
assign P[9][15] = x[9] & y[15];
assign P[10][0] = x[10] & y[0];
assign P[10][1] = x[10] & y[1];
assign P[10][2] = x[10] & y[2];
assign P[10][3] = x[10] & y[3];
assign P[10][4] = x[10] & y[4];
assign P[10][5] = x[10] & y[5];
assign P[10][6] = x[10] & y[6];
assign P[10][7] = x[10] & y[7];
assign P[10][8] = x[10] & y[8];
assign P[10][9] = x[10] & y[9];
assign P[10][10] = x[10] & y[10];
assign P[10][11] = x[10] & y[11];
assign P[10][12] = x[10] & y[12];
assign P[10][13] = x[10] & y[13];
assign P[10][14] = x[10] & y[14];
assign P[10][15] = x[10] & y[15];
assign P[11][0] = x[11] & y[0];
assign P[11][1] = x[11] & y[1];
assign P[11][2] = x[11] & y[2];
assign P[11][3] = x[11] & y[3];
assign P[11][4] = x[11] & y[4];
assign P[11][5] = x[11] & y[5];
assign P[11][6] = x[11] & y[6];
assign P[11][7] = x[11] & y[7];
assign P[11][8] = x[11] & y[8];
assign P[11][9] = x[11] & y[9];
assign P[11][10] = x[11] & y[10];
assign P[11][11] = x[11] & y[11];
assign P[11][12] = x[11] & y[12];
assign P[11][13] = x[11] & y[13];
assign P[11][14] = x[11] & y[14];
assign P[11][15] = x[11] & y[15];
assign P[12][0] = x[12] & y[0];
assign P[12][1] = x[12] & y[1];
assign P[12][2] = x[12] & y[2];
assign P[12][3] = x[12] & y[3];
assign P[12][4] = x[12] & y[4];
assign P[12][5] = x[12] & y[5];
assign P[12][6] = x[12] & y[6];
assign P[12][7] = x[12] & y[7];
assign P[12][8] = x[12] & y[8];
assign P[12][9] = x[12] & y[9];
assign P[12][10] = x[12] & y[10];
assign P[12][11] = x[12] & y[11];
assign P[12][12] = x[12] & y[12];
assign P[12][13] = x[12] & y[13];
assign P[12][14] = x[12] & y[14];
assign P[12][15] = x[12] & y[15];
assign P[13][0] = x[13] & y[0];
assign P[13][1] = x[13] & y[1];
assign P[13][2] = x[13] & y[2];
assign P[13][3] = x[13] & y[3];
assign P[13][4] = x[13] & y[4];
assign P[13][5] = x[13] & y[5];
assign P[13][6] = x[13] & y[6];
assign P[13][7] = x[13] & y[7];
assign P[13][8] = x[13] & y[8];
assign P[13][9] = x[13] & y[9];
assign P[13][10] = x[13] & y[10];
assign P[13][11] = x[13] & y[11];
assign P[13][12] = x[13] & y[12];
assign P[13][13] = x[13] & y[13];
assign P[13][14] = x[13] & y[14];
assign P[13][15] = x[13] & y[15];
assign P[14][0] = x[14] & y[0];
assign P[14][1] = x[14] & y[1];
assign P[14][2] = x[14] & y[2];
assign P[14][3] = x[14] & y[3];
assign P[14][4] = x[14] & y[4];
assign P[14][5] = x[14] & y[5];
assign P[14][6] = x[14] & y[6];
assign P[14][7] = x[14] & y[7];
assign P[14][8] = x[14] & y[8];
assign P[14][9] = x[14] & y[9];
assign P[14][10] = x[14] & y[10];
assign P[14][11] = x[14] & y[11];
assign P[14][12] = x[14] & y[12];
assign P[14][13] = x[14] & y[13];
assign P[14][14] = x[14] & y[14];
assign P[14][15] = x[14] & y[15];
assign P[15][0] = x[15] & y[0];
assign P[15][1] = x[15] & y[1];
assign P[15][2] = x[15] & y[2];
assign P[15][3] = x[15] & y[3];
assign P[15][4] = x[15] & y[4];
assign P[15][5] = x[15] & y[5];
assign P[15][6] = x[15] & y[6];
assign P[15][7] = x[15] & y[7];
assign P[15][8] = x[15] & y[8];
assign P[15][9] = x[15] & y[9];
assign P[15][10] = x[15] & y[10];
assign P[15][11] = x[15] & y[11];
assign P[15][12] = x[15] & y[12];
assign P[15][13] = x[15] & y[13];
assign P[15][14] = x[15] & y[14];
assign P[15][15] = x[15] & y[15];
wire [240:0] S;
wire [240:0] Cout;
Half_Adder HA1 (P[0][13], P[1][12], S[1], Cout[1]);
Full_Adder FA1 (P[0][14], P[1][13], P[2][12], S[2], Cout[2]);
Half_Adder HA2 (P[3][11], P[4][10], S[3], Cout[3]);
Full_Adder FA2 (P[0][15], P[1][14], P[2][13], S[4], Cout[4]);
Full_Adder FA3 (P[3][12], P[4][11], P[5][10], S[5], Cout[5]);
Half_Adder HA3 (P[6][9], P[7][8], S[6], Cout[6]);
Full_Adder FA4 (P[1][15], P[2][14], P[3][13], S[7], Cout[7]);
Full_Adder FA5 (P[4][12], P[5][11], P[6][10], S[8], Cout[8]);
Half_Adder HA4 (P[7][9], P[8][8], S[9], Cout[9]);
Full_Adder FA6 (P[2][15], P[3][14], P[4][13], S[10], Cout[10]);
Full_Adder FA7 (P[5][12], P[6][11], P[7][10], S[11], Cout[11]);
Full_Adder FA8 (P[3][15], P[4][14], P[5][13], S[12], Cout[12]);
Half_Adder HA5 (P[0][9], P[1][8], S[13], Cout[13]);
Full_Adder FA9 (P[0][10], P[1][9], P[2][8], S[14], Cout[14]);
Half_Adder HA6 (P[3][7], P[4][6], S[15], Cout[15]);
Full_Adder FA10 (P[0][11], P[1][10], P[2][9], S[16], Cout[16]);
Full_Adder FA11 (P[3][8], P[4][7], P[5][6], S[17], Cout[17]);
Half_Adder HA7 (P[6][5], P[7][4], S[18], Cout[18]);
Full_Adder FA12 (P[0][12], P[1][11], P[2][10], S[19], Cout[19]);
Full_Adder FA13 (P[3][9], P[4][8], P[5][7], S[20], Cout[20]);
Full_Adder FA14 (P[6][6], P[7][5], P[8][4], S[21], Cout[21]);
Half_Adder HA8 (P[9][3], P[10][2], S[22], Cout[22]);
Full_Adder FA15 (P[2][11], P[3][10], P[4][9], S[23], Cout[23]);
Full_Adder FA16 (P[5][8], P[6][7], P[7][6], S[24], Cout[24]);
Full_Adder FA17 (P[8][5], P[9][4], P[10][3], S[25], Cout[25]);
Full_Adder FA18 (P[11][2], P[12][1], P[13][0], S[26], Cout[26]);
Full_Adder FA19 (P[5][9], P[6][8], P[7][7], S[27], Cout[27]);
Full_Adder FA20 (P[8][6], P[9][5], P[10][4], S[28], Cout[28]);
Full_Adder FA21 (P[11][3], P[12][2], P[13][1], S[29], Cout[29]);
Full_Adder FA22 (P[14][0], Cout[1], S[2], S[30], Cout[30]);
Full_Adder FA23 (P[8][7], P[9][6], P[10][5], S[31], Cout[31]);
Full_Adder FA24 (P[11][4], P[12][3], P[13][2], S[32], Cout[32]);
Full_Adder FA25 (P[14][1], P[15][0], Cout[2], S[33], Cout[33]);
Full_Adder FA26 (Cout[3], S[4], S[5], S[34], Cout[34]);
Full_Adder FA27 (P[9][7], P[10][6], P[11][5], S[35], Cout[35]);
Full_Adder FA28 (P[12][4], P[13][3], P[14][2], S[36], Cout[36]);
Full_Adder FA29 (P[15][1], Cout[4], Cout[5], S[37], Cout[37]);
Full_Adder FA30 (Cout[6], S[7], S[8], S[38], Cout[38]);
Full_Adder FA31 (P[8][9], P[9][8], P[10][7], S[39], Cout[39]);
Full_Adder FA32 (P[11][6], P[12][5], P[13][4], S[40], Cout[40]);
Full_Adder FA33 (P[14][3], P[15][2], Cout[7], S[41], Cout[41]);
Full_Adder FA34 (Cout[8], Cout[9], S[10], S[42], Cout[42]);
Full_Adder FA35 (P[6][12], P[7][11], P[8][10], S[43], Cout[43]);
Full_Adder FA36 (P[9][9], P[10][8], P[11][7], S[44], Cout[44]);
Full_Adder FA37 (P[12][6], P[13][5], P[14][4], S[45], Cout[45]);
Full_Adder FA38 (P[15][3], Cout[10], Cout[11], S[46], Cout[46]);
Full_Adder FA39 (P[4][15], P[5][14], P[6][13], S[47], Cout[47]);
Full_Adder FA40 (P[7][12], P[8][11], P[9][10], S[48], Cout[48]);
Full_Adder FA41 (P[10][9], P[11][8], P[12][7], S[49], Cout[49]);
Full_Adder FA42 (P[13][6], P[14][5], P[15][4], S[50], Cout[50]);
Full_Adder FA43 (P[5][15], P[6][14], P[7][13], S[51], Cout[51]);
Full_Adder FA44 (P[8][12], P[9][11], P[10][10], S[52], Cout[52]);
Full_Adder FA45 (P[11][9], P[12][8], P[13][7], S[53], Cout[53]);
Full_Adder FA46 (P[6][15], P[7][14], P[8][13], S[54], Cout[54]);
Full_Adder FA47 (P[9][12], P[10][11], P[11][10], S[55], Cout[55]);
Full_Adder FA48 (P[7][15], P[8][14], P[9][13], S[56], Cout[56]);
Half_Adder HA9 (P[0][6], P[1][5], S[57], Cout[57]);
Full_Adder FA49 (P[0][7], P[1][6], P[2][5], S[58], Cout[58]);
Half_Adder HA10 (P[3][4], P[4][3], S[59], Cout[59]);
Full_Adder FA50 (P[0][8], P[1][7], P[2][6], S[60], Cout[60]);
Full_Adder FA51 (P[3][5], P[4][4], P[5][3], S[61], Cout[61]);
Half_Adder HA11 (P[6][2], P[7][1], S[62], Cout[62]);
Full_Adder FA52 (P[2][7], P[3][6], P[4][5], S[63], Cout[63]);
Full_Adder FA53 (P[5][4], P[6][3], P[7][2], S[64], Cout[64]);
Full_Adder FA54 (P[8][1], P[9][0], S[13], S[65], Cout[65]);
Full_Adder FA55 (P[5][5], P[6][4], P[7][3], S[66], Cout[66]);
Full_Adder FA56 (P[8][2], P[9][1], P[10][0], S[67], Cout[67]);
Full_Adder FA57 (Cout[13], S[14], S[15], S[68], Cout[68]);
Full_Adder FA58 (P[8][3], P[9][2], P[10][1], S[69], Cout[69]);
Full_Adder FA59 (P[11][0], Cout[14], Cout[15], S[70], Cout[70]);
Full_Adder FA60 (S[16], S[17], S[18], S[71], Cout[71]);
Full_Adder FA61 (P[11][1], P[12][0], Cout[16], S[72], Cout[72]);
Full_Adder FA62 (Cout[17], Cout[18], S[19], S[73], Cout[73]);
Full_Adder FA63 (S[20], S[21], S[22], S[74], Cout[74]);
Full_Adder FA64 (S[1], Cout[19], Cout[20], S[75], Cout[75]);
Full_Adder FA65 (Cout[21], Cout[22], S[23], S[76], Cout[76]);
Full_Adder FA66 (S[24], S[25], S[26], S[77], Cout[77]);
Full_Adder FA67 (S[3], Cout[23], Cout[24], S[78], Cout[78]);
Full_Adder FA68 (Cout[25], Cout[26], S[27], S[79], Cout[79]);
Full_Adder FA69 (S[28], S[29], S[30], S[80], Cout[80]);
Full_Adder FA70 (S[6], Cout[27], Cout[28], S[81], Cout[81]);
Full_Adder FA71 (Cout[29], Cout[30], S[31], S[82], Cout[82]);
Full_Adder FA72 (S[32], S[33], S[34], S[83], Cout[83]);
Full_Adder FA73 (S[9], Cout[31], Cout[32], S[84], Cout[84]);
Full_Adder FA74 (Cout[33], Cout[34], S[35], S[85], Cout[85]);
Full_Adder FA75 (S[36], S[37], S[38], S[86], Cout[86]);
Full_Adder FA76 (S[11], Cout[35], Cout[36], S[87], Cout[87]);
Full_Adder FA77 (Cout[37], Cout[38], S[39], S[88], Cout[88]);
Full_Adder FA78 (S[40], S[41], S[42], S[89], Cout[89]);
Full_Adder FA79 (S[12], Cout[39], Cout[40], S[90], Cout[90]);
Full_Adder FA80 (Cout[41], Cout[42], S[43], S[91], Cout[91]);
Full_Adder FA81 (S[44], S[45], S[46], S[92], Cout[92]);
Full_Adder FA82 (Cout[12], Cout[43], Cout[44], S[93], Cout[93]);
Full_Adder FA83 (Cout[45], Cout[46], S[47], S[94], Cout[94]);
Full_Adder FA84 (S[48], S[49], S[50], S[95], Cout[95]);
Full_Adder FA85 (P[14][6], P[15][5], Cout[47], S[96], Cout[96]);
Full_Adder FA86 (Cout[48], Cout[49], Cout[50], S[97], Cout[97]);
Full_Adder FA87 (S[51], S[52], S[53], S[98], Cout[98]);
Full_Adder FA88 (P[12][9], P[13][8], P[14][7], S[99], Cout[99]);
Full_Adder FA89 (P[15][6], Cout[51], Cout[52], S[100], Cout[100]);
Full_Adder FA90 (Cout[53], S[54], S[55], S[101], Cout[101]);
Full_Adder FA91 (P[10][12], P[11][11], P[12][10], S[102], Cout[102]);
Full_Adder FA92 (P[13][9], P[14][8], P[15][7], S[103], Cout[103]);
Full_Adder FA93 (Cout[54], Cout[55], S[56], S[104], Cout[104]);
Full_Adder FA94 (P[8][15], P[9][14], P[10][13], S[105], Cout[105]);
Full_Adder FA95 (P[11][12], P[12][11], P[13][10], S[106], Cout[106]);
Full_Adder FA96 (P[14][9], P[15][8], Cout[56], S[107], Cout[107]);
Full_Adder FA97 (P[9][15], P[10][14], P[11][13], S[108], Cout[108]);
Full_Adder FA98 (P[12][12], P[13][11], P[14][10], S[109], Cout[109]);
Full_Adder FA99 (P[10][15], P[11][14], P[12][13], S[110], Cout[110]);
Half_Adder HA12 (P[0][4], P[1][3], S[111], Cout[111]);
Full_Adder FA100 (P[0][5], P[1][4], P[2][3], S[112], Cout[112]);
Half_Adder HA13 (P[3][2], P[4][1], S[113], Cout[113]);
Full_Adder FA101 (P[2][4], P[3][3], P[4][2], S[114], Cout[114]);
Full_Adder FA102 (P[5][1], P[6][0], S[57], S[115], Cout[115]);
Full_Adder FA103 (P[5][2], P[6][1], P[7][0], S[116], Cout[116]);
Full_Adder FA104 (Cout[57], S[58], S[59], S[117], Cout[117]);
Full_Adder FA105 (P[8][0], Cout[58], Cout[59], S[118], Cout[118]);
Full_Adder FA106 (S[60], S[61], S[62], S[119], Cout[119]);
Full_Adder FA107 (Cout[60], Cout[61], Cout[62], S[120], Cout[120]);
Full_Adder FA108 (S[63], S[64], S[65], S[121], Cout[121]);
Full_Adder FA109 (Cout[63], Cout[64], Cout[65], S[122], Cout[122]);
Full_Adder FA110 (S[66], S[67], S[68], S[123], Cout[123]);
Full_Adder FA111 (Cout[66], Cout[67], Cout[68], S[124], Cout[124]);
Full_Adder FA112 (S[69], S[70], S[71], S[125], Cout[125]);
Full_Adder FA113 (Cout[69], Cout[70], Cout[71], S[126], Cout[126]);
Full_Adder FA114 (S[72], S[73], S[74], S[127], Cout[127]);
Full_Adder FA115 (Cout[72], Cout[73], Cout[74], S[128], Cout[128]);
Full_Adder FA116 (S[75], S[76], S[77], S[129], Cout[129]);
Full_Adder FA117 (Cout[75], Cout[76], Cout[77], S[130], Cout[130]);
Full_Adder FA118 (S[78], S[79], S[80], S[131], Cout[131]);
Full_Adder FA119 (Cout[78], Cout[79], Cout[80], S[132], Cout[132]);
Full_Adder FA120 (S[81], S[82], S[83], S[133], Cout[133]);
Full_Adder FA121 (Cout[81], Cout[82], Cout[83], S[134], Cout[134]);
Full_Adder FA122 (S[84], S[85], S[86], S[135], Cout[135]);
Full_Adder FA123 (Cout[84], Cout[85], Cout[86], S[136], Cout[136]);
Full_Adder FA124 (S[87], S[88], S[89], S[137], Cout[137]);
Full_Adder FA125 (Cout[87], Cout[88], Cout[89], S[138], Cout[138]);
Full_Adder FA126 (S[90], S[91], S[92], S[139], Cout[139]);
Full_Adder FA127 (Cout[90], Cout[91], Cout[92], S[140], Cout[140]);
Full_Adder FA128 (S[93], S[94], S[95], S[141], Cout[141]);
Full_Adder FA129 (Cout[93], Cout[94], Cout[95], S[142], Cout[142]);
Full_Adder FA130 (S[96], S[97], S[98], S[143], Cout[143]);
Full_Adder FA131 (Cout[96], Cout[97], Cout[98], S[144], Cout[144]);
Full_Adder FA132 (S[99], S[100], S[101], S[145], Cout[145]);
Full_Adder FA133 (Cout[99], Cout[100], Cout[101], S[146], Cout[146]);
Full_Adder FA134 (S[102], S[103], S[104], S[147], Cout[147]);
Full_Adder FA135 (Cout[102], Cout[103], Cout[104], S[148], Cout[148]);
Full_Adder FA136 (S[105], S[106], S[107], S[149], Cout[149]);
Full_Adder FA137 (P[15][9], Cout[105], Cout[106], S[150], Cout[150]);
Full_Adder FA138 (Cout[107], S[108], S[109], S[151], Cout[151]);
Full_Adder FA139 (P[13][12], P[14][11], P[15][10], S[152], Cout[152]);
Full_Adder FA140 (Cout[108], Cout[109], S[110], S[153], Cout[153]);
Full_Adder FA141 (P[11][15], P[12][14], P[13][13], S[154], Cout[154]);
Full_Adder FA142 (P[14][12], P[15][11], Cout[110], S[155], Cout[155]);
Full_Adder FA143 (P[12][15], P[13][14], P[14][13], S[156], Cout[156]);
Half_Adder HA14 (P[0][3], P[1][2], S[157], Cout[157]);
Full_Adder FA144 (P[2][2], P[3][1], P[4][0], S[158], Cout[158]);
Full_Adder FA145 (P[5][0], Cout[111], S[112], S[159], Cout[159]);
Full_Adder FA146 (Cout[112], Cout[113], S[114], S[160], Cout[160]);
Full_Adder FA147 (Cout[114], Cout[115], S[116], S[161], Cout[161]);
Full_Adder FA148 (Cout[116], Cout[117], S[118], S[162], Cout[162]);
Full_Adder FA149 (Cout[118], Cout[119], S[120], S[163], Cout[163]);
Full_Adder FA150 (Cout[120], Cout[121], S[122], S[164], Cout[164]);
Full_Adder FA151 (Cout[122], Cout[123], S[124], S[165], Cout[165]);
Full_Adder FA152 (Cout[124], Cout[125], S[126], S[166], Cout[166]);
Full_Adder FA153 (Cout[126], Cout[127], S[128], S[167], Cout[167]);
Full_Adder FA154 (Cout[128], Cout[129], S[130], S[168], Cout[168]);
Full_Adder FA155 (Cout[130], Cout[131], S[132], S[169], Cout[169]);
Full_Adder FA156 (Cout[132], Cout[133], S[134], S[170], Cout[170]);
Full_Adder FA157 (Cout[134], Cout[135], S[136], S[171], Cout[171]);
Full_Adder FA158 (Cout[136], Cout[137], S[138], S[172], Cout[172]);
Full_Adder FA159 (Cout[138], Cout[139], S[140], S[173], Cout[173]);
Full_Adder FA160 (Cout[140], Cout[141], S[142], S[174], Cout[174]);
Full_Adder FA161 (Cout[142], Cout[143], S[144], S[175], Cout[175]);
Full_Adder FA162 (Cout[144], Cout[145], S[146], S[176], Cout[176]);
Full_Adder FA163 (Cout[146], Cout[147], S[148], S[177], Cout[177]);
Full_Adder FA164 (Cout[148], Cout[149], S[150], S[178], Cout[178]);
Full_Adder FA165 (Cout[150], Cout[151], S[152], S[179], Cout[179]);
Full_Adder FA166 (Cout[152], Cout[153], S[154], S[180], Cout[180]);
Full_Adder FA167 (P[15][12], Cout[154], Cout[155], S[181], Cout[181]);
Full_Adder FA168 (P[13][15], P[14][14], P[15][13], S[182], Cout[182]);
Half_Adder HA15 (P[0][2], P[1][1], S[183], Cout[183]);
Full_Adder FA169 (P[2][1], P[3][0], S[157], S[184], Cout[184]);
Full_Adder FA170 (S[111], Cout[157], S[158], S[185], Cout[185]);
Full_Adder FA171 (S[113], Cout[158], S[159], S[186], Cout[186]);
Full_Adder FA172 (S[115], Cout[159], S[160], S[187], Cout[187]);
Full_Adder FA173 (S[117], Cout[160], S[161], S[188], Cout[188]);
Full_Adder FA174 (S[119], Cout[161], S[162], S[189], Cout[189]);
Full_Adder FA175 (S[121], Cout[162], S[163], S[190], Cout[190]);
Full_Adder FA176 (S[123], Cout[163], S[164], S[191], Cout[191]);
Full_Adder FA177 (S[125], Cout[164], S[165], S[192], Cout[192]);
Full_Adder FA178 (S[127], Cout[165], S[166], S[193], Cout[193]);
Full_Adder FA179 (S[129], Cout[166], S[167], S[194], Cout[194]);
Full_Adder FA180 (S[131], Cout[167], S[168], S[195], Cout[195]);
Full_Adder FA181 (S[133], Cout[168], S[169], S[196], Cout[196]);
Full_Adder FA182 (S[135], Cout[169], S[170], S[197], Cout[197]);
Full_Adder FA183 (S[137], Cout[170], S[171], S[198], Cout[198]);
Full_Adder FA184 (S[139], Cout[171], S[172], S[199], Cout[199]);
Full_Adder FA185 (S[141], Cout[172], S[173], S[200], Cout[200]);
Full_Adder FA186 (S[143], Cout[173], S[174], S[201], Cout[201]);
Full_Adder FA187 (S[145], Cout[174], S[175], S[202], Cout[202]);
Full_Adder FA188 (S[147], Cout[175], S[176], S[203], Cout[203]);
Full_Adder FA189 (S[149], Cout[176], S[177], S[204], Cout[204]);
Full_Adder FA190 (S[151], Cout[177], S[178], S[205], Cout[205]);
Full_Adder FA191 (S[153], Cout[178], S[179], S[206], Cout[206]);
Full_Adder FA192 (S[155], Cout[179], S[180], S[207], Cout[207]);
Full_Adder FA193 (S[156], Cout[180], S[181], S[208], Cout[208]);
Full_Adder FA194 (Cout[156], Cout[181], S[182], S[209], Cout[209]);
Full_Adder FA195 (P[14][15], P[15][14], Cout[182], S[210], Cout[210]);
Half_Adder HA16 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA196 (P[2][0], S[183], Cout[0], S[211], Cout[211]);
Full_Adder FA197 (Cout[183], S[184], Cout[211], S[212], Cout[212]);
Full_Adder FA198 (Cout[184], S[185], Cout[212], S[213], Cout[213]);
Full_Adder FA199 (Cout[185], S[186], Cout[213], S[214], Cout[214]);
Full_Adder FA200 (Cout[186], S[187], Cout[214], S[215], Cout[215]);
Full_Adder FA201 (Cout[187], S[188], Cout[215], S[216], Cout[216]);
Full_Adder FA202 (Cout[188], S[189], Cout[216], S[217], Cout[217]);
Full_Adder FA203 (Cout[189], S[190], Cout[217], S[218], Cout[218]);
Full_Adder FA204 (Cout[190], S[191], Cout[218], S[219], Cout[219]);
Full_Adder FA205 (Cout[191], S[192], Cout[219], S[220], Cout[220]);
Full_Adder FA206 (Cout[192], S[193], Cout[220], S[221], Cout[221]);
Full_Adder FA207 (Cout[193], S[194], Cout[221], S[222], Cout[222]);
Full_Adder FA208 (Cout[194], S[195], Cout[222], S[223], Cout[223]);
Full_Adder FA209 (Cout[195], S[196], Cout[223], S[224], Cout[224]);
Full_Adder FA210 (Cout[196], S[197], Cout[224], S[225], Cout[225]);
Full_Adder FA211 (Cout[197], S[198], Cout[225], S[226], Cout[226]);
Full_Adder FA212 (Cout[198], S[199], Cout[226], S[227], Cout[227]);
Full_Adder FA213 (Cout[199], S[200], Cout[227], S[228], Cout[228]);
Full_Adder FA214 (Cout[200], S[201], Cout[228], S[229], Cout[229]);
Full_Adder FA215 (Cout[201], S[202], Cout[229], S[230], Cout[230]);
Full_Adder FA216 (Cout[202], S[203], Cout[230], S[231], Cout[231]);
Full_Adder FA217 (Cout[203], S[204], Cout[231], S[232], Cout[232]);
Full_Adder FA218 (Cout[204], S[205], Cout[232], S[233], Cout[233]);
Full_Adder FA219 (Cout[205], S[206], Cout[233], S[234], Cout[234]);
Full_Adder FA220 (Cout[206], S[207], Cout[234], S[235], Cout[235]);
Full_Adder FA221 (Cout[207], S[208], Cout[235], S[236], Cout[236]);
Full_Adder FA222 (Cout[208], S[209], Cout[236], S[237], Cout[237]);
Full_Adder FA223 (Cout[209], S[210], Cout[237], S[238], Cout[238]);
Full_Adder FA224 (P[15][15], Cout[210], Cout[238], S[239], Cout[239]);
assign z[31] = Cout[239];
assign z[30] = S[239];
assign z[29] = S[238];
assign z[28] = S[237];
assign z[27] = S[236];
assign z[26] = S[235];
assign z[25] = S[234];
assign z[24] = S[233];
assign z[23] = S[232];
assign z[22] = S[231];
assign z[21] = S[230];
assign z[20] = S[229];
assign z[19] = S[228];
assign z[18] = S[227];
assign z[17] = S[226];
assign z[16] = S[225];
assign z[15] = S[224];
assign z[14] = S[223];
assign z[13] = S[222];
assign z[12] = S[221];
assign z[11] = S[220];
assign z[10] = S[219];
assign z[9] = S[218];
assign z[8] = S[217];
assign z[7] = S[216];
assign z[6] = S[215];
assign z[5] = S[214];
assign z[4] = S[213];
assign z[3] = S[212];
assign z[2] = S[211];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | 4 |
142,192 | data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v | 97,859,536 | Mult_Dadda4.v | v | 55 | 62 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:33: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA1 (P[0][3], P[1][2], S[1], Cout[1]);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.v\n data/full_repos/permissive/97859536/DaddaVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.sv\n Half_Adder\n Half_Adder.v\n Half_Adder.sv\n obj_dir/Half_Adder\n obj_dir/Half_Adder.v\n obj_dir/Half_Adder.sv\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:34: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA2 (P[1][3], P[2][2], S[2], Cout[2]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:35: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA3 (P[0][2], P[1][1], S[3], Cout[3]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:36: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA1 (P[2][1], P[3][0], S[1], S[4], Cout[4]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:37: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA2 (P[3][1], Cout[1], S[2], S[5], Cout[5]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:38: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA3 (P[2][3], P[3][2], Cout[2], S[6], Cout[6]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:39: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA4 (P[0][1], P[1][0], S[0], Cout[0]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:40: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA4 (P[2][0], S[3], Cout[0], S[7], Cout[7]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:41: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA5 (Cout[3], S[4], Cout[7], S[8], Cout[8]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:42: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA6 (Cout[4], S[5], Cout[8], S[9], Cout[9]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:43: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA7 (Cout[5], S[6], Cout[9], S[10], Cout[10]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/DaddaVGen/verilog/Mult_Dadda4.v:44: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA8 (P[3][3], Cout[6], Cout[10], S[11], Cout[11]);\n^~~~~~~~~~\n%Error: Exiting due to 12 error(s)\n" | 313,183 | module | module Mult_Dadda4 # (
parameter N = 4
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
);
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
wire [12:0] S;
wire [12:0] Cout;
Half_Adder HA1 (P[0][3], P[1][2], S[1], Cout[1]);
Half_Adder HA2 (P[1][3], P[2][2], S[2], Cout[2]);
Half_Adder HA3 (P[0][2], P[1][1], S[3], Cout[3]);
Full_Adder FA1 (P[2][1], P[3][0], S[1], S[4], Cout[4]);
Full_Adder FA2 (P[3][1], Cout[1], S[2], S[5], Cout[5]);
Full_Adder FA3 (P[2][3], P[3][2], Cout[2], S[6], Cout[6]);
Half_Adder HA4 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA4 (P[2][0], S[3], Cout[0], S[7], Cout[7]);
Full_Adder FA5 (Cout[3], S[4], Cout[7], S[8], Cout[8]);
Full_Adder FA6 (Cout[4], S[5], Cout[8], S[9], Cout[9]);
Full_Adder FA7 (Cout[5], S[6], Cout[9], S[10], Cout[10]);
Full_Adder FA8 (P[3][3], Cout[6], Cout[10], S[11], Cout[11]);
assign z[7] = Cout[11];
assign z[6] = S[11];
assign z[5] = S[10];
assign z[4] = S[9];
assign z[3] = S[8];
assign z[2] = S[7];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | module Mult_Dadda4 # (
parameter N = 4
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
); |
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
wire [12:0] S;
wire [12:0] Cout;
Half_Adder HA1 (P[0][3], P[1][2], S[1], Cout[1]);
Half_Adder HA2 (P[1][3], P[2][2], S[2], Cout[2]);
Half_Adder HA3 (P[0][2], P[1][1], S[3], Cout[3]);
Full_Adder FA1 (P[2][1], P[3][0], S[1], S[4], Cout[4]);
Full_Adder FA2 (P[3][1], Cout[1], S[2], S[5], Cout[5]);
Full_Adder FA3 (P[2][3], P[3][2], Cout[2], S[6], Cout[6]);
Half_Adder HA4 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA4 (P[2][0], S[3], Cout[0], S[7], Cout[7]);
Full_Adder FA5 (Cout[3], S[4], Cout[7], S[8], Cout[8]);
Full_Adder FA6 (Cout[4], S[5], Cout[8], S[9], Cout[9]);
Full_Adder FA7 (Cout[5], S[6], Cout[9], S[10], Cout[10]);
Full_Adder FA8 (P[3][3], Cout[6], Cout[10], S[11], Cout[11]);
assign z[7] = Cout[11];
assign z[6] = S[11];
assign z[5] = S[10];
assign z[4] = S[9];
assign z[3] = S[8];
assign z[2] = S[7];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | 4 |
142,196 | data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v | 97,859,536 | Mult_Wallace8.v | v | 163 | 63 | [] | [] | [] | [(3, 163)] | null | null | 1: b"%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:81: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA1 (P[0][1], P[1][0], S[0], Cout[0]);\n^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/97859536/WallaceVGen/verilog,data/full_repos/permissive/97859536/Half_Adder\n data/full_repos/permissive/97859536/WallaceVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.v\n data/full_repos/permissive/97859536/WallaceVGen/verilog,data/full_repos/permissive/97859536/Half_Adder.sv\n Half_Adder\n Half_Adder.v\n Half_Adder.sv\n obj_dir/Half_Adder\n obj_dir/Half_Adder.v\n obj_dir/Half_Adder.sv\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:82: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA2 (P[0][2], P[1][1], P[2][0], S[1], Cout[1]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:83: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA3 (P[0][3], P[1][2], P[2][1], S[2], Cout[2]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:84: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA4 (P[0][4], P[1][3], P[2][2], S[3], Cout[3]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:85: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA5 (P[3][1], P[4][0], S[4], Cout[4]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:86: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA6 (P[0][5], P[1][4], P[2][3], S[5], Cout[5]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:87: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA7 (P[3][2], P[4][1], P[5][0], S[6], Cout[6]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:88: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA8 (P[0][6], P[1][5], P[2][4], S[7], Cout[7]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:89: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA9 (P[3][3], P[4][2], P[5][1], S[8], Cout[8]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:90: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA10 (P[0][7], P[1][6], P[2][5], S[9], Cout[9]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:91: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA11 (P[3][4], P[4][3], P[5][2], S[10], Cout[10]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:92: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA12 (P[1][7], P[2][6], P[3][5], S[11], Cout[11]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:93: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA13 (P[4][4], P[5][3], S[12], Cout[12]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:94: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA14 (P[2][7], P[3][6], P[4][5], S[13], Cout[13]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:95: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA15 (P[3][7], P[4][6], P[5][5], S[14], Cout[14]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:96: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA16 (P[4][7], P[5][6], S[15], Cout[15]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:97: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA17 (Cout[0], S[1], S[16], Cout[16]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:98: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA18 (P[3][0], Cout[1], S[2], S[17], Cout[17]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:99: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA19 (Cout[2], S[3], S[4], S[18], Cout[18]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:100: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA20 (Cout[3], Cout[4], S[5], S[19], Cout[19]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:101: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA21 (P[6][0], Cout[5], Cout[6], S[20], Cout[20]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:102: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA22 (S[7], S[8], S[21], Cout[21]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:103: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA23 (P[6][1], P[7][0], Cout[7], S[22], Cout[22]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:104: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA24 (Cout[8], S[9], S[10], S[23], Cout[23]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:105: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA25 (P[6][2], P[7][1], Cout[9], S[24], Cout[24]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:106: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA26 (Cout[10], S[11], S[12], S[25], Cout[25]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:107: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA27 (P[5][4], P[6][3], P[7][2], S[26], Cout[26]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:108: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA28 (Cout[11], Cout[12], S[13], S[27], Cout[27]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:109: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA29 (P[6][4], P[7][3], Cout[13], S[28], Cout[28]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:110: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA30 (P[6][5], P[7][4], Cout[14], S[29], Cout[29]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:111: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA31 (P[5][7], P[6][6], P[7][5], S[30], Cout[30]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:112: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA32 (P[6][7], P[7][6], S[31], Cout[31]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:113: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA33 (Cout[16], S[17], S[32], Cout[32]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:114: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA34 (Cout[17], S[18], S[33], Cout[33]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:115: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA35 (S[6], Cout[18], S[19], S[34], Cout[34]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:116: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA36 (Cout[19], S[20], S[21], S[35], Cout[35]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:117: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA37 (Cout[20], Cout[21], S[22], S[36], Cout[36]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:118: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA38 (Cout[22], Cout[23], S[24], S[37], Cout[37]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:119: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA39 (Cout[24], Cout[25], S[26], S[38], Cout[38]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:120: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA40 (S[14], Cout[26], Cout[27], S[39], Cout[39]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:121: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA41 (S[15], Cout[28], S[40], Cout[40]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:122: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA42 (Cout[15], Cout[29], S[41], Cout[41]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:123: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA43 (Cout[32], S[33], S[42], Cout[42]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:124: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA44 (Cout[33], S[34], S[43], Cout[43]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:125: Cannot find file containing module: 'Half_Adder'\nHalf_Adder HA45 (Cout[34], S[35], S[44], Cout[44]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:126: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA46 (S[23], Cout[35], S[36], S[45], Cout[45]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:127: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA47 (S[25], Cout[36], S[37], S[46], Cout[46]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:128: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA48 (S[27], Cout[37], S[38], S[47], Cout[47]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:129: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA49 (S[28], Cout[38], S[39], S[48], Cout[48]);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/97859536/WallaceVGen/verilog/Mult_Wallace8.v:130: Cannot find file containing module: 'Full_Adder'\nFull_Adder FA50 (S[29], Cout[39], S[40], S[49], Cout[49]);\n^~~~~~~~~~\n%Error: Exiting due to too many errors encountered; --error-limit=50\n" | 313,190 | module | module Mult_Wallace8 # (
parameter N = 8
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
);
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[0][4] = x[0] & y[4];
assign P[0][5] = x[0] & y[5];
assign P[0][6] = x[0] & y[6];
assign P[0][7] = x[0] & y[7];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[1][4] = x[1] & y[4];
assign P[1][5] = x[1] & y[5];
assign P[1][6] = x[1] & y[6];
assign P[1][7] = x[1] & y[7];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[2][4] = x[2] & y[4];
assign P[2][5] = x[2] & y[5];
assign P[2][6] = x[2] & y[6];
assign P[2][7] = x[2] & y[7];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
assign P[3][4] = x[3] & y[4];
assign P[3][5] = x[3] & y[5];
assign P[3][6] = x[3] & y[6];
assign P[3][7] = x[3] & y[7];
assign P[4][0] = x[4] & y[0];
assign P[4][1] = x[4] & y[1];
assign P[4][2] = x[4] & y[2];
assign P[4][3] = x[4] & y[3];
assign P[4][4] = x[4] & y[4];
assign P[4][5] = x[4] & y[5];
assign P[4][6] = x[4] & y[6];
assign P[4][7] = x[4] & y[7];
assign P[5][0] = x[5] & y[0];
assign P[5][1] = x[5] & y[1];
assign P[5][2] = x[5] & y[2];
assign P[5][3] = x[5] & y[3];
assign P[5][4] = x[5] & y[4];
assign P[5][5] = x[5] & y[5];
assign P[5][6] = x[5] & y[6];
assign P[5][7] = x[5] & y[7];
assign P[6][0] = x[6] & y[0];
assign P[6][1] = x[6] & y[1];
assign P[6][2] = x[6] & y[2];
assign P[6][3] = x[6] & y[3];
assign P[6][4] = x[6] & y[4];
assign P[6][5] = x[6] & y[5];
assign P[6][6] = x[6] & y[6];
assign P[6][7] = x[6] & y[7];
assign P[7][0] = x[7] & y[0];
assign P[7][1] = x[7] & y[1];
assign P[7][2] = x[7] & y[2];
assign P[7][3] = x[7] & y[3];
assign P[7][4] = x[7] & y[4];
assign P[7][5] = x[7] & y[5];
assign P[7][6] = x[7] & y[6];
assign P[7][7] = x[7] & y[7];
wire [63:0] S;
wire [63:0] Cout;
Half_Adder HA1 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA2 (P[0][2], P[1][1], P[2][0], S[1], Cout[1]);
Full_Adder FA3 (P[0][3], P[1][2], P[2][1], S[2], Cout[2]);
Full_Adder FA4 (P[0][4], P[1][3], P[2][2], S[3], Cout[3]);
Half_Adder HA5 (P[3][1], P[4][0], S[4], Cout[4]);
Full_Adder FA6 (P[0][5], P[1][4], P[2][3], S[5], Cout[5]);
Full_Adder FA7 (P[3][2], P[4][1], P[5][0], S[6], Cout[6]);
Full_Adder FA8 (P[0][6], P[1][5], P[2][4], S[7], Cout[7]);
Full_Adder FA9 (P[3][3], P[4][2], P[5][1], S[8], Cout[8]);
Full_Adder FA10 (P[0][7], P[1][6], P[2][5], S[9], Cout[9]);
Full_Adder FA11 (P[3][4], P[4][3], P[5][2], S[10], Cout[10]);
Full_Adder FA12 (P[1][7], P[2][6], P[3][5], S[11], Cout[11]);
Half_Adder HA13 (P[4][4], P[5][3], S[12], Cout[12]);
Full_Adder FA14 (P[2][7], P[3][6], P[4][5], S[13], Cout[13]);
Full_Adder FA15 (P[3][7], P[4][6], P[5][5], S[14], Cout[14]);
Half_Adder HA16 (P[4][7], P[5][6], S[15], Cout[15]);
Half_Adder HA17 (Cout[0], S[1], S[16], Cout[16]);
Full_Adder FA18 (P[3][0], Cout[1], S[2], S[17], Cout[17]);
Full_Adder FA19 (Cout[2], S[3], S[4], S[18], Cout[18]);
Full_Adder FA20 (Cout[3], Cout[4], S[5], S[19], Cout[19]);
Full_Adder FA21 (P[6][0], Cout[5], Cout[6], S[20], Cout[20]);
Half_Adder HA22 (S[7], S[8], S[21], Cout[21]);
Full_Adder FA23 (P[6][1], P[7][0], Cout[7], S[22], Cout[22]);
Full_Adder FA24 (Cout[8], S[9], S[10], S[23], Cout[23]);
Full_Adder FA25 (P[6][2], P[7][1], Cout[9], S[24], Cout[24]);
Full_Adder FA26 (Cout[10], S[11], S[12], S[25], Cout[25]);
Full_Adder FA27 (P[5][4], P[6][3], P[7][2], S[26], Cout[26]);
Full_Adder FA28 (Cout[11], Cout[12], S[13], S[27], Cout[27]);
Full_Adder FA29 (P[6][4], P[7][3], Cout[13], S[28], Cout[28]);
Full_Adder FA30 (P[6][5], P[7][4], Cout[14], S[29], Cout[29]);
Full_Adder FA31 (P[5][7], P[6][6], P[7][5], S[30], Cout[30]);
Half_Adder HA32 (P[6][7], P[7][6], S[31], Cout[31]);
Half_Adder HA33 (Cout[16], S[17], S[32], Cout[32]);
Half_Adder HA34 (Cout[17], S[18], S[33], Cout[33]);
Full_Adder FA35 (S[6], Cout[18], S[19], S[34], Cout[34]);
Full_Adder FA36 (Cout[19], S[20], S[21], S[35], Cout[35]);
Full_Adder FA37 (Cout[20], Cout[21], S[22], S[36], Cout[36]);
Full_Adder FA38 (Cout[22], Cout[23], S[24], S[37], Cout[37]);
Full_Adder FA39 (Cout[24], Cout[25], S[26], S[38], Cout[38]);
Full_Adder FA40 (S[14], Cout[26], Cout[27], S[39], Cout[39]);
Half_Adder HA41 (S[15], Cout[28], S[40], Cout[40]);
Half_Adder HA42 (Cout[15], Cout[29], S[41], Cout[41]);
Half_Adder HA43 (Cout[32], S[33], S[42], Cout[42]);
Half_Adder HA44 (Cout[33], S[34], S[43], Cout[43]);
Half_Adder HA45 (Cout[34], S[35], S[44], Cout[44]);
Full_Adder FA46 (S[23], Cout[35], S[36], S[45], Cout[45]);
Full_Adder FA47 (S[25], Cout[36], S[37], S[46], Cout[46]);
Full_Adder FA48 (S[27], Cout[37], S[38], S[47], Cout[47]);
Full_Adder FA49 (S[28], Cout[38], S[39], S[48], Cout[48]);
Full_Adder FA50 (S[29], Cout[39], S[40], S[49], Cout[49]);
Full_Adder FA51 (S[30], Cout[40], S[41], S[50], Cout[50]);
Full_Adder FA52 (Cout[30], S[31], Cout[41], S[51], Cout[51]);
Half_Adder HA53 (P[7][7], Cout[31], S[52], Cout[52]);
Half_Adder HA54 (Cout[42], S[43], S[53], Cout[53]);
Full_Adder FA55 (Cout[43], S[44], Cout[53], S[54], Cout[54]);
Full_Adder FA56 (Cout[44], S[45], Cout[54], S[55], Cout[55]);
Full_Adder FA57 (Cout[45], S[46], Cout[55], S[56], Cout[56]);
Full_Adder FA58 (Cout[46], S[47], Cout[56], S[57], Cout[57]);
Full_Adder FA59 (Cout[47], S[48], Cout[57], S[58], Cout[58]);
Full_Adder FA60 (Cout[48], S[49], Cout[58], S[59], Cout[59]);
Full_Adder FA61 (Cout[49], S[50], Cout[59], S[60], Cout[60]);
Full_Adder FA62 (Cout[50], S[51], Cout[60], S[61], Cout[61]);
Full_Adder FA63 (Cout[51], S[52], Cout[61], S[62], Cout[62]);
Half_Adder HA64 (Cout[52], Cout[62], S[63], Cout[63]);
assign z[15] = S[63];
assign z[14] = S[62];
assign z[13] = S[61];
assign z[12] = S[60];
assign z[11] = S[59];
assign z[10] = S[58];
assign z[9] = S[57];
assign z[8] = S[56];
assign z[7] = S[55];
assign z[6] = S[54];
assign z[5] = S[53];
assign z[4] = S[42];
assign z[3] = S[32];
assign z[2] = S[16];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | module Mult_Wallace8 # (
parameter N = 8
)(
input [N-1:0] x,
input [N-1:0] y,
output [2*N-1:0] z
); |
wire [N-1:0] P[N-1:0];
assign P[0][0] = x[0] & y[0];
assign P[0][1] = x[0] & y[1];
assign P[0][2] = x[0] & y[2];
assign P[0][3] = x[0] & y[3];
assign P[0][4] = x[0] & y[4];
assign P[0][5] = x[0] & y[5];
assign P[0][6] = x[0] & y[6];
assign P[0][7] = x[0] & y[7];
assign P[1][0] = x[1] & y[0];
assign P[1][1] = x[1] & y[1];
assign P[1][2] = x[1] & y[2];
assign P[1][3] = x[1] & y[3];
assign P[1][4] = x[1] & y[4];
assign P[1][5] = x[1] & y[5];
assign P[1][6] = x[1] & y[6];
assign P[1][7] = x[1] & y[7];
assign P[2][0] = x[2] & y[0];
assign P[2][1] = x[2] & y[1];
assign P[2][2] = x[2] & y[2];
assign P[2][3] = x[2] & y[3];
assign P[2][4] = x[2] & y[4];
assign P[2][5] = x[2] & y[5];
assign P[2][6] = x[2] & y[6];
assign P[2][7] = x[2] & y[7];
assign P[3][0] = x[3] & y[0];
assign P[3][1] = x[3] & y[1];
assign P[3][2] = x[3] & y[2];
assign P[3][3] = x[3] & y[3];
assign P[3][4] = x[3] & y[4];
assign P[3][5] = x[3] & y[5];
assign P[3][6] = x[3] & y[6];
assign P[3][7] = x[3] & y[7];
assign P[4][0] = x[4] & y[0];
assign P[4][1] = x[4] & y[1];
assign P[4][2] = x[4] & y[2];
assign P[4][3] = x[4] & y[3];
assign P[4][4] = x[4] & y[4];
assign P[4][5] = x[4] & y[5];
assign P[4][6] = x[4] & y[6];
assign P[4][7] = x[4] & y[7];
assign P[5][0] = x[5] & y[0];
assign P[5][1] = x[5] & y[1];
assign P[5][2] = x[5] & y[2];
assign P[5][3] = x[5] & y[3];
assign P[5][4] = x[5] & y[4];
assign P[5][5] = x[5] & y[5];
assign P[5][6] = x[5] & y[6];
assign P[5][7] = x[5] & y[7];
assign P[6][0] = x[6] & y[0];
assign P[6][1] = x[6] & y[1];
assign P[6][2] = x[6] & y[2];
assign P[6][3] = x[6] & y[3];
assign P[6][4] = x[6] & y[4];
assign P[6][5] = x[6] & y[5];
assign P[6][6] = x[6] & y[6];
assign P[6][7] = x[6] & y[7];
assign P[7][0] = x[7] & y[0];
assign P[7][1] = x[7] & y[1];
assign P[7][2] = x[7] & y[2];
assign P[7][3] = x[7] & y[3];
assign P[7][4] = x[7] & y[4];
assign P[7][5] = x[7] & y[5];
assign P[7][6] = x[7] & y[6];
assign P[7][7] = x[7] & y[7];
wire [63:0] S;
wire [63:0] Cout;
Half_Adder HA1 (P[0][1], P[1][0], S[0], Cout[0]);
Full_Adder FA2 (P[0][2], P[1][1], P[2][0], S[1], Cout[1]);
Full_Adder FA3 (P[0][3], P[1][2], P[2][1], S[2], Cout[2]);
Full_Adder FA4 (P[0][4], P[1][3], P[2][2], S[3], Cout[3]);
Half_Adder HA5 (P[3][1], P[4][0], S[4], Cout[4]);
Full_Adder FA6 (P[0][5], P[1][4], P[2][3], S[5], Cout[5]);
Full_Adder FA7 (P[3][2], P[4][1], P[5][0], S[6], Cout[6]);
Full_Adder FA8 (P[0][6], P[1][5], P[2][4], S[7], Cout[7]);
Full_Adder FA9 (P[3][3], P[4][2], P[5][1], S[8], Cout[8]);
Full_Adder FA10 (P[0][7], P[1][6], P[2][5], S[9], Cout[9]);
Full_Adder FA11 (P[3][4], P[4][3], P[5][2], S[10], Cout[10]);
Full_Adder FA12 (P[1][7], P[2][6], P[3][5], S[11], Cout[11]);
Half_Adder HA13 (P[4][4], P[5][3], S[12], Cout[12]);
Full_Adder FA14 (P[2][7], P[3][6], P[4][5], S[13], Cout[13]);
Full_Adder FA15 (P[3][7], P[4][6], P[5][5], S[14], Cout[14]);
Half_Adder HA16 (P[4][7], P[5][6], S[15], Cout[15]);
Half_Adder HA17 (Cout[0], S[1], S[16], Cout[16]);
Full_Adder FA18 (P[3][0], Cout[1], S[2], S[17], Cout[17]);
Full_Adder FA19 (Cout[2], S[3], S[4], S[18], Cout[18]);
Full_Adder FA20 (Cout[3], Cout[4], S[5], S[19], Cout[19]);
Full_Adder FA21 (P[6][0], Cout[5], Cout[6], S[20], Cout[20]);
Half_Adder HA22 (S[7], S[8], S[21], Cout[21]);
Full_Adder FA23 (P[6][1], P[7][0], Cout[7], S[22], Cout[22]);
Full_Adder FA24 (Cout[8], S[9], S[10], S[23], Cout[23]);
Full_Adder FA25 (P[6][2], P[7][1], Cout[9], S[24], Cout[24]);
Full_Adder FA26 (Cout[10], S[11], S[12], S[25], Cout[25]);
Full_Adder FA27 (P[5][4], P[6][3], P[7][2], S[26], Cout[26]);
Full_Adder FA28 (Cout[11], Cout[12], S[13], S[27], Cout[27]);
Full_Adder FA29 (P[6][4], P[7][3], Cout[13], S[28], Cout[28]);
Full_Adder FA30 (P[6][5], P[7][4], Cout[14], S[29], Cout[29]);
Full_Adder FA31 (P[5][7], P[6][6], P[7][5], S[30], Cout[30]);
Half_Adder HA32 (P[6][7], P[7][6], S[31], Cout[31]);
Half_Adder HA33 (Cout[16], S[17], S[32], Cout[32]);
Half_Adder HA34 (Cout[17], S[18], S[33], Cout[33]);
Full_Adder FA35 (S[6], Cout[18], S[19], S[34], Cout[34]);
Full_Adder FA36 (Cout[19], S[20], S[21], S[35], Cout[35]);
Full_Adder FA37 (Cout[20], Cout[21], S[22], S[36], Cout[36]);
Full_Adder FA38 (Cout[22], Cout[23], S[24], S[37], Cout[37]);
Full_Adder FA39 (Cout[24], Cout[25], S[26], S[38], Cout[38]);
Full_Adder FA40 (S[14], Cout[26], Cout[27], S[39], Cout[39]);
Half_Adder HA41 (S[15], Cout[28], S[40], Cout[40]);
Half_Adder HA42 (Cout[15], Cout[29], S[41], Cout[41]);
Half_Adder HA43 (Cout[32], S[33], S[42], Cout[42]);
Half_Adder HA44 (Cout[33], S[34], S[43], Cout[43]);
Half_Adder HA45 (Cout[34], S[35], S[44], Cout[44]);
Full_Adder FA46 (S[23], Cout[35], S[36], S[45], Cout[45]);
Full_Adder FA47 (S[25], Cout[36], S[37], S[46], Cout[46]);
Full_Adder FA48 (S[27], Cout[37], S[38], S[47], Cout[47]);
Full_Adder FA49 (S[28], Cout[38], S[39], S[48], Cout[48]);
Full_Adder FA50 (S[29], Cout[39], S[40], S[49], Cout[49]);
Full_Adder FA51 (S[30], Cout[40], S[41], S[50], Cout[50]);
Full_Adder FA52 (Cout[30], S[31], Cout[41], S[51], Cout[51]);
Half_Adder HA53 (P[7][7], Cout[31], S[52], Cout[52]);
Half_Adder HA54 (Cout[42], S[43], S[53], Cout[53]);
Full_Adder FA55 (Cout[43], S[44], Cout[53], S[54], Cout[54]);
Full_Adder FA56 (Cout[44], S[45], Cout[54], S[55], Cout[55]);
Full_Adder FA57 (Cout[45], S[46], Cout[55], S[56], Cout[56]);
Full_Adder FA58 (Cout[46], S[47], Cout[56], S[57], Cout[57]);
Full_Adder FA59 (Cout[47], S[48], Cout[57], S[58], Cout[58]);
Full_Adder FA60 (Cout[48], S[49], Cout[58], S[59], Cout[59]);
Full_Adder FA61 (Cout[49], S[50], Cout[59], S[60], Cout[60]);
Full_Adder FA62 (Cout[50], S[51], Cout[60], S[61], Cout[61]);
Full_Adder FA63 (Cout[51], S[52], Cout[61], S[62], Cout[62]);
Half_Adder HA64 (Cout[52], Cout[62], S[63], Cout[63]);
assign z[15] = S[63];
assign z[14] = S[62];
assign z[13] = S[61];
assign z[12] = S[60];
assign z[11] = S[59];
assign z[10] = S[58];
assign z[9] = S[57];
assign z[8] = S[56];
assign z[7] = S[55];
assign z[6] = S[54];
assign z[5] = S[53];
assign z[4] = S[42];
assign z[3] = S[32];
assign z[2] = S[16];
assign z[1] = S[0];
assign z[0] = P[0][0];
endmodule | 4 |
142,197 | data/full_repos/permissive/98115107/alarm_clock.v | 98,115,107 | alarm_clock.v | v | 379 | 105 | [] | [] | [] | [(1, 72), (74, 120), (122, 210), (213, 358), (360, 378)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/98115107/alarm_clock.v:98: Cell has missing pin: \'ld_alarm\'\n datapath D0(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:158: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_end: next_state = s_end; \n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:159: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n default: next_state = s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_hour1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:206: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_alarm;\n ^~\n%Error: Exiting due to 42 warning(s)\n' | 313,324 | module | module alarm_clock(SW, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, CLOCK_50, KEY, LEDG);
input [9:0] SW;
input CLOCK_50;
input [2:0] KEY;
output [6:0] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
output [0:0] LEDG;
wire resetn, load, alarm_reset, alarm_en, alarm_out;
wire [3:0] min1, min2, hour1, hour2, sec1, sec2, timer1, timer2;
assign load = ~KEY[1];
assign resetn = ~KEY[0];
assign alarm_reset = ~KEY[2];
assign alarm_out = LEDG[0];
myClock c0(
.clk(CLOCK_50),
.resetn(resetn),
.alarm_reset(alarm_reset),
.go(load),
.data_in(SW[3:0]),
.min1(min1),
.min2(min2),
.hour1(hour1),
.hour2(hour2),
.sec1(sec1),
.sec2(sec2),
.timer1(timer1),
.timer2(timer2),
.alarm_out(alarm_out)
);
hex_decoder_9MAX H7(
.hex_digit(hour1),
.segments(HEX7)
);
hex_decoder_9MAX H6(
.hex_digit(hour2),
.segments(HEX6)
);
hex_decoder_9MAX H5(
.hex_digit(min1),
.segments(HEX5)
);
hex_decoder_9MAX H4(
.hex_digit(min2),
.segments(HEX4)
);
hex_decoder_9MAX H3(
.hex_digit(sec1),
.segments(HEX3)
);
hex_decoder_9MAX H2(
.hex_digit(sec2),
.segments(HEX2)
);
hex_decoder_9MAX H1(
.hex_digit(timer1),
.segments(HEX1)
);
hex_decoder_9MAX H0(
.hex_digit(timer2),
.segments(HEX0)
);
endmodule | module alarm_clock(SW, HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0, CLOCK_50, KEY, LEDG); |
input [9:0] SW;
input CLOCK_50;
input [2:0] KEY;
output [6:0] HEX7, HEX6, HEX5, HEX4, HEX3, HEX2, HEX1, HEX0;
output [0:0] LEDG;
wire resetn, load, alarm_reset, alarm_en, alarm_out;
wire [3:0] min1, min2, hour1, hour2, sec1, sec2, timer1, timer2;
assign load = ~KEY[1];
assign resetn = ~KEY[0];
assign alarm_reset = ~KEY[2];
assign alarm_out = LEDG[0];
myClock c0(
.clk(CLOCK_50),
.resetn(resetn),
.alarm_reset(alarm_reset),
.go(load),
.data_in(SW[3:0]),
.min1(min1),
.min2(min2),
.hour1(hour1),
.hour2(hour2),
.sec1(sec1),
.sec2(sec2),
.timer1(timer1),
.timer2(timer2),
.alarm_out(alarm_out)
);
hex_decoder_9MAX H7(
.hex_digit(hour1),
.segments(HEX7)
);
hex_decoder_9MAX H6(
.hex_digit(hour2),
.segments(HEX6)
);
hex_decoder_9MAX H5(
.hex_digit(min1),
.segments(HEX5)
);
hex_decoder_9MAX H4(
.hex_digit(min2),
.segments(HEX4)
);
hex_decoder_9MAX H3(
.hex_digit(sec1),
.segments(HEX3)
);
hex_decoder_9MAX H2(
.hex_digit(sec2),
.segments(HEX2)
);
hex_decoder_9MAX H1(
.hex_digit(timer1),
.segments(HEX1)
);
hex_decoder_9MAX H0(
.hex_digit(timer2),
.segments(HEX0)
);
endmodule | 0 |
142,198 | data/full_repos/permissive/98115107/alarm_clock.v | 98,115,107 | alarm_clock.v | v | 379 | 105 | [] | [] | [] | [(1, 72), (74, 120), (122, 210), (213, 358), (360, 378)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/98115107/alarm_clock.v:98: Cell has missing pin: \'ld_alarm\'\n datapath D0(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:158: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_end: next_state = s_end; \n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:159: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n default: next_state = s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_hour1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:206: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_alarm;\n ^~\n%Error: Exiting due to 42 warning(s)\n' | 313,324 | module | module myClock(
input clk,
input resetn, alarm_reset, go,
input [3:0] data_in,
output [3:0] hour1, hour2, min1, min2, sec1, sec2, timer1, timer2,
output alarm_out
);
wire ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start;
control C0(
.clk(clk),
.resetn(resetn),
.reset_alarm(alarm_reset),
.go(go),
.ld_alarm(ld_alarm),
.ld_hour1(ld_hour1),
.ld_hour2(ld_hour2),
.ld_min1(ld_min1),
.ld_min2(ld_min2),
.start(start)
);
datapath D0(
.clk(clk),
.resetn(resetn),
.reset_alarm(alarm_reset),
.ld_hour1(ld_hour1),
.ld_hour2(ld_hour2),
.ld_min1(ld_min1),
.ld_min2(ld_min2),
.start(start),
.data_in(data_in),
.hour1(hour1),
.hour2(hour2),
.min1(min1),
.min2(min2),
.sec1(sec1),
.sec2(sec2),
.timer1(timer1),
.timer2(timer2),
.alarm_out(alarm_out)
);
endmodule | module myClock(
input clk,
input resetn, alarm_reset, go,
input [3:0] data_in,
output [3:0] hour1, hour2, min1, min2, sec1, sec2, timer1, timer2,
output alarm_out
); |
wire ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start;
control C0(
.clk(clk),
.resetn(resetn),
.reset_alarm(alarm_reset),
.go(go),
.ld_alarm(ld_alarm),
.ld_hour1(ld_hour1),
.ld_hour2(ld_hour2),
.ld_min1(ld_min1),
.ld_min2(ld_min2),
.start(start)
);
datapath D0(
.clk(clk),
.resetn(resetn),
.reset_alarm(alarm_reset),
.ld_hour1(ld_hour1),
.ld_hour2(ld_hour2),
.ld_min1(ld_min1),
.ld_min2(ld_min2),
.start(start),
.data_in(data_in),
.hour1(hour1),
.hour2(hour2),
.min1(min1),
.min2(min2),
.sec1(sec1),
.sec2(sec2),
.timer1(timer1),
.timer2(timer2),
.alarm_out(alarm_out)
);
endmodule | 0 |
142,199 | data/full_repos/permissive/98115107/alarm_clock.v | 98,115,107 | alarm_clock.v | v | 379 | 105 | [] | [] | [] | [(1, 72), (74, 120), (122, 210), (213, 358), (360, 378)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/98115107/alarm_clock.v:98: Cell has missing pin: \'ld_alarm\'\n datapath D0(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:158: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_end: next_state = s_end; \n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:159: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n default: next_state = s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_hour1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:206: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_alarm;\n ^~\n%Error: Exiting due to 42 warning(s)\n' | 313,324 | module | module control(
input clk,
input resetn,
input reset_alarm,
input go,
output reg ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start
);
reg [5:0] current_state, next_state;
localparam s_ld_hour1 = 5'd0,
s_ld_hour1_wait = 5'd1,
s_ld_hour2 = 5'd2,
s_ld_hour2_wait = 5'd3,
s_ld_min1 = 5'd4,
s_ld_min1_wait = 5'd5,
s_ld_min2 = 5'd6,
s_ld_min2_wait = 5'd7,
s_ld_alarm = 5'd8,
s_ld_alarm_wait = 5'd9,
s_end = 5'd10;
always@(*)
begin: state_table
case (current_state)
s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;
s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;
s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;
s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;
s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;
s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;
s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;
s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;
s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;
s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;
s_end: next_state = s_end;
default: next_state = s_ld_hour1;
endcase
end
always @(*)
begin: enable_signals
ld_min1 <= 1'b0;
ld_min2 <= 1'b0;
ld_hour1 <= 1'b0;
ld_hour2 <= 1'b0;
ld_alarm <= 1'b0;
start <= 1'b0;
case (current_state)
s_ld_hour1: begin
ld_hour1 <= 1'b1;
end
s_ld_hour2: begin
ld_hour2 <= 1'b1;
end
s_ld_min1: begin
ld_min1 <= 1'b1;
end
s_ld_min2: begin
ld_min2 <= 1'b1;
end
s_ld_alarm: begin
ld_alarm <= 1'b1;
end
s_end: begin
start <= 1'b1;
ld_hour1 <= 1'b0;
ld_hour2 <= 1'b0;
ld_min1 <= 1'b0;
ld_min2 <= 1'b0;
ld_alarm <= 1'b0;
end
endcase
end
always@(posedge clk)
begin: clock_FFs
if(resetn)
current_state <= s_ld_hour1;
else if(reset_alarm)
current_state <= s_ld_alarm;
else
current_state <= next_state;
end
endmodule | module control(
input clk,
input resetn,
input reset_alarm,
input go,
output reg ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start
); |
reg [5:0] current_state, next_state;
localparam s_ld_hour1 = 5'd0,
s_ld_hour1_wait = 5'd1,
s_ld_hour2 = 5'd2,
s_ld_hour2_wait = 5'd3,
s_ld_min1 = 5'd4,
s_ld_min1_wait = 5'd5,
s_ld_min2 = 5'd6,
s_ld_min2_wait = 5'd7,
s_ld_alarm = 5'd8,
s_ld_alarm_wait = 5'd9,
s_end = 5'd10;
always@(*)
begin: state_table
case (current_state)
s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;
s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;
s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;
s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;
s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;
s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;
s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;
s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;
s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;
s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;
s_end: next_state = s_end;
default: next_state = s_ld_hour1;
endcase
end
always @(*)
begin: enable_signals
ld_min1 <= 1'b0;
ld_min2 <= 1'b0;
ld_hour1 <= 1'b0;
ld_hour2 <= 1'b0;
ld_alarm <= 1'b0;
start <= 1'b0;
case (current_state)
s_ld_hour1: begin
ld_hour1 <= 1'b1;
end
s_ld_hour2: begin
ld_hour2 <= 1'b1;
end
s_ld_min1: begin
ld_min1 <= 1'b1;
end
s_ld_min2: begin
ld_min2 <= 1'b1;
end
s_ld_alarm: begin
ld_alarm <= 1'b1;
end
s_end: begin
start <= 1'b1;
ld_hour1 <= 1'b0;
ld_hour2 <= 1'b0;
ld_min1 <= 1'b0;
ld_min2 <= 1'b0;
ld_alarm <= 1'b0;
end
endcase
end
always@(posedge clk)
begin: clock_FFs
if(resetn)
current_state <= s_ld_hour1;
else if(reset_alarm)
current_state <= s_ld_alarm;
else
current_state <= next_state;
end
endmodule | 0 |
142,200 | data/full_repos/permissive/98115107/alarm_clock.v | 98,115,107 | alarm_clock.v | v | 379 | 105 | [] | [] | [] | [(1, 72), (74, 120), (122, 210), (213, 358), (360, 378)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/98115107/alarm_clock.v:98: Cell has missing pin: \'ld_alarm\'\n datapath D0(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:158: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_end: next_state = s_end; \n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:159: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n default: next_state = s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_hour1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:206: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_alarm;\n ^~\n%Error: Exiting due to 42 warning(s)\n' | 313,324 | module | module datapath(
input clk,
input resetn, reset_alarm,
input [3:0] data_in,
input ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start,
output reg [3:0] hour1,
output reg [3:0] hour2,
output reg [3:0] min1,
output reg [3:0] min2,
output reg [3:0] sec1,
output reg [3:0] sec2,
output reg [3:0] timer1,
output reg [3:0] timer2,
output reg alarm_out
);
reg [3:0] hour1_val, hour2_val, min1_val, min2_val, sec1_val, sec2_val, timer1_val, timer2_val;
reg [7:0] alarm_max;
reg [27:0] counter_1s;
localparam counter_1s_max = 28'b10111110101111000001111111;
always@(posedge clk) begin
if(resetn) begin
hour1 <= 4'b0;
hour2 <= 4'b0;
min1 <= 4'b0;
min2 <= 4'b0;
sec1 <= 4'b0;
sec2 <= 4'b0;
timer1 <= 4'b0;
timer2 <= 4'b0;
end
if (reset_alarm) begin
timer1 <= 4'b0;
timer2 <= 4'b0;
end
else begin
counter_1s <= 28'd0;
if(ld_hour1) begin
hour1 <= data_in;
hour1_val <= data_in;
end
if(ld_hour2) begin
hour2 <= data_in;
hour2_val <= data_in;
end
if(ld_min1) begin
min1 <= data_in;
min1_val <= data_in;
end
if(ld_min2) begin
min2 <= data_in;
min2_val <= data_in;
end
if(ld_alarm) begin
case(data_in)
4'b0000:
begin
timer1 <= 4'd1;
timer2 <= 4'd5;
end
4'b0001:
begin
timer1 <= 4'd3;
timer2 <= 4'd0;
end
4'b0010:
begin
timer1 <= 4'd4;
timer2 <= 4'd5;
end
4'b0011:
begin
timer1 <= 4'd6;
timer2 <= 4'd0;
end
default:
begin
timer1 <= 4'd1;
timer2 <= 4'd5;
end
endcase
end
end
if (start) begin
hour1 <= hour1_val;
hour2 <= hour2_val;
min1 <= min1_val;
min2 <= min2_val;
sec1 <= sec1_val;
sec2 <= sec2_val;
counter_1s <= counter_1s + 1'b1;
if (counter_1s == counter_1s_max) begin
if (timer2 == 4'd0) begin
timer2 <= 4'd9;
timer1 <= timer1 - 1'b1;
end else begin
timer2 <= timer2 - 1'b1;
end
if ({timer1, timer2} == 8'b0) begin
alarm_out <= 1'b1;
end
counter_1s <= 28'b0;
sec2_val <= sec2_val + 1'b1;
if (sec2_val >= 9) begin
sec1_val <= sec1_val + 1'b1;
sec2_val <= 4'd0;
end
if ({sec1_val, sec2_val} >= 8'h59) begin
sec1_val <= 4'd0;
sec2_val <= 4'd0;
min2_val <= min2_val + 1'b1;
end
if (min2_val >= 9) begin
min1_val <= min1_val + 1'b1;
min2_val <= 4'd0;
end
if ({min1_val, min2_val} >= 8'h59) begin
min1_val <= 4'd0;
min2_val <= 4'd0;
hour2_val <= hour2_val + 1'b1;
end
if ({hour1_val, hour2_val} >= 8'h24) begin
hour1_val <= 4'b0;
hour2_val <= 4'b0;
end
end
end
end
endmodule | module datapath(
input clk,
input resetn, reset_alarm,
input [3:0] data_in,
input ld_min1, ld_min2, ld_hour1, ld_hour2, ld_alarm, start,
output reg [3:0] hour1,
output reg [3:0] hour2,
output reg [3:0] min1,
output reg [3:0] min2,
output reg [3:0] sec1,
output reg [3:0] sec2,
output reg [3:0] timer1,
output reg [3:0] timer2,
output reg alarm_out
); |
reg [3:0] hour1_val, hour2_val, min1_val, min2_val, sec1_val, sec2_val, timer1_val, timer2_val;
reg [7:0] alarm_max;
reg [27:0] counter_1s;
localparam counter_1s_max = 28'b10111110101111000001111111;
always@(posedge clk) begin
if(resetn) begin
hour1 <= 4'b0;
hour2 <= 4'b0;
min1 <= 4'b0;
min2 <= 4'b0;
sec1 <= 4'b0;
sec2 <= 4'b0;
timer1 <= 4'b0;
timer2 <= 4'b0;
end
if (reset_alarm) begin
timer1 <= 4'b0;
timer2 <= 4'b0;
end
else begin
counter_1s <= 28'd0;
if(ld_hour1) begin
hour1 <= data_in;
hour1_val <= data_in;
end
if(ld_hour2) begin
hour2 <= data_in;
hour2_val <= data_in;
end
if(ld_min1) begin
min1 <= data_in;
min1_val <= data_in;
end
if(ld_min2) begin
min2 <= data_in;
min2_val <= data_in;
end
if(ld_alarm) begin
case(data_in)
4'b0000:
begin
timer1 <= 4'd1;
timer2 <= 4'd5;
end
4'b0001:
begin
timer1 <= 4'd3;
timer2 <= 4'd0;
end
4'b0010:
begin
timer1 <= 4'd4;
timer2 <= 4'd5;
end
4'b0011:
begin
timer1 <= 4'd6;
timer2 <= 4'd0;
end
default:
begin
timer1 <= 4'd1;
timer2 <= 4'd5;
end
endcase
end
end
if (start) begin
hour1 <= hour1_val;
hour2 <= hour2_val;
min1 <= min1_val;
min2 <= min2_val;
sec1 <= sec1_val;
sec2 <= sec2_val;
counter_1s <= counter_1s + 1'b1;
if (counter_1s == counter_1s_max) begin
if (timer2 == 4'd0) begin
timer2 <= 4'd9;
timer1 <= timer1 - 1'b1;
end else begin
timer2 <= timer2 - 1'b1;
end
if ({timer1, timer2} == 8'b0) begin
alarm_out <= 1'b1;
end
counter_1s <= 28'b0;
sec2_val <= sec2_val + 1'b1;
if (sec2_val >= 9) begin
sec1_val <= sec1_val + 1'b1;
sec2_val <= 4'd0;
end
if ({sec1_val, sec2_val} >= 8'h59) begin
sec1_val <= 4'd0;
sec2_val <= 4'd0;
min2_val <= min2_val + 1'b1;
end
if (min2_val >= 9) begin
min1_val <= min1_val + 1'b1;
min2_val <= 4'd0;
end
if ({min1_val, min2_val} >= 8'h59) begin
min1_val <= 4'd0;
min2_val <= 4'd0;
hour2_val <= hour2_val + 1'b1;
end
if ({hour1_val, hour2_val} >= 8'h24) begin
hour1_val <= 4'b0;
hour2_val <= 4'b0;
end
end
end
end
endmodule | 0 |
142,201 | data/full_repos/permissive/98115107/alarm_clock.v | 98,115,107 | alarm_clock.v | v | 379 | 105 | [] | [] | [] | [(1, 72), (74, 120), (122, 210), (213, 358), (360, 378)] | null | null | 1: b'%Warning-PINMISSING: data/full_repos/permissive/98115107/alarm_clock.v:98: Cell has missing pin: \'ld_alarm\'\n datapath D0(\n ^~\n ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:148: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1: next_state = go ? s_ld_hour1_wait : s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:149: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour1_wait: next_state = go ? s_ld_hour1_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:150: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2: next_state = go ? s_ld_hour2_wait : s_ld_hour2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:151: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_hour2_wait: next_state = go ? s_ld_hour2_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:152: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1: next_state = go ? s_ld_min1_wait : s_ld_min1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:153: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min1_wait: next_state = go ? s_ld_min1_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:154: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2: next_state = go ? s_ld_min2_wait : s_ld_min2;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:155: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_min2_wait: next_state = go ? s_ld_min2_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:156: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm: next_state = go ? s_ld_alarm_wait : s_ld_alarm;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional True, but Conditional True\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:157: Operator COND expects 6 bits on the Conditional False, but Conditional False\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_ld_alarm_wait: next_state = go ? s_ld_alarm_wait : s_end;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:158: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n s_end: next_state = s_end; \n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:159: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n default: next_state = s_ld_hour1;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm_wait\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:147: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_hour2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_min2\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:174: Operator CASE expects 6 bits on the Case Item, but Case Item\'s VARREF \'s_end\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n case (current_state)\n ^~~~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:204: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_hour1\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_hour1;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98115107/alarm_clock.v:206: Operator ASSIGNDLY expects 6 bits on the Assign RHS, but Assign RHS\'s VARREF \'s_ld_alarm\' generates 5 bits.\n : ... In instance alarm_clock.c0.C0\n current_state <= s_ld_alarm;\n ^~\n%Error: Exiting due to 42 warning(s)\n' | 313,324 | module | module hex_decoder_9MAX(hex_digit, segments);
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
default: segments = 7'b100_0000;
endcase
endmodule | module hex_decoder_9MAX(hex_digit, segments); |
input [3:0] hex_digit;
output reg [6:0] segments;
always @(*)
case (hex_digit)
4'h0: segments = 7'b100_0000;
4'h1: segments = 7'b111_1001;
4'h2: segments = 7'b010_0100;
4'h3: segments = 7'b011_0000;
4'h4: segments = 7'b001_1001;
4'h5: segments = 7'b001_0010;
4'h6: segments = 7'b000_0010;
4'h7: segments = 7'b111_1000;
4'h8: segments = 7'b000_0000;
4'h9: segments = 7'b001_1000;
default: segments = 7'b100_0000;
endcase
endmodule | 0 |
142,202 | data/full_repos/permissive/98235620/crossdomain/crossdomain_signal.v | 98,235,620 | crossdomain_signal.v | v | 42 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xa9 in position 97: invalid start byte | data/verilator_xmls/c83adf40-b1c0-4ff0-8a6e-a7facd9e8d2e.xml | null | 313,325 | module | module crossdomain_signal (
input reset,
input clk_b,
input sig_domain_a,
output sig_domain_b
);
reg [1:0] sig_domain_b_reg;
always @(posedge reset or posedge clk_b) begin
if (reset) begin
sig_domain_b_reg <= 2'b0;
end
else begin
sig_domain_b_reg[1:0] <= { sig_domain_b_reg[0], sig_domain_a };
end
end
assign sig_domain_b = sig_domain_b_reg[1];
endmodule | module crossdomain_signal (
input reset,
input clk_b,
input sig_domain_a,
output sig_domain_b
); |
reg [1:0] sig_domain_b_reg;
always @(posedge reset or posedge clk_b) begin
if (reset) begin
sig_domain_b_reg <= 2'b0;
end
else begin
sig_domain_b_reg[1:0] <= { sig_domain_b_reg[0], sig_domain_a };
end
end
assign sig_domain_b = sig_domain_b_reg[1];
endmodule | 2 |
142,204 | data/full_repos/permissive/98235620/i2s/tb_module_i2s.v | 98,235,620 | tb_module_i2s.v | v | 120 | 81 | [] | ['general public license', 'free software foundation'] | [] | null | 'utf-8' codec can't decode byte 0xa9 in position 97: invalid start byte | null | 1: b'%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:62: Unsupported or unknown PLI call: $timeformat\n initial $timeformat(-9, 0, " ns", 0);\n ^~~~~~~~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:65: Unsupported: Ignoring delay on this delayed statement.\n #5;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:73: syntax error, unexpected \'@\'\n repeat (100) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:83: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:84: syntax error, unexpected \'@\'\n while (reset) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:93: syntax error, unexpected \'@\'\n repeat (SAMPLE_NCLKS_HALF) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:95: syntax error, unexpected \'@\'\n repeat (SAMPLE_NCLKS_HALF) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:102: syntax error, unexpected \'@\'\n repeat (1000) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:110: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:112: syntax error, unexpected \'@\'\n while (reset) @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98235620/i2s/tb_module_i2s.v:114: syntax error, unexpected \'@\'\n repeat (SAMPLE_NCLKS) @(posedge clk);\n ^\n%Error: Exiting due to 10 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,327 | module | module tb_module_i2s();
localparam CLK_FREQ = 100_000_000;
localparam SAMPLE_WIDTH = 16;
localparam SAMPLE_RATE = 48000;
localparam SAMPLE_FREQ = SAMPLE_RATE * SAMPLE_WIDTH * 2;
localparam SAMPLE_NCLKS = CLK_FREQ / SAMPLE_FREQ;
localparam SAMPLE_NCLKS_HALF = SAMPLE_NCLKS / 2;
reg clk;
reg reset;
reg bclk;
reg lrclk;
reg adcda;
reg [SAMPLE_WIDTH-1:0] left_in;
reg [SAMPLE_WIDTH-1:0] right_in;
wire [SAMPLE_WIDTH-1:0] left_out;
wire [SAMPLE_WIDTH-1:0] right_out;
wire dataready;
wire bclk_s;
wire lrclk_s;
wire dacda;
i2s #(SAMPLE_WIDTH) dut (
.clk (clk ),
.reset (reset ),
.bclk (bclk ),
.lrclk (lrclk ),
.adcda (adcda ),
.left_in (left_in ),
.right_in (right_in ),
.left_out (left_out ),
.right_out (right_out ),
.dataready (dataready ),
.bclk_s (bclk_s ),
.lrclk_s (lrclk_s ),
.dacda (dacda )
);
initial $timeformat(-9, 0, " ns", 0);
always begin
#5;
clk <= ~clk;
end
initial begin
clk <= 0;
reset <= 1;
repeat (100) @(posedge clk);
reset <= 0;
end
initial begin
bclk <= 0;
lrclk <= 0;
adcda <= 0;
@(posedge clk);
while (reset) @(posedge clk);
bclk <= 0;
lrclk <= 0;
adcda <= 0;
forever begin
repeat (2) begin
repeat (SAMPLE_WIDTH+5) begin
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b1;
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b0;
adcda <= $random % 2;
end
lrclk <= ~lrclk;
end
repeat (1000) @(posedge clk);
end
end
initial begin
left_in <= 0;
right_in <= 0;
@(posedge clk);
while (reset) @(posedge clk);
repeat (SAMPLE_NCLKS) @(posedge clk);
left_in <= $random();
right_in <= $random();
end
endmodule | module tb_module_i2s(); |
localparam CLK_FREQ = 100_000_000;
localparam SAMPLE_WIDTH = 16;
localparam SAMPLE_RATE = 48000;
localparam SAMPLE_FREQ = SAMPLE_RATE * SAMPLE_WIDTH * 2;
localparam SAMPLE_NCLKS = CLK_FREQ / SAMPLE_FREQ;
localparam SAMPLE_NCLKS_HALF = SAMPLE_NCLKS / 2;
reg clk;
reg reset;
reg bclk;
reg lrclk;
reg adcda;
reg [SAMPLE_WIDTH-1:0] left_in;
reg [SAMPLE_WIDTH-1:0] right_in;
wire [SAMPLE_WIDTH-1:0] left_out;
wire [SAMPLE_WIDTH-1:0] right_out;
wire dataready;
wire bclk_s;
wire lrclk_s;
wire dacda;
i2s #(SAMPLE_WIDTH) dut (
.clk (clk ),
.reset (reset ),
.bclk (bclk ),
.lrclk (lrclk ),
.adcda (adcda ),
.left_in (left_in ),
.right_in (right_in ),
.left_out (left_out ),
.right_out (right_out ),
.dataready (dataready ),
.bclk_s (bclk_s ),
.lrclk_s (lrclk_s ),
.dacda (dacda )
);
initial $timeformat(-9, 0, " ns", 0);
always begin
#5;
clk <= ~clk;
end
initial begin
clk <= 0;
reset <= 1;
repeat (100) @(posedge clk);
reset <= 0;
end
initial begin
bclk <= 0;
lrclk <= 0;
adcda <= 0;
@(posedge clk);
while (reset) @(posedge clk);
bclk <= 0;
lrclk <= 0;
adcda <= 0;
forever begin
repeat (2) begin
repeat (SAMPLE_WIDTH+5) begin
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b1;
repeat (SAMPLE_NCLKS_HALF) @(posedge clk);
bclk <= 1'b0;
adcda <= $random % 2;
end
lrclk <= ~lrclk;
end
repeat (1000) @(posedge clk);
end
end
initial begin
left_in <= 0;
right_in <= 0;
@(posedge clk);
while (reset) @(posedge clk);
repeat (SAMPLE_NCLKS) @(posedge clk);
left_in <= $random();
right_in <= $random();
end
endmodule | 2 |
142,205 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/0208/src/fmrv32im_timer.v | 98,419,535 | fmrv32im_timer.v | v | 52 | 47 | [] | [] | [] | [(1, 51)] | null | data/verilator_xmls/05767985-6d09-45d0-b51b-06b3ac5e8bd8.xml | null | 313,350 | module | module fmrv32im_timer
(
input RST_N,
input CLK,
input BUS_WE,
input [3:0] BUS_ADDR,
input [31:0] BUS_WDATA,
output reg [31:0] BUS_RDATA,
output wire EXPIRED
);
reg [31:0] counter, mask;
always @(posedge CLK) begin
if(!RST_N) begin
counter <= 0;
mask <= 0;
end else begin
if(BUS_WE & (BUS_ADDR == 4'h0)) begin
counter <= BUS_WDATA;
end else begin
counter <= counter + 32'd1;
end
if(BUS_WE & (BUS_ADDR == 4'h1)) begin
mask <= BUS_WDATA;
end
end
end
assign EXPIRED = (counter >= mask);
always @(*) begin
case(BUS_ADDR)
4'h0:
begin
BUS_RDATA <= counter;
end
4'h1:
begin
BUS_RDATA <= mask;
end
default:
begin
BUS_RDATA <= 32'd0;
end
endcase
end
endmodule | module fmrv32im_timer
(
input RST_N,
input CLK,
input BUS_WE,
input [3:0] BUS_ADDR,
input [31:0] BUS_WDATA,
output reg [31:0] BUS_RDATA,
output wire EXPIRED
); |
reg [31:0] counter, mask;
always @(posedge CLK) begin
if(!RST_N) begin
counter <= 0;
mask <= 0;
end else begin
if(BUS_WE & (BUS_ADDR == 4'h0)) begin
counter <= BUS_WDATA;
end else begin
counter <= counter + 32'd1;
end
if(BUS_WE & (BUS_ADDR == 4'h1)) begin
mask <= BUS_WDATA;
end
end
end
assign EXPIRED = (counter >= mask);
always @(*) begin
case(BUS_ADDR)
4'h0:
begin
BUS_RDATA <= counter;
end
4'h1:
begin
BUS_RDATA <= mask;
end
default:
begin
BUS_RDATA <= 32'd0;
end
endcase
end
endmodule | 15 |
142,211 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_decode.v | 98,419,535 | fmrv32im_decode.v | v | 299 | 88 | [] | [] | [] | [(1, 298)] | null | data/verilator_xmls/b5c8ae8f-94ab-4c40-8f29-9129ff718100.xml | null | 313,357 | module | module fmrv32im_decode
(
input RST_N,
input CLK,
input wire [31:0] INST_CODE,
output wire [4:0] RD_NUM,
output wire [4:0] RS1_NUM,
output wire [4:0] RS2_NUM,
output reg [31:0] IMM,
output reg INST_LUI,
output reg INST_AUIPC,
output reg INST_JAL,
output reg INST_JALR,
output reg INST_BEQ,
output reg INST_BNE,
output reg INST_BLT,
output reg INST_BGE,
output reg INST_BLTU,
output reg INST_BGEU,
output reg INST_LB,
output reg INST_LH,
output reg INST_LW,
output reg INST_LBU,
output reg INST_LHU,
output reg INST_SB,
output reg INST_SH,
output reg INST_SW,
output reg INST_ADDI,
output reg INST_SLTI,
output reg INST_SLTIU,
output reg INST_XORI,
output reg INST_ORI,
output reg INST_ANDI,
output reg INST_SLLI,
output reg INST_SRLI,
output reg INST_SRAI,
output reg INST_ADD,
output reg INST_SUB,
output reg INST_SLL,
output reg INST_SLT,
output reg INST_SLTU,
output reg INST_XOR,
output reg INST_SRL,
output reg INST_SRA,
output reg INST_OR,
output reg INST_AND,
output reg INST_FENCE,
output reg INST_FENCEI,
output reg INST_ECALL,
output reg INST_EBREAK,
output reg INST_MRET,
output reg INST_CSRRW,
output reg INST_CSRRS,
output reg INST_CSRRC,
output reg INST_CSRRWI,
output reg INST_CSRRSI,
output reg INST_CSRRCI,
output reg INST_MUL,
output reg INST_MULH,
output reg INST_MULHSU,
output reg INST_MULHU,
output reg INST_DIV,
output reg INST_DIVU,
output reg INST_REM,
output reg INST_REMU,
output reg INST_CUSTOM0,
output wire ILL_INST
);
reg r_type, i_type, s_type, b_type, u_type, j_type;
reg c0_type;
always @(*) begin
r_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b100);
i_type <= ((INST_CODE[6:5] == 2'b00) && ((INST_CODE[4:2] == 3'b000) ||
(INST_CODE[4:2] == 3'b011) ||
(INST_CODE[4:2] == 3'b100))) ||
((INST_CODE[6:5] == 2'b11) && ((INST_CODE[4:2] == 3'b001) ||
(INST_CODE[4:2] == 3'b100)));
s_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b000);
b_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b000);
u_type <= ((INST_CODE[6:5] == 2'b00) || (INST_CODE[6:5] == 2'b01)) &&
(INST_CODE[4:2] == 3'b101);
j_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b011);
c0_type <= (INST_CODE[6:5] == 2'b00) && (INST_CODE[4:2] == 3'b010);
end
always @(posedge CLK) begin
if(!RST_N) begin
IMM <= 0;
end else begin
IMM <= (i_type)?{{21{INST_CODE[31]}},
INST_CODE[30:20]}:
(s_type)?{{21{INST_CODE[31]}},
INST_CODE[30:25], INST_CODE[11:7]}:
(b_type)?{{20{INST_CODE[31]}},
INST_CODE[7], INST_CODE[30:25], INST_CODE[11:8], 1'b0}:
(u_type)?{INST_CODE[31:12], 12'b0000_0000_0000}:
(j_type)?{{12{INST_CODE[31]}},
INST_CODE[19:12], INST_CODE[20], INST_CODE[30:21], 1'b0}:
32'd0;
end
end
assign RD_NUM = (r_type | i_type | u_type | j_type | c0_type)?INST_CODE[11:7]:5'd0;
assign RS1_NUM = (r_type | i_type | s_type | b_type)?INST_CODE[19:15]:5'd0;
assign RS2_NUM = (r_type | s_type | b_type)?INST_CODE[24:20]:5'd0;
wire [2:0] func3;
wire [6:0] func7;
assign func3 = INST_CODE[14:12];
assign func7 = INST_CODE[31:25];
always @(posedge CLK) begin
if(!RST_N) begin
INST_LUI <= 1'b0;
INST_AUIPC <= 1'b0;
INST_JAL <= 1'b0;
INST_JALR <= 1'b0;
INST_BEQ <= 1'b0;
INST_BNE <= 1'b0;
INST_BLT <= 1'b0;
INST_BGE <= 1'b0;
INST_BLTU <= 1'b0;
INST_BGEU <= 1'b0;
INST_LB <= 1'b0;
INST_LH <= 1'b0;
INST_LW <= 1'b0;
INST_LBU <= 1'b0;
INST_LHU <= 1'b0;
INST_SB <= 1'b0;
INST_SH <= 1'b0;
INST_SW <= 1'b0;
INST_ADDI <= 1'b0;
INST_SLTI <= 1'b0;
INST_SLTIU <= 1'b0;
INST_XORI <= 1'b0;
INST_ORI <= 1'b0;
INST_ANDI <= 1'b0;
INST_SLLI <= 1'b0;
INST_SRLI <= 1'b0;
INST_SRAI <= 1'b0;
INST_ADD <= 1'b0;
INST_SUB <= 1'b0;
INST_SLL <= 1'b0;
INST_SLT <= 1'b0;
INST_SLTU <= 1'b0;
INST_XOR <= 1'b0;
INST_SRL <= 1'b0;
INST_SRA <= 1'b0;
INST_OR <= 1'b0;
INST_AND <= 1'b0;
INST_FENCE <= 1'b0;
INST_FENCEI <= 1'b0;
INST_ECALL <= 1'b0;
INST_EBREAK <= 1'b0;
INST_MRET <= 1'b0;
INST_CSRRW <= 1'b0;
INST_CSRRS <= 1'b0;
INST_CSRRC <= 1'b0;
INST_CSRRWI <= 1'b0;
INST_CSRRSI <= 1'b0;
INST_CSRRCI <= 1'b0;
INST_MUL <= 1'b0;
INST_MULH <= 1'b0;
INST_MULHSU <= 1'b0;
INST_MULHU <= 1'b0;
INST_DIV <= 1'b0;
INST_DIVU <= 1'b0;
INST_REM <= 1'b0;
INST_REMU <= 1'b0;
INST_CUSTOM0 <= 1'b0;
end else begin
INST_LUI <= (INST_CODE[6:0] == 7'b0110111);
INST_AUIPC <= (INST_CODE[6:0] == 7'b0010111);
INST_JAL <= (INST_CODE[6:0] == 7'b1101111);
INST_JALR <= (INST_CODE[6:0] == 7'b1100111);
INST_BEQ <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b000);
INST_BNE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b001);
INST_BLT <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b100);
INST_BGE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b101);
INST_BLTU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b110);
INST_BGEU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b111);
INST_LB <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b000);
INST_LH <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b001);
INST_LW <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b010);
INST_LBU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b100);
INST_LHU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b101);
INST_SB <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b000);
INST_SH <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b001);
INST_SW <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b010);
INST_ADDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b000);
INST_SLTI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b010);
INST_SLTIU <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b011);
INST_XORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b100);
INST_ORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b110);
INST_ANDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b111);
INST_SLLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SRLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRAI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_ADD <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000000);
INST_SUB <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0100000);
INST_SLL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SLT <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000000);
INST_SLTU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000000);
INST_XOR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000000);
INST_SRL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRA <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_OR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000000);
INST_AND <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000000);
INST_FENCE <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b000);
INST_FENCEI <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b001);
INST_ECALL <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0000);
INST_EBREAK <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0001);
INST_MRET <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0011_0000_0010);
INST_CSRRW <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b001);
INST_CSRRS <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b010);
INST_CSRRC <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b011);
INST_CSRRWI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b101);
INST_CSRRSI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b110);
INST_CSRRCI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b111);
INST_MUL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000001);
INST_MULH <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000001);
INST_MULHSU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000001);
INST_MULHU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000001);
INST_DIV <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000001);
INST_DIVU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000001);
INST_REM <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000001);
INST_REMU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000001);
INST_CUSTOM0 <= (INST_CODE[6:0] == 7'b0001011);
end
end
assign ILL_INST = ~(
INST_LUI | INST_AUIPC | INST_JAL | INST_JALR |
INST_BEQ | INST_BNE | INST_BLT | INST_BGE |
INST_BLTU | INST_BGEU |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW |
INST_ADDI | INST_SLTI | INST_SLTIU |
INST_XORI | INST_ORI | INST_ANDI |
INST_SLLI | INST_SRLI | INST_SRAI |
INST_ADD | INST_SUB |
INST_SLL | INST_SLT | INST_SLTU |
INST_XOR | INST_SRL | INST_SRA |
INST_OR | INST_AND |
INST_FENCE | INST_FENCEI |
INST_ECALL | INST_EBREAK |
INST_MRET |
INST_CSRRW | INST_CSRRS | INST_CSRRC |
INST_CSRRWI | INST_CSRRSI | INST_CSRRCI |
INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU |
INST_DIV | INST_DIVU | INST_REM | INST_REMU |
INST_CUSTOM0
);
endmodule | module fmrv32im_decode
(
input RST_N,
input CLK,
input wire [31:0] INST_CODE,
output wire [4:0] RD_NUM,
output wire [4:0] RS1_NUM,
output wire [4:0] RS2_NUM,
output reg [31:0] IMM,
output reg INST_LUI,
output reg INST_AUIPC,
output reg INST_JAL,
output reg INST_JALR,
output reg INST_BEQ,
output reg INST_BNE,
output reg INST_BLT,
output reg INST_BGE,
output reg INST_BLTU,
output reg INST_BGEU,
output reg INST_LB,
output reg INST_LH,
output reg INST_LW,
output reg INST_LBU,
output reg INST_LHU,
output reg INST_SB,
output reg INST_SH,
output reg INST_SW,
output reg INST_ADDI,
output reg INST_SLTI,
output reg INST_SLTIU,
output reg INST_XORI,
output reg INST_ORI,
output reg INST_ANDI,
output reg INST_SLLI,
output reg INST_SRLI,
output reg INST_SRAI,
output reg INST_ADD,
output reg INST_SUB,
output reg INST_SLL,
output reg INST_SLT,
output reg INST_SLTU,
output reg INST_XOR,
output reg INST_SRL,
output reg INST_SRA,
output reg INST_OR,
output reg INST_AND,
output reg INST_FENCE,
output reg INST_FENCEI,
output reg INST_ECALL,
output reg INST_EBREAK,
output reg INST_MRET,
output reg INST_CSRRW,
output reg INST_CSRRS,
output reg INST_CSRRC,
output reg INST_CSRRWI,
output reg INST_CSRRSI,
output reg INST_CSRRCI,
output reg INST_MUL,
output reg INST_MULH,
output reg INST_MULHSU,
output reg INST_MULHU,
output reg INST_DIV,
output reg INST_DIVU,
output reg INST_REM,
output reg INST_REMU,
output reg INST_CUSTOM0,
output wire ILL_INST
); |
reg r_type, i_type, s_type, b_type, u_type, j_type;
reg c0_type;
always @(*) begin
r_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b100);
i_type <= ((INST_CODE[6:5] == 2'b00) && ((INST_CODE[4:2] == 3'b000) ||
(INST_CODE[4:2] == 3'b011) ||
(INST_CODE[4:2] == 3'b100))) ||
((INST_CODE[6:5] == 2'b11) && ((INST_CODE[4:2] == 3'b001) ||
(INST_CODE[4:2] == 3'b100)));
s_type <= (INST_CODE[6:5] == 2'b01) && (INST_CODE[4:2] == 3'b000);
b_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b000);
u_type <= ((INST_CODE[6:5] == 2'b00) || (INST_CODE[6:5] == 2'b01)) &&
(INST_CODE[4:2] == 3'b101);
j_type <= (INST_CODE[6:5] == 2'b11) && (INST_CODE[4:2] == 3'b011);
c0_type <= (INST_CODE[6:5] == 2'b00) && (INST_CODE[4:2] == 3'b010);
end
always @(posedge CLK) begin
if(!RST_N) begin
IMM <= 0;
end else begin
IMM <= (i_type)?{{21{INST_CODE[31]}},
INST_CODE[30:20]}:
(s_type)?{{21{INST_CODE[31]}},
INST_CODE[30:25], INST_CODE[11:7]}:
(b_type)?{{20{INST_CODE[31]}},
INST_CODE[7], INST_CODE[30:25], INST_CODE[11:8], 1'b0}:
(u_type)?{INST_CODE[31:12], 12'b0000_0000_0000}:
(j_type)?{{12{INST_CODE[31]}},
INST_CODE[19:12], INST_CODE[20], INST_CODE[30:21], 1'b0}:
32'd0;
end
end
assign RD_NUM = (r_type | i_type | u_type | j_type | c0_type)?INST_CODE[11:7]:5'd0;
assign RS1_NUM = (r_type | i_type | s_type | b_type)?INST_CODE[19:15]:5'd0;
assign RS2_NUM = (r_type | s_type | b_type)?INST_CODE[24:20]:5'd0;
wire [2:0] func3;
wire [6:0] func7;
assign func3 = INST_CODE[14:12];
assign func7 = INST_CODE[31:25];
always @(posedge CLK) begin
if(!RST_N) begin
INST_LUI <= 1'b0;
INST_AUIPC <= 1'b0;
INST_JAL <= 1'b0;
INST_JALR <= 1'b0;
INST_BEQ <= 1'b0;
INST_BNE <= 1'b0;
INST_BLT <= 1'b0;
INST_BGE <= 1'b0;
INST_BLTU <= 1'b0;
INST_BGEU <= 1'b0;
INST_LB <= 1'b0;
INST_LH <= 1'b0;
INST_LW <= 1'b0;
INST_LBU <= 1'b0;
INST_LHU <= 1'b0;
INST_SB <= 1'b0;
INST_SH <= 1'b0;
INST_SW <= 1'b0;
INST_ADDI <= 1'b0;
INST_SLTI <= 1'b0;
INST_SLTIU <= 1'b0;
INST_XORI <= 1'b0;
INST_ORI <= 1'b0;
INST_ANDI <= 1'b0;
INST_SLLI <= 1'b0;
INST_SRLI <= 1'b0;
INST_SRAI <= 1'b0;
INST_ADD <= 1'b0;
INST_SUB <= 1'b0;
INST_SLL <= 1'b0;
INST_SLT <= 1'b0;
INST_SLTU <= 1'b0;
INST_XOR <= 1'b0;
INST_SRL <= 1'b0;
INST_SRA <= 1'b0;
INST_OR <= 1'b0;
INST_AND <= 1'b0;
INST_FENCE <= 1'b0;
INST_FENCEI <= 1'b0;
INST_ECALL <= 1'b0;
INST_EBREAK <= 1'b0;
INST_MRET <= 1'b0;
INST_CSRRW <= 1'b0;
INST_CSRRS <= 1'b0;
INST_CSRRC <= 1'b0;
INST_CSRRWI <= 1'b0;
INST_CSRRSI <= 1'b0;
INST_CSRRCI <= 1'b0;
INST_MUL <= 1'b0;
INST_MULH <= 1'b0;
INST_MULHSU <= 1'b0;
INST_MULHU <= 1'b0;
INST_DIV <= 1'b0;
INST_DIVU <= 1'b0;
INST_REM <= 1'b0;
INST_REMU <= 1'b0;
INST_CUSTOM0 <= 1'b0;
end else begin
INST_LUI <= (INST_CODE[6:0] == 7'b0110111);
INST_AUIPC <= (INST_CODE[6:0] == 7'b0010111);
INST_JAL <= (INST_CODE[6:0] == 7'b1101111);
INST_JALR <= (INST_CODE[6:0] == 7'b1100111);
INST_BEQ <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b000);
INST_BNE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b001);
INST_BLT <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b100);
INST_BGE <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b101);
INST_BLTU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b110);
INST_BGEU <= (INST_CODE[6:0] == 7'b1100011) && (func3 == 3'b111);
INST_LB <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b000);
INST_LH <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b001);
INST_LW <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b010);
INST_LBU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b100);
INST_LHU <= (INST_CODE[6:0] == 7'b0000011) && (func3 == 3'b101);
INST_SB <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b000);
INST_SH <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b001);
INST_SW <= (INST_CODE[6:0] == 7'b0100011) && (func3 == 3'b010);
INST_ADDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b000);
INST_SLTI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b010);
INST_SLTIU <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b011);
INST_XORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b100);
INST_ORI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b110);
INST_ANDI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b111);
INST_SLLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SRLI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRAI <= (INST_CODE[6:0] == 7'b0010011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_ADD <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000000);
INST_SUB <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0100000);
INST_SLL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000000);
INST_SLT <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000000);
INST_SLTU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000000);
INST_XOR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000000);
INST_SRL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000000);
INST_SRA <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0100000);
INST_OR <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000000);
INST_AND <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000000);
INST_FENCE <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b000);
INST_FENCEI <= (INST_CODE[6:0] == 7'b0001111) && (func3 == 3'b001);
INST_ECALL <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0000);
INST_EBREAK <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0000_0000_0001);
INST_MRET <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b000) &&
(INST_CODE[31:20] == 12'b0011_0000_0010);
INST_CSRRW <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b001);
INST_CSRRS <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b010);
INST_CSRRC <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b011);
INST_CSRRWI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b101);
INST_CSRRSI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b110);
INST_CSRRCI <= (INST_CODE[6:0] == 7'b1110011) && (func3 == 3'b111);
INST_MUL <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b000) &&
(func7 == 7'b0000001);
INST_MULH <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b001) &&
(func7 == 7'b0000001);
INST_MULHSU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b010) &&
(func7 == 7'b0000001);
INST_MULHU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b011) &&
(func7 == 7'b0000001);
INST_DIV <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b100) &&
(func7 == 7'b0000001);
INST_DIVU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b101) &&
(func7 == 7'b0000001);
INST_REM <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b110) &&
(func7 == 7'b0000001);
INST_REMU <= (INST_CODE[6:0] == 7'b0110011) && (func3 == 3'b111) &&
(func7 == 7'b0000001);
INST_CUSTOM0 <= (INST_CODE[6:0] == 7'b0001011);
end
end
assign ILL_INST = ~(
INST_LUI | INST_AUIPC | INST_JAL | INST_JALR |
INST_BEQ | INST_BNE | INST_BLT | INST_BGE |
INST_BLTU | INST_BGEU |
INST_LB | INST_LH | INST_LW | INST_LBU | INST_LHU |
INST_SB | INST_SH | INST_SW |
INST_ADDI | INST_SLTI | INST_SLTIU |
INST_XORI | INST_ORI | INST_ANDI |
INST_SLLI | INST_SRLI | INST_SRAI |
INST_ADD | INST_SUB |
INST_SLL | INST_SLT | INST_SLTU |
INST_XOR | INST_SRL | INST_SRA |
INST_OR | INST_AND |
INST_FENCE | INST_FENCEI |
INST_ECALL | INST_EBREAK |
INST_MRET |
INST_CSRRW | INST_CSRRS | INST_CSRRC |
INST_CSRRWI | INST_CSRRSI | INST_CSRRCI |
INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU |
INST_DIV | INST_DIVU | INST_REM | INST_REMU |
INST_CUSTOM0
);
endmodule | 15 |
142,213 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_madd33.v | 98,419,535 | fmrv32im_madd33.v | v | 45 | 50 | [] | [] | [] | [(1, 44)] | null | data/verilator_xmls/b7d44fb2-2052-47cd-ae98-fd0079c538bb.xml | null | 313,359 | module | module fmrv32im_madd33
(
input RST_N,
input CLK,
input INST_MADD33,
input [31:0] RS1,
input [31:0] RS2,
input [31:0] RS3,
input [31:0] RS4,
input [31:0] RS5,
input [31:0] RS6,
output WAIT,
output READY,
output [31:0] RD
);
reg rslt_active;
reg [31:0] rslt;
always @(posedge CLK) begin
if(!RST_N) begin
rslt_active <= 0;
end else begin
rslt_active <= INST_MADD33;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt <= 0;
end else begin
rslt <= ($signed(RS1) * $signed(RS2)) +
($signed(RS3) * $signed(RS4)) +
($signed(RS5) * $signed(RS6));
end
end
assign RD = (rslt_active)?rslt:32'd0;
assign READY = rslt_active;
assign WAIT = 0;
endmodule | module fmrv32im_madd33
(
input RST_N,
input CLK,
input INST_MADD33,
input [31:0] RS1,
input [31:0] RS2,
input [31:0] RS3,
input [31:0] RS4,
input [31:0] RS5,
input [31:0] RS6,
output WAIT,
output READY,
output [31:0] RD
); |
reg rslt_active;
reg [31:0] rslt;
always @(posedge CLK) begin
if(!RST_N) begin
rslt_active <= 0;
end else begin
rslt_active <= INST_MADD33;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt <= 0;
end else begin
rslt <= ($signed(RS1) * $signed(RS2)) +
($signed(RS3) * $signed(RS4)) +
($signed(RS5) * $signed(RS6));
end
end
assign RD = (rslt_active)?rslt:32'd0;
assign READY = rslt_active;
assign WAIT = 0;
endmodule | 15 |
142,214 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v | 98,419,535 | fmrv32im_mul.v | v | 67 | 77 | [] | [] | [] | [(1, 66)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v:33: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n : ... In instance fmrv32im_mul\n w_rs1 <= $signed(RS1);\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v:35: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n : ... In instance fmrv32im_mul\n w_rs1 <= $unsigned(RS1);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v:38: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s SIGNED generates 32 bits.\n : ... In instance fmrv32im_mul\n w_rs2 <= $signed(RS2);\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_mul.v:40: Operator ASSIGNDLY expects 33 bits on the Assign RHS, but Assign RHS\'s UNSIGNED generates 32 bits.\n : ... In instance fmrv32im_mul\n w_rs2 <= $unsigned(RS2);\n ^~\n%Error: Exiting due to 4 warning(s)\n' | 313,360 | module | module fmrv32im_mul
(
input RST_N,
input CLK,
input INST_MUL,
input INST_MULH,
input INST_MULHSU,
input INST_MULHU,
input [31:0] RS1,
input [31:0] RS2,
output WAIT,
output READY,
output [31:0] RD
);
wire inst_mul, inst_mulh;
wire inst_rs1_signed, inst_rs2_signed;
reg [32:0] w_rs1, w_rs2;
reg [63:0] rslt;
reg rslt_high, rslt_active;
assign inst_mul = INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_mulh = INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_rs1_signed = INST_MULH | INST_MULHSU;
assign inst_rs2_signed = INST_MULH;
always @(*) begin
if(inst_rs1_signed) begin
w_rs1 <= $signed(RS1);
end else begin
w_rs1 <= $unsigned(RS1);
end
if(inst_rs2_signed) begin
w_rs2 <= $signed(RS2);
end else begin
w_rs2 <= $unsigned(RS2);
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt_high <= 0;
rslt_active <= 0;
end else begin
rslt_high <= inst_mulh;
rslt_active <= inst_mul;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt <= 0;
end else begin
rslt <= $signed(w_rs1) * $signed(w_rs2);
end
end
assign RD = (rslt_high)?rslt[63:32]:rslt[31:0];
assign READY = rslt_active;
assign WAIT = 0;
endmodule | module fmrv32im_mul
(
input RST_N,
input CLK,
input INST_MUL,
input INST_MULH,
input INST_MULHSU,
input INST_MULHU,
input [31:0] RS1,
input [31:0] RS2,
output WAIT,
output READY,
output [31:0] RD
); |
wire inst_mul, inst_mulh;
wire inst_rs1_signed, inst_rs2_signed;
reg [32:0] w_rs1, w_rs2;
reg [63:0] rslt;
reg rslt_high, rslt_active;
assign inst_mul = INST_MUL | INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_mulh = INST_MULH | INST_MULHSU | INST_MULHU;
assign inst_rs1_signed = INST_MULH | INST_MULHSU;
assign inst_rs2_signed = INST_MULH;
always @(*) begin
if(inst_rs1_signed) begin
w_rs1 <= $signed(RS1);
end else begin
w_rs1 <= $unsigned(RS1);
end
if(inst_rs2_signed) begin
w_rs2 <= $signed(RS2);
end else begin
w_rs2 <= $unsigned(RS2);
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt_high <= 0;
rslt_active <= 0;
end else begin
rslt_high <= inst_mulh;
rslt_active <= inst_mul;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
rslt <= 0;
end else begin
rslt <= $signed(w_rs1) * $signed(w_rs2);
end
end
assign RD = (rslt_high)?rslt[63:32]:rslt[31:0];
assign READY = rslt_active;
assign WAIT = 0;
endmodule | 15 |
142,215 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/5d65/src/fmrv32im_reg.v | 98,419,535 | fmrv32im_reg.v | v | 202 | 63 | [] | [] | [] | [(1, 201)] | null | data/verilator_xmls/fab561db-82c2-44e0-9e0b-aa9ce0d3bc48.xml | null | 313,361 | module | module fmrv32im_reg
(
input RST_N,
input CLK,
input [4:0] WADDR,
input WE,
input [31:0] WDATA,
input [4:0] RS1ADDR,
output reg [31:0] RS1,
input [4:0] RS2ADDR,
output reg [31:0] RS2,
output [31:0] x10,
output [31:0] x11,
output [31:0] x12,
output [31:0] x13,
output [31:0] x14,
output [31:0] x15,
input PC_WE,
input [31:0] PC_WDATA,
output reg [31:0] PC
);
reg [31:0] reg01, reg02, reg03, reg04, reg05, reg06, reg07,
reg08, reg09, reg0A, reg0B, reg0C, reg0D, reg0E, reg0F,
reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,
reg18, reg19, reg1A, reg1B, reg1C, reg1D, reg1E, reg1F;
always @(posedge CLK) begin
if(!RST_N) begin
reg01 <= 0;
reg02 <= 0;
reg03 <= 0;
reg04 <= 0;
reg05 <= 0;
reg06 <= 0;
reg07 <= 0;
reg08 <= 0;
reg09 <= 0;
reg0A <= 0;
reg0B <= 0;
reg0C <= 0;
reg0D <= 0;
reg0E <= 0;
reg0F <= 0;
reg10 <= 0;
reg11 <= 0;
reg12 <= 0;
reg13 <= 0;
reg14 <= 0;
reg15 <= 0;
reg16 <= 0;
reg17 <= 0;
reg18 <= 0;
reg19 <= 0;
reg1A <= 0;
reg1B <= 0;
reg1C <= 0;
reg1D <= 0;
reg1E <= 0;
reg1F <= 0;
end else begin
if(WE && (WADDR == 5'h01)) reg01 <= WDATA;
if(WE && (WADDR == 5'h02)) reg02 <= WDATA;
if(WE && (WADDR == 5'h03)) reg03 <= WDATA;
if(WE && (WADDR == 5'h04)) reg04 <= WDATA;
if(WE && (WADDR == 5'h05)) reg05 <= WDATA;
if(WE && (WADDR == 5'h06)) reg06 <= WDATA;
if(WE && (WADDR == 5'h07)) reg07 <= WDATA;
if(WE && (WADDR == 5'h08)) reg08 <= WDATA;
if(WE && (WADDR == 5'h09)) reg09 <= WDATA;
if(WE && (WADDR == 5'h0A)) reg0A <= WDATA;
if(WE && (WADDR == 5'h0B)) reg0B <= WDATA;
if(WE && (WADDR == 5'h0C)) reg0C <= WDATA;
if(WE && (WADDR == 5'h0D)) reg0D <= WDATA;
if(WE && (WADDR == 5'h0E)) reg0E <= WDATA;
if(WE && (WADDR == 5'h0F)) reg0F <= WDATA;
if(WE && (WADDR == 5'h10)) reg10 <= WDATA;
if(WE && (WADDR == 5'h11)) reg11 <= WDATA;
if(WE && (WADDR == 5'h12)) reg12 <= WDATA;
if(WE && (WADDR == 5'h13)) reg13 <= WDATA;
if(WE && (WADDR == 5'h14)) reg14 <= WDATA;
if(WE && (WADDR == 5'h15)) reg15 <= WDATA;
if(WE && (WADDR == 5'h16)) reg16 <= WDATA;
if(WE && (WADDR == 5'h17)) reg17 <= WDATA;
if(WE && (WADDR == 5'h18)) reg18 <= WDATA;
if(WE && (WADDR == 5'h19)) reg19 <= WDATA;
if(WE && (WADDR == 5'h1A)) reg1A <= WDATA;
if(WE && (WADDR == 5'h1B)) reg1B <= WDATA;
if(WE && (WADDR == 5'h1C)) reg1C <= WDATA;
if(WE && (WADDR == 5'h1D)) reg1D <= WDATA;
if(WE && (WADDR == 5'h1E)) reg1E <= WDATA;
if(WE && (WADDR == 5'h1F)) reg1F <= WDATA;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
RS1 <= 0;
end else begin
case(RS1ADDR)
5'h01: RS1 <= reg01;
5'h02: RS1 <= reg02;
5'h03: RS1 <= reg03;
5'h04: RS1 <= reg04;
5'h05: RS1 <= reg05;
5'h06: RS1 <= reg06;
5'h07: RS1 <= reg07;
5'h08: RS1 <= reg08;
5'h09: RS1 <= reg09;
5'h0A: RS1 <= reg0A;
5'h0B: RS1 <= reg0B;
5'h0C: RS1 <= reg0C;
5'h0D: RS1 <= reg0D;
5'h0E: RS1 <= reg0E;
5'h0F: RS1 <= reg0F;
5'h10: RS1 <= reg10;
5'h11: RS1 <= reg11;
5'h12: RS1 <= reg12;
5'h13: RS1 <= reg13;
5'h14: RS1 <= reg14;
5'h15: RS1 <= reg15;
5'h16: RS1 <= reg16;
5'h17: RS1 <= reg17;
5'h18: RS1 <= reg18;
5'h19: RS1 <= reg19;
5'h1A: RS1 <= reg1A;
5'h1B: RS1 <= reg1B;
5'h1C: RS1 <= reg1C;
5'h1D: RS1 <= reg1D;
5'h1E: RS1 <= reg1E;
5'h1F: RS1 <= reg1F;
default: RS1 <= 32'd0;
endcase
end
end
always @(posedge CLK) begin
if(!RST_N) begin
RS2 <= 0;
end else begin
case(RS2ADDR)
5'h01: RS2 <= reg01;
5'h02: RS2 <= reg02;
5'h03: RS2 <= reg03;
5'h04: RS2 <= reg04;
5'h05: RS2 <= reg05;
5'h06: RS2 <= reg06;
5'h07: RS2 <= reg07;
5'h08: RS2 <= reg08;
5'h09: RS2 <= reg09;
5'h0A: RS2 <= reg0A;
5'h0B: RS2 <= reg0B;
5'h0C: RS2 <= reg0C;
5'h0D: RS2 <= reg0D;
5'h0E: RS2 <= reg0E;
5'h0F: RS2 <= reg0F;
5'h10: RS2 <= reg10;
5'h11: RS2 <= reg11;
5'h12: RS2 <= reg12;
5'h13: RS2 <= reg13;
5'h14: RS2 <= reg14;
5'h15: RS2 <= reg15;
5'h16: RS2 <= reg16;
5'h17: RS2 <= reg17;
5'h18: RS2 <= reg18;
5'h19: RS2 <= reg19;
5'h1A: RS2 <= reg1A;
5'h1B: RS2 <= reg1B;
5'h1C: RS2 <= reg1C;
5'h1D: RS2 <= reg1D;
5'h1E: RS2 <= reg1E;
5'h1F: RS2 <= reg1F;
default: RS2 <= 32'd0;
endcase
end
end
always @(posedge CLK) begin
if(!RST_N) begin
PC <= 0;
end else begin
if(PC_WE) PC <= PC_WDATA;
end
end
assign x10 = reg0A;
assign x11 = reg0B;
assign x12 = reg0C;
assign x13 = reg0D;
assign x14 = reg0E;
assign x15 = reg0F;
endmodule | module fmrv32im_reg
(
input RST_N,
input CLK,
input [4:0] WADDR,
input WE,
input [31:0] WDATA,
input [4:0] RS1ADDR,
output reg [31:0] RS1,
input [4:0] RS2ADDR,
output reg [31:0] RS2,
output [31:0] x10,
output [31:0] x11,
output [31:0] x12,
output [31:0] x13,
output [31:0] x14,
output [31:0] x15,
input PC_WE,
input [31:0] PC_WDATA,
output reg [31:0] PC
); |
reg [31:0] reg01, reg02, reg03, reg04, reg05, reg06, reg07,
reg08, reg09, reg0A, reg0B, reg0C, reg0D, reg0E, reg0F,
reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,
reg18, reg19, reg1A, reg1B, reg1C, reg1D, reg1E, reg1F;
always @(posedge CLK) begin
if(!RST_N) begin
reg01 <= 0;
reg02 <= 0;
reg03 <= 0;
reg04 <= 0;
reg05 <= 0;
reg06 <= 0;
reg07 <= 0;
reg08 <= 0;
reg09 <= 0;
reg0A <= 0;
reg0B <= 0;
reg0C <= 0;
reg0D <= 0;
reg0E <= 0;
reg0F <= 0;
reg10 <= 0;
reg11 <= 0;
reg12 <= 0;
reg13 <= 0;
reg14 <= 0;
reg15 <= 0;
reg16 <= 0;
reg17 <= 0;
reg18 <= 0;
reg19 <= 0;
reg1A <= 0;
reg1B <= 0;
reg1C <= 0;
reg1D <= 0;
reg1E <= 0;
reg1F <= 0;
end else begin
if(WE && (WADDR == 5'h01)) reg01 <= WDATA;
if(WE && (WADDR == 5'h02)) reg02 <= WDATA;
if(WE && (WADDR == 5'h03)) reg03 <= WDATA;
if(WE && (WADDR == 5'h04)) reg04 <= WDATA;
if(WE && (WADDR == 5'h05)) reg05 <= WDATA;
if(WE && (WADDR == 5'h06)) reg06 <= WDATA;
if(WE && (WADDR == 5'h07)) reg07 <= WDATA;
if(WE && (WADDR == 5'h08)) reg08 <= WDATA;
if(WE && (WADDR == 5'h09)) reg09 <= WDATA;
if(WE && (WADDR == 5'h0A)) reg0A <= WDATA;
if(WE && (WADDR == 5'h0B)) reg0B <= WDATA;
if(WE && (WADDR == 5'h0C)) reg0C <= WDATA;
if(WE && (WADDR == 5'h0D)) reg0D <= WDATA;
if(WE && (WADDR == 5'h0E)) reg0E <= WDATA;
if(WE && (WADDR == 5'h0F)) reg0F <= WDATA;
if(WE && (WADDR == 5'h10)) reg10 <= WDATA;
if(WE && (WADDR == 5'h11)) reg11 <= WDATA;
if(WE && (WADDR == 5'h12)) reg12 <= WDATA;
if(WE && (WADDR == 5'h13)) reg13 <= WDATA;
if(WE && (WADDR == 5'h14)) reg14 <= WDATA;
if(WE && (WADDR == 5'h15)) reg15 <= WDATA;
if(WE && (WADDR == 5'h16)) reg16 <= WDATA;
if(WE && (WADDR == 5'h17)) reg17 <= WDATA;
if(WE && (WADDR == 5'h18)) reg18 <= WDATA;
if(WE && (WADDR == 5'h19)) reg19 <= WDATA;
if(WE && (WADDR == 5'h1A)) reg1A <= WDATA;
if(WE && (WADDR == 5'h1B)) reg1B <= WDATA;
if(WE && (WADDR == 5'h1C)) reg1C <= WDATA;
if(WE && (WADDR == 5'h1D)) reg1D <= WDATA;
if(WE && (WADDR == 5'h1E)) reg1E <= WDATA;
if(WE && (WADDR == 5'h1F)) reg1F <= WDATA;
end
end
always @(posedge CLK) begin
if(!RST_N) begin
RS1 <= 0;
end else begin
case(RS1ADDR)
5'h01: RS1 <= reg01;
5'h02: RS1 <= reg02;
5'h03: RS1 <= reg03;
5'h04: RS1 <= reg04;
5'h05: RS1 <= reg05;
5'h06: RS1 <= reg06;
5'h07: RS1 <= reg07;
5'h08: RS1 <= reg08;
5'h09: RS1 <= reg09;
5'h0A: RS1 <= reg0A;
5'h0B: RS1 <= reg0B;
5'h0C: RS1 <= reg0C;
5'h0D: RS1 <= reg0D;
5'h0E: RS1 <= reg0E;
5'h0F: RS1 <= reg0F;
5'h10: RS1 <= reg10;
5'h11: RS1 <= reg11;
5'h12: RS1 <= reg12;
5'h13: RS1 <= reg13;
5'h14: RS1 <= reg14;
5'h15: RS1 <= reg15;
5'h16: RS1 <= reg16;
5'h17: RS1 <= reg17;
5'h18: RS1 <= reg18;
5'h19: RS1 <= reg19;
5'h1A: RS1 <= reg1A;
5'h1B: RS1 <= reg1B;
5'h1C: RS1 <= reg1C;
5'h1D: RS1 <= reg1D;
5'h1E: RS1 <= reg1E;
5'h1F: RS1 <= reg1F;
default: RS1 <= 32'd0;
endcase
end
end
always @(posedge CLK) begin
if(!RST_N) begin
RS2 <= 0;
end else begin
case(RS2ADDR)
5'h01: RS2 <= reg01;
5'h02: RS2 <= reg02;
5'h03: RS2 <= reg03;
5'h04: RS2 <= reg04;
5'h05: RS2 <= reg05;
5'h06: RS2 <= reg06;
5'h07: RS2 <= reg07;
5'h08: RS2 <= reg08;
5'h09: RS2 <= reg09;
5'h0A: RS2 <= reg0A;
5'h0B: RS2 <= reg0B;
5'h0C: RS2 <= reg0C;
5'h0D: RS2 <= reg0D;
5'h0E: RS2 <= reg0E;
5'h0F: RS2 <= reg0F;
5'h10: RS2 <= reg10;
5'h11: RS2 <= reg11;
5'h12: RS2 <= reg12;
5'h13: RS2 <= reg13;
5'h14: RS2 <= reg14;
5'h15: RS2 <= reg15;
5'h16: RS2 <= reg16;
5'h17: RS2 <= reg17;
5'h18: RS2 <= reg18;
5'h19: RS2 <= reg19;
5'h1A: RS2 <= reg1A;
5'h1B: RS2 <= reg1B;
5'h1C: RS2 <= reg1C;
5'h1D: RS2 <= reg1D;
5'h1E: RS2 <= reg1E;
5'h1F: RS2 <= reg1F;
default: RS2 <= 32'd0;
endcase
end
end
always @(posedge CLK) begin
if(!RST_N) begin
PC <= 0;
end else begin
if(PC_WE) PC <= PC_WDATA;
end
end
assign x10 = reg0A;
assign x11 = reg0B;
assign x12 = reg0C;
assign x13 = reg0D;
assign x14 = reg0E;
assign x15 = reg0F;
endmodule | 15 |
142,216 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/cc90/src/fmrv32im_plic.v | 98,419,535 | fmrv32im_plic.v | v | 89 | 84 | [] | [] | [] | [(1, 88)] | null | data/verilator_xmls/ede622f1-dcba-4c40-b032-521a40336511.xml | null | 313,364 | module | module fmrv32im_plic
(
input RST_N,
input CLK,
input BUS_WE,
input [3:0] BUS_ADDR,
input [31:0] BUS_WDATA,
output reg [31:0] BUS_RDATA,
input [31:0] INT_IN,
output wire INT_OUT
);
reg [31:0] int_reg, int_mask;
always @(posedge CLK) begin
if(!RST_N) begin
int_mask <= 0;
end else begin
if(BUS_WE & (BUS_ADDR == 4'h1)) begin
int_mask <= BUS_WDATA;
end
end
end
wire BUS_WE_reg;
assign BUS_WE_reg = BUS_WE & (BUS_ADDR == 4'h0);
always @(posedge CLK) begin
if(!RST_N) begin
int_reg <= 0;
end else begin
int_reg[00] <= INT_IN[00] | (BUS_WE_reg & BUS_WDATA[00])?1'b0:int_reg[00];
int_reg[01] <= INT_IN[01] | (BUS_WE_reg & BUS_WDATA[01])?1'b0:int_reg[01];
int_reg[02] <= INT_IN[02] | (BUS_WE_reg & BUS_WDATA[02])?1'b0:int_reg[02];
int_reg[03] <= INT_IN[03] | (BUS_WE_reg & BUS_WDATA[03])?1'b0:int_reg[03];
int_reg[04] <= INT_IN[04] | (BUS_WE_reg & BUS_WDATA[04])?1'b0:int_reg[04];
int_reg[05] <= INT_IN[05] | (BUS_WE_reg & BUS_WDATA[05])?1'b0:int_reg[05];
int_reg[06] <= INT_IN[06] | (BUS_WE_reg & BUS_WDATA[06])?1'b0:int_reg[06];
int_reg[07] <= INT_IN[07] | (BUS_WE_reg & BUS_WDATA[07])?1'b0:int_reg[07];
int_reg[08] <= INT_IN[08] | (BUS_WE_reg & BUS_WDATA[08])?1'b0:int_reg[08];
int_reg[09] <= INT_IN[09] | (BUS_WE_reg & BUS_WDATA[09])?1'b0:int_reg[09];
int_reg[10] <= INT_IN[10] | (BUS_WE_reg & BUS_WDATA[10])?1'b0:int_reg[10];
int_reg[11] <= INT_IN[11] | (BUS_WE_reg & BUS_WDATA[11])?1'b0:int_reg[11];
int_reg[12] <= INT_IN[12] | (BUS_WE_reg & BUS_WDATA[12])?1'b0:int_reg[12];
int_reg[13] <= INT_IN[13] | (BUS_WE_reg & BUS_WDATA[13])?1'b0:int_reg[13];
int_reg[14] <= INT_IN[14] | (BUS_WE_reg & BUS_WDATA[14])?1'b0:int_reg[14];
int_reg[15] <= INT_IN[15] | (BUS_WE_reg & BUS_WDATA[15])?1'b0:int_reg[15];
int_reg[16] <= INT_IN[16] | (BUS_WE_reg & BUS_WDATA[16])?1'b0:int_reg[16];
int_reg[17] <= INT_IN[17] | (BUS_WE_reg & BUS_WDATA[17])?1'b0:int_reg[17];
int_reg[18] <= INT_IN[18] | (BUS_WE_reg & BUS_WDATA[18])?1'b0:int_reg[18];
int_reg[19] <= INT_IN[19] | (BUS_WE_reg & BUS_WDATA[19])?1'b0:int_reg[19];
int_reg[20] <= INT_IN[20] | (BUS_WE_reg & BUS_WDATA[20])?1'b0:int_reg[20];
int_reg[21] <= INT_IN[21] | (BUS_WE_reg & BUS_WDATA[21])?1'b0:int_reg[21];
int_reg[22] <= INT_IN[22] | (BUS_WE_reg & BUS_WDATA[22])?1'b0:int_reg[22];
int_reg[23] <= INT_IN[23] | (BUS_WE_reg & BUS_WDATA[23])?1'b0:int_reg[23];
int_reg[24] <= INT_IN[24] | (BUS_WE_reg & BUS_WDATA[24])?1'b0:int_reg[24];
int_reg[25] <= INT_IN[25] | (BUS_WE_reg & BUS_WDATA[25])?1'b0:int_reg[25];
int_reg[26] <= INT_IN[26] | (BUS_WE_reg & BUS_WDATA[26])?1'b0:int_reg[26];
int_reg[27] <= INT_IN[27] | (BUS_WE_reg & BUS_WDATA[27])?1'b0:int_reg[27];
int_reg[28] <= INT_IN[28] | (BUS_WE_reg & BUS_WDATA[28])?1'b0:int_reg[28];
int_reg[29] <= INT_IN[29] | (BUS_WE_reg & BUS_WDATA[29])?1'b0:int_reg[29];
int_reg[30] <= INT_IN[30] | (BUS_WE_reg & BUS_WDATA[30])?1'b0:int_reg[30];
int_reg[31] <= INT_IN[31] | (BUS_WE_reg & BUS_WDATA[31])?1'b0:int_reg[31];
end
end
assign INT_OUT = |(int_reg & (~(int_mask)));
always @(*) begin
case(BUS_ADDR)
4'h0:
begin
BUS_RDATA <= int_reg;
end
4'h1:
begin
BUS_RDATA <= int_mask;
end
default:
begin
BUS_RDATA <= 32'd0;
end
endcase
end
endmodule | module fmrv32im_plic
(
input RST_N,
input CLK,
input BUS_WE,
input [3:0] BUS_ADDR,
input [31:0] BUS_WDATA,
output reg [31:0] BUS_RDATA,
input [31:0] INT_IN,
output wire INT_OUT
); |
reg [31:0] int_reg, int_mask;
always @(posedge CLK) begin
if(!RST_N) begin
int_mask <= 0;
end else begin
if(BUS_WE & (BUS_ADDR == 4'h1)) begin
int_mask <= BUS_WDATA;
end
end
end
wire BUS_WE_reg;
assign BUS_WE_reg = BUS_WE & (BUS_ADDR == 4'h0);
always @(posedge CLK) begin
if(!RST_N) begin
int_reg <= 0;
end else begin
int_reg[00] <= INT_IN[00] | (BUS_WE_reg & BUS_WDATA[00])?1'b0:int_reg[00];
int_reg[01] <= INT_IN[01] | (BUS_WE_reg & BUS_WDATA[01])?1'b0:int_reg[01];
int_reg[02] <= INT_IN[02] | (BUS_WE_reg & BUS_WDATA[02])?1'b0:int_reg[02];
int_reg[03] <= INT_IN[03] | (BUS_WE_reg & BUS_WDATA[03])?1'b0:int_reg[03];
int_reg[04] <= INT_IN[04] | (BUS_WE_reg & BUS_WDATA[04])?1'b0:int_reg[04];
int_reg[05] <= INT_IN[05] | (BUS_WE_reg & BUS_WDATA[05])?1'b0:int_reg[05];
int_reg[06] <= INT_IN[06] | (BUS_WE_reg & BUS_WDATA[06])?1'b0:int_reg[06];
int_reg[07] <= INT_IN[07] | (BUS_WE_reg & BUS_WDATA[07])?1'b0:int_reg[07];
int_reg[08] <= INT_IN[08] | (BUS_WE_reg & BUS_WDATA[08])?1'b0:int_reg[08];
int_reg[09] <= INT_IN[09] | (BUS_WE_reg & BUS_WDATA[09])?1'b0:int_reg[09];
int_reg[10] <= INT_IN[10] | (BUS_WE_reg & BUS_WDATA[10])?1'b0:int_reg[10];
int_reg[11] <= INT_IN[11] | (BUS_WE_reg & BUS_WDATA[11])?1'b0:int_reg[11];
int_reg[12] <= INT_IN[12] | (BUS_WE_reg & BUS_WDATA[12])?1'b0:int_reg[12];
int_reg[13] <= INT_IN[13] | (BUS_WE_reg & BUS_WDATA[13])?1'b0:int_reg[13];
int_reg[14] <= INT_IN[14] | (BUS_WE_reg & BUS_WDATA[14])?1'b0:int_reg[14];
int_reg[15] <= INT_IN[15] | (BUS_WE_reg & BUS_WDATA[15])?1'b0:int_reg[15];
int_reg[16] <= INT_IN[16] | (BUS_WE_reg & BUS_WDATA[16])?1'b0:int_reg[16];
int_reg[17] <= INT_IN[17] | (BUS_WE_reg & BUS_WDATA[17])?1'b0:int_reg[17];
int_reg[18] <= INT_IN[18] | (BUS_WE_reg & BUS_WDATA[18])?1'b0:int_reg[18];
int_reg[19] <= INT_IN[19] | (BUS_WE_reg & BUS_WDATA[19])?1'b0:int_reg[19];
int_reg[20] <= INT_IN[20] | (BUS_WE_reg & BUS_WDATA[20])?1'b0:int_reg[20];
int_reg[21] <= INT_IN[21] | (BUS_WE_reg & BUS_WDATA[21])?1'b0:int_reg[21];
int_reg[22] <= INT_IN[22] | (BUS_WE_reg & BUS_WDATA[22])?1'b0:int_reg[22];
int_reg[23] <= INT_IN[23] | (BUS_WE_reg & BUS_WDATA[23])?1'b0:int_reg[23];
int_reg[24] <= INT_IN[24] | (BUS_WE_reg & BUS_WDATA[24])?1'b0:int_reg[24];
int_reg[25] <= INT_IN[25] | (BUS_WE_reg & BUS_WDATA[25])?1'b0:int_reg[25];
int_reg[26] <= INT_IN[26] | (BUS_WE_reg & BUS_WDATA[26])?1'b0:int_reg[26];
int_reg[27] <= INT_IN[27] | (BUS_WE_reg & BUS_WDATA[27])?1'b0:int_reg[27];
int_reg[28] <= INT_IN[28] | (BUS_WE_reg & BUS_WDATA[28])?1'b0:int_reg[28];
int_reg[29] <= INT_IN[29] | (BUS_WE_reg & BUS_WDATA[29])?1'b0:int_reg[29];
int_reg[30] <= INT_IN[30] | (BUS_WE_reg & BUS_WDATA[30])?1'b0:int_reg[30];
int_reg[31] <= INT_IN[31] | (BUS_WE_reg & BUS_WDATA[31])?1'b0:int_reg[31];
end
end
assign INT_OUT = |(int_reg & (~(int_mask)));
always @(*) begin
case(BUS_ADDR)
4'h0:
begin
BUS_RDATA <= int_reg;
end
4'h1:
begin
BUS_RDATA <= int_mask;
end
default:
begin
BUS_RDATA <= 32'd0;
end
endcase
end
endmodule | 15 |
142,217 | data/full_repos/permissive/98419535/fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/e954/src/fmrv32im_dbussel.v | 98,419,535 | fmrv32im_dbussel.v | v | 90 | 113 | [] | [] | [] | [(1, 89)] | null | data/verilator_xmls/96f2b1f0-b630-414d-b6ac-fb2f618a3d98.xml | null | 313,365 | module | module fmrv32im_BADMEM_sel
(
output D_MEM_WAIT,
input D_MEM_ENA,
input [3:0] D_MEM_WSTB,
input [31:0] D_MEM_ADDR,
input [31:0] D_MEM_WDATA,
output [31:0] D_MEM_RDATA,
output D_MEM_BADMEM_EXCPT,
input C_MEM_WAIT,
output C_MEM_ENA,
output [3:0] C_MEM_WSTB,
output [31:0] C_MEM_ADDR,
output [31:0] C_MEM_WDATA,
input [31:0] C_MEM_RDATA,
input C_MEM_BADMEM_EXCPT,
input PERIPHERAL_BUS_WAIT,
output PERIPHERAL_BUS_ENA,
output [3:0] PERIPHERAL_BUS_WSTB,
output [31:0] PERIPHERAL_BUS_ADDR,
output [31:0] PERIPHERAL_BUS_WDATA,
input [31:0] PERIPHERAL_BUS_RDATA,
output PLIC_BUS_WE,
output [3:0] PLIC_BUS_ADDR,
output [31:0] PLIC_BUS_WDATA,
input [31:0] PLIC_BUS_RDATA,
output TIMER_BUS_WE,
output [3:0] TIMER_BUS_ADDR,
output [31:0] TIMER_BUS_WDATA,
input [31:0] TIMER_BUS_RDATA
);
wire dsel_ram, dsel_io, dsel_sys;
wire dsel_sys_plic, dsel_sys_timer;
wire dsel_illegal;
assign dsel_ram = (D_MEM_ADDR[31:30] == 2'b00);
assign dsel_io = (D_MEM_ADDR[31:30] == 2'b10);
assign dsel_sys = (D_MEM_ADDR[31:30] == 2'b11);
assign dsel_sys_plic = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0000));
assign dsel_sys_timer = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0001));
assign dsel_illegal = D_MEM_ENA & ~(dsel_ram | dsel_io | dsel_sys |
dsel_sys_plic | dsel_sys_timer);
assign C_MEM_ENA = (D_MEM_ENA & dsel_ram)?D_MEM_ENA:1'b0;
assign C_MEM_WSTB = (D_MEM_ENA & dsel_ram)?D_MEM_WSTB:4'd0;
assign C_MEM_ADDR = (D_MEM_ENA & dsel_ram)?D_MEM_ADDR:32'd0;
assign C_MEM_WDATA = (D_MEM_ENA & dsel_ram)?D_MEM_WDATA:32'd0;
assign PERIPHERAL_BUS_ENA = (D_MEM_ENA & dsel_io)?D_MEM_ENA:1'b0;
assign PERIPHERAL_BUS_ADDR = (D_MEM_ENA & dsel_io)?D_MEM_ADDR:32'd0;
assign PERIPHERAL_BUS_WSTB = (D_MEM_ENA & dsel_io)?D_MEM_WSTB:4'd0;
assign PERIPHERAL_BUS_WDATA = (D_MEM_ENA & dsel_io)?D_MEM_WDATA:32'd0;
assign PLIC_BUS_WE = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign PLIC_BUS_ADDR = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ADDR[5:2]:4'd0;
assign PLIC_BUS_WDATA = (D_MEM_ENA & dsel_sys_plic)?D_MEM_WDATA:32'd0;
assign TIMER_BUS_WE = (D_MEM_ENA & dsel_sys_timer)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign TIMER_BUS_ADDR = (D_MEM_ENA & C_MEM_ENA & dsel_sys_timer)?D_MEM_ADDR[5:2]:4'd0;
assign TIMER_BUS_WDATA = (dsel_sys_timer)?D_MEM_WDATA:32'd0;
assign D_MEM_WAIT = (D_MEM_ENA & dsel_ram)?C_MEM_WAIT:
(D_MEM_ENA & dsel_io)?PERIPHERAL_BUS_WAIT:
1'b0;
assign D_MEM_RDATA = (dsel_ram)?C_MEM_RDATA:
(dsel_io)?PERIPHERAL_BUS_RDATA:
(dsel_sys_plic)?PLIC_BUS_RDATA:
(dsel_sys_timer)?TIMER_BUS_RDATA:
32'd0;
assign D_MEM_BADMEM_EXCPT = ((~C_MEM_WAIT & ~PERIPHERAL_BUS_WAIT) & D_MEM_ENA & dsel_ram)?C_MEM_BADMEM_EXCPT:
dsel_illegal;
endmodule | module fmrv32im_BADMEM_sel
(
output D_MEM_WAIT,
input D_MEM_ENA,
input [3:0] D_MEM_WSTB,
input [31:0] D_MEM_ADDR,
input [31:0] D_MEM_WDATA,
output [31:0] D_MEM_RDATA,
output D_MEM_BADMEM_EXCPT,
input C_MEM_WAIT,
output C_MEM_ENA,
output [3:0] C_MEM_WSTB,
output [31:0] C_MEM_ADDR,
output [31:0] C_MEM_WDATA,
input [31:0] C_MEM_RDATA,
input C_MEM_BADMEM_EXCPT,
input PERIPHERAL_BUS_WAIT,
output PERIPHERAL_BUS_ENA,
output [3:0] PERIPHERAL_BUS_WSTB,
output [31:0] PERIPHERAL_BUS_ADDR,
output [31:0] PERIPHERAL_BUS_WDATA,
input [31:0] PERIPHERAL_BUS_RDATA,
output PLIC_BUS_WE,
output [3:0] PLIC_BUS_ADDR,
output [31:0] PLIC_BUS_WDATA,
input [31:0] PLIC_BUS_RDATA,
output TIMER_BUS_WE,
output [3:0] TIMER_BUS_ADDR,
output [31:0] TIMER_BUS_WDATA,
input [31:0] TIMER_BUS_RDATA
); |
wire dsel_ram, dsel_io, dsel_sys;
wire dsel_sys_plic, dsel_sys_timer;
wire dsel_illegal;
assign dsel_ram = (D_MEM_ADDR[31:30] == 2'b00);
assign dsel_io = (D_MEM_ADDR[31:30] == 2'b10);
assign dsel_sys = (D_MEM_ADDR[31:30] == 2'b11);
assign dsel_sys_plic = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0000));
assign dsel_sys_timer = (dsel_sys & (D_MEM_ADDR[29:16] == 14'h0001));
assign dsel_illegal = D_MEM_ENA & ~(dsel_ram | dsel_io | dsel_sys |
dsel_sys_plic | dsel_sys_timer);
assign C_MEM_ENA = (D_MEM_ENA & dsel_ram)?D_MEM_ENA:1'b0;
assign C_MEM_WSTB = (D_MEM_ENA & dsel_ram)?D_MEM_WSTB:4'd0;
assign C_MEM_ADDR = (D_MEM_ENA & dsel_ram)?D_MEM_ADDR:32'd0;
assign C_MEM_WDATA = (D_MEM_ENA & dsel_ram)?D_MEM_WDATA:32'd0;
assign PERIPHERAL_BUS_ENA = (D_MEM_ENA & dsel_io)?D_MEM_ENA:1'b0;
assign PERIPHERAL_BUS_ADDR = (D_MEM_ENA & dsel_io)?D_MEM_ADDR:32'd0;
assign PERIPHERAL_BUS_WSTB = (D_MEM_ENA & dsel_io)?D_MEM_WSTB:4'd0;
assign PERIPHERAL_BUS_WDATA = (D_MEM_ENA & dsel_io)?D_MEM_WDATA:32'd0;
assign PLIC_BUS_WE = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign PLIC_BUS_ADDR = (D_MEM_ENA & dsel_sys_plic)?D_MEM_ADDR[5:2]:4'd0;
assign PLIC_BUS_WDATA = (D_MEM_ENA & dsel_sys_plic)?D_MEM_WDATA:32'd0;
assign TIMER_BUS_WE = (D_MEM_ENA & dsel_sys_timer)?D_MEM_ENA & |D_MEM_WSTB:1'b0;
assign TIMER_BUS_ADDR = (D_MEM_ENA & C_MEM_ENA & dsel_sys_timer)?D_MEM_ADDR[5:2]:4'd0;
assign TIMER_BUS_WDATA = (dsel_sys_timer)?D_MEM_WDATA:32'd0;
assign D_MEM_WAIT = (D_MEM_ENA & dsel_ram)?C_MEM_WAIT:
(D_MEM_ENA & dsel_io)?PERIPHERAL_BUS_WAIT:
1'b0;
assign D_MEM_RDATA = (dsel_ram)?C_MEM_RDATA:
(dsel_io)?PERIPHERAL_BUS_RDATA:
(dsel_sys_plic)?PLIC_BUS_RDATA:
(dsel_sys_timer)?TIMER_BUS_RDATA:
32'd0;
assign D_MEM_BADMEM_EXCPT = ((~C_MEM_WAIT & ~PERIPHERAL_BUS_WAIT) & D_MEM_ENA & dsel_ram)?C_MEM_BADMEM_EXCPT:
dsel_illegal;
endmodule | 15 |
142,218 | data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v | 98,419,535 | fmrv32im_axim.v | v | 297 | 82 | [] | [] | [] | [(1, 296)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:104: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance fmrv32im_axim\n reg_wmem_addr <= 13\'d0;\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:105: Operator ASSIGNDLY expects 32 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance fmrv32im_axim\n reg_w_data <= 1\'b0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:120: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance fmrv32im_axim\n reg_wmem_addr <= 13\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:182: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS\'s CONST \'2\'h2\' generates 2 bits.\n : ... In instance fmrv32im_axim\n assign M_AXI_AWSIZE[2:0] = 2\'b010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:201: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_wmem_addr\' generates 14 bits.\n : ... In instance fmrv32im_axim\n assign WR_REQ_MEM_ADDR = reg_wmem_addr;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:226: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance fmrv32im_axim\n reg_rmem_addr <= 13\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:237: Operator ASSIGNDLY expects 14 bits on the Assign RHS, but Assign RHS\'s CONST \'13\'h0\' generates 13 bits.\n : ... In instance fmrv32im_axim\n reg_rmem_addr <= 13\'d0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:243: Operator NEQ expects 16 bits on the LHS, but LHS\'s SEL generates 6 bits.\n : ... In instance fmrv32im_axim\n if(reg_RD_REQ_len[15:10] != 16\'d0) begin\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:282: Operator ASSIGNW expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'1\'h0\' generates 1 bits.\n : ... In instance fmrv32im_axim\n assign M_AXI_ARLOCK = 1\'b0;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98419535/modules/axim_v1/src/fmrv32im_axim.v:293: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_rmem_addr\' generates 14 bits.\n : ... In instance fmrv32im_axim\n assign RD_REQ_MEM_ADDR = reg_rmem_addr;\n ^\n%Error: Exiting due to 10 warning(s)\n' | 313,411 | module | module fmrv32im_axim
(
input RST_N,
input CLK,
output [0:0] M_AXI_AWID,
output [31:0] M_AXI_AWADDR,
output [7:0] M_AXI_AWLEN,
output [2:0] M_AXI_AWSIZE,
output [1:0] M_AXI_AWBURST,
output M_AXI_AWLOCK,
output [3:0] M_AXI_AWCACHE,
output [2:0] M_AXI_AWPROT,
output [3:0] M_AXI_AWQOS,
output [0:0] M_AXI_AWUSER,
output M_AXI_AWVALID,
input M_AXI_AWREADY,
output [31:0] M_AXI_WDATA,
output [3:0] M_AXI_WSTRB,
output M_AXI_WLAST,
output [0:0] M_AXI_WUSER,
output M_AXI_WVALID,
input M_AXI_WREADY,
input [0:0] M_AXI_BID,
input [1:0] M_AXI_BRESP,
input [0:0] M_AXI_BUSER,
input M_AXI_BVALID,
output M_AXI_BREADY,
output [0:0] M_AXI_ARID,
output [31:0] M_AXI_ARADDR,
output [7:0] M_AXI_ARLEN,
output [2:0] M_AXI_ARSIZE,
output [1:0] M_AXI_ARBURST,
output [1:0] M_AXI_ARLOCK,
output [3:0] M_AXI_ARCACHE,
output [2:0] M_AXI_ARPROT,
output [3:0] M_AXI_ARQOS,
output [0:0] M_AXI_ARUSER,
output M_AXI_ARVALID,
input M_AXI_ARREADY,
input [0:0] M_AXI_RID,
input [31:0] M_AXI_RDATA,
input [1:0] M_AXI_RRESP,
input M_AXI_RLAST,
input [0:0] M_AXI_RUSER,
input M_AXI_RVALID,
output M_AXI_RREADY,
input WR_REQ_START,
input [31:0] WR_REQ_ADDR,
input [15:0] WR_REQ_LEN,
output WR_REQ_READY,
output [9:0] WR_REQ_MEM_ADDR,
input [31:0] WR_REQ_MEM_WDATA,
input RD_REQ_START,
input [31:0] RD_REQ_ADDR,
input [15:0] RD_REQ_LEN,
output RD_REQ_READY,
output RD_REQ_MEM_WE,
output [9:0] RD_REQ_MEM_ADDR,
output [31:0] RD_REQ_MEM_RDATA
);
localparam S_WR_REQ_IDLE = 3'd0;
localparam S_WA_WAIT = 3'd1;
localparam S_WA_START = 3'd2;
localparam S_WD_WAIT = 3'd3;
localparam S_WD_PROC = 3'd4;
localparam S_WR_REQ_WAIT = 3'd5;
reg [2:0] WR_REQ_state;
reg [31:0] reg_WR_REQ_adrs;
reg [15:0] reg_WR_REQ_len;
reg reg_awvalid, reg_wvalid, reg_w_last;
reg [7:0] reg_w_len;
reg [3:0] reg_w_stb;
reg reg_w_delay;
reg [31:0] reg_w_data;
reg [13:0] reg_wmem_addr;
always @(posedge CLK) begin
if(!RST_N) begin
WR_REQ_state <= S_WR_REQ_IDLE;
reg_WR_REQ_adrs[31:0] <= 32'd0;
reg_WR_REQ_len[15:0] <= 16'd0;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
reg_w_stb[3:0] <= 4'd0;
reg_wmem_addr <= 13'd0;
reg_w_data <= 1'b0;
reg_w_delay <= 1'b0;
end else begin
case(WR_REQ_state)
S_WR_REQ_IDLE: begin
if(WR_REQ_START) begin
WR_REQ_state <= S_WA_START;
reg_WR_REQ_adrs[31:0] <= WR_REQ_ADDR[31:0];
reg_WR_REQ_len[15:0] <= WR_REQ_LEN[15:0] -16'd1;
end
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
reg_w_stb[3:0] <= 4'd0;
reg_wmem_addr <= 13'd0;
end
S_WA_START: begin
WR_REQ_state <= S_WD_WAIT;
reg_awvalid <= 1'b1;
reg_WR_REQ_len[15:10] <= reg_WR_REQ_len[15:10] - 6'd1;
if(reg_WR_REQ_len[15:10] != 6'd0) begin
reg_w_len[7:0] <= 8'hFF;
reg_w_last <= 1'b0;
reg_w_stb[3:0] <= 4'hF;
end else begin
reg_w_len[7:0] <= reg_WR_REQ_len[9:2];
reg_w_last <= 1'b1;
reg_w_stb[3:0] <= 4'hF;
end
end
S_WD_WAIT: begin
if(M_AXI_AWREADY) begin
WR_REQ_state <= S_WD_PROC;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b1;
reg_wmem_addr <= reg_wmem_addr +13'd1;
end
end
S_WD_PROC: begin
if(M_AXI_WREADY) begin
if(reg_w_len[7:0] == 8'd0) begin
WR_REQ_state <= S_WR_REQ_WAIT;
reg_wvalid <= 1'b0;
reg_w_stb[3:0] <= 4'h0;
end else begin
reg_w_len[7:0] <= reg_w_len[7:0] -8'd1;
reg_wmem_addr <= reg_wmem_addr +13'd1;
end
end
end
S_WR_REQ_WAIT: begin
if(M_AXI_BVALID) begin
if(reg_w_last) begin
WR_REQ_state <= S_WR_REQ_IDLE;
end else begin
WR_REQ_state <= S_WA_START;
reg_WR_REQ_adrs[31:0] <= reg_WR_REQ_adrs[31:0] + 32'd1024;
end
end
end
default: begin
WR_REQ_state <= S_WR_REQ_IDLE;
end
endcase
end
reg_w_delay <= M_AXI_WREADY;
if((WR_REQ_state == S_WA_START) |
((WR_REQ_state == S_WD_PROC) & reg_w_delay)) begin
reg_w_data <= WR_REQ_MEM_WDATA;
end
end
assign M_AXI_AWID = 1'b0;
assign M_AXI_AWADDR[31:0] = reg_WR_REQ_adrs[31:0];
assign M_AXI_AWLEN[7:0] = reg_w_len[7:0];
assign M_AXI_AWSIZE[2:0] = 2'b010;
assign M_AXI_AWBURST[1:0] = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
assign M_AXI_AWCACHE[3:0] = 4'b0011;
assign M_AXI_AWPROT[2:0] = 3'b000;
assign M_AXI_AWQOS[3:0] = 4'b0000;
assign M_AXI_AWUSER[0] = 1'b1;
assign M_AXI_AWVALID = reg_awvalid;
assign M_AXI_WDATA[31:0] = (reg_w_delay)?WR_REQ_MEM_WDATA:reg_w_data;
assign M_AXI_WSTRB[3:0] = (reg_wvalid)?reg_w_stb:4'h0;
assign M_AXI_WLAST = (reg_w_len[7:0] == 8'd0)?1'b1:1'b0;
assign M_AXI_WUSER = 1;
assign M_AXI_WVALID = reg_wvalid;
assign M_AXI_BREADY = (WR_REQ_state == S_WR_REQ_WAIT)?1'b1:1'b0;
assign WR_REQ_READY = (WR_REQ_state == S_WR_REQ_IDLE)?1'b1:1'b0;
assign WR_REQ_MEM_ADDR = reg_wmem_addr;
localparam S_RD_REQ_IDLE = 3'd0;
localparam S_RS_REQUEST = 3'd1;
localparam S_RA_WAIT = 3'd2;
localparam S_RA_START = 3'd3;
localparam S_RD_REQ_WAIT = 3'd4;
localparam S_RD_REQ_PROC = 3'd5;
reg [2:0] RD_REQ_state;
reg [31:0] reg_RD_REQ_adrs;
reg [15:0] reg_RD_REQ_len;
reg reg_arvalid, reg_r_last;
reg [7:0] reg_r_len;
reg [13:0] reg_rmem_addr;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
RD_REQ_state <= S_RD_REQ_IDLE;
reg_RD_REQ_adrs[31:0] <= 32'd0;
reg_RD_REQ_len[15:0] <= 16'd0;
reg_arvalid <= 1'b0;
reg_r_len[7:0] <= 8'd0;
reg_r_last <= 1'b0;
reg_rmem_addr <= 13'd0;
end else begin
case(RD_REQ_state)
S_RD_REQ_IDLE: begin
if(RD_REQ_START) begin
RD_REQ_state <= S_RA_START;
reg_RD_REQ_adrs[31:0] <= RD_REQ_ADDR[31:0];
reg_RD_REQ_len[15:0] <= RD_REQ_LEN[15:0] -16'd1;
end
reg_arvalid <= 1'b0;
reg_r_len[7:0] <= 8'd0;
reg_rmem_addr <= 13'd0;
end
S_RA_START: begin
RD_REQ_state <= S_RD_REQ_WAIT;
reg_arvalid <= 1'b1;
reg_RD_REQ_len[15:10] <= reg_RD_REQ_len[15:10] -6'd1;
if(reg_RD_REQ_len[15:10] != 16'd0) begin
reg_r_last <= 1'b0;
reg_r_len[7:0] <= 8'd255;
end else begin
reg_r_last <= 1'b1;
reg_r_len[7:0] <= reg_RD_REQ_len[9:2];
end
end
S_RD_REQ_WAIT: begin
if(M_AXI_ARREADY) begin
RD_REQ_state <= S_RD_REQ_PROC;
reg_arvalid <= 1'b0;
end
end
S_RD_REQ_PROC: begin
if(M_AXI_RVALID) begin
reg_rmem_addr <= reg_rmem_addr +1;
if(M_AXI_RLAST) begin
if(reg_r_last) begin
RD_REQ_state <= S_RD_REQ_IDLE;
end else begin
RD_REQ_state <= S_RA_START;
reg_RD_REQ_adrs[31:0] <= reg_RD_REQ_adrs[31:0] + 32'd1024;
end
end else begin
reg_r_len[7:0] <= reg_r_len[7:0] -8'd1;
end
end
end
endcase
end
end
assign M_AXI_ARID = 1'b0;
assign M_AXI_ARADDR[31:0] = reg_RD_REQ_adrs[31:0];
assign M_AXI_ARLEN[7:0] = reg_r_len[7:0];
assign M_AXI_ARSIZE[2:0] = 3'b010;
assign M_AXI_ARBURST[1:0] = 2'b01;
assign M_AXI_ARLOCK = 1'b0;
assign M_AXI_ARCACHE[3:0] = 4'b0011;
assign M_AXI_ARPROT[2:0] = 3'b000;
assign M_AXI_ARQOS[3:0] = 4'b0000;
assign M_AXI_ARUSER[0] = 1'b1;
assign M_AXI_ARVALID = reg_arvalid;
assign M_AXI_RREADY = 1'b1;
assign RD_REQ_READY = (RD_REQ_state == S_RD_REQ_IDLE)?1'b1:1'b0;
assign RD_REQ_MEM_WE = M_AXI_RVALID;
assign RD_REQ_MEM_ADDR = reg_rmem_addr;
assign RD_REQ_MEM_RDATA = M_AXI_RDATA[31:0];
endmodule | module fmrv32im_axim
(
input RST_N,
input CLK,
output [0:0] M_AXI_AWID,
output [31:0] M_AXI_AWADDR,
output [7:0] M_AXI_AWLEN,
output [2:0] M_AXI_AWSIZE,
output [1:0] M_AXI_AWBURST,
output M_AXI_AWLOCK,
output [3:0] M_AXI_AWCACHE,
output [2:0] M_AXI_AWPROT,
output [3:0] M_AXI_AWQOS,
output [0:0] M_AXI_AWUSER,
output M_AXI_AWVALID,
input M_AXI_AWREADY,
output [31:0] M_AXI_WDATA,
output [3:0] M_AXI_WSTRB,
output M_AXI_WLAST,
output [0:0] M_AXI_WUSER,
output M_AXI_WVALID,
input M_AXI_WREADY,
input [0:0] M_AXI_BID,
input [1:0] M_AXI_BRESP,
input [0:0] M_AXI_BUSER,
input M_AXI_BVALID,
output M_AXI_BREADY,
output [0:0] M_AXI_ARID,
output [31:0] M_AXI_ARADDR,
output [7:0] M_AXI_ARLEN,
output [2:0] M_AXI_ARSIZE,
output [1:0] M_AXI_ARBURST,
output [1:0] M_AXI_ARLOCK,
output [3:0] M_AXI_ARCACHE,
output [2:0] M_AXI_ARPROT,
output [3:0] M_AXI_ARQOS,
output [0:0] M_AXI_ARUSER,
output M_AXI_ARVALID,
input M_AXI_ARREADY,
input [0:0] M_AXI_RID,
input [31:0] M_AXI_RDATA,
input [1:0] M_AXI_RRESP,
input M_AXI_RLAST,
input [0:0] M_AXI_RUSER,
input M_AXI_RVALID,
output M_AXI_RREADY,
input WR_REQ_START,
input [31:0] WR_REQ_ADDR,
input [15:0] WR_REQ_LEN,
output WR_REQ_READY,
output [9:0] WR_REQ_MEM_ADDR,
input [31:0] WR_REQ_MEM_WDATA,
input RD_REQ_START,
input [31:0] RD_REQ_ADDR,
input [15:0] RD_REQ_LEN,
output RD_REQ_READY,
output RD_REQ_MEM_WE,
output [9:0] RD_REQ_MEM_ADDR,
output [31:0] RD_REQ_MEM_RDATA
); |
localparam S_WR_REQ_IDLE = 3'd0;
localparam S_WA_WAIT = 3'd1;
localparam S_WA_START = 3'd2;
localparam S_WD_WAIT = 3'd3;
localparam S_WD_PROC = 3'd4;
localparam S_WR_REQ_WAIT = 3'd5;
reg [2:0] WR_REQ_state;
reg [31:0] reg_WR_REQ_adrs;
reg [15:0] reg_WR_REQ_len;
reg reg_awvalid, reg_wvalid, reg_w_last;
reg [7:0] reg_w_len;
reg [3:0] reg_w_stb;
reg reg_w_delay;
reg [31:0] reg_w_data;
reg [13:0] reg_wmem_addr;
always @(posedge CLK) begin
if(!RST_N) begin
WR_REQ_state <= S_WR_REQ_IDLE;
reg_WR_REQ_adrs[31:0] <= 32'd0;
reg_WR_REQ_len[15:0] <= 16'd0;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
reg_w_stb[3:0] <= 4'd0;
reg_wmem_addr <= 13'd0;
reg_w_data <= 1'b0;
reg_w_delay <= 1'b0;
end else begin
case(WR_REQ_state)
S_WR_REQ_IDLE: begin
if(WR_REQ_START) begin
WR_REQ_state <= S_WA_START;
reg_WR_REQ_adrs[31:0] <= WR_REQ_ADDR[31:0];
reg_WR_REQ_len[15:0] <= WR_REQ_LEN[15:0] -16'd1;
end
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b0;
reg_w_last <= 1'b0;
reg_w_len[7:0] <= 8'd0;
reg_w_stb[3:0] <= 4'd0;
reg_wmem_addr <= 13'd0;
end
S_WA_START: begin
WR_REQ_state <= S_WD_WAIT;
reg_awvalid <= 1'b1;
reg_WR_REQ_len[15:10] <= reg_WR_REQ_len[15:10] - 6'd1;
if(reg_WR_REQ_len[15:10] != 6'd0) begin
reg_w_len[7:0] <= 8'hFF;
reg_w_last <= 1'b0;
reg_w_stb[3:0] <= 4'hF;
end else begin
reg_w_len[7:0] <= reg_WR_REQ_len[9:2];
reg_w_last <= 1'b1;
reg_w_stb[3:0] <= 4'hF;
end
end
S_WD_WAIT: begin
if(M_AXI_AWREADY) begin
WR_REQ_state <= S_WD_PROC;
reg_awvalid <= 1'b0;
reg_wvalid <= 1'b1;
reg_wmem_addr <= reg_wmem_addr +13'd1;
end
end
S_WD_PROC: begin
if(M_AXI_WREADY) begin
if(reg_w_len[7:0] == 8'd0) begin
WR_REQ_state <= S_WR_REQ_WAIT;
reg_wvalid <= 1'b0;
reg_w_stb[3:0] <= 4'h0;
end else begin
reg_w_len[7:0] <= reg_w_len[7:0] -8'd1;
reg_wmem_addr <= reg_wmem_addr +13'd1;
end
end
end
S_WR_REQ_WAIT: begin
if(M_AXI_BVALID) begin
if(reg_w_last) begin
WR_REQ_state <= S_WR_REQ_IDLE;
end else begin
WR_REQ_state <= S_WA_START;
reg_WR_REQ_adrs[31:0] <= reg_WR_REQ_adrs[31:0] + 32'd1024;
end
end
end
default: begin
WR_REQ_state <= S_WR_REQ_IDLE;
end
endcase
end
reg_w_delay <= M_AXI_WREADY;
if((WR_REQ_state == S_WA_START) |
((WR_REQ_state == S_WD_PROC) & reg_w_delay)) begin
reg_w_data <= WR_REQ_MEM_WDATA;
end
end
assign M_AXI_AWID = 1'b0;
assign M_AXI_AWADDR[31:0] = reg_WR_REQ_adrs[31:0];
assign M_AXI_AWLEN[7:0] = reg_w_len[7:0];
assign M_AXI_AWSIZE[2:0] = 2'b010;
assign M_AXI_AWBURST[1:0] = 2'b01;
assign M_AXI_AWLOCK = 1'b0;
assign M_AXI_AWCACHE[3:0] = 4'b0011;
assign M_AXI_AWPROT[2:0] = 3'b000;
assign M_AXI_AWQOS[3:0] = 4'b0000;
assign M_AXI_AWUSER[0] = 1'b1;
assign M_AXI_AWVALID = reg_awvalid;
assign M_AXI_WDATA[31:0] = (reg_w_delay)?WR_REQ_MEM_WDATA:reg_w_data;
assign M_AXI_WSTRB[3:0] = (reg_wvalid)?reg_w_stb:4'h0;
assign M_AXI_WLAST = (reg_w_len[7:0] == 8'd0)?1'b1:1'b0;
assign M_AXI_WUSER = 1;
assign M_AXI_WVALID = reg_wvalid;
assign M_AXI_BREADY = (WR_REQ_state == S_WR_REQ_WAIT)?1'b1:1'b0;
assign WR_REQ_READY = (WR_REQ_state == S_WR_REQ_IDLE)?1'b1:1'b0;
assign WR_REQ_MEM_ADDR = reg_wmem_addr;
localparam S_RD_REQ_IDLE = 3'd0;
localparam S_RS_REQUEST = 3'd1;
localparam S_RA_WAIT = 3'd2;
localparam S_RA_START = 3'd3;
localparam S_RD_REQ_WAIT = 3'd4;
localparam S_RD_REQ_PROC = 3'd5;
reg [2:0] RD_REQ_state;
reg [31:0] reg_RD_REQ_adrs;
reg [15:0] reg_RD_REQ_len;
reg reg_arvalid, reg_r_last;
reg [7:0] reg_r_len;
reg [13:0] reg_rmem_addr;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
RD_REQ_state <= S_RD_REQ_IDLE;
reg_RD_REQ_adrs[31:0] <= 32'd0;
reg_RD_REQ_len[15:0] <= 16'd0;
reg_arvalid <= 1'b0;
reg_r_len[7:0] <= 8'd0;
reg_r_last <= 1'b0;
reg_rmem_addr <= 13'd0;
end else begin
case(RD_REQ_state)
S_RD_REQ_IDLE: begin
if(RD_REQ_START) begin
RD_REQ_state <= S_RA_START;
reg_RD_REQ_adrs[31:0] <= RD_REQ_ADDR[31:0];
reg_RD_REQ_len[15:0] <= RD_REQ_LEN[15:0] -16'd1;
end
reg_arvalid <= 1'b0;
reg_r_len[7:0] <= 8'd0;
reg_rmem_addr <= 13'd0;
end
S_RA_START: begin
RD_REQ_state <= S_RD_REQ_WAIT;
reg_arvalid <= 1'b1;
reg_RD_REQ_len[15:10] <= reg_RD_REQ_len[15:10] -6'd1;
if(reg_RD_REQ_len[15:10] != 16'd0) begin
reg_r_last <= 1'b0;
reg_r_len[7:0] <= 8'd255;
end else begin
reg_r_last <= 1'b1;
reg_r_len[7:0] <= reg_RD_REQ_len[9:2];
end
end
S_RD_REQ_WAIT: begin
if(M_AXI_ARREADY) begin
RD_REQ_state <= S_RD_REQ_PROC;
reg_arvalid <= 1'b0;
end
end
S_RD_REQ_PROC: begin
if(M_AXI_RVALID) begin
reg_rmem_addr <= reg_rmem_addr +1;
if(M_AXI_RLAST) begin
if(reg_r_last) begin
RD_REQ_state <= S_RD_REQ_IDLE;
end else begin
RD_REQ_state <= S_RA_START;
reg_RD_REQ_adrs[31:0] <= reg_RD_REQ_adrs[31:0] + 32'd1024;
end
end else begin
reg_r_len[7:0] <= reg_r_len[7:0] -8'd1;
end
end
end
endcase
end
end
assign M_AXI_ARID = 1'b0;
assign M_AXI_ARADDR[31:0] = reg_RD_REQ_adrs[31:0];
assign M_AXI_ARLEN[7:0] = reg_r_len[7:0];
assign M_AXI_ARSIZE[2:0] = 3'b010;
assign M_AXI_ARBURST[1:0] = 2'b01;
assign M_AXI_ARLOCK = 1'b0;
assign M_AXI_ARCACHE[3:0] = 4'b0011;
assign M_AXI_ARPROT[2:0] = 3'b000;
assign M_AXI_ARQOS[3:0] = 4'b0000;
assign M_AXI_ARUSER[0] = 1'b1;
assign M_AXI_ARVALID = reg_arvalid;
assign M_AXI_RREADY = 1'b1;
assign RD_REQ_READY = (RD_REQ_state == S_RD_REQ_IDLE)?1'b1:1'b0;
assign RD_REQ_MEM_WE = M_AXI_RVALID;
assign RD_REQ_MEM_ADDR = reg_rmem_addr;
assign RD_REQ_MEM_RDATA = M_AXI_RDATA[31:0];
endmodule | 15 |
142,220 | data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v | 98,419,535 | fmrv32im_axi_gpio.v | v | 322 | 103 | [] | [] | [] | [(1, 117), (119, 242), (244, 321)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v:225: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_addr\' generates 16 bits.\n : ... In instance fmrv32im_axi_gpio.u_fmrv32im_axi_gpio_ls\n assign LOCAL_ADDR = reg_addr;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,423 | module | module fmrv32im_axi_gpio
(
input RST_N,
input CLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [31:0] GPIO_I,
output [31:0] GPIO_OT
);
wire local_cs;
wire local_rnw;
wire local_ack;
wire [31:0] local_addr;
wire [3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
fmrv32im_axi_gpio_ls u_fmrv32im_axi_gpio_ls
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.LOCAL_CS ( local_cs),
.LOCAL_RNW ( local_rnw),
.LOCAL_ACK ( local_ack),
.LOCAL_ADDR ( local_addr),
.LOCAL_BE ( local_be),
.LOCAL_WDATA ( local_wdata),
.LOCAL_RDATA ( local_rdata)
);
fmrv32im_axi_gpio_ctrl u_fmrv32im_axi_gpio_ctrl
(
.RST_N ( RST_N),
.CLK ( CLK),
.LOCAL_CS ( local_cs),
.LOCAL_RNW ( local_rnw),
.LOCAL_ACK ( local_ack),
.LOCAL_ADDR ( local_addr),
.LOCAL_BE ( local_be),
.LOCAL_WDATA ( local_wdata),
.LOCAL_RDATA ( local_rdata),
.GPIO_I ( GPIO_I),
.GPIO_OT ( GPIO_OT)
);
endmodule | module fmrv32im_axi_gpio
(
input RST_N,
input CLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [31:0] GPIO_I,
output [31:0] GPIO_OT
); |
wire local_cs;
wire local_rnw;
wire local_ack;
wire [31:0] local_addr;
wire [3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
fmrv32im_axi_gpio_ls u_fmrv32im_axi_gpio_ls
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.LOCAL_CS ( local_cs),
.LOCAL_RNW ( local_rnw),
.LOCAL_ACK ( local_ack),
.LOCAL_ADDR ( local_addr),
.LOCAL_BE ( local_be),
.LOCAL_WDATA ( local_wdata),
.LOCAL_RDATA ( local_rdata)
);
fmrv32im_axi_gpio_ctrl u_fmrv32im_axi_gpio_ctrl
(
.RST_N ( RST_N),
.CLK ( CLK),
.LOCAL_CS ( local_cs),
.LOCAL_RNW ( local_rnw),
.LOCAL_ACK ( local_ack),
.LOCAL_ADDR ( local_addr),
.LOCAL_BE ( local_be),
.LOCAL_WDATA ( local_wdata),
.LOCAL_RDATA ( local_rdata),
.GPIO_I ( GPIO_I),
.GPIO_OT ( GPIO_OT)
);
endmodule | 15 |
142,221 | data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v | 98,419,535 | fmrv32im_axi_gpio.v | v | 322 | 103 | [] | [] | [] | [(1, 117), (119, 242), (244, 321)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v:225: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_addr\' generates 16 bits.\n : ... In instance fmrv32im_axi_gpio.u_fmrv32im_axi_gpio_ls\n assign LOCAL_ADDR = reg_addr;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,423 | module | module fmrv32im_axi_gpio_ls
(
input ARESETN,
input ACLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
);
localparam S_IDLE = 2'd0;
localparam S_WRITE = 2'd1;
localparam S_WRITE2 = 2'd2;
localparam S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [15:0] reg_addr;
reg [31:0] reg_wdata;
reg [3:0] reg_be;
always @( posedge ACLK or negedge ARESETN ) begin
if( !ARESETN ) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_addr <= 16'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case( state )
S_IDLE: begin
if( S_AXI_AWVALID ) begin
reg_rnw <= 1'b0;
reg_addr <= S_AXI_AWADDR;
state <= S_WRITE;
end else if( S_AXI_ARVALID ) begin
reg_rnw <= 1'b1;
reg_addr <= S_AXI_ARADDR;
state <= S_READ;
end
end
S_WRITE: begin
if( S_AXI_WVALID ) begin
state <= S_WRITE2;
reg_wdata <= S_AXI_WDATA;
reg_be <= S_AXI_WSTRB;
end
end
S_WRITE2: begin
if( LOCAL_ACK & S_AXI_BREADY ) begin
state <= S_IDLE;
end
end
S_READ: begin
if( LOCAL_ACK & S_AXI_RREADY ) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
assign LOCAL_CS = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADDR = reg_addr;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
assign S_AXI_AWREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_WREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_BVALID = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
assign S_AXI_BRESP = 2'b00;
assign S_AXI_ARREADY = ( state == S_READ || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_RVALID = ( state == S_READ )?LOCAL_ACK:1'b0;
assign S_AXI_RRESP = 2'b00;
assign S_AXI_RDATA = ( state == S_READ )?LOCAL_RDATA:32'd0;
endmodule | module fmrv32im_axi_gpio_ls
(
input ARESETN,
input ACLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
); |
localparam S_IDLE = 2'd0;
localparam S_WRITE = 2'd1;
localparam S_WRITE2 = 2'd2;
localparam S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [15:0] reg_addr;
reg [31:0] reg_wdata;
reg [3:0] reg_be;
always @( posedge ACLK or negedge ARESETN ) begin
if( !ARESETN ) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_addr <= 16'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case( state )
S_IDLE: begin
if( S_AXI_AWVALID ) begin
reg_rnw <= 1'b0;
reg_addr <= S_AXI_AWADDR;
state <= S_WRITE;
end else if( S_AXI_ARVALID ) begin
reg_rnw <= 1'b1;
reg_addr <= S_AXI_ARADDR;
state <= S_READ;
end
end
S_WRITE: begin
if( S_AXI_WVALID ) begin
state <= S_WRITE2;
reg_wdata <= S_AXI_WDATA;
reg_be <= S_AXI_WSTRB;
end
end
S_WRITE2: begin
if( LOCAL_ACK & S_AXI_BREADY ) begin
state <= S_IDLE;
end
end
S_READ: begin
if( LOCAL_ACK & S_AXI_RREADY ) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
assign LOCAL_CS = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADDR = reg_addr;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
assign S_AXI_AWREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_WREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_BVALID = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
assign S_AXI_BRESP = 2'b00;
assign S_AXI_ARREADY = ( state == S_READ || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_RVALID = ( state == S_READ )?LOCAL_ACK:1'b0;
assign S_AXI_RRESP = 2'b00;
assign S_AXI_RDATA = ( state == S_READ )?LOCAL_RDATA:32'd0;
endmodule | 15 |
142,222 | data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v | 98,419,535 | fmrv32im_axi_gpio.v | v | 322 | 103 | [] | [] | [] | [(1, 117), (119, 242), (244, 321)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98419535/modules/gpio_v1/src/fmrv32im_axi_gpio.v:225: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s VARREF \'reg_addr\' generates 16 bits.\n : ... In instance fmrv32im_axi_gpio.u_fmrv32im_axi_gpio_ls\n assign LOCAL_ADDR = reg_addr;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,423 | module | module fmrv32im_axi_gpio_ctrl
(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
input [31:0] GPIO_I,
output [31:0] GPIO_OT
);
localparam A_OUT = 8'h00;
localparam A_IN = 8'h04;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg [31:0] reg_gpio_o;
reg [31:0] reg_rdata;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
always @(posedge CLK) begin
if(!RST_N) begin
reg_gpio_o <= 32'd0;
end else begin
if(wr_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_OUT: begin
reg_gpio_o <= LOCAL_WDATA;
end
default: begin
end
endcase
end
end
end
always @(posedge CLK) begin
if(!RST_N) begin
reg_rdata[31:0] <= 32'd0;
rd_ack <= 1'b0;
end else begin
rd_ack <= rd_ena;
if(rd_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_OUT: begin
reg_rdata[31:0] <= reg_gpio_o[31:0];
end
A_IN: begin
reg_rdata[31:0] <= GPIO_I;
end
default: begin
reg_rdata[31:0] <= 32'd0;
end
endcase
end else begin
reg_rdata[31:0] <= 32'd0;
end
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign GPIO_OT = reg_gpio_o;
endmodule | module fmrv32im_axi_gpio_ctrl
(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [31:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
input [31:0] GPIO_I,
output [31:0] GPIO_OT
); |
localparam A_OUT = 8'h00;
localparam A_IN = 8'h04;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg [31:0] reg_gpio_o;
reg [31:0] reg_rdata;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
always @(posedge CLK) begin
if(!RST_N) begin
reg_gpio_o <= 32'd0;
end else begin
if(wr_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_OUT: begin
reg_gpio_o <= LOCAL_WDATA;
end
default: begin
end
endcase
end
end
end
always @(posedge CLK) begin
if(!RST_N) begin
reg_rdata[31:0] <= 32'd0;
rd_ack <= 1'b0;
end else begin
rd_ack <= rd_ena;
if(rd_ena) begin
case(LOCAL_ADDR[7:0] & 8'hFC)
A_OUT: begin
reg_rdata[31:0] <= reg_gpio_o[31:0];
end
A_IN: begin
reg_rdata[31:0] <= GPIO_I;
end
default: begin
reg_rdata[31:0] <= 32'd0;
end
endcase
end else begin
reg_rdata[31:0] <= 32'd0;
end
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign GPIO_OT = reg_gpio_o;
endmodule | 15 |
142,223 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module fmrv32im_axis_uart
#(
parameter RESET_COUNT = 8'd107
)
(
input RST_N,
input CLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output INTERRUPT,
input RXD,
output TXD,
input [31:0] GPIO_I,
output [31:0] GPIO_O,
output [31:0] GPIO_OT
);
wire local_clk;
wire local_cs;
wire local_rnw;
wire local_ack;
wire [15:0] local_addr;
wire [3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
fmrv32im_axis_uart_axils u_fmrv32im_axis_uart_axils
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.LOCAL_CLK ( local_clk ),
.LOCAL_CS ( local_cs ),
.LOCAL_RNW ( local_rnw ),
.LOCAL_ACK ( local_ack ),
.LOCAL_ADDR ( local_addr ),
.LOCAL_BE ( local_be ),
.LOCAL_WDATA ( local_wdata ),
.LOCAL_RDATA ( local_rdata )
);
wire tx_write;
wire [7:0] tx_wdata;
wire tx_full;
wire tx_afull;
wire tx_empty;
wire rx_read;
wire [7:0] rx_rdata;
wire rx_empty;
wire rx_aempty;
fmrv32im_axis_uart_ctl u_fmrv32im_axis_uart_ctl
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.LOCAL_CS ( local_cs ),
.LOCAL_RNW ( local_rnw ),
.LOCAL_ACK ( local_ack ),
.LOCAL_ADDR ( local_addr[15:0] ),
.LOCAL_BE ( local_be[3:0] ),
.LOCAL_WDATA ( local_wdata[31:0] ),
.LOCAL_RDATA ( local_rdata[31:0] ),
.TX_WRITE ( tx_write ),
.TX_WDATA ( tx_wdata ),
.TX_FULL ( tx_full ),
.TX_AFULL ( tx_afull ),
.TX_EMPTY ( tx_empty ),
.RX_READ ( rx_read ),
.RX_RDATA ( rx_rdata ),
.RX_EMPTY ( rx_empty ),
.RX_AEMPTY ( rx_aempty ),
.INTERRUPT ( INTERRUPT ),
.GPIO_I ( GPIO_I ),
.GPIO_O ( GPIO_O ),
.GPIO_OT ( GPIO_OT )
);
uartcon_top
#(
.RESET_COUNT(RESET_COUNT)
)
u_uart_top
(
.rst_n ( RST_N ),
.clk ( CLK ),
.refclk ( CLK ),
.txd ( TXD ),
.rxd ( RXD ),
.write ( tx_write ),
.wdata ( tx_wdata ),
.full ( tx_full ),
.almost_full ( tx_afull ),
.wempty ( tx_empty ),
.read ( rx_read ),
.rdata ( rx_rdata ),
.empty ( rx_empty ),
.almost_empty ( rx_aempty )
);
endmodule | module fmrv32im_axis_uart
#(
parameter RESET_COUNT = 8'd107
)
(
input RST_N,
input CLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output INTERRUPT,
input RXD,
output TXD,
input [31:0] GPIO_I,
output [31:0] GPIO_O,
output [31:0] GPIO_OT
); |
wire local_clk;
wire local_cs;
wire local_rnw;
wire local_ack;
wire [15:0] local_addr;
wire [3:0] local_be;
wire [31:0] local_wdata;
wire [31:0] local_rdata;
fmrv32im_axis_uart_axils u_fmrv32im_axis_uart_axils
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.LOCAL_CLK ( local_clk ),
.LOCAL_CS ( local_cs ),
.LOCAL_RNW ( local_rnw ),
.LOCAL_ACK ( local_ack ),
.LOCAL_ADDR ( local_addr ),
.LOCAL_BE ( local_be ),
.LOCAL_WDATA ( local_wdata ),
.LOCAL_RDATA ( local_rdata )
);
wire tx_write;
wire [7:0] tx_wdata;
wire tx_full;
wire tx_afull;
wire tx_empty;
wire rx_read;
wire [7:0] rx_rdata;
wire rx_empty;
wire rx_aempty;
fmrv32im_axis_uart_ctl u_fmrv32im_axis_uart_ctl
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.LOCAL_CS ( local_cs ),
.LOCAL_RNW ( local_rnw ),
.LOCAL_ACK ( local_ack ),
.LOCAL_ADDR ( local_addr[15:0] ),
.LOCAL_BE ( local_be[3:0] ),
.LOCAL_WDATA ( local_wdata[31:0] ),
.LOCAL_RDATA ( local_rdata[31:0] ),
.TX_WRITE ( tx_write ),
.TX_WDATA ( tx_wdata ),
.TX_FULL ( tx_full ),
.TX_AFULL ( tx_afull ),
.TX_EMPTY ( tx_empty ),
.RX_READ ( rx_read ),
.RX_RDATA ( rx_rdata ),
.RX_EMPTY ( rx_empty ),
.RX_AEMPTY ( rx_aempty ),
.INTERRUPT ( INTERRUPT ),
.GPIO_I ( GPIO_I ),
.GPIO_O ( GPIO_O ),
.GPIO_OT ( GPIO_OT )
);
uartcon_top
#(
.RESET_COUNT(RESET_COUNT)
)
u_uart_top
(
.rst_n ( RST_N ),
.clk ( CLK ),
.refclk ( CLK ),
.txd ( TXD ),
.rxd ( RXD ),
.write ( tx_write ),
.wdata ( tx_wdata ),
.full ( tx_full ),
.almost_full ( tx_afull ),
.wempty ( tx_empty ),
.read ( rx_read ),
.rdata ( rx_rdata ),
.empty ( rx_empty ),
.almost_empty ( rx_aempty )
);
endmodule | 15 |
142,224 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module fmrv32im_axis_uart_axils
(
input ARESETN,
input ACLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output LOCAL_CLK,
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
);
localparam S_IDLE = 2'd0;
localparam S_WRITE = 2'd1;
localparam S_WRITE2 = 2'd2;
localparam S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [15:0] reg_addr;
reg [31:0] reg_wdata;
reg [3:0] reg_be;
always @( posedge ACLK or negedge ARESETN ) begin
if( !ARESETN ) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_addr <= 16'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case( state )
S_IDLE: begin
if( S_AXI_AWVALID ) begin
reg_rnw <= 1'b0;
reg_addr <= S_AXI_AWADDR;
state <= S_WRITE;
end else if( S_AXI_ARVALID ) begin
reg_rnw <= 1'b1;
reg_addr <= S_AXI_ARADDR;
state <= S_READ;
end
end
S_WRITE: begin
if( S_AXI_WVALID ) begin
state <= S_WRITE2;
reg_wdata <= S_AXI_WDATA;
reg_be <= S_AXI_WSTRB;
end
end
S_WRITE2: begin
if( LOCAL_ACK & S_AXI_BREADY ) begin
state <= S_IDLE;
end
end
S_READ: begin
if( LOCAL_ACK & S_AXI_RREADY ) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
assign LOCAL_CLK = ACLK;
assign LOCAL_CS = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADDR = reg_addr;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
assign S_AXI_AWREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_WREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_BVALID = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
assign S_AXI_BRESP = 2'b00;
assign S_AXI_ARREADY = ( state == S_READ || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_RVALID = ( state == S_READ )?LOCAL_ACK:1'b0;
assign S_AXI_RRESP = 2'b00;
assign S_AXI_RDATA = ( state == S_READ )?LOCAL_RDATA:32'd0;
endmodule | module fmrv32im_axis_uart_axils
(
input ARESETN,
input ACLK,
input [15:0] S_AXI_AWADDR,
input [3:0] S_AXI_AWCACHE,
input [2:0] S_AXI_AWPROT,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input [31:0] S_AXI_WDATA,
input [3:0] S_AXI_WSTRB,
input S_AXI_WVALID,
output S_AXI_WREADY,
output S_AXI_BVALID,
input S_AXI_BREADY,
output [1:0] S_AXI_BRESP,
input [15:0] S_AXI_ARADDR,
input [3:0] S_AXI_ARCACHE,
input [2:0] S_AXI_ARPROT,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output [31:0] S_AXI_RDATA,
output [1:0] S_AXI_RRESP,
output S_AXI_RVALID,
input S_AXI_RREADY,
output LOCAL_CLK,
output LOCAL_CS,
output LOCAL_RNW,
input LOCAL_ACK,
output [31:0] LOCAL_ADDR,
output [3:0] LOCAL_BE,
output [31:0] LOCAL_WDATA,
input [31:0] LOCAL_RDATA
); |
localparam S_IDLE = 2'd0;
localparam S_WRITE = 2'd1;
localparam S_WRITE2 = 2'd2;
localparam S_READ = 2'd3;
reg [1:0] state;
reg reg_rnw;
reg [15:0] reg_addr;
reg [31:0] reg_wdata;
reg [3:0] reg_be;
always @( posedge ACLK or negedge ARESETN ) begin
if( !ARESETN ) begin
state <= S_IDLE;
reg_rnw <= 1'b0;
reg_addr <= 16'd0;
reg_wdata <= 32'd0;
reg_be <= 4'd0;
end else begin
case( state )
S_IDLE: begin
if( S_AXI_AWVALID ) begin
reg_rnw <= 1'b0;
reg_addr <= S_AXI_AWADDR;
state <= S_WRITE;
end else if( S_AXI_ARVALID ) begin
reg_rnw <= 1'b1;
reg_addr <= S_AXI_ARADDR;
state <= S_READ;
end
end
S_WRITE: begin
if( S_AXI_WVALID ) begin
state <= S_WRITE2;
reg_wdata <= S_AXI_WDATA;
reg_be <= S_AXI_WSTRB;
end
end
S_WRITE2: begin
if( LOCAL_ACK & S_AXI_BREADY ) begin
state <= S_IDLE;
end
end
S_READ: begin
if( LOCAL_ACK & S_AXI_RREADY ) begin
state <= S_IDLE;
end
end
default: begin
state <= S_IDLE;
end
endcase
end
end
assign LOCAL_CLK = ACLK;
assign LOCAL_CS = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
assign LOCAL_RNW = reg_rnw;
assign LOCAL_ADDR = reg_addr;
assign LOCAL_BE = reg_be;
assign LOCAL_WDATA = reg_wdata;
assign S_AXI_AWREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_WREADY = ( state == S_WRITE || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_BVALID = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
assign S_AXI_BRESP = 2'b00;
assign S_AXI_ARREADY = ( state == S_READ || state == S_IDLE )?1'b1:1'b0;
assign S_AXI_RVALID = ( state == S_READ )?LOCAL_ACK:1'b0;
assign S_AXI_RRESP = 2'b00;
assign S_AXI_RDATA = ( state == S_READ )?LOCAL_RDATA:32'd0;
endmodule | 15 |
142,225 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module fmrv32im_axis_uart_ctl
(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [15:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output TX_WRITE,
output [7:0] TX_WDATA,
input TX_FULL,
input TX_AFULL,
input TX_EMPTY,
output RX_READ,
input [7:0] RX_RDATA,
input RX_EMPTY,
input RX_AEMPTY,
output INTERRUPT,
input [31:0] GPIO_I,
output [31:0] GPIO_O,
output [31:0] GPIO_OT
);
localparam A_STATUS = 16'h00;
localparam A_INTENA = 16'h04;
localparam A_TXD = 16'h08;
localparam A_RXD = 16'h0C;
localparam A_RATE = 16'h10;
localparam A_GPIO_O = 16'h100;
localparam A_GPIO_I = 16'h104;
localparam A_GPIO_OT = 16'h108;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg [31:0] reg_rdata;
reg wr_ack_d;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
reg reg_int_ena_tx, reg_int_ena_rx;
reg [31:0] reg_gpio_o, reg_gpio_ot;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
wr_ack_d <= 1'b0;
reg_int_ena_rx <= 1'b0;
reg_int_ena_tx <= 1'b0;
reg_gpio_o <= 32'd0;
reg_gpio_ot <= 32'd0;
end else begin
wr_ack_d <= wr_ena;
if(wr_ena) begin
case(LOCAL_ADDR[15:0] & 16'hFFFC)
A_INTENA:
begin
reg_int_ena_tx <= LOCAL_WDATA[1];
reg_int_ena_rx <= LOCAL_WDATA[0];
end
A_GPIO_O:
begin
reg_gpio_o <= LOCAL_WDATA;
end
A_GPIO_OT:
begin
reg_gpio_ot <= LOCAL_WDATA;
end
default:
begin
end
endcase
end
end
end
reg rd_ack_d;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
rd_ack <= 1'b0;
rd_ack_d <= 1'b0;
reg_rdata[31:0] <= 32'd0;
end else begin
rd_ack <= rd_ena;
case(LOCAL_ADDR[15:0] & 16'hFFFC)
A_STATUS: reg_rdata[31:0] <= {16'd0, 5'd0, TX_EMPTY, TX_AFULL, TX_FULL, 6'd0, RX_AEMPTY, RX_EMPTY};
A_INTENA: reg_rdata[31:0] <= {30'd0, reg_int_ena_tx, reg_int_ena_rx};
A_TXD: reg_rdata[31:0] <= 32'd0;
A_RXD: reg_rdata[31:0] <= {24'd0, RX_RDATA};
A_GPIO_O: reg_rdata[31:0] <= reg_gpio_o;
A_GPIO_I: reg_rdata[31:0] <= GPIO_I;
A_GPIO_OT: reg_rdata[31:0] <= reg_gpio_ot;
default: reg_rdata[31:0] <= 32'd0;
endcase
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign TX_WRITE = wr_ena & ~wr_ack_d & ((LOCAL_ADDR[7:0] & 8'hFC) == A_TXD);
assign TX_WDATA = LOCAL_WDATA[7:0];
assign RX_READ = rd_ena & ~rd_ack & ((LOCAL_ADDR[7:0] & 8'hFC) == A_RXD);
assign INTERRUPT = (reg_int_ena_tx & TX_FULL) | (reg_int_ena_rx & RX_EMPTY);
assign GPIO_O = reg_gpio_o;
assign GPIO_OT = reg_gpio_ot;
endmodule | module fmrv32im_axis_uart_ctl
(
input RST_N,
input CLK,
input LOCAL_CS,
input LOCAL_RNW,
output LOCAL_ACK,
input [15:0] LOCAL_ADDR,
input [3:0] LOCAL_BE,
input [31:0] LOCAL_WDATA,
output [31:0] LOCAL_RDATA,
output TX_WRITE,
output [7:0] TX_WDATA,
input TX_FULL,
input TX_AFULL,
input TX_EMPTY,
output RX_READ,
input [7:0] RX_RDATA,
input RX_EMPTY,
input RX_AEMPTY,
output INTERRUPT,
input [31:0] GPIO_I,
output [31:0] GPIO_O,
output [31:0] GPIO_OT
); |
localparam A_STATUS = 16'h00;
localparam A_INTENA = 16'h04;
localparam A_TXD = 16'h08;
localparam A_RXD = 16'h0C;
localparam A_RATE = 16'h10;
localparam A_GPIO_O = 16'h100;
localparam A_GPIO_I = 16'h104;
localparam A_GPIO_OT = 16'h108;
wire wr_ena, rd_ena, wr_ack;
reg rd_ack;
reg [31:0] reg_rdata;
reg wr_ack_d;
assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
assign rd_ena = (LOCAL_CS & LOCAL_RNW)?1'b1:1'b0;
assign wr_ack = wr_ena;
reg reg_int_ena_tx, reg_int_ena_rx;
reg [31:0] reg_gpio_o, reg_gpio_ot;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
wr_ack_d <= 1'b0;
reg_int_ena_rx <= 1'b0;
reg_int_ena_tx <= 1'b0;
reg_gpio_o <= 32'd0;
reg_gpio_ot <= 32'd0;
end else begin
wr_ack_d <= wr_ena;
if(wr_ena) begin
case(LOCAL_ADDR[15:0] & 16'hFFFC)
A_INTENA:
begin
reg_int_ena_tx <= LOCAL_WDATA[1];
reg_int_ena_rx <= LOCAL_WDATA[0];
end
A_GPIO_O:
begin
reg_gpio_o <= LOCAL_WDATA;
end
A_GPIO_OT:
begin
reg_gpio_ot <= LOCAL_WDATA;
end
default:
begin
end
endcase
end
end
end
reg rd_ack_d;
always @(posedge CLK or negedge RST_N) begin
if(!RST_N) begin
rd_ack <= 1'b0;
rd_ack_d <= 1'b0;
reg_rdata[31:0] <= 32'd0;
end else begin
rd_ack <= rd_ena;
case(LOCAL_ADDR[15:0] & 16'hFFFC)
A_STATUS: reg_rdata[31:0] <= {16'd0, 5'd0, TX_EMPTY, TX_AFULL, TX_FULL, 6'd0, RX_AEMPTY, RX_EMPTY};
A_INTENA: reg_rdata[31:0] <= {30'd0, reg_int_ena_tx, reg_int_ena_rx};
A_TXD: reg_rdata[31:0] <= 32'd0;
A_RXD: reg_rdata[31:0] <= {24'd0, RX_RDATA};
A_GPIO_O: reg_rdata[31:0] <= reg_gpio_o;
A_GPIO_I: reg_rdata[31:0] <= GPIO_I;
A_GPIO_OT: reg_rdata[31:0] <= reg_gpio_ot;
default: reg_rdata[31:0] <= 32'd0;
endcase
end
end
assign LOCAL_ACK = (wr_ack | rd_ack);
assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
assign TX_WRITE = wr_ena & ~wr_ack_d & ((LOCAL_ADDR[7:0] & 8'hFC) == A_TXD);
assign TX_WDATA = LOCAL_WDATA[7:0];
assign RX_READ = rd_ena & ~rd_ack & ((LOCAL_ADDR[7:0] & 8'hFC) == A_RXD);
assign INTERRUPT = (reg_int_ena_tx & TX_FULL) | (reg_int_ena_rx & RX_EMPTY);
assign GPIO_O = reg_gpio_o;
assign GPIO_OT = reg_gpio_ot;
endmodule | 15 |
142,226 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module uartcon_top
#(
parameter RESET_COUNT = 8'd107
)
(
input rst_n,
input clk,
input refclk,
output txd,
input rxd,
input write,
input [7:0] wdata,
output full,
output almost_full,
output wempty,
input read,
output [7:0] rdata,
output empty,
output almost_empty
);
wire uart_clk;
wire [7:0] tx_data;
wire tx_empty, tx_almost_empty;
wire load;
wire [7:0] rx_data;
wire rx_full, rx_almost_full;
wire save;
reg tx_empty_reg;
reg tx_empty_d1, tx_empty_d2;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_empty_reg <= 1'b1;
tx_empty_d1 <= 1'b0;
tx_empty_d2 <= 1'b0;
end else begin
tx_empty_d1 <= tx_empty;
tx_empty_d2 <= tx_empty_d1;
if((tx_empty_d2 == 1'b0) && (tx_empty_d1 == 1'b1)) begin
tx_empty_reg <= 1'b1;
end else if(write == 1'b1) begin
tx_empty_reg <= 1'b0;
end
end
end
assign wempty = tx_empty_reg;
uartcon_clk #
#(
.RESET_COUNT(RESET_COUNT)
)
u_uartcon_clk
(
.rst_n ( rst_n ),
.clk ( refclk ),
.out_clk ( uart_clk )
);
uartcon_fifo
#(
.FIFO_DEPTH(7),
.FIFO_WIDTH(8)
)
u_tx_fifo
(
.RST_N ( rst_n ),
.FIFO_WR_CLK ( clk ),
.FIFO_WR_ENA ( write ),
.FIFO_WR_LAST ( 1'b1 ),
.FIFO_WR_DATA ( wdata[7:0] ),
.FIFO_WR_FULL ( full ),
.FIFO_WR_ALM_FULL ( almost_full ),
.FIFO_WR_ALM_COUNT ( 7'd1 ),
.FIFO_RD_CLK ( uart_clk ),
.FIFO_RD_ENA ( load ),
.FIFO_RD_DATA ( tx_data[7:0] ),
.FIFO_RD_EMPTY ( tx_empty ),
.FIFO_RD_ALM_EMPTY ( tx_almost_empty ),
.FIFO_RD_ALM_COUNT ( 7'd1 )
);
uartcon_fifo
#(
.FIFO_DEPTH(7),
.FIFO_WIDTH(8)
)
u_rx_fifo
(
.RST_N ( rst_n ),
.FIFO_WR_CLK ( uart_clk ),
.FIFO_WR_ENA ( save ),
.FIFO_WR_LAST ( 1'b1 ),
.FIFO_WR_DATA ( rx_data[7:0] ),
.FIFO_WR_FULL ( rx_full ),
.FIFO_WR_ALM_FULL ( rx_almost_full ),
.FIFO_WR_ALM_COUNT ( 7'd1 ),
.FIFO_RD_CLK ( clk ),
.FIFO_RD_ENA ( read ),
.FIFO_RD_DATA ( rdata[7:0] ),
.FIFO_RD_EMPTY ( empty ),
.FIFO_RD_ALM_EMPTY ( almost_empty ),
.FIFO_RD_ALM_COUNT ( 7'd1 )
);
uartcon_tx u_uartcon_tx
(
.rst_n ( rst_n ),
.clk ( uart_clk ),
.txd ( txd ),
.valid ( ~tx_empty ),
.load ( load ),
.data ( tx_data[7:0] )
);
uartcon_rx u_uartcon_rx
(
.rst_n ( rst_n ),
.clk ( uart_clk ),
.rxd ( rxd ),
.valid ( save ),
.data ( rx_data[7:0] )
);
endmodule | module uartcon_top
#(
parameter RESET_COUNT = 8'd107
)
(
input rst_n,
input clk,
input refclk,
output txd,
input rxd,
input write,
input [7:0] wdata,
output full,
output almost_full,
output wempty,
input read,
output [7:0] rdata,
output empty,
output almost_empty
); |
wire uart_clk;
wire [7:0] tx_data;
wire tx_empty, tx_almost_empty;
wire load;
wire [7:0] rx_data;
wire rx_full, rx_almost_full;
wire save;
reg tx_empty_reg;
reg tx_empty_d1, tx_empty_d2;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_empty_reg <= 1'b1;
tx_empty_d1 <= 1'b0;
tx_empty_d2 <= 1'b0;
end else begin
tx_empty_d1 <= tx_empty;
tx_empty_d2 <= tx_empty_d1;
if((tx_empty_d2 == 1'b0) && (tx_empty_d1 == 1'b1)) begin
tx_empty_reg <= 1'b1;
end else if(write == 1'b1) begin
tx_empty_reg <= 1'b0;
end
end
end
assign wempty = tx_empty_reg;
uartcon_clk #
#(
.RESET_COUNT(RESET_COUNT)
)
u_uartcon_clk
(
.rst_n ( rst_n ),
.clk ( refclk ),
.out_clk ( uart_clk )
);
uartcon_fifo
#(
.FIFO_DEPTH(7),
.FIFO_WIDTH(8)
)
u_tx_fifo
(
.RST_N ( rst_n ),
.FIFO_WR_CLK ( clk ),
.FIFO_WR_ENA ( write ),
.FIFO_WR_LAST ( 1'b1 ),
.FIFO_WR_DATA ( wdata[7:0] ),
.FIFO_WR_FULL ( full ),
.FIFO_WR_ALM_FULL ( almost_full ),
.FIFO_WR_ALM_COUNT ( 7'd1 ),
.FIFO_RD_CLK ( uart_clk ),
.FIFO_RD_ENA ( load ),
.FIFO_RD_DATA ( tx_data[7:0] ),
.FIFO_RD_EMPTY ( tx_empty ),
.FIFO_RD_ALM_EMPTY ( tx_almost_empty ),
.FIFO_RD_ALM_COUNT ( 7'd1 )
);
uartcon_fifo
#(
.FIFO_DEPTH(7),
.FIFO_WIDTH(8)
)
u_rx_fifo
(
.RST_N ( rst_n ),
.FIFO_WR_CLK ( uart_clk ),
.FIFO_WR_ENA ( save ),
.FIFO_WR_LAST ( 1'b1 ),
.FIFO_WR_DATA ( rx_data[7:0] ),
.FIFO_WR_FULL ( rx_full ),
.FIFO_WR_ALM_FULL ( rx_almost_full ),
.FIFO_WR_ALM_COUNT ( 7'd1 ),
.FIFO_RD_CLK ( clk ),
.FIFO_RD_ENA ( read ),
.FIFO_RD_DATA ( rdata[7:0] ),
.FIFO_RD_EMPTY ( empty ),
.FIFO_RD_ALM_EMPTY ( almost_empty ),
.FIFO_RD_ALM_COUNT ( 7'd1 )
);
uartcon_tx u_uartcon_tx
(
.rst_n ( rst_n ),
.clk ( uart_clk ),
.txd ( txd ),
.valid ( ~tx_empty ),
.load ( load ),
.data ( tx_data[7:0] )
);
uartcon_rx u_uartcon_rx
(
.rst_n ( rst_n ),
.clk ( uart_clk ),
.rxd ( rxd ),
.valid ( save ),
.data ( rx_data[7:0] )
);
endmodule | 15 |
142,227 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module uartcon_clk
#(
parameter RESET_COUNT = 8'd107
)
(
input rst_n,
input clk,
output reg out_clk
);
reg [7:0] count;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count[7:0] <= 8'd0;
out_clk <= 1'b0;
end else begin
if(count[7:0] == RESET_COUNT) begin
count[7:0] <= 8'd0;
out_clk <= ~out_clk;
end else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
endmodule | module uartcon_clk
#(
parameter RESET_COUNT = 8'd107
)
(
input rst_n,
input clk,
output reg out_clk
); |
reg [7:0] count;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
count[7:0] <= 8'd0;
out_clk <= 1'b0;
end else begin
if(count[7:0] == RESET_COUNT) begin
count[7:0] <= 8'd0;
out_clk <= ~out_clk;
end else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
endmodule | 15 |
142,228 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module uartcon_rx
(
input rst_n,
input clk,
input rxd,
output valid,
output [7:0] data
);
reg [2:0] reg_rxd;
reg [1:0] sample_count;
reg [2:0] bit_count;
reg [7:0] rx_data;
reg [3:0] state;
localparam S_IDLE = 4'd0;
localparam S_START = 4'd1;
localparam S_DATA = 4'd2;
localparam S_STOP = 4'd3;
localparam S_LAST = 4'd4;
wire detect_startbit, sample_point;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reg_rxd[2:0] <= 3'd0;
end else begin
reg_rxd[2:0] <= {reg_rxd[1:0], rxd};
end
end
assign detect_startbit = (state == S_IDLE) && (reg_rxd[2] == 1'b1) && (reg_rxd[1] == 1'b0);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sample_count[1:0] <= 2'd0;
end else begin
if(detect_startbit == 1'b1) begin
sample_count[1:0] <= 2'd0;
end else begin
sample_count[1:0] <= sample_count[1:0] + 2'd1;
end
end
end
assign sample_point = (sample_count[1:0] == 2'd0)?1'b1:1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= S_IDLE;
bit_count[2:0] <= 3'd0;
rx_data[7:0] <= 8'd0;
end else begin
case(state)
S_IDLE: begin
if(detect_startbit == 1'b1) begin
state <= S_START;
bit_count[2:0] <= 3'd0;
end
end
S_START: begin
if(sample_point == 1'b1) begin
if(reg_rxd[1] == 1'b0) begin
state <= S_DATA;
end else begin
state <= S_IDLE;
end
end
end
S_DATA: begin
if(sample_point == 1'b1) begin
rx_data[7:0] <= {reg_rxd[1], rx_data[7:1]};
if(bit_count[2:0] == 3'd7) begin
state <= S_STOP;
end else begin
bit_count[2:0] <= bit_count[2:0] + 3'd1;
end
end
end
S_STOP: begin
if(sample_point == 1'b1) begin
if(reg_rxd[1] == 1'b1) begin
state <= S_LAST;
end else begin
state <= S_IDLE;
end
end
end
S_LAST: begin
state <= S_IDLE;
end
endcase
end
end
assign valid = (state == S_LAST)?1'b1:1'b0;
assign data[7:0] = rx_data[7:0];
endmodule | module uartcon_rx
(
input rst_n,
input clk,
input rxd,
output valid,
output [7:0] data
); |
reg [2:0] reg_rxd;
reg [1:0] sample_count;
reg [2:0] bit_count;
reg [7:0] rx_data;
reg [3:0] state;
localparam S_IDLE = 4'd0;
localparam S_START = 4'd1;
localparam S_DATA = 4'd2;
localparam S_STOP = 4'd3;
localparam S_LAST = 4'd4;
wire detect_startbit, sample_point;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
reg_rxd[2:0] <= 3'd0;
end else begin
reg_rxd[2:0] <= {reg_rxd[1:0], rxd};
end
end
assign detect_startbit = (state == S_IDLE) && (reg_rxd[2] == 1'b1) && (reg_rxd[1] == 1'b0);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sample_count[1:0] <= 2'd0;
end else begin
if(detect_startbit == 1'b1) begin
sample_count[1:0] <= 2'd0;
end else begin
sample_count[1:0] <= sample_count[1:0] + 2'd1;
end
end
end
assign sample_point = (sample_count[1:0] == 2'd0)?1'b1:1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= S_IDLE;
bit_count[2:0] <= 3'd0;
rx_data[7:0] <= 8'd0;
end else begin
case(state)
S_IDLE: begin
if(detect_startbit == 1'b1) begin
state <= S_START;
bit_count[2:0] <= 3'd0;
end
end
S_START: begin
if(sample_point == 1'b1) begin
if(reg_rxd[1] == 1'b0) begin
state <= S_DATA;
end else begin
state <= S_IDLE;
end
end
end
S_DATA: begin
if(sample_point == 1'b1) begin
rx_data[7:0] <= {reg_rxd[1], rx_data[7:1]};
if(bit_count[2:0] == 3'd7) begin
state <= S_STOP;
end else begin
bit_count[2:0] <= bit_count[2:0] + 3'd1;
end
end
end
S_STOP: begin
if(sample_point == 1'b1) begin
if(reg_rxd[1] == 1'b1) begin
state <= S_LAST;
end else begin
state <= S_IDLE;
end
end
end
S_LAST: begin
state <= S_IDLE;
end
endcase
end
end
assign valid = (state == S_LAST)?1'b1:1'b0;
assign data[7:0] = rx_data[7:0];
endmodule | 15 |
142,229 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module uartcon_tx
(
input rst_n,
input clk,
output txd,
input valid,
output reg load,
input [7:0] data
);
reg [1:0] sample_count;
reg [2:0] bit_count;
reg [7:0] tx_data;
wire sample_point;
reg [3:0] state;
localparam S_IDLE = 4'd0;
localparam S_START = 4'd1;
localparam S_DATA = 4'd2;
localparam S_STOP = 4'd3;
localparam S_LAST = 4'd4;
reg out_data;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sample_count[1:0] <= 2'd0;
bit_count[2:0] <= 3'd0;
end else begin
if(state != S_IDLE) begin
sample_count[1:0] <= sample_count[1:0] + 2'd1;
end else begin
sample_count[1:0] <= 2'd0;
end
if(state == S_DATA) begin
if(sample_point == 1'b1) begin
bit_count[2:0] <= bit_count[2:0] + 3'd1;
end
end else begin
bit_count[2:0] <= 3'd0;
end
end
end
assign sample_point = (sample_count[1:0] == 2'd3)?1'b1:1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= S_IDLE;
tx_data[7:0] <= 8'd0;
load <= 1'b0;
out_data <= 1'b1;
end else begin
case(state)
S_IDLE: begin
if(valid == 1'b1) begin
state <= S_START;
tx_data[7:0] <= data[7:0];
load <= 1'b1;
end
end
S_START: begin
load <= 1'b0;
out_data <= 1'b0;
if(sample_point == 1'b1) begin
state <= S_DATA;
end
end
S_DATA: begin
out_data <= tx_data[0];
if(sample_point == 1'b1) begin
tx_data[7:0] <= {1'b0, tx_data[7:1]};
if(bit_count[2:0] == 3'd7) begin
state <= S_STOP;
end
end
end
S_STOP: begin
out_data <= 1'b1;
if(sample_point == 1'b1) begin
state <= S_LAST;
end
end
S_LAST: begin
out_data <= 1'b1;
if(sample_point == 1'b1) begin
state <= S_IDLE;
end
end
endcase
end
end
assign txd = out_data;
endmodule | module uartcon_tx
(
input rst_n,
input clk,
output txd,
input valid,
output reg load,
input [7:0] data
); |
reg [1:0] sample_count;
reg [2:0] bit_count;
reg [7:0] tx_data;
wire sample_point;
reg [3:0] state;
localparam S_IDLE = 4'd0;
localparam S_START = 4'd1;
localparam S_DATA = 4'd2;
localparam S_STOP = 4'd3;
localparam S_LAST = 4'd4;
reg out_data;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
sample_count[1:0] <= 2'd0;
bit_count[2:0] <= 3'd0;
end else begin
if(state != S_IDLE) begin
sample_count[1:0] <= sample_count[1:0] + 2'd1;
end else begin
sample_count[1:0] <= 2'd0;
end
if(state == S_DATA) begin
if(sample_point == 1'b1) begin
bit_count[2:0] <= bit_count[2:0] + 3'd1;
end
end else begin
bit_count[2:0] <= 3'd0;
end
end
end
assign sample_point = (sample_count[1:0] == 2'd3)?1'b1:1'b0;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
state <= S_IDLE;
tx_data[7:0] <= 8'd0;
load <= 1'b0;
out_data <= 1'b1;
end else begin
case(state)
S_IDLE: begin
if(valid == 1'b1) begin
state <= S_START;
tx_data[7:0] <= data[7:0];
load <= 1'b1;
end
end
S_START: begin
load <= 1'b0;
out_data <= 1'b0;
if(sample_point == 1'b1) begin
state <= S_DATA;
end
end
S_DATA: begin
out_data <= tx_data[0];
if(sample_point == 1'b1) begin
tx_data[7:0] <= {1'b0, tx_data[7:1]};
if(bit_count[2:0] == 3'd7) begin
state <= S_STOP;
end
end
end
S_STOP: begin
out_data <= 1'b1;
if(sample_point == 1'b1) begin
state <= S_LAST;
end
end
S_LAST: begin
out_data <= 1'b1;
if(sample_point == 1'b1) begin
state <= S_IDLE;
end
end
endcase
end
end
assign txd = out_data;
endmodule | 15 |
142,230 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module uartcon_fifo
#(
parameter FIFO_DEPTH = 8,
parameter FIFO_WIDTH = 32
)
(
input RST_N,
input FIFO_WR_CLK,
input FIFO_WR_ENA,
input [FIFO_WIDTH -1:0] FIFO_WR_DATA,
input FIFO_WR_LAST,
output FIFO_WR_FULL,
output FIFO_WR_ALM_FULL,
input [FIFO_DEPTH -1:0] FIFO_WR_ALM_COUNT,
input FIFO_RD_CLK,
input FIFO_RD_ENA,
output [FIFO_WIDTH -1:0] FIFO_RD_DATA,
output FIFO_RD_EMPTY,
output FIFO_RD_ALM_EMPTY,
input [FIFO_DEPTH -1:0] FIFO_RD_ALM_COUNT
);
reg [FIFO_DEPTH -1:0] wr_adrs, wr_rd_count_d1r, wr_rd_count;
reg wr_full, wr_alm_full;
reg [FIFO_DEPTH -1:0] rd_adrs, rd_wr_count_d1r, rd_wr_count;
reg rd_empty, rd_alm_empty;
wire wr_ena;
reg wr_ena_req;
reg [FIFO_DEPTH -1:0] wr_adrs_req;
wire rd_wr_ena, rd_wr_ena_ack;
reg rd_wr_ena_d1r, rd_wr_ena_d2r, rd_wr_ena_d3r;
reg rd_wr_full_d1r, rd_wr_full;
wire rd_ena;
reg rd_ena_req;
reg [FIFO_DEPTH -1:0] rd_adrs_req;
wire wr_rd_ena, wr_rd_ena_ack;
reg wr_rd_ena_d1r, wr_rd_ena_d2r, wr_rd_ena_d3r;
reg wr_rd_empty_d1r, wr_rd_empty;
wire reserve_ena;
reg reserve_empty, reserve_read;
wire reserve_alm_empty;
reg [FIFO_WIDTH -1:0] reserve_data;
wire [FIFO_WIDTH -1:0] rd_fifo;
assign wr_ena = (!wr_full)?(FIFO_WR_ENA):1'b0;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_adrs <= 0;
end else begin
if(wr_ena) wr_adrs <= wr_adrs + 1;
end
end
wire [FIFO_DEPTH -1:0] wr_adrs_s1, wr_adrs_s2;
assign wr_adrs_s1 = wr_rd_count;
assign wr_adrs_s2 = wr_rd_count -1;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_full <= 1'b0;
wr_alm_full <= 1'b0;
end else begin
if(wr_ena & (wr_adrs == wr_adrs_s1)) begin
wr_full <= 1'b1;
end else if(wr_rd_ena & !(wr_adrs == wr_adrs_s1)) begin
wr_full <= 1'b0;
end
if(wr_ena & ((wr_adrs == wr_adrs_s1) | (wr_adrs == wr_adrs_s2))) begin
wr_alm_full <= 1'b1;
end else if(wr_rd_ena & !((wr_adrs == wr_adrs_s1) | (wr_adrs == wr_adrs_s2))) begin
wr_alm_full <= 1'b0;
end
end
end
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_rd_count_d1r <= {FIFO_DEPTH{1'b1}};
wr_rd_count <= {FIFO_DEPTH{1'b1}};
end else begin
wr_rd_ena_d1r <= rd_ena_req;
wr_rd_ena_d2r <= wr_rd_ena_d1r;
wr_rd_ena_d3r <= wr_rd_ena_d2r;
if(wr_rd_ena) begin
wr_rd_count <= rd_adrs_req;
wr_rd_empty <= rd_empty;
end
end
end
assign wr_rd_ena = wr_rd_ena_d2r & ~wr_rd_ena_d3r;
assign wr_rd_ena_ack = wr_rd_ena_d2r & wr_rd_ena_d3r;
wire [FIFO_DEPTH -1:0] wr_adrs_req_s1;
assign wr_adrs_req_s1 = wr_adrs -1;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_ena_req <= 1'b0;
wr_adrs_req <= 0;
end else begin
if(wr_ena & FIFO_WR_LAST & ~rd_wr_ena_ack) begin
wr_ena_req <= 1'b1;
wr_adrs_req <= wr_adrs;
end else if(rd_wr_ena_ack) begin
wr_ena_req <= 1'b0;
end
end
end
reg rd_empty_d;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_adrs <= 0;
end else begin
if(!rd_empty_d & rd_ena) begin
rd_adrs <= rd_adrs + 1;
end
end
end
wire [FIFO_DEPTH -1:0] rd_adrs_s1, rd_adrs_s2;
assign rd_adrs_s1 = rd_wr_count;
assign rd_adrs_s2 = rd_wr_count -1;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_empty <= 1'b1;
rd_empty_d <= 1'b1;
rd_alm_empty <= 1'b1;
end else begin
if(rd_ena & (rd_adrs == rd_adrs_s1)) begin
rd_empty_d <= 1'b1;
end else if(rd_wr_ena & !(rd_adrs == rd_adrs_s1)) begin
rd_empty_d <= 1'b0;
end
rd_empty <= rd_empty_d;
if(rd_ena & ((rd_adrs == rd_adrs_s1) | (rd_adrs == rd_adrs_s2))) begin
rd_alm_empty <= 1'b1;
end else if(rd_wr_ena & !((rd_adrs == rd_adrs_s1) | (rd_adrs == rd_adrs_s2))) begin
rd_alm_empty <= 1'b0;
end
end
end
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_wr_ena_d1r <= 1'b0;
rd_wr_ena_d2r <= 1'b0;
rd_wr_ena_d3r <= 1'b0;
rd_wr_count_d1r <= {FIFO_DEPTH{1'b1}};
rd_wr_count <= {FIFO_DEPTH{1'b1}};
end else begin
rd_wr_ena_d1r <= wr_ena_req;
rd_wr_ena_d2r <= rd_wr_ena_d1r;
rd_wr_ena_d3r <= rd_wr_ena_d2r;
if(rd_wr_ena) begin
rd_wr_count <= wr_adrs_req;
rd_wr_full <= wr_full;
end
end
end
assign rd_wr_ena = ~rd_wr_ena_d3r & rd_wr_ena_d2r;
assign rd_wr_ena_ack = rd_wr_ena_d3r & rd_wr_ena_d2r;
wire [FIFO_DEPTH -1:0] rd_adrs_req_s1;
assign rd_adrs_req_s1 = rd_adrs -1;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_ena_req <= 1'b0;
rd_adrs_req <= 0;
end else begin
if(~rd_ena_req & (rd_adrs_req != rd_adrs_req_s1) & ~wr_rd_ena_ack) begin
rd_ena_req <= 1'b1;
rd_adrs_req <= rd_adrs_req_s1;
end else if(wr_rd_ena_ack) begin
rd_ena_req <= 1'b0;
end
end
end
reg reserve_empty_d;
reg reserve_rdena;
assign reserve_ena = reserve_empty_d & ~rd_empty & ~FIFO_RD_ENA;
assign rd_ena = reserve_ena;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
reserve_data <= {FIFO_WIDTH{1'b0}};
reserve_empty <= 1'b1;
reserve_rdena <= 1'b0;
reserve_empty_d <= 1'b1;
end else begin
if(rd_ena) begin
reserve_data <= rd_fifo;
end
if(reserve_ena) begin
reserve_empty_d <= 1'b0;
end else if(FIFO_RD_ENA) begin
reserve_empty_d <= 1'b1;
end
if(FIFO_RD_ENA) begin
reserve_empty <= 1'b1;
end else begin
reserve_empty <= reserve_empty_d;
end
reserve_rdena <= FIFO_RD_ENA;
end
end
assign reserve_alm_empty = (rd_empty & ~reserve_empty);
assign FIFO_WR_FULL = wr_full;
assign FIFO_WR_ALM_FULL = wr_alm_full;
assign FIFO_RD_EMPTY = (FIFO_RD_ENA)?rd_empty:reserve_empty;
assign FIFO_RD_ALM_EMPTY = (FIFO_RD_ENA)?rd_alm_empty:reserve_alm_empty;
assign FIFO_RD_DATA = (reserve_empty)?rd_fifo:reserve_data;
fifo_ram #(FIFO_DEPTH,FIFO_WIDTH) u_fifo_ram(
.WR_CLK ( FIFO_WR_CLK ),
.WR_ENA ( wr_ena ),
.WR_ADRS ( wr_adrs ),
.WR_DATA ( FIFO_WR_DATA ),
.RD_CLK ( FIFO_RD_CLK ),
.RD_ADRS ( rd_adrs ),
.RD_DATA ( rd_fifo )
);
endmodule | module uartcon_fifo
#(
parameter FIFO_DEPTH = 8,
parameter FIFO_WIDTH = 32
)
(
input RST_N,
input FIFO_WR_CLK,
input FIFO_WR_ENA,
input [FIFO_WIDTH -1:0] FIFO_WR_DATA,
input FIFO_WR_LAST,
output FIFO_WR_FULL,
output FIFO_WR_ALM_FULL,
input [FIFO_DEPTH -1:0] FIFO_WR_ALM_COUNT,
input FIFO_RD_CLK,
input FIFO_RD_ENA,
output [FIFO_WIDTH -1:0] FIFO_RD_DATA,
output FIFO_RD_EMPTY,
output FIFO_RD_ALM_EMPTY,
input [FIFO_DEPTH -1:0] FIFO_RD_ALM_COUNT
); |
reg [FIFO_DEPTH -1:0] wr_adrs, wr_rd_count_d1r, wr_rd_count;
reg wr_full, wr_alm_full;
reg [FIFO_DEPTH -1:0] rd_adrs, rd_wr_count_d1r, rd_wr_count;
reg rd_empty, rd_alm_empty;
wire wr_ena;
reg wr_ena_req;
reg [FIFO_DEPTH -1:0] wr_adrs_req;
wire rd_wr_ena, rd_wr_ena_ack;
reg rd_wr_ena_d1r, rd_wr_ena_d2r, rd_wr_ena_d3r;
reg rd_wr_full_d1r, rd_wr_full;
wire rd_ena;
reg rd_ena_req;
reg [FIFO_DEPTH -1:0] rd_adrs_req;
wire wr_rd_ena, wr_rd_ena_ack;
reg wr_rd_ena_d1r, wr_rd_ena_d2r, wr_rd_ena_d3r;
reg wr_rd_empty_d1r, wr_rd_empty;
wire reserve_ena;
reg reserve_empty, reserve_read;
wire reserve_alm_empty;
reg [FIFO_WIDTH -1:0] reserve_data;
wire [FIFO_WIDTH -1:0] rd_fifo;
assign wr_ena = (!wr_full)?(FIFO_WR_ENA):1'b0;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_adrs <= 0;
end else begin
if(wr_ena) wr_adrs <= wr_adrs + 1;
end
end
wire [FIFO_DEPTH -1:0] wr_adrs_s1, wr_adrs_s2;
assign wr_adrs_s1 = wr_rd_count;
assign wr_adrs_s2 = wr_rd_count -1;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_full <= 1'b0;
wr_alm_full <= 1'b0;
end else begin
if(wr_ena & (wr_adrs == wr_adrs_s1)) begin
wr_full <= 1'b1;
end else if(wr_rd_ena & !(wr_adrs == wr_adrs_s1)) begin
wr_full <= 1'b0;
end
if(wr_ena & ((wr_adrs == wr_adrs_s1) | (wr_adrs == wr_adrs_s2))) begin
wr_alm_full <= 1'b1;
end else if(wr_rd_ena & !((wr_adrs == wr_adrs_s1) | (wr_adrs == wr_adrs_s2))) begin
wr_alm_full <= 1'b0;
end
end
end
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_rd_count_d1r <= {FIFO_DEPTH{1'b1}};
wr_rd_count <= {FIFO_DEPTH{1'b1}};
end else begin
wr_rd_ena_d1r <= rd_ena_req;
wr_rd_ena_d2r <= wr_rd_ena_d1r;
wr_rd_ena_d3r <= wr_rd_ena_d2r;
if(wr_rd_ena) begin
wr_rd_count <= rd_adrs_req;
wr_rd_empty <= rd_empty;
end
end
end
assign wr_rd_ena = wr_rd_ena_d2r & ~wr_rd_ena_d3r;
assign wr_rd_ena_ack = wr_rd_ena_d2r & wr_rd_ena_d3r;
wire [FIFO_DEPTH -1:0] wr_adrs_req_s1;
assign wr_adrs_req_s1 = wr_adrs -1;
always @(posedge FIFO_WR_CLK or negedge RST_N) begin
if(!RST_N) begin
wr_ena_req <= 1'b0;
wr_adrs_req <= 0;
end else begin
if(wr_ena & FIFO_WR_LAST & ~rd_wr_ena_ack) begin
wr_ena_req <= 1'b1;
wr_adrs_req <= wr_adrs;
end else if(rd_wr_ena_ack) begin
wr_ena_req <= 1'b0;
end
end
end
reg rd_empty_d;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_adrs <= 0;
end else begin
if(!rd_empty_d & rd_ena) begin
rd_adrs <= rd_adrs + 1;
end
end
end
wire [FIFO_DEPTH -1:0] rd_adrs_s1, rd_adrs_s2;
assign rd_adrs_s1 = rd_wr_count;
assign rd_adrs_s2 = rd_wr_count -1;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_empty <= 1'b1;
rd_empty_d <= 1'b1;
rd_alm_empty <= 1'b1;
end else begin
if(rd_ena & (rd_adrs == rd_adrs_s1)) begin
rd_empty_d <= 1'b1;
end else if(rd_wr_ena & !(rd_adrs == rd_adrs_s1)) begin
rd_empty_d <= 1'b0;
end
rd_empty <= rd_empty_d;
if(rd_ena & ((rd_adrs == rd_adrs_s1) | (rd_adrs == rd_adrs_s2))) begin
rd_alm_empty <= 1'b1;
end else if(rd_wr_ena & !((rd_adrs == rd_adrs_s1) | (rd_adrs == rd_adrs_s2))) begin
rd_alm_empty <= 1'b0;
end
end
end
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_wr_ena_d1r <= 1'b0;
rd_wr_ena_d2r <= 1'b0;
rd_wr_ena_d3r <= 1'b0;
rd_wr_count_d1r <= {FIFO_DEPTH{1'b1}};
rd_wr_count <= {FIFO_DEPTH{1'b1}};
end else begin
rd_wr_ena_d1r <= wr_ena_req;
rd_wr_ena_d2r <= rd_wr_ena_d1r;
rd_wr_ena_d3r <= rd_wr_ena_d2r;
if(rd_wr_ena) begin
rd_wr_count <= wr_adrs_req;
rd_wr_full <= wr_full;
end
end
end
assign rd_wr_ena = ~rd_wr_ena_d3r & rd_wr_ena_d2r;
assign rd_wr_ena_ack = rd_wr_ena_d3r & rd_wr_ena_d2r;
wire [FIFO_DEPTH -1:0] rd_adrs_req_s1;
assign rd_adrs_req_s1 = rd_adrs -1;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
rd_ena_req <= 1'b0;
rd_adrs_req <= 0;
end else begin
if(~rd_ena_req & (rd_adrs_req != rd_adrs_req_s1) & ~wr_rd_ena_ack) begin
rd_ena_req <= 1'b1;
rd_adrs_req <= rd_adrs_req_s1;
end else if(wr_rd_ena_ack) begin
rd_ena_req <= 1'b0;
end
end
end
reg reserve_empty_d;
reg reserve_rdena;
assign reserve_ena = reserve_empty_d & ~rd_empty & ~FIFO_RD_ENA;
assign rd_ena = reserve_ena;
always @(posedge FIFO_RD_CLK or negedge RST_N) begin
if(!RST_N) begin
reserve_data <= {FIFO_WIDTH{1'b0}};
reserve_empty <= 1'b1;
reserve_rdena <= 1'b0;
reserve_empty_d <= 1'b1;
end else begin
if(rd_ena) begin
reserve_data <= rd_fifo;
end
if(reserve_ena) begin
reserve_empty_d <= 1'b0;
end else if(FIFO_RD_ENA) begin
reserve_empty_d <= 1'b1;
end
if(FIFO_RD_ENA) begin
reserve_empty <= 1'b1;
end else begin
reserve_empty <= reserve_empty_d;
end
reserve_rdena <= FIFO_RD_ENA;
end
end
assign reserve_alm_empty = (rd_empty & ~reserve_empty);
assign FIFO_WR_FULL = wr_full;
assign FIFO_WR_ALM_FULL = wr_alm_full;
assign FIFO_RD_EMPTY = (FIFO_RD_ENA)?rd_empty:reserve_empty;
assign FIFO_RD_ALM_EMPTY = (FIFO_RD_ENA)?rd_alm_empty:reserve_alm_empty;
assign FIFO_RD_DATA = (reserve_empty)?rd_fifo:reserve_data;
fifo_ram #(FIFO_DEPTH,FIFO_WIDTH) u_fifo_ram(
.WR_CLK ( FIFO_WR_CLK ),
.WR_ENA ( wr_ena ),
.WR_ADRS ( wr_adrs ),
.WR_DATA ( FIFO_WR_DATA ),
.RD_CLK ( FIFO_RD_CLK ),
.RD_ADRS ( rd_adrs ),
.RD_DATA ( rd_fifo )
);
endmodule | 15 |
142,231 | data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v | 98,419,535 | fmrv32im_axis_uart.v | v | 1,094 | 105 | [] | [] | [] | null | line:486: before: "#" | null | 1: b"%Error: data/full_repos/permissive/98419535/modules/uart_v1/src/fmrv32im_axis_uart.v:486: syntax error, unexpected '#', expecting TYPE-IDENTIFIER\n #(\n ^\n%Error: Exiting due to 1 error(s)\n" | 313,426 | module | module fifo_ram
#(
parameter DEPTH = 12,
parameter WIDTH = 32
)
(
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
);
reg [WIDTH -1:0] ram [0:(2**DEPTH) -1];
reg [WIDTH -1:0] rd_reg;
always @(posedge WR_CLK) begin
if(WR_ENA) ram[WR_ADRS] <= WR_DATA;
end
always @(posedge RD_CLK) begin
rd_reg <= ram[RD_ADRS];
end
assign RD_DATA = rd_reg;
endmodule | module fifo_ram
#(
parameter DEPTH = 12,
parameter WIDTH = 32
)
(
input WR_CLK,
input WR_ENA,
input [DEPTH -1:0] WR_ADRS,
input [WIDTH -1:0] WR_DATA,
input RD_CLK,
input [DEPTH -1:0] RD_ADRS,
output [WIDTH -1:0] RD_DATA
); |
reg [WIDTH -1:0] ram [0:(2**DEPTH) -1];
reg [WIDTH -1:0] rd_reg;
always @(posedge WR_CLK) begin
if(WR_ENA) ram[WR_ADRS] <= WR_DATA;
end
always @(posedge RD_CLK) begin
rd_reg <= ram[RD_ADRS];
end
assign RD_DATA = rd_reg;
endmodule | 15 |
142,233 | data/full_repos/permissive/98419535/src/fmrv32im_artya7.v | 98,419,535 | fmrv32im_artya7.v | v | 442 | 73 | [] | [] | [] | null | None: at end of input | null | 1: b"%Error: data/full_repos/permissive/98419535/src/fmrv32im_artya7.v:124: Cannot find file containing module: 'fmrv32im_core'\n fmrv32im_core\n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core.v\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core.sv\n fmrv32im_core\n fmrv32im_core.v\n fmrv32im_core.sv\n obj_dir/fmrv32im_core\n obj_dir/fmrv32im_core.v\n obj_dir/fmrv32im_core.sv\n%Error: data/full_repos/permissive/98419535/src/fmrv32im_artya7.v:282: Cannot find file containing module: 'fmrv32im_axi_osram'\nfmrv32im_axi_osram u_fmrv32im_axi_osram (\n^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98419535/src/fmrv32im_artya7.v:392: Cannot find file containing module: 'fmrv32im_axis_uart'\n fmrv32im_axis_uart u_fmrv32im_axis_uart\n ^~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,429 | module | module fmrv32im_artya7
#(
parameter MEM_FILE = "../../../src/imem.hex"
)
(
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
);
wire CLK;
assign CLK = CLK100MHZ;
wire RST_N;
assign RST_N = 1'b1;
wire [31:0] INTERRUPT;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
wire INTERRUPT_UART;
wire [31:0] gpio_i, gpio_ot;
assign INTERRUPT = {31'd0, INTERRUPT_UART};
fmrv32im_core
#(
.MEM_FILE (MEM_FILE)
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
`ifndef MOD_OSRAM
fmrv32im_axis_dummy u_fmrv32im_axis_dummy
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
`else
fmrv32im_axi_osram u_fmrv32im_axi_osram (
.s_aclk (CLK),
.s_aresetn (RST_N),
.s_axi_awid (MM_AXI_AWID),
.s_axi_awaddr (MM_AXI_AWADDR),
.s_axi_awlen (MM_AXI_AWLEN),
.s_axi_awsize (MM_AXI_AWSIZE),
.s_axi_awburst(MM_AXI_AWBURST),
.s_axi_awvalid(MM_AXI_AWVALID),
.s_axi_awready(MM_AXI_AWREADY),
.s_axi_wdata (MM_AXI_WDATA),
.s_axi_wstrb (MM_AXI_WSTRB),
.s_axi_wlast (MM_AXI_WLAST),
.s_axi_wvalid (MM_AXI_WVALID),
.s_axi_wready (MM_AXI_WREADY),
.s_axi_bid (MM_AXI_BID),
.s_axi_bresp (MM_AXI_BRESP),
.s_axi_bvalid (MM_AXI_BVALID),
.s_axi_bready (MM_AXI_BREADY),
.s_axi_arid (MM_AXI_ARID),
.s_axi_araddr (MM_AXI_ARADDR),
.s_axi_arlen (MM_AXI_ARLEN),
.s_axi_arsize (MM_AXI_ARSIZE),
.s_axi_arburst(MM_AXI_ARBURST),
.s_axi_arvalid(MM_AXI_ARVALID),
.s_axi_arready(MM_AXI_ARREADY),
.s_axi_rid (MM_AXI_RID),
.s_axi_rdata (MM_AXI_RDATA),
.s_axi_rresp (MM_AXI_RRESP),
.s_axi_rlast (MM_AXI_RLAST),
.s_axi_rvalid (MM_AXI_RVALID),
.s_axi_rready (MM_AXI_RREADY)
);
`endif
`ifdef MOD_LED
fmrv32im_axi_gpio u_fmrv32im_axi_gpio
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.S_AXI_AWADDR ( IM_AXI_AWADDR ),
.S_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.S_AXI_AWPROT ( IM_AXI_AWPROT ),
.S_AXI_AWVALID ( IM_AXI_AWVALID ),
.S_AXI_AWREADY ( IM_AXI_AWREADY ),
.S_AXI_WDATA ( IM_AXI_WDATA ),
.S_AXI_WSTRB ( IM_AXI_WSTRB ),
.S_AXI_WVALID ( IM_AXI_WVALID ),
.S_AXI_WREADY ( IM_AXI_WREADY ),
.S_AXI_BRESP ( IM_AXI_BRESP ),
.S_AXI_BVALID ( IM_AXI_BVALID ),
.S_AXI_BREADY ( IM_AXI_BREADY ),
.S_AXI_ARADDR ( IM_AXI_ARADDR ),
.S_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.S_AXI_ARPROT ( IM_AXI_ARPROT ),
.S_AXI_ARVALID ( IM_AXI_ARVALID ),
.S_AXI_ARREADY ( IM_AXI_ARREADY ),
.S_AXI_RDATA ( IM_AXI_RDATA ),
.S_AXI_RRESP ( IM_AXI_RRESP ),
.S_AXI_RVALID ( IM_AXI_RVALID ),
.S_AXI_RREADY ( IM_AXI_RREADY ),
.GPIO_I ( gpio_i ),
.GPIO_OT ( gpio_ot )
);
assign led[2:0] = gpio_ot[2:0];
reg [31:0] count;
reg data;
always @(posedge CLK) begin
if(count >= 100000000) begin
count <= 0;
data <= ~data;
end else begin
count <= count +1;
end
end
assign led[3] = data;
`else
`endif
`ifdef MOD_UART
wire [31:0] gpio;
fmrv32im_axis_uart u_fmrv32im_axis_uart
(
.RST_N(RST_N),
.CLK(CLK),
.S_AXI_AWADDR(IM_AXI_AWADDR),
.S_AXI_AWCACHE(IM_AXI_AWCACHE),
.S_AXI_AWPROT(IM_AXI_AWPROT),
.S_AXI_AWVALID(IM_AXI_AWVALID),
.S_AXI_AWREADY(IM_AXI_AWREADY),
.S_AXI_WDATA(IM_AXI_WDATA),
.S_AXI_WSTRB(IM_AXI_WSTRB),
.S_AXI_WVALID(IM_AXI_WVALID),
.S_AXI_WREADY(IM_AXI_WREADY),
.S_AXI_BVALID(IM_AXI_BVALID),
.S_AXI_BREADY(IM_AXI_BREADY),
.S_AXI_BRESP(IM_AXI_BRESP),
.S_AXI_ARADDR(IM_AXI_ARADDR),
.S_AXI_ARCACHE(IM_AXI_ARCACHE),
.S_AXI_ARPROT(IM_AXI_ARPROT),
.S_AXI_ARVALID(IM_AXI_ARVALID),
.S_AXI_ARREADY(IM_AXI_ARREADY),
.S_AXI_RDATA(IM_AXI_RDATA),
.S_AXI_RRESP(IM_AXI_RRESP),
.S_AXI_RVALID(IM_AXI_RVALID),
.S_AXI_RREADY(IM_AXI_RREADY),
.RXD(uart_txd_in),
.TXD(uart_rxd_out),
.INTERRUPT(INTERRUPT_UART),
.GPIO(gpio)
);
assign led[3:0] = gpio[3:0];
`else
assign INTERRUPT_UART = 1'b0;
`endif
endmodule | module fmrv32im_artya7
#(
parameter MEM_FILE = "../../../src/imem.hex"
)
(
input CLK100MHZ,
input uart_txd_in,
output uart_rxd_out,
output [3:0] led
); |
wire CLK;
assign CLK = CLK100MHZ;
wire RST_N;
assign RST_N = 1'b1;
wire [31:0] INTERRUPT;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
wire INTERRUPT_UART;
wire [31:0] gpio_i, gpio_ot;
assign INTERRUPT = {31'd0, INTERRUPT_UART};
fmrv32im_core
#(
.MEM_FILE (MEM_FILE)
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
`ifndef MOD_OSRAM
fmrv32im_axis_dummy u_fmrv32im_axis_dummy
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
`else
fmrv32im_axi_osram u_fmrv32im_axi_osram (
.s_aclk (CLK),
.s_aresetn (RST_N),
.s_axi_awid (MM_AXI_AWID),
.s_axi_awaddr (MM_AXI_AWADDR),
.s_axi_awlen (MM_AXI_AWLEN),
.s_axi_awsize (MM_AXI_AWSIZE),
.s_axi_awburst(MM_AXI_AWBURST),
.s_axi_awvalid(MM_AXI_AWVALID),
.s_axi_awready(MM_AXI_AWREADY),
.s_axi_wdata (MM_AXI_WDATA),
.s_axi_wstrb (MM_AXI_WSTRB),
.s_axi_wlast (MM_AXI_WLAST),
.s_axi_wvalid (MM_AXI_WVALID),
.s_axi_wready (MM_AXI_WREADY),
.s_axi_bid (MM_AXI_BID),
.s_axi_bresp (MM_AXI_BRESP),
.s_axi_bvalid (MM_AXI_BVALID),
.s_axi_bready (MM_AXI_BREADY),
.s_axi_arid (MM_AXI_ARID),
.s_axi_araddr (MM_AXI_ARADDR),
.s_axi_arlen (MM_AXI_ARLEN),
.s_axi_arsize (MM_AXI_ARSIZE),
.s_axi_arburst(MM_AXI_ARBURST),
.s_axi_arvalid(MM_AXI_ARVALID),
.s_axi_arready(MM_AXI_ARREADY),
.s_axi_rid (MM_AXI_RID),
.s_axi_rdata (MM_AXI_RDATA),
.s_axi_rresp (MM_AXI_RRESP),
.s_axi_rlast (MM_AXI_RLAST),
.s_axi_rvalid (MM_AXI_RVALID),
.s_axi_rready (MM_AXI_RREADY)
);
`endif
`ifdef MOD_LED
fmrv32im_axi_gpio u_fmrv32im_axi_gpio
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.S_AXI_AWADDR ( IM_AXI_AWADDR ),
.S_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.S_AXI_AWPROT ( IM_AXI_AWPROT ),
.S_AXI_AWVALID ( IM_AXI_AWVALID ),
.S_AXI_AWREADY ( IM_AXI_AWREADY ),
.S_AXI_WDATA ( IM_AXI_WDATA ),
.S_AXI_WSTRB ( IM_AXI_WSTRB ),
.S_AXI_WVALID ( IM_AXI_WVALID ),
.S_AXI_WREADY ( IM_AXI_WREADY ),
.S_AXI_BRESP ( IM_AXI_BRESP ),
.S_AXI_BVALID ( IM_AXI_BVALID ),
.S_AXI_BREADY ( IM_AXI_BREADY ),
.S_AXI_ARADDR ( IM_AXI_ARADDR ),
.S_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.S_AXI_ARPROT ( IM_AXI_ARPROT ),
.S_AXI_ARVALID ( IM_AXI_ARVALID ),
.S_AXI_ARREADY ( IM_AXI_ARREADY ),
.S_AXI_RDATA ( IM_AXI_RDATA ),
.S_AXI_RRESP ( IM_AXI_RRESP ),
.S_AXI_RVALID ( IM_AXI_RVALID ),
.S_AXI_RREADY ( IM_AXI_RREADY ),
.GPIO_I ( gpio_i ),
.GPIO_OT ( gpio_ot )
);
assign led[2:0] = gpio_ot[2:0];
reg [31:0] count;
reg data;
always @(posedge CLK) begin
if(count >= 100000000) begin
count <= 0;
data <= ~data;
end else begin
count <= count +1;
end
end
assign led[3] = data;
`else
`endif
`ifdef MOD_UART
wire [31:0] gpio;
fmrv32im_axis_uart u_fmrv32im_axis_uart
(
.RST_N(RST_N),
.CLK(CLK),
.S_AXI_AWADDR(IM_AXI_AWADDR),
.S_AXI_AWCACHE(IM_AXI_AWCACHE),
.S_AXI_AWPROT(IM_AXI_AWPROT),
.S_AXI_AWVALID(IM_AXI_AWVALID),
.S_AXI_AWREADY(IM_AXI_AWREADY),
.S_AXI_WDATA(IM_AXI_WDATA),
.S_AXI_WSTRB(IM_AXI_WSTRB),
.S_AXI_WVALID(IM_AXI_WVALID),
.S_AXI_WREADY(IM_AXI_WREADY),
.S_AXI_BVALID(IM_AXI_BVALID),
.S_AXI_BREADY(IM_AXI_BREADY),
.S_AXI_BRESP(IM_AXI_BRESP),
.S_AXI_ARADDR(IM_AXI_ARADDR),
.S_AXI_ARCACHE(IM_AXI_ARCACHE),
.S_AXI_ARPROT(IM_AXI_ARPROT),
.S_AXI_ARVALID(IM_AXI_ARVALID),
.S_AXI_ARREADY(IM_AXI_ARREADY),
.S_AXI_RDATA(IM_AXI_RDATA),
.S_AXI_RRESP(IM_AXI_RRESP),
.S_AXI_RVALID(IM_AXI_RVALID),
.S_AXI_RREADY(IM_AXI_RREADY),
.RXD(uart_txd_in),
.TXD(uart_rxd_out),
.INTERRUPT(INTERRUPT_UART),
.GPIO(gpio)
);
assign led[3:0] = gpio[3:0];
`else
assign INTERRUPT_UART = 1'b0;
`endif
endmodule | 15 |
142,234 | data/full_repos/permissive/98419535/src/fmrv32im_max10.v | 98,419,535 | fmrv32im_max10.v | v | 325 | 70 | [] | [] | [] | null | line:1 column:1: Illegal character '\x00' | null | 1: b"%Error: data/full_repos/permissive/98419535/src/fmrv32im_max10.v:112: Cannot find file containing module: 'fmrv32im_core'\n fmrv32im_core \n ^~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core.v\n data/full_repos/permissive/98419535/src,data/full_repos/permissive/98419535/fmrv32im_core.sv\n fmrv32im_core\n fmrv32im_core.v\n fmrv32im_core.sv\n obj_dir/fmrv32im_core\n obj_dir/fmrv32im_core.v\n obj_dir/fmrv32im_core.sv\n%Error: data/full_repos/permissive/98419535/src/fmrv32im_max10.v:209: Cannot find file containing module: 'fmrv32im_axis_dummy'\n fmrv32im_axis_dummy u_fmrv32im_axis_dummy\n ^~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98419535/src/fmrv32im_max10.v:269: Cannot find file containing module: 'fmrv32im_axi_gpio'\n fmrv32im_axi_gpio u_fmrv32im_axi_gpio\n ^~~~~~~~~~~~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,430 | module | module fmrv32im_max10
#(
parameter MEM_FILE = "../../src/imem.mif"
)
(
input CLK48MHZ,
output [3:0] led
);
wire CLK;
assign CLK = CLK48MHZ;
wire RST_N;
assign RST_N = 1'b1;
wire [31:0] INTERRUPT;
assign INTERRUPT = 32'd0;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
wire [31:0] gpio_i, gpio_ot;
fmrv32im_core
#(
.MEM_FILE (MEM_FILE)
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
fmrv32im_axis_dummy u_fmrv32im_axis_dummy
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
fmrv32im_axi_gpio u_fmrv32im_axi_gpio
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.S_AXI_AWADDR ( IM_AXI_AWADDR ),
.S_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.S_AXI_AWPROT ( IM_AXI_AWPROT ),
.S_AXI_AWVALID ( IM_AXI_AWVALID ),
.S_AXI_AWREADY ( IM_AXI_AWREADY ),
.S_AXI_WDATA ( IM_AXI_WDATA ),
.S_AXI_WSTRB ( IM_AXI_WSTRB ),
.S_AXI_WVALID ( IM_AXI_WVALID ),
.S_AXI_WREADY ( IM_AXI_WREADY ),
.S_AXI_BRESP ( IM_AXI_BRESP ),
.S_AXI_BVALID ( IM_AXI_BVALID ),
.S_AXI_BREADY ( IM_AXI_BREADY ),
.S_AXI_ARADDR ( IM_AXI_ARADDR ),
.S_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.S_AXI_ARPROT ( IM_AXI_ARPROT ),
.S_AXI_ARVALID ( IM_AXI_ARVALID ),
.S_AXI_ARREADY ( IM_AXI_ARREADY ),
.S_AXI_RDATA ( IM_AXI_RDATA ),
.S_AXI_RRESP ( IM_AXI_RRESP ),
.S_AXI_RVALID ( IM_AXI_RVALID ),
.S_AXI_RREADY ( IM_AXI_RREADY ),
.GPIO_I ( gpio_i ),
.GPIO_OT ( gpio_ot )
);
assign led[2:0] = ~gpio_ot[2:0];
reg [31:0] count;
reg data;
always @(posedge CLK) begin
if(count >= 48000000) begin
count <= 0;
data <= ~data;
end else begin
count <= count +1;
end
end
assign led[3] = ~data;
endmodule | module fmrv32im_max10
#(
parameter MEM_FILE = "../../src/imem.mif"
)
(
input CLK48MHZ,
output [3:0] led
); |
wire CLK;
assign CLK = CLK48MHZ;
wire RST_N;
assign RST_N = 1'b1;
wire [31:0] INTERRUPT;
assign INTERRUPT = 32'd0;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
wire [31:0] gpio_i, gpio_ot;
fmrv32im_core
#(
.MEM_FILE (MEM_FILE)
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
fmrv32im_axis_dummy u_fmrv32im_axis_dummy
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
fmrv32im_axi_gpio u_fmrv32im_axi_gpio
(
.RST_N ( RST_N ),
.CLK ( CLK ),
.S_AXI_AWADDR ( IM_AXI_AWADDR ),
.S_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.S_AXI_AWPROT ( IM_AXI_AWPROT ),
.S_AXI_AWVALID ( IM_AXI_AWVALID ),
.S_AXI_AWREADY ( IM_AXI_AWREADY ),
.S_AXI_WDATA ( IM_AXI_WDATA ),
.S_AXI_WSTRB ( IM_AXI_WSTRB ),
.S_AXI_WVALID ( IM_AXI_WVALID ),
.S_AXI_WREADY ( IM_AXI_WREADY ),
.S_AXI_BRESP ( IM_AXI_BRESP ),
.S_AXI_BVALID ( IM_AXI_BVALID ),
.S_AXI_BREADY ( IM_AXI_BREADY ),
.S_AXI_ARADDR ( IM_AXI_ARADDR ),
.S_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.S_AXI_ARPROT ( IM_AXI_ARPROT ),
.S_AXI_ARVALID ( IM_AXI_ARVALID ),
.S_AXI_ARREADY ( IM_AXI_ARREADY ),
.S_AXI_RDATA ( IM_AXI_RDATA ),
.S_AXI_RRESP ( IM_AXI_RRESP ),
.S_AXI_RVALID ( IM_AXI_RVALID ),
.S_AXI_RREADY ( IM_AXI_RREADY ),
.GPIO_I ( gpio_i ),
.GPIO_OT ( gpio_ot )
);
assign led[2:0] = ~gpio_ot[2:0];
reg [31:0] count;
reg data;
always @(posedge CLK) begin
if(count >= 48000000) begin
count <= 0;
data <= ~data;
end else begin
count <= count +1;
end
end
assign led[3] = ~data;
endmodule | 15 |
142,236 | data/full_repos/permissive/98419535/src/tb_ArtyA7.v | 98,419,535 | tb_ArtyA7.v | v | 239 | 104 | [] | [] | [] | null | line:23: before: "u_ArtyA7" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:23: Unsupported: Verilog 1995 force\n force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:32: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:34: Unsupported: Verilog 1995 force\n force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:50: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:65: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:67: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:77: Unsupported: Ignoring delay on this delayed statement.\n #(2000000);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:90: Unsupported: wait statements\n wait(led==4\'hF);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:92: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:100: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:168: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:171: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:177: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:179: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:181: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:183: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:185: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:187: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:189: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:191: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:193: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:195: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:197: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:199: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:201: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:208: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:210: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:212: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:214: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:216: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:218: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:220: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:222: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:224: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:226: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:232: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,432 | module | module tb_ArtyA7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
#(2000000);
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait(led==4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
ArtyA7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_ArtyA7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule | module tb_ArtyA7; |
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
#(2000000);
u_task_uart.write("e");
u_task_uart.write("c");
u_task_uart.write("h");
u_task_uart.write("o");
u_task_uart.write("b");
u_task_uart.write("a");
u_task_uart.write("c");
u_task_uart.write("k");
u_task_uart.write("\r");
u_task_uart.write("\n");
wait(led==4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
ArtyA7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_ArtyA7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule | 15 |
142,237 | data/full_repos/permissive/98419535/src/tb_ArtyA7.v | 98,419,535 | tb_ArtyA7.v | v | 239 | 104 | [] | [] | [] | null | line:23: before: "u_ArtyA7" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:23: Unsupported: Verilog 1995 force\n force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:32: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:34: Unsupported: Verilog 1995 force\n force u_ArtyA7.u_fmrv32im_artya7_wrapper.fmrv32im_artya7_i.High_dout = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:50: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:65: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:67: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:77: Unsupported: Ignoring delay on this delayed statement.\n #(2000000);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:90: Unsupported: wait statements\n wait(led==4\'hF);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:92: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:100: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:168: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:171: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:177: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:179: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:181: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:183: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:185: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:187: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:189: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:191: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:193: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:195: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:197: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:199: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:201: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:208: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:210: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:212: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:214: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:216: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:218: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:220: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:222: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:224: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:226: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_ArtyA7.v:232: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 5 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,432 | module | module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | module task_uart(
tx,
rx
); |
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | 15 |
142,238 | data/full_repos/permissive/98419535/src/tb_axil_slave_model.v | 98,419,535 | tb_axil_slave_model.v | v | 83 | 51 | [] | [] | [] | [(2, 82)] | null | data/verilator_xmls/bd771972-2edc-49bd-b920-b6e12f3d2b32.xml | null | 313,433 | module | module tb_axil_slave_model
(
input ARESETN,
input ACLK,
input [31:0] M_AXI_AWADDR,
input [3:0] M_AXI_AWCACHE,
input [2:0] M_AXI_AWPROT,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
input [31:0] M_AXI_WDATA,
input [3:0] M_AXI_WSTRB,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
output reg [1:0] M_AXI_BRESP,
output M_AXI_BVALID,
input M_AXI_BREADY,
input [31:0] M_AXI_ARADDR,
input [3:0] M_AXI_ARCACHE,
input [2:0] M_AXI_ARPROT,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
output [31:0] M_AXI_RDATA,
output reg [1:0] M_AXI_RRESP,
output M_AXI_RVALID,
input M_AXI_RREADY
);
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BRESP = 0;
M_AXI_RRESP = 0;
M_AXI_ARREADY = 1;
end
reg axi_rena;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if(!ARESETN) begin
axi_rena <= 0;
axi_length <= 0;
end else begin
if(M_AXI_RVALID & M_AXI_RREADY) begin
axi_rena <= 0;
end else if(M_AXI_ARVALID) begin
axi_rena <= 1;
end
end
end
assign M_AXI_RDATA = M_AXI_ARADDR;
assign M_AXI_RVALID = axi_rena & M_AXI_RREADY;
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN)begin
if(!ARESETN) begin
axi_wvalid <= 0;
end else begin
if(M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule | module tb_axil_slave_model
(
input ARESETN,
input ACLK,
input [31:0] M_AXI_AWADDR,
input [3:0] M_AXI_AWCACHE,
input [2:0] M_AXI_AWPROT,
input M_AXI_AWVALID,
output reg M_AXI_AWREADY,
input [31:0] M_AXI_WDATA,
input [3:0] M_AXI_WSTRB,
input M_AXI_WVALID,
output reg M_AXI_WREADY,
output reg [1:0] M_AXI_BRESP,
output M_AXI_BVALID,
input M_AXI_BREADY,
input [31:0] M_AXI_ARADDR,
input [3:0] M_AXI_ARCACHE,
input [2:0] M_AXI_ARPROT,
input M_AXI_ARVALID,
output reg M_AXI_ARREADY,
output [31:0] M_AXI_RDATA,
output reg [1:0] M_AXI_RRESP,
output M_AXI_RVALID,
input M_AXI_RREADY
); |
initial begin
M_AXI_AWREADY = 1;
M_AXI_WREADY = 1;
M_AXI_BRESP = 0;
M_AXI_RRESP = 0;
M_AXI_ARREADY = 1;
end
reg axi_rena;
reg [7:0] axi_length;
always @(posedge ACLK or negedge ARESETN) begin
if(!ARESETN) begin
axi_rena <= 0;
axi_length <= 0;
end else begin
if(M_AXI_RVALID & M_AXI_RREADY) begin
axi_rena <= 0;
end else if(M_AXI_ARVALID) begin
axi_rena <= 1;
end
end
end
assign M_AXI_RDATA = M_AXI_ARADDR;
assign M_AXI_RVALID = axi_rena & M_AXI_RREADY;
reg axi_wvalid;
always @(posedge ACLK or negedge ARESETN)begin
if(!ARESETN) begin
axi_wvalid <= 0;
end else begin
if(M_AXI_BREADY) begin
axi_wvalid <= 0;
end else if (M_AXI_WVALID) begin
axi_wvalid <= 1;
end
end
end
assign M_AXI_BVALID = axi_wvalid;
endmodule | 15 |
142,240 | data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v | 98,419,535 | tb_fmrv32im_artya7.v | v | 220 | 91 | [] | [] | [] | null | line:23: before: "u_fmrv32im_artya7" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:23: Unsupported: Verilog 1995 force\n force u_fmrv32im_artya7.RST_N = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:32: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:34: Unsupported: Verilog 1995 force\n force u_fmrv32im_artya7.RST_N = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:49: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:63: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:65: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:71: Unsupported: wait statements\n wait((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32\'h0000_0800) &\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:74: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:81: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:149: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:152: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:158: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:160: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:162: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:164: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:166: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:168: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:170: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:172: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:174: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:176: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:178: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:180: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:182: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:189: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:191: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:193: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:195: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:197: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:199: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:201: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:203: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:205: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:207: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:213: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,435 | module | module tb_fmrv32im_artya7;
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_artya7.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_artya7.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_artya7.u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
fmrv32im_artya7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_artya7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_fmrv32im_artya7.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule | module tb_fmrv32im_artya7; |
reg sim_end;
reg RST_N;
reg CLK;
wire uart_txd_in;
wire uart_rxd_out;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_artya7.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_artya7.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_artya7.u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_artya7.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
integer iena_count;
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x", rslt);
$display("Inst Count: %d", iena_count);
$finish();
end
fmrv32im_artya7
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_artya7
(
.CLK100MHZ (CLK),
.uart_txd_in (uart_txd_in),
.uart_rxd_out (uart_rxd_out),
.led (led)
);
always @(posedge CLK) begin
if(!RST_N) begin
iena_count <= 0;
end else begin
if(u_fmrv32im_artya7.u_fmrv32im_core.ibus_ena) begin
iena_count <= iena_count +1;
end
end
end
task_uart u_task_uart(
.tx(uart_txd_in),
.rx(uart_rxd_out)
);
endmodule | 15 |
142,241 | data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v | 98,419,535 | tb_fmrv32im_artya7.v | v | 220 | 91 | [] | [] | [] | null | line:23: before: "u_fmrv32im_artya7" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:23: Unsupported: Verilog 1995 force\n force u_fmrv32im_artya7.RST_N = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:30: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:32: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:34: Unsupported: Verilog 1995 force\n force u_fmrv32im_artya7.RST_N = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:49: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:63: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:65: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:71: Unsupported: wait statements\n wait((u_fmrv32im_artya7.u_fmrv32im_core.dbus_addr == 32\'h0000_0800) &\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:74: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:81: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:149: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:152: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:158: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:160: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:162: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:164: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:166: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:168: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:170: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:172: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:174: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:176: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:178: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:180: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:182: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:189: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:191: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:193: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:195: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:197: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:199: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:201: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:203: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:205: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:207: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_artya7.v:213: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,435 | module | module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | module task_uart(
tx,
rx
); |
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | 15 |
142,242 | data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v | 98,419,535 | tb_fmrv32im_core.v | v | 358 | 91 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xc1 in position 1816: invalid start byte | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:106: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:108: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:118: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:132: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:134: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:140: Unsupported: wait statements\n wait((u_fmrv32im_core.dbus_addr == 32\'h0000_0800) & \n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:143: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_core.v:149: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Error: Exiting due to 6 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,436 | module | module tb_fmrv32im_core;
reg sim_end;
reg RST_N;
reg CLK;
reg [31:0] INTERRUPT;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
INTERRUPT = 0;
#100;
@(posedge CLK);
RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
fmrv32im_core
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
tb_axi_slave_model u_axi_slave
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
tb_axil_slave_model u_axil_slave
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWADDR ( IM_AXI_AWADDR ),
.M_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.M_AXI_AWPROT ( IM_AXI_AWPROT ),
.M_AXI_AWVALID ( IM_AXI_AWVALID ),
.M_AXI_AWREADY ( IM_AXI_AWREADY ),
.M_AXI_WDATA ( IM_AXI_WDATA ),
.M_AXI_WSTRB ( IM_AXI_WSTRB ),
.M_AXI_WVALID ( IM_AXI_WVALID ),
.M_AXI_WREADY ( IM_AXI_WREADY ),
.M_AXI_BRESP ( IM_AXI_BRESP ),
.M_AXI_BVALID ( IM_AXI_BVALID ),
.M_AXI_BREADY ( IM_AXI_BREADY ),
.M_AXI_ARADDR ( IM_AXI_ARADDR ),
.M_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.M_AXI_ARPROT ( IM_AXI_ARPROT ),
.M_AXI_ARVALID ( IM_AXI_ARVALID ),
.M_AXI_ARREADY ( IM_AXI_ARREADY ),
.M_AXI_RDATA ( IM_AXI_RDATA ),
.M_AXI_RRESP ( IM_AXI_RRESP ),
.M_AXI_RVALID ( IM_AXI_RVALID ),
.M_AXI_RREADY ( IM_AXI_RREADY )
);
endmodule | module tb_fmrv32im_core; |
reg sim_end;
reg RST_N;
reg CLK;
reg [31:0] INTERRUPT;
wire [15:0] IM_AXI_AWADDR;
wire [3:0] IM_AXI_AWCACHE;
wire [2:0] IM_AXI_AWPROT;
wire IM_AXI_AWVALID;
wire IM_AXI_AWREADY;
wire [31:0] IM_AXI_WDATA;
wire [3:0] IM_AXI_WSTRB;
wire IM_AXI_WVALID;
wire IM_AXI_WREADY;
wire IM_AXI_BVALID;
wire IM_AXI_BREADY;
wire [1:0] IM_AXI_BRESP;
wire [15:0] IM_AXI_ARADDR;
wire [3:0] IM_AXI_ARCACHE;
wire [2:0] IM_AXI_ARPROT;
wire IM_AXI_ARVALID;
wire IM_AXI_ARREADY;
wire [31:0] IM_AXI_RDATA;
wire [1:0] IM_AXI_RRESP;
wire IM_AXI_RVALID;
wire IM_AXI_RREADY;
wire [0:0] MM_AXI_AWID;
wire [31:0] MM_AXI_AWADDR;
wire [7:0] MM_AXI_AWLEN;
wire [2:0] MM_AXI_AWSIZE;
wire [1:0] MM_AXI_AWBURST;
wire MM_AXI_AWLOCK;
wire [3:0] MM_AXI_AWCACHE;
wire [2:0] MM_AXI_AWPROT;
wire [3:0] MM_AXI_AWQOS;
wire [0:0] MM_AXI_AWUSER;
wire MM_AXI_AWVALID;
wire MM_AXI_AWREADY;
wire [31:0] MM_AXI_WDATA;
wire [3:0] MM_AXI_WSTRB;
wire MM_AXI_WLAST;
wire [0:0] MM_AXI_WUSER;
wire MM_AXI_WVALID;
wire MM_AXI_WREADY;
wire [0:0] MM_AXI_BID;
wire [1:0] MM_AXI_BRESP;
wire [0:0] MM_AXI_BUSER;
wire MM_AXI_BVALID;
wire MM_AXI_BREADY;
wire [0:0] MM_AXI_ARID;
wire [31:0] MM_AXI_ARADDR;
wire [7:0] MM_AXI_ARLEN;
wire [2:0] MM_AXI_ARSIZE;
wire [1:0] MM_AXI_ARBURST;
wire [1:0] MM_AXI_ARLOCK;
wire [3:0] MM_AXI_ARCACHE;
wire [2:0] MM_AXI_ARPROT;
wire [3:0] MM_AXI_ARQOS;
wire [0:0] MM_AXI_ARUSER;
wire MM_AXI_ARVALID;
wire MM_AXI_ARREADY;
wire [0:0] MM_AXI_RID;
wire [31:0] MM_AXI_RDATA;
wire [1:0] MM_AXI_RRESP;
wire MM_AXI_RLAST;
wire [0:0] MM_AXI_RUSER;
wire MM_AXI_RVALID;
wire MM_AXI_RREADY;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
INTERRUPT = 0;
#100;
@(posedge CLK);
RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
fmrv32im_core
#(
.MEM_FILE ("../../../../src/imem.hex")
)
u_fmrv32im_core
(
.RST_N (RST_N),
.CLK (CLK),
.INTERRUPT (INTERRUPT),
.MM_AXI_AWID (MM_AXI_AWID),
.MM_AXI_AWADDR (MM_AXI_AWADDR),
.MM_AXI_AWLEN (MM_AXI_AWLEN),
.MM_AXI_AWSIZE (MM_AXI_AWSIZE),
.MM_AXI_AWBURST (MM_AXI_AWBURST),
.MM_AXI_AWLOCK (MM_AXI_AWLOCK),
.MM_AXI_AWCACHE (MM_AXI_AWCACHE),
.MM_AXI_AWPROT (MM_AXI_AWPROT),
.MM_AXI_AWQOS (MM_AXI_AWQOS),
.MM_AXI_AWUSER (MM_AXI_AWUSER),
.MM_AXI_AWVALID (MM_AXI_AWVALID),
.MM_AXI_AWREADY (MM_AXI_AWREADY),
.MM_AXI_WDATA (MM_AXI_WDATA),
.MM_AXI_WSTRB (MM_AXI_WSTRB),
.MM_AXI_WLAST (MM_AXI_WLAST),
.MM_AXI_WUSER (MM_AXI_WUSER),
.MM_AXI_WVALID (MM_AXI_WVALID),
.MM_AXI_WREADY (MM_AXI_WREADY),
.MM_AXI_BID (MM_AXI_BID),
.MM_AXI_BRESP (MM_AXI_BRESP),
.MM_AXI_BUSER (MM_AXI_BUSER),
.MM_AXI_BVALID (MM_AXI_BVALID),
.MM_AXI_BREADY (MM_AXI_BREADY),
.MM_AXI_ARID (MM_AXI_ARID),
.MM_AXI_ARADDR (MM_AXI_ARADDR),
.MM_AXI_ARLEN (MM_AXI_ARLEN),
.MM_AXI_ARSIZE (MM_AXI_ARSIZE),
.MM_AXI_ARBURST (MM_AXI_ARBURST),
.MM_AXI_ARLOCK (MM_AXI_ARLOCK),
.MM_AXI_ARCACHE (MM_AXI_ARCACHE),
.MM_AXI_ARPROT (MM_AXI_ARPROT),
.MM_AXI_ARQOS (MM_AXI_ARQOS),
.MM_AXI_ARUSER (MM_AXI_ARUSER),
.MM_AXI_ARVALID (MM_AXI_ARVALID),
.MM_AXI_ARREADY (MM_AXI_ARREADY),
.MM_AXI_RID (MM_AXI_RID),
.MM_AXI_RDATA (MM_AXI_RDATA),
.MM_AXI_RRESP (MM_AXI_RRESP),
.MM_AXI_RLAST (MM_AXI_RLAST),
.MM_AXI_RUSER (MM_AXI_RUSER),
.MM_AXI_RVALID (MM_AXI_RVALID),
.MM_AXI_RREADY (MM_AXI_RREADY),
.IM_AXI_AWADDR (IM_AXI_AWADDR),
.IM_AXI_AWCACHE (IM_AXI_AWCACHE),
.IM_AXI_AWPROT (IM_AXI_AWPROT),
.IM_AXI_AWVALID (IM_AXI_AWVALID),
.IM_AXI_AWREADY (IM_AXI_AWREADY),
.IM_AXI_WDATA (IM_AXI_WDATA),
.IM_AXI_WSTRB (IM_AXI_WSTRB),
.IM_AXI_WVALID (IM_AXI_WVALID),
.IM_AXI_WREADY (IM_AXI_WREADY),
.IM_AXI_BVALID (IM_AXI_BVALID),
.IM_AXI_BREADY (IM_AXI_BREADY),
.IM_AXI_BRESP (IM_AXI_BRESP),
.IM_AXI_ARADDR (IM_AXI_ARADDR),
.IM_AXI_ARCACHE (IM_AXI_ARCACHE),
.IM_AXI_ARPROT (IM_AXI_ARPROT),
.IM_AXI_ARVALID (IM_AXI_ARVALID),
.IM_AXI_ARREADY (IM_AXI_ARREADY),
.IM_AXI_RDATA (IM_AXI_RDATA),
.IM_AXI_RRESP (IM_AXI_RRESP),
.IM_AXI_RVALID (IM_AXI_RVALID),
.IM_AXI_RREADY (IM_AXI_RREADY)
);
tb_axi_slave_model u_axi_slave
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWID ( MM_AXI_AWID ),
.M_AXI_AWADDR ( MM_AXI_AWADDR ),
.M_AXI_AWLEN ( MM_AXI_AWLEN ),
.M_AXI_AWSIZE ( MM_AXI_AWSIZE ),
.M_AXI_AWBURST ( MM_AXI_AWBURST ),
.M_AXI_AWLOCK ( MM_AXI_AWLOCK ),
.M_AXI_AWCACHE ( MM_AXI_AWCACHE ),
.M_AXI_AWPROT ( MM_AXI_AWPROT ),
.M_AXI_AWQOS ( MM_AXI_AWQOS ),
.M_AXI_AWUSER ( MM_AXI_AWUSER ),
.M_AXI_AWVALID ( MM_AXI_AWVALID ),
.M_AXI_AWREADY ( MM_AXI_AWREADY ),
.M_AXI_WDATA ( MM_AXI_WDATA ),
.M_AXI_WSTRB ( MM_AXI_WSTRB ),
.M_AXI_WLAST ( MM_AXI_WLAST ),
.M_AXI_WUSER ( MM_AXI_WUSER ),
.M_AXI_WVALID ( MM_AXI_WVALID ),
.M_AXI_WREADY ( MM_AXI_WREADY ),
.M_AXI_BID ( MM_AXI_BID ),
.M_AXI_BRESP ( MM_AXI_BRESP ),
.M_AXI_BUSER ( MM_AXI_BUSER ),
.M_AXI_BVALID ( MM_AXI_BVALID ),
.M_AXI_BREADY ( MM_AXI_BREADY ),
.M_AXI_ARID ( MM_AXI_ARID ),
.M_AXI_ARADDR ( MM_AXI_ARADDR ),
.M_AXI_ARLEN ( MM_AXI_ARLEN ),
.M_AXI_ARSIZE ( MM_AXI_ARSIZE ),
.M_AXI_ARBURST ( MM_AXI_ARBURST ),
.M_AXI_ARLOCK ( MM_AXI_ARLOCK ),
.M_AXI_ARCACHE ( MM_AXI_ARCACHE ),
.M_AXI_ARPROT ( MM_AXI_ARPROT ),
.M_AXI_ARQOS ( MM_AXI_ARQOS ),
.M_AXI_ARUSER ( MM_AXI_ARUSER ),
.M_AXI_ARVALID ( MM_AXI_ARVALID ),
.M_AXI_ARREADY ( MM_AXI_ARREADY ),
.M_AXI_RID ( MM_AXI_RID ),
.M_AXI_RDATA ( MM_AXI_RDATA ),
.M_AXI_RRESP ( MM_AXI_RRESP ),
.M_AXI_RLAST ( MM_AXI_RLAST ),
.M_AXI_RUSER ( MM_AXI_RUSER ),
.M_AXI_RVALID ( MM_AXI_RVALID ),
.M_AXI_RREADY ( MM_AXI_RREADY )
);
tb_axil_slave_model u_axil_slave
(
.ARESETN ( RST_N ),
.ACLK ( CLK ),
.M_AXI_AWADDR ( IM_AXI_AWADDR ),
.M_AXI_AWCACHE ( IM_AXI_AWCACHE ),
.M_AXI_AWPROT ( IM_AXI_AWPROT ),
.M_AXI_AWVALID ( IM_AXI_AWVALID ),
.M_AXI_AWREADY ( IM_AXI_AWREADY ),
.M_AXI_WDATA ( IM_AXI_WDATA ),
.M_AXI_WSTRB ( IM_AXI_WSTRB ),
.M_AXI_WVALID ( IM_AXI_WVALID ),
.M_AXI_WREADY ( IM_AXI_WREADY ),
.M_AXI_BRESP ( IM_AXI_BRESP ),
.M_AXI_BVALID ( IM_AXI_BVALID ),
.M_AXI_BREADY ( IM_AXI_BREADY ),
.M_AXI_ARADDR ( IM_AXI_ARADDR ),
.M_AXI_ARCACHE ( IM_AXI_ARCACHE ),
.M_AXI_ARPROT ( IM_AXI_ARPROT ),
.M_AXI_ARVALID ( IM_AXI_ARVALID ),
.M_AXI_ARREADY ( IM_AXI_ARREADY ),
.M_AXI_RDATA ( IM_AXI_RDATA ),
.M_AXI_RRESP ( IM_AXI_RRESP ),
.M_AXI_RVALID ( IM_AXI_RVALID ),
.M_AXI_RREADY ( IM_AXI_RREADY )
);
endmodule | 15 |
142,243 | data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v | 98,419,535 | tb_fmrv32im_max10.v | v | 87 | 91 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xd3 in position 1818: invalid continuation byte | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:17: Unsupported: Verilog 1995 force\n force u_fmrv32im_max10.RST_N = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:19: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:21: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:23: Unsupported: Verilog 1995 force\n force u_fmrv32im_max10.RST_N = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:46: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:48: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:54: Unsupported: wait statements\n wait((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32\'h0000_0800) & \n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:57: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_fmrv32im_max10.v:63: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Error: Exiting due to 8 error(s), 2 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,437 | module | module tb_fmrv32im_max10;
reg sim_end;
reg RST_N;
reg CLK;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_max10.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_max10.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_max10.u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
fmrv32im_max10
#(
.MEM_FILE ("../../../../src/imem.mif")
)
u_fmrv32im_max10
(
.CLK48MHZ (CLK),
.led (led)
);
endmodule | module tb_fmrv32im_max10; |
reg sim_end;
reg RST_N;
reg CLK;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_fmrv32im_max10.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_fmrv32im_max10.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
reg [31:0] rslt;
always @(posedge CLK) begin
if((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF))
begin
rslt <= u_fmrv32im_max10.u_fmrv32im_core.dbus_wdata;
end
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait((u_fmrv32im_max10.u_fmrv32im_core.dbus_addr == 32'h0000_0800) &
(u_fmrv32im_max10.u_fmrv32im_core.dbus_wstb == 4'hF));
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$display("Result: %8x\n", rslt);
$finish();
end
fmrv32im_max10
#(
.MEM_FILE ("../../../../src/imem.mif")
)
u_fmrv32im_max10
(
.CLK48MHZ (CLK),
.led (led)
);
endmodule | 15 |
142,244 | data/full_repos/permissive/98419535/src/tb_MAX10.v | 98,419,535 | tb_MAX10.v | v | 190 | 91 | [] | [] | [] | null | line:17: before: "u_MAX10" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:17: Unsupported: Verilog 1995 force\n force u_MAX10.RST_N = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:19: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:21: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:23: Unsupported: Verilog 1995 force\n force u_MAX10.RST_N = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:46: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:48: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:58: Unsupported: wait statements\n wait(led == 4\'hF);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:60: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:66: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:119: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:122: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:128: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:130: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:132: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:134: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:136: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:138: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:140: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:142: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:144: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:146: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:148: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:150: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:152: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:159: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:161: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:163: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:165: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:167: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:169: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:171: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:173: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:175: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:177: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:183: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,438 | module | module tb_MAX10;
reg sim_end;
reg RST_N;
reg CLK;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_MAX10.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_MAX10.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait(led == 4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$finish();
end
MAX10
u_MAX10
(
.CLK48MHZ (CLK),
.TXD (txd),
.RXD (rxd),
.LED (led)
);
task_uart u_task_uart(
.tx(rxd),
.rx(txd)
);
endmodule | module tb_MAX10; |
reg sim_end;
reg RST_N;
reg CLK;
wire [3:0] led;
initial begin
sim_end = 1'b0;
RST_N = 1'b0;
CLK = 1'b0;
force u_MAX10.RST_N = 1'b0;
#100;
@(posedge CLK);
RST_N = 1'b1;
force u_MAX10.RST_N = 1'b1;
$display("============================================================");
$display("Simulatin Start");
$display("============================================================");
end
localparam CLK100M = 10;
always begin
#(CLK100M/2) CLK <= ~CLK;
end
initial begin
wait(CLK);
@(posedge CLK);
$display("============================================================");
$display("Process Start");
$display("============================================================");
wait(led == 4'hF);
repeat(10) @(posedge CLK);
sim_end = 1;
end
initial begin
wait(sim_end);
$display("============================================================");
$display("Simulatin Finish");
$display("============================================================");
$finish();
end
MAX10
u_MAX10
(
.CLK48MHZ (CLK),
.TXD (txd),
.RXD (rxd),
.LED (led)
);
task_uart u_task_uart(
.tx(rxd),
.rx(txd)
);
endmodule | 15 |
142,245 | data/full_repos/permissive/98419535/src/tb_MAX10.v | 98,419,535 | tb_MAX10.v | v | 190 | 91 | [] | [] | [] | null | line:17: before: "u_MAX10" | null | 1: b'%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:17: Unsupported: Verilog 1995 force\n force u_MAX10.RST_N = 1\'b0;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:19: Unsupported: Ignoring delay on this delayed statement.\n #100;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:21: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:23: Unsupported: Verilog 1995 force\n force u_MAX10.RST_N = 1\'b1;\n ^~~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:32: Unsupported: Ignoring delay on this delayed statement.\n #(CLK100M/2) CLK <= ~CLK;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:46: Unsupported: wait statements\n wait(CLK);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:48: syntax error, unexpected \'@\'\n @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:58: Unsupported: wait statements\n wait(led == 4\'hF);\n ^~~~\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:60: syntax error, unexpected \'@\'\n repeat(10) @(posedge CLK);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:66: Unsupported: wait statements\n wait(sim_end);\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:119: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2) clk <= ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98419535/src/tb_MAX10.v:122: Unsupported: Ignoring delay on this delayed statement.\n #(1000000000/115200/2/2) clk2 <= ~clk2;\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:128: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:130: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:132: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:134: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:136: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:138: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:140: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:142: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:144: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:146: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:148: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:150: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:152: syntax error, unexpected \'@\'\n @(posedge clk);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:159: syntax error, unexpected \'@\'\n @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:161: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:163: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:165: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:167: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:169: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:171: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:173: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:175: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:177: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: data/full_repos/permissive/98419535/src/tb_MAX10.v:183: syntax error, unexpected \'@\'\n repeat (2) @(posedge clk2);\n ^\n%Error: Exiting due to 32 error(s), 4 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,438 | module | module task_uart(
tx,
rx
);
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | module task_uart(
tx,
rx
); |
output tx;
input rx;
reg tx;
reg clk, clk2;
reg [7:0] rdata;
reg rx_valid;
wire [7:0] rx_char;
initial begin
clk <= 1'b0;
clk2 <= 1'b0;
tx <= 1'b1;
end
always begin
#(1000000000/115200/2) clk <= ~clk;
end
always begin
#(1000000000/115200/2/2) clk2 <= ~clk2;
end
task write;
input [7:0] data;
begin
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b0;
@(posedge clk);
tx <= data[0];
@(posedge clk);
tx <= data[1];
@(posedge clk);
tx <= data[2];
@(posedge clk);
tx <= data[3];
@(posedge clk);
tx <= data[4];
@(posedge clk);
tx <= data[5];
@(posedge clk);
tx <= data[6];
@(posedge clk);
tx <= data[7];
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
tx <= 1'b1;
@(posedge clk);
end
endtask
always begin
rx_valid <= 0;
@(posedge clk2);
if(rx == 1'b0) begin
repeat (2) @(posedge clk2);
rdata[0] <= rx;
repeat (2) @(posedge clk2);
rdata[1] <= rx;
repeat (2) @(posedge clk2);
rdata[2] <= rx;
repeat (2) @(posedge clk2);
rdata[3] <= rx;
repeat (2) @(posedge clk2);
rdata[4] <= rx;
repeat (2) @(posedge clk2);
rdata[5] <= rx;
repeat (2) @(posedge clk2);
rdata[6] <= rx;
repeat (2) @(posedge clk2);
rdata[7] <= rx;
repeat (2) @(posedge clk2);
if(rx == 1'b1) begin
rx_valid <= 1;
$write("%s", rdata[7:0]);
end
repeat (2) @(posedge clk2);
end
end
assign rx_char = (rx_valid)?rdata:8'd0;
endmodule | 15 |
Subsets and Splits