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|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
142,246 | data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v | 98,489,923 | system.v | v | 1,494 | 134 | [] | [] | [] | [(3, 1464), (1467, 1493)] | null | null | 1: b"%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:372: Cannot find file containing module: 'mmcm'\n mmcm ip_mmcm\n ^~~~\n ... Looked in:\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm.v\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm.sv\n mmcm\n mmcm.v\n mmcm.sv\n obj_dir/mmcm\n obj_dir/mmcm.v\n obj_dir/mmcm.sv\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:389: Cannot find file containing module: 'reset_sys'\n reset_sys ip_reset_sys\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:409: Cannot find file containing module: 'PULLUP'\n PULLUP qspi_pullup[3:0]\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:414: Cannot find file containing module: 'IOBUF'\n IOBUF qspi_iobuf[3:0]\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:459: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:476: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:493: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:510: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:527: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:544: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:567: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:584: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:601: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:618: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:635: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:652: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:669: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:686: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:705: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:723: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:740: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:757: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:774: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:791: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:808: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:825: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:842: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:859: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:876: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:893: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:910: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:927: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:944: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:964: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:979: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TCK (.O(jd_2));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:982: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:997: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TMS (.O(jd_5));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1000: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1015: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TDI (.O(jd_4));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1018: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1035: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1050: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TRST_n(.O(jd_1));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1054: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_SRST_n(.O(SRST_n));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1134: Cannot find file containing module: 'E300ArtyDevKitTop'\n E300ArtyDevKitTop dut\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1425: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: Exiting due to 45 error(s)\n" | 313,441 | module | module system
(
input wire CLK100MHZ,
input wire ck_rst,
inout wire led_0,
inout wire led_1,
inout wire led_2,
inout wire led_3,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
inout wire sw_0,
inout wire sw_1,
inout wire sw_2,
input wire sw_3,
inout wire btn_0,
inout wire btn_1,
inout wire btn_2,
inout wire btn_3,
output wire qspi_cs,
output wire qspi_sck,
inout wire [3:0] qspi_dq,
output wire uart_rxd_out,
input wire uart_txd_in,
inout wire ja_0,
inout wire ja_1,
inout wire [19:0] ck_io,
inout wire ck_miso,
inout wire ck_mosi,
inout wire ck_ss,
inout wire ck_sck,
inout wire jd_0,
inout wire jd_1,
inout wire jd_2,
inout wire jd_4,
inout wire jd_5,
input wire jd_6
);
wire clk_out1;
wire hfclk;
wire mmcm_locked;
wire reset_core;
wire reset_bus;
wire reset_periph;
wire reset_intcon_n;
wire reset_periph_n;
wire dut_clock;
wire dut_reset;
wire dut_io_pads_jtag_TCK_i_ival;
wire dut_io_pads_jtag_TCK_o_oval;
wire dut_io_pads_jtag_TCK_o_oe;
wire dut_io_pads_jtag_TCK_o_ie;
wire dut_io_pads_jtag_TCK_o_pue;
wire dut_io_pads_jtag_TCK_o_ds;
wire dut_io_pads_jtag_TMS_i_ival;
wire dut_io_pads_jtag_TMS_o_oval;
wire dut_io_pads_jtag_TMS_o_oe;
wire dut_io_pads_jtag_TMS_o_ie;
wire dut_io_pads_jtag_TMS_o_pue;
wire dut_io_pads_jtag_TMS_o_ds;
wire dut_io_pads_jtag_TDI_i_ival;
wire dut_io_pads_jtag_TDI_o_oval;
wire dut_io_pads_jtag_TDI_o_oe;
wire dut_io_pads_jtag_TDI_o_ie;
wire dut_io_pads_jtag_TDI_o_pue;
wire dut_io_pads_jtag_TDI_o_ds;
wire dut_io_pads_jtag_TDO_i_ival;
wire dut_io_pads_jtag_TDO_o_oval;
wire dut_io_pads_jtag_TDO_o_oe;
wire dut_io_pads_jtag_TDO_o_ie;
wire dut_io_pads_jtag_TDO_o_pue;
wire dut_io_pads_jtag_TDO_o_ds;
wire dut_io_pads_jtag_TRST_n_i_ival;
wire dut_io_pads_jtag_TRST_n_o_oval;
wire dut_io_pads_jtag_TRST_n_o_oe;
wire dut_io_pads_jtag_TRST_n_o_ie;
wire dut_io_pads_jtag_TRST_n_o_pue;
wire dut_io_pads_jtag_TRST_n_o_ds;
wire dut_io_pads_gpio_0_i_ival;
wire dut_io_pads_gpio_0_o_oval;
wire dut_io_pads_gpio_0_o_oe;
wire dut_io_pads_gpio_0_o_ie;
wire dut_io_pads_gpio_0_o_pue;
wire dut_io_pads_gpio_0_o_ds;
wire dut_io_pads_gpio_1_i_ival;
wire dut_io_pads_gpio_1_o_oval;
wire dut_io_pads_gpio_1_o_oe;
wire dut_io_pads_gpio_1_o_ie;
wire dut_io_pads_gpio_1_o_pue;
wire dut_io_pads_gpio_1_o_ds;
wire dut_io_pads_gpio_2_i_ival;
wire dut_io_pads_gpio_2_o_oval;
wire dut_io_pads_gpio_2_o_oe;
wire dut_io_pads_gpio_2_o_ie;
wire dut_io_pads_gpio_2_o_pue;
wire dut_io_pads_gpio_2_o_ds;
wire dut_io_pads_gpio_3_i_ival;
wire dut_io_pads_gpio_3_o_oval;
wire dut_io_pads_gpio_3_o_oe;
wire dut_io_pads_gpio_3_o_ie;
wire dut_io_pads_gpio_3_o_pue;
wire dut_io_pads_gpio_3_o_ds;
wire dut_io_pads_gpio_4_i_ival;
wire dut_io_pads_gpio_4_o_oval;
wire dut_io_pads_gpio_4_o_oe;
wire dut_io_pads_gpio_4_o_ie;
wire dut_io_pads_gpio_4_o_pue;
wire dut_io_pads_gpio_4_o_ds;
wire dut_io_pads_gpio_5_i_ival;
wire dut_io_pads_gpio_5_o_oval;
wire dut_io_pads_gpio_5_o_oe;
wire dut_io_pads_gpio_5_o_ie;
wire dut_io_pads_gpio_5_o_pue;
wire dut_io_pads_gpio_5_o_ds;
wire dut_io_pads_gpio_6_i_ival;
wire dut_io_pads_gpio_6_o_oval;
wire dut_io_pads_gpio_6_o_oe;
wire dut_io_pads_gpio_6_o_ie;
wire dut_io_pads_gpio_6_o_pue;
wire dut_io_pads_gpio_6_o_ds;
wire dut_io_pads_gpio_7_i_ival;
wire dut_io_pads_gpio_7_o_oval;
wire dut_io_pads_gpio_7_o_oe;
wire dut_io_pads_gpio_7_o_ie;
wire dut_io_pads_gpio_7_o_pue;
wire dut_io_pads_gpio_7_o_ds;
wire dut_io_pads_gpio_8_i_ival;
wire dut_io_pads_gpio_8_o_oval;
wire dut_io_pads_gpio_8_o_oe;
wire dut_io_pads_gpio_8_o_ie;
wire dut_io_pads_gpio_8_o_pue;
wire dut_io_pads_gpio_8_o_ds;
wire dut_io_pads_gpio_9_i_ival;
wire dut_io_pads_gpio_9_o_oval;
wire dut_io_pads_gpio_9_o_oe;
wire dut_io_pads_gpio_9_o_ie;
wire dut_io_pads_gpio_9_o_pue;
wire dut_io_pads_gpio_9_o_ds;
wire dut_io_pads_gpio_10_i_ival;
wire dut_io_pads_gpio_10_o_oval;
wire dut_io_pads_gpio_10_o_oe;
wire dut_io_pads_gpio_10_o_ie;
wire dut_io_pads_gpio_10_o_pue;
wire dut_io_pads_gpio_10_o_ds;
wire dut_io_pads_gpio_11_i_ival;
wire dut_io_pads_gpio_11_o_oval;
wire dut_io_pads_gpio_11_o_oe;
wire dut_io_pads_gpio_11_o_ie;
wire dut_io_pads_gpio_11_o_pue;
wire dut_io_pads_gpio_11_o_ds;
wire dut_io_pads_gpio_12_i_ival;
wire dut_io_pads_gpio_12_o_oval;
wire dut_io_pads_gpio_12_o_oe;
wire dut_io_pads_gpio_12_o_ie;
wire dut_io_pads_gpio_12_o_pue;
wire dut_io_pads_gpio_12_o_ds;
wire dut_io_pads_gpio_13_i_ival;
wire dut_io_pads_gpio_13_o_oval;
wire dut_io_pads_gpio_13_o_oe;
wire dut_io_pads_gpio_13_o_ie;
wire dut_io_pads_gpio_13_o_pue;
wire dut_io_pads_gpio_13_o_ds;
wire dut_io_pads_gpio_14_i_ival;
wire dut_io_pads_gpio_14_o_oval;
wire dut_io_pads_gpio_14_o_oe;
wire dut_io_pads_gpio_14_o_ie;
wire dut_io_pads_gpio_14_o_pue;
wire dut_io_pads_gpio_14_o_ds;
wire dut_io_pads_gpio_15_i_ival;
wire dut_io_pads_gpio_15_o_oval;
wire dut_io_pads_gpio_15_o_oe;
wire dut_io_pads_gpio_15_o_ie;
wire dut_io_pads_gpio_15_o_pue;
wire dut_io_pads_gpio_15_o_ds;
wire dut_io_pads_gpio_16_i_ival;
wire dut_io_pads_gpio_16_o_oval;
wire dut_io_pads_gpio_16_o_oe;
wire dut_io_pads_gpio_16_o_ie;
wire dut_io_pads_gpio_16_o_pue;
wire dut_io_pads_gpio_16_o_ds;
wire dut_io_pads_gpio_17_i_ival;
wire dut_io_pads_gpio_17_o_oval;
wire dut_io_pads_gpio_17_o_oe;
wire dut_io_pads_gpio_17_o_ie;
wire dut_io_pads_gpio_17_o_pue;
wire dut_io_pads_gpio_17_o_ds;
wire dut_io_pads_gpio_18_i_ival;
wire dut_io_pads_gpio_18_o_oval;
wire dut_io_pads_gpio_18_o_oe;
wire dut_io_pads_gpio_18_o_ie;
wire dut_io_pads_gpio_18_o_pue;
wire dut_io_pads_gpio_18_o_ds;
wire dut_io_pads_gpio_19_i_ival;
wire dut_io_pads_gpio_19_o_oval;
wire dut_io_pads_gpio_19_o_oe;
wire dut_io_pads_gpio_19_o_ie;
wire dut_io_pads_gpio_19_o_pue;
wire dut_io_pads_gpio_19_o_ds;
wire dut_io_pads_gpio_20_i_ival;
wire dut_io_pads_gpio_20_o_oval;
wire dut_io_pads_gpio_20_o_oe;
wire dut_io_pads_gpio_20_o_ie;
wire dut_io_pads_gpio_20_o_pue;
wire dut_io_pads_gpio_20_o_ds;
wire dut_io_pads_gpio_21_i_ival;
wire dut_io_pads_gpio_21_o_oval;
wire dut_io_pads_gpio_21_o_oe;
wire dut_io_pads_gpio_21_o_ie;
wire dut_io_pads_gpio_21_o_pue;
wire dut_io_pads_gpio_21_o_ds;
wire dut_io_pads_gpio_22_i_ival;
wire dut_io_pads_gpio_22_o_oval;
wire dut_io_pads_gpio_22_o_oe;
wire dut_io_pads_gpio_22_o_ie;
wire dut_io_pads_gpio_22_o_pue;
wire dut_io_pads_gpio_22_o_ds;
wire dut_io_pads_gpio_23_i_ival;
wire dut_io_pads_gpio_23_o_oval;
wire dut_io_pads_gpio_23_o_oe;
wire dut_io_pads_gpio_23_o_ie;
wire dut_io_pads_gpio_23_o_pue;
wire dut_io_pads_gpio_23_o_ds;
wire dut_io_pads_gpio_24_i_ival;
wire dut_io_pads_gpio_24_o_oval;
wire dut_io_pads_gpio_24_o_oe;
wire dut_io_pads_gpio_24_o_ie;
wire dut_io_pads_gpio_24_o_pue;
wire dut_io_pads_gpio_24_o_ds;
wire dut_io_pads_gpio_25_i_ival;
wire dut_io_pads_gpio_25_o_oval;
wire dut_io_pads_gpio_25_o_oe;
wire dut_io_pads_gpio_25_o_ie;
wire dut_io_pads_gpio_25_o_pue;
wire dut_io_pads_gpio_25_o_ds;
wire dut_io_pads_gpio_26_i_ival;
wire dut_io_pads_gpio_26_o_oval;
wire dut_io_pads_gpio_26_o_oe;
wire dut_io_pads_gpio_26_o_ie;
wire dut_io_pads_gpio_26_o_pue;
wire dut_io_pads_gpio_26_o_ds;
wire dut_io_pads_gpio_27_i_ival;
wire dut_io_pads_gpio_27_o_oval;
wire dut_io_pads_gpio_27_o_oe;
wire dut_io_pads_gpio_27_o_ie;
wire dut_io_pads_gpio_27_o_pue;
wire dut_io_pads_gpio_27_o_ds;
wire dut_io_pads_gpio_28_i_ival;
wire dut_io_pads_gpio_28_o_oval;
wire dut_io_pads_gpio_28_o_oe;
wire dut_io_pads_gpio_28_o_ie;
wire dut_io_pads_gpio_28_o_pue;
wire dut_io_pads_gpio_28_o_ds;
wire dut_io_pads_gpio_29_i_ival;
wire dut_io_pads_gpio_29_o_oval;
wire dut_io_pads_gpio_29_o_oe;
wire dut_io_pads_gpio_29_o_ie;
wire dut_io_pads_gpio_29_o_pue;
wire dut_io_pads_gpio_29_o_ds;
wire dut_io_pads_gpio_30_i_ival;
wire dut_io_pads_gpio_30_o_oval;
wire dut_io_pads_gpio_30_o_oe;
wire dut_io_pads_gpio_30_o_ie;
wire dut_io_pads_gpio_30_o_pue;
wire dut_io_pads_gpio_30_o_ds;
wire dut_io_pads_gpio_31_i_ival;
wire dut_io_pads_gpio_31_o_oval;
wire dut_io_pads_gpio_31_o_oe;
wire dut_io_pads_gpio_31_o_ie;
wire dut_io_pads_gpio_31_o_pue;
wire dut_io_pads_gpio_31_o_ds;
wire dut_io_pads_qspi_sck_i_ival;
wire dut_io_pads_qspi_sck_o_oval;
wire dut_io_pads_qspi_sck_o_oe;
wire dut_io_pads_qspi_sck_o_ie;
wire dut_io_pads_qspi_sck_o_pue;
wire dut_io_pads_qspi_sck_o_ds;
wire dut_io_pads_qspi_dq_0_i_ival;
wire dut_io_pads_qspi_dq_0_o_oval;
wire dut_io_pads_qspi_dq_0_o_oe;
wire dut_io_pads_qspi_dq_0_o_ie;
wire dut_io_pads_qspi_dq_0_o_pue;
wire dut_io_pads_qspi_dq_0_o_ds;
wire dut_io_pads_qspi_dq_1_i_ival;
wire dut_io_pads_qspi_dq_1_o_oval;
wire dut_io_pads_qspi_dq_1_o_oe;
wire dut_io_pads_qspi_dq_1_o_ie;
wire dut_io_pads_qspi_dq_1_o_pue;
wire dut_io_pads_qspi_dq_1_o_ds;
wire dut_io_pads_qspi_dq_2_i_ival;
wire dut_io_pads_qspi_dq_2_o_oval;
wire dut_io_pads_qspi_dq_2_o_oe;
wire dut_io_pads_qspi_dq_2_o_ie;
wire dut_io_pads_qspi_dq_2_o_pue;
wire dut_io_pads_qspi_dq_2_o_ds;
wire dut_io_pads_qspi_dq_3_i_ival;
wire dut_io_pads_qspi_dq_3_o_oval;
wire dut_io_pads_qspi_dq_3_o_oe;
wire dut_io_pads_qspi_dq_3_o_ie;
wire dut_io_pads_qspi_dq_3_o_pue;
wire dut_io_pads_qspi_dq_3_o_ds;
wire dut_io_pads_qspi_cs_0_i_ival;
wire dut_io_pads_qspi_cs_0_o_oval;
wire dut_io_pads_qspi_cs_0_o_oe;
wire dut_io_pads_qspi_cs_0_o_ie;
wire dut_io_pads_qspi_cs_0_o_pue;
wire dut_io_pads_qspi_cs_0_o_ds;
wire dut_io_pads_aon_erst_n_i_ival;
wire dut_io_pads_aon_erst_n_o_oval;
wire dut_io_pads_aon_erst_n_o_oe;
wire dut_io_pads_aon_erst_n_o_ie;
wire dut_io_pads_aon_erst_n_o_pue;
wire dut_io_pads_aon_erst_n_o_ds;
wire dut_io_pads_aon_lfextclk_i_ival;
wire dut_io_pads_aon_lfextclk_o_oval;
wire dut_io_pads_aon_lfextclk_o_oe;
wire dut_io_pads_aon_lfextclk_o_ie;
wire dut_io_pads_aon_lfextclk_o_pue;
wire dut_io_pads_aon_lfextclk_o_ds;
wire dut_io_pads_aon_pmu_dwakeup_n_i_ival;
wire dut_io_pads_aon_pmu_dwakeup_n_o_oval;
wire dut_io_pads_aon_pmu_dwakeup_n_o_oe;
wire dut_io_pads_aon_pmu_dwakeup_n_o_ie;
wire dut_io_pads_aon_pmu_dwakeup_n_o_pue;
wire dut_io_pads_aon_pmu_dwakeup_n_o_ds;
wire dut_io_pads_aon_pmu_vddpaden_i_ival;
wire dut_io_pads_aon_pmu_vddpaden_o_oval;
wire dut_io_pads_aon_pmu_vddpaden_o_oe;
wire dut_io_pads_aon_pmu_vddpaden_o_ie;
wire dut_io_pads_aon_pmu_vddpaden_o_pue;
wire dut_io_pads_aon_pmu_vddpaden_o_ds;
wire SRST_n;
mmcm ip_mmcm
(
.clk_in1(CLK100MHZ),
.clk_out1(clk_out1),
.clk_out2(hfclk),
.resetn(ck_rst),
.locked(mmcm_locked)
);
wire slowclk;
clkdivider slowclkgen
(
.clk(clk_out1),
.reset(~mmcm_locked),
.clk_out(slowclk)
);
reset_sys ip_reset_sys
(
.slowest_sync_clk(clk_out1),
.ext_reset_in(ck_rst & SRST_n),
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(mmcm_locked),
.mb_reset(reset_core),
.bus_struct_reset(reset_bus),
.peripheral_reset(reset_periph),
.interconnect_aresetn(reset_intcon_n),
.peripheral_aresetn(reset_periph_n)
);
wire [3:0] qspi_ui_dq_o, qspi_ui_dq_oe;
wire [3:0] qspi_ui_dq_i;
PULLUP qspi_pullup[3:0]
(
.O(qspi_dq)
);
IOBUF qspi_iobuf[3:0]
(
.IO(qspi_dq),
.O(qspi_ui_dq_i),
.I(qspi_ui_dq_o),
.T(~qspi_ui_dq_oe)
);
wire gpio_0;
wire gpio_1;
wire gpio_2;
wire gpio_3;
wire gpio_4;
wire gpio_5;
wire gpio_6;
wire gpio_7;
wire gpio_8;
wire gpio_9;
wire gpio_10;
wire gpio_11;
wire gpio_12;
wire gpio_13;
wire gpio_14;
wire gpio_15;
wire gpio_16;
wire gpio_17;
wire gpio_18;
wire gpio_19;
wire gpio_20;
wire gpio_21;
wire gpio_22;
wire gpio_23;
wire gpio_24;
wire gpio_25;
wire gpio_26;
wire gpio_27;
wire gpio_28;
wire gpio_29;
wire gpio_30;
wire gpio_31;
wire iobuf_gpio_0_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_0
(
.O(iobuf_gpio_0_o),
.IO(gpio_0),
.I(dut_io_pads_gpio_0_o_oval),
.T(~dut_io_pads_gpio_0_o_oe)
);
assign dut_io_pads_gpio_0_i_ival = iobuf_gpio_0_o & dut_io_pads_gpio_0_o_ie;
wire iobuf_gpio_1_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_1
(
.O(iobuf_gpio_1_o),
.IO(gpio_1),
.I(dut_io_pads_gpio_1_o_oval),
.T(~dut_io_pads_gpio_1_o_oe)
);
assign dut_io_pads_gpio_1_i_ival = iobuf_gpio_1_o & dut_io_pads_gpio_1_o_ie;
wire iobuf_gpio_2_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_2
(
.O(iobuf_gpio_2_o),
.IO(gpio_2),
.I(dut_io_pads_gpio_2_o_oval),
.T(~dut_io_pads_gpio_2_o_oe)
);
assign dut_io_pads_gpio_2_i_ival = iobuf_gpio_2_o & dut_io_pads_gpio_2_o_ie;
wire iobuf_gpio_3_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_3
(
.O(iobuf_gpio_3_o),
.IO(gpio_3),
.I(dut_io_pads_gpio_3_o_oval),
.T(~dut_io_pads_gpio_3_o_oe)
);
assign dut_io_pads_gpio_3_i_ival = iobuf_gpio_3_o & dut_io_pads_gpio_3_o_ie;
wire iobuf_gpio_4_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_4
(
.O(iobuf_gpio_4_o),
.IO(gpio_4),
.I(dut_io_pads_gpio_4_o_oval),
.T(~dut_io_pads_gpio_4_o_oe)
);
assign dut_io_pads_gpio_4_i_ival = iobuf_gpio_4_o & dut_io_pads_gpio_4_o_ie;
wire iobuf_gpio_5_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_5
(
.O(iobuf_gpio_5_o),
.IO(gpio_5),
.I(dut_io_pads_gpio_5_o_oval),
.T(~dut_io_pads_gpio_5_o_oe)
);
assign dut_io_pads_gpio_5_i_ival = iobuf_gpio_5_o & dut_io_pads_gpio_5_o_ie;
assign dut_io_pads_gpio_6_i_ival = 1'b0;
assign dut_io_pads_gpio_7_i_ival = 1'b0;
assign dut_io_pads_gpio_8_i_ival = 1'b0;
wire iobuf_gpio_9_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_9
(
.O(iobuf_gpio_9_o),
.IO(gpio_9),
.I(dut_io_pads_gpio_9_o_oval),
.T(~dut_io_pads_gpio_9_o_oe)
);
assign dut_io_pads_gpio_9_i_ival = iobuf_gpio_9_o & dut_io_pads_gpio_9_o_ie;
wire iobuf_gpio_10_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_10
(
.O(iobuf_gpio_10_o),
.IO(gpio_10),
.I(dut_io_pads_gpio_10_o_oval),
.T(~dut_io_pads_gpio_10_o_oe)
);
assign dut_io_pads_gpio_10_i_ival = iobuf_gpio_10_o & dut_io_pads_gpio_10_o_ie;
wire iobuf_gpio_11_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_11
(
.O(iobuf_gpio_11_o),
.IO(gpio_11),
.I(dut_io_pads_gpio_11_o_oval),
.T(~dut_io_pads_gpio_11_o_oe)
);
assign dut_io_pads_gpio_11_i_ival = iobuf_gpio_11_o & dut_io_pads_gpio_11_o_ie;
wire iobuf_gpio_12_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_12
(
.O(iobuf_gpio_12_o),
.IO(gpio_12),
.I(dut_io_pads_gpio_12_o_oval),
.T(~dut_io_pads_gpio_12_o_oe)
);
assign dut_io_pads_gpio_12_i_ival = iobuf_gpio_12_o & dut_io_pads_gpio_12_o_ie;
wire iobuf_gpio_13_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_13
(
.O(iobuf_gpio_13_o),
.IO(gpio_13),
.I(dut_io_pads_gpio_13_o_oval),
.T(~dut_io_pads_gpio_13_o_oe)
);
assign dut_io_pads_gpio_13_i_ival = iobuf_gpio_13_o & dut_io_pads_gpio_13_o_ie;
wire iobuf_gpio_14_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_14
(
.O(iobuf_gpio_14_o),
.IO(gpio_14),
.I(dut_io_pads_gpio_14_o_oval),
.T(~dut_io_pads_gpio_14_o_oe)
);
assign dut_io_pads_gpio_14_i_ival = iobuf_gpio_14_o & dut_io_pads_gpio_14_o_ie;
wire iobuf_gpio_15_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_15
(
.O(iobuf_gpio_15_o),
.IO(gpio_15),
.I(dut_io_pads_gpio_15_o_oval),
.T(~dut_io_pads_gpio_15_o_oe)
);
assign dut_io_pads_gpio_15_i_ival = iobuf_gpio_15_o & dut_io_pads_gpio_15_o_ie;
wire iobuf_gpio_16_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_16
(
.O(iobuf_gpio_16_o),
.IO(gpio_16),
.I(dut_io_pads_gpio_16_o_oval),
.T(~dut_io_pads_gpio_16_o_oe)
);
assign dut_io_pads_gpio_16_i_ival = sw_3 ? (iobuf_gpio_16_o & dut_io_pads_gpio_16_o_ie) : (uart_txd_in & dut_io_pads_gpio_16_o_ie);
wire iobuf_gpio_17_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_17
(
.O(iobuf_gpio_17_o),
.IO(gpio_17),
.I(dut_io_pads_gpio_17_o_oval),
.T(~dut_io_pads_gpio_17_o_oe)
);
assign dut_io_pads_gpio_17_i_ival = iobuf_gpio_17_o & dut_io_pads_gpio_17_o_ie;
assign uart_rxd_out = (dut_io_pads_gpio_17_o_oval & dut_io_pads_gpio_17_o_oe);
wire iobuf_gpio_18_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_18
(
.O(iobuf_gpio_18_o),
.IO(gpio_18),
.I(dut_io_pads_gpio_18_o_oval),
.T(~dut_io_pads_gpio_18_o_oe)
);
assign dut_io_pads_gpio_18_i_ival = iobuf_gpio_18_o & dut_io_pads_gpio_18_o_ie;
wire iobuf_gpio_19_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_19
(
.O(iobuf_gpio_19_o),
.IO(gpio_19),
.I(dut_io_pads_gpio_19_o_oval),
.T(~dut_io_pads_gpio_19_o_oe)
);
assign dut_io_pads_gpio_19_i_ival = iobuf_gpio_19_o & dut_io_pads_gpio_19_o_ie;
wire iobuf_gpio_20_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_20
(
.O(iobuf_gpio_20_o),
.IO(gpio_20),
.I(dut_io_pads_gpio_20_o_oval),
.T(~dut_io_pads_gpio_20_o_oe)
);
assign dut_io_pads_gpio_20_i_ival = iobuf_gpio_20_o & dut_io_pads_gpio_20_o_ie;
wire iobuf_gpio_21_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_21
(
.O(iobuf_gpio_21_o),
.IO(gpio_21),
.I(dut_io_pads_gpio_21_o_oval),
.T(~dut_io_pads_gpio_21_o_oe)
);
assign dut_io_pads_gpio_21_i_ival = iobuf_gpio_21_o & dut_io_pads_gpio_21_o_ie;
wire iobuf_gpio_22_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_22
(
.O(iobuf_gpio_22_o),
.IO(gpio_22),
.I(dut_io_pads_gpio_22_o_oval),
.T(~dut_io_pads_gpio_22_o_oe)
);
assign dut_io_pads_gpio_22_i_ival = iobuf_gpio_22_o & dut_io_pads_gpio_22_o_ie;
wire iobuf_gpio_23_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_23
(
.O(iobuf_gpio_23_o),
.IO(gpio_23),
.I(dut_io_pads_gpio_23_o_oval),
.T(~dut_io_pads_gpio_23_o_oe)
);
assign dut_io_pads_gpio_23_i_ival = iobuf_gpio_23_o & dut_io_pads_gpio_23_o_ie;
wire iobuf_gpio_24_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_24
(
.O(iobuf_gpio_24_o),
.IO(gpio_24),
.I(dut_io_pads_gpio_24_o_oval),
.T(~dut_io_pads_gpio_24_o_oe)
);
assign dut_io_pads_gpio_24_i_ival = iobuf_gpio_24_o & dut_io_pads_gpio_24_o_ie;
wire iobuf_gpio_25_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_25
(
.O(iobuf_gpio_25_o),
.IO(gpio_25),
.I(dut_io_pads_gpio_25_o_oval),
.T(~dut_io_pads_gpio_25_o_oe)
);
assign dut_io_pads_gpio_25_i_ival = iobuf_gpio_25_o & dut_io_pads_gpio_25_o_ie;
wire iobuf_gpio_26_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_26
(
.O(iobuf_gpio_26_o),
.IO(gpio_26),
.I(dut_io_pads_gpio_26_o_oval),
.T(~dut_io_pads_gpio_26_o_oe)
);
assign dut_io_pads_gpio_26_i_ival = iobuf_gpio_26_o & dut_io_pads_gpio_26_o_ie;
wire iobuf_gpio_27_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_27
(
.O(iobuf_gpio_27_o),
.IO(gpio_27),
.I(dut_io_pads_gpio_27_o_oval),
.T(~dut_io_pads_gpio_27_o_oe)
);
assign dut_io_pads_gpio_27_i_ival = iobuf_gpio_27_o & dut_io_pads_gpio_27_o_ie;
wire iobuf_gpio_28_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_28
(
.O(iobuf_gpio_28_o),
.IO(gpio_28),
.I(dut_io_pads_gpio_28_o_oval),
.T(~dut_io_pads_gpio_28_o_oe)
);
assign dut_io_pads_gpio_28_i_ival = iobuf_gpio_28_o & dut_io_pads_gpio_28_o_ie;
wire iobuf_gpio_29_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_29
(
.O(iobuf_gpio_29_o),
.IO(gpio_29),
.I(dut_io_pads_gpio_29_o_oval),
.T(~dut_io_pads_gpio_29_o_oe)
);
assign dut_io_pads_gpio_29_i_ival = iobuf_gpio_29_o & dut_io_pads_gpio_29_o_ie;
wire iobuf_gpio_30_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_30
(
.O(iobuf_gpio_30_o),
.IO(gpio_30),
.I(dut_io_pads_gpio_30_o_oval),
.T(~dut_io_pads_gpio_30_o_oe)
);
assign dut_io_pads_gpio_30_i_ival = iobuf_gpio_30_o & dut_io_pads_gpio_30_o_ie;
wire iobuf_gpio_31_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_31
(
.O(iobuf_gpio_31_o),
.IO(gpio_31),
.I(dut_io_pads_gpio_31_o_oval),
.T(~dut_io_pads_gpio_31_o_oe)
);
assign dut_io_pads_gpio_31_i_ival = iobuf_gpio_31_o & dut_io_pads_gpio_31_o_ie;
wire iobuf_jtag_TCK_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TCK
(
.O(iobuf_jtag_TCK_o),
.IO(jd_2),
.I(dut_io_pads_jtag_TCK_o_oval),
.T(~dut_io_pads_jtag_TCK_o_oe)
);
assign dut_io_pads_jtag_TCK_i_ival = iobuf_jtag_TCK_o & dut_io_pads_jtag_TCK_o_ie;
PULLUP pullup_TCK (.O(jd_2));
wire iobuf_jtag_TMS_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TMS
(
.O(iobuf_jtag_TMS_o),
.IO(jd_5),
.I(dut_io_pads_jtag_TMS_o_oval),
.T(~dut_io_pads_jtag_TMS_o_oe)
);
assign dut_io_pads_jtag_TMS_i_ival = iobuf_jtag_TMS_o & dut_io_pads_jtag_TMS_o_ie;
PULLUP pullup_TMS (.O(jd_5));
wire iobuf_jtag_TDI_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDI
(
.O(iobuf_jtag_TDI_o),
.IO(jd_4),
.I(dut_io_pads_jtag_TDI_o_oval),
.T(~dut_io_pads_jtag_TDI_o_oe)
);
assign dut_io_pads_jtag_TDI_i_ival = iobuf_jtag_TDI_o & dut_io_pads_jtag_TDI_o_ie;
PULLUP pullup_TDI (.O(jd_4));
wire iobuf_jtag_TDO_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDO
(
.O(iobuf_jtag_TDO_o),
.IO(jd_0),
.I(dut_io_pads_jtag_TDO_o_oval),
.T(~dut_io_pads_jtag_TDO_o_oe)
);
assign dut_io_pads_jtag_TDO_i_ival = iobuf_jtag_TDO_o & dut_io_pads_jtag_TDO_o_ie;
wire iobuf_jtag_TRST_n_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TRST_n
(
.O(iobuf_jtag_TRST_n_o),
.IO(jd_1),
.I(dut_io_pads_jtag_TRST_n_o_oval),
.T(~dut_io_pads_jtag_TRST_n_o_oe)
);
assign dut_io_pads_jtag_TRST_n_i_ival = iobuf_jtag_TRST_n_o & dut_io_pads_jtag_TRST_n_o_ie;
PULLUP pullup_TRST_n(.O(jd_1));
assign SRST_n = jd_6;
PULLUP pullup_SRST_n(.O(SRST_n));
assign ck_io[0] = gpio_16;
assign ck_io[1] = gpio_17;
assign ck_io[2] = gpio_18;
assign ck_io[3] = gpio_19;
assign ck_io[4] = gpio_20;
assign ck_io[5] = gpio_21;
assign ck_io[6] = gpio_22;
assign ck_io[7] = gpio_23;
assign ck_io[8] = gpio_0;
assign ck_io[9] = gpio_1;
assign ck_io[10] = gpio_2;
assign ck_io[11] = gpio_3;
assign ck_io[12] = gpio_4;
assign ck_io[13] = gpio_5;
assign ck_io[14] = uart_txd_in;
assign ck_io[15] = gpio_9;
assign ck_io[16] = gpio_10;
assign ck_io[17] = gpio_11;
assign ck_io[18] = gpio_12;
assign ck_io[19] = gpio_13;
assign led0_r = dut_io_pads_gpio_1_o_oval & dut_io_pads_gpio_1_o_oe;
assign led0_g = dut_io_pads_gpio_2_o_oval & dut_io_pads_gpio_2_o_oe;
assign led0_b = dut_io_pads_gpio_3_o_oval & dut_io_pads_gpio_2_o_oe;
assign led1_r = dut_io_pads_gpio_19_o_oval & dut_io_pads_gpio_19_o_oe;
assign led1_g = dut_io_pads_gpio_21_o_oval & dut_io_pads_gpio_21_o_oe;
assign led1_b = dut_io_pads_gpio_22_o_oval & dut_io_pads_gpio_22_o_oe;
assign led2_r = dut_io_pads_gpio_11_o_oval & dut_io_pads_gpio_11_o_oe;
assign led2_g = dut_io_pads_gpio_12_o_oval & dut_io_pads_gpio_12_o_oe;
assign led2_b = dut_io_pads_gpio_13_o_oval & dut_io_pads_gpio_13_o_oe;
assign btn_0 = gpio_15;
assign btn_1 = gpio_30;
assign btn_2 = gpio_31;
assign ja_0 = gpio_25;
assign ja_1 = gpio_24;
assign ck_ss = gpio_26;
assign ck_mosi = gpio_27;
assign ck_miso = gpio_28;
assign ck_sck = gpio_29;
assign led_0 = ck_rst;
assign led_1 = SRST_n;
assign led_2 = dut_io_pads_aon_pmu_dwakeup_n_i_ival;
assign led_3 = gpio_14;
E300ArtyDevKitTop dut
(
.clock(hfclk),
.reset(1'b1),
.io_pads_jtag_TCK_i_ival(dut_io_pads_jtag_TCK_i_ival),
.io_pads_jtag_TCK_o_oval(dut_io_pads_jtag_TCK_o_oval),
.io_pads_jtag_TCK_o_oe(dut_io_pads_jtag_TCK_o_oe),
.io_pads_jtag_TCK_o_ie(dut_io_pads_jtag_TCK_o_ie),
.io_pads_jtag_TCK_o_pue(dut_io_pads_jtag_TCK_o_pue),
.io_pads_jtag_TCK_o_ds(dut_io_pads_jtag_TCK_o_ds),
.io_pads_jtag_TMS_i_ival(dut_io_pads_jtag_TMS_i_ival),
.io_pads_jtag_TMS_o_oval(dut_io_pads_jtag_TMS_o_oval),
.io_pads_jtag_TMS_o_oe(dut_io_pads_jtag_TMS_o_oe),
.io_pads_jtag_TMS_o_ie(dut_io_pads_jtag_TMS_o_ie),
.io_pads_jtag_TMS_o_pue(dut_io_pads_jtag_TMS_o_pue),
.io_pads_jtag_TMS_o_ds(dut_io_pads_jtag_TMS_o_ds),
.io_pads_jtag_TDI_i_ival(dut_io_pads_jtag_TDI_i_ival),
.io_pads_jtag_TDI_o_oval(dut_io_pads_jtag_TDI_o_oval),
.io_pads_jtag_TDI_o_oe(dut_io_pads_jtag_TDI_o_oe),
.io_pads_jtag_TDI_o_ie(dut_io_pads_jtag_TDI_o_ie),
.io_pads_jtag_TDI_o_pue(dut_io_pads_jtag_TDI_o_pue),
.io_pads_jtag_TDI_o_ds(dut_io_pads_jtag_TDI_o_ds),
.io_pads_jtag_TDO_i_ival(dut_io_pads_jtag_TDO_i_ival),
.io_pads_jtag_TDO_o_oval(dut_io_pads_jtag_TDO_o_oval),
.io_pads_jtag_TDO_o_oe(dut_io_pads_jtag_TDO_o_oe),
.io_pads_jtag_TDO_o_ie(dut_io_pads_jtag_TDO_o_ie),
.io_pads_jtag_TDO_o_pue(dut_io_pads_jtag_TDO_o_pue),
.io_pads_jtag_TDO_o_ds(dut_io_pads_jtag_TDO_o_ds),
.io_pads_jtag_TRST_n_i_ival(dut_io_pads_jtag_TRST_n_i_ival),
.io_pads_jtag_TRST_n_o_oval(dut_io_pads_jtag_TRST_n_o_oval),
.io_pads_jtag_TRST_n_o_oe(dut_io_pads_jtag_TRST_n_o_oe),
.io_pads_jtag_TRST_n_o_ie(dut_io_pads_jtag_TRST_n_o_ie),
.io_pads_jtag_TRST_n_o_pue(dut_io_pads_jtag_TRST_n_o_pue),
.io_pads_jtag_TRST_n_o_ds(dut_io_pads_jtag_TRST_n_o_ds),
.io_pads_gpio_0_i_ival(dut_io_pads_gpio_0_i_ival),
.io_pads_gpio_0_o_oval(dut_io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe(dut_io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie(dut_io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue(dut_io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds(dut_io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival(dut_io_pads_gpio_1_i_ival),
.io_pads_gpio_1_o_oval(dut_io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe(dut_io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie(dut_io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue(dut_io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds(dut_io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival(dut_io_pads_gpio_2_i_ival),
.io_pads_gpio_2_o_oval(dut_io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe(dut_io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie(dut_io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue(dut_io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds(dut_io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival(dut_io_pads_gpio_3_i_ival),
.io_pads_gpio_3_o_oval(dut_io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe(dut_io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie(dut_io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue(dut_io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds(dut_io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival(dut_io_pads_gpio_4_i_ival),
.io_pads_gpio_4_o_oval(dut_io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe(dut_io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie(dut_io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue(dut_io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds(dut_io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival(dut_io_pads_gpio_5_i_ival),
.io_pads_gpio_5_o_oval(dut_io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe(dut_io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie(dut_io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue(dut_io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds(dut_io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival(dut_io_pads_gpio_6_i_ival),
.io_pads_gpio_6_o_oval(dut_io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe(dut_io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie(dut_io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue(dut_io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds(dut_io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival(dut_io_pads_gpio_7_i_ival),
.io_pads_gpio_7_o_oval(dut_io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe(dut_io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie(dut_io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue(dut_io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds(dut_io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival(dut_io_pads_gpio_8_i_ival),
.io_pads_gpio_8_o_oval(dut_io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe(dut_io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie(dut_io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue(dut_io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds(dut_io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival(dut_io_pads_gpio_9_i_ival),
.io_pads_gpio_9_o_oval(dut_io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe(dut_io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie(dut_io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue(dut_io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds(dut_io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival(dut_io_pads_gpio_10_i_ival),
.io_pads_gpio_10_o_oval(dut_io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe(dut_io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie(dut_io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue(dut_io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds(dut_io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival(dut_io_pads_gpio_11_i_ival),
.io_pads_gpio_11_o_oval(dut_io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe(dut_io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie(dut_io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue(dut_io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds(dut_io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival(dut_io_pads_gpio_12_i_ival),
.io_pads_gpio_12_o_oval(dut_io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe(dut_io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie(dut_io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue(dut_io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds(dut_io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival(dut_io_pads_gpio_13_i_ival),
.io_pads_gpio_13_o_oval(dut_io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe(dut_io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie(dut_io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue(dut_io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds(dut_io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival(dut_io_pads_gpio_14_i_ival),
.io_pads_gpio_14_o_oval(dut_io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe(dut_io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie(dut_io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue(dut_io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds(dut_io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival(dut_io_pads_gpio_15_i_ival),
.io_pads_gpio_15_o_oval(dut_io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe(dut_io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie(dut_io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue(dut_io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds(dut_io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival(dut_io_pads_gpio_16_i_ival),
.io_pads_gpio_16_o_oval(dut_io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe(dut_io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie(dut_io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue(dut_io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds(dut_io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival(dut_io_pads_gpio_17_i_ival),
.io_pads_gpio_17_o_oval(dut_io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe(dut_io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie(dut_io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue(dut_io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds(dut_io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival(dut_io_pads_gpio_18_i_ival),
.io_pads_gpio_18_o_oval(dut_io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe(dut_io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie(dut_io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue(dut_io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds(dut_io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival(dut_io_pads_gpio_19_i_ival),
.io_pads_gpio_19_o_oval(dut_io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe(dut_io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie(dut_io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue(dut_io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds(dut_io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival(dut_io_pads_gpio_20_i_ival),
.io_pads_gpio_20_o_oval(dut_io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe(dut_io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie(dut_io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue(dut_io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds(dut_io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival(dut_io_pads_gpio_21_i_ival),
.io_pads_gpio_21_o_oval(dut_io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe(dut_io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie(dut_io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue(dut_io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds(dut_io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival(dut_io_pads_gpio_22_i_ival),
.io_pads_gpio_22_o_oval(dut_io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe(dut_io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie(dut_io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue(dut_io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds(dut_io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival(dut_io_pads_gpio_23_i_ival),
.io_pads_gpio_23_o_oval(dut_io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe(dut_io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie(dut_io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue(dut_io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds(dut_io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival(dut_io_pads_gpio_24_i_ival),
.io_pads_gpio_24_o_oval(dut_io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe(dut_io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie(dut_io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue(dut_io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds(dut_io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival(dut_io_pads_gpio_25_i_ival),
.io_pads_gpio_25_o_oval(dut_io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe(dut_io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie(dut_io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue(dut_io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds(dut_io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival(dut_io_pads_gpio_26_i_ival),
.io_pads_gpio_26_o_oval(dut_io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe(dut_io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie(dut_io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue(dut_io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds(dut_io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival(dut_io_pads_gpio_27_i_ival),
.io_pads_gpio_27_o_oval(dut_io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe(dut_io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie(dut_io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue(dut_io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds(dut_io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival(dut_io_pads_gpio_28_i_ival),
.io_pads_gpio_28_o_oval(dut_io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe(dut_io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie(dut_io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue(dut_io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds(dut_io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival(dut_io_pads_gpio_29_i_ival),
.io_pads_gpio_29_o_oval(dut_io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe(dut_io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie(dut_io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue(dut_io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds(dut_io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival(dut_io_pads_gpio_30_i_ival),
.io_pads_gpio_30_o_oval(dut_io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe(dut_io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie(dut_io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue(dut_io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds(dut_io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival(dut_io_pads_gpio_31_i_ival),
.io_pads_gpio_31_o_oval(dut_io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe(dut_io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie(dut_io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue(dut_io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds(dut_io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival(dut_io_pads_qspi_sck_i_ival),
.io_pads_qspi_sck_o_oval(dut_io_pads_qspi_sck_o_oval),
.io_pads_qspi_sck_o_oe(dut_io_pads_qspi_sck_o_oe),
.io_pads_qspi_sck_o_ie(dut_io_pads_qspi_sck_o_ie),
.io_pads_qspi_sck_o_pue(dut_io_pads_qspi_sck_o_pue),
.io_pads_qspi_sck_o_ds(dut_io_pads_qspi_sck_o_ds),
.io_pads_qspi_dq_0_i_ival(dut_io_pads_qspi_dq_0_i_ival),
.io_pads_qspi_dq_0_o_oval(dut_io_pads_qspi_dq_0_o_oval),
.io_pads_qspi_dq_0_o_oe(dut_io_pads_qspi_dq_0_o_oe),
.io_pads_qspi_dq_0_o_ie(dut_io_pads_qspi_dq_0_o_ie),
.io_pads_qspi_dq_0_o_pue(dut_io_pads_qspi_dq_0_o_pue),
.io_pads_qspi_dq_0_o_ds(dut_io_pads_qspi_dq_0_o_ds),
.io_pads_qspi_dq_1_i_ival(dut_io_pads_qspi_dq_1_i_ival),
.io_pads_qspi_dq_1_o_oval(dut_io_pads_qspi_dq_1_o_oval),
.io_pads_qspi_dq_1_o_oe(dut_io_pads_qspi_dq_1_o_oe),
.io_pads_qspi_dq_1_o_ie(dut_io_pads_qspi_dq_1_o_ie),
.io_pads_qspi_dq_1_o_pue(dut_io_pads_qspi_dq_1_o_pue),
.io_pads_qspi_dq_1_o_ds(dut_io_pads_qspi_dq_1_o_ds),
.io_pads_qspi_dq_2_i_ival(dut_io_pads_qspi_dq_2_i_ival),
.io_pads_qspi_dq_2_o_oval(dut_io_pads_qspi_dq_2_o_oval),
.io_pads_qspi_dq_2_o_oe(dut_io_pads_qspi_dq_2_o_oe),
.io_pads_qspi_dq_2_o_ie(dut_io_pads_qspi_dq_2_o_ie),
.io_pads_qspi_dq_2_o_pue(dut_io_pads_qspi_dq_2_o_pue),
.io_pads_qspi_dq_2_o_ds(dut_io_pads_qspi_dq_2_o_ds),
.io_pads_qspi_dq_3_i_ival(dut_io_pads_qspi_dq_3_i_ival),
.io_pads_qspi_dq_3_o_oval(dut_io_pads_qspi_dq_3_o_oval),
.io_pads_qspi_dq_3_o_oe(dut_io_pads_qspi_dq_3_o_oe),
.io_pads_qspi_dq_3_o_ie(dut_io_pads_qspi_dq_3_o_ie),
.io_pads_qspi_dq_3_o_pue(dut_io_pads_qspi_dq_3_o_pue),
.io_pads_qspi_dq_3_o_ds(dut_io_pads_qspi_dq_3_o_ds),
.io_pads_qspi_cs_0_i_ival(dut_io_pads_qspi_cs_0_i_ival),
.io_pads_qspi_cs_0_o_oval(dut_io_pads_qspi_cs_0_o_oval),
.io_pads_qspi_cs_0_o_oe(dut_io_pads_qspi_cs_0_o_oe),
.io_pads_qspi_cs_0_o_ie(dut_io_pads_qspi_cs_0_o_ie),
.io_pads_qspi_cs_0_o_pue(dut_io_pads_qspi_cs_0_o_pue),
.io_pads_qspi_cs_0_o_ds(dut_io_pads_qspi_cs_0_o_ds),
.io_pads_aon_erst_n_i_ival(dut_io_pads_aon_erst_n_i_ival),
.io_pads_aon_erst_n_o_oval(dut_io_pads_aon_erst_n_o_oval),
.io_pads_aon_erst_n_o_oe(dut_io_pads_aon_erst_n_o_oe),
.io_pads_aon_erst_n_o_ie(dut_io_pads_aon_erst_n_o_ie),
.io_pads_aon_erst_n_o_pue(dut_io_pads_aon_erst_n_o_pue),
.io_pads_aon_erst_n_o_ds(dut_io_pads_aon_erst_n_o_ds),
.io_pads_aon_lfextclk_i_ival(dut_io_pads_aon_lfextclk_i_ival),
.io_pads_aon_lfextclk_o_oval(dut_io_pads_aon_lfextclk_o_oval),
.io_pads_aon_lfextclk_o_oe(dut_io_pads_aon_lfextclk_o_oe),
.io_pads_aon_lfextclk_o_ie(dut_io_pads_aon_lfextclk_o_ie),
.io_pads_aon_lfextclk_o_pue(dut_io_pads_aon_lfextclk_o_pue),
.io_pads_aon_lfextclk_o_ds(dut_io_pads_aon_lfextclk_o_ds),
.io_pads_aon_pmu_dwakeup_n_i_ival(dut_io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval(dut_io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_aon_pmu_dwakeup_n_o_oe(dut_io_pads_aon_pmu_dwakeup_n_o_oe),
.io_pads_aon_pmu_dwakeup_n_o_ie(dut_io_pads_aon_pmu_dwakeup_n_o_ie),
.io_pads_aon_pmu_dwakeup_n_o_pue(dut_io_pads_aon_pmu_dwakeup_n_o_pue),
.io_pads_aon_pmu_dwakeup_n_o_ds(dut_io_pads_aon_pmu_dwakeup_n_o_ds),
.io_pads_aon_pmu_vddpaden_i_ival(dut_io_pads_aon_pmu_vddpaden_i_ival),
.io_pads_aon_pmu_vddpaden_o_oval(dut_io_pads_aon_pmu_vddpaden_o_oval),
.io_pads_aon_pmu_vddpaden_o_oe(dut_io_pads_aon_pmu_vddpaden_o_oe),
.io_pads_aon_pmu_vddpaden_o_ie(dut_io_pads_aon_pmu_vddpaden_o_ie),
.io_pads_aon_pmu_vddpaden_o_pue(dut_io_pads_aon_pmu_vddpaden_o_pue),
.io_pads_aon_pmu_vddpaden_o_ds(dut_io_pads_aon_pmu_vddpaden_o_ds)
);
wire iobuf_dwakeup_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_dwakeup_n
(
.O(iobuf_dwakeup_o),
.IO(btn_3),
.I(~dut_io_pads_aon_pmu_dwakeup_n_o_oval),
.T(~dut_io_pads_aon_pmu_dwakeup_n_o_oe)
);
assign dut_io_pads_aon_pmu_dwakeup_n_i_ival = (~iobuf_dwakeup_o) & dut_io_pads_aon_pmu_dwakeup_n_o_ie;
assign dut_io_pads_aon_erst_n_i_ival = ~reset_periph;
assign dut_io_pads_aon_lfextclk_i_ival = slowclk;
assign dut_io_pads_aon_pmu_vddpaden_i_ival = 1'b1;
assign qspi_cs = dut_io_pads_qspi_cs_0_o_oval;
assign qspi_ui_dq_o = {
dut_io_pads_qspi_dq_3_o_oval,
dut_io_pads_qspi_dq_2_o_oval,
dut_io_pads_qspi_dq_1_o_oval,
dut_io_pads_qspi_dq_0_o_oval
};
assign qspi_ui_dq_oe = {
dut_io_pads_qspi_dq_3_o_oe,
dut_io_pads_qspi_dq_2_o_oe,
dut_io_pads_qspi_dq_1_o_oe,
dut_io_pads_qspi_dq_0_o_oe
};
assign dut_io_pads_qspi_dq_0_i_ival = qspi_ui_dq_i[0];
assign dut_io_pads_qspi_dq_1_i_ival = qspi_ui_dq_i[1];
assign dut_io_pads_qspi_dq_2_i_ival = qspi_ui_dq_i[2];
assign dut_io_pads_qspi_dq_3_i_ival = qspi_ui_dq_i[3];
assign qspi_sck = dut_io_pads_qspi_sck_o_oval;
endmodule | module system
(
input wire CLK100MHZ,
input wire ck_rst,
inout wire led_0,
inout wire led_1,
inout wire led_2,
inout wire led_3,
output wire led0_r,
output wire led0_g,
output wire led0_b,
output wire led1_r,
output wire led1_g,
output wire led1_b,
output wire led2_r,
output wire led2_g,
output wire led2_b,
inout wire sw_0,
inout wire sw_1,
inout wire sw_2,
input wire sw_3,
inout wire btn_0,
inout wire btn_1,
inout wire btn_2,
inout wire btn_3,
output wire qspi_cs,
output wire qspi_sck,
inout wire [3:0] qspi_dq,
output wire uart_rxd_out,
input wire uart_txd_in,
inout wire ja_0,
inout wire ja_1,
inout wire [19:0] ck_io,
inout wire ck_miso,
inout wire ck_mosi,
inout wire ck_ss,
inout wire ck_sck,
inout wire jd_0,
inout wire jd_1,
inout wire jd_2,
inout wire jd_4,
inout wire jd_5,
input wire jd_6
); |
wire clk_out1;
wire hfclk;
wire mmcm_locked;
wire reset_core;
wire reset_bus;
wire reset_periph;
wire reset_intcon_n;
wire reset_periph_n;
wire dut_clock;
wire dut_reset;
wire dut_io_pads_jtag_TCK_i_ival;
wire dut_io_pads_jtag_TCK_o_oval;
wire dut_io_pads_jtag_TCK_o_oe;
wire dut_io_pads_jtag_TCK_o_ie;
wire dut_io_pads_jtag_TCK_o_pue;
wire dut_io_pads_jtag_TCK_o_ds;
wire dut_io_pads_jtag_TMS_i_ival;
wire dut_io_pads_jtag_TMS_o_oval;
wire dut_io_pads_jtag_TMS_o_oe;
wire dut_io_pads_jtag_TMS_o_ie;
wire dut_io_pads_jtag_TMS_o_pue;
wire dut_io_pads_jtag_TMS_o_ds;
wire dut_io_pads_jtag_TDI_i_ival;
wire dut_io_pads_jtag_TDI_o_oval;
wire dut_io_pads_jtag_TDI_o_oe;
wire dut_io_pads_jtag_TDI_o_ie;
wire dut_io_pads_jtag_TDI_o_pue;
wire dut_io_pads_jtag_TDI_o_ds;
wire dut_io_pads_jtag_TDO_i_ival;
wire dut_io_pads_jtag_TDO_o_oval;
wire dut_io_pads_jtag_TDO_o_oe;
wire dut_io_pads_jtag_TDO_o_ie;
wire dut_io_pads_jtag_TDO_o_pue;
wire dut_io_pads_jtag_TDO_o_ds;
wire dut_io_pads_jtag_TRST_n_i_ival;
wire dut_io_pads_jtag_TRST_n_o_oval;
wire dut_io_pads_jtag_TRST_n_o_oe;
wire dut_io_pads_jtag_TRST_n_o_ie;
wire dut_io_pads_jtag_TRST_n_o_pue;
wire dut_io_pads_jtag_TRST_n_o_ds;
wire dut_io_pads_gpio_0_i_ival;
wire dut_io_pads_gpio_0_o_oval;
wire dut_io_pads_gpio_0_o_oe;
wire dut_io_pads_gpio_0_o_ie;
wire dut_io_pads_gpio_0_o_pue;
wire dut_io_pads_gpio_0_o_ds;
wire dut_io_pads_gpio_1_i_ival;
wire dut_io_pads_gpio_1_o_oval;
wire dut_io_pads_gpio_1_o_oe;
wire dut_io_pads_gpio_1_o_ie;
wire dut_io_pads_gpio_1_o_pue;
wire dut_io_pads_gpio_1_o_ds;
wire dut_io_pads_gpio_2_i_ival;
wire dut_io_pads_gpio_2_o_oval;
wire dut_io_pads_gpio_2_o_oe;
wire dut_io_pads_gpio_2_o_ie;
wire dut_io_pads_gpio_2_o_pue;
wire dut_io_pads_gpio_2_o_ds;
wire dut_io_pads_gpio_3_i_ival;
wire dut_io_pads_gpio_3_o_oval;
wire dut_io_pads_gpio_3_o_oe;
wire dut_io_pads_gpio_3_o_ie;
wire dut_io_pads_gpio_3_o_pue;
wire dut_io_pads_gpio_3_o_ds;
wire dut_io_pads_gpio_4_i_ival;
wire dut_io_pads_gpio_4_o_oval;
wire dut_io_pads_gpio_4_o_oe;
wire dut_io_pads_gpio_4_o_ie;
wire dut_io_pads_gpio_4_o_pue;
wire dut_io_pads_gpio_4_o_ds;
wire dut_io_pads_gpio_5_i_ival;
wire dut_io_pads_gpio_5_o_oval;
wire dut_io_pads_gpio_5_o_oe;
wire dut_io_pads_gpio_5_o_ie;
wire dut_io_pads_gpio_5_o_pue;
wire dut_io_pads_gpio_5_o_ds;
wire dut_io_pads_gpio_6_i_ival;
wire dut_io_pads_gpio_6_o_oval;
wire dut_io_pads_gpio_6_o_oe;
wire dut_io_pads_gpio_6_o_ie;
wire dut_io_pads_gpio_6_o_pue;
wire dut_io_pads_gpio_6_o_ds;
wire dut_io_pads_gpio_7_i_ival;
wire dut_io_pads_gpio_7_o_oval;
wire dut_io_pads_gpio_7_o_oe;
wire dut_io_pads_gpio_7_o_ie;
wire dut_io_pads_gpio_7_o_pue;
wire dut_io_pads_gpio_7_o_ds;
wire dut_io_pads_gpio_8_i_ival;
wire dut_io_pads_gpio_8_o_oval;
wire dut_io_pads_gpio_8_o_oe;
wire dut_io_pads_gpio_8_o_ie;
wire dut_io_pads_gpio_8_o_pue;
wire dut_io_pads_gpio_8_o_ds;
wire dut_io_pads_gpio_9_i_ival;
wire dut_io_pads_gpio_9_o_oval;
wire dut_io_pads_gpio_9_o_oe;
wire dut_io_pads_gpio_9_o_ie;
wire dut_io_pads_gpio_9_o_pue;
wire dut_io_pads_gpio_9_o_ds;
wire dut_io_pads_gpio_10_i_ival;
wire dut_io_pads_gpio_10_o_oval;
wire dut_io_pads_gpio_10_o_oe;
wire dut_io_pads_gpio_10_o_ie;
wire dut_io_pads_gpio_10_o_pue;
wire dut_io_pads_gpio_10_o_ds;
wire dut_io_pads_gpio_11_i_ival;
wire dut_io_pads_gpio_11_o_oval;
wire dut_io_pads_gpio_11_o_oe;
wire dut_io_pads_gpio_11_o_ie;
wire dut_io_pads_gpio_11_o_pue;
wire dut_io_pads_gpio_11_o_ds;
wire dut_io_pads_gpio_12_i_ival;
wire dut_io_pads_gpio_12_o_oval;
wire dut_io_pads_gpio_12_o_oe;
wire dut_io_pads_gpio_12_o_ie;
wire dut_io_pads_gpio_12_o_pue;
wire dut_io_pads_gpio_12_o_ds;
wire dut_io_pads_gpio_13_i_ival;
wire dut_io_pads_gpio_13_o_oval;
wire dut_io_pads_gpio_13_o_oe;
wire dut_io_pads_gpio_13_o_ie;
wire dut_io_pads_gpio_13_o_pue;
wire dut_io_pads_gpio_13_o_ds;
wire dut_io_pads_gpio_14_i_ival;
wire dut_io_pads_gpio_14_o_oval;
wire dut_io_pads_gpio_14_o_oe;
wire dut_io_pads_gpio_14_o_ie;
wire dut_io_pads_gpio_14_o_pue;
wire dut_io_pads_gpio_14_o_ds;
wire dut_io_pads_gpio_15_i_ival;
wire dut_io_pads_gpio_15_o_oval;
wire dut_io_pads_gpio_15_o_oe;
wire dut_io_pads_gpio_15_o_ie;
wire dut_io_pads_gpio_15_o_pue;
wire dut_io_pads_gpio_15_o_ds;
wire dut_io_pads_gpio_16_i_ival;
wire dut_io_pads_gpio_16_o_oval;
wire dut_io_pads_gpio_16_o_oe;
wire dut_io_pads_gpio_16_o_ie;
wire dut_io_pads_gpio_16_o_pue;
wire dut_io_pads_gpio_16_o_ds;
wire dut_io_pads_gpio_17_i_ival;
wire dut_io_pads_gpio_17_o_oval;
wire dut_io_pads_gpio_17_o_oe;
wire dut_io_pads_gpio_17_o_ie;
wire dut_io_pads_gpio_17_o_pue;
wire dut_io_pads_gpio_17_o_ds;
wire dut_io_pads_gpio_18_i_ival;
wire dut_io_pads_gpio_18_o_oval;
wire dut_io_pads_gpio_18_o_oe;
wire dut_io_pads_gpio_18_o_ie;
wire dut_io_pads_gpio_18_o_pue;
wire dut_io_pads_gpio_18_o_ds;
wire dut_io_pads_gpio_19_i_ival;
wire dut_io_pads_gpio_19_o_oval;
wire dut_io_pads_gpio_19_o_oe;
wire dut_io_pads_gpio_19_o_ie;
wire dut_io_pads_gpio_19_o_pue;
wire dut_io_pads_gpio_19_o_ds;
wire dut_io_pads_gpio_20_i_ival;
wire dut_io_pads_gpio_20_o_oval;
wire dut_io_pads_gpio_20_o_oe;
wire dut_io_pads_gpio_20_o_ie;
wire dut_io_pads_gpio_20_o_pue;
wire dut_io_pads_gpio_20_o_ds;
wire dut_io_pads_gpio_21_i_ival;
wire dut_io_pads_gpio_21_o_oval;
wire dut_io_pads_gpio_21_o_oe;
wire dut_io_pads_gpio_21_o_ie;
wire dut_io_pads_gpio_21_o_pue;
wire dut_io_pads_gpio_21_o_ds;
wire dut_io_pads_gpio_22_i_ival;
wire dut_io_pads_gpio_22_o_oval;
wire dut_io_pads_gpio_22_o_oe;
wire dut_io_pads_gpio_22_o_ie;
wire dut_io_pads_gpio_22_o_pue;
wire dut_io_pads_gpio_22_o_ds;
wire dut_io_pads_gpio_23_i_ival;
wire dut_io_pads_gpio_23_o_oval;
wire dut_io_pads_gpio_23_o_oe;
wire dut_io_pads_gpio_23_o_ie;
wire dut_io_pads_gpio_23_o_pue;
wire dut_io_pads_gpio_23_o_ds;
wire dut_io_pads_gpio_24_i_ival;
wire dut_io_pads_gpio_24_o_oval;
wire dut_io_pads_gpio_24_o_oe;
wire dut_io_pads_gpio_24_o_ie;
wire dut_io_pads_gpio_24_o_pue;
wire dut_io_pads_gpio_24_o_ds;
wire dut_io_pads_gpio_25_i_ival;
wire dut_io_pads_gpio_25_o_oval;
wire dut_io_pads_gpio_25_o_oe;
wire dut_io_pads_gpio_25_o_ie;
wire dut_io_pads_gpio_25_o_pue;
wire dut_io_pads_gpio_25_o_ds;
wire dut_io_pads_gpio_26_i_ival;
wire dut_io_pads_gpio_26_o_oval;
wire dut_io_pads_gpio_26_o_oe;
wire dut_io_pads_gpio_26_o_ie;
wire dut_io_pads_gpio_26_o_pue;
wire dut_io_pads_gpio_26_o_ds;
wire dut_io_pads_gpio_27_i_ival;
wire dut_io_pads_gpio_27_o_oval;
wire dut_io_pads_gpio_27_o_oe;
wire dut_io_pads_gpio_27_o_ie;
wire dut_io_pads_gpio_27_o_pue;
wire dut_io_pads_gpio_27_o_ds;
wire dut_io_pads_gpio_28_i_ival;
wire dut_io_pads_gpio_28_o_oval;
wire dut_io_pads_gpio_28_o_oe;
wire dut_io_pads_gpio_28_o_ie;
wire dut_io_pads_gpio_28_o_pue;
wire dut_io_pads_gpio_28_o_ds;
wire dut_io_pads_gpio_29_i_ival;
wire dut_io_pads_gpio_29_o_oval;
wire dut_io_pads_gpio_29_o_oe;
wire dut_io_pads_gpio_29_o_ie;
wire dut_io_pads_gpio_29_o_pue;
wire dut_io_pads_gpio_29_o_ds;
wire dut_io_pads_gpio_30_i_ival;
wire dut_io_pads_gpio_30_o_oval;
wire dut_io_pads_gpio_30_o_oe;
wire dut_io_pads_gpio_30_o_ie;
wire dut_io_pads_gpio_30_o_pue;
wire dut_io_pads_gpio_30_o_ds;
wire dut_io_pads_gpio_31_i_ival;
wire dut_io_pads_gpio_31_o_oval;
wire dut_io_pads_gpio_31_o_oe;
wire dut_io_pads_gpio_31_o_ie;
wire dut_io_pads_gpio_31_o_pue;
wire dut_io_pads_gpio_31_o_ds;
wire dut_io_pads_qspi_sck_i_ival;
wire dut_io_pads_qspi_sck_o_oval;
wire dut_io_pads_qspi_sck_o_oe;
wire dut_io_pads_qspi_sck_o_ie;
wire dut_io_pads_qspi_sck_o_pue;
wire dut_io_pads_qspi_sck_o_ds;
wire dut_io_pads_qspi_dq_0_i_ival;
wire dut_io_pads_qspi_dq_0_o_oval;
wire dut_io_pads_qspi_dq_0_o_oe;
wire dut_io_pads_qspi_dq_0_o_ie;
wire dut_io_pads_qspi_dq_0_o_pue;
wire dut_io_pads_qspi_dq_0_o_ds;
wire dut_io_pads_qspi_dq_1_i_ival;
wire dut_io_pads_qspi_dq_1_o_oval;
wire dut_io_pads_qspi_dq_1_o_oe;
wire dut_io_pads_qspi_dq_1_o_ie;
wire dut_io_pads_qspi_dq_1_o_pue;
wire dut_io_pads_qspi_dq_1_o_ds;
wire dut_io_pads_qspi_dq_2_i_ival;
wire dut_io_pads_qspi_dq_2_o_oval;
wire dut_io_pads_qspi_dq_2_o_oe;
wire dut_io_pads_qspi_dq_2_o_ie;
wire dut_io_pads_qspi_dq_2_o_pue;
wire dut_io_pads_qspi_dq_2_o_ds;
wire dut_io_pads_qspi_dq_3_i_ival;
wire dut_io_pads_qspi_dq_3_o_oval;
wire dut_io_pads_qspi_dq_3_o_oe;
wire dut_io_pads_qspi_dq_3_o_ie;
wire dut_io_pads_qspi_dq_3_o_pue;
wire dut_io_pads_qspi_dq_3_o_ds;
wire dut_io_pads_qspi_cs_0_i_ival;
wire dut_io_pads_qspi_cs_0_o_oval;
wire dut_io_pads_qspi_cs_0_o_oe;
wire dut_io_pads_qspi_cs_0_o_ie;
wire dut_io_pads_qspi_cs_0_o_pue;
wire dut_io_pads_qspi_cs_0_o_ds;
wire dut_io_pads_aon_erst_n_i_ival;
wire dut_io_pads_aon_erst_n_o_oval;
wire dut_io_pads_aon_erst_n_o_oe;
wire dut_io_pads_aon_erst_n_o_ie;
wire dut_io_pads_aon_erst_n_o_pue;
wire dut_io_pads_aon_erst_n_o_ds;
wire dut_io_pads_aon_lfextclk_i_ival;
wire dut_io_pads_aon_lfextclk_o_oval;
wire dut_io_pads_aon_lfextclk_o_oe;
wire dut_io_pads_aon_lfextclk_o_ie;
wire dut_io_pads_aon_lfextclk_o_pue;
wire dut_io_pads_aon_lfextclk_o_ds;
wire dut_io_pads_aon_pmu_dwakeup_n_i_ival;
wire dut_io_pads_aon_pmu_dwakeup_n_o_oval;
wire dut_io_pads_aon_pmu_dwakeup_n_o_oe;
wire dut_io_pads_aon_pmu_dwakeup_n_o_ie;
wire dut_io_pads_aon_pmu_dwakeup_n_o_pue;
wire dut_io_pads_aon_pmu_dwakeup_n_o_ds;
wire dut_io_pads_aon_pmu_vddpaden_i_ival;
wire dut_io_pads_aon_pmu_vddpaden_o_oval;
wire dut_io_pads_aon_pmu_vddpaden_o_oe;
wire dut_io_pads_aon_pmu_vddpaden_o_ie;
wire dut_io_pads_aon_pmu_vddpaden_o_pue;
wire dut_io_pads_aon_pmu_vddpaden_o_ds;
wire SRST_n;
mmcm ip_mmcm
(
.clk_in1(CLK100MHZ),
.clk_out1(clk_out1),
.clk_out2(hfclk),
.resetn(ck_rst),
.locked(mmcm_locked)
);
wire slowclk;
clkdivider slowclkgen
(
.clk(clk_out1),
.reset(~mmcm_locked),
.clk_out(slowclk)
);
reset_sys ip_reset_sys
(
.slowest_sync_clk(clk_out1),
.ext_reset_in(ck_rst & SRST_n),
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(mmcm_locked),
.mb_reset(reset_core),
.bus_struct_reset(reset_bus),
.peripheral_reset(reset_periph),
.interconnect_aresetn(reset_intcon_n),
.peripheral_aresetn(reset_periph_n)
);
wire [3:0] qspi_ui_dq_o, qspi_ui_dq_oe;
wire [3:0] qspi_ui_dq_i;
PULLUP qspi_pullup[3:0]
(
.O(qspi_dq)
);
IOBUF qspi_iobuf[3:0]
(
.IO(qspi_dq),
.O(qspi_ui_dq_i),
.I(qspi_ui_dq_o),
.T(~qspi_ui_dq_oe)
);
wire gpio_0;
wire gpio_1;
wire gpio_2;
wire gpio_3;
wire gpio_4;
wire gpio_5;
wire gpio_6;
wire gpio_7;
wire gpio_8;
wire gpio_9;
wire gpio_10;
wire gpio_11;
wire gpio_12;
wire gpio_13;
wire gpio_14;
wire gpio_15;
wire gpio_16;
wire gpio_17;
wire gpio_18;
wire gpio_19;
wire gpio_20;
wire gpio_21;
wire gpio_22;
wire gpio_23;
wire gpio_24;
wire gpio_25;
wire gpio_26;
wire gpio_27;
wire gpio_28;
wire gpio_29;
wire gpio_30;
wire gpio_31;
wire iobuf_gpio_0_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_0
(
.O(iobuf_gpio_0_o),
.IO(gpio_0),
.I(dut_io_pads_gpio_0_o_oval),
.T(~dut_io_pads_gpio_0_o_oe)
);
assign dut_io_pads_gpio_0_i_ival = iobuf_gpio_0_o & dut_io_pads_gpio_0_o_ie;
wire iobuf_gpio_1_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_1
(
.O(iobuf_gpio_1_o),
.IO(gpio_1),
.I(dut_io_pads_gpio_1_o_oval),
.T(~dut_io_pads_gpio_1_o_oe)
);
assign dut_io_pads_gpio_1_i_ival = iobuf_gpio_1_o & dut_io_pads_gpio_1_o_ie;
wire iobuf_gpio_2_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_2
(
.O(iobuf_gpio_2_o),
.IO(gpio_2),
.I(dut_io_pads_gpio_2_o_oval),
.T(~dut_io_pads_gpio_2_o_oe)
);
assign dut_io_pads_gpio_2_i_ival = iobuf_gpio_2_o & dut_io_pads_gpio_2_o_ie;
wire iobuf_gpio_3_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_3
(
.O(iobuf_gpio_3_o),
.IO(gpio_3),
.I(dut_io_pads_gpio_3_o_oval),
.T(~dut_io_pads_gpio_3_o_oe)
);
assign dut_io_pads_gpio_3_i_ival = iobuf_gpio_3_o & dut_io_pads_gpio_3_o_ie;
wire iobuf_gpio_4_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_4
(
.O(iobuf_gpio_4_o),
.IO(gpio_4),
.I(dut_io_pads_gpio_4_o_oval),
.T(~dut_io_pads_gpio_4_o_oe)
);
assign dut_io_pads_gpio_4_i_ival = iobuf_gpio_4_o & dut_io_pads_gpio_4_o_ie;
wire iobuf_gpio_5_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_5
(
.O(iobuf_gpio_5_o),
.IO(gpio_5),
.I(dut_io_pads_gpio_5_o_oval),
.T(~dut_io_pads_gpio_5_o_oe)
);
assign dut_io_pads_gpio_5_i_ival = iobuf_gpio_5_o & dut_io_pads_gpio_5_o_ie;
assign dut_io_pads_gpio_6_i_ival = 1'b0;
assign dut_io_pads_gpio_7_i_ival = 1'b0;
assign dut_io_pads_gpio_8_i_ival = 1'b0;
wire iobuf_gpio_9_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_9
(
.O(iobuf_gpio_9_o),
.IO(gpio_9),
.I(dut_io_pads_gpio_9_o_oval),
.T(~dut_io_pads_gpio_9_o_oe)
);
assign dut_io_pads_gpio_9_i_ival = iobuf_gpio_9_o & dut_io_pads_gpio_9_o_ie;
wire iobuf_gpio_10_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_10
(
.O(iobuf_gpio_10_o),
.IO(gpio_10),
.I(dut_io_pads_gpio_10_o_oval),
.T(~dut_io_pads_gpio_10_o_oe)
);
assign dut_io_pads_gpio_10_i_ival = iobuf_gpio_10_o & dut_io_pads_gpio_10_o_ie;
wire iobuf_gpio_11_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_11
(
.O(iobuf_gpio_11_o),
.IO(gpio_11),
.I(dut_io_pads_gpio_11_o_oval),
.T(~dut_io_pads_gpio_11_o_oe)
);
assign dut_io_pads_gpio_11_i_ival = iobuf_gpio_11_o & dut_io_pads_gpio_11_o_ie;
wire iobuf_gpio_12_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_12
(
.O(iobuf_gpio_12_o),
.IO(gpio_12),
.I(dut_io_pads_gpio_12_o_oval),
.T(~dut_io_pads_gpio_12_o_oe)
);
assign dut_io_pads_gpio_12_i_ival = iobuf_gpio_12_o & dut_io_pads_gpio_12_o_ie;
wire iobuf_gpio_13_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_13
(
.O(iobuf_gpio_13_o),
.IO(gpio_13),
.I(dut_io_pads_gpio_13_o_oval),
.T(~dut_io_pads_gpio_13_o_oe)
);
assign dut_io_pads_gpio_13_i_ival = iobuf_gpio_13_o & dut_io_pads_gpio_13_o_ie;
wire iobuf_gpio_14_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_14
(
.O(iobuf_gpio_14_o),
.IO(gpio_14),
.I(dut_io_pads_gpio_14_o_oval),
.T(~dut_io_pads_gpio_14_o_oe)
);
assign dut_io_pads_gpio_14_i_ival = iobuf_gpio_14_o & dut_io_pads_gpio_14_o_ie;
wire iobuf_gpio_15_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_15
(
.O(iobuf_gpio_15_o),
.IO(gpio_15),
.I(dut_io_pads_gpio_15_o_oval),
.T(~dut_io_pads_gpio_15_o_oe)
);
assign dut_io_pads_gpio_15_i_ival = iobuf_gpio_15_o & dut_io_pads_gpio_15_o_ie;
wire iobuf_gpio_16_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_16
(
.O(iobuf_gpio_16_o),
.IO(gpio_16),
.I(dut_io_pads_gpio_16_o_oval),
.T(~dut_io_pads_gpio_16_o_oe)
);
assign dut_io_pads_gpio_16_i_ival = sw_3 ? (iobuf_gpio_16_o & dut_io_pads_gpio_16_o_ie) : (uart_txd_in & dut_io_pads_gpio_16_o_ie);
wire iobuf_gpio_17_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_17
(
.O(iobuf_gpio_17_o),
.IO(gpio_17),
.I(dut_io_pads_gpio_17_o_oval),
.T(~dut_io_pads_gpio_17_o_oe)
);
assign dut_io_pads_gpio_17_i_ival = iobuf_gpio_17_o & dut_io_pads_gpio_17_o_ie;
assign uart_rxd_out = (dut_io_pads_gpio_17_o_oval & dut_io_pads_gpio_17_o_oe);
wire iobuf_gpio_18_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_18
(
.O(iobuf_gpio_18_o),
.IO(gpio_18),
.I(dut_io_pads_gpio_18_o_oval),
.T(~dut_io_pads_gpio_18_o_oe)
);
assign dut_io_pads_gpio_18_i_ival = iobuf_gpio_18_o & dut_io_pads_gpio_18_o_ie;
wire iobuf_gpio_19_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_19
(
.O(iobuf_gpio_19_o),
.IO(gpio_19),
.I(dut_io_pads_gpio_19_o_oval),
.T(~dut_io_pads_gpio_19_o_oe)
);
assign dut_io_pads_gpio_19_i_ival = iobuf_gpio_19_o & dut_io_pads_gpio_19_o_ie;
wire iobuf_gpio_20_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_20
(
.O(iobuf_gpio_20_o),
.IO(gpio_20),
.I(dut_io_pads_gpio_20_o_oval),
.T(~dut_io_pads_gpio_20_o_oe)
);
assign dut_io_pads_gpio_20_i_ival = iobuf_gpio_20_o & dut_io_pads_gpio_20_o_ie;
wire iobuf_gpio_21_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_21
(
.O(iobuf_gpio_21_o),
.IO(gpio_21),
.I(dut_io_pads_gpio_21_o_oval),
.T(~dut_io_pads_gpio_21_o_oe)
);
assign dut_io_pads_gpio_21_i_ival = iobuf_gpio_21_o & dut_io_pads_gpio_21_o_ie;
wire iobuf_gpio_22_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_22
(
.O(iobuf_gpio_22_o),
.IO(gpio_22),
.I(dut_io_pads_gpio_22_o_oval),
.T(~dut_io_pads_gpio_22_o_oe)
);
assign dut_io_pads_gpio_22_i_ival = iobuf_gpio_22_o & dut_io_pads_gpio_22_o_ie;
wire iobuf_gpio_23_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_23
(
.O(iobuf_gpio_23_o),
.IO(gpio_23),
.I(dut_io_pads_gpio_23_o_oval),
.T(~dut_io_pads_gpio_23_o_oe)
);
assign dut_io_pads_gpio_23_i_ival = iobuf_gpio_23_o & dut_io_pads_gpio_23_o_ie;
wire iobuf_gpio_24_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_24
(
.O(iobuf_gpio_24_o),
.IO(gpio_24),
.I(dut_io_pads_gpio_24_o_oval),
.T(~dut_io_pads_gpio_24_o_oe)
);
assign dut_io_pads_gpio_24_i_ival = iobuf_gpio_24_o & dut_io_pads_gpio_24_o_ie;
wire iobuf_gpio_25_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_25
(
.O(iobuf_gpio_25_o),
.IO(gpio_25),
.I(dut_io_pads_gpio_25_o_oval),
.T(~dut_io_pads_gpio_25_o_oe)
);
assign dut_io_pads_gpio_25_i_ival = iobuf_gpio_25_o & dut_io_pads_gpio_25_o_ie;
wire iobuf_gpio_26_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_26
(
.O(iobuf_gpio_26_o),
.IO(gpio_26),
.I(dut_io_pads_gpio_26_o_oval),
.T(~dut_io_pads_gpio_26_o_oe)
);
assign dut_io_pads_gpio_26_i_ival = iobuf_gpio_26_o & dut_io_pads_gpio_26_o_ie;
wire iobuf_gpio_27_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_27
(
.O(iobuf_gpio_27_o),
.IO(gpio_27),
.I(dut_io_pads_gpio_27_o_oval),
.T(~dut_io_pads_gpio_27_o_oe)
);
assign dut_io_pads_gpio_27_i_ival = iobuf_gpio_27_o & dut_io_pads_gpio_27_o_ie;
wire iobuf_gpio_28_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_28
(
.O(iobuf_gpio_28_o),
.IO(gpio_28),
.I(dut_io_pads_gpio_28_o_oval),
.T(~dut_io_pads_gpio_28_o_oe)
);
assign dut_io_pads_gpio_28_i_ival = iobuf_gpio_28_o & dut_io_pads_gpio_28_o_ie;
wire iobuf_gpio_29_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_29
(
.O(iobuf_gpio_29_o),
.IO(gpio_29),
.I(dut_io_pads_gpio_29_o_oval),
.T(~dut_io_pads_gpio_29_o_oe)
);
assign dut_io_pads_gpio_29_i_ival = iobuf_gpio_29_o & dut_io_pads_gpio_29_o_ie;
wire iobuf_gpio_30_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_30
(
.O(iobuf_gpio_30_o),
.IO(gpio_30),
.I(dut_io_pads_gpio_30_o_oval),
.T(~dut_io_pads_gpio_30_o_oe)
);
assign dut_io_pads_gpio_30_i_ival = iobuf_gpio_30_o & dut_io_pads_gpio_30_o_ie;
wire iobuf_gpio_31_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_gpio_31
(
.O(iobuf_gpio_31_o),
.IO(gpio_31),
.I(dut_io_pads_gpio_31_o_oval),
.T(~dut_io_pads_gpio_31_o_oe)
);
assign dut_io_pads_gpio_31_i_ival = iobuf_gpio_31_o & dut_io_pads_gpio_31_o_ie;
wire iobuf_jtag_TCK_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TCK
(
.O(iobuf_jtag_TCK_o),
.IO(jd_2),
.I(dut_io_pads_jtag_TCK_o_oval),
.T(~dut_io_pads_jtag_TCK_o_oe)
);
assign dut_io_pads_jtag_TCK_i_ival = iobuf_jtag_TCK_o & dut_io_pads_jtag_TCK_o_ie;
PULLUP pullup_TCK (.O(jd_2));
wire iobuf_jtag_TMS_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TMS
(
.O(iobuf_jtag_TMS_o),
.IO(jd_5),
.I(dut_io_pads_jtag_TMS_o_oval),
.T(~dut_io_pads_jtag_TMS_o_oe)
);
assign dut_io_pads_jtag_TMS_i_ival = iobuf_jtag_TMS_o & dut_io_pads_jtag_TMS_o_ie;
PULLUP pullup_TMS (.O(jd_5));
wire iobuf_jtag_TDI_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDI
(
.O(iobuf_jtag_TDI_o),
.IO(jd_4),
.I(dut_io_pads_jtag_TDI_o_oval),
.T(~dut_io_pads_jtag_TDI_o_oe)
);
assign dut_io_pads_jtag_TDI_i_ival = iobuf_jtag_TDI_o & dut_io_pads_jtag_TDI_o_ie;
PULLUP pullup_TDI (.O(jd_4));
wire iobuf_jtag_TDO_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDO
(
.O(iobuf_jtag_TDO_o),
.IO(jd_0),
.I(dut_io_pads_jtag_TDO_o_oval),
.T(~dut_io_pads_jtag_TDO_o_oe)
);
assign dut_io_pads_jtag_TDO_i_ival = iobuf_jtag_TDO_o & dut_io_pads_jtag_TDO_o_ie;
wire iobuf_jtag_TRST_n_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TRST_n
(
.O(iobuf_jtag_TRST_n_o),
.IO(jd_1),
.I(dut_io_pads_jtag_TRST_n_o_oval),
.T(~dut_io_pads_jtag_TRST_n_o_oe)
);
assign dut_io_pads_jtag_TRST_n_i_ival = iobuf_jtag_TRST_n_o & dut_io_pads_jtag_TRST_n_o_ie;
PULLUP pullup_TRST_n(.O(jd_1));
assign SRST_n = jd_6;
PULLUP pullup_SRST_n(.O(SRST_n));
assign ck_io[0] = gpio_16;
assign ck_io[1] = gpio_17;
assign ck_io[2] = gpio_18;
assign ck_io[3] = gpio_19;
assign ck_io[4] = gpio_20;
assign ck_io[5] = gpio_21;
assign ck_io[6] = gpio_22;
assign ck_io[7] = gpio_23;
assign ck_io[8] = gpio_0;
assign ck_io[9] = gpio_1;
assign ck_io[10] = gpio_2;
assign ck_io[11] = gpio_3;
assign ck_io[12] = gpio_4;
assign ck_io[13] = gpio_5;
assign ck_io[14] = uart_txd_in;
assign ck_io[15] = gpio_9;
assign ck_io[16] = gpio_10;
assign ck_io[17] = gpio_11;
assign ck_io[18] = gpio_12;
assign ck_io[19] = gpio_13;
assign led0_r = dut_io_pads_gpio_1_o_oval & dut_io_pads_gpio_1_o_oe;
assign led0_g = dut_io_pads_gpio_2_o_oval & dut_io_pads_gpio_2_o_oe;
assign led0_b = dut_io_pads_gpio_3_o_oval & dut_io_pads_gpio_2_o_oe;
assign led1_r = dut_io_pads_gpio_19_o_oval & dut_io_pads_gpio_19_o_oe;
assign led1_g = dut_io_pads_gpio_21_o_oval & dut_io_pads_gpio_21_o_oe;
assign led1_b = dut_io_pads_gpio_22_o_oval & dut_io_pads_gpio_22_o_oe;
assign led2_r = dut_io_pads_gpio_11_o_oval & dut_io_pads_gpio_11_o_oe;
assign led2_g = dut_io_pads_gpio_12_o_oval & dut_io_pads_gpio_12_o_oe;
assign led2_b = dut_io_pads_gpio_13_o_oval & dut_io_pads_gpio_13_o_oe;
assign btn_0 = gpio_15;
assign btn_1 = gpio_30;
assign btn_2 = gpio_31;
assign ja_0 = gpio_25;
assign ja_1 = gpio_24;
assign ck_ss = gpio_26;
assign ck_mosi = gpio_27;
assign ck_miso = gpio_28;
assign ck_sck = gpio_29;
assign led_0 = ck_rst;
assign led_1 = SRST_n;
assign led_2 = dut_io_pads_aon_pmu_dwakeup_n_i_ival;
assign led_3 = gpio_14;
E300ArtyDevKitTop dut
(
.clock(hfclk),
.reset(1'b1),
.io_pads_jtag_TCK_i_ival(dut_io_pads_jtag_TCK_i_ival),
.io_pads_jtag_TCK_o_oval(dut_io_pads_jtag_TCK_o_oval),
.io_pads_jtag_TCK_o_oe(dut_io_pads_jtag_TCK_o_oe),
.io_pads_jtag_TCK_o_ie(dut_io_pads_jtag_TCK_o_ie),
.io_pads_jtag_TCK_o_pue(dut_io_pads_jtag_TCK_o_pue),
.io_pads_jtag_TCK_o_ds(dut_io_pads_jtag_TCK_o_ds),
.io_pads_jtag_TMS_i_ival(dut_io_pads_jtag_TMS_i_ival),
.io_pads_jtag_TMS_o_oval(dut_io_pads_jtag_TMS_o_oval),
.io_pads_jtag_TMS_o_oe(dut_io_pads_jtag_TMS_o_oe),
.io_pads_jtag_TMS_o_ie(dut_io_pads_jtag_TMS_o_ie),
.io_pads_jtag_TMS_o_pue(dut_io_pads_jtag_TMS_o_pue),
.io_pads_jtag_TMS_o_ds(dut_io_pads_jtag_TMS_o_ds),
.io_pads_jtag_TDI_i_ival(dut_io_pads_jtag_TDI_i_ival),
.io_pads_jtag_TDI_o_oval(dut_io_pads_jtag_TDI_o_oval),
.io_pads_jtag_TDI_o_oe(dut_io_pads_jtag_TDI_o_oe),
.io_pads_jtag_TDI_o_ie(dut_io_pads_jtag_TDI_o_ie),
.io_pads_jtag_TDI_o_pue(dut_io_pads_jtag_TDI_o_pue),
.io_pads_jtag_TDI_o_ds(dut_io_pads_jtag_TDI_o_ds),
.io_pads_jtag_TDO_i_ival(dut_io_pads_jtag_TDO_i_ival),
.io_pads_jtag_TDO_o_oval(dut_io_pads_jtag_TDO_o_oval),
.io_pads_jtag_TDO_o_oe(dut_io_pads_jtag_TDO_o_oe),
.io_pads_jtag_TDO_o_ie(dut_io_pads_jtag_TDO_o_ie),
.io_pads_jtag_TDO_o_pue(dut_io_pads_jtag_TDO_o_pue),
.io_pads_jtag_TDO_o_ds(dut_io_pads_jtag_TDO_o_ds),
.io_pads_jtag_TRST_n_i_ival(dut_io_pads_jtag_TRST_n_i_ival),
.io_pads_jtag_TRST_n_o_oval(dut_io_pads_jtag_TRST_n_o_oval),
.io_pads_jtag_TRST_n_o_oe(dut_io_pads_jtag_TRST_n_o_oe),
.io_pads_jtag_TRST_n_o_ie(dut_io_pads_jtag_TRST_n_o_ie),
.io_pads_jtag_TRST_n_o_pue(dut_io_pads_jtag_TRST_n_o_pue),
.io_pads_jtag_TRST_n_o_ds(dut_io_pads_jtag_TRST_n_o_ds),
.io_pads_gpio_0_i_ival(dut_io_pads_gpio_0_i_ival),
.io_pads_gpio_0_o_oval(dut_io_pads_gpio_0_o_oval),
.io_pads_gpio_0_o_oe(dut_io_pads_gpio_0_o_oe),
.io_pads_gpio_0_o_ie(dut_io_pads_gpio_0_o_ie),
.io_pads_gpio_0_o_pue(dut_io_pads_gpio_0_o_pue),
.io_pads_gpio_0_o_ds(dut_io_pads_gpio_0_o_ds),
.io_pads_gpio_1_i_ival(dut_io_pads_gpio_1_i_ival),
.io_pads_gpio_1_o_oval(dut_io_pads_gpio_1_o_oval),
.io_pads_gpio_1_o_oe(dut_io_pads_gpio_1_o_oe),
.io_pads_gpio_1_o_ie(dut_io_pads_gpio_1_o_ie),
.io_pads_gpio_1_o_pue(dut_io_pads_gpio_1_o_pue),
.io_pads_gpio_1_o_ds(dut_io_pads_gpio_1_o_ds),
.io_pads_gpio_2_i_ival(dut_io_pads_gpio_2_i_ival),
.io_pads_gpio_2_o_oval(dut_io_pads_gpio_2_o_oval),
.io_pads_gpio_2_o_oe(dut_io_pads_gpio_2_o_oe),
.io_pads_gpio_2_o_ie(dut_io_pads_gpio_2_o_ie),
.io_pads_gpio_2_o_pue(dut_io_pads_gpio_2_o_pue),
.io_pads_gpio_2_o_ds(dut_io_pads_gpio_2_o_ds),
.io_pads_gpio_3_i_ival(dut_io_pads_gpio_3_i_ival),
.io_pads_gpio_3_o_oval(dut_io_pads_gpio_3_o_oval),
.io_pads_gpio_3_o_oe(dut_io_pads_gpio_3_o_oe),
.io_pads_gpio_3_o_ie(dut_io_pads_gpio_3_o_ie),
.io_pads_gpio_3_o_pue(dut_io_pads_gpio_3_o_pue),
.io_pads_gpio_3_o_ds(dut_io_pads_gpio_3_o_ds),
.io_pads_gpio_4_i_ival(dut_io_pads_gpio_4_i_ival),
.io_pads_gpio_4_o_oval(dut_io_pads_gpio_4_o_oval),
.io_pads_gpio_4_o_oe(dut_io_pads_gpio_4_o_oe),
.io_pads_gpio_4_o_ie(dut_io_pads_gpio_4_o_ie),
.io_pads_gpio_4_o_pue(dut_io_pads_gpio_4_o_pue),
.io_pads_gpio_4_o_ds(dut_io_pads_gpio_4_o_ds),
.io_pads_gpio_5_i_ival(dut_io_pads_gpio_5_i_ival),
.io_pads_gpio_5_o_oval(dut_io_pads_gpio_5_o_oval),
.io_pads_gpio_5_o_oe(dut_io_pads_gpio_5_o_oe),
.io_pads_gpio_5_o_ie(dut_io_pads_gpio_5_o_ie),
.io_pads_gpio_5_o_pue(dut_io_pads_gpio_5_o_pue),
.io_pads_gpio_5_o_ds(dut_io_pads_gpio_5_o_ds),
.io_pads_gpio_6_i_ival(dut_io_pads_gpio_6_i_ival),
.io_pads_gpio_6_o_oval(dut_io_pads_gpio_6_o_oval),
.io_pads_gpio_6_o_oe(dut_io_pads_gpio_6_o_oe),
.io_pads_gpio_6_o_ie(dut_io_pads_gpio_6_o_ie),
.io_pads_gpio_6_o_pue(dut_io_pads_gpio_6_o_pue),
.io_pads_gpio_6_o_ds(dut_io_pads_gpio_6_o_ds),
.io_pads_gpio_7_i_ival(dut_io_pads_gpio_7_i_ival),
.io_pads_gpio_7_o_oval(dut_io_pads_gpio_7_o_oval),
.io_pads_gpio_7_o_oe(dut_io_pads_gpio_7_o_oe),
.io_pads_gpio_7_o_ie(dut_io_pads_gpio_7_o_ie),
.io_pads_gpio_7_o_pue(dut_io_pads_gpio_7_o_pue),
.io_pads_gpio_7_o_ds(dut_io_pads_gpio_7_o_ds),
.io_pads_gpio_8_i_ival(dut_io_pads_gpio_8_i_ival),
.io_pads_gpio_8_o_oval(dut_io_pads_gpio_8_o_oval),
.io_pads_gpio_8_o_oe(dut_io_pads_gpio_8_o_oe),
.io_pads_gpio_8_o_ie(dut_io_pads_gpio_8_o_ie),
.io_pads_gpio_8_o_pue(dut_io_pads_gpio_8_o_pue),
.io_pads_gpio_8_o_ds(dut_io_pads_gpio_8_o_ds),
.io_pads_gpio_9_i_ival(dut_io_pads_gpio_9_i_ival),
.io_pads_gpio_9_o_oval(dut_io_pads_gpio_9_o_oval),
.io_pads_gpio_9_o_oe(dut_io_pads_gpio_9_o_oe),
.io_pads_gpio_9_o_ie(dut_io_pads_gpio_9_o_ie),
.io_pads_gpio_9_o_pue(dut_io_pads_gpio_9_o_pue),
.io_pads_gpio_9_o_ds(dut_io_pads_gpio_9_o_ds),
.io_pads_gpio_10_i_ival(dut_io_pads_gpio_10_i_ival),
.io_pads_gpio_10_o_oval(dut_io_pads_gpio_10_o_oval),
.io_pads_gpio_10_o_oe(dut_io_pads_gpio_10_o_oe),
.io_pads_gpio_10_o_ie(dut_io_pads_gpio_10_o_ie),
.io_pads_gpio_10_o_pue(dut_io_pads_gpio_10_o_pue),
.io_pads_gpio_10_o_ds(dut_io_pads_gpio_10_o_ds),
.io_pads_gpio_11_i_ival(dut_io_pads_gpio_11_i_ival),
.io_pads_gpio_11_o_oval(dut_io_pads_gpio_11_o_oval),
.io_pads_gpio_11_o_oe(dut_io_pads_gpio_11_o_oe),
.io_pads_gpio_11_o_ie(dut_io_pads_gpio_11_o_ie),
.io_pads_gpio_11_o_pue(dut_io_pads_gpio_11_o_pue),
.io_pads_gpio_11_o_ds(dut_io_pads_gpio_11_o_ds),
.io_pads_gpio_12_i_ival(dut_io_pads_gpio_12_i_ival),
.io_pads_gpio_12_o_oval(dut_io_pads_gpio_12_o_oval),
.io_pads_gpio_12_o_oe(dut_io_pads_gpio_12_o_oe),
.io_pads_gpio_12_o_ie(dut_io_pads_gpio_12_o_ie),
.io_pads_gpio_12_o_pue(dut_io_pads_gpio_12_o_pue),
.io_pads_gpio_12_o_ds(dut_io_pads_gpio_12_o_ds),
.io_pads_gpio_13_i_ival(dut_io_pads_gpio_13_i_ival),
.io_pads_gpio_13_o_oval(dut_io_pads_gpio_13_o_oval),
.io_pads_gpio_13_o_oe(dut_io_pads_gpio_13_o_oe),
.io_pads_gpio_13_o_ie(dut_io_pads_gpio_13_o_ie),
.io_pads_gpio_13_o_pue(dut_io_pads_gpio_13_o_pue),
.io_pads_gpio_13_o_ds(dut_io_pads_gpio_13_o_ds),
.io_pads_gpio_14_i_ival(dut_io_pads_gpio_14_i_ival),
.io_pads_gpio_14_o_oval(dut_io_pads_gpio_14_o_oval),
.io_pads_gpio_14_o_oe(dut_io_pads_gpio_14_o_oe),
.io_pads_gpio_14_o_ie(dut_io_pads_gpio_14_o_ie),
.io_pads_gpio_14_o_pue(dut_io_pads_gpio_14_o_pue),
.io_pads_gpio_14_o_ds(dut_io_pads_gpio_14_o_ds),
.io_pads_gpio_15_i_ival(dut_io_pads_gpio_15_i_ival),
.io_pads_gpio_15_o_oval(dut_io_pads_gpio_15_o_oval),
.io_pads_gpio_15_o_oe(dut_io_pads_gpio_15_o_oe),
.io_pads_gpio_15_o_ie(dut_io_pads_gpio_15_o_ie),
.io_pads_gpio_15_o_pue(dut_io_pads_gpio_15_o_pue),
.io_pads_gpio_15_o_ds(dut_io_pads_gpio_15_o_ds),
.io_pads_gpio_16_i_ival(dut_io_pads_gpio_16_i_ival),
.io_pads_gpio_16_o_oval(dut_io_pads_gpio_16_o_oval),
.io_pads_gpio_16_o_oe(dut_io_pads_gpio_16_o_oe),
.io_pads_gpio_16_o_ie(dut_io_pads_gpio_16_o_ie),
.io_pads_gpio_16_o_pue(dut_io_pads_gpio_16_o_pue),
.io_pads_gpio_16_o_ds(dut_io_pads_gpio_16_o_ds),
.io_pads_gpio_17_i_ival(dut_io_pads_gpio_17_i_ival),
.io_pads_gpio_17_o_oval(dut_io_pads_gpio_17_o_oval),
.io_pads_gpio_17_o_oe(dut_io_pads_gpio_17_o_oe),
.io_pads_gpio_17_o_ie(dut_io_pads_gpio_17_o_ie),
.io_pads_gpio_17_o_pue(dut_io_pads_gpio_17_o_pue),
.io_pads_gpio_17_o_ds(dut_io_pads_gpio_17_o_ds),
.io_pads_gpio_18_i_ival(dut_io_pads_gpio_18_i_ival),
.io_pads_gpio_18_o_oval(dut_io_pads_gpio_18_o_oval),
.io_pads_gpio_18_o_oe(dut_io_pads_gpio_18_o_oe),
.io_pads_gpio_18_o_ie(dut_io_pads_gpio_18_o_ie),
.io_pads_gpio_18_o_pue(dut_io_pads_gpio_18_o_pue),
.io_pads_gpio_18_o_ds(dut_io_pads_gpio_18_o_ds),
.io_pads_gpio_19_i_ival(dut_io_pads_gpio_19_i_ival),
.io_pads_gpio_19_o_oval(dut_io_pads_gpio_19_o_oval),
.io_pads_gpio_19_o_oe(dut_io_pads_gpio_19_o_oe),
.io_pads_gpio_19_o_ie(dut_io_pads_gpio_19_o_ie),
.io_pads_gpio_19_o_pue(dut_io_pads_gpio_19_o_pue),
.io_pads_gpio_19_o_ds(dut_io_pads_gpio_19_o_ds),
.io_pads_gpio_20_i_ival(dut_io_pads_gpio_20_i_ival),
.io_pads_gpio_20_o_oval(dut_io_pads_gpio_20_o_oval),
.io_pads_gpio_20_o_oe(dut_io_pads_gpio_20_o_oe),
.io_pads_gpio_20_o_ie(dut_io_pads_gpio_20_o_ie),
.io_pads_gpio_20_o_pue(dut_io_pads_gpio_20_o_pue),
.io_pads_gpio_20_o_ds(dut_io_pads_gpio_20_o_ds),
.io_pads_gpio_21_i_ival(dut_io_pads_gpio_21_i_ival),
.io_pads_gpio_21_o_oval(dut_io_pads_gpio_21_o_oval),
.io_pads_gpio_21_o_oe(dut_io_pads_gpio_21_o_oe),
.io_pads_gpio_21_o_ie(dut_io_pads_gpio_21_o_ie),
.io_pads_gpio_21_o_pue(dut_io_pads_gpio_21_o_pue),
.io_pads_gpio_21_o_ds(dut_io_pads_gpio_21_o_ds),
.io_pads_gpio_22_i_ival(dut_io_pads_gpio_22_i_ival),
.io_pads_gpio_22_o_oval(dut_io_pads_gpio_22_o_oval),
.io_pads_gpio_22_o_oe(dut_io_pads_gpio_22_o_oe),
.io_pads_gpio_22_o_ie(dut_io_pads_gpio_22_o_ie),
.io_pads_gpio_22_o_pue(dut_io_pads_gpio_22_o_pue),
.io_pads_gpio_22_o_ds(dut_io_pads_gpio_22_o_ds),
.io_pads_gpio_23_i_ival(dut_io_pads_gpio_23_i_ival),
.io_pads_gpio_23_o_oval(dut_io_pads_gpio_23_o_oval),
.io_pads_gpio_23_o_oe(dut_io_pads_gpio_23_o_oe),
.io_pads_gpio_23_o_ie(dut_io_pads_gpio_23_o_ie),
.io_pads_gpio_23_o_pue(dut_io_pads_gpio_23_o_pue),
.io_pads_gpio_23_o_ds(dut_io_pads_gpio_23_o_ds),
.io_pads_gpio_24_i_ival(dut_io_pads_gpio_24_i_ival),
.io_pads_gpio_24_o_oval(dut_io_pads_gpio_24_o_oval),
.io_pads_gpio_24_o_oe(dut_io_pads_gpio_24_o_oe),
.io_pads_gpio_24_o_ie(dut_io_pads_gpio_24_o_ie),
.io_pads_gpio_24_o_pue(dut_io_pads_gpio_24_o_pue),
.io_pads_gpio_24_o_ds(dut_io_pads_gpio_24_o_ds),
.io_pads_gpio_25_i_ival(dut_io_pads_gpio_25_i_ival),
.io_pads_gpio_25_o_oval(dut_io_pads_gpio_25_o_oval),
.io_pads_gpio_25_o_oe(dut_io_pads_gpio_25_o_oe),
.io_pads_gpio_25_o_ie(dut_io_pads_gpio_25_o_ie),
.io_pads_gpio_25_o_pue(dut_io_pads_gpio_25_o_pue),
.io_pads_gpio_25_o_ds(dut_io_pads_gpio_25_o_ds),
.io_pads_gpio_26_i_ival(dut_io_pads_gpio_26_i_ival),
.io_pads_gpio_26_o_oval(dut_io_pads_gpio_26_o_oval),
.io_pads_gpio_26_o_oe(dut_io_pads_gpio_26_o_oe),
.io_pads_gpio_26_o_ie(dut_io_pads_gpio_26_o_ie),
.io_pads_gpio_26_o_pue(dut_io_pads_gpio_26_o_pue),
.io_pads_gpio_26_o_ds(dut_io_pads_gpio_26_o_ds),
.io_pads_gpio_27_i_ival(dut_io_pads_gpio_27_i_ival),
.io_pads_gpio_27_o_oval(dut_io_pads_gpio_27_o_oval),
.io_pads_gpio_27_o_oe(dut_io_pads_gpio_27_o_oe),
.io_pads_gpio_27_o_ie(dut_io_pads_gpio_27_o_ie),
.io_pads_gpio_27_o_pue(dut_io_pads_gpio_27_o_pue),
.io_pads_gpio_27_o_ds(dut_io_pads_gpio_27_o_ds),
.io_pads_gpio_28_i_ival(dut_io_pads_gpio_28_i_ival),
.io_pads_gpio_28_o_oval(dut_io_pads_gpio_28_o_oval),
.io_pads_gpio_28_o_oe(dut_io_pads_gpio_28_o_oe),
.io_pads_gpio_28_o_ie(dut_io_pads_gpio_28_o_ie),
.io_pads_gpio_28_o_pue(dut_io_pads_gpio_28_o_pue),
.io_pads_gpio_28_o_ds(dut_io_pads_gpio_28_o_ds),
.io_pads_gpio_29_i_ival(dut_io_pads_gpio_29_i_ival),
.io_pads_gpio_29_o_oval(dut_io_pads_gpio_29_o_oval),
.io_pads_gpio_29_o_oe(dut_io_pads_gpio_29_o_oe),
.io_pads_gpio_29_o_ie(dut_io_pads_gpio_29_o_ie),
.io_pads_gpio_29_o_pue(dut_io_pads_gpio_29_o_pue),
.io_pads_gpio_29_o_ds(dut_io_pads_gpio_29_o_ds),
.io_pads_gpio_30_i_ival(dut_io_pads_gpio_30_i_ival),
.io_pads_gpio_30_o_oval(dut_io_pads_gpio_30_o_oval),
.io_pads_gpio_30_o_oe(dut_io_pads_gpio_30_o_oe),
.io_pads_gpio_30_o_ie(dut_io_pads_gpio_30_o_ie),
.io_pads_gpio_30_o_pue(dut_io_pads_gpio_30_o_pue),
.io_pads_gpio_30_o_ds(dut_io_pads_gpio_30_o_ds),
.io_pads_gpio_31_i_ival(dut_io_pads_gpio_31_i_ival),
.io_pads_gpio_31_o_oval(dut_io_pads_gpio_31_o_oval),
.io_pads_gpio_31_o_oe(dut_io_pads_gpio_31_o_oe),
.io_pads_gpio_31_o_ie(dut_io_pads_gpio_31_o_ie),
.io_pads_gpio_31_o_pue(dut_io_pads_gpio_31_o_pue),
.io_pads_gpio_31_o_ds(dut_io_pads_gpio_31_o_ds),
.io_pads_qspi_sck_i_ival(dut_io_pads_qspi_sck_i_ival),
.io_pads_qspi_sck_o_oval(dut_io_pads_qspi_sck_o_oval),
.io_pads_qspi_sck_o_oe(dut_io_pads_qspi_sck_o_oe),
.io_pads_qspi_sck_o_ie(dut_io_pads_qspi_sck_o_ie),
.io_pads_qspi_sck_o_pue(dut_io_pads_qspi_sck_o_pue),
.io_pads_qspi_sck_o_ds(dut_io_pads_qspi_sck_o_ds),
.io_pads_qspi_dq_0_i_ival(dut_io_pads_qspi_dq_0_i_ival),
.io_pads_qspi_dq_0_o_oval(dut_io_pads_qspi_dq_0_o_oval),
.io_pads_qspi_dq_0_o_oe(dut_io_pads_qspi_dq_0_o_oe),
.io_pads_qspi_dq_0_o_ie(dut_io_pads_qspi_dq_0_o_ie),
.io_pads_qspi_dq_0_o_pue(dut_io_pads_qspi_dq_0_o_pue),
.io_pads_qspi_dq_0_o_ds(dut_io_pads_qspi_dq_0_o_ds),
.io_pads_qspi_dq_1_i_ival(dut_io_pads_qspi_dq_1_i_ival),
.io_pads_qspi_dq_1_o_oval(dut_io_pads_qspi_dq_1_o_oval),
.io_pads_qspi_dq_1_o_oe(dut_io_pads_qspi_dq_1_o_oe),
.io_pads_qspi_dq_1_o_ie(dut_io_pads_qspi_dq_1_o_ie),
.io_pads_qspi_dq_1_o_pue(dut_io_pads_qspi_dq_1_o_pue),
.io_pads_qspi_dq_1_o_ds(dut_io_pads_qspi_dq_1_o_ds),
.io_pads_qspi_dq_2_i_ival(dut_io_pads_qspi_dq_2_i_ival),
.io_pads_qspi_dq_2_o_oval(dut_io_pads_qspi_dq_2_o_oval),
.io_pads_qspi_dq_2_o_oe(dut_io_pads_qspi_dq_2_o_oe),
.io_pads_qspi_dq_2_o_ie(dut_io_pads_qspi_dq_2_o_ie),
.io_pads_qspi_dq_2_o_pue(dut_io_pads_qspi_dq_2_o_pue),
.io_pads_qspi_dq_2_o_ds(dut_io_pads_qspi_dq_2_o_ds),
.io_pads_qspi_dq_3_i_ival(dut_io_pads_qspi_dq_3_i_ival),
.io_pads_qspi_dq_3_o_oval(dut_io_pads_qspi_dq_3_o_oval),
.io_pads_qspi_dq_3_o_oe(dut_io_pads_qspi_dq_3_o_oe),
.io_pads_qspi_dq_3_o_ie(dut_io_pads_qspi_dq_3_o_ie),
.io_pads_qspi_dq_3_o_pue(dut_io_pads_qspi_dq_3_o_pue),
.io_pads_qspi_dq_3_o_ds(dut_io_pads_qspi_dq_3_o_ds),
.io_pads_qspi_cs_0_i_ival(dut_io_pads_qspi_cs_0_i_ival),
.io_pads_qspi_cs_0_o_oval(dut_io_pads_qspi_cs_0_o_oval),
.io_pads_qspi_cs_0_o_oe(dut_io_pads_qspi_cs_0_o_oe),
.io_pads_qspi_cs_0_o_ie(dut_io_pads_qspi_cs_0_o_ie),
.io_pads_qspi_cs_0_o_pue(dut_io_pads_qspi_cs_0_o_pue),
.io_pads_qspi_cs_0_o_ds(dut_io_pads_qspi_cs_0_o_ds),
.io_pads_aon_erst_n_i_ival(dut_io_pads_aon_erst_n_i_ival),
.io_pads_aon_erst_n_o_oval(dut_io_pads_aon_erst_n_o_oval),
.io_pads_aon_erst_n_o_oe(dut_io_pads_aon_erst_n_o_oe),
.io_pads_aon_erst_n_o_ie(dut_io_pads_aon_erst_n_o_ie),
.io_pads_aon_erst_n_o_pue(dut_io_pads_aon_erst_n_o_pue),
.io_pads_aon_erst_n_o_ds(dut_io_pads_aon_erst_n_o_ds),
.io_pads_aon_lfextclk_i_ival(dut_io_pads_aon_lfextclk_i_ival),
.io_pads_aon_lfextclk_o_oval(dut_io_pads_aon_lfextclk_o_oval),
.io_pads_aon_lfextclk_o_oe(dut_io_pads_aon_lfextclk_o_oe),
.io_pads_aon_lfextclk_o_ie(dut_io_pads_aon_lfextclk_o_ie),
.io_pads_aon_lfextclk_o_pue(dut_io_pads_aon_lfextclk_o_pue),
.io_pads_aon_lfextclk_o_ds(dut_io_pads_aon_lfextclk_o_ds),
.io_pads_aon_pmu_dwakeup_n_i_ival(dut_io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_dwakeup_n_o_oval(dut_io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_aon_pmu_dwakeup_n_o_oe(dut_io_pads_aon_pmu_dwakeup_n_o_oe),
.io_pads_aon_pmu_dwakeup_n_o_ie(dut_io_pads_aon_pmu_dwakeup_n_o_ie),
.io_pads_aon_pmu_dwakeup_n_o_pue(dut_io_pads_aon_pmu_dwakeup_n_o_pue),
.io_pads_aon_pmu_dwakeup_n_o_ds(dut_io_pads_aon_pmu_dwakeup_n_o_ds),
.io_pads_aon_pmu_vddpaden_i_ival(dut_io_pads_aon_pmu_vddpaden_i_ival),
.io_pads_aon_pmu_vddpaden_o_oval(dut_io_pads_aon_pmu_vddpaden_o_oval),
.io_pads_aon_pmu_vddpaden_o_oe(dut_io_pads_aon_pmu_vddpaden_o_oe),
.io_pads_aon_pmu_vddpaden_o_ie(dut_io_pads_aon_pmu_vddpaden_o_ie),
.io_pads_aon_pmu_vddpaden_o_pue(dut_io_pads_aon_pmu_vddpaden_o_pue),
.io_pads_aon_pmu_vddpaden_o_ds(dut_io_pads_aon_pmu_vddpaden_o_ds)
);
wire iobuf_dwakeup_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_dwakeup_n
(
.O(iobuf_dwakeup_o),
.IO(btn_3),
.I(~dut_io_pads_aon_pmu_dwakeup_n_o_oval),
.T(~dut_io_pads_aon_pmu_dwakeup_n_o_oe)
);
assign dut_io_pads_aon_pmu_dwakeup_n_i_ival = (~iobuf_dwakeup_o) & dut_io_pads_aon_pmu_dwakeup_n_o_ie;
assign dut_io_pads_aon_erst_n_i_ival = ~reset_periph;
assign dut_io_pads_aon_lfextclk_i_ival = slowclk;
assign dut_io_pads_aon_pmu_vddpaden_i_ival = 1'b1;
assign qspi_cs = dut_io_pads_qspi_cs_0_o_oval;
assign qspi_ui_dq_o = {
dut_io_pads_qspi_dq_3_o_oval,
dut_io_pads_qspi_dq_2_o_oval,
dut_io_pads_qspi_dq_1_o_oval,
dut_io_pads_qspi_dq_0_o_oval
};
assign qspi_ui_dq_oe = {
dut_io_pads_qspi_dq_3_o_oe,
dut_io_pads_qspi_dq_2_o_oe,
dut_io_pads_qspi_dq_1_o_oe,
dut_io_pads_qspi_dq_0_o_oe
};
assign dut_io_pads_qspi_dq_0_i_ival = qspi_ui_dq_i[0];
assign dut_io_pads_qspi_dq_1_i_ival = qspi_ui_dq_i[1];
assign dut_io_pads_qspi_dq_2_i_ival = qspi_ui_dq_i[2];
assign dut_io_pads_qspi_dq_3_i_ival = qspi_ui_dq_i[3];
assign qspi_sck = dut_io_pads_qspi_sck_o_oval;
endmodule | 0 |
142,247 | data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v | 98,489,923 | system.v | v | 1,494 | 134 | [] | [] | [] | [(3, 1464), (1467, 1493)] | null | null | 1: b"%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:372: Cannot find file containing module: 'mmcm'\n mmcm ip_mmcm\n ^~~~\n ... Looked in:\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm.v\n data/full_repos/permissive/98489923/fpga/e300artydevkit/src,data/full_repos/permissive/98489923/mmcm.sv\n mmcm\n mmcm.v\n mmcm.sv\n obj_dir/mmcm\n obj_dir/mmcm.v\n obj_dir/mmcm.sv\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:389: Cannot find file containing module: 'reset_sys'\n reset_sys ip_reset_sys\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:409: Cannot find file containing module: 'PULLUP'\n PULLUP qspi_pullup[3:0]\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:414: Cannot find file containing module: 'IOBUF'\n IOBUF qspi_iobuf[3:0]\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:459: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:476: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:493: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:510: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:527: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:544: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:567: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:584: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:601: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:618: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:635: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:652: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:669: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:686: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:705: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:723: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:740: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:757: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:774: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:791: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:808: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:825: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:842: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:859: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:876: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:893: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:910: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:927: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:944: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:964: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:979: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TCK (.O(jd_2));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:982: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:997: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TMS (.O(jd_5));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1000: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1015: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TDI (.O(jd_4));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1018: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1035: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1050: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_TRST_n(.O(jd_1));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1054: Cannot find file containing module: 'PULLUP'\n PULLUP pullup_SRST_n(.O(SRST_n));\n ^~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1134: Cannot find file containing module: 'E300ArtyDevKitTop'\n E300ArtyDevKitTop dut\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98489923/fpga/e300artydevkit/src/system.v:1425: Cannot find file containing module: 'IOBUF'\n IOBUF\n ^~~~~\n%Error: Exiting due to 45 error(s)\n" | 313,441 | module | module clkdivider
(
input wire clk,
input wire reset,
output reg clk_out
);
reg [7:0] counter;
always @(posedge clk)
begin
if (reset)
begin
counter <= 8'd0;
clk_out <= 1'b0;
end
else if (counter == 8'hff)
begin
counter <= 8'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule | module clkdivider
(
input wire clk,
input wire reset,
output reg clk_out
); |
reg [7:0] counter;
always @(posedge clk)
begin
if (reset)
begin
counter <= 8'd0;
clk_out <= 1'b0;
end
else if (counter == 8'hff)
begin
counter <= 8'd0;
clk_out <= ~clk_out;
end
else
begin
counter <= counter+1;
end
end
endmodule | 0 |
142,248 | data/full_repos/permissive/98489923/fpga/u500vc707devkit/src/system.v | 98,489,923 | system.v | v | 169 | 52 | [] | [] | [] | [(5, 166)] | null | null | 1: b"%Error: data/full_repos/permissive/98489923/fpga/u500vc707devkit/src/system.v:60: Cannot find file containing module: 'U500VC707DevKitTop'\nU500VC707DevKitTop top\n^~~~~~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98489923/fpga/u500vc707devkit/src,data/full_repos/permissive/98489923/U500VC707DevKitTop\n data/full_repos/permissive/98489923/fpga/u500vc707devkit/src,data/full_repos/permissive/98489923/U500VC707DevKitTop.v\n data/full_repos/permissive/98489923/fpga/u500vc707devkit/src,data/full_repos/permissive/98489923/U500VC707DevKitTop.sv\n U500VC707DevKitTop\n U500VC707DevKitTop.v\n U500VC707DevKitTop.sv\n obj_dir/U500VC707DevKitTop\n obj_dir/U500VC707DevKitTop.v\n obj_dir/U500VC707DevKitTop.sv\n%Error: data/full_repos/permissive/98489923/fpga/u500vc707devkit/src/system.v:140: Cannot find file containing module: 'sdio_spi_bridge'\n sdio_spi_bridge ip_sdio_spi\n ^~~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 313,443 | module | module system
(
input wire sys_diff_clock_clk_n,
input wire sys_diff_clock_clk_p,
input wire reset,
output wire [13:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_cas_n,
output wire [0:0] ddr3_ck_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_cke,
output wire [0:0] ddr3_cs_n,
output wire [7:0] ddr3_dm,
inout wire [63:0] ddr3_dq,
inout wire [7:0] ddr3_dqs_n,
inout wire [7:0] ddr3_dqs_p,
output wire [0:0] ddr3_odt,
output wire ddr3_ras_n,
output wire ddr3_reset_n,
output wire ddr3_we_n,
output wire [7:0] led,
output wire uart_tx,
input wire uart_rx,
output wire uart_rtsn,
input wire uart_ctsn,
output wire sdio_clk,
inout wire sdio_cmd,
inout wire [3:0] sdio_dat,
input wire jtag_TCK,
input wire jtag_TMS,
input wire jtag_TDI,
output wire jtag_TDO,
output wire [0:0] pci_exp_txp,
output wire [0:0] pci_exp_txn,
input wire [0:0] pci_exp_rxp,
input wire [0:0] pci_exp_rxn,
input wire pci_exp_refclk_rxp,
input wire pci_exp_refclk_rxn
);
reg [1:0] uart_rx_sync;
wire [3:0] sd_spi_dq_i;
wire [3:0] sd_spi_dq_o;
wire sd_spi_sck;
wire sd_spi_cs;
wire top_clock,top_reset;
U500VC707DevKitTop top
(
.io_uarts_0_rxd(uart_rx_sync[1]),
.io_uarts_0_txd(uart_tx),
.io_spis_0_sck(sd_spi_sck),
.io_spis_0_dq_0_i(sd_spi_dq_i[0]),
.io_spis_0_dq_1_i(sd_spi_dq_i[1]),
.io_spis_0_dq_2_i(sd_spi_dq_i[2]),
.io_spis_0_dq_3_i(sd_spi_dq_i[3]),
.io_spis_0_dq_0_o(sd_spi_dq_o[0]),
.io_spis_0_dq_1_o(sd_spi_dq_o[1]),
.io_spis_0_dq_2_o(sd_spi_dq_o[2]),
.io_spis_0_dq_3_o(sd_spi_dq_o[3]),
.io_spis_0_dq_0_oe(),
.io_spis_0_dq_1_oe(),
.io_spis_0_dq_2_oe(),
.io_spis_0_dq_3_oe(),
.io_spis_0_cs_0(sd_spi_cs),
.io_gpio_pins_0_i_ival(1'b0),
.io_gpio_pins_1_i_ival(1'b0),
.io_gpio_pins_2_i_ival(1'b0),
.io_gpio_pins_3_i_ival(1'b0),
.io_gpio_pins_0_o_oval(led[0]),
.io_gpio_pins_1_o_oval(led[1]),
.io_gpio_pins_2_o_oval(led[2]),
.io_gpio_pins_3_o_oval(led[3]),
.io_gpio_pins_0_o_oe(),
.io_gpio_pins_1_o_oe(),
.io_gpio_pins_2_o_oe(),
.io_gpio_pins_3_o_oe(),
.io_gpio_pins_0_o_pue(),
.io_gpio_pins_1_o_pue(),
.io_gpio_pins_2_o_pue(),
.io_gpio_pins_3_o_pue(),
.io_gpio_pins_0_o_ds(),
.io_gpio_pins_1_o_ds(),
.io_gpio_pins_2_o_ds(),
.io_gpio_pins_3_o_ds(),
.io_jtag_TRST(1'b0),
.io_jtag_TCK(jtag_TCK),
.io_jtag_TMS(jtag_TMS),
.io_jtag_TDI(jtag_TDI),
.io_jtag_DRV_TDO(),
.io_jtag_TDO(jtag_TDO),
.io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
.io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
.io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
.io_xilinxvc707mig_ddr3_addr(ddr3_addr),
.io_xilinxvc707mig_ddr3_ba(ddr3_ba),
.io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
.io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
.io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
.io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
.io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
.io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
.io_xilinxvc707mig_ddr3_cke(ddr3_cke),
.io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
.io_xilinxvc707mig_ddr3_dm(ddr3_dm),
.io_xilinxvc707mig_ddr3_odt(ddr3_odt),
.io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
.io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
.io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
.io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
.io_pcie_refclk_p(pci_exp_refclk_rxp),
.io_pcie_refclk_n(pci_exp_refclk_rxn),
.io_sys_clk_p(sys_diff_clock_clk_p),
.io_sys_clk_n(sys_diff_clock_clk_n),
.io_sys_reset(reset),
.io_core_clock(top_clock),
.io_core_reset(top_reset)
);
sdio_spi_bridge ip_sdio_spi
(
.clk(top_clock),
.reset(top_reset),
.sd_cmd(sdio_cmd),
.sd_dat(sdio_dat),
.sd_sck(sdio_clk),
.spi_sck(sd_spi_sck),
.spi_dq_o(sd_spi_dq_o),
.spi_dq_i(sd_spi_dq_i),
.spi_cs(sd_spi_cs)
);
assign uart_rtsn =1'b0;
always @(posedge top_clock) begin
if (top_reset) begin
uart_rx_sync <= 2'b11;
end else begin
uart_rx_sync[0] <= uart_rx;
uart_rx_sync[1] <= uart_rx_sync[0];
end
end
assign led[7:4] = 4'b0000;
endmodule | module system
(
input wire sys_diff_clock_clk_n,
input wire sys_diff_clock_clk_p,
input wire reset,
output wire [13:0] ddr3_addr,
output wire [2:0] ddr3_ba,
output wire ddr3_cas_n,
output wire [0:0] ddr3_ck_n,
output wire [0:0] ddr3_ck_p,
output wire [0:0] ddr3_cke,
output wire [0:0] ddr3_cs_n,
output wire [7:0] ddr3_dm,
inout wire [63:0] ddr3_dq,
inout wire [7:0] ddr3_dqs_n,
inout wire [7:0] ddr3_dqs_p,
output wire [0:0] ddr3_odt,
output wire ddr3_ras_n,
output wire ddr3_reset_n,
output wire ddr3_we_n,
output wire [7:0] led,
output wire uart_tx,
input wire uart_rx,
output wire uart_rtsn,
input wire uart_ctsn,
output wire sdio_clk,
inout wire sdio_cmd,
inout wire [3:0] sdio_dat,
input wire jtag_TCK,
input wire jtag_TMS,
input wire jtag_TDI,
output wire jtag_TDO,
output wire [0:0] pci_exp_txp,
output wire [0:0] pci_exp_txn,
input wire [0:0] pci_exp_rxp,
input wire [0:0] pci_exp_rxn,
input wire pci_exp_refclk_rxp,
input wire pci_exp_refclk_rxn
); |
reg [1:0] uart_rx_sync;
wire [3:0] sd_spi_dq_i;
wire [3:0] sd_spi_dq_o;
wire sd_spi_sck;
wire sd_spi_cs;
wire top_clock,top_reset;
U500VC707DevKitTop top
(
.io_uarts_0_rxd(uart_rx_sync[1]),
.io_uarts_0_txd(uart_tx),
.io_spis_0_sck(sd_spi_sck),
.io_spis_0_dq_0_i(sd_spi_dq_i[0]),
.io_spis_0_dq_1_i(sd_spi_dq_i[1]),
.io_spis_0_dq_2_i(sd_spi_dq_i[2]),
.io_spis_0_dq_3_i(sd_spi_dq_i[3]),
.io_spis_0_dq_0_o(sd_spi_dq_o[0]),
.io_spis_0_dq_1_o(sd_spi_dq_o[1]),
.io_spis_0_dq_2_o(sd_spi_dq_o[2]),
.io_spis_0_dq_3_o(sd_spi_dq_o[3]),
.io_spis_0_dq_0_oe(),
.io_spis_0_dq_1_oe(),
.io_spis_0_dq_2_oe(),
.io_spis_0_dq_3_oe(),
.io_spis_0_cs_0(sd_spi_cs),
.io_gpio_pins_0_i_ival(1'b0),
.io_gpio_pins_1_i_ival(1'b0),
.io_gpio_pins_2_i_ival(1'b0),
.io_gpio_pins_3_i_ival(1'b0),
.io_gpio_pins_0_o_oval(led[0]),
.io_gpio_pins_1_o_oval(led[1]),
.io_gpio_pins_2_o_oval(led[2]),
.io_gpio_pins_3_o_oval(led[3]),
.io_gpio_pins_0_o_oe(),
.io_gpio_pins_1_o_oe(),
.io_gpio_pins_2_o_oe(),
.io_gpio_pins_3_o_oe(),
.io_gpio_pins_0_o_pue(),
.io_gpio_pins_1_o_pue(),
.io_gpio_pins_2_o_pue(),
.io_gpio_pins_3_o_pue(),
.io_gpio_pins_0_o_ds(),
.io_gpio_pins_1_o_ds(),
.io_gpio_pins_2_o_ds(),
.io_gpio_pins_3_o_ds(),
.io_jtag_TRST(1'b0),
.io_jtag_TCK(jtag_TCK),
.io_jtag_TMS(jtag_TMS),
.io_jtag_TDI(jtag_TDI),
.io_jtag_DRV_TDO(),
.io_jtag_TDO(jtag_TDO),
.io_xilinxvc707mig__inout_ddr3_dq(ddr3_dq),
.io_xilinxvc707mig__inout_ddr3_dqs_n(ddr3_dqs_n),
.io_xilinxvc707mig__inout_ddr3_dqs_p(ddr3_dqs_p),
.io_xilinxvc707mig_ddr3_addr(ddr3_addr),
.io_xilinxvc707mig_ddr3_ba(ddr3_ba),
.io_xilinxvc707mig_ddr3_ras_n(ddr3_ras_n),
.io_xilinxvc707mig_ddr3_cas_n(ddr3_cas_n),
.io_xilinxvc707mig_ddr3_we_n(ddr3_we_n),
.io_xilinxvc707mig_ddr3_reset_n(ddr3_reset_n),
.io_xilinxvc707mig_ddr3_ck_p(ddr3_ck_p),
.io_xilinxvc707mig_ddr3_ck_n(ddr3_ck_n),
.io_xilinxvc707mig_ddr3_cke(ddr3_cke),
.io_xilinxvc707mig_ddr3_cs_n(ddr3_cs_n),
.io_xilinxvc707mig_ddr3_dm(ddr3_dm),
.io_xilinxvc707mig_ddr3_odt(ddr3_odt),
.io_xilinxvc707pcie_pci_exp_txp(pci_exp_txp),
.io_xilinxvc707pcie_pci_exp_txn(pci_exp_txn),
.io_xilinxvc707pcie_pci_exp_rxp(pci_exp_rxp),
.io_xilinxvc707pcie_pci_exp_rxn(pci_exp_rxn),
.io_pcie_refclk_p(pci_exp_refclk_rxp),
.io_pcie_refclk_n(pci_exp_refclk_rxn),
.io_sys_clk_p(sys_diff_clock_clk_p),
.io_sys_clk_n(sys_diff_clock_clk_n),
.io_sys_reset(reset),
.io_core_clock(top_clock),
.io_core_reset(top_reset)
);
sdio_spi_bridge ip_sdio_spi
(
.clk(top_clock),
.reset(top_reset),
.sd_cmd(sdio_cmd),
.sd_dat(sdio_dat),
.sd_sck(sdio_clk),
.spi_sck(sd_spi_sck),
.spi_dq_o(sd_spi_dq_o),
.spi_dq_i(sd_spi_dq_i),
.spi_cs(sd_spi_cs)
);
assign uart_rtsn =1'b0;
always @(posedge top_clock) begin
if (top_reset) begin
uart_rx_sync <= 2'b11;
end else begin
uart_rx_sync[0] <= uart_rx;
uart_rx_sync[1] <= uart_rx_sync[0];
end
end
assign led[7:4] = 4'b0000;
endmodule | 0 |
142,249 | data/full_repos/permissive/98490156/demo.v | 98,490,156 | demo.v | v | 88 | 61 | [] | [] | [] | [(5, 87)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/demo.v:46: Cannot find file containing module: 'llabs'\nllabs labs(\n^~~~~\n ... Looked in:\n data/full_repos/permissive/98490156,data/full_repos/permissive/98490156/llabs\n data/full_repos/permissive/98490156,data/full_repos/permissive/98490156/llabs.v\n data/full_repos/permissive/98490156,data/full_repos/permissive/98490156/llabs.sv\n llabs\n llabs.v\n llabs.sv\n obj_dir/llabs\n obj_dir/llabs.v\n obj_dir/llabs.sv\n%Error: Exiting due to 1 error(s)\n" | 313,444 | module | module FiveSons(
CLOCK_50,
KEY,
SW,
LEDR,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output [17:0] LEDR;
wire [50:0] debug;
assign LEDR[17:0] = debug[17:0];
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
reg [255 : 0] board;
wire [1:0] gaming_status;
wire [3:0] pointer_loc_x;
wire [3:0] pointer_loc_y;
wire Reset;
llabs labs(
.working(SW[15]),
.Clck(CLOCK_50),
.board(board),
.gaming_status(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_y),
.Reset(Reset),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.debug_output(debug)
);
assign Reset = SW[17];
assign gaming_status = 2'b0;
assign pointer_loc_x = 4'b0;
assign pointer_loc_y = 4'b0;
always@(*)
begin
if(SW[16] == 1)
begin
board[`CO_TO_OFFSET(SW[3:0], SW[7:4]) +: 2] = 2'b01;
end
end
endmodule | module FiveSons(
CLOCK_50,
KEY,
SW,
LEDR,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output [17:0] LEDR;
wire [50:0] debug;
assign LEDR[17:0] = debug[17:0];
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
reg [255 : 0] board;
wire [1:0] gaming_status;
wire [3:0] pointer_loc_x;
wire [3:0] pointer_loc_y;
wire Reset;
llabs labs(
.working(SW[15]),
.Clck(CLOCK_50),
.board(board),
.gaming_status(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_y),
.Reset(Reset),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.debug_output(debug)
);
assign Reset = SW[17];
assign gaming_status = 2'b0;
assign pointer_loc_x = 4'b0;
assign pointer_loc_y = 4'b0;
always@(*)
begin
if(SW[16] == 1)
begin
board[`CO_TO_OFFSET(SW[3:0], SW[7:4]) +: 2] = 2'b01;
end
end
endmodule | 0 |
142,250 | data/full_repos/permissive/98490156/complishment_coordi/Color.v | 98,490,156 | Color.v | v | 27 | 75 | [] | [] | [] | [(4, 25)] | null | data/verilator_xmls/b8e41986-1a95-4832-aaf6-b9f871328c94.xml | null | 313,445 | module | module Color(turn, resetn, out, change_enable);
input turn, change_enable;
input resetn;
output [1:0] out;
reg [1:0] color;
initial begin
color = 2'b01;
end
always@(posedge turn, negedge resetn)
begin
if(!resetn) color = 2'b01;
else if (color == 2'b01 && change_enable) color = 2'b10;
else if (color == 2'b10 && change_enable) color = 2'b01;
end
assign out = color;
endmodule | module Color(turn, resetn, out, change_enable); |
input turn, change_enable;
input resetn;
output [1:0] out;
reg [1:0] color;
initial begin
color = 2'b01;
end
always@(posedge turn, negedge resetn)
begin
if(!resetn) color = 2'b01;
else if (color == 2'b01 && change_enable) color = 2'b10;
else if (color == 2'b10 && change_enable) color = 2'b01;
end
assign out = color;
endmodule | 0 |
142,251 | data/full_repos/permissive/98490156/complishment_coordi/control.v | 98,490,156 | control.v | v | 76 | 96 | [] | [] | [] | [(5, 75)] | null | data/verilator_xmls/1fcda580-fe92-4d77-b404-44fbd215e7c5.xml | null | 313,446 | module | module control(clock, resetn, put, change_turn, change_able_read);
input clock;
input resetn;
input put;
output reg change_turn;
output reg change_able_read;
localparam INITIAL = 3'd0,
CHOICE = 3'd1,
PUT_WAIT = 3'd2,
CHECK = 3'd3,
CHANGE = 3'd4;
reg [2:0] current_state, next_state;
always@(*)
begin
case (current_state)
INITIAL: next_state = CHOICE;
CHOICE: next_state = (put == 1'b0) ? PUT_WAIT : CHOICE;
PUT_WAIT: next_state = (put == 1'b0) ? PUT_WAIT : CHECK;
CHECK: next_state = CHANGE;
CHANGE: next_state = CHOICE;
default: next_state = INITIAL;
endcase
end
always @(*)
begin
case (current_state)
CHOICE: begin
change_turn = 1'b0;
change_able_read = 1'b1;
end
CHANGE: begin
change_turn = 1'b1;
change_able_read = 1'b0;
end
default: begin
change_turn = 1'b0;
change_able_read = 1'b0;
end
endcase
end
always@(posedge clock, negedge resetn)
begin
if(!resetn)
current_state <= INITIAL;
else
current_state <= next_state;
end
endmodule | module control(clock, resetn, put, change_turn, change_able_read); |
input clock;
input resetn;
input put;
output reg change_turn;
output reg change_able_read;
localparam INITIAL = 3'd0,
CHOICE = 3'd1,
PUT_WAIT = 3'd2,
CHECK = 3'd3,
CHANGE = 3'd4;
reg [2:0] current_state, next_state;
always@(*)
begin
case (current_state)
INITIAL: next_state = CHOICE;
CHOICE: next_state = (put == 1'b0) ? PUT_WAIT : CHOICE;
PUT_WAIT: next_state = (put == 1'b0) ? PUT_WAIT : CHECK;
CHECK: next_state = CHANGE;
CHANGE: next_state = CHOICE;
default: next_state = INITIAL;
endcase
end
always @(*)
begin
case (current_state)
CHOICE: begin
change_turn = 1'b0;
change_able_read = 1'b1;
end
CHANGE: begin
change_turn = 1'b1;
change_able_read = 1'b0;
end
default: begin
change_turn = 1'b0;
change_able_read = 1'b0;
end
endcase
end
always@(posedge clock, negedge resetn)
begin
if(!resetn)
current_state <= INITIAL;
else
current_state <= next_state;
end
endmodule | 0 |
142,252 | data/full_repos/permissive/98490156/complishment_coordi/DataPath.v | 98,490,156 | DataPath.v | v | 151 | 143 | [] | [] | [] | [(4, 149)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:38: Cannot find file containing module: 'Hexdisplay'\n Hexdisplay row_display(.out(hex1), .in(coordi[7:4]));\n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/Hexdisplay\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/Hexdisplay.v\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/Hexdisplay.sv\n Hexdisplay\n Hexdisplay.v\n Hexdisplay.sv\n obj_dir/Hexdisplay\n obj_dir/Hexdisplay.v\n obj_dir/Hexdisplay.sv\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:39: Cannot find file containing module: 'Hexdisplay'\n Hexdisplay col_display(.out(hex0), .in(coordi[3:0]));\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:48: Cannot find file containing module: 'Memory_Write'\n Memory_Write dataIn(.in(color[1:0]), .select(coordi[7:0]), .out(memory[511:0]), .clock(put), .reset(resetn), .write_enable(write_enable));\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:50: Cannot find file containing module: 'Memory_Read'\n Memory_Read dataOut(.in(memory[511:0]), .select(coordi[7:0]), .out(current_state[1:0]));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:52: Cannot find file containing module: 'Enable_control'\n Enable_control able(.current_state(current_state[1:0]), .out(write_enable));\n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:66: Cannot find file containing module: 'Color'\n Color getcolor(.turn(turn_control), .resetn(resetn), .out(color), .change_enable(change_enable));\n ^~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:71: Cannot find file containing module: 'All_Check'\n All_Check checkBoard(.memory(memory[511:0]), .ans(check_ans[1:0]));\n ^~~~~~~~~\n%Error: data/full_repos/permissive/98490156/complishment_coordi/DataPath.v:118: Cannot find file containing module: 'llabs'\n llabs labs(\n ^~~~~\n%Error: Exiting due to 8 error(s)\n" | 313,447 | module | module DataPath(coordi, resetn, put, turn_control, change_able_read, ledr, ledg, hex0, hex1, clock,
vga_clk,
vga_hs,
vga_vs,
vga_blank_n,
vga_sync_n,
vga_r,
vga_g,
vga_b
);
input [7:0] coordi;
input resetn;
input put;
input turn_control;
input change_able_read;
input clock;
output [6:0] hex0, hex1;
output [7:0] ledg, ledr;
output vga_clk;
output vga_hs;
output vga_vs;
output vga_blank_n;
output vga_sync_n;
output [9:0] vga_r;
output [9:0] vga_g;
output [9:0] vga_b;
Hexdisplay row_display(.out(hex1), .in(coordi[7:4]));
Hexdisplay col_display(.out(hex0), .in(coordi[3:0]));
wire [511:0] memory;
wire [1:0] current_state;
wire write_enable;
Memory_Write dataIn(.in(color[1:0]), .select(coordi[7:0]), .out(memory[511:0]), .clock(put), .reset(resetn), .write_enable(write_enable));
Memory_Read dataOut(.in(memory[511:0]), .select(coordi[7:0]), .out(current_state[1:0]));
Enable_control able(.current_state(current_state[1:0]), .out(write_enable));
wire [1:0] color;
wire change_enable;
reg record;
always@(*)
begin
if(change_able_read) record <= write_enable;
end
assign change_enable = record;
Color getcolor(.turn(turn_control), .resetn(resetn), .out(color), .change_enable(change_enable));
wire [1:0] check_ans;
All_Check checkBoard(.memory(memory[511:0]), .ans(check_ans[1:0]));
reg dis_choice;
always@(*)
begin
if(check_ans[1:0] != 2'b00) dis_choice = 1'b1;
else dis_choice = 1'b0;
end
reg [7:0] lg, lr;
always@(*)
begin
if(dis_choice) begin
if(check_ans[1:0] == 2'b01) begin
lr[7] = 1'b1;
lr[0] = 1'b0;
lg[0] = 1'b0;
lg[7] = 1'b0;
end
else begin
lr[7] = 1'b0;
lr[0] = 1'b0;
lg[0] = 1'b1;
lg[7] = 1'b0;
end
end
else begin
if(color[1:0] == 2'b01) begin
lr[7] = 1'b0;
lr[0] = 1'b1;
lg[0] = 1'b0;
lg[7] = 1'b0;
end
else begin
lr[7] = 1'b0;
lr[0] = 1'b0;
lg[0] = 1'b0;
lg[7] = 1'b1;
end
end
end
llabs labs(
.Clck(clock),
.board(memory),
.gaming_status(check_ans[1:0]),
.pointer_loc_x(coordi[3:0]),
.pointer_loc_y(coordi[7:4]),
.Reset(resetn),
.VGA_CLK(vga_clk),
.VGA_HS(vga_hs),
.VGA_VS(vga_vs),
.VGA_BLANK_N(vga_blank_n),
.VGA_SYNC_N(vga_sync_n),
.VGA_R(vga_r),
.VGA_G(vga_g),
.VGA_B(vga_b)
);
assign ledr[7] = lr[7];
assign ledr[0] = lr[0];
assign ledg[7] = lg[7];
assign ledg[0] = lg[0];
assign ledr[5] = write_enable;
assign ledr[4] = change_able_read;
assign ledr[3] = change_enable;
endmodule | module DataPath(coordi, resetn, put, turn_control, change_able_read, ledr, ledg, hex0, hex1, clock,
vga_clk,
vga_hs,
vga_vs,
vga_blank_n,
vga_sync_n,
vga_r,
vga_g,
vga_b
); |
input [7:0] coordi;
input resetn;
input put;
input turn_control;
input change_able_read;
input clock;
output [6:0] hex0, hex1;
output [7:0] ledg, ledr;
output vga_clk;
output vga_hs;
output vga_vs;
output vga_blank_n;
output vga_sync_n;
output [9:0] vga_r;
output [9:0] vga_g;
output [9:0] vga_b;
Hexdisplay row_display(.out(hex1), .in(coordi[7:4]));
Hexdisplay col_display(.out(hex0), .in(coordi[3:0]));
wire [511:0] memory;
wire [1:0] current_state;
wire write_enable;
Memory_Write dataIn(.in(color[1:0]), .select(coordi[7:0]), .out(memory[511:0]), .clock(put), .reset(resetn), .write_enable(write_enable));
Memory_Read dataOut(.in(memory[511:0]), .select(coordi[7:0]), .out(current_state[1:0]));
Enable_control able(.current_state(current_state[1:0]), .out(write_enable));
wire [1:0] color;
wire change_enable;
reg record;
always@(*)
begin
if(change_able_read) record <= write_enable;
end
assign change_enable = record;
Color getcolor(.turn(turn_control), .resetn(resetn), .out(color), .change_enable(change_enable));
wire [1:0] check_ans;
All_Check checkBoard(.memory(memory[511:0]), .ans(check_ans[1:0]));
reg dis_choice;
always@(*)
begin
if(check_ans[1:0] != 2'b00) dis_choice = 1'b1;
else dis_choice = 1'b0;
end
reg [7:0] lg, lr;
always@(*)
begin
if(dis_choice) begin
if(check_ans[1:0] == 2'b01) begin
lr[7] = 1'b1;
lr[0] = 1'b0;
lg[0] = 1'b0;
lg[7] = 1'b0;
end
else begin
lr[7] = 1'b0;
lr[0] = 1'b0;
lg[0] = 1'b1;
lg[7] = 1'b0;
end
end
else begin
if(color[1:0] == 2'b01) begin
lr[7] = 1'b0;
lr[0] = 1'b1;
lg[0] = 1'b0;
lg[7] = 1'b0;
end
else begin
lr[7] = 1'b0;
lr[0] = 1'b0;
lg[0] = 1'b0;
lg[7] = 1'b1;
end
end
end
llabs labs(
.Clck(clock),
.board(memory),
.gaming_status(check_ans[1:0]),
.pointer_loc_x(coordi[3:0]),
.pointer_loc_y(coordi[7:4]),
.Reset(resetn),
.VGA_CLK(vga_clk),
.VGA_HS(vga_hs),
.VGA_VS(vga_vs),
.VGA_BLANK_N(vga_blank_n),
.VGA_SYNC_N(vga_sync_n),
.VGA_R(vga_r),
.VGA_G(vga_g),
.VGA_B(vga_b)
);
assign ledr[7] = lr[7];
assign ledr[0] = lr[0];
assign ledg[7] = lg[7];
assign ledg[0] = lg[0];
assign ledr[5] = write_enable;
assign ledr[4] = change_able_read;
assign ledr[3] = change_enable;
endmodule | 0 |
142,253 | data/full_repos/permissive/98490156/complishment_coordi/GoBang.v | 98,490,156 | GoBang.v | v | 54 | 130 | [] | [] | [] | [(4, 51)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/complishment_coordi/GoBang.v:35: Cannot find file containing module: 'control'\n control ct(.clock(CLOCK_50), .resetn(KEY[1]), .put(SW[12]), .change_turn(turn_control), .change_able_read(change_able_read));\n ^~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/control\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/control.v\n data/full_repos/permissive/98490156/complishment_coordi,data/full_repos/permissive/98490156/control.sv\n control\n control.v\n control.sv\n obj_dir/control\n obj_dir/control.v\n obj_dir/control.sv\n%Error: data/full_repos/permissive/98490156/complishment_coordi/GoBang.v:38: Cannot find file containing module: 'DataPath'\n DataPath board(.coordi(SW[7:0]), .resetn(KEY[1]), .put(SW[12]),\n ^~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 313,448 | module | module GoBang(SW, KEY, LEDR, LEDG, HEX0, HEX1, CLOCK_50,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input [12:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0, HEX1;
output [7:0] LEDR, LEDG;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire turn_control, change_able_read;
control ct(.clock(CLOCK_50), .resetn(KEY[1]), .put(SW[12]), .change_turn(turn_control), .change_able_read(change_able_read));
DataPath board(.coordi(SW[7:0]), .resetn(KEY[1]), .put(SW[12]),
.turn_control(turn_control), .change_able_read(change_able_read), .ledr(LEDR[7:0]), .ledg(LEDG[7:0]),
.hex0(HEX0[6:0]), .hex1(HEX1[6:0]), .clock(CLOCK_50),
.vga_clk(VGA_CLK),
.vga_hs(VGA_HS),
.vga_vs(VGA_VS),
.vga_blank_n(VGA_BLANK_N),
.vga_sync_n(VGA_SYNC_N),
.vga_r(VGA_R),
.vga_g(VGA_G),
.vga_b(VGA_B)
);
endmodule | module GoBang(SW, KEY, LEDR, LEDG, HEX0, HEX1, CLOCK_50,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input [12:0] SW;
input [3:0] KEY;
input CLOCK_50;
output [6:0] HEX0, HEX1;
output [7:0] LEDR, LEDG;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire turn_control, change_able_read;
control ct(.clock(CLOCK_50), .resetn(KEY[1]), .put(SW[12]), .change_turn(turn_control), .change_able_read(change_able_read));
DataPath board(.coordi(SW[7:0]), .resetn(KEY[1]), .put(SW[12]),
.turn_control(turn_control), .change_able_read(change_able_read), .ledr(LEDR[7:0]), .ledg(LEDG[7:0]),
.hex0(HEX0[6:0]), .hex1(HEX1[6:0]), .clock(CLOCK_50),
.vga_clk(VGA_CLK),
.vga_hs(VGA_HS),
.vga_vs(VGA_VS),
.vga_blank_n(VGA_BLANK_N),
.vga_sync_n(VGA_SYNC_N),
.vga_r(VGA_R),
.vga_g(VGA_G),
.vga_b(VGA_B)
);
endmodule | 0 |
142,254 | data/full_repos/permissive/98490156/complishment_coordi/memory/D_Flip_Flop.v | 98,490,156 | D_Flip_Flop.v | v | 23 | 100 | [] | [] | [] | [(4, 22)] | null | data/verilator_xmls/97e2d677-545b-497d-8f80-5113cf3a47a0.xml | null | 313,454 | module | module D_Flip_Flop(d, clock, write_enable, reset, q);
input d, clock, reset, write_enable;
output reg q;
initial begin
q = 0;
end
always@(posedge clock, negedge reset) begin
if (reset == 1'b0)
q <= 0;
else if (write_enable)
q <= d;
end
endmodule | module D_Flip_Flop(d, clock, write_enable, reset, q); |
input d, clock, reset, write_enable;
output reg q;
initial begin
q = 0;
end
always@(posedge clock, negedge reset) begin
if (reset == 1'b0)
q <= 0;
else if (write_enable)
q <= d;
end
endmodule | 0 |
142,255 | data/full_repos/permissive/98490156/complishment_coordi/memory/Y_Coordinate_Select_Read.v | 98,490,156 | Y_Coordinate_Select_Read.v | v | 15 | 96 | [] | [] | [] | [(6, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/complishment_coordi/memory/Y_Coordinate_Select_Read.v:12: Cannot find file containing module: 'Select16to1'\n Select16to1 getDataFromPoint(.in(in), .select(select), .out(out));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/complishment_coordi/memory,data/full_repos/permissive/98490156/Select16to1\n data/full_repos/permissive/98490156/complishment_coordi/memory,data/full_repos/permissive/98490156/Select16to1.v\n data/full_repos/permissive/98490156/complishment_coordi/memory,data/full_repos/permissive/98490156/Select16to1.sv\n Select16to1\n Select16to1.v\n Select16to1.sv\n obj_dir/Select16to1\n obj_dir/Select16to1.v\n obj_dir/Select16to1.sv\n%Error: Exiting due to 1 error(s)\n" | 313,462 | module | module Y_Coordinate_Select_Read(in, select, out);
input [31:0] in;
input [3:0] select;
output [1:0] out;
Select16to1 getDataFromPoint(.in(in), .select(select), .out(out));
endmodule | module Y_Coordinate_Select_Read(in, select, out); |
input [31:0] in;
input [3:0] select;
output [1:0] out;
Select16to1 getDataFromPoint(.in(in), .select(select), .out(out));
endmodule | 0 |
142,256 | data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate/Coordi_Gener.v | 98,490,156 | Coordi_Gener.v | v | 10 | 102 | [] | [] | [] | [(1, 9)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate/Coordi_Gener.v:6: Cannot find file containing module: 'X_Coordi_Gener'\n X_Coordi_Gener xcoodi(.down(down), .control_set(control_set), .resetn(resetn), .out(out[7:4]));\n ^~~~~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate,data/full_repos/permissive/98490156/X_Coordi_Gener\n data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate,data/full_repos/permissive/98490156/X_Coordi_Gener.v\n data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate,data/full_repos/permissive/98490156/X_Coordi_Gener.sv\n X_Coordi_Gener\n X_Coordi_Gener.v\n X_Coordi_Gener.sv\n obj_dir/X_Coordi_Gener\n obj_dir/X_Coordi_Gener.v\n obj_dir/X_Coordi_Gener.sv\n%Error: data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate/Coordi_Gener.v:7: Cannot find file containing module: 'Y_Coordi_Gener'\n Y_Coordi_Gener ycoodi(.right(right), .control_set(control_set), .resetn(resetn), .out(out[3:0]));\n ^~~~~~~~~~~~~~\n%Error: Exiting due to 2 error(s)\n" | 313,480 | module | module Coordi_Gener(right, down, control_set, resetn, out);
input right, down;
input resetn, control_set;
output [7:0] out;
X_Coordi_Gener xcoodi(.down(down), .control_set(control_set), .resetn(resetn), .out(out[7:4]));
Y_Coordi_Gener ycoodi(.right(right), .control_set(control_set), .resetn(resetn), .out(out[3:0]));
endmodule | module Coordi_Gener(right, down, control_set, resetn, out); |
input right, down;
input resetn, control_set;
output [7:0] out;
X_Coordi_Gener xcoodi(.down(down), .control_set(control_set), .resetn(resetn), .out(out[7:4]));
Y_Coordi_Gener ycoodi(.right(right), .control_set(control_set), .resetn(resetn), .out(out[3:0]));
endmodule | 0 |
142,257 | data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate/X_Coordi_Gener.v | 98,490,156 | X_Coordi_Gener.v | v | 24 | 63 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/f6c0a3b3-8191-4aa2-a6b7-49800b7c0238.xml | null | 313,481 | module | module X_Coordi_Gener(down, control_set, resetn, out);
input down;
input resetn, control_set;
output [3:0] out;
reg [3:0] xco;
initial begin
xco = 4'd0;
end
always@(posedge down, negedge resetn, posedge control_set)
begin
if(!resetn || control_set) xco <= 4'd0;
else begin
if(xco == 4'd15) xco <= 4'd0;
else xco <= xco + 4'b0001;
end
end
assign out[3:0] = xco[3:0];
endmodule | module X_Coordi_Gener(down, control_set, resetn, out); |
input down;
input resetn, control_set;
output [3:0] out;
reg [3:0] xco;
initial begin
xco = 4'd0;
end
always@(posedge down, negedge resetn, posedge control_set)
begin
if(!resetn || control_set) xco <= 4'd0;
else begin
if(xco == 4'd15) xco <= 4'd0;
else xco <= xco + 4'b0001;
end
end
assign out[3:0] = xco[3:0];
endmodule | 0 |
142,258 | data/full_repos/permissive/98490156/indebug_pointer/Coordinate_Generate/Y_Coordi_Gener.v | 98,490,156 | Y_Coordi_Gener.v | v | 24 | 64 | [] | [] | [] | [(1, 23)] | null | data/verilator_xmls/880b5f7e-094c-4c22-9fc6-f0f7e0fefafc.xml | null | 313,482 | module | module Y_Coordi_Gener(right, control_set, resetn, out);
input right;
input resetn, control_set;
output [3:0] out;
reg [3:0] yco;
initial begin
yco = 4'd0;
end
always@(posedge right, negedge resetn, posedge control_set)
begin
if(!resetn || control_set) yco <= 4'd0;
else begin
if(yco == 4'd15) yco <= 4'd0;
else yco <= yco + 4'b0001;
end
end
assign out[3:0] = yco[3:0];
endmodule | module Y_Coordi_Gener(right, control_set, resetn, out); |
input right;
input resetn, control_set;
output [3:0] out;
reg [3:0] yco;
initial begin
yco = 4'd0;
end
always@(posedge right, negedge resetn, posedge control_set)
begin
if(!resetn || control_set) yco <= 4'd0;
else begin
if(yco == 4'd15) yco <= 4'd0;
else yco <= yco + 4'b0001;
end
end
assign out[3:0] = yco[3:0];
endmodule | 0 |
142,259 | data/full_repos/permissive/98490156/logic_part/counters.v | 98,490,156 | counters.v | v | 508 | 106 | [] | [] | [] | [(1, 109), (111, 219), (221, 363), (365, 507)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98490156/logic_part/counters.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'horizontal_check\'\nmodule horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~~~\n : ... Top module \'verticle_check\'\nmodule verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'lean1_check\'\nmodule lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n : ... Top module \'lean2_check\'\nmodule lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,500 | module | module horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if (pointer[3:0] < 4'd4)
begin
curradd[7:0] = {pointer[7:4], 4'd0};
endadd[7:0] = {pointer[7:4], pointer[3:0] + 4'd4};
end
else if (pointer[3:0] > 4'd11)
begin
curradd = {pointer[7:4], pointer[3:0] - 4'd4};
endadd = {pointer[7:4], 4'd15};
end
else
begin
curradd = {pointer[7:4], pointer[3:0] - 4'd4};
endadd = {pointer[7:4], pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT: curradd[3:0] = curradd[3:0] + 4'd1;
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | module horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk); |
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if (pointer[3:0] < 4'd4)
begin
curradd[7:0] = {pointer[7:4], 4'd0};
endadd[7:0] = {pointer[7:4], pointer[3:0] + 4'd4};
end
else if (pointer[3:0] > 4'd11)
begin
curradd = {pointer[7:4], pointer[3:0] - 4'd4};
endadd = {pointer[7:4], 4'd15};
end
else
begin
curradd = {pointer[7:4], pointer[3:0] - 4'd4};
endadd = {pointer[7:4], pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT: curradd[3:0] = curradd[3:0] + 4'd1;
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | 0 |
142,260 | data/full_repos/permissive/98490156/logic_part/counters.v | 98,490,156 | counters.v | v | 508 | 106 | [] | [] | [] | [(1, 109), (111, 219), (221, 363), (365, 507)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98490156/logic_part/counters.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'horizontal_check\'\nmodule horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~~~\n : ... Top module \'verticle_check\'\nmodule verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'lean1_check\'\nmodule lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n : ... Top module \'lean2_check\'\nmodule lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,500 | module | module verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if (pointer[7:4] < 4'd4)
begin
curradd = {4'd0, pointer[3:0]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0]};
end
else if (pointer[7:4] > 4'd11)
begin
curradd = {pointer[7:4] - 4'd4, pointer[3:0]};
endadd = {4'd15, pointer[3:0]};
end
else
begin
curradd = {pointer[7:4] - 4'd4, pointer[3:0]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0]};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT: curradd[7:4] = curradd[7:4] + 4'd1;
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | module verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk); |
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if (pointer[7:4] < 4'd4)
begin
curradd = {4'd0, pointer[3:0]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0]};
end
else if (pointer[7:4] > 4'd11)
begin
curradd = {pointer[7:4] - 4'd4, pointer[3:0]};
endadd = {4'd15, pointer[3:0]};
end
else
begin
curradd = {pointer[7:4] - 4'd4, pointer[3:0]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0]};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT: curradd[7:4] = curradd[7:4] + 4'd1;
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | 0 |
142,261 | data/full_repos/permissive/98490156/logic_part/counters.v | 98,490,156 | counters.v | v | 508 | 106 | [] | [] | [] | [(1, 109), (111, 219), (221, 363), (365, 507)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98490156/logic_part/counters.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'horizontal_check\'\nmodule horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~~~\n : ... Top module \'verticle_check\'\nmodule verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'lean1_check\'\nmodule lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n : ... Top module \'lean2_check\'\nmodule lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,500 | module | module lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if ((pointer[3:0] < 4'd4) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] - pointer[3:0] , 4'd0};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[7:4] < 4'd4) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {4'd0 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[7:4] > 4'd11) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] <= 4'd3)) begin
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
if (pointer[7:4] < pointer[3:0]) curradd = {4'd0, pointer[3:0] - pointer[7:4]};
else curradd = {pointer[7:4] - pointer[3:0], 4'd0};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] >= 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
if (pointer[7:4] > pointer[3:0]) endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
else endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] >= 4'd12)) begin
curradd = {pointer[7:4] - pointer[3:0] , 4'd0};
endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] <= 4'd3)) begin
curradd = {4'd0 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT:begin
curradd[3:0] = curradd[3:0] + 4'd1;
curradd[7:4] = curradd[7:4] + 4'd1;
end
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | module lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk); |
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if ((pointer[3:0] < 4'd4) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] - pointer[3:0] , 4'd0};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[7:4] < 4'd4) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {4'd0 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[7:4] > 4'd11) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] <= 4'd3)) begin
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
if (pointer[7:4] < pointer[3:0]) curradd = {4'd0, pointer[3:0] - pointer[7:4]};
else curradd = {pointer[7:4] - pointer[3:0], 4'd0};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] >= 4'd12)) begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
if (pointer[7:4] > pointer[3:0]) endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
else endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] >= 4'd12)) begin
curradd = {pointer[7:4] - pointer[3:0] , 4'd0};
endadd = {4'd15, pointer[3:0] + (4'd15 - pointer[7:4])};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] <= 4'd3)) begin
curradd = {4'd0 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] + (4'd15 - pointer[3:0]), 4'd15};
end
else begin
curradd = {pointer[7:4] - 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] + 4'd4, pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT:begin
curradd[3:0] = curradd[3:0] + 4'd1;
curradd[7:4] = curradd[7:4] + 4'd1;
end
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | 0 |
142,262 | data/full_repos/permissive/98490156/logic_part/counters.v | 98,490,156 | counters.v | v | 508 | 106 | [] | [] | [] | [(1, 109), (111, 219), (221, 363), (365, 507)] | null | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98490156/logic_part/counters.v:111: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'horizontal_check\'\nmodule horizontal_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~~~\n : ... Top module \'verticle_check\'\nmodule verticle_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~~~~\n : ... Top module \'lean1_check\'\nmodule lean1_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n : ... Top module \'lean2_check\'\nmodule lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);\n ^~~~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,500 | module | module lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk);
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if ((pointer[3:0] < 4'd4) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] + pointer[3:0] , 4'd0};
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[7:4] < 4'd4) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {pointer[7:4] + 4'd4, pointer[3:0] - 4'd4};
endadd = {4'd0 , pointer[3:0] + pointer[7:4]};
end
else if ((pointer[7:4] > 4'd11) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {4'd15, pointer[3:0] - (4'd15 - pointer[7:4])};
endadd = {pointer[7:4] - 4'd4 , pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] <= 4'd3)) begin
curradd = {pointer[7:4] + pointer[3:0] , 4'd0};
endadd = {4'd0, pointer[3:0] + pointer[7:4]};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] >= 4'd12)) begin
curradd = {4'd15 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] >= 4'd12)) begin
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
if ((4'd15 - pointer[7:4]) < pointer[3:0]) curradd = {4'd15, pointer[3:0] - (4'd15 - pointer[7:4])};
else curradd = {pointer[7:4] + pointer[3:0], 4'd0};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] <= 4'd3)) begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
if (pointer[7:4] < (4'd15 - pointer[3:0])) endadd = {4'd0, pointer[3:0] + pointer[7:4]};
else endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT:begin
curradd[3:0] = curradd[3:0] + 4'd1;
curradd[7:4] = curradd[7:4] - 4'd1;
end
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | module lean2_check(reset, active, pointer, chess, address, currstate, success, active_next, clk); |
input active, reset;
input [7:0] pointer;
input [1:0] chess, currstate;
input clk;
output [7:0] address;
output active_next, success;
reg [3:0] curr_state, nxt_state;
reg [7:0] curradd, endadd;
reg [2:0] count;
reg [1:0] curstate, ches;
reg actnex, suc;
assign active_next = actnex;
assign success = suc;
assign address = curradd;
localparam WAIT = 4'd0,
INITIAL = 4'd1,
COUNT = 4'd2,
COUNT_WAIT = 4'd3,
SUCCESS = 4'd4,
FAIL = 4'd5;
initial begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
curr_state = WAIT;
nxt_state = WAIT;
end
always @(*) begin
case(curr_state)
WAIT: nxt_state = (active) ? INITIAL : WAIT;
INITIAL: nxt_state = COUNT;
COUNT:begin
if (curradd == endadd) nxt_state = FAIL;
else if (count == 3'd5) nxt_state = SUCCESS;
else nxt_state = COUNT_WAIT;
end
COUNT_WAIT: nxt_state = COUNT;
SUCCESS: begin
nxt_state = SUCCESS;
end
FAIL: begin
nxt_state = FAIL;
end
default: nxt_state = WAIT;
endcase
end
always @(curr_state) begin
case(curr_state)
WAIT: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
INITIAL: begin
ches = chess;
if ((pointer[3:0] < 4'd4) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] + pointer[3:0] , 4'd0};
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] > 4'd3) && (pointer[7:4] < 4'd12)) begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[7:4] < 4'd4) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {pointer[7:4] + 4'd4, pointer[3:0] - 4'd4};
endadd = {4'd0 , pointer[3:0] + pointer[7:4]};
end
else if ((pointer[7:4] > 4'd11) && (pointer[3:0] > 4'd3) && (pointer[3:0] < 4'd12)) begin
curradd = {4'd15, pointer[3:0] - (4'd15 - pointer[7:4])};
endadd = {pointer[7:4] - 4'd4 , pointer[3:0] + 4'd4};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] <= 4'd3)) begin
curradd = {pointer[7:4] + pointer[3:0] , 4'd0};
endadd = {4'd0, pointer[3:0] + pointer[7:4]};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] >= 4'd12)) begin
curradd = {4'd15 , pointer[3:0] - pointer[7:4]};
endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else if ((pointer[3:0] < 4'd4) && (pointer[7:4] >= 4'd12)) begin
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
if ((4'd15 - pointer[7:4]) < pointer[3:0]) curradd = {4'd15, pointer[3:0] - (4'd15 - pointer[7:4])};
else curradd = {pointer[7:4] + pointer[3:0], 4'd0};
end
else if ((pointer[3:0] >= 4'd12) && (pointer[7:4] <= 4'd3)) begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
if (pointer[7:4] < (4'd15 - pointer[3:0])) endadd = {4'd0, pointer[3:0] + pointer[7:4]};
else endadd = {pointer[7:4] - (4'd15 - pointer[3:0]), 4'd15};
end
else begin
curradd = {pointer[7:4] + 4'd4 , pointer[3:0] - 4'd4};
endadd = {pointer[7:4] - 4'd4, pointer[3:0] + 4'd4};
end
end
COUNT:begin
curstate = currstate;
if (ches == curstate) count[2:0] = count[2:0] + 3'd1;
else count[2:0] = 3'd0;
end
COUNT_WAIT:begin
curradd[3:0] = curradd[3:0] + 4'd1;
curradd[7:4] = curradd[7:4] - 4'd1;
end
SUCCESS: suc = 1'd1;
FAIL: actnex = 1'b1;
default: begin
curradd = 8'd0;
endadd = 8'd0;
count = 3'd0;
curstate = 2'd0;
ches = 2'd0;
actnex = 1'd0;
suc = 1'd0;
end
endcase
end
always @(posedge clk, posedge reset) begin
if (reset == 1'b1) curr_state = WAIT;
else curr_state = nxt_state;
end
endmodule | 0 |
142,263 | data/full_repos/permissive/98490156/logic_part/Main.v | 98,490,156 | Main.v | v | 183 | 125 | [] | [] | [] | null | line:14: before: ")" | null | 1: b"%Error: data/full_repos/permissive/98490156/logic_part/Main.v:14: syntax error, unexpected ')', expecting '['\n);\n^\n%Error: data/full_repos/permissive/98490156/logic_part/Main.v:69: syntax error, unexpected IDENTIFIER\n pospulse_gen p1(pointer_reset, pointer_reset_pulse, CLOCK_50);\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/Main.v:97: syntax error, unexpected initial\n initial begin\n ^~~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,501 | module | module try(KEY,
CLOCK_50,
SW,
);
input [3:0] KEY;
input CLOCK_50;
input [17:0] SW;
wire [7:0] pointer;
wire pointer_reset_pulse, play_pulse, check_activate_pulse, check_reset_pulse;
wire [511:0] board;
wire [7:0] add;
wire [1:0] content_write, board_chess;
wire round_suc, round_fai;
reg pointer_reset, play, check_activate, check_reset;
reg [1:0] curr_player;
reg [7:0] prev_add;
reg [1:0] game_state;
reg [3:0] curr_state, nxt_state;
reg[7:0] pointr;
pospulse_gen p1(pointer_reset, pointer_reset_pulse, CLOCK_50);
pospulse_gen p2(play, play_pulse, CLOCK_50);
pospulse_gen p3(check_activate, check_activate_pulse, CLOCK_50);
pospulse_gen p4(check_reset, check_reset_pulse, CLOCK_50);
mux2218 mx1(pointr, prev_add, KEY[0], add);
mux2212 mx2(curr_player, 2'b00, KEY[0], content_write);
Memory_Write mem(.in(content_write), .select(add), .out(board), .clock(play_pulse), .reset(SW[17]));
Memory_Read mr(.in(board), .select(pointr), .out(board_chess));
pointer pt(KEY[3], KEY[2], pointer_reset_pulse, pointer);
overall_check oc(.reset(check_reset_pulse), .active(check_activate_pulse),
.pointer(pointr), .chess(curr_player), .success(round_suc), .fail(round_fai), .board(board), .clk(CLOCK_50));
localparam WAIT_SELECT = 4'd0,
BEGIN_REGRET = 4'd1,
BEGIN_PLAY = 4'd2,
PLAY = 4'd3,
BEGIN_CHECK = 4'd4,
END_CHECK = 4'd5,
END_ROUND = 4'd6,
WIN = 4'd7,
BLACK = 2'b01,
WHITE = 2'b10;
initial begin
check_activate = 1'b0;
pointer_reset = 1'b0;
play = 1'b0;
check_reset = 1'b0;
curr_player = BLACK;
prev_add = 8'd0;
game_state = 2'd0;
curr_state = WAIT_SELECT;
nxt_state = WAIT_SELECT;
pointr = 8'd0;
end
always @(*) begin
case(curr_state)
WAIT_SELECT: begin
if (KEY[1] == 1'b0) nxt_state = BEGIN_PLAY;
else if (KEY[0] == 1'b0) nxt_state = BEGIN_REGRET;
else nxt_state = WAIT_SELECT;
end
BEGIN_REGRET: begin
if (KEY[0] == 1'b1) nxt_state = WAIT_SELECT;
else nxt_state = BEGIN_REGRET;
end
BEGIN_PLAY: begin
if (board_chess != 2'd0) nxt_state = WAIT_SELECT;
else nxt_state = PLAY;
end
PLAY: nxt_state = BEGIN_CHECK;
BEGIN_CHECK: begin
if (check_reset_pulse == 1'b0) nxt_state = END_CHECK;
else nxt_state = BEGIN_CHECK;
end
END_CHECK: begin
if (round_suc == 1'b1) nxt_state = WIN;
else if (round_fai == 1'b1) nxt_state = END_ROUND;
else nxt_state = END_CHECK;
end
WIN: nxt_state = WIN;
END_ROUND: nxt_state = WAIT_SELECT;
default: nxt_state = WAIT_SELECT;
endcase
end
always @(curr_state) begin
case(curr_state)
BEGIN_REGRET:begin
play = !play;
curr_player = ~curr_player;
end
PLAY: begin
play = !play;
prev_add = pointer;
end
BEGIN_CHECK: check_reset = !check_reset;
END_CHECK: check_activate = !check_activate;
WIN: game_state = curr_player;
END_ROUND : begin
pointer_reset = !pointer_reset;
check_reset = !check_reset;
if (curr_player == BLACK) curr_player = WHITE;
else curr_player = BLACK;
end
endcase
end
always @(negedge SW[17], posedge CLOCK_50) begin
if (SW[17] == 1'b0) curr_state = END_ROUND;
else curr_state = nxt_state;
end
endmodule | module try(KEY,
CLOCK_50,
SW,
); |
input [3:0] KEY;
input CLOCK_50;
input [17:0] SW;
wire [7:0] pointer;
wire pointer_reset_pulse, play_pulse, check_activate_pulse, check_reset_pulse;
wire [511:0] board;
wire [7:0] add;
wire [1:0] content_write, board_chess;
wire round_suc, round_fai;
reg pointer_reset, play, check_activate, check_reset;
reg [1:0] curr_player;
reg [7:0] prev_add;
reg [1:0] game_state;
reg [3:0] curr_state, nxt_state;
reg[7:0] pointr;
pospulse_gen p1(pointer_reset, pointer_reset_pulse, CLOCK_50);
pospulse_gen p2(play, play_pulse, CLOCK_50);
pospulse_gen p3(check_activate, check_activate_pulse, CLOCK_50);
pospulse_gen p4(check_reset, check_reset_pulse, CLOCK_50);
mux2218 mx1(pointr, prev_add, KEY[0], add);
mux2212 mx2(curr_player, 2'b00, KEY[0], content_write);
Memory_Write mem(.in(content_write), .select(add), .out(board), .clock(play_pulse), .reset(SW[17]));
Memory_Read mr(.in(board), .select(pointr), .out(board_chess));
pointer pt(KEY[3], KEY[2], pointer_reset_pulse, pointer);
overall_check oc(.reset(check_reset_pulse), .active(check_activate_pulse),
.pointer(pointr), .chess(curr_player), .success(round_suc), .fail(round_fai), .board(board), .clk(CLOCK_50));
localparam WAIT_SELECT = 4'd0,
BEGIN_REGRET = 4'd1,
BEGIN_PLAY = 4'd2,
PLAY = 4'd3,
BEGIN_CHECK = 4'd4,
END_CHECK = 4'd5,
END_ROUND = 4'd6,
WIN = 4'd7,
BLACK = 2'b01,
WHITE = 2'b10;
initial begin
check_activate = 1'b0;
pointer_reset = 1'b0;
play = 1'b0;
check_reset = 1'b0;
curr_player = BLACK;
prev_add = 8'd0;
game_state = 2'd0;
curr_state = WAIT_SELECT;
nxt_state = WAIT_SELECT;
pointr = 8'd0;
end
always @(*) begin
case(curr_state)
WAIT_SELECT: begin
if (KEY[1] == 1'b0) nxt_state = BEGIN_PLAY;
else if (KEY[0] == 1'b0) nxt_state = BEGIN_REGRET;
else nxt_state = WAIT_SELECT;
end
BEGIN_REGRET: begin
if (KEY[0] == 1'b1) nxt_state = WAIT_SELECT;
else nxt_state = BEGIN_REGRET;
end
BEGIN_PLAY: begin
if (board_chess != 2'd0) nxt_state = WAIT_SELECT;
else nxt_state = PLAY;
end
PLAY: nxt_state = BEGIN_CHECK;
BEGIN_CHECK: begin
if (check_reset_pulse == 1'b0) nxt_state = END_CHECK;
else nxt_state = BEGIN_CHECK;
end
END_CHECK: begin
if (round_suc == 1'b1) nxt_state = WIN;
else if (round_fai == 1'b1) nxt_state = END_ROUND;
else nxt_state = END_CHECK;
end
WIN: nxt_state = WIN;
END_ROUND: nxt_state = WAIT_SELECT;
default: nxt_state = WAIT_SELECT;
endcase
end
always @(curr_state) begin
case(curr_state)
BEGIN_REGRET:begin
play = !play;
curr_player = ~curr_player;
end
PLAY: begin
play = !play;
prev_add = pointer;
end
BEGIN_CHECK: check_reset = !check_reset;
END_CHECK: check_activate = !check_activate;
WIN: game_state = curr_player;
END_ROUND : begin
pointer_reset = !pointer_reset;
check_reset = !check_reset;
if (curr_player == BLACK) curr_player = WHITE;
else curr_player = BLACK;
end
endcase
end
always @(negedge SW[17], posedge CLOCK_50) begin
if (SW[17] == 1'b0) curr_state = END_ROUND;
else curr_state = nxt_state;
end
endmodule | 0 |
142,264 | data/full_repos/permissive/98490156/logic_part/mux2212.v | 98,490,156 | mux2212.v | v | 10 | 39 | [] | [] | [] | [(1, 9)] | null | data/verilator_xmls/f19fd4d0-4a0a-4755-98d0-70b2fb070b1b.xml | null | 313,502 | module | module mux2212(in1, in2, choice, out);
input[1:0] in1,in2;
input choice;
output reg [1:0] out;
always@(*) begin
if (choice == 1'b1) out = in1;
else out = in2;
end
endmodule | module mux2212(in1, in2, choice, out); |
input[1:0] in1,in2;
input choice;
output reg [1:0] out;
always@(*) begin
if (choice == 1'b1) out = in1;
else out = in2;
end
endmodule | 0 |
142,265 | data/full_repos/permissive/98490156/logic_part/overall_check.v | 98,490,156 | overall_check.v | v | 216 | 114 | [] | [] | [] | [(1, 48), (50, 215)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:16: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr1(.in(board), .select(ad1), .out(re1));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read.v\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read.sv\n Memory_Read\n Memory_Read.v\n Memory_Read.sv\n obj_dir/Memory_Read\n obj_dir/Memory_Read.v\n obj_dir/Memory_Read.sv\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:17: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr2(.in(board), .select(ad2), .out(re2));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:18: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr3(.in(board), .select(ad3), .out(re3));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:19: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr4(.in(board), .select(ad4), .out(re4));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:27: Cannot find file containing module: 'horizontal_check'\n horizontal_check ck0(.reset(reset_next), .active(active_next[0]), \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:32: Cannot find file containing module: 'verticle_check'\n verticle_check ck1(.reset(reset_next), .active(active_next[1]), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:37: Cannot find file containing module: 'lean1_check'\n lean1_check ck2(.reset(reset_next), .active(active_next[2]), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:42: Cannot find file containing module: 'lean2_check'\n lean2_check ck3(.reset(reset_next), .active(active_next[3]), \n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 313,504 | module | module overall_check(reset, active, pointer, chess, success, fail, board, clk);
input reset, active, clk;
input [1:0] chess;
input [7:0] pointer;
input [511:0] board;
output success, fail;
wire [3:0] active_next;
wire reset_next;
wire [3:0] success_result, active_next_result;
wire [1:0] re1, re2, re3, re4;
wire [7:0] ad1, ad2, ad3, ad4;
Memory_Read mr1(.in(board), .select(ad1), .out(re1));
Memory_Read mr2(.in(board), .select(ad2), .out(re2));
Memory_Read mr3(.in(board), .select(ad3), .out(re3));
Memory_Read mr4(.in(board), .select(ad4), .out(re4));
control counters_control(.clock(clk), .resetn(reset),
.go(active), .active_next(active_next_result[3:0]), .success(success_result[3:0]),
.set(reset_next), .active(active_next[3:0]), .final_suc(success), .final_fai(fail));
horizontal_check ck0(.reset(reset_next), .active(active_next[0]),
.pointer(pointer), .chess(chess), .address(ad1), .currstate(re1),
.success(success_result[0]), .active_next(active_next_result[0]),
.clk(clk));
verticle_check ck1(.reset(reset_next), .active(active_next[1]),
.pointer(pointer), .chess(chess), .address(ad2), .currstate(re2),
.success(success_result[1]), .active_next(active_next_result[1]),
.clk(clk));
lean1_check ck2(.reset(reset_next), .active(active_next[2]),
.pointer(pointer), .chess(chess), .address(ad3), .currstate(re3),
.success(success_result[2]), .active_next(active_next_result[2]),
.clk(clk));
lean2_check ck3(.reset(reset_next), .active(active_next[3]),
.pointer(pointer), .chess(chess), .address(ad4), .currstate(re4),
.success(success_result[3]), .active_next(active_next_result[3]),
.clk(clk));
endmodule | module overall_check(reset, active, pointer, chess, success, fail, board, clk); |
input reset, active, clk;
input [1:0] chess;
input [7:0] pointer;
input [511:0] board;
output success, fail;
wire [3:0] active_next;
wire reset_next;
wire [3:0] success_result, active_next_result;
wire [1:0] re1, re2, re3, re4;
wire [7:0] ad1, ad2, ad3, ad4;
Memory_Read mr1(.in(board), .select(ad1), .out(re1));
Memory_Read mr2(.in(board), .select(ad2), .out(re2));
Memory_Read mr3(.in(board), .select(ad3), .out(re3));
Memory_Read mr4(.in(board), .select(ad4), .out(re4));
control counters_control(.clock(clk), .resetn(reset),
.go(active), .active_next(active_next_result[3:0]), .success(success_result[3:0]),
.set(reset_next), .active(active_next[3:0]), .final_suc(success), .final_fai(fail));
horizontal_check ck0(.reset(reset_next), .active(active_next[0]),
.pointer(pointer), .chess(chess), .address(ad1), .currstate(re1),
.success(success_result[0]), .active_next(active_next_result[0]),
.clk(clk));
verticle_check ck1(.reset(reset_next), .active(active_next[1]),
.pointer(pointer), .chess(chess), .address(ad2), .currstate(re2),
.success(success_result[1]), .active_next(active_next_result[1]),
.clk(clk));
lean1_check ck2(.reset(reset_next), .active(active_next[2]),
.pointer(pointer), .chess(chess), .address(ad3), .currstate(re3),
.success(success_result[2]), .active_next(active_next_result[2]),
.clk(clk));
lean2_check ck3(.reset(reset_next), .active(active_next[3]),
.pointer(pointer), .chess(chess), .address(ad4), .currstate(re4),
.success(success_result[3]), .active_next(active_next_result[3]),
.clk(clk));
endmodule | 0 |
142,266 | data/full_repos/permissive/98490156/logic_part/overall_check.v | 98,490,156 | overall_check.v | v | 216 | 114 | [] | [] | [] | [(1, 48), (50, 215)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:16: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr1(.in(board), .select(ad1), .out(re1));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read.v\n data/full_repos/permissive/98490156/logic_part,data/full_repos/permissive/98490156/Memory_Read.sv\n Memory_Read\n Memory_Read.v\n Memory_Read.sv\n obj_dir/Memory_Read\n obj_dir/Memory_Read.v\n obj_dir/Memory_Read.sv\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:17: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr2(.in(board), .select(ad2), .out(re2));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:18: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr3(.in(board), .select(ad3), .out(re3));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:19: Cannot find file containing module: 'Memory_Read'\n Memory_Read mr4(.in(board), .select(ad4), .out(re4));\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:27: Cannot find file containing module: 'horizontal_check'\n horizontal_check ck0(.reset(reset_next), .active(active_next[0]), \n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:32: Cannot find file containing module: 'verticle_check'\n verticle_check ck1(.reset(reset_next), .active(active_next[1]), \n ^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:37: Cannot find file containing module: 'lean1_check'\n lean1_check ck2(.reset(reset_next), .active(active_next[2]), \n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/logic_part/overall_check.v:42: Cannot find file containing module: 'lean2_check'\n lean2_check ck3(.reset(reset_next), .active(active_next[3]), \n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n" | 313,504 | module | module control(clock, resetn, go, active_next, success, set, active, final_suc, final_fai);
input clock, resetn, go;
input [3:0] active_next, success;
output reg set;
output reg [3:0] active;
output reg final_suc, final_fai;
localparam HORI_CHECK = 4'd0,
HORI_WAIT = 4'd1,
VERTI_CHECK = 4'd2,
VERTI_WAIT = 4'd3,
LEAN_ONE_CHECK = 4'd4,
LEAN_ONE_WAIT = 4'd5,
LEAN_TWO_CHECK = 4'd6,
LEAN_TWO_WAIT = 4'd7,
SUCCESS = 4'd8,
FAIL = 4'd9,
INITIAL = 4'd10,
INITIAL_WAIT = 4'd11;
reg [3:0] current_state, next_state;
initial begin
set = 1'b1;
active = 4'd0;
final_fai = 1'b0;
final_suc = 1'b0;
current_state = INITIAL;
next_state = INITIAL;
end
always@(*)
begin: state_table
case (current_state)
INITIAL: if(go) next_state = INITIAL_WAIT;
else next_state = INITIAL;
INITIAL_WAIT: if(go) next_state = INITIAL_WAIT;
else next_state = HORI_CHECK;
HORI_CHECK: next_state = HORI_WAIT;
HORI_WAIT:
begin
if(success[0]) next_state = SUCCESS;
if(active_next[0]) next_state = VERTI_CHECK;
end
VERTI_CHECK: next_state = VERTI_WAIT;
VERTI_WAIT:
begin
if(success[1]) next_state = SUCCESS;
if(active_next[1]) next_state = LEAN_ONE_CHECK;
end
LEAN_ONE_CHECK: next_state = LEAN_ONE_WAIT;
LEAN_ONE_WAIT:
begin
if(success[2]) next_state = SUCCESS;
if(active_next[2]) next_state = LEAN_TWO_CHECK;
end
LEAN_TWO_CHECK: next_state = LEAN_TWO_WAIT;
LEAN_TWO_WAIT:
begin
if(success[3]) next_state = SUCCESS;
if(active_next[3]) next_state = FAIL;
end
SUCCESS: next_state = SUCCESS;
FAIL: next_state = FAIL;
default:
next_state = INITIAL;
endcase
end
always @(*)
begin: enable_signals
case (current_state)
INITIAL : begin
set = 1'b1;
active[3:0] = 4'd0;
final_suc = 1'b0;
final_fai = 1'b0;
end
INITIAL_WAIT : set = 1'b0;
HORI_CHECK : begin
set = 1'b1;
active[3:0] = 4'b0001;
end
HORI_WAIT : begin
set = 1'b0;
active[3:0] = 4'b0001;
end
VERTI_CHECK: begin
set = 1'b1;
active[3:0] = 4'b0010;
end
VERTI_WAIT: begin
set = 1'b0;
active[3:0] = 4'b0010;
end
LEAN_ONE_CHECK: begin
set = 1'b1;
active[3:0] = 4'b0100;
end
LEAN_ONE_WAIT: begin
set = 1'b0;
active[3:0] = 4'b0100;
end
LEAN_TWO_CHECK: begin
set = 1'b1;
active[3:0] = 4'b1000;
end
LEAN_TWO_WAIT: begin
set = 1'b0;
active[3:0] = 4'b1000;
end
SUCCESS: final_suc = 1'b1;
FAIL: final_fai = 1'b1;
endcase
end
always@(posedge clock, posedge resetn)
begin
if(resetn)
current_state <= INITIAL;
else
current_state <= next_state;
end
endmodule | module control(clock, resetn, go, active_next, success, set, active, final_suc, final_fai); |
input clock, resetn, go;
input [3:0] active_next, success;
output reg set;
output reg [3:0] active;
output reg final_suc, final_fai;
localparam HORI_CHECK = 4'd0,
HORI_WAIT = 4'd1,
VERTI_CHECK = 4'd2,
VERTI_WAIT = 4'd3,
LEAN_ONE_CHECK = 4'd4,
LEAN_ONE_WAIT = 4'd5,
LEAN_TWO_CHECK = 4'd6,
LEAN_TWO_WAIT = 4'd7,
SUCCESS = 4'd8,
FAIL = 4'd9,
INITIAL = 4'd10,
INITIAL_WAIT = 4'd11;
reg [3:0] current_state, next_state;
initial begin
set = 1'b1;
active = 4'd0;
final_fai = 1'b0;
final_suc = 1'b0;
current_state = INITIAL;
next_state = INITIAL;
end
always@(*)
begin: state_table
case (current_state)
INITIAL: if(go) next_state = INITIAL_WAIT;
else next_state = INITIAL;
INITIAL_WAIT: if(go) next_state = INITIAL_WAIT;
else next_state = HORI_CHECK;
HORI_CHECK: next_state = HORI_WAIT;
HORI_WAIT:
begin
if(success[0]) next_state = SUCCESS;
if(active_next[0]) next_state = VERTI_CHECK;
end
VERTI_CHECK: next_state = VERTI_WAIT;
VERTI_WAIT:
begin
if(success[1]) next_state = SUCCESS;
if(active_next[1]) next_state = LEAN_ONE_CHECK;
end
LEAN_ONE_CHECK: next_state = LEAN_ONE_WAIT;
LEAN_ONE_WAIT:
begin
if(success[2]) next_state = SUCCESS;
if(active_next[2]) next_state = LEAN_TWO_CHECK;
end
LEAN_TWO_CHECK: next_state = LEAN_TWO_WAIT;
LEAN_TWO_WAIT:
begin
if(success[3]) next_state = SUCCESS;
if(active_next[3]) next_state = FAIL;
end
SUCCESS: next_state = SUCCESS;
FAIL: next_state = FAIL;
default:
next_state = INITIAL;
endcase
end
always @(*)
begin: enable_signals
case (current_state)
INITIAL : begin
set = 1'b1;
active[3:0] = 4'd0;
final_suc = 1'b0;
final_fai = 1'b0;
end
INITIAL_WAIT : set = 1'b0;
HORI_CHECK : begin
set = 1'b1;
active[3:0] = 4'b0001;
end
HORI_WAIT : begin
set = 1'b0;
active[3:0] = 4'b0001;
end
VERTI_CHECK: begin
set = 1'b1;
active[3:0] = 4'b0010;
end
VERTI_WAIT: begin
set = 1'b0;
active[3:0] = 4'b0010;
end
LEAN_ONE_CHECK: begin
set = 1'b1;
active[3:0] = 4'b0100;
end
LEAN_ONE_WAIT: begin
set = 1'b0;
active[3:0] = 4'b0100;
end
LEAN_TWO_CHECK: begin
set = 1'b1;
active[3:0] = 4'b1000;
end
LEAN_TWO_WAIT: begin
set = 1'b0;
active[3:0] = 4'b1000;
end
SUCCESS: final_suc = 1'b1;
FAIL: final_fai = 1'b1;
endcase
end
always@(posedge clock, posedge resetn)
begin
if(resetn)
current_state <= INITIAL;
else
current_state <= next_state;
end
endmodule | 0 |
142,267 | data/full_repos/permissive/98490156/logic_part/pointer.v | 98,490,156 | pointer.v | v | 23 | 46 | [] | [] | [] | [(1, 22)] | null | data/verilator_xmls/82637397-94f9-425a-9298-88b5b669ca73.xml | null | 313,505 | module | module pointer(inx, iny, reset, loca);
input inx, iny, reset;
output reg [7:0] loca;
initial begin
loca[7:0] = 8'd0;
end
always @(negedge inx, posedge reset) begin
if (reset == 1'b1) loca[3:0] = 4'd0;
else begin
if (loca[3:0] == 4'b1111) loca[3:0] = 4'd0;
else loca[3:0] = loca[3:0] + 4'b1;
end
end
always @(negedge iny, posedge reset) begin
if (reset == 1'b1) loca[7:4] = 4'd0;
else begin
if (loca[7:4] == 4'b1111) loca[7:4] = 4'd0;
else loca[7:4] = loca[7:4] + 4'b1;
end
end
endmodule | module pointer(inx, iny, reset, loca); |
input inx, iny, reset;
output reg [7:0] loca;
initial begin
loca[7:0] = 8'd0;
end
always @(negedge inx, posedge reset) begin
if (reset == 1'b1) loca[3:0] = 4'd0;
else begin
if (loca[3:0] == 4'b1111) loca[3:0] = 4'd0;
else loca[3:0] = loca[3:0] + 4'b1;
end
end
always @(negedge iny, posedge reset) begin
if (reset == 1'b1) loca[7:4] = 4'd0;
else begin
if (loca[7:4] == 4'b1111) loca[7:4] = 4'd0;
else loca[7:4] = loca[7:4] + 4'b1;
end
end
endmodule | 0 |
142,268 | data/full_repos/permissive/98490156/logic_part/pospulse_gen.v | 98,490,156 | pospulse_gen.v | v | 8 | 37 | [] | [] | [] | [(1, 8)] | null | data/verilator_xmls/41f76d70-6a9d-486e-a362-fb84b0991d52.xml | null | 313,506 | module | module pospulse_gen(in, pulse, clk);
input in;
input clk;
output pulse;
reg state;
always @(posedge clk) state <= in;
assign pulse = state != in;
endmodule | module pospulse_gen(in, pulse, clk); |
input in;
input clk;
output pulse;
reg state;
always @(posedge clk) state <= in;
assign pulse = state != in;
endmodule | 0 |
142,269 | data/full_repos/permissive/98490156/lowlevelabs/flasher.v | 98,490,156 | flasher.v | v | 161 | 64 | [] | [] | [] | null | line:137: before: "." | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:29: Define or directive not defined: \'`COLOR_SIZE\'\n input [`COLOR_SIZE - 1: 0] read_data;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:31: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\n output reg [`MEMORY_SIZE_BITS - 1 : 0] read_addr;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:52: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n reg [`SCR_WIDTH_BITS - 1: 0] x_co;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:53: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n reg [`SCR_HEIGHT_BITS - 1 :0] y_co;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:107: Define or directive not defined: \'`COOR_TO_OFFSET\'\n read_addr = `COOR_TO_OFFSET(x_co, y_co);\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:107: syntax error, unexpected \',\'\n read_addr = `COOR_TO_OFFSET(x_co, y_co);\n ^\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:122: Define or directive not defined: \'`SCR_WIDTH\'\n if(x_co == `SCR_WIDTH && y_co == `SCR_HEIGHT)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:122: syntax error, unexpected &&, expecting TYPE-IDENTIFIER\n if(x_co == `SCR_WIDTH && y_co == `SCR_HEIGHT)\n ^~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:122: Define or directive not defined: \'`SCR_HEIGHT\'\n if(x_co == `SCR_WIDTH && y_co == `SCR_HEIGHT)\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:128: syntax error, unexpected else, expecting endcase\n else\n ^~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:130: Define or directive not defined: \'`SCR_WIDTH\'\n if (x_co == `SCR_WIDTH)\n ^~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/flasher.v:138: syntax error, unexpected \'=\', expecting IDENTIFIER\n each_cycle = READ_DATA;\n ^\n%Error: Cannot continue\n' | 313,507 | module | module screenFlash(
Clck,
in_cont_signal,
read_addr,
read_data,
Reset,
out_cont_signal,
next_fin_signal,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input Clck, in_cont_signal, Reset, next_fin_signal;
input [`COLOR_SIZE - 1: 0] read_data;
output reg out_cont_signal;
output reg [`MEMORY_SIZE_BITS - 1 : 0] read_addr;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
reg [1:0] each_cycle;
reg print_enable;
localparam READ_DATA = 2'b00,
SET_CO = 2'b01,
START_PR = 2'b10,
FINIS_PR = 2'b11;
reg [`SCR_WIDTH_BITS - 1: 0] x_co;
reg [`SCR_HEIGHT_BITS - 1 :0] y_co;
vga_adapter VGA(
.resetn(Reset),
.clock(Clck),
.colour(read_data),
.x(x_co),
.y(y_co),
.plot(print_enable),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
initial
begin
out_cont_signal = 0;
read_addr = 0;
x_co = 0;
y_co = 0;
each_cycle = READ_DATA;
print_enable = 0;
out_cont_signal = 0;
end
always@(posedge Clck)
begin
if(Reset == 0)
begin
out_cont_signal = 0;
x_co = 0;
y_co = 0;
each_cycle = READ_DATA;
end
else
if(in_cont_signal == 1 && out_cont_signal == 0)
begin
case(each_cycle)
READ_DATA:
begin
read_addr = `COOR_TO_OFFSET(x_co, y_co);
each_cycle = START_PR;
end
START_PR:
begin
print_enable = 1;
each_cycle = FINIS_PR;
end
FINIS_PR:
begin
print_enable = 0;
each_cycle = SET_CO;
end
SET_CO:
begin
if(x_co == `SCR_WIDTH && y_co == `SCR_HEIGHT)
begin
x_co = 0;
y_co = 0;
out_cont_signal = 1;
end
else
begin
if (x_co == `SCR_WIDTH)
begin
y_co = y_co + 1'd1;
x_co = 0;
end
else
x_co = x_co + 1'd1;
end
each_cycle = READ_DATA;
end
endcase
end
else
if(next_fin_signal == 1)
out_cont_signal = 0;
end
endmodule | module screenFlash(
Clck,
in_cont_signal,
read_addr,
read_data,
Reset,
out_cont_signal,
next_fin_signal,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input Clck, in_cont_signal, Reset, next_fin_signal;
input [`COLOR_SIZE - 1: 0] read_data;
output reg out_cont_signal;
output reg [`MEMORY_SIZE_BITS - 1 : 0] read_addr;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
reg [1:0] each_cycle;
reg print_enable;
localparam READ_DATA = 2'b00,
SET_CO = 2'b01,
START_PR = 2'b10,
FINIS_PR = 2'b11;
reg [`SCR_WIDTH_BITS - 1: 0] x_co;
reg [`SCR_HEIGHT_BITS - 1 :0] y_co;
vga_adapter VGA(
.resetn(Reset),
.clock(Clck),
.colour(read_data),
.x(x_co),
.y(y_co),
.plot(print_enable),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
initial
begin
out_cont_signal = 0;
read_addr = 0;
x_co = 0;
y_co = 0;
each_cycle = READ_DATA;
print_enable = 0;
out_cont_signal = 0;
end
always@(posedge Clck)
begin
if(Reset == 0)
begin
out_cont_signal = 0;
x_co = 0;
y_co = 0;
each_cycle = READ_DATA;
end
else
if(in_cont_signal == 1 && out_cont_signal == 0)
begin
case(each_cycle)
READ_DATA:
begin
read_addr = `COOR_TO_OFFSET(x_co, y_co);
each_cycle = START_PR;
end
START_PR:
begin
print_enable = 1;
each_cycle = FINIS_PR;
end
FINIS_PR:
begin
print_enable = 0;
each_cycle = SET_CO;
end
SET_CO:
begin
if(x_co == `SCR_WIDTH && y_co == `SCR_HEIGHT)
begin
x_co = 0;
y_co = 0;
out_cont_signal = 1;
end
else
begin
if (x_co == `SCR_WIDTH)
begin
y_co = y_co + 1'd1;
x_co = 0;
end
else
x_co = x_co + 1'd1;
end
each_cycle = READ_DATA;
end
endcase
end
else
if(next_fin_signal == 1)
out_cont_signal = 0;
end
endmodule | 0 |
142,270 | data/full_repos/permissive/98490156/lowlevelabs/llabs.v | 98,490,156 | llabs.v | v | 161 | 91 | [] | [] | [] | [(66, 197), (199, 224)] | null | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:30: Define or directive not defined: \'`BOARD_SIZE\'\n input [`BOARD_SIZE - 1 : 0] board;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:31: Define or directive not defined: \'`WINNING_STATUS_BITS\'\n input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:32: Define or directive not defined: \'`BOARD_WIDTH_BITS\'\n input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:33: Define or directive not defined: \'`BOARD_HEIGHT_BITS\'\n input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:53: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\n wire [`MEMORY_SIZE_BITS - 1:0] address_0, address_1, address_2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:54: Define or directive not defined: \'`COLOR_SIZE\'\n wire [`COLOR_SIZE - 1 : 0] color;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:56: Define or directive not defined: \'`COLOR_SIZE\'\n wire [`COLOR_SIZE - 1: 0] mem_output;\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 313,509 | module | module llabs(
working,
Clck,
board,
gaming_status,
pointer_loc_x,
pointer_loc_y,
Reset,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B,
debug_output
);
input Clck, Reset, working;
input [`BOARD_SIZE - 1 : 0] board;
input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;
input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output [50:0] debug_output;
wire DummyStart_painter, painter_flasher, flasher_DummyStart;
wire [`MEMORY_SIZE_BITS - 1:0] address_0, address_1, address_2;
wire [`COLOR_SIZE - 1 : 0] color;
wire print_enable;
wire [`COLOR_SIZE - 1: 0] mem_output;
ram1122x3 videoMem(
.address(address_0),
.clock(Clck),
.data(color),
.wren(print_enable),
.q(mem_output)
);
assign address_0 = address_1 | address_2;
assign debug_output[2:0] = {DummyStart_painter, painter_flasher, flasher_DummyStart};
DummyStart ds(
.working(working),
.in_cont_signal(flasher_DummyStart),
.out_cont_signal(DummyStart_painter),
.next_out_cont_signal(painter_flasher),
.Clck(Clck)
);
painter pt(
.in_cont_signal(DummyStart_painter),
.out_cont_signal(painter_flasher),
.next_out_cont_signal(flasher_DummyStart),
.board(board),
.winning_information(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_x),
.Clck(Clck),
.Reset(Reset),
.address(address_1),
.color(color),
.print_enable(print_enable)
);
screenFlash sf(
.Clck(Clck),
.in_cont_signal(painter_flasher),
.read_addr(address_2),
.read_data(mem_output),
.Reset(Reset),
.out_cont_signal(flasher_DummyStart),
.next_fin_signal(DummyStart_painter),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule | module llabs(
working,
Clck,
board,
gaming_status,
pointer_loc_x,
pointer_loc_y,
Reset,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B,
debug_output
); |
input Clck, Reset, working;
input [`BOARD_SIZE - 1 : 0] board;
input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;
input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
output [50:0] debug_output;
wire DummyStart_painter, painter_flasher, flasher_DummyStart;
wire [`MEMORY_SIZE_BITS - 1:0] address_0, address_1, address_2;
wire [`COLOR_SIZE - 1 : 0] color;
wire print_enable;
wire [`COLOR_SIZE - 1: 0] mem_output;
ram1122x3 videoMem(
.address(address_0),
.clock(Clck),
.data(color),
.wren(print_enable),
.q(mem_output)
);
assign address_0 = address_1 | address_2;
assign debug_output[2:0] = {DummyStart_painter, painter_flasher, flasher_DummyStart};
DummyStart ds(
.working(working),
.in_cont_signal(flasher_DummyStart),
.out_cont_signal(DummyStart_painter),
.next_out_cont_signal(painter_flasher),
.Clck(Clck)
);
painter pt(
.in_cont_signal(DummyStart_painter),
.out_cont_signal(painter_flasher),
.next_out_cont_signal(flasher_DummyStart),
.board(board),
.winning_information(gaming_status),
.pointer_loc_x(pointer_loc_x),
.pointer_loc_y(pointer_loc_x),
.Clck(Clck),
.Reset(Reset),
.address(address_1),
.color(color),
.print_enable(print_enable)
);
screenFlash sf(
.Clck(Clck),
.in_cont_signal(painter_flasher),
.read_addr(address_2),
.read_data(mem_output),
.Reset(Reset),
.out_cont_signal(flasher_DummyStart),
.next_fin_signal(DummyStart_painter),
.VGA_CLK(VGA_CLK),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK_N(VGA_BLANK_N),
.VGA_SYNC_N(VGA_SYNC_N),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)
);
endmodule | 0 |
142,271 | data/full_repos/permissive/98490156/lowlevelabs/llabs.v | 98,490,156 | llabs.v | v | 161 | 91 | [] | [] | [] | [(66, 197), (199, 224)] | null | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:30: Define or directive not defined: \'`BOARD_SIZE\'\n input [`BOARD_SIZE - 1 : 0] board;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:31: Define or directive not defined: \'`WINNING_STATUS_BITS\'\n input [`WINNING_STATUS_BITS - 1 : 0] gaming_status;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:32: Define or directive not defined: \'`BOARD_WIDTH_BITS\'\n input [`BOARD_WIDTH_BITS - 1 : 0] pointer_loc_x;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:33: Define or directive not defined: \'`BOARD_HEIGHT_BITS\'\n input [`BOARD_HEIGHT_BITS - 1 : 0] pointer_loc_y;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:53: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\n wire [`MEMORY_SIZE_BITS - 1:0] address_0, address_1, address_2;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:54: Define or directive not defined: \'`COLOR_SIZE\'\n wire [`COLOR_SIZE - 1 : 0] color;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/llabs.v:56: Define or directive not defined: \'`COLOR_SIZE\'\n wire [`COLOR_SIZE - 1: 0] mem_output;\n ^~~~~~~~~~~\n%Error: Exiting due to 8 error(s)\n' | 313,509 | module | module DummyStart(
working,
in_cont_signal,
out_cont_signal,
next_out_cont_signal,
Clck
);
input working, in_cont_signal, next_out_cont_signal, Clck;
output reg out_cont_signal;
always@(posedge Clck)
begin
if(next_out_cont_signal == 1)
out_cont_signal = 0;
else
if(in_cont_signal == 1 || working == 1)
out_cont_signal = 1;
end
endmodule | module DummyStart(
working,
in_cont_signal,
out_cont_signal,
next_out_cont_signal,
Clck
); |
input working, in_cont_signal, next_out_cont_signal, Clck;
output reg out_cont_signal;
always@(posedge Clck)
begin
if(next_out_cont_signal == 1)
out_cont_signal = 0;
else
if(in_cont_signal == 1 || working == 1)
out_cont_signal = 1;
end
endmodule | 0 |
142,272 | data/full_repos/permissive/98490156/lowlevelabs/painter.v | 98,490,156 | painter.v | v | 356 | 97 | [] | [] | [] | [(66, 291), (294, 418)] | null | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:30: Define or directive not defined: \'`BOARD_SIZE\'\n input [`BOARD_SIZE - 1:0] board;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:31: Define or directive not defined: \'`WINNING_STATUS_BITS\'\n input [`WINNING_STATUS_BITS - 1 : 0] winning_information;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:32: Define or directive not defined: \'`BOARD_WIDTH_BITS\'\n input [`BOARD_WIDTH_BITS - 1:0] pointer_loc_x;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:33: Define or directive not defined: \'`BOARD_HEIGHT_BITS\'\n input [`BOARD_HEIGHT_BITS - 1:0] pointer_loc_y;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:36: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\n output [`MEMORY_SIZE_BITS - 1 : 0] address;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:61: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n reg [`SCR_WIDTH_BITS - 1 : 0] board_x;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:62: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n reg [`SCR_HEIGHT_BITS - 1 : 0] board_y;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:63: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:64: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`MAP_BOARDXY_BOARDCO\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: syntax error, unexpected \',\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`CHESS_STATUS_BITS\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`CHESS_WITH_NONE\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: Define or directive not defined: \'`MAP_BOARDXY_BOARDCO\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: syntax error, unexpected \',\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: Define or directive not defined: \'`CHESS_STATUS_BITS\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:137: Define or directive not defined: \'`CHESS_WITH_BLACK\'\n `CHESS_WITH_BLACK: color = COLOR_BLACK;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:138: Define or directive not defined: \'`CHESS_WITH_BLUE\'\n `CHESS_WITH_BLUE : color = COLOR_BLUE;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:139: Define or directive not defined: \'`CHESS_WITH_WIN\'\n `CHESS_WITH_WIN: color = COLOR_YELLOW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:140: Define or directive not defined: \'`CHESS_WITH_NONE\'\n `CHESS_WITH_NONE : color = COLOR_BLACK;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:143: Define or directive not defined: \'`MAP_BOARDXCO_PIXELXCOSTART\'\n pixel_x_start = `MAP_BOARDXCO_PIXELXCOSTART(board_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:144: Define or directive not defined: \'`MAP_BOARDYCO_PIXELYCOSTART\'\n pixel_y_start = `MAP_BOARDYCO_PIXELYCOSTART(board_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:145: Define or directive not defined: \'`MAP_BOARDXCO_PIXELXCOEND\'\n pixel_x_end = `MAP_BOARDXCO_PIXELXCOEND(board_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:146: Define or directive not defined: \'`MAP_BOARDYCO_PIXELYCOEND\'\n pixel_y_end = `MAP_BOARDYCO_PIXELYCOEND(board_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:155: Define or directive not defined: \'`BOARD_WIDTH\'\n if(board_x == `BOARD_WIDTH - 1 &&\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:156: Define or directive not defined: \'`BOARD_HEIGHT\'\n board_y == `BOARD_HEIGHT - 1)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:164: Define or directive not defined: \'`BOARD_WIDTH\'\n if(board_x == `BOARD_WIDTH - 1)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:190: Define or directive not defined: \'`MAP_POINTERCO_PIXELCO\'\n pixel_x_start = `MAP_POINTERCO_PIXELCO(pointer_loc_x);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:191: Define or directive not defined: \'`MAP_POINTERCO_PIXELCO\'\n pixel_y_start = `MAP_POINTERCO_PIXELCO(pointer_loc_y);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:192: Define or directive not defined: \'`MAP_POINTERCO_PIXELCOEND\'\n pixel_x_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:193: Define or directive not defined: \'`MAP_POINTERCO_PIXELCOEND\'\n pixel_y_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:217: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:254: Define or directive not defined: \'`SCR_WIDTH_BITS\'\ninput [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:255: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\ninput [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:257: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\noutput reg [`MEMORY_SIZE_BITS - 1 : 0] address;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:277: Define or directive not defined: \'`SCR_WIDTH_BITS\'\nreg [`SCR_WIDTH_BITS - 1 : 0] pixel_x, pixel_x_reco_start, pixel_x_reco_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:278: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\nreg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y, pixel_y_reco_start, pixel_y_reco_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:312: Define or directive not defined: \'`MAP_PIXELCO_MEMADDR\'\n address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:312: syntax error, unexpected \',\'\n address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);\n ^\n%Error: Exiting due to 40 error(s)\n' | 313,510 | module | module painter(
in_cont_signal,
out_cont_signal,
next_out_cont_signal,
board,
winning_information,
pointer_loc_x,
pointer_loc_y,
Clck,
Reset,
address,
color,
print_enable
);
input in_cont_signal, next_out_cont_signal, Clck, Reset;
input [`BOARD_SIZE - 1:0] board;
input [`WINNING_STATUS_BITS - 1 : 0] winning_information;
input [`BOARD_WIDTH_BITS - 1:0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1:0] pointer_loc_y;
output reg out_cont_signal;
output print_enable;
output [`MEMORY_SIZE_BITS - 1 : 0] address;
output reg [2:0] color;
localparam
CP_LOAD_VAL = 2'd0,
CP_PAINT_EN = 2'd1,
CP_PAINT_DE = 2'd2,
CP_NEXT_VAL = 2'd3,
POINTERP_LOAD_VAL = 2'd0,
POINTERP_PAINT = 2'd1,
COLOR_BLACK = 3'b010,
COLOR_BLUE = 3'b001,
COLOR_YELLOW= 3'b110,
BOARD_PAINTING = 2'd0,
CHESS_PAINTING = 2'd1,
POINTER_PAINTING = 2'd2,
UPPER_PAINTING = 2'd3,
FINDING = 1'd0,
PAINTING = 1'd1;
reg [1:0] PAINTING_STAGE;
reg [1:0] POINTER_PAINTING_STAGE;
reg [`SCR_WIDTH_BITS - 1 : 0] board_x;
reg [`SCR_HEIGHT_BITS - 1 : 0] board_y;
reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;
reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;
reg CHESS_CYCLE;
reg start_paint_chess, paint_chess_load;
wire end_paint_chess;
initial
begin
board_x = 0;
board_y = 0;
pixel_x_start = 0;
pixel_y_start = 0;
pixel_x_end = 0;
pixel_y_end = 0;
PAINTING_STAGE = CHESS_PAINTING;
CHESS_CYCLE = FINDING;
color = 0;
POINTER_PAINTING_STAGE = POINTERP_LOAD_VAL;
out_cont_signal = 0;
start_paint_chess = 0;
paint_chess_load = 0;
end
paint_chess pc(
.pixel_x_start(pixel_x_start),
.pixel_y_start(pixel_y_start),
.pixel_x_end(pixel_x_end),
.pixel_y_end(pixel_y_end),
.address(address),
.print_enable(print_enable),
.Clck(Clck),
.in_cont_signal(start_paint_chess),
.out_cont_signal(end_paint_chess),
.pixel_load_signal(paint_chess_load)
);
always@(posedge Clck)
begin
if(Reset == 0)
begin
end
else
if(in_cont_signal == 1 && out_cont_signal == 0)
begin
if(PAINTING_STAGE == BOARD_PAINTING)
begin
PAINTING_STAGE = CHESS_PAINTING;
end
if(PAINTING_STAGE == CHESS_PAINTING)
begin
if(CHESS_CYCLE == FINDING)
begin
if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)
begin
CHESS_CYCLE = PAINTING;
case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])
`CHESS_WITH_BLACK: color = COLOR_BLACK;
`CHESS_WITH_BLUE : color = COLOR_BLUE;
`CHESS_WITH_WIN: color = COLOR_YELLOW;
`CHESS_WITH_NONE : color = COLOR_BLACK;
endcase
pixel_x_start = `MAP_BOARDXCO_PIXELXCOSTART(board_x);
pixel_y_start = `MAP_BOARDYCO_PIXELYCOSTART(board_y);
pixel_x_end = `MAP_BOARDXCO_PIXELXCOEND(board_x);
pixel_y_end = `MAP_BOARDYCO_PIXELYCOEND(board_y);
paint_chess_load = 1;
start_paint_chess = 1;
end
if(board_x == `BOARD_WIDTH - 1 &&
board_y == `BOARD_HEIGHT - 1)
begin
PAINTING_STAGE = POINTER_PAINTING;
CHESS_CYCLE = FINDING;
end
else
if(board_x == `BOARD_WIDTH - 1)
begin
board_y = board_y + 1'd1;
board_x = 0;
end
else
board_x = board_x + 1'd1;
end
else
begin
if(end_paint_chess == 1)
begin
start_paint_chess = 0;
CHESS_CYCLE = FINDING;
end
paint_chess_load = 0;
end
end
if(PAINTING_STAGE == POINTER_PAINTING)
begin
if(POINTER_PAINTING_STAGE == POINTERP_LOAD_VAL)
begin
pixel_x_start = `MAP_POINTERCO_PIXELCO(pointer_loc_x);
pixel_y_start = `MAP_POINTERCO_PIXELCO(pointer_loc_y);
pixel_x_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_x);
pixel_y_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_y);
POINTER_PAINTING_STAGE = POINTER_PAINTING;
start_paint_chess = 1;
end
else
begin
if(end_paint_chess == 1)
begin
start_paint_chess = 0;
POINTER_PAINTING_STAGE = POINTERP_LOAD_VAL;
PAINTING_STAGE = UPPER_PAINTING;
end
end
end
if(PAINTING_STAGE == UPPER_PAINTING)
begin
PAINTING_STAGE = BOARD_PAINTING;
out_cont_signal = 1;
end
end
else
begin
if(next_out_cont_signal == 1)
out_cont_signal = 0;
end
end
endmodule | module painter(
in_cont_signal,
out_cont_signal,
next_out_cont_signal,
board,
winning_information,
pointer_loc_x,
pointer_loc_y,
Clck,
Reset,
address,
color,
print_enable
); |
input in_cont_signal, next_out_cont_signal, Clck, Reset;
input [`BOARD_SIZE - 1:0] board;
input [`WINNING_STATUS_BITS - 1 : 0] winning_information;
input [`BOARD_WIDTH_BITS - 1:0] pointer_loc_x;
input [`BOARD_HEIGHT_BITS - 1:0] pointer_loc_y;
output reg out_cont_signal;
output print_enable;
output [`MEMORY_SIZE_BITS - 1 : 0] address;
output reg [2:0] color;
localparam
CP_LOAD_VAL = 2'd0,
CP_PAINT_EN = 2'd1,
CP_PAINT_DE = 2'd2,
CP_NEXT_VAL = 2'd3,
POINTERP_LOAD_VAL = 2'd0,
POINTERP_PAINT = 2'd1,
COLOR_BLACK = 3'b010,
COLOR_BLUE = 3'b001,
COLOR_YELLOW= 3'b110,
BOARD_PAINTING = 2'd0,
CHESS_PAINTING = 2'd1,
POINTER_PAINTING = 2'd2,
UPPER_PAINTING = 2'd3,
FINDING = 1'd0,
PAINTING = 1'd1;
reg [1:0] PAINTING_STAGE;
reg [1:0] POINTER_PAINTING_STAGE;
reg [`SCR_WIDTH_BITS - 1 : 0] board_x;
reg [`SCR_HEIGHT_BITS - 1 : 0] board_y;
reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;
reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;
reg CHESS_CYCLE;
reg start_paint_chess, paint_chess_load;
wire end_paint_chess;
initial
begin
board_x = 0;
board_y = 0;
pixel_x_start = 0;
pixel_y_start = 0;
pixel_x_end = 0;
pixel_y_end = 0;
PAINTING_STAGE = CHESS_PAINTING;
CHESS_CYCLE = FINDING;
color = 0;
POINTER_PAINTING_STAGE = POINTERP_LOAD_VAL;
out_cont_signal = 0;
start_paint_chess = 0;
paint_chess_load = 0;
end
paint_chess pc(
.pixel_x_start(pixel_x_start),
.pixel_y_start(pixel_y_start),
.pixel_x_end(pixel_x_end),
.pixel_y_end(pixel_y_end),
.address(address),
.print_enable(print_enable),
.Clck(Clck),
.in_cont_signal(start_paint_chess),
.out_cont_signal(end_paint_chess),
.pixel_load_signal(paint_chess_load)
);
always@(posedge Clck)
begin
if(Reset == 0)
begin
end
else
if(in_cont_signal == 1 && out_cont_signal == 0)
begin
if(PAINTING_STAGE == BOARD_PAINTING)
begin
PAINTING_STAGE = CHESS_PAINTING;
end
if(PAINTING_STAGE == CHESS_PAINTING)
begin
if(CHESS_CYCLE == FINDING)
begin
if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)
begin
CHESS_CYCLE = PAINTING;
case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])
`CHESS_WITH_BLACK: color = COLOR_BLACK;
`CHESS_WITH_BLUE : color = COLOR_BLUE;
`CHESS_WITH_WIN: color = COLOR_YELLOW;
`CHESS_WITH_NONE : color = COLOR_BLACK;
endcase
pixel_x_start = `MAP_BOARDXCO_PIXELXCOSTART(board_x);
pixel_y_start = `MAP_BOARDYCO_PIXELYCOSTART(board_y);
pixel_x_end = `MAP_BOARDXCO_PIXELXCOEND(board_x);
pixel_y_end = `MAP_BOARDYCO_PIXELYCOEND(board_y);
paint_chess_load = 1;
start_paint_chess = 1;
end
if(board_x == `BOARD_WIDTH - 1 &&
board_y == `BOARD_HEIGHT - 1)
begin
PAINTING_STAGE = POINTER_PAINTING;
CHESS_CYCLE = FINDING;
end
else
if(board_x == `BOARD_WIDTH - 1)
begin
board_y = board_y + 1'd1;
board_x = 0;
end
else
board_x = board_x + 1'd1;
end
else
begin
if(end_paint_chess == 1)
begin
start_paint_chess = 0;
CHESS_CYCLE = FINDING;
end
paint_chess_load = 0;
end
end
if(PAINTING_STAGE == POINTER_PAINTING)
begin
if(POINTER_PAINTING_STAGE == POINTERP_LOAD_VAL)
begin
pixel_x_start = `MAP_POINTERCO_PIXELCO(pointer_loc_x);
pixel_y_start = `MAP_POINTERCO_PIXELCO(pointer_loc_y);
pixel_x_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_x);
pixel_y_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_y);
POINTER_PAINTING_STAGE = POINTER_PAINTING;
start_paint_chess = 1;
end
else
begin
if(end_paint_chess == 1)
begin
start_paint_chess = 0;
POINTER_PAINTING_STAGE = POINTERP_LOAD_VAL;
PAINTING_STAGE = UPPER_PAINTING;
end
end
end
if(PAINTING_STAGE == UPPER_PAINTING)
begin
PAINTING_STAGE = BOARD_PAINTING;
out_cont_signal = 1;
end
end
else
begin
if(next_out_cont_signal == 1)
out_cont_signal = 0;
end
end
endmodule | 0 |
142,273 | data/full_repos/permissive/98490156/lowlevelabs/painter.v | 98,490,156 | painter.v | v | 356 | 97 | [] | [] | [] | [(66, 291), (294, 418)] | null | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:1: Cannot find include file: header.v\n`include "header.v" \n ^~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.v\n data/full_repos/permissive/98490156/lowlevelabs,data/full_repos/permissive/98490156/header.v.sv\n header.v\n header.v.v\n header.v.sv\n obj_dir/header.v\n obj_dir/header.v.v\n obj_dir/header.v.sv\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:30: Define or directive not defined: \'`BOARD_SIZE\'\n input [`BOARD_SIZE - 1:0] board;\n ^~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:31: Define or directive not defined: \'`WINNING_STATUS_BITS\'\n input [`WINNING_STATUS_BITS - 1 : 0] winning_information;\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:32: Define or directive not defined: \'`BOARD_WIDTH_BITS\'\n input [`BOARD_WIDTH_BITS - 1:0] pointer_loc_x;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:33: Define or directive not defined: \'`BOARD_HEIGHT_BITS\'\n input [`BOARD_HEIGHT_BITS - 1:0] pointer_loc_y;\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:36: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\n output [`MEMORY_SIZE_BITS - 1 : 0] address;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:61: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n reg [`SCR_WIDTH_BITS - 1 : 0] board_x;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:62: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n reg [`SCR_HEIGHT_BITS - 1 : 0] board_y;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:63: Define or directive not defined: \'`SCR_WIDTH_BITS\'\n reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:64: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\n reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`MAP_BOARDXY_BOARDCO\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: syntax error, unexpected \',\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`CHESS_STATUS_BITS\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:132: Define or directive not defined: \'`CHESS_WITH_NONE\'\n if(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS] != `CHESS_WITH_NONE)\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: Define or directive not defined: \'`MAP_BOARDXY_BOARDCO\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: syntax error, unexpected \',\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:136: Define or directive not defined: \'`CHESS_STATUS_BITS\'\n case(board[`MAP_BOARDXY_BOARDCO(board_x, board_y) +: `CHESS_STATUS_BITS])\n ^~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:137: Define or directive not defined: \'`CHESS_WITH_BLACK\'\n `CHESS_WITH_BLACK: color = COLOR_BLACK;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:138: Define or directive not defined: \'`CHESS_WITH_BLUE\'\n `CHESS_WITH_BLUE : color = COLOR_BLUE;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:139: Define or directive not defined: \'`CHESS_WITH_WIN\'\n `CHESS_WITH_WIN: color = COLOR_YELLOW;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:140: Define or directive not defined: \'`CHESS_WITH_NONE\'\n `CHESS_WITH_NONE : color = COLOR_BLACK;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:143: Define or directive not defined: \'`MAP_BOARDXCO_PIXELXCOSTART\'\n pixel_x_start = `MAP_BOARDXCO_PIXELXCOSTART(board_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:144: Define or directive not defined: \'`MAP_BOARDYCO_PIXELYCOSTART\'\n pixel_y_start = `MAP_BOARDYCO_PIXELYCOSTART(board_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:145: Define or directive not defined: \'`MAP_BOARDXCO_PIXELXCOEND\'\n pixel_x_end = `MAP_BOARDXCO_PIXELXCOEND(board_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:146: Define or directive not defined: \'`MAP_BOARDYCO_PIXELYCOEND\'\n pixel_y_end = `MAP_BOARDYCO_PIXELYCOEND(board_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:155: Define or directive not defined: \'`BOARD_WIDTH\'\n if(board_x == `BOARD_WIDTH - 1 &&\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:156: Define or directive not defined: \'`BOARD_HEIGHT\'\n board_y == `BOARD_HEIGHT - 1)\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:164: Define or directive not defined: \'`BOARD_WIDTH\'\n if(board_x == `BOARD_WIDTH - 1)\n ^~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:190: Define or directive not defined: \'`MAP_POINTERCO_PIXELCO\'\n pixel_x_start = `MAP_POINTERCO_PIXELCO(pointer_loc_x);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:191: Define or directive not defined: \'`MAP_POINTERCO_PIXELCO\'\n pixel_y_start = `MAP_POINTERCO_PIXELCO(pointer_loc_y);\n ^~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:192: Define or directive not defined: \'`MAP_POINTERCO_PIXELCOEND\'\n pixel_x_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_x);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:193: Define or directive not defined: \'`MAP_POINTERCO_PIXELCOEND\'\n pixel_y_end = `MAP_POINTERCO_PIXELCOEND(pointer_loc_y);\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:217: syntax error, unexpected else\n else\n ^~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:254: Define or directive not defined: \'`SCR_WIDTH_BITS\'\ninput [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:255: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\ninput [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:257: Define or directive not defined: \'`MEMORY_SIZE_BITS\'\noutput reg [`MEMORY_SIZE_BITS - 1 : 0] address;\n ^~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:277: Define or directive not defined: \'`SCR_WIDTH_BITS\'\nreg [`SCR_WIDTH_BITS - 1 : 0] pixel_x, pixel_x_reco_start, pixel_x_reco_end;\n ^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:278: Define or directive not defined: \'`SCR_HEIGHT_BITS\'\nreg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y, pixel_y_reco_start, pixel_y_reco_end;\n ^~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:312: Define or directive not defined: \'`MAP_PIXELCO_MEMADDR\'\n address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);\n ^~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/lowlevelabs/painter.v:312: syntax error, unexpected \',\'\n address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);\n ^\n%Error: Exiting due to 40 error(s)\n' | 313,510 | module | module paint_chess(
pixel_x_start,
pixel_y_start,
pixel_x_end,
pixel_y_end,
address,
print_enable,
Clck,
in_cont_signal,
out_cont_signal,
pixel_load_signal
);
input [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;
input [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;
input Clck, in_cont_signal, pixel_load_signal;
output reg [`MEMORY_SIZE_BITS - 1 : 0] address;
output reg print_enable, out_cont_signal;
localparam
CP_LOAD_VAL = 2'd0,
CP_PAINT_EN = 2'd1,
CP_PAINT_DE = 2'd2,
CP_NEXT_VAL = 2'd3,
COLOR_BLACK = 3'b000,
COLOR_BLUE = 3'b001,
COLOR_YELLOW= 3'b110,
BOARD_PAINTING = 2'd0,
CHESS_PAINTING = 2'd1,
POINTER_PAINTING = 2'd2,
UPPER_PAINTING = 2'd3,
FINDING = 1'd0,
PAINTING = 1'd1;
reg [1:0] CHESS_PAINTING_STAGE;
reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x, pixel_x_reco_start, pixel_x_reco_end;
reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y, pixel_y_reco_start, pixel_y_reco_end;
initial
begin
address = 0;
out_cont_signal = 0;
print_enable = 0;
CHESS_PAINTING_STAGE = CP_LOAD_VAL;
pixel_x_reco_start = 0;
pixel_x_reco_end = 0;
pixel_y_reco_start = 0;
pixel_y_reco_end = 0;
end
always@(pixel_load_signal)
begin
end
always@(posedge Clck)
begin
if(pixel_load_signal == 1)
begin
pixel_x = pixel_x_start;
pixel_y = pixel_y_start;
end
if(in_cont_signal == 1 &&
out_cont_signal == 0)
begin
case(CHESS_PAINTING_STAGE)
CP_LOAD_VAL :
begin
address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);
print_enable = 1;
CHESS_PAINTING_STAGE = CP_PAINT_EN;
end
CP_PAINT_EN :
begin
print_enable = 1;
CHESS_PAINTING_STAGE = CP_PAINT_DE;
end
CP_PAINT_DE :
begin
print_enable = 0;
CHESS_PAINTING_STAGE = CP_NEXT_VAL;
end
CP_NEXT_VAL :
begin
if(pixel_x == pixel_x_end - 1 &&
pixel_y == pixel_y_end - 1)
begin
out_cont_signal = 1;
end
else
if(pixel_x == pixel_x_end - 1)
begin
pixel_y = pixel_y + 1'd1;
pixel_x = pixel_x_start;
end
else
pixel_x = pixel_x + 1'd1;
CHESS_PAINTING_STAGE = CP_LOAD_VAL;
end
endcase
end
else
if(in_cont_signal == 0)
out_cont_signal = 0;
end
endmodule | module paint_chess(
pixel_x_start,
pixel_y_start,
pixel_x_end,
pixel_y_end,
address,
print_enable,
Clck,
in_cont_signal,
out_cont_signal,
pixel_load_signal
); |
input [`SCR_WIDTH_BITS - 1 : 0] pixel_x_start, pixel_x_end;
input [`SCR_HEIGHT_BITS - 1 : 0] pixel_y_start, pixel_y_end;
input Clck, in_cont_signal, pixel_load_signal;
output reg [`MEMORY_SIZE_BITS - 1 : 0] address;
output reg print_enable, out_cont_signal;
localparam
CP_LOAD_VAL = 2'd0,
CP_PAINT_EN = 2'd1,
CP_PAINT_DE = 2'd2,
CP_NEXT_VAL = 2'd3,
COLOR_BLACK = 3'b000,
COLOR_BLUE = 3'b001,
COLOR_YELLOW= 3'b110,
BOARD_PAINTING = 2'd0,
CHESS_PAINTING = 2'd1,
POINTER_PAINTING = 2'd2,
UPPER_PAINTING = 2'd3,
FINDING = 1'd0,
PAINTING = 1'd1;
reg [1:0] CHESS_PAINTING_STAGE;
reg [`SCR_WIDTH_BITS - 1 : 0] pixel_x, pixel_x_reco_start, pixel_x_reco_end;
reg [`SCR_HEIGHT_BITS - 1 : 0] pixel_y, pixel_y_reco_start, pixel_y_reco_end;
initial
begin
address = 0;
out_cont_signal = 0;
print_enable = 0;
CHESS_PAINTING_STAGE = CP_LOAD_VAL;
pixel_x_reco_start = 0;
pixel_x_reco_end = 0;
pixel_y_reco_start = 0;
pixel_y_reco_end = 0;
end
always@(pixel_load_signal)
begin
end
always@(posedge Clck)
begin
if(pixel_load_signal == 1)
begin
pixel_x = pixel_x_start;
pixel_y = pixel_y_start;
end
if(in_cont_signal == 1 &&
out_cont_signal == 0)
begin
case(CHESS_PAINTING_STAGE)
CP_LOAD_VAL :
begin
address = `MAP_PIXELCO_MEMADDR(pixel_x, pixel_y);
print_enable = 1;
CHESS_PAINTING_STAGE = CP_PAINT_EN;
end
CP_PAINT_EN :
begin
print_enable = 1;
CHESS_PAINTING_STAGE = CP_PAINT_DE;
end
CP_PAINT_DE :
begin
print_enable = 0;
CHESS_PAINTING_STAGE = CP_NEXT_VAL;
end
CP_NEXT_VAL :
begin
if(pixel_x == pixel_x_end - 1 &&
pixel_y == pixel_y_end - 1)
begin
out_cont_signal = 1;
end
else
if(pixel_x == pixel_x_end - 1)
begin
pixel_y = pixel_y + 1'd1;
pixel_x = pixel_x_start;
end
else
pixel_x = pixel_x + 1'd1;
CHESS_PAINTING_STAGE = CP_LOAD_VAL;
end
endcase
end
else
if(in_cont_signal == 0)
out_cont_signal = 0;
end
endmodule | 0 |
142,274 | data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v | 98,490,156 | part2.v | v | 275 | 92 | [] | [] | [] | null | line:73: before: "." | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:57: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.v\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:96: Input port connection \'SW\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SW\' generates 18 bits.\n : ... In instance lab6b\n .SW(SW),\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 313,514 | module | module lab6b
(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
);
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire resetn;
assign resetn = SW[17];
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
wire [`STATE_SIZE : 0] present_state;
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire [`CMD_SIZE:0] cmd;
FSM control(
.clk(CLOCK_50),
.START_LOAD(SW[16]),
.GO(SW[15]),
.RESET_N(resetn),
.present_state(present_state));
Datapath datapath(
.clkk(CLOCK_50),
.present_state(present_state),
.SW(SW),
.KEY(KEY),
.XX(x),
.YY(y),
.PLOT(writeEn),
.COLR(colour));
endmodule | module lab6b
(
CLOCK_50,
KEY,
SW,
VGA_CLK,
VGA_HS,
VGA_VS,
VGA_BLANK_N,
VGA_SYNC_N,
VGA_R,
VGA_G,
VGA_B
); |
input CLOCK_50;
input [17:0] SW;
input [3:0] KEY;
output VGA_CLK;
output VGA_HS;
output VGA_VS;
output VGA_BLANK_N;
output VGA_SYNC_N;
output [9:0] VGA_R;
output [9:0] VGA_G;
output [9:0] VGA_B;
wire resetn;
assign resetn = SW[17];
wire [2:0] colour;
wire [7:0] x;
wire [6:0] y;
wire writeEn;
wire [`STATE_SIZE : 0] present_state;
vga_adapter VGA(
.resetn(resetn),
.clock(CLOCK_50),
.colour(colour),
.x(x),
.y(y),
.plot(writeEn),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
wire [`CMD_SIZE:0] cmd;
FSM control(
.clk(CLOCK_50),
.START_LOAD(SW[16]),
.GO(SW[15]),
.RESET_N(resetn),
.present_state(present_state));
Datapath datapath(
.clkk(CLOCK_50),
.present_state(present_state),
.SW(SW),
.KEY(KEY),
.XX(x),
.YY(y),
.PLOT(writeEn),
.COLR(colour));
endmodule | 0 |
142,275 | data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v | 98,490,156 | part2.v | v | 275 | 92 | [] | [] | [] | null | line:73: before: "." | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:57: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.v\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:96: Input port connection \'SW\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SW\' generates 18 bits.\n : ... In instance lab6b\n .SW(SW),\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 313,514 | module | module FSM(
clk,
START_LOAD,
GO,
RESET_N,
present_state
);
input START_LOAD,GO;
input RESET_N;
output reg[`STATE_SIZE : 0] present_state;
reg[`STATE_SIZE : 0] next_state;
input clk;
localparam INPUT_X = 5'd0,
INPUT_Y = 5'd1,
INPUT_COLR = 5'd2,
DR17 = 5'd31,
DR1 = 5'd3,
DR2 = 5'd4,
DR3 = 5'd5,
DR4 = 5'd6,
DR5 = 5'd7,
DR6 = 5'd8,
DR7 = 5'd9,
DR8 = 5'd10,
DR9 = 5'd11,
DR10 = 5'd12,
DR11 = 5'd13,
DR12 = 5'd14,
DR13 = 5'd15,
DR14 = 5'd16,
DR15 = 5'd17,
DR16 = 5'd18,
WAIT_X = 5'd19,
WAIT_Y = 5'd20,
WAIT_COLR = 5'd21;
always@(*) begin
case(present_state)
WAIT_X : next_state = (START_LOAD == 1 ? INPUT_X : WAIT_X);
INPUT_X : next_state = (START_LOAD == 1 ? INPUT_X : WAIT_Y);
WAIT_Y : next_state = (START_LOAD == 1 ? INPUT_Y : WAIT_Y);
INPUT_Y : next_state = (START_LOAD == 1 ? INPUT_Y : WAIT_COLR);
WAIT_COLR : next_state = (GO == 1 ? INPUT_COLR : WAIT_COLR);
INPUT_COLR : next_state = (GO == 0 ? DR1 : INPUT_COLR);
DR1 : next_state = DR2;
DR2 : next_state = DR3;
DR3 : next_state = DR4;
DR4 : next_state = DR5;
DR5 : next_state = DR6;
DR6 : next_state = DR7;
DR7 : next_state = DR8;
DR8 : next_state = DR9;
DR9 : next_state = DR10;
DR10 : next_state = DR11;
DR11 : next_state = DR12;
DR12 : next_state = DR13;
DR13 : next_state = DR14;
DR14 : next_state = DR15;
DR15 : next_state = DR16;
DR16 : next_state = DR17;
DR17 : next_state = WAIT_X;
default : next_state = WAIT_X;
endcase
end
always@(posedge clk) begin
if(RESET_N == 0)
present_state <= WAIT_X;
else
present_state <= next_state;
end
endmodule | module FSM(
clk,
START_LOAD,
GO,
RESET_N,
present_state
); |
input START_LOAD,GO;
input RESET_N;
output reg[`STATE_SIZE : 0] present_state;
reg[`STATE_SIZE : 0] next_state;
input clk;
localparam INPUT_X = 5'd0,
INPUT_Y = 5'd1,
INPUT_COLR = 5'd2,
DR17 = 5'd31,
DR1 = 5'd3,
DR2 = 5'd4,
DR3 = 5'd5,
DR4 = 5'd6,
DR5 = 5'd7,
DR6 = 5'd8,
DR7 = 5'd9,
DR8 = 5'd10,
DR9 = 5'd11,
DR10 = 5'd12,
DR11 = 5'd13,
DR12 = 5'd14,
DR13 = 5'd15,
DR14 = 5'd16,
DR15 = 5'd17,
DR16 = 5'd18,
WAIT_X = 5'd19,
WAIT_Y = 5'd20,
WAIT_COLR = 5'd21;
always@(*) begin
case(present_state)
WAIT_X : next_state = (START_LOAD == 1 ? INPUT_X : WAIT_X);
INPUT_X : next_state = (START_LOAD == 1 ? INPUT_X : WAIT_Y);
WAIT_Y : next_state = (START_LOAD == 1 ? INPUT_Y : WAIT_Y);
INPUT_Y : next_state = (START_LOAD == 1 ? INPUT_Y : WAIT_COLR);
WAIT_COLR : next_state = (GO == 1 ? INPUT_COLR : WAIT_COLR);
INPUT_COLR : next_state = (GO == 0 ? DR1 : INPUT_COLR);
DR1 : next_state = DR2;
DR2 : next_state = DR3;
DR3 : next_state = DR4;
DR4 : next_state = DR5;
DR5 : next_state = DR6;
DR6 : next_state = DR7;
DR7 : next_state = DR8;
DR8 : next_state = DR9;
DR9 : next_state = DR10;
DR10 : next_state = DR11;
DR11 : next_state = DR12;
DR12 : next_state = DR13;
DR13 : next_state = DR14;
DR14 : next_state = DR15;
DR15 : next_state = DR16;
DR16 : next_state = DR17;
DR17 : next_state = WAIT_X;
default : next_state = WAIT_X;
endcase
end
always@(posedge clk) begin
if(RESET_N == 0)
present_state <= WAIT_X;
else
present_state <= next_state;
end
endmodule | 0 |
142,276 | data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v | 98,490,156 | part2.v | v | 275 | 92 | [] | [] | [] | null | line:73: before: "." | null | 1: b'%Error: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:57: Cannot find file containing module: \'vga_adapter\'\n vga_adapter VGA(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.v\n data/full_repos/permissive/98490156/lowlevelabs/VGA,data/full_repos/permissive/98490156/vga_adapter.sv\n vga_adapter\n vga_adapter.v\n vga_adapter.sv\n obj_dir/vga_adapter\n obj_dir/vga_adapter.v\n obj_dir/vga_adapter.sv\n%Warning-WIDTH: data/full_repos/permissive/98490156/lowlevelabs/VGA/part2.v:96: Input port connection \'SW\' expects 10 bits on the pin connection, but pin connection\'s VARREF \'SW\' generates 18 bits.\n : ... In instance lab6b\n .SW(SW),\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n' | 313,514 | module | module Datapath(
clkk,
present_state,
SW,
KEY,
XX,
YY,
PLOT,
COLR
);
input [9:0] SW;
input [3:0] KEY;
input [`STATE_SIZE : 0] present_state;
input clkk;
output reg [`COX_SIZE - 1: 0] XX;
output reg [`COY_SIZE - 1: 0] YY;
output reg [`RGB_SIZE - 1:0] COLR;
output reg PLOT;
localparam INPUT_X = 5'd0,
INPUT_Y = 5'd1,
INPUT_COLR = 5'd2,
DR17 = 5'd31,
DR1 = 5'd3,
DR2 = 5'd4,
DR3 = 5'd5,
DR4 = 5'd6,
DR5 = 5'd7,
DR6 = 5'd8,
DR7 = 5'd9,
DR8 = 5'd10,
DR9 = 5'd11,
DR10 = 5'd12,
DR11 = 5'd13,
DR12 = 5'd14,
DR13 = 5'd15,
DR14 = 5'd16,
DR15 = 5'd17,
DR16 = 5'd18,
WAIT_X = 5'd19,
WAIT_Y = 5'd20,
WAIT_COLR = 5'd21;
always@(posedge clkk) begin
case(present_state)
WAIT_X : XX <= XX;
INPUT_X : XX <= {1'b0,SW[6:0]};
WAIT_Y : XX <= XX;
INPUT_Y : YY <= SW[6:0];
WAIT_COLR : YY <= YY;
INPUT_COLR : COLR = SW[9:7];
DR1 : PLOT = 1;
DR2 : XX = XX + 1;
DR3 : XX = XX + 1;
DR4 : XX = XX + 1;
DR5 : begin XX = XX - 3; YY = YY + 1; end
DR6 : XX = XX + 1;
DR7 : XX = XX + 1;
DR8 : XX = XX + 1;
DR9 : begin XX = XX - 3; YY = YY + 1; end
DR10 : XX = XX + 1;
DR11 : XX = XX + 1;
DR12 : XX = XX + 1;
DR13 : begin XX = XX - 3; YY = YY + 1; end
DR14 : XX = XX + 1;
DR15 : XX = XX + 1;
DR16 : XX = XX + 1;
DR17 : PLOT = 0;
default : ;
endcase
end
endmodule | module Datapath(
clkk,
present_state,
SW,
KEY,
XX,
YY,
PLOT,
COLR
); |
input [9:0] SW;
input [3:0] KEY;
input [`STATE_SIZE : 0] present_state;
input clkk;
output reg [`COX_SIZE - 1: 0] XX;
output reg [`COY_SIZE - 1: 0] YY;
output reg [`RGB_SIZE - 1:0] COLR;
output reg PLOT;
localparam INPUT_X = 5'd0,
INPUT_Y = 5'd1,
INPUT_COLR = 5'd2,
DR17 = 5'd31,
DR1 = 5'd3,
DR2 = 5'd4,
DR3 = 5'd5,
DR4 = 5'd6,
DR5 = 5'd7,
DR6 = 5'd8,
DR7 = 5'd9,
DR8 = 5'd10,
DR9 = 5'd11,
DR10 = 5'd12,
DR11 = 5'd13,
DR12 = 5'd14,
DR13 = 5'd15,
DR14 = 5'd16,
DR15 = 5'd17,
DR16 = 5'd18,
WAIT_X = 5'd19,
WAIT_Y = 5'd20,
WAIT_COLR = 5'd21;
always@(posedge clkk) begin
case(present_state)
WAIT_X : XX <= XX;
INPUT_X : XX <= {1'b0,SW[6:0]};
WAIT_Y : XX <= XX;
INPUT_Y : YY <= SW[6:0];
WAIT_COLR : YY <= YY;
INPUT_COLR : COLR = SW[9:7];
DR1 : PLOT = 1;
DR2 : XX = XX + 1;
DR3 : XX = XX + 1;
DR4 : XX = XX + 1;
DR5 : begin XX = XX - 3; YY = YY + 1; end
DR6 : XX = XX + 1;
DR7 : XX = XX + 1;
DR8 : XX = XX + 1;
DR9 : begin XX = XX - 3; YY = YY + 1; end
DR10 : XX = XX + 1;
DR11 : XX = XX + 1;
DR12 : XX = XX + 1;
DR13 : begin XX = XX - 3; YY = YY + 1; end
DR14 : XX = XX + 1;
DR15 : XX = XX + 1;
DR16 : XX = XX + 1;
DR17 : PLOT = 0;
default : ;
endcase
end
endmodule | 0 |
142,277 | data/full_repos/permissive/98490156/memory/Memory_Write.v | 98,490,156 | Memory_Write.v | v | 67 | 163 | [] | [] | [] | [(6, 66)] | null | null | 1: b"%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:23: Cannot find file containing module: 'Select1to16'\n Select1to16 transDataToRow(.in(in[1:0]), .select(select[7:4]), .out(row_in[31:0]));\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98490156/memory,data/full_repos/permissive/98490156/Select1to16\n data/full_repos/permissive/98490156/memory,data/full_repos/permissive/98490156/Select1to16.v\n data/full_repos/permissive/98490156/memory,data/full_repos/permissive/98490156/Select1to16.sv\n Select1to16\n Select1to16.v\n Select1to16.sv\n obj_dir/Select1to16\n obj_dir/Select1to16.v\n obj_dir/Select1to16.sv\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:25: Cannot find file containing module: 'Enable_select'\n Enable_select enableEachRow(.enable(1'b1), .select(select[7:4]), .out(enable[15:0]));\n ^~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:31: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin0(.in(row_in[1:0]), .select(select[3:0]), .out(data_out[31:0]), .clock(clock), .reset(reset), .write_enable(enable[0]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:33: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin1(.in(row_in[3:2]), .select(select[3:0]), .out(data_out[63:32]), .clock(clock), .reset(reset), .write_enable(enable[1]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:35: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin2(.in(row_in[5:4]), .select(select[3:0]), .out(data_out[95:64]), .clock(clock), .reset(reset), .write_enable(enable[2]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:37: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin3(.in(row_in[7:6]), .select(select[3:0]), .out(data_out[127:96]), .clock(clock), .reset(reset), .write_enable(enable[3]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:39: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin4(.in(row_in[9:8]), .select(select[3:0]), .out(data_out[159:128]), .clock(clock), .reset(reset), .write_enable(enable[4]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:41: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin5(.in(row_in[11:10]), .select(select[3:0]), .out(data_out[191:160]), .clock(clock), .reset(reset), .write_enable(enable[5]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:43: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin6(.in(row_in[13:12]), .select(select[3:0]), .out(data_out[223:192]), .clock(clock), .reset(reset), .write_enable(enable[6]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:45: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin7(.in(row_in[15:14]), .select(select[3:0]), .out(data_out[255:224]), .clock(clock), .reset(reset), .write_enable(enable[7]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:47: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin8(.in(row_in[17:16]), .select(select[3:0]), .out(data_out[287:256]), .clock(clock), .reset(reset), .write_enable(enable[8]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:49: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin9(.in(row_in[19:18]), .select(select[3:0]), .out(data_out[319:288]), .clock(clock), .reset(reset), .write_enable(enable[9]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:51: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin10(.in(row_in[21:20]), .select(select[3:0]), .out(data_out[351:320]), .clock(clock), .reset(reset), .write_enable(enable[10]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:53: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin11(.in(row_in[23:22]), .select(select[3:0]), .out(data_out[383:352]), .clock(clock), .reset(reset), .write_enable(enable[11]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:55: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin12(.in(row_in[25:24]), .select(select[3:0]), .out(data_out[415:384]), .clock(clock), .reset(reset), .write_enable(enable[12]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:57: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin13(.in(row_in[27:26]), .select(select[3:0]), .out(data_out[447:416]), .clock(clock), .reset(reset), .write_enable(enable[13]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:59: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin14(.in(row_in[29:28]), .select(select[3:0]), .out(data_out[479:448]), .clock(clock), .reset(reset), .write_enable(enable[14]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98490156/memory/Memory_Write.v:61: Cannot find file containing module: 'Y_Coordinate_Select_Write'\n Y_Coordinate_Select_Write rowin15(.in(row_in[31:30]), .select(select[3:0]), .out(data_out[511:480]), .clock(clock), .reset(reset), .write_enable(enable[15]));\n ^~~~~~~~~~~~~~~~~~~~~~~~~\n%Error: Exiting due to 18 error(s)\n" | 313,522 | module | module Memory_Write(in, select, out, clock, reset);
input [1:0] in;
input [7:0] select;
input clock, reset;
output [511:0] out;
wire [511:0] data_out;
wire [31:0] row_in;
wire [15:0] enable;
Select1to16 transDataToRow(.in(in[1:0]), .select(select[7:4]), .out(row_in[31:0]));
Enable_select enableEachRow(.enable(1'b1), .select(select[7:4]), .out(enable[15:0]));
Y_Coordinate_Select_Write rowin0(.in(row_in[1:0]), .select(select[3:0]), .out(data_out[31:0]), .clock(clock), .reset(reset), .write_enable(enable[0]));
Y_Coordinate_Select_Write rowin1(.in(row_in[3:2]), .select(select[3:0]), .out(data_out[63:32]), .clock(clock), .reset(reset), .write_enable(enable[1]));
Y_Coordinate_Select_Write rowin2(.in(row_in[5:4]), .select(select[3:0]), .out(data_out[95:64]), .clock(clock), .reset(reset), .write_enable(enable[2]));
Y_Coordinate_Select_Write rowin3(.in(row_in[7:6]), .select(select[3:0]), .out(data_out[127:96]), .clock(clock), .reset(reset), .write_enable(enable[3]));
Y_Coordinate_Select_Write rowin4(.in(row_in[9:8]), .select(select[3:0]), .out(data_out[159:128]), .clock(clock), .reset(reset), .write_enable(enable[4]));
Y_Coordinate_Select_Write rowin5(.in(row_in[11:10]), .select(select[3:0]), .out(data_out[191:160]), .clock(clock), .reset(reset), .write_enable(enable[5]));
Y_Coordinate_Select_Write rowin6(.in(row_in[13:12]), .select(select[3:0]), .out(data_out[223:192]), .clock(clock), .reset(reset), .write_enable(enable[6]));
Y_Coordinate_Select_Write rowin7(.in(row_in[15:14]), .select(select[3:0]), .out(data_out[255:224]), .clock(clock), .reset(reset), .write_enable(enable[7]));
Y_Coordinate_Select_Write rowin8(.in(row_in[17:16]), .select(select[3:0]), .out(data_out[287:256]), .clock(clock), .reset(reset), .write_enable(enable[8]));
Y_Coordinate_Select_Write rowin9(.in(row_in[19:18]), .select(select[3:0]), .out(data_out[319:288]), .clock(clock), .reset(reset), .write_enable(enable[9]));
Y_Coordinate_Select_Write rowin10(.in(row_in[21:20]), .select(select[3:0]), .out(data_out[351:320]), .clock(clock), .reset(reset), .write_enable(enable[10]));
Y_Coordinate_Select_Write rowin11(.in(row_in[23:22]), .select(select[3:0]), .out(data_out[383:352]), .clock(clock), .reset(reset), .write_enable(enable[11]));
Y_Coordinate_Select_Write rowin12(.in(row_in[25:24]), .select(select[3:0]), .out(data_out[415:384]), .clock(clock), .reset(reset), .write_enable(enable[12]));
Y_Coordinate_Select_Write rowin13(.in(row_in[27:26]), .select(select[3:0]), .out(data_out[447:416]), .clock(clock), .reset(reset), .write_enable(enable[13]));
Y_Coordinate_Select_Write rowin14(.in(row_in[29:28]), .select(select[3:0]), .out(data_out[479:448]), .clock(clock), .reset(reset), .write_enable(enable[14]));
Y_Coordinate_Select_Write rowin15(.in(row_in[31:30]), .select(select[3:0]), .out(data_out[511:480]), .clock(clock), .reset(reset), .write_enable(enable[15]));
assign out[511:0] = data_out[511:0];
endmodule | module Memory_Write(in, select, out, clock, reset); |
input [1:0] in;
input [7:0] select;
input clock, reset;
output [511:0] out;
wire [511:0] data_out;
wire [31:0] row_in;
wire [15:0] enable;
Select1to16 transDataToRow(.in(in[1:0]), .select(select[7:4]), .out(row_in[31:0]));
Enable_select enableEachRow(.enable(1'b1), .select(select[7:4]), .out(enable[15:0]));
Y_Coordinate_Select_Write rowin0(.in(row_in[1:0]), .select(select[3:0]), .out(data_out[31:0]), .clock(clock), .reset(reset), .write_enable(enable[0]));
Y_Coordinate_Select_Write rowin1(.in(row_in[3:2]), .select(select[3:0]), .out(data_out[63:32]), .clock(clock), .reset(reset), .write_enable(enable[1]));
Y_Coordinate_Select_Write rowin2(.in(row_in[5:4]), .select(select[3:0]), .out(data_out[95:64]), .clock(clock), .reset(reset), .write_enable(enable[2]));
Y_Coordinate_Select_Write rowin3(.in(row_in[7:6]), .select(select[3:0]), .out(data_out[127:96]), .clock(clock), .reset(reset), .write_enable(enable[3]));
Y_Coordinate_Select_Write rowin4(.in(row_in[9:8]), .select(select[3:0]), .out(data_out[159:128]), .clock(clock), .reset(reset), .write_enable(enable[4]));
Y_Coordinate_Select_Write rowin5(.in(row_in[11:10]), .select(select[3:0]), .out(data_out[191:160]), .clock(clock), .reset(reset), .write_enable(enable[5]));
Y_Coordinate_Select_Write rowin6(.in(row_in[13:12]), .select(select[3:0]), .out(data_out[223:192]), .clock(clock), .reset(reset), .write_enable(enable[6]));
Y_Coordinate_Select_Write rowin7(.in(row_in[15:14]), .select(select[3:0]), .out(data_out[255:224]), .clock(clock), .reset(reset), .write_enable(enable[7]));
Y_Coordinate_Select_Write rowin8(.in(row_in[17:16]), .select(select[3:0]), .out(data_out[287:256]), .clock(clock), .reset(reset), .write_enable(enable[8]));
Y_Coordinate_Select_Write rowin9(.in(row_in[19:18]), .select(select[3:0]), .out(data_out[319:288]), .clock(clock), .reset(reset), .write_enable(enable[9]));
Y_Coordinate_Select_Write rowin10(.in(row_in[21:20]), .select(select[3:0]), .out(data_out[351:320]), .clock(clock), .reset(reset), .write_enable(enable[10]));
Y_Coordinate_Select_Write rowin11(.in(row_in[23:22]), .select(select[3:0]), .out(data_out[383:352]), .clock(clock), .reset(reset), .write_enable(enable[11]));
Y_Coordinate_Select_Write rowin12(.in(row_in[25:24]), .select(select[3:0]), .out(data_out[415:384]), .clock(clock), .reset(reset), .write_enable(enable[12]));
Y_Coordinate_Select_Write rowin13(.in(row_in[27:26]), .select(select[3:0]), .out(data_out[447:416]), .clock(clock), .reset(reset), .write_enable(enable[13]));
Y_Coordinate_Select_Write rowin14(.in(row_in[29:28]), .select(select[3:0]), .out(data_out[479:448]), .clock(clock), .reset(reset), .write_enable(enable[14]));
Y_Coordinate_Select_Write rowin15(.in(row_in[31:30]), .select(select[3:0]), .out(data_out[511:480]), .clock(clock), .reset(reset), .write_enable(enable[15]));
assign out[511:0] = data_out[511:0];
endmodule | 0 |
142,278 | data/full_repos/permissive/98495486/rtl model/freqcount.v | 98,495,486 | freqcount.v | v | 103 | 86 | [] | [] | [] | [(26, 102)] | null | null | 1: b'%Error: Cannot find file containing module: model,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.sv\n model,data/full_repos/permissive/98495486\n model,data/full_repos/permissive/98495486.v\n model,data/full_repos/permissive/98495486.sv\n obj_dir/model,data/full_repos/permissive/98495486\n obj_dir/model,data/full_repos/permissive/98495486.v\n obj_dir/model,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/freqcount.v\n%Error: Exiting due to 3 error(s)\n' | 313,528 | module | module freqcount(
input clk,
input rst_n,
input start,
input start_done,
input [3:0] data_in,
input ack_coding,
output reg req_coding,
output wire [18:0] data_out0,
output wire [18:0] data_out1,
output wire [18:0] data_out2,
output wire [18:0] data_out3,
output wire [18:0] data_out4,
output wire [18:0] data_out5,
output wire [18:0] data_out6,
output wire [18:0] data_out7,
output wire [18:0] data_out8,
output wire [18:0] data_out9
);
reg processing;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
processing <= 1'b0;
else if (start)
processing <= 1'b1;
else if (start_done)
processing <= 1'b0;
end
reg [7:0] data_mem [0:9];
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (i = 0; i < 10; i = i + 1) begin
data_mem[i] <= 8'b0;
end
end else if (processing) begin
case(data_in)
4'b0000: data_mem[0] <= data_mem[0] + 1;
4'b0001: data_mem[1] <= data_mem[1] + 1;
4'b0010: data_mem[2] <= data_mem[2] + 1;
4'b0011: data_mem[3] <= data_mem[3] + 1;
4'b0100: data_mem[4] <= data_mem[4] + 1;
4'b0101: data_mem[5] <= data_mem[5] + 1;
4'b0110: data_mem[6] <= data_mem[6] + 1;
4'b0111: data_mem[7] <= data_mem[7] + 1;
4'b1000: data_mem[8] <= data_mem[8] + 1;
4'b1001: data_mem[9] <= data_mem[9] + 1;
default: ;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
req_coding <= 1'b0;
else if (start_done)
req_coding <= 1'b1;
else if (ack_coding)
req_coding <= 1'b0;
end
assign data_out0 = {6'b0, 5'd0, data_mem[0]};
assign data_out1 = {6'b0, 5'd1, data_mem[1]};
assign data_out2 = {6'b0, 5'd2, data_mem[2]};
assign data_out3 = {6'b0, 5'd3, data_mem[3]};
assign data_out4 = {6'b0, 5'd4, data_mem[4]};
assign data_out5 = {6'b0, 5'd5, data_mem[5]};
assign data_out6 = {6'b0, 5'd6, data_mem[6]};
assign data_out7 = {6'b0, 5'd7, data_mem[7]};
assign data_out8 = {6'b0, 5'd8, data_mem[8]};
assign data_out9 = {6'b0, 5'd9, data_mem[9]};
endmodule | module freqcount(
input clk,
input rst_n,
input start,
input start_done,
input [3:0] data_in,
input ack_coding,
output reg req_coding,
output wire [18:0] data_out0,
output wire [18:0] data_out1,
output wire [18:0] data_out2,
output wire [18:0] data_out3,
output wire [18:0] data_out4,
output wire [18:0] data_out5,
output wire [18:0] data_out6,
output wire [18:0] data_out7,
output wire [18:0] data_out8,
output wire [18:0] data_out9
); |
reg processing;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
processing <= 1'b0;
else if (start)
processing <= 1'b1;
else if (start_done)
processing <= 1'b0;
end
reg [7:0] data_mem [0:9];
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (i = 0; i < 10; i = i + 1) begin
data_mem[i] <= 8'b0;
end
end else if (processing) begin
case(data_in)
4'b0000: data_mem[0] <= data_mem[0] + 1;
4'b0001: data_mem[1] <= data_mem[1] + 1;
4'b0010: data_mem[2] <= data_mem[2] + 1;
4'b0011: data_mem[3] <= data_mem[3] + 1;
4'b0100: data_mem[4] <= data_mem[4] + 1;
4'b0101: data_mem[5] <= data_mem[5] + 1;
4'b0110: data_mem[6] <= data_mem[6] + 1;
4'b0111: data_mem[7] <= data_mem[7] + 1;
4'b1000: data_mem[8] <= data_mem[8] + 1;
4'b1001: data_mem[9] <= data_mem[9] + 1;
default: ;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
req_coding <= 1'b0;
else if (start_done)
req_coding <= 1'b1;
else if (ack_coding)
req_coding <= 1'b0;
end
assign data_out0 = {6'b0, 5'd0, data_mem[0]};
assign data_out1 = {6'b0, 5'd1, data_mem[1]};
assign data_out2 = {6'b0, 5'd2, data_mem[2]};
assign data_out3 = {6'b0, 5'd3, data_mem[3]};
assign data_out4 = {6'b0, 5'd4, data_mem[4]};
assign data_out5 = {6'b0, 5'd5, data_mem[5]};
assign data_out6 = {6'b0, 5'd6, data_mem[6]};
assign data_out7 = {6'b0, 5'd7, data_mem[7]};
assign data_out8 = {6'b0, 5'd8, data_mem[8]};
assign data_out9 = {6'b0, 5'd9, data_mem[9]};
endmodule | 6 |
142,279 | data/full_repos/permissive/98495486/rtl model/HuffmanCode.v | 98,495,486 | HuffmanCode.v | v | 594 | 87 | [] | [] | [] | [(13, 593)] | null | null | 1: b'%Error: Cannot find file containing module: model,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.sv\n model,data/full_repos/permissive/98495486\n model,data/full_repos/permissive/98495486.v\n model,data/full_repos/permissive/98495486.sv\n obj_dir/model,data/full_repos/permissive/98495486\n obj_dir/model,data/full_repos/permissive/98495486.v\n obj_dir/model,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/HuffmanCode.v\n%Error: Exiting due to 3 error(s)\n' | 313,529 | module | module HuffmanCode (
input clk,
input rst_n,
input [18:0] data_in0,
input [18:0] data_in1,
input [18:0] data_in2,
input [18:0] data_in3,
input [18:0] data_in4,
input [18:0] data_in5,
input [18:0] data_in6,
input [18:0] data_in7,
input [18:0] data_in8,
input [18:0] data_in9,
input req_coding,
output reg ack_coding,
output reg [8:0] data_out,
output reg [3:0] data_len,
output wire trans_start
);
localparam IDLE = 2'd0;
localparam CODING = 2'd1;
localparam TRAVERSE = 2'd2;
localparam OUTPUT = 2'd3;
reg [1:0] state;
reg [1:0] next_state;
reg [3:0] phase;
reg [3:0] next_phase;
reg [3:0] loop;
reg [3:0] next_loop;
reg [18:0] mem [0:18];
reg [18:0] a0;
reg [18:0] a1;
reg [18:0] a2;
reg [18:0] a3;
reg [18:0] a4;
reg [18:0] a5;
reg [18:0] a6;
reg [18:0] a7;
reg [18:0] a8;
reg [18:0] a9;
reg [18:0] a10;
reg [18:0] a11;
reg [18:0] a12;
reg [18:0] a13;
reg [18:0] a14;
reg [18:0] a15;
wire [18:0] sort0;
wire [18:0] sort1;
wire [18:0] sort2;
wire [18:0] sort3;
wire [18:0] sort4;
wire [18:0] sort5;
wire [18:0] sort6;
wire [18:0] sort7;
wire [18:0] sort8;
wire [18:0] sort9;
wire [18:0] sort10;
wire [18:0] sort11;
wire [18:0] sort12;
wire [18:0] sort13;
wire [18:0] sort14;
wire [18:0] sort15;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
ack_coding <= 1'b0;
else if (req_coding)
ack_coding <= 1'b1;
else
ack_coding <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= IDLE;
phase <= 4'b0;
loop <= 4'd0;
end else begin
state <= next_state;
phase <= next_phase;
loop <= next_loop;
end
end
always @(*) begin
case (state)
IDLE: begin
if (req_coding)
next_state = CODING;
else
next_state = IDLE;
next_phase = 4'b0;
next_loop = 4'd0;
end
CODING: begin
if (phase == 4'd9) begin
next_state = TRAVERSE;
next_phase = 4'd0;
end else begin
next_state = CODING;
next_phase = phase + 1;
end
next_loop = 4'd0;
end
TRAVERSE: begin
if (phase == 4'd8) begin
next_state = OUTPUT;
next_phase = 4'd0;
next_loop = code_length[0];
end else begin
next_state = TRAVERSE;
next_phase = phase + 1;
next_loop = 4'd0;
end
end
OUTPUT: begin
if (loop == 4'd1) begin
if (phase == 4'd9) begin
next_state = IDLE;
next_phase = 4'd0;
next_loop = 4'd0;
end else begin
next_state = OUTPUT;
next_phase = phase + 1;
next_loop = code_length[phase+1];
end
end
else begin
next_state = OUTPUT;
next_phase = phase;
next_loop = loop - 1;
end
end
default: begin
next_state = state;
next_phase = phase;
next_loop = loop;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
a0 <= 19'b0;
a1 <= 19'b0;
a2 <= 19'b0;
a3 <= 19'b0;
a4 <= 19'b0;
a5 <= 19'b0;
a6 <= 19'b0;
a7 <= 19'b0;
a8 <= 19'b0;
a9 <= 19'b0;
a10 <= 19'b0;
a11 <= 19'b0;
a12 <= 19'b0;
a13 <= 19'b0;
a14 <= 19'b0;
a15 <= 19'b0;
end
else if (state==CODING) begin
case(phase)
4'd0: begin
a0 <= data_in0;
a1 <= data_in1;
a2 <= data_in2;
a3 <= data_in3;
a4 <= data_in4;
a5 <= data_in5;
a6 <= data_in6;
a7 <= data_in7;
a8 <= data_in8;
a9 <= data_in9;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd1: begin
a0 <= {6'b0, 5'd10, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= sort8;
a8 <= sort9;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd2: begin
a0 <= {6'b0, 5'd11, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= sort8;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd3: begin
a0 <= {6'b0, 5'd12, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd4: begin
a0 <= {6'b0, 5'd13, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd5: begin
a0 <= {6'b0, 5'd14, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd6: begin
a0 <= {6'b0, 5'd15, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd7: begin
a0 <= {6'b0, 5'd16, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= 19'd255;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd8: begin
a0 <= {6'b0, 5'd17, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= 19'd255;
a3 <= 19'd255;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd9: begin
a0 <= 19'b0;
a1 <= 19'b0;
a2 <= 19'b0;
a3 <= 19'b0;
a4 <= 19'b0;
a5 <= 19'b0;
a6 <= 19'b0;
a7 <= 19'b0;
a8 <= 19'b0;
a9 <= 19'b0;
a10 <= 19'b0;
a11 <= 19'b0;
a12 <= 19'b0;
a13 <= 19'b0;
a14 <= 19'b0;
a15 <= 19'b0;
end
default: begin
a0 <= 20'b0;
a1 <= 20'b0;
a2 <= 20'b0;
a3 <= 20'b0;
a4 <= 20'b0;
a5 <= 20'b0;
a6 <= 20'b0;
a7 <= 20'b0;
a8 <= 20'b0;
a9 <= 20'b0;
a10 <= 20'b0;
a11 <= 20'b0;
a12 <= 20'b0;
a13 <= 20'b0;
a14 <= 20'b0;
a15 <= 20'b0;
end
endcase
end
else begin
a0 <= 20'b0;
a1 <= 20'b0;
a2 <= 20'b0;
a3 <= 20'b0;
a4 <= 20'b0;
a5 <= 20'b0;
a6 <= 20'b0;
a7 <= 20'b0;
a8 <= 20'b0;
a9 <= 20'b0;
a10 <= 20'b0;
a11 <= 20'b0;
a12 <= 20'b0;
a13 <= 20'b0;
a14 <= 20'b0;
a15 <= 20'b0;
end
end
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (i = 0; i < 19; i = i + 1) begin
mem[i] <= 19'b0;
end
end
else if (state == CODING) begin
case (phase)
4'd0: ;
4'd1: begin
mem[sort0[12:8]] <= {5'd10, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd10, 1'd1, sort1[12:0]};
end
4'd2: begin
mem[sort0[12:8]] <= {5'd11, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd11, 1'd1, sort1[12:0]};
end
4'd3: begin
mem[sort0[12:8]] <= {5'd12, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd12, 1'd1, sort1[12:0]};
end
4'd4: begin
mem[sort0[12:8]] <= {5'd13, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd13, 1'd1, sort1[12:0]};
end
4'd5: begin
mem[sort0[12:8]] <= {5'd14, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd14, 1'd1, sort1[12:0]};
end
4'd6: begin
mem[sort0[12:8]] <= {5'd15, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd15, 1'd1, sort1[12:0]};
end
4'd7: begin
mem[sort0[12:8]] <= {5'd16, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd16, 1'd1, sort1[12:0]};
end
4'd8: begin
mem[sort0[12:8]] <= {5'd17, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd17, 1'd1, sort1[12:0]};
end
4'd9: begin
mem[sort0[12:8]] <= {5'd18, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd18, 1'd1, sort1[12:0]};
mem[18] <= {5'd31, 1'd0, 5'd18, sort0[7:0]+sort1[7:0]};
end
default: ;
endcase
end
end
SortX16 # (
.DSIZE (5'd19),
.OFFSET (4'd8)
) sortx16_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.a8 (a8),
.a9 (a9),
.a10 (a10),
.a11 (a11),
.a12 (a12),
.a13 (a13),
.a14 (a14),
.a15 (a15),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7),
.sort8 (sort8),
.sort9 (sort9),
.sort10 (sort10),
.sort11 (sort11),
.sort12 (sort12),
.sort13 (sort13),
.sort14 (sort14),
.sort15 (sort15)
);
genvar j;
reg [8:0] code_result [0:9];
reg [3:0] code_length [0:9];
reg [4:0] index [0:9];
generate
for (j = 0; j < 10; j = j + 1) begin
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
code_result[j] <= 9'b0;
code_length[j] <= 4'b0;
index[j] <= 5'b0;
end else if (state == TRAVERSE) begin
case (phase)
4'd0: begin
code_result[j][0] <= mem[j][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[j][18:14];
end
4'd1: begin
if (index[j] != 5'd18) begin
code_result[j][1] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd2: begin
if (index[j] != 5'd18) begin
code_result[j][2] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd3: begin
if (index[j] != 5'd18) begin
code_result[j][3] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd4: begin
if (index[j] != 5'd18) begin
code_result[j][4] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd5: begin
if (index[j] != 5'd18) begin
code_result[j][5] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd6: begin
if (index[j] != 5'd18) begin
code_result[j][6] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd7: begin
if (index[j] != 5'd18) begin
code_result[j][7] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd8: begin
if (index[j] != 5'd18) begin
code_result[j][8] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
default: begin
code_result[j] <= 9'b0;
code_length[j] <= 4'b0;
index[j] <= 5'b0;
end
endcase
end
end
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 9'd0;
data_len <= 4'd0;
end
else begin
if (next_state == OUTPUT) begin
data_out <= code_result[next_phase];
data_len <= code_length[next_phase];
end
else begin
data_out <= 9'd0;
data_len <= 4'd0;
end
end
end
assign trans_start = (state == OUTPUT) ? 1'b1 : 1'b0;
endmodule | module HuffmanCode (
input clk,
input rst_n,
input [18:0] data_in0,
input [18:0] data_in1,
input [18:0] data_in2,
input [18:0] data_in3,
input [18:0] data_in4,
input [18:0] data_in5,
input [18:0] data_in6,
input [18:0] data_in7,
input [18:0] data_in8,
input [18:0] data_in9,
input req_coding,
output reg ack_coding,
output reg [8:0] data_out,
output reg [3:0] data_len,
output wire trans_start
); |
localparam IDLE = 2'd0;
localparam CODING = 2'd1;
localparam TRAVERSE = 2'd2;
localparam OUTPUT = 2'd3;
reg [1:0] state;
reg [1:0] next_state;
reg [3:0] phase;
reg [3:0] next_phase;
reg [3:0] loop;
reg [3:0] next_loop;
reg [18:0] mem [0:18];
reg [18:0] a0;
reg [18:0] a1;
reg [18:0] a2;
reg [18:0] a3;
reg [18:0] a4;
reg [18:0] a5;
reg [18:0] a6;
reg [18:0] a7;
reg [18:0] a8;
reg [18:0] a9;
reg [18:0] a10;
reg [18:0] a11;
reg [18:0] a12;
reg [18:0] a13;
reg [18:0] a14;
reg [18:0] a15;
wire [18:0] sort0;
wire [18:0] sort1;
wire [18:0] sort2;
wire [18:0] sort3;
wire [18:0] sort4;
wire [18:0] sort5;
wire [18:0] sort6;
wire [18:0] sort7;
wire [18:0] sort8;
wire [18:0] sort9;
wire [18:0] sort10;
wire [18:0] sort11;
wire [18:0] sort12;
wire [18:0] sort13;
wire [18:0] sort14;
wire [18:0] sort15;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
ack_coding <= 1'b0;
else if (req_coding)
ack_coding <= 1'b1;
else
ack_coding <= 1'b0;
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state <= IDLE;
phase <= 4'b0;
loop <= 4'd0;
end else begin
state <= next_state;
phase <= next_phase;
loop <= next_loop;
end
end
always @(*) begin
case (state)
IDLE: begin
if (req_coding)
next_state = CODING;
else
next_state = IDLE;
next_phase = 4'b0;
next_loop = 4'd0;
end
CODING: begin
if (phase == 4'd9) begin
next_state = TRAVERSE;
next_phase = 4'd0;
end else begin
next_state = CODING;
next_phase = phase + 1;
end
next_loop = 4'd0;
end
TRAVERSE: begin
if (phase == 4'd8) begin
next_state = OUTPUT;
next_phase = 4'd0;
next_loop = code_length[0];
end else begin
next_state = TRAVERSE;
next_phase = phase + 1;
next_loop = 4'd0;
end
end
OUTPUT: begin
if (loop == 4'd1) begin
if (phase == 4'd9) begin
next_state = IDLE;
next_phase = 4'd0;
next_loop = 4'd0;
end else begin
next_state = OUTPUT;
next_phase = phase + 1;
next_loop = code_length[phase+1];
end
end
else begin
next_state = OUTPUT;
next_phase = phase;
next_loop = loop - 1;
end
end
default: begin
next_state = state;
next_phase = phase;
next_loop = loop;
end
endcase
end
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
a0 <= 19'b0;
a1 <= 19'b0;
a2 <= 19'b0;
a3 <= 19'b0;
a4 <= 19'b0;
a5 <= 19'b0;
a6 <= 19'b0;
a7 <= 19'b0;
a8 <= 19'b0;
a9 <= 19'b0;
a10 <= 19'b0;
a11 <= 19'b0;
a12 <= 19'b0;
a13 <= 19'b0;
a14 <= 19'b0;
a15 <= 19'b0;
end
else if (state==CODING) begin
case(phase)
4'd0: begin
a0 <= data_in0;
a1 <= data_in1;
a2 <= data_in2;
a3 <= data_in3;
a4 <= data_in4;
a5 <= data_in5;
a6 <= data_in6;
a7 <= data_in7;
a8 <= data_in8;
a9 <= data_in9;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd1: begin
a0 <= {6'b0, 5'd10, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= sort8;
a8 <= sort9;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd2: begin
a0 <= {6'b0, 5'd11, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= sort8;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd3: begin
a0 <= {6'b0, 5'd12, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= sort7;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd4: begin
a0 <= {6'b0, 5'd13, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= sort6;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd5: begin
a0 <= {6'b0, 5'd14, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= sort5;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd6: begin
a0 <= {6'b0, 5'd15, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= sort4;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd7: begin
a0 <= {6'b0, 5'd16, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= sort3;
a3 <= 19'd255;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd8: begin
a0 <= {6'b0, 5'd17, sort0[7:0]+sort1[7:0]};
a1 <= sort2;
a2 <= 19'd255;
a3 <= 19'd255;
a4 <= 19'd255;
a5 <= 19'd255;
a6 <= 19'd255;
a7 <= 19'd255;
a8 <= 19'd255;
a9 <= 19'd255;
a10 <= 19'd255;
a11 <= 19'd255;
a12 <= 19'd255;
a13 <= 19'd255;
a14 <= 19'd255;
a15 <= 19'd255;
end
4'd9: begin
a0 <= 19'b0;
a1 <= 19'b0;
a2 <= 19'b0;
a3 <= 19'b0;
a4 <= 19'b0;
a5 <= 19'b0;
a6 <= 19'b0;
a7 <= 19'b0;
a8 <= 19'b0;
a9 <= 19'b0;
a10 <= 19'b0;
a11 <= 19'b0;
a12 <= 19'b0;
a13 <= 19'b0;
a14 <= 19'b0;
a15 <= 19'b0;
end
default: begin
a0 <= 20'b0;
a1 <= 20'b0;
a2 <= 20'b0;
a3 <= 20'b0;
a4 <= 20'b0;
a5 <= 20'b0;
a6 <= 20'b0;
a7 <= 20'b0;
a8 <= 20'b0;
a9 <= 20'b0;
a10 <= 20'b0;
a11 <= 20'b0;
a12 <= 20'b0;
a13 <= 20'b0;
a14 <= 20'b0;
a15 <= 20'b0;
end
endcase
end
else begin
a0 <= 20'b0;
a1 <= 20'b0;
a2 <= 20'b0;
a3 <= 20'b0;
a4 <= 20'b0;
a5 <= 20'b0;
a6 <= 20'b0;
a7 <= 20'b0;
a8 <= 20'b0;
a9 <= 20'b0;
a10 <= 20'b0;
a11 <= 20'b0;
a12 <= 20'b0;
a13 <= 20'b0;
a14 <= 20'b0;
a15 <= 20'b0;
end
end
integer i;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
for (i = 0; i < 19; i = i + 1) begin
mem[i] <= 19'b0;
end
end
else if (state == CODING) begin
case (phase)
4'd0: ;
4'd1: begin
mem[sort0[12:8]] <= {5'd10, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd10, 1'd1, sort1[12:0]};
end
4'd2: begin
mem[sort0[12:8]] <= {5'd11, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd11, 1'd1, sort1[12:0]};
end
4'd3: begin
mem[sort0[12:8]] <= {5'd12, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd12, 1'd1, sort1[12:0]};
end
4'd4: begin
mem[sort0[12:8]] <= {5'd13, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd13, 1'd1, sort1[12:0]};
end
4'd5: begin
mem[sort0[12:8]] <= {5'd14, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd14, 1'd1, sort1[12:0]};
end
4'd6: begin
mem[sort0[12:8]] <= {5'd15, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd15, 1'd1, sort1[12:0]};
end
4'd7: begin
mem[sort0[12:8]] <= {5'd16, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd16, 1'd1, sort1[12:0]};
end
4'd8: begin
mem[sort0[12:8]] <= {5'd17, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd17, 1'd1, sort1[12:0]};
end
4'd9: begin
mem[sort0[12:8]] <= {5'd18, 1'd0, sort0[12:0]};
mem[sort1[12:8]] <= {5'd18, 1'd1, sort1[12:0]};
mem[18] <= {5'd31, 1'd0, 5'd18, sort0[7:0]+sort1[7:0]};
end
default: ;
endcase
end
end
SortX16 # (
.DSIZE (5'd19),
.OFFSET (4'd8)
) sortx16_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.a8 (a8),
.a9 (a9),
.a10 (a10),
.a11 (a11),
.a12 (a12),
.a13 (a13),
.a14 (a14),
.a15 (a15),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7),
.sort8 (sort8),
.sort9 (sort9),
.sort10 (sort10),
.sort11 (sort11),
.sort12 (sort12),
.sort13 (sort13),
.sort14 (sort14),
.sort15 (sort15)
);
genvar j;
reg [8:0] code_result [0:9];
reg [3:0] code_length [0:9];
reg [4:0] index [0:9];
generate
for (j = 0; j < 10; j = j + 1) begin
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
code_result[j] <= 9'b0;
code_length[j] <= 4'b0;
index[j] <= 5'b0;
end else if (state == TRAVERSE) begin
case (phase)
4'd0: begin
code_result[j][0] <= mem[j][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[j][18:14];
end
4'd1: begin
if (index[j] != 5'd18) begin
code_result[j][1] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd2: begin
if (index[j] != 5'd18) begin
code_result[j][2] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd3: begin
if (index[j] != 5'd18) begin
code_result[j][3] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd4: begin
if (index[j] != 5'd18) begin
code_result[j][4] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd5: begin
if (index[j] != 5'd18) begin
code_result[j][5] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd6: begin
if (index[j] != 5'd18) begin
code_result[j][6] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd7: begin
if (index[j] != 5'd18) begin
code_result[j][7] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
4'd8: begin
if (index[j] != 5'd18) begin
code_result[j][8] <= mem[index[j]][13];
code_length[j] <= code_length[j] + 1;
index[j] <= mem[index[j]][18:14];
end
end
default: begin
code_result[j] <= 9'b0;
code_length[j] <= 4'b0;
index[j] <= 5'b0;
end
endcase
end
end
end
endgenerate
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 9'd0;
data_len <= 4'd0;
end
else begin
if (next_state == OUTPUT) begin
data_out <= code_result[next_phase];
data_len <= code_length[next_phase];
end
else begin
data_out <= 9'd0;
data_len <= 4'd0;
end
end
end
assign trans_start = (state == OUTPUT) ? 1'b1 : 1'b0;
endmodule | 6 |
142,280 | data/full_repos/permissive/98495486/rtl model/huffman_top.v | 98,495,486 | huffman_top.v | v | 92 | 86 | [] | [] | [] | [(13, 91)] | null | null | 1: b'%Error: Cannot find file containing module: model,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.sv\n model,data/full_repos/permissive/98495486\n model,data/full_repos/permissive/98495486.v\n model,data/full_repos/permissive/98495486.sv\n obj_dir/model,data/full_repos/permissive/98495486\n obj_dir/model,data/full_repos/permissive/98495486.v\n obj_dir/model,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/huffman_top.v\n%Error: Exiting due to 3 error(s)\n' | 313,530 | module | module huffman_top(
input clk,
input rst_n,
input start,
input start_done,
input [3:0] data_in,
output wire output_data,
output wire output_start,
output wire output_done
);
wire ack_coding;
wire req_coding;
wire [18:0] data0;
wire [18:0] data1;
wire [18:0] data2;
wire [18:0] data3;
wire [18:0] data4;
wire [18:0] data5;
wire [18:0] data6;
wire [18:0] data7;
wire [18:0] data8;
wire [18:0] data9;
wire [8:0] data_para;
wire [3:0] data_len;
wire trans_start;
freqcount freq_inst(
.clk (clk),
.rst_n (rst_n),
.start (start),
.start_done (start_done),
.data_in (data_in),
.ack_coding (ack_coding),
.req_coding (req_coding),
.data_out0 (data0),
.data_out1 (data1),
.data_out2 (data2),
.data_out3 (data3),
.data_out4 (data4),
.data_out5 (data5),
.data_out6 (data6),
.data_out7 (data7),
.data_out8 (data8),
.data_out9 (data9)
);
HuffmanCode huffmancode (
.clk (clk),
.rst_n (rst_n),
.data_in0 (data0),
.data_in1 (data1),
.data_in2 (data2),
.data_in3 (data3),
.data_in4 (data4),
.data_in5 (data5),
.data_in6 (data6),
.data_in7 (data7),
.data_in8 (data8),
.data_in9 (data9),
.req_coding (req_coding),
.ack_coding (ack_coding),
.data_out (data_para),
.data_len (data_len),
.trans_start(trans_start)
);
para2ser para2ser_inst(
.clk (clk),
.rst_n (rst_n),
.trans_start (trans_start),
.data (data_para),
.data_len (data_len),
.output_data (output_data),
.output_start (output_start),
.output_done (output_done)
);
endmodule | module huffman_top(
input clk,
input rst_n,
input start,
input start_done,
input [3:0] data_in,
output wire output_data,
output wire output_start,
output wire output_done
); |
wire ack_coding;
wire req_coding;
wire [18:0] data0;
wire [18:0] data1;
wire [18:0] data2;
wire [18:0] data3;
wire [18:0] data4;
wire [18:0] data5;
wire [18:0] data6;
wire [18:0] data7;
wire [18:0] data8;
wire [18:0] data9;
wire [8:0] data_para;
wire [3:0] data_len;
wire trans_start;
freqcount freq_inst(
.clk (clk),
.rst_n (rst_n),
.start (start),
.start_done (start_done),
.data_in (data_in),
.ack_coding (ack_coding),
.req_coding (req_coding),
.data_out0 (data0),
.data_out1 (data1),
.data_out2 (data2),
.data_out3 (data3),
.data_out4 (data4),
.data_out5 (data5),
.data_out6 (data6),
.data_out7 (data7),
.data_out8 (data8),
.data_out9 (data9)
);
HuffmanCode huffmancode (
.clk (clk),
.rst_n (rst_n),
.data_in0 (data0),
.data_in1 (data1),
.data_in2 (data2),
.data_in3 (data3),
.data_in4 (data4),
.data_in5 (data5),
.data_in6 (data6),
.data_in7 (data7),
.data_in8 (data8),
.data_in9 (data9),
.req_coding (req_coding),
.ack_coding (ack_coding),
.data_out (data_para),
.data_len (data_len),
.trans_start(trans_start)
);
para2ser para2ser_inst(
.clk (clk),
.rst_n (rst_n),
.trans_start (trans_start),
.data (data_para),
.data_len (data_len),
.output_data (output_data),
.output_start (output_start),
.output_done (output_done)
);
endmodule | 6 |
142,281 | data/full_repos/permissive/98495486/rtl model/para2ser.v | 98,495,486 | para2ser.v | v | 57 | 70 | [] | [] | [] | [(14, 56)] | null | null | 1: b'%Error: Cannot find file containing module: model,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model,data/full_repos/permissive/98495486.sv\n model,data/full_repos/permissive/98495486\n model,data/full_repos/permissive/98495486.v\n model,data/full_repos/permissive/98495486.sv\n obj_dir/model,data/full_repos/permissive/98495486\n obj_dir/model,data/full_repos/permissive/98495486.v\n obj_dir/model,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/para2ser.v\n%Error: Exiting due to 3 error(s)\n' | 313,531 | module | module para2ser(
input clk,
input rst_n,
input trans_start,
input [8:0] data,
input [3:0] data_len,
output wire output_data,
output wire output_start,
output wire output_done
);
reg [3:0] data_cnt;
reg [8:0] data_reg;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
data_cnt <= 4'b0;
data_reg <= 9'b0;
end
else if(trans_start) begin
data_cnt <= (data_cnt == 4'b0) ? data_len-1 : data_cnt-1;
data_reg <= data;
end
end
reg trans_start_q1;
reg trans_start_q2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trans_start_q1 <= 1'b0;
trans_start_q2 <= 1'b0;
end
else begin
trans_start_q1 <= trans_start;
trans_start_q2 <= trans_start_q1;
end
end
assign output_start = trans_start & ~trans_start_q1;
assign output_done = ~trans_start_q1 & trans_start_q2;
assign output_data = (data_reg >> data_cnt) & 1'b1;
endmodule | module para2ser(
input clk,
input rst_n,
input trans_start,
input [8:0] data,
input [3:0] data_len,
output wire output_data,
output wire output_start,
output wire output_done
); |
reg [3:0] data_cnt;
reg [8:0] data_reg;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
data_cnt <= 4'b0;
data_reg <= 9'b0;
end
else if(trans_start) begin
data_cnt <= (data_cnt == 4'b0) ? data_len-1 : data_cnt-1;
data_reg <= data;
end
end
reg trans_start_q1;
reg trans_start_q2;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
trans_start_q1 <= 1'b0;
trans_start_q2 <= 1'b0;
end
else begin
trans_start_q1 <= trans_start;
trans_start_q2 <= trans_start_q1;
end
end
assign output_start = trans_start & ~trans_start_q1;
assign output_done = ~trans_start_q1 & trans_start_q2;
assign output_data = (data_reg >> data_cnt) & 1'b1;
endmodule | 6 |
142,283 | data/full_repos/permissive/98495486/rtl model/sortnet/SortElement.v | 98,495,486 | SortElement.v | v | 15 | 56 | [] | [] | [] | [(1, 14)] | null | null | 1: b'%Error: Cannot find file containing module: model/sortnet,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.sv\n model/sortnet,data/full_repos/permissive/98495486\n model/sortnet,data/full_repos/permissive/98495486.v\n model/sortnet,data/full_repos/permissive/98495486.sv\n obj_dir/model/sortnet,data/full_repos/permissive/98495486\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.v\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/sortnet/SortElement.v\n%Error: Exiting due to 3 error(s)\n' | 313,534 | module | module SortElement # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a,
input [DSIZE-1:0] b,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1
);
assign sort0 = a[OFFSET-1:0] > b[OFFSET-1:0] ? b : a;
assign sort1 = a[OFFSET-1:0] > b[OFFSET-1:0] ? a : b;
endmodule | module SortElement # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a,
input [DSIZE-1:0] b,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1
); |
assign sort0 = a[OFFSET-1:0] > b[OFFSET-1:0] ? b : a;
assign sort1 = a[OFFSET-1:0] > b[OFFSET-1:0] ? a : b;
endmodule | 6 |
142,284 | data/full_repos/permissive/98495486/rtl model/sortnet/SortX16.v | 98,495,486 | SortX16.v | v | 236 | 34 | [] | [] | [] | [(1, 235)] | null | null | 1: b'%Error: Cannot find file containing module: model/sortnet,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.sv\n model/sortnet,data/full_repos/permissive/98495486\n model/sortnet,data/full_repos/permissive/98495486.v\n model/sortnet,data/full_repos/permissive/98495486.sv\n obj_dir/model/sortnet,data/full_repos/permissive/98495486\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.v\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/sortnet/SortX16.v\n%Error: Exiting due to 3 error(s)\n' | 313,535 | module | module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
);
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule | module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
); |
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule | 6 |
142,285 | data/full_repos/permissive/98495486/rtl model/sortnet/SortX4.v | 98,495,486 | SortX4.v | v | 84 | 33 | [] | [] | [] | [(1, 83)] | null | null | 1: b'%Error: Cannot find file containing module: model/sortnet,data/full_repos/permissive/98495486\n ... Looked in:\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.v\n data/full_repos/permissive/98495486/rtl/model/sortnet,data/full_repos/permissive/98495486.sv\n model/sortnet,data/full_repos/permissive/98495486\n model/sortnet,data/full_repos/permissive/98495486.v\n model/sortnet,data/full_repos/permissive/98495486.sv\n obj_dir/model/sortnet,data/full_repos/permissive/98495486\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.v\n obj_dir/model/sortnet,data/full_repos/permissive/98495486.sv\n%Error: Cannot find file containing module: data/full_repos/permissive/98495486/rtl\n%Error: Cannot find file containing module: model/sortnet/SortX4.v\n%Error: Exiting due to 3 error(s)\n' | 313,536 | module | module SortX4 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3
);
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a1),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a2),
.b(a3),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sort0_0),
.b(sort1_1),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sort0_1),
.b(sort1_0),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sort2_0),
.b(sort3_0),
.sort0(sort0),
.sort1(sort1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sort3_1),
.b(sort2_1),
.sort0(sort2),
.sort1(sort3)
);
endmodule | module SortX4 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3
); |
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(a0),
.b(a1),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(a2),
.b(a3),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sort0_0),
.b(sort1_1),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sort0_1),
.b(sort1_0),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sort2_0),
.b(sort3_0),
.sort0(sort0),
.sort1(sort1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sort3_1),
.b(sort2_1),
.sort0(sort2),
.sort1(sort3)
);
endmodule | 6 |
142,287 | data/full_repos/permissive/98495486/simulation/huffman_test.v | 98,495,486 | huffman_test.v | v | 78 | 84 | [] | [] | [] | [(22, 77)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:31: Unsupported: Ignoring delay on this delayed statement.\n #10 rst_n = 1\'b0;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:32: Unsupported: Ignoring delay on this delayed statement.\n #10 rst_n = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:36: Unsupported: Ignoring delay on this delayed statement.\n forever #1 clk = ~clk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:40: Unsupported: Ignoring delay on this delayed statement.\n #50 start = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:41: Unsupported: Ignoring delay on this delayed statement.\n #2 start = 1\'b0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n #52 data_in = 4\'d0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n #10 data_in = 4\'d1; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:47: Unsupported: Ignoring delay on this delayed statement.\n #2 data_in = 4\'d2; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:48: Unsupported: Ignoring delay on this delayed statement.\n #6 data_in = 4\'d3; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:49: Unsupported: Ignoring delay on this delayed statement.\n #4 data_in = 4\'d4; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:50: Unsupported: Ignoring delay on this delayed statement.\n #18 data_in = 4\'d5; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:51: Unsupported: Ignoring delay on this delayed statement.\n #14 data_in = 4\'d6; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:52: Unsupported: Ignoring delay on this delayed statement.\n #8 data_in = 4\'d7; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:53: Unsupported: Ignoring delay on this delayed statement.\n #16 data_in = 4\'d8; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:54: Unsupported: Ignoring delay on this delayed statement.\n #12 data_in = 4\'d0; \n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:58: Unsupported: Ignoring delay on this delayed statement.\n #140 start_done = 1\'b1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98495486/simulation/huffman_test.v:59: Unsupported: Ignoring delay on this delayed statement.\n #2 start_done = 1\'b0;\n ^\n%Error: data/full_repos/permissive/98495486/simulation/huffman_test.v:66: Cannot find file containing module: \'huffman_top\'\n huffman_top sim_top(\n ^~~~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98495486/simulation,data/full_repos/permissive/98495486/huffman_top\n data/full_repos/permissive/98495486/simulation,data/full_repos/permissive/98495486/huffman_top.v\n data/full_repos/permissive/98495486/simulation,data/full_repos/permissive/98495486/huffman_top.sv\n huffman_top\n huffman_top.v\n huffman_top.sv\n obj_dir/huffman_top\n obj_dir/huffman_top.v\n obj_dir/huffman_top.sv\n%Error: Exiting due to 1 error(s), 17 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,538 | module | module huffmancode_test();
reg clk;
reg rst_n;
reg start;
reg start_done;
reg [3:0] data_in;
initial begin
rst_n = 1'b1;
#10 rst_n = 1'b0;
#10 rst_n = 1'b1;
end
initial begin
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
start = 1'b0;
#50 start = 1'b1;
#2 start = 1'b0;
end
initial begin
data_in = 4'b0;
#52 data_in = 4'd0;
#10 data_in = 4'd1;
#2 data_in = 4'd2;
#6 data_in = 4'd3;
#4 data_in = 4'd4;
#18 data_in = 4'd5;
#14 data_in = 4'd6;
#8 data_in = 4'd7;
#16 data_in = 4'd8;
#12 data_in = 4'd0;
end
initial begin
start_done = 1'b0;
#140 start_done = 1'b1;
#2 start_done = 1'b0;
end
wire output_data;
wire output_start;
wire output_done;
huffman_top sim_top(
.clk (clk),
.rst_n (rst_n),
.start (start),
.start_done (start_done),
.data_in (data_in),
.output_data (output_data),
.output_start (output_start),
.output_done (output_done)
);
endmodule | module huffmancode_test(); |
reg clk;
reg rst_n;
reg start;
reg start_done;
reg [3:0] data_in;
initial begin
rst_n = 1'b1;
#10 rst_n = 1'b0;
#10 rst_n = 1'b1;
end
initial begin
clk = 1'b1;
forever #1 clk = ~clk;
end
initial begin
start = 1'b0;
#50 start = 1'b1;
#2 start = 1'b0;
end
initial begin
data_in = 4'b0;
#52 data_in = 4'd0;
#10 data_in = 4'd1;
#2 data_in = 4'd2;
#6 data_in = 4'd3;
#4 data_in = 4'd4;
#18 data_in = 4'd5;
#14 data_in = 4'd6;
#8 data_in = 4'd7;
#16 data_in = 4'd8;
#12 data_in = 4'd0;
end
initial begin
start_done = 1'b0;
#140 start_done = 1'b1;
#2 start_done = 1'b0;
end
wire output_data;
wire output_start;
wire output_done;
huffman_top sim_top(
.clk (clk),
.rst_n (rst_n),
.start (start),
.start_done (start_done),
.data_in (data_in),
.output_data (output_data),
.output_start (output_start),
.output_done (output_done)
);
endmodule | 6 |
142,291 | data/full_repos/permissive/98596700/vm1801mini/serial.v | 98,596,700 | serial.v | v | 196 | 89 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xef in position 6: invalid continuation byte | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98596700/vm1801mini/serial.v:145: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'serial_rx\'\nmodule serial_rx(\n ^~~~~~~~~\n : ... Top module \'serial_tx\'\nmodule serial_tx(\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,794 | module | module serial_rx(
input wire reset,
input wire clk,
input wire rx,
input wire rxread,
output [7:0]rxbyte,
output reg ready = 0
);
parameter RCONST = 2396;
reg [3:0]num_bits = 10;
reg [7:0]shift_reg = 0;
reg [11:0]cnt = 0;
assign rxbyte = shift_reg;
always @(posedge clk or negedge reset)
begin
if(!reset) begin
num_bits <= 4'd10;
shift_reg <= 0;
cnt <= 0;
ready <= 0;
end
else begin
if(num_bits == 4'd10 && rx == 1'b0)
num_bits <= 4'd0;
else if(cnt == RCONST)
num_bits <= num_bits + 1'b1;
if(cnt == RCONST/2 && num_bits < 4'd9) shift_reg <= {rx,shift_reg[7:1]};
cnt <= (cnt == RCONST || num_bits == 4'd10)? 12'd0 : cnt + 1'b1;
ready <= (ready)? !rxread : (cnt == RCONST/2 && num_bits == 4'd9);
end
end
endmodule | module serial_rx(
input wire reset,
input wire clk,
input wire rx,
input wire rxread,
output [7:0]rxbyte,
output reg ready = 0
); |
parameter RCONST = 2396;
reg [3:0]num_bits = 10;
reg [7:0]shift_reg = 0;
reg [11:0]cnt = 0;
assign rxbyte = shift_reg;
always @(posedge clk or negedge reset)
begin
if(!reset) begin
num_bits <= 4'd10;
shift_reg <= 0;
cnt <= 0;
ready <= 0;
end
else begin
if(num_bits == 4'd10 && rx == 1'b0)
num_bits <= 4'd0;
else if(cnt == RCONST)
num_bits <= num_bits + 1'b1;
if(cnt == RCONST/2 && num_bits < 4'd9) shift_reg <= {rx,shift_reg[7:1]};
cnt <= (cnt == RCONST || num_bits == 4'd10)? 12'd0 : cnt + 1'b1;
ready <= (ready)? !rxread : (cnt == RCONST/2 && num_bits == 4'd9);
end
end
endmodule | 1 |
142,292 | data/full_repos/permissive/98596700/vm1801mini/serial.v | 98,596,700 | serial.v | v | 196 | 89 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xef in position 6: invalid continuation byte | null | 1: b'%Warning-MULTITOP: data/full_repos/permissive/98596700/vm1801mini/serial.v:145: Multiple top level modules\n : ... Suggest see manual; fix the duplicates, or use --top-module to select top.\n ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message.\n : ... Top module \'serial_rx\'\nmodule serial_rx(\n ^~~~~~~~~\n : ... Top module \'serial_tx\'\nmodule serial_tx(\n ^~~~~~~~~\n%Error: Exiting due to 1 warning(s)\n' | 313,794 | module | module serial_tx(
input reset,
input clk,
input [7:0]sbyte,
input send,
output tx,
output reg busy = 1'b0
);
parameter RCONST = 2396;
reg [8:0]send_reg = 9'b1_1111_1111;
reg [3:0]send_num = 10;
reg [11:0]send_cnt;
wire send_time;
assign send_time = (send_cnt == RCONST);
assign tx = send_reg[0];
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
send_num <= 10;
send_cnt <= 0;
end
else
begin
if(send) begin
send_reg <= {sbyte,1'b0};
send_num <= 0;
end
else if(send_time && send_num != 10) begin
send_reg <= {1'b1,send_reg[8:1]};
send_num <= send_num + 1'b1;
end
send_cnt <= (send | send_time)? 12'd0 : send_cnt + 1'b1;
end
end
always@(posedge clk)
begin
busy <= (send_num != 10);
end
endmodule | module serial_tx(
input reset,
input clk,
input [7:0]sbyte,
input send,
output tx,
output reg busy = 1'b0
); |
parameter RCONST = 2396;
reg [8:0]send_reg = 9'b1_1111_1111;
reg [3:0]send_num = 10;
reg [11:0]send_cnt;
wire send_time;
assign send_time = (send_cnt == RCONST);
assign tx = send_reg[0];
always @(posedge clk or negedge reset)
begin
if(!reset)
begin
send_num <= 10;
send_cnt <= 0;
end
else
begin
if(send) begin
send_reg <= {sbyte,1'b0};
send_num <= 0;
end
else if(send_time && send_num != 10) begin
send_reg <= {1'b1,send_reg[8:1]};
send_num <= send_num + 1'b1;
end
send_cnt <= (send | send_time)? 12'd0 : send_cnt + 1'b1;
end
end
always@(posedge clk)
begin
busy <= (send_num != 10);
end
endmodule | 1 |
142,293 | data/full_repos/permissive/98596700/vm1801mini/svga.v | 98,596,700 | svga.v | v | 151 | 95 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xf0 in position 835: invalid continuation byte | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:104: Operator EQ expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n : ... In instance video\n({SelVSh,SelHSh} == 4\'b001)? 16\'h0 :\n ^~\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:105: Operator EQ expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n : ... In instance video\n({SelVSh,SelHSh} == 4\'b011)? 16\'h0 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:106: Operator EQ expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n : ... In instance video\n({SelVSh,SelHSh} == 4\'b111)? 16\'h0 :\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:107: Operator EQ expects 4 bits on the LHS, but LHS\'s REPLICATE generates 3 bits.\n : ... In instance video\n({SelVSh,SelHSh} == 4\'b110)? PIXCOLOR : 16\'h0;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:118: Logical Operator COND expects 1 bit on the Conditional Test, but Conditional Test\'s VARREF \'Req\' generates 2 bits.\n : ... In instance video\n if(!colcnt[0]) SHIFT[7:0] <= (Req)? PIXDATA[7:0] : {SHIFT[6:0], 1\'b0};\n ^\n%Warning-WIDTH: data/full_repos/permissive/98596700/vm1801mini/svga.v:127: Operator ADD expects 10 bits on the RHS, but RHS\'s VARREF \'H_SYNC\' generates 1 bits.\n : ... In instance video\n vcnt <= vcnt + H_SYNC;\n ^\n%Error: Exiting due to 6 warning(s)\n' | 313,795 | module | module video(
output [15:0]RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0]PIXADDR,
input [7:0]PIXDATA,
input PixClock
);
reg [7:0]SHIFT;
assign RGB = {
wCOLOR[15:11],
wCOLOR[10:5],
wCOLOR[4:0]
};
wire [10:0]HFrontPorch = 24;
wire [10:0]HBackPorch = 144;
wire [10:0]LeftBorder = 0;
wire [10:0]HAddrVideo = LeftBorder + 1024;
wire [10:0]RightBorder = HAddrVideo + 0;
wire [10:0]HTotalTime = 1328;
wire [10:0]HSyncStartTime = 1048;
wire [9:0]VBackPorch = 28;
wire [9:0]TopBorder = VBackPorch + 128;
wire [9:0]VAddrVideo = TopBorder + 512;
wire [9:0]BottomBorder = VAddrVideo + 128;
wire [9:0]VTotalTime = 806;
wire [9:0]VSyncStartTime = 771;
reg [10:0]hcnt = 0;
reg [9:0]vcnt = 0;
reg [9:0]colcnt = 0;
reg [8:0]rowcnt = 0;
wire H_SYNC = (hcnt==HSyncStartTime);
wire wVBackPorch = (vcnt < VBackPorch)? 1'b0 : 1'b1;
reg SelHSh = 1'b0;
wire [1:0]SelVSh =
(vcnt < VBackPorch)? 2'b00 :
(vcnt < TopBorder)? 2'b01 :
(vcnt < VAddrVideo)? 2'b11 :
(vcnt < BottomBorder)? 2'b01 : 2'b00;
`define Border 16'h1
`define BLANK 16'h0
assign PIXADDR = {rowcnt[8:1],colcnt[9:4]};
wire pixreq = (colcnt[3:0] == 4'b0000);
wire [15:0]PIXCOLOR = (SHIFT[7])? 16'h03E0 : 16'd0;
wire [15:0]wCOLOR =
({SelVSh,SelHSh} == 4'b001)? `BLANK :
({SelVSh,SelHSh} == 4'b011)? `BLANK :
({SelVSh,SelHSh} == 4'b111)? `BLANK :
({SelVSh,SelHSh} == 4'b110)? PIXCOLOR : `BLANK;
reg [1:0]Req = 2'b00;
always@(posedge PixClock) begin
Req <= {Req[0], pixreq};
if(!colcnt[0]) SHIFT[7:0] <= (Req)? PIXDATA[7:0] : {SHIFT[6:0], 1'b0};
if(vcnt==VTotalTime) begin
VSync <= 1'b1;
vcnt <= 0;
rowcnt <= 0;
end
else begin
if(vcnt==VSyncStartTime) VSync <= 1'b0;
vcnt <= vcnt + H_SYNC;
end
if((hcnt == HSyncStartTime) | (hcnt==(HTotalTime - HBackPorch))) HSync <= !HSync;
if((hcnt == HAddrVideo)|(hcnt == HTotalTime)) SelHSh <= !SelHSh;
if(hcnt == HTotalTime) begin
hcnt <= 0;
colcnt <= 0;
if(vcnt > TopBorder) begin
rowcnt <= rowcnt + 1'b1;
end
end
else begin
hcnt <= hcnt + 1'b1;
end
if({SelVSh,SelHSh} == 3'b110) colcnt <= colcnt + 1'b1;
end
endmodule | module video(
output [15:0]RGB,
output reg HSync = 1,
output reg VSync = 1,
output [13:0]PIXADDR,
input [7:0]PIXDATA,
input PixClock
); |
reg [7:0]SHIFT;
assign RGB = {
wCOLOR[15:11],
wCOLOR[10:5],
wCOLOR[4:0]
};
wire [10:0]HFrontPorch = 24;
wire [10:0]HBackPorch = 144;
wire [10:0]LeftBorder = 0;
wire [10:0]HAddrVideo = LeftBorder + 1024;
wire [10:0]RightBorder = HAddrVideo + 0;
wire [10:0]HTotalTime = 1328;
wire [10:0]HSyncStartTime = 1048;
wire [9:0]VBackPorch = 28;
wire [9:0]TopBorder = VBackPorch + 128;
wire [9:0]VAddrVideo = TopBorder + 512;
wire [9:0]BottomBorder = VAddrVideo + 128;
wire [9:0]VTotalTime = 806;
wire [9:0]VSyncStartTime = 771;
reg [10:0]hcnt = 0;
reg [9:0]vcnt = 0;
reg [9:0]colcnt = 0;
reg [8:0]rowcnt = 0;
wire H_SYNC = (hcnt==HSyncStartTime);
wire wVBackPorch = (vcnt < VBackPorch)? 1'b0 : 1'b1;
reg SelHSh = 1'b0;
wire [1:0]SelVSh =
(vcnt < VBackPorch)? 2'b00 :
(vcnt < TopBorder)? 2'b01 :
(vcnt < VAddrVideo)? 2'b11 :
(vcnt < BottomBorder)? 2'b01 : 2'b00;
`define Border 16'h1
`define BLANK 16'h0
assign PIXADDR = {rowcnt[8:1],colcnt[9:4]};
wire pixreq = (colcnt[3:0] == 4'b0000);
wire [15:0]PIXCOLOR = (SHIFT[7])? 16'h03E0 : 16'd0;
wire [15:0]wCOLOR =
({SelVSh,SelHSh} == 4'b001)? `BLANK :
({SelVSh,SelHSh} == 4'b011)? `BLANK :
({SelVSh,SelHSh} == 4'b111)? `BLANK :
({SelVSh,SelHSh} == 4'b110)? PIXCOLOR : `BLANK;
reg [1:0]Req = 2'b00;
always@(posedge PixClock) begin
Req <= {Req[0], pixreq};
if(!colcnt[0]) SHIFT[7:0] <= (Req)? PIXDATA[7:0] : {SHIFT[6:0], 1'b0};
if(vcnt==VTotalTime) begin
VSync <= 1'b1;
vcnt <= 0;
rowcnt <= 0;
end
else begin
if(vcnt==VSyncStartTime) VSync <= 1'b0;
vcnt <= vcnt + H_SYNC;
end
if((hcnt == HSyncStartTime) | (hcnt==(HTotalTime - HBackPorch))) HSync <= !HSync;
if((hcnt == HAddrVideo)|(hcnt == HTotalTime)) SelHSh <= !SelHSh;
if(hcnt == HTotalTime) begin
hcnt <= 0;
colcnt <= 0;
if(vcnt > TopBorder) begin
rowcnt <= rowcnt + 1'b1;
end
end
else begin
hcnt <= hcnt + 1'b1;
end
if({SelVSh,SelHSh} == 3'b110) colcnt <= colcnt + 1'b1;
end
endmodule | 1 |
142,294 | data/full_repos/permissive/98596700/vm1801mini/sysgen.v | 98,596,700 | sysgen.v | v | 149 | 114 | [] | [] | [] | [(21, 148)] | null | null | 1: b"%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:33: Cannot find file containing module: 'BUFG'\n BUFG BUFG_FBCLK (\n ^~~~\n ... Looked in:\n data/full_repos/permissive/98596700/vm1801mini,data/full_repos/permissive/98596700/BUFG\n data/full_repos/permissive/98596700/vm1801mini,data/full_repos/permissive/98596700/BUFG.v\n data/full_repos/permissive/98596700/vm1801mini,data/full_repos/permissive/98596700/BUFG.sv\n BUFG\n BUFG.v\n BUFG.sv\n obj_dir/BUFG\n obj_dir/BUFG.v\n obj_dir/BUFG.sv\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:41: Cannot find file containing module: 'DCM_SP'\n DCM_SP #(\n ^~~~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:81: Cannot find file containing module: 'BUFG'\n BUFG BUFG_SMCLKFB (\n ^~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:86: Cannot find file containing module: 'BUFG'\n BUFG BUFG_SMCLK (\n ^~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:91: Cannot find file containing module: 'DCM_SP'\n DCM_SP #(\n ^~~~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:131: Cannot find file containing module: 'BUFG'\n BUFG BUFG_CLKCPUN (\n ^~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:136: Cannot find file containing module: 'BUFG'\n BUFG BUFG_CLKCPUP (\n ^~~~\n%Error: data/full_repos/permissive/98596700/vm1801mini/sysgen.v:141: Cannot find file containing module: 'BUFG'\n BUFG BUFG_CLKCPUFB (\n ^~~~\n%Error: Exiting due to 8 error(s)\n" | 313,796 | module | module SYNC(
output clk75,
output clk50p,
output clk50n,
input CLK
);
wire clk_fb0_nb, clk_fb0_buf;
wire clk_fb2_nb, clk_fb2_buf;
wire clk75_nb, clk50p_nb, clk50n_nb;
wire clkbuf;
BUFG BUFG_FBCLK (
.O(clkbuf),
.I(CLK)
);
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(16),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833333),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DSS_MODE("NONE"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hc080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_CPU (
.CLK0(clk_fb0_nb),
.CLKDV(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX180(),
.CLKFB(clk_fb0_buf),
.CLKFX(clk75_nb),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKIN(clkbuf),
.PSCLK(),
.PSINCDEC(),
.PSEN(1'b0),
.DSSEN(1'b0),
.RST(1'b0)
);
BUFG BUFG_SMCLKFB (
.O(clk_fb0_buf),
.I(clk_fb0_nb)
);
BUFG BUFG_SMCLK (
.O(clk75),
.I(clk75_nb)
);
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(24),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833333),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DSS_MODE("NONE"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hc080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_VIDEO (
.CLK0(clk_fb2_nb),
.CLKDV(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX180(clk50n_nb),
.CLKFB(clk_fb2_buf),
.CLKFX(clk50p_nb),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKIN(clkbuf),
.PSCLK(),
.PSINCDEC(),
.PSEN(1'b0),
.DSSEN(1'b0),
.RST(1'b0)
);
BUFG BUFG_CLKCPUN (
.O(clk50n),
.I(clk50n_nb)
);
BUFG BUFG_CLKCPUP (
.O(clk50p),
.I(clk50p_nb)
);
BUFG BUFG_CLKCPUFB (
.O(clk_fb2_buf),
.I(clk_fb2_nb)
);
endmodule | module SYNC(
output clk75,
output clk50p,
output clk50n,
input CLK
); |
wire clk_fb0_nb, clk_fb0_buf;
wire clk_fb2_nb, clk_fb2_buf;
wire clk75_nb, clk50p_nb, clk50n_nb;
wire clkbuf;
BUFG BUFG_FBCLK (
.O(clkbuf),
.I(CLK)
);
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(16),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833333),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DSS_MODE("NONE"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hc080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_CPU (
.CLK0(clk_fb0_nb),
.CLKDV(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX180(),
.CLKFB(clk_fb0_buf),
.CLKFX(clk75_nb),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKIN(clkbuf),
.PSCLK(),
.PSINCDEC(),
.PSEN(1'b0),
.DSSEN(1'b0),
.RST(1'b0)
);
BUFG BUFG_SMCLKFB (
.O(clk_fb0_buf),
.I(clk_fb0_nb)
);
BUFG BUFG_SMCLK (
.O(clk75),
.I(clk75_nb)
);
DCM_SP #(
.CLKDV_DIVIDE(2.0),
.CLKFX_DIVIDE(24),
.CLKFX_MULTIPLY(25),
.CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(20.833333),
.CLKOUT_PHASE_SHIFT("NONE"),
.CLK_FEEDBACK("1X"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
.DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"),
.DSS_MODE("NONE"),
.DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hc080),
.PHASE_SHIFT(0),
.STARTUP_WAIT("FALSE")
)
DCM_SP_VIDEO (
.CLK0(clk_fb2_nb),
.CLKDV(),
.CLK90(),
.CLK180(),
.CLK270(),
.CLK2X(),
.CLK2X180(),
.CLKFX180(clk50n_nb),
.CLKFB(clk_fb2_buf),
.CLKFX(clk50p_nb),
.LOCKED(),
.PSDONE(),
.STATUS(),
.CLKIN(clkbuf),
.PSCLK(),
.PSINCDEC(),
.PSEN(1'b0),
.DSSEN(1'b0),
.RST(1'b0)
);
BUFG BUFG_CLKCPUN (
.O(clk50n),
.I(clk50n_nb)
);
BUFG BUFG_CLKCPUP (
.O(clk50p),
.I(clk50p_nb)
);
BUFG BUFG_CLKCPUFB (
.O(clk_fb2_buf),
.I(clk_fb2_nb)
);
endmodule | 1 |
142,296 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module ALU(ALUOut,in1,in2,ALUFun,Sign);
output [31:0] ALUOut;
input [31:0] in1;
input [31:0] in2;
input [5:0] ALUFun;
input Sign;
wire [31:0] cmp_out,shift_out,logic_out,addsub_out;
addsub adsb(.S(addsub_out),.Z(Z),.V(V),.N(N),.in1(in1),.in2(in2),.ALUFun(ALUFun[0]),.Sign(Sign));
cmp cp(.S(cmp_out),.V(V),.N(N),.ALUFun(ALUFun[3:1]),.in1(in1),.in2(in2),.Sign(Sign));
logic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));
shift sft(.out(shift_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[1:0]));
assign ALUOut=ALUFun[5]?(ALUFun[4]?cmp_out:shift_out):
(ALUFun[4]?logic_out:addsub_out);
endmodule | module ALU(ALUOut,in1,in2,ALUFun,Sign); |
output [31:0] ALUOut;
input [31:0] in1;
input [31:0] in2;
input [5:0] ALUFun;
input Sign;
wire [31:0] cmp_out,shift_out,logic_out,addsub_out;
addsub adsb(.S(addsub_out),.Z(Z),.V(V),.N(N),.in1(in1),.in2(in2),.ALUFun(ALUFun[0]),.Sign(Sign));
cmp cp(.S(cmp_out),.V(V),.N(N),.ALUFun(ALUFun[3:1]),.in1(in1),.in2(in2),.Sign(Sign));
logic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));
shift sft(.out(shift_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[1:0]));
assign ALUOut=ALUFun[5]?(ALUFun[4]?cmp_out:shift_out):
(ALUFun[4]?logic_out:addsub_out);
endmodule | 0 |
142,297 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module addsub(S,Z,V,N,in1,in2,ALUFun,Sign);
output [31:0] S;
output Z,V,N;
input [31:0] in1, in2;
input ALUFun,Sign;
wire [31:0]s_add,s_sub;
wire z_add,v_add,n_add, z_sub,v_sub,n_sub;
wire [31:0] inv_in2;
assign inv_in2 = ~in2+1;
assign s_add = in1+in2;
assign z_add = (s_add==0);
assign n_add = Sign&s_add[31];
assign v_add = Sign&(s_add[31]^in1[31])&~(in1[31]^in2[31]);
assign s_sub = in1+inv_in2;
assign z_sub = (s_sub==0);
assign n_sub = Sign&s_sub[31];
assign v_sub = Sign&(s_sub[31]^in1[31])&~(in1[31]^inv_in2[31]);
assign S=ALUFun?s_sub:s_add;
assign Z=ALUFun?z_sub:z_add;
assign N=ALUFun?n_sub:n_add;
assign V=ALUFun?v_sub:v_add;
endmodule | module addsub(S,Z,V,N,in1,in2,ALUFun,Sign); |
output [31:0] S;
output Z,V,N;
input [31:0] in1, in2;
input ALUFun,Sign;
wire [31:0]s_add,s_sub;
wire z_add,v_add,n_add, z_sub,v_sub,n_sub;
wire [31:0] inv_in2;
assign inv_in2 = ~in2+1;
assign s_add = in1+in2;
assign z_add = (s_add==0);
assign n_add = Sign&s_add[31];
assign v_add = Sign&(s_add[31]^in1[31])&~(in1[31]^in2[31]);
assign s_sub = in1+inv_in2;
assign z_sub = (s_sub==0);
assign n_sub = Sign&s_sub[31];
assign v_sub = Sign&(s_sub[31]^in1[31])&~(in1[31]^inv_in2[31]);
assign S=ALUFun?s_sub:s_add;
assign Z=ALUFun?z_sub:z_add;
assign N=ALUFun?n_sub:n_add;
assign V=ALUFun?v_sub:v_add;
endmodule | 0 |
142,298 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module cmp(S,V,N,ALUFun,in1,in2,Sign);
input V,N,Sign;
input [2:0] ALUFun;
input [31:0] in1,in2;
output [31:0] S;
wire EQ,NEQ,LT,LEZ,LTZ,GTZ;
assign EQ=in1==in2;
assign NEQ=~(in1==in2);
assign LT=(~V&N)|(V&in1[31]);
assign EQZ=(in1==0);
assign LEZ=Sign?(in1[31]||EQZ):EQZ;
assign LTZ=Sign?(in1[31]):0;
assign GTZ=Sign?(~in1[31]):~EQZ;
assign S=(ALUFun[2]==0)?
(
(ALUFun[1]==0)?
((ALUFun[0]==0)?NEQ:EQ)
:
((ALUFun[0]==0)?LT:0)
)
:
(
(ALUFun[1]==0)?
((ALUFun[0]==0)?0:LTZ)
:
((ALUFun[0]==0)?LEZ:GTZ)
);
endmodule | module cmp(S,V,N,ALUFun,in1,in2,Sign); |
input V,N,Sign;
input [2:0] ALUFun;
input [31:0] in1,in2;
output [31:0] S;
wire EQ,NEQ,LT,LEZ,LTZ,GTZ;
assign EQ=in1==in2;
assign NEQ=~(in1==in2);
assign LT=(~V&N)|(V&in1[31]);
assign EQZ=(in1==0);
assign LEZ=Sign?(in1[31]||EQZ):EQZ;
assign LTZ=Sign?(in1[31]):0;
assign GTZ=Sign?(~in1[31]):~EQZ;
assign S=(ALUFun[2]==0)?
(
(ALUFun[1]==0)?
((ALUFun[0]==0)?NEQ:EQ)
:
((ALUFun[0]==0)?LT:0)
)
:
(
(ALUFun[1]==0)?
((ALUFun[0]==0)?0:LTZ)
:
((ALUFun[0]==0)?LEZ:GTZ)
);
endmodule | 0 |
142,299 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module logic(out,in1,in2,ALUFun);
output [31:0] out;
input [31:0] in1,in2;
input [3:0] ALUFun;
wire [31:0] _and,_or,_xor,_nor;
assign _and=in1&in2;
assign _or=in1|in2;
assign _xor=in1^in2;
assign _nor=~(in1|in2);
assign out=(ALUFun[3]==1)?(
(ALUFun[2]==1)?_or:(
(ALUFun[1]==1)?in1:_and))
:
((ALUFun[2]==1)?_xor:_nor);
endmodule | module logic(out,in1,in2,ALUFun); |
output [31:0] out;
input [31:0] in1,in2;
input [3:0] ALUFun;
wire [31:0] _and,_or,_xor,_nor;
assign _and=in1&in2;
assign _or=in1|in2;
assign _xor=in1^in2;
assign _nor=~(in1|in2);
assign out=(ALUFun[3]==1)?(
(ALUFun[2]==1)?_or:(
(ALUFun[1]==1)?in1:_and))
:
((ALUFun[2]==1)?_xor:_nor);
endmodule | 0 |
142,300 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _arshift1(out,in);
input [31:0] in;
output [31:0] out;
wire temp;
assign temp=(in[31]==1)?1'b1:1'b0;
assign out={temp,in[31:1]};
endmodule | module _arshift1(out,in); |
input [31:0] in;
output [31:0] out;
wire temp;
assign temp=(in[31]==1)?1'b1:1'b0;
assign out={temp,in[31:1]};
endmodule | 0 |
142,301 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _arshift2(out,in);
input [31:0] in;
output [31:0] out;
wire [1:0] temp;
assign temp=(in[31]==1)?2'b11:2'b00;
assign out={temp,in[31:2]};
endmodule | module _arshift2(out,in); |
input [31:0] in;
output [31:0] out;
wire [1:0] temp;
assign temp=(in[31]==1)?2'b11:2'b00;
assign out={temp,in[31:2]};
endmodule | 0 |
142,302 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _arshift4(out,in);
input [31:0] in;
output [31:0] out;
wire [3:0] temp;
assign temp=(in[31]==1)?4'b1111:4'b0000;
assign out={temp,in[31:4]};
endmodule | module _arshift4(out,in); |
input [31:0] in;
output [31:0] out;
wire [3:0] temp;
assign temp=(in[31]==1)?4'b1111:4'b0000;
assign out={temp,in[31:4]};
endmodule | 0 |
142,303 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _arshift8(out,in);
input [31:0] in;
output [31:0] out;
wire [7:0] temp;
assign temp=(in[31]==1)?8'hFF:8'h00;
assign out={temp,in[31:8]};
endmodule | module _arshift8(out,in); |
input [31:0] in;
output [31:0] out;
wire [7:0] temp;
assign temp=(in[31]==1)?8'hFF:8'h00;
assign out={temp,in[31:8]};
endmodule | 0 |
142,304 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _arshift16(out,in);
input [31:0] in;
output [31:0] out;
wire [15:0] temp;
assign temp=(in[31]==1)?16'hFFFF:16'h0000;
assign out={temp,in[31:16]};
endmodule | module _arshift16(out,in); |
input [31:0] in;
output [31:0] out;
wire [15:0] temp;
assign temp=(in[31]==1)?16'hFFFF:16'h0000;
assign out={temp,in[31:16]};
endmodule | 0 |
142,305 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module arshift(out,in,shamt);
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_arshift16 ar16(_out16,_in16);
_arshift8 ar8(_out8,_in8);
_arshift4 ar4(_out4,_in4);
_arshift2 ar2(_out2,_in2);
_arshift1 ar1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:((
shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | module arshift(out,in,shamt); |
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_arshift16 ar16(_out16,_in16);
_arshift8 ar8(_out8,_in8);
_arshift4 ar4(_out4,_in4);
_arshift2 ar2(_out2,_in2);
_arshift1 ar1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:((
shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | 0 |
142,306 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module rshift(out,in,shamt);
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_rshift16 r16(_out16,_in16);
_rshift8 r8(_out8,_in8);
_rshift4 r4(_out4,_in4);
_rshift2 r2(_out2,_in2);
_rshift1 r1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | module rshift(out,in,shamt); |
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_rshift16 r16(_out16,_in16);
_rshift8 r8(_out8,_in8);
_rshift4 r4(_out4,_in4);
_rshift2 r2(_out2,_in2);
_rshift1 r1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | 0 |
142,307 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module lshift(out,in,shamt);
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_lshift16 l16(_out16,_in16);
_lshift8 l8(_out8,_in8);
_lshift4 l4(_out4,_in4);
_lshift2 l2(_out2,_in2);
_lshift1 l1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | module lshift(out,in,shamt); |
output [31:0] out;
input [31:0] in;
input [4:0] shamt;
wire [31:0] _out1,_out2,_out4,_out8,_out16;
wire [31:0] _in1,_in2,_in4,_in8,_in16;
_lshift16 l16(_out16,_in16);
_lshift8 l8(_out8,_in8);
_lshift4 l4(_out4,_in4);
_lshift2 l2(_out2,_in2);
_lshift1 l1(_out1,_in1);
assign _in16=in;
assign _in8=(shamt[4]==1)?_out16:in;
assign _in4=(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in);
assign _in2=(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in));
assign _in1=(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in)));
assign out=(shamt[0]==1)?_out1:(
(shamt[1]==1)?_out2:(
(shamt[2]==1)?_out4:(
(shamt[3]==1)?_out8:(
(shamt[4]==1)?_out16:in))));
endmodule | 0 |
142,308 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module shift(out,in1,in2,ALUFun);
output [31:0] out;
input [31:0] in1,in2;
input [1:0] ALUFun;
wire [31:0] _arout,_rout,_lout;
arshift ar(.out(_arout),.in(in2),.shamt(in1[4:0]));
rshift r(.out(_rout),.in(in2),.shamt(in1[4:0]));
lshift l(.out(_lout),.in(in2),.shamt(in1[4:0]));
assign out=(ALUFun[1]==1)?_arout:(
(ALUFun[0]==1)?_rout:_lout);
endmodule | module shift(out,in1,in2,ALUFun); |
output [31:0] out;
input [31:0] in1,in2;
input [1:0] ALUFun;
wire [31:0] _arout,_rout,_lout;
arshift ar(.out(_arout),.in(in2),.shamt(in1[4:0]));
rshift r(.out(_rout),.in(in2),.shamt(in1[4:0]));
lshift l(.out(_lout),.in(in2),.shamt(in1[4:0]));
assign out=(ALUFun[1]==1)?_arout:(
(ALUFun[0]==1)?_rout:_lout);
endmodule | 0 |
142,309 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _rshift1(out,in);
input [31:0] in;
output [31:0] out;
assign out={1'b0,in[31:1]};
endmodule | module _rshift1(out,in); |
input [31:0] in;
output [31:0] out;
assign out={1'b0,in[31:1]};
endmodule | 0 |
142,310 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _rshift2(out,in);
input [31:0] in;
output [31:0] out;
assign out={2'b0,in[31:2]};
endmodule | module _rshift2(out,in); |
input [31:0] in;
output [31:0] out;
assign out={2'b0,in[31:2]};
endmodule | 0 |
142,311 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _rshift4(out,in);
input [31:0] in;
output [31:0] out;
assign out={4'b0,in[31:4]};
endmodule | module _rshift4(out,in); |
input [31:0] in;
output [31:0] out;
assign out={4'b0,in[31:4]};
endmodule | 0 |
142,312 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _rshift8(out,in);
input [31:0] in;
output [31:0] out;
assign out={8'b0,in[31:8]};
endmodule | module _rshift8(out,in); |
input [31:0] in;
output [31:0] out;
assign out={8'b0,in[31:8]};
endmodule | 0 |
142,313 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _rshift16(out,in);
input [31:0] in;
output [31:0] out;
assign out={16'b0,in[31:16]};
endmodule | module _rshift16(out,in); |
input [31:0] in;
output [31:0] out;
assign out={16'b0,in[31:16]};
endmodule | 0 |
142,314 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _lshift1(out,in);
input [31:0] in;
output [31:0] out;
assign out={in[30:0],1'b0};
endmodule | module _lshift1(out,in); |
input [31:0] in;
output [31:0] out;
assign out={in[30:0],1'b0};
endmodule | 0 |
142,315 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _lshift2(out,in);
input [31:0] in;
output [31:0] out;
assign out={in[29:0],2'b0};
endmodule | module _lshift2(out,in); |
input [31:0] in;
output [31:0] out;
assign out={in[29:0],2'b0};
endmodule | 0 |
142,316 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _lshift4(out,in);
input [31:0] in;
output [31:0] out;
assign out={in[27:0],4'b0};
endmodule | module _lshift4(out,in); |
input [31:0] in;
output [31:0] out;
assign out={in[27:0],4'b0};
endmodule | 0 |
142,317 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _lshift8(out,in);
input [31:0] in;
output [31:0] out;
assign out={in[23:0],8'b0};
endmodule | module _lshift8(out,in); |
input [31:0] in;
output [31:0] out;
assign out={in[23:0],8'b0};
endmodule | 0 |
142,318 | data/full_repos/permissive/98616431/ALU.v | 98,616,431 | ALU.v | v | 302 | 98 | [] | [] | [] | null | line:10: before: "(" | null | 1: b"%Error: data/full_repos/permissive/98616431/ALU.v:10: syntax error, unexpected '(', expecting ',' or ';'\nlogic lgc(.out(logic_out),.in1(in1),.in2(in2),.ALUFun(ALUFun[3:0]));\n ^\n%Error: data/full_repos/permissive/98616431/ALU.v:77: syntax error, unexpected logic, expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER\nmodule logic(out,in1,in2,ALUFun);\n ^~~~~\n%Error: data/full_repos/permissive/98616431/ALU.v:82: syntax error, unexpected assign\nassign _and=in1&in2;\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,802 | module | module _lshift16(out,in);
input [31:0] in;
output [31:0] out;
assign out={in[15:0],16'b0};
endmodule | module _lshift16(out,in); |
input [31:0] in;
output [31:0] out;
assign out={in[15:0],16'b0};
endmodule | 0 |
142,319 | data/full_repos/permissive/98616431/branch_compare.v | 98,616,431 | branch_compare.v | v | 12 | 70 | [] | [] | [] | [(1, 12)] | null | data/verilator_xmls/7e1e7552-a18d-4e7e-b098-46b3ea36ac4a.xml | null | 313,803 | module | module branch_compare(bcompare_out,ALUin1,ALUin2,ALUFunct_41);
output bcompare_out;
input [31:0] ALUin1,ALUin2;
input [3:0] ALUFunct_41;
assign bcompare_out=(ALUFunct_41==4'b1001)?ALUin1==ALUin2:
(ALUFunct_41==4'b1000)?ALUin1!=ALUin2:
(ALUFunct_41==4'b1110)?(ALUin1[31]==1||ALUin1[30:0]==0):
(ALUFunct_41==4'b1111)?(ALUin1[31]!=0&&ALUin1[30:0]>0):
ALUin1[31]==1;
endmodule | module branch_compare(bcompare_out,ALUin1,ALUin2,ALUFunct_41); |
output bcompare_out;
input [31:0] ALUin1,ALUin2;
input [3:0] ALUFunct_41;
assign bcompare_out=(ALUFunct_41==4'b1001)?ALUin1==ALUin2:
(ALUFunct_41==4'b1000)?ALUin1!=ALUin2:
(ALUFunct_41==4'b1110)?(ALUin1[31]==1||ALUin1[30:0]==0):
(ALUFunct_41==4'b1111)?(ALUin1[31]!=0&&ALUin1[30:0]>0):
ALUin1[31]==1;
endmodule | 0 |
142,320 | data/full_repos/permissive/98616431/Control.v | 98,616,431 | Control.v | v | 101 | 129 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | data/verilator_xmls/5a4b1649-1c1f-40a4-ac97-43ff1a8cddab.xml | null | 313,804 | module | module Control(Instruct, IRQ, PC_31,PCSrc, RegDst, RegWrite,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);
input [31:0]Instruct;
input IRQ,PC_31;
output [2:0]PCSrc;
output [1:0]RegDst;
output [1:0]MemToReg;
output [5:0]ALUFun;
output RegWrite,ALUSrc1, ALUSrc2, Sign, MemWr, MemRd,EXTOp, LUOp;
wire [5:0] OpCode;
assign OpCode = Instruct[31:26];
wire[5:0] Funct;
assign Funct = Instruct[5:0];
wire ill_operation,interuption;
assign ill_operation = ~(((OpCode == 6'h23) || (OpCode == 6'h2b) || (OpCode == 6'h0f) ||
(OpCode == 6'h08) || (OpCode == 6'h09) || (OpCode == 6'h0c) || (OpCode == 6'h20) ||
(OpCode == 6'h0a) || (OpCode == 6'h0b) || (OpCode == 6'h04) || (OpCode == 6'h05) ||
(OpCode == 6'h06) || (OpCode == 6'h07) || (OpCode == 6'h01) || (OpCode == 6'h02) ||
(OpCode == 6'h03) || ((OpCode == 6'h00) && ((Funct == 6'h00) || (Funct == 6'h02) ||
(Funct == 6'h03) || (Funct == 6'h22) || (Funct == 6'h23) || (Funct == 6'h08) ||
(Funct == 6'h09) || (Funct == 6'h20) || (Funct == 6'h21) || (Funct == 6'h24) ||
(Funct == 6'h25) || (Funct == 6'h26) || (Funct == 6'h27) || (Funct == 6'h2a) )))||PC_31);
assign interuption = (~PC_31)&&IRQ;
assign PCSrc[2:0]=
(interuption)?5:
(ill_operation)?4:
((OpCode == 6'h04)||(OpCode == 6'h05)||(OpCode == 6'h06)||(OpCode == 6'h07))?1:
((OpCode == 6'h02)||(OpCode == 6'h03))?2:
((OpCode == 6'h00)&&((Funct==6'h08)||(Funct==6'h09)))?3:
0;
assign RegDst[1:0] =
(ill_operation||interuption)?3:
(OpCode == 6'h03||(OpCode==0&&Funct==6'h09))?2:
(OpCode == 0)?0:
1;
assign RegWrite=
(ill_operation||interuption)?1:
((OpCode == 6'h2b)||(OpCode == 6'h04)||(OpCode == 6'h02)||(OpCode == 6'h06)||
(OpCode == 6'h05)||(OpCode == 6'h07)||(OpCode == 6'h01)||(Instruct == 0)||
((OpCode == 6'h00)&&(Funct==6'h08))||Instruct==0)?0:
1;
assign ALUSrc1 =
((OpCode == 0)&&((Funct == 0)||(Funct == 6'h02)||Funct == 6'h03))?1:
0;
assign ALUSrc2 =
(OpCode == 6'h00 || OpCode == 6'h04 || OpCode == 6'h05 ||
OpCode == 6'h06 || OpCode == 6'h07 || OpCode == 6'h01)?0:
1;
assign ALUFun =
((OpCode == 6'h25)||((OpCode == 0)&&(Funct == 6'h25)))?6'b011110:
((OpCode == 0)&&((Funct == 6'h22)||(Funct == 6'h23)))?6'b000001:
((OpCode == 6'h0c)||((OpCode == 0)&&(Funct == 6'h24)))?6'b011000:
((OpCode == 0)&&(Funct == 6'h26))?6'b010110:
((OpCode == 0)&&(Funct == 6'h27))?6'b010001:
((OpCode == 0)&&(Funct == 0))?6'b100000:
((OpCode == 0)&&(Funct == 6'h02))?6'b100001:
((OpCode == 0)&&(Funct == 6'h03))?6'b100011:
((OpCode == 6'h0a)||(OpCode == 6'h0b)||((OpCode == 0)&&(Funct == 6'h2a)))?6'b110101:
(OpCode == 6'h04)?6'b110011:
(OpCode == 6'h05)?6'b110001:
(OpCode == 6'h06)?6'b111101:
(OpCode == 6'h07)?6'b111111:
(OpCode == 6'h01)?6'b111011:
0;
assign Sign =
((OpCode == 6'h09 || OpCode == 6'h0b)||
(OpCode == 6'h00 && (Funct == 6'h23 || Funct == 6'h21)))? 0:
1;
assign MemRd =
(OpCode == 6'h23)?1:
0;
assign MemWr =
(OpCode == 6'h2b)?1:
0;
assign MemToReg =
(interuption||ill_operation)?2:
(OpCode == 6'h23)?1:
((OpCode == 6'h03)||((OpCode == 0)&&((Funct == 6'h08)||(Funct == 6'h09))))?2:
0;
assign EXTOp =
(OpCode == 6'h0c)? 0:
1;
assign LUOp =
(OpCode == 6'h0f)? 1:
0;
endmodule | module Control(Instruct, IRQ, PC_31,PCSrc, RegDst, RegWrite,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp); |
input [31:0]Instruct;
input IRQ,PC_31;
output [2:0]PCSrc;
output [1:0]RegDst;
output [1:0]MemToReg;
output [5:0]ALUFun;
output RegWrite,ALUSrc1, ALUSrc2, Sign, MemWr, MemRd,EXTOp, LUOp;
wire [5:0] OpCode;
assign OpCode = Instruct[31:26];
wire[5:0] Funct;
assign Funct = Instruct[5:0];
wire ill_operation,interuption;
assign ill_operation = ~(((OpCode == 6'h23) || (OpCode == 6'h2b) || (OpCode == 6'h0f) ||
(OpCode == 6'h08) || (OpCode == 6'h09) || (OpCode == 6'h0c) || (OpCode == 6'h20) ||
(OpCode == 6'h0a) || (OpCode == 6'h0b) || (OpCode == 6'h04) || (OpCode == 6'h05) ||
(OpCode == 6'h06) || (OpCode == 6'h07) || (OpCode == 6'h01) || (OpCode == 6'h02) ||
(OpCode == 6'h03) || ((OpCode == 6'h00) && ((Funct == 6'h00) || (Funct == 6'h02) ||
(Funct == 6'h03) || (Funct == 6'h22) || (Funct == 6'h23) || (Funct == 6'h08) ||
(Funct == 6'h09) || (Funct == 6'h20) || (Funct == 6'h21) || (Funct == 6'h24) ||
(Funct == 6'h25) || (Funct == 6'h26) || (Funct == 6'h27) || (Funct == 6'h2a) )))||PC_31);
assign interuption = (~PC_31)&&IRQ;
assign PCSrc[2:0]=
(interuption)?5:
(ill_operation)?4:
((OpCode == 6'h04)||(OpCode == 6'h05)||(OpCode == 6'h06)||(OpCode == 6'h07))?1:
((OpCode == 6'h02)||(OpCode == 6'h03))?2:
((OpCode == 6'h00)&&((Funct==6'h08)||(Funct==6'h09)))?3:
0;
assign RegDst[1:0] =
(ill_operation||interuption)?3:
(OpCode == 6'h03||(OpCode==0&&Funct==6'h09))?2:
(OpCode == 0)?0:
1;
assign RegWrite=
(ill_operation||interuption)?1:
((OpCode == 6'h2b)||(OpCode == 6'h04)||(OpCode == 6'h02)||(OpCode == 6'h06)||
(OpCode == 6'h05)||(OpCode == 6'h07)||(OpCode == 6'h01)||(Instruct == 0)||
((OpCode == 6'h00)&&(Funct==6'h08))||Instruct==0)?0:
1;
assign ALUSrc1 =
((OpCode == 0)&&((Funct == 0)||(Funct == 6'h02)||Funct == 6'h03))?1:
0;
assign ALUSrc2 =
(OpCode == 6'h00 || OpCode == 6'h04 || OpCode == 6'h05 ||
OpCode == 6'h06 || OpCode == 6'h07 || OpCode == 6'h01)?0:
1;
assign ALUFun =
((OpCode == 6'h25)||((OpCode == 0)&&(Funct == 6'h25)))?6'b011110:
((OpCode == 0)&&((Funct == 6'h22)||(Funct == 6'h23)))?6'b000001:
((OpCode == 6'h0c)||((OpCode == 0)&&(Funct == 6'h24)))?6'b011000:
((OpCode == 0)&&(Funct == 6'h26))?6'b010110:
((OpCode == 0)&&(Funct == 6'h27))?6'b010001:
((OpCode == 0)&&(Funct == 0))?6'b100000:
((OpCode == 0)&&(Funct == 6'h02))?6'b100001:
((OpCode == 0)&&(Funct == 6'h03))?6'b100011:
((OpCode == 6'h0a)||(OpCode == 6'h0b)||((OpCode == 0)&&(Funct == 6'h2a)))?6'b110101:
(OpCode == 6'h04)?6'b110011:
(OpCode == 6'h05)?6'b110001:
(OpCode == 6'h06)?6'b111101:
(OpCode == 6'h07)?6'b111111:
(OpCode == 6'h01)?6'b111011:
0;
assign Sign =
((OpCode == 6'h09 || OpCode == 6'h0b)||
(OpCode == 6'h00 && (Funct == 6'h23 || Funct == 6'h21)))? 0:
1;
assign MemRd =
(OpCode == 6'h23)?1:
0;
assign MemWr =
(OpCode == 6'h2b)?1:
0;
assign MemToReg =
(interuption||ill_operation)?2:
(OpCode == 6'h23)?1:
((OpCode == 6'h03)||((OpCode == 0)&&((Funct == 6'h08)||(Funct == 6'h09))))?2:
0;
assign EXTOp =
(OpCode == 6'h0c)? 0:
1;
assign LUOp =
(OpCode == 6'h0f)? 1:
0;
endmodule | 0 |
142,321 | data/full_repos/permissive/98616431/cpuclk.v | 98,616,431 | cpuclk.v | v | 27 | 42 | [] | [] | [] | [(1, 27)] | null | data/verilator_xmls/ea8c80b7-8679-41a1-ba69-e8b00daa6f72.xml | null | 313,805 | module | module cpuclk(clk,sysclk,reset);
output reg clk;
input sysclk,reset;
reg [6:0] s;
initial begin
s<=0;
clk<=0;
end
always @(posedge sysclk or negedge reset)
begin
if (~reset)
begin
s<=0;
clk<=0;
end
else begin
s<=s+1;
if(s==50)
begin
s<=0;
clk<=~clk;
end
end
end
endmodule | module cpuclk(clk,sysclk,reset); |
output reg clk;
input sysclk,reset;
reg [6:0] s;
initial begin
s<=0;
clk<=0;
end
always @(posedge sysclk or negedge reset)
begin
if (~reset)
begin
s<=0;
clk<=0;
end
else begin
s<=s+1;
if(s==50)
begin
s<=0;
clk<=~clk;
end
end
end
endmodule | 0 |
142,322 | data/full_repos/permissive/98616431/cpu_clk_tb.v | 98,616,431 | cpu_clk_tb.v | v | 9 | 29 | [] | [] | [] | [(1, 8)] | null | null | 1: b'%Error: data/full_repos/permissive/98616431/cpu_clk_tb.v:4: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98616431/cpu_clk_tb.v:6: Unsupported: Ignoring delay on this delayed statement.\nforever #2 sysclk<=~sysclk;\n ^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 error(s), 1 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,806 | module | module cpu_clk_tb;
reg sysclk;
cpuclk U_cpuclk(clk,sysclk);
initial fork
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | module cpu_clk_tb; |
reg sysclk;
cpuclk U_cpuclk(clk,sysclk);
initial fork
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | 0 |
142,323 | data/full_repos/permissive/98616431/EX_MEM_Register.v | 98,616,431 | EX_MEM_Register.v | v | 85 | 129 | [] | [] | [] | [(1, 85)] | null | data/verilator_xmls/06d3156e-3331-470a-9e4c-afa3529ca771.xml | null | 313,808 | module | module EX_MEM_Register (clk, FORWARD, PCSrc_in, RegWr_in,
MemWr_in, MemRd_in, MemToReg_in,
NewPC_in, PC4_in , ALUResult_in, RegToMemData_in, RdAdress_in,
PCadd4, PC4_ID, Flushed_out_ID, Flushed_out_EX,
PCSrc_out, RegWr_out, MemWr_out, MemRd_out, MemToReg_out,
NewPC_out, PC4_out ,ALUResult_out, RegToMemData_out, RdAdress_out, reset,PCSrc_ID);
input clk,reset;
input [2:0] PCSrc_ID;
input FORWARD,Flushed_out_ID, Flushed_out_EX;
input [2:0] PCSrc_in;
input RegWr_in, MemWr_in,MemRd_in;
input [1:0] MemToReg_in;
input [31:0] NewPC_in, ALUResult_in, RegToMemData_in, PC4_in ;
input [4:0] RdAdress_in;
output [2:0] PCSrc_out;
output RegWr_out, MemWr_out,MemRd_out;
output [1:0] MemToReg_out;
input [31:0] PCadd4, PC4_ID;
output [31:0] NewPC_out, ALUResult_out, RegToMemData_out, PC4_out;
output [4:0] RdAdress_out;
reg [2:0] PCSrc_reg;
reg RegWr_reg, MemWr_reg,MemRd_reg;
reg [1:0] MemToReg_reg;
reg [31:0] NewPC_reg, ALUResult_reg, RegToMemData_reg, PC4_reg;
reg [4:0] RdAdress_reg;
always @(posedge clk or negedge reset) begin
if(~reset) begin
PCSrc_reg = 0;
RegWr_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 0;
NewPC_reg = 32'h80000004;
PC4_reg = 32'h80000004;
ALUResult_reg = 0;
RegToMemData_reg = 0;
RdAdress_reg = 0;
end
else begin
if (FORWARD) begin
RegWr_reg = 1;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 2;
PC4_reg = (PC4_in[31]||Flushed_out_EX)?((PC4_ID[31]||Flushed_out_ID)?PCadd4:PC4_ID):PC4_in;
RdAdress_reg = 26;
end
else begin
RegWr_reg = RegWr_in;
MemWr_reg = MemWr_in;
MemRd_reg = MemRd_in;
MemToReg_reg = MemToReg_in;
PC4_reg = PC4_in;
RdAdress_reg = RdAdress_in;
end
PCSrc_reg = PCSrc_ID;
NewPC_reg = NewPC_in;
ALUResult_reg = ALUResult_in;
RegToMemData_reg = RegToMemData_in;
end
end
assign PCSrc_out = PCSrc_reg;
assign RegWr_out = RegWr_reg;
assign MemWr_out = MemWr_reg;
assign MemRd_out = MemRd_reg;
assign MemToReg_out = MemToReg_reg;
assign NewPC_out = NewPC_reg;
assign PC4_out = PC4_reg;
assign ALUResult_out = ALUResult_reg;
assign RegToMemData_out = RegToMemData_reg;
assign RdAdress_out = RdAdress_reg;
endmodule | module EX_MEM_Register (clk, FORWARD, PCSrc_in, RegWr_in,
MemWr_in, MemRd_in, MemToReg_in,
NewPC_in, PC4_in , ALUResult_in, RegToMemData_in, RdAdress_in,
PCadd4, PC4_ID, Flushed_out_ID, Flushed_out_EX,
PCSrc_out, RegWr_out, MemWr_out, MemRd_out, MemToReg_out,
NewPC_out, PC4_out ,ALUResult_out, RegToMemData_out, RdAdress_out, reset,PCSrc_ID); |
input clk,reset;
input [2:0] PCSrc_ID;
input FORWARD,Flushed_out_ID, Flushed_out_EX;
input [2:0] PCSrc_in;
input RegWr_in, MemWr_in,MemRd_in;
input [1:0] MemToReg_in;
input [31:0] NewPC_in, ALUResult_in, RegToMemData_in, PC4_in ;
input [4:0] RdAdress_in;
output [2:0] PCSrc_out;
output RegWr_out, MemWr_out,MemRd_out;
output [1:0] MemToReg_out;
input [31:0] PCadd4, PC4_ID;
output [31:0] NewPC_out, ALUResult_out, RegToMemData_out, PC4_out;
output [4:0] RdAdress_out;
reg [2:0] PCSrc_reg;
reg RegWr_reg, MemWr_reg,MemRd_reg;
reg [1:0] MemToReg_reg;
reg [31:0] NewPC_reg, ALUResult_reg, RegToMemData_reg, PC4_reg;
reg [4:0] RdAdress_reg;
always @(posedge clk or negedge reset) begin
if(~reset) begin
PCSrc_reg = 0;
RegWr_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 0;
NewPC_reg = 32'h80000004;
PC4_reg = 32'h80000004;
ALUResult_reg = 0;
RegToMemData_reg = 0;
RdAdress_reg = 0;
end
else begin
if (FORWARD) begin
RegWr_reg = 1;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 2;
PC4_reg = (PC4_in[31]||Flushed_out_EX)?((PC4_ID[31]||Flushed_out_ID)?PCadd4:PC4_ID):PC4_in;
RdAdress_reg = 26;
end
else begin
RegWr_reg = RegWr_in;
MemWr_reg = MemWr_in;
MemRd_reg = MemRd_in;
MemToReg_reg = MemToReg_in;
PC4_reg = PC4_in;
RdAdress_reg = RdAdress_in;
end
PCSrc_reg = PCSrc_ID;
NewPC_reg = NewPC_in;
ALUResult_reg = ALUResult_in;
RegToMemData_reg = RegToMemData_in;
end
end
assign PCSrc_out = PCSrc_reg;
assign RegWr_out = RegWr_reg;
assign MemWr_out = MemWr_reg;
assign MemRd_out = MemRd_reg;
assign MemToReg_out = MemToReg_reg;
assign NewPC_out = NewPC_reg;
assign PC4_out = PC4_reg;
assign ALUResult_out = ALUResult_reg;
assign RegToMemData_out = RegToMemData_reg;
assign RdAdress_out = RdAdress_reg;
endmodule | 0 |
142,324 | data/full_repos/permissive/98616431/Forward.v | 98,616,431 | Forward.v | v | 36 | 99 | [] | [] | [] | [(1, 36)] | null | data/verilator_xmls/8fb4a10f-a9c1-40f0-9774-26725ecd952c.xml | null | 313,809 | module | module forward(ForwardA,ForwardB,EX_MEM_RegWr,MEM_WB_RegWr,EX_MEM_Rd,MEM_WB_Rd,ID_EX_Rs,ID_EX_Rt);
input EX_MEM_RegWr,MEM_WB_RegWr;
input [4:0] EX_MEM_Rd, ID_EX_Rs,ID_EX_Rt,MEM_WB_Rd;
output [1:0] ForwardA,ForwardB;
assign ForwardA = (EX_MEM_RegWr&&EX_MEM_Rd!=0&&EX_MEM_Rd==ID_EX_Rs)?2'b10:
(MEM_WB_RegWr&&MEM_WB_Rd!=0&&MEM_WB_Rd==ID_EX_Rs)?2'b01:
2'b00;
assign ForwardB = (EX_MEM_RegWr&&EX_MEM_Rd!=0&&EX_MEM_Rd==ID_EX_Rt)?2'b10:
(MEM_WB_RegWr&&MEM_WB_Rd!=0&&MEM_WB_Rd==ID_EX_Rt)?2'b01:
2'b00;
endmodule | module forward(ForwardA,ForwardB,EX_MEM_RegWr,MEM_WB_RegWr,EX_MEM_Rd,MEM_WB_Rd,ID_EX_Rs,ID_EX_Rt); |
input EX_MEM_RegWr,MEM_WB_RegWr;
input [4:0] EX_MEM_Rd, ID_EX_Rs,ID_EX_Rt,MEM_WB_Rd;
output [1:0] ForwardA,ForwardB;
assign ForwardA = (EX_MEM_RegWr&&EX_MEM_Rd!=0&&EX_MEM_Rd==ID_EX_Rs)?2'b10:
(MEM_WB_RegWr&&MEM_WB_Rd!=0&&MEM_WB_Rd==ID_EX_Rs)?2'b01:
2'b00;
assign ForwardB = (EX_MEM_RegWr&&EX_MEM_Rd!=0&&EX_MEM_Rd==ID_EX_Rt)?2'b10:
(MEM_WB_RegWr&&MEM_WB_Rd!=0&&MEM_WB_Rd==ID_EX_Rt)?2'b01:
2'b00;
endmodule | 0 |
142,325 | data/full_repos/permissive/98616431/Generator.v | 98,616,431 | Generator.v | v | 21 | 36 | [] | [] | [] | [(2, 21)] | null | data/verilator_xmls/846d6fe4-b30b-491e-8b88-1b4e16e806b9.xml | null | 313,810 | module | module Generator(clk,baudrate_clk);
input clk;
output baudrate_clk;
reg baud_clk;
reg [8:0] baud_count;
assign baudrate_clk = baud_clk;
initial begin
baud_clk <= 0;
baud_count <= 0;
end
always @(posedge clk) begin
if (baud_count == 325) begin
baud_count <= 0;
baud_clk <= ~baud_clk;
end
else begin
baud_count <= baud_count + 1;
end
end
endmodule | module Generator(clk,baudrate_clk); |
input clk;
output baudrate_clk;
reg baud_clk;
reg [8:0] baud_count;
assign baudrate_clk = baud_clk;
initial begin
baud_clk <= 0;
baud_count <= 0;
end
always @(posedge clk) begin
if (baud_count == 325) begin
baud_count <= 0;
baud_clk <= ~baud_clk;
end
else begin
baud_count <= baud_count + 1;
end
end
endmodule | 0 |
142,326 | data/full_repos/permissive/98616431/Hazard_Detection.v | 98,616,431 | Hazard_Detection.v | v | 22 | 162 | [] | [] | [] | null | 'utf-8' codec can't decode bytes in position 214-215: invalid continuation byte | data/verilator_xmls/96425ff8-f455-483f-a5c8-ba2f6b36596c.xml | null | 313,811 | module | module HazardDetection(EX_PCSrc, ALUOut_0, ID_PCSrc, ID_EX_MEMRd, ID_EX_Rt,IF_ID_Rs,IF_ID_Rt, bubble,ID_EX_Flush,IF_ID_Flush,EX_MEM_FORWARD);
input ID_EX_MEMRd;
input [2:0] EX_PCSrc, ID_PCSrc;
input ALUOut_0;
input [4:0] ID_EX_Rt,IF_ID_Rs,IF_ID_Rt;
output bubble,ID_EX_Flush,IF_ID_Flush,EX_MEM_FORWARD;
wire jIF_ID_Flush,bIF_ID_Flush,bID_EX_Flush,jrIF_ID_Flush,jrID_EX_Flush;
wire int_expt_Flush;
assign int_expt_Flush = ID_PCSrc==4||ID_PCSrc==5;
assign bubble = (~ID_EX_Flush || ~IF_ID_Flush) && ID_EX_MEMRd && ((ID_EX_Rt==IF_ID_Rs && ID_EX_Rt!=0) || ((ID_EX_Rt==IF_ID_Rt)&&(ID_EX_Rt!=0)));
assign bID_EX_Flush = (EX_PCSrc==3'b001) && (ALUOut_0==1);
assign jIF_ID_Flush = ID_PCSrc==3'b010;
assign jrIF_ID_Flush = EX_PCSrc==3'b011;
assign jrID_EX_Flush = jrIF_ID_Flush;
assign IF_ID_Flush = jIF_ID_Flush|jrIF_ID_Flush|bIF_ID_Flush|int_expt_Flush;
assign bIF_ID_Flush = bID_EX_Flush;
assign ID_EX_Flush = bID_EX_Flush|jrID_EX_Flush|int_expt_Flush;
assign EX_MEM_FORWARD =int_expt_Flush;
endmodule | module HazardDetection(EX_PCSrc, ALUOut_0, ID_PCSrc, ID_EX_MEMRd, ID_EX_Rt,IF_ID_Rs,IF_ID_Rt, bubble,ID_EX_Flush,IF_ID_Flush,EX_MEM_FORWARD); |
input ID_EX_MEMRd;
input [2:0] EX_PCSrc, ID_PCSrc;
input ALUOut_0;
input [4:0] ID_EX_Rt,IF_ID_Rs,IF_ID_Rt;
output bubble,ID_EX_Flush,IF_ID_Flush,EX_MEM_FORWARD;
wire jIF_ID_Flush,bIF_ID_Flush,bID_EX_Flush,jrIF_ID_Flush,jrID_EX_Flush;
wire int_expt_Flush;
assign int_expt_Flush = ID_PCSrc==4||ID_PCSrc==5;
assign bubble = (~ID_EX_Flush || ~IF_ID_Flush) && ID_EX_MEMRd && ((ID_EX_Rt==IF_ID_Rs && ID_EX_Rt!=0) || ((ID_EX_Rt==IF_ID_Rt)&&(ID_EX_Rt!=0)));
assign bID_EX_Flush = (EX_PCSrc==3'b001) && (ALUOut_0==1);
assign jIF_ID_Flush = ID_PCSrc==3'b010;
assign jrIF_ID_Flush = EX_PCSrc==3'b011;
assign jrID_EX_Flush = jrIF_ID_Flush;
assign IF_ID_Flush = jIF_ID_Flush|jrIF_ID_Flush|bIF_ID_Flush|int_expt_Flush;
assign bIF_ID_Flush = bID_EX_Flush;
assign ID_EX_Flush = bID_EX_Flush|jrID_EX_Flush|int_expt_Flush;
assign EX_MEM_FORWARD =int_expt_Flush;
endmodule | 0 |
142,327 | data/full_repos/permissive/98616431/ID_EX_Register.v | 98,616,431 | ID_EX_Register.v | v | 112 | 94 | [] | [] | [] | [(1, 112)] | null | data/verilator_xmls/6b6ec717-f290-44cb-b65b-f15c8c10ad22.xml | null | 313,812 | module | module ID_EX_Register (clk, Flush, PCSrc_in, RegDst_in, RegWr_in, ALUSrc1_in, ALUSrc2_in,
ALUFun_in, Sign_in, MemWr_in, MemRd_in, MemToReg_in,
PC4_in, R1_in, R2_in, Imm_in, RdAdress_in, Shamt_in,Instruction_in,Flushed_in,
PCSrc_out, RegDst_out, RegWr_out, ALUSrc1_out, ALUSrc2_out,
ALUFun_out, Sign_out, MemWr_out, MemRd_out, MemToReg_out,
PC4_out, R1_out, R2_out, Imm_out, RdAdress_out, Shamt_out,Instruction_out,reset,Flushed_out);
input clk,Flush;
input reset,Flushed_in;
input [2:0] PCSrc_in;
input [1:0] RegDst_in;
input RegWr_in, ALUSrc1_in, ALUSrc2_in, Sign_in, MemWr_in,MemRd_in;
input [5:0] ALUFun_in;
input [1:0] MemToReg_in;
input [31:0] PC4_in, R1_in, R2_in, Imm_in,Instruction_in;
input [4:0] RdAdress_in,Shamt_in;
output [2:0] PCSrc_out;
output [1:0] RegDst_out;
output RegWr_out, ALUSrc1_out, ALUSrc2_out, Sign_out, MemWr_out,MemRd_out,Flushed_out;
output [5:0] ALUFun_out;
output [1:0] MemToReg_out;
output [31:0] PC4_out, R1_out, R2_out, Imm_out,Instruction_out;
output [4:0] RdAdress_out,Shamt_out;
reg [2:0] PCSrc_reg;
reg [1:0] RegDst_reg;
reg RegWr_reg, ALUSrc1_reg, ALUSrc2_reg, Sign_reg, MemWr_reg,MemRd_reg,Flushed_reg;
reg [5:0] ALUFun_reg;
reg [1:0] MemToReg_reg;
reg [31:0] PC4_reg, R1_reg, R2_reg, Imm_reg,Instruction_reg;
reg [4:0] RdAdress_reg, Shamt_reg;
always @(posedge clk or negedge reset) begin
if (~reset)
begin
PCSrc_reg = 0;
RegDst_reg = 0;
RegWr_reg = 0;
ALUSrc1_reg = 0;
ALUSrc2_reg = 0;
ALUFun_reg = 0;
Sign_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 0;
PC4_reg = 32'h80000004;
R1_reg = 0;
R2_reg = 0;
Imm_reg = 0;
RdAdress_reg = 0;
Shamt_reg = 0;
Instruction_reg = 0;
Flushed_reg = 0;
end
else begin
if(Flush) begin
PCSrc_reg = 0;
RegWr_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
PC4_reg = PC4_in;
Flushed_reg = 1;
end
else begin
PCSrc_reg = PCSrc_in;
RegWr_reg = RegWr_in;
MemWr_reg = MemWr_in;
MemRd_reg = MemRd_in;
PC4_reg = PC4_in;
Flushed_reg = Flushed_in;
end
RegDst_reg = RegDst_in;
ALUSrc1_reg = ALUSrc1_in;
ALUSrc2_reg = ALUSrc2_in;
ALUFun_reg = ALUFun_in;
Sign_reg = Sign_in;
MemToReg_reg = MemToReg_in;
R1_reg = R1_in;
R2_reg = R2_in;
Imm_reg = Imm_in;
RdAdress_reg = RdAdress_in;
Shamt_reg = Shamt_in;
Instruction_reg = Instruction_in;
end
end
assign PCSrc_out = PCSrc_reg;
assign RegDst_out = RegDst_reg;
assign RegWr_out = RegWr_reg;
assign ALUSrc1_out = ALUSrc1_reg;
assign ALUSrc2_out = ALUSrc2_reg;
assign ALUFun_out = ALUFun_reg;
assign Sign_out = Sign_reg;
assign MemWr_out = MemWr_reg;
assign MemRd_out = MemRd_reg;
assign MemToReg_out = MemToReg_reg;
assign PC4_out = PC4_reg;
assign R1_out = R1_reg;
assign R2_out = R2_reg;
assign Imm_out = Imm_reg;
assign RdAdress_out = RdAdress_reg;
assign Shamt_out = Shamt_reg;
assign Instruction_out = Instruction_reg;
assign Flushed_out = Flushed_reg;
endmodule | module ID_EX_Register (clk, Flush, PCSrc_in, RegDst_in, RegWr_in, ALUSrc1_in, ALUSrc2_in,
ALUFun_in, Sign_in, MemWr_in, MemRd_in, MemToReg_in,
PC4_in, R1_in, R2_in, Imm_in, RdAdress_in, Shamt_in,Instruction_in,Flushed_in,
PCSrc_out, RegDst_out, RegWr_out, ALUSrc1_out, ALUSrc2_out,
ALUFun_out, Sign_out, MemWr_out, MemRd_out, MemToReg_out,
PC4_out, R1_out, R2_out, Imm_out, RdAdress_out, Shamt_out,Instruction_out,reset,Flushed_out); |
input clk,Flush;
input reset,Flushed_in;
input [2:0] PCSrc_in;
input [1:0] RegDst_in;
input RegWr_in, ALUSrc1_in, ALUSrc2_in, Sign_in, MemWr_in,MemRd_in;
input [5:0] ALUFun_in;
input [1:0] MemToReg_in;
input [31:0] PC4_in, R1_in, R2_in, Imm_in,Instruction_in;
input [4:0] RdAdress_in,Shamt_in;
output [2:0] PCSrc_out;
output [1:0] RegDst_out;
output RegWr_out, ALUSrc1_out, ALUSrc2_out, Sign_out, MemWr_out,MemRd_out,Flushed_out;
output [5:0] ALUFun_out;
output [1:0] MemToReg_out;
output [31:0] PC4_out, R1_out, R2_out, Imm_out,Instruction_out;
output [4:0] RdAdress_out,Shamt_out;
reg [2:0] PCSrc_reg;
reg [1:0] RegDst_reg;
reg RegWr_reg, ALUSrc1_reg, ALUSrc2_reg, Sign_reg, MemWr_reg,MemRd_reg,Flushed_reg;
reg [5:0] ALUFun_reg;
reg [1:0] MemToReg_reg;
reg [31:0] PC4_reg, R1_reg, R2_reg, Imm_reg,Instruction_reg;
reg [4:0] RdAdress_reg, Shamt_reg;
always @(posedge clk or negedge reset) begin
if (~reset)
begin
PCSrc_reg = 0;
RegDst_reg = 0;
RegWr_reg = 0;
ALUSrc1_reg = 0;
ALUSrc2_reg = 0;
ALUFun_reg = 0;
Sign_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
MemToReg_reg = 0;
PC4_reg = 32'h80000004;
R1_reg = 0;
R2_reg = 0;
Imm_reg = 0;
RdAdress_reg = 0;
Shamt_reg = 0;
Instruction_reg = 0;
Flushed_reg = 0;
end
else begin
if(Flush) begin
PCSrc_reg = 0;
RegWr_reg = 0;
MemWr_reg = 0;
MemRd_reg = 0;
PC4_reg = PC4_in;
Flushed_reg = 1;
end
else begin
PCSrc_reg = PCSrc_in;
RegWr_reg = RegWr_in;
MemWr_reg = MemWr_in;
MemRd_reg = MemRd_in;
PC4_reg = PC4_in;
Flushed_reg = Flushed_in;
end
RegDst_reg = RegDst_in;
ALUSrc1_reg = ALUSrc1_in;
ALUSrc2_reg = ALUSrc2_in;
ALUFun_reg = ALUFun_in;
Sign_reg = Sign_in;
MemToReg_reg = MemToReg_in;
R1_reg = R1_in;
R2_reg = R2_in;
Imm_reg = Imm_in;
RdAdress_reg = RdAdress_in;
Shamt_reg = Shamt_in;
Instruction_reg = Instruction_in;
end
end
assign PCSrc_out = PCSrc_reg;
assign RegDst_out = RegDst_reg;
assign RegWr_out = RegWr_reg;
assign ALUSrc1_out = ALUSrc1_reg;
assign ALUSrc2_out = ALUSrc2_reg;
assign ALUFun_out = ALUFun_reg;
assign Sign_out = Sign_reg;
assign MemWr_out = MemWr_reg;
assign MemRd_out = MemRd_reg;
assign MemToReg_out = MemToReg_reg;
assign PC4_out = PC4_reg;
assign R1_out = R1_reg;
assign R2_out = R2_reg;
assign Imm_out = Imm_reg;
assign RdAdress_out = RdAdress_reg;
assign Shamt_out = Shamt_reg;
assign Instruction_out = Instruction_reg;
assign Flushed_out = Flushed_reg;
endmodule | 0 |
142,328 | data/full_repos/permissive/98616431/IF_ID_Register.v | 98,616,431 | IF_ID_Register.v | v | 32 | 115 | [] | [] | [] | [(1, 32)] | null | data/verilator_xmls/85c440d0-9964-46e3-b4b8-ff80f46e75df.xml | null | 313,813 | module | module IF_ID_Register(clk, Flush, Instruction_in, PC4_in, Instruction_out, PC4_out,reset, IRQ, PC31, Flushed_out);
input [31:0] Instruction_in, PC4_in;
input Flush, clk;
input reset;
input IRQ, PC31;
output Flushed_out;
output [31:0] Instruction_out, PC4_out;
reg [31:0] Instruction_reg, PC4_reg;
reg Flushed_reg;
always @(posedge clk or negedge reset) begin
if (~reset) begin
Instruction_reg = 0;
PC4_reg = 32'h80000004;
Flushed_reg = 0;
end
else begin
PC4_reg[30:0] = PC4_in[30:0];
PC4_reg[31] = PC31?PC4_in[31]:IRQ?1:PC4_in[31];
if(Flush) begin
Instruction_reg = 0;
Flushed_reg = 1;
end
else begin
Instruction_reg = Instruction_in;
Flushed_reg = 0;
end
end
end
assign Instruction_out = Instruction_reg;
assign PC4_out = PC4_reg;
assign Flushed_out = Flushed_reg;
endmodule | module IF_ID_Register(clk, Flush, Instruction_in, PC4_in, Instruction_out, PC4_out,reset, IRQ, PC31, Flushed_out); |
input [31:0] Instruction_in, PC4_in;
input Flush, clk;
input reset;
input IRQ, PC31;
output Flushed_out;
output [31:0] Instruction_out, PC4_out;
reg [31:0] Instruction_reg, PC4_reg;
reg Flushed_reg;
always @(posedge clk or negedge reset) begin
if (~reset) begin
Instruction_reg = 0;
PC4_reg = 32'h80000004;
Flushed_reg = 0;
end
else begin
PC4_reg[30:0] = PC4_in[30:0];
PC4_reg[31] = PC31?PC4_in[31]:IRQ?1:PC4_in[31];
if(Flush) begin
Instruction_reg = 0;
Flushed_reg = 1;
end
else begin
Instruction_reg = Instruction_in;
Flushed_reg = 0;
end
end
end
assign Instruction_out = Instruction_reg;
assign PC4_out = PC4_reg;
assign Flushed_out = Flushed_reg;
endmodule | 0 |
142,329 | data/full_repos/permissive/98616431/MEM_WB_Register.v | 98,616,431 | MEM_WB_Register.v | v | 64 | 78 | [] | [] | [] | [(1, 64)] | null | data/verilator_xmls/9bd895e7-4c89-4ec8-b626-72f5031fd1be.xml | null | 313,814 | module | module MEM_WB_Register (clk, RegWr_in,
MemToReg_in, PC4_in,
Data_in, ALUResult_in, RdAdress_in,
RegWr_out, MemToReg_out, PC4_out,
Data_out, ALUResult_out, RdAdress_out,
peri_rddata, uart_data, peri_rddata_WB, uart_data_WB, reset);
input clk, reset;
input RegWr_in;
input [1:0] MemToReg_in;
input [31:0] PC4_in, Data_in, ALUResult_in, peri_rddata, uart_data;
input [4:0] RdAdress_in;
output RegWr_out;
output [1:0] MemToReg_out;
output [31:0] PC4_out, Data_out, ALUResult_out, peri_rddata_WB, uart_data_WB;
output [4:0] RdAdress_out;
reg RegWr_reg;
reg [1:0] MemToReg_reg;
reg [31:0] PC4_reg, Data_reg, ALUResult_reg, peri_rddata_reg, uart_data_reg;
reg [4:0] RdAdress_reg;
always @(posedge clk or negedge reset) begin
if(~reset) begin
RegWr_reg = 0;
MemToReg_reg = 0;
Data_reg = 0;
ALUResult_reg = 0;
RdAdress_reg = 0;
peri_rddata_reg = 0;
uart_data_reg = 0;
PC4_reg = PC4_in;
end
else begin
RegWr_reg = RegWr_in;
MemToReg_reg = MemToReg_in;
Data_reg = Data_in;
ALUResult_reg = ALUResult_in;
RdAdress_reg = RdAdress_in;
peri_rddata_reg = peri_rddata;
uart_data_reg = uart_data;
PC4_reg = PC4_in;
end
end
assign RegWr_out = RegWr_reg;
assign MemToReg_out = MemToReg_reg;
assign Data_out = Data_reg;
assign ALUResult_out = ALUResult_reg;
assign RdAdress_out = RdAdress_reg;
assign peri_rddata_WB = peri_rddata_reg;
assign uart_data_WB = uart_data_reg;
assign PC4_out = PC4_reg;
endmodule | module MEM_WB_Register (clk, RegWr_in,
MemToReg_in, PC4_in,
Data_in, ALUResult_in, RdAdress_in,
RegWr_out, MemToReg_out, PC4_out,
Data_out, ALUResult_out, RdAdress_out,
peri_rddata, uart_data, peri_rddata_WB, uart_data_WB, reset); |
input clk, reset;
input RegWr_in;
input [1:0] MemToReg_in;
input [31:0] PC4_in, Data_in, ALUResult_in, peri_rddata, uart_data;
input [4:0] RdAdress_in;
output RegWr_out;
output [1:0] MemToReg_out;
output [31:0] PC4_out, Data_out, ALUResult_out, peri_rddata_WB, uart_data_WB;
output [4:0] RdAdress_out;
reg RegWr_reg;
reg [1:0] MemToReg_reg;
reg [31:0] PC4_reg, Data_reg, ALUResult_reg, peri_rddata_reg, uart_data_reg;
reg [4:0] RdAdress_reg;
always @(posedge clk or negedge reset) begin
if(~reset) begin
RegWr_reg = 0;
MemToReg_reg = 0;
Data_reg = 0;
ALUResult_reg = 0;
RdAdress_reg = 0;
peri_rddata_reg = 0;
uart_data_reg = 0;
PC4_reg = PC4_in;
end
else begin
RegWr_reg = RegWr_in;
MemToReg_reg = MemToReg_in;
Data_reg = Data_in;
ALUResult_reg = ALUResult_in;
RdAdress_reg = RdAdress_in;
peri_rddata_reg = peri_rddata;
uart_data_reg = uart_data;
PC4_reg = PC4_in;
end
end
assign RegWr_out = RegWr_reg;
assign MemToReg_out = MemToReg_reg;
assign Data_out = Data_reg;
assign ALUResult_out = ALUResult_reg;
assign RdAdress_out = RdAdress_reg;
assign peri_rddata_WB = peri_rddata_reg;
assign uart_data_WB = uart_data_reg;
assign PC4_out = PC4_reg;
endmodule | 0 |
142,330 | data/full_repos/permissive/98616431/Muti_cycle.v | 98,616,431 | Muti_cycle.v | v | 155 | 174 | [] | [] | [] | null | 'utf-8' codec can't decode bytes in position 1861-1862: invalid continuation byte | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/98616431/Muti_cycle.v:35: Signal definition not found, creating implicitly: \'clk\'\nassign clk = sysclk; \n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-WIDTH: data/full_repos/permissive/98616431/Muti_cycle.v:28: Operator ASSIGNW expects 10 bits on the Assign RHS, but Assign RHS\'s SEL generates 8 bits.\n : ... In instance Muti_cycle\nassign watchdog = PC[9:2]; \n ^\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:38: Cannot find file containing module: \'ROM5\'\nROM5 U_rom(PC[30:0],Instruct);\n^~~~\n ... Looked in:\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/ROM5\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/ROM5.v\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/ROM5.sv\n ROM5\n ROM5.v\n ROM5.sv\n obj_dir/ROM5\n obj_dir/ROM5.v\n obj_dir/ROM5.sv\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:45: Cannot find file containing module: \'IF_ID_Register\'\nIF_ID_Register U_IF_ID_Register(clk, IF_ID_Flush0, Instruct, PCadd4, Instruction_ID, PC4_ID,reset,IRQ_sync, PC4_ID[31],Flushed_out_ID);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:69: Cannot find file containing module: \'Control\'\nControl U_control(Instruction_ID, IRQ_sync, PC4_ID[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);\n^~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:85: Cannot find file containing module: \'RegFile\'\nRegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr_WB,RdAdress_WB,DataBusC);\n^~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:94: Cannot find file containing module: \'ID_EX_Register\'\nID_EX_Register U_ID_EX_Register(clk, ID_EX_Flush, PCSrc, RegDst, RegWr, ALUSrc1, ALUSrc2,\n^~~~~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/98616431/Muti_cycle.v:111: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Shamt_EX\' generates 5 bits.\n : ... In instance Muti_cycle\nassign ALUIn1=ALUSrc1_EX?Shamt_EX:DataBusA_Forwarded;\n ^\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:113: Cannot find file containing module: \'branch_compare\'\nbranch_compare U_branch_compare(bcomp,ALUIn1,ALUIn2,ALUFun_EX[4:1]);\n^~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:114: Cannot find file containing module: \'ALU\'\nALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun_EX,Sign_EX);\n^~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:118: Cannot find file containing module: \'EX_MEM_Register\'\nEX_MEM_Register U_EX_MEM_Register(clk, EX_MEM_FORWARD,PCSrc_EX, RegWr_EX,\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:130: Cannot find file containing module: \'DataMem\'\nDataMem U_mem(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,mem_rddata);\n^~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:131: Cannot find file containing module: \'Peripheral\'\nPeripheral U_peripheral(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,peri_rddata,led,switch,digi,irqout);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:132: Cannot find file containing module: \'Uart\'\nUart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd_MEM, MemWr_MEM, ALUOut_MEM, RegToMemData_MEM, uart_data, rx_irq, tx_irq);\n^~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:134: Cannot find file containing module: \'MEM_WB_Register\'\nMEM_WB_Register U_MEM_WB_Register(clk, RegWr_MEM,\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:151: Cannot find file containing module: \'HazardDetection\'\nHazardDetection U_HazardDetection(PCSrc_EX, bcomp, PCSrc, MemRd, Rt,Instruct[25:21], Instruct[20:16], bubble,ID_EX_Flush,IF_ID_Flush, EX_MEM_FORWARD);\n^~~~~~~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/Muti_cycle.v:154: Cannot find file containing module: \'forward\'\nforward U_forward(ForwardA,ForwardB,RegWr_MEM,RegWr_WB,RdAdress_MEM,RdAdress_WB,Rs_EX,Rt_EX); \n^~~~~~~\n%Error: Exiting due to 14 error(s), 3 warning(s)\n' | 313,816 | module | module Muti_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx);
input reset,sysclk;
input uart_rx;
output uart_tx;
output [11:0] digi;
output [7:0] led;
input [7:0] switch;
reg [31:0] PC;wire [31:0] Instruct;
wire [31:0] _PCadd4,PCadd4,ConBA,JT,DataBusA,DataBusA_EX,DataBusB,DataBusB_EX,Instruction_ID, Instruction_EX, PC4_ID, PC4_WB,PC4_EX, PC4_MEM;
wire [4:0] RdAdress_MEM, RdAdress_EX,Rt_EX,Rs_EX;
wire [15:0] Imm16;wire [4:0] Shamt, Shamt_EX;
wire [4:0] Rd, Rt, Rs;
wire [31:0] ALUOut, PCIn, ALUOut_MEM, ALUOut_WB, Data_WB, peri_rddata_WB, uart_data_WB, Imm_EX;
wire [5:0] ALUFun,ALUFun_EX;
wire [1:0] ForwardA,ForwardB;
wire [2:0] PCSrc,PCSrc_EX,PCSrc_MEM;wire [1:0] RegDst,RegDst_EX;wire [1:0] MemToReg,MemToReg_EX,MemToReg_MEM,MemToReg_WB;
wire RegWr,ALUSrc1,ALUSrc2, Sign, MemWr, MemRd, EXTOp, LUOp, RegWr_EX, ALUSrc1_EX, ALUSrc2_EX,
Sign_EX, MemWr_EX, MemRd_EX,
RegWr_WB,
bubble,ID_EX_Flush,IF_ID_Flush, IF_ID_Flush0, EX_MEM_FORWARD;
wire bcomp;
wire Flushed_out_ID, Flushed_out_EX;
wire IRQ; reg IRQ_sync;
wire [9:0] watchdog;
assign watchdog = PC[9:2];
assign IF_ID_Flush0 = bubble | IF_ID_Flush;
parameter ILLOP=32'h80000004;
parameter XADR=32'h80000008;
parameter Ra=31;
assign clk = sysclk;
ROM5 U_rom(PC[30:0],Instruct);
assign _PCadd4=PC+4;
assign PCadd4={PC[31],_PCadd4[30:0]};
IF_ID_Register U_IF_ID_Register(clk, IF_ID_Flush0, Instruct, PCadd4, Instruction_ID, PC4_ID,reset,IRQ_sync, PC4_ID[31],Flushed_out_ID);
always @(negedge reset or posedge clk)
begin
if(~reset)
PC<=32'h80000000;
else if(~bubble)
PC <= PCIn;
end
always @(negedge reset or posedge clk)
begin
if (~reset)
IRQ_sync<=0;
else
IRQ_sync<=IRQ;
end
wire [31:0] DataBusA_Forwarded, DataBusB_Forwarded;
assign PCIn=
(PCSrc==3'b100)?ILLOP:
(PCSrc==3'b101)?XADR:
(PCSrc_EX==3'b001&&bcomp)?ConBA:
(PCSrc_EX==3'b011)?DataBusA_Forwarded:
(PCSrc==3'b010)?JT:PCadd4;
Control U_control(Instruction_ID, IRQ_sync, PC4_ID[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);
assign JT={PC4_ID[31:28],Instruction_ID[25:0],2'b0};
assign Imm16=Instruction_ID[15:0];
assign Rd=Instruction_ID[15:11];
assign Rt=Instruction_ID[20:16];
assign Rs=Instruction_ID[25:21];
parameter Xp=26;
wire [4:0] AddrC,RdAdress_WB;wire [31:0] DataBusC;
wire [31:0] EXTout,LUout,_EXTout_shift2;
RegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr_WB,RdAdress_WB,DataBusC);
assign AddrC=(RegDst==0)?Rd:
(RegDst==1)?Rt:
(RegDst==2)?Ra:Xp;
assign EXTout=EXTOp?(Imm16[15]?{16'hFFFF,Imm16}:{16'h0000,Imm16}):{16'h0000,Imm16};
assign LUout=LUOp?{Imm16,16'b0}:EXTout;
assign Shamt=Instruction_ID[10:6];
ID_EX_Register U_ID_EX_Register(clk, ID_EX_Flush, PCSrc, RegDst, RegWr, ALUSrc1, ALUSrc2,
ALUFun, Sign, MemWr, MemRd, MemToReg,
PC4_ID, DataBusA, DataBusB, LUout, AddrC,Shamt,Instruction_ID,Flushed_out_ID,
PCSrc_EX, RegDst_EX, RegWr_EX, ALUSrc1_EX, ALUSrc2_EX,
ALUFun_EX, Sign_EX, MemWr_EX, MemRd_EX, MemToReg_EX,
PC4_EX, DataBusA_EX, DataBusB_EX, Imm_EX, RdAdress_EX, Shamt_EX,Instruction_EX,reset, Flushed_out_EX);
assign Rt_EX=Instruction_EX[20:16];
assign Rs_EX=Instruction_EX[25:21];
wire [31:0] ALUIn1,ALUIn2;
wire [31:0] RegToMemData_MEM;
wire [31:0] NewPC_MEM;
assign DataBusA_Forwarded = (ForwardA == 2'b10)?ALUOut_MEM:(ForwardA == 2'b01)?DataBusC:DataBusA_EX;
assign DataBusB_Forwarded = (ForwardB == 2'b10)?ALUOut_MEM:(ForwardB == 2'b01)?DataBusC:DataBusB_EX;
assign ALUIn1=ALUSrc1_EX?Shamt_EX:DataBusA_Forwarded;
assign ALUIn2=ALUSrc2_EX?Imm_EX:DataBusB_Forwarded;
branch_compare U_branch_compare(bcomp,ALUIn1,ALUIn2,ALUFun_EX[4:1]);
ALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun_EX,Sign_EX);
assign _EXTout_shift2={Imm_EX[29:0],2'b00};
assign ConBA=PC4_EX+_EXTout_shift2;
EX_MEM_Register U_EX_MEM_Register(clk, EX_MEM_FORWARD,PCSrc_EX, RegWr_EX,
MemWr_EX, MemRd_EX, MemToReg_EX,
PCIn, PC4_EX , ALUOut,DataBusB_Forwarded, RdAdress_EX,
PCadd4, PC4_ID, Flushed_out_ID, Flushed_out_EX,
PCSrc_MEM, RegWr_MEM, MemWr_MEM, MemRd_MEM, MemToReg_MEM,
NewPC_MEM, PC4_MEM ,ALUOut_MEM,RegToMemData_MEM, RdAdress_MEM, reset, PCSrc);
wire [31:0] mem_rddata,peri_rddata,uart_data;
wire uart_tx,uart_rx,irqout,rx_irq,tx_irq;
wire [7:0] led,switch;
wire [11:0] digi;
DataMem U_mem(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,mem_rddata);
Peripheral U_peripheral(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,peri_rddata,led,switch,digi,irqout);
Uart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd_MEM, MemWr_MEM, ALUOut_MEM, RegToMemData_MEM, uart_data, rx_irq, tx_irq);
assign IRQ=rx_irq|tx_irq|irqout;
MEM_WB_Register U_MEM_WB_Register(clk, RegWr_MEM,
MemToReg_MEM, PC4_MEM,
mem_rddata, ALUOut_MEM, RdAdress_MEM,
RegWr_WB, MemToReg_WB, PC4_WB,
Data_WB, ALUOut_WB, RdAdress_WB,
peri_rddata, uart_data, peri_rddata_WB, uart_data_WB, reset);
assign DataBusC=(MemToReg_WB==0)?ALUOut_WB:
(MemToReg_WB==1)?(Data_WB|peri_rddata_WB|uart_data_WB):PC4_WB;
HazardDetection U_HazardDetection(PCSrc_EX, bcomp, PCSrc, MemRd,Rt,Instruct[25:21],Instruct[20:16], bubble,ID_EX_Flush,IF_ID_Flush, EX_MEM_FORWARD);
forward U_forward(ForwardA,ForwardB,RegWr_MEM,RegWr_WB,RdAdress_MEM,RdAdress_WB,Rs_EX,Rt_EX);
endmodule | module Muti_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx); |
input reset,sysclk;
input uart_rx;
output uart_tx;
output [11:0] digi;
output [7:0] led;
input [7:0] switch;
reg [31:0] PC;wire [31:0] Instruct;
wire [31:0] _PCadd4,PCadd4,ConBA,JT,DataBusA,DataBusA_EX,DataBusB,DataBusB_EX,Instruction_ID, Instruction_EX, PC4_ID, PC4_WB,PC4_EX, PC4_MEM;
wire [4:0] RdAdress_MEM, RdAdress_EX,Rt_EX,Rs_EX;
wire [15:0] Imm16;wire [4:0] Shamt, Shamt_EX;
wire [4:0] Rd, Rt, Rs;
wire [31:0] ALUOut, PCIn, ALUOut_MEM, ALUOut_WB, Data_WB, peri_rddata_WB, uart_data_WB, Imm_EX;
wire [5:0] ALUFun,ALUFun_EX;
wire [1:0] ForwardA,ForwardB;
wire [2:0] PCSrc,PCSrc_EX,PCSrc_MEM;wire [1:0] RegDst,RegDst_EX;wire [1:0] MemToReg,MemToReg_EX,MemToReg_MEM,MemToReg_WB;
wire RegWr,ALUSrc1,ALUSrc2, Sign, MemWr, MemRd, EXTOp, LUOp, RegWr_EX, ALUSrc1_EX, ALUSrc2_EX,
Sign_EX, MemWr_EX, MemRd_EX,
RegWr_WB,
bubble,ID_EX_Flush,IF_ID_Flush, IF_ID_Flush0, EX_MEM_FORWARD;
wire bcomp;
wire Flushed_out_ID, Flushed_out_EX;
wire IRQ; reg IRQ_sync;
wire [9:0] watchdog;
assign watchdog = PC[9:2];
assign IF_ID_Flush0 = bubble | IF_ID_Flush;
parameter ILLOP=32'h80000004;
parameter XADR=32'h80000008;
parameter Ra=31;
assign clk = sysclk;
ROM5 U_rom(PC[30:0],Instruct);
assign _PCadd4=PC+4;
assign PCadd4={PC[31],_PCadd4[30:0]};
IF_ID_Register U_IF_ID_Register(clk, IF_ID_Flush0, Instruct, PCadd4, Instruction_ID, PC4_ID,reset,IRQ_sync, PC4_ID[31],Flushed_out_ID);
always @(negedge reset or posedge clk)
begin
if(~reset)
PC<=32'h80000000;
else if(~bubble)
PC <= PCIn;
end
always @(negedge reset or posedge clk)
begin
if (~reset)
IRQ_sync<=0;
else
IRQ_sync<=IRQ;
end
wire [31:0] DataBusA_Forwarded, DataBusB_Forwarded;
assign PCIn=
(PCSrc==3'b100)?ILLOP:
(PCSrc==3'b101)?XADR:
(PCSrc_EX==3'b001&&bcomp)?ConBA:
(PCSrc_EX==3'b011)?DataBusA_Forwarded:
(PCSrc==3'b010)?JT:PCadd4;
Control U_control(Instruction_ID, IRQ_sync, PC4_ID[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);
assign JT={PC4_ID[31:28],Instruction_ID[25:0],2'b0};
assign Imm16=Instruction_ID[15:0];
assign Rd=Instruction_ID[15:11];
assign Rt=Instruction_ID[20:16];
assign Rs=Instruction_ID[25:21];
parameter Xp=26;
wire [4:0] AddrC,RdAdress_WB;wire [31:0] DataBusC;
wire [31:0] EXTout,LUout,_EXTout_shift2;
RegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr_WB,RdAdress_WB,DataBusC);
assign AddrC=(RegDst==0)?Rd:
(RegDst==1)?Rt:
(RegDst==2)?Ra:Xp;
assign EXTout=EXTOp?(Imm16[15]?{16'hFFFF,Imm16}:{16'h0000,Imm16}):{16'h0000,Imm16};
assign LUout=LUOp?{Imm16,16'b0}:EXTout;
assign Shamt=Instruction_ID[10:6];
ID_EX_Register U_ID_EX_Register(clk, ID_EX_Flush, PCSrc, RegDst, RegWr, ALUSrc1, ALUSrc2,
ALUFun, Sign, MemWr, MemRd, MemToReg,
PC4_ID, DataBusA, DataBusB, LUout, AddrC,Shamt,Instruction_ID,Flushed_out_ID,
PCSrc_EX, RegDst_EX, RegWr_EX, ALUSrc1_EX, ALUSrc2_EX,
ALUFun_EX, Sign_EX, MemWr_EX, MemRd_EX, MemToReg_EX,
PC4_EX, DataBusA_EX, DataBusB_EX, Imm_EX, RdAdress_EX, Shamt_EX,Instruction_EX,reset, Flushed_out_EX);
assign Rt_EX=Instruction_EX[20:16];
assign Rs_EX=Instruction_EX[25:21];
wire [31:0] ALUIn1,ALUIn2;
wire [31:0] RegToMemData_MEM;
wire [31:0] NewPC_MEM;
assign DataBusA_Forwarded = (ForwardA == 2'b10)?ALUOut_MEM:(ForwardA == 2'b01)?DataBusC:DataBusA_EX;
assign DataBusB_Forwarded = (ForwardB == 2'b10)?ALUOut_MEM:(ForwardB == 2'b01)?DataBusC:DataBusB_EX;
assign ALUIn1=ALUSrc1_EX?Shamt_EX:DataBusA_Forwarded;
assign ALUIn2=ALUSrc2_EX?Imm_EX:DataBusB_Forwarded;
branch_compare U_branch_compare(bcomp,ALUIn1,ALUIn2,ALUFun_EX[4:1]);
ALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun_EX,Sign_EX);
assign _EXTout_shift2={Imm_EX[29:0],2'b00};
assign ConBA=PC4_EX+_EXTout_shift2;
EX_MEM_Register U_EX_MEM_Register(clk, EX_MEM_FORWARD,PCSrc_EX, RegWr_EX,
MemWr_EX, MemRd_EX, MemToReg_EX,
PCIn, PC4_EX , ALUOut,DataBusB_Forwarded, RdAdress_EX,
PCadd4, PC4_ID, Flushed_out_ID, Flushed_out_EX,
PCSrc_MEM, RegWr_MEM, MemWr_MEM, MemRd_MEM, MemToReg_MEM,
NewPC_MEM, PC4_MEM ,ALUOut_MEM,RegToMemData_MEM, RdAdress_MEM, reset, PCSrc);
wire [31:0] mem_rddata,peri_rddata,uart_data;
wire uart_tx,uart_rx,irqout,rx_irq,tx_irq;
wire [7:0] led,switch;
wire [11:0] digi;
DataMem U_mem(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,mem_rddata);
Peripheral U_peripheral(reset,clk,MemRd_MEM,MemWr_MEM,ALUOut_MEM,RegToMemData_MEM,peri_rddata,led,switch,digi,irqout);
Uart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd_MEM, MemWr_MEM, ALUOut_MEM, RegToMemData_MEM, uart_data, rx_irq, tx_irq);
assign IRQ=rx_irq|tx_irq|irqout;
MEM_WB_Register U_MEM_WB_Register(clk, RegWr_MEM,
MemToReg_MEM, PC4_MEM,
mem_rddata, ALUOut_MEM, RdAdress_MEM,
RegWr_WB, MemToReg_WB, PC4_WB,
Data_WB, ALUOut_WB, RdAdress_WB,
peri_rddata, uart_data, peri_rddata_WB, uart_data_WB, reset);
assign DataBusC=(MemToReg_WB==0)?ALUOut_WB:
(MemToReg_WB==1)?(Data_WB|peri_rddata_WB|uart_data_WB):PC4_WB;
HazardDetection U_HazardDetection(PCSrc_EX, bcomp, PCSrc, MemRd,Rt,Instruct[25:21],Instruct[20:16], bubble,ID_EX_Flush,IF_ID_Flush, EX_MEM_FORWARD);
forward U_forward(ForwardA,ForwardB,RegWr_MEM,RegWr_WB,RdAdress_MEM,RdAdress_WB,Rs_EX,Rt_EX);
endmodule | 0 |
142,331 | data/full_repos/permissive/98616431/Muti_test.v | 98,616,431 | Muti_test.v | v | 24 | 73 | [] | [] | [] | [(4, 24)] | null | null | 1: b'%Error: data/full_repos/permissive/98616431/Muti_test.v:14: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Muti_test.v:17: Unsupported: Ignoring delay on this delayed statement.\n#5 reset<=0; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Muti_test.v:18: Unsupported: Ignoring delay on this delayed statement.\n#125 reset<=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Muti_test.v:20: Unsupported: Ignoring delay on this delayed statement.\nforever #2 sysclk<=~sysclk;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,817 | module | module Muti_cycle_tb;
reg sysclk,reset;
wire [11:0] digi;
wire [7:0] led, switch;
wire uart_tx;
reg uart_rx;
initial begin
uart_rx = 1;
end
Muti_cycle U_single_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx);
initial fork
reset<=1;
uart_rx<=1;
#5 reset<=0;
#125 reset<=1;
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | module Muti_cycle_tb; |
reg sysclk,reset;
wire [11:0] digi;
wire [7:0] led, switch;
wire uart_tx;
reg uart_rx;
initial begin
uart_rx = 1;
end
Muti_cycle U_single_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx);
initial fork
reset<=1;
uart_rx<=1;
#5 reset<=0;
#125 reset<=1;
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | 0 |
142,332 | data/full_repos/permissive/98616431/Receiver.v | 98,616,431 | Receiver.v | v | 64 | 57 | [] | [] | [] | [(2, 64)] | null | data/verilator_xmls/1b07fa2a-bd47-4180-82f5-dcccd4b42319.xml | null | 313,819 | module | module Receiver(baudrate_clk,uart_rx,rx_data,rx_status);
input uart_rx,baudrate_clk;
output [7:0] rx_data;
output rx_status;
reg [7:0] data;
reg status;
assign rx_data = data;
assign rx_status = status;
reg sample;
reg sampled;
reg receiving;
reg [2:0] counter;
reg [3:0] bits;
reg [9:0] tmp;
initial begin
sample <= 0;
sampled <= 0;
receiving <= 0;
status <= 0;
data <= 0;
counter <= 0;
tmp <= 0;
bits <= 0;
end
always @(posedge baudrate_clk) begin
if ((~receiving)&&(~uart_rx)) begin
receiving <= 1;
sample <= 0;
end
if (receiving) begin
if (counter == 7) begin
counter <= 0;
sample <= ~sample;
end
else begin
counter <= counter + 1;
end
end
if (sample) begin
if (~sampled) begin
tmp [bits] <= uart_rx;
bits <= bits + 1;
sampled <= 1;
end
end
else begin
if (sampled) begin
sampled <= 0;
end
end
if (bits == 10) begin
bits <= 0;
receiving <= 0;
if (tmp[9]) begin
data[7:0] <= tmp[8:1];
status <= 1;
end
end
if (status) begin
status <= 0;
end
end
endmodule | module Receiver(baudrate_clk,uart_rx,rx_data,rx_status); |
input uart_rx,baudrate_clk;
output [7:0] rx_data;
output rx_status;
reg [7:0] data;
reg status;
assign rx_data = data;
assign rx_status = status;
reg sample;
reg sampled;
reg receiving;
reg [2:0] counter;
reg [3:0] bits;
reg [9:0] tmp;
initial begin
sample <= 0;
sampled <= 0;
receiving <= 0;
status <= 0;
data <= 0;
counter <= 0;
tmp <= 0;
bits <= 0;
end
always @(posedge baudrate_clk) begin
if ((~receiving)&&(~uart_rx)) begin
receiving <= 1;
sample <= 0;
end
if (receiving) begin
if (counter == 7) begin
counter <= 0;
sample <= ~sample;
end
else begin
counter <= counter + 1;
end
end
if (sample) begin
if (~sampled) begin
tmp [bits] <= uart_rx;
bits <= bits + 1;
sampled <= 1;
end
end
else begin
if (sampled) begin
sampled <= 0;
end
end
if (bits == 10) begin
bits <= 0;
receiving <= 0;
if (tmp[9]) begin
data[7:0] <= tmp[8:1];
status <= 1;
end
end
if (status) begin
status <= 0;
end
end
endmodule | 0 |
142,333 | data/full_repos/permissive/98616431/Reg_test.v | 98,616,431 | Reg_test.v | v | 52 | 68 | [] | [] | [] | [(4, 52)] | null | null | 1: b'%Error: data/full_repos/permissive/98616431/Reg_test.v:34: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Reg_test.v:45: Unsupported: Ignoring delay on this delayed statement.\n#5 Reset<=0; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Reg_test.v:46: Unsupported: Ignoring delay on this delayed statement.\n#10 Reset<=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/Reg_test.v:48: Unsupported: Ignoring delay on this delayed statement.\nforever #2 clk<=~clk;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,821 | module | module Reg_tb;
reg clk,Reset;
reg [2:0] PCSrc_in;
reg RegWr_in, MemWr_in,MemRd_in;
reg [1:0] MemToReg_in;
reg [31:0] NewPC_in, ALUResult_in, RegToMemData_in, PC4_in ;
reg [4:0] RdAdress_in;
wire [2:0] PCSrc_out;
wire RegWr_out, MemWr_out,MemRd_out;
wire [1:0] MemToReg_out;
wire [31:0] NewPC_out, ALUResult_out, RegToMemData_out, PC4_out;
wire [4:0] RdAdress_out;
EX_MEM_Register U(clk, Reset, PCSrc_in, RegWr_in,
MemWr_in, MemRd_in, MemToReg_in,
NewPC_in, PC4_in , ALUResult_in, RegToMemData_in, RdAdress_in,
PCSrc_out, RegWr_out, MemWr_out, MemRd_out, MemToReg_out,
NewPC_out, PC4_out ,ALUResult_out, RegToMemData_out, RdAdress_out);
initial fork
clk<=0;
RegWr_in=1;
MemToReg_in=2;
PC4_in=7;
ALUResult_in=9;
RdAdress_in = 14;
#5 Reset<=0;
#10 Reset<=1;
forever #2 clk<=~clk;
join
endmodule | module Reg_tb; |
reg clk,Reset;
reg [2:0] PCSrc_in;
reg RegWr_in, MemWr_in,MemRd_in;
reg [1:0] MemToReg_in;
reg [31:0] NewPC_in, ALUResult_in, RegToMemData_in, PC4_in ;
reg [4:0] RdAdress_in;
wire [2:0] PCSrc_out;
wire RegWr_out, MemWr_out,MemRd_out;
wire [1:0] MemToReg_out;
wire [31:0] NewPC_out, ALUResult_out, RegToMemData_out, PC4_out;
wire [4:0] RdAdress_out;
EX_MEM_Register U(clk, Reset, PCSrc_in, RegWr_in,
MemWr_in, MemRd_in, MemToReg_in,
NewPC_in, PC4_in , ALUResult_in, RegToMemData_in, RdAdress_in,
PCSrc_out, RegWr_out, MemWr_out, MemRd_out, MemToReg_out,
NewPC_out, PC4_out ,ALUResult_out, RegToMemData_out, RdAdress_out);
initial fork
clk<=0;
RegWr_in=1;
MemToReg_in=2;
PC4_in=7;
ALUResult_in=9;
RdAdress_in = 14;
#5 Reset<=0;
#10 Reset<=1;
forever #2 clk<=~clk;
join
endmodule | 0 |
142,334 | data/full_repos/permissive/98616431/rom_ori.v | 98,616,431 | rom_ori.v | v | 48 | 66 | [] | [] | [] | [(3, 47)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98616431/rom_ori.v:10: Bit extraction of array[31:0] requires 5 bit index, not 29 bits.\n : ... In instance ROM\nassign data=(addr < ROM_SIZE)?ROMDATA[addr[30:2]]:32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,823 | module | module ROM (addr,data);
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 32;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h3c114000;
ROMDATA[6] <= 32'h26310004;
ROMDATA[7] <= 32'h241000aa;
ROMDATA[8] <= 32'hae200000;
ROMDATA[9] <= 32'h08100000;
ROMDATA[10] <= 32'h0c000000;
ROMDATA[11] <= 32'h00000000;
ROMDATA[12] <= 32'h3402000a;
ROMDATA[13] <= 32'h0000000c;
ROMDATA[14] <= 32'h0000_0000;
ROMDATA[15]<= 32'h0274_8825;
ROMDATA[16] <= 32'h0800_0015;
ROMDATA[17] <= 32'h0274_8820;
ROMDATA[18] <= 32'h0800_0015;
ROMDATA[19] <= 32'h0274_882A;
ROMDATA[20] <= 32'h1011_0002;
ROMDATA[21] <= 32'h0293_8822;
ROMDATA[22] <= 32'h0800_0015;
ROMDATA[23] <= 32'h0274_8822;
ROMDATA[24] <= 32'h0800_0015;
ROMDATA[25] <= 32'h0274_8824;
ROMDATA[26] <= 32'hae11_0003;
ROMDATA[27] <= 32'h0800_0001;
for (i=28;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | module ROM (addr,data); |
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 32;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h3c114000;
ROMDATA[6] <= 32'h26310004;
ROMDATA[7] <= 32'h241000aa;
ROMDATA[8] <= 32'hae200000;
ROMDATA[9] <= 32'h08100000;
ROMDATA[10] <= 32'h0c000000;
ROMDATA[11] <= 32'h00000000;
ROMDATA[12] <= 32'h3402000a;
ROMDATA[13] <= 32'h0000000c;
ROMDATA[14] <= 32'h0000_0000;
ROMDATA[15]<= 32'h0274_8825;
ROMDATA[16] <= 32'h0800_0015;
ROMDATA[17] <= 32'h0274_8820;
ROMDATA[18] <= 32'h0800_0015;
ROMDATA[19] <= 32'h0274_882A;
ROMDATA[20] <= 32'h1011_0002;
ROMDATA[21] <= 32'h0293_8822;
ROMDATA[22] <= 32'h0800_0015;
ROMDATA[23] <= 32'h0274_8822;
ROMDATA[24] <= 32'h0800_0015;
ROMDATA[25] <= 32'h0274_8824;
ROMDATA[26] <= 32'hae11_0003;
ROMDATA[27] <= 32'h0800_0001;
for (i=28;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | 0 |
142,335 | data/full_repos/permissive/98616431/rom_stable.v | 98,616,431 | rom_stable.v | v | 171 | 66 | [] | [] | [] | [(3, 170)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98616431/rom_stable.v:10: Bit extraction of array[255:0] requires 8 bit index, not 29 bits.\n : ... In instance ROM5\nassign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,824 | module | module ROM5 (addr,data);
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 256;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h0800006b;
ROMDATA[1] <= 32'h08000067;
ROMDATA[2] <= 32'h08000003;
ROMDATA[3] <= 32'h3c194000;
ROMDATA[4] <= 32'h8f310008;
ROMDATA[5] <= 32'h32380004;
ROMDATA[6] <= 32'h3231fffb;
ROMDATA[7] <= 32'haf310008;
ROMDATA[8] <= 32'h17000010;
ROMDATA[9] <= 32'h8f310020;
ROMDATA[10] <= 32'h322f0008;
ROMDATA[11] <= 32'h15e00054;
ROMDATA[12] <= 32'h322e0004;
ROMDATA[13] <= 32'h15c00001;
ROMDATA[14] <= 32'h08000067;
ROMDATA[15] <= 32'h20020000;
ROMDATA[16] <= 32'h08000011;
ROMDATA[17] <= 32'h8f310008;
ROMDATA[18] <= 32'h20180002;
ROMDATA[19] <= 32'h02388825;
ROMDATA[20] <= 32'haf310008;
ROMDATA[21] <= 32'h20180003;
ROMDATA[22] <= 32'haf380020;
ROMDATA[23] <= 32'h235afffc;
ROMDATA[24] <= 32'h03400008;
ROMDATA[25] <= 32'h8f320014;
ROMDATA[26] <= 32'h324f0f00;
ROMDATA[27] <= 32'h200a0700;
ROMDATA[28] <= 32'h20090b00;
ROMDATA[29] <= 32'h11ea000a;
ROMDATA[30] <= 32'h200a0b00;
ROMDATA[31] <= 32'h20090d00;
ROMDATA[32] <= 32'h11ea0009;
ROMDATA[33] <= 32'h200a0d00;
ROMDATA[34] <= 32'h20090e00;
ROMDATA[35] <= 32'h11ea0009;
ROMDATA[36] <= 32'h20090700;
ROMDATA[37] <= 32'h30ce00f0;
ROMDATA[38] <= 32'h000e7102;
ROMDATA[39] <= 32'h0800002f;
ROMDATA[40] <= 32'h30ce000f;
ROMDATA[41] <= 32'h0800002f;
ROMDATA[42] <= 32'h30ee00f0;
ROMDATA[43] <= 32'h000e7102;
ROMDATA[44] <= 32'h0800002f;
ROMDATA[45] <= 32'h30ee000f;
ROMDATA[46] <= 32'h0800002f;
ROMDATA[47] <= 32'h200d0000;
ROMDATA[48] <= 32'h200c00c0;
ROMDATA[49] <= 32'h11ae002b;
ROMDATA[50] <= 32'h200d0001;
ROMDATA[51] <= 32'h200c00f9;
ROMDATA[52] <= 32'h11ae0028;
ROMDATA[53] <= 32'h200d0002;
ROMDATA[54] <= 32'h200c00a4;
ROMDATA[55] <= 32'h11ae0025;
ROMDATA[56] <= 32'h200d0003;
ROMDATA[57] <= 32'h200c00b0;
ROMDATA[58] <= 32'h11ae0022;
ROMDATA[59] <= 32'h200d0004;
ROMDATA[60] <= 32'h200c0099;
ROMDATA[61] <= 32'h11ae001f;
ROMDATA[62] <= 32'h200d0005;
ROMDATA[63] <= 32'h200c0092;
ROMDATA[64] <= 32'h11ae001c;
ROMDATA[65] <= 32'h200d0006;
ROMDATA[66] <= 32'h200c0082;
ROMDATA[67] <= 32'h11ae0019;
ROMDATA[68] <= 32'h200d0007;
ROMDATA[69] <= 32'h200c00f8;
ROMDATA[70] <= 32'h11ae0016;
ROMDATA[71] <= 32'h200d0008;
ROMDATA[72] <= 32'h200c0080;
ROMDATA[73] <= 32'h11ae0013;
ROMDATA[74] <= 32'h200d0009;
ROMDATA[75] <= 32'h200c0090;
ROMDATA[76] <= 32'h11ae0010;
ROMDATA[77] <= 32'h200d000a;
ROMDATA[78] <= 32'h200c0088;
ROMDATA[79] <= 32'h11ae000d;
ROMDATA[80] <= 32'h200d000b;
ROMDATA[81] <= 32'h200c0083;
ROMDATA[82] <= 32'h11ae000a;
ROMDATA[83] <= 32'h200d000c;
ROMDATA[84] <= 32'h200c00c6;
ROMDATA[85] <= 32'h11ae0007;
ROMDATA[86] <= 32'h200d000d;
ROMDATA[87] <= 32'h200c00a1;
ROMDATA[88] <= 32'h11ae0004;
ROMDATA[89] <= 32'h200d000e;
ROMDATA[90] <= 32'h200c0086;
ROMDATA[91] <= 32'h11ae0001;
ROMDATA[92] <= 32'h200c008e;
ROMDATA[93] <= 32'h01899020;
ROMDATA[94] <= 32'haf320014;
ROMDATA[95] <= 32'h08000011;
ROMDATA[96] <= 32'h10800004;
ROMDATA[97] <= 32'h10a00001;
ROMDATA[98] <= 32'h08000011;
ROMDATA[99] <= 32'h8f25001c;
ROMDATA[100] <= 32'h08000011;
ROMDATA[101] <= 32'h8f24001c;
ROMDATA[102] <= 32'h08000011;
ROMDATA[103] <= 32'h08000067;
ROMDATA[104] <= 32'h001ff840;
ROMDATA[105] <= 32'h001ff842;
ROMDATA[106] <= 32'h03e00008;
ROMDATA[107] <= 32'h0c000068;
ROMDATA[108] <= 32'h3c194000;
ROMDATA[109] <= 32'haf200008;
ROMDATA[110] <= 32'h3c18ffff;
ROMDATA[111] <= 32'h2018d8ef;
ROMDATA[112] <= 32'haf380000;
ROMDATA[113] <= 32'h3c18ffff;
ROMDATA[114] <= 32'h2018ffff;
ROMDATA[115] <= 32'haf380004;
ROMDATA[116] <= 32'haf380014;
ROMDATA[117] <= 32'h20180003;
ROMDATA[118] <= 32'haf380008;
ROMDATA[119] <= 32'h2018000e;
ROMDATA[120] <= 32'haf380020;
ROMDATA[121] <= 32'h1080ffff;
ROMDATA[122] <= 32'h10a0fffe;
ROMDATA[123] <= 32'h00803020;
ROMDATA[124] <= 32'h00a03820;
ROMDATA[125] <= 32'h2018000c;
ROMDATA[126] <= 32'haf380020;
ROMDATA[127] <= 32'h00c7402a;
ROMDATA[128] <= 32'h15000004;
ROMDATA[129] <= 32'h00c73022;
ROMDATA[130] <= 32'h14c0fffc;
ROMDATA[131] <= 32'h00073020;
ROMDATA[132] <= 32'h08000087;
ROMDATA[133] <= 32'h00e63822;
ROMDATA[134] <= 32'h14e0fff8;
ROMDATA[135] <= 32'h00c01020;
ROMDATA[136] <= 32'haf22000c;
ROMDATA[137] <= 32'h20040000;
ROMDATA[138] <= 32'h20040000;
ROMDATA[139] <= 32'h8f380020;
ROMDATA[140] <= 32'h33180010;
ROMDATA[141] <= 32'h1700fffd;
ROMDATA[142] <= 32'haf220018;
ROMDATA[143] <= 32'h2018000d;
ROMDATA[144] <= 32'haf380020;
ROMDATA[145] <= 32'h1440ffff;
ROMDATA[146] <= 32'h2018000e;
ROMDATA[147] <= 32'haf380020;
ROMDATA[148] <= 32'h08000079;
for (i=149;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | module ROM5 (addr,data); |
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 256;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h0800006b;
ROMDATA[1] <= 32'h08000067;
ROMDATA[2] <= 32'h08000003;
ROMDATA[3] <= 32'h3c194000;
ROMDATA[4] <= 32'h8f310008;
ROMDATA[5] <= 32'h32380004;
ROMDATA[6] <= 32'h3231fffb;
ROMDATA[7] <= 32'haf310008;
ROMDATA[8] <= 32'h17000010;
ROMDATA[9] <= 32'h8f310020;
ROMDATA[10] <= 32'h322f0008;
ROMDATA[11] <= 32'h15e00054;
ROMDATA[12] <= 32'h322e0004;
ROMDATA[13] <= 32'h15c00001;
ROMDATA[14] <= 32'h08000067;
ROMDATA[15] <= 32'h20020000;
ROMDATA[16] <= 32'h08000011;
ROMDATA[17] <= 32'h8f310008;
ROMDATA[18] <= 32'h20180002;
ROMDATA[19] <= 32'h02388825;
ROMDATA[20] <= 32'haf310008;
ROMDATA[21] <= 32'h20180003;
ROMDATA[22] <= 32'haf380020;
ROMDATA[23] <= 32'h235afffc;
ROMDATA[24] <= 32'h03400008;
ROMDATA[25] <= 32'h8f320014;
ROMDATA[26] <= 32'h324f0f00;
ROMDATA[27] <= 32'h200a0700;
ROMDATA[28] <= 32'h20090b00;
ROMDATA[29] <= 32'h11ea000a;
ROMDATA[30] <= 32'h200a0b00;
ROMDATA[31] <= 32'h20090d00;
ROMDATA[32] <= 32'h11ea0009;
ROMDATA[33] <= 32'h200a0d00;
ROMDATA[34] <= 32'h20090e00;
ROMDATA[35] <= 32'h11ea0009;
ROMDATA[36] <= 32'h20090700;
ROMDATA[37] <= 32'h30ce00f0;
ROMDATA[38] <= 32'h000e7102;
ROMDATA[39] <= 32'h0800002f;
ROMDATA[40] <= 32'h30ce000f;
ROMDATA[41] <= 32'h0800002f;
ROMDATA[42] <= 32'h30ee00f0;
ROMDATA[43] <= 32'h000e7102;
ROMDATA[44] <= 32'h0800002f;
ROMDATA[45] <= 32'h30ee000f;
ROMDATA[46] <= 32'h0800002f;
ROMDATA[47] <= 32'h200d0000;
ROMDATA[48] <= 32'h200c00c0;
ROMDATA[49] <= 32'h11ae002b;
ROMDATA[50] <= 32'h200d0001;
ROMDATA[51] <= 32'h200c00f9;
ROMDATA[52] <= 32'h11ae0028;
ROMDATA[53] <= 32'h200d0002;
ROMDATA[54] <= 32'h200c00a4;
ROMDATA[55] <= 32'h11ae0025;
ROMDATA[56] <= 32'h200d0003;
ROMDATA[57] <= 32'h200c00b0;
ROMDATA[58] <= 32'h11ae0022;
ROMDATA[59] <= 32'h200d0004;
ROMDATA[60] <= 32'h200c0099;
ROMDATA[61] <= 32'h11ae001f;
ROMDATA[62] <= 32'h200d0005;
ROMDATA[63] <= 32'h200c0092;
ROMDATA[64] <= 32'h11ae001c;
ROMDATA[65] <= 32'h200d0006;
ROMDATA[66] <= 32'h200c0082;
ROMDATA[67] <= 32'h11ae0019;
ROMDATA[68] <= 32'h200d0007;
ROMDATA[69] <= 32'h200c00f8;
ROMDATA[70] <= 32'h11ae0016;
ROMDATA[71] <= 32'h200d0008;
ROMDATA[72] <= 32'h200c0080;
ROMDATA[73] <= 32'h11ae0013;
ROMDATA[74] <= 32'h200d0009;
ROMDATA[75] <= 32'h200c0090;
ROMDATA[76] <= 32'h11ae0010;
ROMDATA[77] <= 32'h200d000a;
ROMDATA[78] <= 32'h200c0088;
ROMDATA[79] <= 32'h11ae000d;
ROMDATA[80] <= 32'h200d000b;
ROMDATA[81] <= 32'h200c0083;
ROMDATA[82] <= 32'h11ae000a;
ROMDATA[83] <= 32'h200d000c;
ROMDATA[84] <= 32'h200c00c6;
ROMDATA[85] <= 32'h11ae0007;
ROMDATA[86] <= 32'h200d000d;
ROMDATA[87] <= 32'h200c00a1;
ROMDATA[88] <= 32'h11ae0004;
ROMDATA[89] <= 32'h200d000e;
ROMDATA[90] <= 32'h200c0086;
ROMDATA[91] <= 32'h11ae0001;
ROMDATA[92] <= 32'h200c008e;
ROMDATA[93] <= 32'h01899020;
ROMDATA[94] <= 32'haf320014;
ROMDATA[95] <= 32'h08000011;
ROMDATA[96] <= 32'h10800004;
ROMDATA[97] <= 32'h10a00001;
ROMDATA[98] <= 32'h08000011;
ROMDATA[99] <= 32'h8f25001c;
ROMDATA[100] <= 32'h08000011;
ROMDATA[101] <= 32'h8f24001c;
ROMDATA[102] <= 32'h08000011;
ROMDATA[103] <= 32'h08000067;
ROMDATA[104] <= 32'h001ff840;
ROMDATA[105] <= 32'h001ff842;
ROMDATA[106] <= 32'h03e00008;
ROMDATA[107] <= 32'h0c000068;
ROMDATA[108] <= 32'h3c194000;
ROMDATA[109] <= 32'haf200008;
ROMDATA[110] <= 32'h3c18ffff;
ROMDATA[111] <= 32'h2018d8ef;
ROMDATA[112] <= 32'haf380000;
ROMDATA[113] <= 32'h3c18ffff;
ROMDATA[114] <= 32'h2018ffff;
ROMDATA[115] <= 32'haf380004;
ROMDATA[116] <= 32'haf380014;
ROMDATA[117] <= 32'h20180003;
ROMDATA[118] <= 32'haf380008;
ROMDATA[119] <= 32'h2018000e;
ROMDATA[120] <= 32'haf380020;
ROMDATA[121] <= 32'h1080ffff;
ROMDATA[122] <= 32'h10a0fffe;
ROMDATA[123] <= 32'h00803020;
ROMDATA[124] <= 32'h00a03820;
ROMDATA[125] <= 32'h2018000c;
ROMDATA[126] <= 32'haf380020;
ROMDATA[127] <= 32'h00c7402a;
ROMDATA[128] <= 32'h15000004;
ROMDATA[129] <= 32'h00c73022;
ROMDATA[130] <= 32'h14c0fffc;
ROMDATA[131] <= 32'h00073020;
ROMDATA[132] <= 32'h08000087;
ROMDATA[133] <= 32'h00e63822;
ROMDATA[134] <= 32'h14e0fff8;
ROMDATA[135] <= 32'h00c01020;
ROMDATA[136] <= 32'haf22000c;
ROMDATA[137] <= 32'h20040000;
ROMDATA[138] <= 32'h20040000;
ROMDATA[139] <= 32'h8f380020;
ROMDATA[140] <= 32'h33180010;
ROMDATA[141] <= 32'h1700fffd;
ROMDATA[142] <= 32'haf220018;
ROMDATA[143] <= 32'h2018000d;
ROMDATA[144] <= 32'haf380020;
ROMDATA[145] <= 32'h1440ffff;
ROMDATA[146] <= 32'h2018000e;
ROMDATA[147] <= 32'haf380020;
ROMDATA[148] <= 32'h08000079;
for (i=149;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | 0 |
142,336 | data/full_repos/permissive/98616431/rom_test.v | 98,616,431 | rom_test.v | v | 43 | 66 | [] | [] | [] | [(3, 42)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98616431/rom_test.v:10: Bit extraction of array[31:0] requires 5 bit index, not 29 bits.\n : ... In instance ROM\nassign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,825 | module | module ROM (addr,data);
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 32;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h3c118000;
ROMDATA[6] <= 32'h241000aa;
ROMDATA[7] <= 32'h26310004;
ROMDATA[8] <= 32'hae200000;
ROMDATA[9] <= 32'h0c00000a;
ROMDATA[10] <= 32'h00112100;
ROMDATA[11] <= 32'h001128C3;
ROMDATA[12] <= 32'h00918825;
ROMDATA[13] <= 32'h00918820;
ROMDATA[14] <= 32'hAE110003;
ROMDATA[15] <= 32'h0274882A;
ROMDATA[16] <= 32'h10110001;
ROMDATA[17] <= 32'h00858822;
ROMDATA[18] <= 32'h00a48822;
ROMDATA[19] <= 32'h8E140003;
ROMDATA[20] <= 32'h08000001;
for (i=21;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | module ROM (addr,data); |
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 32;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h3c118000;
ROMDATA[6] <= 32'h241000aa;
ROMDATA[7] <= 32'h26310004;
ROMDATA[8] <= 32'hae200000;
ROMDATA[9] <= 32'h0c00000a;
ROMDATA[10] <= 32'h00112100;
ROMDATA[11] <= 32'h001128C3;
ROMDATA[12] <= 32'h00918825;
ROMDATA[13] <= 32'h00918820;
ROMDATA[14] <= 32'hAE110003;
ROMDATA[15] <= 32'h0274882A;
ROMDATA[16] <= 32'h10110001;
ROMDATA[17] <= 32'h00858822;
ROMDATA[18] <= 32'h00a48822;
ROMDATA[19] <= 32'h8E140003;
ROMDATA[20] <= 32'h08000001;
for (i=21;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | 0 |
142,337 | data/full_repos/permissive/98616431/rom_test2.v | 98,616,431 | rom_test2.v | v | 62 | 66 | [] | [] | [] | [(3, 61)] | null | null | 1: b'%Warning-WIDTH: data/full_repos/permissive/98616431/rom_test2.v:10: Bit extraction of array[63:0] requires 6 bit index, not 29 bits.\n : ... In instance ROM\nassign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32\'b0;\n ^\n ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.\n%Error: Exiting due to 1 warning(s)\n' | 313,826 | module | module ROM (addr,data);
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 64;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h21ef0001;
ROMDATA[6] <= 32'h21ef0001;
ROMDATA[7] <= 32'hae0f0000;
ROMDATA[8] <= 32'h21ce0001;
ROMDATA[9] <= 32'h3c090001;
ROMDATA[10] <= 32'h10000000;
ROMDATA[11] <= 32'h0c00000f;
ROMDATA[12] <= 32'h8e090000;
ROMDATA[13] <= 32'h21290001;
ROMDATA[14] <= 32'h21290001;
ROMDATA[15] <= 32'h8e110000;
ROMDATA[16] <= 32'h26310004;
ROMDATA[17] <= 32'h241000aa;
ROMDATA[18] <= 32'hae110003;
ROMDATA[19] <= 32'h0c000014;
ROMDATA[20] <= 32'h00112100;
ROMDATA[21] <= 32'h10000005;
ROMDATA[22] <= 32'h000e7040;
ROMDATA[23] <= 32'h000e7040;
ROMDATA[24] <= 32'h0800001c;
ROMDATA[25] <= 32'h000f7840;
ROMDATA[26] <= 32'h000f7840;
ROMDATA[27] <= 32'h216b0001;
ROMDATA[28] <= 32'h001128c3;
ROMDATA[29] <= 32'h00918825;
ROMDATA[30] <= 32'h00918820;
ROMDATA[31] <= 32'hae110003;
ROMDATA[32] <= 32'h0274882a;
ROMDATA[33] <= 32'h10110001;
ROMDATA[34] <= 32'h02938822;
ROMDATA[35] <= 32'h02748822;
ROMDATA[36] <= 32'h8e140003;
ROMDATA[37] <= 32'h08000000;
for (i=38;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | module ROM (addr,data); |
input [30:0] addr;
output [31:0] data;
localparam ROM_SIZE = 64;
(* rom_style = "distributed" *) reg [31:0] ROMDATA[ROM_SIZE-1:0];
assign data=(addr[30:2] < ROM_SIZE)?ROMDATA[addr[30:2]]:32'b0;
integer i;
initial begin
ROMDATA[0] <= 32'h00000000;
ROMDATA[1] <= 32'h00000000;
ROMDATA[2] <= 32'h00000000;
ROMDATA[3] <= 32'h00000000;
ROMDATA[4] <= 32'h00000000;
ROMDATA[5] <= 32'h21ef0001;
ROMDATA[6] <= 32'h21ef0001;
ROMDATA[7] <= 32'hae0f0000;
ROMDATA[8] <= 32'h21ce0001;
ROMDATA[9] <= 32'h3c090001;
ROMDATA[10] <= 32'h10000000;
ROMDATA[11] <= 32'h0c00000f;
ROMDATA[12] <= 32'h8e090000;
ROMDATA[13] <= 32'h21290001;
ROMDATA[14] <= 32'h21290001;
ROMDATA[15] <= 32'h8e110000;
ROMDATA[16] <= 32'h26310004;
ROMDATA[17] <= 32'h241000aa;
ROMDATA[18] <= 32'hae110003;
ROMDATA[19] <= 32'h0c000014;
ROMDATA[20] <= 32'h00112100;
ROMDATA[21] <= 32'h10000005;
ROMDATA[22] <= 32'h000e7040;
ROMDATA[23] <= 32'h000e7040;
ROMDATA[24] <= 32'h0800001c;
ROMDATA[25] <= 32'h000f7840;
ROMDATA[26] <= 32'h000f7840;
ROMDATA[27] <= 32'h216b0001;
ROMDATA[28] <= 32'h001128c3;
ROMDATA[29] <= 32'h00918825;
ROMDATA[30] <= 32'h00918820;
ROMDATA[31] <= 32'hae110003;
ROMDATA[32] <= 32'h0274882a;
ROMDATA[33] <= 32'h10110001;
ROMDATA[34] <= 32'h02938822;
ROMDATA[35] <= 32'h02748822;
ROMDATA[36] <= 32'h8e140003;
ROMDATA[37] <= 32'h08000000;
for (i=38;i<ROM_SIZE;i=i+1) begin
ROMDATA[i] <= 32'b0;
end
end
endmodule | 0 |
142,338 | data/full_repos/permissive/98616431/Sender.v | 98,616,431 | Sender.v | v | 52 | 61 | [] | [] | [] | [(2, 52)] | null | data/verilator_xmls/afa5af72-d0c4-4170-9618-d278ed7aaf25.xml | null | 313,828 | module | module Sender(tx_data,tx_en,baudrate_clk,uart_tx,tx_status);
input [7:0] tx_data;
input tx_en,baudrate_clk;
output uart_tx,tx_status;
reg uart;
reg sending;
assign uart_tx = uart;
assign tx_status = ~sending;
reg en;
reg [3:0] counter;
reg [3:0] bits;
reg [9:0] tmp;
initial begin
counter <= 0;
tmp <= 0;
uart <= 1;
bits <= 0;
en <= 0;
sending <= 0;
end
always @(posedge baudrate_clk or posedge tx_en) begin
if (tx_en) begin
en <= 1;
end
else begin
if (en) begin
en <= 0;
uart <= 0;
sending <= 1;
tmp <= {1'b1, tx_data[7:0], 1'b0};
bits <= 1;
end
if (sending) begin
if (counter == 15) begin
if (bits == 10) begin
sending <= 0;
bits <= 0;
end
else begin
uart <= tmp [bits];
bits <= bits + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule | module Sender(tx_data,tx_en,baudrate_clk,uart_tx,tx_status); |
input [7:0] tx_data;
input tx_en,baudrate_clk;
output uart_tx,tx_status;
reg uart;
reg sending;
assign uart_tx = uart;
assign tx_status = ~sending;
reg en;
reg [3:0] counter;
reg [3:0] bits;
reg [9:0] tmp;
initial begin
counter <= 0;
tmp <= 0;
uart <= 1;
bits <= 0;
en <= 0;
sending <= 0;
end
always @(posedge baudrate_clk or posedge tx_en) begin
if (tx_en) begin
en <= 1;
end
else begin
if (en) begin
en <= 0;
uart <= 0;
sending <= 1;
tmp <= {1'b1, tx_data[7:0], 1'b0};
bits <= 1;
end
if (sending) begin
if (counter == 15) begin
if (bits == 10) begin
sending <= 0;
bits <= 0;
end
else begin
uart <= tmp [bits];
bits <= bits + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule | 0 |
142,339 | data/full_repos/permissive/98616431/single_cycle.v | 98,616,431 | single_cycle.v | v | 84 | 130 | [] | [] | [] | [(1, 84)] | null | null | 1: b'%Warning-IMPLICIT: data/full_repos/permissive/98616431/single_cycle.v:44: Signal definition not found, creating implicitly: \'clk\'\nalways @(negedge reset or posedge clk)\n ^~~\n ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.\n%Warning-IMPLICIT: data/full_repos/permissive/98616431/single_cycle.v:79: Signal definition not found, creating implicitly: \'IRQ\'\nassign IRQ=tx_irq|rx_irq|irqout;\n ^~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:21: Cannot find file containing module: \'cpuclk\'\ncpuclk U_cpuclk(clk,sysclk,reset);\n^~~~~~\n ... Looked in:\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/cpuclk\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/cpuclk.v\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/cpuclk.sv\n cpuclk\n cpuclk.v\n cpuclk.sv\n obj_dir/cpuclk\n obj_dir/cpuclk.v\n obj_dir/cpuclk.sv\n%Error: data/full_repos/permissive/98616431/single_cycle.v:23: Cannot find file containing module: \'ROM5\'\nROM5 U_rom(PC[30:0],Instruct);\n^~~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:24: Cannot find file containing module: \'Control\'\nControl U_control(Instruct, IRQ, PC[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);\n^~~~~~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:57: Cannot find file containing module: \'RegFile\'\nRegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr,AddrC,DataBusC);\n^~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/98616431/single_cycle.v:63: Operator COND expects 32 bits on the Conditional True, but Conditional True\'s VARREF \'Shamt\' generates 5 bits.\n : ... In instance single_cycle\nassign ALUIn1=ALUSrc1?Shamt:DataBusA;\n ^\n%Error: data/full_repos/permissive/98616431/single_cycle.v:69: Cannot find file containing module: \'ALU\'\nALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun,Sign);\n^~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:76: Cannot find file containing module: \'DataMem\'\nDataMem U_mem(reset,clk,MemRd,MemWr,ALUOut,DataBusB,mem_rddata);\n^~~~~~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:77: Cannot find file containing module: \'Peripheral\'\nPeripheral U_peripheral(reset,clk,MemRd,MemWr,ALUOut,DataBusB,peri_rddata,led,switch,digi,irqout);\n^~~~~~~~~~\n%Error: data/full_repos/permissive/98616431/single_cycle.v:78: Cannot find file containing module: \'Uart\'\nUart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd, MemWr, ALUOut, DataBusB, uart_data, rx_irq, tx_irq);\n^~~~\n%Error: Exiting due to 8 error(s), 3 warning(s)\n' | 313,829 | module | module single_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx);
input reset,sysclk;
input uart_rx;
output uart_tx;
output [11:0] digi;
output [7:0] led;
input [7:0] switch;
reg [31:0] PC;wire [31:0] Instruct;
wire [31:0] _PCadd4,PCadd4,ConBA,JT,DataBusA,DataBusB;
wire [15:0] Imm16;wire [4:0] Shamt;
wire [4:0] Rd, Rt, Rs;
wire [31:0] ALUOut, PCIn, PC1;wire [5:0] ALUFun;
wire [7:0] watchdog;
wire [2:0] PCSrc;wire [1:0] RegDst;wire [1:0] MemToReg;
wire RegWr,ALUSrc1,ALUSrc2, Sign, MemWr, MemRd, EXTOp, LUOp;
parameter ILLOP=32'h80000004;
parameter XADR=32'h80000008;
parameter Ra=31;
cpuclk U_cpuclk(clk,sysclk,reset);
ROM5 U_rom(PC[30:0],Instruct);
Control U_control(Instruct, IRQ, PC[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);
assign watchdog = PC[9:2];
assign JT={PC[31:28],Instruct[25:0],2'b0};
assign Imm16=Instruct[15:0];
assign Shamt=Instruct[10:6];
assign Rd=Instruct[15:11];
assign Rt=Instruct[20:16];
assign Rs=Instruct[25:21];
assign _PCadd4=PC+4;
assign PCadd4={PC[31],_PCadd4[30:0]};
assign PC1=ALUOut[0]?ConBA:PCadd4;
assign PCIn=(PCSrc==3'b000)?PCadd4:
(PCSrc==3'b001)?PC1:
(PCSrc==3'b010)?JT:
(PCSrc==3'b011)?DataBusA:
(PCSrc==3'b100)?ILLOP:XADR;
always @(negedge reset or posedge clk)
begin
if(~reset)
PC<=32'h80000000;
else
PC <= PCIn;
end
parameter Xp=26;
wire [4:0] AddrC;wire [31:0] DataBusC;
wire [31:0] ALUIn1,ALUIn2;
wire [31:0] EXTout,LUout,_EXTout_shift2;
RegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr,AddrC,DataBusC);
assign AddrC=(RegDst==0)?Rd:
(RegDst==1)?Rt:
(RegDst==2)?Ra:Xp;
assign EXTout=EXTOp?(Imm16[15]?{16'hFFFF,Imm16}:{16'h0000,Imm16}):{16'h0000,Imm16};
assign LUout=LUOp?{Imm16,16'b0}:EXTout;
assign ALUIn1=ALUSrc1?Shamt:DataBusA;
assign ALUIn2=ALUSrc2?LUout:DataBusB;
assign _EXTout_shift2={EXTout[29:0],2'b00};
assign ConBA=PCadd4+_EXTout_shift2;
ALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun,Sign);
wire [31:0] mem_rddata,peri_rddata,uart_data;
wire uart_tx,uart_rx,irqout,rx_irq,tx_irq;
wire [7:0] led,switch;
wire [11:0] digi;
DataMem U_mem(reset,clk,MemRd,MemWr,ALUOut,DataBusB,mem_rddata);
Peripheral U_peripheral(reset,clk,MemRd,MemWr,ALUOut,DataBusB,peri_rddata,led,switch,digi,irqout);
Uart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd, MemWr, ALUOut, DataBusB, uart_data, rx_irq, tx_irq);
assign IRQ=tx_irq|rx_irq|irqout;
assign DataBusC=(MemToReg==0)?ALUOut:
(MemToReg==1)?(mem_rddata|peri_rddata|uart_data):PCadd4;
endmodule | module single_cycle(reset,sysclk,switch,digi,led,uart_rx,uart_tx); |
input reset,sysclk;
input uart_rx;
output uart_tx;
output [11:0] digi;
output [7:0] led;
input [7:0] switch;
reg [31:0] PC;wire [31:0] Instruct;
wire [31:0] _PCadd4,PCadd4,ConBA,JT,DataBusA,DataBusB;
wire [15:0] Imm16;wire [4:0] Shamt;
wire [4:0] Rd, Rt, Rs;
wire [31:0] ALUOut, PCIn, PC1;wire [5:0] ALUFun;
wire [7:0] watchdog;
wire [2:0] PCSrc;wire [1:0] RegDst;wire [1:0] MemToReg;
wire RegWr,ALUSrc1,ALUSrc2, Sign, MemWr, MemRd, EXTOp, LUOp;
parameter ILLOP=32'h80000004;
parameter XADR=32'h80000008;
parameter Ra=31;
cpuclk U_cpuclk(clk,sysclk,reset);
ROM5 U_rom(PC[30:0],Instruct);
Control U_control(Instruct, IRQ, PC[31],PCSrc, RegDst, RegWr,ALUSrc1, ALUSrc2, ALUFun, Sign, MemWr, MemRd, MemToReg,EXTOp, LUOp);
assign watchdog = PC[9:2];
assign JT={PC[31:28],Instruct[25:0],2'b0};
assign Imm16=Instruct[15:0];
assign Shamt=Instruct[10:6];
assign Rd=Instruct[15:11];
assign Rt=Instruct[20:16];
assign Rs=Instruct[25:21];
assign _PCadd4=PC+4;
assign PCadd4={PC[31],_PCadd4[30:0]};
assign PC1=ALUOut[0]?ConBA:PCadd4;
assign PCIn=(PCSrc==3'b000)?PCadd4:
(PCSrc==3'b001)?PC1:
(PCSrc==3'b010)?JT:
(PCSrc==3'b011)?DataBusA:
(PCSrc==3'b100)?ILLOP:XADR;
always @(negedge reset or posedge clk)
begin
if(~reset)
PC<=32'h80000000;
else
PC <= PCIn;
end
parameter Xp=26;
wire [4:0] AddrC;wire [31:0] DataBusC;
wire [31:0] ALUIn1,ALUIn2;
wire [31:0] EXTout,LUout,_EXTout_shift2;
RegFile U_regfile(reset,clk,Rs,DataBusA,Rt,DataBusB,RegWr,AddrC,DataBusC);
assign AddrC=(RegDst==0)?Rd:
(RegDst==1)?Rt:
(RegDst==2)?Ra:Xp;
assign EXTout=EXTOp?(Imm16[15]?{16'hFFFF,Imm16}:{16'h0000,Imm16}):{16'h0000,Imm16};
assign LUout=LUOp?{Imm16,16'b0}:EXTout;
assign ALUIn1=ALUSrc1?Shamt:DataBusA;
assign ALUIn2=ALUSrc2?LUout:DataBusB;
assign _EXTout_shift2={EXTout[29:0],2'b00};
assign ConBA=PCadd4+_EXTout_shift2;
ALU U_alu(ALUOut,ALUIn1,ALUIn2,ALUFun,Sign);
wire [31:0] mem_rddata,peri_rddata,uart_data;
wire uart_tx,uart_rx,irqout,rx_irq,tx_irq;
wire [7:0] led,switch;
wire [11:0] digi;
DataMem U_mem(reset,clk,MemRd,MemWr,ALUOut,DataBusB,mem_rddata);
Peripheral U_peripheral(reset,clk,MemRd,MemWr,ALUOut,DataBusB,peri_rddata,led,switch,digi,irqout);
Uart U_uart(sysclk, clk, reset, uart_tx, uart_rx, MemRd, MemWr, ALUOut, DataBusB, uart_data, rx_irq, tx_irq);
assign IRQ=tx_irq|rx_irq|irqout;
assign DataBusC=(MemToReg==0)?ALUOut:
(MemToReg==1)?(mem_rddata|peri_rddata|uart_data):PCadd4;
endmodule | 0 |
142,340 | data/full_repos/permissive/98616431/single_cycle_tb.v | 98,616,431 | single_cycle_tb.v | v | 17 | 59 | [] | [] | [] | [(3, 17)] | null | null | 1: b'%Error: data/full_repos/permissive/98616431/single_cycle_tb.v:8: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb.v:10: Unsupported: Ignoring delay on this delayed statement.\n#5 reset<=0; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb.v:11: Unsupported: Ignoring delay on this delayed statement.\n#125 reset<=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb.v:13: Unsupported: Ignoring delay on this delayed statement.\nforever #2 sysclk<=~sysclk;\n ^\n%Error: Exiting due to 1 error(s), 3 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,830 | module | module single_cycle_tb;
reg sysclk,reset;
wire [11:0] digi;
wire [7:0] led, switch;
single_cycle U_single_cycle(reset,sysclk,switch,digi,led);
initial fork
reset<=1;
#5 reset<=0;
#125 reset<=1;
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | module single_cycle_tb; |
reg sysclk,reset;
wire [11:0] digi;
wire [7:0] led, switch;
single_cycle U_single_cycle(reset,sysclk,switch,digi,led);
initial fork
reset<=1;
#5 reset<=0;
#125 reset<=1;
sysclk<=0;
forever #2 sysclk<=~sysclk;
join
endmodule | 0 |
142,341 | data/full_repos/permissive/98616431/single_cycle_tb_uart.v | 98,616,431 | single_cycle_tb_uart.v | v | 59 | 37 | [] | [] | [] | [(3, 59)] | null | null | 1: b'%Error: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:23: Unsupported: fork statements\ninitial fork\n ^~~~\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:25: Unsupported: Ignoring delay on this delayed statement.\n#5 reset<=0; \n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:26: Unsupported: Ignoring delay on this delayed statement.\n#10 reset<=1;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:34: Unsupported: Ignoring delay on this delayed statement.\n forever #5 sysclk <= ~sysclk;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:37: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:38: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:39: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:40: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:41: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:42: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:43: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:44: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:45: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:46: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:48: Unsupported: Ignoring delay on this delayed statement.\n #1041670 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:49: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:50: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:51: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:52: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 0;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:53: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:54: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:55: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:56: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/single_cycle_tb_uart.v:57: Unsupported: Ignoring delay on this delayed statement.\n #104167 uart_rx <= 1;\n ^\n%Error: Exiting due to 1 error(s), 23 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,831 | module | module single_cycle_tb_with_uart ;
reg uart_rx ;
wire [7:0] led ;
wire [11:0] digi ;
reg sysclk ;
reg [7:0] switch ;
wire uart_tx ;
reg reset ;
single_cycle
DUT (
.uart_rx (uart_rx ) ,
.led (led ) ,
.digi (digi ) ,
.sysclk (sysclk ) ,
.switch (switch ) ,
.uart_tx (uart_tx ) ,
.reset (reset ) );
initial fork
reset<=1;
#5 reset<=0;
#10 reset<=1;
join
initial begin
switch <= 0;
sysclk <= 0;
uart_rx <= 1;
end
initial begin
forever #5 sysclk <= ~sysclk;
end
initial begin
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#1041670 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
end
endmodule | module single_cycle_tb_with_uart ; |
reg uart_rx ;
wire [7:0] led ;
wire [11:0] digi ;
reg sysclk ;
reg [7:0] switch ;
wire uart_tx ;
reg reset ;
single_cycle
DUT (
.uart_rx (uart_rx ) ,
.led (led ) ,
.digi (digi ) ,
.sysclk (sysclk ) ,
.switch (switch ) ,
.uart_tx (uart_tx ) ,
.reset (reset ) );
initial fork
reset<=1;
#5 reset<=0;
#10 reset<=1;
join
initial begin
switch <= 0;
sysclk <= 0;
uart_rx <= 1;
end
initial begin
forever #5 sysclk <= ~sysclk;
end
initial begin
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#1041670 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 0;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
#104167 uart_rx <= 1;
end
endmodule | 0 |
142,342 | data/full_repos/permissive/98616431/tb_ALU.v | 98,616,431 | tb_ALU.v | v | 29 | 63 | [] | [] | [] | [(1, 28)] | null | null | 1: b'%Warning-STMTDLY: data/full_repos/permissive/98616431/tb_ALU.v:20: Unsupported: Ignoring delay on this delayed statement.\n#20 ALUFun[5:4]<=01;\n^\n ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.\n%Warning-STMTDLY: data/full_repos/permissive/98616431/tb_ALU.v:21: Unsupported: Ignoring delay on this delayed statement.\n#20 ALUFun[5:4]<=11;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/tb_ALU.v:22: Unsupported: Ignoring delay on this delayed statement.\n#20 ALUFun[5:4]<=10;\n^\n%Warning-STMTDLY: data/full_repos/permissive/98616431/tb_ALU.v:23: Unsupported: Ignoring delay on this delayed statement.\n#20 ALUFun[5:4]<=00;\n^\n%Warning-IMPLICIT: data/full_repos/permissive/98616431/tb_ALU.v:12: Signal definition not found, creating implicitly: \'add_sub_out\'\n : ... Suggested alternative: \'addsub_out\'\nassign add_sub_out=010;\n ^~~~~~~~~~~\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh6f\' generates 32 or 7 bits.\n : ... In instance tb_ALU\nassign cmp_out=111;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:10: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sh65\' generates 32 or 7 bits.\n : ... In instance tb_ALU\nassign shift_out=101;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:12: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sha\' generates 32 or 4 bits.\n : ... In instance tb_ALU\nassign add_sub_out=010;\n ^\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:13: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS\'s EQ generates 1 bits.\n : ... In instance tb_ALU\nassign S=(a==0);\n ^\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:21: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?shb\' generates 32 or 4 bits.\n : ... In instance tb_ALU\n#20 ALUFun[5:4]<=11;\n ^~\n%Warning-WIDTH: data/full_repos/permissive/98616431/tb_ALU.v:22: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS\'s CONST \'?32?sha\' generates 32 or 4 bits.\n : ... In instance tb_ALU\n#20 ALUFun[5:4]<=10;\n ^~\n%Error: Exiting due to 11 warning(s)\n ... See the manual and https://verilator.org for more assistance.\n' | 313,833 | module | module tb_ALU;
reg [5:0] ALUFun;
wire [31:0] S;
wire a;
wire [3:0] cmp_out,shift_out,logic_out,addsub_out;
wire [3:0] ALUOut;
assign a=0;
assign cmp_out=111;
assign shift_out=101;
assign logic_out=011;
assign add_sub_out=010;
assign S=(a==0);
assign ALUOut=ALUFun[5]?(ALUFun[4]?cmp_out:shift_out):
(ALUFun[4]?logic_out:addsub_out);
initial begin
ALUFun<=0;
#20 ALUFun[5:4]<=01;
#20 ALUFun[5:4]<=11;
#20 ALUFun[5:4]<=10;
#20 ALUFun[5:4]<=00;
end
endmodule | module tb_ALU; |
reg [5:0] ALUFun;
wire [31:0] S;
wire a;
wire [3:0] cmp_out,shift_out,logic_out,addsub_out;
wire [3:0] ALUOut;
assign a=0;
assign cmp_out=111;
assign shift_out=101;
assign logic_out=011;
assign add_sub_out=010;
assign S=(a==0);
assign ALUOut=ALUFun[5]?(ALUFun[4]?cmp_out:shift_out):
(ALUFun[4]?logic_out:addsub_out);
initial begin
ALUFun<=0;
#20 ALUFun[5:4]<=01;
#20 ALUFun[5:4]<=11;
#20 ALUFun[5:4]<=10;
#20 ALUFun[5:4]<=00;
end
endmodule | 0 |
142,343 | data/full_repos/permissive/98616431/test_arith.v | 98,616,431 | test_arith.v | v | 15 | 46 | [] | [] | [] | [(1, 14)] | null | null | 1: b"%Error: data/full_repos/permissive/98616431/test_arith.v:7: Too many digits for 4 bit number: 4'b11111\nassign b=4'b11111;\n ^~~~~~~~\n%Error: Exiting due to 1 error(s)\n" | 313,834 | module | module test_arith;
wire [3:0] a;
wire [4:0] b;
wire g_a,g_b,g_e;
wire [30:0] e;
assign a=4'b1111;
assign b=4'b11111;
assign e=31'b1111111111111111111111111111111;
assign g_a=a>0;
assign g_b=b>0;
assign g_e=e>0;
endmodule | module test_arith; |
wire [3:0] a;
wire [4:0] b;
wire g_a,g_b,g_e;
wire [30:0] e;
assign a=4'b1111;
assign b=4'b11111;
assign e=31'b1111111111111111111111111111111;
assign g_a=a>0;
assign g_b=b>0;
assign g_e=e>0;
endmodule | 0 |
142,344 | data/full_repos/permissive/98616431/Uart.v | 98,616,431 | Uart.v | v | 108 | 84 | [] | [] | [] | null | [Errno 2] No such file or directory: 'preprocess.output' | null | 1: b"%Error: data/full_repos/permissive/98616431/Uart.v:27: Cannot find file containing module: 'Generator'\nGenerator G(sysclk,baudrate_clk);\n^~~~~~~~~\n ... Looked in:\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/Generator\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/Generator.v\n data/full_repos/permissive/98616431,data/full_repos/permissive/98616431/Generator.sv\n Generator\n Generator.v\n Generator.sv\n obj_dir/Generator\n obj_dir/Generator.v\n obj_dir/Generator.sv\n%Error: data/full_repos/permissive/98616431/Uart.v:28: Cannot find file containing module: 'Receiver'\nReceiver R(baudrate_clk,uart_rx,rx_data,rx_status);\n^~~~~~~~\n%Error: data/full_repos/permissive/98616431/Uart.v:29: Cannot find file containing module: 'Sender'\nSender S(tx_data,tx_en,baudrate_clk,uart_tx,tx_status);\n^~~~~~\n%Error: Exiting due to 3 error(s)\n" | 313,835 | module | module Uart(sysclk,clk,reset,uart_tx,uart_rx,rd,wr,addr,wdata,rdata,rx_irq,tx_irq);
input [31:0] addr;
input [31:0] wdata;
output [31:0] rdata;
reg [31:0] rdata;
input rd,wr,reset,uart_rx,sysclk,clk;
output uart_tx,rx_irq,tx_irq;
wire rx_status,tx_status,tx_en,baudrate_clk;
wire [7:0] tx_data;
wire [7:0] rx_data;
reg en;
reg [7:0] data;
reg [7:0] rx_tmp;
reg [7:0] tx_tmp;
reg tx_ready;
reg [4:0] uart_con;
reg con2,con3;
assign tx_data = data;
assign tx_en = en;
assign tx_irq = uart_con[0]&uart_con[2];
assign rx_irq = uart_con[1]&uart_con[3];
Generator G(sysclk,baudrate_clk);
Receiver R(baudrate_clk,uart_rx,rx_data,rx_status);
Sender S(tx_data,tx_en,baudrate_clk,uart_tx,tx_status);
always@(*) begin
uart_con[4] <= ~tx_status;
if(rd) begin
case(addr)
32'h40000018: rdata <= {24'b0,tx_tmp};
32'h4000001C: rdata <= {24'b0,rx_tmp};
32'h40000020: rdata <= {27'b0,uart_con};
default: rdata <= 32'b0;
endcase
end
else
rdata <= 32'b0;
end
always@(negedge reset or posedge clk) begin
if(~reset) begin
con3 <= 0;
con2 <= 0;
uart_con[3:2] <= 2'b00;
uart_con[1:0] <= 2'b11;
tx_tmp <= 8'b0;
tx_ready <= 0;
data <= 0;
rx_tmp <= 8'b0;
end
else begin
if(wr) begin
case(addr)
32'h40000018: begin tx_tmp <= wdata[7:0]; tx_ready <= 1; end
32'h40000020: uart_con[1:0] <= wdata[1:0];
default: ;
endcase
end
if (rd & (addr == 32'h40000020)) begin
if (uart_con[1])
uart_con[3] <= 0;
if (uart_con[0])
uart_con[2] <= 0;
end
if (tx_status & ~con2) begin
con2 <= 1;
uart_con[2] <= 1;
end
if (con2 & ~tx_status) begin
con2 <= 0;
end
if (rx_status & ~con3) begin
con3 <= 1;
uart_con[3] <= 1;
rx_tmp <= rx_data;
end
if (con3 & ~rx_status) begin
con3 <= 0;
end
if(tx_status & tx_ready) begin
tx_ready <= 0;
data <= tx_tmp;
end
end
end
always @(negedge reset or posedge baudrate_clk or posedge tx_ready) begin
if (~reset) begin
en <= 0;
end
else begin
if (en) begin
en <= 0;
end
if (tx_status & tx_ready) begin
en <= 1;
end
end
end
endmodule | module Uart(sysclk,clk,reset,uart_tx,uart_rx,rd,wr,addr,wdata,rdata,rx_irq,tx_irq); |
input [31:0] addr;
input [31:0] wdata;
output [31:0] rdata;
reg [31:0] rdata;
input rd,wr,reset,uart_rx,sysclk,clk;
output uart_tx,rx_irq,tx_irq;
wire rx_status,tx_status,tx_en,baudrate_clk;
wire [7:0] tx_data;
wire [7:0] rx_data;
reg en;
reg [7:0] data;
reg [7:0] rx_tmp;
reg [7:0] tx_tmp;
reg tx_ready;
reg [4:0] uart_con;
reg con2,con3;
assign tx_data = data;
assign tx_en = en;
assign tx_irq = uart_con[0]&uart_con[2];
assign rx_irq = uart_con[1]&uart_con[3];
Generator G(sysclk,baudrate_clk);
Receiver R(baudrate_clk,uart_rx,rx_data,rx_status);
Sender S(tx_data,tx_en,baudrate_clk,uart_tx,tx_status);
always@(*) begin
uart_con[4] <= ~tx_status;
if(rd) begin
case(addr)
32'h40000018: rdata <= {24'b0,tx_tmp};
32'h4000001C: rdata <= {24'b0,rx_tmp};
32'h40000020: rdata <= {27'b0,uart_con};
default: rdata <= 32'b0;
endcase
end
else
rdata <= 32'b0;
end
always@(negedge reset or posedge clk) begin
if(~reset) begin
con3 <= 0;
con2 <= 0;
uart_con[3:2] <= 2'b00;
uart_con[1:0] <= 2'b11;
tx_tmp <= 8'b0;
tx_ready <= 0;
data <= 0;
rx_tmp <= 8'b0;
end
else begin
if(wr) begin
case(addr)
32'h40000018: begin tx_tmp <= wdata[7:0]; tx_ready <= 1; end
32'h40000020: uart_con[1:0] <= wdata[1:0];
default: ;
endcase
end
if (rd & (addr == 32'h40000020)) begin
if (uart_con[1])
uart_con[3] <= 0;
if (uart_con[0])
uart_con[2] <= 0;
end
if (tx_status & ~con2) begin
con2 <= 1;
uart_con[2] <= 1;
end
if (con2 & ~tx_status) begin
con2 <= 0;
end
if (rx_status & ~con3) begin
con3 <= 1;
uart_con[3] <= 1;
rx_tmp <= rx_data;
end
if (con3 & ~rx_status) begin
con3 <= 0;
end
if(tx_status & tx_ready) begin
tx_ready <= 0;
data <= tx_tmp;
end
end
end
always @(negedge reset or posedge baudrate_clk or posedge tx_ready) begin
if (~reset) begin
en <= 0;
end
else begin
if (en) begin
en <= 0;
end
if (tx_status & tx_ready) begin
en <= 1;
end
end
end
endmodule | 0 |
142,345 | data/full_repos/permissive/98702386/CPU/Adder.v | 98,702,386 | Adder.v | v | 37 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 457: invalid start byte | data/verilator_xmls/9392f2a9-dd8b-43d2-95f8-1af9ab047dde.xml | null | 313,836 | module | module Adder(
src1_i,
src2_i,
sum_o
);
input [32-1:0] src1_i;
input [32-1:0] src2_i;
output [32-1:0] sum_o;
wire [32-1:0] sum_o;
assign sum_o = src1_i + src2_i;
endmodule | module Adder(
src1_i,
src2_i,
sum_o
); |
input [32-1:0] src1_i;
input [32-1:0] src2_i;
output [32-1:0] sum_o;
wire [32-1:0] sum_o;
assign sum_o = src1_i + src2_i;
endmodule | 0 |
142,346 | data/full_repos/permissive/98702386/CPU/ALU.v | 98,702,386 | ALU.v | v | 83 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 455: invalid start byte | data/verilator_xmls/54c4a829-8d49-438a-ae51-f87bb1ae481f.xml | null | 313,837 | module | module ALU(
src1_i,
src2_i,
ctrl_i,
result_o,
zero_o
);
input [32-1:0] src1_i;
input [32-1:0] src2_i;
input [4-1:0] ctrl_i;
output [32-1:0] result_o;
output zero_o;
reg [32-1:0] result_o;
wire zero_o;
wire signed [31:0]tmp1;
assign tmp1 = src2_i;
wire signed [31:0]tmp2;
assign tmp2 = src1_i;
reg [63:0]mul_result;
parameter AND = 4'b0000;
parameter OR = 4'b0001;
parameter ADD = 4'b0010;
parameter SUB = 4'b0110;
parameter SLT = 4'b0111;
parameter NOR = 4'b1100;
parameter SLTU = 4'b1101;
parameter SHIFT = 4'b1110;
parameter MUL = 4'b1000;
assign zero_o = (result_o==32'b0)? 1:0;
always@(*)
begin
case(ctrl_i)
AND: result_o <= src1_i & src2_i;
OR: result_o <= src1_i | src2_i;
ADD: result_o <= src1_i + src2_i;
SUB: result_o <= src1_i - src2_i;
SLT: result_o <= (tmp2 < tmp1)? 1 : 0;
SLTU: result_o <= (tmp2 < src2_i)? 1 : 0;
NOR: result_o <= ~(src1_i | src2_i);
SHIFT: result_o <= tmp1 >>> src1_i;
MUL:
begin
mul_result = src1_i * src2_i;
result_o = mul_result[31:0];
end
default:
result_o <= 0;
endcase
end
endmodule | module ALU(
src1_i,
src2_i,
ctrl_i,
result_o,
zero_o
); |
input [32-1:0] src1_i;
input [32-1:0] src2_i;
input [4-1:0] ctrl_i;
output [32-1:0] result_o;
output zero_o;
reg [32-1:0] result_o;
wire zero_o;
wire signed [31:0]tmp1;
assign tmp1 = src2_i;
wire signed [31:0]tmp2;
assign tmp2 = src1_i;
reg [63:0]mul_result;
parameter AND = 4'b0000;
parameter OR = 4'b0001;
parameter ADD = 4'b0010;
parameter SUB = 4'b0110;
parameter SLT = 4'b0111;
parameter NOR = 4'b1100;
parameter SLTU = 4'b1101;
parameter SHIFT = 4'b1110;
parameter MUL = 4'b1000;
assign zero_o = (result_o==32'b0)? 1:0;
always@(*)
begin
case(ctrl_i)
AND: result_o <= src1_i & src2_i;
OR: result_o <= src1_i | src2_i;
ADD: result_o <= src1_i + src2_i;
SUB: result_o <= src1_i - src2_i;
SLT: result_o <= (tmp2 < tmp1)? 1 : 0;
SLTU: result_o <= (tmp2 < src2_i)? 1 : 0;
NOR: result_o <= ~(src1_i | src2_i);
SHIFT: result_o <= tmp1 >>> src1_i;
MUL:
begin
mul_result = src1_i * src2_i;
result_o = mul_result[31:0];
end
default:
result_o <= 0;
endcase
end
endmodule | 0 |
142,347 | data/full_repos/permissive/98702386/CPU/ALU_Ctrl.v | 98,702,386 | ALU_Ctrl.v | v | 113 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 466: invalid start byte | data/verilator_xmls/5e928d9a-9a65-4d33-80c5-2f36009b35f3.xml | null | 313,838 | module | module ALU_Ctrl(
funct_i,
ALUOp_i,
ALUCtrl_o,
shamt_o,
bne_beq_o,
is_nop
);
input [6-1:0] funct_i;
input [3-1:0] ALUOp_i;
output reg [4-1:0] ALUCtrl_o;
output reg shamt_o ;
output reg bne_beq_o;
output reg is_nop;
parameter AND = 4'b0000;
parameter OR = 4'b0001;
parameter ADD = 4'b0010;
parameter SUB = 4'b0110;
parameter SLT = 4'b0111;
parameter NOR = 4'b1100;
parameter SLTU = 4'b1101;
parameter SHIFT = 4'b1110;
parameter MUL = 4'b1000;
parameter alu_R_type = 3'b000;
parameter alu_addi = 3'b001;
parameter alu_beq = 3'b010;
parameter alu_bne = 3'b011;
parameter alu_ori = 3'b101;
parameter alu_sltiu = 3'b110;
parameter alu_lwsw = 3'b111;
always @(*) begin
shamt_o <= 0;
is_nop <= 0;
case(ALUOp_i)
alu_R_type:
begin
if(funct_i==6'b100000)
ALUCtrl_o <= ADD;
else if(funct_i==6'b100010)
ALUCtrl_o <= SUB;
else if(funct_i==6'b100100)
ALUCtrl_o <= AND;
else if(funct_i==6'b100101)
ALUCtrl_o <= OR;
else if(funct_i==6'b101010)
ALUCtrl_o <= SLT;
else if(funct_i==6'b000011)
begin
ALUCtrl_o <= SHIFT;
shamt_o <= 1;
end
else if(funct_i==6'b000111)
ALUCtrl_o <= SHIFT;
else if(funct_i==6'b011000)
ALUCtrl_o <= MUL;
else if(funct_i==6'b000000)
is_nop <= 1;
end
alu_addi:
ALUCtrl_o <= ADD;
alu_beq:
begin
ALUCtrl_o <= SUB;
bne_beq_o = 1;
end
alu_bne:
begin
ALUCtrl_o <= SUB;
bne_beq_o = 0;
end
alu_ori:
ALUCtrl_o <= OR;
alu_sltiu:
ALUCtrl_o <= SLTU;
alu_lwsw:
ALUCtrl_o <= ADD;
endcase
end
endmodule | module ALU_Ctrl(
funct_i,
ALUOp_i,
ALUCtrl_o,
shamt_o,
bne_beq_o,
is_nop
); |
input [6-1:0] funct_i;
input [3-1:0] ALUOp_i;
output reg [4-1:0] ALUCtrl_o;
output reg shamt_o ;
output reg bne_beq_o;
output reg is_nop;
parameter AND = 4'b0000;
parameter OR = 4'b0001;
parameter ADD = 4'b0010;
parameter SUB = 4'b0110;
parameter SLT = 4'b0111;
parameter NOR = 4'b1100;
parameter SLTU = 4'b1101;
parameter SHIFT = 4'b1110;
parameter MUL = 4'b1000;
parameter alu_R_type = 3'b000;
parameter alu_addi = 3'b001;
parameter alu_beq = 3'b010;
parameter alu_bne = 3'b011;
parameter alu_ori = 3'b101;
parameter alu_sltiu = 3'b110;
parameter alu_lwsw = 3'b111;
always @(*) begin
shamt_o <= 0;
is_nop <= 0;
case(ALUOp_i)
alu_R_type:
begin
if(funct_i==6'b100000)
ALUCtrl_o <= ADD;
else if(funct_i==6'b100010)
ALUCtrl_o <= SUB;
else if(funct_i==6'b100100)
ALUCtrl_o <= AND;
else if(funct_i==6'b100101)
ALUCtrl_o <= OR;
else if(funct_i==6'b101010)
ALUCtrl_o <= SLT;
else if(funct_i==6'b000011)
begin
ALUCtrl_o <= SHIFT;
shamt_o <= 1;
end
else if(funct_i==6'b000111)
ALUCtrl_o <= SHIFT;
else if(funct_i==6'b011000)
ALUCtrl_o <= MUL;
else if(funct_i==6'b000000)
is_nop <= 1;
end
alu_addi:
ALUCtrl_o <= ADD;
alu_beq:
begin
ALUCtrl_o <= SUB;
bne_beq_o = 1;
end
alu_bne:
begin
ALUCtrl_o <= SUB;
bne_beq_o = 0;
end
alu_ori:
ALUCtrl_o <= OR;
alu_sltiu:
ALUCtrl_o <= SLTU;
alu_lwsw:
ALUCtrl_o <= ADD;
endcase
end
endmodule | 0 |
142,348 | data/full_repos/permissive/98702386/CPU/Decoder.v | 98,702,386 | Decoder.v | v | 176 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 459: invalid start byte | data/verilator_xmls/ca505e1f-6024-48fd-882f-42337f53864c.xml | null | 313,840 | module | module Decoder(
instr_op_i,
RegWrite_o,
ALU_op_o,
ALUSrc_o,
RegDst_o,
Branch_o,
MemRead_o,
MemWrite_o,
MemToReg_o
);
input [6-1:0] instr_op_i;
output RegWrite_o;
output [3-1:0] ALU_op_o;
output ALUSrc_o;
output RegDst_o;
output Branch_o;
output MemRead_o;
output MemWrite_o;
output MemToReg_o;
reg [3-1:0] ALU_op_o;
reg ALUSrc_o;
reg RegWrite_o;
reg RegDst_o;
reg Branch_o;
reg MemRead_o;
reg MemWrite_o;
reg MemToReg_o;
parameter addi = 6'b001000;
parameter R_type = 6'b000000;
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter ori = 6'b001101;
parameter sltiu = 6'b001001;
parameter lw = 6'b100011;
parameter sw = 6'b101011;
parameter alu_R_type = 3'b000;
parameter alu_addi = 3'b001;
parameter alu_beq = 3'b010;
parameter alu_bne = 3'b011;
parameter alu_ori = 3'b101;
parameter alu_sltiu = 3'b110;
parameter alu_lwsw = 3'b111;
always@(*)
begin
case(instr_op_i)
addi:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_addi;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
R_type:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 1;
ALU_op_o = alu_R_type;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
beq:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 0;
ALU_op_o = alu_beq;
Branch_o = 1;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
bne:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 0;
ALU_op_o = alu_bne;
Branch_o = 1;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
ori:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_ori;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
sltiu:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_sltiu;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
lw:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_lwsw;
Branch_o = 0;
MemRead_o = 1;
MemWrite_o = 0;
MemToReg_o = 1;
end
sw:
begin
RegDst_o = 1;
ALUSrc_o = 1;
RegWrite_o = 0;
ALU_op_o = alu_lwsw;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 1;
MemToReg_o = 0;
end
endcase
end
endmodule | module Decoder(
instr_op_i,
RegWrite_o,
ALU_op_o,
ALUSrc_o,
RegDst_o,
Branch_o,
MemRead_o,
MemWrite_o,
MemToReg_o
); |
input [6-1:0] instr_op_i;
output RegWrite_o;
output [3-1:0] ALU_op_o;
output ALUSrc_o;
output RegDst_o;
output Branch_o;
output MemRead_o;
output MemWrite_o;
output MemToReg_o;
reg [3-1:0] ALU_op_o;
reg ALUSrc_o;
reg RegWrite_o;
reg RegDst_o;
reg Branch_o;
reg MemRead_o;
reg MemWrite_o;
reg MemToReg_o;
parameter addi = 6'b001000;
parameter R_type = 6'b000000;
parameter beq = 6'b000100;
parameter bne = 6'b000101;
parameter ori = 6'b001101;
parameter sltiu = 6'b001001;
parameter lw = 6'b100011;
parameter sw = 6'b101011;
parameter alu_R_type = 3'b000;
parameter alu_addi = 3'b001;
parameter alu_beq = 3'b010;
parameter alu_bne = 3'b011;
parameter alu_ori = 3'b101;
parameter alu_sltiu = 3'b110;
parameter alu_lwsw = 3'b111;
always@(*)
begin
case(instr_op_i)
addi:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_addi;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
R_type:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 1;
ALU_op_o = alu_R_type;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
beq:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 0;
ALU_op_o = alu_beq;
Branch_o = 1;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
bne:
begin
RegDst_o = 1;
ALUSrc_o = 0;
RegWrite_o = 0;
ALU_op_o = alu_bne;
Branch_o = 1;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
ori:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_ori;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
sltiu:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_sltiu;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 0;
MemToReg_o = 0;
end
lw:
begin
RegDst_o = 0;
ALUSrc_o = 1;
RegWrite_o = 1;
ALU_op_o = alu_lwsw;
Branch_o = 0;
MemRead_o = 1;
MemWrite_o = 0;
MemToReg_o = 1;
end
sw:
begin
RegDst_o = 1;
ALUSrc_o = 1;
RegWrite_o = 0;
ALU_op_o = alu_lwsw;
Branch_o = 0;
MemRead_o = 0;
MemWrite_o = 1;
MemToReg_o = 0;
end
endcase
end
endmodule | 0 |
142,349 | data/full_repos/permissive/98702386/CPU/Forwarding_Unit.v | 98,702,386 | Forwarding_Unit.v | v | 86 | 105 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 492: invalid start byte | data/verilator_xmls/67c4d51f-9e0d-4ba6-929c-7e3d91c574ec.xml | null | 313,841 | module | module Forwarding_Unit(
exmem_rd,
idex_rs,
idex_rt,
memwb_rd,
exmem_RegWrite,
memwb_RegWrite,
forwardA,
forwardB
);
input [4:0] exmem_rd;
input [4:0] idex_rs;
input [4:0] idex_rt;
input [4:0] memwb_rd;
input exmem_RegWrite;
input memwb_RegWrite;
output reg [1:0] forwardA;
output reg [1:0] forwardB;
wire ex_hazard_rs, ex_hazard_rt, mem_hazard_rs, mem_hazard_rt;
assign ex_hazard_rs = (exmem_RegWrite && (exmem_rd!=0) && (exmem_rd==idex_rs))? 1:0;
assign ex_hazard_rt = (exmem_RegWrite && (exmem_rd!=0) && (exmem_rd==idex_rt))? 1:0;
assign mem_hazard_rs = (memwb_RegWrite && (memwb_rd!=0) && (memwb_rd==idex_rs) && !(ex_hazard_rs))? 1:0;
assign mem_hazard_rt = (memwb_RegWrite && (memwb_rd!=0) && (memwb_rd==idex_rt) && !(ex_hazard_rt))? 1:0;
always@(*)begin
if(ex_hazard_rs)
begin
forwardA <= 2'b10;
if(mem_hazard_rt)
forwardB <= 2'b01;
else
forwardB <= 2'b00;
end
else if(ex_hazard_rt)
begin
if(mem_hazard_rs)
forwardA <= 2'b01;
else
forwardA <= 2'b00;
forwardB <= 2'b10;
end
else if(mem_hazard_rs)
begin
forwardA <= 2'b01;
if(ex_hazard_rt)
forwardB <= 2'b10;
else
forwardB <= 2'b00;
end
else if(mem_hazard_rt)
begin
if(ex_hazard_rs)
forwardA <= 2'b10;
else
forwardA <= 2'b00;
forwardB <= 2'b01;
end
else
begin
forwardA <= 2'b00;
forwardB <= 2'b00;
end
end
endmodule | module Forwarding_Unit(
exmem_rd,
idex_rs,
idex_rt,
memwb_rd,
exmem_RegWrite,
memwb_RegWrite,
forwardA,
forwardB
); |
input [4:0] exmem_rd;
input [4:0] idex_rs;
input [4:0] idex_rt;
input [4:0] memwb_rd;
input exmem_RegWrite;
input memwb_RegWrite;
output reg [1:0] forwardA;
output reg [1:0] forwardB;
wire ex_hazard_rs, ex_hazard_rt, mem_hazard_rs, mem_hazard_rt;
assign ex_hazard_rs = (exmem_RegWrite && (exmem_rd!=0) && (exmem_rd==idex_rs))? 1:0;
assign ex_hazard_rt = (exmem_RegWrite && (exmem_rd!=0) && (exmem_rd==idex_rt))? 1:0;
assign mem_hazard_rs = (memwb_RegWrite && (memwb_rd!=0) && (memwb_rd==idex_rs) && !(ex_hazard_rs))? 1:0;
assign mem_hazard_rt = (memwb_RegWrite && (memwb_rd!=0) && (memwb_rd==idex_rt) && !(ex_hazard_rt))? 1:0;
always@(*)begin
if(ex_hazard_rs)
begin
forwardA <= 2'b10;
if(mem_hazard_rt)
forwardB <= 2'b01;
else
forwardB <= 2'b00;
end
else if(ex_hazard_rt)
begin
if(mem_hazard_rs)
forwardA <= 2'b01;
else
forwardA <= 2'b00;
forwardB <= 2'b10;
end
else if(mem_hazard_rs)
begin
forwardA <= 2'b01;
if(ex_hazard_rt)
forwardB <= 2'b10;
else
forwardB <= 2'b00;
end
else if(mem_hazard_rt)
begin
if(ex_hazard_rs)
forwardA <= 2'b10;
else
forwardA <= 2'b00;
forwardB <= 2'b01;
end
else
begin
forwardA <= 2'b00;
forwardB <= 2'b00;
end
end
endmodule | 0 |
142,350 | data/full_repos/permissive/98702386/CPU/Hazard_Detection_Unit.v | 98,702,386 | Hazard_Detection_Unit.v | v | 73 | 83 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 498: invalid start byte | data/verilator_xmls/fec1cc36-f924-48fd-afc8-26283dcbc54c.xml | null | 313,842 | module | module Hazard_Detection_Unit(
idex_MemRead,
idex_rt,
ifid_rs,
ifid_rt,
PCWrite,
ifid_Write,
if_flush,
mem_branch,
ex_branch,
id_branch
);
input idex_MemRead;
input [4:0] idex_rt;
input [4:0] ifid_rs;
input [4:0] ifid_rt;
input ex_branch;
input id_branch;
input mem_branch;
output reg PCWrite;
output reg ifid_Write;
output reg if_flush;
parameter beq = 6'b000100;
parameter bne = 6'b000101;
always@(*)begin
if(idex_MemRead && ((idex_rt==ifid_rs) || (idex_rt==ifid_rt)))
begin
PCWrite <= 0;
ifid_Write <= 0;
if_flush <= 0;
end
else if(mem_branch | ex_branch | id_branch )
begin
if(mem_branch)
PCWrite <= 1;
else
PCWrite <= 0;
ifid_Write <= 0;
if_flush <= 1;
end
else
begin
PCWrite <= 1;
ifid_Write <= 1;
if_flush <= 0;
end
end
endmodule | module Hazard_Detection_Unit(
idex_MemRead,
idex_rt,
ifid_rs,
ifid_rt,
PCWrite,
ifid_Write,
if_flush,
mem_branch,
ex_branch,
id_branch
); |
input idex_MemRead;
input [4:0] idex_rt;
input [4:0] ifid_rs;
input [4:0] ifid_rt;
input ex_branch;
input id_branch;
input mem_branch;
output reg PCWrite;
output reg ifid_Write;
output reg if_flush;
parameter beq = 6'b000100;
parameter bne = 6'b000101;
always@(*)begin
if(idex_MemRead && ((idex_rt==ifid_rs) || (idex_rt==ifid_rt)))
begin
PCWrite <= 0;
ifid_Write <= 0;
if_flush <= 0;
end
else if(mem_branch | ex_branch | id_branch )
begin
if(mem_branch)
PCWrite <= 1;
else
PCWrite <= 0;
ifid_Write <= 0;
if_flush <= 1;
end
else
begin
PCWrite <= 1;
ifid_Write <= 1;
if_flush <= 0;
end
end
endmodule | 0 |
142,351 | data/full_repos/permissive/98702386/CPU/Instr_Memory.v | 98,702,386 | Instr_Memory.v | v | 49 | 97 | [] | [] | [] | null | 'utf-8' codec can't decode byte 0xa8 in position 470: invalid start byte | data/verilator_xmls/99fa00b3-d903-475b-ae03-39858dbafc34.xml | null | 313,843 | module | module Instr_Memory(
pc_addr_i,
instr_o
);
input [32-1:0] pc_addr_i;
output [32-1:0] instr_o;
reg [32-1:0] instr_o;
integer i;
reg [32-1:0] Instr_Mem [0:32-1];
always @(pc_addr_i) begin
instr_o = Instr_Mem[pc_addr_i/4];
end
initial begin
for ( i=0; i<32; i=i+1 )
Instr_Mem[i] = 32'b0;
$readmemb("CO_P4_test_1.txt", Instr_Mem);
end
endmodule | module Instr_Memory(
pc_addr_i,
instr_o
); |
input [32-1:0] pc_addr_i;
output [32-1:0] instr_o;
reg [32-1:0] instr_o;
integer i;
reg [32-1:0] Instr_Mem [0:32-1];
always @(pc_addr_i) begin
instr_o = Instr_Mem[pc_addr_i/4];
end
initial begin
for ( i=0; i<32; i=i+1 )
Instr_Mem[i] = 32'b0;
$readmemb("CO_P4_test_1.txt", Instr_Mem);
end
endmodule | 0 |
Subsets and Splits