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module bp_be_pipe_mul
(
clk_i,
reset_i,
kill_ex1_i,
kill_ex2_i,
decode_i,
rs1_i,
rs2_i,
data_o
);
input [50:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input kill_ex1_i;
input kill_ex2_i;
wire [63:0] data_o;
assign data_o[0] = 1'b0;
assign data_o[1] = 1'b0;
assign data_o[2] = 1'b0;
assign data_o[3] = 1'b0;
assign data_o[4] = 1'b0;
assign data_o[5] = 1'b0;
assign data_o[6] = 1'b0;
assign data_o[7] = 1'b0;
assign data_o[8] = 1'b0;
assign data_o[9] = 1'b0;
assign data_o[10] = 1'b0;
assign data_o[11] = 1'b0;
assign data_o[12] = 1'b0;
assign data_o[13] = 1'b0;
assign data_o[14] = 1'b0;
assign data_o[15] = 1'b0;
assign data_o[16] = 1'b0;
assign data_o[17] = 1'b0;
assign data_o[18] = 1'b0;
assign data_o[19] = 1'b0;
assign data_o[20] = 1'b0;
assign data_o[21] = 1'b0;
assign data_o[22] = 1'b0;
assign data_o[23] = 1'b0;
assign data_o[24] = 1'b0;
assign data_o[25] = 1'b0;
assign data_o[26] = 1'b0;
assign data_o[27] = 1'b0;
assign data_o[28] = 1'b0;
assign data_o[29] = 1'b0;
assign data_o[30] = 1'b0;
assign data_o[31] = 1'b0;
assign data_o[32] = 1'b0;
assign data_o[33] = 1'b0;
assign data_o[34] = 1'b0;
assign data_o[35] = 1'b0;
assign data_o[36] = 1'b0;
assign data_o[37] = 1'b0;
assign data_o[38] = 1'b0;
assign data_o[39] = 1'b0;
assign data_o[40] = 1'b0;
assign data_o[41] = 1'b0;
assign data_o[42] = 1'b0;
assign data_o[43] = 1'b0;
assign data_o[44] = 1'b0;
assign data_o[45] = 1'b0;
assign data_o[46] = 1'b0;
assign data_o[47] = 1'b0;
assign data_o[48] = 1'b0;
assign data_o[49] = 1'b0;
assign data_o[50] = 1'b0;
assign data_o[51] = 1'b0;
assign data_o[52] = 1'b0;
assign data_o[53] = 1'b0;
assign data_o[54] = 1'b0;
assign data_o[55] = 1'b0;
assign data_o[56] = 1'b0;
assign data_o[57] = 1'b0;
assign data_o[58] = 1'b0;
assign data_o[59] = 1'b0;
assign data_o[60] = 1'b0;
assign data_o[61] = 1'b0;
assign data_o[62] = 1'b0;
assign data_o[63] = 1'b0;
endmodule |
module bsg_lru_pseudo_tree_decode_ways_p8
(
way_id_i,
data_o,
mask_o
);
input [2:0] way_id_i;
output [6:0] data_o;
output [6:0] mask_o;
wire [6:0] data_o,mask_o;
wire N0,N1,N2;
assign mask_o[0] = 1'b1;
assign data_o[0] = 1'b1 & N0;
assign N0 = ~way_id_i[2];
assign mask_o[1] = 1'b1 & N0;
assign data_o[1] = mask_o[1] & N1;
assign N1 = ~way_id_i[1];
assign mask_o[2] = 1'b1 & way_id_i[2];
assign data_o[2] = mask_o[2] & N1;
assign mask_o[3] = mask_o[1] & N1;
assign data_o[3] = mask_o[3] & N2;
assign N2 = ~way_id_i[0];
assign mask_o[4] = mask_o[1] & way_id_i[1];
assign data_o[4] = mask_o[4] & N2;
assign mask_o[5] = mask_o[2] & N1;
assign data_o[5] = mask_o[5] & N2;
assign mask_o[6] = mask_o[2] & way_id_i[1];
assign data_o[6] = mask_o[6] & N2;
endmodule |
module bsg_link_iddr_phy_width_p9
(
clk_i,
data_i,
data_r_o
);
input [8:0] data_i;
output [17:0] data_r_o;
input clk_i;
wire [17:0] data_r_o;
wire N0;
wire [8:0] data_p_r,data_n_r;
reg data_p_r_8_sv2v_reg,data_p_r_7_sv2v_reg,data_p_r_6_sv2v_reg,data_p_r_5_sv2v_reg,
data_p_r_4_sv2v_reg,data_p_r_3_sv2v_reg,data_p_r_2_sv2v_reg,data_p_r_1_sv2v_reg,
data_p_r_0_sv2v_reg,data_n_r_8_sv2v_reg,data_n_r_7_sv2v_reg,data_n_r_6_sv2v_reg,
data_n_r_5_sv2v_reg,data_n_r_4_sv2v_reg,data_n_r_3_sv2v_reg,data_n_r_2_sv2v_reg,
data_n_r_1_sv2v_reg,data_n_r_0_sv2v_reg,data_r_o_17_sv2v_reg,
data_r_o_16_sv2v_reg,data_r_o_15_sv2v_reg,data_r_o_14_sv2v_reg,data_r_o_13_sv2v_reg,
data_r_o_12_sv2v_reg,data_r_o_11_sv2v_reg,data_r_o_10_sv2v_reg,data_r_o_9_sv2v_reg,
data_r_o_8_sv2v_reg,data_r_o_7_sv2v_reg,data_r_o_6_sv2v_reg,data_r_o_5_sv2v_reg,
data_r_o_4_sv2v_reg,data_r_o_3_sv2v_reg,data_r_o_2_sv2v_reg,data_r_o_1_sv2v_reg,
data_r_o_0_sv2v_reg;
assign data_p_r[8] = data_p_r_8_sv2v_reg;
assign data_p_r[7] = data_p_r_7_sv2v_reg;
assign data_p_r[6] = data_p_r_6_sv2v_reg;
assign data_p_r[5] = data_p_r_5_sv2v_reg;
assign data_p_r[4] = data_p_r_4_sv2v_reg;
assign data_p_r[3] = data_p_r_3_sv2v_reg;
assign data_p_r[2] = data_p_r_2_sv2v_reg;
assign data_p_r[1] = data_p_r_1_sv2v_reg;
assign data_p_r[0] = data_p_r_0_sv2v_reg;
assign data_n_r[8] = data_n_r_8_sv2v_reg;
assign data_n_r[7] = data_n_r_7_sv2v_reg;
assign data_n_r[6] = data_n_r_6_sv2v_reg;
assign data_n_r[5] = data_n_r_5_sv2v_reg;
assign data_n_r[4] = data_n_r_4_sv2v_reg;
assign data_n_r[3] = data_n_r_3_sv2v_reg;
assign data_n_r[2] = data_n_r_2_sv2v_reg;
assign data_n_r[1] = data_n_r_1_sv2v_reg;
assign data_n_r[0] = data_n_r_0_sv2v_reg;
assign data_r_o[17] = data_r_o_17_sv2v_reg;
assign data_r_o[16] = data_r_o_16_sv2v_reg;
assign data_r_o[15] = data_r_o_15_sv2v_reg;
assign data_r_o[14] = data_r_o_14_sv2v_reg;
assign data_r_o[13] = data_r_o_13_sv2v_reg;
assign data_r_o[12] = data_r_o_12_sv2v_reg;
assign data_r_o[11] = data_r_o_11_sv2v_reg;
assign data_r_o[10] = data_r_o_10_sv2v_reg;
assign data_r_o[9] = data_r_o_9_sv2v_reg;
assign data_r_o[8] = data_r_o_8_sv2v_reg;
assign data_r_o[7] = data_r_o_7_sv2v_reg;
assign data_r_o[6] = data_r_o_6_sv2v_reg;
assign data_r_o[5] = data_r_o_5_sv2v_reg;
assign data_r_o[4] = data_r_o_4_sv2v_reg;
assign data_r_o[3] = data_r_o_3_sv2v_reg;
assign data_r_o[2] = data_r_o_2_sv2v_reg;
assign data_r_o[1] = data_r_o_1_sv2v_reg;
assign data_r_o[0] = data_r_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_p_r_0_sv2v_reg <= data_i[0];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_8_sv2v_reg <= data_i[8];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_7_sv2v_reg <= data_i[7];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_6_sv2v_reg <= data_i[6];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_5_sv2v_reg <= data_i[5];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_4_sv2v_reg <= data_i[4];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_3_sv2v_reg <= data_i[3];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_2_sv2v_reg <= data_i[2];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_1_sv2v_reg <= data_i[1];
end
end
always @(posedge N0) begin
if(1'b1) begin
data_n_r_0_sv2v_reg <= data_i[0];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_17_sv2v_reg <= data_n_r[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_16_sv2v_reg <= data_n_r[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_15_sv2v_reg <= data_n_r[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_14_sv2v_reg <= data_n_r[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_13_sv2v_reg <= data_n_r[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_12_sv2v_reg <= data_n_r[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_11_sv2v_reg <= data_n_r[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_10_sv2v_reg <= data_n_r[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_9_sv2v_reg <= data_n_r[0];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_8_sv2v_reg <= data_p_r[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_7_sv2v_reg <= data_p_r[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_6_sv2v_reg <= data_p_r[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_5_sv2v_reg <= data_p_r[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_4_sv2v_reg <= data_p_r[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_3_sv2v_reg <= data_p_r[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_2_sv2v_reg <= data_p_r[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_1_sv2v_reg <= data_p_r[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_0_sv2v_reg <= data_p_r[0];
end
end
assign N0 = ~clk_i;
endmodule |
module bp_me_lce_id_to_cord_05
(
lce_id_i,
lce_cord_o,
lce_cid_o
);
input [5:0] lce_id_i;
output [4:0] lce_cord_o;
output [1:0] lce_cid_o;
wire [4:0] lce_cord_o;
wire [1:0] lce_cid_o;
wire N0,N1,N2,N3,N4,N5,N6,N7;
assign lce_cord_o[1] = 1'b0;
assign lce_cid_o[1] = 1'b0;
assign { N5, N4, N3 } = 1'b1 + lce_id_i[4:2];
assign { lce_cord_o[4:2], lce_cord_o[0:0] } = (N0)? { N5, N4, N3, lce_id_i[1:1] } :
(N1)? { 1'b0, 1'b0, 1'b0, lce_id_i[0:0] } : 1'b0;
assign N0 = N2;
assign N1 = N7;
assign lce_cid_o[0] = (N0)? lce_id_i[0] :
(N1)? 1'b0 : 1'b0;
assign N2 = ~N7;
assign N7 = N6 | lce_id_i[3];
assign N6 = lce_id_i[5] | lce_id_i[4];
endmodule |
module bsg_nand_width_p5_harden_p1
(
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0,N1,N2,N3,N4;
assign o[4] = ~N0;
assign N0 = a_i[4] & b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] & b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] & b_i[2];
assign o[1] = ~N3;
assign N3 = a_i[1] & b_i[1];
assign o[0] = ~N4;
assign N4 = a_i[0] & b_i[0];
endmodule |
module bsg_sync_sync_1_unit
(
oclk_i,
iclk_data_i,
oclk_data_o
);
input [0:0] iclk_data_i;
output [0:0] oclk_data_o;
input oclk_i;
wire [0:0] oclk_data_o,bsg_SYNC_1_r;
reg bsg_SYNC_1_r_0_sv2v_reg,oclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
endmodule |
module bsg_transpose_width_p3_els_p3
(
i,
o
);
input [8:0] i;
output [8:0] o;
wire [8:0] o;
assign o[8] = i[8];
assign o[7] = i[5];
assign o[6] = i[2];
assign o[5] = i[7];
assign o[4] = i[4];
assign o[3] = i[1];
assign o[2] = i[6];
assign o[1] = i[3];
assign o[0] = i[0];
endmodule |
module bsg_mux_segmented_segments_p5_segment_width_p64
(
data0_i,
data1_i,
sel_i,
data_o
);
input [319:0] data0_i;
input [319:0] data1_i;
input [4:0] sel_i;
output [319:0] data_o;
wire [319:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
assign data_o[63:0] = (N0)? data1_i[63:0] :
(N5)? data0_i[63:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[127:64] = (N1)? data1_i[127:64] :
(N6)? data0_i[127:64] : 1'b0;
assign N1 = sel_i[1];
assign data_o[191:128] = (N2)? data1_i[191:128] :
(N7)? data0_i[191:128] : 1'b0;
assign N2 = sel_i[2];
assign data_o[255:192] = (N3)? data1_i[255:192] :
(N8)? data0_i[255:192] : 1'b0;
assign N3 = sel_i[3];
assign data_o[319:256] = (N4)? data1_i[319:256] :
(N9)? data0_i[319:256] : 1'b0;
assign N4 = sel_i[4];
assign N5 = ~sel_i[0];
assign N6 = ~sel_i[1];
assign N7 = ~sel_i[2];
assign N8 = ~sel_i[3];
assign N9 = ~sel_i[4];
endmodule |
module bsg_dff_reset_en_width_p4_reset_val_p0
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [3:0] data_i;
output [3:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [3:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
reg data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_3_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N9)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N9)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N8 = ~reset_i;
assign N9 = en_i & N8;
endmodule |
module bsg_dff_reset_en_width_p2
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [1:0] data_i;
output [1:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [1:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7;
reg data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N7)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N5, N4 } = (N0)? { 1'b0, 1'b0 } :
(N7)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N6 = ~reset_i;
assign N7 = en_i & N6;
endmodule |
module bsg_mux2_gatestack_width_p3_harden_p1
(
i0,
i1,
i2,
o
);
input [2:0] i0;
input [2:0] i1;
input [2:0] i2;
output [2:0] o;
wire [2:0] o;
wire N0,N1,N2,N3,N4,N5;
assign o[0] = (N0)? i1[0] :
(N3)? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1)? i1[1] :
(N4)? i0[1] : 1'b0;
assign N1 = i2[1];
assign o[2] = (N2)? i1[2] :
(N5)? i0[2] : 1'b0;
assign N2 = i2[2];
assign N3 = ~i2[0];
assign N4 = ~i2[1];
assign N5 = ~i2[2];
endmodule |
module bsg_round_robin_arb_inputs_p3
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [2:0] reqs_i;
output [2:0] grants_o;
output [2:0] sel_one_hot_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [2:0] grants_o,sel_one_hot_o;
wire [1:0] tag_o,last_r;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59;
reg last_r_1_sv2v_reg,last_r_0_sv2v_reg;
assign last_r[1] = last_r_1_sv2v_reg;
assign last_r[0] = last_r_0_sv2v_reg;
assign N10 = N7 & N8;
assign N11 = N10 & N9;
assign N14 = N12 & N13;
assign N15 = N14 & reqs_i[1];
assign N16 = last_r[1] | last_r[0];
assign N17 = N7 | reqs_i[1];
assign N18 = N16 | N17;
assign N20 = last_r[1] | last_r[0];
assign N21 = reqs_i[2] | reqs_i[1];
assign N22 = N20 | N21;
assign N23 = N22 | N9;
assign N25 = last_r[1] | N13;
assign N26 = N25 | N7;
assign N28 = N12 & last_r[0];
assign N29 = N7 & reqs_i[0];
assign N30 = N28 & N29;
assign N31 = last_r[1] | N13;
assign N32 = reqs_i[2] | N8;
assign N33 = N31 | N32;
assign N34 = N33 | reqs_i[0];
assign N36 = last_r[1] & N13;
assign N37 = N36 & reqs_i[0];
assign N38 = last_r[1] & N13;
assign N39 = reqs_i[1] & N9;
assign N40 = N38 & N39;
assign N41 = N12 | last_r[0];
assign N42 = N41 | N17;
assign N43 = N42 | reqs_i[0];
assign N45 = last_r[1] & last_r[0];
assign N46 = N45 & reqs_i[2];
assign N47 = last_r[1] & last_r[0];
assign N48 = N47 & reqs_i[0];
assign N49 = last_r[1] & last_r[0];
assign N50 = N49 & reqs_i[1];
always @(posedge clk_i) begin
if(N57) begin
last_r_1_sv2v_reg <= N55;
end
end
always @(posedge clk_i) begin
if(N57) begin
last_r_0_sv2v_reg <= N54;
end
end
assign sel_one_hot_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1, 1'b0 } :
(N19)? { 1'b1, 1'b0, 1'b0 } :
(N24)? { 1'b0, 1'b0, 1'b1 } :
(N27)? { 1'b1, 1'b0, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b1 } :
(N35)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0 } :
(N44)? { 1'b1, 1'b0, 1'b0 } : 1'b0;
assign N0 = N11;
assign N1 = N15;
assign N2 = N30;
assign N3 = N37;
assign N4 = N40;
assign tag_o = (N0)? { 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1 } :
(N19)? { 1'b1, 1'b0 } :
(N24)? { 1'b0, 1'b0 } :
(N27)? { 1'b1, 1'b0 } :
(N2)? { 1'b0, 1'b0 } :
(N35)? { 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0 } :
(N4)? { 1'b0, 1'b1 } :
(N44)? { 1'b1, 1'b0 } :
(N51)? { 1'b0, 1'b0 } : 1'b0;
assign { N55, N54 } = (N5)? { 1'b0, 1'b0 } :
(N6)? tag_o : 1'b0;
assign N5 = reset_i;
assign N6 = N53;
assign N7 = ~reqs_i[2];
assign N8 = ~reqs_i[1];
assign N9 = ~reqs_i[0];
assign N12 = ~last_r[1];
assign N13 = ~last_r[0];
assign N19 = ~N18;
assign N24 = ~N23;
assign N27 = ~N26;
assign N35 = ~N34;
assign N44 = ~N43;
assign N51 = N46 | N58;
assign N58 = N48 | N50;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N59 | reqs_i[0];
assign N59 = reqs_i[2] | reqs_i[1];
assign N52 = ~yumi_i;
assign N53 = ~reset_i;
assign N56 = N52 & N53;
assign N57 = ~N56;
endmodule |
module bsg_mem_1r1w_synth_width_p4_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [3:0] w_data_i;
input [0:0] r_addr_i;
output [3:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [3:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
wire [7:0] mem;
reg mem_7_sv2v_reg,mem_6_sv2v_reg,mem_5_sv2v_reg,mem_4_sv2v_reg,mem_3_sv2v_reg,
mem_2_sv2v_reg,mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[7] = mem_7_sv2v_reg;
assign mem[6] = mem_6_sv2v_reg;
assign mem[5] = mem_5_sv2v_reg;
assign mem[4] = mem_4_sv2v_reg;
assign mem[3] = mem_3_sv2v_reg;
assign mem[2] = mem_2_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[7] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[6] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[5] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[4] : 1'b0;
always @(posedge w_clk_i) begin
if(N8) begin
mem_7_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_6_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_5_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_4_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_3_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_2_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_1_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
endmodule |
module bsg_concentrate_static_17
(
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_en_width_p62_harden_p0
(
clk_i,
data_i,
en_i,
data_o
);
input [61:0] data_i;
output [61:0] data_o;
input clk_i;
input en_i;
wire [61:0] data_o;
reg data_o_61_sv2v_reg,data_o_60_sv2v_reg,data_o_59_sv2v_reg,data_o_58_sv2v_reg,
data_o_57_sv2v_reg,data_o_56_sv2v_reg,data_o_55_sv2v_reg,data_o_54_sv2v_reg,
data_o_53_sv2v_reg,data_o_52_sv2v_reg,data_o_51_sv2v_reg,data_o_50_sv2v_reg,
data_o_49_sv2v_reg,data_o_48_sv2v_reg,data_o_47_sv2v_reg,data_o_46_sv2v_reg,
data_o_45_sv2v_reg,data_o_44_sv2v_reg,data_o_43_sv2v_reg,data_o_42_sv2v_reg,data_o_41_sv2v_reg,
data_o_40_sv2v_reg,data_o_39_sv2v_reg,data_o_38_sv2v_reg,data_o_37_sv2v_reg,
data_o_36_sv2v_reg,data_o_35_sv2v_reg,data_o_34_sv2v_reg,data_o_33_sv2v_reg,
data_o_32_sv2v_reg,data_o_31_sv2v_reg,data_o_30_sv2v_reg,data_o_29_sv2v_reg,
data_o_28_sv2v_reg,data_o_27_sv2v_reg,data_o_26_sv2v_reg,data_o_25_sv2v_reg,
data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,
data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,
data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,
data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,
data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,
data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[61] = data_o_61_sv2v_reg;
assign data_o[60] = data_o_60_sv2v_reg;
assign data_o[59] = data_o_59_sv2v_reg;
assign data_o[58] = data_o_58_sv2v_reg;
assign data_o[57] = data_o_57_sv2v_reg;
assign data_o[56] = data_o_56_sv2v_reg;
assign data_o[55] = data_o_55_sv2v_reg;
assign data_o[54] = data_o_54_sv2v_reg;
assign data_o[53] = data_o_53_sv2v_reg;
assign data_o[52] = data_o_52_sv2v_reg;
assign data_o[51] = data_o_51_sv2v_reg;
assign data_o[50] = data_o_50_sv2v_reg;
assign data_o[49] = data_o_49_sv2v_reg;
assign data_o[48] = data_o_48_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(en_i) begin
data_o_61_sv2v_reg <= data_i[61];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_60_sv2v_reg <= data_i[60];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_59_sv2v_reg <= data_i[59];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_58_sv2v_reg <= data_i[58];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_57_sv2v_reg <= data_i[57];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_56_sv2v_reg <= data_i[56];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_55_sv2v_reg <= data_i[55];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_54_sv2v_reg <= data_i[54];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_53_sv2v_reg <= data_i[53];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_52_sv2v_reg <= data_i[52];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_51_sv2v_reg <= data_i[51];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_50_sv2v_reg <= data_i[50];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_49_sv2v_reg <= data_i[49];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_48_sv2v_reg <= data_i[48];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_47_sv2v_reg <= data_i[47];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_46_sv2v_reg <= data_i[46];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_45_sv2v_reg <= data_i[45];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_44_sv2v_reg <= data_i[44];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_43_sv2v_reg <= data_i[43];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_42_sv2v_reg <= data_i[42];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_41_sv2v_reg <= data_i[41];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_40_sv2v_reg <= data_i[40];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_39_sv2v_reg <= data_i[39];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_38_sv2v_reg <= data_i[38];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_37_sv2v_reg <= data_i[37];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_36_sv2v_reg <= data_i[36];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_35_sv2v_reg <= data_i[35];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_34_sv2v_reg <= data_i[34];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_33_sv2v_reg <= data_i[33];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_32_sv2v_reg <= data_i[32];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_31_sv2v_reg <= data_i[31];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_30_sv2v_reg <= data_i[30];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_29_sv2v_reg <= data_i[29];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_28_sv2v_reg <= data_i[28];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_27_sv2v_reg <= data_i[27];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_26_sv2v_reg <= data_i[26];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_25_sv2v_reg <= data_i[25];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_24_sv2v_reg <= data_i[24];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_23_sv2v_reg <= data_i[23];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_22_sv2v_reg <= data_i[22];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_21_sv2v_reg <= data_i[21];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_20_sv2v_reg <= data_i[20];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_19_sv2v_reg <= data_i[19];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_18_sv2v_reg <= data_i[18];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_launch_sync_sync_posedge_1_unit
(
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [0:0] iclk_data_i;
output [0:0] iclk_data_o;
output [0:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [0:0] iclk_data_o,oclk_data_o,bsg_SYNC_1_r;
wire N0,N1,N2,N3;
reg iclk_data_o_0_sv2v_reg,bsg_SYNC_1_r_0_sv2v_reg,oclk_data_o_0_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_0_sv2v_reg <= N3;
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign N3 = (N0)? 1'b0 :
(N1)? iclk_data_i[0] : 1'b0;
assign N0 = iclk_reset_i;
assign N1 = N2;
assign N2 = ~iclk_reset_i;
endmodule |
module bsg_dff_reset_02
(
clk_i,
reset_i,
data_i,
data_o
);
input [1:0] data_i;
output [1:0] data_o;
input clk_i;
input reset_i;
wire [1:0] data_o;
wire N0,N1,N2,N3,N4;
reg data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N4, N3 } = (N0)? { 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_counter_set_down_4_1
(
clk_i,
reset_i,
set_i,
val_i,
down_i,
count_r_o
);
input [3:0] val_i;
output [3:0] count_r_o;
input clk_i;
input reset_i;
input set_i;
input down_i;
wire [3:0] count_r_o,ctr_n;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18;
reg count_r_o_3_sv2v_reg,count_r_o_2_sv2v_reg,count_r_o_1_sv2v_reg,
count_r_o_0_sv2v_reg;
assign count_r_o[3] = count_r_o_3_sv2v_reg;
assign count_r_o[2] = count_r_o_2_sv2v_reg;
assign count_r_o[1] = count_r_o_1_sv2v_reg;
assign count_r_o[0] = count_r_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N18) begin
count_r_o_3_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(N18) begin
count_r_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N18) begin
count_r_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N18) begin
count_r_o_0_sv2v_reg <= N4;
end
end
assign { N14, N13, N12, N11 } = count_r_o - 1'b1;
assign { N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? ctr_n : 1'b0;
assign N0 = reset_i;
assign N1 = N3;
assign ctr_n = (N2)? val_i :
(N16)? { N14, N13, N12, N11 } : 1'b0;
assign N2 = set_i;
assign N3 = ~reset_i;
assign N8 = down_i | set_i;
assign N9 = ~N8;
assign N10 = N16;
assign N15 = ~set_i;
assign N16 = down_i & N15;
assign N17 = N9 & N3;
assign N18 = ~N17;
endmodule |
module bsg_decode_num_out_p4
(
i,
o
);
input [1:0] i;
output [3:0] o;
wire [3:0] o;
assign o = { 1'b0, 1'b0, 1'b0, 1'b1 } << i;
endmodule |
module bsg_mux_one_hot_128_02
(
data_i,
sel_one_hot_i,
data_o
);
input [255:0] data_i;
input [1:0] sel_one_hot_i;
output [127:0] data_o;
wire [127:0] data_o;
wire [255:0] data_masked;
assign data_masked[127] = data_i[127] & sel_one_hot_i[0];
assign data_masked[126] = data_i[126] & sel_one_hot_i[0];
assign data_masked[125] = data_i[125] & sel_one_hot_i[0];
assign data_masked[124] = data_i[124] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[0];
assign data_masked[122] = data_i[122] & sel_one_hot_i[0];
assign data_masked[121] = data_i[121] & sel_one_hot_i[0];
assign data_masked[120] = data_i[120] & sel_one_hot_i[0];
assign data_masked[119] = data_i[119] & sel_one_hot_i[0];
assign data_masked[118] = data_i[118] & sel_one_hot_i[0];
assign data_masked[117] = data_i[117] & sel_one_hot_i[0];
assign data_masked[116] = data_i[116] & sel_one_hot_i[0];
assign data_masked[115] = data_i[115] & sel_one_hot_i[0];
assign data_masked[114] = data_i[114] & sel_one_hot_i[0];
assign data_masked[113] = data_i[113] & sel_one_hot_i[0];
assign data_masked[112] = data_i[112] & sel_one_hot_i[0];
assign data_masked[111] = data_i[111] & sel_one_hot_i[0];
assign data_masked[110] = data_i[110] & sel_one_hot_i[0];
assign data_masked[109] = data_i[109] & sel_one_hot_i[0];
assign data_masked[108] = data_i[108] & sel_one_hot_i[0];
assign data_masked[107] = data_i[107] & sel_one_hot_i[0];
assign data_masked[106] = data_i[106] & sel_one_hot_i[0];
assign data_masked[105] = data_i[105] & sel_one_hot_i[0];
assign data_masked[104] = data_i[104] & sel_one_hot_i[0];
assign data_masked[103] = data_i[103] & sel_one_hot_i[0];
assign data_masked[102] = data_i[102] & sel_one_hot_i[0];
assign data_masked[101] = data_i[101] & sel_one_hot_i[0];
assign data_masked[100] = data_i[100] & sel_one_hot_i[0];
assign data_masked[99] = data_i[99] & sel_one_hot_i[0];
assign data_masked[98] = data_i[98] & sel_one_hot_i[0];
assign data_masked[97] = data_i[97] & sel_one_hot_i[0];
assign data_masked[96] = data_i[96] & sel_one_hot_i[0];
assign data_masked[95] = data_i[95] & sel_one_hot_i[0];
assign data_masked[94] = data_i[94] & sel_one_hot_i[0];
assign data_masked[93] = data_i[93] & sel_one_hot_i[0];
assign data_masked[92] = data_i[92] & sel_one_hot_i[0];
assign data_masked[91] = data_i[91] & sel_one_hot_i[0];
assign data_masked[90] = data_i[90] & sel_one_hot_i[0];
assign data_masked[89] = data_i[89] & sel_one_hot_i[0];
assign data_masked[88] = data_i[88] & sel_one_hot_i[0];
assign data_masked[87] = data_i[87] & sel_one_hot_i[0];
assign data_masked[86] = data_i[86] & sel_one_hot_i[0];
assign data_masked[85] = data_i[85] & sel_one_hot_i[0];
assign data_masked[84] = data_i[84] & sel_one_hot_i[0];
assign data_masked[83] = data_i[83] & sel_one_hot_i[0];
assign data_masked[82] = data_i[82] & sel_one_hot_i[0];
assign data_masked[81] = data_i[81] & sel_one_hot_i[0];
assign data_masked[80] = data_i[80] & sel_one_hot_i[0];
assign data_masked[79] = data_i[79] & sel_one_hot_i[0];
assign data_masked[78] = data_i[78] & sel_one_hot_i[0];
assign data_masked[77] = data_i[77] & sel_one_hot_i[0];
assign data_masked[76] = data_i[76] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[255] = data_i[255] & sel_one_hot_i[1];
assign data_masked[254] = data_i[254] & sel_one_hot_i[1];
assign data_masked[253] = data_i[253] & sel_one_hot_i[1];
assign data_masked[252] = data_i[252] & sel_one_hot_i[1];
assign data_masked[251] = data_i[251] & sel_one_hot_i[1];
assign data_masked[250] = data_i[250] & sel_one_hot_i[1];
assign data_masked[249] = data_i[249] & sel_one_hot_i[1];
assign data_masked[248] = data_i[248] & sel_one_hot_i[1];
assign data_masked[247] = data_i[247] & sel_one_hot_i[1];
assign data_masked[246] = data_i[246] & sel_one_hot_i[1];
assign data_masked[245] = data_i[245] & sel_one_hot_i[1];
assign data_masked[244] = data_i[244] & sel_one_hot_i[1];
assign data_masked[243] = data_i[243] & sel_one_hot_i[1];
assign data_masked[242] = data_i[242] & sel_one_hot_i[1];
assign data_masked[241] = data_i[241] & sel_one_hot_i[1];
assign data_masked[240] = data_i[240] & sel_one_hot_i[1];
assign data_masked[239] = data_i[239] & sel_one_hot_i[1];
assign data_masked[238] = data_i[238] & sel_one_hot_i[1];
assign data_masked[237] = data_i[237] & sel_one_hot_i[1];
assign data_masked[236] = data_i[236] & sel_one_hot_i[1];
assign data_masked[235] = data_i[235] & sel_one_hot_i[1];
assign data_masked[234] = data_i[234] & sel_one_hot_i[1];
assign data_masked[233] = data_i[233] & sel_one_hot_i[1];
assign data_masked[232] = data_i[232] & sel_one_hot_i[1];
assign data_masked[231] = data_i[231] & sel_one_hot_i[1];
assign data_masked[230] = data_i[230] & sel_one_hot_i[1];
assign data_masked[229] = data_i[229] & sel_one_hot_i[1];
assign data_masked[228] = data_i[228] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[1];
assign data_masked[226] = data_i[226] & sel_one_hot_i[1];
assign data_masked[225] = data_i[225] & sel_one_hot_i[1];
assign data_masked[224] = data_i[224] & sel_one_hot_i[1];
assign data_masked[223] = data_i[223] & sel_one_hot_i[1];
assign data_masked[222] = data_i[222] & sel_one_hot_i[1];
assign data_masked[221] = data_i[221] & sel_one_hot_i[1];
assign data_masked[220] = data_i[220] & sel_one_hot_i[1];
assign data_masked[219] = data_i[219] & sel_one_hot_i[1];
assign data_masked[218] = data_i[218] & sel_one_hot_i[1];
assign data_masked[217] = data_i[217] & sel_one_hot_i[1];
assign data_masked[216] = data_i[216] & sel_one_hot_i[1];
assign data_masked[215] = data_i[215] & sel_one_hot_i[1];
assign data_masked[214] = data_i[214] & sel_one_hot_i[1];
assign data_masked[213] = data_i[213] & sel_one_hot_i[1];
assign data_masked[212] = data_i[212] & sel_one_hot_i[1];
assign data_masked[211] = data_i[211] & sel_one_hot_i[1];
assign data_masked[210] = data_i[210] & sel_one_hot_i[1];
assign data_masked[209] = data_i[209] & sel_one_hot_i[1];
assign data_masked[208] = data_i[208] & sel_one_hot_i[1];
assign data_masked[207] = data_i[207] & sel_one_hot_i[1];
assign data_masked[206] = data_i[206] & sel_one_hot_i[1];
assign data_masked[205] = data_i[205] & sel_one_hot_i[1];
assign data_masked[204] = data_i[204] & sel_one_hot_i[1];
assign data_masked[203] = data_i[203] & sel_one_hot_i[1];
assign data_masked[202] = data_i[202] & sel_one_hot_i[1];
assign data_masked[201] = data_i[201] & sel_one_hot_i[1];
assign data_masked[200] = data_i[200] & sel_one_hot_i[1];
assign data_masked[199] = data_i[199] & sel_one_hot_i[1];
assign data_masked[198] = data_i[198] & sel_one_hot_i[1];
assign data_masked[197] = data_i[197] & sel_one_hot_i[1];
assign data_masked[196] = data_i[196] & sel_one_hot_i[1];
assign data_masked[195] = data_i[195] & sel_one_hot_i[1];
assign data_masked[194] = data_i[194] & sel_one_hot_i[1];
assign data_masked[193] = data_i[193] & sel_one_hot_i[1];
assign data_masked[192] = data_i[192] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[1];
assign data_masked[190] = data_i[190] & sel_one_hot_i[1];
assign data_masked[189] = data_i[189] & sel_one_hot_i[1];
assign data_masked[188] = data_i[188] & sel_one_hot_i[1];
assign data_masked[187] = data_i[187] & sel_one_hot_i[1];
assign data_masked[186] = data_i[186] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[1];
assign data_masked[184] = data_i[184] & sel_one_hot_i[1];
assign data_masked[183] = data_i[183] & sel_one_hot_i[1];
assign data_masked[182] = data_i[182] & sel_one_hot_i[1];
assign data_masked[181] = data_i[181] & sel_one_hot_i[1];
assign data_masked[180] = data_i[180] & sel_one_hot_i[1];
assign data_masked[179] = data_i[179] & sel_one_hot_i[1];
assign data_masked[178] = data_i[178] & sel_one_hot_i[1];
assign data_masked[177] = data_i[177] & sel_one_hot_i[1];
assign data_masked[176] = data_i[176] & sel_one_hot_i[1];
assign data_masked[175] = data_i[175] & sel_one_hot_i[1];
assign data_masked[174] = data_i[174] & sel_one_hot_i[1];
assign data_masked[173] = data_i[173] & sel_one_hot_i[1];
assign data_masked[172] = data_i[172] & sel_one_hot_i[1];
assign data_masked[171] = data_i[171] & sel_one_hot_i[1];
assign data_masked[170] = data_i[170] & sel_one_hot_i[1];
assign data_masked[169] = data_i[169] & sel_one_hot_i[1];
assign data_masked[168] = data_i[168] & sel_one_hot_i[1];
assign data_masked[167] = data_i[167] & sel_one_hot_i[1];
assign data_masked[166] = data_i[166] & sel_one_hot_i[1];
assign data_masked[165] = data_i[165] & sel_one_hot_i[1];
assign data_masked[164] = data_i[164] & sel_one_hot_i[1];
assign data_masked[163] = data_i[163] & sel_one_hot_i[1];
assign data_masked[162] = data_i[162] & sel_one_hot_i[1];
assign data_masked[161] = data_i[161] & sel_one_hot_i[1];
assign data_masked[160] = data_i[160] & sel_one_hot_i[1];
assign data_masked[159] = data_i[159] & sel_one_hot_i[1];
assign data_masked[158] = data_i[158] & sel_one_hot_i[1];
assign data_masked[157] = data_i[157] & sel_one_hot_i[1];
assign data_masked[156] = data_i[156] & sel_one_hot_i[1];
assign data_masked[155] = data_i[155] & sel_one_hot_i[1];
assign data_masked[154] = data_i[154] & sel_one_hot_i[1];
assign data_masked[153] = data_i[153] & sel_one_hot_i[1];
assign data_masked[152] = data_i[152] & sel_one_hot_i[1];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_o[0] = data_masked[128] | data_masked[0];
assign data_o[1] = data_masked[129] | data_masked[1];
assign data_o[2] = data_masked[130] | data_masked[2];
assign data_o[3] = data_masked[131] | data_masked[3];
assign data_o[4] = data_masked[132] | data_masked[4];
assign data_o[5] = data_masked[133] | data_masked[5];
assign data_o[6] = data_masked[134] | data_masked[6];
assign data_o[7] = data_masked[135] | data_masked[7];
assign data_o[8] = data_masked[136] | data_masked[8];
assign data_o[9] = data_masked[137] | data_masked[9];
assign data_o[10] = data_masked[138] | data_masked[10];
assign data_o[11] = data_masked[139] | data_masked[11];
assign data_o[12] = data_masked[140] | data_masked[12];
assign data_o[13] = data_masked[141] | data_masked[13];
assign data_o[14] = data_masked[142] | data_masked[14];
assign data_o[15] = data_masked[143] | data_masked[15];
assign data_o[16] = data_masked[144] | data_masked[16];
assign data_o[17] = data_masked[145] | data_masked[17];
assign data_o[18] = data_masked[146] | data_masked[18];
assign data_o[19] = data_masked[147] | data_masked[19];
assign data_o[20] = data_masked[148] | data_masked[20];
assign data_o[21] = data_masked[149] | data_masked[21];
assign data_o[22] = data_masked[150] | data_masked[22];
assign data_o[23] = data_masked[151] | data_masked[23];
assign data_o[24] = data_masked[152] | data_masked[24];
assign data_o[25] = data_masked[153] | data_masked[25];
assign data_o[26] = data_masked[154] | data_masked[26];
assign data_o[27] = data_masked[155] | data_masked[27];
assign data_o[28] = data_masked[156] | data_masked[28];
assign data_o[29] = data_masked[157] | data_masked[29];
assign data_o[30] = data_masked[158] | data_masked[30];
assign data_o[31] = data_masked[159] | data_masked[31];
assign data_o[32] = data_masked[160] | data_masked[32];
assign data_o[33] = data_masked[161] | data_masked[33];
assign data_o[34] = data_masked[162] | data_masked[34];
assign data_o[35] = data_masked[163] | data_masked[35];
assign data_o[36] = data_masked[164] | data_masked[36];
assign data_o[37] = data_masked[165] | data_masked[37];
assign data_o[38] = data_masked[166] | data_masked[38];
assign data_o[39] = data_masked[167] | data_masked[39];
assign data_o[40] = data_masked[168] | data_masked[40];
assign data_o[41] = data_masked[169] | data_masked[41];
assign data_o[42] = data_masked[170] | data_masked[42];
assign data_o[43] = data_masked[171] | data_masked[43];
assign data_o[44] = data_masked[172] | data_masked[44];
assign data_o[45] = data_masked[173] | data_masked[45];
assign data_o[46] = data_masked[174] | data_masked[46];
assign data_o[47] = data_masked[175] | data_masked[47];
assign data_o[48] = data_masked[176] | data_masked[48];
assign data_o[49] = data_masked[177] | data_masked[49];
assign data_o[50] = data_masked[178] | data_masked[50];
assign data_o[51] = data_masked[179] | data_masked[51];
assign data_o[52] = data_masked[180] | data_masked[52];
assign data_o[53] = data_masked[181] | data_masked[53];
assign data_o[54] = data_masked[182] | data_masked[54];
assign data_o[55] = data_masked[183] | data_masked[55];
assign data_o[56] = data_masked[184] | data_masked[56];
assign data_o[57] = data_masked[185] | data_masked[57];
assign data_o[58] = data_masked[186] | data_masked[58];
assign data_o[59] = data_masked[187] | data_masked[59];
assign data_o[60] = data_masked[188] | data_masked[60];
assign data_o[61] = data_masked[189] | data_masked[61];
assign data_o[62] = data_masked[190] | data_masked[62];
assign data_o[63] = data_masked[191] | data_masked[63];
assign data_o[64] = data_masked[192] | data_masked[64];
assign data_o[65] = data_masked[193] | data_masked[65];
assign data_o[66] = data_masked[194] | data_masked[66];
assign data_o[67] = data_masked[195] | data_masked[67];
assign data_o[68] = data_masked[196] | data_masked[68];
assign data_o[69] = data_masked[197] | data_masked[69];
assign data_o[70] = data_masked[198] | data_masked[70];
assign data_o[71] = data_masked[199] | data_masked[71];
assign data_o[72] = data_masked[200] | data_masked[72];
assign data_o[73] = data_masked[201] | data_masked[73];
assign data_o[74] = data_masked[202] | data_masked[74];
assign data_o[75] = data_masked[203] | data_masked[75];
assign data_o[76] = data_masked[204] | data_masked[76];
assign data_o[77] = data_masked[205] | data_masked[77];
assign data_o[78] = data_masked[206] | data_masked[78];
assign data_o[79] = data_masked[207] | data_masked[79];
assign data_o[80] = data_masked[208] | data_masked[80];
assign data_o[81] = data_masked[209] | data_masked[81];
assign data_o[82] = data_masked[210] | data_masked[82];
assign data_o[83] = data_masked[211] | data_masked[83];
assign data_o[84] = data_masked[212] | data_masked[84];
assign data_o[85] = data_masked[213] | data_masked[85];
assign data_o[86] = data_masked[214] | data_masked[86];
assign data_o[87] = data_masked[215] | data_masked[87];
assign data_o[88] = data_masked[216] | data_masked[88];
assign data_o[89] = data_masked[217] | data_masked[89];
assign data_o[90] = data_masked[218] | data_masked[90];
assign data_o[91] = data_masked[219] | data_masked[91];
assign data_o[92] = data_masked[220] | data_masked[92];
assign data_o[93] = data_masked[221] | data_masked[93];
assign data_o[94] = data_masked[222] | data_masked[94];
assign data_o[95] = data_masked[223] | data_masked[95];
assign data_o[96] = data_masked[224] | data_masked[96];
assign data_o[97] = data_masked[225] | data_masked[97];
assign data_o[98] = data_masked[226] | data_masked[98];
assign data_o[99] = data_masked[227] | data_masked[99];
assign data_o[100] = data_masked[228] | data_masked[100];
assign data_o[101] = data_masked[229] | data_masked[101];
assign data_o[102] = data_masked[230] | data_masked[102];
assign data_o[103] = data_masked[231] | data_masked[103];
assign data_o[104] = data_masked[232] | data_masked[104];
assign data_o[105] = data_masked[233] | data_masked[105];
assign data_o[106] = data_masked[234] | data_masked[106];
assign data_o[107] = data_masked[235] | data_masked[107];
assign data_o[108] = data_masked[236] | data_masked[108];
assign data_o[109] = data_masked[237] | data_masked[109];
assign data_o[110] = data_masked[238] | data_masked[110];
assign data_o[111] = data_masked[239] | data_masked[111];
assign data_o[112] = data_masked[240] | data_masked[112];
assign data_o[113] = data_masked[241] | data_masked[113];
assign data_o[114] = data_masked[242] | data_masked[114];
assign data_o[115] = data_masked[243] | data_masked[115];
assign data_o[116] = data_masked[244] | data_masked[116];
assign data_o[117] = data_masked[245] | data_masked[117];
assign data_o[118] = data_masked[246] | data_masked[118];
assign data_o[119] = data_masked[247] | data_masked[119];
assign data_o[120] = data_masked[248] | data_masked[120];
assign data_o[121] = data_masked[249] | data_masked[121];
assign data_o[122] = data_masked[250] | data_masked[122];
assign data_o[123] = data_masked[251] | data_masked[123];
assign data_o[124] = data_masked[252] | data_masked[124];
assign data_o[125] = data_masked[253] | data_masked[125];
assign data_o[126] = data_masked[254] | data_masked[126];
assign data_o[127] = data_masked[255] | data_masked[127];
endmodule |
module bsg_counter_up_down_max_val_p9_init_val_p0_max_step_p1
(
clk_i,
reset_i,
up_i,
down_i,
count_o
);
input [0:0] up_i;
input [0:0] down_i;
output [3:0] count_o;
input clk_i;
input reset_i;
wire [3:0] count_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
reg count_o_3_sv2v_reg,count_o_2_sv2v_reg,count_o_1_sv2v_reg,count_o_0_sv2v_reg;
assign count_o[3] = count_o_3_sv2v_reg;
assign count_o[2] = count_o_2_sv2v_reg;
assign count_o[1] = count_o_1_sv2v_reg;
assign count_o[0] = count_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
count_o_3_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_2_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_1_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_0_sv2v_reg <= N11;
end
end
assign { N6, N5, N4, N3 } = count_o - down_i[0];
assign { N10, N9, N8, N7 } = { N6, N5, N4, N3 } + up_i[0];
assign { N14, N13, N12, N11 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N10, N9, N8, N7 } : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_tag_master_els_p9_lg_width_p4
(
clk_i,
en_i,
data_i,
clients_r_o
);
output [35:0] clients_r_o;
input clk_i;
input en_i;
input data_i;
wire [35:0] clients_r_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,clients_r_o_0__clk_,clients_r_o_0__en_,data_i_r,_1_net_,
_2_net_,N8,v_n,bsg_tag_n_op_,bsg_tag_n_param_,N9,N10,N11,N12,N13,N14,N15,N16,
N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,
N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67;
wire [5:0] zeros_ctr_r;
wire [1:0] state_r,state_n;
wire [4:0] hdr_ptr_r,hdr_ptr_n;
wire [8:0] hdr_r,hdr_n,clients_decode;
reg data_i_r_sv2v_reg,hdr_ptr_r_4_sv2v_reg,hdr_ptr_r_3_sv2v_reg,
hdr_ptr_r_2_sv2v_reg,hdr_ptr_r_1_sv2v_reg,hdr_ptr_r_0_sv2v_reg,state_r_1_sv2v_reg,
state_r_0_sv2v_reg,hdr_r_8_sv2v_reg,hdr_r_7_sv2v_reg,hdr_r_6_sv2v_reg,hdr_r_5_sv2v_reg,
hdr_r_4_sv2v_reg,hdr_r_3_sv2v_reg,hdr_r_2_sv2v_reg,hdr_r_1_sv2v_reg,hdr_r_0_sv2v_reg,
clients_r_o_2_sv2v_reg,clients_r_o_1_sv2v_reg,clients_r_o_6_sv2v_reg,
clients_r_o_5_sv2v_reg,clients_r_o_10_sv2v_reg,clients_r_o_9_sv2v_reg,clients_r_o_14_sv2v_reg,
clients_r_o_13_sv2v_reg,clients_r_o_18_sv2v_reg,clients_r_o_17_sv2v_reg,
clients_r_o_22_sv2v_reg,clients_r_o_21_sv2v_reg,clients_r_o_26_sv2v_reg,
clients_r_o_25_sv2v_reg,clients_r_o_30_sv2v_reg,clients_r_o_29_sv2v_reg,clients_r_o_34_sv2v_reg,
clients_r_o_33_sv2v_reg;
assign data_i_r = data_i_r_sv2v_reg;
assign hdr_ptr_r[4] = hdr_ptr_r_4_sv2v_reg;
assign hdr_ptr_r[3] = hdr_ptr_r_3_sv2v_reg;
assign hdr_ptr_r[2] = hdr_ptr_r_2_sv2v_reg;
assign hdr_ptr_r[1] = hdr_ptr_r_1_sv2v_reg;
assign hdr_ptr_r[0] = hdr_ptr_r_0_sv2v_reg;
assign state_r[1] = state_r_1_sv2v_reg;
assign state_r[0] = state_r_0_sv2v_reg;
assign hdr_r[8] = hdr_r_8_sv2v_reg;
assign hdr_r[7] = hdr_r_7_sv2v_reg;
assign hdr_r[6] = hdr_r_6_sv2v_reg;
assign hdr_r[5] = hdr_r_5_sv2v_reg;
assign hdr_r[4] = hdr_r_4_sv2v_reg;
assign hdr_r[3] = hdr_r_3_sv2v_reg;
assign hdr_r[2] = hdr_r_2_sv2v_reg;
assign hdr_r[1] = hdr_r_1_sv2v_reg;
assign hdr_r[0] = hdr_r_0_sv2v_reg;
assign clients_r_o[2] = clients_r_o_2_sv2v_reg;
assign clients_r_o[1] = clients_r_o_1_sv2v_reg;
assign clients_r_o[6] = clients_r_o_6_sv2v_reg;
assign clients_r_o[5] = clients_r_o_5_sv2v_reg;
assign clients_r_o[10] = clients_r_o_10_sv2v_reg;
assign clients_r_o[9] = clients_r_o_9_sv2v_reg;
assign clients_r_o[14] = clients_r_o_14_sv2v_reg;
assign clients_r_o[13] = clients_r_o_13_sv2v_reg;
assign clients_r_o[18] = clients_r_o_18_sv2v_reg;
assign clients_r_o[17] = clients_r_o_17_sv2v_reg;
assign clients_r_o[22] = clients_r_o_22_sv2v_reg;
assign clients_r_o[21] = clients_r_o_21_sv2v_reg;
assign clients_r_o[26] = clients_r_o_26_sv2v_reg;
assign clients_r_o[25] = clients_r_o_25_sv2v_reg;
assign clients_r_o[30] = clients_r_o_30_sv2v_reg;
assign clients_r_o[29] = clients_r_o_29_sv2v_reg;
assign clients_r_o[34] = clients_r_o_34_sv2v_reg;
assign clients_r_o[33] = clients_r_o_33_sv2v_reg;
assign clients_r_o_0__clk_ = clk_i;
assign clients_r_o[35] = clients_r_o_0__clk_;
assign clients_r_o[31] = clients_r_o_0__clk_;
assign clients_r_o[27] = clients_r_o_0__clk_;
assign clients_r_o[23] = clients_r_o_0__clk_;
assign clients_r_o[19] = clients_r_o_0__clk_;
assign clients_r_o[15] = clients_r_o_0__clk_;
assign clients_r_o[11] = clients_r_o_0__clk_;
assign clients_r_o[7] = clients_r_o_0__clk_;
assign clients_r_o[3] = clients_r_o_0__clk_;
assign clients_r_o_0__en_ = en_i;
assign clients_r_o[32] = clients_r_o_0__en_;
assign clients_r_o[28] = clients_r_o_0__en_;
assign clients_r_o[24] = clients_r_o_0__en_;
assign clients_r_o[20] = clients_r_o_0__en_;
assign clients_r_o[16] = clients_r_o_0__en_;
assign clients_r_o[12] = clients_r_o_0__en_;
assign clients_r_o[8] = clients_r_o_0__en_;
assign clients_r_o[4] = clients_r_o_0__en_;
assign clients_r_o[0] = clients_r_o_0__en_;
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
data_i_r_sv2v_reg <= data_i;
end
end
bsg_counter_clear_up_max_val_p63_init_val_p0
bccu
(
.clk_i(clients_r_o_0__clk_),
.reset_i(1'b0),
.clear_i(_1_net_),
.up_i(_2_net_),
.count_o(zeros_ctr_r)
);
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
hdr_ptr_r_4_sv2v_reg <= 1'b0;
end else if(N49) begin
hdr_ptr_r_4_sv2v_reg <= hdr_ptr_n[4];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
hdr_ptr_r_3_sv2v_reg <= 1'b0;
end else if(N49) begin
hdr_ptr_r_3_sv2v_reg <= hdr_ptr_n[3];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
hdr_ptr_r_2_sv2v_reg <= 1'b0;
end else if(N49) begin
hdr_ptr_r_2_sv2v_reg <= hdr_ptr_n[2];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
hdr_ptr_r_1_sv2v_reg <= 1'b0;
end else if(N49) begin
hdr_ptr_r_1_sv2v_reg <= hdr_ptr_n[1];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
hdr_ptr_r_0_sv2v_reg <= 1'b0;
end else if(N49) begin
hdr_ptr_r_0_sv2v_reg <= hdr_ptr_n[0];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
state_r_1_sv2v_reg <= 1'b0;
end else if(N51) begin
state_r_1_sv2v_reg <= state_n[1];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N8) begin
state_r_0_sv2v_reg <= 1'b0;
end else if(N51) begin
state_r_0_sv2v_reg <= state_n[0];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N49) begin
hdr_r_8_sv2v_reg <= hdr_n[8];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N49) begin
hdr_r_7_sv2v_reg <= hdr_n[7];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N49) begin
hdr_r_6_sv2v_reg <= hdr_n[6];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N49) begin
hdr_r_5_sv2v_reg <= hdr_n[5];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N49) begin
hdr_r_4_sv2v_reg <= hdr_n[4];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N52) begin
hdr_r_3_sv2v_reg <= hdr_n[3];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N52) begin
hdr_r_2_sv2v_reg <= hdr_n[2];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N52) begin
hdr_r_1_sv2v_reg <= hdr_n[1];
end
end
always @(posedge clients_r_o_0__clk_) begin
if(N52) begin
hdr_r_0_sv2v_reg <= hdr_n[0];
end
end
assign N11 = N9 & N10;
assign N12 = state_r[1] | N10;
assign N14 = N9 | state_r[0];
assign N16 = state_r[1] & state_r[0];
assign clients_decode = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, v_n } << hdr_r[8:5];
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_2_sv2v_reg <= N30;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_1_sv2v_reg <= N31;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_6_sv2v_reg <= N32;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_5_sv2v_reg <= N33;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_10_sv2v_reg <= N34;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_9_sv2v_reg <= N35;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_14_sv2v_reg <= N36;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_13_sv2v_reg <= N37;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_18_sv2v_reg <= N38;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_17_sv2v_reg <= N39;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_22_sv2v_reg <= N40;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_21_sv2v_reg <= N41;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_26_sv2v_reg <= N42;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_25_sv2v_reg <= N43;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_30_sv2v_reg <= N44;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_29_sv2v_reg <= N45;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_34_sv2v_reg <= N46;
end
end
always @(posedge clients_r_o_0__clk_) begin
if(1'b1) begin
clients_r_o_33_sv2v_reg <= N47;
end
end
assign N53 = ~hdr_r[0];
assign N54 = hdr_r[2] | hdr_r[3];
assign N55 = hdr_r[1] | N54;
assign N56 = N53 | N55;
assign N57 = ~N56;
assign N58 = hdr_r[3] | hdr_r[4];
assign N59 = hdr_r[2] | N58;
assign N60 = hdr_r[1] | N59;
assign N61 = ~hdr_ptr_r[3];
assign N62 = N61 | hdr_ptr_r[4];
assign N63 = hdr_ptr_r[2] | N62;
assign N64 = hdr_ptr_r[1] | N63;
assign N65 = hdr_ptr_r[0] | N64;
assign N66 = ~N65;
assign { N21, N20, N19, N18, N17 } = hdr_ptr_r + 1'b1;
assign { N29, N28, N27, N26 } = hdr_r[3:0] - 1'b1;
assign { N23, N22 } = (N0)? { N60, 1'b0 } :
(N1)? state_r : 1'b0;
assign N0 = N66;
assign N1 = N65;
assign { N25, N24 } = (N2)? { 1'b0, 1'b0 } :
(N3)? state_r : 1'b0;
assign N2 = N57;
assign N3 = N56;
assign state_n = (N4)? { 1'b0, 1'b1 } :
(N5)? { N23, N22 } :
(N6)? { N25, N24 } :
(N7)? { 1'b1, 1'b1 } : 1'b0;
assign N4 = N11;
assign N5 = N13;
assign N6 = N15;
assign N7 = N16;
assign hdr_ptr_n = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N5)? { N21, N20, N19, N18, N17 } : 1'b0;
assign hdr_n[3:0] = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N5)? hdr_r[4:1] :
(N6)? { N29, N28, N27, N26 } : 1'b0;
assign hdr_n[8:4] = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N5)? { data_i_r, hdr_r[8:5] } : 1'b0;
assign v_n = (N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b1 :
(N7)? 1'b0 : 1'b0;
assign { bsg_tag_n_op_, bsg_tag_n_param_ } = (N4)? { 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b0 } :
(N6)? { hdr_r[4:4], data_i_r } :
(N7)? { 1'b0, 1'b0 } : 1'b0;
assign _2_net_ = ~data_i_r;
assign _1_net_ = data_i_r | zeros_ctr_r[5];
assign N8 = zeros_ctr_r[5] & N67;
assign N67 = ~data_i_r;
assign N9 = ~state_r[1];
assign N10 = ~state_r[0];
assign N13 = ~N12;
assign N15 = ~N14;
assign N30 = clients_decode[0] & bsg_tag_n_op_;
assign N31 = clients_decode[0] & bsg_tag_n_param_;
assign N32 = clients_decode[1] & bsg_tag_n_op_;
assign N33 = clients_decode[1] & bsg_tag_n_param_;
assign N34 = clients_decode[2] & bsg_tag_n_op_;
assign N35 = clients_decode[2] & bsg_tag_n_param_;
assign N36 = clients_decode[3] & bsg_tag_n_op_;
assign N37 = clients_decode[3] & bsg_tag_n_param_;
assign N38 = clients_decode[4] & bsg_tag_n_op_;
assign N39 = clients_decode[4] & bsg_tag_n_param_;
assign N40 = clients_decode[5] & bsg_tag_n_op_;
assign N41 = clients_decode[5] & bsg_tag_n_param_;
assign N42 = clients_decode[6] & bsg_tag_n_op_;
assign N43 = clients_decode[6] & bsg_tag_n_param_;
assign N44 = clients_decode[7] & bsg_tag_n_op_;
assign N45 = clients_decode[7] & bsg_tag_n_param_;
assign N46 = clients_decode[8] & bsg_tag_n_op_;
assign N47 = clients_decode[8] & bsg_tag_n_param_;
assign N48 = N15 | N16;
assign N49 = ~N48;
assign N50 = N67 & N11;
assign N51 = ~N50;
assign N52 = ~N16;
endmodule |
module bsg_counter_up_down_variable_max_val_p64_init_val_p64_max_step_p64
(
clk_i,
reset_i,
up_i,
down_i,
count_o
);
input [6:0] up_i;
input [6:0] down_i;
output [6:0] count_o;
input clk_i;
input reset_i;
wire [6:0] count_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23;
reg count_o_6_sv2v_reg,count_o_5_sv2v_reg,count_o_4_sv2v_reg,count_o_3_sv2v_reg,
count_o_2_sv2v_reg,count_o_1_sv2v_reg,count_o_0_sv2v_reg;
assign count_o[6] = count_o_6_sv2v_reg;
assign count_o[5] = count_o_5_sv2v_reg;
assign count_o[4] = count_o_4_sv2v_reg;
assign count_o[3] = count_o_3_sv2v_reg;
assign count_o[2] = count_o_2_sv2v_reg;
assign count_o[1] = count_o_1_sv2v_reg;
assign count_o[0] = count_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
count_o_6_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_5_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_4_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_3_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_2_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_1_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_0_sv2v_reg <= N17;
end
end
assign { N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i;
assign { N16, N15, N14, N13, N12, N11, N10 } = { N9, N8, N7, N6, N5, N4, N3 } + up_i;
assign { N23, N22, N21, N20, N19, N18, N17 } = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N16, N15, N14, N13, N12, N11, N10 } : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_circular_ptr_slots_p8_max_add_p1
(
clk,
reset_i,
add_i,
o,
n_o
);
input [0:0] add_i;
output [2:0] o;
output [2:0] n_o;
input clk;
input reset_i;
wire [2:0] o,n_o,genblk1_genblk1_ptr_r_p1;
wire N0,N1,N2;
reg o_2_sv2v_reg,o_1_sv2v_reg,o_0_sv2v_reg;
assign o[2] = o_2_sv2v_reg;
assign o[1] = o_1_sv2v_reg;
assign o[0] = o_0_sv2v_reg;
always @(posedge clk) begin
if(reset_i) begin
o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_2_sv2v_reg <= n_o[2];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_1_sv2v_reg <= n_o[1];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_0_sv2v_reg <= n_o[0];
end
end
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign n_o = (N0)? genblk1_genblk1_ptr_r_p1 :
(N1)? o : 1'b0;
assign N0 = add_i[0];
assign N1 = N2;
assign N2 = ~add_i[0];
endmodule |
module bsg_parallel_in_serial_out_width_p16_els_p4
(
clk_i,
reset_i,
valid_i,
data_i,
ready_o,
valid_o,
data_o,
yumi_i
);
input [63:0] data_i;
output [15:0] data_o;
input clk_i;
input reset_i;
input valid_i;
input yumi_i;
output ready_o;
output valid_o;
wire [15:0] data_o;
wire ready_o,valid_o,N0,N1,piso_done_tx_n,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,
N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27;
wire [1:0] piso_shift_ctr_r;
wire [0:0] piso_state_n;
wire [63:0] piso_data_r;
reg valid_o_sv2v_reg,piso_data_r_63_sv2v_reg,piso_data_r_62_sv2v_reg,
piso_data_r_61_sv2v_reg,piso_data_r_60_sv2v_reg,piso_data_r_59_sv2v_reg,
piso_data_r_58_sv2v_reg,piso_data_r_57_sv2v_reg,piso_data_r_56_sv2v_reg,piso_data_r_55_sv2v_reg,
piso_data_r_54_sv2v_reg,piso_data_r_53_sv2v_reg,piso_data_r_52_sv2v_reg,
piso_data_r_51_sv2v_reg,piso_data_r_50_sv2v_reg,piso_data_r_49_sv2v_reg,
piso_data_r_48_sv2v_reg,piso_data_r_47_sv2v_reg,piso_data_r_46_sv2v_reg,piso_data_r_45_sv2v_reg,
piso_data_r_44_sv2v_reg,piso_data_r_43_sv2v_reg,piso_data_r_42_sv2v_reg,
piso_data_r_41_sv2v_reg,piso_data_r_40_sv2v_reg,piso_data_r_39_sv2v_reg,
piso_data_r_38_sv2v_reg,piso_data_r_37_sv2v_reg,piso_data_r_36_sv2v_reg,piso_data_r_35_sv2v_reg,
piso_data_r_34_sv2v_reg,piso_data_r_33_sv2v_reg,piso_data_r_32_sv2v_reg,
piso_data_r_31_sv2v_reg,piso_data_r_30_sv2v_reg,piso_data_r_29_sv2v_reg,
piso_data_r_28_sv2v_reg,piso_data_r_27_sv2v_reg,piso_data_r_26_sv2v_reg,piso_data_r_25_sv2v_reg,
piso_data_r_24_sv2v_reg,piso_data_r_23_sv2v_reg,piso_data_r_22_sv2v_reg,
piso_data_r_21_sv2v_reg,piso_data_r_20_sv2v_reg,piso_data_r_19_sv2v_reg,
piso_data_r_18_sv2v_reg,piso_data_r_17_sv2v_reg,piso_data_r_16_sv2v_reg,piso_data_r_15_sv2v_reg,
piso_data_r_14_sv2v_reg,piso_data_r_13_sv2v_reg,piso_data_r_12_sv2v_reg,
piso_data_r_11_sv2v_reg,piso_data_r_10_sv2v_reg,piso_data_r_9_sv2v_reg,piso_data_r_8_sv2v_reg,
piso_data_r_7_sv2v_reg,piso_data_r_6_sv2v_reg,piso_data_r_5_sv2v_reg,
piso_data_r_4_sv2v_reg,piso_data_r_3_sv2v_reg,piso_data_r_2_sv2v_reg,piso_data_r_1_sv2v_reg,
piso_data_r_0_sv2v_reg,piso_shift_ctr_r_1_sv2v_reg,piso_shift_ctr_r_0_sv2v_reg;
assign valid_o = valid_o_sv2v_reg;
assign piso_data_r[63] = piso_data_r_63_sv2v_reg;
assign piso_data_r[62] = piso_data_r_62_sv2v_reg;
assign piso_data_r[61] = piso_data_r_61_sv2v_reg;
assign piso_data_r[60] = piso_data_r_60_sv2v_reg;
assign piso_data_r[59] = piso_data_r_59_sv2v_reg;
assign piso_data_r[58] = piso_data_r_58_sv2v_reg;
assign piso_data_r[57] = piso_data_r_57_sv2v_reg;
assign piso_data_r[56] = piso_data_r_56_sv2v_reg;
assign piso_data_r[55] = piso_data_r_55_sv2v_reg;
assign piso_data_r[54] = piso_data_r_54_sv2v_reg;
assign piso_data_r[53] = piso_data_r_53_sv2v_reg;
assign piso_data_r[52] = piso_data_r_52_sv2v_reg;
assign piso_data_r[51] = piso_data_r_51_sv2v_reg;
assign piso_data_r[50] = piso_data_r_50_sv2v_reg;
assign piso_data_r[49] = piso_data_r_49_sv2v_reg;
assign piso_data_r[48] = piso_data_r_48_sv2v_reg;
assign piso_data_r[47] = piso_data_r_47_sv2v_reg;
assign piso_data_r[46] = piso_data_r_46_sv2v_reg;
assign piso_data_r[45] = piso_data_r_45_sv2v_reg;
assign piso_data_r[44] = piso_data_r_44_sv2v_reg;
assign piso_data_r[43] = piso_data_r_43_sv2v_reg;
assign piso_data_r[42] = piso_data_r_42_sv2v_reg;
assign piso_data_r[41] = piso_data_r_41_sv2v_reg;
assign piso_data_r[40] = piso_data_r_40_sv2v_reg;
assign piso_data_r[39] = piso_data_r_39_sv2v_reg;
assign piso_data_r[38] = piso_data_r_38_sv2v_reg;
assign piso_data_r[37] = piso_data_r_37_sv2v_reg;
assign piso_data_r[36] = piso_data_r_36_sv2v_reg;
assign piso_data_r[35] = piso_data_r_35_sv2v_reg;
assign piso_data_r[34] = piso_data_r_34_sv2v_reg;
assign piso_data_r[33] = piso_data_r_33_sv2v_reg;
assign piso_data_r[32] = piso_data_r_32_sv2v_reg;
assign piso_data_r[31] = piso_data_r_31_sv2v_reg;
assign piso_data_r[30] = piso_data_r_30_sv2v_reg;
assign piso_data_r[29] = piso_data_r_29_sv2v_reg;
assign piso_data_r[28] = piso_data_r_28_sv2v_reg;
assign piso_data_r[27] = piso_data_r_27_sv2v_reg;
assign piso_data_r[26] = piso_data_r_26_sv2v_reg;
assign piso_data_r[25] = piso_data_r_25_sv2v_reg;
assign piso_data_r[24] = piso_data_r_24_sv2v_reg;
assign piso_data_r[23] = piso_data_r_23_sv2v_reg;
assign piso_data_r[22] = piso_data_r_22_sv2v_reg;
assign piso_data_r[21] = piso_data_r_21_sv2v_reg;
assign piso_data_r[20] = piso_data_r_20_sv2v_reg;
assign piso_data_r[19] = piso_data_r_19_sv2v_reg;
assign piso_data_r[18] = piso_data_r_18_sv2v_reg;
assign piso_data_r[17] = piso_data_r_17_sv2v_reg;
assign piso_data_r[16] = piso_data_r_16_sv2v_reg;
assign piso_data_r[15] = piso_data_r_15_sv2v_reg;
assign piso_data_r[14] = piso_data_r_14_sv2v_reg;
assign piso_data_r[13] = piso_data_r_13_sv2v_reg;
assign piso_data_r[12] = piso_data_r_12_sv2v_reg;
assign piso_data_r[11] = piso_data_r_11_sv2v_reg;
assign piso_data_r[10] = piso_data_r_10_sv2v_reg;
assign piso_data_r[9] = piso_data_r_9_sv2v_reg;
assign piso_data_r[8] = piso_data_r_8_sv2v_reg;
assign piso_data_r[7] = piso_data_r_7_sv2v_reg;
assign piso_data_r[6] = piso_data_r_6_sv2v_reg;
assign piso_data_r[5] = piso_data_r_5_sv2v_reg;
assign piso_data_r[4] = piso_data_r_4_sv2v_reg;
assign piso_data_r[3] = piso_data_r_3_sv2v_reg;
assign piso_data_r[2] = piso_data_r_2_sv2v_reg;
assign piso_data_r[1] = piso_data_r_1_sv2v_reg;
assign piso_data_r[0] = piso_data_r_0_sv2v_reg;
assign piso_shift_ctr_r[1] = piso_shift_ctr_r_1_sv2v_reg;
assign piso_shift_ctr_r[0] = piso_shift_ctr_r_0_sv2v_reg;
always @(posedge clk_i) begin
if(reset_i) begin
valid_o_sv2v_reg <= 1'b0;
end else if(N3) begin
valid_o_sv2v_reg <= piso_state_n[0];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_63_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_63_sv2v_reg <= data_i[63];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_62_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_62_sv2v_reg <= data_i[62];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_61_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_61_sv2v_reg <= data_i[61];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_60_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_60_sv2v_reg <= data_i[60];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_59_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_59_sv2v_reg <= data_i[59];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_58_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_58_sv2v_reg <= data_i[58];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_57_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_57_sv2v_reg <= data_i[57];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_56_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_56_sv2v_reg <= data_i[56];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_55_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_55_sv2v_reg <= data_i[55];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_54_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_54_sv2v_reg <= data_i[54];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_53_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_53_sv2v_reg <= data_i[53];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_52_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_52_sv2v_reg <= data_i[52];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_51_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_51_sv2v_reg <= data_i[51];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_50_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_50_sv2v_reg <= data_i[50];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_49_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_49_sv2v_reg <= data_i[49];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_48_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_48_sv2v_reg <= data_i[48];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_47_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_47_sv2v_reg <= data_i[47];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_46_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_46_sv2v_reg <= data_i[46];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_45_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_45_sv2v_reg <= data_i[45];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_44_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_44_sv2v_reg <= data_i[44];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_43_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_43_sv2v_reg <= data_i[43];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_42_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_42_sv2v_reg <= data_i[42];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_41_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_41_sv2v_reg <= data_i[41];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_40_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_40_sv2v_reg <= data_i[40];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_39_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_39_sv2v_reg <= data_i[39];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_38_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_38_sv2v_reg <= data_i[38];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_37_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_37_sv2v_reg <= data_i[37];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_36_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_36_sv2v_reg <= data_i[36];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_35_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_35_sv2v_reg <= data_i[35];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_34_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_34_sv2v_reg <= data_i[34];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_33_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_33_sv2v_reg <= data_i[33];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_32_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_32_sv2v_reg <= data_i[32];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_31_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_31_sv2v_reg <= data_i[31];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_30_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_30_sv2v_reg <= data_i[30];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_29_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_29_sv2v_reg <= data_i[29];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_28_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_28_sv2v_reg <= data_i[28];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_27_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_27_sv2v_reg <= data_i[27];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_26_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_26_sv2v_reg <= data_i[26];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_25_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_25_sv2v_reg <= data_i[25];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_24_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_24_sv2v_reg <= data_i[24];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_23_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_23_sv2v_reg <= data_i[23];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_22_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_22_sv2v_reg <= data_i[22];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_21_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_21_sv2v_reg <= data_i[21];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_20_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_20_sv2v_reg <= data_i[20];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_19_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_19_sv2v_reg <= data_i[19];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_18_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_18_sv2v_reg <= data_i[18];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_17_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_16_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_15_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_14_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_13_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_12_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_11_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_10_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_9_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_8_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_7_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_6_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_5_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_4_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_3_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_2_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_1_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_data_r_0_sv2v_reg <= 1'b0;
end else if(N6) begin
piso_data_r_0_sv2v_reg <= data_i[0];
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_shift_ctr_r_1_sv2v_reg <= 1'b0;
end else if(N22) begin
piso_shift_ctr_r_1_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(reset_i) begin
piso_shift_ctr_r_0_sv2v_reg <= 1'b0;
end else if(N22) begin
piso_shift_ctr_r_0_sv2v_reg <= N9;
end
end
assign data_o[15] = (N17)? piso_data_r[15] :
(N19)? piso_data_r[31] :
(N18)? piso_data_r[47] :
(N20)? piso_data_r[63] : 1'b0;
assign data_o[14] = (N17)? piso_data_r[14] :
(N19)? piso_data_r[30] :
(N18)? piso_data_r[46] :
(N20)? piso_data_r[62] : 1'b0;
assign data_o[13] = (N17)? piso_data_r[13] :
(N19)? piso_data_r[29] :
(N18)? piso_data_r[45] :
(N20)? piso_data_r[61] : 1'b0;
assign data_o[12] = (N17)? piso_data_r[12] :
(N19)? piso_data_r[28] :
(N18)? piso_data_r[44] :
(N20)? piso_data_r[60] : 1'b0;
assign data_o[11] = (N17)? piso_data_r[11] :
(N19)? piso_data_r[27] :
(N18)? piso_data_r[43] :
(N20)? piso_data_r[59] : 1'b0;
assign data_o[10] = (N17)? piso_data_r[10] :
(N19)? piso_data_r[26] :
(N18)? piso_data_r[42] :
(N20)? piso_data_r[58] : 1'b0;
assign data_o[9] = (N17)? piso_data_r[9] :
(N19)? piso_data_r[25] :
(N18)? piso_data_r[41] :
(N20)? piso_data_r[57] : 1'b0;
assign data_o[8] = (N17)? piso_data_r[8] :
(N19)? piso_data_r[24] :
(N18)? piso_data_r[40] :
(N20)? piso_data_r[56] : 1'b0;
assign data_o[7] = (N17)? piso_data_r[7] :
(N19)? piso_data_r[23] :
(N18)? piso_data_r[39] :
(N20)? piso_data_r[55] : 1'b0;
assign data_o[6] = (N17)? piso_data_r[6] :
(N19)? piso_data_r[22] :
(N18)? piso_data_r[38] :
(N20)? piso_data_r[54] : 1'b0;
assign data_o[5] = (N17)? piso_data_r[5] :
(N19)? piso_data_r[21] :
(N18)? piso_data_r[37] :
(N20)? piso_data_r[53] : 1'b0;
assign data_o[4] = (N17)? piso_data_r[4] :
(N19)? piso_data_r[20] :
(N18)? piso_data_r[36] :
(N20)? piso_data_r[52] : 1'b0;
assign data_o[3] = (N17)? piso_data_r[3] :
(N19)? piso_data_r[19] :
(N18)? piso_data_r[35] :
(N20)? piso_data_r[51] : 1'b0;
assign data_o[2] = (N17)? piso_data_r[2] :
(N19)? piso_data_r[18] :
(N18)? piso_data_r[34] :
(N20)? piso_data_r[50] : 1'b0;
assign data_o[1] = (N17)? piso_data_r[1] :
(N19)? piso_data_r[17] :
(N18)? piso_data_r[33] :
(N20)? piso_data_r[49] : 1'b0;
assign data_o[0] = (N17)? piso_data_r[0] :
(N19)? piso_data_r[16] :
(N18)? piso_data_r[32] :
(N20)? piso_data_r[48] : 1'b0;
assign N23 = ~valid_o;
assign N24 = piso_shift_ctr_r[0] & piso_shift_ctr_r[1];
assign { N14, N13 } = piso_shift_ctr_r + 1'b1;
assign piso_state_n[0] = (N0)? 1'b1 :
(N5)? 1'b0 : 1'b0;
assign N0 = N2;
assign { N10, N9 } = (N1)? { 1'b0, 1'b0 } :
(N8)? { N14, N13 } : 1'b0;
assign N1 = N7;
assign piso_done_tx_n = N25 & yumi_i;
assign N25 = valid_o & N24;
assign ready_o = N23 | piso_done_tx_n;
assign N2 = ready_o & valid_i;
assign N3 = piso_done_tx_n | N2;
assign N4 = ~N2;
assign N5 = piso_done_tx_n & N4;
assign N6 = ready_o & valid_i;
assign N7 = ready_o & valid_i;
assign N8 = ~N7;
assign N11 = N26 & N27;
assign N26 = valid_o & yumi_i;
assign N27 = ~piso_done_tx_n;
assign N12 = ~N11;
assign N15 = ~piso_shift_ctr_r[0];
assign N16 = ~piso_shift_ctr_r[1];
assign N17 = N15 & N16;
assign N18 = N15 & piso_shift_ctr_r[1];
assign N19 = piso_shift_ctr_r[0] & N16;
assign N20 = piso_shift_ctr_r[0] & piso_shift_ctr_r[1];
assign N21 = N12 & N8;
assign N22 = ~N21;
endmodule |
module bsg_dff_reset_width_p13
(
clk_i,
reset_i,
data_i,
data_o
);
input [12:0] data_i;
output [12:0] data_o;
input clk_i;
input reset_i;
wire [12:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
reg data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,
data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,
data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_wormhole_router_decoder_dor_1_2_1
(
target_cord_i,
my_cord_i,
req_o
);
input [2:0] target_cord_i;
input [2:0] my_cord_i;
output [2:0] req_o;
wire [2:0] req_o;
wire N0,N1;
assign req_o[0] = target_cord_i == my_cord_i;
assign req_o[1] = target_cord_i < my_cord_i;
assign req_o[2] = N0 & N1;
assign N0 = ~req_o[0];
assign N1 = ~req_o[1];
endmodule |
module bsg_mux_width_p8_els_p8
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [2:0] sel_i;
output [7:0] data_o;
wire [7:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign data_o[7] = (N7)? data_i[7] :
(N9)? data_i[15] :
(N11)? data_i[23] :
(N13)? data_i[31] :
(N8)? data_i[39] :
(N10)? data_i[47] :
(N12)? data_i[55] :
(N14)? data_i[63] : 1'b0;
assign data_o[6] = (N7)? data_i[6] :
(N9)? data_i[14] :
(N11)? data_i[22] :
(N13)? data_i[30] :
(N8)? data_i[38] :
(N10)? data_i[46] :
(N12)? data_i[54] :
(N14)? data_i[62] : 1'b0;
assign data_o[5] = (N7)? data_i[5] :
(N9)? data_i[13] :
(N11)? data_i[21] :
(N13)? data_i[29] :
(N8)? data_i[37] :
(N10)? data_i[45] :
(N12)? data_i[53] :
(N14)? data_i[61] : 1'b0;
assign data_o[4] = (N7)? data_i[4] :
(N9)? data_i[12] :
(N11)? data_i[20] :
(N13)? data_i[28] :
(N8)? data_i[36] :
(N10)? data_i[44] :
(N12)? data_i[52] :
(N14)? data_i[60] : 1'b0;
assign data_o[3] = (N7)? data_i[3] :
(N9)? data_i[11] :
(N11)? data_i[19] :
(N13)? data_i[27] :
(N8)? data_i[35] :
(N10)? data_i[43] :
(N12)? data_i[51] :
(N14)? data_i[59] : 1'b0;
assign data_o[2] = (N7)? data_i[2] :
(N9)? data_i[10] :
(N11)? data_i[18] :
(N13)? data_i[26] :
(N8)? data_i[34] :
(N10)? data_i[42] :
(N12)? data_i[50] :
(N14)? data_i[58] : 1'b0;
assign data_o[1] = (N7)? data_i[1] :
(N9)? data_i[9] :
(N11)? data_i[17] :
(N13)? data_i[25] :
(N8)? data_i[33] :
(N10)? data_i[41] :
(N12)? data_i[49] :
(N14)? data_i[57] : 1'b0;
assign data_o[0] = (N7)? data_i[0] :
(N9)? data_i[8] :
(N11)? data_i[16] :
(N13)? data_i[24] :
(N8)? data_i[32] :
(N10)? data_i[40] :
(N12)? data_i[48] :
(N14)? data_i[56] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
assign N6 = ~sel_i[2];
assign N7 = N2 & N6;
assign N8 = N2 & sel_i[2];
assign N9 = N4 & N6;
assign N10 = N4 & sel_i[2];
assign N11 = N3 & N6;
assign N12 = N3 & sel_i[2];
assign N13 = N5 & N6;
assign N14 = N5 & sel_i[2];
endmodule |
module bp_pma_05
(
ptag_v_i,
ptag_i,
uncached_o
);
input [27:0] ptag_i;
input ptag_v_i;
output uncached_o;
wire uncached_o,is_local_addr,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
assign N0 = ptag_i[26] | ptag_i[27];
assign N1 = ptag_i[25] | N0;
assign is_local_addr = ~N9;
assign N9 = N8 | ptag_i[19];
assign N8 = N7 | ptag_i[20];
assign N7 = N6 | ptag_i[21];
assign N6 = N5 | ptag_i[22];
assign N5 = N4 | ptag_i[23];
assign N4 = N3 | ptag_i[24];
assign N3 = N2 | ptag_i[25];
assign N2 = ptag_i[27] | ptag_i[26];
assign uncached_o = ptag_v_i & N10;
assign N10 = is_local_addr | N1;
endmodule |
module bsg_unconcentrate_static_1b
(
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_,o_3_,o_1_,o_0_;
assign o[2] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_decode_num_out_p5
(
i,
o
);
input [2:0] i;
output [4:0] o;
wire [4:0] o;
assign o = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << i;
endmodule |
module bsg_nor3_width_p4_harden_p1
(
a_i,
b_i,
c_i,
o
);
input [3:0] a_i;
input [3:0] b_i;
input [3:0] c_i;
output [3:0] o;
wire [3:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7;
assign o[3] = ~N1;
assign N1 = N0 | c_i[3];
assign N0 = a_i[3] | b_i[3];
assign o[2] = ~N3;
assign N3 = N2 | c_i[2];
assign N2 = a_i[2] | b_i[2];
assign o[1] = ~N5;
assign N5 = N4 | c_i[1];
assign N4 = a_i[1] | b_i[1];
assign o[0] = ~N7;
assign N7 = N6 | c_i[0];
assign N6 = a_i[0] | b_i[0];
endmodule |
module bsg_mux_width_p32_els_p2
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [0:0] sel_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1;
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[63] : 1'b0;
assign N0 = sel_i[0];
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[62] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[61] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[60] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[59] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[58] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[57] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[56] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[55] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[54] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[53] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[52] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[51] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[50] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[49] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[48] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[47] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[46] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[45] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[44] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[43] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[42] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[41] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[40] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[39] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[38] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[37] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[36] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[35] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[34] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[33] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[32] : 1'b0;
assign N1 = ~sel_i[0];
endmodule |
module bsg_scan_width_p16_or_p1_lo_to_hi_p1
(
i,
o
);
input [15:0] i;
output [15:0] o;
wire [15:0] o;
wire t_3__15_,t_3__14_,t_3__13_,t_3__12_,t_3__11_,t_3__10_,t_3__9_,t_3__8_,t_3__7_,
t_3__6_,t_3__5_,t_3__4_,t_3__3_,t_3__2_,t_3__1_,t_3__0_,t_2__15_,t_2__14_,
t_2__13_,t_2__12_,t_2__11_,t_2__10_,t_2__9_,t_2__8_,t_2__7_,t_2__6_,t_2__5_,t_2__4_,
t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__15_,t_1__14_,t_1__13_,t_1__12_,t_1__11_,
t_1__10_,t_1__9_,t_1__8_,t_1__7_,t_1__6_,t_1__5_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,
t_1__0_;
assign t_1__15_ = i[0] | 1'b0;
assign t_1__14_ = i[1] | i[0];
assign t_1__13_ = i[2] | i[1];
assign t_1__12_ = i[3] | i[2];
assign t_1__11_ = i[4] | i[3];
assign t_1__10_ = i[5] | i[4];
assign t_1__9_ = i[6] | i[5];
assign t_1__8_ = i[7] | i[6];
assign t_1__7_ = i[8] | i[7];
assign t_1__6_ = i[9] | i[8];
assign t_1__5_ = i[10] | i[9];
assign t_1__4_ = i[11] | i[10];
assign t_1__3_ = i[12] | i[11];
assign t_1__2_ = i[13] | i[12];
assign t_1__1_ = i[14] | i[13];
assign t_1__0_ = i[15] | i[14];
assign t_2__15_ = t_1__15_ | 1'b0;
assign t_2__14_ = t_1__14_ | 1'b0;
assign t_2__13_ = t_1__13_ | t_1__15_;
assign t_2__12_ = t_1__12_ | t_1__14_;
assign t_2__11_ = t_1__11_ | t_1__13_;
assign t_2__10_ = t_1__10_ | t_1__12_;
assign t_2__9_ = t_1__9_ | t_1__11_;
assign t_2__8_ = t_1__8_ | t_1__10_;
assign t_2__7_ = t_1__7_ | t_1__9_;
assign t_2__6_ = t_1__6_ | t_1__8_;
assign t_2__5_ = t_1__5_ | t_1__7_;
assign t_2__4_ = t_1__4_ | t_1__6_;
assign t_2__3_ = t_1__3_ | t_1__5_;
assign t_2__2_ = t_1__2_ | t_1__4_;
assign t_2__1_ = t_1__1_ | t_1__3_;
assign t_2__0_ = t_1__0_ | t_1__2_;
assign t_3__15_ = t_2__15_ | 1'b0;
assign t_3__14_ = t_2__14_ | 1'b0;
assign t_3__13_ = t_2__13_ | 1'b0;
assign t_3__12_ = t_2__12_ | 1'b0;
assign t_3__11_ = t_2__11_ | t_2__15_;
assign t_3__10_ = t_2__10_ | t_2__14_;
assign t_3__9_ = t_2__9_ | t_2__13_;
assign t_3__8_ = t_2__8_ | t_2__12_;
assign t_3__7_ = t_2__7_ | t_2__11_;
assign t_3__6_ = t_2__6_ | t_2__10_;
assign t_3__5_ = t_2__5_ | t_2__9_;
assign t_3__4_ = t_2__4_ | t_2__8_;
assign t_3__3_ = t_2__3_ | t_2__7_;
assign t_3__2_ = t_2__2_ | t_2__6_;
assign t_3__1_ = t_2__1_ | t_2__5_;
assign t_3__0_ = t_2__0_ | t_2__4_;
assign o[0] = t_3__15_ | 1'b0;
assign o[1] = t_3__14_ | 1'b0;
assign o[2] = t_3__13_ | 1'b0;
assign o[3] = t_3__12_ | 1'b0;
assign o[4] = t_3__11_ | 1'b0;
assign o[5] = t_3__10_ | 1'b0;
assign o[6] = t_3__9_ | 1'b0;
assign o[7] = t_3__8_ | 1'b0;
assign o[8] = t_3__7_ | t_3__15_;
assign o[9] = t_3__6_ | t_3__14_;
assign o[10] = t_3__5_ | t_3__13_;
assign o[11] = t_3__4_ | t_3__12_;
assign o[12] = t_3__3_ | t_3__11_;
assign o[13] = t_3__2_ | t_3__10_;
assign o[14] = t_3__1_ | t_3__9_;
assign o[15] = t_3__0_ | t_3__8_;
endmodule |
module bsg_dff_reset_width_p6
(
clk_i,
reset_i,
data_i,
data_o
);
input [5:0] data_i;
output [5:0] data_o;
input clk_i;
input reset_i;
wire [5:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
reg data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_concentrate_static_09
(
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[3];
assign o[0] = i[0];
endmodule |
module bsg_array_concentrate_static_09_128
(
i,
o
);
input [639:0] i;
output [255:0] o;
wire [255:0] o;
assign o[255] = i[511];
assign o[254] = i[510];
assign o[253] = i[509];
assign o[252] = i[508];
assign o[251] = i[507];
assign o[250] = i[506];
assign o[249] = i[505];
assign o[248] = i[504];
assign o[247] = i[503];
assign o[246] = i[502];
assign o[245] = i[501];
assign o[244] = i[500];
assign o[243] = i[499];
assign o[242] = i[498];
assign o[241] = i[497];
assign o[240] = i[496];
assign o[239] = i[495];
assign o[238] = i[494];
assign o[237] = i[493];
assign o[236] = i[492];
assign o[235] = i[491];
assign o[234] = i[490];
assign o[233] = i[489];
assign o[232] = i[488];
assign o[231] = i[487];
assign o[230] = i[486];
assign o[229] = i[485];
assign o[228] = i[484];
assign o[227] = i[483];
assign o[226] = i[482];
assign o[225] = i[481];
assign o[224] = i[480];
assign o[223] = i[479];
assign o[222] = i[478];
assign o[221] = i[477];
assign o[220] = i[476];
assign o[219] = i[475];
assign o[218] = i[474];
assign o[217] = i[473];
assign o[216] = i[472];
assign o[215] = i[471];
assign o[214] = i[470];
assign o[213] = i[469];
assign o[212] = i[468];
assign o[211] = i[467];
assign o[210] = i[466];
assign o[209] = i[465];
assign o[208] = i[464];
assign o[207] = i[463];
assign o[206] = i[462];
assign o[205] = i[461];
assign o[204] = i[460];
assign o[203] = i[459];
assign o[202] = i[458];
assign o[201] = i[457];
assign o[200] = i[456];
assign o[199] = i[455];
assign o[198] = i[454];
assign o[197] = i[453];
assign o[196] = i[452];
assign o[195] = i[451];
assign o[194] = i[450];
assign o[193] = i[449];
assign o[192] = i[448];
assign o[191] = i[447];
assign o[190] = i[446];
assign o[189] = i[445];
assign o[188] = i[444];
assign o[187] = i[443];
assign o[186] = i[442];
assign o[185] = i[441];
assign o[184] = i[440];
assign o[183] = i[439];
assign o[182] = i[438];
assign o[181] = i[437];
assign o[180] = i[436];
assign o[179] = i[435];
assign o[178] = i[434];
assign o[177] = i[433];
assign o[176] = i[432];
assign o[175] = i[431];
assign o[174] = i[430];
assign o[173] = i[429];
assign o[172] = i[428];
assign o[171] = i[427];
assign o[170] = i[426];
assign o[169] = i[425];
assign o[168] = i[424];
assign o[167] = i[423];
assign o[166] = i[422];
assign o[165] = i[421];
assign o[164] = i[420];
assign o[163] = i[419];
assign o[162] = i[418];
assign o[161] = i[417];
assign o[160] = i[416];
assign o[159] = i[415];
assign o[158] = i[414];
assign o[157] = i[413];
assign o[156] = i[412];
assign o[155] = i[411];
assign o[154] = i[410];
assign o[153] = i[409];
assign o[152] = i[408];
assign o[151] = i[407];
assign o[150] = i[406];
assign o[149] = i[405];
assign o[148] = i[404];
assign o[147] = i[403];
assign o[146] = i[402];
assign o[145] = i[401];
assign o[144] = i[400];
assign o[143] = i[399];
assign o[142] = i[398];
assign o[141] = i[397];
assign o[140] = i[396];
assign o[139] = i[395];
assign o[138] = i[394];
assign o[137] = i[393];
assign o[136] = i[392];
assign o[135] = i[391];
assign o[134] = i[390];
assign o[133] = i[389];
assign o[132] = i[388];
assign o[131] = i[387];
assign o[130] = i[386];
assign o[129] = i[385];
assign o[128] = i[384];
assign o[127] = i[127];
assign o[126] = i[126];
assign o[125] = i[125];
assign o[124] = i[124];
assign o[123] = i[123];
assign o[122] = i[122];
assign o[121] = i[121];
assign o[120] = i[120];
assign o[119] = i[119];
assign o[118] = i[118];
assign o[117] = i[117];
assign o[116] = i[116];
assign o[115] = i[115];
assign o[114] = i[114];
assign o[113] = i[113];
assign o[112] = i[112];
assign o[111] = i[111];
assign o[110] = i[110];
assign o[109] = i[109];
assign o[108] = i[108];
assign o[107] = i[107];
assign o[106] = i[106];
assign o[105] = i[105];
assign o[104] = i[104];
assign o[103] = i[103];
assign o[102] = i[102];
assign o[101] = i[101];
assign o[100] = i[100];
assign o[99] = i[99];
assign o[98] = i[98];
assign o[97] = i[97];
assign o[96] = i[96];
assign o[95] = i[95];
assign o[94] = i[94];
assign o[93] = i[93];
assign o[92] = i[92];
assign o[91] = i[91];
assign o[90] = i[90];
assign o[89] = i[89];
assign o[88] = i[88];
assign o[87] = i[87];
assign o[86] = i[86];
assign o[85] = i[85];
assign o[84] = i[84];
assign o[83] = i[83];
assign o[82] = i[82];
assign o[81] = i[81];
assign o[80] = i[80];
assign o[79] = i[79];
assign o[78] = i[78];
assign o[77] = i[77];
assign o[76] = i[76];
assign o[75] = i[75];
assign o[74] = i[74];
assign o[73] = i[73];
assign o[72] = i[72];
assign o[71] = i[71];
assign o[70] = i[70];
assign o[69] = i[69];
assign o[68] = i[68];
assign o[67] = i[67];
assign o[66] = i[66];
assign o[65] = i[65];
assign o[64] = i[64];
assign o[63] = i[63];
assign o[62] = i[62];
assign o[61] = i[61];
assign o[60] = i[60];
assign o[59] = i[59];
assign o[58] = i[58];
assign o[57] = i[57];
assign o[56] = i[56];
assign o[55] = i[55];
assign o[54] = i[54];
assign o[53] = i[53];
assign o[52] = i[52];
assign o[51] = i[51];
assign o[50] = i[50];
assign o[49] = i[49];
assign o[48] = i[48];
assign o[47] = i[47];
assign o[46] = i[46];
assign o[45] = i[45];
assign o[44] = i[44];
assign o[43] = i[43];
assign o[42] = i[42];
assign o[41] = i[41];
assign o[40] = i[40];
assign o[39] = i[39];
assign o[38] = i[38];
assign o[37] = i[37];
assign o[36] = i[36];
assign o[35] = i[35];
assign o[34] = i[34];
assign o[33] = i[33];
assign o[32] = i[32];
assign o[31] = i[31];
assign o[30] = i[30];
assign o[29] = i[29];
assign o[28] = i[28];
assign o[27] = i[27];
assign o[26] = i[26];
assign o[25] = i[25];
assign o[24] = i[24];
assign o[23] = i[23];
assign o[22] = i[22];
assign o[21] = i[21];
assign o[20] = i[20];
assign o[19] = i[19];
assign o[18] = i[18];
assign o[17] = i[17];
assign o[16] = i[16];
assign o[15] = i[15];
assign o[14] = i[14];
assign o[13] = i[13];
assign o[12] = i[12];
assign o[11] = i[11];
assign o[10] = i[10];
assign o[9] = i[9];
assign o[8] = i[8];
assign o[7] = i[7];
assign o[6] = i[6];
assign o[5] = i[5];
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_reset_en_width_p27
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [26:0] data_i;
output [26:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [26:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
reg data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,
data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,
data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,
data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,
data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,
data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_26_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_25_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_24_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_23_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_22_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_21_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_20_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_19_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_18_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_17_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_16_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_15_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_14_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_13_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_12_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_11_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_10_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_9_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_8_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_7_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_6_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_5_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_4_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_3_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N32)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N32)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N31 = ~reset_i;
assign N32 = en_i & N31;
endmodule |
module bsg_scan_width_p3_or_p1_lo_to_hi_p1
(
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
wire t_1__2_,t_1__1_,t_1__0_;
assign t_1__2_ = i[0] | 1'b0;
assign t_1__1_ = i[1] | i[0];
assign t_1__0_ = i[2] | i[1];
assign o[0] = t_1__2_ | 1'b0;
assign o[1] = t_1__1_ | 1'b0;
assign o[2] = t_1__0_ | t_1__2_;
endmodule |
module bsg_buf_width_p1
(
i,
o
);
input [0:0] i;
output [0:0] o;
wire [0:0] o;
assign o[0] = i[0];
endmodule |
module bsg_circular_ptr_slots_p16_max_add_p1
(
clk,
reset_i,
add_i,
o,
n_o
);
input [0:0] add_i;
output [3:0] o;
output [3:0] n_o;
input clk;
input reset_i;
wire [3:0] o,n_o,genblk1_genblk1_ptr_r_p1;
wire N0,N1,N2;
reg o_3_sv2v_reg,o_2_sv2v_reg,o_1_sv2v_reg,o_0_sv2v_reg;
assign o[3] = o_3_sv2v_reg;
assign o[2] = o_2_sv2v_reg;
assign o[1] = o_1_sv2v_reg;
assign o[0] = o_0_sv2v_reg;
always @(posedge clk) begin
if(reset_i) begin
o_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_3_sv2v_reg <= n_o[3];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_2_sv2v_reg <= n_o[2];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_1_sv2v_reg <= n_o[1];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_0_sv2v_reg <= n_o[0];
end
end
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign n_o = (N0)? genblk1_genblk1_ptr_r_p1 :
(N1)? o : 1'b0;
assign N0 = add_i[0];
assign N1 = N2;
assign N2 = ~add_i[0];
endmodule |
module bsg_dff_reset_04
(
clk_i,
reset_i,
data_i,
data_o
);
input [3:0] data_i;
output [3:0] data_o;
input clk_i;
input reset_i;
wire [3:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6;
reg data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_unconcentrate_static_05
(
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_2_,o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_circular_ptr_slots_p64_max_add_p1
(
clk,
reset_i,
add_i,
o,
n_o
);
input [0:0] add_i;
output [5:0] o;
output [5:0] n_o;
input clk;
input reset_i;
wire [5:0] o,n_o,genblk1_genblk1_ptr_r_p1;
wire N0,N1,N2;
reg o_5_sv2v_reg,o_4_sv2v_reg,o_3_sv2v_reg,o_2_sv2v_reg,o_1_sv2v_reg,o_0_sv2v_reg;
assign o[5] = o_5_sv2v_reg;
assign o[4] = o_4_sv2v_reg;
assign o[3] = o_3_sv2v_reg;
assign o[2] = o_2_sv2v_reg;
assign o[1] = o_1_sv2v_reg;
assign o[0] = o_0_sv2v_reg;
always @(posedge clk) begin
if(reset_i) begin
o_5_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_5_sv2v_reg <= n_o[5];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_4_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_4_sv2v_reg <= n_o[4];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_3_sv2v_reg <= n_o[3];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_2_sv2v_reg <= n_o[2];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_1_sv2v_reg <= n_o[1];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_0_sv2v_reg <= n_o[0];
end
end
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign n_o = (N0)? genblk1_genblk1_ptr_r_p1 :
(N1)? o : 1'b0;
assign N0 = add_i[0];
assign N1 = N2;
assign N2 = ~add_i[0];
endmodule |
module bsg_counter_clear_up_max_val_p65_init_val_p0
(
clk_i,
reset_i,
clear_i,
up_i,
count_o
);
output [6:0] count_o;
input clk_i;
input reset_i;
input clear_i;
input up_i;
wire [6:0] count_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26;
reg count_o_6_sv2v_reg,count_o_5_sv2v_reg,count_o_4_sv2v_reg,count_o_3_sv2v_reg,
count_o_2_sv2v_reg,count_o_1_sv2v_reg,count_o_0_sv2v_reg;
assign count_o[6] = count_o_6_sv2v_reg;
assign count_o[5] = count_o_5_sv2v_reg;
assign count_o[4] = count_o_4_sv2v_reg;
assign count_o[3] = count_o_3_sv2v_reg;
assign count_o[2] = count_o_2_sv2v_reg;
assign count_o[1] = count_o_1_sv2v_reg;
assign count_o[0] = count_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
count_o_6_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_5_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_4_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_3_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_2_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_1_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o_0_sv2v_reg <= N13;
end
end
assign { N12, N11, N10, N9, N8, N7, N6 } = { N26, N25, N24, N23, N22, N21, N20 } + up_i;
assign { N19, N18, N17, N16, N15, N14, N13 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N12, N11, N10, N9, N8, N7, N6 } : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign { N26, N25, N24, N23, N22, N21, N20 } = count_o * N4;
assign N2 = ~reset_i;
assign N3 = N2;
assign N4 = ~clear_i;
assign N5 = N3 & N4;
endmodule |
module bsg_concentrate_static_11
(
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[4];
assign o[0] = i[0];
endmodule |
module bp_me_cord_to_id_05
(
cord_i,
core_id_o,
cce_id_o,
lce_id0_o,
lce_id1_o
);
input [4:0] cord_i;
output [1:0] core_id_o;
output [3:0] cce_id_o;
output [5:0] lce_id0_o;
output [5:0] lce_id1_o;
wire [1:0] core_id_o;
wire [3:0] cce_id_o;
wire [5:0] lce_id0_o,lce_id1_o;
wire N6,N7,N8,cord_in_cc_li,N9,cord_in_mc_li,N10,cord_in_ac_li,N11,N12,N13,N14,N15,
N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,
N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,
N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71;
assign cce_id_o[1] = core_id_o[1];
assign cce_id_o[0] = core_id_o[0];
assign N7 = cord_i[1:0] <= { 1'b1, 1'b0 };
assign N8 = cord_i[4:2] <= { 1'b1, 1'b1 };
assign N9 = cord_i[4:2] > { 1'b1, 1'b1 };
assign N10 = cord_i[1:0] > { 1'b1, 1'b0 };
assign { N16, N15, N14 } = cord_i[4:2] - 1'b1;
assign { N20, N19, N18, N17 } = cord_i[1:0] + { N16, N15, N14, 1'b0 };
assign { N26, N25, N24, N23, N22, N21 } = { N20, N19, N18, N17, 1'b0 } + 1'b1;
assign { N31, N30, N29, N28 } = { 1'b1, 1'b0, 1'b0 } + cord_i[1:0];
assign { N36, N35, N34, N33, N32 } = { 1'b1, 1'b0, 1'b0, 1'b0 } + cord_i[1:0];
assign lce_id1_o[0] = N21;
assign lce_id1_o[1] = N22;
assign lce_id1_o[2] = N23;
assign lce_id1_o[3] = N24;
assign lce_id1_o[4] = N25;
assign lce_id1_o[5] = N26;
assign { N55, N54, N53, N52 } = { 1'b1, 1'b0, 1'b0 } + cord_i[1:0];
assign { N60, N59, N58, N57, N56 } = { 1'b1, 1'b0, 1'b0, 1'b0 } + cord_i[1:0];
assign { N41, N40, N39, N38 } = cord_i[4:2] - 1'b1;
assign { N45, N44, N43, N42 } = { 1'b1, 1'b0, 1'b0 } + { N41, N40, N39, N38 };
assign { N51, N50, N49, N48, N47, N46 } = { 1'b1, 1'b0, 1'b0, 1'b0 } + { N41, N41, N41, N40, N39, N38 };
assign { cce_id_o[3:2], core_id_o } = (N6)? { N20, N19, N18, N17 } :
(N62)? { N31, N30, N29, N28 } :
(N65)? { N45, N44, N43, N42 } :
(N13)? { N55, N54, N53, N52 } : 1'b0;
assign N6 = cord_in_cc_li;
assign lce_id0_o = (N6)? { 1'b0, N20, N19, N18, N17, 1'b0 } :
(N62)? { 1'b0, N36, N35, N34, N33, N32 } :
(N65)? { N51, N50, N49, N48, N47, N46 } :
(N13)? { 1'b0, N60, N59, N58, N57, N56 } : 1'b0;
assign cord_in_cc_li = N68 & N8;
assign N68 = N7 & N67;
assign N67 = N66 | cord_i[2];
assign N66 = cord_i[4] | cord_i[3];
assign cord_in_mc_li = N7 & N9;
assign cord_in_ac_li = N71 & N8;
assign N71 = N10 & N70;
assign N70 = N69 | cord_i[2];
assign N69 = cord_i[4] | cord_i[3];
assign N11 = cord_in_mc_li | cord_in_cc_li;
assign N12 = cord_in_ac_li | N11;
assign N13 = ~N12;
assign N27 = N62;
assign N37 = N65;
assign N61 = ~cord_in_cc_li;
assign N62 = cord_in_mc_li & N61;
assign N63 = ~cord_in_mc_li;
assign N64 = N61 & N63;
assign N65 = cord_in_ac_li & N64;
endmodule |
module bsg_unconcentrate_static_7
(
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_reset_width_p11
(
clk_i,
reset_i,
data_i,
data_o
);
input [10:0] data_i;
output [10:0] data_o;
input clk_i;
input reset_i;
wire [10:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
reg data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,
data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,
data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_swap_width_p128
(
data_i,
swap_i,
data_o
);
input [255:0] data_i;
output [255:0] data_o;
input swap_i;
wire [255:0] data_o;
wire N0,N1,N2;
assign data_o = (N0)? { data_i[127:0], data_i[255:128] } :
(N1)? data_i : 1'b0;
assign N0 = swap_i;
assign N1 = N2;
assign N2 = ~swap_i;
endmodule |
module bsg_round_robin_arb_inputs_p2
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [1:0] reqs_i;
output [1:0] grants_o;
output [1:0] sel_one_hot_o;
output [0:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [1:0] grants_o,sel_one_hot_o;
wire [0:0] tag_o,last_r;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22;
reg last_r_0_sv2v_reg;
assign last_r[0] = last_r_0_sv2v_reg;
always @(posedge clk_i) begin
if(N22) begin
last_r_0_sv2v_reg <= N20;
end
end
assign N13 = N0 & N1;
assign N0 = ~reqs_i[1];
assign N1 = ~reqs_i[0];
assign N14 = reqs_i[1] & N2;
assign N2 = ~last_r[0];
assign N15 = N3 & reqs_i[0] & N4;
assign N3 = ~reqs_i[1];
assign N4 = ~last_r[0];
assign N16 = reqs_i[0] & last_r[0];
assign N17 = reqs_i[1] & N5 & last_r[0];
assign N5 = ~reqs_i[0];
assign sel_one_hot_o = (N6)? { 1'b0, 1'b0 } :
(N7)? { 1'b1, 1'b0 } :
(N8)? { 1'b0, 1'b1 } :
(N9)? { 1'b0, 1'b1 } :
(N10)? { 1'b1, 1'b0 } : 1'b0;
assign N6 = N13;
assign N7 = N14;
assign N8 = N15;
assign N9 = N16;
assign N10 = N17;
assign tag_o[0] = (N6)? 1'b0 :
(N7)? 1'b1 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 : 1'b0;
assign N20 = (N11)? 1'b0 :
(N12)? tag_o[0] : 1'b0;
assign N11 = reset_i;
assign N12 = N19;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = reqs_i[1] | reqs_i[0];
assign N18 = ~yumi_i;
assign N19 = ~reset_i;
assign N21 = N18 & N19;
assign N22 = ~N21;
endmodule |
module bsg_mux_segmented_segments_p8_segment_width_p8
(
data0_i,
data1_i,
sel_i,
data_o
);
input [63:0] data0_i;
input [63:0] data1_i;
input [7:0] sel_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
assign data_o[7:0] = (N0)? data1_i[7:0] :
(N8)? data0_i[7:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[15:8] = (N1)? data1_i[15:8] :
(N9)? data0_i[15:8] : 1'b0;
assign N1 = sel_i[1];
assign data_o[23:16] = (N2)? data1_i[23:16] :
(N10)? data0_i[23:16] : 1'b0;
assign N2 = sel_i[2];
assign data_o[31:24] = (N3)? data1_i[31:24] :
(N11)? data0_i[31:24] : 1'b0;
assign N3 = sel_i[3];
assign data_o[39:32] = (N4)? data1_i[39:32] :
(N12)? data0_i[39:32] : 1'b0;
assign N4 = sel_i[4];
assign data_o[47:40] = (N5)? data1_i[47:40] :
(N13)? data0_i[47:40] : 1'b0;
assign N5 = sel_i[5];
assign data_o[55:48] = (N6)? data1_i[55:48] :
(N14)? data0_i[55:48] : 1'b0;
assign N6 = sel_i[6];
assign data_o[63:56] = (N7)? data1_i[63:56] :
(N15)? data0_i[63:56] : 1'b0;
assign N7 = sel_i[7];
assign N8 = ~sel_i[0];
assign N9 = ~sel_i[1];
assign N10 = ~sel_i[2];
assign N11 = ~sel_i[3];
assign N12 = ~sel_i[4];
assign N13 = ~sel_i[5];
assign N14 = ~sel_i[6];
assign N15 = ~sel_i[7];
endmodule |
module bsg_dff_reset_en_width_p10
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [9:0] data_i;
output [9:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [9:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
reg data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,
data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_9_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_8_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_7_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_6_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_5_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_4_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_3_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N15)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N15)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N14 = ~reset_i;
assign N15 = en_i & N14;
endmodule |
module bsg_mux_one_hot_128_04
(
data_i,
sel_one_hot_i,
data_o
);
input [511:0] data_i;
input [3:0] sel_one_hot_i;
output [127:0] data_o;
wire [127:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,
N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,
N246,N247,N248,N249,N250,N251,N252,N253,N254,N255;
wire [511:0] data_masked;
assign data_masked[127] = data_i[127] & sel_one_hot_i[0];
assign data_masked[126] = data_i[126] & sel_one_hot_i[0];
assign data_masked[125] = data_i[125] & sel_one_hot_i[0];
assign data_masked[124] = data_i[124] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[0];
assign data_masked[122] = data_i[122] & sel_one_hot_i[0];
assign data_masked[121] = data_i[121] & sel_one_hot_i[0];
assign data_masked[120] = data_i[120] & sel_one_hot_i[0];
assign data_masked[119] = data_i[119] & sel_one_hot_i[0];
assign data_masked[118] = data_i[118] & sel_one_hot_i[0];
assign data_masked[117] = data_i[117] & sel_one_hot_i[0];
assign data_masked[116] = data_i[116] & sel_one_hot_i[0];
assign data_masked[115] = data_i[115] & sel_one_hot_i[0];
assign data_masked[114] = data_i[114] & sel_one_hot_i[0];
assign data_masked[113] = data_i[113] & sel_one_hot_i[0];
assign data_masked[112] = data_i[112] & sel_one_hot_i[0];
assign data_masked[111] = data_i[111] & sel_one_hot_i[0];
assign data_masked[110] = data_i[110] & sel_one_hot_i[0];
assign data_masked[109] = data_i[109] & sel_one_hot_i[0];
assign data_masked[108] = data_i[108] & sel_one_hot_i[0];
assign data_masked[107] = data_i[107] & sel_one_hot_i[0];
assign data_masked[106] = data_i[106] & sel_one_hot_i[0];
assign data_masked[105] = data_i[105] & sel_one_hot_i[0];
assign data_masked[104] = data_i[104] & sel_one_hot_i[0];
assign data_masked[103] = data_i[103] & sel_one_hot_i[0];
assign data_masked[102] = data_i[102] & sel_one_hot_i[0];
assign data_masked[101] = data_i[101] & sel_one_hot_i[0];
assign data_masked[100] = data_i[100] & sel_one_hot_i[0];
assign data_masked[99] = data_i[99] & sel_one_hot_i[0];
assign data_masked[98] = data_i[98] & sel_one_hot_i[0];
assign data_masked[97] = data_i[97] & sel_one_hot_i[0];
assign data_masked[96] = data_i[96] & sel_one_hot_i[0];
assign data_masked[95] = data_i[95] & sel_one_hot_i[0];
assign data_masked[94] = data_i[94] & sel_one_hot_i[0];
assign data_masked[93] = data_i[93] & sel_one_hot_i[0];
assign data_masked[92] = data_i[92] & sel_one_hot_i[0];
assign data_masked[91] = data_i[91] & sel_one_hot_i[0];
assign data_masked[90] = data_i[90] & sel_one_hot_i[0];
assign data_masked[89] = data_i[89] & sel_one_hot_i[0];
assign data_masked[88] = data_i[88] & sel_one_hot_i[0];
assign data_masked[87] = data_i[87] & sel_one_hot_i[0];
assign data_masked[86] = data_i[86] & sel_one_hot_i[0];
assign data_masked[85] = data_i[85] & sel_one_hot_i[0];
assign data_masked[84] = data_i[84] & sel_one_hot_i[0];
assign data_masked[83] = data_i[83] & sel_one_hot_i[0];
assign data_masked[82] = data_i[82] & sel_one_hot_i[0];
assign data_masked[81] = data_i[81] & sel_one_hot_i[0];
assign data_masked[80] = data_i[80] & sel_one_hot_i[0];
assign data_masked[79] = data_i[79] & sel_one_hot_i[0];
assign data_masked[78] = data_i[78] & sel_one_hot_i[0];
assign data_masked[77] = data_i[77] & sel_one_hot_i[0];
assign data_masked[76] = data_i[76] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[255] = data_i[255] & sel_one_hot_i[1];
assign data_masked[254] = data_i[254] & sel_one_hot_i[1];
assign data_masked[253] = data_i[253] & sel_one_hot_i[1];
assign data_masked[252] = data_i[252] & sel_one_hot_i[1];
assign data_masked[251] = data_i[251] & sel_one_hot_i[1];
assign data_masked[250] = data_i[250] & sel_one_hot_i[1];
assign data_masked[249] = data_i[249] & sel_one_hot_i[1];
assign data_masked[248] = data_i[248] & sel_one_hot_i[1];
assign data_masked[247] = data_i[247] & sel_one_hot_i[1];
assign data_masked[246] = data_i[246] & sel_one_hot_i[1];
assign data_masked[245] = data_i[245] & sel_one_hot_i[1];
assign data_masked[244] = data_i[244] & sel_one_hot_i[1];
assign data_masked[243] = data_i[243] & sel_one_hot_i[1];
assign data_masked[242] = data_i[242] & sel_one_hot_i[1];
assign data_masked[241] = data_i[241] & sel_one_hot_i[1];
assign data_masked[240] = data_i[240] & sel_one_hot_i[1];
assign data_masked[239] = data_i[239] & sel_one_hot_i[1];
assign data_masked[238] = data_i[238] & sel_one_hot_i[1];
assign data_masked[237] = data_i[237] & sel_one_hot_i[1];
assign data_masked[236] = data_i[236] & sel_one_hot_i[1];
assign data_masked[235] = data_i[235] & sel_one_hot_i[1];
assign data_masked[234] = data_i[234] & sel_one_hot_i[1];
assign data_masked[233] = data_i[233] & sel_one_hot_i[1];
assign data_masked[232] = data_i[232] & sel_one_hot_i[1];
assign data_masked[231] = data_i[231] & sel_one_hot_i[1];
assign data_masked[230] = data_i[230] & sel_one_hot_i[1];
assign data_masked[229] = data_i[229] & sel_one_hot_i[1];
assign data_masked[228] = data_i[228] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[1];
assign data_masked[226] = data_i[226] & sel_one_hot_i[1];
assign data_masked[225] = data_i[225] & sel_one_hot_i[1];
assign data_masked[224] = data_i[224] & sel_one_hot_i[1];
assign data_masked[223] = data_i[223] & sel_one_hot_i[1];
assign data_masked[222] = data_i[222] & sel_one_hot_i[1];
assign data_masked[221] = data_i[221] & sel_one_hot_i[1];
assign data_masked[220] = data_i[220] & sel_one_hot_i[1];
assign data_masked[219] = data_i[219] & sel_one_hot_i[1];
assign data_masked[218] = data_i[218] & sel_one_hot_i[1];
assign data_masked[217] = data_i[217] & sel_one_hot_i[1];
assign data_masked[216] = data_i[216] & sel_one_hot_i[1];
assign data_masked[215] = data_i[215] & sel_one_hot_i[1];
assign data_masked[214] = data_i[214] & sel_one_hot_i[1];
assign data_masked[213] = data_i[213] & sel_one_hot_i[1];
assign data_masked[212] = data_i[212] & sel_one_hot_i[1];
assign data_masked[211] = data_i[211] & sel_one_hot_i[1];
assign data_masked[210] = data_i[210] & sel_one_hot_i[1];
assign data_masked[209] = data_i[209] & sel_one_hot_i[1];
assign data_masked[208] = data_i[208] & sel_one_hot_i[1];
assign data_masked[207] = data_i[207] & sel_one_hot_i[1];
assign data_masked[206] = data_i[206] & sel_one_hot_i[1];
assign data_masked[205] = data_i[205] & sel_one_hot_i[1];
assign data_masked[204] = data_i[204] & sel_one_hot_i[1];
assign data_masked[203] = data_i[203] & sel_one_hot_i[1];
assign data_masked[202] = data_i[202] & sel_one_hot_i[1];
assign data_masked[201] = data_i[201] & sel_one_hot_i[1];
assign data_masked[200] = data_i[200] & sel_one_hot_i[1];
assign data_masked[199] = data_i[199] & sel_one_hot_i[1];
assign data_masked[198] = data_i[198] & sel_one_hot_i[1];
assign data_masked[197] = data_i[197] & sel_one_hot_i[1];
assign data_masked[196] = data_i[196] & sel_one_hot_i[1];
assign data_masked[195] = data_i[195] & sel_one_hot_i[1];
assign data_masked[194] = data_i[194] & sel_one_hot_i[1];
assign data_masked[193] = data_i[193] & sel_one_hot_i[1];
assign data_masked[192] = data_i[192] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[1];
assign data_masked[190] = data_i[190] & sel_one_hot_i[1];
assign data_masked[189] = data_i[189] & sel_one_hot_i[1];
assign data_masked[188] = data_i[188] & sel_one_hot_i[1];
assign data_masked[187] = data_i[187] & sel_one_hot_i[1];
assign data_masked[186] = data_i[186] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[1];
assign data_masked[184] = data_i[184] & sel_one_hot_i[1];
assign data_masked[183] = data_i[183] & sel_one_hot_i[1];
assign data_masked[182] = data_i[182] & sel_one_hot_i[1];
assign data_masked[181] = data_i[181] & sel_one_hot_i[1];
assign data_masked[180] = data_i[180] & sel_one_hot_i[1];
assign data_masked[179] = data_i[179] & sel_one_hot_i[1];
assign data_masked[178] = data_i[178] & sel_one_hot_i[1];
assign data_masked[177] = data_i[177] & sel_one_hot_i[1];
assign data_masked[176] = data_i[176] & sel_one_hot_i[1];
assign data_masked[175] = data_i[175] & sel_one_hot_i[1];
assign data_masked[174] = data_i[174] & sel_one_hot_i[1];
assign data_masked[173] = data_i[173] & sel_one_hot_i[1];
assign data_masked[172] = data_i[172] & sel_one_hot_i[1];
assign data_masked[171] = data_i[171] & sel_one_hot_i[1];
assign data_masked[170] = data_i[170] & sel_one_hot_i[1];
assign data_masked[169] = data_i[169] & sel_one_hot_i[1];
assign data_masked[168] = data_i[168] & sel_one_hot_i[1];
assign data_masked[167] = data_i[167] & sel_one_hot_i[1];
assign data_masked[166] = data_i[166] & sel_one_hot_i[1];
assign data_masked[165] = data_i[165] & sel_one_hot_i[1];
assign data_masked[164] = data_i[164] & sel_one_hot_i[1];
assign data_masked[163] = data_i[163] & sel_one_hot_i[1];
assign data_masked[162] = data_i[162] & sel_one_hot_i[1];
assign data_masked[161] = data_i[161] & sel_one_hot_i[1];
assign data_masked[160] = data_i[160] & sel_one_hot_i[1];
assign data_masked[159] = data_i[159] & sel_one_hot_i[1];
assign data_masked[158] = data_i[158] & sel_one_hot_i[1];
assign data_masked[157] = data_i[157] & sel_one_hot_i[1];
assign data_masked[156] = data_i[156] & sel_one_hot_i[1];
assign data_masked[155] = data_i[155] & sel_one_hot_i[1];
assign data_masked[154] = data_i[154] & sel_one_hot_i[1];
assign data_masked[153] = data_i[153] & sel_one_hot_i[1];
assign data_masked[152] = data_i[152] & sel_one_hot_i[1];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_masked[383] = data_i[383] & sel_one_hot_i[2];
assign data_masked[382] = data_i[382] & sel_one_hot_i[2];
assign data_masked[381] = data_i[381] & sel_one_hot_i[2];
assign data_masked[380] = data_i[380] & sel_one_hot_i[2];
assign data_masked[379] = data_i[379] & sel_one_hot_i[2];
assign data_masked[378] = data_i[378] & sel_one_hot_i[2];
assign data_masked[377] = data_i[377] & sel_one_hot_i[2];
assign data_masked[376] = data_i[376] & sel_one_hot_i[2];
assign data_masked[375] = data_i[375] & sel_one_hot_i[2];
assign data_masked[374] = data_i[374] & sel_one_hot_i[2];
assign data_masked[373] = data_i[373] & sel_one_hot_i[2];
assign data_masked[372] = data_i[372] & sel_one_hot_i[2];
assign data_masked[371] = data_i[371] & sel_one_hot_i[2];
assign data_masked[370] = data_i[370] & sel_one_hot_i[2];
assign data_masked[369] = data_i[369] & sel_one_hot_i[2];
assign data_masked[368] = data_i[368] & sel_one_hot_i[2];
assign data_masked[367] = data_i[367] & sel_one_hot_i[2];
assign data_masked[366] = data_i[366] & sel_one_hot_i[2];
assign data_masked[365] = data_i[365] & sel_one_hot_i[2];
assign data_masked[364] = data_i[364] & sel_one_hot_i[2];
assign data_masked[363] = data_i[363] & sel_one_hot_i[2];
assign data_masked[362] = data_i[362] & sel_one_hot_i[2];
assign data_masked[361] = data_i[361] & sel_one_hot_i[2];
assign data_masked[360] = data_i[360] & sel_one_hot_i[2];
assign data_masked[359] = data_i[359] & sel_one_hot_i[2];
assign data_masked[358] = data_i[358] & sel_one_hot_i[2];
assign data_masked[357] = data_i[357] & sel_one_hot_i[2];
assign data_masked[356] = data_i[356] & sel_one_hot_i[2];
assign data_masked[355] = data_i[355] & sel_one_hot_i[2];
assign data_masked[354] = data_i[354] & sel_one_hot_i[2];
assign data_masked[353] = data_i[353] & sel_one_hot_i[2];
assign data_masked[352] = data_i[352] & sel_one_hot_i[2];
assign data_masked[351] = data_i[351] & sel_one_hot_i[2];
assign data_masked[350] = data_i[350] & sel_one_hot_i[2];
assign data_masked[349] = data_i[349] & sel_one_hot_i[2];
assign data_masked[348] = data_i[348] & sel_one_hot_i[2];
assign data_masked[347] = data_i[347] & sel_one_hot_i[2];
assign data_masked[346] = data_i[346] & sel_one_hot_i[2];
assign data_masked[345] = data_i[345] & sel_one_hot_i[2];
assign data_masked[344] = data_i[344] & sel_one_hot_i[2];
assign data_masked[343] = data_i[343] & sel_one_hot_i[2];
assign data_masked[342] = data_i[342] & sel_one_hot_i[2];
assign data_masked[341] = data_i[341] & sel_one_hot_i[2];
assign data_masked[340] = data_i[340] & sel_one_hot_i[2];
assign data_masked[339] = data_i[339] & sel_one_hot_i[2];
assign data_masked[338] = data_i[338] & sel_one_hot_i[2];
assign data_masked[337] = data_i[337] & sel_one_hot_i[2];
assign data_masked[336] = data_i[336] & sel_one_hot_i[2];
assign data_masked[335] = data_i[335] & sel_one_hot_i[2];
assign data_masked[334] = data_i[334] & sel_one_hot_i[2];
assign data_masked[333] = data_i[333] & sel_one_hot_i[2];
assign data_masked[332] = data_i[332] & sel_one_hot_i[2];
assign data_masked[331] = data_i[331] & sel_one_hot_i[2];
assign data_masked[330] = data_i[330] & sel_one_hot_i[2];
assign data_masked[329] = data_i[329] & sel_one_hot_i[2];
assign data_masked[328] = data_i[328] & sel_one_hot_i[2];
assign data_masked[327] = data_i[327] & sel_one_hot_i[2];
assign data_masked[326] = data_i[326] & sel_one_hot_i[2];
assign data_masked[325] = data_i[325] & sel_one_hot_i[2];
assign data_masked[324] = data_i[324] & sel_one_hot_i[2];
assign data_masked[323] = data_i[323] & sel_one_hot_i[2];
assign data_masked[322] = data_i[322] & sel_one_hot_i[2];
assign data_masked[321] = data_i[321] & sel_one_hot_i[2];
assign data_masked[320] = data_i[320] & sel_one_hot_i[2];
assign data_masked[319] = data_i[319] & sel_one_hot_i[2];
assign data_masked[318] = data_i[318] & sel_one_hot_i[2];
assign data_masked[317] = data_i[317] & sel_one_hot_i[2];
assign data_masked[316] = data_i[316] & sel_one_hot_i[2];
assign data_masked[315] = data_i[315] & sel_one_hot_i[2];
assign data_masked[314] = data_i[314] & sel_one_hot_i[2];
assign data_masked[313] = data_i[313] & sel_one_hot_i[2];
assign data_masked[312] = data_i[312] & sel_one_hot_i[2];
assign data_masked[311] = data_i[311] & sel_one_hot_i[2];
assign data_masked[310] = data_i[310] & sel_one_hot_i[2];
assign data_masked[309] = data_i[309] & sel_one_hot_i[2];
assign data_masked[308] = data_i[308] & sel_one_hot_i[2];
assign data_masked[307] = data_i[307] & sel_one_hot_i[2];
assign data_masked[306] = data_i[306] & sel_one_hot_i[2];
assign data_masked[305] = data_i[305] & sel_one_hot_i[2];
assign data_masked[304] = data_i[304] & sel_one_hot_i[2];
assign data_masked[303] = data_i[303] & sel_one_hot_i[2];
assign data_masked[302] = data_i[302] & sel_one_hot_i[2];
assign data_masked[301] = data_i[301] & sel_one_hot_i[2];
assign data_masked[300] = data_i[300] & sel_one_hot_i[2];
assign data_masked[299] = data_i[299] & sel_one_hot_i[2];
assign data_masked[298] = data_i[298] & sel_one_hot_i[2];
assign data_masked[297] = data_i[297] & sel_one_hot_i[2];
assign data_masked[296] = data_i[296] & sel_one_hot_i[2];
assign data_masked[295] = data_i[295] & sel_one_hot_i[2];
assign data_masked[294] = data_i[294] & sel_one_hot_i[2];
assign data_masked[293] = data_i[293] & sel_one_hot_i[2];
assign data_masked[292] = data_i[292] & sel_one_hot_i[2];
assign data_masked[291] = data_i[291] & sel_one_hot_i[2];
assign data_masked[290] = data_i[290] & sel_one_hot_i[2];
assign data_masked[289] = data_i[289] & sel_one_hot_i[2];
assign data_masked[288] = data_i[288] & sel_one_hot_i[2];
assign data_masked[287] = data_i[287] & sel_one_hot_i[2];
assign data_masked[286] = data_i[286] & sel_one_hot_i[2];
assign data_masked[285] = data_i[285] & sel_one_hot_i[2];
assign data_masked[284] = data_i[284] & sel_one_hot_i[2];
assign data_masked[283] = data_i[283] & sel_one_hot_i[2];
assign data_masked[282] = data_i[282] & sel_one_hot_i[2];
assign data_masked[281] = data_i[281] & sel_one_hot_i[2];
assign data_masked[280] = data_i[280] & sel_one_hot_i[2];
assign data_masked[279] = data_i[279] & sel_one_hot_i[2];
assign data_masked[278] = data_i[278] & sel_one_hot_i[2];
assign data_masked[277] = data_i[277] & sel_one_hot_i[2];
assign data_masked[276] = data_i[276] & sel_one_hot_i[2];
assign data_masked[275] = data_i[275] & sel_one_hot_i[2];
assign data_masked[274] = data_i[274] & sel_one_hot_i[2];
assign data_masked[273] = data_i[273] & sel_one_hot_i[2];
assign data_masked[272] = data_i[272] & sel_one_hot_i[2];
assign data_masked[271] = data_i[271] & sel_one_hot_i[2];
assign data_masked[270] = data_i[270] & sel_one_hot_i[2];
assign data_masked[269] = data_i[269] & sel_one_hot_i[2];
assign data_masked[268] = data_i[268] & sel_one_hot_i[2];
assign data_masked[267] = data_i[267] & sel_one_hot_i[2];
assign data_masked[266] = data_i[266] & sel_one_hot_i[2];
assign data_masked[265] = data_i[265] & sel_one_hot_i[2];
assign data_masked[264] = data_i[264] & sel_one_hot_i[2];
assign data_masked[263] = data_i[263] & sel_one_hot_i[2];
assign data_masked[262] = data_i[262] & sel_one_hot_i[2];
assign data_masked[261] = data_i[261] & sel_one_hot_i[2];
assign data_masked[260] = data_i[260] & sel_one_hot_i[2];
assign data_masked[259] = data_i[259] & sel_one_hot_i[2];
assign data_masked[258] = data_i[258] & sel_one_hot_i[2];
assign data_masked[257] = data_i[257] & sel_one_hot_i[2];
assign data_masked[256] = data_i[256] & sel_one_hot_i[2];
assign data_masked[511] = data_i[511] & sel_one_hot_i[3];
assign data_masked[510] = data_i[510] & sel_one_hot_i[3];
assign data_masked[509] = data_i[509] & sel_one_hot_i[3];
assign data_masked[508] = data_i[508] & sel_one_hot_i[3];
assign data_masked[507] = data_i[507] & sel_one_hot_i[3];
assign data_masked[506] = data_i[506] & sel_one_hot_i[3];
assign data_masked[505] = data_i[505] & sel_one_hot_i[3];
assign data_masked[504] = data_i[504] & sel_one_hot_i[3];
assign data_masked[503] = data_i[503] & sel_one_hot_i[3];
assign data_masked[502] = data_i[502] & sel_one_hot_i[3];
assign data_masked[501] = data_i[501] & sel_one_hot_i[3];
assign data_masked[500] = data_i[500] & sel_one_hot_i[3];
assign data_masked[499] = data_i[499] & sel_one_hot_i[3];
assign data_masked[498] = data_i[498] & sel_one_hot_i[3];
assign data_masked[497] = data_i[497] & sel_one_hot_i[3];
assign data_masked[496] = data_i[496] & sel_one_hot_i[3];
assign data_masked[495] = data_i[495] & sel_one_hot_i[3];
assign data_masked[494] = data_i[494] & sel_one_hot_i[3];
assign data_masked[493] = data_i[493] & sel_one_hot_i[3];
assign data_masked[492] = data_i[492] & sel_one_hot_i[3];
assign data_masked[491] = data_i[491] & sel_one_hot_i[3];
assign data_masked[490] = data_i[490] & sel_one_hot_i[3];
assign data_masked[489] = data_i[489] & sel_one_hot_i[3];
assign data_masked[488] = data_i[488] & sel_one_hot_i[3];
assign data_masked[487] = data_i[487] & sel_one_hot_i[3];
assign data_masked[486] = data_i[486] & sel_one_hot_i[3];
assign data_masked[485] = data_i[485] & sel_one_hot_i[3];
assign data_masked[484] = data_i[484] & sel_one_hot_i[3];
assign data_masked[483] = data_i[483] & sel_one_hot_i[3];
assign data_masked[482] = data_i[482] & sel_one_hot_i[3];
assign data_masked[481] = data_i[481] & sel_one_hot_i[3];
assign data_masked[480] = data_i[480] & sel_one_hot_i[3];
assign data_masked[479] = data_i[479] & sel_one_hot_i[3];
assign data_masked[478] = data_i[478] & sel_one_hot_i[3];
assign data_masked[477] = data_i[477] & sel_one_hot_i[3];
assign data_masked[476] = data_i[476] & sel_one_hot_i[3];
assign data_masked[475] = data_i[475] & sel_one_hot_i[3];
assign data_masked[474] = data_i[474] & sel_one_hot_i[3];
assign data_masked[473] = data_i[473] & sel_one_hot_i[3];
assign data_masked[472] = data_i[472] & sel_one_hot_i[3];
assign data_masked[471] = data_i[471] & sel_one_hot_i[3];
assign data_masked[470] = data_i[470] & sel_one_hot_i[3];
assign data_masked[469] = data_i[469] & sel_one_hot_i[3];
assign data_masked[468] = data_i[468] & sel_one_hot_i[3];
assign data_masked[467] = data_i[467] & sel_one_hot_i[3];
assign data_masked[466] = data_i[466] & sel_one_hot_i[3];
assign data_masked[465] = data_i[465] & sel_one_hot_i[3];
assign data_masked[464] = data_i[464] & sel_one_hot_i[3];
assign data_masked[463] = data_i[463] & sel_one_hot_i[3];
assign data_masked[462] = data_i[462] & sel_one_hot_i[3];
assign data_masked[461] = data_i[461] & sel_one_hot_i[3];
assign data_masked[460] = data_i[460] & sel_one_hot_i[3];
assign data_masked[459] = data_i[459] & sel_one_hot_i[3];
assign data_masked[458] = data_i[458] & sel_one_hot_i[3];
assign data_masked[457] = data_i[457] & sel_one_hot_i[3];
assign data_masked[456] = data_i[456] & sel_one_hot_i[3];
assign data_masked[455] = data_i[455] & sel_one_hot_i[3];
assign data_masked[454] = data_i[454] & sel_one_hot_i[3];
assign data_masked[453] = data_i[453] & sel_one_hot_i[3];
assign data_masked[452] = data_i[452] & sel_one_hot_i[3];
assign data_masked[451] = data_i[451] & sel_one_hot_i[3];
assign data_masked[450] = data_i[450] & sel_one_hot_i[3];
assign data_masked[449] = data_i[449] & sel_one_hot_i[3];
assign data_masked[448] = data_i[448] & sel_one_hot_i[3];
assign data_masked[447] = data_i[447] & sel_one_hot_i[3];
assign data_masked[446] = data_i[446] & sel_one_hot_i[3];
assign data_masked[445] = data_i[445] & sel_one_hot_i[3];
assign data_masked[444] = data_i[444] & sel_one_hot_i[3];
assign data_masked[443] = data_i[443] & sel_one_hot_i[3];
assign data_masked[442] = data_i[442] & sel_one_hot_i[3];
assign data_masked[441] = data_i[441] & sel_one_hot_i[3];
assign data_masked[440] = data_i[440] & sel_one_hot_i[3];
assign data_masked[439] = data_i[439] & sel_one_hot_i[3];
assign data_masked[438] = data_i[438] & sel_one_hot_i[3];
assign data_masked[437] = data_i[437] & sel_one_hot_i[3];
assign data_masked[436] = data_i[436] & sel_one_hot_i[3];
assign data_masked[435] = data_i[435] & sel_one_hot_i[3];
assign data_masked[434] = data_i[434] & sel_one_hot_i[3];
assign data_masked[433] = data_i[433] & sel_one_hot_i[3];
assign data_masked[432] = data_i[432] & sel_one_hot_i[3];
assign data_masked[431] = data_i[431] & sel_one_hot_i[3];
assign data_masked[430] = data_i[430] & sel_one_hot_i[3];
assign data_masked[429] = data_i[429] & sel_one_hot_i[3];
assign data_masked[428] = data_i[428] & sel_one_hot_i[3];
assign data_masked[427] = data_i[427] & sel_one_hot_i[3];
assign data_masked[426] = data_i[426] & sel_one_hot_i[3];
assign data_masked[425] = data_i[425] & sel_one_hot_i[3];
assign data_masked[424] = data_i[424] & sel_one_hot_i[3];
assign data_masked[423] = data_i[423] & sel_one_hot_i[3];
assign data_masked[422] = data_i[422] & sel_one_hot_i[3];
assign data_masked[421] = data_i[421] & sel_one_hot_i[3];
assign data_masked[420] = data_i[420] & sel_one_hot_i[3];
assign data_masked[419] = data_i[419] & sel_one_hot_i[3];
assign data_masked[418] = data_i[418] & sel_one_hot_i[3];
assign data_masked[417] = data_i[417] & sel_one_hot_i[3];
assign data_masked[416] = data_i[416] & sel_one_hot_i[3];
assign data_masked[415] = data_i[415] & sel_one_hot_i[3];
assign data_masked[414] = data_i[414] & sel_one_hot_i[3];
assign data_masked[413] = data_i[413] & sel_one_hot_i[3];
assign data_masked[412] = data_i[412] & sel_one_hot_i[3];
assign data_masked[411] = data_i[411] & sel_one_hot_i[3];
assign data_masked[410] = data_i[410] & sel_one_hot_i[3];
assign data_masked[409] = data_i[409] & sel_one_hot_i[3];
assign data_masked[408] = data_i[408] & sel_one_hot_i[3];
assign data_masked[407] = data_i[407] & sel_one_hot_i[3];
assign data_masked[406] = data_i[406] & sel_one_hot_i[3];
assign data_masked[405] = data_i[405] & sel_one_hot_i[3];
assign data_masked[404] = data_i[404] & sel_one_hot_i[3];
assign data_masked[403] = data_i[403] & sel_one_hot_i[3];
assign data_masked[402] = data_i[402] & sel_one_hot_i[3];
assign data_masked[401] = data_i[401] & sel_one_hot_i[3];
assign data_masked[400] = data_i[400] & sel_one_hot_i[3];
assign data_masked[399] = data_i[399] & sel_one_hot_i[3];
assign data_masked[398] = data_i[398] & sel_one_hot_i[3];
assign data_masked[397] = data_i[397] & sel_one_hot_i[3];
assign data_masked[396] = data_i[396] & sel_one_hot_i[3];
assign data_masked[395] = data_i[395] & sel_one_hot_i[3];
assign data_masked[394] = data_i[394] & sel_one_hot_i[3];
assign data_masked[393] = data_i[393] & sel_one_hot_i[3];
assign data_masked[392] = data_i[392] & sel_one_hot_i[3];
assign data_masked[391] = data_i[391] & sel_one_hot_i[3];
assign data_masked[390] = data_i[390] & sel_one_hot_i[3];
assign data_masked[389] = data_i[389] & sel_one_hot_i[3];
assign data_masked[388] = data_i[388] & sel_one_hot_i[3];
assign data_masked[387] = data_i[387] & sel_one_hot_i[3];
assign data_masked[386] = data_i[386] & sel_one_hot_i[3];
assign data_masked[385] = data_i[385] & sel_one_hot_i[3];
assign data_masked[384] = data_i[384] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[128];
assign N0 = data_masked[384] | data_masked[256];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[129];
assign N2 = data_masked[385] | data_masked[257];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[130];
assign N4 = data_masked[386] | data_masked[258];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[131];
assign N6 = data_masked[387] | data_masked[259];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[132];
assign N8 = data_masked[388] | data_masked[260];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[133];
assign N10 = data_masked[389] | data_masked[261];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[134];
assign N12 = data_masked[390] | data_masked[262];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[135];
assign N14 = data_masked[391] | data_masked[263];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[136];
assign N16 = data_masked[392] | data_masked[264];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[137];
assign N18 = data_masked[393] | data_masked[265];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[138];
assign N20 = data_masked[394] | data_masked[266];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[139];
assign N22 = data_masked[395] | data_masked[267];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[140];
assign N24 = data_masked[396] | data_masked[268];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[141];
assign N26 = data_masked[397] | data_masked[269];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[142];
assign N28 = data_masked[398] | data_masked[270];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[143];
assign N30 = data_masked[399] | data_masked[271];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[144];
assign N32 = data_masked[400] | data_masked[272];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[145];
assign N34 = data_masked[401] | data_masked[273];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[146];
assign N36 = data_masked[402] | data_masked[274];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[147];
assign N38 = data_masked[403] | data_masked[275];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[148];
assign N40 = data_masked[404] | data_masked[276];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[149];
assign N42 = data_masked[405] | data_masked[277];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[150];
assign N44 = data_masked[406] | data_masked[278];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[151];
assign N46 = data_masked[407] | data_masked[279];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[152];
assign N48 = data_masked[408] | data_masked[280];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[153];
assign N50 = data_masked[409] | data_masked[281];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[154];
assign N52 = data_masked[410] | data_masked[282];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[155];
assign N54 = data_masked[411] | data_masked[283];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[156];
assign N56 = data_masked[412] | data_masked[284];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[157];
assign N58 = data_masked[413] | data_masked[285];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[158];
assign N60 = data_masked[414] | data_masked[286];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[159];
assign N62 = data_masked[415] | data_masked[287];
assign data_o[32] = N65 | data_masked[32];
assign N65 = N64 | data_masked[160];
assign N64 = data_masked[416] | data_masked[288];
assign data_o[33] = N67 | data_masked[33];
assign N67 = N66 | data_masked[161];
assign N66 = data_masked[417] | data_masked[289];
assign data_o[34] = N69 | data_masked[34];
assign N69 = N68 | data_masked[162];
assign N68 = data_masked[418] | data_masked[290];
assign data_o[35] = N71 | data_masked[35];
assign N71 = N70 | data_masked[163];
assign N70 = data_masked[419] | data_masked[291];
assign data_o[36] = N73 | data_masked[36];
assign N73 = N72 | data_masked[164];
assign N72 = data_masked[420] | data_masked[292];
assign data_o[37] = N75 | data_masked[37];
assign N75 = N74 | data_masked[165];
assign N74 = data_masked[421] | data_masked[293];
assign data_o[38] = N77 | data_masked[38];
assign N77 = N76 | data_masked[166];
assign N76 = data_masked[422] | data_masked[294];
assign data_o[39] = N79 | data_masked[39];
assign N79 = N78 | data_masked[167];
assign N78 = data_masked[423] | data_masked[295];
assign data_o[40] = N81 | data_masked[40];
assign N81 = N80 | data_masked[168];
assign N80 = data_masked[424] | data_masked[296];
assign data_o[41] = N83 | data_masked[41];
assign N83 = N82 | data_masked[169];
assign N82 = data_masked[425] | data_masked[297];
assign data_o[42] = N85 | data_masked[42];
assign N85 = N84 | data_masked[170];
assign N84 = data_masked[426] | data_masked[298];
assign data_o[43] = N87 | data_masked[43];
assign N87 = N86 | data_masked[171];
assign N86 = data_masked[427] | data_masked[299];
assign data_o[44] = N89 | data_masked[44];
assign N89 = N88 | data_masked[172];
assign N88 = data_masked[428] | data_masked[300];
assign data_o[45] = N91 | data_masked[45];
assign N91 = N90 | data_masked[173];
assign N90 = data_masked[429] | data_masked[301];
assign data_o[46] = N93 | data_masked[46];
assign N93 = N92 | data_masked[174];
assign N92 = data_masked[430] | data_masked[302];
assign data_o[47] = N95 | data_masked[47];
assign N95 = N94 | data_masked[175];
assign N94 = data_masked[431] | data_masked[303];
assign data_o[48] = N97 | data_masked[48];
assign N97 = N96 | data_masked[176];
assign N96 = data_masked[432] | data_masked[304];
assign data_o[49] = N99 | data_masked[49];
assign N99 = N98 | data_masked[177];
assign N98 = data_masked[433] | data_masked[305];
assign data_o[50] = N101 | data_masked[50];
assign N101 = N100 | data_masked[178];
assign N100 = data_masked[434] | data_masked[306];
assign data_o[51] = N103 | data_masked[51];
assign N103 = N102 | data_masked[179];
assign N102 = data_masked[435] | data_masked[307];
assign data_o[52] = N105 | data_masked[52];
assign N105 = N104 | data_masked[180];
assign N104 = data_masked[436] | data_masked[308];
assign data_o[53] = N107 | data_masked[53];
assign N107 = N106 | data_masked[181];
assign N106 = data_masked[437] | data_masked[309];
assign data_o[54] = N109 | data_masked[54];
assign N109 = N108 | data_masked[182];
assign N108 = data_masked[438] | data_masked[310];
assign data_o[55] = N111 | data_masked[55];
assign N111 = N110 | data_masked[183];
assign N110 = data_masked[439] | data_masked[311];
assign data_o[56] = N113 | data_masked[56];
assign N113 = N112 | data_masked[184];
assign N112 = data_masked[440] | data_masked[312];
assign data_o[57] = N115 | data_masked[57];
assign N115 = N114 | data_masked[185];
assign N114 = data_masked[441] | data_masked[313];
assign data_o[58] = N117 | data_masked[58];
assign N117 = N116 | data_masked[186];
assign N116 = data_masked[442] | data_masked[314];
assign data_o[59] = N119 | data_masked[59];
assign N119 = N118 | data_masked[187];
assign N118 = data_masked[443] | data_masked[315];
assign data_o[60] = N121 | data_masked[60];
assign N121 = N120 | data_masked[188];
assign N120 = data_masked[444] | data_masked[316];
assign data_o[61] = N123 | data_masked[61];
assign N123 = N122 | data_masked[189];
assign N122 = data_masked[445] | data_masked[317];
assign data_o[62] = N125 | data_masked[62];
assign N125 = N124 | data_masked[190];
assign N124 = data_masked[446] | data_masked[318];
assign data_o[63] = N127 | data_masked[63];
assign N127 = N126 | data_masked[191];
assign N126 = data_masked[447] | data_masked[319];
assign data_o[64] = N129 | data_masked[64];
assign N129 = N128 | data_masked[192];
assign N128 = data_masked[448] | data_masked[320];
assign data_o[65] = N131 | data_masked[65];
assign N131 = N130 | data_masked[193];
assign N130 = data_masked[449] | data_masked[321];
assign data_o[66] = N133 | data_masked[66];
assign N133 = N132 | data_masked[194];
assign N132 = data_masked[450] | data_masked[322];
assign data_o[67] = N135 | data_masked[67];
assign N135 = N134 | data_masked[195];
assign N134 = data_masked[451] | data_masked[323];
assign data_o[68] = N137 | data_masked[68];
assign N137 = N136 | data_masked[196];
assign N136 = data_masked[452] | data_masked[324];
assign data_o[69] = N139 | data_masked[69];
assign N139 = N138 | data_masked[197];
assign N138 = data_masked[453] | data_masked[325];
assign data_o[70] = N141 | data_masked[70];
assign N141 = N140 | data_masked[198];
assign N140 = data_masked[454] | data_masked[326];
assign data_o[71] = N143 | data_masked[71];
assign N143 = N142 | data_masked[199];
assign N142 = data_masked[455] | data_masked[327];
assign data_o[72] = N145 | data_masked[72];
assign N145 = N144 | data_masked[200];
assign N144 = data_masked[456] | data_masked[328];
assign data_o[73] = N147 | data_masked[73];
assign N147 = N146 | data_masked[201];
assign N146 = data_masked[457] | data_masked[329];
assign data_o[74] = N149 | data_masked[74];
assign N149 = N148 | data_masked[202];
assign N148 = data_masked[458] | data_masked[330];
assign data_o[75] = N151 | data_masked[75];
assign N151 = N150 | data_masked[203];
assign N150 = data_masked[459] | data_masked[331];
assign data_o[76] = N153 | data_masked[76];
assign N153 = N152 | data_masked[204];
assign N152 = data_masked[460] | data_masked[332];
assign data_o[77] = N155 | data_masked[77];
assign N155 = N154 | data_masked[205];
assign N154 = data_masked[461] | data_masked[333];
assign data_o[78] = N157 | data_masked[78];
assign N157 = N156 | data_masked[206];
assign N156 = data_masked[462] | data_masked[334];
assign data_o[79] = N159 | data_masked[79];
assign N159 = N158 | data_masked[207];
assign N158 = data_masked[463] | data_masked[335];
assign data_o[80] = N161 | data_masked[80];
assign N161 = N160 | data_masked[208];
assign N160 = data_masked[464] | data_masked[336];
assign data_o[81] = N163 | data_masked[81];
assign N163 = N162 | data_masked[209];
assign N162 = data_masked[465] | data_masked[337];
assign data_o[82] = N165 | data_masked[82];
assign N165 = N164 | data_masked[210];
assign N164 = data_masked[466] | data_masked[338];
assign data_o[83] = N167 | data_masked[83];
assign N167 = N166 | data_masked[211];
assign N166 = data_masked[467] | data_masked[339];
assign data_o[84] = N169 | data_masked[84];
assign N169 = N168 | data_masked[212];
assign N168 = data_masked[468] | data_masked[340];
assign data_o[85] = N171 | data_masked[85];
assign N171 = N170 | data_masked[213];
assign N170 = data_masked[469] | data_masked[341];
assign data_o[86] = N173 | data_masked[86];
assign N173 = N172 | data_masked[214];
assign N172 = data_masked[470] | data_masked[342];
assign data_o[87] = N175 | data_masked[87];
assign N175 = N174 | data_masked[215];
assign N174 = data_masked[471] | data_masked[343];
assign data_o[88] = N177 | data_masked[88];
assign N177 = N176 | data_masked[216];
assign N176 = data_masked[472] | data_masked[344];
assign data_o[89] = N179 | data_masked[89];
assign N179 = N178 | data_masked[217];
assign N178 = data_masked[473] | data_masked[345];
assign data_o[90] = N181 | data_masked[90];
assign N181 = N180 | data_masked[218];
assign N180 = data_masked[474] | data_masked[346];
assign data_o[91] = N183 | data_masked[91];
assign N183 = N182 | data_masked[219];
assign N182 = data_masked[475] | data_masked[347];
assign data_o[92] = N185 | data_masked[92];
assign N185 = N184 | data_masked[220];
assign N184 = data_masked[476] | data_masked[348];
assign data_o[93] = N187 | data_masked[93];
assign N187 = N186 | data_masked[221];
assign N186 = data_masked[477] | data_masked[349];
assign data_o[94] = N189 | data_masked[94];
assign N189 = N188 | data_masked[222];
assign N188 = data_masked[478] | data_masked[350];
assign data_o[95] = N191 | data_masked[95];
assign N191 = N190 | data_masked[223];
assign N190 = data_masked[479] | data_masked[351];
assign data_o[96] = N193 | data_masked[96];
assign N193 = N192 | data_masked[224];
assign N192 = data_masked[480] | data_masked[352];
assign data_o[97] = N195 | data_masked[97];
assign N195 = N194 | data_masked[225];
assign N194 = data_masked[481] | data_masked[353];
assign data_o[98] = N197 | data_masked[98];
assign N197 = N196 | data_masked[226];
assign N196 = data_masked[482] | data_masked[354];
assign data_o[99] = N199 | data_masked[99];
assign N199 = N198 | data_masked[227];
assign N198 = data_masked[483] | data_masked[355];
assign data_o[100] = N201 | data_masked[100];
assign N201 = N200 | data_masked[228];
assign N200 = data_masked[484] | data_masked[356];
assign data_o[101] = N203 | data_masked[101];
assign N203 = N202 | data_masked[229];
assign N202 = data_masked[485] | data_masked[357];
assign data_o[102] = N205 | data_masked[102];
assign N205 = N204 | data_masked[230];
assign N204 = data_masked[486] | data_masked[358];
assign data_o[103] = N207 | data_masked[103];
assign N207 = N206 | data_masked[231];
assign N206 = data_masked[487] | data_masked[359];
assign data_o[104] = N209 | data_masked[104];
assign N209 = N208 | data_masked[232];
assign N208 = data_masked[488] | data_masked[360];
assign data_o[105] = N211 | data_masked[105];
assign N211 = N210 | data_masked[233];
assign N210 = data_masked[489] | data_masked[361];
assign data_o[106] = N213 | data_masked[106];
assign N213 = N212 | data_masked[234];
assign N212 = data_masked[490] | data_masked[362];
assign data_o[107] = N215 | data_masked[107];
assign N215 = N214 | data_masked[235];
assign N214 = data_masked[491] | data_masked[363];
assign data_o[108] = N217 | data_masked[108];
assign N217 = N216 | data_masked[236];
assign N216 = data_masked[492] | data_masked[364];
assign data_o[109] = N219 | data_masked[109];
assign N219 = N218 | data_masked[237];
assign N218 = data_masked[493] | data_masked[365];
assign data_o[110] = N221 | data_masked[110];
assign N221 = N220 | data_masked[238];
assign N220 = data_masked[494] | data_masked[366];
assign data_o[111] = N223 | data_masked[111];
assign N223 = N222 | data_masked[239];
assign N222 = data_masked[495] | data_masked[367];
assign data_o[112] = N225 | data_masked[112];
assign N225 = N224 | data_masked[240];
assign N224 = data_masked[496] | data_masked[368];
assign data_o[113] = N227 | data_masked[113];
assign N227 = N226 | data_masked[241];
assign N226 = data_masked[497] | data_masked[369];
assign data_o[114] = N229 | data_masked[114];
assign N229 = N228 | data_masked[242];
assign N228 = data_masked[498] | data_masked[370];
assign data_o[115] = N231 | data_masked[115];
assign N231 = N230 | data_masked[243];
assign N230 = data_masked[499] | data_masked[371];
assign data_o[116] = N233 | data_masked[116];
assign N233 = N232 | data_masked[244];
assign N232 = data_masked[500] | data_masked[372];
assign data_o[117] = N235 | data_masked[117];
assign N235 = N234 | data_masked[245];
assign N234 = data_masked[501] | data_masked[373];
assign data_o[118] = N237 | data_masked[118];
assign N237 = N236 | data_masked[246];
assign N236 = data_masked[502] | data_masked[374];
assign data_o[119] = N239 | data_masked[119];
assign N239 = N238 | data_masked[247];
assign N238 = data_masked[503] | data_masked[375];
assign data_o[120] = N241 | data_masked[120];
assign N241 = N240 | data_masked[248];
assign N240 = data_masked[504] | data_masked[376];
assign data_o[121] = N243 | data_masked[121];
assign N243 = N242 | data_masked[249];
assign N242 = data_masked[505] | data_masked[377];
assign data_o[122] = N245 | data_masked[122];
assign N245 = N244 | data_masked[250];
assign N244 = data_masked[506] | data_masked[378];
assign data_o[123] = N247 | data_masked[123];
assign N247 = N246 | data_masked[251];
assign N246 = data_masked[507] | data_masked[379];
assign data_o[124] = N249 | data_masked[124];
assign N249 = N248 | data_masked[252];
assign N248 = data_masked[508] | data_masked[380];
assign data_o[125] = N251 | data_masked[125];
assign N251 = N250 | data_masked[253];
assign N250 = data_masked[509] | data_masked[381];
assign data_o[126] = N253 | data_masked[126];
assign N253 = N252 | data_masked[254];
assign N252 = data_masked[510] | data_masked[382];
assign data_o[127] = N255 | data_masked[127];
assign N255 = N254 | data_masked[255];
assign N254 = data_masked[511] | data_masked[383];
endmodule |
module bsg_concentrate_static_0f
(
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_decode_num_out_p3
(
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
assign o = { 1'b0, 1'b0, 1'b1 } << i;
endmodule |
module bsg_dff_reset_width_p65
(
clk_i,
reset_i,
data_i,
data_o
);
input [64:0] data_i;
output [64:0] data_o;
input clk_i;
input reset_i;
wire [64:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67;
reg data_o_64_sv2v_reg,data_o_63_sv2v_reg,data_o_62_sv2v_reg,data_o_61_sv2v_reg,
data_o_60_sv2v_reg,data_o_59_sv2v_reg,data_o_58_sv2v_reg,data_o_57_sv2v_reg,
data_o_56_sv2v_reg,data_o_55_sv2v_reg,data_o_54_sv2v_reg,data_o_53_sv2v_reg,
data_o_52_sv2v_reg,data_o_51_sv2v_reg,data_o_50_sv2v_reg,data_o_49_sv2v_reg,
data_o_48_sv2v_reg,data_o_47_sv2v_reg,data_o_46_sv2v_reg,data_o_45_sv2v_reg,data_o_44_sv2v_reg,
data_o_43_sv2v_reg,data_o_42_sv2v_reg,data_o_41_sv2v_reg,data_o_40_sv2v_reg,
data_o_39_sv2v_reg,data_o_38_sv2v_reg,data_o_37_sv2v_reg,data_o_36_sv2v_reg,
data_o_35_sv2v_reg,data_o_34_sv2v_reg,data_o_33_sv2v_reg,data_o_32_sv2v_reg,
data_o_31_sv2v_reg,data_o_30_sv2v_reg,data_o_29_sv2v_reg,data_o_28_sv2v_reg,
data_o_27_sv2v_reg,data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,
data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,
data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,
data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,
data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,
data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[64] = data_o_64_sv2v_reg;
assign data_o[63] = data_o_63_sv2v_reg;
assign data_o[62] = data_o_62_sv2v_reg;
assign data_o[61] = data_o_61_sv2v_reg;
assign data_o[60] = data_o_60_sv2v_reg;
assign data_o[59] = data_o_59_sv2v_reg;
assign data_o[58] = data_o_58_sv2v_reg;
assign data_o[57] = data_o_57_sv2v_reg;
assign data_o[56] = data_o_56_sv2v_reg;
assign data_o[55] = data_o_55_sv2v_reg;
assign data_o[54] = data_o_54_sv2v_reg;
assign data_o[53] = data_o_53_sv2v_reg;
assign data_o[52] = data_o_52_sv2v_reg;
assign data_o[51] = data_o_51_sv2v_reg;
assign data_o[50] = data_o_50_sv2v_reg;
assign data_o[49] = data_o_49_sv2v_reg;
assign data_o[48] = data_o_48_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_64_sv2v_reg <= N67;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_63_sv2v_reg <= N66;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_62_sv2v_reg <= N65;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_61_sv2v_reg <= N64;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_60_sv2v_reg <= N63;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_59_sv2v_reg <= N62;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_58_sv2v_reg <= N61;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_57_sv2v_reg <= N60;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_56_sv2v_reg <= N59;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_55_sv2v_reg <= N58;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_54_sv2v_reg <= N57;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_53_sv2v_reg <= N56;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_52_sv2v_reg <= N55;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_51_sv2v_reg <= N54;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_50_sv2v_reg <= N53;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_49_sv2v_reg <= N52;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_48_sv2v_reg <= N51;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_47_sv2v_reg <= N50;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_46_sv2v_reg <= N49;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_45_sv2v_reg <= N48;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_44_sv2v_reg <= N47;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_43_sv2v_reg <= N46;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_42_sv2v_reg <= N45;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_41_sv2v_reg <= N44;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_40_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_39_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_38_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_round_robin_arb_inputs_p1
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [0:0] reqs_i;
output [0:0] grants_o;
output [0:0] sel_one_hot_o;
output [0:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [0:0] grants_o,sel_one_hot_o,tag_o;
wire v_o,N0,N1,N2;
assign tag_o[0] = 1'b0;
assign v_o = reqs_i[0];
assign N2 = ~reqs_i[0];
assign sel_one_hot_o[0] = (N0)? 1'b0 :
(N1)? 1'b1 : 1'b0;
assign N0 = N2;
assign N1 = reqs_i[0];
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
endmodule |
module bsg_hash_bank_banks_p2_width_p5
(
i,
bank_o,
index_o
);
input [4:0] i;
output [0:0] bank_o;
output [3:0] index_o;
wire [0:0] bank_o;
wire [3:0] index_o;
wire index_o_3_,index_o_2_,index_o_1_,index_o_0_;
assign bank_o[0] = i[4];
assign index_o_3_ = i[3];
assign index_o[3] = index_o_3_;
assign index_o_2_ = i[2];
assign index_o[2] = index_o_2_;
assign index_o_1_ = i[1];
assign index_o[1] = index_o_1_;
assign index_o_0_ = i[0];
assign index_o[0] = index_o_0_;
endmodule |
module bsg_mux2_gatestack_width_p2_harden_p1
(
i0,
i1,
i2,
o
);
input [1:0] i0;
input [1:0] i1;
input [1:0] i2;
output [1:0] o;
wire [1:0] o;
wire N0,N1,N2,N3;
assign o[0] = (N0)? i1[0] :
(N2)? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1)? i1[1] :
(N3)? i0[1] : 1'b0;
assign N1 = i2[1];
assign N2 = ~i2[0];
assign N3 = ~i2[1];
endmodule |
module bsg_dff_en_width_p16_harden_p0
(
clk_i,
data_i,
en_i,
data_o
);
input [15:0] data_i;
output [15:0] data_o;
input clk_i;
input en_i;
wire [15:0] data_o;
reg data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,
data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,
data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,
data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(en_i) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_dff_reset_width_p41
(
clk_i,
reset_i,
data_i,
data_o
);
input [40:0] data_i;
output [40:0] data_o;
input clk_i;
input reset_i;
wire [40:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43;
reg data_o_40_sv2v_reg,data_o_39_sv2v_reg,data_o_38_sv2v_reg,data_o_37_sv2v_reg,
data_o_36_sv2v_reg,data_o_35_sv2v_reg,data_o_34_sv2v_reg,data_o_33_sv2v_reg,
data_o_32_sv2v_reg,data_o_31_sv2v_reg,data_o_30_sv2v_reg,data_o_29_sv2v_reg,
data_o_28_sv2v_reg,data_o_27_sv2v_reg,data_o_26_sv2v_reg,data_o_25_sv2v_reg,
data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,
data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,
data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,
data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,
data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,
data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_40_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_39_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_38_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_unconcentrate_static_3
(
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_1_,o_0_;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_dff_width_p4_harden_p0_strength_p2
(
clk_i,
data_i,
data_o
);
input [3:0] data_i;
output [3:0] data_o;
input clk_i;
wire [3:0] data_o;
reg data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_concentrate_static_3
(
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_round_robin_arb_05
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [4:0] reqs_i;
output [4:0] grants_o;
output [4:0] sel_one_hot_o;
output [2:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [4:0] grants_o,sel_one_hot_o;
wire [2:0] tag_o,last_r;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,
N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,
N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,
N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,
N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,
N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195;
reg last_r_2_sv2v_reg,last_r_1_sv2v_reg,last_r_0_sv2v_reg;
assign last_r[2] = last_r_2_sv2v_reg;
assign last_r[1] = last_r_1_sv2v_reg;
assign last_r[0] = last_r_0_sv2v_reg;
assign N21 = N19 & N88;
assign N22 = N21 & N37;
assign N23 = N22 & N20;
assign N27 = N24 & N25;
assign N28 = N26 & reqs_i[1];
assign N29 = N27 & N28;
assign N31 = N24 & N25;
assign N32 = N26 & reqs_i[2];
assign N33 = N31 & N32;
assign N34 = N33 & N30;
assign N35 = N24 & N25;
assign N36 = N26 & reqs_i[3];
assign N37 = N56 & N30;
assign N38 = N35 & N36;
assign N39 = N38 & N37;
assign N40 = last_r[2] | last_r[1];
assign N41 = last_r[0] | N19;
assign N42 = N40 | N41;
assign N43 = N63 | reqs_i[1];
assign N44 = N42 | N43;
assign N46 = last_r[2] | last_r[1];
assign N47 = last_r[0] | reqs_i[4];
assign N48 = reqs_i[1] | N20;
assign N49 = N46 | N47;
assign N50 = N63 | N48;
assign N51 = N49 | N50;
assign N53 = N24 & N25;
assign N54 = last_r[0] & reqs_i[2];
assign N55 = N53 & N54;
assign N57 = N24 & N25;
assign N58 = last_r[0] & reqs_i[3];
assign N59 = N57 & N58;
assign N60 = N59 & N56;
assign N61 = last_r[2] | last_r[1];
assign N62 = N26 | N19;
assign N63 = reqs_i[3] | reqs_i[2];
assign N64 = N61 | N62;
assign N65 = N64 | N63;
assign N67 = N24 & N25;
assign N68 = last_r[0] & N19;
assign N69 = N88 & N56;
assign N70 = N67 & N68;
assign N71 = N69 & reqs_i[0];
assign N72 = N70 & N71;
assign N73 = last_r[2] | last_r[1];
assign N74 = N26 | reqs_i[4];
assign N75 = N30 | reqs_i[0];
assign N76 = N73 | N74;
assign N77 = N63 | N75;
assign N78 = N76 | N77;
assign N80 = N24 & last_r[1];
assign N81 = N26 & reqs_i[3];
assign N82 = N80 & N81;
assign N83 = last_r[2] | N25;
assign N84 = last_r[0] | N19;
assign N85 = N83 | N84;
assign N86 = N85 | reqs_i[3];
assign N89 = N24 & last_r[1];
assign N90 = N26 & N19;
assign N91 = N88 & reqs_i[0];
assign N92 = N89 & N90;
assign N93 = N92 & N91;
assign N94 = N24 & last_r[1];
assign N95 = N26 & N19;
assign N96 = N88 & reqs_i[1];
assign N97 = N94 & N95;
assign N98 = N96 & N20;
assign N99 = N97 & N98;
assign N100 = last_r[2] | N25;
assign N101 = last_r[0] | reqs_i[4];
assign N102 = reqs_i[3] | N56;
assign N103 = reqs_i[1] | reqs_i[0];
assign N104 = N100 | N101;
assign N105 = N102 | N103;
assign N106 = N104 | N105;
assign N108 = last_r[2] | N25;
assign N109 = N26 | N19;
assign N110 = N108 | N109;
assign N112 = N24 & last_r[1];
assign N113 = last_r[0] & N19;
assign N114 = N112 & N113;
assign N115 = N114 & reqs_i[0];
assign N116 = N24 & last_r[1];
assign N117 = last_r[0] & N19;
assign N118 = reqs_i[1] & N20;
assign N119 = N116 & N117;
assign N120 = N119 & N118;
assign N121 = N24 & last_r[1];
assign N122 = last_r[0] & N19;
assign N123 = reqs_i[2] & N30;
assign N124 = N121 & N122;
assign N125 = N123 & N20;
assign N126 = N124 & N125;
assign N127 = last_r[2] | N25;
assign N128 = N26 | reqs_i[4];
assign N129 = N88 | reqs_i[2];
assign N130 = N127 | N128;
assign N131 = N129 | N103;
assign N132 = N130 | N131;
assign N134 = last_r[2] & N25;
assign N135 = N26 & reqs_i[0];
assign N136 = N134 & N135;
assign N137 = last_r[2] & N25;
assign N138 = N26 & reqs_i[1];
assign N139 = N137 & N138;
assign N140 = N139 & N20;
assign N141 = last_r[2] & N25;
assign N142 = N26 & reqs_i[2];
assign N143 = N30 & N20;
assign N144 = N141 & N142;
assign N145 = N144 & N143;
assign N146 = last_r[2] & N25;
assign N147 = N26 & reqs_i[3];
assign N148 = N146 & N147;
assign N149 = N37 & N20;
assign N150 = N148 & N149;
assign N151 = N24 | last_r[1];
assign N152 = last_r[0] | N19;
assign N153 = N151 | N152;
assign N154 = N63 | N103;
assign N155 = N153 | N154;
assign N157 = last_r[2] & last_r[0];
assign N158 = N157 & reqs_i[2];
assign N159 = last_r[2] & last_r[0];
assign N160 = N159 & reqs_i[3];
assign N161 = last_r[2] & last_r[0];
assign N162 = N161 & reqs_i[4];
assign N163 = last_r[2] & last_r[0];
assign N164 = N163 & reqs_i[0];
assign N165 = last_r[2] & last_r[0];
assign N166 = N165 & reqs_i[1];
assign N167 = last_r[2] & last_r[1];
assign N168 = N167 & reqs_i[3];
assign N169 = last_r[2] & last_r[1];
assign N170 = N169 & reqs_i[4];
assign N171 = last_r[2] & last_r[1];
assign N172 = N171 & reqs_i[0];
assign N173 = last_r[2] & last_r[1];
assign N174 = N173 & reqs_i[1];
assign N175 = last_r[2] & last_r[1];
assign N176 = N175 & reqs_i[2];
always @(posedge clk_i) begin
if(N184) begin
last_r_2_sv2v_reg <= N182;
end
end
always @(posedge clk_i) begin
if(N184) begin
last_r_1_sv2v_reg <= N181;
end
end
always @(posedge clk_i) begin
if(N184) begin
last_r_0_sv2v_reg <= N180;
end
end
assign sel_one_hot_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N45)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N52)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N66)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N79)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N7)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N87)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N107)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N111)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N10)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N11)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N12)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N133)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N13)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N14)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N15)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N16)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N156)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N23;
assign N1 = N29;
assign N2 = N34;
assign N3 = N39;
assign N4 = N55;
assign N5 = N60;
assign N6 = N72;
assign N7 = N82;
assign N8 = N93;
assign N9 = N99;
assign N10 = N115;
assign N11 = N120;
assign N12 = N126;
assign N13 = N136;
assign N14 = N140;
assign N15 = N145;
assign N16 = N150;
assign tag_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b1 } :
(N45)? { 1'b1, 1'b0, 1'b0 } :
(N52)? { 1'b0, 1'b0, 1'b0 } :
(N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b1 } :
(N66)? { 1'b1, 1'b0, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0 } :
(N79)? { 1'b0, 1'b0, 1'b1 } :
(N7)? { 1'b0, 1'b1, 1'b1 } :
(N87)? { 1'b1, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b0, 1'b0 } :
(N9)? { 1'b0, 1'b0, 1'b1 } :
(N107)? { 1'b0, 1'b1, 1'b0 } :
(N111)? { 1'b1, 1'b0, 1'b0 } :
(N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? { 1'b0, 1'b0, 1'b1 } :
(N12)? { 1'b0, 1'b1, 1'b0 } :
(N133)? { 1'b0, 1'b1, 1'b1 } :
(N13)? { 1'b0, 1'b0, 1'b0 } :
(N14)? { 1'b0, 1'b0, 1'b1 } :
(N15)? { 1'b0, 1'b1, 1'b0 } :
(N16)? { 1'b0, 1'b1, 1'b1 } :
(N156)? { 1'b1, 1'b0, 1'b0 } :
(N177)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign { N182, N181, N180 } = (N17)? { 1'b0, 1'b0, 1'b0 } :
(N18)? tag_o : 1'b0;
assign N17 = reset_i;
assign N18 = N179;
assign N19 = ~reqs_i[4];
assign N20 = ~reqs_i[0];
assign N24 = ~last_r[2];
assign N25 = ~last_r[1];
assign N26 = ~last_r[0];
assign N30 = ~reqs_i[1];
assign N45 = ~N44;
assign N52 = ~N51;
assign N56 = ~reqs_i[2];
assign N66 = ~N65;
assign N79 = ~N78;
assign N87 = ~N86;
assign N88 = ~reqs_i[3];
assign N107 = ~N106;
assign N111 = ~N110;
assign N133 = ~N132;
assign N156 = ~N155;
assign N177 = N158 | N192;
assign N192 = N160 | N191;
assign N191 = N162 | N190;
assign N190 = N164 | N189;
assign N189 = N166 | N188;
assign N188 = N168 | N187;
assign N187 = N170 | N186;
assign N186 = N172 | N185;
assign N185 = N174 | N176;
assign grants_o[4] = sel_one_hot_o[4] & grants_en_i;
assign grants_o[3] = sel_one_hot_o[3] & grants_en_i;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N195 | reqs_i[0];
assign N195 = N194 | reqs_i[1];
assign N194 = N193 | reqs_i[2];
assign N193 = reqs_i[4] | reqs_i[3];
assign N178 = ~yumi_i;
assign N179 = ~reset_i;
assign N183 = N178 & N179;
assign N184 = ~N183;
endmodule |
module bsg_dff_reset_en_width_p1_reset_val_p0
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [0:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6;
reg data_o_0_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N6)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign N4 = (N0)? 1'b0 :
(N6)? data_i[0] : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N5 = ~reset_i;
assign N6 = en_i & N5;
endmodule |
module bsg_launch_sync_sync_async_reset_negedge_5_unit
(
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [4:0] iclk_data_i;
output [4:0] iclk_data_o;
output [4:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [4:0] iclk_data_o,oclk_data_o,bsg_SYNC_1_r;
wire N0;
reg iclk_data_o_4_sv2v_reg,iclk_data_o_3_sv2v_reg,iclk_data_o_2_sv2v_reg,
iclk_data_o_1_sv2v_reg,iclk_data_o_0_sv2v_reg,bsg_SYNC_1_r_4_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,bsg_SYNC_1_r_2_sv2v_reg,bsg_SYNC_1_r_1_sv2v_reg,bsg_SYNC_1_r_0_sv2v_reg,
oclk_data_o_4_sv2v_reg,oclk_data_o_3_sv2v_reg,oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,oclk_data_o_0_sv2v_reg;
assign iclk_data_o[4] = iclk_data_o_4_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[4] = bsg_SYNC_1_r_4_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[4] = oclk_data_o_4_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge N0 or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
iclk_data_o_4_sv2v_reg <= 1'b0;
end else if(1'b1) begin
iclk_data_o_4_sv2v_reg <= iclk_data_i[4];
end
end
always @(posedge N0 or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
iclk_data_o_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
iclk_data_o_3_sv2v_reg <= iclk_data_i[3];
end
end
always @(posedge N0 or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
iclk_data_o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
iclk_data_o_2_sv2v_reg <= iclk_data_i[2];
end
end
always @(posedge N0 or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
iclk_data_o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
iclk_data_o_1_sv2v_reg <= iclk_data_i[1];
end
end
always @(posedge N0 or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
iclk_data_o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
iclk_data_o_0_sv2v_reg <= iclk_data_i[0];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
bsg_SYNC_1_r_4_sv2v_reg <= 1'b0;
end else if(1'b1) begin
bsg_SYNC_1_r_4_sv2v_reg <= iclk_data_o[4];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
bsg_SYNC_1_r_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
bsg_SYNC_1_r_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
bsg_SYNC_1_r_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
bsg_SYNC_1_r_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
oclk_data_o_4_sv2v_reg <= 1'b0;
end else if(1'b1) begin
oclk_data_o_4_sv2v_reg <= bsg_SYNC_1_r[4];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
oclk_data_o_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
oclk_data_o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
oclk_data_o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
end
end
always @(posedge oclk_i or posedge iclk_reset_i) begin
if(iclk_reset_i) begin
oclk_data_o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign N0 = ~iclk_i;
endmodule |
module bsg_array_concentrate_static_1b_128
(
i,
o
);
input [639:0] i;
output [511:0] o;
wire [511:0] o;
assign o[511] = i[639];
assign o[510] = i[638];
assign o[509] = i[637];
assign o[508] = i[636];
assign o[507] = i[635];
assign o[506] = i[634];
assign o[505] = i[633];
assign o[504] = i[632];
assign o[503] = i[631];
assign o[502] = i[630];
assign o[501] = i[629];
assign o[500] = i[628];
assign o[499] = i[627];
assign o[498] = i[626];
assign o[497] = i[625];
assign o[496] = i[624];
assign o[495] = i[623];
assign o[494] = i[622];
assign o[493] = i[621];
assign o[492] = i[620];
assign o[491] = i[619];
assign o[490] = i[618];
assign o[489] = i[617];
assign o[488] = i[616];
assign o[487] = i[615];
assign o[486] = i[614];
assign o[485] = i[613];
assign o[484] = i[612];
assign o[483] = i[611];
assign o[482] = i[610];
assign o[481] = i[609];
assign o[480] = i[608];
assign o[479] = i[607];
assign o[478] = i[606];
assign o[477] = i[605];
assign o[476] = i[604];
assign o[475] = i[603];
assign o[474] = i[602];
assign o[473] = i[601];
assign o[472] = i[600];
assign o[471] = i[599];
assign o[470] = i[598];
assign o[469] = i[597];
assign o[468] = i[596];
assign o[467] = i[595];
assign o[466] = i[594];
assign o[465] = i[593];
assign o[464] = i[592];
assign o[463] = i[591];
assign o[462] = i[590];
assign o[461] = i[589];
assign o[460] = i[588];
assign o[459] = i[587];
assign o[458] = i[586];
assign o[457] = i[585];
assign o[456] = i[584];
assign o[455] = i[583];
assign o[454] = i[582];
assign o[453] = i[581];
assign o[452] = i[580];
assign o[451] = i[579];
assign o[450] = i[578];
assign o[449] = i[577];
assign o[448] = i[576];
assign o[447] = i[575];
assign o[446] = i[574];
assign o[445] = i[573];
assign o[444] = i[572];
assign o[443] = i[571];
assign o[442] = i[570];
assign o[441] = i[569];
assign o[440] = i[568];
assign o[439] = i[567];
assign o[438] = i[566];
assign o[437] = i[565];
assign o[436] = i[564];
assign o[435] = i[563];
assign o[434] = i[562];
assign o[433] = i[561];
assign o[432] = i[560];
assign o[431] = i[559];
assign o[430] = i[558];
assign o[429] = i[557];
assign o[428] = i[556];
assign o[427] = i[555];
assign o[426] = i[554];
assign o[425] = i[553];
assign o[424] = i[552];
assign o[423] = i[551];
assign o[422] = i[550];
assign o[421] = i[549];
assign o[420] = i[548];
assign o[419] = i[547];
assign o[418] = i[546];
assign o[417] = i[545];
assign o[416] = i[544];
assign o[415] = i[543];
assign o[414] = i[542];
assign o[413] = i[541];
assign o[412] = i[540];
assign o[411] = i[539];
assign o[410] = i[538];
assign o[409] = i[537];
assign o[408] = i[536];
assign o[407] = i[535];
assign o[406] = i[534];
assign o[405] = i[533];
assign o[404] = i[532];
assign o[403] = i[531];
assign o[402] = i[530];
assign o[401] = i[529];
assign o[400] = i[528];
assign o[399] = i[527];
assign o[398] = i[526];
assign o[397] = i[525];
assign o[396] = i[524];
assign o[395] = i[523];
assign o[394] = i[522];
assign o[393] = i[521];
assign o[392] = i[520];
assign o[391] = i[519];
assign o[390] = i[518];
assign o[389] = i[517];
assign o[388] = i[516];
assign o[387] = i[515];
assign o[386] = i[514];
assign o[385] = i[513];
assign o[384] = i[512];
assign o[383] = i[511];
assign o[382] = i[510];
assign o[381] = i[509];
assign o[380] = i[508];
assign o[379] = i[507];
assign o[378] = i[506];
assign o[377] = i[505];
assign o[376] = i[504];
assign o[375] = i[503];
assign o[374] = i[502];
assign o[373] = i[501];
assign o[372] = i[500];
assign o[371] = i[499];
assign o[370] = i[498];
assign o[369] = i[497];
assign o[368] = i[496];
assign o[367] = i[495];
assign o[366] = i[494];
assign o[365] = i[493];
assign o[364] = i[492];
assign o[363] = i[491];
assign o[362] = i[490];
assign o[361] = i[489];
assign o[360] = i[488];
assign o[359] = i[487];
assign o[358] = i[486];
assign o[357] = i[485];
assign o[356] = i[484];
assign o[355] = i[483];
assign o[354] = i[482];
assign o[353] = i[481];
assign o[352] = i[480];
assign o[351] = i[479];
assign o[350] = i[478];
assign o[349] = i[477];
assign o[348] = i[476];
assign o[347] = i[475];
assign o[346] = i[474];
assign o[345] = i[473];
assign o[344] = i[472];
assign o[343] = i[471];
assign o[342] = i[470];
assign o[341] = i[469];
assign o[340] = i[468];
assign o[339] = i[467];
assign o[338] = i[466];
assign o[337] = i[465];
assign o[336] = i[464];
assign o[335] = i[463];
assign o[334] = i[462];
assign o[333] = i[461];
assign o[332] = i[460];
assign o[331] = i[459];
assign o[330] = i[458];
assign o[329] = i[457];
assign o[328] = i[456];
assign o[327] = i[455];
assign o[326] = i[454];
assign o[325] = i[453];
assign o[324] = i[452];
assign o[323] = i[451];
assign o[322] = i[450];
assign o[321] = i[449];
assign o[320] = i[448];
assign o[319] = i[447];
assign o[318] = i[446];
assign o[317] = i[445];
assign o[316] = i[444];
assign o[315] = i[443];
assign o[314] = i[442];
assign o[313] = i[441];
assign o[312] = i[440];
assign o[311] = i[439];
assign o[310] = i[438];
assign o[309] = i[437];
assign o[308] = i[436];
assign o[307] = i[435];
assign o[306] = i[434];
assign o[305] = i[433];
assign o[304] = i[432];
assign o[303] = i[431];
assign o[302] = i[430];
assign o[301] = i[429];
assign o[300] = i[428];
assign o[299] = i[427];
assign o[298] = i[426];
assign o[297] = i[425];
assign o[296] = i[424];
assign o[295] = i[423];
assign o[294] = i[422];
assign o[293] = i[421];
assign o[292] = i[420];
assign o[291] = i[419];
assign o[290] = i[418];
assign o[289] = i[417];
assign o[288] = i[416];
assign o[287] = i[415];
assign o[286] = i[414];
assign o[285] = i[413];
assign o[284] = i[412];
assign o[283] = i[411];
assign o[282] = i[410];
assign o[281] = i[409];
assign o[280] = i[408];
assign o[279] = i[407];
assign o[278] = i[406];
assign o[277] = i[405];
assign o[276] = i[404];
assign o[275] = i[403];
assign o[274] = i[402];
assign o[273] = i[401];
assign o[272] = i[400];
assign o[271] = i[399];
assign o[270] = i[398];
assign o[269] = i[397];
assign o[268] = i[396];
assign o[267] = i[395];
assign o[266] = i[394];
assign o[265] = i[393];
assign o[264] = i[392];
assign o[263] = i[391];
assign o[262] = i[390];
assign o[261] = i[389];
assign o[260] = i[388];
assign o[259] = i[387];
assign o[258] = i[386];
assign o[257] = i[385];
assign o[256] = i[384];
assign o[255] = i[255];
assign o[254] = i[254];
assign o[253] = i[253];
assign o[252] = i[252];
assign o[251] = i[251];
assign o[250] = i[250];
assign o[249] = i[249];
assign o[248] = i[248];
assign o[247] = i[247];
assign o[246] = i[246];
assign o[245] = i[245];
assign o[244] = i[244];
assign o[243] = i[243];
assign o[242] = i[242];
assign o[241] = i[241];
assign o[240] = i[240];
assign o[239] = i[239];
assign o[238] = i[238];
assign o[237] = i[237];
assign o[236] = i[236];
assign o[235] = i[235];
assign o[234] = i[234];
assign o[233] = i[233];
assign o[232] = i[232];
assign o[231] = i[231];
assign o[230] = i[230];
assign o[229] = i[229];
assign o[228] = i[228];
assign o[227] = i[227];
assign o[226] = i[226];
assign o[225] = i[225];
assign o[224] = i[224];
assign o[223] = i[223];
assign o[222] = i[222];
assign o[221] = i[221];
assign o[220] = i[220];
assign o[219] = i[219];
assign o[218] = i[218];
assign o[217] = i[217];
assign o[216] = i[216];
assign o[215] = i[215];
assign o[214] = i[214];
assign o[213] = i[213];
assign o[212] = i[212];
assign o[211] = i[211];
assign o[210] = i[210];
assign o[209] = i[209];
assign o[208] = i[208];
assign o[207] = i[207];
assign o[206] = i[206];
assign o[205] = i[205];
assign o[204] = i[204];
assign o[203] = i[203];
assign o[202] = i[202];
assign o[201] = i[201];
assign o[200] = i[200];
assign o[199] = i[199];
assign o[198] = i[198];
assign o[197] = i[197];
assign o[196] = i[196];
assign o[195] = i[195];
assign o[194] = i[194];
assign o[193] = i[193];
assign o[192] = i[192];
assign o[191] = i[191];
assign o[190] = i[190];
assign o[189] = i[189];
assign o[188] = i[188];
assign o[187] = i[187];
assign o[186] = i[186];
assign o[185] = i[185];
assign o[184] = i[184];
assign o[183] = i[183];
assign o[182] = i[182];
assign o[181] = i[181];
assign o[180] = i[180];
assign o[179] = i[179];
assign o[178] = i[178];
assign o[177] = i[177];
assign o[176] = i[176];
assign o[175] = i[175];
assign o[174] = i[174];
assign o[173] = i[173];
assign o[172] = i[172];
assign o[171] = i[171];
assign o[170] = i[170];
assign o[169] = i[169];
assign o[168] = i[168];
assign o[167] = i[167];
assign o[166] = i[166];
assign o[165] = i[165];
assign o[164] = i[164];
assign o[163] = i[163];
assign o[162] = i[162];
assign o[161] = i[161];
assign o[160] = i[160];
assign o[159] = i[159];
assign o[158] = i[158];
assign o[157] = i[157];
assign o[156] = i[156];
assign o[155] = i[155];
assign o[154] = i[154];
assign o[153] = i[153];
assign o[152] = i[152];
assign o[151] = i[151];
assign o[150] = i[150];
assign o[149] = i[149];
assign o[148] = i[148];
assign o[147] = i[147];
assign o[146] = i[146];
assign o[145] = i[145];
assign o[144] = i[144];
assign o[143] = i[143];
assign o[142] = i[142];
assign o[141] = i[141];
assign o[140] = i[140];
assign o[139] = i[139];
assign o[138] = i[138];
assign o[137] = i[137];
assign o[136] = i[136];
assign o[135] = i[135];
assign o[134] = i[134];
assign o[133] = i[133];
assign o[132] = i[132];
assign o[131] = i[131];
assign o[130] = i[130];
assign o[129] = i[129];
assign o[128] = i[128];
assign o[127] = i[127];
assign o[126] = i[126];
assign o[125] = i[125];
assign o[124] = i[124];
assign o[123] = i[123];
assign o[122] = i[122];
assign o[121] = i[121];
assign o[120] = i[120];
assign o[119] = i[119];
assign o[118] = i[118];
assign o[117] = i[117];
assign o[116] = i[116];
assign o[115] = i[115];
assign o[114] = i[114];
assign o[113] = i[113];
assign o[112] = i[112];
assign o[111] = i[111];
assign o[110] = i[110];
assign o[109] = i[109];
assign o[108] = i[108];
assign o[107] = i[107];
assign o[106] = i[106];
assign o[105] = i[105];
assign o[104] = i[104];
assign o[103] = i[103];
assign o[102] = i[102];
assign o[101] = i[101];
assign o[100] = i[100];
assign o[99] = i[99];
assign o[98] = i[98];
assign o[97] = i[97];
assign o[96] = i[96];
assign o[95] = i[95];
assign o[94] = i[94];
assign o[93] = i[93];
assign o[92] = i[92];
assign o[91] = i[91];
assign o[90] = i[90];
assign o[89] = i[89];
assign o[88] = i[88];
assign o[87] = i[87];
assign o[86] = i[86];
assign o[85] = i[85];
assign o[84] = i[84];
assign o[83] = i[83];
assign o[82] = i[82];
assign o[81] = i[81];
assign o[80] = i[80];
assign o[79] = i[79];
assign o[78] = i[78];
assign o[77] = i[77];
assign o[76] = i[76];
assign o[75] = i[75];
assign o[74] = i[74];
assign o[73] = i[73];
assign o[72] = i[72];
assign o[71] = i[71];
assign o[70] = i[70];
assign o[69] = i[69];
assign o[68] = i[68];
assign o[67] = i[67];
assign o[66] = i[66];
assign o[65] = i[65];
assign o[64] = i[64];
assign o[63] = i[63];
assign o[62] = i[62];
assign o[61] = i[61];
assign o[60] = i[60];
assign o[59] = i[59];
assign o[58] = i[58];
assign o[57] = i[57];
assign o[56] = i[56];
assign o[55] = i[55];
assign o[54] = i[54];
assign o[53] = i[53];
assign o[52] = i[52];
assign o[51] = i[51];
assign o[50] = i[50];
assign o[49] = i[49];
assign o[48] = i[48];
assign o[47] = i[47];
assign o[46] = i[46];
assign o[45] = i[45];
assign o[44] = i[44];
assign o[43] = i[43];
assign o[42] = i[42];
assign o[41] = i[41];
assign o[40] = i[40];
assign o[39] = i[39];
assign o[38] = i[38];
assign o[37] = i[37];
assign o[36] = i[36];
assign o[35] = i[35];
assign o[34] = i[34];
assign o[33] = i[33];
assign o[32] = i[32];
assign o[31] = i[31];
assign o[30] = i[30];
assign o[29] = i[29];
assign o[28] = i[28];
assign o[27] = i[27];
assign o[26] = i[26];
assign o[25] = i[25];
assign o[24] = i[24];
assign o[23] = i[23];
assign o[22] = i[22];
assign o[21] = i[21];
assign o[20] = i[20];
assign o[19] = i[19];
assign o[18] = i[18];
assign o[17] = i[17];
assign o[16] = i[16];
assign o[15] = i[15];
assign o[14] = i[14];
assign o[13] = i[13];
assign o[12] = i[12];
assign o[11] = i[11];
assign o[10] = i[10];
assign o[9] = i[9];
assign o[8] = i[8];
assign o[7] = i[7];
assign o[6] = i[6];
assign o[5] = i[5];
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_reset_en_width_p3_harden_p1
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [2:0] data_i;
output [2:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [2:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
reg data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N8)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N8)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N7 = ~reset_i;
assign N8 = en_i & N7;
endmodule |
module bp_be_int_alu
(
src1_i,
src2_i,
op_i,
opw_v_i,
result_o
);
input [63:0] src1_i;
input [63:0] src2_i;
input [4:0] op_i;
output [63:0] result_o;
input opw_v_i;
wire [63:0] result_o,result_sgn;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,
N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,
N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,N260,N261,
N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,N274,N275,N276,N277,
N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,N290,N291,N292,N293,
N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,
N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,
N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,N338,N339,N340,N341,
N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,N354,N355,N356,N357,
N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,N370,N371,N372,N373,
N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,N385,N386,N387,N388,N389,
N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,N401,N402,N403,N404,N405,
N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,N417,N418,N419,N420,N421,
N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,N433,N434,N435,N436,N437,
N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,N449,N450,N451,N452,N453,
N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,N465,N466,N467,N468,N469,
N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,N481,N482,N483,N484,N485,
N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,N497,N498,N499,N500,N501,
N502,N503,N504,N505,N506,N507,N508,N509,N510,N511,N512,N513,N514,N515,N516,N517,
N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,N529,N530,N531,N532,N533,
N534,N535,N536,N537,N538,N539,N540,N541,N542,N543,N544,N545,N546,N547,N548,N549,
N550,N551,N552,N553,N554,N555,N556,N557,N558,N559,N560,N561,N562,N563,N564,N565,
N566,N567,N568,N569,N570,N571,N572,N573,N574,N575,N576,N577,N578,N579,N580,N581,
N582,N583,N584,N585,N586,N587,N588,N589,N590,N591,N592,N593,N594,N595,N596,N597,
N598,N599,N600,N601,N602,N603,N604,N605,N606,N607,N608,N609,N610,N611,N612,N613,
N614,N615,N616,N617,N618,N619,N620,N621,N622,N623,N624,N625,N626,N627,N628,N629,
N630,N631,N632,N633,N634,N635,N636,N637,N638,N639,N640,N641,N642,N643,N644,N645,
N646,N647,N648,N649,N650,N651,N652,N653,N654,N655,N656,N657,N658,N659,N660,N661,
N662,N663,N664,N665,N666,N667,N668,N669,N670,N671,N672,N673,N674,N675,N676,N677,
N678,N679,N680,N681,N682,N683,N684,N685,N686,N687,N688,N689,N690,N691,N692,N693,
N694,N695,N696,N697,N698,N699,N700,N701,N702,N703,N704,N705,N706,N707,N708,N709,
N710,N711,N712,N713,N714,N715,N716,N717,N718,N719,N720,N721,N722,N723,N724,N725,
N726,N727,N728,N729,N730,N731,N732,N733,N734,N735,N736,N737,N738,N739,N740,N741,
N742,N743,N744,N745,N746,N747,N748,N749,N750,N751,N752,N753,N754,N755,N756,N757,
N758,N759,N760,N761,N762,N763,N764,N765,N766,N767,N768,N769,N770,N771,N772,N773,
N774,N775,N776,N777,N778,N779,N780,N781,N782,N783,N784,N785,N786,N787,N788,N789,
N790,N791,N792,N793,N794,N795,N796,N797,N798,N799,N800,N801,N802,N803,N804,N805,
N806,N807,N808,N809,N810,N811,N812,N813,N814,N815,N816,N817,N818,N819,N820,N821,
N822,N823,N824,N825,N826,N827,N828,N829,N830,N831,N832,N833,N834,N835,N836,N837,
N838,N839,N840,N841,N842,N843,N844,N845,N846,N847,N848,N849,N850,N851,N852,N853,
N854,N855,N856,N857,N858,N859,N860,N861,N862,N863,N864;
wire [31:0] resultw_sgn;
assign N27 = N238 & N249;
assign N30 = N40 & N244;
assign N31 = N30 & N41;
assign N32 = N42 | op_i[0];
assign N34 = op_i[3] | op_i[2];
assign N35 = N34 | N41;
assign N37 = N245 | N41;
assign N39 = N263 & op_i[0];
assign N42 = N40 | op_i[2];
assign N43 = N42 | N41;
assign N44 = op_i[2] & N41;
assign { N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110 } = src1_i[31:0] << src2_i[4:0];
assign { N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142 } = src1_i[31:0] >> src2_i[4:0];
assign { N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174 } = $signed(src1_i[31:0]) >>> src2_i[4:0];
assign N240 = N249 & N41;
assign N241 = N30 & N240;
assign N242 = N42 | N246;
assign N245 = op_i[3] | N244;
assign N246 = op_i[1] | op_i[0];
assign N247 = N245 | N246;
assign N250 = N249 | op_i[0];
assign N251 = N245 | N250;
assign N253 = N249 | N41;
assign N254 = N245 | N253;
assign N256 = N34 | N278;
assign N258 = N245 | N278;
assign N260 = N40 | N244;
assign N261 = N260 | N278;
assign N263 = op_i[3] & op_i[2];
assign N264 = op_i[1] & op_i[0];
assign N265 = N263 & N264;
assign N266 = N34 | N250;
assign N268 = N42 | N250;
assign N270 = N260 | N246;
assign N272 = N260 | N250;
assign N274 = N34 | N253;
assign N276 = N42 | N253;
assign N278 = op_i[1] | N41;
assign N279 = N42 | N278;
assign { N664, N663, N662, N661, N660, N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601 } = src1_i << src2_i[5:0];
assign { N728, N727, N726, N725, N724, N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665 } = src1_i >> src2_i[5:0];
assign { N792, N791, N790, N789, N788, N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729 } = $signed(src1_i) >>> src2_i[5:0];
assign N793 = $signed(src1_i) < $signed(src2_i);
assign N794 = $signed(src1_i) >= $signed(src2_i);
assign N795 = src1_i == src2_i;
assign N796 = src1_i != src2_i;
assign N797 = src1_i < src2_i;
assign N798 = src1_i >= src2_i;
assign { N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46 } = $signed(src1_i[31:0]) + $signed(src2_i[31:0]);
assign { N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281 } = $signed(src1_i) + $signed(src2_i);
assign { N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78 } = $signed(src1_i[31:0]) - $signed(src2_i[31:0]);
assign { N408, N407, N406, N405, N404, N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345 } = $signed(src1_i) - $signed(src2_i);
assign { N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206 } = (N0)? { N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46 } :
(N1)? { N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78 } :
(N2)? { N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110 } :
(N3)? { N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142 } :
(N4)? { N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N31;
assign N1 = N33;
assign N2 = N36;
assign N3 = N38;
assign N4 = N39;
assign N5 = N45;
assign resultw_sgn = (N6)? { N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206 } :
(N28)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N6 = N27;
assign { N862, N861, N860, N859, N858, N857, N856, N855, N854, N853, N852, N851, N850, N849, N848, N847, N846, N845, N844, N843, N842, N841, N840, N839, N838, N837, N836, N835, N834, N833, N832, N831, N830, N829, N828, N827, N826, N825, N824, N823, N822, N821, N820, N819, N818, N817, N816, N815, N814, N813, N812, N811, N810, N809, N808, N807, N806, N805, N804, N803, N802, N801, N800, N799 } = (N7)? { N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281 } :
(N8)? { N408, N407, N406, N405, N404, N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345 } :
(N9)? { N409, N410, N411, N412, N413, N414, N415, N416, N417, N418, N419, N420, N421, N422, N423, N424, N425, N426, N427, N428, N429, N430, N431, N432, N433, N434, N435, N436, N437, N438, N439, N440, N441, N442, N443, N444, N445, N446, N447, N448, N449, N450, N451, N452, N453, N454, N455, N456, N457, N458, N459, N460, N461, N462, N463, N464, N465, N466, N467, N468, N469, N470, N471, N472 } :
(N10)? { N473, N474, N475, N476, N477, N478, N479, N480, N481, N482, N483, N484, N485, N486, N487, N488, N489, N490, N491, N492, N493, N494, N495, N496, N497, N498, N499, N500, N501, N502, N503, N504, N505, N506, N507, N508, N509, N510, N511, N512, N513, N514, N515, N516, N517, N518, N519, N520, N521, N522, N523, N524, N525, N526, N527, N528, N529, N530, N531, N532, N533, N534, N535, N536 } :
(N11)? { N537, N538, N539, N540, N541, N542, N543, N544, N545, N546, N547, N548, N549, N550, N551, N552, N553, N554, N555, N556, N557, N558, N559, N560, N561, N562, N563, N564, N565, N566, N567, N568, N569, N570, N571, N572, N573, N574, N575, N576, N577, N578, N579, N580, N581, N582, N583, N584, N585, N586, N587, N588, N589, N590, N591, N592, N593, N594, N595, N596, N597, N598, N599, N600 } :
(N12)? { N664, N663, N662, N661, N660, N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601 } :
(N13)? { N728, N727, N726, N725, N724, N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665 } :
(N14)? { N792, N791, N790, N789, N788, N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729 } :
(N15)? src2_i :
(N16)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N793 } :
(N17)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N794 } :
(N18)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N795 } :
(N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N796 } :
(N20)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N797 } :
(N21)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N798 } :
(N22)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N7 = N241;
assign N8 = N243;
assign N9 = N248;
assign N10 = N252;
assign N11 = N255;
assign N12 = N257;
assign N13 = N259;
assign N14 = N262;
assign N15 = N265;
assign N16 = N267;
assign N17 = N269;
assign N18 = N271;
assign N19 = N273;
assign N20 = N275;
assign N21 = N277;
assign N22 = N280;
assign result_sgn = (N23)? { N862, N861, N860, N859, N858, N857, N856, N855, N854, N853, N852, N851, N850, N849, N848, N847, N846, N845, N844, N843, N842, N841, N840, N839, N838, N837, N836, N835, N834, N833, N832, N831, N830, N829, N828, N827, N826, N825, N824, N823, N822, N821, N820, N819, N818, N817, N816, N815, N814, N813, N812, N811, N810, N809, N808, N807, N806, N805, N804, N803, N802, N801, N800, N799 } :
(N24)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N23 = N238;
assign N24 = op_i[4];
assign result_o = (N25)? { resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn } :
(N26)? result_sgn : 1'b0;
assign N25 = opw_v_i;
assign N26 = N863;
assign N28 = ~N27;
assign N29 = N27;
assign N33 = ~N32;
assign N36 = ~N35;
assign N38 = ~N37;
assign N40 = ~op_i[3];
assign N41 = ~op_i[0];
assign N45 = N864 | N44;
assign N864 = ~N43;
assign N238 = ~op_i[4];
assign N239 = N238;
assign N243 = ~N242;
assign N244 = ~op_i[2];
assign N248 = ~N247;
assign N249 = ~op_i[1];
assign N252 = ~N251;
assign N255 = ~N254;
assign N257 = ~N256;
assign N259 = ~N258;
assign N262 = ~N261;
assign N267 = ~N266;
assign N269 = ~N268;
assign N271 = ~N270;
assign N273 = ~N272;
assign N275 = ~N274;
assign N277 = ~N276;
assign N280 = ~N279;
assign N409 = src1_i[63] ^ src2_i[63];
assign N410 = src1_i[62] ^ src2_i[62];
assign N411 = src1_i[61] ^ src2_i[61];
assign N412 = src1_i[60] ^ src2_i[60];
assign N413 = src1_i[59] ^ src2_i[59];
assign N414 = src1_i[58] ^ src2_i[58];
assign N415 = src1_i[57] ^ src2_i[57];
assign N416 = src1_i[56] ^ src2_i[56];
assign N417 = src1_i[55] ^ src2_i[55];
assign N418 = src1_i[54] ^ src2_i[54];
assign N419 = src1_i[53] ^ src2_i[53];
assign N420 = src1_i[52] ^ src2_i[52];
assign N421 = src1_i[51] ^ src2_i[51];
assign N422 = src1_i[50] ^ src2_i[50];
assign N423 = src1_i[49] ^ src2_i[49];
assign N424 = src1_i[48] ^ src2_i[48];
assign N425 = src1_i[47] ^ src2_i[47];
assign N426 = src1_i[46] ^ src2_i[46];
assign N427 = src1_i[45] ^ src2_i[45];
assign N428 = src1_i[44] ^ src2_i[44];
assign N429 = src1_i[43] ^ src2_i[43];
assign N430 = src1_i[42] ^ src2_i[42];
assign N431 = src1_i[41] ^ src2_i[41];
assign N432 = src1_i[40] ^ src2_i[40];
assign N433 = src1_i[39] ^ src2_i[39];
assign N434 = src1_i[38] ^ src2_i[38];
assign N435 = src1_i[37] ^ src2_i[37];
assign N436 = src1_i[36] ^ src2_i[36];
assign N437 = src1_i[35] ^ src2_i[35];
assign N438 = src1_i[34] ^ src2_i[34];
assign N439 = src1_i[33] ^ src2_i[33];
assign N440 = src1_i[32] ^ src2_i[32];
assign N441 = src1_i[31] ^ src2_i[31];
assign N442 = src1_i[30] ^ src2_i[30];
assign N443 = src1_i[29] ^ src2_i[29];
assign N444 = src1_i[28] ^ src2_i[28];
assign N445 = src1_i[27] ^ src2_i[27];
assign N446 = src1_i[26] ^ src2_i[26];
assign N447 = src1_i[25] ^ src2_i[25];
assign N448 = src1_i[24] ^ src2_i[24];
assign N449 = src1_i[23] ^ src2_i[23];
assign N450 = src1_i[22] ^ src2_i[22];
assign N451 = src1_i[21] ^ src2_i[21];
assign N452 = src1_i[20] ^ src2_i[20];
assign N453 = src1_i[19] ^ src2_i[19];
assign N454 = src1_i[18] ^ src2_i[18];
assign N455 = src1_i[17] ^ src2_i[17];
assign N456 = src1_i[16] ^ src2_i[16];
assign N457 = src1_i[15] ^ src2_i[15];
assign N458 = src1_i[14] ^ src2_i[14];
assign N459 = src1_i[13] ^ src2_i[13];
assign N460 = src1_i[12] ^ src2_i[12];
assign N461 = src1_i[11] ^ src2_i[11];
assign N462 = src1_i[10] ^ src2_i[10];
assign N463 = src1_i[9] ^ src2_i[9];
assign N464 = src1_i[8] ^ src2_i[8];
assign N465 = src1_i[7] ^ src2_i[7];
assign N466 = src1_i[6] ^ src2_i[6];
assign N467 = src1_i[5] ^ src2_i[5];
assign N468 = src1_i[4] ^ src2_i[4];
assign N469 = src1_i[3] ^ src2_i[3];
assign N470 = src1_i[2] ^ src2_i[2];
assign N471 = src1_i[1] ^ src2_i[1];
assign N472 = src1_i[0] ^ src2_i[0];
assign N473 = src1_i[63] | src2_i[63];
assign N474 = src1_i[62] | src2_i[62];
assign N475 = src1_i[61] | src2_i[61];
assign N476 = src1_i[60] | src2_i[60];
assign N477 = src1_i[59] | src2_i[59];
assign N478 = src1_i[58] | src2_i[58];
assign N479 = src1_i[57] | src2_i[57];
assign N480 = src1_i[56] | src2_i[56];
assign N481 = src1_i[55] | src2_i[55];
assign N482 = src1_i[54] | src2_i[54];
assign N483 = src1_i[53] | src2_i[53];
assign N484 = src1_i[52] | src2_i[52];
assign N485 = src1_i[51] | src2_i[51];
assign N486 = src1_i[50] | src2_i[50];
assign N487 = src1_i[49] | src2_i[49];
assign N488 = src1_i[48] | src2_i[48];
assign N489 = src1_i[47] | src2_i[47];
assign N490 = src1_i[46] | src2_i[46];
assign N491 = src1_i[45] | src2_i[45];
assign N492 = src1_i[44] | src2_i[44];
assign N493 = src1_i[43] | src2_i[43];
assign N494 = src1_i[42] | src2_i[42];
assign N495 = src1_i[41] | src2_i[41];
assign N496 = src1_i[40] | src2_i[40];
assign N497 = src1_i[39] | src2_i[39];
assign N498 = src1_i[38] | src2_i[38];
assign N499 = src1_i[37] | src2_i[37];
assign N500 = src1_i[36] | src2_i[36];
assign N501 = src1_i[35] | src2_i[35];
assign N502 = src1_i[34] | src2_i[34];
assign N503 = src1_i[33] | src2_i[33];
assign N504 = src1_i[32] | src2_i[32];
assign N505 = src1_i[31] | src2_i[31];
assign N506 = src1_i[30] | src2_i[30];
assign N507 = src1_i[29] | src2_i[29];
assign N508 = src1_i[28] | src2_i[28];
assign N509 = src1_i[27] | src2_i[27];
assign N510 = src1_i[26] | src2_i[26];
assign N511 = src1_i[25] | src2_i[25];
assign N512 = src1_i[24] | src2_i[24];
assign N513 = src1_i[23] | src2_i[23];
assign N514 = src1_i[22] | src2_i[22];
assign N515 = src1_i[21] | src2_i[21];
assign N516 = src1_i[20] | src2_i[20];
assign N517 = src1_i[19] | src2_i[19];
assign N518 = src1_i[18] | src2_i[18];
assign N519 = src1_i[17] | src2_i[17];
assign N520 = src1_i[16] | src2_i[16];
assign N521 = src1_i[15] | src2_i[15];
assign N522 = src1_i[14] | src2_i[14];
assign N523 = src1_i[13] | src2_i[13];
assign N524 = src1_i[12] | src2_i[12];
assign N525 = src1_i[11] | src2_i[11];
assign N526 = src1_i[10] | src2_i[10];
assign N527 = src1_i[9] | src2_i[9];
assign N528 = src1_i[8] | src2_i[8];
assign N529 = src1_i[7] | src2_i[7];
assign N530 = src1_i[6] | src2_i[6];
assign N531 = src1_i[5] | src2_i[5];
assign N532 = src1_i[4] | src2_i[4];
assign N533 = src1_i[3] | src2_i[3];
assign N534 = src1_i[2] | src2_i[2];
assign N535 = src1_i[1] | src2_i[1];
assign N536 = src1_i[0] | src2_i[0];
assign N537 = src1_i[63] & src2_i[63];
assign N538 = src1_i[62] & src2_i[62];
assign N539 = src1_i[61] & src2_i[61];
assign N540 = src1_i[60] & src2_i[60];
assign N541 = src1_i[59] & src2_i[59];
assign N542 = src1_i[58] & src2_i[58];
assign N543 = src1_i[57] & src2_i[57];
assign N544 = src1_i[56] & src2_i[56];
assign N545 = src1_i[55] & src2_i[55];
assign N546 = src1_i[54] & src2_i[54];
assign N547 = src1_i[53] & src2_i[53];
assign N548 = src1_i[52] & src2_i[52];
assign N549 = src1_i[51] & src2_i[51];
assign N550 = src1_i[50] & src2_i[50];
assign N551 = src1_i[49] & src2_i[49];
assign N552 = src1_i[48] & src2_i[48];
assign N553 = src1_i[47] & src2_i[47];
assign N554 = src1_i[46] & src2_i[46];
assign N555 = src1_i[45] & src2_i[45];
assign N556 = src1_i[44] & src2_i[44];
assign N557 = src1_i[43] & src2_i[43];
assign N558 = src1_i[42] & src2_i[42];
assign N559 = src1_i[41] & src2_i[41];
assign N560 = src1_i[40] & src2_i[40];
assign N561 = src1_i[39] & src2_i[39];
assign N562 = src1_i[38] & src2_i[38];
assign N563 = src1_i[37] & src2_i[37];
assign N564 = src1_i[36] & src2_i[36];
assign N565 = src1_i[35] & src2_i[35];
assign N566 = src1_i[34] & src2_i[34];
assign N567 = src1_i[33] & src2_i[33];
assign N568 = src1_i[32] & src2_i[32];
assign N569 = src1_i[31] & src2_i[31];
assign N570 = src1_i[30] & src2_i[30];
assign N571 = src1_i[29] & src2_i[29];
assign N572 = src1_i[28] & src2_i[28];
assign N573 = src1_i[27] & src2_i[27];
assign N574 = src1_i[26] & src2_i[26];
assign N575 = src1_i[25] & src2_i[25];
assign N576 = src1_i[24] & src2_i[24];
assign N577 = src1_i[23] & src2_i[23];
assign N578 = src1_i[22] & src2_i[22];
assign N579 = src1_i[21] & src2_i[21];
assign N580 = src1_i[20] & src2_i[20];
assign N581 = src1_i[19] & src2_i[19];
assign N582 = src1_i[18] & src2_i[18];
assign N583 = src1_i[17] & src2_i[17];
assign N584 = src1_i[16] & src2_i[16];
assign N585 = src1_i[15] & src2_i[15];
assign N586 = src1_i[14] & src2_i[14];
assign N587 = src1_i[13] & src2_i[13];
assign N588 = src1_i[12] & src2_i[12];
assign N589 = src1_i[11] & src2_i[11];
assign N590 = src1_i[10] & src2_i[10];
assign N591 = src1_i[9] & src2_i[9];
assign N592 = src1_i[8] & src2_i[8];
assign N593 = src1_i[7] & src2_i[7];
assign N594 = src1_i[6] & src2_i[6];
assign N595 = src1_i[5] & src2_i[5];
assign N596 = src1_i[4] & src2_i[4];
assign N597 = src1_i[3] & src2_i[3];
assign N598 = src1_i[2] & src2_i[2];
assign N599 = src1_i[1] & src2_i[1];
assign N600 = src1_i[0] & src2_i[0];
assign N863 = ~opw_v_i;
endmodule |
module bsg_dff_reset_width_p38
(
clk_i,
reset_i,
data_i,
data_o
);
input [37:0] data_i;
output [37:0] data_o;
input clk_i;
input reset_i;
wire [37:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40;
reg data_o_37_sv2v_reg,data_o_36_sv2v_reg,data_o_35_sv2v_reg,data_o_34_sv2v_reg,
data_o_33_sv2v_reg,data_o_32_sv2v_reg,data_o_31_sv2v_reg,data_o_30_sv2v_reg,
data_o_29_sv2v_reg,data_o_28_sv2v_reg,data_o_27_sv2v_reg,data_o_26_sv2v_reg,
data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,
data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,
data_o_16_sv2v_reg,data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,
data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,
data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,
data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_mux_one_hot_width_p41_els_p1
(
data_i,
sel_one_hot_i,
data_o
);
input [40:0] data_i;
input [0:0] sel_one_hot_i;
output [40:0] data_o;
wire [40:0] data_o;
assign data_o[40] = data_i[40] & sel_one_hot_i[0];
assign data_o[39] = data_i[39] & sel_one_hot_i[0];
assign data_o[38] = data_i[38] & sel_one_hot_i[0];
assign data_o[37] = data_i[37] & sel_one_hot_i[0];
assign data_o[36] = data_i[36] & sel_one_hot_i[0];
assign data_o[35] = data_i[35] & sel_one_hot_i[0];
assign data_o[34] = data_i[34] & sel_one_hot_i[0];
assign data_o[33] = data_i[33] & sel_one_hot_i[0];
assign data_o[32] = data_i[32] & sel_one_hot_i[0];
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i[29] & sel_one_hot_i[0];
assign data_o[28] = data_i[28] & sel_one_hot_i[0];
assign data_o[27] = data_i[27] & sel_one_hot_i[0];
assign data_o[26] = data_i[26] & sel_one_hot_i[0];
assign data_o[25] = data_i[25] & sel_one_hot_i[0];
assign data_o[24] = data_i[24] & sel_one_hot_i[0];
assign data_o[23] = data_i[23] & sel_one_hot_i[0];
assign data_o[22] = data_i[22] & sel_one_hot_i[0];
assign data_o[21] = data_i[21] & sel_one_hot_i[0];
assign data_o[20] = data_i[20] & sel_one_hot_i[0];
assign data_o[19] = data_i[19] & sel_one_hot_i[0];
assign data_o[18] = data_i[18] & sel_one_hot_i[0];
assign data_o[17] = data_i[17] & sel_one_hot_i[0];
assign data_o[16] = data_i[16] & sel_one_hot_i[0];
assign data_o[15] = data_i[15] & sel_one_hot_i[0];
assign data_o[14] = data_i[14] & sel_one_hot_i[0];
assign data_o[13] = data_i[13] & sel_one_hot_i[0];
assign data_o[12] = data_i[12] & sel_one_hot_i[0];
assign data_o[11] = data_i[11] & sel_one_hot_i[0];
assign data_o[10] = data_i[10] & sel_one_hot_i[0];
assign data_o[9] = data_i[9] & sel_one_hot_i[0];
assign data_o[8] = data_i[8] & sel_one_hot_i[0];
assign data_o[7] = data_i[7] & sel_one_hot_i[0];
assign data_o[6] = data_i[6] & sel_one_hot_i[0];
assign data_o[5] = data_i[5] & sel_one_hot_i[0];
assign data_o[4] = data_i[4] & sel_one_hot_i[0];
assign data_o[3] = data_i[3] & sel_one_hot_i[0];
assign data_o[2] = data_i[2] & sel_one_hot_i[0];
assign data_o[1] = data_i[1] & sel_one_hot_i[0];
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule |
module bsg_counter_set_en_lg_max_val_lp64_reset_val_p0
(
clk_i,
reset_i,
set_i,
en_i,
val_i,
count_o
);
input [63:0] val_i;
output [63:0] count_o;
input clk_i;
input reset_i;
input set_i;
input en_i;
wire [63:0] count_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138;
reg count_o_63_sv2v_reg,count_o_62_sv2v_reg,count_o_61_sv2v_reg,count_o_60_sv2v_reg,
count_o_59_sv2v_reg,count_o_58_sv2v_reg,count_o_57_sv2v_reg,count_o_56_sv2v_reg,
count_o_55_sv2v_reg,count_o_54_sv2v_reg,count_o_53_sv2v_reg,count_o_52_sv2v_reg,
count_o_51_sv2v_reg,count_o_50_sv2v_reg,count_o_49_sv2v_reg,count_o_48_sv2v_reg,
count_o_47_sv2v_reg,count_o_46_sv2v_reg,count_o_45_sv2v_reg,count_o_44_sv2v_reg,
count_o_43_sv2v_reg,count_o_42_sv2v_reg,count_o_41_sv2v_reg,count_o_40_sv2v_reg,
count_o_39_sv2v_reg,count_o_38_sv2v_reg,count_o_37_sv2v_reg,count_o_36_sv2v_reg,
count_o_35_sv2v_reg,count_o_34_sv2v_reg,count_o_33_sv2v_reg,count_o_32_sv2v_reg,
count_o_31_sv2v_reg,count_o_30_sv2v_reg,count_o_29_sv2v_reg,count_o_28_sv2v_reg,
count_o_27_sv2v_reg,count_o_26_sv2v_reg,count_o_25_sv2v_reg,count_o_24_sv2v_reg,
count_o_23_sv2v_reg,count_o_22_sv2v_reg,count_o_21_sv2v_reg,count_o_20_sv2v_reg,
count_o_19_sv2v_reg,count_o_18_sv2v_reg,count_o_17_sv2v_reg,count_o_16_sv2v_reg,
count_o_15_sv2v_reg,count_o_14_sv2v_reg,count_o_13_sv2v_reg,count_o_12_sv2v_reg,
count_o_11_sv2v_reg,count_o_10_sv2v_reg,count_o_9_sv2v_reg,count_o_8_sv2v_reg,
count_o_7_sv2v_reg,count_o_6_sv2v_reg,count_o_5_sv2v_reg,count_o_4_sv2v_reg,
count_o_3_sv2v_reg,count_o_2_sv2v_reg,count_o_1_sv2v_reg,count_o_0_sv2v_reg;
assign count_o[63] = count_o_63_sv2v_reg;
assign count_o[62] = count_o_62_sv2v_reg;
assign count_o[61] = count_o_61_sv2v_reg;
assign count_o[60] = count_o_60_sv2v_reg;
assign count_o[59] = count_o_59_sv2v_reg;
assign count_o[58] = count_o_58_sv2v_reg;
assign count_o[57] = count_o_57_sv2v_reg;
assign count_o[56] = count_o_56_sv2v_reg;
assign count_o[55] = count_o_55_sv2v_reg;
assign count_o[54] = count_o_54_sv2v_reg;
assign count_o[53] = count_o_53_sv2v_reg;
assign count_o[52] = count_o_52_sv2v_reg;
assign count_o[51] = count_o_51_sv2v_reg;
assign count_o[50] = count_o_50_sv2v_reg;
assign count_o[49] = count_o_49_sv2v_reg;
assign count_o[48] = count_o_48_sv2v_reg;
assign count_o[47] = count_o_47_sv2v_reg;
assign count_o[46] = count_o_46_sv2v_reg;
assign count_o[45] = count_o_45_sv2v_reg;
assign count_o[44] = count_o_44_sv2v_reg;
assign count_o[43] = count_o_43_sv2v_reg;
assign count_o[42] = count_o_42_sv2v_reg;
assign count_o[41] = count_o_41_sv2v_reg;
assign count_o[40] = count_o_40_sv2v_reg;
assign count_o[39] = count_o_39_sv2v_reg;
assign count_o[38] = count_o_38_sv2v_reg;
assign count_o[37] = count_o_37_sv2v_reg;
assign count_o[36] = count_o_36_sv2v_reg;
assign count_o[35] = count_o_35_sv2v_reg;
assign count_o[34] = count_o_34_sv2v_reg;
assign count_o[33] = count_o_33_sv2v_reg;
assign count_o[32] = count_o_32_sv2v_reg;
assign count_o[31] = count_o_31_sv2v_reg;
assign count_o[30] = count_o_30_sv2v_reg;
assign count_o[29] = count_o_29_sv2v_reg;
assign count_o[28] = count_o_28_sv2v_reg;
assign count_o[27] = count_o_27_sv2v_reg;
assign count_o[26] = count_o_26_sv2v_reg;
assign count_o[25] = count_o_25_sv2v_reg;
assign count_o[24] = count_o_24_sv2v_reg;
assign count_o[23] = count_o_23_sv2v_reg;
assign count_o[22] = count_o_22_sv2v_reg;
assign count_o[21] = count_o_21_sv2v_reg;
assign count_o[20] = count_o_20_sv2v_reg;
assign count_o[19] = count_o_19_sv2v_reg;
assign count_o[18] = count_o_18_sv2v_reg;
assign count_o[17] = count_o_17_sv2v_reg;
assign count_o[16] = count_o_16_sv2v_reg;
assign count_o[15] = count_o_15_sv2v_reg;
assign count_o[14] = count_o_14_sv2v_reg;
assign count_o[13] = count_o_13_sv2v_reg;
assign count_o[12] = count_o_12_sv2v_reg;
assign count_o[11] = count_o_11_sv2v_reg;
assign count_o[10] = count_o_10_sv2v_reg;
assign count_o[9] = count_o_9_sv2v_reg;
assign count_o[8] = count_o_8_sv2v_reg;
assign count_o[7] = count_o_7_sv2v_reg;
assign count_o[6] = count_o_6_sv2v_reg;
assign count_o[5] = count_o_5_sv2v_reg;
assign count_o[4] = count_o_4_sv2v_reg;
assign count_o[3] = count_o_3_sv2v_reg;
assign count_o[2] = count_o_2_sv2v_reg;
assign count_o[1] = count_o_1_sv2v_reg;
assign count_o[0] = count_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N69) begin
count_o_63_sv2v_reg <= N133;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_62_sv2v_reg <= N132;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_61_sv2v_reg <= N131;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_60_sv2v_reg <= N130;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_59_sv2v_reg <= N129;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_58_sv2v_reg <= N128;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_57_sv2v_reg <= N127;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_56_sv2v_reg <= N126;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_55_sv2v_reg <= N125;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_54_sv2v_reg <= N124;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_53_sv2v_reg <= N123;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_52_sv2v_reg <= N122;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_51_sv2v_reg <= N121;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_50_sv2v_reg <= N120;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_49_sv2v_reg <= N119;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_48_sv2v_reg <= N118;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_47_sv2v_reg <= N117;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_46_sv2v_reg <= N116;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_45_sv2v_reg <= N115;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_44_sv2v_reg <= N114;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_43_sv2v_reg <= N113;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_42_sv2v_reg <= N112;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_41_sv2v_reg <= N111;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_40_sv2v_reg <= N110;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_39_sv2v_reg <= N109;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_38_sv2v_reg <= N108;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_37_sv2v_reg <= N107;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_36_sv2v_reg <= N106;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_35_sv2v_reg <= N105;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_34_sv2v_reg <= N104;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_33_sv2v_reg <= N103;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_32_sv2v_reg <= N102;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_31_sv2v_reg <= N101;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_30_sv2v_reg <= N100;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_29_sv2v_reg <= N99;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_28_sv2v_reg <= N98;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_27_sv2v_reg <= N97;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_26_sv2v_reg <= N96;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_25_sv2v_reg <= N95;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_24_sv2v_reg <= N94;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_23_sv2v_reg <= N93;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_22_sv2v_reg <= N92;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_21_sv2v_reg <= N91;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_20_sv2v_reg <= N90;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_19_sv2v_reg <= N89;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_18_sv2v_reg <= N88;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_17_sv2v_reg <= N87;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_16_sv2v_reg <= N86;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_15_sv2v_reg <= N85;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_14_sv2v_reg <= N84;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_13_sv2v_reg <= N83;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_12_sv2v_reg <= N82;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_11_sv2v_reg <= N81;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_10_sv2v_reg <= N80;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_9_sv2v_reg <= N79;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_8_sv2v_reg <= N78;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_7_sv2v_reg <= N77;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_6_sv2v_reg <= N76;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_5_sv2v_reg <= N75;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_4_sv2v_reg <= N74;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_3_sv2v_reg <= N73;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_2_sv2v_reg <= N72;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_1_sv2v_reg <= N71;
end
end
always @(posedge clk_i) begin
if(N69) begin
count_o_0_sv2v_reg <= N70;
end
end
assign { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } = count_o + 1'b1;
assign N69 = (N0)? 1'b1 :
(N135)? 1'b1 :
(N138)? 1'b1 :
(N3)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N135)? val_i :
(N138)? { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } : 1'b0;
assign N1 = set_i | reset_i;
assign N2 = en_i | N1;
assign N3 = ~N2;
assign N4 = N138;
assign N134 = ~reset_i;
assign N135 = set_i & N134;
assign N136 = ~set_i;
assign N137 = N134 & N136;
assign N138 = en_i & N137;
endmodule |
module bsg_concentrate_static_03
(
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_mux_width_p8_els_p4
(
data_i,
sel_i,
data_o
);
input [31:0] data_i;
input [1:0] sel_i;
output [7:0] data_o;
wire [7:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[7] = (N2)? data_i[7] :
(N4)? data_i[15] :
(N3)? data_i[23] :
(N5)? data_i[31] : 1'b0;
assign data_o[6] = (N2)? data_i[6] :
(N4)? data_i[14] :
(N3)? data_i[22] :
(N5)? data_i[30] : 1'b0;
assign data_o[5] = (N2)? data_i[5] :
(N4)? data_i[13] :
(N3)? data_i[21] :
(N5)? data_i[29] : 1'b0;
assign data_o[4] = (N2)? data_i[4] :
(N4)? data_i[12] :
(N3)? data_i[20] :
(N5)? data_i[28] : 1'b0;
assign data_o[3] = (N2)? data_i[3] :
(N4)? data_i[11] :
(N3)? data_i[19] :
(N5)? data_i[27] : 1'b0;
assign data_o[2] = (N2)? data_i[2] :
(N4)? data_i[10] :
(N3)? data_i[18] :
(N5)? data_i[26] : 1'b0;
assign data_o[1] = (N2)? data_i[1] :
(N4)? data_i[9] :
(N3)? data_i[17] :
(N5)? data_i[25] : 1'b0;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[8] :
(N3)? data_i[16] :
(N5)? data_i[24] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule |
module bsg_mux_one_hot_62_2
(
data_i,
sel_one_hot_i,
data_o
);
input [123:0] data_i;
input [1:0] sel_one_hot_i;
output [61:0] data_o;
wire [61:0] data_o;
wire [123:0] data_masked;
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_o[0] = data_masked[62] | data_masked[0];
assign data_o[1] = data_masked[63] | data_masked[1];
assign data_o[2] = data_masked[64] | data_masked[2];
assign data_o[3] = data_masked[65] | data_masked[3];
assign data_o[4] = data_masked[66] | data_masked[4];
assign data_o[5] = data_masked[67] | data_masked[5];
assign data_o[6] = data_masked[68] | data_masked[6];
assign data_o[7] = data_masked[69] | data_masked[7];
assign data_o[8] = data_masked[70] | data_masked[8];
assign data_o[9] = data_masked[71] | data_masked[9];
assign data_o[10] = data_masked[72] | data_masked[10];
assign data_o[11] = data_masked[73] | data_masked[11];
assign data_o[12] = data_masked[74] | data_masked[12];
assign data_o[13] = data_masked[75] | data_masked[13];
assign data_o[14] = data_masked[76] | data_masked[14];
assign data_o[15] = data_masked[77] | data_masked[15];
assign data_o[16] = data_masked[78] | data_masked[16];
assign data_o[17] = data_masked[79] | data_masked[17];
assign data_o[18] = data_masked[80] | data_masked[18];
assign data_o[19] = data_masked[81] | data_masked[19];
assign data_o[20] = data_masked[82] | data_masked[20];
assign data_o[21] = data_masked[83] | data_masked[21];
assign data_o[22] = data_masked[84] | data_masked[22];
assign data_o[23] = data_masked[85] | data_masked[23];
assign data_o[24] = data_masked[86] | data_masked[24];
assign data_o[25] = data_masked[87] | data_masked[25];
assign data_o[26] = data_masked[88] | data_masked[26];
assign data_o[27] = data_masked[89] | data_masked[27];
assign data_o[28] = data_masked[90] | data_masked[28];
assign data_o[29] = data_masked[91] | data_masked[29];
assign data_o[30] = data_masked[92] | data_masked[30];
assign data_o[31] = data_masked[93] | data_masked[31];
assign data_o[32] = data_masked[94] | data_masked[32];
assign data_o[33] = data_masked[95] | data_masked[33];
assign data_o[34] = data_masked[96] | data_masked[34];
assign data_o[35] = data_masked[97] | data_masked[35];
assign data_o[36] = data_masked[98] | data_masked[36];
assign data_o[37] = data_masked[99] | data_masked[37];
assign data_o[38] = data_masked[100] | data_masked[38];
assign data_o[39] = data_masked[101] | data_masked[39];
assign data_o[40] = data_masked[102] | data_masked[40];
assign data_o[41] = data_masked[103] | data_masked[41];
assign data_o[42] = data_masked[104] | data_masked[42];
assign data_o[43] = data_masked[105] | data_masked[43];
assign data_o[44] = data_masked[106] | data_masked[44];
assign data_o[45] = data_masked[107] | data_masked[45];
assign data_o[46] = data_masked[108] | data_masked[46];
assign data_o[47] = data_masked[109] | data_masked[47];
assign data_o[48] = data_masked[110] | data_masked[48];
assign data_o[49] = data_masked[111] | data_masked[49];
assign data_o[50] = data_masked[112] | data_masked[50];
assign data_o[51] = data_masked[113] | data_masked[51];
assign data_o[52] = data_masked[114] | data_masked[52];
assign data_o[53] = data_masked[115] | data_masked[53];
assign data_o[54] = data_masked[116] | data_masked[54];
assign data_o[55] = data_masked[117] | data_masked[55];
assign data_o[56] = data_masked[118] | data_masked[56];
assign data_o[57] = data_masked[119] | data_masked[57];
assign data_o[58] = data_masked[120] | data_masked[58];
assign data_o[59] = data_masked[121] | data_masked[59];
assign data_o[60] = data_masked[122] | data_masked[60];
assign data_o[61] = data_masked[123] | data_masked[61];
endmodule |
module bsg_concentrate_static_5
(
i,
o
);
input [2:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule |
module bp_fe_instr_scan_05
(
instr_i,
scan_o
);
input [31:0] instr_i;
output [42:0] scan_o;
wire [42:0] scan_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42;
assign scan_o[2] = 1'b0;
assign scan_o[3] = 1'b0;
assign scan_o[4] = 1'b0;
assign N11 = instr_i[6] & instr_i[5];
assign N12 = N10 & instr_i[1];
assign N13 = N11 & N12;
assign N14 = N13 & instr_i[0];
assign N18 = N16 & N17;
assign N19 = instr_i[3] & instr_i[2];
assign N20 = instr_i[3] | N17;
assign N21 = N16 | instr_i[2];
assign { N9, N8 } = (N0)? { 1'b1, 1'b1 } :
(N1)? { 1'b0, 1'b1 } :
(N2)? { 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b0 } : 1'b0;
assign N0 = N18;
assign N1 = N19;
assign N2 = N6;
assign N3 = N7;
assign scan_o[1:0] = (N4)? { N9, N8 } :
(N15)? { 1'b0, 1'b0 } : 1'b0;
assign N4 = N14;
assign { N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23 } = (N0)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[7:7], instr_i[30:25], instr_i[11:8] } :
(N1)? { instr_i[31:31], instr_i[19:12], instr_i[20:20], instr_i[30:21] } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N5 = N22;
assign scan_o[42:5] = (N4)? { N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23 } :
(N15)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N6 = ~N20;
assign N7 = ~N21;
assign N10 = ~instr_i[4];
assign N15 = ~N14;
assign N16 = ~instr_i[3];
assign N17 = ~instr_i[2];
assign N22 = N6 | N7;
endmodule |
module bsg_dff_en_width_p1
(
clk_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clk_i;
input en_i;
wire [0:0] data_o;
reg data_o_0_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(en_i) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_concentrate_static_7
(
i,
o
);
input [2:0] i;
output [2:0] o;
wire [2:0] o;
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_expand_bitmask_in_width_p8_expand_p8
(
i,
o
);
input [7:0] i;
output [63:0] o;
wire [63:0] o;
wire o_63_,o_55_,o_47_,o_39_,o_31_,o_23_,o_15_,o_7_;
assign o_63_ = i[7];
assign o[56] = o_63_;
assign o[57] = o_63_;
assign o[58] = o_63_;
assign o[59] = o_63_;
assign o[60] = o_63_;
assign o[61] = o_63_;
assign o[62] = o_63_;
assign o[63] = o_63_;
assign o_55_ = i[6];
assign o[48] = o_55_;
assign o[49] = o_55_;
assign o[50] = o_55_;
assign o[51] = o_55_;
assign o[52] = o_55_;
assign o[53] = o_55_;
assign o[54] = o_55_;
assign o[55] = o_55_;
assign o_47_ = i[5];
assign o[40] = o_47_;
assign o[41] = o_47_;
assign o[42] = o_47_;
assign o[43] = o_47_;
assign o[44] = o_47_;
assign o[45] = o_47_;
assign o[46] = o_47_;
assign o[47] = o_47_;
assign o_39_ = i[4];
assign o[32] = o_39_;
assign o[33] = o_39_;
assign o[34] = o_39_;
assign o[35] = o_39_;
assign o[36] = o_39_;
assign o[37] = o_39_;
assign o[38] = o_39_;
assign o[39] = o_39_;
assign o_31_ = i[3];
assign o[24] = o_31_;
assign o[25] = o_31_;
assign o[26] = o_31_;
assign o[27] = o_31_;
assign o[28] = o_31_;
assign o[29] = o_31_;
assign o[30] = o_31_;
assign o[31] = o_31_;
assign o_23_ = i[2];
assign o[16] = o_23_;
assign o[17] = o_23_;
assign o[18] = o_23_;
assign o[19] = o_23_;
assign o[20] = o_23_;
assign o[21] = o_23_;
assign o[22] = o_23_;
assign o[23] = o_23_;
assign o_15_ = i[1];
assign o[8] = o_15_;
assign o[9] = o_15_;
assign o[10] = o_15_;
assign o[11] = o_15_;
assign o[12] = o_15_;
assign o[13] = o_15_;
assign o[14] = o_15_;
assign o[15] = o_15_;
assign o_7_ = i[0];
assign o[0] = o_7_;
assign o[1] = o_7_;
assign o[2] = o_7_;
assign o[3] = o_7_;
assign o[4] = o_7_;
assign o[5] = o_7_;
assign o[6] = o_7_;
assign o[7] = o_7_;
endmodule |
module bsg_unconcentrate_static_11
(
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_,o_0_;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_4_ = i[1];
assign o[4] = o_4_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mux_width_p128_els_p2
(
data_i,
sel_i,
data_o
);
input [255:0] data_i;
input [0:0] sel_i;
output [127:0] data_o;
wire [127:0] data_o;
wire N0,N1;
assign data_o[127] = (N1)? data_i[127] :
(N0)? data_i[255] : 1'b0;
assign N0 = sel_i[0];
assign data_o[126] = (N1)? data_i[126] :
(N0)? data_i[254] : 1'b0;
assign data_o[125] = (N1)? data_i[125] :
(N0)? data_i[253] : 1'b0;
assign data_o[124] = (N1)? data_i[124] :
(N0)? data_i[252] : 1'b0;
assign data_o[123] = (N1)? data_i[123] :
(N0)? data_i[251] : 1'b0;
assign data_o[122] = (N1)? data_i[122] :
(N0)? data_i[250] : 1'b0;
assign data_o[121] = (N1)? data_i[121] :
(N0)? data_i[249] : 1'b0;
assign data_o[120] = (N1)? data_i[120] :
(N0)? data_i[248] : 1'b0;
assign data_o[119] = (N1)? data_i[119] :
(N0)? data_i[247] : 1'b0;
assign data_o[118] = (N1)? data_i[118] :
(N0)? data_i[246] : 1'b0;
assign data_o[117] = (N1)? data_i[117] :
(N0)? data_i[245] : 1'b0;
assign data_o[116] = (N1)? data_i[116] :
(N0)? data_i[244] : 1'b0;
assign data_o[115] = (N1)? data_i[115] :
(N0)? data_i[243] : 1'b0;
assign data_o[114] = (N1)? data_i[114] :
(N0)? data_i[242] : 1'b0;
assign data_o[113] = (N1)? data_i[113] :
(N0)? data_i[241] : 1'b0;
assign data_o[112] = (N1)? data_i[112] :
(N0)? data_i[240] : 1'b0;
assign data_o[111] = (N1)? data_i[111] :
(N0)? data_i[239] : 1'b0;
assign data_o[110] = (N1)? data_i[110] :
(N0)? data_i[238] : 1'b0;
assign data_o[109] = (N1)? data_i[109] :
(N0)? data_i[237] : 1'b0;
assign data_o[108] = (N1)? data_i[108] :
(N0)? data_i[236] : 1'b0;
assign data_o[107] = (N1)? data_i[107] :
(N0)? data_i[235] : 1'b0;
assign data_o[106] = (N1)? data_i[106] :
(N0)? data_i[234] : 1'b0;
assign data_o[105] = (N1)? data_i[105] :
(N0)? data_i[233] : 1'b0;
assign data_o[104] = (N1)? data_i[104] :
(N0)? data_i[232] : 1'b0;
assign data_o[103] = (N1)? data_i[103] :
(N0)? data_i[231] : 1'b0;
assign data_o[102] = (N1)? data_i[102] :
(N0)? data_i[230] : 1'b0;
assign data_o[101] = (N1)? data_i[101] :
(N0)? data_i[229] : 1'b0;
assign data_o[100] = (N1)? data_i[100] :
(N0)? data_i[228] : 1'b0;
assign data_o[99] = (N1)? data_i[99] :
(N0)? data_i[227] : 1'b0;
assign data_o[98] = (N1)? data_i[98] :
(N0)? data_i[226] : 1'b0;
assign data_o[97] = (N1)? data_i[97] :
(N0)? data_i[225] : 1'b0;
assign data_o[96] = (N1)? data_i[96] :
(N0)? data_i[224] : 1'b0;
assign data_o[95] = (N1)? data_i[95] :
(N0)? data_i[223] : 1'b0;
assign data_o[94] = (N1)? data_i[94] :
(N0)? data_i[222] : 1'b0;
assign data_o[93] = (N1)? data_i[93] :
(N0)? data_i[221] : 1'b0;
assign data_o[92] = (N1)? data_i[92] :
(N0)? data_i[220] : 1'b0;
assign data_o[91] = (N1)? data_i[91] :
(N0)? data_i[219] : 1'b0;
assign data_o[90] = (N1)? data_i[90] :
(N0)? data_i[218] : 1'b0;
assign data_o[89] = (N1)? data_i[89] :
(N0)? data_i[217] : 1'b0;
assign data_o[88] = (N1)? data_i[88] :
(N0)? data_i[216] : 1'b0;
assign data_o[87] = (N1)? data_i[87] :
(N0)? data_i[215] : 1'b0;
assign data_o[86] = (N1)? data_i[86] :
(N0)? data_i[214] : 1'b0;
assign data_o[85] = (N1)? data_i[85] :
(N0)? data_i[213] : 1'b0;
assign data_o[84] = (N1)? data_i[84] :
(N0)? data_i[212] : 1'b0;
assign data_o[83] = (N1)? data_i[83] :
(N0)? data_i[211] : 1'b0;
assign data_o[82] = (N1)? data_i[82] :
(N0)? data_i[210] : 1'b0;
assign data_o[81] = (N1)? data_i[81] :
(N0)? data_i[209] : 1'b0;
assign data_o[80] = (N1)? data_i[80] :
(N0)? data_i[208] : 1'b0;
assign data_o[79] = (N1)? data_i[79] :
(N0)? data_i[207] : 1'b0;
assign data_o[78] = (N1)? data_i[78] :
(N0)? data_i[206] : 1'b0;
assign data_o[77] = (N1)? data_i[77] :
(N0)? data_i[205] : 1'b0;
assign data_o[76] = (N1)? data_i[76] :
(N0)? data_i[204] : 1'b0;
assign data_o[75] = (N1)? data_i[75] :
(N0)? data_i[203] : 1'b0;
assign data_o[74] = (N1)? data_i[74] :
(N0)? data_i[202] : 1'b0;
assign data_o[73] = (N1)? data_i[73] :
(N0)? data_i[201] : 1'b0;
assign data_o[72] = (N1)? data_i[72] :
(N0)? data_i[200] : 1'b0;
assign data_o[71] = (N1)? data_i[71] :
(N0)? data_i[199] : 1'b0;
assign data_o[70] = (N1)? data_i[70] :
(N0)? data_i[198] : 1'b0;
assign data_o[69] = (N1)? data_i[69] :
(N0)? data_i[197] : 1'b0;
assign data_o[68] = (N1)? data_i[68] :
(N0)? data_i[196] : 1'b0;
assign data_o[67] = (N1)? data_i[67] :
(N0)? data_i[195] : 1'b0;
assign data_o[66] = (N1)? data_i[66] :
(N0)? data_i[194] : 1'b0;
assign data_o[65] = (N1)? data_i[65] :
(N0)? data_i[193] : 1'b0;
assign data_o[64] = (N1)? data_i[64] :
(N0)? data_i[192] : 1'b0;
assign data_o[63] = (N1)? data_i[63] :
(N0)? data_i[191] : 1'b0;
assign data_o[62] = (N1)? data_i[62] :
(N0)? data_i[190] : 1'b0;
assign data_o[61] = (N1)? data_i[61] :
(N0)? data_i[189] : 1'b0;
assign data_o[60] = (N1)? data_i[60] :
(N0)? data_i[188] : 1'b0;
assign data_o[59] = (N1)? data_i[59] :
(N0)? data_i[187] : 1'b0;
assign data_o[58] = (N1)? data_i[58] :
(N0)? data_i[186] : 1'b0;
assign data_o[57] = (N1)? data_i[57] :
(N0)? data_i[185] : 1'b0;
assign data_o[56] = (N1)? data_i[56] :
(N0)? data_i[184] : 1'b0;
assign data_o[55] = (N1)? data_i[55] :
(N0)? data_i[183] : 1'b0;
assign data_o[54] = (N1)? data_i[54] :
(N0)? data_i[182] : 1'b0;
assign data_o[53] = (N1)? data_i[53] :
(N0)? data_i[181] : 1'b0;
assign data_o[52] = (N1)? data_i[52] :
(N0)? data_i[180] : 1'b0;
assign data_o[51] = (N1)? data_i[51] :
(N0)? data_i[179] : 1'b0;
assign data_o[50] = (N1)? data_i[50] :
(N0)? data_i[178] : 1'b0;
assign data_o[49] = (N1)? data_i[49] :
(N0)? data_i[177] : 1'b0;
assign data_o[48] = (N1)? data_i[48] :
(N0)? data_i[176] : 1'b0;
assign data_o[47] = (N1)? data_i[47] :
(N0)? data_i[175] : 1'b0;
assign data_o[46] = (N1)? data_i[46] :
(N0)? data_i[174] : 1'b0;
assign data_o[45] = (N1)? data_i[45] :
(N0)? data_i[173] : 1'b0;
assign data_o[44] = (N1)? data_i[44] :
(N0)? data_i[172] : 1'b0;
assign data_o[43] = (N1)? data_i[43] :
(N0)? data_i[171] : 1'b0;
assign data_o[42] = (N1)? data_i[42] :
(N0)? data_i[170] : 1'b0;
assign data_o[41] = (N1)? data_i[41] :
(N0)? data_i[169] : 1'b0;
assign data_o[40] = (N1)? data_i[40] :
(N0)? data_i[168] : 1'b0;
assign data_o[39] = (N1)? data_i[39] :
(N0)? data_i[167] : 1'b0;
assign data_o[38] = (N1)? data_i[38] :
(N0)? data_i[166] : 1'b0;
assign data_o[37] = (N1)? data_i[37] :
(N0)? data_i[165] : 1'b0;
assign data_o[36] = (N1)? data_i[36] :
(N0)? data_i[164] : 1'b0;
assign data_o[35] = (N1)? data_i[35] :
(N0)? data_i[163] : 1'b0;
assign data_o[34] = (N1)? data_i[34] :
(N0)? data_i[162] : 1'b0;
assign data_o[33] = (N1)? data_i[33] :
(N0)? data_i[161] : 1'b0;
assign data_o[32] = (N1)? data_i[32] :
(N0)? data_i[160] : 1'b0;
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[159] : 1'b0;
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[158] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[157] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[156] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[155] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[154] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[153] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[152] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[151] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[150] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[149] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[148] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[147] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[146] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[145] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[144] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[143] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[142] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[141] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[140] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[139] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[138] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[137] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[136] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[135] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[134] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[133] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[132] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[131] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[130] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[129] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[128] : 1'b0;
assign N1 = ~sel_i[0];
endmodule |
module bsg_mem_1r1w_synth_width_p1_els_p8_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [2:0] w_addr_i;
input [0:0] w_data_i;
input [2:0] r_addr_i;
output [0:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [0:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45;
wire [7:0] mem;
reg mem_7_sv2v_reg,mem_6_sv2v_reg,mem_5_sv2v_reg,mem_4_sv2v_reg,mem_3_sv2v_reg,
mem_2_sv2v_reg,mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[7] = mem_7_sv2v_reg;
assign mem[6] = mem_6_sv2v_reg;
assign mem[5] = mem_5_sv2v_reg;
assign mem[4] = mem_4_sv2v_reg;
assign mem[3] = mem_3_sv2v_reg;
assign mem[2] = mem_2_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[0] = (N17)? mem[0] :
(N19)? mem[1] :
(N21)? mem[2] :
(N23)? mem[3] :
(N18)? mem[4] :
(N20)? mem[5] :
(N22)? mem[6] :
(N24)? mem[7] : 1'b0;
always @(posedge w_clk_i) begin
if(N41) begin
mem_7_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N40) begin
mem_6_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N39) begin
mem_5_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N38) begin
mem_4_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N37) begin
mem_3_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N36) begin
mem_2_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N35) begin
mem_1_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N34) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N42 = w_addr_i[0] & w_addr_i[1];
assign N33 = N42 & w_addr_i[2];
assign N43 = N0 & w_addr_i[1];
assign N0 = ~w_addr_i[0];
assign N32 = N43 & w_addr_i[2];
assign N44 = w_addr_i[0] & N1;
assign N1 = ~w_addr_i[1];
assign N31 = N44 & w_addr_i[2];
assign N45 = N2 & N3;
assign N2 = ~w_addr_i[0];
assign N3 = ~w_addr_i[1];
assign N30 = N45 & w_addr_i[2];
assign N29 = N42 & N4;
assign N4 = ~w_addr_i[2];
assign N28 = N43 & N5;
assign N5 = ~w_addr_i[2];
assign N27 = N44 & N6;
assign N6 = ~w_addr_i[2];
assign N26 = N45 & N7;
assign N7 = ~w_addr_i[2];
assign { N41, N40, N39, N38, N37, N36, N35, N34 } = (N8)? { N33, N32, N31, N30, N29, N28, N27, N26 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = w_v_i;
assign N9 = N25;
assign N10 = ~r_addr_i[0];
assign N11 = ~r_addr_i[1];
assign N12 = N10 & N11;
assign N13 = N10 & r_addr_i[1];
assign N14 = r_addr_i[0] & N11;
assign N15 = r_addr_i[0] & r_addr_i[1];
assign N16 = ~r_addr_i[2];
assign N17 = N12 & N16;
assign N18 = N12 & r_addr_i[2];
assign N19 = N14 & N16;
assign N20 = N14 & r_addr_i[2];
assign N21 = N13 & N16;
assign N22 = N13 & r_addr_i[2];
assign N23 = N15 & N16;
assign N24 = N15 & r_addr_i[2];
assign N25 = ~w_v_i;
endmodule |
module bsg_array_concentrate_static_11_128
(
i,
o
);
input [639:0] i;
output [255:0] o;
wire [255:0] o;
assign o[255] = i[639];
assign o[254] = i[638];
assign o[253] = i[637];
assign o[252] = i[636];
assign o[251] = i[635];
assign o[250] = i[634];
assign o[249] = i[633];
assign o[248] = i[632];
assign o[247] = i[631];
assign o[246] = i[630];
assign o[245] = i[629];
assign o[244] = i[628];
assign o[243] = i[627];
assign o[242] = i[626];
assign o[241] = i[625];
assign o[240] = i[624];
assign o[239] = i[623];
assign o[238] = i[622];
assign o[237] = i[621];
assign o[236] = i[620];
assign o[235] = i[619];
assign o[234] = i[618];
assign o[233] = i[617];
assign o[232] = i[616];
assign o[231] = i[615];
assign o[230] = i[614];
assign o[229] = i[613];
assign o[228] = i[612];
assign o[227] = i[611];
assign o[226] = i[610];
assign o[225] = i[609];
assign o[224] = i[608];
assign o[223] = i[607];
assign o[222] = i[606];
assign o[221] = i[605];
assign o[220] = i[604];
assign o[219] = i[603];
assign o[218] = i[602];
assign o[217] = i[601];
assign o[216] = i[600];
assign o[215] = i[599];
assign o[214] = i[598];
assign o[213] = i[597];
assign o[212] = i[596];
assign o[211] = i[595];
assign o[210] = i[594];
assign o[209] = i[593];
assign o[208] = i[592];
assign o[207] = i[591];
assign o[206] = i[590];
assign o[205] = i[589];
assign o[204] = i[588];
assign o[203] = i[587];
assign o[202] = i[586];
assign o[201] = i[585];
assign o[200] = i[584];
assign o[199] = i[583];
assign o[198] = i[582];
assign o[197] = i[581];
assign o[196] = i[580];
assign o[195] = i[579];
assign o[194] = i[578];
assign o[193] = i[577];
assign o[192] = i[576];
assign o[191] = i[575];
assign o[190] = i[574];
assign o[189] = i[573];
assign o[188] = i[572];
assign o[187] = i[571];
assign o[186] = i[570];
assign o[185] = i[569];
assign o[184] = i[568];
assign o[183] = i[567];
assign o[182] = i[566];
assign o[181] = i[565];
assign o[180] = i[564];
assign o[179] = i[563];
assign o[178] = i[562];
assign o[177] = i[561];
assign o[176] = i[560];
assign o[175] = i[559];
assign o[174] = i[558];
assign o[173] = i[557];
assign o[172] = i[556];
assign o[171] = i[555];
assign o[170] = i[554];
assign o[169] = i[553];
assign o[168] = i[552];
assign o[167] = i[551];
assign o[166] = i[550];
assign o[165] = i[549];
assign o[164] = i[548];
assign o[163] = i[547];
assign o[162] = i[546];
assign o[161] = i[545];
assign o[160] = i[544];
assign o[159] = i[543];
assign o[158] = i[542];
assign o[157] = i[541];
assign o[156] = i[540];
assign o[155] = i[539];
assign o[154] = i[538];
assign o[153] = i[537];
assign o[152] = i[536];
assign o[151] = i[535];
assign o[150] = i[534];
assign o[149] = i[533];
assign o[148] = i[532];
assign o[147] = i[531];
assign o[146] = i[530];
assign o[145] = i[529];
assign o[144] = i[528];
assign o[143] = i[527];
assign o[142] = i[526];
assign o[141] = i[525];
assign o[140] = i[524];
assign o[139] = i[523];
assign o[138] = i[522];
assign o[137] = i[521];
assign o[136] = i[520];
assign o[135] = i[519];
assign o[134] = i[518];
assign o[133] = i[517];
assign o[132] = i[516];
assign o[131] = i[515];
assign o[130] = i[514];
assign o[129] = i[513];
assign o[128] = i[512];
assign o[127] = i[127];
assign o[126] = i[126];
assign o[125] = i[125];
assign o[124] = i[124];
assign o[123] = i[123];
assign o[122] = i[122];
assign o[121] = i[121];
assign o[120] = i[120];
assign o[119] = i[119];
assign o[118] = i[118];
assign o[117] = i[117];
assign o[116] = i[116];
assign o[115] = i[115];
assign o[114] = i[114];
assign o[113] = i[113];
assign o[112] = i[112];
assign o[111] = i[111];
assign o[110] = i[110];
assign o[109] = i[109];
assign o[108] = i[108];
assign o[107] = i[107];
assign o[106] = i[106];
assign o[105] = i[105];
assign o[104] = i[104];
assign o[103] = i[103];
assign o[102] = i[102];
assign o[101] = i[101];
assign o[100] = i[100];
assign o[99] = i[99];
assign o[98] = i[98];
assign o[97] = i[97];
assign o[96] = i[96];
assign o[95] = i[95];
assign o[94] = i[94];
assign o[93] = i[93];
assign o[92] = i[92];
assign o[91] = i[91];
assign o[90] = i[90];
assign o[89] = i[89];
assign o[88] = i[88];
assign o[87] = i[87];
assign o[86] = i[86];
assign o[85] = i[85];
assign o[84] = i[84];
assign o[83] = i[83];
assign o[82] = i[82];
assign o[81] = i[81];
assign o[80] = i[80];
assign o[79] = i[79];
assign o[78] = i[78];
assign o[77] = i[77];
assign o[76] = i[76];
assign o[75] = i[75];
assign o[74] = i[74];
assign o[73] = i[73];
assign o[72] = i[72];
assign o[71] = i[71];
assign o[70] = i[70];
assign o[69] = i[69];
assign o[68] = i[68];
assign o[67] = i[67];
assign o[66] = i[66];
assign o[65] = i[65];
assign o[64] = i[64];
assign o[63] = i[63];
assign o[62] = i[62];
assign o[61] = i[61];
assign o[60] = i[60];
assign o[59] = i[59];
assign o[58] = i[58];
assign o[57] = i[57];
assign o[56] = i[56];
assign o[55] = i[55];
assign o[54] = i[54];
assign o[53] = i[53];
assign o[52] = i[52];
assign o[51] = i[51];
assign o[50] = i[50];
assign o[49] = i[49];
assign o[48] = i[48];
assign o[47] = i[47];
assign o[46] = i[46];
assign o[45] = i[45];
assign o[44] = i[44];
assign o[43] = i[43];
assign o[42] = i[42];
assign o[41] = i[41];
assign o[40] = i[40];
assign o[39] = i[39];
assign o[38] = i[38];
assign o[37] = i[37];
assign o[36] = i[36];
assign o[35] = i[35];
assign o[34] = i[34];
assign o[33] = i[33];
assign o[32] = i[32];
assign o[31] = i[31];
assign o[30] = i[30];
assign o[29] = i[29];
assign o[28] = i[28];
assign o[27] = i[27];
assign o[26] = i[26];
assign o[25] = i[25];
assign o[24] = i[24];
assign o[23] = i[23];
assign o[22] = i[22];
assign o[21] = i[21];
assign o[20] = i[20];
assign o[19] = i[19];
assign o[18] = i[18];
assign o[17] = i[17];
assign o[16] = i[16];
assign o[15] = i[15];
assign o[14] = i[14];
assign o[13] = i[13];
assign o[12] = i[12];
assign o[11] = i[11];
assign o[10] = i[10];
assign o[9] = i[9];
assign o[8] = i[8];
assign o[7] = i[7];
assign o[6] = i[6];
assign o[5] = i[5];
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_width_p5_harden_p0_strength_p4
(
clk_i,
data_i,
data_o
);
input [4:0] data_i;
output [4:0] data_o;
input clk_i;
wire [4:0] data_o;
reg data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_muxi2_gatestack_width_p5_harden_p1
(
i0,
i1,
i2,
o
);
input [4:0] i0;
input [4:0] i1;
input [4:0] i2;
output [4:0] o;
wire [4:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign N6 = (N0)? i1[0] :
(N5)? i0[0] : 1'b0;
assign N0 = i2[0];
assign N8 = (N1)? i1[1] :
(N7)? i0[1] : 1'b0;
assign N1 = i2[1];
assign N10 = (N2)? i1[2] :
(N9)? i0[2] : 1'b0;
assign N2 = i2[2];
assign N12 = (N3)? i1[3] :
(N11)? i0[3] : 1'b0;
assign N3 = i2[3];
assign N14 = (N4)? i1[4] :
(N13)? i0[4] : 1'b0;
assign N4 = i2[4];
assign N5 = ~i2[0];
assign o[0] = ~N6;
assign N7 = ~i2[1];
assign o[1] = ~N8;
assign N9 = ~i2[2];
assign o[2] = ~N10;
assign N11 = ~i2[3];
assign o[3] = ~N12;
assign N13 = ~i2[4];
assign o[4] = ~N14;
endmodule |
module bsg_concentrate_static_05
(
i,
o
);
input [4:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[2];
assign o[0] = i[0];
endmodule |
module bsg_unconcentrate_static_0f
(
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_,o_2_,o_1_,o_0_;
assign o[4] = 1'b0;
assign o_3_ = i[3];
assign o[3] = o_3_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mux2_gatestack_width_p9_harden_p1
(
i0,
i1,
i2,
o
);
input [8:0] i0;
input [8:0] i1;
input [8:0] i2;
output [8:0] o;
wire [8:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17;
assign o[0] = (N0)? i1[0] :
(N9)? i0[0] : 1'b0;
assign N0 = i2[0];
assign o[1] = (N1)? i1[1] :
(N10)? i0[1] : 1'b0;
assign N1 = i2[1];
assign o[2] = (N2)? i1[2] :
(N11)? i0[2] : 1'b0;
assign N2 = i2[2];
assign o[3] = (N3)? i1[3] :
(N12)? i0[3] : 1'b0;
assign N3 = i2[3];
assign o[4] = (N4)? i1[4] :
(N13)? i0[4] : 1'b0;
assign N4 = i2[4];
assign o[5] = (N5)? i1[5] :
(N14)? i0[5] : 1'b0;
assign N5 = i2[5];
assign o[6] = (N6)? i1[6] :
(N15)? i0[6] : 1'b0;
assign N6 = i2[6];
assign o[7] = (N7)? i1[7] :
(N16)? i0[7] : 1'b0;
assign N7 = i2[7];
assign o[8] = (N8)? i1[8] :
(N17)? i0[8] : 1'b0;
assign N8 = i2[8];
assign N9 = ~i2[0];
assign N10 = ~i2[1];
assign N11 = ~i2[2];
assign N12 = ~i2[3];
assign N13 = ~i2[4];
assign N14 = ~i2[5];
assign N15 = ~i2[6];
assign N16 = ~i2[7];
assign N17 = ~i2[8];
endmodule |
module bp_cce_pending_num_way_groups_p16
(
clk_i,
reset_i,
w_v_i,
w_way_group_i,
pending_i,
r_v_i,
r_way_group_i,
pending_o,
pending_v_o
);
input [3:0] w_way_group_i;
input [3:0] r_way_group_i;
input clk_i;
input reset_i;
input w_v_i;
input pending_i;
input r_v_i;
output pending_o;
output pending_v_o;
wire pending_o,pending_v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,
N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,
N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,
N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,
N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,
N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,
N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,
N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,
N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,
N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,
N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,
N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,
N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,
N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255;
wire [31:0] pending_bits_r,pending_bits_n;
reg pending_bits_r_31_sv2v_reg,pending_bits_r_30_sv2v_reg,
pending_bits_r_29_sv2v_reg,pending_bits_r_28_sv2v_reg,pending_bits_r_27_sv2v_reg,
pending_bits_r_26_sv2v_reg,pending_bits_r_25_sv2v_reg,pending_bits_r_24_sv2v_reg,
pending_bits_r_23_sv2v_reg,pending_bits_r_22_sv2v_reg,pending_bits_r_21_sv2v_reg,
pending_bits_r_20_sv2v_reg,pending_bits_r_19_sv2v_reg,pending_bits_r_18_sv2v_reg,
pending_bits_r_17_sv2v_reg,pending_bits_r_16_sv2v_reg,pending_bits_r_15_sv2v_reg,
pending_bits_r_14_sv2v_reg,pending_bits_r_13_sv2v_reg,pending_bits_r_12_sv2v_reg,
pending_bits_r_11_sv2v_reg,pending_bits_r_10_sv2v_reg,pending_bits_r_9_sv2v_reg,
pending_bits_r_8_sv2v_reg,pending_bits_r_7_sv2v_reg,pending_bits_r_6_sv2v_reg,
pending_bits_r_5_sv2v_reg,pending_bits_r_4_sv2v_reg,pending_bits_r_3_sv2v_reg,
pending_bits_r_2_sv2v_reg,pending_bits_r_1_sv2v_reg,pending_bits_r_0_sv2v_reg;
assign pending_bits_r[31] = pending_bits_r_31_sv2v_reg;
assign pending_bits_r[30] = pending_bits_r_30_sv2v_reg;
assign pending_bits_r[29] = pending_bits_r_29_sv2v_reg;
assign pending_bits_r[28] = pending_bits_r_28_sv2v_reg;
assign pending_bits_r[27] = pending_bits_r_27_sv2v_reg;
assign pending_bits_r[26] = pending_bits_r_26_sv2v_reg;
assign pending_bits_r[25] = pending_bits_r_25_sv2v_reg;
assign pending_bits_r[24] = pending_bits_r_24_sv2v_reg;
assign pending_bits_r[23] = pending_bits_r_23_sv2v_reg;
assign pending_bits_r[22] = pending_bits_r_22_sv2v_reg;
assign pending_bits_r[21] = pending_bits_r_21_sv2v_reg;
assign pending_bits_r[20] = pending_bits_r_20_sv2v_reg;
assign pending_bits_r[19] = pending_bits_r_19_sv2v_reg;
assign pending_bits_r[18] = pending_bits_r_18_sv2v_reg;
assign pending_bits_r[17] = pending_bits_r_17_sv2v_reg;
assign pending_bits_r[16] = pending_bits_r_16_sv2v_reg;
assign pending_bits_r[15] = pending_bits_r_15_sv2v_reg;
assign pending_bits_r[14] = pending_bits_r_14_sv2v_reg;
assign pending_bits_r[13] = pending_bits_r_13_sv2v_reg;
assign pending_bits_r[12] = pending_bits_r_12_sv2v_reg;
assign pending_bits_r[11] = pending_bits_r_11_sv2v_reg;
assign pending_bits_r[10] = pending_bits_r_10_sv2v_reg;
assign pending_bits_r[9] = pending_bits_r_9_sv2v_reg;
assign pending_bits_r[8] = pending_bits_r_8_sv2v_reg;
assign pending_bits_r[7] = pending_bits_r_7_sv2v_reg;
assign pending_bits_r[6] = pending_bits_r_6_sv2v_reg;
assign pending_bits_r[5] = pending_bits_r_5_sv2v_reg;
assign pending_bits_r[4] = pending_bits_r_4_sv2v_reg;
assign pending_bits_r[3] = pending_bits_r_3_sv2v_reg;
assign pending_bits_r[2] = pending_bits_r_2_sv2v_reg;
assign pending_bits_r[1] = pending_bits_r_1_sv2v_reg;
assign pending_bits_r[0] = pending_bits_r_0_sv2v_reg;
assign pending_v_o = r_v_i;
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_31_sv2v_reg <= N63;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_30_sv2v_reg <= N62;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_29_sv2v_reg <= N61;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_28_sv2v_reg <= N60;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_27_sv2v_reg <= N59;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_26_sv2v_reg <= N58;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_25_sv2v_reg <= N57;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_24_sv2v_reg <= N56;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_23_sv2v_reg <= N55;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_22_sv2v_reg <= N54;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_21_sv2v_reg <= N53;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_20_sv2v_reg <= N52;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_19_sv2v_reg <= N51;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_18_sv2v_reg <= N50;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_17_sv2v_reg <= N49;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_16_sv2v_reg <= N48;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_15_sv2v_reg <= N47;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_14_sv2v_reg <= N46;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_13_sv2v_reg <= N45;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_12_sv2v_reg <= N44;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_11_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_10_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_9_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_8_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_7_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_6_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_5_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_4_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_3_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_2_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_1_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
pending_bits_r_0_sv2v_reg <= N32;
end
end
assign N100 = (N84)? pending_bits_r[1] :
(N86)? pending_bits_r[3] :
(N88)? pending_bits_r[5] :
(N90)? pending_bits_r[7] :
(N92)? pending_bits_r[9] :
(N94)? pending_bits_r[11] :
(N96)? pending_bits_r[13] :
(N98)? pending_bits_r[15] :
(N85)? pending_bits_r[17] :
(N87)? pending_bits_r[19] :
(N89)? pending_bits_r[21] :
(N91)? pending_bits_r[23] :
(N93)? pending_bits_r[25] :
(N95)? pending_bits_r[27] :
(N97)? pending_bits_r[29] :
(N99)? pending_bits_r[31] : 1'b0;
assign N101 = (N84)? pending_bits_r[0] :
(N86)? pending_bits_r[2] :
(N88)? pending_bits_r[4] :
(N90)? pending_bits_r[6] :
(N92)? pending_bits_r[8] :
(N94)? pending_bits_r[10] :
(N96)? pending_bits_r[12] :
(N98)? pending_bits_r[14] :
(N85)? pending_bits_r[16] :
(N87)? pending_bits_r[18] :
(N89)? pending_bits_r[20] :
(N91)? pending_bits_r[22] :
(N93)? pending_bits_r[24] :
(N95)? pending_bits_r[26] :
(N97)? pending_bits_r[28] :
(N99)? pending_bits_r[30] : 1'b0;
assign N104 = (N84)? pending_bits_r[1] :
(N86)? pending_bits_r[3] :
(N88)? pending_bits_r[5] :
(N90)? pending_bits_r[7] :
(N92)? pending_bits_r[9] :
(N94)? pending_bits_r[11] :
(N96)? pending_bits_r[13] :
(N98)? pending_bits_r[15] :
(N85)? pending_bits_r[17] :
(N87)? pending_bits_r[19] :
(N89)? pending_bits_r[21] :
(N91)? pending_bits_r[23] :
(N93)? pending_bits_r[25] :
(N95)? pending_bits_r[27] :
(N97)? pending_bits_r[29] :
(N99)? pending_bits_r[31] : 1'b0;
assign N105 = (N84)? pending_bits_r[0] :
(N86)? pending_bits_r[2] :
(N88)? pending_bits_r[4] :
(N90)? pending_bits_r[6] :
(N92)? pending_bits_r[8] :
(N94)? pending_bits_r[10] :
(N96)? pending_bits_r[12] :
(N98)? pending_bits_r[14] :
(N85)? pending_bits_r[16] :
(N87)? pending_bits_r[18] :
(N89)? pending_bits_r[20] :
(N91)? pending_bits_r[22] :
(N93)? pending_bits_r[24] :
(N95)? pending_bits_r[26] :
(N97)? pending_bits_r[28] :
(N99)? pending_bits_r[30] : 1'b0;
assign N206 = w_way_group_i == r_way_group_i;
assign N241 = (N225)? pending_bits_n[1] :
(N227)? pending_bits_n[3] :
(N229)? pending_bits_n[5] :
(N231)? pending_bits_n[7] :
(N233)? pending_bits_n[9] :
(N235)? pending_bits_n[11] :
(N237)? pending_bits_n[13] :
(N239)? pending_bits_n[15] :
(N226)? pending_bits_n[17] :
(N228)? pending_bits_n[19] :
(N230)? pending_bits_n[21] :
(N232)? pending_bits_n[23] :
(N234)? pending_bits_n[25] :
(N236)? pending_bits_n[27] :
(N238)? pending_bits_n[29] :
(N240)? pending_bits_n[31] : 1'b0;
assign N242 = (N225)? pending_bits_n[0] :
(N227)? pending_bits_n[2] :
(N229)? pending_bits_n[4] :
(N231)? pending_bits_n[6] :
(N233)? pending_bits_n[8] :
(N235)? pending_bits_n[10] :
(N237)? pending_bits_n[12] :
(N239)? pending_bits_n[14] :
(N226)? pending_bits_n[16] :
(N228)? pending_bits_n[18] :
(N230)? pending_bits_n[20] :
(N232)? pending_bits_n[22] :
(N234)? pending_bits_n[24] :
(N236)? pending_bits_n[26] :
(N238)? pending_bits_n[28] :
(N240)? pending_bits_n[30] : 1'b0;
assign N243 = (N225)? pending_bits_r[1] :
(N227)? pending_bits_r[3] :
(N229)? pending_bits_r[5] :
(N231)? pending_bits_r[7] :
(N233)? pending_bits_r[9] :
(N235)? pending_bits_r[11] :
(N237)? pending_bits_r[13] :
(N239)? pending_bits_r[15] :
(N226)? pending_bits_r[17] :
(N228)? pending_bits_r[19] :
(N230)? pending_bits_r[21] :
(N232)? pending_bits_r[23] :
(N234)? pending_bits_r[25] :
(N236)? pending_bits_r[27] :
(N238)? pending_bits_r[29] :
(N240)? pending_bits_r[31] : 1'b0;
assign N244 = (N225)? pending_bits_r[0] :
(N227)? pending_bits_r[2] :
(N229)? pending_bits_r[4] :
(N231)? pending_bits_r[6] :
(N233)? pending_bits_r[8] :
(N235)? pending_bits_r[10] :
(N237)? pending_bits_r[12] :
(N239)? pending_bits_r[14] :
(N226)? pending_bits_r[16] :
(N228)? pending_bits_r[18] :
(N230)? pending_bits_r[20] :
(N232)? pending_bits_r[22] :
(N234)? pending_bits_r[24] :
(N236)? pending_bits_r[26] :
(N238)? pending_bits_r[28] :
(N240)? pending_bits_r[30] : 1'b0;
assign N245 = N242 | N241;
assign N246 = N244 | N243;
assign { N103, N102 } = { N100, N101 } + 1'b1;
assign { N107, N106 } = { N104, N105 } - 1'b1;
assign N247 = w_way_group_i[2] & w_way_group_i[3];
assign N248 = N0 & w_way_group_i[3];
assign N0 = ~w_way_group_i[2];
assign N249 = w_way_group_i[2] & N1;
assign N1 = ~w_way_group_i[3];
assign N250 = N2 & N3;
assign N2 = ~w_way_group_i[2];
assign N3 = ~w_way_group_i[3];
assign N251 = w_way_group_i[0] & w_way_group_i[1];
assign N252 = N4 & w_way_group_i[1];
assign N4 = ~w_way_group_i[0];
assign N253 = w_way_group_i[0] & N5;
assign N5 = ~w_way_group_i[1];
assign N254 = N6 & N7;
assign N6 = ~w_way_group_i[0];
assign N7 = ~w_way_group_i[1];
assign N125 = N247 & N251;
assign N124 = N247 & N252;
assign N123 = N247 & N253;
assign N122 = N247 & N254;
assign N121 = N248 & N251;
assign N120 = N248 & N252;
assign N119 = N248 & N253;
assign N118 = N248 & N254;
assign N117 = N249 & N251;
assign N116 = N249 & N252;
assign N115 = N249 & N253;
assign N114 = N249 & N254;
assign N113 = N250 & N251;
assign N112 = N250 & N252;
assign N111 = N250 & N253;
assign N110 = N250 & N254;
assign { N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32 } = (N8)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N9)? pending_bits_n : 1'b0;
assign N8 = reset_i;
assign N9 = N31;
assign { N109, N108 } = (N10)? { N103, N102 } :
(N11)? { N107, N106 } : 1'b0;
assign N10 = pending_i;
assign N11 = N67;
assign { N128, N127 } = (N12)? { N108, N109 } :
(N126)? { pending_bits_r[0:0], pending_bits_r[1:1] } : 1'b0;
assign N12 = N110;
assign { N131, N130 } = (N13)? { N108, N109 } :
(N129)? { pending_bits_r[2:2], pending_bits_r[3:3] } : 1'b0;
assign N13 = N111;
assign { N134, N133 } = (N14)? { N108, N109 } :
(N132)? { pending_bits_r[4:4], pending_bits_r[5:5] } : 1'b0;
assign N14 = N112;
assign { N137, N136 } = (N15)? { N108, N109 } :
(N135)? { pending_bits_r[6:6], pending_bits_r[7:7] } : 1'b0;
assign N15 = N113;
assign { N140, N139 } = (N16)? { N108, N109 } :
(N138)? { pending_bits_r[8:8], pending_bits_r[9:9] } : 1'b0;
assign N16 = N114;
assign { N143, N142 } = (N17)? { N108, N109 } :
(N141)? { pending_bits_r[10:10], pending_bits_r[11:11] } : 1'b0;
assign N17 = N115;
assign { N146, N145 } = (N18)? { N108, N109 } :
(N144)? { pending_bits_r[12:12], pending_bits_r[13:13] } : 1'b0;
assign N18 = N116;
assign { N149, N148 } = (N19)? { N108, N109 } :
(N147)? { pending_bits_r[14:14], pending_bits_r[15:15] } : 1'b0;
assign N19 = N117;
assign { N152, N151 } = (N20)? { N108, N109 } :
(N150)? { pending_bits_r[16:16], pending_bits_r[17:17] } : 1'b0;
assign N20 = N118;
assign { N155, N154 } = (N21)? { N108, N109 } :
(N153)? { pending_bits_r[18:18], pending_bits_r[19:19] } : 1'b0;
assign N21 = N119;
assign { N158, N157 } = (N22)? { N108, N109 } :
(N156)? { pending_bits_r[20:20], pending_bits_r[21:21] } : 1'b0;
assign N22 = N120;
assign { N161, N160 } = (N23)? { N108, N109 } :
(N159)? { pending_bits_r[22:22], pending_bits_r[23:23] } : 1'b0;
assign N23 = N121;
assign { N164, N163 } = (N24)? { N108, N109 } :
(N162)? { pending_bits_r[24:24], pending_bits_r[25:25] } : 1'b0;
assign N24 = N122;
assign { N167, N166 } = (N25)? { N108, N109 } :
(N165)? { pending_bits_r[26:26], pending_bits_r[27:27] } : 1'b0;
assign N25 = N123;
assign { N170, N169 } = (N26)? { N108, N109 } :
(N168)? { pending_bits_r[28:28], pending_bits_r[29:29] } : 1'b0;
assign N26 = N124;
assign { N173, N172 } = (N27)? { N108, N109 } :
(N171)? { pending_bits_r[30:30], pending_bits_r[31:31] } : 1'b0;
assign N27 = N125;
assign { N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174 } = (N28)? { N172, N173, N169, N170, N166, N167, N163, N164, N160, N161, N157, N158, N154, N155, N151, N152, N148, N149, N145, N146, N142, N143, N139, N140, N136, N137, N133, N134, N130, N131, N127, N128 } :
(N29)? pending_bits_r : 1'b0;
assign N28 = w_v_i;
assign N29 = N65;
assign pending_bits_n = (N8)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N9)? { N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174 } : 1'b0;
assign pending_o = (N30)? N245 :
(N208)? N246 : 1'b0;
assign N30 = N207;
assign N31 = ~reset_i;
assign N64 = N31;
assign N65 = ~w_v_i;
assign N66 = N64 & w_v_i;
assign N67 = ~pending_i;
assign N68 = ~w_way_group_i[0];
assign N69 = ~w_way_group_i[1];
assign N70 = N68 & N69;
assign N71 = N68 & w_way_group_i[1];
assign N72 = w_way_group_i[0] & N69;
assign N73 = w_way_group_i[0] & w_way_group_i[1];
assign N74 = ~w_way_group_i[2];
assign N75 = N70 & N74;
assign N76 = N70 & w_way_group_i[2];
assign N77 = N72 & N74;
assign N78 = N72 & w_way_group_i[2];
assign N79 = N71 & N74;
assign N80 = N71 & w_way_group_i[2];
assign N81 = N73 & N74;
assign N82 = N73 & w_way_group_i[2];
assign N83 = ~w_way_group_i[3];
assign N84 = N75 & N83;
assign N85 = N75 & w_way_group_i[3];
assign N86 = N77 & N83;
assign N87 = N77 & w_way_group_i[3];
assign N88 = N79 & N83;
assign N89 = N79 & w_way_group_i[3];
assign N90 = N81 & N83;
assign N91 = N81 & w_way_group_i[3];
assign N92 = N76 & N83;
assign N93 = N76 & w_way_group_i[3];
assign N94 = N78 & N83;
assign N95 = N78 & w_way_group_i[3];
assign N96 = N80 & N83;
assign N97 = N80 & w_way_group_i[3];
assign N98 = N82 & N83;
assign N99 = N82 & w_way_group_i[3];
assign N126 = ~N110;
assign N129 = ~N111;
assign N132 = ~N112;
assign N135 = ~N113;
assign N138 = ~N114;
assign N141 = ~N115;
assign N144 = ~N116;
assign N147 = ~N117;
assign N150 = ~N118;
assign N153 = ~N119;
assign N156 = ~N120;
assign N159 = ~N121;
assign N162 = ~N122;
assign N165 = ~N123;
assign N168 = ~N124;
assign N171 = ~N125;
assign N207 = N255 & N206;
assign N255 = pending_v_o & w_v_i;
assign N208 = ~N207;
assign N209 = ~r_way_group_i[0];
assign N210 = ~r_way_group_i[1];
assign N211 = N209 & N210;
assign N212 = N209 & r_way_group_i[1];
assign N213 = r_way_group_i[0] & N210;
assign N214 = r_way_group_i[0] & r_way_group_i[1];
assign N215 = ~r_way_group_i[2];
assign N216 = N211 & N215;
assign N217 = N211 & r_way_group_i[2];
assign N218 = N213 & N215;
assign N219 = N213 & r_way_group_i[2];
assign N220 = N212 & N215;
assign N221 = N212 & r_way_group_i[2];
assign N222 = N214 & N215;
assign N223 = N214 & r_way_group_i[2];
assign N224 = ~r_way_group_i[3];
assign N225 = N216 & N224;
assign N226 = N216 & r_way_group_i[3];
assign N227 = N218 & N224;
assign N228 = N218 & r_way_group_i[3];
assign N229 = N220 & N224;
assign N230 = N220 & r_way_group_i[3];
assign N231 = N222 & N224;
assign N232 = N222 & r_way_group_i[3];
assign N233 = N217 & N224;
assign N234 = N217 & r_way_group_i[3];
assign N235 = N219 & N224;
assign N236 = N219 & r_way_group_i[3];
assign N237 = N221 & N224;
assign N238 = N221 & r_way_group_i[3];
assign N239 = N223 & N224;
assign N240 = N223 & r_way_group_i[3];
endmodule |
module bp_be_detector_05
(
clk_i,
reset_i,
cfg_bus_i,
isd_status_i,
calc_status_i,
expected_npc_i,
fe_cmd_ready_i,
mmu_cmd_ready_i,
credits_full_i,
credits_empty_i,
debug_mode_i,
single_step_i,
chk_dispatch_v_o
);
input [309:0] cfg_bus_i;
input [85:0] isd_status_i;
input [106:0] calc_status_i;
input [38:0] expected_npc_i;
input clk_i;
input reset_i;
input fe_cmd_ready_i;
input mmu_cmd_ready_i;
input credits_full_i;
input credits_empty_i;
input debug_mode_i;
input single_step_i;
output chk_dispatch_v_o;
wire chk_dispatch_v_o,N0,N1,N2,N3,N4,N5,instr_in_pipe_v,mem_in_pipe_v,fence_haz_v,
interrupt_haz_v,debug_haz_v,queue_haz_v,step_haz_v,serial_haz_v,control_haz_v,
data_haz_v,struct_haz_v,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57;
wire [2:0] rs1_match_vector,rs2_match_vector,frs1_data_haz_v,frs2_data_haz_v;
wire [1:0] irs1_data_haz_v,irs2_data_haz_v;
assign N0 = isd_status_i[11:7] == calc_status_i[4:0];
assign N1 = isd_status_i[4:0] == calc_status_i[4:0];
assign N2 = isd_status_i[11:7] == calc_status_i[17:13];
assign N3 = isd_status_i[4:0] == calc_status_i[17:13];
assign N4 = isd_status_i[11:7] == calc_status_i[30:26];
assign N5 = isd_status_i[4:0] == calc_status_i[30:26];
assign N6 = isd_status_i[10] | isd_status_i[11];
assign N7 = isd_status_i[9] | N6;
assign N8 = isd_status_i[8] | N7;
assign N9 = isd_status_i[7] | N8;
assign N10 = isd_status_i[3] | isd_status_i[4];
assign N11 = isd_status_i[2] | N10;
assign N12 = isd_status_i[1] | N11;
assign N13 = isd_status_i[0] | N12;
assign rs1_match_vector[0] = N9 & N0;
assign rs2_match_vector[0] = N13 & N1;
assign rs1_match_vector[1] = N9 & N2;
assign rs2_match_vector[1] = N13 & N3;
assign rs1_match_vector[2] = N9 & N4;
assign rs2_match_vector[2] = N13 & N5;
assign irs1_data_haz_v[0] = N14 & N15;
assign N14 = isd_status_i[13] & rs1_match_vector[0];
assign N15 = calc_status_i[10] | calc_status_i[9];
assign irs2_data_haz_v[0] = N16 & N17;
assign N16 = isd_status_i[6] & rs2_match_vector[0];
assign N17 = calc_status_i[10] | calc_status_i[9];
assign frs1_data_haz_v[0] = N18 & N19;
assign N18 = isd_status_i[12] & rs1_match_vector[0];
assign N19 = calc_status_i[8] | calc_status_i[7];
assign frs2_data_haz_v[0] = N20 & N21;
assign N20 = isd_status_i[5] & rs2_match_vector[0];
assign N21 = calc_status_i[8] | calc_status_i[7];
assign irs1_data_haz_v[1] = N22 & calc_status_i[22];
assign N22 = isd_status_i[13] & rs1_match_vector[1];
assign irs2_data_haz_v[1] = N23 & calc_status_i[22];
assign N23 = isd_status_i[6] & rs2_match_vector[1];
assign frs1_data_haz_v[1] = N24 & N25;
assign N24 = isd_status_i[12] & rs1_match_vector[1];
assign N25 = calc_status_i[21] | calc_status_i[20];
assign frs2_data_haz_v[1] = N26 & N27;
assign N26 = isd_status_i[5] & rs2_match_vector[1];
assign N27 = calc_status_i[21] | calc_status_i[20];
assign frs1_data_haz_v[2] = N28 & calc_status_i[33];
assign N28 = isd_status_i[12] & rs1_match_vector[2];
assign frs2_data_haz_v[2] = N29 & calc_status_i[33];
assign N29 = isd_status_i[5] & rs2_match_vector[2];
assign instr_in_pipe_v = N30 | calc_status_i[38];
assign N30 = calc_status_i[12] | calc_status_i[25];
assign mem_in_pipe_v = N31 | calc_status_i[31];
assign N31 = calc_status_i[5] | calc_status_i[18];
assign fence_haz_v = N34 | N35;
assign N34 = isd_status_i[15] & N33;
assign N33 = N32 | mem_in_pipe_v;
assign N32 = ~credits_empty_i;
assign N35 = isd_status_i[14] & credits_full_i;
assign interrupt_haz_v = isd_status_i[16] & instr_in_pipe_v;
assign debug_haz_v = N37 | N38;
assign N37 = N36 & debug_mode_i;
assign N36 = ~isd_status_i[17];
assign N38 = isd_status_i[17] & instr_in_pipe_v;
assign queue_haz_v = ~fe_cmd_ready_i;
assign step_haz_v = single_step_i & instr_in_pipe_v;
assign serial_haz_v = N40 | calc_status_i[45];
assign N40 = N39 | calc_status_i[32];
assign N39 = calc_status_i[6] | calc_status_i[19];
assign control_haz_v = N43 | debug_haz_v;
assign N43 = N42 | serial_haz_v;
assign N42 = N41 | step_haz_v;
assign N41 = fence_haz_v | interrupt_haz_v;
assign data_haz_v = N49 | N51;
assign N49 = N46 | N48;
assign N46 = N44 | N45;
assign N44 = irs1_data_haz_v[1] | irs1_data_haz_v[0];
assign N45 = irs2_data_haz_v[1] | irs2_data_haz_v[0];
assign N48 = N47 | frs1_data_haz_v[0];
assign N47 = frs1_data_haz_v[2] | frs1_data_haz_v[1];
assign N51 = N50 | frs2_data_haz_v[0];
assign N50 = frs2_data_haz_v[2] | frs2_data_haz_v[1];
assign struct_haz_v = N54 | queue_haz_v;
assign N54 = N52 | N53;
assign N52 = cfg_bus_i[309] & N36;
assign N53 = ~mmu_cmd_ready_i;
assign chk_dispatch_v_o = cfg_bus_i[223] | N57;
assign N57 = ~N56;
assign N56 = N55 | struct_haz_v;
assign N55 = control_haz_v | data_haz_v;
endmodule |
module bsg_unconcentrate_static_17
(
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_,o_2_,o_1_,o_0_;
assign o[3] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_2_ = i[2];
assign o[2] = o_2_;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mem_1r1w_synth_width_p5_els_p16_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [3:0] w_addr_i;
input [4:0] w_data_i;
input [3:0] r_addr_i;
output [4:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [4:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82;
wire [79:0] mem;
reg mem_79_sv2v_reg,mem_78_sv2v_reg,mem_77_sv2v_reg,mem_76_sv2v_reg,mem_75_sv2v_reg,
mem_74_sv2v_reg,mem_73_sv2v_reg,mem_72_sv2v_reg,mem_71_sv2v_reg,mem_70_sv2v_reg,
mem_69_sv2v_reg,mem_68_sv2v_reg,mem_67_sv2v_reg,mem_66_sv2v_reg,mem_65_sv2v_reg,
mem_64_sv2v_reg,mem_63_sv2v_reg,mem_62_sv2v_reg,mem_61_sv2v_reg,mem_60_sv2v_reg,
mem_59_sv2v_reg,mem_58_sv2v_reg,mem_57_sv2v_reg,mem_56_sv2v_reg,mem_55_sv2v_reg,
mem_54_sv2v_reg,mem_53_sv2v_reg,mem_52_sv2v_reg,mem_51_sv2v_reg,mem_50_sv2v_reg,
mem_49_sv2v_reg,mem_48_sv2v_reg,mem_47_sv2v_reg,mem_46_sv2v_reg,mem_45_sv2v_reg,
mem_44_sv2v_reg,mem_43_sv2v_reg,mem_42_sv2v_reg,mem_41_sv2v_reg,mem_40_sv2v_reg,
mem_39_sv2v_reg,mem_38_sv2v_reg,mem_37_sv2v_reg,mem_36_sv2v_reg,mem_35_sv2v_reg,
mem_34_sv2v_reg,mem_33_sv2v_reg,mem_32_sv2v_reg,mem_31_sv2v_reg,mem_30_sv2v_reg,
mem_29_sv2v_reg,mem_28_sv2v_reg,mem_27_sv2v_reg,mem_26_sv2v_reg,mem_25_sv2v_reg,
mem_24_sv2v_reg,mem_23_sv2v_reg,mem_22_sv2v_reg,mem_21_sv2v_reg,mem_20_sv2v_reg,
mem_19_sv2v_reg,mem_18_sv2v_reg,mem_17_sv2v_reg,mem_16_sv2v_reg,mem_15_sv2v_reg,
mem_14_sv2v_reg,mem_13_sv2v_reg,mem_12_sv2v_reg,mem_11_sv2v_reg,mem_10_sv2v_reg,
mem_9_sv2v_reg,mem_8_sv2v_reg,mem_7_sv2v_reg,mem_6_sv2v_reg,mem_5_sv2v_reg,
mem_4_sv2v_reg,mem_3_sv2v_reg,mem_2_sv2v_reg,mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[79] = mem_79_sv2v_reg;
assign mem[78] = mem_78_sv2v_reg;
assign mem[77] = mem_77_sv2v_reg;
assign mem[76] = mem_76_sv2v_reg;
assign mem[75] = mem_75_sv2v_reg;
assign mem[74] = mem_74_sv2v_reg;
assign mem[73] = mem_73_sv2v_reg;
assign mem[72] = mem_72_sv2v_reg;
assign mem[71] = mem_71_sv2v_reg;
assign mem[70] = mem_70_sv2v_reg;
assign mem[69] = mem_69_sv2v_reg;
assign mem[68] = mem_68_sv2v_reg;
assign mem[67] = mem_67_sv2v_reg;
assign mem[66] = mem_66_sv2v_reg;
assign mem[65] = mem_65_sv2v_reg;
assign mem[64] = mem_64_sv2v_reg;
assign mem[63] = mem_63_sv2v_reg;
assign mem[62] = mem_62_sv2v_reg;
assign mem[61] = mem_61_sv2v_reg;
assign mem[60] = mem_60_sv2v_reg;
assign mem[59] = mem_59_sv2v_reg;
assign mem[58] = mem_58_sv2v_reg;
assign mem[57] = mem_57_sv2v_reg;
assign mem[56] = mem_56_sv2v_reg;
assign mem[55] = mem_55_sv2v_reg;
assign mem[54] = mem_54_sv2v_reg;
assign mem[53] = mem_53_sv2v_reg;
assign mem[52] = mem_52_sv2v_reg;
assign mem[51] = mem_51_sv2v_reg;
assign mem[50] = mem_50_sv2v_reg;
assign mem[49] = mem_49_sv2v_reg;
assign mem[48] = mem_48_sv2v_reg;
assign mem[47] = mem_47_sv2v_reg;
assign mem[46] = mem_46_sv2v_reg;
assign mem[45] = mem_45_sv2v_reg;
assign mem[44] = mem_44_sv2v_reg;
assign mem[43] = mem_43_sv2v_reg;
assign mem[42] = mem_42_sv2v_reg;
assign mem[41] = mem_41_sv2v_reg;
assign mem[40] = mem_40_sv2v_reg;
assign mem[39] = mem_39_sv2v_reg;
assign mem[38] = mem_38_sv2v_reg;
assign mem[37] = mem_37_sv2v_reg;
assign mem[36] = mem_36_sv2v_reg;
assign mem[35] = mem_35_sv2v_reg;
assign mem[34] = mem_34_sv2v_reg;
assign mem[33] = mem_33_sv2v_reg;
assign mem[32] = mem_32_sv2v_reg;
assign mem[31] = mem_31_sv2v_reg;
assign mem[30] = mem_30_sv2v_reg;
assign mem[29] = mem_29_sv2v_reg;
assign mem[28] = mem_28_sv2v_reg;
assign mem[27] = mem_27_sv2v_reg;
assign mem[26] = mem_26_sv2v_reg;
assign mem[25] = mem_25_sv2v_reg;
assign mem[24] = mem_24_sv2v_reg;
assign mem[23] = mem_23_sv2v_reg;
assign mem[22] = mem_22_sv2v_reg;
assign mem[21] = mem_21_sv2v_reg;
assign mem[20] = mem_20_sv2v_reg;
assign mem[19] = mem_19_sv2v_reg;
assign mem[18] = mem_18_sv2v_reg;
assign mem[17] = mem_17_sv2v_reg;
assign mem[16] = mem_16_sv2v_reg;
assign mem[15] = mem_15_sv2v_reg;
assign mem[14] = mem_14_sv2v_reg;
assign mem[13] = mem_13_sv2v_reg;
assign mem[12] = mem_12_sv2v_reg;
assign mem[11] = mem_11_sv2v_reg;
assign mem[10] = mem_10_sv2v_reg;
assign mem[9] = mem_9_sv2v_reg;
assign mem[8] = mem_8_sv2v_reg;
assign mem[7] = mem_7_sv2v_reg;
assign mem[6] = mem_6_sv2v_reg;
assign mem[5] = mem_5_sv2v_reg;
assign mem[4] = mem_4_sv2v_reg;
assign mem[3] = mem_3_sv2v_reg;
assign mem[2] = mem_2_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[4] = (N26)? mem[4] :
(N28)? mem[9] :
(N30)? mem[14] :
(N32)? mem[19] :
(N34)? mem[24] :
(N36)? mem[29] :
(N38)? mem[34] :
(N40)? mem[39] :
(N27)? mem[44] :
(N29)? mem[49] :
(N31)? mem[54] :
(N33)? mem[59] :
(N35)? mem[64] :
(N37)? mem[69] :
(N39)? mem[74] :
(N41)? mem[79] : 1'b0;
assign r_data_o[3] = (N26)? mem[3] :
(N28)? mem[8] :
(N30)? mem[13] :
(N32)? mem[18] :
(N34)? mem[23] :
(N36)? mem[28] :
(N38)? mem[33] :
(N40)? mem[38] :
(N27)? mem[43] :
(N29)? mem[48] :
(N31)? mem[53] :
(N33)? mem[58] :
(N35)? mem[63] :
(N37)? mem[68] :
(N39)? mem[73] :
(N41)? mem[78] : 1'b0;
assign r_data_o[2] = (N26)? mem[2] :
(N28)? mem[7] :
(N30)? mem[12] :
(N32)? mem[17] :
(N34)? mem[22] :
(N36)? mem[27] :
(N38)? mem[32] :
(N40)? mem[37] :
(N27)? mem[42] :
(N29)? mem[47] :
(N31)? mem[52] :
(N33)? mem[57] :
(N35)? mem[62] :
(N37)? mem[67] :
(N39)? mem[72] :
(N41)? mem[77] : 1'b0;
assign r_data_o[1] = (N26)? mem[1] :
(N28)? mem[6] :
(N30)? mem[11] :
(N32)? mem[16] :
(N34)? mem[21] :
(N36)? mem[26] :
(N38)? mem[31] :
(N40)? mem[36] :
(N27)? mem[41] :
(N29)? mem[46] :
(N31)? mem[51] :
(N33)? mem[56] :
(N35)? mem[61] :
(N37)? mem[66] :
(N39)? mem[71] :
(N41)? mem[76] : 1'b0;
assign r_data_o[0] = (N26)? mem[0] :
(N28)? mem[5] :
(N30)? mem[10] :
(N32)? mem[15] :
(N34)? mem[20] :
(N36)? mem[25] :
(N38)? mem[30] :
(N40)? mem[35] :
(N27)? mem[40] :
(N29)? mem[45] :
(N31)? mem[50] :
(N33)? mem[55] :
(N35)? mem[60] :
(N37)? mem[65] :
(N39)? mem[70] :
(N41)? mem[75] : 1'b0;
always @(posedge w_clk_i) begin
if(N74) begin
mem_79_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N74) begin
mem_78_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N74) begin
mem_77_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N74) begin
mem_76_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N74) begin
mem_75_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N73) begin
mem_74_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N73) begin
mem_73_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N73) begin
mem_72_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N73) begin
mem_71_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N73) begin
mem_70_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N72) begin
mem_69_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N72) begin
mem_68_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N72) begin
mem_67_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N72) begin
mem_66_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N72) begin
mem_65_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N71) begin
mem_64_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N71) begin
mem_63_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N71) begin
mem_62_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N71) begin
mem_61_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N71) begin
mem_60_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N70) begin
mem_59_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N70) begin
mem_58_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N70) begin
mem_57_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N70) begin
mem_56_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N70) begin
mem_55_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N69) begin
mem_54_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N69) begin
mem_53_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N69) begin
mem_52_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N69) begin
mem_51_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N69) begin
mem_50_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N68) begin
mem_49_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N68) begin
mem_48_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N68) begin
mem_47_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N68) begin
mem_46_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N68) begin
mem_45_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N67) begin
mem_44_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N67) begin
mem_43_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N67) begin
mem_42_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N67) begin
mem_41_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N67) begin
mem_40_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N66) begin
mem_39_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N66) begin
mem_38_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N66) begin
mem_37_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N66) begin
mem_36_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N66) begin
mem_35_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N65) begin
mem_34_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N65) begin
mem_33_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N65) begin
mem_32_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N65) begin
mem_31_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N65) begin
mem_30_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N64) begin
mem_29_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N64) begin
mem_28_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N64) begin
mem_27_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N64) begin
mem_26_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N64) begin
mem_25_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N63) begin
mem_24_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N63) begin
mem_23_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N63) begin
mem_22_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N63) begin
mem_21_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N63) begin
mem_20_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N62) begin
mem_19_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N62) begin
mem_18_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N62) begin
mem_17_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N62) begin
mem_16_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N62) begin
mem_15_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N61) begin
mem_14_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N61) begin
mem_13_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N61) begin
mem_12_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N61) begin
mem_11_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N61) begin
mem_10_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N60) begin
mem_9_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N60) begin
mem_8_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N60) begin
mem_7_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N60) begin
mem_6_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N60) begin
mem_5_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N59) begin
mem_4_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N59) begin
mem_3_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N59) begin
mem_2_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N59) begin
mem_1_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N59) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N75 = w_addr_i[2] & w_addr_i[3];
assign N76 = N0 & w_addr_i[3];
assign N0 = ~w_addr_i[2];
assign N77 = w_addr_i[2] & N1;
assign N1 = ~w_addr_i[3];
assign N78 = N2 & N3;
assign N2 = ~w_addr_i[2];
assign N3 = ~w_addr_i[3];
assign N79 = w_addr_i[0] & w_addr_i[1];
assign N80 = N4 & w_addr_i[1];
assign N4 = ~w_addr_i[0];
assign N81 = w_addr_i[0] & N5;
assign N5 = ~w_addr_i[1];
assign N82 = N6 & N7;
assign N6 = ~w_addr_i[0];
assign N7 = ~w_addr_i[1];
assign N58 = N75 & N79;
assign N57 = N75 & N80;
assign N56 = N75 & N81;
assign N55 = N75 & N82;
assign N54 = N76 & N79;
assign N53 = N76 & N80;
assign N52 = N76 & N81;
assign N51 = N76 & N82;
assign N50 = N77 & N79;
assign N49 = N77 & N80;
assign N48 = N77 & N81;
assign N47 = N77 & N82;
assign N46 = N78 & N79;
assign N45 = N78 & N80;
assign N44 = N78 & N81;
assign N43 = N78 & N82;
assign { N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59 } = (N8)? { N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = w_v_i;
assign N9 = N42;
assign N10 = ~r_addr_i[0];
assign N11 = ~r_addr_i[1];
assign N12 = N10 & N11;
assign N13 = N10 & r_addr_i[1];
assign N14 = r_addr_i[0] & N11;
assign N15 = r_addr_i[0] & r_addr_i[1];
assign N16 = ~r_addr_i[2];
assign N17 = N12 & N16;
assign N18 = N12 & r_addr_i[2];
assign N19 = N14 & N16;
assign N20 = N14 & r_addr_i[2];
assign N21 = N13 & N16;
assign N22 = N13 & r_addr_i[2];
assign N23 = N15 & N16;
assign N24 = N15 & r_addr_i[2];
assign N25 = ~r_addr_i[3];
assign N26 = N17 & N25;
assign N27 = N17 & r_addr_i[3];
assign N28 = N19 & N25;
assign N29 = N19 & r_addr_i[3];
assign N30 = N21 & N25;
assign N31 = N21 & r_addr_i[3];
assign N32 = N23 & N25;
assign N33 = N23 & r_addr_i[3];
assign N34 = N18 & N25;
assign N35 = N18 & r_addr_i[3];
assign N36 = N20 & N25;
assign N37 = N20 & r_addr_i[3];
assign N38 = N22 & N25;
assign N39 = N22 & r_addr_i[3];
assign N40 = N24 & N25;
assign N41 = N24 & r_addr_i[3];
assign N42 = ~w_v_i;
endmodule |
module bsg_swap_width_p256
(
data_i,
swap_i,
data_o
);
input [511:0] data_i;
output [511:0] data_o;
input swap_i;
wire [511:0] data_o;
wire N0,N1,N2;
assign data_o = (N0)? { data_i[255:0], data_i[511:256] } :
(N1)? data_i : 1'b0;
assign N0 = swap_i;
assign N1 = N2;
assign N2 = ~swap_i;
endmodule |
module bsg_mux_width_p1_els_p2
(
data_i,
sel_i,
data_o
);
input [1:0] data_i;
input [0:0] sel_i;
output [0:0] data_o;
wire [0:0] data_o;
wire N0,N1;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[1] : 1'b0;
assign N0 = sel_i[0];
assign N1 = ~sel_i[0];
endmodule |
module bp_be_pipe_fp
(
clk_i,
reset_i,
decode_i,
rs1_i,
rs2_i,
data_o
);
input [29:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
output [63:0] data_o;
input clk_i;
input reset_i;
wire [63:0] data_o;
assign data_o[0] = 1'b0;
assign data_o[1] = 1'b0;
assign data_o[2] = 1'b0;
assign data_o[3] = 1'b0;
assign data_o[4] = 1'b0;
assign data_o[5] = 1'b0;
assign data_o[6] = 1'b0;
assign data_o[7] = 1'b0;
assign data_o[8] = 1'b0;
assign data_o[9] = 1'b0;
assign data_o[10] = 1'b0;
assign data_o[11] = 1'b0;
assign data_o[12] = 1'b0;
assign data_o[13] = 1'b0;
assign data_o[14] = 1'b0;
assign data_o[15] = 1'b0;
assign data_o[16] = 1'b0;
assign data_o[17] = 1'b0;
assign data_o[18] = 1'b0;
assign data_o[19] = 1'b0;
assign data_o[20] = 1'b0;
assign data_o[21] = 1'b0;
assign data_o[22] = 1'b0;
assign data_o[23] = 1'b0;
assign data_o[24] = 1'b0;
assign data_o[25] = 1'b0;
assign data_o[26] = 1'b0;
assign data_o[27] = 1'b0;
assign data_o[28] = 1'b0;
assign data_o[29] = 1'b0;
assign data_o[30] = 1'b0;
assign data_o[31] = 1'b0;
assign data_o[32] = 1'b0;
assign data_o[33] = 1'b0;
assign data_o[34] = 1'b0;
assign data_o[35] = 1'b0;
assign data_o[36] = 1'b0;
assign data_o[37] = 1'b0;
assign data_o[38] = 1'b0;
assign data_o[39] = 1'b0;
assign data_o[40] = 1'b0;
assign data_o[41] = 1'b0;
assign data_o[42] = 1'b0;
assign data_o[43] = 1'b0;
assign data_o[44] = 1'b0;
assign data_o[45] = 1'b0;
assign data_o[46] = 1'b0;
assign data_o[47] = 1'b0;
assign data_o[48] = 1'b0;
assign data_o[49] = 1'b0;
assign data_o[50] = 1'b0;
assign data_o[51] = 1'b0;
assign data_o[52] = 1'b0;
assign data_o[53] = 1'b0;
assign data_o[54] = 1'b0;
assign data_o[55] = 1'b0;
assign data_o[56] = 1'b0;
assign data_o[57] = 1'b0;
assign data_o[58] = 1'b0;
assign data_o[59] = 1'b0;
assign data_o[60] = 1'b0;
assign data_o[61] = 1'b0;
assign data_o[62] = 1'b0;
assign data_o[63] = 1'b0;
endmodule |
module bsg_mem_1r1w_synth_width_p1_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [0:0] w_data_i;
input [0:0] r_addr_i;
output [0:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [0:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
wire [1:0] mem;
reg mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[1] : 1'b0;
assign N0 = r_addr_i[0];
always @(posedge w_clk_i) begin
if(N8) begin
mem_1_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
endmodule |
module bsg_dff_reset_width_p84
(
clk_i,
reset_i,
data_i,
data_o
);
input [83:0] data_i;
output [83:0] data_o;
input clk_i;
input reset_i;
wire [83:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86;
reg data_o_83_sv2v_reg,data_o_82_sv2v_reg,data_o_81_sv2v_reg,data_o_80_sv2v_reg,
data_o_79_sv2v_reg,data_o_78_sv2v_reg,data_o_77_sv2v_reg,data_o_76_sv2v_reg,
data_o_75_sv2v_reg,data_o_74_sv2v_reg,data_o_73_sv2v_reg,data_o_72_sv2v_reg,
data_o_71_sv2v_reg,data_o_70_sv2v_reg,data_o_69_sv2v_reg,data_o_68_sv2v_reg,
data_o_67_sv2v_reg,data_o_66_sv2v_reg,data_o_65_sv2v_reg,data_o_64_sv2v_reg,data_o_63_sv2v_reg,
data_o_62_sv2v_reg,data_o_61_sv2v_reg,data_o_60_sv2v_reg,data_o_59_sv2v_reg,
data_o_58_sv2v_reg,data_o_57_sv2v_reg,data_o_56_sv2v_reg,data_o_55_sv2v_reg,
data_o_54_sv2v_reg,data_o_53_sv2v_reg,data_o_52_sv2v_reg,data_o_51_sv2v_reg,
data_o_50_sv2v_reg,data_o_49_sv2v_reg,data_o_48_sv2v_reg,data_o_47_sv2v_reg,
data_o_46_sv2v_reg,data_o_45_sv2v_reg,data_o_44_sv2v_reg,data_o_43_sv2v_reg,data_o_42_sv2v_reg,
data_o_41_sv2v_reg,data_o_40_sv2v_reg,data_o_39_sv2v_reg,data_o_38_sv2v_reg,
data_o_37_sv2v_reg,data_o_36_sv2v_reg,data_o_35_sv2v_reg,data_o_34_sv2v_reg,
data_o_33_sv2v_reg,data_o_32_sv2v_reg,data_o_31_sv2v_reg,data_o_30_sv2v_reg,
data_o_29_sv2v_reg,data_o_28_sv2v_reg,data_o_27_sv2v_reg,data_o_26_sv2v_reg,
data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,data_o_21_sv2v_reg,
data_o_20_sv2v_reg,data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,
data_o_16_sv2v_reg,data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,
data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,
data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,
data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[83] = data_o_83_sv2v_reg;
assign data_o[82] = data_o_82_sv2v_reg;
assign data_o[81] = data_o_81_sv2v_reg;
assign data_o[80] = data_o_80_sv2v_reg;
assign data_o[79] = data_o_79_sv2v_reg;
assign data_o[78] = data_o_78_sv2v_reg;
assign data_o[77] = data_o_77_sv2v_reg;
assign data_o[76] = data_o_76_sv2v_reg;
assign data_o[75] = data_o_75_sv2v_reg;
assign data_o[74] = data_o_74_sv2v_reg;
assign data_o[73] = data_o_73_sv2v_reg;
assign data_o[72] = data_o_72_sv2v_reg;
assign data_o[71] = data_o_71_sv2v_reg;
assign data_o[70] = data_o_70_sv2v_reg;
assign data_o[69] = data_o_69_sv2v_reg;
assign data_o[68] = data_o_68_sv2v_reg;
assign data_o[67] = data_o_67_sv2v_reg;
assign data_o[66] = data_o_66_sv2v_reg;
assign data_o[65] = data_o_65_sv2v_reg;
assign data_o[64] = data_o_64_sv2v_reg;
assign data_o[63] = data_o_63_sv2v_reg;
assign data_o[62] = data_o_62_sv2v_reg;
assign data_o[61] = data_o_61_sv2v_reg;
assign data_o[60] = data_o_60_sv2v_reg;
assign data_o[59] = data_o_59_sv2v_reg;
assign data_o[58] = data_o_58_sv2v_reg;
assign data_o[57] = data_o_57_sv2v_reg;
assign data_o[56] = data_o_56_sv2v_reg;
assign data_o[55] = data_o_55_sv2v_reg;
assign data_o[54] = data_o_54_sv2v_reg;
assign data_o[53] = data_o_53_sv2v_reg;
assign data_o[52] = data_o_52_sv2v_reg;
assign data_o[51] = data_o_51_sv2v_reg;
assign data_o[50] = data_o_50_sv2v_reg;
assign data_o[49] = data_o_49_sv2v_reg;
assign data_o[48] = data_o_48_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_83_sv2v_reg <= N86;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_82_sv2v_reg <= N85;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_81_sv2v_reg <= N84;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_80_sv2v_reg <= N83;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_79_sv2v_reg <= N82;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_78_sv2v_reg <= N81;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_77_sv2v_reg <= N80;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_76_sv2v_reg <= N79;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_75_sv2v_reg <= N78;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_74_sv2v_reg <= N77;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_73_sv2v_reg <= N76;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_72_sv2v_reg <= N75;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_71_sv2v_reg <= N74;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_70_sv2v_reg <= N73;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_69_sv2v_reg <= N72;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_68_sv2v_reg <= N71;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_67_sv2v_reg <= N70;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_66_sv2v_reg <= N69;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_65_sv2v_reg <= N68;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_64_sv2v_reg <= N67;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_63_sv2v_reg <= N66;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_62_sv2v_reg <= N65;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_61_sv2v_reg <= N64;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_60_sv2v_reg <= N63;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_59_sv2v_reg <= N62;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_58_sv2v_reg <= N61;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_57_sv2v_reg <= N60;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_56_sv2v_reg <= N59;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_55_sv2v_reg <= N58;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_54_sv2v_reg <= N57;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_53_sv2v_reg <= N56;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_52_sv2v_reg <= N55;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_51_sv2v_reg <= N54;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_50_sv2v_reg <= N53;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_49_sv2v_reg <= N52;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_48_sv2v_reg <= N51;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_47_sv2v_reg <= N50;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_46_sv2v_reg <= N49;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_45_sv2v_reg <= N48;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_44_sv2v_reg <= N47;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_43_sv2v_reg <= N46;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_42_sv2v_reg <= N45;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_41_sv2v_reg <= N44;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_40_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_39_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_38_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
Subsets and Splits