module
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|
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module RegRst_0x9f365fdf6c8998a
(
input wire [ 0:0] clk,
input wire [ 1:0] in_,
output reg [ 1:0] out,
input wire [ 0:0] reset
);
// localparam declarations
localparam reset_value = 0;
// PYMTL SOURCE:
//
// @s.posedge_clk
// def seq_logic():
// if s.reset:
// s.out.next = reset_value
// else:
// s.out.next = s.in_
// logic for seq_logic()
always @ (posedge clk) begin
if (reset) begin
out <= reset_value;
end
else begin
out <= in_;
end
end
endmodule |
module ZeroComparator_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
input wire [ 15:0] in_,
output reg [ 0:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// s.out.value = s.in_ == 0
// logic for comb_logic()
always @ (*) begin
out = (in_ == 0);
end
endmodule |
module PMPChecker( // @[:[email protected]]
input io_pmp_0_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_0_cfg_a, // @[:[email protected]]
input io_pmp_0_cfg_x, // @[:[email protected]]
input io_pmp_0_cfg_w, // @[:[email protected]]
input io_pmp_0_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_0_addr, // @[:[email protected]]
input [31:0] io_pmp_0_mask, // @[:[email protected]]
input io_pmp_1_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_1_cfg_a, // @[:[email protected]]
input io_pmp_1_cfg_x, // @[:[email protected]]
input io_pmp_1_cfg_w, // @[:[email protected]]
input io_pmp_1_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_1_addr, // @[:[email protected]]
input [31:0] io_pmp_1_mask, // @[:[email protected]]
input io_pmp_2_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_2_cfg_a, // @[:[email protected]]
input io_pmp_2_cfg_x, // @[:[email protected]]
input io_pmp_2_cfg_w, // @[:[email protected]]
input io_pmp_2_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_2_addr, // @[:[email protected]]
input [31:0] io_pmp_2_mask, // @[:[email protected]]
input io_pmp_3_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_3_cfg_a, // @[:[email protected]]
input io_pmp_3_cfg_x, // @[:[email protected]]
input io_pmp_3_cfg_w, // @[:[email protected]]
input io_pmp_3_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_3_addr, // @[:[email protected]]
input [31:0] io_pmp_3_mask, // @[:[email protected]]
input io_pmp_4_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_4_cfg_a, // @[:[email protected]]
input io_pmp_4_cfg_x, // @[:[email protected]]
input io_pmp_4_cfg_w, // @[:[email protected]]
input io_pmp_4_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_4_addr, // @[:[email protected]]
input [31:0] io_pmp_4_mask, // @[:[email protected]]
input io_pmp_5_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_5_cfg_a, // @[:[email protected]]
input io_pmp_5_cfg_x, // @[:[email protected]]
input io_pmp_5_cfg_w, // @[:[email protected]]
input io_pmp_5_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_5_addr, // @[:[email protected]]
input [31:0] io_pmp_5_mask, // @[:[email protected]]
input io_pmp_6_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_6_cfg_a, // @[:[email protected]]
input io_pmp_6_cfg_x, // @[:[email protected]]
input io_pmp_6_cfg_w, // @[:[email protected]]
input io_pmp_6_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_6_addr, // @[:[email protected]]
input [31:0] io_pmp_6_mask, // @[:[email protected]]
input io_pmp_7_cfg_l, // @[:[email protected]]
input [1:0] io_pmp_7_cfg_a, // @[:[email protected]]
input io_pmp_7_cfg_x, // @[:[email protected]]
input io_pmp_7_cfg_w, // @[:[email protected]]
input io_pmp_7_cfg_r, // @[:[email protected]]
input [29:0] io_pmp_7_addr, // @[:[email protected]]
input [31:0] io_pmp_7_mask, // @[:[email protected]]
input [31:0] io_addr, // @[:[email protected]]
output io_r, // @[:[email protected]]
output io_w, // @[:[email protected]]
output io_x // @[:[email protected]]
);
wire _T_10; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_11; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_12; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_13; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_14; // @[PMP.scala 60:27:[email protected]]
wire [31:0] _T_15; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_16; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_17; // @[PMP.scala 63:52:[email protected]]
wire _T_18; // @[PMP.scala 63:58:[email protected]]
wire _T_19; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_24; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_25; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_26; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_27; // @[PMP.scala 60:27:[email protected]]
wire _T_28; // @[PMP.scala 77:9:[email protected]]
wire _T_29; // @[PMP.scala 88:5:[email protected]]
wire _T_34; // @[PMP.scala 77:9:[email protected]]
wire _T_35; // @[PMP.scala 94:48:[email protected]]
wire _T_36; // @[PMP.scala 132:61:[email protected]]
wire _T_37; // @[PMP.scala 132:8:[email protected]]
wire _T_38; // @[PMP.scala 163:29:[email protected]]
wire _T_91; // @[PMP.scala 181:40:[email protected]]
wire _T_93; // @[PMP.scala 182:40:[email protected]]
wire _T_95; // @[PMP.scala 183:40:[email protected]]
wire _T_97_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_97_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_97_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_98; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_103; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_104; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_105; // @[PMP.scala 63:52:[email protected]]
wire _T_106; // @[PMP.scala 63:58:[email protected]]
wire _T_107; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_112; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_113; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_114; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_115; // @[PMP.scala 60:27:[email protected]]
wire _T_116; // @[PMP.scala 77:9:[email protected]]
wire _T_117; // @[PMP.scala 88:5:[email protected]]
wire _T_123; // @[PMP.scala 94:48:[email protected]]
wire _T_124; // @[PMP.scala 132:61:[email protected]]
wire _T_125; // @[PMP.scala 132:8:[email protected]]
wire _T_126; // @[PMP.scala 163:29:[email protected]]
wire _T_179; // @[PMP.scala 181:40:[email protected]]
wire _T_181; // @[PMP.scala 182:40:[email protected]]
wire _T_183; // @[PMP.scala 183:40:[email protected]]
wire _T_185_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_185_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_185_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_186; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_191; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_192; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_193; // @[PMP.scala 63:52:[email protected]]
wire _T_194; // @[PMP.scala 63:58:[email protected]]
wire _T_195; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_200; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_201; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_202; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_203; // @[PMP.scala 60:27:[email protected]]
wire _T_204; // @[PMP.scala 77:9:[email protected]]
wire _T_205; // @[PMP.scala 88:5:[email protected]]
wire _T_211; // @[PMP.scala 94:48:[email protected]]
wire _T_212; // @[PMP.scala 132:61:[email protected]]
wire _T_213; // @[PMP.scala 132:8:[email protected]]
wire _T_214; // @[PMP.scala 163:29:[email protected]]
wire _T_267; // @[PMP.scala 181:40:[email protected]]
wire _T_269; // @[PMP.scala 182:40:[email protected]]
wire _T_271; // @[PMP.scala 183:40:[email protected]]
wire _T_273_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_273_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_273_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_274; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_279; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_280; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_281; // @[PMP.scala 63:52:[email protected]]
wire _T_282; // @[PMP.scala 63:58:[email protected]]
wire _T_283; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_288; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_289; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_290; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_291; // @[PMP.scala 60:27:[email protected]]
wire _T_292; // @[PMP.scala 77:9:[email protected]]
wire _T_293; // @[PMP.scala 88:5:[email protected]]
wire _T_299; // @[PMP.scala 94:48:[email protected]]
wire _T_300; // @[PMP.scala 132:61:[email protected]]
wire _T_301; // @[PMP.scala 132:8:[email protected]]
wire _T_302; // @[PMP.scala 163:29:[email protected]]
wire _T_355; // @[PMP.scala 181:40:[email protected]]
wire _T_357; // @[PMP.scala 182:40:[email protected]]
wire _T_359; // @[PMP.scala 183:40:[email protected]]
wire _T_361_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_361_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_361_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_362; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_367; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_368; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_369; // @[PMP.scala 63:52:[email protected]]
wire _T_370; // @[PMP.scala 63:58:[email protected]]
wire _T_371; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_376; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_377; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_378; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_379; // @[PMP.scala 60:27:[email protected]]
wire _T_380; // @[PMP.scala 77:9:[email protected]]
wire _T_381; // @[PMP.scala 88:5:[email protected]]
wire _T_387; // @[PMP.scala 94:48:[email protected]]
wire _T_388; // @[PMP.scala 132:61:[email protected]]
wire _T_389; // @[PMP.scala 132:8:[email protected]]
wire _T_390; // @[PMP.scala 163:29:[email protected]]
wire _T_443; // @[PMP.scala 181:40:[email protected]]
wire _T_445; // @[PMP.scala 182:40:[email protected]]
wire _T_447; // @[PMP.scala 183:40:[email protected]]
wire _T_449_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_449_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_449_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_450; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_455; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_456; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_457; // @[PMP.scala 63:52:[email protected]]
wire _T_458; // @[PMP.scala 63:58:[email protected]]
wire _T_459; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_464; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_465; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_466; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_467; // @[PMP.scala 60:27:[email protected]]
wire _T_468; // @[PMP.scala 77:9:[email protected]]
wire _T_469; // @[PMP.scala 88:5:[email protected]]
wire _T_475; // @[PMP.scala 94:48:[email protected]]
wire _T_476; // @[PMP.scala 132:61:[email protected]]
wire _T_477; // @[PMP.scala 132:8:[email protected]]
wire _T_478; // @[PMP.scala 163:29:[email protected]]
wire _T_531; // @[PMP.scala 181:40:[email protected]]
wire _T_533; // @[PMP.scala 182:40:[email protected]]
wire _T_535; // @[PMP.scala 183:40:[email protected]]
wire _T_537_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_537_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_537_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_538; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_543; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_544; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_545; // @[PMP.scala 63:52:[email protected]]
wire _T_546; // @[PMP.scala 63:58:[email protected]]
wire _T_547; // @[PMP.scala 46:26:[email protected]]
wire [31:0] _T_552; // @[PMP.scala 60:36:[email protected]]
wire [31:0] _T_553; // @[PMP.scala 60:29:[email protected]]
wire [31:0] _T_554; // @[PMP.scala 60:48:[email protected]]
wire [31:0] _T_555; // @[PMP.scala 60:27:[email protected]]
wire _T_556; // @[PMP.scala 77:9:[email protected]]
wire _T_557; // @[PMP.scala 88:5:[email protected]]
wire _T_563; // @[PMP.scala 94:48:[email protected]]
wire _T_564; // @[PMP.scala 132:61:[email protected]]
wire _T_565; // @[PMP.scala 132:8:[email protected]]
wire _T_566; // @[PMP.scala 163:29:[email protected]]
wire _T_619; // @[PMP.scala 181:40:[email protected]]
wire _T_621; // @[PMP.scala 182:40:[email protected]]
wire _T_623; // @[PMP.scala 183:40:[email protected]]
wire _T_625_cfg_x; // @[PMP.scala 184:8:[email protected]]
wire _T_625_cfg_w; // @[PMP.scala 184:8:[email protected]]
wire _T_625_cfg_r; // @[PMP.scala 184:8:[email protected]]
wire _T_626; // @[PMP.scala 45:20:[email protected]]
wire [31:0] _T_631; // @[PMP.scala 63:47:[email protected]]
wire [31:0] _T_632; // @[PMP.scala 63:54:[email protected]]
wire [31:0] _T_633; // @[PMP.scala 63:52:[email protected]]
wire _T_634; // @[PMP.scala 63:58:[email protected]]
wire _T_635; // @[PMP.scala 46:26:[email protected]]
wire _T_652; // @[PMP.scala 132:61:[email protected]]
wire _T_653; // @[PMP.scala 132:8:[email protected]]
wire _T_654; // @[PMP.scala 163:29:[email protected]]
wire _T_707; // @[PMP.scala 181:40:[email protected]]
wire _T_709; // @[PMP.scala 182:40:[email protected]]
wire _T_711; // @[PMP.scala 183:40:[email protected]]
assign _T_10 = io_pmp_7_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_11 = {io_pmp_7_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_12 = ~ _T_11; // @[PMP.scala 60:29:[email protected]]
assign _T_13 = _T_12 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_14 = ~ _T_13; // @[PMP.scala 60:27:[email protected]]
assign _T_15 = io_addr ^ _T_14; // @[PMP.scala 63:47:[email protected]]
assign _T_16 = ~ io_pmp_7_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_17 = _T_15 & _T_16; // @[PMP.scala 63:52:[email protected]]
assign _T_18 = _T_17 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_19 = io_pmp_7_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_24 = {io_pmp_6_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_25 = ~ _T_24; // @[PMP.scala 60:29:[email protected]]
assign _T_26 = _T_25 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_27 = ~ _T_26; // @[PMP.scala 60:27:[email protected]]
assign _T_28 = io_addr < _T_27; // @[PMP.scala 77:9:[email protected]]
assign _T_29 = _T_28 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_34 = io_addr < _T_14; // @[PMP.scala 77:9:[email protected]]
assign _T_35 = _T_29 & _T_34; // @[PMP.scala 94:48:[email protected]]
assign _T_36 = _T_19 & _T_35; // @[PMP.scala 132:61:[email protected]]
assign _T_37 = _T_10 ? _T_18 : _T_36; // @[PMP.scala 132:8:[email protected]]
assign _T_38 = io_pmp_7_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_91 = io_pmp_7_cfg_r | _T_38; // @[PMP.scala 181:40:[email protected]]
assign _T_93 = io_pmp_7_cfg_w | _T_38; // @[PMP.scala 182:40:[email protected]]
assign _T_95 = io_pmp_7_cfg_x | _T_38; // @[PMP.scala 183:40:[email protected]]
assign _T_97_cfg_x = _T_37 ? _T_95 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_97_cfg_w = _T_37 ? _T_93 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_97_cfg_r = _T_37 ? _T_91 : 1'h1; // @[PMP.scala 184:8:[email protected]]
assign _T_98 = io_pmp_6_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_103 = io_addr ^ _T_27; // @[PMP.scala 63:47:[email protected]]
assign _T_104 = ~ io_pmp_6_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_105 = _T_103 & _T_104; // @[PMP.scala 63:52:[email protected]]
assign _T_106 = _T_105 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_107 = io_pmp_6_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_112 = {io_pmp_5_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_113 = ~ _T_112; // @[PMP.scala 60:29:[email protected]]
assign _T_114 = _T_113 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_115 = ~ _T_114; // @[PMP.scala 60:27:[email protected]]
assign _T_116 = io_addr < _T_115; // @[PMP.scala 77:9:[email protected]]
assign _T_117 = _T_116 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_123 = _T_117 & _T_28; // @[PMP.scala 94:48:[email protected]]
assign _T_124 = _T_107 & _T_123; // @[PMP.scala 132:61:[email protected]]
assign _T_125 = _T_98 ? _T_106 : _T_124; // @[PMP.scala 132:8:[email protected]]
assign _T_126 = io_pmp_6_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_179 = io_pmp_6_cfg_r | _T_126; // @[PMP.scala 181:40:[email protected]]
assign _T_181 = io_pmp_6_cfg_w | _T_126; // @[PMP.scala 182:40:[email protected]]
assign _T_183 = io_pmp_6_cfg_x | _T_126; // @[PMP.scala 183:40:[email protected]]
assign _T_185_cfg_x = _T_125 ? _T_183 : _T_97_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_185_cfg_w = _T_125 ? _T_181 : _T_97_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_185_cfg_r = _T_125 ? _T_179 : _T_97_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_186 = io_pmp_5_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_191 = io_addr ^ _T_115; // @[PMP.scala 63:47:[email protected]]
assign _T_192 = ~ io_pmp_5_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_193 = _T_191 & _T_192; // @[PMP.scala 63:52:[email protected]]
assign _T_194 = _T_193 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_195 = io_pmp_5_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_200 = {io_pmp_4_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_201 = ~ _T_200; // @[PMP.scala 60:29:[email protected]]
assign _T_202 = _T_201 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_203 = ~ _T_202; // @[PMP.scala 60:27:[email protected]]
assign _T_204 = io_addr < _T_203; // @[PMP.scala 77:9:[email protected]]
assign _T_205 = _T_204 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_211 = _T_205 & _T_116; // @[PMP.scala 94:48:[email protected]]
assign _T_212 = _T_195 & _T_211; // @[PMP.scala 132:61:[email protected]]
assign _T_213 = _T_186 ? _T_194 : _T_212; // @[PMP.scala 132:8:[email protected]]
assign _T_214 = io_pmp_5_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_267 = io_pmp_5_cfg_r | _T_214; // @[PMP.scala 181:40:[email protected]]
assign _T_269 = io_pmp_5_cfg_w | _T_214; // @[PMP.scala 182:40:[email protected]]
assign _T_271 = io_pmp_5_cfg_x | _T_214; // @[PMP.scala 183:40:[email protected]]
assign _T_273_cfg_x = _T_213 ? _T_271 : _T_185_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_273_cfg_w = _T_213 ? _T_269 : _T_185_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_273_cfg_r = _T_213 ? _T_267 : _T_185_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_274 = io_pmp_4_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_279 = io_addr ^ _T_203; // @[PMP.scala 63:47:[email protected]]
assign _T_280 = ~ io_pmp_4_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_281 = _T_279 & _T_280; // @[PMP.scala 63:52:[email protected]]
assign _T_282 = _T_281 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_283 = io_pmp_4_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_288 = {io_pmp_3_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_289 = ~ _T_288; // @[PMP.scala 60:29:[email protected]]
assign _T_290 = _T_289 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_291 = ~ _T_290; // @[PMP.scala 60:27:[email protected]]
assign _T_292 = io_addr < _T_291; // @[PMP.scala 77:9:[email protected]]
assign _T_293 = _T_292 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_299 = _T_293 & _T_204; // @[PMP.scala 94:48:[email protected]]
assign _T_300 = _T_283 & _T_299; // @[PMP.scala 132:61:[email protected]]
assign _T_301 = _T_274 ? _T_282 : _T_300; // @[PMP.scala 132:8:[email protected]]
assign _T_302 = io_pmp_4_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_355 = io_pmp_4_cfg_r | _T_302; // @[PMP.scala 181:40:[email protected]]
assign _T_357 = io_pmp_4_cfg_w | _T_302; // @[PMP.scala 182:40:[email protected]]
assign _T_359 = io_pmp_4_cfg_x | _T_302; // @[PMP.scala 183:40:[email protected]]
assign _T_361_cfg_x = _T_301 ? _T_359 : _T_273_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_361_cfg_w = _T_301 ? _T_357 : _T_273_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_361_cfg_r = _T_301 ? _T_355 : _T_273_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_362 = io_pmp_3_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_367 = io_addr ^ _T_291; // @[PMP.scala 63:47:[email protected]]
assign _T_368 = ~ io_pmp_3_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_369 = _T_367 & _T_368; // @[PMP.scala 63:52:[email protected]]
assign _T_370 = _T_369 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_371 = io_pmp_3_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_376 = {io_pmp_2_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_377 = ~ _T_376; // @[PMP.scala 60:29:[email protected]]
assign _T_378 = _T_377 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_379 = ~ _T_378; // @[PMP.scala 60:27:[email protected]]
assign _T_380 = io_addr < _T_379; // @[PMP.scala 77:9:[email protected]]
assign _T_381 = _T_380 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_387 = _T_381 & _T_292; // @[PMP.scala 94:48:[email protected]]
assign _T_388 = _T_371 & _T_387; // @[PMP.scala 132:61:[email protected]]
assign _T_389 = _T_362 ? _T_370 : _T_388; // @[PMP.scala 132:8:[email protected]]
assign _T_390 = io_pmp_3_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_443 = io_pmp_3_cfg_r | _T_390; // @[PMP.scala 181:40:[email protected]]
assign _T_445 = io_pmp_3_cfg_w | _T_390; // @[PMP.scala 182:40:[email protected]]
assign _T_447 = io_pmp_3_cfg_x | _T_390; // @[PMP.scala 183:40:[email protected]]
assign _T_449_cfg_x = _T_389 ? _T_447 : _T_361_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_449_cfg_w = _T_389 ? _T_445 : _T_361_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_449_cfg_r = _T_389 ? _T_443 : _T_361_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_450 = io_pmp_2_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_455 = io_addr ^ _T_379; // @[PMP.scala 63:47:[email protected]]
assign _T_456 = ~ io_pmp_2_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_457 = _T_455 & _T_456; // @[PMP.scala 63:52:[email protected]]
assign _T_458 = _T_457 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_459 = io_pmp_2_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_464 = {io_pmp_1_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_465 = ~ _T_464; // @[PMP.scala 60:29:[email protected]]
assign _T_466 = _T_465 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_467 = ~ _T_466; // @[PMP.scala 60:27:[email protected]]
assign _T_468 = io_addr < _T_467; // @[PMP.scala 77:9:[email protected]]
assign _T_469 = _T_468 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_475 = _T_469 & _T_380; // @[PMP.scala 94:48:[email protected]]
assign _T_476 = _T_459 & _T_475; // @[PMP.scala 132:61:[email protected]]
assign _T_477 = _T_450 ? _T_458 : _T_476; // @[PMP.scala 132:8:[email protected]]
assign _T_478 = io_pmp_2_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_531 = io_pmp_2_cfg_r | _T_478; // @[PMP.scala 181:40:[email protected]]
assign _T_533 = io_pmp_2_cfg_w | _T_478; // @[PMP.scala 182:40:[email protected]]
assign _T_535 = io_pmp_2_cfg_x | _T_478; // @[PMP.scala 183:40:[email protected]]
assign _T_537_cfg_x = _T_477 ? _T_535 : _T_449_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_537_cfg_w = _T_477 ? _T_533 : _T_449_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_537_cfg_r = _T_477 ? _T_531 : _T_449_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_538 = io_pmp_1_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_543 = io_addr ^ _T_467; // @[PMP.scala 63:47:[email protected]]
assign _T_544 = ~ io_pmp_1_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_545 = _T_543 & _T_544; // @[PMP.scala 63:52:[email protected]]
assign _T_546 = _T_545 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_547 = io_pmp_1_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_552 = {io_pmp_0_addr, 2'h0}; // @[PMP.scala 60:36:[email protected]]
assign _T_553 = ~ _T_552; // @[PMP.scala 60:29:[email protected]]
assign _T_554 = _T_553 | 32'h3; // @[PMP.scala 60:48:[email protected]]
assign _T_555 = ~ _T_554; // @[PMP.scala 60:27:[email protected]]
assign _T_556 = io_addr < _T_555; // @[PMP.scala 77:9:[email protected]]
assign _T_557 = _T_556 == 1'h0; // @[PMP.scala 88:5:[email protected]]
assign _T_563 = _T_557 & _T_468; // @[PMP.scala 94:48:[email protected]]
assign _T_564 = _T_547 & _T_563; // @[PMP.scala 132:61:[email protected]]
assign _T_565 = _T_538 ? _T_546 : _T_564; // @[PMP.scala 132:8:[email protected]]
assign _T_566 = io_pmp_1_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_619 = io_pmp_1_cfg_r | _T_566; // @[PMP.scala 181:40:[email protected]]
assign _T_621 = io_pmp_1_cfg_w | _T_566; // @[PMP.scala 182:40:[email protected]]
assign _T_623 = io_pmp_1_cfg_x | _T_566; // @[PMP.scala 183:40:[email protected]]
assign _T_625_cfg_x = _T_565 ? _T_623 : _T_537_cfg_x; // @[PMP.scala 184:8:[email protected]]
assign _T_625_cfg_w = _T_565 ? _T_621 : _T_537_cfg_w; // @[PMP.scala 184:8:[email protected]]
assign _T_625_cfg_r = _T_565 ? _T_619 : _T_537_cfg_r; // @[PMP.scala 184:8:[email protected]]
assign _T_626 = io_pmp_0_cfg_a[1]; // @[PMP.scala 45:20:[email protected]]
assign _T_631 = io_addr ^ _T_555; // @[PMP.scala 63:47:[email protected]]
assign _T_632 = ~ io_pmp_0_mask; // @[PMP.scala 63:54:[email protected]]
assign _T_633 = _T_631 & _T_632; // @[PMP.scala 63:52:[email protected]]
assign _T_634 = _T_633 == 32'h0; // @[PMP.scala 63:58:[email protected]]
assign _T_635 = io_pmp_0_cfg_a[0]; // @[PMP.scala 46:26:[email protected]]
assign _T_652 = _T_635 & _T_556; // @[PMP.scala 132:61:[email protected]]
assign _T_653 = _T_626 ? _T_634 : _T_652; // @[PMP.scala 132:8:[email protected]]
assign _T_654 = io_pmp_0_cfg_l == 1'h0; // @[PMP.scala 163:29:[email protected]]
assign _T_707 = io_pmp_0_cfg_r | _T_654; // @[PMP.scala 181:40:[email protected]]
assign _T_709 = io_pmp_0_cfg_w | _T_654; // @[PMP.scala 182:40:[email protected]]
assign _T_711 = io_pmp_0_cfg_x | _T_654; // @[PMP.scala 183:40:[email protected]]
assign io_r = _T_653 ? _T_707 : _T_625_cfg_r; // @[PMP.scala 187:8:[email protected]]
assign io_w = _T_653 ? _T_709 : _T_625_cfg_w; // @[PMP.scala 188:8:[email protected]]
assign io_x = _T_653 ? _T_711 : _T_625_cfg_x; // @[PMP.scala 189:8:[email protected]]
endmodule |
module Queue_40( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask, // @[:[email protected]]
output [31:0] io_deq_bits_data // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_7;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_9;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_address__T_18_addr = value_1;
assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_address__T_10_data = io_enq_bits_address;
assign _T_address__T_10_addr = value;
assign _T_address__T_10_mask = 1'h1;
assign _T_address__T_10_en = io_enq_ready & io_enq_valid;
assign _T_mask__T_18_addr = value_1;
assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_mask__T_10_data = io_enq_bits_mask;
assign _T_mask__T_10_addr = value;
assign _T_mask__T_10_mask = 1'h1;
assign _T_mask__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_address[initvar] = _RAND_4[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_mask[initvar] = _RAND_5[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
value = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value_1 = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_address__T_10_en & _T_address__T_10_mask) begin
_T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_mask__T_10_en & _T_mask__T_10_mask) begin
_T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule |
module Queue_39( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [1:0] io_enq_bits_param, // @[:[email protected]]
input [3:0] io_enq_bits_size, // @[:[email protected]]
input io_enq_bits_source, // @[:[email protected]]
input io_enq_bits_sink, // @[:[email protected]]
input io_enq_bits_denied, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_corrupt, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [1:0] io_deq_bits_param, // @[:[email protected]]
output [3:0] io_deq_bits_size, // @[:[email protected]]
output io_deq_bits_source, // @[:[email protected]]
output io_deq_bits_sink, // @[:[email protected]]
output io_deq_bits_denied, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_sink [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_denied [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_sink__T_18_addr = value_1;
assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_sink__T_10_data = io_enq_bits_sink;
assign _T_sink__T_10_addr = value;
assign _T_sink__T_10_mask = 1'h1;
assign _T_sink__T_10_en = io_enq_ready & io_enq_valid;
assign _T_denied__T_18_addr = value_1;
assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_denied__T_10_data = io_enq_bits_denied;
assign _T_denied__T_10_addr = value;
assign _T_denied__T_10_mask = 1'h1;
assign _T_denied__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = io_enq_bits_corrupt;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_sink[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_sink__T_10_en & _T_sink__T_10_mask) begin
_T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_denied__T_10_en & _T_denied__T_10_mask) begin
_T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule |
module AMOALU( // @[:[email protected]]
input [4:0] io_cmd, // @[:[email protected]]
input [31:0] io_lhs, // @[:[email protected]]
input [31:0] io_rhs, // @[:[email protected]]
output [31:0] io_out_unmasked // @[:[email protected]]
);
wire _T; // @[AMOALU.scala 64:20:[email protected]]
wire _T_1; // @[AMOALU.scala 64:43:[email protected]]
wire max; // @[AMOALU.scala 64:33:[email protected]]
wire _T_2; // @[AMOALU.scala 65:20:[email protected]]
wire _T_3; // @[AMOALU.scala 65:43:[email protected]]
wire min; // @[AMOALU.scala 65:33:[email protected]]
wire add; // @[AMOALU.scala 66:20:[email protected]]
wire _T_4; // @[AMOALU.scala 67:26:[email protected]]
wire _T_5; // @[AMOALU.scala 67:48:[email protected]]
wire logic_and; // @[AMOALU.scala 67:38:[email protected]]
wire _T_6; // @[AMOALU.scala 68:26:[email protected]]
wire logic_xor; // @[AMOALU.scala 68:39:[email protected]]
wire [31:0] adder_out; // @[AMOALU.scala 73:21:[email protected]]
wire [4:0] _T_14; // @[AMOALU.scala 86:17:[email protected]]
wire _T_16; // @[AMOALU.scala 86:25:[email protected]]
wire _T_17; // @[AMOALU.scala 88:12:[email protected]]
wire _T_18; // @[AMOALU.scala 88:23:[email protected]]
wire _T_19; // @[AMOALU.scala 88:18:[email protected]]
wire _T_22; // @[AMOALU.scala 79:35:[email protected]]
wire _T_25; // @[AMOALU.scala 88:58:[email protected]]
wire less; // @[AMOALU.scala 88:10:[email protected]]
wire _T_26; // @[AMOALU.scala 94:23:[email protected]]
wire [31:0] minmax; // @[AMOALU.scala 94:19:[email protected]]
wire [31:0] _T_27; // @[AMOALU.scala 96:27:[email protected]]
wire [31:0] _T_28; // @[AMOALU.scala 96:8:[email protected]]
wire [31:0] _T_29; // @[AMOALU.scala 97:27:[email protected]]
wire [31:0] _T_30; // @[AMOALU.scala 97:8:[email protected]]
wire [31:0] logic_; // @[AMOALU.scala 96:42:[email protected]]
wire _T_31; // @[AMOALU.scala 100:19:[email protected]]
wire [31:0] _T_32; // @[AMOALU.scala 100:8:[email protected]]
assign _T = io_cmd == 5'hd; // @[AMOALU.scala 64:20:[email protected]]
assign _T_1 = io_cmd == 5'hf; // @[AMOALU.scala 64:43:[email protected]]
assign max = _T | _T_1; // @[AMOALU.scala 64:33:[email protected]]
assign _T_2 = io_cmd == 5'hc; // @[AMOALU.scala 65:20:[email protected]]
assign _T_3 = io_cmd == 5'he; // @[AMOALU.scala 65:43:[email protected]]
assign min = _T_2 | _T_3; // @[AMOALU.scala 65:33:[email protected]]
assign add = io_cmd == 5'h8; // @[AMOALU.scala 66:20:[email protected]]
assign _T_4 = io_cmd == 5'ha; // @[AMOALU.scala 67:26:[email protected]]
assign _T_5 = io_cmd == 5'hb; // @[AMOALU.scala 67:48:[email protected]]
assign logic_and = _T_4 | _T_5; // @[AMOALU.scala 67:38:[email protected]]
assign _T_6 = io_cmd == 5'h9; // @[AMOALU.scala 68:26:[email protected]]
assign logic_xor = _T_6 | _T_4; // @[AMOALU.scala 68:39:[email protected]]
assign adder_out = io_lhs + io_rhs; // @[AMOALU.scala 73:21:[email protected]]
assign _T_14 = io_cmd & 5'h2; // @[AMOALU.scala 86:17:[email protected]]
assign _T_16 = _T_14 == 5'h0; // @[AMOALU.scala 86:25:[email protected]]
assign _T_17 = io_lhs[31]; // @[AMOALU.scala 88:12:[email protected]]
assign _T_18 = io_rhs[31]; // @[AMOALU.scala 88:23:[email protected]]
assign _T_19 = _T_17 == _T_18; // @[AMOALU.scala 88:18:[email protected]]
assign _T_22 = io_lhs < io_rhs; // @[AMOALU.scala 79:35:[email protected]]
assign _T_25 = _T_16 ? _T_17 : _T_18; // @[AMOALU.scala 88:58:[email protected]]
assign less = _T_19 ? _T_22 : _T_25; // @[AMOALU.scala 88:10:[email protected]]
assign _T_26 = less ? min : max; // @[AMOALU.scala 94:23:[email protected]]
assign minmax = _T_26 ? io_lhs : io_rhs; // @[AMOALU.scala 94:19:[email protected]]
assign _T_27 = io_lhs & io_rhs; // @[AMOALU.scala 96:27:[email protected]]
assign _T_28 = logic_and ? _T_27 : 32'h0; // @[AMOALU.scala 96:8:[email protected]]
assign _T_29 = io_lhs ^ io_rhs; // @[AMOALU.scala 97:27:[email protected]]
assign _T_30 = logic_xor ? _T_29 : 32'h0; // @[AMOALU.scala 97:8:[email protected]]
assign logic_ = _T_28 | _T_30; // @[AMOALU.scala 96:42:[email protected]]
assign _T_31 = logic_and | logic_xor; // @[AMOALU.scala 100:19:[email protected]]
assign _T_32 = _T_31 ? logic_ : minmax; // @[AMOALU.scala 100:8:[email protected]]
assign io_out_unmasked = add ? adder_out : _T_32; // @[AMOALU.scala 105:19:[email protected]]
endmodule |
module MulDiv( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_req_ready, // @[:[email protected]]
input io_req_valid, // @[:[email protected]]
input [3:0] io_req_bits_fn, // @[:[email protected]]
input [31:0] io_req_bits_in1, // @[:[email protected]]
input [31:0] io_req_bits_in2, // @[:[email protected]]
input [4:0] io_req_bits_tag, // @[:[email protected]]
input io_kill, // @[:[email protected]]
input io_resp_ready, // @[:[email protected]]
output io_resp_valid, // @[:[email protected]]
output [31:0] io_resp_bits_data, // @[:[email protected]]
output [4:0] io_resp_bits_tag // @[:[email protected]]
);
reg [2:0] state; // @[Multiplier.scala 51:18:[email protected]]
reg [31:0] _RAND_0;
reg [4:0] req_tag; // @[Multiplier.scala 53:16:[email protected]]
reg [31:0] _RAND_1;
reg [5:0] count; // @[Multiplier.scala 54:18:[email protected]]
reg [31:0] _RAND_2;
reg neg_out; // @[Multiplier.scala 57:20:[email protected]]
reg [31:0] _RAND_3;
reg isHi; // @[Multiplier.scala 58:17:[email protected]]
reg [31:0] _RAND_4;
reg resHi; // @[Multiplier.scala 59:18:[email protected]]
reg [31:0] _RAND_5;
reg [32:0] divisor; // @[Multiplier.scala 60:20:[email protected]]
reg [63:0] _RAND_6;
reg [65:0] remainder; // @[Multiplier.scala 61:22:[email protected]]
reg [95:0] _RAND_7;
wire [3:0] _T; // @[Decode.scala 14:65:[email protected]]
wire cmdMul; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_3; // @[Decode.scala 14:65:[email protected]]
wire _T_4; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_5; // @[Decode.scala 14:65:[email protected]]
wire _T_6; // @[Decode.scala 14:121:[email protected]]
wire cmdHi; // @[Decode.scala 15:30:[email protected]]
wire [3:0] _T_9; // @[Decode.scala 14:65:[email protected]]
wire _T_10; // @[Decode.scala 14:121:[email protected]]
wire [3:0] _T_11; // @[Decode.scala 14:65:[email protected]]
wire _T_12; // @[Decode.scala 14:121:[email protected]]
wire lhsSigned; // @[Decode.scala 15:30:[email protected]]
wire _T_16; // @[Decode.scala 14:121:[email protected]]
wire rhsSigned; // @[Decode.scala 15:30:[email protected]]
wire _T_22; // @[Multiplier.scala 81:48:[email protected]]
wire lhs_sign; // @[Multiplier.scala 81:23:[email protected]]
wire [15:0] _T_26; // @[Multiplier.scala 82:43:[email protected]]
wire [15:0] _T_28; // @[Multiplier.scala 83:15:[email protected]]
wire [31:0] lhs_in; // @[Cat.scala 30:58:[email protected]]
wire _T_32; // @[Multiplier.scala 81:48:[email protected]]
wire rhs_sign; // @[Multiplier.scala 81:23:[email protected]]
wire [15:0] _T_36; // @[Multiplier.scala 82:43:[email protected]]
wire [15:0] _T_38; // @[Multiplier.scala 83:15:[email protected]]
wire [32:0] _T_39; // @[Multiplier.scala 88:29:[email protected]]
wire [32:0] subtractor; // @[Multiplier.scala 88:37:[email protected]]
wire [31:0] _T_41; // @[Multiplier.scala 89:36:[email protected]]
wire [31:0] _T_42; // @[Multiplier.scala 89:57:[email protected]]
wire [31:0] result; // @[Multiplier.scala 89:19:[email protected]]
wire [31:0] negated_remainder; // @[Multiplier.scala 90:27:[email protected]]
wire _T_44; // @[Multiplier.scala 92:39:[email protected]]
wire _T_45; // @[Multiplier.scala 93:20:[email protected]]
wire _T_46; // @[Multiplier.scala 96:18:[email protected]]
wire _T_47; // @[Multiplier.scala 101:39:[email protected]]
wire _T_48; // @[Multiplier.scala 106:39:[email protected]]
wire [32:0] _T_49; // @[Multiplier.scala 107:31:[email protected]]
wire [64:0] _T_51; // @[Cat.scala 30:58:[email protected]]
wire _T_52; // @[Multiplier.scala 108:31:[email protected]]
wire [31:0] _T_53; // @[Multiplier.scala 109:24:[email protected]]
wire [32:0] _T_54; // @[Multiplier.scala 110:23:[email protected]]
wire [32:0] _T_55; // @[Multiplier.scala 110:37:[email protected]]
wire [32:0] _T_56; // @[Multiplier.scala 111:26:[email protected]]
wire [7:0] _T_57; // @[Multiplier.scala 112:38:[email protected]]
wire [8:0] _T_58; // @[Cat.scala 30:58:[email protected]]
wire [8:0] _T_59; // @[Multiplier.scala 112:60:[email protected]]
wire [32:0] _GEN_35; // @[Multiplier.scala 112:67:[email protected]]
wire [41:0] _T_60; // @[Multiplier.scala 112:67:[email protected]]
wire [41:0] _GEN_36; // @[Multiplier.scala 112:76:[email protected]]
wire [41:0] _T_62; // @[Multiplier.scala 112:76:[email protected]]
wire [41:0] _T_63; // @[Multiplier.scala 112:76:[email protected]]
wire [23:0] _T_64; // @[Multiplier.scala 113:38:[email protected]]
wire [41:0] _T_65; // @[Cat.scala 30:58:[email protected]]
wire [65:0] _T_66; // @[Cat.scala 30:58:[email protected]]
wire _T_67; // @[Multiplier.scala 114:32:[email protected]]
wire _T_68; // @[Multiplier.scala 114:57:[email protected]]
wire _T_77; // @[Multiplier.scala 118:7:[email protected]]
wire [32:0] _T_88; // @[Multiplier.scala 120:37:[email protected]]
wire [31:0] _T_90; // @[Multiplier.scala 120:82:[email protected]]
wire [64:0] _T_91; // @[Cat.scala 30:58:[email protected]]
wire [32:0] _T_92; // @[Multiplier.scala 121:34:[email protected]]
wire [31:0] _T_93; // @[Multiplier.scala 121:67:[email protected]]
wire [65:0] _T_95; // @[Cat.scala 30:58:[email protected]]
wire [5:0] _T_97; // @[Multiplier.scala 123:20:[email protected]]
wire _T_98; // @[Multiplier.scala 124:25:[email protected]]
wire _T_100; // @[Multiplier.scala 129:39:[email protected]]
wire _T_101; // @[Multiplier.scala 133:28:[email protected]]
wire [31:0] _T_102; // @[Multiplier.scala 134:24:[email protected]]
wire [31:0] _T_103; // @[Multiplier.scala 134:45:[email protected]]
wire [31:0] _T_104; // @[Multiplier.scala 134:14:[email protected]]
wire _T_106; // @[Multiplier.scala 134:67:[email protected]]
wire [64:0] _T_108; // @[Cat.scala 30:58:[email protected]]
wire _T_109; // @[Multiplier.scala 138:17:[email protected]]
wire _T_113; // @[Multiplier.scala 146:24:[email protected]]
wire _T_116; // @[Multiplier.scala 146:30:[email protected]]
wire _T_118; // @[Multiplier.scala 159:18:[email protected]]
wire _T_119; // @[Decoupled.scala 37:37:[email protected]]
wire _T_120; // @[Multiplier.scala 161:24:[email protected]]
wire _T_121; // @[Decoupled.scala 37:37:[email protected]]
wire _T_122; // @[Multiplier.scala 165:46:[email protected]]
wire _T_129; // @[Multiplier.scala 169:46:[email protected]]
wire [32:0] _T_131; // @[Cat.scala 30:58:[email protected]]
wire [15:0] _T_140; // @[Multiplier.scala 176:69:[email protected]]
wire [15:0] loOut; // @[Multiplier.scala 176:86:[email protected]]
wire _T_149; // @[Multiplier.scala 180:27:[email protected]]
wire _T_150; // @[Multiplier.scala 180:51:[email protected]]
assign _T = io_req_bits_fn & 4'h4; // @[Decode.scala 14:65:[email protected]]
assign cmdMul = _T == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign _T_3 = io_req_bits_fn & 4'h5; // @[Decode.scala 14:65:[email protected]]
assign _T_4 = _T_3 == 4'h1; // @[Decode.scala 14:121:[email protected]]
assign _T_5 = io_req_bits_fn & 4'h2; // @[Decode.scala 14:65:[email protected]]
assign _T_6 = _T_5 == 4'h2; // @[Decode.scala 14:121:[email protected]]
assign cmdHi = _T_4 | _T_6; // @[Decode.scala 15:30:[email protected]]
assign _T_9 = io_req_bits_fn & 4'h6; // @[Decode.scala 14:65:[email protected]]
assign _T_10 = _T_9 == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign _T_11 = io_req_bits_fn & 4'h1; // @[Decode.scala 14:65:[email protected]]
assign _T_12 = _T_11 == 4'h0; // @[Decode.scala 14:121:[email protected]]
assign lhsSigned = _T_10 | _T_12; // @[Decode.scala 15:30:[email protected]]
assign _T_16 = _T_3 == 4'h4; // @[Decode.scala 14:121:[email protected]]
assign rhsSigned = _T_10 | _T_16; // @[Decode.scala 15:30:[email protected]]
assign _T_22 = io_req_bits_in1[31]; // @[Multiplier.scala 81:48:[email protected]]
assign lhs_sign = lhsSigned & _T_22; // @[Multiplier.scala 81:23:[email protected]]
assign _T_26 = io_req_bits_in1[31:16]; // @[Multiplier.scala 82:43:[email protected]]
assign _T_28 = io_req_bits_in1[15:0]; // @[Multiplier.scala 83:15:[email protected]]
assign lhs_in = {_T_26,_T_28}; // @[Cat.scala 30:58:[email protected]]
assign _T_32 = io_req_bits_in2[31]; // @[Multiplier.scala 81:48:[email protected]]
assign rhs_sign = rhsSigned & _T_32; // @[Multiplier.scala 81:23:[email protected]]
assign _T_36 = io_req_bits_in2[31:16]; // @[Multiplier.scala 82:43:[email protected]]
assign _T_38 = io_req_bits_in2[15:0]; // @[Multiplier.scala 83:15:[email protected]]
assign _T_39 = remainder[64:32]; // @[Multiplier.scala 88:29:[email protected]]
assign subtractor = _T_39 - divisor; // @[Multiplier.scala 88:37:[email protected]]
assign _T_41 = remainder[64:33]; // @[Multiplier.scala 89:36:[email protected]]
assign _T_42 = remainder[31:0]; // @[Multiplier.scala 89:57:[email protected]]
assign result = resHi ? _T_41 : _T_42; // @[Multiplier.scala 89:19:[email protected]]
assign negated_remainder = 32'h0 - result; // @[Multiplier.scala 90:27:[email protected]]
assign _T_44 = state == 3'h1; // @[Multiplier.scala 92:39:[email protected]]
assign _T_45 = remainder[31]; // @[Multiplier.scala 93:20:[email protected]]
assign _T_46 = divisor[31]; // @[Multiplier.scala 96:18:[email protected]]
assign _T_47 = state == 3'h5; // @[Multiplier.scala 101:39:[email protected]]
assign _T_48 = state == 3'h2; // @[Multiplier.scala 106:39:[email protected]]
assign _T_49 = remainder[65:33]; // @[Multiplier.scala 107:31:[email protected]]
assign _T_51 = {_T_49,_T_42}; // @[Cat.scala 30:58:[email protected]]
assign _T_52 = remainder[32]; // @[Multiplier.scala 108:31:[email protected]]
assign _T_53 = _T_51[31:0]; // @[Multiplier.scala 109:24:[email protected]]
assign _T_54 = _T_51[64:32]; // @[Multiplier.scala 110:23:[email protected]]
assign _T_55 = $signed(_T_54); // @[Multiplier.scala 110:37:[email protected]]
assign _T_56 = $signed(divisor); // @[Multiplier.scala 111:26:[email protected]]
assign _T_57 = _T_53[7:0]; // @[Multiplier.scala 112:38:[email protected]]
assign _T_58 = {_T_52,_T_57}; // @[Cat.scala 30:58:[email protected]]
assign _T_59 = $signed(_T_58); // @[Multiplier.scala 112:60:[email protected]]
assign _GEN_35 = {{24{_T_59[8]}},_T_59}; // @[Multiplier.scala 112:67:[email protected]]
assign _T_60 = $signed(_GEN_35) * $signed(_T_56); // @[Multiplier.scala 112:67:[email protected]]
assign _GEN_36 = {{9{_T_55[32]}},_T_55}; // @[Multiplier.scala 112:76:[email protected]]
assign _T_62 = $signed(_T_60) + $signed(_GEN_36); // @[Multiplier.scala 112:76:[email protected]]
assign _T_63 = $signed(_T_62); // @[Multiplier.scala 112:76:[email protected]]
assign _T_64 = _T_53[31:8]; // @[Multiplier.scala 113:38:[email protected]]
assign _T_65 = $unsigned(_T_63); // @[Cat.scala 30:58:[email protected]]
assign _T_66 = {_T_65,_T_64}; // @[Cat.scala 30:58:[email protected]]
assign _T_67 = count == 6'h2; // @[Multiplier.scala 114:32:[email protected]]
assign _T_68 = _T_67 & neg_out; // @[Multiplier.scala 114:57:[email protected]]
assign _T_77 = isHi == 1'h0; // @[Multiplier.scala 118:7:[email protected]]
assign _T_88 = _T_66[64:32]; // @[Multiplier.scala 120:37:[email protected]]
assign _T_90 = _T_66[31:0]; // @[Multiplier.scala 120:82:[email protected]]
assign _T_91 = {_T_88,_T_90}; // @[Cat.scala 30:58:[email protected]]
assign _T_92 = _T_91[64:32]; // @[Multiplier.scala 121:34:[email protected]]
assign _T_93 = _T_91[31:0]; // @[Multiplier.scala 121:67:[email protected]]
assign _T_95 = {_T_92,_T_68,_T_93}; // @[Cat.scala 30:58:[email protected]]
assign _T_97 = count + 6'h1; // @[Multiplier.scala 123:20:[email protected]]
assign _T_98 = count == 6'h3; // @[Multiplier.scala 124:25:[email protected]]
assign _T_100 = state == 3'h3; // @[Multiplier.scala 129:39:[email protected]]
assign _T_101 = subtractor[32]; // @[Multiplier.scala 133:28:[email protected]]
assign _T_102 = remainder[63:32]; // @[Multiplier.scala 134:24:[email protected]]
assign _T_103 = subtractor[31:0]; // @[Multiplier.scala 134:45:[email protected]]
assign _T_104 = _T_101 ? _T_102 : _T_103; // @[Multiplier.scala 134:14:[email protected]]
assign _T_106 = _T_101 == 1'h0; // @[Multiplier.scala 134:67:[email protected]]
assign _T_108 = {_T_104,_T_42,_T_106}; // @[Cat.scala 30:58:[email protected]]
assign _T_109 = count == 6'h20; // @[Multiplier.scala 138:17:[email protected]]
assign _T_113 = count == 6'h0; // @[Multiplier.scala 146:24:[email protected]]
assign _T_116 = _T_113 & _T_106; // @[Multiplier.scala 146:30:[email protected]]
assign _T_118 = _T_116 & _T_77; // @[Multiplier.scala 159:18:[email protected]]
assign _T_119 = io_resp_ready & io_resp_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_120 = _T_119 | io_kill; // @[Multiplier.scala 161:24:[email protected]]
assign _T_121 = io_req_ready & io_req_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_122 = lhs_sign | rhs_sign; // @[Multiplier.scala 165:46:[email protected]]
assign _T_129 = lhs_sign != rhs_sign; // @[Multiplier.scala 169:46:[email protected]]
assign _T_131 = {rhs_sign,_T_36,_T_38}; // @[Cat.scala 30:58:[email protected]]
assign _T_140 = result[31:16]; // @[Multiplier.scala 176:69:[email protected]]
assign loOut = result[15:0]; // @[Multiplier.scala 176:86:[email protected]]
assign _T_149 = state == 3'h6; // @[Multiplier.scala 180:27:[email protected]]
assign _T_150 = state == 3'h7; // @[Multiplier.scala 180:51:[email protected]]
assign io_req_ready = state == 3'h0; // @[Multiplier.scala 181:16:[email protected]]
assign io_resp_valid = _T_149 | _T_150; // @[Multiplier.scala 180:17:[email protected]]
assign io_resp_bits_data = {_T_140,loOut}; // @[Multiplier.scala 179:21:[email protected]]
assign io_resp_bits_tag = req_tag; // @[Multiplier.scala 178:16:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
state = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
req_tag = _RAND_1[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
count = _RAND_2[5:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
neg_out = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
isHi = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
resHi = _RAND_5[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {2{`RANDOM}};
divisor = _RAND_6[32:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {3{`RANDOM}};
remainder = _RAND_7[65:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
state <= 3'h0;
end else begin
if (_T_121) begin
if (cmdMul) begin
state <= 3'h2;
end else begin
if (_T_122) begin
state <= 3'h1;
end else begin
state <= 3'h3;
end
end
end else begin
if (_T_120) begin
state <= 3'h0;
end else begin
if (_T_100) begin
if (_T_109) begin
if (neg_out) begin
state <= 3'h5;
end else begin
state <= 3'h7;
end
end else begin
if (_T_48) begin
if (_T_98) begin
state <= 3'h6;
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end
end else begin
if (_T_48) begin
if (_T_98) begin
state <= 3'h6;
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end else begin
if (_T_47) begin
state <= 3'h7;
end else begin
if (_T_44) begin
state <= 3'h3;
end
end
end
end
end
end
end
if (_T_121) begin
req_tag <= io_req_bits_tag;
end
if (_T_121) begin
count <= 6'h0;
end else begin
if (_T_100) begin
count <= _T_97;
end else begin
if (_T_48) begin
count <= _T_97;
end
end
end
if (_T_121) begin
if (cmdHi) begin
neg_out <= lhs_sign;
end else begin
neg_out <= _T_129;
end
end else begin
if (_T_100) begin
if (_T_118) begin
neg_out <= 1'h0;
end
end
end
if (_T_121) begin
isHi <= cmdHi;
end
if (_T_121) begin
resHi <= 1'h0;
end else begin
if (_T_100) begin
if (_T_109) begin
resHi <= isHi;
end else begin
if (_T_48) begin
if (_T_98) begin
resHi <= isHi;
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end
end else begin
if (_T_48) begin
if (_T_98) begin
resHi <= isHi;
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end else begin
if (_T_47) begin
resHi <= 1'h0;
end
end
end
end
if (_T_121) begin
divisor <= _T_131;
end else begin
if (_T_44) begin
if (_T_46) begin
divisor <= subtractor;
end
end
end
if (_T_121) begin
remainder <= {{34'd0}, lhs_in};
end else begin
if (_T_100) begin
remainder <= {{1'd0}, _T_108};
end else begin
if (_T_48) begin
remainder <= _T_95;
end else begin
if (_T_47) begin
remainder <= {{34'd0}, negated_remainder};
end else begin
if (_T_44) begin
if (_T_45) begin
remainder <= {{34'd0}, negated_remainder};
end
end
end
end
end
end
end
endmodule |
module Queue_41( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [1:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output io_deq_bits_sink, // @[:[email protected]]
output io_deq_bits_denied, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [1:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [1:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [1:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [2:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [4:0] _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire [4:0] _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [4:0] _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_sink [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire _T_sink__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_sink__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_denied [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire _T_denied__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_denied__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = 2'h0;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_sink__T_18_addr = value_1;
assign _T_sink__T_18_data = _T_sink[_T_sink__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_sink__T_10_data = 1'h0;
assign _T_sink__T_10_addr = value;
assign _T_sink__T_10_mask = 1'h1;
assign _T_sink__T_10_en = io_enq_ready & io_enq_valid;
assign _T_denied__T_18_addr = value_1;
assign _T_denied__T_18_data = _T_denied[_T_denied__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_denied__T_10_data = 1'h0;
assign _T_denied__T_10_addr = value;
assign _T_denied__T_10_mask = 1'h1;
assign _T_denied__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = 1'h0;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_sink = _T_sink__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_denied = _T_denied__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[1:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[4:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_sink[initvar] = _RAND_4[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_denied[initvar] = _RAND_5[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_sink__T_10_en & _T_sink__T_10_mask) begin
_T_sink[_T_sink__T_10_addr] <= _T_sink__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_denied__T_10_en & _T_denied__T_10_mask) begin
_T_denied[_T_denied__T_10_addr] <= _T_denied__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule |
module ScratchpadSlavePort( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output auto_in_a_ready, // @[:[email protected]]
input auto_in_a_valid, // @[:[email protected]]
input [2:0] auto_in_a_bits_opcode, // @[:[email protected]]
input [2:0] auto_in_a_bits_param, // @[:[email protected]]
input [1:0] auto_in_a_bits_size, // @[:[email protected]]
input [10:0] auto_in_a_bits_source, // @[:[email protected]]
input [31:0] auto_in_a_bits_address, // @[:[email protected]]
input [3:0] auto_in_a_bits_mask, // @[:[email protected]]
input [31:0] auto_in_a_bits_data, // @[:[email protected]]
input auto_in_d_ready, // @[:[email protected]]
output auto_in_d_valid, // @[:[email protected]]
output [2:0] auto_in_d_bits_opcode, // @[:[email protected]]
output [1:0] auto_in_d_bits_size, // @[:[email protected]]
output [10:0] auto_in_d_bits_source, // @[:[email protected]]
output [31:0] auto_in_d_bits_data, // @[:[email protected]]
input io_dmem_req_ready, // @[:[email protected]]
output io_dmem_req_valid, // @[:[email protected]]
output [31:0] io_dmem_req_bits_addr, // @[:[email protected]]
output [4:0] io_dmem_req_bits_cmd, // @[:[email protected]]
output [1:0] io_dmem_req_bits_size, // @[:[email protected]]
output io_dmem_s1_kill, // @[:[email protected]]
output [31:0] io_dmem_s1_data_data, // @[:[email protected]]
output [3:0] io_dmem_s1_data_mask, // @[:[email protected]]
input io_dmem_s2_nack, // @[:[email protected]]
input io_dmem_resp_valid, // @[:[email protected]]
input [31:0] io_dmem_resp_bits_data_raw // @[:[email protected]]
);
reg [2:0] state; // @[ScratchpadSlavePort.scala 46:20:[email protected]]
reg [31:0] _RAND_0;
wire _T; // @[ScratchpadSlavePort.scala 48:17:[email protected]]
wire _T_51; // @[ScratchpadSlavePort.scala 98:50:[email protected]]
wire tl_in_d_valid; // @[ScratchpadSlavePort.scala 98:41:[email protected]]
wire _T_1; // @[Decoupled.scala 37:37:[email protected]]
wire _T_6; // @[ScratchpadSlavePort.scala 86:23:[email protected]]
wire _T_7; // @[ScratchpadSlavePort.scala 86:44:[email protected]]
wire _T_8; // @[ScratchpadSlavePort.scala 86:56:[email protected]]
wire _T_9; // @[ScratchpadSlavePort.scala 86:78:[email protected]]
wire ready; // @[ScratchpadSlavePort.scala 86:35:[email protected]]
wire _T_10; // @[ScratchpadSlavePort.scala 87:38:[email protected]]
wire _T_11; // @[ScratchpadSlavePort.scala 87:57:[email protected]]
wire dmem_req_valid; // @[ScratchpadSlavePort.scala 87:48:[email protected]]
wire _T_2; // @[ScratchpadSlavePort.scala 52:26:[email protected]]
reg [2:0] acq_opcode; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_1;
reg [2:0] acq_param; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_2;
reg [1:0] acq_size; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_3;
reg [10:0] acq_source; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] acq_address; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_5;
reg [3:0] acq_mask; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_6;
reg [31:0] acq_data; // @[ScratchpadSlavePort.scala 54:18:[email protected]]
reg [31:0] _RAND_7;
wire tl_in_a_ready; // @[ScratchpadSlavePort.scala 91:40:[email protected]]
wire _T_3; // @[Decoupled.scala 37:37:[email protected]]
wire ready_likely; // @[ScratchpadSlavePort.scala 85:42:[email protected]]
wire _T_13; // @[ScratchpadSlavePort.scala 88:48:[email protected]]
wire [2:0] _T_17_opcode; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
wire [2:0] _T_17_param; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
wire _T_21; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_22; // @[Mux.scala 69:16:[email protected]]
wire _T_23; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_24; // @[Mux.scala 69:16:[email protected]]
wire _T_25; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_26; // @[Mux.scala 69:16:[email protected]]
wire _T_27; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_28; // @[Mux.scala 69:16:[email protected]]
wire _T_29; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_30; // @[Mux.scala 69:16:[email protected]]
wire [2:0] _T_33; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_35; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_37; // @[Mux.scala 69:16:[email protected]]
wire [3:0] _T_39; // @[Mux.scala 69:16:[email protected]]
wire _T_42; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_43; // @[Mux.scala 69:16:[email protected]]
wire _T_44; // @[Mux.scala 69:19:[email protected]]
wire [3:0] _T_45; // @[Mux.scala 69:16:[email protected]]
wire _T_46; // @[Mux.scala 69:19:[email protected]]
wire [4:0] _T_47; // @[Mux.scala 69:16:[email protected]]
wire _T_48; // @[Mux.scala 69:19:[email protected]]
wire _T_53; // @[package.scala 15:47:[email protected]]
wire _T_54; // @[package.scala 15:47:[email protected]]
wire _T_55; // @[package.scala 15:62:[email protected]]
reg [31:0] _T_60; // @[Reg.scala 15:16:[email protected]]
reg [31:0] _RAND_8;
assign _T = state == 3'h1; // @[ScratchpadSlavePort.scala 48:17:[email protected]]
assign _T_51 = state == 3'h4; // @[ScratchpadSlavePort.scala 98:50:[email protected]]
assign tl_in_d_valid = io_dmem_resp_valid | _T_51; // @[ScratchpadSlavePort.scala 98:41:[email protected]]
assign _T_1 = auto_in_d_ready & tl_in_d_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_6 = state == 3'h0; // @[ScratchpadSlavePort.scala 86:23:[email protected]]
assign _T_7 = state == 3'h2; // @[ScratchpadSlavePort.scala 86:44:[email protected]]
assign _T_8 = _T_7 & io_dmem_resp_valid; // @[ScratchpadSlavePort.scala 86:56:[email protected]]
assign _T_9 = _T_8 & auto_in_d_ready; // @[ScratchpadSlavePort.scala 86:78:[email protected]]
assign ready = _T_6 | _T_9; // @[ScratchpadSlavePort.scala 86:35:[email protected]]
assign _T_10 = auto_in_a_valid & ready; // @[ScratchpadSlavePort.scala 87:38:[email protected]]
assign _T_11 = state == 3'h3; // @[ScratchpadSlavePort.scala 87:57:[email protected]]
assign dmem_req_valid = _T_10 | _T_11; // @[ScratchpadSlavePort.scala 87:48:[email protected]]
assign _T_2 = dmem_req_valid & io_dmem_req_ready; // @[ScratchpadSlavePort.scala 52:26:[email protected]]
assign tl_in_a_ready = io_dmem_req_ready & ready; // @[ScratchpadSlavePort.scala 91:40:[email protected]]
assign _T_3 = tl_in_a_ready & auto_in_a_valid; // @[Decoupled.scala 37:37:[email protected]]
assign ready_likely = _T_6 | _T_7; // @[ScratchpadSlavePort.scala 85:42:[email protected]]
assign _T_13 = auto_in_a_valid & ready_likely; // @[ScratchpadSlavePort.scala 88:48:[email protected]]
assign _T_17_opcode = _T_11 ? acq_opcode : auto_in_a_bits_opcode; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
assign _T_17_param = _T_11 ? acq_param : auto_in_a_bits_param; // @[ScratchpadSlavePort.scala 92:41:[email protected]]
assign _T_21 = 3'h4 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_22 = _T_21 ? 4'h8 : 4'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_23 = 3'h3 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_24 = _T_23 ? 4'hf : _T_22; // @[Mux.scala 69:16:[email protected]]
assign _T_25 = 3'h2 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_26 = _T_25 ? 4'he : _T_24; // @[Mux.scala 69:16:[email protected]]
assign _T_27 = 3'h1 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_28 = _T_27 ? 4'hd : _T_26; // @[Mux.scala 69:16:[email protected]]
assign _T_29 = 3'h0 == _T_17_param; // @[Mux.scala 69:19:[email protected]]
assign _T_30 = _T_29 ? 4'hc : _T_28; // @[Mux.scala 69:16:[email protected]]
assign _T_33 = _T_23 ? 3'h4 : 3'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_35 = _T_25 ? 4'hb : {{1'd0}, _T_33}; // @[Mux.scala 69:16:[email protected]]
assign _T_37 = _T_27 ? 4'ha : _T_35; // @[Mux.scala 69:16:[email protected]]
assign _T_39 = _T_29 ? 4'h9 : _T_37; // @[Mux.scala 69:16:[email protected]]
assign _T_42 = 3'h3 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_43 = _T_42 ? _T_39 : 4'h0; // @[Mux.scala 69:16:[email protected]]
assign _T_44 = 3'h2 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_45 = _T_44 ? _T_30 : _T_43; // @[Mux.scala 69:16:[email protected]]
assign _T_46 = 3'h1 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_47 = _T_46 ? 5'h11 : {{1'd0}, _T_45}; // @[Mux.scala 69:16:[email protected]]
assign _T_48 = 3'h0 == _T_17_opcode; // @[Mux.scala 69:19:[email protected]]
assign _T_53 = acq_opcode == 3'h0; // @[package.scala 15:47:[email protected]]
assign _T_54 = acq_opcode == 3'h1; // @[package.scala 15:47:[email protected]]
assign _T_55 = _T_53 | _T_54; // @[package.scala 15:62:[email protected]]
assign auto_in_a_ready = io_dmem_req_ready & ready; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_valid = io_dmem_resp_valid | _T_51; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_opcode = _T_55 ? 3'h0 : 3'h1; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_size = acq_size; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_source = acq_source; // @[LazyModule.scala 173:31:[email protected]]
assign auto_in_d_bits_data = _T_7 ? io_dmem_resp_bits_data_raw : _T_60; // @[LazyModule.scala 173:31:[email protected]]
assign io_dmem_req_valid = _T_13 | _T_11; // @[ScratchpadSlavePort.scala 90:23:[email protected]]
assign io_dmem_req_bits_addr = _T_11 ? acq_address : auto_in_a_bits_address; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_req_bits_cmd = _T_48 ? 5'h1 : _T_47; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_req_bits_size = _T_11 ? acq_size : auto_in_a_bits_size; // @[ScratchpadSlavePort.scala 92:22:[email protected]]
assign io_dmem_s1_kill = state != 3'h1; // @[ScratchpadSlavePort.scala 95:21:[email protected]]
assign io_dmem_s1_data_data = acq_data; // @[ScratchpadSlavePort.scala 93:26:[email protected]]
assign io_dmem_s1_data_mask = acq_mask; // @[ScratchpadSlavePort.scala 94:26:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
state = _RAND_0[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
acq_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
acq_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
acq_size = _RAND_3[1:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
acq_source = _RAND_4[10:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
acq_address = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
acq_mask = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
acq_data = _RAND_7[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_60 = _RAND_8[31:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
state <= 3'h0;
end else begin
if (_T_2) begin
state <= 3'h1;
end else begin
if (io_dmem_s2_nack) begin
state <= 3'h3;
end else begin
if (_T_1) begin
state <= 3'h0;
end else begin
if (io_dmem_resp_valid) begin
state <= 3'h4;
end else begin
if (_T) begin
state <= 3'h2;
end
end
end
end
end
end
if (_T_3) begin
acq_opcode <= auto_in_a_bits_opcode;
end
if (_T_3) begin
acq_param <= auto_in_a_bits_param;
end
if (_T_3) begin
acq_size <= auto_in_a_bits_size;
end
if (_T_3) begin
acq_source <= auto_in_a_bits_source;
end
if (_T_3) begin
acq_address <= auto_in_a_bits_address;
end
if (_T_3) begin
acq_mask <= auto_in_a_bits_mask;
end
if (_T_3) begin
acq_data <= auto_in_a_bits_data;
end
if (_T_7) begin
_T_60 <= io_dmem_resp_bits_data_raw;
end
end
endmodule |
module IntXbar_4( // @[:[email protected]]
input auto_int_in_2_0, // @[:[email protected]]
input auto_int_in_1_0, // @[:[email protected]]
input auto_int_in_1_1, // @[:[email protected]]
input auto_int_in_0_0, // @[:[email protected]]
output auto_int_out_0, // @[:[email protected]]
output auto_int_out_1, // @[:[email protected]]
output auto_int_out_2, // @[:[email protected]]
output auto_int_out_3 // @[:[email protected]]
);
assign auto_int_out_0 = auto_int_in_0_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_1 = auto_int_in_1_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_2 = auto_int_in_1_1; // @[LazyModule.scala 173:49:[email protected]]
assign auto_int_out_3 = auto_int_in_2_0; // @[LazyModule.scala 173:49:[email protected]]
endmodule |
module IntSyncCrossingSink_2( // @[:[email protected]]
input auto_in_sync_0, // @[:[email protected]]
output auto_out_0 // @[:[email protected]]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:[email protected]]
endmodule |
module SynchronizerShiftReg_w1_d3( // @[:[email protected]]
input clock, // @[:[email protected]]
input io_d, // @[:[email protected]]
output io_q // @[:[email protected]]
);
reg sync_0; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_0;
reg sync_1; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_1;
reg sync_2; // @[ShiftReg.scala 114:16:[email protected]]
reg [31:0] _RAND_2;
assign io_q = sync_0; // @[ShiftReg.scala 123:8:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
sync_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
sync_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
sync_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
sync_0 <= sync_1;
sync_1 <= sync_2;
sync_2 <= io_d;
end
endmodule |
module HellaCacheArbiter( // @[:[email protected]]
input clock, // @[:[email protected]]
output io_requestor_0_req_ready, // @[:[email protected]]
input io_requestor_0_req_valid, // @[:[email protected]]
input [31:0] io_requestor_0_req_bits_addr, // @[:[email protected]]
input [6:0] io_requestor_0_req_bits_tag, // @[:[email protected]]
input [4:0] io_requestor_0_req_bits_cmd, // @[:[email protected]]
input [1:0] io_requestor_0_req_bits_size, // @[:[email protected]]
input io_requestor_0_req_bits_signed, // @[:[email protected]]
input io_requestor_0_s1_kill, // @[:[email protected]]
input [31:0] io_requestor_0_s1_data_data, // @[:[email protected]]
output io_requestor_0_s2_nack, // @[:[email protected]]
output io_requestor_0_resp_valid, // @[:[email protected]]
output [6:0] io_requestor_0_resp_bits_tag, // @[:[email protected]]
output [31:0] io_requestor_0_resp_bits_data, // @[:[email protected]]
output io_requestor_0_resp_bits_replay, // @[:[email protected]]
output io_requestor_0_resp_bits_has_data, // @[:[email protected]]
output [31:0] io_requestor_0_resp_bits_data_word_bypass, // @[:[email protected]]
output io_requestor_0_replay_next, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ma_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ma_st, // @[:[email protected]]
output io_requestor_0_s2_xcpt_pf_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_pf_st, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ae_ld, // @[:[email protected]]
output io_requestor_0_s2_xcpt_ae_st, // @[:[email protected]]
output io_requestor_0_ordered, // @[:[email protected]]
output io_requestor_0_perf_grant, // @[:[email protected]]
output io_requestor_1_req_ready, // @[:[email protected]]
input io_requestor_1_req_valid, // @[:[email protected]]
input [31:0] io_requestor_1_req_bits_addr, // @[:[email protected]]
input [4:0] io_requestor_1_req_bits_cmd, // @[:[email protected]]
input [1:0] io_requestor_1_req_bits_size, // @[:[email protected]]
input io_requestor_1_s1_kill, // @[:[email protected]]
input [31:0] io_requestor_1_s1_data_data, // @[:[email protected]]
input [3:0] io_requestor_1_s1_data_mask, // @[:[email protected]]
output io_requestor_1_s2_nack, // @[:[email protected]]
output io_requestor_1_resp_valid, // @[:[email protected]]
output [31:0] io_requestor_1_resp_bits_data_raw, // @[:[email protected]]
input io_mem_req_ready, // @[:[email protected]]
output io_mem_req_valid, // @[:[email protected]]
output [31:0] io_mem_req_bits_addr, // @[:[email protected]]
output [6:0] io_mem_req_bits_tag, // @[:[email protected]]
output [4:0] io_mem_req_bits_cmd, // @[:[email protected]]
output [1:0] io_mem_req_bits_size, // @[:[email protected]]
output io_mem_req_bits_signed, // @[:[email protected]]
output io_mem_req_bits_phys, // @[:[email protected]]
output io_mem_s1_kill, // @[:[email protected]]
output [31:0] io_mem_s1_data_data, // @[:[email protected]]
output [3:0] io_mem_s1_data_mask, // @[:[email protected]]
input io_mem_s2_nack, // @[:[email protected]]
input io_mem_resp_valid, // @[:[email protected]]
input [6:0] io_mem_resp_bits_tag, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data, // @[:[email protected]]
input io_mem_resp_bits_replay, // @[:[email protected]]
input io_mem_resp_bits_has_data, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data_word_bypass, // @[:[email protected]]
input [31:0] io_mem_resp_bits_data_raw, // @[:[email protected]]
input io_mem_replay_next, // @[:[email protected]]
input io_mem_s2_xcpt_ma_ld, // @[:[email protected]]
input io_mem_s2_xcpt_ma_st, // @[:[email protected]]
input io_mem_s2_xcpt_pf_ld, // @[:[email protected]]
input io_mem_s2_xcpt_pf_st, // @[:[email protected]]
input io_mem_s2_xcpt_ae_ld, // @[:[email protected]]
input io_mem_s2_xcpt_ae_st, // @[:[email protected]]
input io_mem_ordered, // @[:[email protected]]
input io_mem_perf_grant // @[:[email protected]]
);
reg _T; // @[HellaCacheArbiter.scala 19:20:[email protected]]
reg [31:0] _RAND_0;
reg _T_1; // @[HellaCacheArbiter.scala 20:20:[email protected]]
reg [31:0] _RAND_1;
wire _T_4; // @[HellaCacheArbiter.scala 27:67:[email protected]]
wire [7:0] _T_7; // @[Cat.scala 30:58:[email protected]]
wire [7:0] _GEN_1; // @[HellaCacheArbiter.scala 49:26:[email protected]]
wire _T_8; // @[HellaCacheArbiter.scala 50:21:[email protected]]
wire _T_9; // @[HellaCacheArbiter.scala 51:21:[email protected]]
wire _T_10; // @[HellaCacheArbiter.scala 59:41:[email protected]]
wire _T_11; // @[HellaCacheArbiter.scala 59:57:[email protected]]
wire [5:0] _T_15; // @[HellaCacheArbiter.scala 70:45:[email protected]]
assign _T_4 = io_requestor_0_req_valid == 1'h0; // @[HellaCacheArbiter.scala 27:67:[email protected]]
assign _T_7 = {io_requestor_0_req_bits_tag,1'h0}; // @[Cat.scala 30:58:[email protected]]
assign _GEN_1 = io_requestor_0_req_valid ? _T_7 : 8'h1; // @[HellaCacheArbiter.scala 49:26:[email protected]]
assign _T_8 = _T == 1'h0; // @[HellaCacheArbiter.scala 50:21:[email protected]]
assign _T_9 = _T_1 == 1'h0; // @[HellaCacheArbiter.scala 51:21:[email protected]]
assign _T_10 = io_mem_resp_bits_tag[0]; // @[HellaCacheArbiter.scala 59:41:[email protected]]
assign _T_11 = _T_10 == 1'h0; // @[HellaCacheArbiter.scala 59:57:[email protected]]
assign _T_15 = io_mem_resp_bits_tag[6:1]; // @[HellaCacheArbiter.scala 70:45:[email protected]]
assign io_requestor_0_req_ready = io_mem_req_ready; // @[HellaCacheArbiter.scala 25:31:[email protected]]
assign io_requestor_0_s2_nack = io_mem_s2_nack & _T_9; // @[HellaCacheArbiter.scala 64:31:[email protected]]
assign io_requestor_0_resp_valid = io_mem_resp_valid & _T_11; // @[HellaCacheArbiter.scala 60:18:[email protected]]
assign io_requestor_0_resp_bits_tag = {{1'd0}, _T_15}; // @[HellaCacheArbiter.scala 69:17:[email protected] HellaCacheArbiter.scala 70:21:[email protected]]
assign io_requestor_0_resp_bits_data = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_replay = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_has_data = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_resp_bits_data_word_bypass = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_requestor_0_replay_next = io_mem_replay_next; // @[HellaCacheArbiter.scala 72:35:[email protected]]
assign io_requestor_0_s2_xcpt_ma_ld = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ma_st = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_pf_ld = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_pf_st = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ae_ld = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_s2_xcpt_ae_st = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala 61:31:[email protected]]
assign io_requestor_0_ordered = io_mem_ordered; // @[HellaCacheArbiter.scala 62:31:[email protected]]
assign io_requestor_0_perf_grant = io_mem_perf_grant; // @[HellaCacheArbiter.scala 63:28:[email protected]]
assign io_requestor_1_req_ready = io_requestor_0_req_ready & _T_4; // @[HellaCacheArbiter.scala 27:33:[email protected]]
assign io_requestor_1_s2_nack = io_mem_s2_nack & _T_1; // @[HellaCacheArbiter.scala 64:31:[email protected]]
assign io_requestor_1_resp_valid = io_mem_resp_valid & _T_10; // @[HellaCacheArbiter.scala 60:18:[email protected]]
assign io_requestor_1_resp_bits_data_raw = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala 69:17:[email protected]]
assign io_mem_req_valid = io_requestor_0_req_valid | io_requestor_1_req_valid; // @[HellaCacheArbiter.scala 24:22:[email protected]]
assign io_mem_req_bits_addr = io_requestor_0_req_valid ? io_requestor_0_req_bits_addr : io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_tag = _GEN_1[6:0]; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 33:29:[email protected] HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 33:29:[email protected]]
assign io_mem_req_bits_cmd = io_requestor_0_req_valid ? io_requestor_0_req_bits_cmd : io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_size = io_requestor_0_req_valid ? io_requestor_0_req_bits_size : io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_signed = io_requestor_0_req_valid ? io_requestor_0_req_bits_signed : 1'h0; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_req_bits_phys = io_requestor_0_req_valid ? 1'h0 : 1'h1; // @[HellaCacheArbiter.scala 32:25:[email protected] HellaCacheArbiter.scala 32:25:[email protected]]
assign io_mem_s1_kill = _T_8 ? io_requestor_0_s1_kill : io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala 37:24:[email protected] HellaCacheArbiter.scala 37:24:[email protected]]
assign io_mem_s1_data_data = _T_8 ? io_requestor_0_s1_data_data : io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala 38:24:[email protected] HellaCacheArbiter.scala 38:24:[email protected]]
assign io_mem_s1_data_mask = _T_8 ? 4'h0 : io_requestor_1_s1_data_mask; // @[HellaCacheArbiter.scala 38:24:[email protected] HellaCacheArbiter.scala 38:24:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (io_requestor_0_req_valid) begin
_T <= 1'h0;
end else begin
_T <= 1'h1;
end
_T_1 <= _T;
end
endmodule |
module Queue_38( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [3:0] io_enq_bits_size, // @[:[email protected]]
input io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_corrupt, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [3:0] io_deq_bits_size, // @[:[email protected]]
output io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_corrupt // @[:[email protected]]
);
reg [2:0] _T_opcode [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_0;
wire [2:0] _T_opcode__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_opcode__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [2:0] _T_param [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_1;
wire [2:0] _T_param__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [2:0] _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_param__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_size [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_2;
wire [3:0] _T_size__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_size__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_source [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_3;
wire _T_source__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_source__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_address [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_4;
wire [31:0] _T_address__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_address__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [3:0] _T_mask [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_5;
wire [3:0] _T_mask__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [3:0] _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_mask__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _T_data [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_6;
wire [31:0] _T_data__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire [31:0] _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_data__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg _T_corrupt [0:1]; // @[Decoupled.scala 215:24:[email protected]]
reg [31:0] _RAND_7;
wire _T_corrupt__T_18_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_18_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_addr; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_mask; // @[Decoupled.scala 215:24:[email protected]]
wire _T_corrupt__T_10_en; // @[Decoupled.scala 215:24:[email protected]]
reg value; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_8;
reg value_1; // @[Counter.scala 26:33:[email protected]]
reg [31:0] _RAND_9;
reg _T_1; // @[Decoupled.scala 218:35:[email protected]]
reg [31:0] _RAND_10;
wire _T_2; // @[Decoupled.scala 220:41:[email protected]]
wire _T_3; // @[Decoupled.scala 221:36:[email protected]]
wire _T_4; // @[Decoupled.scala 221:33:[email protected]]
wire _T_5; // @[Decoupled.scala 222:32:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_8; // @[Decoupled.scala 37:37:[email protected]]
wire _T_12; // @[Counter.scala 35:22:[email protected]]
wire _T_14; // @[Counter.scala 35:22:[email protected]]
wire _T_15; // @[Decoupled.scala 233:16:[email protected]]
assign _T_opcode__T_18_addr = value_1;
assign _T_opcode__T_18_data = _T_opcode[_T_opcode__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_opcode__T_10_data = io_enq_bits_opcode;
assign _T_opcode__T_10_addr = value;
assign _T_opcode__T_10_mask = 1'h1;
assign _T_opcode__T_10_en = io_enq_ready & io_enq_valid;
assign _T_param__T_18_addr = value_1;
assign _T_param__T_18_data = _T_param[_T_param__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_param__T_10_data = io_enq_bits_param;
assign _T_param__T_10_addr = value;
assign _T_param__T_10_mask = 1'h1;
assign _T_param__T_10_en = io_enq_ready & io_enq_valid;
assign _T_size__T_18_addr = value_1;
assign _T_size__T_18_data = _T_size[_T_size__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_size__T_10_data = io_enq_bits_size;
assign _T_size__T_10_addr = value;
assign _T_size__T_10_mask = 1'h1;
assign _T_size__T_10_en = io_enq_ready & io_enq_valid;
assign _T_source__T_18_addr = value_1;
assign _T_source__T_18_data = _T_source[_T_source__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_source__T_10_data = io_enq_bits_source;
assign _T_source__T_10_addr = value;
assign _T_source__T_10_mask = 1'h1;
assign _T_source__T_10_en = io_enq_ready & io_enq_valid;
assign _T_address__T_18_addr = value_1;
assign _T_address__T_18_data = _T_address[_T_address__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_address__T_10_data = io_enq_bits_address;
assign _T_address__T_10_addr = value;
assign _T_address__T_10_mask = 1'h1;
assign _T_address__T_10_en = io_enq_ready & io_enq_valid;
assign _T_mask__T_18_addr = value_1;
assign _T_mask__T_18_data = _T_mask[_T_mask__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_mask__T_10_data = io_enq_bits_mask;
assign _T_mask__T_10_addr = value;
assign _T_mask__T_10_mask = 1'h1;
assign _T_mask__T_10_en = io_enq_ready & io_enq_valid;
assign _T_data__T_18_addr = value_1;
assign _T_data__T_18_data = _T_data[_T_data__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_data__T_10_data = io_enq_bits_data;
assign _T_data__T_10_addr = value;
assign _T_data__T_10_mask = 1'h1;
assign _T_data__T_10_en = io_enq_ready & io_enq_valid;
assign _T_corrupt__T_18_addr = value_1;
assign _T_corrupt__T_18_data = _T_corrupt[_T_corrupt__T_18_addr]; // @[Decoupled.scala 215:24:[email protected]]
assign _T_corrupt__T_10_data = io_enq_bits_corrupt;
assign _T_corrupt__T_10_addr = value;
assign _T_corrupt__T_10_mask = 1'h1;
assign _T_corrupt__T_10_en = io_enq_ready & io_enq_valid;
assign _T_2 = value == value_1; // @[Decoupled.scala 220:41:[email protected]]
assign _T_3 = _T_1 == 1'h0; // @[Decoupled.scala 221:36:[email protected]]
assign _T_4 = _T_2 & _T_3; // @[Decoupled.scala 221:33:[email protected]]
assign _T_5 = _T_2 & _T_1; // @[Decoupled.scala 222:32:[email protected]]
assign _T_6 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_8 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_12 = value + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_14 = value_1 + 1'h1; // @[Counter.scala 35:22:[email protected]]
assign _T_15 = _T_6 != _T_8; // @[Decoupled.scala 233:16:[email protected]]
assign io_enq_ready = _T_5 == 1'h0; // @[Decoupled.scala 238:16:[email protected]]
assign io_deq_valid = _T_4 == 1'h0; // @[Decoupled.scala 237:16:[email protected]]
assign io_deq_bits_opcode = _T_opcode__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_param = _T_param__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_size = _T_size__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_source = _T_source__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_address = _T_address__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_mask = _T_mask__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_data = _T_data__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
assign io_deq_bits_corrupt = _T_corrupt__T_18_data; // @[Decoupled.scala 239:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
_RAND_0 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_opcode[initvar] = _RAND_0[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_1 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_param[initvar] = _RAND_1[2:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_2 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_size[initvar] = _RAND_2[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_3 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_source[initvar] = _RAND_3[0:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_4 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_address[initvar] = _RAND_4[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_5 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_mask[initvar] = _RAND_5[3:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_6 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_data[initvar] = _RAND_6[31:0];
`endif // RANDOMIZE_MEM_INIT
_RAND_7 = {1{`RANDOM}};
`ifdef RANDOMIZE_MEM_INIT
for (initvar = 0; initvar < 2; initvar = initvar+1)
_T_corrupt[initvar] = _RAND_7[0:0];
`endif // RANDOMIZE_MEM_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
value = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
value_1 = _RAND_9[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_1 = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if(_T_opcode__T_10_en & _T_opcode__T_10_mask) begin
_T_opcode[_T_opcode__T_10_addr] <= _T_opcode__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_param__T_10_en & _T_param__T_10_mask) begin
_T_param[_T_param__T_10_addr] <= _T_param__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_size__T_10_en & _T_size__T_10_mask) begin
_T_size[_T_size__T_10_addr] <= _T_size__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_source__T_10_en & _T_source__T_10_mask) begin
_T_source[_T_source__T_10_addr] <= _T_source__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_address__T_10_en & _T_address__T_10_mask) begin
_T_address[_T_address__T_10_addr] <= _T_address__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_mask__T_10_en & _T_mask__T_10_mask) begin
_T_mask[_T_mask__T_10_addr] <= _T_mask__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_data__T_10_en & _T_data__T_10_mask) begin
_T_data[_T_data__T_10_addr] <= _T_data__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if(_T_corrupt__T_10_en & _T_corrupt__T_10_mask) begin
_T_corrupt[_T_corrupt__T_10_addr] <= _T_corrupt__T_10_data; // @[Decoupled.scala 215:24:[email protected]]
end
if (reset) begin
value <= 1'h0;
end else begin
if (_T_6) begin
value <= _T_12;
end
end
if (reset) begin
value_1 <= 1'h0;
end else begin
if (_T_8) begin
value_1 <= _T_14;
end
end
if (reset) begin
_T_1 <= 1'h0;
end else begin
if (_T_15) begin
_T_1 <= _T_6;
end
end
end
endmodule |
module Repeater_5( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
input io_repeat, // @[:[email protected]]
output io_full, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [2:0] io_enq_bits_opcode, // @[:[email protected]]
input [2:0] io_enq_bits_param, // @[:[email protected]]
input [2:0] io_enq_bits_size, // @[:[email protected]]
input [4:0] io_enq_bits_source, // @[:[email protected]]
input [31:0] io_enq_bits_address, // @[:[email protected]]
input [3:0] io_enq_bits_mask, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [2:0] io_deq_bits_opcode, // @[:[email protected]]
output [2:0] io_deq_bits_param, // @[:[email protected]]
output [2:0] io_deq_bits_size, // @[:[email protected]]
output [4:0] io_deq_bits_source, // @[:[email protected]]
output [31:0] io_deq_bits_address, // @[:[email protected]]
output [3:0] io_deq_bits_mask // @[:[email protected]]
);
reg full; // @[Repeater.scala 18:21:[email protected]]
reg [31:0] _RAND_0;
reg [2:0] saved_opcode; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_1;
reg [2:0] saved_param; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_2;
reg [2:0] saved_size; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_3;
reg [4:0] saved_source; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] saved_address; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_5;
reg [3:0] saved_mask; // @[Repeater.scala 19:18:[email protected]]
reg [31:0] _RAND_6;
wire _T_1; // @[Repeater.scala 23:35:[email protected]]
wire _T_4; // @[Decoupled.scala 37:37:[email protected]]
wire _T_5; // @[Repeater.scala 27:23:[email protected]]
wire _T_6; // @[Decoupled.scala 37:37:[email protected]]
wire _T_7; // @[Repeater.scala 28:26:[email protected]]
wire _T_8; // @[Repeater.scala 28:23:[email protected]]
assign _T_1 = full == 1'h0; // @[Repeater.scala 23:35:[email protected]]
assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_5 = _T_4 & io_repeat; // @[Repeater.scala 27:23:[email protected]]
assign _T_6 = io_deq_ready & io_deq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_7 = io_repeat == 1'h0; // @[Repeater.scala 28:26:[email protected]]
assign _T_8 = _T_6 & _T_7; // @[Repeater.scala 28:23:[email protected]]
assign io_full = full; // @[Repeater.scala 25:11:[email protected]]
assign io_enq_ready = io_deq_ready & _T_1; // @[Repeater.scala 23:16:[email protected]]
assign io_deq_valid = io_enq_valid | full; // @[Repeater.scala 22:16:[email protected]]
assign io_deq_bits_opcode = full ? saved_opcode : io_enq_bits_opcode; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_param = full ? saved_param : io_enq_bits_param; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_size = full ? saved_size : io_enq_bits_size; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_source = full ? saved_source : io_enq_bits_source; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_address = full ? saved_address : io_enq_bits_address; // @[Repeater.scala 24:15:[email protected]]
assign io_deq_bits_mask = full ? saved_mask : io_enq_bits_mask; // @[Repeater.scala 24:15:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
full = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
saved_opcode = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
saved_param = _RAND_2[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
saved_size = _RAND_3[2:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
saved_source = _RAND_4[4:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
saved_address = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
saved_mask = _RAND_6[3:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
full <= 1'h0;
end else begin
if (_T_8) begin
full <= 1'h0;
end else begin
if (_T_5) begin
full <= 1'h1;
end
end
end
if (_T_5) begin
saved_opcode <= io_enq_bits_opcode;
end
if (_T_5) begin
saved_param <= io_enq_bits_param;
end
if (_T_5) begin
saved_size <= io_enq_bits_size;
end
if (_T_5) begin
saved_source <= io_enq_bits_source;
end
if (_T_5) begin
saved_address <= io_enq_bits_address;
end
if (_T_5) begin
saved_mask <= io_enq_bits_mask;
end
end
endmodule |
module ShiftQueue( // @[:[email protected]]
input clock, // @[:[email protected]]
input reset, // @[:[email protected]]
output io_enq_ready, // @[:[email protected]]
input io_enq_valid, // @[:[email protected]]
input [31:0] io_enq_bits_pc, // @[:[email protected]]
input [31:0] io_enq_bits_data, // @[:[email protected]]
input io_enq_bits_xcpt_ae_inst, // @[:[email protected]]
input io_enq_bits_replay, // @[:[email protected]]
input io_deq_ready, // @[:[email protected]]
output io_deq_valid, // @[:[email protected]]
output [31:0] io_deq_bits_pc, // @[:[email protected]]
output [31:0] io_deq_bits_data, // @[:[email protected]]
output io_deq_bits_xcpt_ae_inst, // @[:[email protected]]
output io_deq_bits_replay, // @[:[email protected]]
output [4:0] io_mask // @[:[email protected]]
);
reg _T_1_0; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_0;
reg _T_1_1; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_1;
reg _T_1_2; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_2;
reg _T_1_3; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_3;
reg _T_1_4; // @[ShiftQueue.scala 20:30:[email protected]]
reg [31:0] _RAND_4;
reg [31:0] _T_2_0_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_5;
reg [31:0] _T_2_0_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_6;
reg _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_7;
reg _T_2_0_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_8;
reg [31:0] _T_2_1_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_9;
reg [31:0] _T_2_1_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_10;
reg _T_2_1_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_11;
reg _T_2_1_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_12;
reg [31:0] _T_2_2_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_13;
reg [31:0] _T_2_2_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_14;
reg _T_2_2_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_15;
reg _T_2_2_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_16;
reg [31:0] _T_2_3_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_17;
reg [31:0] _T_2_3_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_18;
reg _T_2_3_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_19;
reg _T_2_3_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_20;
reg [31:0] _T_2_4_pc; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_21;
reg [31:0] _T_2_4_data; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_22;
reg _T_2_4_xcpt_ae_inst; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_23;
reg _T_2_4_replay; // @[ShiftQueue.scala 21:25:[email protected]]
reg [31:0] _RAND_24;
wire _T_4; // @[Decoupled.scala 37:37:[email protected]]
wire _T_6; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_7; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_10; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_11; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_12; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_19; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_24; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_25; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_28; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_29; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_30; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_37; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_42; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_43; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_46; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_47; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_48; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_55; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_60; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_61; // @[ShiftQueue.scala 29:28:[email protected]]
wire _T_64; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_65; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_66; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_73; // @[ShiftQueue.scala 36:45:[email protected]]
wire _T_77; // @[ShiftQueue.scala 29:45:[email protected]]
wire _T_81; // @[ShiftQueue.scala 30:48:[email protected]]
wire _T_82; // @[ShiftQueue.scala 30:45:[email protected]]
wire _T_83; // @[ShiftQueue.scala 28:10:[email protected]]
wire _T_90; // @[ShiftQueue.scala 36:45:[email protected]]
wire [1:0] _T_94; // @[ShiftQueue.scala 52:20:[email protected]]
wire [2:0] _T_96; // @[ShiftQueue.scala 52:20:[email protected]]
assign _T_4 = io_enq_ready & io_enq_valid; // @[Decoupled.scala 37:37:[email protected]]
assign _T_6 = _T_4 & _T_1_0; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_7 = _T_1_1 | _T_6; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_10 = _T_1_0 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_11 = _T_4 & _T_10; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_12 = io_deq_ready ? _T_7 : _T_11; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_19 = _T_4 | _T_1_0; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_24 = _T_4 & _T_1_1; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_25 = _T_1_2 | _T_24; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_28 = _T_1_1 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_29 = _T_6 & _T_28; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_30 = io_deq_ready ? _T_25 : _T_29; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_37 = _T_6 | _T_1_1; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_42 = _T_4 & _T_1_2; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_43 = _T_1_3 | _T_42; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_46 = _T_1_2 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_47 = _T_24 & _T_46; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_48 = io_deq_ready ? _T_43 : _T_47; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_55 = _T_24 | _T_1_2; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_60 = _T_4 & _T_1_3; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_61 = _T_1_4 | _T_60; // @[ShiftQueue.scala 29:28:[email protected]]
assign _T_64 = _T_1_3 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_65 = _T_42 & _T_64; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_66 = io_deq_ready ? _T_61 : _T_65; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_73 = _T_42 | _T_1_3; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_77 = _T_4 & _T_1_4; // @[ShiftQueue.scala 29:45:[email protected]]
assign _T_81 = _T_1_4 == 1'h0; // @[ShiftQueue.scala 30:48:[email protected]]
assign _T_82 = _T_60 & _T_81; // @[ShiftQueue.scala 30:45:[email protected]]
assign _T_83 = io_deq_ready ? _T_77 : _T_82; // @[ShiftQueue.scala 28:10:[email protected]]
assign _T_90 = _T_60 | _T_1_4; // @[ShiftQueue.scala 36:45:[email protected]]
assign _T_94 = {_T_1_1,_T_1_0}; // @[ShiftQueue.scala 52:20:[email protected]]
assign _T_96 = {_T_1_4,_T_1_3,_T_1_2}; // @[ShiftQueue.scala 52:20:[email protected]]
assign io_enq_ready = _T_1_4 == 1'h0; // @[ShiftQueue.scala 39:16:[email protected]]
assign io_deq_valid = io_enq_valid ? 1'h1 : _T_1_0; // @[ShiftQueue.scala 40:16:[email protected] ShiftQueue.scala 44:40:[email protected]]
assign io_deq_bits_pc = _T_10 ? io_enq_bits_pc : _T_2_0_pc; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_data = _T_10 ? io_enq_bits_data : _T_2_0_data; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_xcpt_ae_inst = _T_10 ? io_enq_bits_xcpt_ae_inst : _T_2_0_xcpt_ae_inst; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_deq_bits_replay = _T_10 ? io_enq_bits_replay : _T_2_0_replay; // @[ShiftQueue.scala 41:15:[email protected] ShiftQueue.scala 45:36:[email protected]]
assign io_mask = {_T_96,_T_94}; // @[ShiftQueue.scala 52:11:[email protected]]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
_T_1_0 = _RAND_0[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_1 = {1{`RANDOM}};
_T_1_1 = _RAND_1[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_2 = {1{`RANDOM}};
_T_1_2 = _RAND_2[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_3 = {1{`RANDOM}};
_T_1_3 = _RAND_3[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_4 = {1{`RANDOM}};
_T_1_4 = _RAND_4[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_5 = {1{`RANDOM}};
_T_2_0_pc = _RAND_5[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_6 = {1{`RANDOM}};
_T_2_0_data = _RAND_6[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_7 = {1{`RANDOM}};
_T_2_0_xcpt_ae_inst = _RAND_7[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_8 = {1{`RANDOM}};
_T_2_0_replay = _RAND_8[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_9 = {1{`RANDOM}};
_T_2_1_pc = _RAND_9[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_10 = {1{`RANDOM}};
_T_2_1_data = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_11 = {1{`RANDOM}};
_T_2_1_xcpt_ae_inst = _RAND_11[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_12 = {1{`RANDOM}};
_T_2_1_replay = _RAND_12[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_13 = {1{`RANDOM}};
_T_2_2_pc = _RAND_13[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_14 = {1{`RANDOM}};
_T_2_2_data = _RAND_14[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_15 = {1{`RANDOM}};
_T_2_2_xcpt_ae_inst = _RAND_15[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_16 = {1{`RANDOM}};
_T_2_2_replay = _RAND_16[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_17 = {1{`RANDOM}};
_T_2_3_pc = _RAND_17[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_18 = {1{`RANDOM}};
_T_2_3_data = _RAND_18[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_19 = {1{`RANDOM}};
_T_2_3_xcpt_ae_inst = _RAND_19[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_20 = {1{`RANDOM}};
_T_2_3_replay = _RAND_20[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_21 = {1{`RANDOM}};
_T_2_4_pc = _RAND_21[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_22 = {1{`RANDOM}};
_T_2_4_data = _RAND_22[31:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_23 = {1{`RANDOM}};
_T_2_4_xcpt_ae_inst = _RAND_23[0:0];
`endif // RANDOMIZE_REG_INIT
`ifdef RANDOMIZE_REG_INIT
_RAND_24 = {1{`RANDOM}};
_T_2_4_replay = _RAND_24[0:0];
`endif // RANDOMIZE_REG_INIT
`endif // RANDOMIZE
end
always @(posedge clock) begin
if (reset) begin
_T_1_0 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_0 <= _T_7;
end else begin
_T_1_0 <= _T_19;
end
end
if (reset) begin
_T_1_1 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_1 <= _T_25;
end else begin
_T_1_1 <= _T_37;
end
end
if (reset) begin
_T_1_2 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_2 <= _T_43;
end else begin
_T_1_2 <= _T_55;
end
end
if (reset) begin
_T_1_3 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_3 <= _T_61;
end else begin
_T_1_3 <= _T_73;
end
end
if (reset) begin
_T_1_4 <= 1'h0;
end else begin
if (io_deq_ready) begin
_T_1_4 <= _T_77;
end else begin
_T_1_4 <= _T_90;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_pc <= _T_2_1_pc;
end else begin
_T_2_0_pc <= io_enq_bits_pc;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_data <= _T_2_1_data;
end else begin
_T_2_0_data <= io_enq_bits_data;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_xcpt_ae_inst <= _T_2_1_xcpt_ae_inst;
end else begin
_T_2_0_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_12) begin
if (_T_1_1) begin
_T_2_0_replay <= _T_2_1_replay;
end else begin
_T_2_0_replay <= io_enq_bits_replay;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_pc <= _T_2_2_pc;
end else begin
_T_2_1_pc <= io_enq_bits_pc;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_data <= _T_2_2_data;
end else begin
_T_2_1_data <= io_enq_bits_data;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_xcpt_ae_inst <= _T_2_2_xcpt_ae_inst;
end else begin
_T_2_1_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_30) begin
if (_T_1_2) begin
_T_2_1_replay <= _T_2_2_replay;
end else begin
_T_2_1_replay <= io_enq_bits_replay;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_pc <= _T_2_3_pc;
end else begin
_T_2_2_pc <= io_enq_bits_pc;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_data <= _T_2_3_data;
end else begin
_T_2_2_data <= io_enq_bits_data;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_xcpt_ae_inst <= _T_2_3_xcpt_ae_inst;
end else begin
_T_2_2_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_48) begin
if (_T_1_3) begin
_T_2_2_replay <= _T_2_3_replay;
end else begin
_T_2_2_replay <= io_enq_bits_replay;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_pc <= _T_2_4_pc;
end else begin
_T_2_3_pc <= io_enq_bits_pc;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_data <= _T_2_4_data;
end else begin
_T_2_3_data <= io_enq_bits_data;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_xcpt_ae_inst <= _T_2_4_xcpt_ae_inst;
end else begin
_T_2_3_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
end
if (_T_66) begin
if (_T_1_4) begin
_T_2_3_replay <= _T_2_4_replay;
end else begin
_T_2_3_replay <= io_enq_bits_replay;
end
end
if (_T_83) begin
_T_2_4_pc <= io_enq_bits_pc;
end
if (_T_83) begin
_T_2_4_data <= io_enq_bits_data;
end
if (_T_83) begin
_T_2_4_xcpt_ae_inst <= io_enq_bits_xcpt_ae_inst;
end
if (_T_83) begin
_T_2_4_replay <= io_enq_bits_replay;
end
end
endmodule |
module IntSyncCrossingSink_1( // @[:[email protected]]
input auto_in_sync_0, // @[:[email protected]]
input auto_in_sync_1, // @[:[email protected]]
output auto_out_0, // @[:[email protected]]
output auto_out_1 // @[:[email protected]]
);
assign auto_out_0 = auto_in_sync_0; // @[LazyModule.scala 173:49:[email protected]]
assign auto_out_1 = auto_in_sync_1; // @[LazyModule.scala 173:49:[email protected]]
endmodule |
module bsg_scan_width_p8_or_p1_lo_to_hi_p1
(
i,
o
);
input [7:0] i;
output [7:0] o;
wire [7:0] o;
wire t_2__7_,t_2__6_,t_2__5_,t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__7_,t_1__6_,
t_1__5_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
assign t_1__7_ = i[0] | 1'b0;
assign t_1__6_ = i[1] | i[0];
assign t_1__5_ = i[2] | i[1];
assign t_1__4_ = i[3] | i[2];
assign t_1__3_ = i[4] | i[3];
assign t_1__2_ = i[5] | i[4];
assign t_1__1_ = i[6] | i[5];
assign t_1__0_ = i[7] | i[6];
assign t_2__7_ = t_1__7_ | 1'b0;
assign t_2__6_ = t_1__6_ | 1'b0;
assign t_2__5_ = t_1__5_ | t_1__7_;
assign t_2__4_ = t_1__4_ | t_1__6_;
assign t_2__3_ = t_1__3_ | t_1__5_;
assign t_2__2_ = t_1__2_ | t_1__4_;
assign t_2__1_ = t_1__1_ | t_1__3_;
assign t_2__0_ = t_1__0_ | t_1__2_;
assign o[0] = t_2__7_ | 1'b0;
assign o[1] = t_2__6_ | 1'b0;
assign o[2] = t_2__5_ | 1'b0;
assign o[3] = t_2__4_ | 1'b0;
assign o[4] = t_2__3_ | t_2__7_;
assign o[5] = t_2__2_ | t_2__6_;
assign o[6] = t_2__1_ | t_2__5_;
assign o[7] = t_2__0_ | t_2__4_;
endmodule |
module itlb_vaddr_width_p56_paddr_width_p22_eaddr_width_p64_btb_indx_width_p9_bht_indx_width_p5_ras_addr_width_p22_asid_width_p10_ppn_start_bit_p12_tag_width_p10
(
clk_i,
reset_i,
fe_itlb_i,
fe_itlb_v_i,
fe_itlb_ready_o,
pc_gen_itlb_i,
pc_gen_itlb_v_i,
pc_gen_itlb_ready_o,
itlb_icache_o,
itlb_icache_data_resp_v_o,
itlb_icache_data_resp_ready_i,
itlb_fe_o,
itlb_fe_v_o,
itlb_fe_ready_i
);
input [108:0] fe_itlb_i;
input [63:0] pc_gen_itlb_i;
output [9:0] itlb_icache_o;
output [133:0] itlb_fe_o;
input clk_i;
input reset_i;
input fe_itlb_v_i;
input pc_gen_itlb_v_i;
input itlb_icache_data_resp_ready_i;
input itlb_fe_ready_i;
output fe_itlb_ready_o;
output pc_gen_itlb_ready_o;
output itlb_icache_data_resp_v_o;
output itlb_fe_v_o;
wire [133:0] itlb_fe_o;
wire fe_itlb_ready_o,pc_gen_itlb_ready_o,itlb_icache_data_resp_v_o,itlb_fe_v_o;
reg [9:0] itlb_icache_o;
assign pc_gen_itlb_ready_o = 1'b1;
assign itlb_icache_data_resp_v_o = 1'b1;
assign fe_itlb_ready_o = 1'b0;
assign itlb_fe_v_o = 1'b0;
always @(posedge clk_i) begin
if(1'b1) begin
{ itlb_icache_o[9:0] } <= { pc_gen_itlb_i[21:12] };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p36_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [35:0] w_data_i;
input [0:0] r_addr_i;
output [35:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [35:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [71:0] mem;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[71] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[70] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[69] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[68] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[67] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[66] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[65] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[64] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[63] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[62] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[61] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[60] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[59] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[58] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[57] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[56] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[55] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[54] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[53] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[52] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[51] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[50] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[49] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[48] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[47] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[46] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[45] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[44] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[43] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[42] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[41] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[40] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[39] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[38] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[37] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[36] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[71:36] } <= { w_data_i[35:0] };
end
if(N7) begin
{ mem[35:0] } <= { w_data_i[35:0] };
end
end
endmodule |
module instr_scan_eaddr_width_p64_instr_width_p32
(
instr_i,
scan_o
);
input [31:0] instr_i;
output [68:0] scan_o;
wire [68:0] scan_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,
N23,N24,N25,N26,N27,N28,N29,N30;
assign scan_o[66] = 1'b0;
assign scan_o[67] = 1'b0;
assign N7 = instr_i[0] & instr_i[1];
assign scan_o[68] = ~N7;
assign N9 = ~instr_i[6];
assign N10 = ~instr_i[5];
assign N11 = ~instr_i[3];
assign N12 = ~instr_i[2];
assign N13 = ~instr_i[1];
assign N14 = ~instr_i[0];
assign N15 = N10 | N9;
assign N16 = instr_i[4] | N15;
assign N17 = N11 | N16;
assign N18 = N12 | N17;
assign N19 = N13 | N18;
assign N20 = N14 | N19;
assign N21 = ~N20;
assign N22 = instr_i[3] | N16;
assign N23 = N12 | N22;
assign N24 = N13 | N23;
assign N25 = N14 | N24;
assign N26 = ~N25;
assign N27 = instr_i[2] | N22;
assign N28 = N13 | N27;
assign N29 = N14 | N28;
assign N30 = ~N29;
assign scan_o[65:64] = (N0)? { 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1 } :
(N4)? { 1'b1, N20 } : 1'b0;
assign N0 = N30;
assign N1 = N26;
assign scan_o[63:0] = (N0)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[7:7], instr_i[30:25], instr_i[11:8], 1'b0 } :
(N1)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:20] } :
(N2)? { instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[31:31], instr_i[19:12], instr_i[20:20], instr_i[30:21], 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N21;
assign N3 = N26 | N30;
assign N4 = ~N3;
assign N5 = N21 | N3;
assign N6 = ~N5;
endmodule |
module bp_be_dcache_lru_encode_ways_p8
(
lru_i,
way_id_o
);
input [6:0] lru_i;
output [2:0] way_id_o;
wire [2:0] way_id_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = lru_i[3] & N9;
assign N14 = N13 & N10;
assign N16 = N15 & lru_i[1];
assign N17 = N16 & N10;
assign N18 = lru_i[4] & lru_i[1];
assign N19 = N18 & N10;
assign N22 = N20 & N21;
assign N23 = N22 & lru_i[0];
assign N24 = lru_i[5] & N21;
assign N25 = N24 & lru_i[0];
assign N27 = N26 & lru_i[2];
assign N28 = N27 & lru_i[0];
assign N29 = lru_i[6] & lru_i[2];
assign N30 = N29 & lru_i[0];
assign way_id_o = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b1, 1'b1 } :
(N4)? { 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b1, 1'b0, 1'b1 } :
(N6)? { 1'b1, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b1, 1'b1 } : 1'b0;
assign N0 = N12;
assign N1 = N14;
assign N2 = N17;
assign N3 = N19;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign N8 = ~lru_i[3];
assign N9 = ~lru_i[1];
assign N10 = ~lru_i[0];
assign N15 = ~lru_i[4];
assign N20 = ~lru_i[5];
assign N21 = ~lru_i[2];
assign N26 = ~lru_i[6];
endmodule |
module bp_fe_lce_data_cmd_data_width_p64_lce_addr_width_p22_lce_data_width_p512_num_cce_p1_num_lce_p2_lce_sets_p64_ways_p8_block_size_in_bytes_p8
(
cce_data_received_o,
lce_data_cmd_i,
lce_data_cmd_v_i,
lce_data_cmd_yumi_o,
data_mem_pkt_v_o,
data_mem_pkt_o,
data_mem_pkt_yumi_i
);
input [539:0] lce_data_cmd_i;
output [521:0] data_mem_pkt_o;
input lce_data_cmd_v_i;
input data_mem_pkt_yumi_i;
output cce_data_received_o;
output lce_data_cmd_yumi_o;
output data_mem_pkt_v_o;
wire [521:0] data_mem_pkt_o;
wire cce_data_received_o,lce_data_cmd_yumi_o,data_mem_pkt_v_o,data_mem_pkt_yumi_i,
lce_data_cmd_v_i;
assign data_mem_pkt_o[512] = 1'b1;
assign lce_data_cmd_yumi_o = data_mem_pkt_yumi_i;
assign data_mem_pkt_v_o = lce_data_cmd_v_i;
assign data_mem_pkt_o[521] = lce_data_cmd_i[523];
assign data_mem_pkt_o[520] = lce_data_cmd_i[522];
assign data_mem_pkt_o[519] = lce_data_cmd_i[521];
assign data_mem_pkt_o[518] = lce_data_cmd_i[520];
assign data_mem_pkt_o[517] = lce_data_cmd_i[519];
assign data_mem_pkt_o[516] = lce_data_cmd_i[518];
assign data_mem_pkt_o[515] = lce_data_cmd_i[536];
assign data_mem_pkt_o[514] = lce_data_cmd_i[535];
assign data_mem_pkt_o[513] = lce_data_cmd_i[534];
assign data_mem_pkt_o[511] = lce_data_cmd_i[511];
assign data_mem_pkt_o[510] = lce_data_cmd_i[510];
assign data_mem_pkt_o[509] = lce_data_cmd_i[509];
assign data_mem_pkt_o[508] = lce_data_cmd_i[508];
assign data_mem_pkt_o[507] = lce_data_cmd_i[507];
assign data_mem_pkt_o[506] = lce_data_cmd_i[506];
assign data_mem_pkt_o[505] = lce_data_cmd_i[505];
assign data_mem_pkt_o[504] = lce_data_cmd_i[504];
assign data_mem_pkt_o[503] = lce_data_cmd_i[503];
assign data_mem_pkt_o[502] = lce_data_cmd_i[502];
assign data_mem_pkt_o[501] = lce_data_cmd_i[501];
assign data_mem_pkt_o[500] = lce_data_cmd_i[500];
assign data_mem_pkt_o[499] = lce_data_cmd_i[499];
assign data_mem_pkt_o[498] = lce_data_cmd_i[498];
assign data_mem_pkt_o[497] = lce_data_cmd_i[497];
assign data_mem_pkt_o[496] = lce_data_cmd_i[496];
assign data_mem_pkt_o[495] = lce_data_cmd_i[495];
assign data_mem_pkt_o[494] = lce_data_cmd_i[494];
assign data_mem_pkt_o[493] = lce_data_cmd_i[493];
assign data_mem_pkt_o[492] = lce_data_cmd_i[492];
assign data_mem_pkt_o[491] = lce_data_cmd_i[491];
assign data_mem_pkt_o[490] = lce_data_cmd_i[490];
assign data_mem_pkt_o[489] = lce_data_cmd_i[489];
assign data_mem_pkt_o[488] = lce_data_cmd_i[488];
assign data_mem_pkt_o[487] = lce_data_cmd_i[487];
assign data_mem_pkt_o[486] = lce_data_cmd_i[486];
assign data_mem_pkt_o[485] = lce_data_cmd_i[485];
assign data_mem_pkt_o[484] = lce_data_cmd_i[484];
assign data_mem_pkt_o[483] = lce_data_cmd_i[483];
assign data_mem_pkt_o[482] = lce_data_cmd_i[482];
assign data_mem_pkt_o[481] = lce_data_cmd_i[481];
assign data_mem_pkt_o[480] = lce_data_cmd_i[480];
assign data_mem_pkt_o[479] = lce_data_cmd_i[479];
assign data_mem_pkt_o[478] = lce_data_cmd_i[478];
assign data_mem_pkt_o[477] = lce_data_cmd_i[477];
assign data_mem_pkt_o[476] = lce_data_cmd_i[476];
assign data_mem_pkt_o[475] = lce_data_cmd_i[475];
assign data_mem_pkt_o[474] = lce_data_cmd_i[474];
assign data_mem_pkt_o[473] = lce_data_cmd_i[473];
assign data_mem_pkt_o[472] = lce_data_cmd_i[472];
assign data_mem_pkt_o[471] = lce_data_cmd_i[471];
assign data_mem_pkt_o[470] = lce_data_cmd_i[470];
assign data_mem_pkt_o[469] = lce_data_cmd_i[469];
assign data_mem_pkt_o[468] = lce_data_cmd_i[468];
assign data_mem_pkt_o[467] = lce_data_cmd_i[467];
assign data_mem_pkt_o[466] = lce_data_cmd_i[466];
assign data_mem_pkt_o[465] = lce_data_cmd_i[465];
assign data_mem_pkt_o[464] = lce_data_cmd_i[464];
assign data_mem_pkt_o[463] = lce_data_cmd_i[463];
assign data_mem_pkt_o[462] = lce_data_cmd_i[462];
assign data_mem_pkt_o[461] = lce_data_cmd_i[461];
assign data_mem_pkt_o[460] = lce_data_cmd_i[460];
assign data_mem_pkt_o[459] = lce_data_cmd_i[459];
assign data_mem_pkt_o[458] = lce_data_cmd_i[458];
assign data_mem_pkt_o[457] = lce_data_cmd_i[457];
assign data_mem_pkt_o[456] = lce_data_cmd_i[456];
assign data_mem_pkt_o[455] = lce_data_cmd_i[455];
assign data_mem_pkt_o[454] = lce_data_cmd_i[454];
assign data_mem_pkt_o[453] = lce_data_cmd_i[453];
assign data_mem_pkt_o[452] = lce_data_cmd_i[452];
assign data_mem_pkt_o[451] = lce_data_cmd_i[451];
assign data_mem_pkt_o[450] = lce_data_cmd_i[450];
assign data_mem_pkt_o[449] = lce_data_cmd_i[449];
assign data_mem_pkt_o[448] = lce_data_cmd_i[448];
assign data_mem_pkt_o[447] = lce_data_cmd_i[447];
assign data_mem_pkt_o[446] = lce_data_cmd_i[446];
assign data_mem_pkt_o[445] = lce_data_cmd_i[445];
assign data_mem_pkt_o[444] = lce_data_cmd_i[444];
assign data_mem_pkt_o[443] = lce_data_cmd_i[443];
assign data_mem_pkt_o[442] = lce_data_cmd_i[442];
assign data_mem_pkt_o[441] = lce_data_cmd_i[441];
assign data_mem_pkt_o[440] = lce_data_cmd_i[440];
assign data_mem_pkt_o[439] = lce_data_cmd_i[439];
assign data_mem_pkt_o[438] = lce_data_cmd_i[438];
assign data_mem_pkt_o[437] = lce_data_cmd_i[437];
assign data_mem_pkt_o[436] = lce_data_cmd_i[436];
assign data_mem_pkt_o[435] = lce_data_cmd_i[435];
assign data_mem_pkt_o[434] = lce_data_cmd_i[434];
assign data_mem_pkt_o[433] = lce_data_cmd_i[433];
assign data_mem_pkt_o[432] = lce_data_cmd_i[432];
assign data_mem_pkt_o[431] = lce_data_cmd_i[431];
assign data_mem_pkt_o[430] = lce_data_cmd_i[430];
assign data_mem_pkt_o[429] = lce_data_cmd_i[429];
assign data_mem_pkt_o[428] = lce_data_cmd_i[428];
assign data_mem_pkt_o[427] = lce_data_cmd_i[427];
assign data_mem_pkt_o[426] = lce_data_cmd_i[426];
assign data_mem_pkt_o[425] = lce_data_cmd_i[425];
assign data_mem_pkt_o[424] = lce_data_cmd_i[424];
assign data_mem_pkt_o[423] = lce_data_cmd_i[423];
assign data_mem_pkt_o[422] = lce_data_cmd_i[422];
assign data_mem_pkt_o[421] = lce_data_cmd_i[421];
assign data_mem_pkt_o[420] = lce_data_cmd_i[420];
assign data_mem_pkt_o[419] = lce_data_cmd_i[419];
assign data_mem_pkt_o[418] = lce_data_cmd_i[418];
assign data_mem_pkt_o[417] = lce_data_cmd_i[417];
assign data_mem_pkt_o[416] = lce_data_cmd_i[416];
assign data_mem_pkt_o[415] = lce_data_cmd_i[415];
assign data_mem_pkt_o[414] = lce_data_cmd_i[414];
assign data_mem_pkt_o[413] = lce_data_cmd_i[413];
assign data_mem_pkt_o[412] = lce_data_cmd_i[412];
assign data_mem_pkt_o[411] = lce_data_cmd_i[411];
assign data_mem_pkt_o[410] = lce_data_cmd_i[410];
assign data_mem_pkt_o[409] = lce_data_cmd_i[409];
assign data_mem_pkt_o[408] = lce_data_cmd_i[408];
assign data_mem_pkt_o[407] = lce_data_cmd_i[407];
assign data_mem_pkt_o[406] = lce_data_cmd_i[406];
assign data_mem_pkt_o[405] = lce_data_cmd_i[405];
assign data_mem_pkt_o[404] = lce_data_cmd_i[404];
assign data_mem_pkt_o[403] = lce_data_cmd_i[403];
assign data_mem_pkt_o[402] = lce_data_cmd_i[402];
assign data_mem_pkt_o[401] = lce_data_cmd_i[401];
assign data_mem_pkt_o[400] = lce_data_cmd_i[400];
assign data_mem_pkt_o[399] = lce_data_cmd_i[399];
assign data_mem_pkt_o[398] = lce_data_cmd_i[398];
assign data_mem_pkt_o[397] = lce_data_cmd_i[397];
assign data_mem_pkt_o[396] = lce_data_cmd_i[396];
assign data_mem_pkt_o[395] = lce_data_cmd_i[395];
assign data_mem_pkt_o[394] = lce_data_cmd_i[394];
assign data_mem_pkt_o[393] = lce_data_cmd_i[393];
assign data_mem_pkt_o[392] = lce_data_cmd_i[392];
assign data_mem_pkt_o[391] = lce_data_cmd_i[391];
assign data_mem_pkt_o[390] = lce_data_cmd_i[390];
assign data_mem_pkt_o[389] = lce_data_cmd_i[389];
assign data_mem_pkt_o[388] = lce_data_cmd_i[388];
assign data_mem_pkt_o[387] = lce_data_cmd_i[387];
assign data_mem_pkt_o[386] = lce_data_cmd_i[386];
assign data_mem_pkt_o[385] = lce_data_cmd_i[385];
assign data_mem_pkt_o[384] = lce_data_cmd_i[384];
assign data_mem_pkt_o[383] = lce_data_cmd_i[383];
assign data_mem_pkt_o[382] = lce_data_cmd_i[382];
assign data_mem_pkt_o[381] = lce_data_cmd_i[381];
assign data_mem_pkt_o[380] = lce_data_cmd_i[380];
assign data_mem_pkt_o[379] = lce_data_cmd_i[379];
assign data_mem_pkt_o[378] = lce_data_cmd_i[378];
assign data_mem_pkt_o[377] = lce_data_cmd_i[377];
assign data_mem_pkt_o[376] = lce_data_cmd_i[376];
assign data_mem_pkt_o[375] = lce_data_cmd_i[375];
assign data_mem_pkt_o[374] = lce_data_cmd_i[374];
assign data_mem_pkt_o[373] = lce_data_cmd_i[373];
assign data_mem_pkt_o[372] = lce_data_cmd_i[372];
assign data_mem_pkt_o[371] = lce_data_cmd_i[371];
assign data_mem_pkt_o[370] = lce_data_cmd_i[370];
assign data_mem_pkt_o[369] = lce_data_cmd_i[369];
assign data_mem_pkt_o[368] = lce_data_cmd_i[368];
assign data_mem_pkt_o[367] = lce_data_cmd_i[367];
assign data_mem_pkt_o[366] = lce_data_cmd_i[366];
assign data_mem_pkt_o[365] = lce_data_cmd_i[365];
assign data_mem_pkt_o[364] = lce_data_cmd_i[364];
assign data_mem_pkt_o[363] = lce_data_cmd_i[363];
assign data_mem_pkt_o[362] = lce_data_cmd_i[362];
assign data_mem_pkt_o[361] = lce_data_cmd_i[361];
assign data_mem_pkt_o[360] = lce_data_cmd_i[360];
assign data_mem_pkt_o[359] = lce_data_cmd_i[359];
assign data_mem_pkt_o[358] = lce_data_cmd_i[358];
assign data_mem_pkt_o[357] = lce_data_cmd_i[357];
assign data_mem_pkt_o[356] = lce_data_cmd_i[356];
assign data_mem_pkt_o[355] = lce_data_cmd_i[355];
assign data_mem_pkt_o[354] = lce_data_cmd_i[354];
assign data_mem_pkt_o[353] = lce_data_cmd_i[353];
assign data_mem_pkt_o[352] = lce_data_cmd_i[352];
assign data_mem_pkt_o[351] = lce_data_cmd_i[351];
assign data_mem_pkt_o[350] = lce_data_cmd_i[350];
assign data_mem_pkt_o[349] = lce_data_cmd_i[349];
assign data_mem_pkt_o[348] = lce_data_cmd_i[348];
assign data_mem_pkt_o[347] = lce_data_cmd_i[347];
assign data_mem_pkt_o[346] = lce_data_cmd_i[346];
assign data_mem_pkt_o[345] = lce_data_cmd_i[345];
assign data_mem_pkt_o[344] = lce_data_cmd_i[344];
assign data_mem_pkt_o[343] = lce_data_cmd_i[343];
assign data_mem_pkt_o[342] = lce_data_cmd_i[342];
assign data_mem_pkt_o[341] = lce_data_cmd_i[341];
assign data_mem_pkt_o[340] = lce_data_cmd_i[340];
assign data_mem_pkt_o[339] = lce_data_cmd_i[339];
assign data_mem_pkt_o[338] = lce_data_cmd_i[338];
assign data_mem_pkt_o[337] = lce_data_cmd_i[337];
assign data_mem_pkt_o[336] = lce_data_cmd_i[336];
assign data_mem_pkt_o[335] = lce_data_cmd_i[335];
assign data_mem_pkt_o[334] = lce_data_cmd_i[334];
assign data_mem_pkt_o[333] = lce_data_cmd_i[333];
assign data_mem_pkt_o[332] = lce_data_cmd_i[332];
assign data_mem_pkt_o[331] = lce_data_cmd_i[331];
assign data_mem_pkt_o[330] = lce_data_cmd_i[330];
assign data_mem_pkt_o[329] = lce_data_cmd_i[329];
assign data_mem_pkt_o[328] = lce_data_cmd_i[328];
assign data_mem_pkt_o[327] = lce_data_cmd_i[327];
assign data_mem_pkt_o[326] = lce_data_cmd_i[326];
assign data_mem_pkt_o[325] = lce_data_cmd_i[325];
assign data_mem_pkt_o[324] = lce_data_cmd_i[324];
assign data_mem_pkt_o[323] = lce_data_cmd_i[323];
assign data_mem_pkt_o[322] = lce_data_cmd_i[322];
assign data_mem_pkt_o[321] = lce_data_cmd_i[321];
assign data_mem_pkt_o[320] = lce_data_cmd_i[320];
assign data_mem_pkt_o[319] = lce_data_cmd_i[319];
assign data_mem_pkt_o[318] = lce_data_cmd_i[318];
assign data_mem_pkt_o[317] = lce_data_cmd_i[317];
assign data_mem_pkt_o[316] = lce_data_cmd_i[316];
assign data_mem_pkt_o[315] = lce_data_cmd_i[315];
assign data_mem_pkt_o[314] = lce_data_cmd_i[314];
assign data_mem_pkt_o[313] = lce_data_cmd_i[313];
assign data_mem_pkt_o[312] = lce_data_cmd_i[312];
assign data_mem_pkt_o[311] = lce_data_cmd_i[311];
assign data_mem_pkt_o[310] = lce_data_cmd_i[310];
assign data_mem_pkt_o[309] = lce_data_cmd_i[309];
assign data_mem_pkt_o[308] = lce_data_cmd_i[308];
assign data_mem_pkt_o[307] = lce_data_cmd_i[307];
assign data_mem_pkt_o[306] = lce_data_cmd_i[306];
assign data_mem_pkt_o[305] = lce_data_cmd_i[305];
assign data_mem_pkt_o[304] = lce_data_cmd_i[304];
assign data_mem_pkt_o[303] = lce_data_cmd_i[303];
assign data_mem_pkt_o[302] = lce_data_cmd_i[302];
assign data_mem_pkt_o[301] = lce_data_cmd_i[301];
assign data_mem_pkt_o[300] = lce_data_cmd_i[300];
assign data_mem_pkt_o[299] = lce_data_cmd_i[299];
assign data_mem_pkt_o[298] = lce_data_cmd_i[298];
assign data_mem_pkt_o[297] = lce_data_cmd_i[297];
assign data_mem_pkt_o[296] = lce_data_cmd_i[296];
assign data_mem_pkt_o[295] = lce_data_cmd_i[295];
assign data_mem_pkt_o[294] = lce_data_cmd_i[294];
assign data_mem_pkt_o[293] = lce_data_cmd_i[293];
assign data_mem_pkt_o[292] = lce_data_cmd_i[292];
assign data_mem_pkt_o[291] = lce_data_cmd_i[291];
assign data_mem_pkt_o[290] = lce_data_cmd_i[290];
assign data_mem_pkt_o[289] = lce_data_cmd_i[289];
assign data_mem_pkt_o[288] = lce_data_cmd_i[288];
assign data_mem_pkt_o[287] = lce_data_cmd_i[287];
assign data_mem_pkt_o[286] = lce_data_cmd_i[286];
assign data_mem_pkt_o[285] = lce_data_cmd_i[285];
assign data_mem_pkt_o[284] = lce_data_cmd_i[284];
assign data_mem_pkt_o[283] = lce_data_cmd_i[283];
assign data_mem_pkt_o[282] = lce_data_cmd_i[282];
assign data_mem_pkt_o[281] = lce_data_cmd_i[281];
assign data_mem_pkt_o[280] = lce_data_cmd_i[280];
assign data_mem_pkt_o[279] = lce_data_cmd_i[279];
assign data_mem_pkt_o[278] = lce_data_cmd_i[278];
assign data_mem_pkt_o[277] = lce_data_cmd_i[277];
assign data_mem_pkt_o[276] = lce_data_cmd_i[276];
assign data_mem_pkt_o[275] = lce_data_cmd_i[275];
assign data_mem_pkt_o[274] = lce_data_cmd_i[274];
assign data_mem_pkt_o[273] = lce_data_cmd_i[273];
assign data_mem_pkt_o[272] = lce_data_cmd_i[272];
assign data_mem_pkt_o[271] = lce_data_cmd_i[271];
assign data_mem_pkt_o[270] = lce_data_cmd_i[270];
assign data_mem_pkt_o[269] = lce_data_cmd_i[269];
assign data_mem_pkt_o[268] = lce_data_cmd_i[268];
assign data_mem_pkt_o[267] = lce_data_cmd_i[267];
assign data_mem_pkt_o[266] = lce_data_cmd_i[266];
assign data_mem_pkt_o[265] = lce_data_cmd_i[265];
assign data_mem_pkt_o[264] = lce_data_cmd_i[264];
assign data_mem_pkt_o[263] = lce_data_cmd_i[263];
assign data_mem_pkt_o[262] = lce_data_cmd_i[262];
assign data_mem_pkt_o[261] = lce_data_cmd_i[261];
assign data_mem_pkt_o[260] = lce_data_cmd_i[260];
assign data_mem_pkt_o[259] = lce_data_cmd_i[259];
assign data_mem_pkt_o[258] = lce_data_cmd_i[258];
assign data_mem_pkt_o[257] = lce_data_cmd_i[257];
assign data_mem_pkt_o[256] = lce_data_cmd_i[256];
assign data_mem_pkt_o[255] = lce_data_cmd_i[255];
assign data_mem_pkt_o[254] = lce_data_cmd_i[254];
assign data_mem_pkt_o[253] = lce_data_cmd_i[253];
assign data_mem_pkt_o[252] = lce_data_cmd_i[252];
assign data_mem_pkt_o[251] = lce_data_cmd_i[251];
assign data_mem_pkt_o[250] = lce_data_cmd_i[250];
assign data_mem_pkt_o[249] = lce_data_cmd_i[249];
assign data_mem_pkt_o[248] = lce_data_cmd_i[248];
assign data_mem_pkt_o[247] = lce_data_cmd_i[247];
assign data_mem_pkt_o[246] = lce_data_cmd_i[246];
assign data_mem_pkt_o[245] = lce_data_cmd_i[245];
assign data_mem_pkt_o[244] = lce_data_cmd_i[244];
assign data_mem_pkt_o[243] = lce_data_cmd_i[243];
assign data_mem_pkt_o[242] = lce_data_cmd_i[242];
assign data_mem_pkt_o[241] = lce_data_cmd_i[241];
assign data_mem_pkt_o[240] = lce_data_cmd_i[240];
assign data_mem_pkt_o[239] = lce_data_cmd_i[239];
assign data_mem_pkt_o[238] = lce_data_cmd_i[238];
assign data_mem_pkt_o[237] = lce_data_cmd_i[237];
assign data_mem_pkt_o[236] = lce_data_cmd_i[236];
assign data_mem_pkt_o[235] = lce_data_cmd_i[235];
assign data_mem_pkt_o[234] = lce_data_cmd_i[234];
assign data_mem_pkt_o[233] = lce_data_cmd_i[233];
assign data_mem_pkt_o[232] = lce_data_cmd_i[232];
assign data_mem_pkt_o[231] = lce_data_cmd_i[231];
assign data_mem_pkt_o[230] = lce_data_cmd_i[230];
assign data_mem_pkt_o[229] = lce_data_cmd_i[229];
assign data_mem_pkt_o[228] = lce_data_cmd_i[228];
assign data_mem_pkt_o[227] = lce_data_cmd_i[227];
assign data_mem_pkt_o[226] = lce_data_cmd_i[226];
assign data_mem_pkt_o[225] = lce_data_cmd_i[225];
assign data_mem_pkt_o[224] = lce_data_cmd_i[224];
assign data_mem_pkt_o[223] = lce_data_cmd_i[223];
assign data_mem_pkt_o[222] = lce_data_cmd_i[222];
assign data_mem_pkt_o[221] = lce_data_cmd_i[221];
assign data_mem_pkt_o[220] = lce_data_cmd_i[220];
assign data_mem_pkt_o[219] = lce_data_cmd_i[219];
assign data_mem_pkt_o[218] = lce_data_cmd_i[218];
assign data_mem_pkt_o[217] = lce_data_cmd_i[217];
assign data_mem_pkt_o[216] = lce_data_cmd_i[216];
assign data_mem_pkt_o[215] = lce_data_cmd_i[215];
assign data_mem_pkt_o[214] = lce_data_cmd_i[214];
assign data_mem_pkt_o[213] = lce_data_cmd_i[213];
assign data_mem_pkt_o[212] = lce_data_cmd_i[212];
assign data_mem_pkt_o[211] = lce_data_cmd_i[211];
assign data_mem_pkt_o[210] = lce_data_cmd_i[210];
assign data_mem_pkt_o[209] = lce_data_cmd_i[209];
assign data_mem_pkt_o[208] = lce_data_cmd_i[208];
assign data_mem_pkt_o[207] = lce_data_cmd_i[207];
assign data_mem_pkt_o[206] = lce_data_cmd_i[206];
assign data_mem_pkt_o[205] = lce_data_cmd_i[205];
assign data_mem_pkt_o[204] = lce_data_cmd_i[204];
assign data_mem_pkt_o[203] = lce_data_cmd_i[203];
assign data_mem_pkt_o[202] = lce_data_cmd_i[202];
assign data_mem_pkt_o[201] = lce_data_cmd_i[201];
assign data_mem_pkt_o[200] = lce_data_cmd_i[200];
assign data_mem_pkt_o[199] = lce_data_cmd_i[199];
assign data_mem_pkt_o[198] = lce_data_cmd_i[198];
assign data_mem_pkt_o[197] = lce_data_cmd_i[197];
assign data_mem_pkt_o[196] = lce_data_cmd_i[196];
assign data_mem_pkt_o[195] = lce_data_cmd_i[195];
assign data_mem_pkt_o[194] = lce_data_cmd_i[194];
assign data_mem_pkt_o[193] = lce_data_cmd_i[193];
assign data_mem_pkt_o[192] = lce_data_cmd_i[192];
assign data_mem_pkt_o[191] = lce_data_cmd_i[191];
assign data_mem_pkt_o[190] = lce_data_cmd_i[190];
assign data_mem_pkt_o[189] = lce_data_cmd_i[189];
assign data_mem_pkt_o[188] = lce_data_cmd_i[188];
assign data_mem_pkt_o[187] = lce_data_cmd_i[187];
assign data_mem_pkt_o[186] = lce_data_cmd_i[186];
assign data_mem_pkt_o[185] = lce_data_cmd_i[185];
assign data_mem_pkt_o[184] = lce_data_cmd_i[184];
assign data_mem_pkt_o[183] = lce_data_cmd_i[183];
assign data_mem_pkt_o[182] = lce_data_cmd_i[182];
assign data_mem_pkt_o[181] = lce_data_cmd_i[181];
assign data_mem_pkt_o[180] = lce_data_cmd_i[180];
assign data_mem_pkt_o[179] = lce_data_cmd_i[179];
assign data_mem_pkt_o[178] = lce_data_cmd_i[178];
assign data_mem_pkt_o[177] = lce_data_cmd_i[177];
assign data_mem_pkt_o[176] = lce_data_cmd_i[176];
assign data_mem_pkt_o[175] = lce_data_cmd_i[175];
assign data_mem_pkt_o[174] = lce_data_cmd_i[174];
assign data_mem_pkt_o[173] = lce_data_cmd_i[173];
assign data_mem_pkt_o[172] = lce_data_cmd_i[172];
assign data_mem_pkt_o[171] = lce_data_cmd_i[171];
assign data_mem_pkt_o[170] = lce_data_cmd_i[170];
assign data_mem_pkt_o[169] = lce_data_cmd_i[169];
assign data_mem_pkt_o[168] = lce_data_cmd_i[168];
assign data_mem_pkt_o[167] = lce_data_cmd_i[167];
assign data_mem_pkt_o[166] = lce_data_cmd_i[166];
assign data_mem_pkt_o[165] = lce_data_cmd_i[165];
assign data_mem_pkt_o[164] = lce_data_cmd_i[164];
assign data_mem_pkt_o[163] = lce_data_cmd_i[163];
assign data_mem_pkt_o[162] = lce_data_cmd_i[162];
assign data_mem_pkt_o[161] = lce_data_cmd_i[161];
assign data_mem_pkt_o[160] = lce_data_cmd_i[160];
assign data_mem_pkt_o[159] = lce_data_cmd_i[159];
assign data_mem_pkt_o[158] = lce_data_cmd_i[158];
assign data_mem_pkt_o[157] = lce_data_cmd_i[157];
assign data_mem_pkt_o[156] = lce_data_cmd_i[156];
assign data_mem_pkt_o[155] = lce_data_cmd_i[155];
assign data_mem_pkt_o[154] = lce_data_cmd_i[154];
assign data_mem_pkt_o[153] = lce_data_cmd_i[153];
assign data_mem_pkt_o[152] = lce_data_cmd_i[152];
assign data_mem_pkt_o[151] = lce_data_cmd_i[151];
assign data_mem_pkt_o[150] = lce_data_cmd_i[150];
assign data_mem_pkt_o[149] = lce_data_cmd_i[149];
assign data_mem_pkt_o[148] = lce_data_cmd_i[148];
assign data_mem_pkt_o[147] = lce_data_cmd_i[147];
assign data_mem_pkt_o[146] = lce_data_cmd_i[146];
assign data_mem_pkt_o[145] = lce_data_cmd_i[145];
assign data_mem_pkt_o[144] = lce_data_cmd_i[144];
assign data_mem_pkt_o[143] = lce_data_cmd_i[143];
assign data_mem_pkt_o[142] = lce_data_cmd_i[142];
assign data_mem_pkt_o[141] = lce_data_cmd_i[141];
assign data_mem_pkt_o[140] = lce_data_cmd_i[140];
assign data_mem_pkt_o[139] = lce_data_cmd_i[139];
assign data_mem_pkt_o[138] = lce_data_cmd_i[138];
assign data_mem_pkt_o[137] = lce_data_cmd_i[137];
assign data_mem_pkt_o[136] = lce_data_cmd_i[136];
assign data_mem_pkt_o[135] = lce_data_cmd_i[135];
assign data_mem_pkt_o[134] = lce_data_cmd_i[134];
assign data_mem_pkt_o[133] = lce_data_cmd_i[133];
assign data_mem_pkt_o[132] = lce_data_cmd_i[132];
assign data_mem_pkt_o[131] = lce_data_cmd_i[131];
assign data_mem_pkt_o[130] = lce_data_cmd_i[130];
assign data_mem_pkt_o[129] = lce_data_cmd_i[129];
assign data_mem_pkt_o[128] = lce_data_cmd_i[128];
assign data_mem_pkt_o[127] = lce_data_cmd_i[127];
assign data_mem_pkt_o[126] = lce_data_cmd_i[126];
assign data_mem_pkt_o[125] = lce_data_cmd_i[125];
assign data_mem_pkt_o[124] = lce_data_cmd_i[124];
assign data_mem_pkt_o[123] = lce_data_cmd_i[123];
assign data_mem_pkt_o[122] = lce_data_cmd_i[122];
assign data_mem_pkt_o[121] = lce_data_cmd_i[121];
assign data_mem_pkt_o[120] = lce_data_cmd_i[120];
assign data_mem_pkt_o[119] = lce_data_cmd_i[119];
assign data_mem_pkt_o[118] = lce_data_cmd_i[118];
assign data_mem_pkt_o[117] = lce_data_cmd_i[117];
assign data_mem_pkt_o[116] = lce_data_cmd_i[116];
assign data_mem_pkt_o[115] = lce_data_cmd_i[115];
assign data_mem_pkt_o[114] = lce_data_cmd_i[114];
assign data_mem_pkt_o[113] = lce_data_cmd_i[113];
assign data_mem_pkt_o[112] = lce_data_cmd_i[112];
assign data_mem_pkt_o[111] = lce_data_cmd_i[111];
assign data_mem_pkt_o[110] = lce_data_cmd_i[110];
assign data_mem_pkt_o[109] = lce_data_cmd_i[109];
assign data_mem_pkt_o[108] = lce_data_cmd_i[108];
assign data_mem_pkt_o[107] = lce_data_cmd_i[107];
assign data_mem_pkt_o[106] = lce_data_cmd_i[106];
assign data_mem_pkt_o[105] = lce_data_cmd_i[105];
assign data_mem_pkt_o[104] = lce_data_cmd_i[104];
assign data_mem_pkt_o[103] = lce_data_cmd_i[103];
assign data_mem_pkt_o[102] = lce_data_cmd_i[102];
assign data_mem_pkt_o[101] = lce_data_cmd_i[101];
assign data_mem_pkt_o[100] = lce_data_cmd_i[100];
assign data_mem_pkt_o[99] = lce_data_cmd_i[99];
assign data_mem_pkt_o[98] = lce_data_cmd_i[98];
assign data_mem_pkt_o[97] = lce_data_cmd_i[97];
assign data_mem_pkt_o[96] = lce_data_cmd_i[96];
assign data_mem_pkt_o[95] = lce_data_cmd_i[95];
assign data_mem_pkt_o[94] = lce_data_cmd_i[94];
assign data_mem_pkt_o[93] = lce_data_cmd_i[93];
assign data_mem_pkt_o[92] = lce_data_cmd_i[92];
assign data_mem_pkt_o[91] = lce_data_cmd_i[91];
assign data_mem_pkt_o[90] = lce_data_cmd_i[90];
assign data_mem_pkt_o[89] = lce_data_cmd_i[89];
assign data_mem_pkt_o[88] = lce_data_cmd_i[88];
assign data_mem_pkt_o[87] = lce_data_cmd_i[87];
assign data_mem_pkt_o[86] = lce_data_cmd_i[86];
assign data_mem_pkt_o[85] = lce_data_cmd_i[85];
assign data_mem_pkt_o[84] = lce_data_cmd_i[84];
assign data_mem_pkt_o[83] = lce_data_cmd_i[83];
assign data_mem_pkt_o[82] = lce_data_cmd_i[82];
assign data_mem_pkt_o[81] = lce_data_cmd_i[81];
assign data_mem_pkt_o[80] = lce_data_cmd_i[80];
assign data_mem_pkt_o[79] = lce_data_cmd_i[79];
assign data_mem_pkt_o[78] = lce_data_cmd_i[78];
assign data_mem_pkt_o[77] = lce_data_cmd_i[77];
assign data_mem_pkt_o[76] = lce_data_cmd_i[76];
assign data_mem_pkt_o[75] = lce_data_cmd_i[75];
assign data_mem_pkt_o[74] = lce_data_cmd_i[74];
assign data_mem_pkt_o[73] = lce_data_cmd_i[73];
assign data_mem_pkt_o[72] = lce_data_cmd_i[72];
assign data_mem_pkt_o[71] = lce_data_cmd_i[71];
assign data_mem_pkt_o[70] = lce_data_cmd_i[70];
assign data_mem_pkt_o[69] = lce_data_cmd_i[69];
assign data_mem_pkt_o[68] = lce_data_cmd_i[68];
assign data_mem_pkt_o[67] = lce_data_cmd_i[67];
assign data_mem_pkt_o[66] = lce_data_cmd_i[66];
assign data_mem_pkt_o[65] = lce_data_cmd_i[65];
assign data_mem_pkt_o[64] = lce_data_cmd_i[64];
assign data_mem_pkt_o[63] = lce_data_cmd_i[63];
assign data_mem_pkt_o[62] = lce_data_cmd_i[62];
assign data_mem_pkt_o[61] = lce_data_cmd_i[61];
assign data_mem_pkt_o[60] = lce_data_cmd_i[60];
assign data_mem_pkt_o[59] = lce_data_cmd_i[59];
assign data_mem_pkt_o[58] = lce_data_cmd_i[58];
assign data_mem_pkt_o[57] = lce_data_cmd_i[57];
assign data_mem_pkt_o[56] = lce_data_cmd_i[56];
assign data_mem_pkt_o[55] = lce_data_cmd_i[55];
assign data_mem_pkt_o[54] = lce_data_cmd_i[54];
assign data_mem_pkt_o[53] = lce_data_cmd_i[53];
assign data_mem_pkt_o[52] = lce_data_cmd_i[52];
assign data_mem_pkt_o[51] = lce_data_cmd_i[51];
assign data_mem_pkt_o[50] = lce_data_cmd_i[50];
assign data_mem_pkt_o[49] = lce_data_cmd_i[49];
assign data_mem_pkt_o[48] = lce_data_cmd_i[48];
assign data_mem_pkt_o[47] = lce_data_cmd_i[47];
assign data_mem_pkt_o[46] = lce_data_cmd_i[46];
assign data_mem_pkt_o[45] = lce_data_cmd_i[45];
assign data_mem_pkt_o[44] = lce_data_cmd_i[44];
assign data_mem_pkt_o[43] = lce_data_cmd_i[43];
assign data_mem_pkt_o[42] = lce_data_cmd_i[42];
assign data_mem_pkt_o[41] = lce_data_cmd_i[41];
assign data_mem_pkt_o[40] = lce_data_cmd_i[40];
assign data_mem_pkt_o[39] = lce_data_cmd_i[39];
assign data_mem_pkt_o[38] = lce_data_cmd_i[38];
assign data_mem_pkt_o[37] = lce_data_cmd_i[37];
assign data_mem_pkt_o[36] = lce_data_cmd_i[36];
assign data_mem_pkt_o[35] = lce_data_cmd_i[35];
assign data_mem_pkt_o[34] = lce_data_cmd_i[34];
assign data_mem_pkt_o[33] = lce_data_cmd_i[33];
assign data_mem_pkt_o[32] = lce_data_cmd_i[32];
assign data_mem_pkt_o[31] = lce_data_cmd_i[31];
assign data_mem_pkt_o[30] = lce_data_cmd_i[30];
assign data_mem_pkt_o[29] = lce_data_cmd_i[29];
assign data_mem_pkt_o[28] = lce_data_cmd_i[28];
assign data_mem_pkt_o[27] = lce_data_cmd_i[27];
assign data_mem_pkt_o[26] = lce_data_cmd_i[26];
assign data_mem_pkt_o[25] = lce_data_cmd_i[25];
assign data_mem_pkt_o[24] = lce_data_cmd_i[24];
assign data_mem_pkt_o[23] = lce_data_cmd_i[23];
assign data_mem_pkt_o[22] = lce_data_cmd_i[22];
assign data_mem_pkt_o[21] = lce_data_cmd_i[21];
assign data_mem_pkt_o[20] = lce_data_cmd_i[20];
assign data_mem_pkt_o[19] = lce_data_cmd_i[19];
assign data_mem_pkt_o[18] = lce_data_cmd_i[18];
assign data_mem_pkt_o[17] = lce_data_cmd_i[17];
assign data_mem_pkt_o[16] = lce_data_cmd_i[16];
assign data_mem_pkt_o[15] = lce_data_cmd_i[15];
assign data_mem_pkt_o[14] = lce_data_cmd_i[14];
assign data_mem_pkt_o[13] = lce_data_cmd_i[13];
assign data_mem_pkt_o[12] = lce_data_cmd_i[12];
assign data_mem_pkt_o[11] = lce_data_cmd_i[11];
assign data_mem_pkt_o[10] = lce_data_cmd_i[10];
assign data_mem_pkt_o[9] = lce_data_cmd_i[9];
assign data_mem_pkt_o[8] = lce_data_cmd_i[8];
assign data_mem_pkt_o[7] = lce_data_cmd_i[7];
assign data_mem_pkt_o[6] = lce_data_cmd_i[6];
assign data_mem_pkt_o[5] = lce_data_cmd_i[5];
assign data_mem_pkt_o[4] = lce_data_cmd_i[4];
assign data_mem_pkt_o[3] = lce_data_cmd_i[3];
assign data_mem_pkt_o[2] = lce_data_cmd_i[2];
assign data_mem_pkt_o[1] = lce_data_cmd_i[1];
assign data_mem_pkt_o[0] = lce_data_cmd_i[0];
assign cce_data_received_o = lce_data_cmd_v_i & data_mem_pkt_yumi_i;
endmodule |
module bsg_encode_one_hot_width_p1
(
i,
addr_o,
v_o
);
input [0:0] i;
output [0:0] addr_o;
output v_o;
wire [0:0] addr_o;
wire v_o;
assign v_o = i[0];
assign addr_o[0] = 1'b0;
endmodule |
module bsg_decode_num_out_p8
(
i,
o
);
input [2:0] i;
output [7:0] o;
wire [7:0] o;
assign o = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << i;
endmodule |
module bsg_round_robin_arb_inputs_p4
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [3:0] reqs_i;
output [3:0] grants_o;
output [3:0] sel_one_hot_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [3:0] grants_o,sel_one_hot_o;
wire [1:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103;
reg [1:0] last_r;
assign N79 = N0 & N1 & (N2 & N3);
assign N0 = ~reqs_i[1];
assign N1 = ~reqs_i[2];
assign N2 = ~reqs_i[0];
assign N3 = ~reqs_i[3];
assign N80 = reqs_i[1] & N4 & N5;
assign N4 = ~last_r[0];
assign N5 = ~last_r[1];
assign N81 = N6 & reqs_i[2] & (N7 & N8);
assign N6 = ~reqs_i[1];
assign N7 = ~last_r[0];
assign N8 = ~last_r[1];
assign N82 = N9 & N10 & (reqs_i[3] & N11) & N12;
assign N9 = ~reqs_i[1];
assign N10 = ~reqs_i[2];
assign N11 = ~last_r[0];
assign N12 = ~last_r[1];
assign N13 = N17 & N18;
assign N14 = N13 & reqs_i[0];
assign N15 = N14 & N19;
assign N16 = N15 & N20;
assign N83 = N16 & N21;
assign N17 = ~reqs_i[1];
assign N18 = ~reqs_i[2];
assign N19 = ~reqs_i[3];
assign N20 = ~last_r[0];
assign N21 = ~last_r[1];
assign N84 = reqs_i[2] & last_r[0] & N22;
assign N22 = ~last_r[1];
assign N85 = N23 & reqs_i[3] & (last_r[0] & N24);
assign N23 = ~reqs_i[2];
assign N24 = ~last_r[1];
assign N86 = N25 & reqs_i[0] & (N26 & last_r[0]) & N27;
assign N25 = ~reqs_i[2];
assign N26 = ~reqs_i[3];
assign N27 = ~last_r[1];
assign N28 = reqs_i[1] & N32;
assign N29 = N28 & N33;
assign N30 = N29 & N34;
assign N31 = N30 & last_r[0];
assign N87 = N31 & N35;
assign N32 = ~reqs_i[2];
assign N33 = ~reqs_i[0];
assign N34 = ~reqs_i[3];
assign N35 = ~last_r[1];
assign N88 = reqs_i[3] & N36 & last_r[1];
assign N36 = ~last_r[0];
assign N89 = reqs_i[0] & N37 & (N38 & last_r[1]);
assign N37 = ~reqs_i[3];
assign N38 = ~last_r[0];
assign N90 = reqs_i[1] & N39 & (N40 & N41) & last_r[1];
assign N39 = ~reqs_i[0];
assign N40 = ~reqs_i[3];
assign N41 = ~last_r[0];
assign N42 = N46 & reqs_i[2];
assign N43 = N42 & N47;
assign N44 = N43 & N48;
assign N45 = N44 & N49;
assign N91 = N45 & last_r[1];
assign N46 = ~reqs_i[1];
assign N47 = ~reqs_i[0];
assign N48 = ~reqs_i[3];
assign N49 = ~last_r[0];
assign N92 = reqs_i[0] & last_r[0] & last_r[1];
assign N93 = reqs_i[1] & N50 & (last_r[0] & last_r[1]);
assign N50 = ~reqs_i[0];
assign N94 = N51 & reqs_i[2] & (N52 & last_r[0]) & last_r[1];
assign N51 = ~reqs_i[1];
assign N52 = ~reqs_i[0];
assign N53 = N57 & N58;
assign N54 = N53 & N59;
assign N55 = N54 & reqs_i[3];
assign N56 = N55 & last_r[0];
assign N95 = N56 & last_r[1];
assign N57 = ~reqs_i[1];
assign N58 = ~reqs_i[2];
assign N59 = ~reqs_i[0];
assign sel_one_hot_o = (N60)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N62)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N63)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N64)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N65)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N66)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N67)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N68)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N69)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N70)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N71)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N72)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N73)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N74)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N75)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N76)? { 1'b1, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N60 = N79;
assign N61 = N80;
assign N62 = N81;
assign N63 = N82;
assign N64 = N83;
assign N65 = N84;
assign N66 = N85;
assign N67 = N86;
assign N68 = N87;
assign N69 = N88;
assign N70 = N89;
assign N71 = N90;
assign N72 = N91;
assign N73 = N92;
assign N74 = N93;
assign N75 = N94;
assign N76 = N95;
assign tag_o = (N60)? { 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b1 } :
(N62)? { 1'b1, 1'b0 } :
(N63)? { 1'b1, 1'b1 } :
(N64)? { 1'b0, 1'b0 } :
(N65)? { 1'b1, 1'b0 } :
(N66)? { 1'b1, 1'b1 } :
(N67)? { 1'b0, 1'b0 } :
(N68)? { 1'b0, 1'b1 } :
(N69)? { 1'b1, 1'b1 } :
(N70)? { 1'b0, 1'b0 } :
(N71)? { 1'b0, 1'b1 } :
(N72)? { 1'b1, 1'b0 } :
(N73)? { 1'b0, 1'b0 } :
(N74)? { 1'b0, 1'b1 } :
(N75)? { 1'b1, 1'b0 } :
(N76)? { 1'b1, 1'b1 } : 1'b0;
assign { N99, N98 } = (N77)? { 1'b0, 1'b0 } :
(N78)? tag_o : 1'b0;
assign N77 = reset_i;
assign N78 = N97;
assign grants_o[3] = sel_one_hot_o[3] & grants_en_i;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N103 | reqs_i[0];
assign N103 = N102 | reqs_i[1];
assign N102 = reqs_i[3] | reqs_i[2];
assign N96 = ~yumi_i;
assign N97 = ~reset_i;
assign N100 = N96 & N97;
assign N101 = ~N100;
always @(posedge clk_i) begin
if(N101) begin
{ last_r[1:0] } <= { N99, N98 };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p109_els_p8_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [2:0] w_addr_i;
input [108:0] w_data_i;
input [2:0] r_addr_i;
output [108:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [108:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53;
reg [871:0] mem;
assign r_data_o[108] = (N17)? mem[108] :
(N19)? mem[217] :
(N21)? mem[326] :
(N23)? mem[435] :
(N18)? mem[544] :
(N20)? mem[653] :
(N22)? mem[762] :
(N24)? mem[871] : 1'b0;
assign r_data_o[107] = (N17)? mem[107] :
(N19)? mem[216] :
(N21)? mem[325] :
(N23)? mem[434] :
(N18)? mem[543] :
(N20)? mem[652] :
(N22)? mem[761] :
(N24)? mem[870] : 1'b0;
assign r_data_o[106] = (N17)? mem[106] :
(N19)? mem[215] :
(N21)? mem[324] :
(N23)? mem[433] :
(N18)? mem[542] :
(N20)? mem[651] :
(N22)? mem[760] :
(N24)? mem[869] : 1'b0;
assign r_data_o[105] = (N17)? mem[105] :
(N19)? mem[214] :
(N21)? mem[323] :
(N23)? mem[432] :
(N18)? mem[541] :
(N20)? mem[650] :
(N22)? mem[759] :
(N24)? mem[868] : 1'b0;
assign r_data_o[104] = (N17)? mem[104] :
(N19)? mem[213] :
(N21)? mem[322] :
(N23)? mem[431] :
(N18)? mem[540] :
(N20)? mem[649] :
(N22)? mem[758] :
(N24)? mem[867] : 1'b0;
assign r_data_o[103] = (N17)? mem[103] :
(N19)? mem[212] :
(N21)? mem[321] :
(N23)? mem[430] :
(N18)? mem[539] :
(N20)? mem[648] :
(N22)? mem[757] :
(N24)? mem[866] : 1'b0;
assign r_data_o[102] = (N17)? mem[102] :
(N19)? mem[211] :
(N21)? mem[320] :
(N23)? mem[429] :
(N18)? mem[538] :
(N20)? mem[647] :
(N22)? mem[756] :
(N24)? mem[865] : 1'b0;
assign r_data_o[101] = (N17)? mem[101] :
(N19)? mem[210] :
(N21)? mem[319] :
(N23)? mem[428] :
(N18)? mem[537] :
(N20)? mem[646] :
(N22)? mem[755] :
(N24)? mem[864] : 1'b0;
assign r_data_o[100] = (N17)? mem[100] :
(N19)? mem[209] :
(N21)? mem[318] :
(N23)? mem[427] :
(N18)? mem[536] :
(N20)? mem[645] :
(N22)? mem[754] :
(N24)? mem[863] : 1'b0;
assign r_data_o[99] = (N17)? mem[99] :
(N19)? mem[208] :
(N21)? mem[317] :
(N23)? mem[426] :
(N18)? mem[535] :
(N20)? mem[644] :
(N22)? mem[753] :
(N24)? mem[862] : 1'b0;
assign r_data_o[98] = (N17)? mem[98] :
(N19)? mem[207] :
(N21)? mem[316] :
(N23)? mem[425] :
(N18)? mem[534] :
(N20)? mem[643] :
(N22)? mem[752] :
(N24)? mem[861] : 1'b0;
assign r_data_o[97] = (N17)? mem[97] :
(N19)? mem[206] :
(N21)? mem[315] :
(N23)? mem[424] :
(N18)? mem[533] :
(N20)? mem[642] :
(N22)? mem[751] :
(N24)? mem[860] : 1'b0;
assign r_data_o[96] = (N17)? mem[96] :
(N19)? mem[205] :
(N21)? mem[314] :
(N23)? mem[423] :
(N18)? mem[532] :
(N20)? mem[641] :
(N22)? mem[750] :
(N24)? mem[859] : 1'b0;
assign r_data_o[95] = (N17)? mem[95] :
(N19)? mem[204] :
(N21)? mem[313] :
(N23)? mem[422] :
(N18)? mem[531] :
(N20)? mem[640] :
(N22)? mem[749] :
(N24)? mem[858] : 1'b0;
assign r_data_o[94] = (N17)? mem[94] :
(N19)? mem[203] :
(N21)? mem[312] :
(N23)? mem[421] :
(N18)? mem[530] :
(N20)? mem[639] :
(N22)? mem[748] :
(N24)? mem[857] : 1'b0;
assign r_data_o[93] = (N17)? mem[93] :
(N19)? mem[202] :
(N21)? mem[311] :
(N23)? mem[420] :
(N18)? mem[529] :
(N20)? mem[638] :
(N22)? mem[747] :
(N24)? mem[856] : 1'b0;
assign r_data_o[92] = (N17)? mem[92] :
(N19)? mem[201] :
(N21)? mem[310] :
(N23)? mem[419] :
(N18)? mem[528] :
(N20)? mem[637] :
(N22)? mem[746] :
(N24)? mem[855] : 1'b0;
assign r_data_o[91] = (N17)? mem[91] :
(N19)? mem[200] :
(N21)? mem[309] :
(N23)? mem[418] :
(N18)? mem[527] :
(N20)? mem[636] :
(N22)? mem[745] :
(N24)? mem[854] : 1'b0;
assign r_data_o[90] = (N17)? mem[90] :
(N19)? mem[199] :
(N21)? mem[308] :
(N23)? mem[417] :
(N18)? mem[526] :
(N20)? mem[635] :
(N22)? mem[744] :
(N24)? mem[853] : 1'b0;
assign r_data_o[89] = (N17)? mem[89] :
(N19)? mem[198] :
(N21)? mem[307] :
(N23)? mem[416] :
(N18)? mem[525] :
(N20)? mem[634] :
(N22)? mem[743] :
(N24)? mem[852] : 1'b0;
assign r_data_o[88] = (N17)? mem[88] :
(N19)? mem[197] :
(N21)? mem[306] :
(N23)? mem[415] :
(N18)? mem[524] :
(N20)? mem[633] :
(N22)? mem[742] :
(N24)? mem[851] : 1'b0;
assign r_data_o[87] = (N17)? mem[87] :
(N19)? mem[196] :
(N21)? mem[305] :
(N23)? mem[414] :
(N18)? mem[523] :
(N20)? mem[632] :
(N22)? mem[741] :
(N24)? mem[850] : 1'b0;
assign r_data_o[86] = (N17)? mem[86] :
(N19)? mem[195] :
(N21)? mem[304] :
(N23)? mem[413] :
(N18)? mem[522] :
(N20)? mem[631] :
(N22)? mem[740] :
(N24)? mem[849] : 1'b0;
assign r_data_o[85] = (N17)? mem[85] :
(N19)? mem[194] :
(N21)? mem[303] :
(N23)? mem[412] :
(N18)? mem[521] :
(N20)? mem[630] :
(N22)? mem[739] :
(N24)? mem[848] : 1'b0;
assign r_data_o[84] = (N17)? mem[84] :
(N19)? mem[193] :
(N21)? mem[302] :
(N23)? mem[411] :
(N18)? mem[520] :
(N20)? mem[629] :
(N22)? mem[738] :
(N24)? mem[847] : 1'b0;
assign r_data_o[83] = (N17)? mem[83] :
(N19)? mem[192] :
(N21)? mem[301] :
(N23)? mem[410] :
(N18)? mem[519] :
(N20)? mem[628] :
(N22)? mem[737] :
(N24)? mem[846] : 1'b0;
assign r_data_o[82] = (N17)? mem[82] :
(N19)? mem[191] :
(N21)? mem[300] :
(N23)? mem[409] :
(N18)? mem[518] :
(N20)? mem[627] :
(N22)? mem[736] :
(N24)? mem[845] : 1'b0;
assign r_data_o[81] = (N17)? mem[81] :
(N19)? mem[190] :
(N21)? mem[299] :
(N23)? mem[408] :
(N18)? mem[517] :
(N20)? mem[626] :
(N22)? mem[735] :
(N24)? mem[844] : 1'b0;
assign r_data_o[80] = (N17)? mem[80] :
(N19)? mem[189] :
(N21)? mem[298] :
(N23)? mem[407] :
(N18)? mem[516] :
(N20)? mem[625] :
(N22)? mem[734] :
(N24)? mem[843] : 1'b0;
assign r_data_o[79] = (N17)? mem[79] :
(N19)? mem[188] :
(N21)? mem[297] :
(N23)? mem[406] :
(N18)? mem[515] :
(N20)? mem[624] :
(N22)? mem[733] :
(N24)? mem[842] : 1'b0;
assign r_data_o[78] = (N17)? mem[78] :
(N19)? mem[187] :
(N21)? mem[296] :
(N23)? mem[405] :
(N18)? mem[514] :
(N20)? mem[623] :
(N22)? mem[732] :
(N24)? mem[841] : 1'b0;
assign r_data_o[77] = (N17)? mem[77] :
(N19)? mem[186] :
(N21)? mem[295] :
(N23)? mem[404] :
(N18)? mem[513] :
(N20)? mem[622] :
(N22)? mem[731] :
(N24)? mem[840] : 1'b0;
assign r_data_o[76] = (N17)? mem[76] :
(N19)? mem[185] :
(N21)? mem[294] :
(N23)? mem[403] :
(N18)? mem[512] :
(N20)? mem[621] :
(N22)? mem[730] :
(N24)? mem[839] : 1'b0;
assign r_data_o[75] = (N17)? mem[75] :
(N19)? mem[184] :
(N21)? mem[293] :
(N23)? mem[402] :
(N18)? mem[511] :
(N20)? mem[620] :
(N22)? mem[729] :
(N24)? mem[838] : 1'b0;
assign r_data_o[74] = (N17)? mem[74] :
(N19)? mem[183] :
(N21)? mem[292] :
(N23)? mem[401] :
(N18)? mem[510] :
(N20)? mem[619] :
(N22)? mem[728] :
(N24)? mem[837] : 1'b0;
assign r_data_o[73] = (N17)? mem[73] :
(N19)? mem[182] :
(N21)? mem[291] :
(N23)? mem[400] :
(N18)? mem[509] :
(N20)? mem[618] :
(N22)? mem[727] :
(N24)? mem[836] : 1'b0;
assign r_data_o[72] = (N17)? mem[72] :
(N19)? mem[181] :
(N21)? mem[290] :
(N23)? mem[399] :
(N18)? mem[508] :
(N20)? mem[617] :
(N22)? mem[726] :
(N24)? mem[835] : 1'b0;
assign r_data_o[71] = (N17)? mem[71] :
(N19)? mem[180] :
(N21)? mem[289] :
(N23)? mem[398] :
(N18)? mem[507] :
(N20)? mem[616] :
(N22)? mem[725] :
(N24)? mem[834] : 1'b0;
assign r_data_o[70] = (N17)? mem[70] :
(N19)? mem[179] :
(N21)? mem[288] :
(N23)? mem[397] :
(N18)? mem[506] :
(N20)? mem[615] :
(N22)? mem[724] :
(N24)? mem[833] : 1'b0;
assign r_data_o[69] = (N17)? mem[69] :
(N19)? mem[178] :
(N21)? mem[287] :
(N23)? mem[396] :
(N18)? mem[505] :
(N20)? mem[614] :
(N22)? mem[723] :
(N24)? mem[832] : 1'b0;
assign r_data_o[68] = (N17)? mem[68] :
(N19)? mem[177] :
(N21)? mem[286] :
(N23)? mem[395] :
(N18)? mem[504] :
(N20)? mem[613] :
(N22)? mem[722] :
(N24)? mem[831] : 1'b0;
assign r_data_o[67] = (N17)? mem[67] :
(N19)? mem[176] :
(N21)? mem[285] :
(N23)? mem[394] :
(N18)? mem[503] :
(N20)? mem[612] :
(N22)? mem[721] :
(N24)? mem[830] : 1'b0;
assign r_data_o[66] = (N17)? mem[66] :
(N19)? mem[175] :
(N21)? mem[284] :
(N23)? mem[393] :
(N18)? mem[502] :
(N20)? mem[611] :
(N22)? mem[720] :
(N24)? mem[829] : 1'b0;
assign r_data_o[65] = (N17)? mem[65] :
(N19)? mem[174] :
(N21)? mem[283] :
(N23)? mem[392] :
(N18)? mem[501] :
(N20)? mem[610] :
(N22)? mem[719] :
(N24)? mem[828] : 1'b0;
assign r_data_o[64] = (N17)? mem[64] :
(N19)? mem[173] :
(N21)? mem[282] :
(N23)? mem[391] :
(N18)? mem[500] :
(N20)? mem[609] :
(N22)? mem[718] :
(N24)? mem[827] : 1'b0;
assign r_data_o[63] = (N17)? mem[63] :
(N19)? mem[172] :
(N21)? mem[281] :
(N23)? mem[390] :
(N18)? mem[499] :
(N20)? mem[608] :
(N22)? mem[717] :
(N24)? mem[826] : 1'b0;
assign r_data_o[62] = (N17)? mem[62] :
(N19)? mem[171] :
(N21)? mem[280] :
(N23)? mem[389] :
(N18)? mem[498] :
(N20)? mem[607] :
(N22)? mem[716] :
(N24)? mem[825] : 1'b0;
assign r_data_o[61] = (N17)? mem[61] :
(N19)? mem[170] :
(N21)? mem[279] :
(N23)? mem[388] :
(N18)? mem[497] :
(N20)? mem[606] :
(N22)? mem[715] :
(N24)? mem[824] : 1'b0;
assign r_data_o[60] = (N17)? mem[60] :
(N19)? mem[169] :
(N21)? mem[278] :
(N23)? mem[387] :
(N18)? mem[496] :
(N20)? mem[605] :
(N22)? mem[714] :
(N24)? mem[823] : 1'b0;
assign r_data_o[59] = (N17)? mem[59] :
(N19)? mem[168] :
(N21)? mem[277] :
(N23)? mem[386] :
(N18)? mem[495] :
(N20)? mem[604] :
(N22)? mem[713] :
(N24)? mem[822] : 1'b0;
assign r_data_o[58] = (N17)? mem[58] :
(N19)? mem[167] :
(N21)? mem[276] :
(N23)? mem[385] :
(N18)? mem[494] :
(N20)? mem[603] :
(N22)? mem[712] :
(N24)? mem[821] : 1'b0;
assign r_data_o[57] = (N17)? mem[57] :
(N19)? mem[166] :
(N21)? mem[275] :
(N23)? mem[384] :
(N18)? mem[493] :
(N20)? mem[602] :
(N22)? mem[711] :
(N24)? mem[820] : 1'b0;
assign r_data_o[56] = (N17)? mem[56] :
(N19)? mem[165] :
(N21)? mem[274] :
(N23)? mem[383] :
(N18)? mem[492] :
(N20)? mem[601] :
(N22)? mem[710] :
(N24)? mem[819] : 1'b0;
assign r_data_o[55] = (N17)? mem[55] :
(N19)? mem[164] :
(N21)? mem[273] :
(N23)? mem[382] :
(N18)? mem[491] :
(N20)? mem[600] :
(N22)? mem[709] :
(N24)? mem[818] : 1'b0;
assign r_data_o[54] = (N17)? mem[54] :
(N19)? mem[163] :
(N21)? mem[272] :
(N23)? mem[381] :
(N18)? mem[490] :
(N20)? mem[599] :
(N22)? mem[708] :
(N24)? mem[817] : 1'b0;
assign r_data_o[53] = (N17)? mem[53] :
(N19)? mem[162] :
(N21)? mem[271] :
(N23)? mem[380] :
(N18)? mem[489] :
(N20)? mem[598] :
(N22)? mem[707] :
(N24)? mem[816] : 1'b0;
assign r_data_o[52] = (N17)? mem[52] :
(N19)? mem[161] :
(N21)? mem[270] :
(N23)? mem[379] :
(N18)? mem[488] :
(N20)? mem[597] :
(N22)? mem[706] :
(N24)? mem[815] : 1'b0;
assign r_data_o[51] = (N17)? mem[51] :
(N19)? mem[160] :
(N21)? mem[269] :
(N23)? mem[378] :
(N18)? mem[487] :
(N20)? mem[596] :
(N22)? mem[705] :
(N24)? mem[814] : 1'b0;
assign r_data_o[50] = (N17)? mem[50] :
(N19)? mem[159] :
(N21)? mem[268] :
(N23)? mem[377] :
(N18)? mem[486] :
(N20)? mem[595] :
(N22)? mem[704] :
(N24)? mem[813] : 1'b0;
assign r_data_o[49] = (N17)? mem[49] :
(N19)? mem[158] :
(N21)? mem[267] :
(N23)? mem[376] :
(N18)? mem[485] :
(N20)? mem[594] :
(N22)? mem[703] :
(N24)? mem[812] : 1'b0;
assign r_data_o[48] = (N17)? mem[48] :
(N19)? mem[157] :
(N21)? mem[266] :
(N23)? mem[375] :
(N18)? mem[484] :
(N20)? mem[593] :
(N22)? mem[702] :
(N24)? mem[811] : 1'b0;
assign r_data_o[47] = (N17)? mem[47] :
(N19)? mem[156] :
(N21)? mem[265] :
(N23)? mem[374] :
(N18)? mem[483] :
(N20)? mem[592] :
(N22)? mem[701] :
(N24)? mem[810] : 1'b0;
assign r_data_o[46] = (N17)? mem[46] :
(N19)? mem[155] :
(N21)? mem[264] :
(N23)? mem[373] :
(N18)? mem[482] :
(N20)? mem[591] :
(N22)? mem[700] :
(N24)? mem[809] : 1'b0;
assign r_data_o[45] = (N17)? mem[45] :
(N19)? mem[154] :
(N21)? mem[263] :
(N23)? mem[372] :
(N18)? mem[481] :
(N20)? mem[590] :
(N22)? mem[699] :
(N24)? mem[808] : 1'b0;
assign r_data_o[44] = (N17)? mem[44] :
(N19)? mem[153] :
(N21)? mem[262] :
(N23)? mem[371] :
(N18)? mem[480] :
(N20)? mem[589] :
(N22)? mem[698] :
(N24)? mem[807] : 1'b0;
assign r_data_o[43] = (N17)? mem[43] :
(N19)? mem[152] :
(N21)? mem[261] :
(N23)? mem[370] :
(N18)? mem[479] :
(N20)? mem[588] :
(N22)? mem[697] :
(N24)? mem[806] : 1'b0;
assign r_data_o[42] = (N17)? mem[42] :
(N19)? mem[151] :
(N21)? mem[260] :
(N23)? mem[369] :
(N18)? mem[478] :
(N20)? mem[587] :
(N22)? mem[696] :
(N24)? mem[805] : 1'b0;
assign r_data_o[41] = (N17)? mem[41] :
(N19)? mem[150] :
(N21)? mem[259] :
(N23)? mem[368] :
(N18)? mem[477] :
(N20)? mem[586] :
(N22)? mem[695] :
(N24)? mem[804] : 1'b0;
assign r_data_o[40] = (N17)? mem[40] :
(N19)? mem[149] :
(N21)? mem[258] :
(N23)? mem[367] :
(N18)? mem[476] :
(N20)? mem[585] :
(N22)? mem[694] :
(N24)? mem[803] : 1'b0;
assign r_data_o[39] = (N17)? mem[39] :
(N19)? mem[148] :
(N21)? mem[257] :
(N23)? mem[366] :
(N18)? mem[475] :
(N20)? mem[584] :
(N22)? mem[693] :
(N24)? mem[802] : 1'b0;
assign r_data_o[38] = (N17)? mem[38] :
(N19)? mem[147] :
(N21)? mem[256] :
(N23)? mem[365] :
(N18)? mem[474] :
(N20)? mem[583] :
(N22)? mem[692] :
(N24)? mem[801] : 1'b0;
assign r_data_o[37] = (N17)? mem[37] :
(N19)? mem[146] :
(N21)? mem[255] :
(N23)? mem[364] :
(N18)? mem[473] :
(N20)? mem[582] :
(N22)? mem[691] :
(N24)? mem[800] : 1'b0;
assign r_data_o[36] = (N17)? mem[36] :
(N19)? mem[145] :
(N21)? mem[254] :
(N23)? mem[363] :
(N18)? mem[472] :
(N20)? mem[581] :
(N22)? mem[690] :
(N24)? mem[799] : 1'b0;
assign r_data_o[35] = (N17)? mem[35] :
(N19)? mem[144] :
(N21)? mem[253] :
(N23)? mem[362] :
(N18)? mem[471] :
(N20)? mem[580] :
(N22)? mem[689] :
(N24)? mem[798] : 1'b0;
assign r_data_o[34] = (N17)? mem[34] :
(N19)? mem[143] :
(N21)? mem[252] :
(N23)? mem[361] :
(N18)? mem[470] :
(N20)? mem[579] :
(N22)? mem[688] :
(N24)? mem[797] : 1'b0;
assign r_data_o[33] = (N17)? mem[33] :
(N19)? mem[142] :
(N21)? mem[251] :
(N23)? mem[360] :
(N18)? mem[469] :
(N20)? mem[578] :
(N22)? mem[687] :
(N24)? mem[796] : 1'b0;
assign r_data_o[32] = (N17)? mem[32] :
(N19)? mem[141] :
(N21)? mem[250] :
(N23)? mem[359] :
(N18)? mem[468] :
(N20)? mem[577] :
(N22)? mem[686] :
(N24)? mem[795] : 1'b0;
assign r_data_o[31] = (N17)? mem[31] :
(N19)? mem[140] :
(N21)? mem[249] :
(N23)? mem[358] :
(N18)? mem[467] :
(N20)? mem[576] :
(N22)? mem[685] :
(N24)? mem[794] : 1'b0;
assign r_data_o[30] = (N17)? mem[30] :
(N19)? mem[139] :
(N21)? mem[248] :
(N23)? mem[357] :
(N18)? mem[466] :
(N20)? mem[575] :
(N22)? mem[684] :
(N24)? mem[793] : 1'b0;
assign r_data_o[29] = (N17)? mem[29] :
(N19)? mem[138] :
(N21)? mem[247] :
(N23)? mem[356] :
(N18)? mem[465] :
(N20)? mem[574] :
(N22)? mem[683] :
(N24)? mem[792] : 1'b0;
assign r_data_o[28] = (N17)? mem[28] :
(N19)? mem[137] :
(N21)? mem[246] :
(N23)? mem[355] :
(N18)? mem[464] :
(N20)? mem[573] :
(N22)? mem[682] :
(N24)? mem[791] : 1'b0;
assign r_data_o[27] = (N17)? mem[27] :
(N19)? mem[136] :
(N21)? mem[245] :
(N23)? mem[354] :
(N18)? mem[463] :
(N20)? mem[572] :
(N22)? mem[681] :
(N24)? mem[790] : 1'b0;
assign r_data_o[26] = (N17)? mem[26] :
(N19)? mem[135] :
(N21)? mem[244] :
(N23)? mem[353] :
(N18)? mem[462] :
(N20)? mem[571] :
(N22)? mem[680] :
(N24)? mem[789] : 1'b0;
assign r_data_o[25] = (N17)? mem[25] :
(N19)? mem[134] :
(N21)? mem[243] :
(N23)? mem[352] :
(N18)? mem[461] :
(N20)? mem[570] :
(N22)? mem[679] :
(N24)? mem[788] : 1'b0;
assign r_data_o[24] = (N17)? mem[24] :
(N19)? mem[133] :
(N21)? mem[242] :
(N23)? mem[351] :
(N18)? mem[460] :
(N20)? mem[569] :
(N22)? mem[678] :
(N24)? mem[787] : 1'b0;
assign r_data_o[23] = (N17)? mem[23] :
(N19)? mem[132] :
(N21)? mem[241] :
(N23)? mem[350] :
(N18)? mem[459] :
(N20)? mem[568] :
(N22)? mem[677] :
(N24)? mem[786] : 1'b0;
assign r_data_o[22] = (N17)? mem[22] :
(N19)? mem[131] :
(N21)? mem[240] :
(N23)? mem[349] :
(N18)? mem[458] :
(N20)? mem[567] :
(N22)? mem[676] :
(N24)? mem[785] : 1'b0;
assign r_data_o[21] = (N17)? mem[21] :
(N19)? mem[130] :
(N21)? mem[239] :
(N23)? mem[348] :
(N18)? mem[457] :
(N20)? mem[566] :
(N22)? mem[675] :
(N24)? mem[784] : 1'b0;
assign r_data_o[20] = (N17)? mem[20] :
(N19)? mem[129] :
(N21)? mem[238] :
(N23)? mem[347] :
(N18)? mem[456] :
(N20)? mem[565] :
(N22)? mem[674] :
(N24)? mem[783] : 1'b0;
assign r_data_o[19] = (N17)? mem[19] :
(N19)? mem[128] :
(N21)? mem[237] :
(N23)? mem[346] :
(N18)? mem[455] :
(N20)? mem[564] :
(N22)? mem[673] :
(N24)? mem[782] : 1'b0;
assign r_data_o[18] = (N17)? mem[18] :
(N19)? mem[127] :
(N21)? mem[236] :
(N23)? mem[345] :
(N18)? mem[454] :
(N20)? mem[563] :
(N22)? mem[672] :
(N24)? mem[781] : 1'b0;
assign r_data_o[17] = (N17)? mem[17] :
(N19)? mem[126] :
(N21)? mem[235] :
(N23)? mem[344] :
(N18)? mem[453] :
(N20)? mem[562] :
(N22)? mem[671] :
(N24)? mem[780] : 1'b0;
assign r_data_o[16] = (N17)? mem[16] :
(N19)? mem[125] :
(N21)? mem[234] :
(N23)? mem[343] :
(N18)? mem[452] :
(N20)? mem[561] :
(N22)? mem[670] :
(N24)? mem[779] : 1'b0;
assign r_data_o[15] = (N17)? mem[15] :
(N19)? mem[124] :
(N21)? mem[233] :
(N23)? mem[342] :
(N18)? mem[451] :
(N20)? mem[560] :
(N22)? mem[669] :
(N24)? mem[778] : 1'b0;
assign r_data_o[14] = (N17)? mem[14] :
(N19)? mem[123] :
(N21)? mem[232] :
(N23)? mem[341] :
(N18)? mem[450] :
(N20)? mem[559] :
(N22)? mem[668] :
(N24)? mem[777] : 1'b0;
assign r_data_o[13] = (N17)? mem[13] :
(N19)? mem[122] :
(N21)? mem[231] :
(N23)? mem[340] :
(N18)? mem[449] :
(N20)? mem[558] :
(N22)? mem[667] :
(N24)? mem[776] : 1'b0;
assign r_data_o[12] = (N17)? mem[12] :
(N19)? mem[121] :
(N21)? mem[230] :
(N23)? mem[339] :
(N18)? mem[448] :
(N20)? mem[557] :
(N22)? mem[666] :
(N24)? mem[775] : 1'b0;
assign r_data_o[11] = (N17)? mem[11] :
(N19)? mem[120] :
(N21)? mem[229] :
(N23)? mem[338] :
(N18)? mem[447] :
(N20)? mem[556] :
(N22)? mem[665] :
(N24)? mem[774] : 1'b0;
assign r_data_o[10] = (N17)? mem[10] :
(N19)? mem[119] :
(N21)? mem[228] :
(N23)? mem[337] :
(N18)? mem[446] :
(N20)? mem[555] :
(N22)? mem[664] :
(N24)? mem[773] : 1'b0;
assign r_data_o[9] = (N17)? mem[9] :
(N19)? mem[118] :
(N21)? mem[227] :
(N23)? mem[336] :
(N18)? mem[445] :
(N20)? mem[554] :
(N22)? mem[663] :
(N24)? mem[772] : 1'b0;
assign r_data_o[8] = (N17)? mem[8] :
(N19)? mem[117] :
(N21)? mem[226] :
(N23)? mem[335] :
(N18)? mem[444] :
(N20)? mem[553] :
(N22)? mem[662] :
(N24)? mem[771] : 1'b0;
assign r_data_o[7] = (N17)? mem[7] :
(N19)? mem[116] :
(N21)? mem[225] :
(N23)? mem[334] :
(N18)? mem[443] :
(N20)? mem[552] :
(N22)? mem[661] :
(N24)? mem[770] : 1'b0;
assign r_data_o[6] = (N17)? mem[6] :
(N19)? mem[115] :
(N21)? mem[224] :
(N23)? mem[333] :
(N18)? mem[442] :
(N20)? mem[551] :
(N22)? mem[660] :
(N24)? mem[769] : 1'b0;
assign r_data_o[5] = (N17)? mem[5] :
(N19)? mem[114] :
(N21)? mem[223] :
(N23)? mem[332] :
(N18)? mem[441] :
(N20)? mem[550] :
(N22)? mem[659] :
(N24)? mem[768] : 1'b0;
assign r_data_o[4] = (N17)? mem[4] :
(N19)? mem[113] :
(N21)? mem[222] :
(N23)? mem[331] :
(N18)? mem[440] :
(N20)? mem[549] :
(N22)? mem[658] :
(N24)? mem[767] : 1'b0;
assign r_data_o[3] = (N17)? mem[3] :
(N19)? mem[112] :
(N21)? mem[221] :
(N23)? mem[330] :
(N18)? mem[439] :
(N20)? mem[548] :
(N22)? mem[657] :
(N24)? mem[766] : 1'b0;
assign r_data_o[2] = (N17)? mem[2] :
(N19)? mem[111] :
(N21)? mem[220] :
(N23)? mem[329] :
(N18)? mem[438] :
(N20)? mem[547] :
(N22)? mem[656] :
(N24)? mem[765] : 1'b0;
assign r_data_o[1] = (N17)? mem[1] :
(N19)? mem[110] :
(N21)? mem[219] :
(N23)? mem[328] :
(N18)? mem[437] :
(N20)? mem[546] :
(N22)? mem[655] :
(N24)? mem[764] : 1'b0;
assign r_data_o[0] = (N17)? mem[0] :
(N19)? mem[109] :
(N21)? mem[218] :
(N23)? mem[327] :
(N18)? mem[436] :
(N20)? mem[545] :
(N22)? mem[654] :
(N24)? mem[763] : 1'b0;
assign N50 = w_addr_i[0] & w_addr_i[1];
assign N33 = N50 & w_addr_i[2];
assign N51 = N0 & w_addr_i[1];
assign N0 = ~w_addr_i[0];
assign N32 = N51 & w_addr_i[2];
assign N52 = w_addr_i[0] & N1;
assign N1 = ~w_addr_i[1];
assign N31 = N52 & w_addr_i[2];
assign N53 = N2 & N3;
assign N2 = ~w_addr_i[0];
assign N3 = ~w_addr_i[1];
assign N30 = N53 & w_addr_i[2];
assign N29 = N50 & N4;
assign N4 = ~w_addr_i[2];
assign N28 = N51 & N5;
assign N5 = ~w_addr_i[2];
assign N27 = N52 & N6;
assign N6 = ~w_addr_i[2];
assign N26 = N53 & N7;
assign N7 = ~w_addr_i[2];
assign { N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34 } = (N8)? { N33, N33, N32, N32, N31, N31, N30, N30, N29, N29, N28, N28, N27, N27, N26, N26 } :
(N9)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = w_v_i;
assign N9 = N25;
assign N10 = ~r_addr_i[0];
assign N11 = ~r_addr_i[1];
assign N12 = N10 & N11;
assign N13 = N10 & r_addr_i[1];
assign N14 = r_addr_i[0] & N11;
assign N15 = r_addr_i[0] & r_addr_i[1];
assign N16 = ~r_addr_i[2];
assign N17 = N12 & N16;
assign N18 = N12 & r_addr_i[2];
assign N19 = N14 & N16;
assign N20 = N14 & r_addr_i[2];
assign N21 = N13 & N16;
assign N22 = N13 & r_addr_i[2];
assign N23 = N15 & N16;
assign N24 = N15 & r_addr_i[2];
assign N25 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N48) begin
{ mem[871:773], mem[763:763] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N49) begin
{ mem[772:764] } <= { w_data_i[9:1] };
end
if(N46) begin
{ mem[762:664], mem[654:654] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N47) begin
{ mem[663:655] } <= { w_data_i[9:1] };
end
if(N44) begin
{ mem[653:555], mem[545:545] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N45) begin
{ mem[554:546] } <= { w_data_i[9:1] };
end
if(N42) begin
{ mem[544:446], mem[436:436] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N43) begin
{ mem[445:437] } <= { w_data_i[9:1] };
end
if(N40) begin
{ mem[435:337], mem[327:327] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N41) begin
{ mem[336:328] } <= { w_data_i[9:1] };
end
if(N38) begin
{ mem[326:228], mem[218:218] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N39) begin
{ mem[227:219] } <= { w_data_i[9:1] };
end
if(N36) begin
{ mem[217:119], mem[109:109] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N37) begin
{ mem[118:110] } <= { w_data_i[9:1] };
end
if(N34) begin
{ mem[108:10], mem[0:0] } <= { w_data_i[108:10], w_data_i[0:0] };
end
if(N35) begin
{ mem[9:1] } <= { w_data_i[9:1] };
end
end
endmodule |
module bsg_mux_one_hot_width_p64_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [319:0] data_i;
input [4:0] sel_one_hot_i;
output [63:0] data_o;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191;
wire [319:0] data_masked;
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[127] = data_i[127] & sel_one_hot_i[1];
assign data_masked[126] = data_i[126] & sel_one_hot_i[1];
assign data_masked[125] = data_i[125] & sel_one_hot_i[1];
assign data_masked[124] = data_i[124] & sel_one_hot_i[1];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[2];
assign data_masked[190] = data_i[190] & sel_one_hot_i[2];
assign data_masked[189] = data_i[189] & sel_one_hot_i[2];
assign data_masked[188] = data_i[188] & sel_one_hot_i[2];
assign data_masked[187] = data_i[187] & sel_one_hot_i[2];
assign data_masked[186] = data_i[186] & sel_one_hot_i[2];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[2];
assign data_masked[150] = data_i[150] & sel_one_hot_i[2];
assign data_masked[149] = data_i[149] & sel_one_hot_i[2];
assign data_masked[148] = data_i[148] & sel_one_hot_i[2];
assign data_masked[147] = data_i[147] & sel_one_hot_i[2];
assign data_masked[146] = data_i[146] & sel_one_hot_i[2];
assign data_masked[145] = data_i[145] & sel_one_hot_i[2];
assign data_masked[144] = data_i[144] & sel_one_hot_i[2];
assign data_masked[143] = data_i[143] & sel_one_hot_i[2];
assign data_masked[142] = data_i[142] & sel_one_hot_i[2];
assign data_masked[141] = data_i[141] & sel_one_hot_i[2];
assign data_masked[140] = data_i[140] & sel_one_hot_i[2];
assign data_masked[139] = data_i[139] & sel_one_hot_i[2];
assign data_masked[138] = data_i[138] & sel_one_hot_i[2];
assign data_masked[137] = data_i[137] & sel_one_hot_i[2];
assign data_masked[136] = data_i[136] & sel_one_hot_i[2];
assign data_masked[135] = data_i[135] & sel_one_hot_i[2];
assign data_masked[134] = data_i[134] & sel_one_hot_i[2];
assign data_masked[133] = data_i[133] & sel_one_hot_i[2];
assign data_masked[132] = data_i[132] & sel_one_hot_i[2];
assign data_masked[131] = data_i[131] & sel_one_hot_i[2];
assign data_masked[130] = data_i[130] & sel_one_hot_i[2];
assign data_masked[129] = data_i[129] & sel_one_hot_i[2];
assign data_masked[128] = data_i[128] & sel_one_hot_i[2];
assign data_masked[255] = data_i[255] & sel_one_hot_i[3];
assign data_masked[254] = data_i[254] & sel_one_hot_i[3];
assign data_masked[253] = data_i[253] & sel_one_hot_i[3];
assign data_masked[252] = data_i[252] & sel_one_hot_i[3];
assign data_masked[251] = data_i[251] & sel_one_hot_i[3];
assign data_masked[250] = data_i[250] & sel_one_hot_i[3];
assign data_masked[249] = data_i[249] & sel_one_hot_i[3];
assign data_masked[248] = data_i[248] & sel_one_hot_i[3];
assign data_masked[247] = data_i[247] & sel_one_hot_i[3];
assign data_masked[246] = data_i[246] & sel_one_hot_i[3];
assign data_masked[245] = data_i[245] & sel_one_hot_i[3];
assign data_masked[244] = data_i[244] & sel_one_hot_i[3];
assign data_masked[243] = data_i[243] & sel_one_hot_i[3];
assign data_masked[242] = data_i[242] & sel_one_hot_i[3];
assign data_masked[241] = data_i[241] & sel_one_hot_i[3];
assign data_masked[240] = data_i[240] & sel_one_hot_i[3];
assign data_masked[239] = data_i[239] & sel_one_hot_i[3];
assign data_masked[238] = data_i[238] & sel_one_hot_i[3];
assign data_masked[237] = data_i[237] & sel_one_hot_i[3];
assign data_masked[236] = data_i[236] & sel_one_hot_i[3];
assign data_masked[235] = data_i[235] & sel_one_hot_i[3];
assign data_masked[234] = data_i[234] & sel_one_hot_i[3];
assign data_masked[233] = data_i[233] & sel_one_hot_i[3];
assign data_masked[232] = data_i[232] & sel_one_hot_i[3];
assign data_masked[231] = data_i[231] & sel_one_hot_i[3];
assign data_masked[230] = data_i[230] & sel_one_hot_i[3];
assign data_masked[229] = data_i[229] & sel_one_hot_i[3];
assign data_masked[228] = data_i[228] & sel_one_hot_i[3];
assign data_masked[227] = data_i[227] & sel_one_hot_i[3];
assign data_masked[226] = data_i[226] & sel_one_hot_i[3];
assign data_masked[225] = data_i[225] & sel_one_hot_i[3];
assign data_masked[224] = data_i[224] & sel_one_hot_i[3];
assign data_masked[223] = data_i[223] & sel_one_hot_i[3];
assign data_masked[222] = data_i[222] & sel_one_hot_i[3];
assign data_masked[221] = data_i[221] & sel_one_hot_i[3];
assign data_masked[220] = data_i[220] & sel_one_hot_i[3];
assign data_masked[219] = data_i[219] & sel_one_hot_i[3];
assign data_masked[218] = data_i[218] & sel_one_hot_i[3];
assign data_masked[217] = data_i[217] & sel_one_hot_i[3];
assign data_masked[216] = data_i[216] & sel_one_hot_i[3];
assign data_masked[215] = data_i[215] & sel_one_hot_i[3];
assign data_masked[214] = data_i[214] & sel_one_hot_i[3];
assign data_masked[213] = data_i[213] & sel_one_hot_i[3];
assign data_masked[212] = data_i[212] & sel_one_hot_i[3];
assign data_masked[211] = data_i[211] & sel_one_hot_i[3];
assign data_masked[210] = data_i[210] & sel_one_hot_i[3];
assign data_masked[209] = data_i[209] & sel_one_hot_i[3];
assign data_masked[208] = data_i[208] & sel_one_hot_i[3];
assign data_masked[207] = data_i[207] & sel_one_hot_i[3];
assign data_masked[206] = data_i[206] & sel_one_hot_i[3];
assign data_masked[205] = data_i[205] & sel_one_hot_i[3];
assign data_masked[204] = data_i[204] & sel_one_hot_i[3];
assign data_masked[203] = data_i[203] & sel_one_hot_i[3];
assign data_masked[202] = data_i[202] & sel_one_hot_i[3];
assign data_masked[201] = data_i[201] & sel_one_hot_i[3];
assign data_masked[200] = data_i[200] & sel_one_hot_i[3];
assign data_masked[199] = data_i[199] & sel_one_hot_i[3];
assign data_masked[198] = data_i[198] & sel_one_hot_i[3];
assign data_masked[197] = data_i[197] & sel_one_hot_i[3];
assign data_masked[196] = data_i[196] & sel_one_hot_i[3];
assign data_masked[195] = data_i[195] & sel_one_hot_i[3];
assign data_masked[194] = data_i[194] & sel_one_hot_i[3];
assign data_masked[193] = data_i[193] & sel_one_hot_i[3];
assign data_masked[192] = data_i[192] & sel_one_hot_i[3];
assign data_masked[319] = data_i[319] & sel_one_hot_i[4];
assign data_masked[318] = data_i[318] & sel_one_hot_i[4];
assign data_masked[317] = data_i[317] & sel_one_hot_i[4];
assign data_masked[316] = data_i[316] & sel_one_hot_i[4];
assign data_masked[315] = data_i[315] & sel_one_hot_i[4];
assign data_masked[314] = data_i[314] & sel_one_hot_i[4];
assign data_masked[313] = data_i[313] & sel_one_hot_i[4];
assign data_masked[312] = data_i[312] & sel_one_hot_i[4];
assign data_masked[311] = data_i[311] & sel_one_hot_i[4];
assign data_masked[310] = data_i[310] & sel_one_hot_i[4];
assign data_masked[309] = data_i[309] & sel_one_hot_i[4];
assign data_masked[308] = data_i[308] & sel_one_hot_i[4];
assign data_masked[307] = data_i[307] & sel_one_hot_i[4];
assign data_masked[306] = data_i[306] & sel_one_hot_i[4];
assign data_masked[305] = data_i[305] & sel_one_hot_i[4];
assign data_masked[304] = data_i[304] & sel_one_hot_i[4];
assign data_masked[303] = data_i[303] & sel_one_hot_i[4];
assign data_masked[302] = data_i[302] & sel_one_hot_i[4];
assign data_masked[301] = data_i[301] & sel_one_hot_i[4];
assign data_masked[300] = data_i[300] & sel_one_hot_i[4];
assign data_masked[299] = data_i[299] & sel_one_hot_i[4];
assign data_masked[298] = data_i[298] & sel_one_hot_i[4];
assign data_masked[297] = data_i[297] & sel_one_hot_i[4];
assign data_masked[296] = data_i[296] & sel_one_hot_i[4];
assign data_masked[295] = data_i[295] & sel_one_hot_i[4];
assign data_masked[294] = data_i[294] & sel_one_hot_i[4];
assign data_masked[293] = data_i[293] & sel_one_hot_i[4];
assign data_masked[292] = data_i[292] & sel_one_hot_i[4];
assign data_masked[291] = data_i[291] & sel_one_hot_i[4];
assign data_masked[290] = data_i[290] & sel_one_hot_i[4];
assign data_masked[289] = data_i[289] & sel_one_hot_i[4];
assign data_masked[288] = data_i[288] & sel_one_hot_i[4];
assign data_masked[287] = data_i[287] & sel_one_hot_i[4];
assign data_masked[286] = data_i[286] & sel_one_hot_i[4];
assign data_masked[285] = data_i[285] & sel_one_hot_i[4];
assign data_masked[284] = data_i[284] & sel_one_hot_i[4];
assign data_masked[283] = data_i[283] & sel_one_hot_i[4];
assign data_masked[282] = data_i[282] & sel_one_hot_i[4];
assign data_masked[281] = data_i[281] & sel_one_hot_i[4];
assign data_masked[280] = data_i[280] & sel_one_hot_i[4];
assign data_masked[279] = data_i[279] & sel_one_hot_i[4];
assign data_masked[278] = data_i[278] & sel_one_hot_i[4];
assign data_masked[277] = data_i[277] & sel_one_hot_i[4];
assign data_masked[276] = data_i[276] & sel_one_hot_i[4];
assign data_masked[275] = data_i[275] & sel_one_hot_i[4];
assign data_masked[274] = data_i[274] & sel_one_hot_i[4];
assign data_masked[273] = data_i[273] & sel_one_hot_i[4];
assign data_masked[272] = data_i[272] & sel_one_hot_i[4];
assign data_masked[271] = data_i[271] & sel_one_hot_i[4];
assign data_masked[270] = data_i[270] & sel_one_hot_i[4];
assign data_masked[269] = data_i[269] & sel_one_hot_i[4];
assign data_masked[268] = data_i[268] & sel_one_hot_i[4];
assign data_masked[267] = data_i[267] & sel_one_hot_i[4];
assign data_masked[266] = data_i[266] & sel_one_hot_i[4];
assign data_masked[265] = data_i[265] & sel_one_hot_i[4];
assign data_masked[264] = data_i[264] & sel_one_hot_i[4];
assign data_masked[263] = data_i[263] & sel_one_hot_i[4];
assign data_masked[262] = data_i[262] & sel_one_hot_i[4];
assign data_masked[261] = data_i[261] & sel_one_hot_i[4];
assign data_masked[260] = data_i[260] & sel_one_hot_i[4];
assign data_masked[259] = data_i[259] & sel_one_hot_i[4];
assign data_masked[258] = data_i[258] & sel_one_hot_i[4];
assign data_masked[257] = data_i[257] & sel_one_hot_i[4];
assign data_masked[256] = data_i[256] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[64];
assign N1 = N0 | data_masked[128];
assign N0 = data_masked[256] | data_masked[192];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[65];
assign N4 = N3 | data_masked[129];
assign N3 = data_masked[257] | data_masked[193];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[66];
assign N7 = N6 | data_masked[130];
assign N6 = data_masked[258] | data_masked[194];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[67];
assign N10 = N9 | data_masked[131];
assign N9 = data_masked[259] | data_masked[195];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[68];
assign N13 = N12 | data_masked[132];
assign N12 = data_masked[260] | data_masked[196];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[69];
assign N16 = N15 | data_masked[133];
assign N15 = data_masked[261] | data_masked[197];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[70];
assign N19 = N18 | data_masked[134];
assign N18 = data_masked[262] | data_masked[198];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[71];
assign N22 = N21 | data_masked[135];
assign N21 = data_masked[263] | data_masked[199];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[72];
assign N25 = N24 | data_masked[136];
assign N24 = data_masked[264] | data_masked[200];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[73];
assign N28 = N27 | data_masked[137];
assign N27 = data_masked[265] | data_masked[201];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[74];
assign N31 = N30 | data_masked[138];
assign N30 = data_masked[266] | data_masked[202];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[75];
assign N34 = N33 | data_masked[139];
assign N33 = data_masked[267] | data_masked[203];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[76];
assign N37 = N36 | data_masked[140];
assign N36 = data_masked[268] | data_masked[204];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[77];
assign N40 = N39 | data_masked[141];
assign N39 = data_masked[269] | data_masked[205];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[78];
assign N43 = N42 | data_masked[142];
assign N42 = data_masked[270] | data_masked[206];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[79];
assign N46 = N45 | data_masked[143];
assign N45 = data_masked[271] | data_masked[207];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[80];
assign N49 = N48 | data_masked[144];
assign N48 = data_masked[272] | data_masked[208];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[81];
assign N52 = N51 | data_masked[145];
assign N51 = data_masked[273] | data_masked[209];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[82];
assign N55 = N54 | data_masked[146];
assign N54 = data_masked[274] | data_masked[210];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[83];
assign N58 = N57 | data_masked[147];
assign N57 = data_masked[275] | data_masked[211];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[84];
assign N61 = N60 | data_masked[148];
assign N60 = data_masked[276] | data_masked[212];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[85];
assign N64 = N63 | data_masked[149];
assign N63 = data_masked[277] | data_masked[213];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[86];
assign N67 = N66 | data_masked[150];
assign N66 = data_masked[278] | data_masked[214];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[87];
assign N70 = N69 | data_masked[151];
assign N69 = data_masked[279] | data_masked[215];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[88];
assign N73 = N72 | data_masked[152];
assign N72 = data_masked[280] | data_masked[216];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[89];
assign N76 = N75 | data_masked[153];
assign N75 = data_masked[281] | data_masked[217];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[90];
assign N79 = N78 | data_masked[154];
assign N78 = data_masked[282] | data_masked[218];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[91];
assign N82 = N81 | data_masked[155];
assign N81 = data_masked[283] | data_masked[219];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[92];
assign N85 = N84 | data_masked[156];
assign N84 = data_masked[284] | data_masked[220];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[93];
assign N88 = N87 | data_masked[157];
assign N87 = data_masked[285] | data_masked[221];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[94];
assign N91 = N90 | data_masked[158];
assign N90 = data_masked[286] | data_masked[222];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[95];
assign N94 = N93 | data_masked[159];
assign N93 = data_masked[287] | data_masked[223];
assign data_o[32] = N98 | data_masked[32];
assign N98 = N97 | data_masked[96];
assign N97 = N96 | data_masked[160];
assign N96 = data_masked[288] | data_masked[224];
assign data_o[33] = N101 | data_masked[33];
assign N101 = N100 | data_masked[97];
assign N100 = N99 | data_masked[161];
assign N99 = data_masked[289] | data_masked[225];
assign data_o[34] = N104 | data_masked[34];
assign N104 = N103 | data_masked[98];
assign N103 = N102 | data_masked[162];
assign N102 = data_masked[290] | data_masked[226];
assign data_o[35] = N107 | data_masked[35];
assign N107 = N106 | data_masked[99];
assign N106 = N105 | data_masked[163];
assign N105 = data_masked[291] | data_masked[227];
assign data_o[36] = N110 | data_masked[36];
assign N110 = N109 | data_masked[100];
assign N109 = N108 | data_masked[164];
assign N108 = data_masked[292] | data_masked[228];
assign data_o[37] = N113 | data_masked[37];
assign N113 = N112 | data_masked[101];
assign N112 = N111 | data_masked[165];
assign N111 = data_masked[293] | data_masked[229];
assign data_o[38] = N116 | data_masked[38];
assign N116 = N115 | data_masked[102];
assign N115 = N114 | data_masked[166];
assign N114 = data_masked[294] | data_masked[230];
assign data_o[39] = N119 | data_masked[39];
assign N119 = N118 | data_masked[103];
assign N118 = N117 | data_masked[167];
assign N117 = data_masked[295] | data_masked[231];
assign data_o[40] = N122 | data_masked[40];
assign N122 = N121 | data_masked[104];
assign N121 = N120 | data_masked[168];
assign N120 = data_masked[296] | data_masked[232];
assign data_o[41] = N125 | data_masked[41];
assign N125 = N124 | data_masked[105];
assign N124 = N123 | data_masked[169];
assign N123 = data_masked[297] | data_masked[233];
assign data_o[42] = N128 | data_masked[42];
assign N128 = N127 | data_masked[106];
assign N127 = N126 | data_masked[170];
assign N126 = data_masked[298] | data_masked[234];
assign data_o[43] = N131 | data_masked[43];
assign N131 = N130 | data_masked[107];
assign N130 = N129 | data_masked[171];
assign N129 = data_masked[299] | data_masked[235];
assign data_o[44] = N134 | data_masked[44];
assign N134 = N133 | data_masked[108];
assign N133 = N132 | data_masked[172];
assign N132 = data_masked[300] | data_masked[236];
assign data_o[45] = N137 | data_masked[45];
assign N137 = N136 | data_masked[109];
assign N136 = N135 | data_masked[173];
assign N135 = data_masked[301] | data_masked[237];
assign data_o[46] = N140 | data_masked[46];
assign N140 = N139 | data_masked[110];
assign N139 = N138 | data_masked[174];
assign N138 = data_masked[302] | data_masked[238];
assign data_o[47] = N143 | data_masked[47];
assign N143 = N142 | data_masked[111];
assign N142 = N141 | data_masked[175];
assign N141 = data_masked[303] | data_masked[239];
assign data_o[48] = N146 | data_masked[48];
assign N146 = N145 | data_masked[112];
assign N145 = N144 | data_masked[176];
assign N144 = data_masked[304] | data_masked[240];
assign data_o[49] = N149 | data_masked[49];
assign N149 = N148 | data_masked[113];
assign N148 = N147 | data_masked[177];
assign N147 = data_masked[305] | data_masked[241];
assign data_o[50] = N152 | data_masked[50];
assign N152 = N151 | data_masked[114];
assign N151 = N150 | data_masked[178];
assign N150 = data_masked[306] | data_masked[242];
assign data_o[51] = N155 | data_masked[51];
assign N155 = N154 | data_masked[115];
assign N154 = N153 | data_masked[179];
assign N153 = data_masked[307] | data_masked[243];
assign data_o[52] = N158 | data_masked[52];
assign N158 = N157 | data_masked[116];
assign N157 = N156 | data_masked[180];
assign N156 = data_masked[308] | data_masked[244];
assign data_o[53] = N161 | data_masked[53];
assign N161 = N160 | data_masked[117];
assign N160 = N159 | data_masked[181];
assign N159 = data_masked[309] | data_masked[245];
assign data_o[54] = N164 | data_masked[54];
assign N164 = N163 | data_masked[118];
assign N163 = N162 | data_masked[182];
assign N162 = data_masked[310] | data_masked[246];
assign data_o[55] = N167 | data_masked[55];
assign N167 = N166 | data_masked[119];
assign N166 = N165 | data_masked[183];
assign N165 = data_masked[311] | data_masked[247];
assign data_o[56] = N170 | data_masked[56];
assign N170 = N169 | data_masked[120];
assign N169 = N168 | data_masked[184];
assign N168 = data_masked[312] | data_masked[248];
assign data_o[57] = N173 | data_masked[57];
assign N173 = N172 | data_masked[121];
assign N172 = N171 | data_masked[185];
assign N171 = data_masked[313] | data_masked[249];
assign data_o[58] = N176 | data_masked[58];
assign N176 = N175 | data_masked[122];
assign N175 = N174 | data_masked[186];
assign N174 = data_masked[314] | data_masked[250];
assign data_o[59] = N179 | data_masked[59];
assign N179 = N178 | data_masked[123];
assign N178 = N177 | data_masked[187];
assign N177 = data_masked[315] | data_masked[251];
assign data_o[60] = N182 | data_masked[60];
assign N182 = N181 | data_masked[124];
assign N181 = N180 | data_masked[188];
assign N180 = data_masked[316] | data_masked[252];
assign data_o[61] = N185 | data_masked[61];
assign N185 = N184 | data_masked[125];
assign N184 = N183 | data_masked[189];
assign N183 = data_masked[317] | data_masked[253];
assign data_o[62] = N188 | data_masked[62];
assign N188 = N187 | data_masked[126];
assign N187 = N186 | data_masked[190];
assign N186 = data_masked[318] | data_masked[254];
assign data_o[63] = N191 | data_masked[63];
assign N191 = N190 | data_masked[127];
assign N190 = N189 | data_masked[191];
assign N189 = data_masked[319] | data_masked[255];
endmodule |
module bsg_circular_ptr_slots_p32_max_add_p31
(
clk,
reset_i,
add_i,
o
);
input [4:0] add_i;
output [4:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7;
wire [4:0] ptr_n;
reg [4:0] o;
assign ptr_n = o + add_i;
assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? ptr_n : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
always @(posedge clk) begin
if(1'b1) begin
{ o[4:0] } <= { N7, N6, N5, N4, N3 };
end
end
endmodule |
module bsg_mux_one_hot_width_p28_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [139:0] data_i;
input [4:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83;
wire [139:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[63] = data_i[63] & sel_one_hot_i[2];
assign data_masked[62] = data_i[62] & sel_one_hot_i[2];
assign data_masked[61] = data_i[61] & sel_one_hot_i[2];
assign data_masked[60] = data_i[60] & sel_one_hot_i[2];
assign data_masked[59] = data_i[59] & sel_one_hot_i[2];
assign data_masked[58] = data_i[58] & sel_one_hot_i[2];
assign data_masked[57] = data_i[57] & sel_one_hot_i[2];
assign data_masked[56] = data_i[56] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[95] = data_i[95] & sel_one_hot_i[3];
assign data_masked[94] = data_i[94] & sel_one_hot_i[3];
assign data_masked[93] = data_i[93] & sel_one_hot_i[3];
assign data_masked[92] = data_i[92] & sel_one_hot_i[3];
assign data_masked[91] = data_i[91] & sel_one_hot_i[3];
assign data_masked[90] = data_i[90] & sel_one_hot_i[3];
assign data_masked[89] = data_i[89] & sel_one_hot_i[3];
assign data_masked[88] = data_i[88] & sel_one_hot_i[3];
assign data_masked[87] = data_i[87] & sel_one_hot_i[3];
assign data_masked[86] = data_i[86] & sel_one_hot_i[3];
assign data_masked[85] = data_i[85] & sel_one_hot_i[3];
assign data_masked[84] = data_i[84] & sel_one_hot_i[3];
assign data_masked[139] = data_i[139] & sel_one_hot_i[4];
assign data_masked[138] = data_i[138] & sel_one_hot_i[4];
assign data_masked[137] = data_i[137] & sel_one_hot_i[4];
assign data_masked[136] = data_i[136] & sel_one_hot_i[4];
assign data_masked[135] = data_i[135] & sel_one_hot_i[4];
assign data_masked[134] = data_i[134] & sel_one_hot_i[4];
assign data_masked[133] = data_i[133] & sel_one_hot_i[4];
assign data_masked[132] = data_i[132] & sel_one_hot_i[4];
assign data_masked[131] = data_i[131] & sel_one_hot_i[4];
assign data_masked[130] = data_i[130] & sel_one_hot_i[4];
assign data_masked[129] = data_i[129] & sel_one_hot_i[4];
assign data_masked[128] = data_i[128] & sel_one_hot_i[4];
assign data_masked[127] = data_i[127] & sel_one_hot_i[4];
assign data_masked[126] = data_i[126] & sel_one_hot_i[4];
assign data_masked[125] = data_i[125] & sel_one_hot_i[4];
assign data_masked[124] = data_i[124] & sel_one_hot_i[4];
assign data_masked[123] = data_i[123] & sel_one_hot_i[4];
assign data_masked[122] = data_i[122] & sel_one_hot_i[4];
assign data_masked[121] = data_i[121] & sel_one_hot_i[4];
assign data_masked[120] = data_i[120] & sel_one_hot_i[4];
assign data_masked[119] = data_i[119] & sel_one_hot_i[4];
assign data_masked[118] = data_i[118] & sel_one_hot_i[4];
assign data_masked[117] = data_i[117] & sel_one_hot_i[4];
assign data_masked[116] = data_i[116] & sel_one_hot_i[4];
assign data_masked[115] = data_i[115] & sel_one_hot_i[4];
assign data_masked[114] = data_i[114] & sel_one_hot_i[4];
assign data_masked[113] = data_i[113] & sel_one_hot_i[4];
assign data_masked[112] = data_i[112] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[28];
assign N1 = N0 | data_masked[56];
assign N0 = data_masked[112] | data_masked[84];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[29];
assign N4 = N3 | data_masked[57];
assign N3 = data_masked[113] | data_masked[85];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[30];
assign N7 = N6 | data_masked[58];
assign N6 = data_masked[114] | data_masked[86];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[31];
assign N10 = N9 | data_masked[59];
assign N9 = data_masked[115] | data_masked[87];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[32];
assign N13 = N12 | data_masked[60];
assign N12 = data_masked[116] | data_masked[88];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[33];
assign N16 = N15 | data_masked[61];
assign N15 = data_masked[117] | data_masked[89];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[34];
assign N19 = N18 | data_masked[62];
assign N18 = data_masked[118] | data_masked[90];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[35];
assign N22 = N21 | data_masked[63];
assign N21 = data_masked[119] | data_masked[91];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[36];
assign N25 = N24 | data_masked[64];
assign N24 = data_masked[120] | data_masked[92];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[37];
assign N28 = N27 | data_masked[65];
assign N27 = data_masked[121] | data_masked[93];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[38];
assign N31 = N30 | data_masked[66];
assign N30 = data_masked[122] | data_masked[94];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[39];
assign N34 = N33 | data_masked[67];
assign N33 = data_masked[123] | data_masked[95];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[40];
assign N37 = N36 | data_masked[68];
assign N36 = data_masked[124] | data_masked[96];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[41];
assign N40 = N39 | data_masked[69];
assign N39 = data_masked[125] | data_masked[97];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[42];
assign N43 = N42 | data_masked[70];
assign N42 = data_masked[126] | data_masked[98];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[43];
assign N46 = N45 | data_masked[71];
assign N45 = data_masked[127] | data_masked[99];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[44];
assign N49 = N48 | data_masked[72];
assign N48 = data_masked[128] | data_masked[100];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[45];
assign N52 = N51 | data_masked[73];
assign N51 = data_masked[129] | data_masked[101];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[46];
assign N55 = N54 | data_masked[74];
assign N54 = data_masked[130] | data_masked[102];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[47];
assign N58 = N57 | data_masked[75];
assign N57 = data_masked[131] | data_masked[103];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[48];
assign N61 = N60 | data_masked[76];
assign N60 = data_masked[132] | data_masked[104];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[49];
assign N64 = N63 | data_masked[77];
assign N63 = data_masked[133] | data_masked[105];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[50];
assign N67 = N66 | data_masked[78];
assign N66 = data_masked[134] | data_masked[106];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[51];
assign N70 = N69 | data_masked[79];
assign N69 = data_masked[135] | data_masked[107];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[52];
assign N73 = N72 | data_masked[80];
assign N72 = data_masked[136] | data_masked[108];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[53];
assign N76 = N75 | data_masked[81];
assign N75 = data_masked[137] | data_masked[109];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[54];
assign N79 = N78 | data_masked[82];
assign N78 = data_masked[138] | data_masked[110];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[55];
assign N82 = N81 | data_masked[83];
assign N81 = data_masked[139] | data_masked[111];
endmodule |
module bsg_circular_ptr_slots_p8_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [2:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
wire [2:0] genblk1_genblk1_ptr_r_p1;
reg [2:0] o;
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N6 = ~add_i[0];
assign N7 = N6 & N2;
assign N8 = ~N7;
always @(posedge clk) begin
if(N8) begin
{ o[2:0] } <= { N5, N4, N3 };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p26_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [25:0] w_data_i;
input [0:0] r_addr_i;
output [25:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [25:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [51:0] mem;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[51] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[50] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[49] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[48] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[47] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[46] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[45] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[44] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[43] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[42] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[41] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[40] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[39] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[38] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[37] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[36] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[35] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[34] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[33] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[32] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[31] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[30] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[29] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[28] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[27] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[26] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[51:26] } <= { w_data_i[25:0] };
end
if(N7) begin
{ mem[25:0] } <= { w_data_i[25:0] };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p55_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [54:0] w_data_i;
input [0:0] r_addr_i;
output [54:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [54:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [109:0] mem;
assign r_data_o[54] = (N3)? mem[54] :
(N0)? mem[109] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[53] = (N3)? mem[53] :
(N0)? mem[108] : 1'b0;
assign r_data_o[52] = (N3)? mem[52] :
(N0)? mem[107] : 1'b0;
assign r_data_o[51] = (N3)? mem[51] :
(N0)? mem[106] : 1'b0;
assign r_data_o[50] = (N3)? mem[50] :
(N0)? mem[105] : 1'b0;
assign r_data_o[49] = (N3)? mem[49] :
(N0)? mem[104] : 1'b0;
assign r_data_o[48] = (N3)? mem[48] :
(N0)? mem[103] : 1'b0;
assign r_data_o[47] = (N3)? mem[47] :
(N0)? mem[102] : 1'b0;
assign r_data_o[46] = (N3)? mem[46] :
(N0)? mem[101] : 1'b0;
assign r_data_o[45] = (N3)? mem[45] :
(N0)? mem[100] : 1'b0;
assign r_data_o[44] = (N3)? mem[44] :
(N0)? mem[99] : 1'b0;
assign r_data_o[43] = (N3)? mem[43] :
(N0)? mem[98] : 1'b0;
assign r_data_o[42] = (N3)? mem[42] :
(N0)? mem[97] : 1'b0;
assign r_data_o[41] = (N3)? mem[41] :
(N0)? mem[96] : 1'b0;
assign r_data_o[40] = (N3)? mem[40] :
(N0)? mem[95] : 1'b0;
assign r_data_o[39] = (N3)? mem[39] :
(N0)? mem[94] : 1'b0;
assign r_data_o[38] = (N3)? mem[38] :
(N0)? mem[93] : 1'b0;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[92] : 1'b0;
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[91] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[90] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[89] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[88] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[87] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[86] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[85] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[84] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[83] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[82] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[81] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[80] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[79] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[78] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[77] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[76] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[75] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[74] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[73] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[72] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[71] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[70] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[69] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[68] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[67] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[66] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[65] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[64] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[63] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[62] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[61] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[60] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[59] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[58] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[57] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[56] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[55] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[109:55] } <= { w_data_i[54:0] };
end
if(N7) begin
{ mem[54:0] } <= { w_data_i[54:0] };
end
end
endmodule |
module bsg_mux_one_hot_width_p28_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [55:0] data_i;
input [1:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire [55:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_o[0] = data_masked[28] | data_masked[0];
assign data_o[1] = data_masked[29] | data_masked[1];
assign data_o[2] = data_masked[30] | data_masked[2];
assign data_o[3] = data_masked[31] | data_masked[3];
assign data_o[4] = data_masked[32] | data_masked[4];
assign data_o[5] = data_masked[33] | data_masked[5];
assign data_o[6] = data_masked[34] | data_masked[6];
assign data_o[7] = data_masked[35] | data_masked[7];
assign data_o[8] = data_masked[36] | data_masked[8];
assign data_o[9] = data_masked[37] | data_masked[9];
assign data_o[10] = data_masked[38] | data_masked[10];
assign data_o[11] = data_masked[39] | data_masked[11];
assign data_o[12] = data_masked[40] | data_masked[12];
assign data_o[13] = data_masked[41] | data_masked[13];
assign data_o[14] = data_masked[42] | data_masked[14];
assign data_o[15] = data_masked[43] | data_masked[15];
assign data_o[16] = data_masked[44] | data_masked[16];
assign data_o[17] = data_masked[45] | data_masked[17];
assign data_o[18] = data_masked[46] | data_masked[18];
assign data_o[19] = data_masked[47] | data_masked[19];
assign data_o[20] = data_masked[48] | data_masked[20];
assign data_o[21] = data_masked[49] | data_masked[21];
assign data_o[22] = data_masked[50] | data_masked[22];
assign data_o[23] = data_masked[51] | data_masked[23];
assign data_o[24] = data_masked[52] | data_masked[24];
assign data_o[25] = data_masked[53] | data_masked[25];
assign data_o[26] = data_masked[54] | data_masked[26];
assign data_o[27] = data_masked[55] | data_masked[27];
endmodule |
module bp_be_pipe_mem_vaddr_width_p56_lce_sets_p64_cce_block_size_in_bytes_p64
(
clk_i,
reset_i,
decode_i,
rs1_i,
rs2_i,
imm_i,
exc_i,
mmu_cmd_o,
mmu_cmd_v_o,
mmu_cmd_ready_i,
mmu_resp_i,
mmu_resp_v_i,
mmu_resp_ready_o,
result_o,
cache_miss_o
);
input [42:0] decode_i;
input [63:0] rs1_i;
input [63:0] rs2_i;
input [63:0] imm_i;
input [6:0] exc_i;
output [123:0] mmu_cmd_o;
input [70:0] mmu_resp_i;
output [63:0] result_o;
input clk_i;
input reset_i;
input mmu_cmd_ready_i;
input mmu_resp_v_i;
output mmu_cmd_v_o;
output mmu_resp_ready_o;
output cache_miss_o;
wire [123:0] mmu_cmd_o;
wire [63:0] result_o;
wire mmu_cmd_v_o,mmu_resp_ready_o,cache_miss_o,N0,N1,N2,N3,N4,N5,N6,N7;
assign mmu_resp_ready_o = 1'b1;
assign mmu_cmd_o[123] = decode_i[22];
assign mmu_cmd_o[122] = decode_i[21];
assign mmu_cmd_o[121] = decode_i[20];
assign mmu_cmd_o[120] = decode_i[19];
assign mmu_cmd_o[63] = rs2_i[63];
assign mmu_cmd_o[62] = rs2_i[62];
assign mmu_cmd_o[61] = rs2_i[61];
assign mmu_cmd_o[60] = rs2_i[60];
assign mmu_cmd_o[59] = rs2_i[59];
assign mmu_cmd_o[58] = rs2_i[58];
assign mmu_cmd_o[57] = rs2_i[57];
assign mmu_cmd_o[56] = rs2_i[56];
assign mmu_cmd_o[55] = rs2_i[55];
assign mmu_cmd_o[54] = rs2_i[54];
assign mmu_cmd_o[53] = rs2_i[53];
assign mmu_cmd_o[52] = rs2_i[52];
assign mmu_cmd_o[51] = rs2_i[51];
assign mmu_cmd_o[50] = rs2_i[50];
assign mmu_cmd_o[49] = rs2_i[49];
assign mmu_cmd_o[48] = rs2_i[48];
assign mmu_cmd_o[47] = rs2_i[47];
assign mmu_cmd_o[46] = rs2_i[46];
assign mmu_cmd_o[45] = rs2_i[45];
assign mmu_cmd_o[44] = rs2_i[44];
assign mmu_cmd_o[43] = rs2_i[43];
assign mmu_cmd_o[42] = rs2_i[42];
assign mmu_cmd_o[41] = rs2_i[41];
assign mmu_cmd_o[40] = rs2_i[40];
assign mmu_cmd_o[39] = rs2_i[39];
assign mmu_cmd_o[38] = rs2_i[38];
assign mmu_cmd_o[37] = rs2_i[37];
assign mmu_cmd_o[36] = rs2_i[36];
assign mmu_cmd_o[35] = rs2_i[35];
assign mmu_cmd_o[34] = rs2_i[34];
assign mmu_cmd_o[33] = rs2_i[33];
assign mmu_cmd_o[32] = rs2_i[32];
assign mmu_cmd_o[31] = rs2_i[31];
assign mmu_cmd_o[30] = rs2_i[30];
assign mmu_cmd_o[29] = rs2_i[29];
assign mmu_cmd_o[28] = rs2_i[28];
assign mmu_cmd_o[27] = rs2_i[27];
assign mmu_cmd_o[26] = rs2_i[26];
assign mmu_cmd_o[25] = rs2_i[25];
assign mmu_cmd_o[24] = rs2_i[24];
assign mmu_cmd_o[23] = rs2_i[23];
assign mmu_cmd_o[22] = rs2_i[22];
assign mmu_cmd_o[21] = rs2_i[21];
assign mmu_cmd_o[20] = rs2_i[20];
assign mmu_cmd_o[19] = rs2_i[19];
assign mmu_cmd_o[18] = rs2_i[18];
assign mmu_cmd_o[17] = rs2_i[17];
assign mmu_cmd_o[16] = rs2_i[16];
assign mmu_cmd_o[15] = rs2_i[15];
assign mmu_cmd_o[14] = rs2_i[14];
assign mmu_cmd_o[13] = rs2_i[13];
assign mmu_cmd_o[12] = rs2_i[12];
assign mmu_cmd_o[11] = rs2_i[11];
assign mmu_cmd_o[10] = rs2_i[10];
assign mmu_cmd_o[9] = rs2_i[9];
assign mmu_cmd_o[8] = rs2_i[8];
assign mmu_cmd_o[7] = rs2_i[7];
assign mmu_cmd_o[6] = rs2_i[6];
assign mmu_cmd_o[5] = rs2_i[5];
assign mmu_cmd_o[4] = rs2_i[4];
assign mmu_cmd_o[3] = rs2_i[3];
assign mmu_cmd_o[2] = rs2_i[2];
assign mmu_cmd_o[1] = rs2_i[1];
assign mmu_cmd_o[0] = rs2_i[0];
assign result_o[63] = mmu_resp_i[70];
assign result_o[62] = mmu_resp_i[69];
assign result_o[61] = mmu_resp_i[68];
assign result_o[60] = mmu_resp_i[67];
assign result_o[59] = mmu_resp_i[66];
assign result_o[58] = mmu_resp_i[65];
assign result_o[57] = mmu_resp_i[64];
assign result_o[56] = mmu_resp_i[63];
assign result_o[55] = mmu_resp_i[62];
assign result_o[54] = mmu_resp_i[61];
assign result_o[53] = mmu_resp_i[60];
assign result_o[52] = mmu_resp_i[59];
assign result_o[51] = mmu_resp_i[58];
assign result_o[50] = mmu_resp_i[57];
assign result_o[49] = mmu_resp_i[56];
assign result_o[48] = mmu_resp_i[55];
assign result_o[47] = mmu_resp_i[54];
assign result_o[46] = mmu_resp_i[53];
assign result_o[45] = mmu_resp_i[52];
assign result_o[44] = mmu_resp_i[51];
assign result_o[43] = mmu_resp_i[50];
assign result_o[42] = mmu_resp_i[49];
assign result_o[41] = mmu_resp_i[48];
assign result_o[40] = mmu_resp_i[47];
assign result_o[39] = mmu_resp_i[46];
assign result_o[38] = mmu_resp_i[45];
assign result_o[37] = mmu_resp_i[44];
assign result_o[36] = mmu_resp_i[43];
assign result_o[35] = mmu_resp_i[42];
assign result_o[34] = mmu_resp_i[41];
assign result_o[33] = mmu_resp_i[40];
assign result_o[32] = mmu_resp_i[39];
assign result_o[31] = mmu_resp_i[38];
assign result_o[30] = mmu_resp_i[37];
assign result_o[29] = mmu_resp_i[36];
assign result_o[28] = mmu_resp_i[35];
assign result_o[27] = mmu_resp_i[34];
assign result_o[26] = mmu_resp_i[33];
assign result_o[25] = mmu_resp_i[32];
assign result_o[24] = mmu_resp_i[31];
assign result_o[23] = mmu_resp_i[30];
assign result_o[22] = mmu_resp_i[29];
assign result_o[21] = mmu_resp_i[28];
assign result_o[20] = mmu_resp_i[27];
assign result_o[19] = mmu_resp_i[26];
assign result_o[18] = mmu_resp_i[25];
assign result_o[17] = mmu_resp_i[24];
assign result_o[16] = mmu_resp_i[23];
assign result_o[15] = mmu_resp_i[22];
assign result_o[14] = mmu_resp_i[21];
assign result_o[13] = mmu_resp_i[20];
assign result_o[12] = mmu_resp_i[19];
assign result_o[11] = mmu_resp_i[18];
assign result_o[10] = mmu_resp_i[17];
assign result_o[9] = mmu_resp_i[16];
assign result_o[8] = mmu_resp_i[15];
assign result_o[7] = mmu_resp_i[14];
assign result_o[6] = mmu_resp_i[13];
assign result_o[5] = mmu_resp_i[12];
assign result_o[4] = mmu_resp_i[11];
assign result_o[3] = mmu_resp_i[10];
assign result_o[2] = mmu_resp_i[9];
assign result_o[1] = mmu_resp_i[8];
assign result_o[0] = mmu_resp_i[7];
assign cache_miss_o = mmu_resp_i[0];
assign mmu_cmd_o[119:64] = rs1_i[55:0] + imm_i[55:0];
assign mmu_cmd_v_o = N0 & N7;
assign N0 = decode_i[29] | decode_i[30];
assign N7 = ~N6;
assign N6 = N5 | exc_i[0];
assign N5 = N4 | exc_i[1];
assign N4 = N3 | exc_i[2];
assign N3 = N2 | exc_i[3];
assign N2 = N1 | exc_i[4];
assign N1 = exc_i[6] | exc_i[5];
endmodule |
module bp_be_int_alu
(
src1_i,
src2_i,
op_i,
opw_v_i,
result_o
);
input [63:0] src1_i;
input [63:0] src2_i;
input [3:0] op_i;
output [63:0] result_o;
input opw_v_i;
wire [63:0] result_o,result_sgn;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,
N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,
N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,N260,N261,
N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,N274,N275,N276,N277,
N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,N290,N291,N292,N293,
N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,
N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,
N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,N338,N339,N340,N341,
N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,N354,N355,N356,N357,
N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,N370,N371,N372,N373,
N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,N385,N386,N387,N388,N389,
N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,N401,N402,N403,N404,N405,
N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,N417,N418,N419,N420,N421,
N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,N433,N434,N435,N436,N437,
N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,N449,N450,N451,N452,N453,
N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,N465,N466,N467,N468,N469,
N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,N481,N482,N483,N484,N485,
N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,N497,N498,N499,N500,N501,
N502,N503,N504,N505,N506,N507,N508,N509,N510,N511,N512,N513,N514,N515,N516,N517,
N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,N529,N530,N531,N532,N533,
N534,N535,N536,N537,N538,N539,N540,N541,N542,N543,N544,N545,N546,N547,N548,N549,
N550,N551,N552,N553,N554,N555,N556,N557,N558,N559,N560,N561,N562,N563,N564,N565,
N566,N567,N568,N569,N570,N571,N572,N573,N574,N575,N576,N577,N578,N579,N580,N581,
N582,N583,N584,N585,N586,N587,N588,N589,N590,N591,N592,N593,N594,N595,N596,N597,
N598,N599,N600,N601,N602,N603,N604,N605,N606,N607,N608,N609,N610,N611,N612,N613,
N614,N615,N616,N617,N618,N619,N620,N621,N622,N623,N624,N625,N626,N627,N628,N629,
N630,N631,N632,N633,N634,N635,N636,N637,N638,N639,N640,N641,N642,N643,N644,N645,
N646,N647,N648,N649,N650,N651,N652,N653,N654,N655,N656,N657,N658,N659,N660,N661,
N662,N663,N664,N665,N666,N667,N668,N669,N670,N671,N672,N673,N674,N675,N676,N677,
N678,N679,N680,N681,N682,N683,N684,N685,N686,N687,N688,N689,N690,N691,N692,N693,
N694,N695,N696,N697,N698,N699,N700,N701,N702,N703,N704,N705,N706,N707,N708,N709,
N710,N711,N712,N713,N714,N715,N716,N717,N718,N719,N720,N721,N722,N723,N724,N725,
N726,N727,N728,N729,N730,N731,N732,N733,N734,N735,N736,N737,N738,N739,N740,N741,
N742,N743,N744,N745,N746,N747,N748,N749,N750,N751,N752,N753,N754,N755,N756,N757,
N758,N759,N760,N761,N762,N763,N764,N765,N766,N767,N768,N769,N770,N771,N772,N773,
N774,N775,N776,N777,N778,N779,N780,N781,N782,N783,N784,N785,N786,N787,N788,N789,
N790,N791,N792,N793,N794,N795;
wire [31:0] resultw_sgn;
assign N27 = N231 & N35;
assign N28 = N272 | op_i[0];
assign N30 = N248 | N35;
assign N32 = N237 | N35;
assign N34 = N256 & op_i[0];
assign N36 = N272 | N35;
assign N37 = op_i[2] & N35;
assign { N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103 } = src1_i[31:0] << src2_i[4:0];
assign { N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135 } = src1_i[31:0] >> src2_i[4:0];
assign { N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167 } = $signed(src1_i[31:0]) >>> src2_i[4:0];
assign N231 = N271 & N236;
assign N232 = N241 & N35;
assign N233 = N231 & N232;
assign N234 = N272 | N238;
assign N237 = op_i[3] | N236;
assign N238 = op_i[1] | op_i[0];
assign N239 = N237 | N238;
assign N242 = N241 | op_i[0];
assign N243 = N237 | N242;
assign N245 = N241 | N35;
assign N246 = N237 | N245;
assign N248 = op_i[3] | op_i[2];
assign N249 = N248 | N273;
assign N251 = N237 | N273;
assign N253 = N271 | N236;
assign N254 = N253 | N273;
assign N256 = op_i[3] & op_i[2];
assign N257 = op_i[1] & op_i[0];
assign N258 = N256 & N257;
assign N259 = N248 | N242;
assign N261 = N272 | N242;
assign N263 = N253 | N238;
assign N265 = N253 | N242;
assign N267 = N248 | N245;
assign N269 = N272 | N245;
assign N272 = N271 | op_i[2];
assign N273 = op_i[1] | N35;
assign N274 = N272 | N273;
assign { N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601, N600, N599, N598, N597, N596 } = src1_i << src2_i[5:0];
assign { N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665, N664, N663, N662, N661, N660 } = src1_i >> src2_i[5:0];
assign { N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729, N728, N727, N726, N725, N724 } = $signed(src1_i) >>> src2_i[5:0];
assign N788 = $signed(src1_i) < $signed(src2_i);
assign N789 = $signed(src1_i) >= $signed(src2_i);
assign N790 = src1_i == src2_i;
assign N791 = src1_i != src2_i;
assign N792 = src1_i < src2_i;
assign N793 = src1_i >= src2_i;
assign { N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276 } = $signed(src1_i) + $signed(src2_i);
assign { N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39 } = $signed(src1_i[31:0]) + $signed(src2_i[31:0]);
assign { N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340 } = $signed(src1_i) - $signed(src2_i);
assign { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } = $signed(src1_i[31:0]) - $signed(src2_i[31:0]);
assign { N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199 } = (N0)? { N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39 } :
(N1)? { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } :
(N2)? { N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103 } :
(N3)? { N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135 } :
(N4)? { N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N27;
assign N1 = N29;
assign N2 = N31;
assign N3 = N33;
assign N4 = N34;
assign N5 = N38;
assign resultw_sgn = (N6)? { N230, N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N6 = N241;
assign N7 = op_i[1];
assign result_sgn = (N8)? { N339, N338, N337, N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304, N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N293, N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276 } :
(N9)? { N403, N402, N401, N400, N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N387, N386, N385, N384, N383, N382, N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350, N349, N348, N347, N346, N345, N344, N343, N342, N341, N340 } :
(N10)? { N404, N405, N406, N407, N408, N409, N410, N411, N412, N413, N414, N415, N416, N417, N418, N419, N420, N421, N422, N423, N424, N425, N426, N427, N428, N429, N430, N431, N432, N433, N434, N435, N436, N437, N438, N439, N440, N441, N442, N443, N444, N445, N446, N447, N448, N449, N450, N451, N452, N453, N454, N455, N456, N457, N458, N459, N460, N461, N462, N463, N464, N465, N466, N467 } :
(N11)? { N468, N469, N470, N471, N472, N473, N474, N475, N476, N477, N478, N479, N480, N481, N482, N483, N484, N485, N486, N487, N488, N489, N490, N491, N492, N493, N494, N495, N496, N497, N498, N499, N500, N501, N502, N503, N504, N505, N506, N507, N508, N509, N510, N511, N512, N513, N514, N515, N516, N517, N518, N519, N520, N521, N522, N523, N524, N525, N526, N527, N528, N529, N530, N531 } :
(N12)? { N532, N533, N534, N535, N536, N537, N538, N539, N540, N541, N542, N543, N544, N545, N546, N547, N548, N549, N550, N551, N552, N553, N554, N555, N556, N557, N558, N559, N560, N561, N562, N563, N564, N565, N566, N567, N568, N569, N570, N571, N572, N573, N574, N575, N576, N577, N578, N579, N580, N581, N582, N583, N584, N585, N586, N587, N588, N589, N590, N591, N592, N593, N594, N595 } :
(N13)? { N659, N658, N657, N656, N655, N654, N653, N652, N651, N650, N649, N648, N647, N646, N645, N644, N643, N642, N641, N640, N639, N638, N637, N636, N635, N634, N633, N632, N631, N630, N629, N628, N627, N626, N625, N624, N623, N622, N621, N620, N619, N618, N617, N616, N615, N614, N613, N612, N611, N610, N609, N608, N607, N606, N605, N604, N603, N602, N601, N600, N599, N598, N597, N596 } :
(N14)? { N723, N722, N721, N720, N719, N718, N717, N716, N715, N714, N713, N712, N711, N710, N709, N708, N707, N706, N705, N704, N703, N702, N701, N700, N699, N698, N697, N696, N695, N694, N693, N692, N691, N690, N689, N688, N687, N686, N685, N684, N683, N682, N681, N680, N679, N678, N677, N676, N675, N674, N673, N672, N671, N670, N669, N668, N667, N666, N665, N664, N663, N662, N661, N660 } :
(N15)? { N787, N786, N785, N784, N783, N782, N781, N780, N779, N778, N777, N776, N775, N774, N773, N772, N771, N770, N769, N768, N767, N766, N765, N764, N763, N762, N761, N760, N759, N758, N757, N756, N755, N754, N753, N752, N751, N750, N749, N748, N747, N746, N745, N744, N743, N742, N741, N740, N739, N738, N737, N736, N735, N734, N733, N732, N731, N730, N729, N728, N727, N726, N725, N724 } :
(N16)? src2_i :
(N17)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N788 } :
(N18)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N789 } :
(N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N790 } :
(N20)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N791 } :
(N21)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N792 } :
(N22)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N793 } :
(N23)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N8 = N233;
assign N9 = N235;
assign N10 = N240;
assign N11 = N244;
assign N12 = N247;
assign N13 = N250;
assign N14 = N252;
assign N15 = N255;
assign N16 = N258;
assign N17 = N260;
assign N18 = N262;
assign N19 = N264;
assign N20 = N266;
assign N21 = N268;
assign N22 = N270;
assign N23 = N275;
assign result_o = (N24)? { resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn[31:31], resultw_sgn } :
(N25)? result_sgn : 1'b0;
assign N24 = opw_v_i;
assign N25 = N794;
assign N26 = N241;
assign N29 = ~N28;
assign N31 = ~N30;
assign N33 = ~N32;
assign N35 = ~op_i[0];
assign N38 = N795 | N37;
assign N795 = ~N36;
assign N235 = ~N234;
assign N236 = ~op_i[2];
assign N240 = ~N239;
assign N241 = ~op_i[1];
assign N244 = ~N243;
assign N247 = ~N246;
assign N250 = ~N249;
assign N252 = ~N251;
assign N255 = ~N254;
assign N260 = ~N259;
assign N262 = ~N261;
assign N264 = ~N263;
assign N266 = ~N265;
assign N268 = ~N267;
assign N270 = ~N269;
assign N271 = ~op_i[3];
assign N275 = ~N274;
assign N404 = src1_i[63] ^ src2_i[63];
assign N405 = src1_i[62] ^ src2_i[62];
assign N406 = src1_i[61] ^ src2_i[61];
assign N407 = src1_i[60] ^ src2_i[60];
assign N408 = src1_i[59] ^ src2_i[59];
assign N409 = src1_i[58] ^ src2_i[58];
assign N410 = src1_i[57] ^ src2_i[57];
assign N411 = src1_i[56] ^ src2_i[56];
assign N412 = src1_i[55] ^ src2_i[55];
assign N413 = src1_i[54] ^ src2_i[54];
assign N414 = src1_i[53] ^ src2_i[53];
assign N415 = src1_i[52] ^ src2_i[52];
assign N416 = src1_i[51] ^ src2_i[51];
assign N417 = src1_i[50] ^ src2_i[50];
assign N418 = src1_i[49] ^ src2_i[49];
assign N419 = src1_i[48] ^ src2_i[48];
assign N420 = src1_i[47] ^ src2_i[47];
assign N421 = src1_i[46] ^ src2_i[46];
assign N422 = src1_i[45] ^ src2_i[45];
assign N423 = src1_i[44] ^ src2_i[44];
assign N424 = src1_i[43] ^ src2_i[43];
assign N425 = src1_i[42] ^ src2_i[42];
assign N426 = src1_i[41] ^ src2_i[41];
assign N427 = src1_i[40] ^ src2_i[40];
assign N428 = src1_i[39] ^ src2_i[39];
assign N429 = src1_i[38] ^ src2_i[38];
assign N430 = src1_i[37] ^ src2_i[37];
assign N431 = src1_i[36] ^ src2_i[36];
assign N432 = src1_i[35] ^ src2_i[35];
assign N433 = src1_i[34] ^ src2_i[34];
assign N434 = src1_i[33] ^ src2_i[33];
assign N435 = src1_i[32] ^ src2_i[32];
assign N436 = src1_i[31] ^ src2_i[31];
assign N437 = src1_i[30] ^ src2_i[30];
assign N438 = src1_i[29] ^ src2_i[29];
assign N439 = src1_i[28] ^ src2_i[28];
assign N440 = src1_i[27] ^ src2_i[27];
assign N441 = src1_i[26] ^ src2_i[26];
assign N442 = src1_i[25] ^ src2_i[25];
assign N443 = src1_i[24] ^ src2_i[24];
assign N444 = src1_i[23] ^ src2_i[23];
assign N445 = src1_i[22] ^ src2_i[22];
assign N446 = src1_i[21] ^ src2_i[21];
assign N447 = src1_i[20] ^ src2_i[20];
assign N448 = src1_i[19] ^ src2_i[19];
assign N449 = src1_i[18] ^ src2_i[18];
assign N450 = src1_i[17] ^ src2_i[17];
assign N451 = src1_i[16] ^ src2_i[16];
assign N452 = src1_i[15] ^ src2_i[15];
assign N453 = src1_i[14] ^ src2_i[14];
assign N454 = src1_i[13] ^ src2_i[13];
assign N455 = src1_i[12] ^ src2_i[12];
assign N456 = src1_i[11] ^ src2_i[11];
assign N457 = src1_i[10] ^ src2_i[10];
assign N458 = src1_i[9] ^ src2_i[9];
assign N459 = src1_i[8] ^ src2_i[8];
assign N460 = src1_i[7] ^ src2_i[7];
assign N461 = src1_i[6] ^ src2_i[6];
assign N462 = src1_i[5] ^ src2_i[5];
assign N463 = src1_i[4] ^ src2_i[4];
assign N464 = src1_i[3] ^ src2_i[3];
assign N465 = src1_i[2] ^ src2_i[2];
assign N466 = src1_i[1] ^ src2_i[1];
assign N467 = src1_i[0] ^ src2_i[0];
assign N468 = src1_i[63] | src2_i[63];
assign N469 = src1_i[62] | src2_i[62];
assign N470 = src1_i[61] | src2_i[61];
assign N471 = src1_i[60] | src2_i[60];
assign N472 = src1_i[59] | src2_i[59];
assign N473 = src1_i[58] | src2_i[58];
assign N474 = src1_i[57] | src2_i[57];
assign N475 = src1_i[56] | src2_i[56];
assign N476 = src1_i[55] | src2_i[55];
assign N477 = src1_i[54] | src2_i[54];
assign N478 = src1_i[53] | src2_i[53];
assign N479 = src1_i[52] | src2_i[52];
assign N480 = src1_i[51] | src2_i[51];
assign N481 = src1_i[50] | src2_i[50];
assign N482 = src1_i[49] | src2_i[49];
assign N483 = src1_i[48] | src2_i[48];
assign N484 = src1_i[47] | src2_i[47];
assign N485 = src1_i[46] | src2_i[46];
assign N486 = src1_i[45] | src2_i[45];
assign N487 = src1_i[44] | src2_i[44];
assign N488 = src1_i[43] | src2_i[43];
assign N489 = src1_i[42] | src2_i[42];
assign N490 = src1_i[41] | src2_i[41];
assign N491 = src1_i[40] | src2_i[40];
assign N492 = src1_i[39] | src2_i[39];
assign N493 = src1_i[38] | src2_i[38];
assign N494 = src1_i[37] | src2_i[37];
assign N495 = src1_i[36] | src2_i[36];
assign N496 = src1_i[35] | src2_i[35];
assign N497 = src1_i[34] | src2_i[34];
assign N498 = src1_i[33] | src2_i[33];
assign N499 = src1_i[32] | src2_i[32];
assign N500 = src1_i[31] | src2_i[31];
assign N501 = src1_i[30] | src2_i[30];
assign N502 = src1_i[29] | src2_i[29];
assign N503 = src1_i[28] | src2_i[28];
assign N504 = src1_i[27] | src2_i[27];
assign N505 = src1_i[26] | src2_i[26];
assign N506 = src1_i[25] | src2_i[25];
assign N507 = src1_i[24] | src2_i[24];
assign N508 = src1_i[23] | src2_i[23];
assign N509 = src1_i[22] | src2_i[22];
assign N510 = src1_i[21] | src2_i[21];
assign N511 = src1_i[20] | src2_i[20];
assign N512 = src1_i[19] | src2_i[19];
assign N513 = src1_i[18] | src2_i[18];
assign N514 = src1_i[17] | src2_i[17];
assign N515 = src1_i[16] | src2_i[16];
assign N516 = src1_i[15] | src2_i[15];
assign N517 = src1_i[14] | src2_i[14];
assign N518 = src1_i[13] | src2_i[13];
assign N519 = src1_i[12] | src2_i[12];
assign N520 = src1_i[11] | src2_i[11];
assign N521 = src1_i[10] | src2_i[10];
assign N522 = src1_i[9] | src2_i[9];
assign N523 = src1_i[8] | src2_i[8];
assign N524 = src1_i[7] | src2_i[7];
assign N525 = src1_i[6] | src2_i[6];
assign N526 = src1_i[5] | src2_i[5];
assign N527 = src1_i[4] | src2_i[4];
assign N528 = src1_i[3] | src2_i[3];
assign N529 = src1_i[2] | src2_i[2];
assign N530 = src1_i[1] | src2_i[1];
assign N531 = src1_i[0] | src2_i[0];
assign N532 = src1_i[63] & src2_i[63];
assign N533 = src1_i[62] & src2_i[62];
assign N534 = src1_i[61] & src2_i[61];
assign N535 = src1_i[60] & src2_i[60];
assign N536 = src1_i[59] & src2_i[59];
assign N537 = src1_i[58] & src2_i[58];
assign N538 = src1_i[57] & src2_i[57];
assign N539 = src1_i[56] & src2_i[56];
assign N540 = src1_i[55] & src2_i[55];
assign N541 = src1_i[54] & src2_i[54];
assign N542 = src1_i[53] & src2_i[53];
assign N543 = src1_i[52] & src2_i[52];
assign N544 = src1_i[51] & src2_i[51];
assign N545 = src1_i[50] & src2_i[50];
assign N546 = src1_i[49] & src2_i[49];
assign N547 = src1_i[48] & src2_i[48];
assign N548 = src1_i[47] & src2_i[47];
assign N549 = src1_i[46] & src2_i[46];
assign N550 = src1_i[45] & src2_i[45];
assign N551 = src1_i[44] & src2_i[44];
assign N552 = src1_i[43] & src2_i[43];
assign N553 = src1_i[42] & src2_i[42];
assign N554 = src1_i[41] & src2_i[41];
assign N555 = src1_i[40] & src2_i[40];
assign N556 = src1_i[39] & src2_i[39];
assign N557 = src1_i[38] & src2_i[38];
assign N558 = src1_i[37] & src2_i[37];
assign N559 = src1_i[36] & src2_i[36];
assign N560 = src1_i[35] & src2_i[35];
assign N561 = src1_i[34] & src2_i[34];
assign N562 = src1_i[33] & src2_i[33];
assign N563 = src1_i[32] & src2_i[32];
assign N564 = src1_i[31] & src2_i[31];
assign N565 = src1_i[30] & src2_i[30];
assign N566 = src1_i[29] & src2_i[29];
assign N567 = src1_i[28] & src2_i[28];
assign N568 = src1_i[27] & src2_i[27];
assign N569 = src1_i[26] & src2_i[26];
assign N570 = src1_i[25] & src2_i[25];
assign N571 = src1_i[24] & src2_i[24];
assign N572 = src1_i[23] & src2_i[23];
assign N573 = src1_i[22] & src2_i[22];
assign N574 = src1_i[21] & src2_i[21];
assign N575 = src1_i[20] & src2_i[20];
assign N576 = src1_i[19] & src2_i[19];
assign N577 = src1_i[18] & src2_i[18];
assign N578 = src1_i[17] & src2_i[17];
assign N579 = src1_i[16] & src2_i[16];
assign N580 = src1_i[15] & src2_i[15];
assign N581 = src1_i[14] & src2_i[14];
assign N582 = src1_i[13] & src2_i[13];
assign N583 = src1_i[12] & src2_i[12];
assign N584 = src1_i[11] & src2_i[11];
assign N585 = src1_i[10] & src2_i[10];
assign N586 = src1_i[9] & src2_i[9];
assign N587 = src1_i[8] & src2_i[8];
assign N588 = src1_i[7] & src2_i[7];
assign N589 = src1_i[6] & src2_i[6];
assign N590 = src1_i[5] & src2_i[5];
assign N591 = src1_i[4] & src2_i[4];
assign N592 = src1_i[3] & src2_i[3];
assign N593 = src1_i[2] & src2_i[2];
assign N594 = src1_i[1] & src2_i[1];
assign N595 = src1_i[0] & src2_i[0];
assign N794 = ~opw_v_i;
endmodule |
module bsg_circular_ptr_slots_p32_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [4:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10;
wire [4:0] genblk1_genblk1_ptr_r_p1;
reg [4:0] o;
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N8 = ~add_i[0];
assign N9 = N8 & N2;
assign N10 = ~N9;
always @(posedge clk) begin
if(N10) begin
{ o[4:0] } <= { N7, N6, N5, N4, N3 };
end
end
endmodule |
module bsg_scan_width_p5_or_p1_lo_to_hi_p1
(
i,
o
);
input [4:0] i;
output [4:0] o;
wire [4:0] o;
wire t_2__4_,t_2__3_,t_2__2_,t_2__1_,t_2__0_,t_1__4_,t_1__3_,t_1__2_,t_1__1_,t_1__0_;
assign t_1__4_ = i[0] | 1'b0;
assign t_1__3_ = i[1] | i[0];
assign t_1__2_ = i[2] | i[1];
assign t_1__1_ = i[3] | i[2];
assign t_1__0_ = i[4] | i[3];
assign t_2__4_ = t_1__4_ | 1'b0;
assign t_2__3_ = t_1__3_ | 1'b0;
assign t_2__2_ = t_1__2_ | t_1__4_;
assign t_2__1_ = t_1__1_ | t_1__3_;
assign t_2__0_ = t_1__0_ | t_1__2_;
assign o[0] = t_2__4_ | 1'b0;
assign o[1] = t_2__3_ | 1'b0;
assign o[2] = t_2__2_ | 1'b0;
assign o[3] = t_2__1_ | 1'b0;
assign o[4] = t_2__0_ | t_2__4_;
endmodule |
module bp_cce_inst_decode_inst_width_p95_inst_addr_width_p8
(
clk_i,
reset_i,
inst_i,
inst_v_i,
lce_req_v_i,
lce_resp_v_i,
lce_data_resp_v_i,
mem_resp_v_i,
mem_data_resp_v_i,
pending_v_i,
lce_cmd_ready_i,
lce_data_cmd_ready_i,
mem_cmd_ready_i,
mem_data_cmd_ready_i,
decoded_inst_o,
decoded_inst_v_o,
pc_stall_o,
pc_branch_target_o
);
input [94:0] inst_i;
output [122:0] decoded_inst_o;
output [7:0] pc_branch_target_o;
input clk_i;
input reset_i;
input inst_v_i;
input lce_req_v_i;
input lce_resp_v_i;
input lce_data_resp_v_i;
input mem_resp_v_i;
input mem_data_resp_v_i;
input pending_v_i;
input lce_cmd_ready_i;
input lce_data_cmd_ready_i;
input mem_cmd_ready_i;
input mem_data_cmd_ready_i;
output decoded_inst_v_o;
output pc_stall_o;
wire [122:0] decoded_inst_o;
wire [7:0] pc_branch_target_o;
wire decoded_inst_v_o,pc_stall_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,pushq_op,
popq_op,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,N36,N37,N38,wfq_op,stall_op,wfq_q_ready,N39,N40,N41,N42,N43,
N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,
N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,
N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,
N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,
N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,
N151,N152;
assign N41 = N99 & N96;
assign N42 = inst_i[62] | N96;
assign N44 = N99 | inst_i[61];
assign N46 = inst_i[62] & inst_i[61];
assign N54 = inst_i[93] | inst_i[94];
assign N55 = inst_i[92] | N54;
assign N56 = ~N55;
assign N57 = ~inst_i[92];
assign N58 = N57 | N54;
assign N59 = ~N58;
assign N60 = ~inst_i[94];
assign N61 = ~inst_i[93];
assign N62 = N61 | N60;
assign N63 = inst_i[92] | N62;
assign N64 = ~N63;
assign N65 = inst_i[90] | inst_i[91];
assign N66 = inst_i[89] | N65;
assign N67 = ~N66;
assign N68 = inst_i[93] | N60;
assign N69 = inst_i[92] | N68;
assign N70 = ~N69;
assign N71 = ~inst_i[89];
assign N72 = N71 | N65;
assign N73 = ~N72;
assign N74 = ~inst_i[90];
assign N75 = N74 | inst_i[91];
assign N76 = inst_i[89] | N75;
assign N77 = ~N76;
assign N78 = inst_i[59] | inst_i[60];
assign N79 = inst_i[58] | N78;
assign N80 = ~N79;
assign N81 = ~inst_i[60];
assign N82 = inst_i[59] | N81;
assign N83 = inst_i[58] | N82;
assign N84 = ~N83;
assign N85 = ~inst_i[58];
assign N86 = N85 | N82;
assign N87 = ~N86;
assign N88 = N85 | N78;
assign N89 = ~N88;
assign N90 = ~inst_i[59];
assign N91 = N90 | inst_i[60];
assign N92 = inst_i[58] | N91;
assign N93 = ~N92;
assign N94 = inst_i[61] | inst_i[62];
assign N95 = ~N94;
assign N96 = ~inst_i[61];
assign N97 = N96 | inst_i[62];
assign N98 = ~N97;
assign N99 = ~inst_i[62];
assign N100 = inst_i[61] | N99;
assign N101 = ~N100;
assign N102 = inst_i[61] & inst_i[62];
assign N103 = ~inst_i[75];
assign N104 = ~inst_i[74];
assign N105 = inst_i[77] | inst_i[78];
assign N106 = inst_i[76] | N105;
assign N107 = N103 | N106;
assign N108 = N104 | N107;
assign N109 = ~N108;
assign N110 = inst_i[74] | N107;
assign N111 = ~N110;
assign N112 = inst_i[75] | N106;
assign N113 = N104 | N112;
assign N114 = ~N113;
assign N115 = inst_i[74] | N112;
assign N116 = ~N115;
assign N117 = N61 | inst_i[94];
assign N118 = inst_i[92] | N117;
assign N119 = ~N118;
assign N120 = inst_i[93] & inst_i[94];
assign N121 = inst_i[92] & N120;
assign N122 = N57 | N68;
assign N123 = ~N122;
assign N124 = inst_i[90] & inst_i[91];
assign N125 = inst_i[89] & N124;
assign { N18, N17, N16 } = (N0)? inst_i[91:89] :
(N1)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N70;
assign N1 = N69;
assign { N21, N20, N19 } = (N2)? inst_i[91:89] :
(N3)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N123;
assign N3 = N122;
assign decoded_inst_v_o = (N4)? 1'b0 :
(N14)? inst_v_i : 1'b0;
assign N4 = N13;
assign decoded_inst_o = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N14)? { inst_i[91:58], N15, inst_i[57:28], N18, N17, N16, N70, N21, N20, N19, N123, inst_i[27:19], inst_i[60:58], inst_i[18:18], N119, N56, N22, N23, N24, N25, N26, inst_i[17:12], N27, N28, N29, inst_i[11:0], N30, N31, N32, N33, N34, N35, N36, N37, N38 } : 1'b0;
assign N51 = (N5)? N47 :
(N6)? N48 :
(N7)? N49 :
(N8)? N50 : 1'b0;
assign N5 = N41;
assign N6 = N43;
assign N7 = N45;
assign N8 = N46;
assign N52 = (N9)? N51 :
(N10)? N39 : 1'b0;
assign N9 = pushq_op;
assign N10 = N40;
assign pc_stall_o = (N11)? 1'b0 :
(N12)? N52 : 1'b0;
assign N11 = reset_i;
assign N12 = N53;
assign pc_branch_target_o = (N11)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N12)? inst_i[65:58] : 1'b0;
assign pushq_op = N121 & N73;
assign popq_op = N121 & N77;
assign N13 = reset_i | N126;
assign N126 = ~inst_v_i;
assign N14 = ~N13;
assign N15 = N56 | N59;
assign N22 = N109 & N127;
assign N127 = N119 | N56;
assign N23 = N111 & N128;
assign N128 = N119 | N56;
assign N24 = N114 & N129;
assign N129 = N119 | N56;
assign N25 = N116 & N130;
assign N130 = N119 | N56;
assign N26 = N132 | N25;
assign N132 = N131 | N24;
assign N131 = N22 | N23;
assign N27 = N64 & N67;
assign N28 = N70 & N73;
assign N29 = N70 & N77;
assign N30 = popq_op & N80;
assign N31 = popq_op & N84;
assign N32 = popq_op & N87;
assign N33 = popq_op & N89;
assign N34 = popq_op & N93;
assign N35 = N133 & N95;
assign N133 = lce_cmd_ready_i & pushq_op;
assign N36 = N134 & N98;
assign N134 = lce_data_cmd_ready_i & pushq_op;
assign N37 = N135 & N101;
assign N135 = mem_cmd_ready_i & pushq_op;
assign N38 = N136 & N102;
assign N136 = mem_data_cmd_ready_i & pushq_op;
assign wfq_op = N121 & N67;
assign stall_op = N64 & N125;
assign wfq_q_ready = N145 | N146;
assign N145 = N143 | N144;
assign N143 = N141 | N142;
assign N141 = N139 | N140;
assign N139 = N137 | N138;
assign N137 = inst_i[63] & lce_req_v_i;
assign N138 = inst_i[62] & lce_resp_v_i;
assign N140 = inst_i[61] & lce_data_resp_v_i;
assign N142 = inst_i[60] & mem_resp_v_i;
assign N144 = inst_i[59] & mem_data_resp_v_i;
assign N146 = inst_i[58] & pending_v_i;
assign N39 = stall_op | N148;
assign N148 = wfq_op & N147;
assign N147 = ~wfq_q_ready;
assign N40 = ~pushq_op;
assign N43 = ~N42;
assign N45 = ~N44;
assign N47 = N39 | N149;
assign N149 = ~lce_cmd_ready_i;
assign N48 = N39 | N150;
assign N150 = ~lce_data_cmd_ready_i;
assign N49 = N39 | N151;
assign N151 = ~mem_cmd_ready_i;
assign N50 = N39 | N152;
assign N152 = ~mem_data_cmd_ready_i;
assign N53 = ~reset_i;
endmodule |
module bsg_mux_one_hot_width_p28_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [111:0] data_i;
input [3:0] sel_one_hot_i;
output [27:0] data_o;
wire [27:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55;
wire [111:0] data_masked;
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[31] = data_i[31] & sel_one_hot_i[1];
assign data_masked[30] = data_i[30] & sel_one_hot_i[1];
assign data_masked[29] = data_i[29] & sel_one_hot_i[1];
assign data_masked[28] = data_i[28] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[63] = data_i[63] & sel_one_hot_i[2];
assign data_masked[62] = data_i[62] & sel_one_hot_i[2];
assign data_masked[61] = data_i[61] & sel_one_hot_i[2];
assign data_masked[60] = data_i[60] & sel_one_hot_i[2];
assign data_masked[59] = data_i[59] & sel_one_hot_i[2];
assign data_masked[58] = data_i[58] & sel_one_hot_i[2];
assign data_masked[57] = data_i[57] & sel_one_hot_i[2];
assign data_masked[56] = data_i[56] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[95] = data_i[95] & sel_one_hot_i[3];
assign data_masked[94] = data_i[94] & sel_one_hot_i[3];
assign data_masked[93] = data_i[93] & sel_one_hot_i[3];
assign data_masked[92] = data_i[92] & sel_one_hot_i[3];
assign data_masked[91] = data_i[91] & sel_one_hot_i[3];
assign data_masked[90] = data_i[90] & sel_one_hot_i[3];
assign data_masked[89] = data_i[89] & sel_one_hot_i[3];
assign data_masked[88] = data_i[88] & sel_one_hot_i[3];
assign data_masked[87] = data_i[87] & sel_one_hot_i[3];
assign data_masked[86] = data_i[86] & sel_one_hot_i[3];
assign data_masked[85] = data_i[85] & sel_one_hot_i[3];
assign data_masked[84] = data_i[84] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[28];
assign N0 = data_masked[84] | data_masked[56];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[29];
assign N2 = data_masked[85] | data_masked[57];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[30];
assign N4 = data_masked[86] | data_masked[58];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[31];
assign N6 = data_masked[87] | data_masked[59];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[32];
assign N8 = data_masked[88] | data_masked[60];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[33];
assign N10 = data_masked[89] | data_masked[61];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[34];
assign N12 = data_masked[90] | data_masked[62];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[35];
assign N14 = data_masked[91] | data_masked[63];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[36];
assign N16 = data_masked[92] | data_masked[64];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[37];
assign N18 = data_masked[93] | data_masked[65];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[38];
assign N20 = data_masked[94] | data_masked[66];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[39];
assign N22 = data_masked[95] | data_masked[67];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[40];
assign N24 = data_masked[96] | data_masked[68];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[41];
assign N26 = data_masked[97] | data_masked[69];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[42];
assign N28 = data_masked[98] | data_masked[70];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[43];
assign N30 = data_masked[99] | data_masked[71];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[44];
assign N32 = data_masked[100] | data_masked[72];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[45];
assign N34 = data_masked[101] | data_masked[73];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[46];
assign N36 = data_masked[102] | data_masked[74];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[47];
assign N38 = data_masked[103] | data_masked[75];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[48];
assign N40 = data_masked[104] | data_masked[76];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[49];
assign N42 = data_masked[105] | data_masked[77];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[50];
assign N44 = data_masked[106] | data_masked[78];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[51];
assign N46 = data_masked[107] | data_masked[79];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[52];
assign N48 = data_masked[108] | data_masked[80];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[53];
assign N50 = data_masked[109] | data_masked[81];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[54];
assign N52 = data_masked[110] | data_masked[82];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[55];
assign N54 = data_masked[111] | data_masked[83];
endmodule |
module bsg_mem_1r1w_synth_width_p32_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [31:0] w_data_i;
input [0:0] r_addr_i;
output [31:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [31:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [63:0] mem;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[63] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[62] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[61] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[60] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[59] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[58] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[57] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[56] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[55] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[54] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[53] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[52] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[51] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[50] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[49] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[48] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[47] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[46] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[45] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[44] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[43] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[42] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[41] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[40] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[39] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[38] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[37] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[36] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[35] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[34] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[33] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[32] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[63:32] } <= { w_data_i[31:0] };
end
if(N7) begin
{ mem[31:0] } <= { w_data_i[31:0] };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p27_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [26:0] w_data_i;
input [0:0] r_addr_i;
output [26:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [26:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [53:0] mem;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[53] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[52] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[51] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[50] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[49] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[48] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[47] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[46] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[45] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[44] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[43] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[42] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[41] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[40] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[39] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[38] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[37] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[36] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[35] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[34] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[33] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[32] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[31] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[30] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[29] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[28] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[27] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[53:27] } <= { w_data_i[26:0] };
end
if(N7) begin
{ mem[26:0] } <= { w_data_i[26:0] };
end
end
endmodule |
module bsg_mux_one_hot_width_p32_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [159:0] data_i;
input [4:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95;
wire [159:0] data_masked;
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[113] = data_i[113] & sel_one_hot_i[3];
assign data_masked[112] = data_i[112] & sel_one_hot_i[3];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_masked[159] = data_i[159] & sel_one_hot_i[4];
assign data_masked[158] = data_i[158] & sel_one_hot_i[4];
assign data_masked[157] = data_i[157] & sel_one_hot_i[4];
assign data_masked[156] = data_i[156] & sel_one_hot_i[4];
assign data_masked[155] = data_i[155] & sel_one_hot_i[4];
assign data_masked[154] = data_i[154] & sel_one_hot_i[4];
assign data_masked[153] = data_i[153] & sel_one_hot_i[4];
assign data_masked[152] = data_i[152] & sel_one_hot_i[4];
assign data_masked[151] = data_i[151] & sel_one_hot_i[4];
assign data_masked[150] = data_i[150] & sel_one_hot_i[4];
assign data_masked[149] = data_i[149] & sel_one_hot_i[4];
assign data_masked[148] = data_i[148] & sel_one_hot_i[4];
assign data_masked[147] = data_i[147] & sel_one_hot_i[4];
assign data_masked[146] = data_i[146] & sel_one_hot_i[4];
assign data_masked[145] = data_i[145] & sel_one_hot_i[4];
assign data_masked[144] = data_i[144] & sel_one_hot_i[4];
assign data_masked[143] = data_i[143] & sel_one_hot_i[4];
assign data_masked[142] = data_i[142] & sel_one_hot_i[4];
assign data_masked[141] = data_i[141] & sel_one_hot_i[4];
assign data_masked[140] = data_i[140] & sel_one_hot_i[4];
assign data_masked[139] = data_i[139] & sel_one_hot_i[4];
assign data_masked[138] = data_i[138] & sel_one_hot_i[4];
assign data_masked[137] = data_i[137] & sel_one_hot_i[4];
assign data_masked[136] = data_i[136] & sel_one_hot_i[4];
assign data_masked[135] = data_i[135] & sel_one_hot_i[4];
assign data_masked[134] = data_i[134] & sel_one_hot_i[4];
assign data_masked[133] = data_i[133] & sel_one_hot_i[4];
assign data_masked[132] = data_i[132] & sel_one_hot_i[4];
assign data_masked[131] = data_i[131] & sel_one_hot_i[4];
assign data_masked[130] = data_i[130] & sel_one_hot_i[4];
assign data_masked[129] = data_i[129] & sel_one_hot_i[4];
assign data_masked[128] = data_i[128] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[32];
assign N1 = N0 | data_masked[64];
assign N0 = data_masked[128] | data_masked[96];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[33];
assign N4 = N3 | data_masked[65];
assign N3 = data_masked[129] | data_masked[97];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[34];
assign N7 = N6 | data_masked[66];
assign N6 = data_masked[130] | data_masked[98];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[35];
assign N10 = N9 | data_masked[67];
assign N9 = data_masked[131] | data_masked[99];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[36];
assign N13 = N12 | data_masked[68];
assign N12 = data_masked[132] | data_masked[100];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[37];
assign N16 = N15 | data_masked[69];
assign N15 = data_masked[133] | data_masked[101];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[38];
assign N19 = N18 | data_masked[70];
assign N18 = data_masked[134] | data_masked[102];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[39];
assign N22 = N21 | data_masked[71];
assign N21 = data_masked[135] | data_masked[103];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[40];
assign N25 = N24 | data_masked[72];
assign N24 = data_masked[136] | data_masked[104];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[41];
assign N28 = N27 | data_masked[73];
assign N27 = data_masked[137] | data_masked[105];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[42];
assign N31 = N30 | data_masked[74];
assign N30 = data_masked[138] | data_masked[106];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[43];
assign N34 = N33 | data_masked[75];
assign N33 = data_masked[139] | data_masked[107];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[44];
assign N37 = N36 | data_masked[76];
assign N36 = data_masked[140] | data_masked[108];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[45];
assign N40 = N39 | data_masked[77];
assign N39 = data_masked[141] | data_masked[109];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[46];
assign N43 = N42 | data_masked[78];
assign N42 = data_masked[142] | data_masked[110];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[47];
assign N46 = N45 | data_masked[79];
assign N45 = data_masked[143] | data_masked[111];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[48];
assign N49 = N48 | data_masked[80];
assign N48 = data_masked[144] | data_masked[112];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[49];
assign N52 = N51 | data_masked[81];
assign N51 = data_masked[145] | data_masked[113];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[50];
assign N55 = N54 | data_masked[82];
assign N54 = data_masked[146] | data_masked[114];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[51];
assign N58 = N57 | data_masked[83];
assign N57 = data_masked[147] | data_masked[115];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[52];
assign N61 = N60 | data_masked[84];
assign N60 = data_masked[148] | data_masked[116];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[53];
assign N64 = N63 | data_masked[85];
assign N63 = data_masked[149] | data_masked[117];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[54];
assign N67 = N66 | data_masked[86];
assign N66 = data_masked[150] | data_masked[118];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[55];
assign N70 = N69 | data_masked[87];
assign N69 = data_masked[151] | data_masked[119];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[56];
assign N73 = N72 | data_masked[88];
assign N72 = data_masked[152] | data_masked[120];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[57];
assign N76 = N75 | data_masked[89];
assign N75 = data_masked[153] | data_masked[121];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[58];
assign N79 = N78 | data_masked[90];
assign N78 = data_masked[154] | data_masked[122];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[59];
assign N82 = N81 | data_masked[91];
assign N81 = data_masked[155] | data_masked[123];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[60];
assign N85 = N84 | data_masked[92];
assign N84 = data_masked[156] | data_masked[124];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[61];
assign N88 = N87 | data_masked[93];
assign N87 = data_masked[157] | data_masked[125];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[62];
assign N91 = N90 | data_masked[94];
assign N90 = data_masked[158] | data_masked[126];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[63];
assign N94 = N93 | data_masked[95];
assign N93 = data_masked[159] | data_masked[127];
endmodule |
module bsg_mesh_router_dor_decoder_x_cord_width_p1_y_cord_width_p1_dirs_lp5_XY_order_p0
(
clk_i,
v_i,
x_dirs_i,
y_dirs_i,
my_x_i,
my_y_i,
req_o
);
input [4:0] v_i;
input [4:0] x_dirs_i;
input [4:0] y_dirs_i;
input [0:0] my_x_i;
input [0:0] my_y_i;
output [24:0] req_o;
input clk_i;
wire [24:0] req_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,y_gt_0,x_lt_0,
y_lt_0,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N37,N38,N39,N40,N41,N42;
wire [4:0] x_eq,y_eq,x_gt;
wire [4:3] y_gt;
wire [4:2] x_lt;
wire [4:4] y_lt;
assign req_o[12] = 1'b0;
assign req_o[6] = 1'b0;
assign req_o[24] = 1'b0;
assign req_o[18] = 1'b0;
assign req_o[14] = 1'b0;
assign req_o[13] = 1'b0;
assign req_o[9] = 1'b0;
assign req_o[8] = 1'b0;
assign N0 = x_dirs_i[0] ^ my_x_i[0];
assign x_eq[0] = ~N0;
assign N1 = y_dirs_i[0] ^ my_y_i[0];
assign y_eq[0] = ~N1;
assign x_gt[0] = x_dirs_i[0] & N2;
assign N2 = ~my_x_i[0];
assign y_gt_0 = y_dirs_i[0] & N3;
assign N3 = ~my_y_i[0];
assign N4 = x_dirs_i[1] ^ my_x_i[0];
assign x_eq[1] = ~N4;
assign N5 = y_dirs_i[1] ^ my_y_i[0];
assign y_eq[1] = ~N5;
assign x_gt[1] = x_dirs_i[1] & N6;
assign N6 = ~my_x_i[0];
assign N7 = x_dirs_i[2] ^ my_x_i[0];
assign x_eq[2] = ~N7;
assign N8 = y_dirs_i[2] ^ my_y_i[0];
assign y_eq[2] = ~N8;
assign x_gt[2] = x_dirs_i[2] & N9;
assign N9 = ~my_x_i[0];
assign N10 = x_dirs_i[3] ^ my_x_i[0];
assign x_eq[3] = ~N10;
assign N11 = y_dirs_i[3] ^ my_y_i[0];
assign y_eq[3] = ~N11;
assign x_gt[3] = x_dirs_i[3] & N12;
assign N12 = ~my_x_i[0];
assign y_gt[3] = y_dirs_i[3] & N13;
assign N13 = ~my_y_i[0];
assign N14 = x_dirs_i[4] ^ my_x_i[0];
assign x_eq[4] = ~N14;
assign N15 = y_dirs_i[4] ^ my_y_i[0];
assign y_eq[4] = ~N15;
assign x_gt[4] = x_dirs_i[4] & N16;
assign N16 = ~my_x_i[0];
assign y_gt[4] = y_dirs_i[4] & N17;
assign N17 = ~my_y_i[0];
assign x_lt_0 = N18 & N19;
assign N18 = ~x_gt[0];
assign N19 = ~x_eq[0];
assign y_lt_0 = N20 & N21;
assign N20 = ~y_gt_0;
assign N21 = ~y_eq[0];
assign x_lt[2] = N22 & N23;
assign N22 = ~x_gt[2];
assign N23 = ~x_eq[2];
assign x_lt[3] = N24 & N25;
assign N24 = ~x_gt[3];
assign N25 = ~x_eq[3];
assign x_lt[4] = N26 & N27;
assign N26 = ~x_gt[4];
assign N27 = ~x_eq[4];
assign y_lt[4] = N28 & N29;
assign N28 = ~y_gt[4];
assign N29 = ~y_eq[4];
assign req_o[16] = N30 & x_lt[3];
assign N30 = v_i[3] & y_eq[3];
assign req_o[17] = N31 & x_gt[3];
assign N31 = v_i[3] & y_eq[3];
assign req_o[21] = N32 & x_lt[4];
assign N32 = v_i[4] & y_eq[4];
assign req_o[22] = N33 & x_gt[4];
assign N33 = v_i[4] & y_eq[4];
assign req_o[19] = v_i[3] & y_gt[3];
assign req_o[23] = v_i[4] & y_lt[4];
assign req_o[7] = N34 & x_gt[1];
assign N34 = v_i[1] & y_eq[1];
assign req_o[11] = N35 & x_lt[2];
assign N35 = v_i[2] & y_eq[2];
assign req_o[4] = v_i[0] & y_gt_0;
assign req_o[3] = v_i[0] & y_lt_0;
assign req_o[0] = N36 & y_eq[0];
assign N36 = v_i[0] & x_eq[0];
assign req_o[2] = N37 & x_gt[0];
assign N37 = v_i[0] & y_eq[0];
assign req_o[1] = N38 & x_lt_0;
assign N38 = v_i[0] & y_eq[0];
assign req_o[5] = N39 & y_eq[1];
assign N39 = v_i[1] & x_eq[1];
assign req_o[10] = N40 & y_eq[2];
assign N40 = v_i[2] & x_eq[2];
assign req_o[15] = N41 & y_eq[3];
assign N41 = v_i[3] & x_eq[3];
assign req_o[20] = N42 & y_eq[4];
assign N42 = v_i[4] & x_eq[4];
endmodule |
module bp_be_detector_vaddr_width_p56_paddr_width_p22_asid_width_p10_branch_metadata_fwd_width_p36
(
clk_i,
reset_i,
calc_status_i,
expected_npc_i,
mmu_cmd_ready_i,
chk_dispatch_v_o,
chk_roll_o,
chk_poison_isd_o,
chk_poison_ex_o
);
input [301:0] calc_status_i;
input [63:0] expected_npc_i;
input clk_i;
input reset_i;
input mmu_cmd_ready_i;
output chk_dispatch_v_o;
output chk_roll_o;
output chk_poison_isd_o;
output chk_poison_ex_o;
wire chk_dispatch_v_o,chk_roll_o,chk_poison_isd_o,chk_poison_ex_o,N0,N1,N2,N3,N4,N5,
data_haz_v,struct_haz_v,N6,mispredict_v,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,
N38,N39,N40,N41,N42,N43,N44;
wire [2:0] rs1_match_vector,rs2_match_vector,frs1_data_haz_v,frs2_data_haz_v;
wire [1:0] irs1_data_haz_v,irs2_data_haz_v;
assign chk_roll_o = calc_status_i[3];
assign N0 = calc_status_i[234:230] == calc_status_i[73:69];
assign N1 = calc_status_i[227:223] == calc_status_i[73:69];
assign N2 = calc_status_i[234:230] == calc_status_i[83:79];
assign N3 = calc_status_i[227:223] == calc_status_i[83:79];
assign N4 = calc_status_i[234:230] == calc_status_i[93:89];
assign N5 = calc_status_i[227:223] == calc_status_i[93:89];
assign N6 = calc_status_i[300:237] != expected_npc_i;
assign N7 = calc_status_i[233] | calc_status_i[234];
assign N8 = calc_status_i[232] | N7;
assign N9 = calc_status_i[231] | N8;
assign N10 = calc_status_i[230] | N9;
assign N11 = calc_status_i[226] | calc_status_i[227];
assign N12 = calc_status_i[225] | N11;
assign N13 = calc_status_i[224] | N12;
assign N14 = calc_status_i[223] | N13;
assign rs1_match_vector[0] = N10 & N0;
assign rs2_match_vector[0] = N14 & N1;
assign rs1_match_vector[1] = N10 & N2;
assign rs2_match_vector[1] = N14 & N3;
assign rs1_match_vector[2] = N10 & N4;
assign rs2_match_vector[2] = N14 & N5;
assign irs1_data_haz_v[0] = N15 & N16;
assign N15 = calc_status_i[236] & rs1_match_vector[0];
assign N16 = calc_status_i[77] | calc_status_i[76];
assign irs2_data_haz_v[0] = N17 & N18;
assign N17 = calc_status_i[229] & rs2_match_vector[0];
assign N18 = calc_status_i[77] | calc_status_i[76];
assign frs1_data_haz_v[0] = N19 & N20;
assign N19 = calc_status_i[235] & rs1_match_vector[0];
assign N20 = calc_status_i[75] | calc_status_i[74];
assign frs2_data_haz_v[0] = N21 & N22;
assign N21 = calc_status_i[228] & rs2_match_vector[0];
assign N22 = calc_status_i[75] | calc_status_i[74];
assign irs1_data_haz_v[1] = N23 & calc_status_i[86];
assign N23 = calc_status_i[236] & rs1_match_vector[1];
assign irs2_data_haz_v[1] = N24 & calc_status_i[86];
assign N24 = calc_status_i[229] & rs2_match_vector[1];
assign frs1_data_haz_v[1] = N25 & N26;
assign N25 = calc_status_i[235] & rs1_match_vector[1];
assign N26 = calc_status_i[85] | calc_status_i[84];
assign frs2_data_haz_v[1] = N27 & N28;
assign N27 = calc_status_i[228] & rs2_match_vector[1];
assign N28 = calc_status_i[85] | calc_status_i[84];
assign frs1_data_haz_v[2] = N29 & calc_status_i[94];
assign N29 = calc_status_i[235] & rs1_match_vector[2];
assign frs2_data_haz_v[2] = N30 & calc_status_i[94];
assign N30 = calc_status_i[228] & rs2_match_vector[2];
assign data_haz_v = N36 | N38;
assign N36 = N33 | N35;
assign N33 = N31 | N32;
assign N31 = irs1_data_haz_v[1] | irs1_data_haz_v[0];
assign N32 = irs2_data_haz_v[1] | irs2_data_haz_v[0];
assign N35 = N34 | frs1_data_haz_v[0];
assign N34 = frs1_data_haz_v[2] | frs1_data_haz_v[1];
assign N38 = N37 | frs2_data_haz_v[0];
assign N37 = frs2_data_haz_v[2] | frs2_data_haz_v[1];
assign struct_haz_v = ~mmu_cmd_ready_i;
assign mispredict_v = calc_status_i[301] & N6;
assign chk_dispatch_v_o = ~N39;
assign N39 = data_haz_v | struct_haz_v;
assign chk_poison_isd_o = N42 | calc_status_i[1];
assign N42 = N41 | calc_status_i[2];
assign N41 = N40 | calc_status_i[3];
assign N40 = reset_i | mispredict_v;
assign chk_poison_ex_o = N44 | calc_status_i[1];
assign N44 = N43 | calc_status_i[2];
assign N43 = reset_i | calc_status_i[3];
endmodule |
module bsg_mux_one_hot_width_p32_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [127:0] data_i;
input [3:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63;
wire [127:0] data_masked;
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[32] = data_i[32] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_masked[65] = data_i[65] & sel_one_hot_i[2];
assign data_masked[64] = data_i[64] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[113] = data_i[113] & sel_one_hot_i[3];
assign data_masked[112] = data_i[112] & sel_one_hot_i[3];
assign data_masked[111] = data_i[111] & sel_one_hot_i[3];
assign data_masked[110] = data_i[110] & sel_one_hot_i[3];
assign data_masked[109] = data_i[109] & sel_one_hot_i[3];
assign data_masked[108] = data_i[108] & sel_one_hot_i[3];
assign data_masked[107] = data_i[107] & sel_one_hot_i[3];
assign data_masked[106] = data_i[106] & sel_one_hot_i[3];
assign data_masked[105] = data_i[105] & sel_one_hot_i[3];
assign data_masked[104] = data_i[104] & sel_one_hot_i[3];
assign data_masked[103] = data_i[103] & sel_one_hot_i[3];
assign data_masked[102] = data_i[102] & sel_one_hot_i[3];
assign data_masked[101] = data_i[101] & sel_one_hot_i[3];
assign data_masked[100] = data_i[100] & sel_one_hot_i[3];
assign data_masked[99] = data_i[99] & sel_one_hot_i[3];
assign data_masked[98] = data_i[98] & sel_one_hot_i[3];
assign data_masked[97] = data_i[97] & sel_one_hot_i[3];
assign data_masked[96] = data_i[96] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[32];
assign N0 = data_masked[96] | data_masked[64];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[33];
assign N2 = data_masked[97] | data_masked[65];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[34];
assign N4 = data_masked[98] | data_masked[66];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[35];
assign N6 = data_masked[99] | data_masked[67];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[36];
assign N8 = data_masked[100] | data_masked[68];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[37];
assign N10 = data_masked[101] | data_masked[69];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[38];
assign N12 = data_masked[102] | data_masked[70];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[39];
assign N14 = data_masked[103] | data_masked[71];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[40];
assign N16 = data_masked[104] | data_masked[72];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[41];
assign N18 = data_masked[105] | data_masked[73];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[42];
assign N20 = data_masked[106] | data_masked[74];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[43];
assign N22 = data_masked[107] | data_masked[75];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[44];
assign N24 = data_masked[108] | data_masked[76];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[45];
assign N26 = data_masked[109] | data_masked[77];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[46];
assign N28 = data_masked[110] | data_masked[78];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[47];
assign N30 = data_masked[111] | data_masked[79];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[48];
assign N32 = data_masked[112] | data_masked[80];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[49];
assign N34 = data_masked[113] | data_masked[81];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[50];
assign N36 = data_masked[114] | data_masked[82];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[51];
assign N38 = data_masked[115] | data_masked[83];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[52];
assign N40 = data_masked[116] | data_masked[84];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[53];
assign N42 = data_masked[117] | data_masked[85];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[54];
assign N44 = data_masked[118] | data_masked[86];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[55];
assign N46 = data_masked[119] | data_masked[87];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[56];
assign N48 = data_masked[120] | data_masked[88];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[57];
assign N50 = data_masked[121] | data_masked[89];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[58];
assign N52 = data_masked[122] | data_masked[90];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[59];
assign N54 = data_masked[123] | data_masked[91];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[60];
assign N56 = data_masked[124] | data_masked[92];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[61];
assign N58 = data_masked[125] | data_masked[93];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[62];
assign N60 = data_masked[126] | data_masked[94];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[63];
assign N62 = data_masked[127] | data_masked[95];
endmodule |
module bsg_decode_num_out_p2
(
i,
o
);
input [0:0] i;
output [1:0] o;
wire [1:0] o;
assign o = { 1'b0, 1'b1 } << i[0];
endmodule |
module bp_be_dcache_lru_decode_ways_p8
(
way_id_i,
data_o,
mask_o
);
input [2:0] way_id_i;
output [6:0] data_o;
output [6:0] mask_o;
wire [6:0] data_o,mask_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30;
assign mask_o[0] = 1'b1;
assign N11 = N8 & N9;
assign N12 = N11 & N10;
assign N13 = way_id_i[2] | way_id_i[1];
assign N14 = N13 | N10;
assign N16 = way_id_i[2] | N9;
assign N17 = N16 | way_id_i[0];
assign N19 = N16 | N10;
assign N21 = N8 | way_id_i[1];
assign N22 = N21 | way_id_i[0];
assign N24 = N21 | N10;
assign N26 = N8 | N9;
assign N27 = N26 | way_id_i[0];
assign N29 = way_id_i[2] & way_id_i[1];
assign N30 = N29 & way_id_i[0];
assign data_o = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N12;
assign N1 = N15;
assign N2 = N18;
assign N3 = N20;
assign N4 = N23;
assign N5 = N25;
assign N6 = N28;
assign N7 = N30;
assign mask_o[6:1] = (N0)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N5)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N7)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } : 1'b0;
assign N8 = ~way_id_i[2];
assign N9 = ~way_id_i[1];
assign N10 = ~way_id_i[0];
assign N15 = ~N14;
assign N18 = ~N17;
assign N20 = ~N19;
assign N23 = ~N22;
assign N25 = ~N24;
assign N28 = ~N27;
endmodule |
module bp_cce_alu_width_p16
(
v_i,
opd_a_i,
opd_b_i,
alu_op_i,
v_o,
res_o,
branch_res_o
);
input [15:0] opd_a_i;
input [15:0] opd_b_i;
input [2:0] alu_op_i;
output [15:0] res_o;
input v_i;
output v_o;
output branch_res_o;
wire [15:0] res_o;
wire v_o,branch_res_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,v_i,equal,less,N11,N12,N13,
N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,
N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,
N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,
N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,
N94,N95,N96,N97,N98,N99,N100,N101;
assign v_o = v_i;
assign equal = opd_a_i == opd_b_i;
assign less = opd_a_i < opd_b_i;
assign N12 = alu_op_i[2] | N28;
assign N13 = N12 | alu_op_i[0];
assign N16 = N12 | N15;
assign N18 = N27 | alu_op_i[1];
assign N19 = N18 | alu_op_i[0];
assign N21 = N18 | N15;
assign N23 = alu_op_i[2] & alu_op_i[1];
assign N24 = N23 & alu_op_i[0];
assign N25 = N27 | N28;
assign N26 = N25 | alu_op_i[0];
assign N29 = N27 & N28;
assign { N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37 } = opd_a_i + opd_b_i;
assign { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53 } = opd_a_i - opd_b_i;
assign N33 = (N0)? equal :
(N1)? N31 :
(N2)? less :
(N3)? N32 :
(N4)? 1'b1 :
(N5)? 1'b0 : 1'b0;
assign N0 = N14;
assign N1 = N17;
assign N2 = N20;
assign N3 = N22;
assign N4 = N24;
assign N5 = N30;
assign branch_res_o = (N6)? N33 :
(N7)? 1'b0 : 1'b0;
assign N6 = v_i;
assign N7 = N11;
assign { N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69 } = (N8)? { N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37 } :
(N9)? { N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53 } : 1'b0;
assign N8 = N15;
assign N9 = alu_op_i[0];
assign { N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85 } = (N10)? { N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69 } :
(N35)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N10 = N29;
assign res_o = (N6)? { N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N11 = ~v_i;
assign N14 = ~N13;
assign N15 = ~alu_op_i[0];
assign N17 = ~N16;
assign N20 = ~N19;
assign N22 = ~N21;
assign N27 = ~alu_op_i[2];
assign N28 = ~alu_op_i[1];
assign N30 = N101 | N29;
assign N101 = ~N26;
assign N31 = ~equal;
assign N32 = less | equal;
assign N34 = v_i;
assign N35 = ~N29;
assign N36 = N34 & N29;
endmodule |
module bsg_mux_width_p16_els_p4
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [1:0] sel_i;
output [15:0] data_o;
wire [15:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[15] = (N2)? data_i[15] :
(N4)? data_i[31] :
(N3)? data_i[47] :
(N5)? data_i[63] : 1'b0;
assign data_o[14] = (N2)? data_i[14] :
(N4)? data_i[30] :
(N3)? data_i[46] :
(N5)? data_i[62] : 1'b0;
assign data_o[13] = (N2)? data_i[13] :
(N4)? data_i[29] :
(N3)? data_i[45] :
(N5)? data_i[61] : 1'b0;
assign data_o[12] = (N2)? data_i[12] :
(N4)? data_i[28] :
(N3)? data_i[44] :
(N5)? data_i[60] : 1'b0;
assign data_o[11] = (N2)? data_i[11] :
(N4)? data_i[27] :
(N3)? data_i[43] :
(N5)? data_i[59] : 1'b0;
assign data_o[10] = (N2)? data_i[10] :
(N4)? data_i[26] :
(N3)? data_i[42] :
(N5)? data_i[58] : 1'b0;
assign data_o[9] = (N2)? data_i[9] :
(N4)? data_i[25] :
(N3)? data_i[41] :
(N5)? data_i[57] : 1'b0;
assign data_o[8] = (N2)? data_i[8] :
(N4)? data_i[24] :
(N3)? data_i[40] :
(N5)? data_i[56] : 1'b0;
assign data_o[7] = (N2)? data_i[7] :
(N4)? data_i[23] :
(N3)? data_i[39] :
(N5)? data_i[55] : 1'b0;
assign data_o[6] = (N2)? data_i[6] :
(N4)? data_i[22] :
(N3)? data_i[38] :
(N5)? data_i[54] : 1'b0;
assign data_o[5] = (N2)? data_i[5] :
(N4)? data_i[21] :
(N3)? data_i[37] :
(N5)? data_i[53] : 1'b0;
assign data_o[4] = (N2)? data_i[4] :
(N4)? data_i[20] :
(N3)? data_i[36] :
(N5)? data_i[52] : 1'b0;
assign data_o[3] = (N2)? data_i[3] :
(N4)? data_i[19] :
(N3)? data_i[35] :
(N5)? data_i[51] : 1'b0;
assign data_o[2] = (N2)? data_i[2] :
(N4)? data_i[18] :
(N3)? data_i[34] :
(N5)? data_i[50] : 1'b0;
assign data_o[1] = (N2)? data_i[1] :
(N4)? data_i[17] :
(N3)? data_i[33] :
(N5)? data_i[49] : 1'b0;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[16] :
(N3)? data_i[32] :
(N5)? data_i[48] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule |
module bsg_mux_one_hot_width_p38_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [189:0] data_i;
input [4:0] sel_one_hot_i;
output [37:0] data_o;
wire [37:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113;
wire [189:0] data_masked;
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[2];
assign data_masked[112] = data_i[112] & sel_one_hot_i[2];
assign data_masked[111] = data_i[111] & sel_one_hot_i[2];
assign data_masked[110] = data_i[110] & sel_one_hot_i[2];
assign data_masked[109] = data_i[109] & sel_one_hot_i[2];
assign data_masked[108] = data_i[108] & sel_one_hot_i[2];
assign data_masked[107] = data_i[107] & sel_one_hot_i[2];
assign data_masked[106] = data_i[106] & sel_one_hot_i[2];
assign data_masked[105] = data_i[105] & sel_one_hot_i[2];
assign data_masked[104] = data_i[104] & sel_one_hot_i[2];
assign data_masked[103] = data_i[103] & sel_one_hot_i[2];
assign data_masked[102] = data_i[102] & sel_one_hot_i[2];
assign data_masked[101] = data_i[101] & sel_one_hot_i[2];
assign data_masked[100] = data_i[100] & sel_one_hot_i[2];
assign data_masked[99] = data_i[99] & sel_one_hot_i[2];
assign data_masked[98] = data_i[98] & sel_one_hot_i[2];
assign data_masked[97] = data_i[97] & sel_one_hot_i[2];
assign data_masked[96] = data_i[96] & sel_one_hot_i[2];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[3];
assign data_masked[150] = data_i[150] & sel_one_hot_i[3];
assign data_masked[149] = data_i[149] & sel_one_hot_i[3];
assign data_masked[148] = data_i[148] & sel_one_hot_i[3];
assign data_masked[147] = data_i[147] & sel_one_hot_i[3];
assign data_masked[146] = data_i[146] & sel_one_hot_i[3];
assign data_masked[145] = data_i[145] & sel_one_hot_i[3];
assign data_masked[144] = data_i[144] & sel_one_hot_i[3];
assign data_masked[143] = data_i[143] & sel_one_hot_i[3];
assign data_masked[142] = data_i[142] & sel_one_hot_i[3];
assign data_masked[141] = data_i[141] & sel_one_hot_i[3];
assign data_masked[140] = data_i[140] & sel_one_hot_i[3];
assign data_masked[139] = data_i[139] & sel_one_hot_i[3];
assign data_masked[138] = data_i[138] & sel_one_hot_i[3];
assign data_masked[137] = data_i[137] & sel_one_hot_i[3];
assign data_masked[136] = data_i[136] & sel_one_hot_i[3];
assign data_masked[135] = data_i[135] & sel_one_hot_i[3];
assign data_masked[134] = data_i[134] & sel_one_hot_i[3];
assign data_masked[133] = data_i[133] & sel_one_hot_i[3];
assign data_masked[132] = data_i[132] & sel_one_hot_i[3];
assign data_masked[131] = data_i[131] & sel_one_hot_i[3];
assign data_masked[130] = data_i[130] & sel_one_hot_i[3];
assign data_masked[129] = data_i[129] & sel_one_hot_i[3];
assign data_masked[128] = data_i[128] & sel_one_hot_i[3];
assign data_masked[127] = data_i[127] & sel_one_hot_i[3];
assign data_masked[126] = data_i[126] & sel_one_hot_i[3];
assign data_masked[125] = data_i[125] & sel_one_hot_i[3];
assign data_masked[124] = data_i[124] & sel_one_hot_i[3];
assign data_masked[123] = data_i[123] & sel_one_hot_i[3];
assign data_masked[122] = data_i[122] & sel_one_hot_i[3];
assign data_masked[121] = data_i[121] & sel_one_hot_i[3];
assign data_masked[120] = data_i[120] & sel_one_hot_i[3];
assign data_masked[119] = data_i[119] & sel_one_hot_i[3];
assign data_masked[118] = data_i[118] & sel_one_hot_i[3];
assign data_masked[117] = data_i[117] & sel_one_hot_i[3];
assign data_masked[116] = data_i[116] & sel_one_hot_i[3];
assign data_masked[115] = data_i[115] & sel_one_hot_i[3];
assign data_masked[114] = data_i[114] & sel_one_hot_i[3];
assign data_masked[189] = data_i[189] & sel_one_hot_i[4];
assign data_masked[188] = data_i[188] & sel_one_hot_i[4];
assign data_masked[187] = data_i[187] & sel_one_hot_i[4];
assign data_masked[186] = data_i[186] & sel_one_hot_i[4];
assign data_masked[185] = data_i[185] & sel_one_hot_i[4];
assign data_masked[184] = data_i[184] & sel_one_hot_i[4];
assign data_masked[183] = data_i[183] & sel_one_hot_i[4];
assign data_masked[182] = data_i[182] & sel_one_hot_i[4];
assign data_masked[181] = data_i[181] & sel_one_hot_i[4];
assign data_masked[180] = data_i[180] & sel_one_hot_i[4];
assign data_masked[179] = data_i[179] & sel_one_hot_i[4];
assign data_masked[178] = data_i[178] & sel_one_hot_i[4];
assign data_masked[177] = data_i[177] & sel_one_hot_i[4];
assign data_masked[176] = data_i[176] & sel_one_hot_i[4];
assign data_masked[175] = data_i[175] & sel_one_hot_i[4];
assign data_masked[174] = data_i[174] & sel_one_hot_i[4];
assign data_masked[173] = data_i[173] & sel_one_hot_i[4];
assign data_masked[172] = data_i[172] & sel_one_hot_i[4];
assign data_masked[171] = data_i[171] & sel_one_hot_i[4];
assign data_masked[170] = data_i[170] & sel_one_hot_i[4];
assign data_masked[169] = data_i[169] & sel_one_hot_i[4];
assign data_masked[168] = data_i[168] & sel_one_hot_i[4];
assign data_masked[167] = data_i[167] & sel_one_hot_i[4];
assign data_masked[166] = data_i[166] & sel_one_hot_i[4];
assign data_masked[165] = data_i[165] & sel_one_hot_i[4];
assign data_masked[164] = data_i[164] & sel_one_hot_i[4];
assign data_masked[163] = data_i[163] & sel_one_hot_i[4];
assign data_masked[162] = data_i[162] & sel_one_hot_i[4];
assign data_masked[161] = data_i[161] & sel_one_hot_i[4];
assign data_masked[160] = data_i[160] & sel_one_hot_i[4];
assign data_masked[159] = data_i[159] & sel_one_hot_i[4];
assign data_masked[158] = data_i[158] & sel_one_hot_i[4];
assign data_masked[157] = data_i[157] & sel_one_hot_i[4];
assign data_masked[156] = data_i[156] & sel_one_hot_i[4];
assign data_masked[155] = data_i[155] & sel_one_hot_i[4];
assign data_masked[154] = data_i[154] & sel_one_hot_i[4];
assign data_masked[153] = data_i[153] & sel_one_hot_i[4];
assign data_masked[152] = data_i[152] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[38];
assign N1 = N0 | data_masked[76];
assign N0 = data_masked[152] | data_masked[114];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[39];
assign N4 = N3 | data_masked[77];
assign N3 = data_masked[153] | data_masked[115];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[40];
assign N7 = N6 | data_masked[78];
assign N6 = data_masked[154] | data_masked[116];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[41];
assign N10 = N9 | data_masked[79];
assign N9 = data_masked[155] | data_masked[117];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[42];
assign N13 = N12 | data_masked[80];
assign N12 = data_masked[156] | data_masked[118];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[43];
assign N16 = N15 | data_masked[81];
assign N15 = data_masked[157] | data_masked[119];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[44];
assign N19 = N18 | data_masked[82];
assign N18 = data_masked[158] | data_masked[120];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[45];
assign N22 = N21 | data_masked[83];
assign N21 = data_masked[159] | data_masked[121];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[46];
assign N25 = N24 | data_masked[84];
assign N24 = data_masked[160] | data_masked[122];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[47];
assign N28 = N27 | data_masked[85];
assign N27 = data_masked[161] | data_masked[123];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[48];
assign N31 = N30 | data_masked[86];
assign N30 = data_masked[162] | data_masked[124];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[49];
assign N34 = N33 | data_masked[87];
assign N33 = data_masked[163] | data_masked[125];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[50];
assign N37 = N36 | data_masked[88];
assign N36 = data_masked[164] | data_masked[126];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[51];
assign N40 = N39 | data_masked[89];
assign N39 = data_masked[165] | data_masked[127];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[52];
assign N43 = N42 | data_masked[90];
assign N42 = data_masked[166] | data_masked[128];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[53];
assign N46 = N45 | data_masked[91];
assign N45 = data_masked[167] | data_masked[129];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[54];
assign N49 = N48 | data_masked[92];
assign N48 = data_masked[168] | data_masked[130];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[55];
assign N52 = N51 | data_masked[93];
assign N51 = data_masked[169] | data_masked[131];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[56];
assign N55 = N54 | data_masked[94];
assign N54 = data_masked[170] | data_masked[132];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[57];
assign N58 = N57 | data_masked[95];
assign N57 = data_masked[171] | data_masked[133];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[58];
assign N61 = N60 | data_masked[96];
assign N60 = data_masked[172] | data_masked[134];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[59];
assign N64 = N63 | data_masked[97];
assign N63 = data_masked[173] | data_masked[135];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[60];
assign N67 = N66 | data_masked[98];
assign N66 = data_masked[174] | data_masked[136];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[61];
assign N70 = N69 | data_masked[99];
assign N69 = data_masked[175] | data_masked[137];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[62];
assign N73 = N72 | data_masked[100];
assign N72 = data_masked[176] | data_masked[138];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[63];
assign N76 = N75 | data_masked[101];
assign N75 = data_masked[177] | data_masked[139];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[64];
assign N79 = N78 | data_masked[102];
assign N78 = data_masked[178] | data_masked[140];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[65];
assign N82 = N81 | data_masked[103];
assign N81 = data_masked[179] | data_masked[141];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[66];
assign N85 = N84 | data_masked[104];
assign N84 = data_masked[180] | data_masked[142];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[67];
assign N88 = N87 | data_masked[105];
assign N87 = data_masked[181] | data_masked[143];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[68];
assign N91 = N90 | data_masked[106];
assign N90 = data_masked[182] | data_masked[144];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[69];
assign N94 = N93 | data_masked[107];
assign N93 = data_masked[183] | data_masked[145];
assign data_o[32] = N98 | data_masked[32];
assign N98 = N97 | data_masked[70];
assign N97 = N96 | data_masked[108];
assign N96 = data_masked[184] | data_masked[146];
assign data_o[33] = N101 | data_masked[33];
assign N101 = N100 | data_masked[71];
assign N100 = N99 | data_masked[109];
assign N99 = data_masked[185] | data_masked[147];
assign data_o[34] = N104 | data_masked[34];
assign N104 = N103 | data_masked[72];
assign N103 = N102 | data_masked[110];
assign N102 = data_masked[186] | data_masked[148];
assign data_o[35] = N107 | data_masked[35];
assign N107 = N106 | data_masked[73];
assign N106 = N105 | data_masked[111];
assign N105 = data_masked[187] | data_masked[149];
assign data_o[36] = N110 | data_masked[36];
assign N110 = N109 | data_masked[74];
assign N109 = N108 | data_masked[112];
assign N108 = data_masked[188] | data_masked[150];
assign data_o[37] = N113 | data_masked[37];
assign N113 = N112 | data_masked[75];
assign N112 = N111 | data_masked[113];
assign N111 = data_masked[189] | data_masked[151];
endmodule |
module rvdff_WIDTH1
(
din,
clk,
rst_l,
dout
);
input [0:0] din;
output [0:0] dout;
input clk;
input rst_l;
wire N0;
reg [0:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH31
(
din,
clk,
rst_l,
dout
);
input [30:0] din;
output [30:0] dout;
input clk;
input rst_l;
wire N0;
reg [30:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH13
(
din,
clk,
rst_l,
dout
);
input [12:0] din;
output [12:0] dout;
input clk;
input rst_l;
wire N0;
reg [12:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH67
(
din,
clk,
rst_l,
dout
);
input [66:0] din;
output [66:0] dout;
input clk;
input rst_l;
wire N0;
reg [66:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[66] <= 1'b0;
end else if(1'b1) begin
dout[66] <= din[66];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[65] <= 1'b0;
end else if(1'b1) begin
dout[65] <= din[65];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[64] <= 1'b0;
end else if(1'b1) begin
dout[64] <= din[64];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[63] <= 1'b0;
end else if(1'b1) begin
dout[63] <= din[63];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[62] <= 1'b0;
end else if(1'b1) begin
dout[62] <= din[62];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[61] <= 1'b0;
end else if(1'b1) begin
dout[61] <= din[61];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[60] <= 1'b0;
end else if(1'b1) begin
dout[60] <= din[60];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[59] <= 1'b0;
end else if(1'b1) begin
dout[59] <= din[59];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[58] <= 1'b0;
end else if(1'b1) begin
dout[58] <= din[58];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[57] <= 1'b0;
end else if(1'b1) begin
dout[57] <= din[57];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[56] <= 1'b0;
end else if(1'b1) begin
dout[56] <= din[56];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[55] <= 1'b0;
end else if(1'b1) begin
dout[55] <= din[55];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[54] <= 1'b0;
end else if(1'b1) begin
dout[54] <= din[54];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[53] <= 1'b0;
end else if(1'b1) begin
dout[53] <= din[53];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[52] <= 1'b0;
end else if(1'b1) begin
dout[52] <= din[52];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[51] <= 1'b0;
end else if(1'b1) begin
dout[51] <= din[51];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[50] <= 1'b0;
end else if(1'b1) begin
dout[50] <= din[50];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[49] <= 1'b0;
end else if(1'b1) begin
dout[49] <= din[49];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[48] <= 1'b0;
end else if(1'b1) begin
dout[48] <= din[48];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[47] <= 1'b0;
end else if(1'b1) begin
dout[47] <= din[47];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[46] <= 1'b0;
end else if(1'b1) begin
dout[46] <= din[46];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[45] <= 1'b0;
end else if(1'b1) begin
dout[45] <= din[45];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[44] <= 1'b0;
end else if(1'b1) begin
dout[44] <= din[44];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[43] <= 1'b0;
end else if(1'b1) begin
dout[43] <= din[43];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[42] <= 1'b0;
end else if(1'b1) begin
dout[42] <= din[42];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[41] <= 1'b0;
end else if(1'b1) begin
dout[41] <= din[41];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[40] <= 1'b0;
end else if(1'b1) begin
dout[40] <= din[40];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[39] <= 1'b0;
end else if(1'b1) begin
dout[39] <= din[39];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[38] <= 1'b0;
end else if(1'b1) begin
dout[38] <= din[38];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[37] <= 1'b0;
end else if(1'b1) begin
dout[37] <= din[37];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH37
(
din,
clk,
rst_l,
dout
);
input [36:0] din;
output [36:0] dout;
input clk;
input rst_l;
wire N0;
reg [36:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvbtb_tag_hash
(
pc,
hash
);
input [31:1] pc;
output [8:0] hash;
wire [8:0] hash;
assign hash[8] = pc[23] ^ pc[14];
assign hash[7] = pc[22] ^ pc[13];
assign hash[6] = pc[21] ^ pc[12];
assign hash[5] = pc[20] ^ pc[11];
assign hash[4] = pc[19] ^ pc[10];
assign hash[3] = pc[18] ^ pc[9];
assign hash[2] = pc[17] ^ pc[8];
assign hash[1] = pc[16] ^ pc[7];
assign hash[0] = pc[15] ^ pc[6];
endmodule |
module rvdff_WIDTH16
(
din,
clk,
rst_l,
dout
);
input [15:0] din;
output [15:0] dout;
input clk;
input rst_l;
wire N0;
reg [15:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH7
(
din,
clk,
rst_l,
dout
);
input [6:0] din;
output [6:0] dout;
input clk;
input rst_l;
wire N0;
reg [6:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module dec_dec_ctl
(
inst,
out_alu_,
out_rs1_,
out_rs2_,
out_imm12_,
out_rd_,
out_shimm5_,
out_imm20_,
out_pc_,
out_load_,
out_store_,
out_lsu_,
out_add_,
out_sub_,
out_land_,
out_lor_,
out_lxor_,
out_sll_,
out_sra_,
out_srl_,
out_slt_,
out_unsign_,
out_condbr_,
out_beq_,
out_bne_,
out_bge_,
out_blt_,
out_jal_,
out_by_,
out_half_,
out_word_,
out_csr_read_,
out_csr_clr_,
out_csr_set_,
out_csr_write_,
out_csr_imm_,
out_presync_,
out_postsync_,
out_ebreak_,
out_ecall_,
out_mret_,
out_mul_,
out_rs1_sign_,
out_rs2_sign_,
out_low_,
out_div_,
out_rem_,
out_fence_,
out_fence_i_,
out_pm_alu_,
out_legal_
);
input [31:0] inst;
output out_alu_;
output out_rs1_;
output out_rs2_;
output out_imm12_;
output out_rd_;
output out_shimm5_;
output out_imm20_;
output out_pc_;
output out_load_;
output out_store_;
output out_lsu_;
output out_add_;
output out_sub_;
output out_land_;
output out_lor_;
output out_lxor_;
output out_sll_;
output out_sra_;
output out_srl_;
output out_slt_;
output out_unsign_;
output out_condbr_;
output out_beq_;
output out_bne_;
output out_bge_;
output out_blt_;
output out_jal_;
output out_by_;
output out_half_;
output out_word_;
output out_csr_read_;
output out_csr_clr_;
output out_csr_set_;
output out_csr_write_;
output out_csr_imm_;
output out_presync_;
output out_postsync_;
output out_ebreak_;
output out_ecall_;
output out_mret_;
output out_mul_;
output out_rs1_sign_;
output out_rs2_sign_;
output out_low_;
output out_div_;
output out_rem_;
output out_fence_;
output out_fence_i_;
output out_pm_alu_;
output out_legal_;
wire out_alu_,out_rs1_,out_rs2_,out_imm12_,out_rd_,out_shimm5_,out_imm20_,out_pc_,
out_load_,out_store_,out_lsu_,out_add_,out_sub_,out_land_,out_lor_,out_lxor_,
out_sll_,out_sra_,out_srl_,out_slt_,out_unsign_,out_condbr_,out_beq_,out_bne_,
out_bge_,out_blt_,out_jal_,out_by_,out_half_,out_word_,out_csr_read_,out_csr_clr_,
out_csr_set_,out_csr_write_,out_csr_imm_,out_presync_,out_postsync_,out_ebreak_,
out_ecall_,out_mret_,out_mul_,out_rs1_sign_,out_rs2_sign_,out_low_,out_div_,out_rem_,
out_fence_,out_fence_i_,out_pm_alu_,out_legal_,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,
N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,
N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,
N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,
N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,
N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,
N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,
N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,
N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,
N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,
N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,
N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,
N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,
N252,N253,N254,N255,N256,N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,
N268,N269,N270,N271,N272,N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,
N284,N285,N286,N287,N288,N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,
N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,
N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,
N332,N333,N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,
N348,N349,N350,N351,N352,N353,N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,
N364,N365,N366,N367,N368,N369,N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,
N380,N381,N382,N383,N384,N385,N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,
N396,N397,N398,N399,N400,N401,N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,
N412,N413,N414,N415,N416,N417,N418,N419,N420,N421,N422,N423,N424,N425,N426,N427,
N428,N429,N430,N431,N432,N433,N434,N435,N436,N437,N438,N439,N440,N441,N442,N443,
N444,N445,N446,N447,N448,N449,N450,N451,N452,N453,N454,N455,N456,N457,N458,N459,
N460,N461,N462,N463,N464,N465,N466,N467,N468,N469,N470,N471,N472,N473,N474,N475,
N476,N477,N478,N479,N480,N481,N482,N483,N484,N485,N486,N487,N488,N489,N490,N491,
N492,N493,N494,N495,N496,N497,N498,N499,N500,N501,N502,N503,N504,N505,N506,N507,
N508,N509,N510,N511,N512,N513,N514,N515,N516,N517,N518,N519,N520,N521,N522,N523,
N524,N525,N526,N527,N528,N529,N530,N531,N532,N533,N534,N535,N536,N537,N538,N539,
N540,N541,N542,N543,N544,N545,N546,N547,N548,N549,N550,N551,N552,N553,N554,N555,
N556,N557,N558,N559,N560,N561,N562,N563,N564,N565,N566,N567,N568,N569,N570,N571,
N572,N573,N574,N575,N576,N577,N578,N579,N580,N581,N582,N583,N584,N585,N586,N587,
N588,N589,N590,N591,N592,N593,N594,N595,N596,N597,N598,N599,N600,N601,N602,N603,
N604,N605,N606,N607,N608,N609,N610,N611,N612,N613,N614,N615,N616,N617,N618,N619,
N620,N621,N622,N623,N624,N625,N626,N627,N628,N629,N630,N631,N632,N633,N634,N635,
N636,N637,N638,N639,N640,N641,N642,N643,N644,N645,N646,N647,N648,N649,N650,N651,
N652,N653,N654,N655,N656,N657,N658,N659,N660,N661,N662,N663,N664,N665,N666,N667,
N668,N669,N670,N671,N672,N673,N674,N675,N676,N677,N678,N679,N680,N681,N682,N683,
N684,N685,N686,N687,N688,N689,N690,N691,N692,N693,N694,N695,N696,N697,N698,N699,
N700,N701,N702,N703,N704,N705,N706,N707,N708,N709,N710,N711,N712,N713,N714,N715,
N716,N717,N718,N719,N720,N721,N722,N723,N724,N725,N726;
assign out_alu_ = N32 | N34;
assign N32 = N29 | N31;
assign N29 = inst[2] | inst[6];
assign N31 = N30 & inst[4];
assign N30 = ~inst[25];
assign N34 = N33 & inst[4];
assign N33 = ~inst[5];
assign N0 = ~inst[13];
assign N1 = ~inst[2];
assign out_rs1_ = N71 | N73;
assign N71 = N67 | N70;
assign N67 = N64 | N66;
assign N64 = N61 | N63;
assign N61 = N58 | N60;
assign N58 = N55 | N57;
assign N55 = N52 | N54;
assign N52 = N49 | N51;
assign N49 = N46 | N48;
assign N46 = N43 | N45;
assign N43 = N40 | N42;
assign N40 = N37 | N39;
assign N37 = N36 & N1;
assign N36 = N35 & N0;
assign N35 = ~inst[14];
assign N39 = N38 & N1;
assign N38 = N0 & inst[11];
assign N42 = N41 & N1;
assign N41 = inst[19] & inst[13];
assign N45 = N44 & N1;
assign N44 = N0 & inst[10];
assign N48 = N47 & N1;
assign N47 = inst[18] & inst[13];
assign N51 = N50 & N1;
assign N50 = N0 & inst[9];
assign N54 = N53 & N1;
assign N53 = inst[17] & inst[13];
assign N57 = N56 & N1;
assign N56 = N0 & inst[8];
assign N60 = N59 & N1;
assign N59 = inst[16] & inst[13];
assign N63 = N62 & N1;
assign N62 = N0 & inst[7];
assign N66 = N65 & N1;
assign N65 = inst[15] & inst[13];
assign N70 = N68 & N69;
assign N68 = ~inst[4];
assign N69 = ~inst[3];
assign N73 = N72 & N1;
assign N72 = ~inst[6];
assign out_rs2_ = N75 | N77;
assign N75 = N74 & N1;
assign N74 = inst[5] & N68;
assign N77 = N76 & N1;
assign N76 = N72 & inst[5];
assign N2 = ~inst[12];
assign out_imm12_ = N87 | N90;
assign N87 = N83 | N86;
assign N83 = N79 | N82;
assign N79 = N78 & inst[2];
assign N78 = N68 & N69;
assign N82 = N81 & N1;
assign N81 = N80 & inst[4];
assign N80 = inst[13] & N33;
assign N86 = N85 & inst[4];
assign N85 = N84 & inst[6];
assign N84 = N0 & N2;
assign N90 = N89 & N1;
assign N89 = N88 & inst[4];
assign N88 = N2 & N33;
assign out_rd_ = N93 | inst[4];
assign N93 = N91 | N92;
assign N91 = N33 & N1;
assign N92 = inst[5] & inst[2];
assign out_shimm5_ = N96 & N1;
assign N96 = N95 & inst[4];
assign N95 = N94 & N33;
assign N94 = N0 & inst[12];
assign out_imm20_ = N97 | N98;
assign N97 = inst[5] & inst[3];
assign N98 = inst[4] & inst[2];
assign out_pc_ = N100 | N101;
assign N100 = N99 & inst[2];
assign N99 = N33 & N69;
assign N101 = inst[5] & inst[3];
assign out_load_ = N102 & N1;
assign N102 = N33 & N68;
assign out_store_ = N103 & N68;
assign N103 = N72 & inst[5];
assign out_lsu_ = N104 & N1;
assign N104 = N72 & N68;
assign out_add_ = N111 | N119;
assign N111 = N108 | N110;
assign N108 = N107 & inst[4];
assign N107 = N106 & N33;
assign N106 = N105 & N2;
assign N105 = N35 & N0;
assign N110 = N109 & inst[2];
assign N109 = N33 & N69;
assign N119 = N118 & N1;
assign N118 = N117 & inst[4];
assign N117 = N116 & N72;
assign N116 = N115 & N2;
assign N115 = N114 & N0;
assign N114 = N113 & N35;
assign N113 = N112 & N30;
assign N112 = ~inst[30];
assign out_sub_ = N135 | N137;
assign N135 = N130 | N134;
assign N130 = N124 | N129;
assign N124 = N123 & N1;
assign N123 = N122 & inst[4];
assign N122 = N121 & inst[5];
assign N121 = N120 & N72;
assign N120 = inst[30] & N2;
assign N129 = N128 & N1;
assign N128 = N127 & inst[4];
assign N127 = N126 & N72;
assign N126 = N125 & inst[13];
assign N125 = N30 & N35;
assign N134 = N133 & N1;
assign N133 = N132 & inst[4];
assign N132 = N131 & N33;
assign N131 = N35 & inst[13];
assign N137 = N136 & N1;
assign N136 = inst[6] & N68;
assign out_land_ = N141 | N146;
assign N141 = N140 & N1;
assign N140 = N139 & N33;
assign N139 = N138 & inst[12];
assign N138 = inst[14] & inst[13];
assign N146 = N145 & N1;
assign N145 = N144 & N72;
assign N144 = N143 & inst[12];
assign N143 = N142 & inst[13];
assign N142 = N30 & inst[14];
assign out_lor_ = N179 | N181;
assign N179 = N176 | N178;
assign N176 = N173 | N175;
assign N173 = N170 | N172;
assign N170 = N167 | N169;
assign N167 = N162 | N166;
assign N162 = N159 | N161;
assign N159 = N156 | N158;
assign N156 = N153 | N155;
assign N153 = N147 | N152;
assign N147 = N72 & inst[3];
assign N152 = N151 & N1;
assign N151 = N150 & inst[4];
assign N150 = N149 & N2;
assign N149 = N148 & inst[13];
assign N148 = N30 & inst[14];
assign N155 = N154 & inst[2];
assign N154 = inst[5] & inst[4];
assign N158 = N157 & inst[4];
assign N157 = N2 & inst[6];
assign N161 = N160 & inst[4];
assign N160 = inst[13] & inst[6];
assign N166 = N165 & N1;
assign N165 = N164 & N33;
assign N164 = N163 & N2;
assign N163 = inst[14] & inst[13];
assign N169 = N168 & inst[4];
assign N168 = inst[7] & inst[6];
assign N172 = N171 & inst[4];
assign N171 = inst[8] & inst[6];
assign N175 = N174 & inst[4];
assign N174 = inst[9] & inst[6];
assign N178 = N177 & inst[4];
assign N177 = inst[10] & inst[6];
assign N181 = N180 & inst[4];
assign N180 = inst[11] & inst[6];
assign out_lxor_ = N186 | N191;
assign N186 = N185 & N1;
assign N185 = N184 & inst[4];
assign N184 = N183 & N2;
assign N183 = N182 & N0;
assign N182 = N30 & inst[14];
assign N191 = N190 & N1;
assign N190 = N189 & inst[4];
assign N189 = N188 & N33;
assign N188 = N187 & N2;
assign N187 = inst[14] & N0;
assign out_sll_ = N196 & N1;
assign N196 = N195 & inst[4];
assign N195 = N194 & N72;
assign N194 = N193 & inst[12];
assign N193 = N192 & N0;
assign N192 = N30 & N35;
assign out_sra_ = N200 & N1;
assign N200 = N199 & inst[4];
assign N199 = N198 & N72;
assign N198 = N197 & inst[12];
assign N197 = inst[30] & N0;
assign out_srl_ = N206 & N1;
assign N206 = N205 & inst[4];
assign N205 = N204 & N72;
assign N204 = N203 & inst[12];
assign N203 = N202 & N0;
assign N202 = N201 & inst[14];
assign N201 = N112 & N30;
assign out_slt_ = N211 | N215;
assign N211 = N210 & N1;
assign N210 = N209 & inst[4];
assign N209 = N208 & N72;
assign N208 = N207 & inst[13];
assign N207 = N30 & N35;
assign N215 = N214 & N1;
assign N214 = N213 & inst[4];
assign N213 = N212 & N33;
assign N212 = N35 & inst[13];
assign out_unsign_ = N232 | N237;
assign N232 = N226 | N231;
assign N226 = N223 | N225;
assign N223 = N219 | N222;
assign N219 = N218 & N1;
assign N218 = N217 & N33;
assign N217 = N216 & inst[12];
assign N216 = N35 & inst[13];
assign N222 = N221 & N1;
assign N221 = N220 & N68;
assign N220 = inst[13] & inst[6];
assign N225 = N224 & N68;
assign N224 = inst[14] & N33;
assign N231 = N230 & N1;
assign N230 = N229 & N72;
assign N229 = N228 & inst[12];
assign N228 = N227 & inst[13];
assign N227 = N30 & N35;
assign N237 = N236 & N1;
assign N236 = N235 & inst[5];
assign N235 = N234 & N72;
assign N234 = N233 & inst[12];
assign N233 = inst[25] & inst[14];
assign out_condbr_ = N238 & N1;
assign N238 = inst[6] & N68;
assign out_beq_ = N241 & N1;
assign N241 = N240 & N68;
assign N240 = N239 & inst[6];
assign N239 = N35 & N2;
assign out_bne_ = N244 & N1;
assign N244 = N243 & N68;
assign N243 = N242 & inst[6];
assign N242 = N35 & inst[12];
assign out_bge_ = N247 & N1;
assign N247 = N246 & N68;
assign N246 = N245 & inst[5];
assign N245 = inst[14] & inst[12];
assign out_blt_ = N250 & N1;
assign N250 = N249 & N68;
assign N249 = N248 & inst[5];
assign N248 = inst[14] & N2;
assign out_jal_ = inst[6] & inst[2];
assign out_by_ = N253 & N1;
assign N253 = N252 & N68;
assign N252 = N251 & N72;
assign N251 = N0 & N2;
assign out_half_ = N255 & N1;
assign N255 = N254 & N68;
assign N254 = inst[12] & N72;
assign out_word_ = N256 & N68;
assign N256 = inst[13] & N72;
assign out_csr_read_ = N270 | N272;
assign N270 = N267 | N269;
assign N267 = N264 | N266;
assign N264 = N261 | N263;
assign N261 = N258 | N260;
assign N258 = N257 & inst[4];
assign N257 = inst[13] & inst[6];
assign N260 = N259 & inst[4];
assign N259 = inst[7] & inst[6];
assign N263 = N262 & inst[4];
assign N262 = inst[8] & inst[6];
assign N266 = N265 & inst[4];
assign N265 = inst[9] & inst[6];
assign N269 = N268 & inst[4];
assign N268 = inst[10] & inst[6];
assign N272 = N271 & inst[4];
assign N271 = inst[11] & inst[6];
assign out_csr_clr_ = N291 | N295;
assign N291 = N286 | N290;
assign N286 = N281 | N285;
assign N281 = N276 | N280;
assign N276 = N275 & inst[4];
assign N275 = N274 & inst[6];
assign N274 = N273 & inst[12];
assign N273 = inst[15] & inst[13];
assign N280 = N279 & inst[4];
assign N279 = N278 & inst[6];
assign N278 = N277 & inst[12];
assign N277 = inst[16] & inst[13];
assign N285 = N284 & inst[4];
assign N284 = N283 & inst[6];
assign N283 = N282 & inst[12];
assign N282 = inst[17] & inst[13];
assign N290 = N289 & inst[4];
assign N289 = N288 & inst[6];
assign N288 = N287 & inst[12];
assign N287 = inst[18] & inst[13];
assign N295 = N294 & inst[4];
assign N294 = N293 & inst[6];
assign N293 = N292 & inst[12];
assign N292 = inst[19] & inst[13];
assign out_csr_set_ = N310 | N313;
assign N310 = N306 | N309;
assign N306 = N302 | N305;
assign N302 = N298 | N301;
assign N298 = N297 & inst[4];
assign N297 = N296 & inst[6];
assign N296 = inst[15] & N2;
assign N301 = N300 & inst[4];
assign N300 = N299 & inst[6];
assign N299 = inst[16] & N2;
assign N305 = N304 & inst[4];
assign N304 = N303 & inst[6];
assign N303 = inst[17] & N2;
assign N309 = N308 & inst[4];
assign N308 = N307 & inst[6];
assign N307 = inst[18] & N2;
assign N313 = N312 & inst[4];
assign N312 = N311 & inst[6];
assign N311 = inst[19] & N2;
assign out_csr_write_ = N315 & inst[4];
assign N315 = N314 & inst[6];
assign N314 = N0 & inst[12];
assign out_csr_imm_ = N334 | N337;
assign N334 = N330 | N333;
assign N330 = N326 | N329;
assign N326 = N322 | N325;
assign N322 = N318 | N321;
assign N318 = N317 & inst[4];
assign N317 = N316 & inst[6];
assign N316 = inst[14] & N0;
assign N321 = N320 & inst[4];
assign N320 = N319 & inst[6];
assign N319 = inst[15] & inst[14];
assign N325 = N324 & inst[4];
assign N324 = N323 & inst[6];
assign N323 = inst[16] & inst[14];
assign N329 = N328 & inst[4];
assign N328 = N327 & inst[6];
assign N327 = inst[17] & inst[14];
assign N333 = N332 & inst[4];
assign N332 = N331 & inst[6];
assign N331 = inst[18] & inst[14];
assign N337 = N336 & inst[4];
assign N336 = N335 & inst[6];
assign N335 = inst[19] & inst[14];
assign out_presync_ = N379 | N382;
assign N379 = N375 | N378;
assign N375 = N371 | N374;
assign N371 = N367 | N370;
assign N367 = N363 | N366;
assign N363 = N359 | N362;
assign N359 = N355 | N358;
assign N355 = N351 | N354;
assign N351 = N347 | N350;
assign N347 = N343 | N346;
assign N343 = N338 | N342;
assign N338 = N33 & inst[3];
assign N342 = N341 & N1;
assign N341 = N340 & inst[5];
assign N340 = N339 & N72;
assign N339 = inst[25] & inst[14];
assign N346 = N345 & inst[4];
assign N345 = N344 & inst[6];
assign N344 = N0 & inst[7];
assign N350 = N349 & inst[4];
assign N349 = N348 & inst[6];
assign N348 = N0 & inst[8];
assign N354 = N353 & inst[4];
assign N353 = N352 & inst[6];
assign N352 = N0 & inst[9];
assign N358 = N357 & inst[4];
assign N357 = N356 & inst[6];
assign N356 = N0 & inst[10];
assign N362 = N361 & inst[4];
assign N361 = N360 & inst[6];
assign N360 = N0 & inst[11];
assign N366 = N365 & inst[4];
assign N365 = N364 & inst[6];
assign N364 = inst[15] & inst[13];
assign N370 = N369 & inst[4];
assign N369 = N368 & inst[6];
assign N368 = inst[16] & inst[13];
assign N374 = N373 & inst[4];
assign N373 = N372 & inst[6];
assign N372 = inst[17] & inst[13];
assign N378 = N377 & inst[4];
assign N377 = N376 & inst[6];
assign N376 = inst[18] & inst[13];
assign N382 = N381 & inst[4];
assign N381 = N380 & inst[6];
assign N380 = inst[19] & inst[13];
assign out_postsync_ = N431 | N434;
assign N431 = N427 | N430;
assign N427 = N423 | N426;
assign N423 = N419 | N422;
assign N419 = N415 | N418;
assign N415 = N411 | N414;
assign N411 = N407 | N410;
assign N407 = N403 | N406;
assign N403 = N399 | N402;
assign N399 = N395 | N398;
assign N395 = N390 | N394;
assign N390 = N384 | N389;
assign N384 = N383 & inst[3];
assign N383 = inst[12] & N33;
assign N389 = N388 & inst[4];
assign N388 = N387 & inst[6];
assign N387 = N386 & N2;
assign N386 = N385 & N0;
assign N385 = ~inst[22];
assign N394 = N393 & N1;
assign N393 = N392 & inst[5];
assign N392 = N391 & N72;
assign N391 = inst[25] & inst[14];
assign N398 = N397 & inst[4];
assign N397 = N396 & inst[6];
assign N396 = N0 & inst[7];
assign N402 = N401 & inst[4];
assign N401 = N400 & inst[6];
assign N400 = N0 & inst[8];
assign N406 = N405 & inst[4];
assign N405 = N404 & inst[6];
assign N404 = N0 & inst[9];
assign N410 = N409 & inst[4];
assign N409 = N408 & inst[6];
assign N408 = N0 & inst[10];
assign N414 = N413 & inst[4];
assign N413 = N412 & inst[6];
assign N412 = N0 & inst[11];
assign N418 = N417 & inst[4];
assign N417 = N416 & inst[6];
assign N416 = inst[15] & inst[13];
assign N422 = N421 & inst[4];
assign N421 = N420 & inst[6];
assign N420 = inst[16] & inst[13];
assign N426 = N425 & inst[4];
assign N425 = N424 & inst[6];
assign N424 = inst[17] & inst[13];
assign N430 = N429 & inst[4];
assign N429 = N428 & inst[6];
assign N428 = inst[18] & inst[13];
assign N434 = N433 & inst[4];
assign N433 = N432 & inst[6];
assign N432 = inst[19] & inst[13];
assign out_ebreak_ = N438 & inst[4];
assign N438 = N437 & inst[6];
assign N437 = N436 & N2;
assign N436 = N435 & N0;
assign N435 = N385 & inst[20];
assign out_ecall_ = N444 & inst[4];
assign N444 = N443 & inst[6];
assign N443 = N442 & N2;
assign N442 = N441 & N0;
assign N441 = N439 & N440;
assign N439 = ~inst[21];
assign N440 = ~inst[20];
assign out_mret_ = N447 & inst[4];
assign N447 = N446 & inst[6];
assign N446 = N445 & N2;
assign N445 = inst[29] & N0;
assign out_mul_ = N451 & N1;
assign N451 = N450 & inst[4];
assign N450 = N449 & inst[5];
assign N449 = N448 & N72;
assign N448 = inst[25] & N35;
assign N3 = inst[25] & N35;
assign out_rs1_sign_ = N457 | N462;
assign N457 = N456 & N1;
assign N456 = N455 & inst[4];
assign N455 = N454 & inst[5];
assign N454 = N453 & N72;
assign N453 = N452 & N2;
assign N452 = N3 & inst[13];
assign N462 = N461 & N1;
assign N461 = N460 & inst[4];
assign N460 = N459 & N72;
assign N459 = N458 & inst[12];
assign N458 = N3 & N0;
assign out_rs2_sign_ = N467 & N1;
assign N467 = N466 & inst[4];
assign N466 = N465 & N72;
assign N465 = N464 & inst[12];
assign N464 = N463 & N0;
assign N463 = inst[25] & N35;
assign out_low_ = N472 & N1;
assign N472 = N471 & inst[4];
assign N471 = N470 & inst[5];
assign N470 = N469 & N2;
assign N469 = N468 & N0;
assign N468 = inst[25] & N35;
assign out_div_ = N475 & N1;
assign N475 = N474 & inst[5];
assign N474 = N473 & N72;
assign N473 = inst[25] & inst[14];
assign out_rem_ = N479 & N1;
assign N479 = N478 & inst[5];
assign N478 = N477 & N72;
assign N477 = N476 & inst[13];
assign N476 = inst[25] & inst[14];
assign out_fence_ = N33 & inst[3];
assign out_fence_i_ = N480 & inst[3];
assign N480 = inst[12] & N33;
assign out_pm_alu_ = N489 | N490;
assign N489 = N486 | N488;
assign N486 = N484 | N485;
assign N484 = N483 & inst[4];
assign N483 = N482 & N2;
assign N482 = N481 & N0;
assign N481 = inst[28] & inst[22];
assign N485 = inst[4] & inst[2];
assign N488 = N487 & inst[4];
assign N487 = N30 & N72;
assign N490 = N33 & inst[4];
assign N4 = ~inst[31];
assign N5 = N4 & N112;
assign N6 = ~inst[27];
assign N7 = ~inst[26];
assign N8 = ~inst[24];
assign N9 = ~inst[23];
assign N10 = ~inst[19];
assign N11 = ~inst[18];
assign N12 = ~inst[17];
assign N13 = ~inst[16];
assign N14 = ~inst[15];
assign N15 = ~inst[11];
assign N16 = ~inst[10];
assign N17 = ~inst[9];
assign N18 = ~inst[8];
assign N19 = ~inst[7];
assign N20 = ~inst[29];
assign N21 = N5 & N20;
assign N22 = ~inst[28];
assign N23 = N21 & N22;
assign N24 = N491 & N7;
assign N491 = N23 & N6;
assign N25 = N24 & N30;
assign N26 = N494 & N439;
assign N494 = N493 & N385;
assign N493 = N492 & N9;
assign N492 = N25 & N8;
assign N27 = N498 & N30;
assign N498 = N497 & N7;
assign N497 = N496 & N6;
assign N496 = N495 & N22;
assign N495 = N4 & N20;
assign N28 = N35 & N0;
assign out_legal_ = N721 | N726;
assign N721 = N713 | N720;
assign N713 = N706 | N712;
assign N706 = N699 | N705;
assign N699 = N691 | N698;
assign N691 = N683 | N690;
assign N683 = N662 | N682;
assign N662 = N641 | N661;
assign N641 = N633 | N640;
assign N633 = N626 | N632;
assign N626 = N619 | N625;
assign N619 = N611 | N618;
assign N611 = N603 | N610;
assign N603 = N596 | N602;
assign N596 = N587 | N595;
assign N587 = N578 | N586;
assign N578 = N572 | N577;
assign N572 = N554 | N571;
assign N554 = N526 | N553;
assign N526 = N525 & inst[0];
assign N525 = N524 & inst[1];
assign N524 = N523 & N1;
assign N523 = N522 & N69;
assign N522 = N521 & inst[4];
assign N521 = N520 & inst[5];
assign N520 = N519 & inst[6];
assign N519 = N518 & N19;
assign N518 = N517 & N18;
assign N517 = N516 & N17;
assign N516 = N515 & N16;
assign N515 = N514 & N15;
assign N514 = N513 & N35;
assign N513 = N512 & N14;
assign N512 = N511 & N13;
assign N511 = N510 & N12;
assign N510 = N509 & N11;
assign N509 = N508 & N10;
assign N508 = N507 & N440;
assign N507 = N506 & inst[21];
assign N506 = N505 & N385;
assign N505 = N504 & N9;
assign N504 = N503 & N8;
assign N503 = N502 & N30;
assign N502 = N501 & N7;
assign N501 = N500 & N6;
assign N500 = N499 & inst[28];
assign N499 = N5 & inst[29];
assign N553 = N552 & inst[0];
assign N552 = N551 & inst[1];
assign N551 = N550 & N1;
assign N550 = N549 & N69;
assign N549 = N548 & inst[4];
assign N548 = N547 & inst[5];
assign N547 = N546 & inst[6];
assign N546 = N545 & N19;
assign N545 = N544 & N18;
assign N544 = N543 & N17;
assign N543 = N542 & N16;
assign N542 = N541 & N15;
assign N541 = N540 & N35;
assign N540 = N539 & N14;
assign N539 = N538 & N13;
assign N538 = N537 & N12;
assign N537 = N536 & N11;
assign N536 = N535 & N10;
assign N535 = N534 & inst[20];
assign N534 = N533 & N439;
assign N533 = N532 & inst[22];
assign N532 = N531 & N9;
assign N531 = N530 & N8;
assign N530 = N529 & N30;
assign N529 = N528 & N7;
assign N528 = N527 & N6;
assign N527 = N21 & inst[28];
assign N571 = N570 & inst[0];
assign N570 = N569 & inst[1];
assign N569 = N568 & N1;
assign N568 = N567 & N69;
assign N567 = N566 & inst[4];
assign N566 = N565 & inst[5];
assign N565 = N564 & N19;
assign N564 = N563 & N18;
assign N563 = N562 & N17;
assign N562 = N561 & N16;
assign N561 = N560 & N15;
assign N560 = N559 & N35;
assign N559 = N558 & N14;
assign N558 = N557 & N13;
assign N557 = N556 & N12;
assign N556 = N555 & N11;
assign N555 = N26 & N10;
assign N577 = N576 & inst[0];
assign N576 = N575 & inst[1];
assign N575 = N574 & N69;
assign N574 = N573 & inst[4];
assign N573 = N25 & N72;
assign N586 = N585 & inst[0];
assign N585 = N584 & inst[1];
assign N584 = N583 & N1;
assign N583 = N582 & N69;
assign N582 = N581 & N72;
assign N581 = N580 & N2;
assign N580 = N579 & N0;
assign N579 = N27 & N35;
assign N595 = N594 & inst[0];
assign N594 = N593 & inst[1];
assign N593 = N592 & N69;
assign N592 = N591 & inst[4];
assign N591 = N590 & N72;
assign N590 = N589 & inst[12];
assign N589 = N588 & N0;
assign N588 = N27 & inst[14];
assign N602 = N601 & inst[0];
assign N601 = N600 & inst[1];
assign N600 = N599 & N69;
assign N599 = N598 & inst[4];
assign N598 = N597 & inst[5];
assign N597 = N24 & N72;
assign N610 = N609 & inst[0];
assign N609 = N608 & inst[1];
assign N608 = N607 & N69;
assign N607 = N606 & N68;
assign N606 = N605 & inst[5];
assign N605 = N604 & inst[6];
assign N604 = N28 & N2;
assign N618 = N617 & inst[0];
assign N617 = N616 & inst[1];
assign N616 = N615 & N1;
assign N615 = N614 & N69;
assign N614 = N613 & N68;
assign N613 = N612 & inst[5];
assign N612 = inst[14] & inst[6];
assign N625 = N624 & inst[0];
assign N624 = N623 & inst[1];
assign N623 = N622 & N69;
assign N622 = N621 & inst[4];
assign N621 = N620 & N33;
assign N620 = N2 & N72;
assign N632 = N631 & inst[0];
assign N631 = N630 & inst[1];
assign N630 = N629 & N1;
assign N629 = N628 & N69;
assign N628 = N627 & N68;
assign N627 = N28 & inst[5];
assign N640 = N639 & inst[0];
assign N639 = N638 & inst[1];
assign N638 = N637 & N1;
assign N637 = N636 & N69;
assign N636 = N635 & inst[4];
assign N635 = N634 & inst[5];
assign N634 = inst[12] & inst[6];
assign N661 = N660 & inst[0];
assign N660 = N659 & inst[1];
assign N659 = N658 & inst[2];
assign N658 = N657 & inst[3];
assign N657 = N656 & N68;
assign N656 = N655 & N33;
assign N655 = N654 & N72;
assign N654 = N653 & N19;
assign N653 = N652 & N18;
assign N652 = N651 & N17;
assign N651 = N650 & N16;
assign N650 = N649 & N15;
assign N649 = N648 & N0;
assign N648 = N647 & N35;
assign N647 = N646 & N14;
assign N646 = N645 & N13;
assign N645 = N644 & N12;
assign N644 = N643 & N11;
assign N643 = N642 & N10;
assign N642 = N26 & N440;
assign N682 = N681 & inst[0];
assign N681 = N680 & inst[1];
assign N680 = N679 & inst[2];
assign N679 = N678 & inst[3];
assign N678 = N677 & N68;
assign N677 = N676 & N33;
assign N676 = N675 & N72;
assign N675 = N674 & N19;
assign N674 = N673 & N18;
assign N673 = N672 & N17;
assign N672 = N671 & N16;
assign N671 = N670 & N15;
assign N670 = N669 & N2;
assign N669 = N668 & N0;
assign N668 = N667 & N35;
assign N667 = N666 & N14;
assign N666 = N665 & N13;
assign N665 = N664 & N12;
assign N664 = N663 & N11;
assign N663 = N23 & N10;
assign N690 = N689 & inst[0];
assign N689 = N688 & inst[1];
assign N688 = N687 & N1;
assign N687 = N686 & N69;
assign N686 = N685 & inst[4];
assign N685 = N684 & inst[5];
assign N684 = inst[13] & inst[6];
assign N698 = N697 & inst[0];
assign N697 = N696 & inst[1];
assign N696 = N695 & N1;
assign N695 = N694 & N69;
assign N694 = N693 & N68;
assign N693 = N692 & N33;
assign N692 = N0 & N72;
assign N705 = N704 & inst[0];
assign N704 = N703 & inst[1];
assign N703 = N702 & inst[2];
assign N702 = N701 & inst[3];
assign N701 = N700 & N68;
assign N700 = inst[6] & inst[5];
assign N712 = N711 & inst[0];
assign N711 = N710 & inst[1];
assign N710 = N709 & N69;
assign N709 = N708 & inst[4];
assign N708 = N707 & N33;
assign N707 = inst[13] & N72;
assign N720 = N719 & inst[0];
assign N719 = N718 & inst[1];
assign N718 = N717 & N1;
assign N717 = N716 & N69;
assign N716 = N715 & N68;
assign N715 = N714 & N72;
assign N714 = N35 & N2;
assign N726 = N725 & inst[0];
assign N725 = N724 & inst[1];
assign N724 = N723 & inst[2];
assign N723 = N722 & N69;
assign N722 = N72 & inst[4];
endmodule |
module rvecc_encode
(
din,
ecc_out
);
input [31:0] din;
output [6:0] ecc_out;
wire [6:0] ecc_out;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113;
assign ecc_out[0] = N15 ^ din[30];
assign N15 = N14 ^ din[28];
assign N14 = N13 ^ din[26];
assign N13 = N12 ^ din[25];
assign N12 = N11 ^ din[23];
assign N11 = N10 ^ din[21];
assign N10 = N9 ^ din[19];
assign N9 = N8 ^ din[17];
assign N8 = N7 ^ din[15];
assign N7 = N6 ^ din[13];
assign N6 = N5 ^ din[11];
assign N5 = N4 ^ din[10];
assign N4 = N3 ^ din[8];
assign N3 = N2 ^ din[6];
assign N2 = N1 ^ din[4];
assign N1 = N0 ^ din[3];
assign N0 = din[0] ^ din[1];
assign ecc_out[1] = N31 ^ din[31];
assign N31 = N30 ^ din[28];
assign N30 = N29 ^ din[27];
assign N29 = N28 ^ din[25];
assign N28 = N27 ^ din[24];
assign N27 = N26 ^ din[21];
assign N26 = N25 ^ din[20];
assign N25 = N24 ^ din[17];
assign N24 = N23 ^ din[16];
assign N23 = N22 ^ din[13];
assign N22 = N21 ^ din[12];
assign N21 = N20 ^ din[10];
assign N20 = N19 ^ din[9];
assign N19 = N18 ^ din[6];
assign N18 = N17 ^ din[5];
assign N17 = N16 ^ din[3];
assign N16 = din[0] ^ din[2];
assign ecc_out[2] = N47 ^ din[31];
assign N47 = N46 ^ din[30];
assign N46 = N45 ^ din[29];
assign N45 = N44 ^ din[25];
assign N44 = N43 ^ din[24];
assign N43 = N42 ^ din[23];
assign N42 = N41 ^ din[22];
assign N41 = N40 ^ din[17];
assign N40 = N39 ^ din[16];
assign N39 = N38 ^ din[15];
assign N38 = N37 ^ din[14];
assign N37 = N36 ^ din[10];
assign N36 = N35 ^ din[9];
assign N35 = N34 ^ din[8];
assign N34 = N33 ^ din[7];
assign N33 = N32 ^ din[3];
assign N32 = din[1] ^ din[2];
assign ecc_out[3] = N60 ^ din[25];
assign N60 = N59 ^ din[24];
assign N59 = N58 ^ din[23];
assign N58 = N57 ^ din[22];
assign N57 = N56 ^ din[21];
assign N56 = N55 ^ din[20];
assign N55 = N54 ^ din[19];
assign N54 = N53 ^ din[18];
assign N53 = N52 ^ din[10];
assign N52 = N51 ^ din[9];
assign N51 = N50 ^ din[8];
assign N50 = N49 ^ din[7];
assign N49 = N48 ^ din[6];
assign N48 = din[4] ^ din[5];
assign ecc_out[4] = N73 ^ din[25];
assign N73 = N72 ^ din[24];
assign N72 = N71 ^ din[23];
assign N71 = N70 ^ din[22];
assign N70 = N69 ^ din[21];
assign N69 = N68 ^ din[20];
assign N68 = N67 ^ din[19];
assign N67 = N66 ^ din[18];
assign N66 = N65 ^ din[17];
assign N65 = N64 ^ din[16];
assign N64 = N63 ^ din[15];
assign N63 = N62 ^ din[14];
assign N62 = N61 ^ din[13];
assign N61 = din[11] ^ din[12];
assign ecc_out[5] = N77 ^ din[31];
assign N77 = N76 ^ din[30];
assign N76 = N75 ^ din[29];
assign N75 = N74 ^ din[28];
assign N74 = din[26] ^ din[27];
assign ecc_out[6] = N108 ^ N113;
assign N108 = N107 ^ din[0];
assign N107 = N106 ^ din[1];
assign N106 = N105 ^ din[2];
assign N105 = N104 ^ din[3];
assign N104 = N103 ^ din[4];
assign N103 = N102 ^ din[5];
assign N102 = N101 ^ din[6];
assign N101 = N100 ^ din[7];
assign N100 = N99 ^ din[8];
assign N99 = N98 ^ din[9];
assign N98 = N97 ^ din[10];
assign N97 = N96 ^ din[11];
assign N96 = N95 ^ din[12];
assign N95 = N94 ^ din[13];
assign N94 = N93 ^ din[14];
assign N93 = N92 ^ din[15];
assign N92 = N91 ^ din[16];
assign N91 = N90 ^ din[17];
assign N90 = N89 ^ din[18];
assign N89 = N88 ^ din[19];
assign N88 = N87 ^ din[20];
assign N87 = N86 ^ din[21];
assign N86 = N85 ^ din[22];
assign N85 = N84 ^ din[23];
assign N84 = N83 ^ din[24];
assign N83 = N82 ^ din[25];
assign N82 = N81 ^ din[26];
assign N81 = N80 ^ din[27];
assign N80 = N79 ^ din[28];
assign N79 = N78 ^ din[29];
assign N78 = din[31] ^ din[30];
assign N113 = N112 ^ ecc_out[0];
assign N112 = N111 ^ ecc_out[1];
assign N111 = N110 ^ ecc_out[2];
assign N110 = N109 ^ ecc_out[3];
assign N109 = ecc_out[5] ^ ecc_out[4];
endmodule |
module rvdff_WIDTH22
(
din,
clk,
rst_l,
dout
);
input [21:0] din;
output [21:0] dout;
input clk;
input rst_l;
wire N0;
reg [21:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH9
(
din,
clk,
rst_l,
dout
);
input [8:0] din;
output [8:0] dout;
input clk;
input rst_l;
wire N0;
reg [8:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rveven_paritygen_WIDTH16
(
data_in,
parity_out
);
input [15:0] data_in;
output parity_out;
wire parity_out,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
assign parity_out = N13 ^ data_in[0];
assign N13 = N12 ^ data_in[1];
assign N12 = N11 ^ data_in[2];
assign N11 = N10 ^ data_in[3];
assign N10 = N9 ^ data_in[4];
assign N9 = N8 ^ data_in[5];
assign N8 = N7 ^ data_in[6];
assign N7 = N6 ^ data_in[7];
assign N6 = N5 ^ data_in[8];
assign N5 = N4 ^ data_in[9];
assign N4 = N3 ^ data_in[10];
assign N3 = N2 ^ data_in[11];
assign N2 = N1 ^ data_in[12];
assign N1 = N0 ^ data_in[13];
assign N0 = data_in[15] ^ data_in[14];
endmodule |
module dmi_jtag_to_core_sync
(
rd_en,
wr_en,
rst_n,
clk,
reg_en,
reg_wr_en
);
input rd_en;
input wr_en;
input rst_n;
input clk;
output reg_en;
output reg_wr_en;
wire reg_en,reg_wr_en,c_rd_en,N0,N1,N2;
reg [2:0] wren,rden;
always @(posedge clk or posedge N0) begin
if(N0) begin
wren[2] <= 1'b0;
end else if(1'b1) begin
wren[2] <= wren[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
wren[1] <= 1'b0;
end else if(1'b1) begin
wren[1] <= wren[0];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
wren[0] <= 1'b0;
end else if(1'b1) begin
wren[0] <= wr_en;
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
rden[2] <= 1'b0;
end else if(1'b1) begin
rden[2] <= rden[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
rden[1] <= 1'b0;
end else if(1'b1) begin
rden[1] <= rden[0];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
rden[0] <= 1'b0;
end else if(1'b1) begin
rden[0] <= rd_en;
end
end
assign reg_en = reg_wr_en | c_rd_en;
assign N0 = ~rst_n;
assign c_rd_en = rden[1] & N1;
assign N1 = ~rden[2];
assign reg_wr_en = wren[1] & N2;
assign N2 = ~wren[2];
endmodule |
module rvmaskandmatch
(
mask,
data,
masken,
match
);
input [31:0] mask;
input [31:0] data;
input masken;
output match;
wire match,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,masken_or_fullmask,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,
N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,
N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,
N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,
N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,
N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,
N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,
N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,
N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,
N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,
N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,
N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,
N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,
N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,
N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,
N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,
N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,
N353,N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,
N369,N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,
N385,N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,
N401,N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,
N417,N418,N419,N420,N421,N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,
N433,N434,N435,N436,N437,N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,
N449,N450,N451,N452,N453,N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,
N465,N466,N467,N468,N469,N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,
N481,N482,N483,N484,N485,N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,
N497,N498,N499,N500,N501,N502,N503,N504,N505,N506,N507,N508,N509,N510,N511,N512,
N513,N514,N515,N516,N517,N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,
N529,N530,N531,N532,N533,N534,N535,N536,N537,N538,N539,N540,N541,N542,N543,N544,
N545,N546,N547,N548,N549,N550,N551,N552,N553,N554,N555,N556,N557,N558,N559,N560,
N561,N562,N563,N564,N565,N566,N567,N568,N569,N570,N571,N572,N573,N574,N575,N576,
N577,N578,N579,N580,N581,N582,N583,N584,N585,N586,N587,N588,N589,N590,N591,N592,
N593,N594,N595,N596,N597,N598,N599,N600,N601,N602,N603,N604,N605,N606,N607,N608,
N609,N610,N611,N612,N613,N614,N615,N616,N617,N618,N619,N620,N621,N622,N623,N624,
N625,N626,N627,N628,N629,N630,N631,N632,N633,N634,N635,N636,N637,N638,N639,N640,
N641,N642,N643,N644,N645,N646,N647,N648,N649,N650,N651,N652,N653,N654,N655,N656,
N657,N658,N659,N660,N661,N662,N663,N664,N665,N666,N667,N668,N669,N670,N671,N672,
N673,N674,N675,N676,N677,N678,N679,N680,N681,N682,N683;
wire [31:0] matchvec;
assign N0 = mask[0] ^ data[0];
assign N63 = ~N0;
assign N1 = mask[1] ^ data[1];
assign N66 = ~N1;
assign N2 = mask[2] ^ data[2];
assign N69 = ~N2;
assign N3 = mask[3] ^ data[3];
assign N72 = ~N3;
assign N4 = mask[4] ^ data[4];
assign N75 = ~N4;
assign N5 = mask[5] ^ data[5];
assign N78 = ~N5;
assign N6 = mask[6] ^ data[6];
assign N81 = ~N6;
assign N7 = mask[7] ^ data[7];
assign N84 = ~N7;
assign N8 = mask[8] ^ data[8];
assign N87 = ~N8;
assign N9 = mask[9] ^ data[9];
assign N90 = ~N9;
assign N10 = mask[10] ^ data[10];
assign N93 = ~N10;
assign N11 = mask[11] ^ data[11];
assign N96 = ~N11;
assign N12 = mask[12] ^ data[12];
assign N99 = ~N12;
assign N13 = mask[13] ^ data[13];
assign N102 = ~N13;
assign N14 = mask[14] ^ data[14];
assign N105 = ~N14;
assign N15 = mask[15] ^ data[15];
assign N108 = ~N15;
assign N16 = mask[16] ^ data[16];
assign N111 = ~N16;
assign N17 = mask[17] ^ data[17];
assign N114 = ~N17;
assign N18 = mask[18] ^ data[18];
assign N117 = ~N18;
assign N19 = mask[19] ^ data[19];
assign N120 = ~N19;
assign N20 = mask[20] ^ data[20];
assign N123 = ~N20;
assign N21 = mask[21] ^ data[21];
assign N126 = ~N21;
assign N22 = mask[22] ^ data[22];
assign N129 = ~N22;
assign N23 = mask[23] ^ data[23];
assign N132 = ~N23;
assign N24 = mask[24] ^ data[24];
assign N135 = ~N24;
assign N25 = mask[25] ^ data[25];
assign N138 = ~N25;
assign N26 = mask[26] ^ data[26];
assign N141 = ~N26;
assign N27 = mask[27] ^ data[27];
assign N144 = ~N27;
assign N28 = mask[28] ^ data[28];
assign N147 = ~N28;
assign N29 = mask[29] ^ data[29];
assign N150 = ~N29;
assign N30 = mask[30] ^ data[30];
assign N153 = ~N30;
assign N31 = mask[31] ^ data[31];
assign N156 = ~N31;
assign matchvec[1] = (N32)? 1'b1 :
(N65)? N66 : 1'b0;
assign N32 = N64;
assign matchvec[2] = (N33)? 1'b1 :
(N68)? N69 : 1'b0;
assign N33 = N67;
assign matchvec[3] = (N34)? 1'b1 :
(N71)? N72 : 1'b0;
assign N34 = N70;
assign matchvec[4] = (N35)? 1'b1 :
(N74)? N75 : 1'b0;
assign N35 = N73;
assign matchvec[5] = (N36)? 1'b1 :
(N77)? N78 : 1'b0;
assign N36 = N76;
assign matchvec[6] = (N37)? 1'b1 :
(N80)? N81 : 1'b0;
assign N37 = N79;
assign matchvec[7] = (N38)? 1'b1 :
(N83)? N84 : 1'b0;
assign N38 = N82;
assign matchvec[8] = (N39)? 1'b1 :
(N86)? N87 : 1'b0;
assign N39 = N85;
assign matchvec[9] = (N40)? 1'b1 :
(N89)? N90 : 1'b0;
assign N40 = N88;
assign matchvec[10] = (N41)? 1'b1 :
(N92)? N93 : 1'b0;
assign N41 = N91;
assign matchvec[11] = (N42)? 1'b1 :
(N95)? N96 : 1'b0;
assign N42 = N94;
assign matchvec[12] = (N43)? 1'b1 :
(N98)? N99 : 1'b0;
assign N43 = N97;
assign matchvec[13] = (N44)? 1'b1 :
(N101)? N102 : 1'b0;
assign N44 = N100;
assign matchvec[14] = (N45)? 1'b1 :
(N104)? N105 : 1'b0;
assign N45 = N103;
assign matchvec[15] = (N46)? 1'b1 :
(N107)? N108 : 1'b0;
assign N46 = N106;
assign matchvec[16] = (N47)? 1'b1 :
(N110)? N111 : 1'b0;
assign N47 = N109;
assign matchvec[17] = (N48)? 1'b1 :
(N113)? N114 : 1'b0;
assign N48 = N112;
assign matchvec[18] = (N49)? 1'b1 :
(N116)? N117 : 1'b0;
assign N49 = N115;
assign matchvec[19] = (N50)? 1'b1 :
(N119)? N120 : 1'b0;
assign N50 = N118;
assign matchvec[20] = (N51)? 1'b1 :
(N122)? N123 : 1'b0;
assign N51 = N121;
assign matchvec[21] = (N52)? 1'b1 :
(N125)? N126 : 1'b0;
assign N52 = N124;
assign matchvec[22] = (N53)? 1'b1 :
(N128)? N129 : 1'b0;
assign N53 = N127;
assign matchvec[23] = (N54)? 1'b1 :
(N131)? N132 : 1'b0;
assign N54 = N130;
assign matchvec[24] = (N55)? 1'b1 :
(N134)? N135 : 1'b0;
assign N55 = N133;
assign matchvec[25] = (N56)? 1'b1 :
(N137)? N138 : 1'b0;
assign N56 = N136;
assign matchvec[26] = (N57)? 1'b1 :
(N140)? N141 : 1'b0;
assign N57 = N139;
assign matchvec[27] = (N58)? 1'b1 :
(N143)? N144 : 1'b0;
assign N58 = N142;
assign matchvec[28] = (N59)? 1'b1 :
(N146)? N147 : 1'b0;
assign N59 = N145;
assign matchvec[29] = (N60)? 1'b1 :
(N149)? N150 : 1'b0;
assign N60 = N148;
assign matchvec[30] = (N61)? 1'b1 :
(N152)? N153 : 1'b0;
assign N61 = N151;
assign matchvec[31] = (N62)? 1'b1 :
(N155)? N156 : 1'b0;
assign N62 = N154;
assign masken_or_fullmask = masken & N188;
assign N188 = ~N187;
assign N187 = N186 & mask[0];
assign N186 = N185 & mask[1];
assign N185 = N184 & mask[2];
assign N184 = N183 & mask[3];
assign N183 = N182 & mask[4];
assign N182 = N181 & mask[5];
assign N181 = N180 & mask[6];
assign N180 = N179 & mask[7];
assign N179 = N178 & mask[8];
assign N178 = N177 & mask[9];
assign N177 = N176 & mask[10];
assign N176 = N175 & mask[11];
assign N175 = N174 & mask[12];
assign N174 = N173 & mask[13];
assign N173 = N172 & mask[14];
assign N172 = N171 & mask[15];
assign N171 = N170 & mask[16];
assign N170 = N169 & mask[17];
assign N169 = N168 & mask[18];
assign N168 = N167 & mask[19];
assign N167 = N166 & mask[20];
assign N166 = N165 & mask[21];
assign N165 = N164 & mask[22];
assign N164 = N163 & mask[23];
assign N163 = N162 & mask[24];
assign N162 = N161 & mask[25];
assign N161 = N160 & mask[26];
assign N160 = N159 & mask[27];
assign N159 = N158 & mask[28];
assign N158 = N157 & mask[29];
assign N157 = mask[31] & mask[30];
assign matchvec[0] = masken_or_fullmask | N63;
assign N64 = mask[0] & masken_or_fullmask;
assign N65 = ~N64;
assign N67 = N189 & masken_or_fullmask;
assign N189 = mask[1] & mask[0];
assign N68 = ~N67;
assign N70 = N191 & masken_or_fullmask;
assign N191 = N190 & mask[0];
assign N190 = mask[2] & mask[1];
assign N71 = ~N70;
assign N73 = N194 & masken_or_fullmask;
assign N194 = N193 & mask[0];
assign N193 = N192 & mask[1];
assign N192 = mask[3] & mask[2];
assign N74 = ~N73;
assign N76 = N198 & masken_or_fullmask;
assign N198 = N197 & mask[0];
assign N197 = N196 & mask[1];
assign N196 = N195 & mask[2];
assign N195 = mask[4] & mask[3];
assign N77 = ~N76;
assign N79 = N203 & masken_or_fullmask;
assign N203 = N202 & mask[0];
assign N202 = N201 & mask[1];
assign N201 = N200 & mask[2];
assign N200 = N199 & mask[3];
assign N199 = mask[5] & mask[4];
assign N80 = ~N79;
assign N82 = N209 & masken_or_fullmask;
assign N209 = N208 & mask[0];
assign N208 = N207 & mask[1];
assign N207 = N206 & mask[2];
assign N206 = N205 & mask[3];
assign N205 = N204 & mask[4];
assign N204 = mask[6] & mask[5];
assign N83 = ~N82;
assign N85 = N216 & masken_or_fullmask;
assign N216 = N215 & mask[0];
assign N215 = N214 & mask[1];
assign N214 = N213 & mask[2];
assign N213 = N212 & mask[3];
assign N212 = N211 & mask[4];
assign N211 = N210 & mask[5];
assign N210 = mask[7] & mask[6];
assign N86 = ~N85;
assign N88 = N224 & masken_or_fullmask;
assign N224 = N223 & mask[0];
assign N223 = N222 & mask[1];
assign N222 = N221 & mask[2];
assign N221 = N220 & mask[3];
assign N220 = N219 & mask[4];
assign N219 = N218 & mask[5];
assign N218 = N217 & mask[6];
assign N217 = mask[8] & mask[7];
assign N89 = ~N88;
assign N91 = N233 & masken_or_fullmask;
assign N233 = N232 & mask[0];
assign N232 = N231 & mask[1];
assign N231 = N230 & mask[2];
assign N230 = N229 & mask[3];
assign N229 = N228 & mask[4];
assign N228 = N227 & mask[5];
assign N227 = N226 & mask[6];
assign N226 = N225 & mask[7];
assign N225 = mask[9] & mask[8];
assign N92 = ~N91;
assign N94 = N243 & masken_or_fullmask;
assign N243 = N242 & mask[0];
assign N242 = N241 & mask[1];
assign N241 = N240 & mask[2];
assign N240 = N239 & mask[3];
assign N239 = N238 & mask[4];
assign N238 = N237 & mask[5];
assign N237 = N236 & mask[6];
assign N236 = N235 & mask[7];
assign N235 = N234 & mask[8];
assign N234 = mask[10] & mask[9];
assign N95 = ~N94;
assign N97 = N254 & masken_or_fullmask;
assign N254 = N253 & mask[0];
assign N253 = N252 & mask[1];
assign N252 = N251 & mask[2];
assign N251 = N250 & mask[3];
assign N250 = N249 & mask[4];
assign N249 = N248 & mask[5];
assign N248 = N247 & mask[6];
assign N247 = N246 & mask[7];
assign N246 = N245 & mask[8];
assign N245 = N244 & mask[9];
assign N244 = mask[11] & mask[10];
assign N98 = ~N97;
assign N100 = N266 & masken_or_fullmask;
assign N266 = N265 & mask[0];
assign N265 = N264 & mask[1];
assign N264 = N263 & mask[2];
assign N263 = N262 & mask[3];
assign N262 = N261 & mask[4];
assign N261 = N260 & mask[5];
assign N260 = N259 & mask[6];
assign N259 = N258 & mask[7];
assign N258 = N257 & mask[8];
assign N257 = N256 & mask[9];
assign N256 = N255 & mask[10];
assign N255 = mask[12] & mask[11];
assign N101 = ~N100;
assign N103 = N279 & masken_or_fullmask;
assign N279 = N278 & mask[0];
assign N278 = N277 & mask[1];
assign N277 = N276 & mask[2];
assign N276 = N275 & mask[3];
assign N275 = N274 & mask[4];
assign N274 = N273 & mask[5];
assign N273 = N272 & mask[6];
assign N272 = N271 & mask[7];
assign N271 = N270 & mask[8];
assign N270 = N269 & mask[9];
assign N269 = N268 & mask[10];
assign N268 = N267 & mask[11];
assign N267 = mask[13] & mask[12];
assign N104 = ~N103;
assign N106 = N293 & masken_or_fullmask;
assign N293 = N292 & mask[0];
assign N292 = N291 & mask[1];
assign N291 = N290 & mask[2];
assign N290 = N289 & mask[3];
assign N289 = N288 & mask[4];
assign N288 = N287 & mask[5];
assign N287 = N286 & mask[6];
assign N286 = N285 & mask[7];
assign N285 = N284 & mask[8];
assign N284 = N283 & mask[9];
assign N283 = N282 & mask[10];
assign N282 = N281 & mask[11];
assign N281 = N280 & mask[12];
assign N280 = mask[14] & mask[13];
assign N107 = ~N106;
assign N109 = N308 & masken_or_fullmask;
assign N308 = N307 & mask[0];
assign N307 = N306 & mask[1];
assign N306 = N305 & mask[2];
assign N305 = N304 & mask[3];
assign N304 = N303 & mask[4];
assign N303 = N302 & mask[5];
assign N302 = N301 & mask[6];
assign N301 = N300 & mask[7];
assign N300 = N299 & mask[8];
assign N299 = N298 & mask[9];
assign N298 = N297 & mask[10];
assign N297 = N296 & mask[11];
assign N296 = N295 & mask[12];
assign N295 = N294 & mask[13];
assign N294 = mask[15] & mask[14];
assign N110 = ~N109;
assign N112 = N324 & masken_or_fullmask;
assign N324 = N323 & mask[0];
assign N323 = N322 & mask[1];
assign N322 = N321 & mask[2];
assign N321 = N320 & mask[3];
assign N320 = N319 & mask[4];
assign N319 = N318 & mask[5];
assign N318 = N317 & mask[6];
assign N317 = N316 & mask[7];
assign N316 = N315 & mask[8];
assign N315 = N314 & mask[9];
assign N314 = N313 & mask[10];
assign N313 = N312 & mask[11];
assign N312 = N311 & mask[12];
assign N311 = N310 & mask[13];
assign N310 = N309 & mask[14];
assign N309 = mask[16] & mask[15];
assign N113 = ~N112;
assign N115 = N341 & masken_or_fullmask;
assign N341 = N340 & mask[0];
assign N340 = N339 & mask[1];
assign N339 = N338 & mask[2];
assign N338 = N337 & mask[3];
assign N337 = N336 & mask[4];
assign N336 = N335 & mask[5];
assign N335 = N334 & mask[6];
assign N334 = N333 & mask[7];
assign N333 = N332 & mask[8];
assign N332 = N331 & mask[9];
assign N331 = N330 & mask[10];
assign N330 = N329 & mask[11];
assign N329 = N328 & mask[12];
assign N328 = N327 & mask[13];
assign N327 = N326 & mask[14];
assign N326 = N325 & mask[15];
assign N325 = mask[17] & mask[16];
assign N116 = ~N115;
assign N118 = N359 & masken_or_fullmask;
assign N359 = N358 & mask[0];
assign N358 = N357 & mask[1];
assign N357 = N356 & mask[2];
assign N356 = N355 & mask[3];
assign N355 = N354 & mask[4];
assign N354 = N353 & mask[5];
assign N353 = N352 & mask[6];
assign N352 = N351 & mask[7];
assign N351 = N350 & mask[8];
assign N350 = N349 & mask[9];
assign N349 = N348 & mask[10];
assign N348 = N347 & mask[11];
assign N347 = N346 & mask[12];
assign N346 = N345 & mask[13];
assign N345 = N344 & mask[14];
assign N344 = N343 & mask[15];
assign N343 = N342 & mask[16];
assign N342 = mask[18] & mask[17];
assign N119 = ~N118;
assign N121 = N378 & masken_or_fullmask;
assign N378 = N377 & mask[0];
assign N377 = N376 & mask[1];
assign N376 = N375 & mask[2];
assign N375 = N374 & mask[3];
assign N374 = N373 & mask[4];
assign N373 = N372 & mask[5];
assign N372 = N371 & mask[6];
assign N371 = N370 & mask[7];
assign N370 = N369 & mask[8];
assign N369 = N368 & mask[9];
assign N368 = N367 & mask[10];
assign N367 = N366 & mask[11];
assign N366 = N365 & mask[12];
assign N365 = N364 & mask[13];
assign N364 = N363 & mask[14];
assign N363 = N362 & mask[15];
assign N362 = N361 & mask[16];
assign N361 = N360 & mask[17];
assign N360 = mask[19] & mask[18];
assign N122 = ~N121;
assign N124 = N398 & masken_or_fullmask;
assign N398 = N397 & mask[0];
assign N397 = N396 & mask[1];
assign N396 = N395 & mask[2];
assign N395 = N394 & mask[3];
assign N394 = N393 & mask[4];
assign N393 = N392 & mask[5];
assign N392 = N391 & mask[6];
assign N391 = N390 & mask[7];
assign N390 = N389 & mask[8];
assign N389 = N388 & mask[9];
assign N388 = N387 & mask[10];
assign N387 = N386 & mask[11];
assign N386 = N385 & mask[12];
assign N385 = N384 & mask[13];
assign N384 = N383 & mask[14];
assign N383 = N382 & mask[15];
assign N382 = N381 & mask[16];
assign N381 = N380 & mask[17];
assign N380 = N379 & mask[18];
assign N379 = mask[20] & mask[19];
assign N125 = ~N124;
assign N127 = N419 & masken_or_fullmask;
assign N419 = N418 & mask[0];
assign N418 = N417 & mask[1];
assign N417 = N416 & mask[2];
assign N416 = N415 & mask[3];
assign N415 = N414 & mask[4];
assign N414 = N413 & mask[5];
assign N413 = N412 & mask[6];
assign N412 = N411 & mask[7];
assign N411 = N410 & mask[8];
assign N410 = N409 & mask[9];
assign N409 = N408 & mask[10];
assign N408 = N407 & mask[11];
assign N407 = N406 & mask[12];
assign N406 = N405 & mask[13];
assign N405 = N404 & mask[14];
assign N404 = N403 & mask[15];
assign N403 = N402 & mask[16];
assign N402 = N401 & mask[17];
assign N401 = N400 & mask[18];
assign N400 = N399 & mask[19];
assign N399 = mask[21] & mask[20];
assign N128 = ~N127;
assign N130 = N441 & masken_or_fullmask;
assign N441 = N440 & mask[0];
assign N440 = N439 & mask[1];
assign N439 = N438 & mask[2];
assign N438 = N437 & mask[3];
assign N437 = N436 & mask[4];
assign N436 = N435 & mask[5];
assign N435 = N434 & mask[6];
assign N434 = N433 & mask[7];
assign N433 = N432 & mask[8];
assign N432 = N431 & mask[9];
assign N431 = N430 & mask[10];
assign N430 = N429 & mask[11];
assign N429 = N428 & mask[12];
assign N428 = N427 & mask[13];
assign N427 = N426 & mask[14];
assign N426 = N425 & mask[15];
assign N425 = N424 & mask[16];
assign N424 = N423 & mask[17];
assign N423 = N422 & mask[18];
assign N422 = N421 & mask[19];
assign N421 = N420 & mask[20];
assign N420 = mask[22] & mask[21];
assign N131 = ~N130;
assign N133 = N464 & masken_or_fullmask;
assign N464 = N463 & mask[0];
assign N463 = N462 & mask[1];
assign N462 = N461 & mask[2];
assign N461 = N460 & mask[3];
assign N460 = N459 & mask[4];
assign N459 = N458 & mask[5];
assign N458 = N457 & mask[6];
assign N457 = N456 & mask[7];
assign N456 = N455 & mask[8];
assign N455 = N454 & mask[9];
assign N454 = N453 & mask[10];
assign N453 = N452 & mask[11];
assign N452 = N451 & mask[12];
assign N451 = N450 & mask[13];
assign N450 = N449 & mask[14];
assign N449 = N448 & mask[15];
assign N448 = N447 & mask[16];
assign N447 = N446 & mask[17];
assign N446 = N445 & mask[18];
assign N445 = N444 & mask[19];
assign N444 = N443 & mask[20];
assign N443 = N442 & mask[21];
assign N442 = mask[23] & mask[22];
assign N134 = ~N133;
assign N136 = N488 & masken_or_fullmask;
assign N488 = N487 & mask[0];
assign N487 = N486 & mask[1];
assign N486 = N485 & mask[2];
assign N485 = N484 & mask[3];
assign N484 = N483 & mask[4];
assign N483 = N482 & mask[5];
assign N482 = N481 & mask[6];
assign N481 = N480 & mask[7];
assign N480 = N479 & mask[8];
assign N479 = N478 & mask[9];
assign N478 = N477 & mask[10];
assign N477 = N476 & mask[11];
assign N476 = N475 & mask[12];
assign N475 = N474 & mask[13];
assign N474 = N473 & mask[14];
assign N473 = N472 & mask[15];
assign N472 = N471 & mask[16];
assign N471 = N470 & mask[17];
assign N470 = N469 & mask[18];
assign N469 = N468 & mask[19];
assign N468 = N467 & mask[20];
assign N467 = N466 & mask[21];
assign N466 = N465 & mask[22];
assign N465 = mask[24] & mask[23];
assign N137 = ~N136;
assign N139 = N513 & masken_or_fullmask;
assign N513 = N512 & mask[0];
assign N512 = N511 & mask[1];
assign N511 = N510 & mask[2];
assign N510 = N509 & mask[3];
assign N509 = N508 & mask[4];
assign N508 = N507 & mask[5];
assign N507 = N506 & mask[6];
assign N506 = N505 & mask[7];
assign N505 = N504 & mask[8];
assign N504 = N503 & mask[9];
assign N503 = N502 & mask[10];
assign N502 = N501 & mask[11];
assign N501 = N500 & mask[12];
assign N500 = N499 & mask[13];
assign N499 = N498 & mask[14];
assign N498 = N497 & mask[15];
assign N497 = N496 & mask[16];
assign N496 = N495 & mask[17];
assign N495 = N494 & mask[18];
assign N494 = N493 & mask[19];
assign N493 = N492 & mask[20];
assign N492 = N491 & mask[21];
assign N491 = N490 & mask[22];
assign N490 = N489 & mask[23];
assign N489 = mask[25] & mask[24];
assign N140 = ~N139;
assign N142 = N539 & masken_or_fullmask;
assign N539 = N538 & mask[0];
assign N538 = N537 & mask[1];
assign N537 = N536 & mask[2];
assign N536 = N535 & mask[3];
assign N535 = N534 & mask[4];
assign N534 = N533 & mask[5];
assign N533 = N532 & mask[6];
assign N532 = N531 & mask[7];
assign N531 = N530 & mask[8];
assign N530 = N529 & mask[9];
assign N529 = N528 & mask[10];
assign N528 = N527 & mask[11];
assign N527 = N526 & mask[12];
assign N526 = N525 & mask[13];
assign N525 = N524 & mask[14];
assign N524 = N523 & mask[15];
assign N523 = N522 & mask[16];
assign N522 = N521 & mask[17];
assign N521 = N520 & mask[18];
assign N520 = N519 & mask[19];
assign N519 = N518 & mask[20];
assign N518 = N517 & mask[21];
assign N517 = N516 & mask[22];
assign N516 = N515 & mask[23];
assign N515 = N514 & mask[24];
assign N514 = mask[26] & mask[25];
assign N143 = ~N142;
assign N145 = N566 & masken_or_fullmask;
assign N566 = N565 & mask[0];
assign N565 = N564 & mask[1];
assign N564 = N563 & mask[2];
assign N563 = N562 & mask[3];
assign N562 = N561 & mask[4];
assign N561 = N560 & mask[5];
assign N560 = N559 & mask[6];
assign N559 = N558 & mask[7];
assign N558 = N557 & mask[8];
assign N557 = N556 & mask[9];
assign N556 = N555 & mask[10];
assign N555 = N554 & mask[11];
assign N554 = N553 & mask[12];
assign N553 = N552 & mask[13];
assign N552 = N551 & mask[14];
assign N551 = N550 & mask[15];
assign N550 = N549 & mask[16];
assign N549 = N548 & mask[17];
assign N548 = N547 & mask[18];
assign N547 = N546 & mask[19];
assign N546 = N545 & mask[20];
assign N545 = N544 & mask[21];
assign N544 = N543 & mask[22];
assign N543 = N542 & mask[23];
assign N542 = N541 & mask[24];
assign N541 = N540 & mask[25];
assign N540 = mask[27] & mask[26];
assign N146 = ~N145;
assign N148 = N594 & masken_or_fullmask;
assign N594 = N593 & mask[0];
assign N593 = N592 & mask[1];
assign N592 = N591 & mask[2];
assign N591 = N590 & mask[3];
assign N590 = N589 & mask[4];
assign N589 = N588 & mask[5];
assign N588 = N587 & mask[6];
assign N587 = N586 & mask[7];
assign N586 = N585 & mask[8];
assign N585 = N584 & mask[9];
assign N584 = N583 & mask[10];
assign N583 = N582 & mask[11];
assign N582 = N581 & mask[12];
assign N581 = N580 & mask[13];
assign N580 = N579 & mask[14];
assign N579 = N578 & mask[15];
assign N578 = N577 & mask[16];
assign N577 = N576 & mask[17];
assign N576 = N575 & mask[18];
assign N575 = N574 & mask[19];
assign N574 = N573 & mask[20];
assign N573 = N572 & mask[21];
assign N572 = N571 & mask[22];
assign N571 = N570 & mask[23];
assign N570 = N569 & mask[24];
assign N569 = N568 & mask[25];
assign N568 = N567 & mask[26];
assign N567 = mask[28] & mask[27];
assign N149 = ~N148;
assign N151 = N623 & masken_or_fullmask;
assign N623 = N622 & mask[0];
assign N622 = N621 & mask[1];
assign N621 = N620 & mask[2];
assign N620 = N619 & mask[3];
assign N619 = N618 & mask[4];
assign N618 = N617 & mask[5];
assign N617 = N616 & mask[6];
assign N616 = N615 & mask[7];
assign N615 = N614 & mask[8];
assign N614 = N613 & mask[9];
assign N613 = N612 & mask[10];
assign N612 = N611 & mask[11];
assign N611 = N610 & mask[12];
assign N610 = N609 & mask[13];
assign N609 = N608 & mask[14];
assign N608 = N607 & mask[15];
assign N607 = N606 & mask[16];
assign N606 = N605 & mask[17];
assign N605 = N604 & mask[18];
assign N604 = N603 & mask[19];
assign N603 = N602 & mask[20];
assign N602 = N601 & mask[21];
assign N601 = N600 & mask[22];
assign N600 = N599 & mask[23];
assign N599 = N598 & mask[24];
assign N598 = N597 & mask[25];
assign N597 = N596 & mask[26];
assign N596 = N595 & mask[27];
assign N595 = mask[29] & mask[28];
assign N152 = ~N151;
assign N154 = N653 & masken_or_fullmask;
assign N653 = N652 & mask[0];
assign N652 = N651 & mask[1];
assign N651 = N650 & mask[2];
assign N650 = N649 & mask[3];
assign N649 = N648 & mask[4];
assign N648 = N647 & mask[5];
assign N647 = N646 & mask[6];
assign N646 = N645 & mask[7];
assign N645 = N644 & mask[8];
assign N644 = N643 & mask[9];
assign N643 = N642 & mask[10];
assign N642 = N641 & mask[11];
assign N641 = N640 & mask[12];
assign N640 = N639 & mask[13];
assign N639 = N638 & mask[14];
assign N638 = N637 & mask[15];
assign N637 = N636 & mask[16];
assign N636 = N635 & mask[17];
assign N635 = N634 & mask[18];
assign N634 = N633 & mask[19];
assign N633 = N632 & mask[20];
assign N632 = N631 & mask[21];
assign N631 = N630 & mask[22];
assign N630 = N629 & mask[23];
assign N629 = N628 & mask[24];
assign N628 = N627 & mask[25];
assign N627 = N626 & mask[26];
assign N626 = N625 & mask[27];
assign N625 = N624 & mask[28];
assign N624 = mask[30] & mask[29];
assign N155 = ~N154;
assign match = N683 & matchvec[0];
assign N683 = N682 & matchvec[1];
assign N682 = N681 & matchvec[2];
assign N681 = N680 & matchvec[3];
assign N680 = N679 & matchvec[4];
assign N679 = N678 & matchvec[5];
assign N678 = N677 & matchvec[6];
assign N677 = N676 & matchvec[7];
assign N676 = N675 & matchvec[8];
assign N675 = N674 & matchvec[9];
assign N674 = N673 & matchvec[10];
assign N673 = N672 & matchvec[11];
assign N672 = N671 & matchvec[12];
assign N671 = N670 & matchvec[13];
assign N670 = N669 & matchvec[14];
assign N669 = N668 & matchvec[15];
assign N668 = N667 & matchvec[16];
assign N667 = N666 & matchvec[17];
assign N666 = N665 & matchvec[18];
assign N665 = N664 & matchvec[19];
assign N664 = N663 & matchvec[20];
assign N663 = N662 & matchvec[21];
assign N662 = N661 & matchvec[22];
assign N661 = N660 & matchvec[23];
assign N660 = N659 & matchvec[24];
assign N659 = N658 & matchvec[25];
assign N658 = N657 & matchvec[26];
assign N657 = N656 & matchvec[27];
assign N656 = N655 & matchvec[28];
assign N655 = N654 & matchvec[29];
assign N654 = matchvec[31] & matchvec[30];
endmodule |
module rvdff_WIDTH48
(
din,
clk,
rst_l,
dout
);
input [47:0] din;
output [47:0] dout;
input clk;
input rst_l;
wire N0;
reg [47:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[47] <= 1'b0;
end else if(1'b1) begin
dout[47] <= din[47];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[46] <= 1'b0;
end else if(1'b1) begin
dout[46] <= din[46];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[45] <= 1'b0;
end else if(1'b1) begin
dout[45] <= din[45];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[44] <= 1'b0;
end else if(1'b1) begin
dout[44] <= din[44];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[43] <= 1'b0;
end else if(1'b1) begin
dout[43] <= din[43];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[42] <= 1'b0;
end else if(1'b1) begin
dout[42] <= din[42];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[41] <= 1'b0;
end else if(1'b1) begin
dout[41] <= din[41];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[40] <= 1'b0;
end else if(1'b1) begin
dout[40] <= din[40];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[39] <= 1'b0;
end else if(1'b1) begin
dout[39] <= din[39];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[38] <= 1'b0;
end else if(1'b1) begin
dout[38] <= din[38];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[37] <= 1'b0;
end else if(1'b1) begin
dout[37] <= din[37];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvdff_WIDTH4
(
din,
clk,
rst_l,
dout
);
input [3:0] din;
output [3:0] dout;
input clk;
input rst_l;
wire N0;
reg [3:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvbradder
(
pc,
offset,
dout
);
input [31:1] pc;
input [12:1] offset;
output [31:1] dout;
wire [31:1] dout;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,cout,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,
N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,
N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,
N149,N150,N151,N152,N153;
wire [31:13] pc_inc,pc_dec;
assign { cout, dout[12:1] } = pc[12:1] + offset;
assign pc_inc = pc[31:13] + 1'b1;
assign pc_dec = pc[31:13] - 1'b1;
assign dout[31] = N24 | N27;
assign N24 = N20 | N23;
assign N20 = N19 & pc[31];
assign N0 = offset[12] ^ cout;
assign N19 = ~N0;
assign N23 = N22 & pc_inc[31];
assign N22 = N21 & cout;
assign N21 = ~offset[12];
assign N27 = N26 & pc_dec[31];
assign N26 = offset[12] & N25;
assign N25 = ~cout;
assign dout[30] = N32 | N34;
assign N32 = N29 | N31;
assign N29 = N28 & pc[30];
assign N1 = offset[12] ^ cout;
assign N28 = ~N1;
assign N31 = N30 & pc_inc[30];
assign N30 = N21 & cout;
assign N34 = N33 & pc_dec[30];
assign N33 = offset[12] & N25;
assign dout[29] = N39 | N41;
assign N39 = N36 | N38;
assign N36 = N35 & pc[29];
assign N2 = offset[12] ^ cout;
assign N35 = ~N2;
assign N38 = N37 & pc_inc[29];
assign N37 = N21 & cout;
assign N41 = N40 & pc_dec[29];
assign N40 = offset[12] & N25;
assign dout[28] = N46 | N48;
assign N46 = N43 | N45;
assign N43 = N42 & pc[28];
assign N3 = offset[12] ^ cout;
assign N42 = ~N3;
assign N45 = N44 & pc_inc[28];
assign N44 = N21 & cout;
assign N48 = N47 & pc_dec[28];
assign N47 = offset[12] & N25;
assign dout[27] = N53 | N55;
assign N53 = N50 | N52;
assign N50 = N49 & pc[27];
assign N4 = offset[12] ^ cout;
assign N49 = ~N4;
assign N52 = N51 & pc_inc[27];
assign N51 = N21 & cout;
assign N55 = N54 & pc_dec[27];
assign N54 = offset[12] & N25;
assign dout[26] = N60 | N62;
assign N60 = N57 | N59;
assign N57 = N56 & pc[26];
assign N5 = offset[12] ^ cout;
assign N56 = ~N5;
assign N59 = N58 & pc_inc[26];
assign N58 = N21 & cout;
assign N62 = N61 & pc_dec[26];
assign N61 = offset[12] & N25;
assign dout[25] = N67 | N69;
assign N67 = N64 | N66;
assign N64 = N63 & pc[25];
assign N6 = offset[12] ^ cout;
assign N63 = ~N6;
assign N66 = N65 & pc_inc[25];
assign N65 = N21 & cout;
assign N69 = N68 & pc_dec[25];
assign N68 = offset[12] & N25;
assign dout[24] = N74 | N76;
assign N74 = N71 | N73;
assign N71 = N70 & pc[24];
assign N7 = offset[12] ^ cout;
assign N70 = ~N7;
assign N73 = N72 & pc_inc[24];
assign N72 = N21 & cout;
assign N76 = N75 & pc_dec[24];
assign N75 = offset[12] & N25;
assign dout[23] = N81 | N83;
assign N81 = N78 | N80;
assign N78 = N77 & pc[23];
assign N8 = offset[12] ^ cout;
assign N77 = ~N8;
assign N80 = N79 & pc_inc[23];
assign N79 = N21 & cout;
assign N83 = N82 & pc_dec[23];
assign N82 = offset[12] & N25;
assign dout[22] = N88 | N90;
assign N88 = N85 | N87;
assign N85 = N84 & pc[22];
assign N9 = offset[12] ^ cout;
assign N84 = ~N9;
assign N87 = N86 & pc_inc[22];
assign N86 = N21 & cout;
assign N90 = N89 & pc_dec[22];
assign N89 = offset[12] & N25;
assign dout[21] = N95 | N97;
assign N95 = N92 | N94;
assign N92 = N91 & pc[21];
assign N10 = offset[12] ^ cout;
assign N91 = ~N10;
assign N94 = N93 & pc_inc[21];
assign N93 = N21 & cout;
assign N97 = N96 & pc_dec[21];
assign N96 = offset[12] & N25;
assign dout[20] = N102 | N104;
assign N102 = N99 | N101;
assign N99 = N98 & pc[20];
assign N11 = offset[12] ^ cout;
assign N98 = ~N11;
assign N101 = N100 & pc_inc[20];
assign N100 = N21 & cout;
assign N104 = N103 & pc_dec[20];
assign N103 = offset[12] & N25;
assign dout[19] = N109 | N111;
assign N109 = N106 | N108;
assign N106 = N105 & pc[19];
assign N12 = offset[12] ^ cout;
assign N105 = ~N12;
assign N108 = N107 & pc_inc[19];
assign N107 = N21 & cout;
assign N111 = N110 & pc_dec[19];
assign N110 = offset[12] & N25;
assign dout[18] = N116 | N118;
assign N116 = N113 | N115;
assign N113 = N112 & pc[18];
assign N13 = offset[12] ^ cout;
assign N112 = ~N13;
assign N115 = N114 & pc_inc[18];
assign N114 = N21 & cout;
assign N118 = N117 & pc_dec[18];
assign N117 = offset[12] & N25;
assign dout[17] = N123 | N125;
assign N123 = N120 | N122;
assign N120 = N119 & pc[17];
assign N14 = offset[12] ^ cout;
assign N119 = ~N14;
assign N122 = N121 & pc_inc[17];
assign N121 = N21 & cout;
assign N125 = N124 & pc_dec[17];
assign N124 = offset[12] & N25;
assign dout[16] = N130 | N132;
assign N130 = N127 | N129;
assign N127 = N126 & pc[16];
assign N15 = offset[12] ^ cout;
assign N126 = ~N15;
assign N129 = N128 & pc_inc[16];
assign N128 = N21 & cout;
assign N132 = N131 & pc_dec[16];
assign N131 = offset[12] & N25;
assign dout[15] = N137 | N139;
assign N137 = N134 | N136;
assign N134 = N133 & pc[15];
assign N16 = offset[12] ^ cout;
assign N133 = ~N16;
assign N136 = N135 & pc_inc[15];
assign N135 = N21 & cout;
assign N139 = N138 & pc_dec[15];
assign N138 = offset[12] & N25;
assign dout[14] = N144 | N146;
assign N144 = N141 | N143;
assign N141 = N140 & pc[14];
assign N17 = offset[12] ^ cout;
assign N140 = ~N17;
assign N143 = N142 & pc_inc[14];
assign N142 = N21 & cout;
assign N146 = N145 & pc_dec[14];
assign N145 = offset[12] & N25;
assign dout[13] = N151 | N153;
assign N151 = N148 | N150;
assign N148 = N147 & pc[13];
assign N18 = offset[12] ^ cout;
assign N147 = ~N18;
assign N150 = N149 & pc_inc[13];
assign N149 = N21 & cout;
assign N153 = N152 & pc_dec[13];
assign N152 = offset[12] & N25;
endmodule |
module rvdff_WIDTH18
(
din,
clk,
rst_l,
dout
);
input [17:0] din;
output [17:0] dout;
input clk;
input rst_l;
wire N0;
reg [17:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvrangecheck_f00c0000_32
(
addr,
in_range,
in_region
);
input [31:0] addr;
output in_range;
output in_region;
wire in_range,in_region,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,
N17,N18,N19,N20,N21,N23,N24;
assign N0 = ~addr[31];
assign N1 = ~addr[30];
assign N2 = ~addr[29];
assign N3 = ~addr[28];
assign N4 = ~addr[19];
assign N5 = ~addr[18];
assign N6 = N1 | N0;
assign N7 = N2 | N6;
assign N8 = N3 | N7;
assign N9 = addr[27] | N8;
assign N10 = addr[26] | N9;
assign N11 = addr[25] | N10;
assign N12 = addr[24] | N11;
assign N13 = addr[23] | N12;
assign N14 = addr[22] | N13;
assign N15 = addr[21] | N14;
assign N16 = addr[20] | N15;
assign N17 = N4 | N16;
assign N18 = N5 | N17;
assign N19 = addr[17] | N18;
assign N20 = addr[16] | N19;
assign N21 = addr[15] | N20;
assign in_range = ~N21;
assign N23 = addr[30] & addr[31];
assign N24 = addr[29] & N23;
assign in_region = addr[28] & N24;
endmodule |
module rvdff_WIDTH53
(
din,
clk,
rst_l,
dout
);
input [52:0] din;
output [52:0] dout;
input clk;
input rst_l;
wire N0;
reg [52:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[52] <= 1'b0;
end else if(1'b1) begin
dout[52] <= din[52];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[51] <= 1'b0;
end else if(1'b1) begin
dout[51] <= din[51];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[50] <= 1'b0;
end else if(1'b1) begin
dout[50] <= din[50];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[49] <= 1'b0;
end else if(1'b1) begin
dout[49] <= din[49];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[48] <= 1'b0;
end else if(1'b1) begin
dout[48] <= din[48];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[47] <= 1'b0;
end else if(1'b1) begin
dout[47] <= din[47];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[46] <= 1'b0;
end else if(1'b1) begin
dout[46] <= din[46];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[45] <= 1'b0;
end else if(1'b1) begin
dout[45] <= din[45];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[44] <= 1'b0;
end else if(1'b1) begin
dout[44] <= din[44];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[43] <= 1'b0;
end else if(1'b1) begin
dout[43] <= din[43];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[42] <= 1'b0;
end else if(1'b1) begin
dout[42] <= din[42];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[41] <= 1'b0;
end else if(1'b1) begin
dout[41] <= din[41];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[40] <= 1'b0;
end else if(1'b1) begin
dout[40] <= din[40];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[39] <= 1'b0;
end else if(1'b1) begin
dout[39] <= din[39];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[38] <= 1'b0;
end else if(1'b1) begin
dout[38] <= din[38];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[37] <= 1'b0;
end else if(1'b1) begin
dout[37] <= din[37];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[36] <= 1'b0;
end else if(1'b1) begin
dout[36] <= din[36];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[35] <= 1'b0;
end else if(1'b1) begin
dout[35] <= din[35];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[34] <= 1'b0;
end else if(1'b1) begin
dout[34] <= din[34];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[33] <= 1'b0;
end else if(1'b1) begin
dout[33] <= din[33];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[32] <= 1'b0;
end else if(1'b1) begin
dout[32] <= din[32];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[31] <= 1'b0;
end else if(1'b1) begin
dout[31] <= din[31];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[30] <= 1'b0;
end else if(1'b1) begin
dout[30] <= din[30];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[29] <= 1'b0;
end else if(1'b1) begin
dout[29] <= din[29];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[28] <= 1'b0;
end else if(1'b1) begin
dout[28] <= din[28];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[27] <= 1'b0;
end else if(1'b1) begin
dout[27] <= din[27];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[26] <= 1'b0;
end else if(1'b1) begin
dout[26] <= din[26];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[25] <= 1'b0;
end else if(1'b1) begin
dout[25] <= din[25];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[24] <= 1'b0;
end else if(1'b1) begin
dout[24] <= din[24];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[23] <= 1'b0;
end else if(1'b1) begin
dout[23] <= din[23];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[22] <= 1'b0;
end else if(1'b1) begin
dout[22] <= din[22];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[21] <= 1'b0;
end else if(1'b1) begin
dout[21] <= din[21];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[20] <= 1'b0;
end else if(1'b1) begin
dout[20] <= din[20];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[19] <= 1'b0;
end else if(1'b1) begin
dout[19] <= din[19];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[18] <= 1'b0;
end else if(1'b1) begin
dout[18] <= din[18];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[17] <= 1'b0;
end else if(1'b1) begin
dout[17] <= din[17];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[16] <= 1'b0;
end else if(1'b1) begin
dout[16] <= din[16];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[15] <= 1'b0;
end else if(1'b1) begin
dout[15] <= din[15];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[14] <= 1'b0;
end else if(1'b1) begin
dout[14] <= din[14];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[13] <= 1'b0;
end else if(1'b1) begin
dout[13] <= din[13];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[12] <= 1'b0;
end else if(1'b1) begin
dout[12] <= din[12];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rveven_paritycheck
(
data_in,
parity_in,
parity_err
);
input [15:0] data_in;
input parity_in;
output parity_err;
wire parity_err,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign parity_err = N14 ^ parity_in;
assign N14 = N13 ^ data_in[0];
assign N13 = N12 ^ data_in[1];
assign N12 = N11 ^ data_in[2];
assign N11 = N10 ^ data_in[3];
assign N10 = N9 ^ data_in[4];
assign N9 = N8 ^ data_in[5];
assign N8 = N7 ^ data_in[6];
assign N7 = N6 ^ data_in[7];
assign N6 = N5 ^ data_in[8];
assign N5 = N4 ^ data_in[9];
assign N4 = N3 ^ data_in[10];
assign N3 = N2 ^ data_in[11];
assign N2 = N1 ^ data_in[12];
assign N1 = N0 ^ data_in[13];
assign N0 = data_in[15] ^ data_in[14];
endmodule |
module cmp_and_mux_ID_BITS8_INTPRIORITY_BITS4
(
a_id,
a_priority,
b_id,
b_priority,
out_id,
out_priority
);
input [7:0] a_id;
input [3:0] a_priority;
input [7:0] b_id;
input [3:0] b_priority;
output [7:0] out_id;
output [3:0] out_priority;
wire [7:0] out_id;
wire [3:0] out_priority;
wire N0,N1,a_is_lt_b,N2;
assign a_is_lt_b = a_priority < b_priority;
assign out_id = (N0)? b_id :
(N1)? a_id : 1'b0;
assign N0 = a_is_lt_b;
assign N1 = N2;
assign out_priority = (N0)? b_priority :
(N1)? a_priority : 1'b0;
assign N2 = ~a_is_lt_b;
endmodule |
module rvbtb_addr_hash
(
pc,
hash
);
input [31:1] pc;
output [5:4] hash;
wire [5:4] hash;
wire N0,N1;
assign hash[5] = N0 ^ pc[9];
assign N0 = pc[5] ^ pc[7];
assign hash[4] = N1 ^ pc[8];
assign N1 = pc[4] ^ pc[6];
endmodule |
module rvdff_WIDTH12
(
din,
clk,
rst_l,
dout
);
input [11:0] din;
output [11:0] dout;
input clk;
input rst_l;
wire N0;
reg [11:0] dout;
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[11] <= 1'b0;
end else if(1'b1) begin
dout[11] <= din[11];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[10] <= 1'b0;
end else if(1'b1) begin
dout[10] <= din[10];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[9] <= 1'b0;
end else if(1'b1) begin
dout[9] <= din[9];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[8] <= 1'b0;
end else if(1'b1) begin
dout[8] <= din[8];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[7] <= 1'b0;
end else if(1'b1) begin
dout[7] <= din[7];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[6] <= 1'b0;
end else if(1'b1) begin
dout[6] <= din[6];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[5] <= 1'b0;
end else if(1'b1) begin
dout[5] <= din[5];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[4] <= 1'b0;
end else if(1'b1) begin
dout[4] <= din[4];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[3] <= 1'b0;
end else if(1'b1) begin
dout[3] <= din[3];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[2] <= 1'b0;
end else if(1'b1) begin
dout[2] <= din[2];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[1] <= 1'b0;
end else if(1'b1) begin
dout[1] <= din[1];
end
end
always @(posedge clk or posedge N0) begin
if(N0) begin
dout[0] <= 1'b0;
end else if(1'b1) begin
dout[0] <= din[0];
end
end
assign N0 = ~rst_l;
endmodule |
module rvbtb_ghr_hash
(
hashin,
ghr,
hash
);
input [5:4] hashin;
input [4:0] ghr;
output [7:4] hash;
wire [7:4] hash;
assign hash[6] = ghr[2];
assign hash[7] = ghr[3] ^ ghr[4];
assign hash[5] = hashin[5] ^ ghr[1];
assign hash[4] = hashin[4] ^ ghr[0];
endmodule |
module rvrangecheck_f0040000_64
(
addr,
in_range,
in_region
);
input [31:0] addr;
output in_range;
output in_region;
wire in_range,in_region,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,
N17,N18,N19,N21,N22;
assign N0 = ~addr[31];
assign N1 = ~addr[30];
assign N2 = ~addr[29];
assign N3 = ~addr[28];
assign N4 = ~addr[18];
assign N5 = N1 | N0;
assign N6 = N2 | N5;
assign N7 = N3 | N6;
assign N8 = addr[27] | N7;
assign N9 = addr[26] | N8;
assign N10 = addr[25] | N9;
assign N11 = addr[24] | N10;
assign N12 = addr[23] | N11;
assign N13 = addr[22] | N12;
assign N14 = addr[21] | N13;
assign N15 = addr[20] | N14;
assign N16 = addr[19] | N15;
assign N17 = N4 | N16;
assign N18 = addr[17] | N17;
assign N19 = addr[16] | N18;
assign in_range = ~N19;
assign N21 = addr[30] & addr[31];
assign N22 = addr[29] & N21;
assign in_region = addr[28] & N22;
endmodule |
module dynamic_input_route_request_calc(route_req_n, route_req_e, route_req_s, route_req_w, route_req_p,
default_ready_n, default_ready_e, default_ready_s, default_ready_w, default_ready_p,
my_loc_x_in, my_loc_y_in, my_chip_id_in, abs_x, abs_y, abs_chip_id, final_bits, length, header_in);
// begin port declarations
output route_req_n;
output route_req_e;
output route_req_s;
output route_req_w;
output route_req_p;
output default_ready_n;
output default_ready_e;
output default_ready_s;
output default_ready_w;
output default_ready_p;
input [8-1:0] my_loc_x_in;
input [8-1:0] my_loc_y_in;
input [14-1:0] my_chip_id_in;
input [8-1:0] abs_x;
input [8-1:0] abs_y;
input [14-1:0] abs_chip_id;
input [2:0] final_bits;
input [8-1:0] length;
input header_in;
// end port declarations
//fbit declarations
//This is the state
//NONE
//inputs to the state
//NONE
//wires
wire more_x;
wire more_y;
wire less_x;
wire less_y;
wire done_x;
wire done_y;
wire off_chip;
wire done;
wire north;
wire east;
wire south;
wire west;
wire proc;
wire north_calc;
wire south_calc;
//wire regs
//assigns
assign off_chip = abs_chip_id != my_chip_id_in;
assign more_x = off_chip ? 0 > my_loc_x_in : abs_x > my_loc_x_in;
assign more_y = off_chip ? 0 > my_loc_y_in : abs_y > my_loc_y_in;
assign less_x = off_chip ? 0 < my_loc_x_in : abs_x < my_loc_x_in;
assign less_y = off_chip ? 0 < my_loc_y_in : abs_y < my_loc_y_in;
assign done_x = off_chip ? 0 == my_loc_x_in : abs_x == my_loc_x_in;
assign done_y = off_chip ? 0 == my_loc_y_in : abs_y == my_loc_y_in;
assign done = done_x & done_y;
assign north_calc = done_x & less_y;
assign south_calc = done_x & more_y;
assign north = north_calc | ((final_bits == 3'b101) & done);
assign south = south_calc | ((final_bits == 3'b011) & done);
assign east = more_x | ((final_bits == 3'b100) & done);
assign west = less_x | ((final_bits == 3'b010) & done);
assign proc = ((final_bits == 3'b000) & done);
assign route_req_n = header_in & north;
assign route_req_e = header_in & east;
assign route_req_s = header_in & south;
assign route_req_w = header_in & west;
assign route_req_p = header_in & proc;
assign default_ready_n = route_req_n;
assign default_ready_e = route_req_e;
assign default_ready_s = route_req_s;
assign default_ready_w = route_req_w;
assign default_ready_p = route_req_p;
//instantiations
endmodule |
module one_of_eight(in0,in1,in2,in3,in4,in5,in6,in7,sel,out);
parameter WIDTH = 8;
parameter BHC = 10;
input [2:0] sel;
input [WIDTH-1:0] in0,in1,in2,in3,in4,in5,in6,in7;
output reg [WIDTH-1:0] out;
always@ (*)
begin
out={WIDTH{1'b0}};
case(sel)
3'd0:out=in0;
3'd1:out=in1;
3'd2:out=in2;
3'd3:out=in3;
3'd4:out=in4;
3'd5:out=in5;
3'd6:out=in6;
3'd7:out=in7;
default:; // indicates null
endcase
end
endmodule |
module bus_compare_equal (a, b, bus_equal);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] a, b;
output wire bus_equal;
assign bus_equal = (a==b) ? 1'b1 : 1'b0;
endmodule |
module space_avail_top (valid,
yummy,
spc_avail,
clk,
reset);
parameter BUFFER_SIZE = 4;
parameter BUFFER_BITS = 3;
input valid; // sending data to the output
input yummy; // output consumed data
output spc_avail; // is there space available?
input clk;
input reset;
//This is the state
reg yummy_f;
reg valid_f;
reg [BUFFER_BITS-1:0] count_f;
reg is_one_f;
reg is_two_or_more_f;
//wires
wire [BUFFER_BITS-1:0] count_plus_1;
wire [BUFFER_BITS-1:0] count_minus_1;
wire up;
wire down;
//wire regs
reg [BUFFER_BITS-1:0] count_temp;
//assigns
assign count_plus_1 = count_f + 1'b1;
assign count_minus_1 = count_f - 1'b1;
assign spc_avail = (is_two_or_more_f | yummy_f | (is_one_f & ~valid_f));
assign up = yummy_f & ~valid_f;
assign down = ~yummy_f & valid_f;
always @ (count_f or count_plus_1 or count_minus_1 or up or down)
begin
case (count_f)
0:
begin
if(up)
begin
count_temp <= count_plus_1;
end
else
begin
count_temp <= count_f;
end
end
BUFFER_SIZE:
begin
if(down)
begin
count_temp <= count_minus_1;
end
else
begin
count_temp <= count_f;
end
end
default:
begin
case ({up, down})
2'b10: count_temp <= count_plus_1;
2'b01: count_temp <= count_minus_1;
default: count_temp <= count_f;
endcase
end
endcase
end
wire top_bits_zero_temp = ~| count_temp[BUFFER_BITS-1:1];
always @ (posedge clk)
begin
if(reset)
begin
count_f <= BUFFER_SIZE;
yummy_f <= 1'b0;
valid_f <= 1'b0;
is_one_f <= (BUFFER_SIZE == 1);
is_two_or_more_f <= (BUFFER_SIZE >= 2);
end
else
begin
count_f <= count_temp;
yummy_f <= yummy;
valid_f <= valid;
is_one_f <= top_bits_zero_temp & count_temp[0];
is_two_or_more_f <= ~top_bits_zero_temp;
end
end
endmodule |
module flip_bus (in, out);
parameter WIDTH = 8;
parameter BHC = 10;
input [WIDTH-1:0] in;
output wire [WIDTH-1:0] out;
assign out = ~in;
endmodule |
module one_of_five(in0,in1,in2,in3,in4,sel,out);
parameter WIDTH = 8;
parameter BHC = 10;
input [2:0] sel;
input [WIDTH-1:0] in0,in1,in2,in3,in4;
output reg [WIDTH-1:0] out;
always@(*)
begin
out={WIDTH{1'b0}};
case(sel)
3'd0:out=in0;
3'd1:out=in1;
3'd2:out=in2;
3'd3:out=in3;
3'd4:out=in4;
default:; // indicates null
endcase
end
endmodule |
module dynamic_output_control(thanks_a, thanks_b, thanks_c, thanks_d, thanks_x, valid_out, current_route, ec_wants_to_send_but_cannot, clk, reset, route_req_a_in, route_req_b_in, route_req_c_in, route_req_d_in, route_req_x_in, tail_a_in, tail_b_in, tail_c_in, tail_d_in, tail_x_in, valid_out_temp, default_ready, space_avail);
// begin port declarations
output thanks_a;
output thanks_b;
output thanks_c;
output thanks_d;
output thanks_x;
output valid_out;
output [2:0] current_route;
output ec_wants_to_send_but_cannot;
input clk;
input reset;
input route_req_a_in;
input route_req_b_in;
input route_req_c_in;
input route_req_d_in;
input route_req_x_in;
input tail_a_in;
input tail_b_in;
input tail_c_in;
input tail_d_in;
input tail_x_in;
input valid_out_temp;
input default_ready;
input space_avail;
// end port declarations
//This is the state
reg [2:0]current_route_f;
reg planned_f;
//inputs to the state
wire [2:0] current_route_temp;
//wires
wire planned_or_default;
// wire route_req_all_or;
wire route_req_all_or_with_planned;
wire route_req_all_but_default;
wire valid_out_internal;
//wire regs
reg new_route_needed;
reg planned_temp;
reg [2:0] new_route;
reg tail_current_route;
/*reg route_req_planned;*/
reg route_req_a_mask;
reg route_req_b_mask;
reg route_req_c_mask;
reg route_req_d_mask;
reg route_req_x_mask;
//more wire regs for the thanks lines
reg thanks_a;
reg thanks_b;
reg thanks_c;
reg thanks_d;
reg thanks_x;
reg ec_wants_to_send_but_cannot;
//assigns
assign planned_or_default = planned_f | default_ready;
assign valid_out_internal = valid_out_temp & planned_or_default & space_avail;
// mbt: if valid_out_interal is a critical path, we can use some "bleeder" gates to decrease the load of the ec stuff
always @(posedge clk)
begin
ec_wants_to_send_but_cannot <= valid_out_temp & planned_or_default & ~space_avail;
end
/* assign route_req_all_or = route_req_a_in | route_req_b_in | route_req_c_in | route_req_d_in | route_req_x_in; */
assign current_route_temp = (new_route_needed) ? new_route : current_route_f;
assign current_route = current_route_f;
//this is everything except the currentl planned route's request
assign route_req_all_or_with_planned = (route_req_a_in & route_req_a_mask) | (route_req_b_in & route_req_b_mask) | (route_req_c_in & route_req_c_mask) | (route_req_d_in & route_req_d_mask) | (route_req_x_in & route_req_x_mask);
//calculates whether the nib that we are going to has space
assign route_req_all_but_default = route_req_b_in | route_req_c_in | route_req_d_in | route_req_x_in;
assign valid_out = valid_out_internal;
//instantiations
//space_avail space(.valid(valid_out_internal), .clk(clk), .reset(reset), .yummy(yummy_in), .spc_avail(space_avail));
//THIS HAS BEEN MOVED to dynamic_output_top
//a mux for current_route_f's tail bit
always @ (current_route_f or tail_a_in or tail_b_in or tail_c_in or tail_d_in or tail_x_in)
begin
(* parallel_case *) case(current_route_f)
3'b000:
begin
tail_current_route <= tail_a_in;
end
3'b001:
begin
tail_current_route <= tail_b_in;
end
3'b010:
begin
tail_current_route <= tail_c_in;
end
3'b011:
begin
tail_current_route <= tail_d_in;
end
3'b100:
begin
tail_current_route <= tail_x_in;
end
default:
begin
tail_current_route <= 1'bx; //This is probably dangerous, but I
//really need the speed here and
//I don't want the synthesizer to
//mess me up if I put a real value
//here
end
endcase
end
always @ (current_route_f or valid_out_internal)
begin
case(current_route_f)
3'b000:
begin
thanks_a <= valid_out_internal;
thanks_b <= 1'b0;
thanks_c <= 1'b0;
thanks_d <= 1'b0;
thanks_x <= 1'b0;
end
3'b001:
begin
thanks_a <= 1'b0;
thanks_b <= valid_out_internal;
thanks_c <= 1'b0;
thanks_d <= 1'b0;
thanks_x <= 1'b0;
end
3'b010:
begin
thanks_a <= 1'b0;
thanks_b <= 1'b0;
thanks_c <= valid_out_internal;
thanks_d <= 1'b0;
thanks_x <= 1'b0;
end
3'b011:
begin
thanks_a <= 1'b0;
thanks_b <= 1'b0;
thanks_c <= 1'b0;
thanks_d <= valid_out_internal;
thanks_x <= 1'b0;
end
3'b100:
begin
thanks_a <= 1'b0;
thanks_b <= 1'b0;
thanks_c <= 1'b0;
thanks_d <= 1'b0;
thanks_x <= valid_out_internal;
end
default:
begin
thanks_a <= 1'bx;
thanks_b <= 1'bx;
thanks_c <= 1'bx;
thanks_d <= 1'bx;
thanks_x <= 1'bx;
//once again this is very dangerous
//but I want to see the timing this
//way and we sould never get here
end
endcase
end
//this is the rotating priority encoder
/*
always @(current_route_f or route_req_a_in or route_req_b_in or route_req_c_in or route_req_d_in or route_req_x_in)
begin
case(current_route_f)
`ROUTE_A:
begin
new_route <= (route_req_b_in)?`ROUTE_B:((route_req_c_in)?`ROUTE_C:((route_req_d_in)?`ROUTE_D:((route_req_x_in)?`ROUTE_X:`ROUTE_A)));
end
`ROUTE_B:
begin
new_route <= (route_req_c_in)?`ROUTE_C:((route_req_d_in)?`ROUTE_D:((route_req_x_in)?`ROUTE_X:((route_req_a_in)?`ROUTE_A:((route_req_b_in)?`ROUTE_B:`ROUTE_A))));
end
`ROUTE_C:
begin
new_route <= (route_req_d_in)?`ROUTE_D:((route_req_x_in)?`ROUTE_X:((route_req_a_in)?`ROUTE_A:((route_req_b_in)?`ROUTE_B:((route_req_c_in)?`ROUTE_C:`ROUTE_A))));
end
`ROUTE_D:
begin
new_route <= (route_req_c_in)?`ROUTE_C:((route_req_d_in)?`ROUTE_D:((route_req_x_in)?`ROUTE_X:((route_req_a_in)?`ROUTE_A:((route_req_b_in)?`ROUTE_B:`ROUTE_A))));
end
`ROUTE_X:
begin
new_route <= (route_req_x_in)?`ROUTE_X:((route_req_a_in)?`ROUTE_A:((route_req_b_in)?`ROUTE_B:((route_req_c_in)?`ROUTE_C:((route_req_d_in)?`ROUTE_D:`ROUTE_A))));
end
default:
begin
new_route <= `ROUTE_A;
//this one I am not willing to chince on
end
endcase
end
*/
//end the rotating priority encoder
//this is the rotating priority encoder
always @(current_route_f or route_req_a_in or route_req_b_in or route_req_c_in or route_req_d_in or route_req_x_in)
begin
case(current_route_f)
3'b000:
begin
new_route <= (route_req_b_in)?3'b001:((route_req_c_in)?3'b010:((route_req_d_in)?3'b011:((route_req_x_in)?3'b100:3'b000)));
end
3'b001:
begin
new_route <= (route_req_c_in)?3'b010:((route_req_d_in)?3'b011:((route_req_x_in)?3'b100:((route_req_a_in)?3'b000:3'b000)));
end
3'b010:
begin
new_route <= (route_req_d_in)?3'b011:((route_req_x_in)?3'b100:((route_req_a_in)?3'b000:((route_req_b_in)?3'b001:3'b000)));
end
3'b011:
begin
new_route <= (route_req_x_in)?3'b100:((route_req_a_in)?3'b000:((route_req_b_in)?3'b001:((route_req_c_in)?3'b010:3'b000)));
end
3'b100:
begin
new_route <= (route_req_a_in)?3'b000:((route_req_b_in)?3'b001:((route_req_c_in)?3'b010:((route_req_d_in)?3'b011:3'b000)));
end
default:
begin
new_route <= 3'b000;
//this one I am not willing to chince on
end
endcase
end
//end the rotating priority encoder
always @(current_route_f or planned_f)
begin
if(planned_f)
begin
case(current_route_f)
3'b000:
begin
route_req_a_mask <= 1'b0;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b1;
end
3'b001:
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b0;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b1;
end
3'b010:
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b0;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b1;
end
3'b011:
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b0;
route_req_x_mask <= 1'b1;
end
3'b100:
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b0;
end
default:
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b1;
end
endcase
end
else
begin
route_req_a_mask <= 1'b1;
route_req_b_mask <= 1'b1;
route_req_c_mask <= 1'b1;
route_req_d_mask <= 1'b1;
route_req_x_mask <= 1'b1;
end
end
//calculation of new_route_needed
always @ (planned_f or tail_current_route or valid_out_internal or default_ready)
begin
(* parallel_case *) case({default_ready, valid_out_internal, tail_current_route, planned_f})
4'b0000: new_route_needed <= 1'b1;
4'b0001: new_route_needed <= 1'b0;
4'b0010: new_route_needed <= 1'b1;
4'b0011: new_route_needed <= 1'b0;
4'b0100: new_route_needed <= 1'b0; //This line should probably be turned to a 1 if we are to implement "Mikes fairness" schema
4'b0101: new_route_needed <= 1'b0; //This line should probably be turned to a 1 if we are to implement "Mikes fairness" schema
4'b0110: new_route_needed <= 1'b1;
4'b0111: new_route_needed <= 1'b1;
4'b1000: new_route_needed <= 1'b1;
4'b1001: new_route_needed <= 1'b0;
// 4'b1010: new_route_needed <= 1'b0; //this is scary CHECK THIS BEFORE CHIP SHIPS
4'b1010: new_route_needed <= 1'b1; //this is the case where there is a zero length message on the default route that is not being sent this cycle therefore we should let something be locked in, but it doesn't necessarily just the default route. Remember that the default route is the last choice in the priority encoder, but if nothing else is requesting, the default route will be planned and locked in.
//yanqiz change from 0->1
4'b1011: new_route_needed <= 1'b0;
4'b1100: new_route_needed <= 1'b0;
4'b1101: new_route_needed <= 1'b0;
4'b1110: new_route_needed <= 1'b1;
4'b1111: new_route_needed <= 1'b1;
default: new_route_needed <= 1'b1;
//safest choice should never occur
endcase
end
//calculation of planned_temp
//random five input function
always @ (planned_f or tail_current_route or valid_out_internal or default_ready or route_req_all_or_with_planned or route_req_all_but_default)
begin
(* parallel_case *) case({route_req_all_or_with_planned, default_ready, valid_out_internal, tail_current_route, planned_f})
5'b00000: planned_temp <= 1'b0;
5'b00001: planned_temp <= 1'b1;
5'b00010: planned_temp <= 1'b0;
5'b00011: planned_temp <= 1'b1;
5'b00100: planned_temp <= 1'b0; //error what did we just send
5'b00101: planned_temp <= 1'b1;
5'b00110: planned_temp <= 1'b0; //error
5'b00111: planned_temp <= 1'b0;
5'b01000: planned_temp <= 1'b0; //error
5'b01001: planned_temp <= 1'b1;
5'b01010: planned_temp <= 1'b0; //This actually cannot happen
5'b01011: planned_temp <= 1'b1;
5'b01100: planned_temp <= 1'b0; //What did we just send?
5'b01101: planned_temp <= 1'b1;
5'b01110: planned_temp <= 1'b0; //error
5'b01111: planned_temp <= 1'b0; //The default route is
//currently planned but
//is ending this cycle
//and nobody else wants to go
//This is a delayed zero length
//message on the through route
5'b10000: planned_temp <= 1'b1;
5'b10001: planned_temp <= 1'b1;
5'b10010: planned_temp <= 1'b1;
5'b10011: planned_temp <= 1'b1;
5'b10100: planned_temp <= 1'b1;
5'b10101: planned_temp <= 1'b1;
5'b10110: planned_temp <= 1'b1;
5'b10111: planned_temp <= 1'b1;
5'b11000: planned_temp <= 1'b1;
5'b11001: planned_temp <= 1'b1;
5'b11010: planned_temp <= 1'b1;
5'b11011: planned_temp <= 1'b1;
5'b11100: planned_temp <= 1'b1;
5'b11101: planned_temp <= 1'b1;
// 5'b11110: planned_temp <= 1'b0; //This is wrong becasue if
//there is a default
//route zero length message
//that is being sent and
//somebody else wants to send
//on the next cycle
5'b11110: planned_temp <= route_req_all_but_default;
5'b11111: planned_temp <= 1'b1;
default: planned_temp <= 1'b0;
endcase
end
//take care of syncrhonous stuff
always @(posedge clk)
begin
if(reset)
begin
current_route_f <= 3'd0;
planned_f <= 1'd0;
end
else
begin
current_route_f <= current_route_temp;
planned_f <= planned_temp;
end
end
endmodule |
module bp_cce_inst_decode_inst_width_p96_inst_addr_width_p8
(
clk_i,
reset_i,
inst_i,
inst_v_i,
lce_req_v_i,
lce_resp_v_i,
lce_data_resp_v_i,
mem_resp_v_i,
mem_data_resp_v_i,
pending_v_i,
lce_cmd_ready_i,
lce_data_cmd_ready_i,
mem_cmd_ready_i,
mem_data_cmd_ready_i,
decoded_inst_o,
decoded_inst_v_o,
pc_stall_o,
pc_branch_target_o
);
input [95:0] inst_i;
output [127:0] decoded_inst_o;
output [7:0] pc_branch_target_o;
input clk_i;
input reset_i;
input inst_v_i;
input lce_req_v_i;
input lce_resp_v_i;
input lce_data_resp_v_i;
input mem_resp_v_i;
input mem_data_resp_v_i;
input pending_v_i;
input lce_cmd_ready_i;
input lce_data_cmd_ready_i;
input mem_cmd_ready_i;
input mem_data_cmd_ready_i;
output decoded_inst_v_o;
output pc_stall_o;
wire [127:0] decoded_inst_o;
wire [7:0] pc_branch_target_o;
wire decoded_inst_v_o,pc_stall_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,pushq_op,
popq_op,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,wfq_op,stall_op,wfq_q_ready,N42,N43,
N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,
N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,
N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,
N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,
N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,
N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,
N151,N152,N153,N154,N155;
assign N44 = N102 & N99;
assign N45 = inst_i[63] | N99;
assign N47 = N102 | inst_i[62];
assign N49 = inst_i[63] & inst_i[62];
assign N57 = inst_i[94] | inst_i[95];
assign N58 = inst_i[93] | N57;
assign N59 = ~N58;
assign N60 = ~inst_i[93];
assign N61 = N60 | N57;
assign N62 = ~N61;
assign N63 = ~inst_i[95];
assign N64 = ~inst_i[94];
assign N65 = N64 | N63;
assign N66 = inst_i[93] | N65;
assign N67 = ~N66;
assign N68 = inst_i[91] | inst_i[92];
assign N69 = inst_i[90] | N68;
assign N70 = ~N69;
assign N71 = inst_i[94] | N63;
assign N72 = inst_i[93] | N71;
assign N73 = ~N72;
assign N74 = ~inst_i[90];
assign N75 = N74 | N68;
assign N76 = ~N75;
assign N77 = ~inst_i[91];
assign N78 = N77 | inst_i[92];
assign N79 = inst_i[90] | N78;
assign N80 = ~N79;
assign N81 = inst_i[60] | inst_i[61];
assign N82 = inst_i[59] | N81;
assign N83 = ~N82;
assign N84 = ~inst_i[60];
assign N85 = N84 | inst_i[61];
assign N86 = inst_i[59] | N85;
assign N87 = ~N86;
assign N88 = ~inst_i[61];
assign N89 = inst_i[60] | N88;
assign N90 = inst_i[59] | N89;
assign N91 = ~N90;
assign N92 = ~inst_i[59];
assign N93 = N92 | N89;
assign N94 = ~N93;
assign N95 = N92 | N81;
assign N96 = ~N95;
assign N97 = inst_i[62] | inst_i[63];
assign N98 = ~N97;
assign N99 = ~inst_i[62];
assign N100 = N99 | inst_i[63];
assign N101 = ~N100;
assign N102 = ~inst_i[63];
assign N103 = inst_i[62] | N102;
assign N104 = ~N103;
assign N105 = inst_i[62] & inst_i[63];
assign N106 = ~inst_i[76];
assign N107 = ~inst_i[75];
assign N108 = inst_i[78] | inst_i[79];
assign N109 = inst_i[77] | N108;
assign N110 = N106 | N109;
assign N111 = N107 | N110;
assign N112 = ~N111;
assign N113 = inst_i[75] | N110;
assign N114 = ~N113;
assign N115 = inst_i[76] | N109;
assign N116 = N107 | N115;
assign N117 = ~N116;
assign N118 = inst_i[75] | N115;
assign N119 = ~N118;
assign N120 = N64 | inst_i[95];
assign N121 = inst_i[93] | N120;
assign N122 = ~N121;
assign N123 = inst_i[94] & inst_i[95];
assign N124 = inst_i[93] & N123;
assign N125 = N60 | N71;
assign N126 = ~N125;
assign N127 = inst_i[91] & inst_i[92];
assign N128 = inst_i[90] & N127;
assign { N18, N17, N16 } = (N0)? inst_i[92:90] :
(N1)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N73;
assign N1 = N72;
assign { N21, N20, N19 } = (N2)? inst_i[92:90] :
(N3)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N2 = N126;
assign N3 = N125;
assign decoded_inst_v_o = (N4)? 1'b0 :
(N14)? inst_v_i : 1'b0;
assign N4 = N13;
assign decoded_inst_o = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N14)? { inst_i[92:59], N15, inst_i[58:29], N18, N17, N16, N73, N21, N20, N19, N126, inst_i[28:20], inst_i[61:59], inst_i[19:19], N122, N59, N22, N23, N24, N25, N26, inst_i[18:13], N27, N28, N29, inst_i[12:0], N39, N40, N41, inst_i[12:12], N30, N31, N32, N33, N34, N35, N36, N37, N38 } : 1'b0;
assign N54 = (N5)? N50 :
(N6)? N51 :
(N7)? N52 :
(N8)? N53 : 1'b0;
assign N5 = N44;
assign N6 = N46;
assign N7 = N48;
assign N8 = N49;
assign N55 = (N9)? N54 :
(N10)? N42 : 1'b0;
assign N9 = pushq_op;
assign N10 = N43;
assign pc_stall_o = (N11)? 1'b0 :
(N12)? N55 : 1'b0;
assign N11 = reset_i;
assign N12 = N56;
assign pc_branch_target_o = (N11)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N12)? inst_i[66:59] : 1'b0;
assign pushq_op = N124 & N76;
assign popq_op = N124 & N80;
assign N13 = reset_i | N129;
assign N129 = ~inst_v_i;
assign N14 = ~N13;
assign N15 = N59 | N62;
assign N22 = N112 & N130;
assign N130 = N122 | N59;
assign N23 = N114 & N131;
assign N131 = N122 | N59;
assign N24 = N117 & N132;
assign N132 = N122 | N59;
assign N25 = N119 & N133;
assign N133 = N122 | N59;
assign N26 = N135 | N25;
assign N135 = N134 | N24;
assign N134 = N22 | N23;
assign N27 = N67 & N70;
assign N28 = N73 & N76;
assign N29 = N73 & N80;
assign N30 = popq_op & N83;
assign N31 = popq_op & N91;
assign N32 = popq_op & N94;
assign N33 = popq_op & N96;
assign N34 = popq_op & N87;
assign N35 = N136 & N98;
assign N136 = lce_cmd_ready_i & pushq_op;
assign N36 = pushq_op & N101;
assign N37 = N137 & N104;
assign N137 = mem_cmd_ready_i & pushq_op;
assign N38 = N138 & N105;
assign N138 = mem_data_cmd_ready_i & pushq_op;
assign N39 = popq_op & N83;
assign N40 = popq_op & N87;
assign N41 = popq_op & N139;
assign N139 = N83 | N87;
assign wfq_op = N124 & N70;
assign stall_op = N67 & N128;
assign wfq_q_ready = N148 | N149;
assign N148 = N146 | N147;
assign N146 = N144 | N145;
assign N144 = N142 | N143;
assign N142 = N140 | N141;
assign N140 = inst_i[64] & lce_req_v_i;
assign N141 = inst_i[63] & lce_resp_v_i;
assign N143 = inst_i[62] & lce_data_resp_v_i;
assign N145 = inst_i[61] & mem_resp_v_i;
assign N147 = inst_i[60] & mem_data_resp_v_i;
assign N149 = inst_i[59] & pending_v_i;
assign N42 = stall_op | N151;
assign N151 = wfq_op & N150;
assign N150 = ~wfq_q_ready;
assign N43 = ~pushq_op;
assign N46 = ~N45;
assign N48 = ~N47;
assign N50 = N42 | N152;
assign N152 = ~lce_cmd_ready_i;
assign N51 = N42 | N153;
assign N153 = ~lce_data_cmd_ready_i;
assign N52 = N42 | N154;
assign N154 = ~mem_cmd_ready_i;
assign N53 = N42 | N155;
assign N155 = ~mem_data_cmd_ready_i;
assign N56 = ~reset_i;
endmodule |
module bsg_mux_one_hot_width_p131_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [523:0] data_i;
input [3:0] sel_one_hot_i;
output [130:0] data_o;
wire [130:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,N228,N229,
N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,N244,N245,
N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,N258,N259,N260,N261;
wire [523:0] data_masked;
assign data_masked[130] = data_i[130] & sel_one_hot_i[0];
assign data_masked[129] = data_i[129] & sel_one_hot_i[0];
assign data_masked[128] = data_i[128] & sel_one_hot_i[0];
assign data_masked[127] = data_i[127] & sel_one_hot_i[0];
assign data_masked[126] = data_i[126] & sel_one_hot_i[0];
assign data_masked[125] = data_i[125] & sel_one_hot_i[0];
assign data_masked[124] = data_i[124] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[0];
assign data_masked[122] = data_i[122] & sel_one_hot_i[0];
assign data_masked[121] = data_i[121] & sel_one_hot_i[0];
assign data_masked[120] = data_i[120] & sel_one_hot_i[0];
assign data_masked[119] = data_i[119] & sel_one_hot_i[0];
assign data_masked[118] = data_i[118] & sel_one_hot_i[0];
assign data_masked[117] = data_i[117] & sel_one_hot_i[0];
assign data_masked[116] = data_i[116] & sel_one_hot_i[0];
assign data_masked[115] = data_i[115] & sel_one_hot_i[0];
assign data_masked[114] = data_i[114] & sel_one_hot_i[0];
assign data_masked[113] = data_i[113] & sel_one_hot_i[0];
assign data_masked[112] = data_i[112] & sel_one_hot_i[0];
assign data_masked[111] = data_i[111] & sel_one_hot_i[0];
assign data_masked[110] = data_i[110] & sel_one_hot_i[0];
assign data_masked[109] = data_i[109] & sel_one_hot_i[0];
assign data_masked[108] = data_i[108] & sel_one_hot_i[0];
assign data_masked[107] = data_i[107] & sel_one_hot_i[0];
assign data_masked[106] = data_i[106] & sel_one_hot_i[0];
assign data_masked[105] = data_i[105] & sel_one_hot_i[0];
assign data_masked[104] = data_i[104] & sel_one_hot_i[0];
assign data_masked[103] = data_i[103] & sel_one_hot_i[0];
assign data_masked[102] = data_i[102] & sel_one_hot_i[0];
assign data_masked[101] = data_i[101] & sel_one_hot_i[0];
assign data_masked[100] = data_i[100] & sel_one_hot_i[0];
assign data_masked[99] = data_i[99] & sel_one_hot_i[0];
assign data_masked[98] = data_i[98] & sel_one_hot_i[0];
assign data_masked[97] = data_i[97] & sel_one_hot_i[0];
assign data_masked[96] = data_i[96] & sel_one_hot_i[0];
assign data_masked[95] = data_i[95] & sel_one_hot_i[0];
assign data_masked[94] = data_i[94] & sel_one_hot_i[0];
assign data_masked[93] = data_i[93] & sel_one_hot_i[0];
assign data_masked[92] = data_i[92] & sel_one_hot_i[0];
assign data_masked[91] = data_i[91] & sel_one_hot_i[0];
assign data_masked[90] = data_i[90] & sel_one_hot_i[0];
assign data_masked[89] = data_i[89] & sel_one_hot_i[0];
assign data_masked[88] = data_i[88] & sel_one_hot_i[0];
assign data_masked[87] = data_i[87] & sel_one_hot_i[0];
assign data_masked[86] = data_i[86] & sel_one_hot_i[0];
assign data_masked[85] = data_i[85] & sel_one_hot_i[0];
assign data_masked[84] = data_i[84] & sel_one_hot_i[0];
assign data_masked[83] = data_i[83] & sel_one_hot_i[0];
assign data_masked[82] = data_i[82] & sel_one_hot_i[0];
assign data_masked[81] = data_i[81] & sel_one_hot_i[0];
assign data_masked[80] = data_i[80] & sel_one_hot_i[0];
assign data_masked[79] = data_i[79] & sel_one_hot_i[0];
assign data_masked[78] = data_i[78] & sel_one_hot_i[0];
assign data_masked[77] = data_i[77] & sel_one_hot_i[0];
assign data_masked[76] = data_i[76] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[261] = data_i[261] & sel_one_hot_i[1];
assign data_masked[260] = data_i[260] & sel_one_hot_i[1];
assign data_masked[259] = data_i[259] & sel_one_hot_i[1];
assign data_masked[258] = data_i[258] & sel_one_hot_i[1];
assign data_masked[257] = data_i[257] & sel_one_hot_i[1];
assign data_masked[256] = data_i[256] & sel_one_hot_i[1];
assign data_masked[255] = data_i[255] & sel_one_hot_i[1];
assign data_masked[254] = data_i[254] & sel_one_hot_i[1];
assign data_masked[253] = data_i[253] & sel_one_hot_i[1];
assign data_masked[252] = data_i[252] & sel_one_hot_i[1];
assign data_masked[251] = data_i[251] & sel_one_hot_i[1];
assign data_masked[250] = data_i[250] & sel_one_hot_i[1];
assign data_masked[249] = data_i[249] & sel_one_hot_i[1];
assign data_masked[248] = data_i[248] & sel_one_hot_i[1];
assign data_masked[247] = data_i[247] & sel_one_hot_i[1];
assign data_masked[246] = data_i[246] & sel_one_hot_i[1];
assign data_masked[245] = data_i[245] & sel_one_hot_i[1];
assign data_masked[244] = data_i[244] & sel_one_hot_i[1];
assign data_masked[243] = data_i[243] & sel_one_hot_i[1];
assign data_masked[242] = data_i[242] & sel_one_hot_i[1];
assign data_masked[241] = data_i[241] & sel_one_hot_i[1];
assign data_masked[240] = data_i[240] & sel_one_hot_i[1];
assign data_masked[239] = data_i[239] & sel_one_hot_i[1];
assign data_masked[238] = data_i[238] & sel_one_hot_i[1];
assign data_masked[237] = data_i[237] & sel_one_hot_i[1];
assign data_masked[236] = data_i[236] & sel_one_hot_i[1];
assign data_masked[235] = data_i[235] & sel_one_hot_i[1];
assign data_masked[234] = data_i[234] & sel_one_hot_i[1];
assign data_masked[233] = data_i[233] & sel_one_hot_i[1];
assign data_masked[232] = data_i[232] & sel_one_hot_i[1];
assign data_masked[231] = data_i[231] & sel_one_hot_i[1];
assign data_masked[230] = data_i[230] & sel_one_hot_i[1];
assign data_masked[229] = data_i[229] & sel_one_hot_i[1];
assign data_masked[228] = data_i[228] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[1];
assign data_masked[226] = data_i[226] & sel_one_hot_i[1];
assign data_masked[225] = data_i[225] & sel_one_hot_i[1];
assign data_masked[224] = data_i[224] & sel_one_hot_i[1];
assign data_masked[223] = data_i[223] & sel_one_hot_i[1];
assign data_masked[222] = data_i[222] & sel_one_hot_i[1];
assign data_masked[221] = data_i[221] & sel_one_hot_i[1];
assign data_masked[220] = data_i[220] & sel_one_hot_i[1];
assign data_masked[219] = data_i[219] & sel_one_hot_i[1];
assign data_masked[218] = data_i[218] & sel_one_hot_i[1];
assign data_masked[217] = data_i[217] & sel_one_hot_i[1];
assign data_masked[216] = data_i[216] & sel_one_hot_i[1];
assign data_masked[215] = data_i[215] & sel_one_hot_i[1];
assign data_masked[214] = data_i[214] & sel_one_hot_i[1];
assign data_masked[213] = data_i[213] & sel_one_hot_i[1];
assign data_masked[212] = data_i[212] & sel_one_hot_i[1];
assign data_masked[211] = data_i[211] & sel_one_hot_i[1];
assign data_masked[210] = data_i[210] & sel_one_hot_i[1];
assign data_masked[209] = data_i[209] & sel_one_hot_i[1];
assign data_masked[208] = data_i[208] & sel_one_hot_i[1];
assign data_masked[207] = data_i[207] & sel_one_hot_i[1];
assign data_masked[206] = data_i[206] & sel_one_hot_i[1];
assign data_masked[205] = data_i[205] & sel_one_hot_i[1];
assign data_masked[204] = data_i[204] & sel_one_hot_i[1];
assign data_masked[203] = data_i[203] & sel_one_hot_i[1];
assign data_masked[202] = data_i[202] & sel_one_hot_i[1];
assign data_masked[201] = data_i[201] & sel_one_hot_i[1];
assign data_masked[200] = data_i[200] & sel_one_hot_i[1];
assign data_masked[199] = data_i[199] & sel_one_hot_i[1];
assign data_masked[198] = data_i[198] & sel_one_hot_i[1];
assign data_masked[197] = data_i[197] & sel_one_hot_i[1];
assign data_masked[196] = data_i[196] & sel_one_hot_i[1];
assign data_masked[195] = data_i[195] & sel_one_hot_i[1];
assign data_masked[194] = data_i[194] & sel_one_hot_i[1];
assign data_masked[193] = data_i[193] & sel_one_hot_i[1];
assign data_masked[192] = data_i[192] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[1];
assign data_masked[190] = data_i[190] & sel_one_hot_i[1];
assign data_masked[189] = data_i[189] & sel_one_hot_i[1];
assign data_masked[188] = data_i[188] & sel_one_hot_i[1];
assign data_masked[187] = data_i[187] & sel_one_hot_i[1];
assign data_masked[186] = data_i[186] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[1];
assign data_masked[184] = data_i[184] & sel_one_hot_i[1];
assign data_masked[183] = data_i[183] & sel_one_hot_i[1];
assign data_masked[182] = data_i[182] & sel_one_hot_i[1];
assign data_masked[181] = data_i[181] & sel_one_hot_i[1];
assign data_masked[180] = data_i[180] & sel_one_hot_i[1];
assign data_masked[179] = data_i[179] & sel_one_hot_i[1];
assign data_masked[178] = data_i[178] & sel_one_hot_i[1];
assign data_masked[177] = data_i[177] & sel_one_hot_i[1];
assign data_masked[176] = data_i[176] & sel_one_hot_i[1];
assign data_masked[175] = data_i[175] & sel_one_hot_i[1];
assign data_masked[174] = data_i[174] & sel_one_hot_i[1];
assign data_masked[173] = data_i[173] & sel_one_hot_i[1];
assign data_masked[172] = data_i[172] & sel_one_hot_i[1];
assign data_masked[171] = data_i[171] & sel_one_hot_i[1];
assign data_masked[170] = data_i[170] & sel_one_hot_i[1];
assign data_masked[169] = data_i[169] & sel_one_hot_i[1];
assign data_masked[168] = data_i[168] & sel_one_hot_i[1];
assign data_masked[167] = data_i[167] & sel_one_hot_i[1];
assign data_masked[166] = data_i[166] & sel_one_hot_i[1];
assign data_masked[165] = data_i[165] & sel_one_hot_i[1];
assign data_masked[164] = data_i[164] & sel_one_hot_i[1];
assign data_masked[163] = data_i[163] & sel_one_hot_i[1];
assign data_masked[162] = data_i[162] & sel_one_hot_i[1];
assign data_masked[161] = data_i[161] & sel_one_hot_i[1];
assign data_masked[160] = data_i[160] & sel_one_hot_i[1];
assign data_masked[159] = data_i[159] & sel_one_hot_i[1];
assign data_masked[158] = data_i[158] & sel_one_hot_i[1];
assign data_masked[157] = data_i[157] & sel_one_hot_i[1];
assign data_masked[156] = data_i[156] & sel_one_hot_i[1];
assign data_masked[155] = data_i[155] & sel_one_hot_i[1];
assign data_masked[154] = data_i[154] & sel_one_hot_i[1];
assign data_masked[153] = data_i[153] & sel_one_hot_i[1];
assign data_masked[152] = data_i[152] & sel_one_hot_i[1];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[392] = data_i[392] & sel_one_hot_i[2];
assign data_masked[391] = data_i[391] & sel_one_hot_i[2];
assign data_masked[390] = data_i[390] & sel_one_hot_i[2];
assign data_masked[389] = data_i[389] & sel_one_hot_i[2];
assign data_masked[388] = data_i[388] & sel_one_hot_i[2];
assign data_masked[387] = data_i[387] & sel_one_hot_i[2];
assign data_masked[386] = data_i[386] & sel_one_hot_i[2];
assign data_masked[385] = data_i[385] & sel_one_hot_i[2];
assign data_masked[384] = data_i[384] & sel_one_hot_i[2];
assign data_masked[383] = data_i[383] & sel_one_hot_i[2];
assign data_masked[382] = data_i[382] & sel_one_hot_i[2];
assign data_masked[381] = data_i[381] & sel_one_hot_i[2];
assign data_masked[380] = data_i[380] & sel_one_hot_i[2];
assign data_masked[379] = data_i[379] & sel_one_hot_i[2];
assign data_masked[378] = data_i[378] & sel_one_hot_i[2];
assign data_masked[377] = data_i[377] & sel_one_hot_i[2];
assign data_masked[376] = data_i[376] & sel_one_hot_i[2];
assign data_masked[375] = data_i[375] & sel_one_hot_i[2];
assign data_masked[374] = data_i[374] & sel_one_hot_i[2];
assign data_masked[373] = data_i[373] & sel_one_hot_i[2];
assign data_masked[372] = data_i[372] & sel_one_hot_i[2];
assign data_masked[371] = data_i[371] & sel_one_hot_i[2];
assign data_masked[370] = data_i[370] & sel_one_hot_i[2];
assign data_masked[369] = data_i[369] & sel_one_hot_i[2];
assign data_masked[368] = data_i[368] & sel_one_hot_i[2];
assign data_masked[367] = data_i[367] & sel_one_hot_i[2];
assign data_masked[366] = data_i[366] & sel_one_hot_i[2];
assign data_masked[365] = data_i[365] & sel_one_hot_i[2];
assign data_masked[364] = data_i[364] & sel_one_hot_i[2];
assign data_masked[363] = data_i[363] & sel_one_hot_i[2];
assign data_masked[362] = data_i[362] & sel_one_hot_i[2];
assign data_masked[361] = data_i[361] & sel_one_hot_i[2];
assign data_masked[360] = data_i[360] & sel_one_hot_i[2];
assign data_masked[359] = data_i[359] & sel_one_hot_i[2];
assign data_masked[358] = data_i[358] & sel_one_hot_i[2];
assign data_masked[357] = data_i[357] & sel_one_hot_i[2];
assign data_masked[356] = data_i[356] & sel_one_hot_i[2];
assign data_masked[355] = data_i[355] & sel_one_hot_i[2];
assign data_masked[354] = data_i[354] & sel_one_hot_i[2];
assign data_masked[353] = data_i[353] & sel_one_hot_i[2];
assign data_masked[352] = data_i[352] & sel_one_hot_i[2];
assign data_masked[351] = data_i[351] & sel_one_hot_i[2];
assign data_masked[350] = data_i[350] & sel_one_hot_i[2];
assign data_masked[349] = data_i[349] & sel_one_hot_i[2];
assign data_masked[348] = data_i[348] & sel_one_hot_i[2];
assign data_masked[347] = data_i[347] & sel_one_hot_i[2];
assign data_masked[346] = data_i[346] & sel_one_hot_i[2];
assign data_masked[345] = data_i[345] & sel_one_hot_i[2];
assign data_masked[344] = data_i[344] & sel_one_hot_i[2];
assign data_masked[343] = data_i[343] & sel_one_hot_i[2];
assign data_masked[342] = data_i[342] & sel_one_hot_i[2];
assign data_masked[341] = data_i[341] & sel_one_hot_i[2];
assign data_masked[340] = data_i[340] & sel_one_hot_i[2];
assign data_masked[339] = data_i[339] & sel_one_hot_i[2];
assign data_masked[338] = data_i[338] & sel_one_hot_i[2];
assign data_masked[337] = data_i[337] & sel_one_hot_i[2];
assign data_masked[336] = data_i[336] & sel_one_hot_i[2];
assign data_masked[335] = data_i[335] & sel_one_hot_i[2];
assign data_masked[334] = data_i[334] & sel_one_hot_i[2];
assign data_masked[333] = data_i[333] & sel_one_hot_i[2];
assign data_masked[332] = data_i[332] & sel_one_hot_i[2];
assign data_masked[331] = data_i[331] & sel_one_hot_i[2];
assign data_masked[330] = data_i[330] & sel_one_hot_i[2];
assign data_masked[329] = data_i[329] & sel_one_hot_i[2];
assign data_masked[328] = data_i[328] & sel_one_hot_i[2];
assign data_masked[327] = data_i[327] & sel_one_hot_i[2];
assign data_masked[326] = data_i[326] & sel_one_hot_i[2];
assign data_masked[325] = data_i[325] & sel_one_hot_i[2];
assign data_masked[324] = data_i[324] & sel_one_hot_i[2];
assign data_masked[323] = data_i[323] & sel_one_hot_i[2];
assign data_masked[322] = data_i[322] & sel_one_hot_i[2];
assign data_masked[321] = data_i[321] & sel_one_hot_i[2];
assign data_masked[320] = data_i[320] & sel_one_hot_i[2];
assign data_masked[319] = data_i[319] & sel_one_hot_i[2];
assign data_masked[318] = data_i[318] & sel_one_hot_i[2];
assign data_masked[317] = data_i[317] & sel_one_hot_i[2];
assign data_masked[316] = data_i[316] & sel_one_hot_i[2];
assign data_masked[315] = data_i[315] & sel_one_hot_i[2];
assign data_masked[314] = data_i[314] & sel_one_hot_i[2];
assign data_masked[313] = data_i[313] & sel_one_hot_i[2];
assign data_masked[312] = data_i[312] & sel_one_hot_i[2];
assign data_masked[311] = data_i[311] & sel_one_hot_i[2];
assign data_masked[310] = data_i[310] & sel_one_hot_i[2];
assign data_masked[309] = data_i[309] & sel_one_hot_i[2];
assign data_masked[308] = data_i[308] & sel_one_hot_i[2];
assign data_masked[307] = data_i[307] & sel_one_hot_i[2];
assign data_masked[306] = data_i[306] & sel_one_hot_i[2];
assign data_masked[305] = data_i[305] & sel_one_hot_i[2];
assign data_masked[304] = data_i[304] & sel_one_hot_i[2];
assign data_masked[303] = data_i[303] & sel_one_hot_i[2];
assign data_masked[302] = data_i[302] & sel_one_hot_i[2];
assign data_masked[301] = data_i[301] & sel_one_hot_i[2];
assign data_masked[300] = data_i[300] & sel_one_hot_i[2];
assign data_masked[299] = data_i[299] & sel_one_hot_i[2];
assign data_masked[298] = data_i[298] & sel_one_hot_i[2];
assign data_masked[297] = data_i[297] & sel_one_hot_i[2];
assign data_masked[296] = data_i[296] & sel_one_hot_i[2];
assign data_masked[295] = data_i[295] & sel_one_hot_i[2];
assign data_masked[294] = data_i[294] & sel_one_hot_i[2];
assign data_masked[293] = data_i[293] & sel_one_hot_i[2];
assign data_masked[292] = data_i[292] & sel_one_hot_i[2];
assign data_masked[291] = data_i[291] & sel_one_hot_i[2];
assign data_masked[290] = data_i[290] & sel_one_hot_i[2];
assign data_masked[289] = data_i[289] & sel_one_hot_i[2];
assign data_masked[288] = data_i[288] & sel_one_hot_i[2];
assign data_masked[287] = data_i[287] & sel_one_hot_i[2];
assign data_masked[286] = data_i[286] & sel_one_hot_i[2];
assign data_masked[285] = data_i[285] & sel_one_hot_i[2];
assign data_masked[284] = data_i[284] & sel_one_hot_i[2];
assign data_masked[283] = data_i[283] & sel_one_hot_i[2];
assign data_masked[282] = data_i[282] & sel_one_hot_i[2];
assign data_masked[281] = data_i[281] & sel_one_hot_i[2];
assign data_masked[280] = data_i[280] & sel_one_hot_i[2];
assign data_masked[279] = data_i[279] & sel_one_hot_i[2];
assign data_masked[278] = data_i[278] & sel_one_hot_i[2];
assign data_masked[277] = data_i[277] & sel_one_hot_i[2];
assign data_masked[276] = data_i[276] & sel_one_hot_i[2];
assign data_masked[275] = data_i[275] & sel_one_hot_i[2];
assign data_masked[274] = data_i[274] & sel_one_hot_i[2];
assign data_masked[273] = data_i[273] & sel_one_hot_i[2];
assign data_masked[272] = data_i[272] & sel_one_hot_i[2];
assign data_masked[271] = data_i[271] & sel_one_hot_i[2];
assign data_masked[270] = data_i[270] & sel_one_hot_i[2];
assign data_masked[269] = data_i[269] & sel_one_hot_i[2];
assign data_masked[268] = data_i[268] & sel_one_hot_i[2];
assign data_masked[267] = data_i[267] & sel_one_hot_i[2];
assign data_masked[266] = data_i[266] & sel_one_hot_i[2];
assign data_masked[265] = data_i[265] & sel_one_hot_i[2];
assign data_masked[264] = data_i[264] & sel_one_hot_i[2];
assign data_masked[263] = data_i[263] & sel_one_hot_i[2];
assign data_masked[262] = data_i[262] & sel_one_hot_i[2];
assign data_masked[523] = data_i[523] & sel_one_hot_i[3];
assign data_masked[522] = data_i[522] & sel_one_hot_i[3];
assign data_masked[521] = data_i[521] & sel_one_hot_i[3];
assign data_masked[520] = data_i[520] & sel_one_hot_i[3];
assign data_masked[519] = data_i[519] & sel_one_hot_i[3];
assign data_masked[518] = data_i[518] & sel_one_hot_i[3];
assign data_masked[517] = data_i[517] & sel_one_hot_i[3];
assign data_masked[516] = data_i[516] & sel_one_hot_i[3];
assign data_masked[515] = data_i[515] & sel_one_hot_i[3];
assign data_masked[514] = data_i[514] & sel_one_hot_i[3];
assign data_masked[513] = data_i[513] & sel_one_hot_i[3];
assign data_masked[512] = data_i[512] & sel_one_hot_i[3];
assign data_masked[511] = data_i[511] & sel_one_hot_i[3];
assign data_masked[510] = data_i[510] & sel_one_hot_i[3];
assign data_masked[509] = data_i[509] & sel_one_hot_i[3];
assign data_masked[508] = data_i[508] & sel_one_hot_i[3];
assign data_masked[507] = data_i[507] & sel_one_hot_i[3];
assign data_masked[506] = data_i[506] & sel_one_hot_i[3];
assign data_masked[505] = data_i[505] & sel_one_hot_i[3];
assign data_masked[504] = data_i[504] & sel_one_hot_i[3];
assign data_masked[503] = data_i[503] & sel_one_hot_i[3];
assign data_masked[502] = data_i[502] & sel_one_hot_i[3];
assign data_masked[501] = data_i[501] & sel_one_hot_i[3];
assign data_masked[500] = data_i[500] & sel_one_hot_i[3];
assign data_masked[499] = data_i[499] & sel_one_hot_i[3];
assign data_masked[498] = data_i[498] & sel_one_hot_i[3];
assign data_masked[497] = data_i[497] & sel_one_hot_i[3];
assign data_masked[496] = data_i[496] & sel_one_hot_i[3];
assign data_masked[495] = data_i[495] & sel_one_hot_i[3];
assign data_masked[494] = data_i[494] & sel_one_hot_i[3];
assign data_masked[493] = data_i[493] & sel_one_hot_i[3];
assign data_masked[492] = data_i[492] & sel_one_hot_i[3];
assign data_masked[491] = data_i[491] & sel_one_hot_i[3];
assign data_masked[490] = data_i[490] & sel_one_hot_i[3];
assign data_masked[489] = data_i[489] & sel_one_hot_i[3];
assign data_masked[488] = data_i[488] & sel_one_hot_i[3];
assign data_masked[487] = data_i[487] & sel_one_hot_i[3];
assign data_masked[486] = data_i[486] & sel_one_hot_i[3];
assign data_masked[485] = data_i[485] & sel_one_hot_i[3];
assign data_masked[484] = data_i[484] & sel_one_hot_i[3];
assign data_masked[483] = data_i[483] & sel_one_hot_i[3];
assign data_masked[482] = data_i[482] & sel_one_hot_i[3];
assign data_masked[481] = data_i[481] & sel_one_hot_i[3];
assign data_masked[480] = data_i[480] & sel_one_hot_i[3];
assign data_masked[479] = data_i[479] & sel_one_hot_i[3];
assign data_masked[478] = data_i[478] & sel_one_hot_i[3];
assign data_masked[477] = data_i[477] & sel_one_hot_i[3];
assign data_masked[476] = data_i[476] & sel_one_hot_i[3];
assign data_masked[475] = data_i[475] & sel_one_hot_i[3];
assign data_masked[474] = data_i[474] & sel_one_hot_i[3];
assign data_masked[473] = data_i[473] & sel_one_hot_i[3];
assign data_masked[472] = data_i[472] & sel_one_hot_i[3];
assign data_masked[471] = data_i[471] & sel_one_hot_i[3];
assign data_masked[470] = data_i[470] & sel_one_hot_i[3];
assign data_masked[469] = data_i[469] & sel_one_hot_i[3];
assign data_masked[468] = data_i[468] & sel_one_hot_i[3];
assign data_masked[467] = data_i[467] & sel_one_hot_i[3];
assign data_masked[466] = data_i[466] & sel_one_hot_i[3];
assign data_masked[465] = data_i[465] & sel_one_hot_i[3];
assign data_masked[464] = data_i[464] & sel_one_hot_i[3];
assign data_masked[463] = data_i[463] & sel_one_hot_i[3];
assign data_masked[462] = data_i[462] & sel_one_hot_i[3];
assign data_masked[461] = data_i[461] & sel_one_hot_i[3];
assign data_masked[460] = data_i[460] & sel_one_hot_i[3];
assign data_masked[459] = data_i[459] & sel_one_hot_i[3];
assign data_masked[458] = data_i[458] & sel_one_hot_i[3];
assign data_masked[457] = data_i[457] & sel_one_hot_i[3];
assign data_masked[456] = data_i[456] & sel_one_hot_i[3];
assign data_masked[455] = data_i[455] & sel_one_hot_i[3];
assign data_masked[454] = data_i[454] & sel_one_hot_i[3];
assign data_masked[453] = data_i[453] & sel_one_hot_i[3];
assign data_masked[452] = data_i[452] & sel_one_hot_i[3];
assign data_masked[451] = data_i[451] & sel_one_hot_i[3];
assign data_masked[450] = data_i[450] & sel_one_hot_i[3];
assign data_masked[449] = data_i[449] & sel_one_hot_i[3];
assign data_masked[448] = data_i[448] & sel_one_hot_i[3];
assign data_masked[447] = data_i[447] & sel_one_hot_i[3];
assign data_masked[446] = data_i[446] & sel_one_hot_i[3];
assign data_masked[445] = data_i[445] & sel_one_hot_i[3];
assign data_masked[444] = data_i[444] & sel_one_hot_i[3];
assign data_masked[443] = data_i[443] & sel_one_hot_i[3];
assign data_masked[442] = data_i[442] & sel_one_hot_i[3];
assign data_masked[441] = data_i[441] & sel_one_hot_i[3];
assign data_masked[440] = data_i[440] & sel_one_hot_i[3];
assign data_masked[439] = data_i[439] & sel_one_hot_i[3];
assign data_masked[438] = data_i[438] & sel_one_hot_i[3];
assign data_masked[437] = data_i[437] & sel_one_hot_i[3];
assign data_masked[436] = data_i[436] & sel_one_hot_i[3];
assign data_masked[435] = data_i[435] & sel_one_hot_i[3];
assign data_masked[434] = data_i[434] & sel_one_hot_i[3];
assign data_masked[433] = data_i[433] & sel_one_hot_i[3];
assign data_masked[432] = data_i[432] & sel_one_hot_i[3];
assign data_masked[431] = data_i[431] & sel_one_hot_i[3];
assign data_masked[430] = data_i[430] & sel_one_hot_i[3];
assign data_masked[429] = data_i[429] & sel_one_hot_i[3];
assign data_masked[428] = data_i[428] & sel_one_hot_i[3];
assign data_masked[427] = data_i[427] & sel_one_hot_i[3];
assign data_masked[426] = data_i[426] & sel_one_hot_i[3];
assign data_masked[425] = data_i[425] & sel_one_hot_i[3];
assign data_masked[424] = data_i[424] & sel_one_hot_i[3];
assign data_masked[423] = data_i[423] & sel_one_hot_i[3];
assign data_masked[422] = data_i[422] & sel_one_hot_i[3];
assign data_masked[421] = data_i[421] & sel_one_hot_i[3];
assign data_masked[420] = data_i[420] & sel_one_hot_i[3];
assign data_masked[419] = data_i[419] & sel_one_hot_i[3];
assign data_masked[418] = data_i[418] & sel_one_hot_i[3];
assign data_masked[417] = data_i[417] & sel_one_hot_i[3];
assign data_masked[416] = data_i[416] & sel_one_hot_i[3];
assign data_masked[415] = data_i[415] & sel_one_hot_i[3];
assign data_masked[414] = data_i[414] & sel_one_hot_i[3];
assign data_masked[413] = data_i[413] & sel_one_hot_i[3];
assign data_masked[412] = data_i[412] & sel_one_hot_i[3];
assign data_masked[411] = data_i[411] & sel_one_hot_i[3];
assign data_masked[410] = data_i[410] & sel_one_hot_i[3];
assign data_masked[409] = data_i[409] & sel_one_hot_i[3];
assign data_masked[408] = data_i[408] & sel_one_hot_i[3];
assign data_masked[407] = data_i[407] & sel_one_hot_i[3];
assign data_masked[406] = data_i[406] & sel_one_hot_i[3];
assign data_masked[405] = data_i[405] & sel_one_hot_i[3];
assign data_masked[404] = data_i[404] & sel_one_hot_i[3];
assign data_masked[403] = data_i[403] & sel_one_hot_i[3];
assign data_masked[402] = data_i[402] & sel_one_hot_i[3];
assign data_masked[401] = data_i[401] & sel_one_hot_i[3];
assign data_masked[400] = data_i[400] & sel_one_hot_i[3];
assign data_masked[399] = data_i[399] & sel_one_hot_i[3];
assign data_masked[398] = data_i[398] & sel_one_hot_i[3];
assign data_masked[397] = data_i[397] & sel_one_hot_i[3];
assign data_masked[396] = data_i[396] & sel_one_hot_i[3];
assign data_masked[395] = data_i[395] & sel_one_hot_i[3];
assign data_masked[394] = data_i[394] & sel_one_hot_i[3];
assign data_masked[393] = data_i[393] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[131];
assign N0 = data_masked[393] | data_masked[262];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[132];
assign N2 = data_masked[394] | data_masked[263];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[133];
assign N4 = data_masked[395] | data_masked[264];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[134];
assign N6 = data_masked[396] | data_masked[265];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[135];
assign N8 = data_masked[397] | data_masked[266];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[136];
assign N10 = data_masked[398] | data_masked[267];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[137];
assign N12 = data_masked[399] | data_masked[268];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[138];
assign N14 = data_masked[400] | data_masked[269];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[139];
assign N16 = data_masked[401] | data_masked[270];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[140];
assign N18 = data_masked[402] | data_masked[271];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[141];
assign N20 = data_masked[403] | data_masked[272];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[142];
assign N22 = data_masked[404] | data_masked[273];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[143];
assign N24 = data_masked[405] | data_masked[274];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[144];
assign N26 = data_masked[406] | data_masked[275];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[145];
assign N28 = data_masked[407] | data_masked[276];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[146];
assign N30 = data_masked[408] | data_masked[277];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[147];
assign N32 = data_masked[409] | data_masked[278];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[148];
assign N34 = data_masked[410] | data_masked[279];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[149];
assign N36 = data_masked[411] | data_masked[280];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[150];
assign N38 = data_masked[412] | data_masked[281];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[151];
assign N40 = data_masked[413] | data_masked[282];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[152];
assign N42 = data_masked[414] | data_masked[283];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[153];
assign N44 = data_masked[415] | data_masked[284];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[154];
assign N46 = data_masked[416] | data_masked[285];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[155];
assign N48 = data_masked[417] | data_masked[286];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[156];
assign N50 = data_masked[418] | data_masked[287];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[157];
assign N52 = data_masked[419] | data_masked[288];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[158];
assign N54 = data_masked[420] | data_masked[289];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[159];
assign N56 = data_masked[421] | data_masked[290];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[160];
assign N58 = data_masked[422] | data_masked[291];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[161];
assign N60 = data_masked[423] | data_masked[292];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[162];
assign N62 = data_masked[424] | data_masked[293];
assign data_o[32] = N65 | data_masked[32];
assign N65 = N64 | data_masked[163];
assign N64 = data_masked[425] | data_masked[294];
assign data_o[33] = N67 | data_masked[33];
assign N67 = N66 | data_masked[164];
assign N66 = data_masked[426] | data_masked[295];
assign data_o[34] = N69 | data_masked[34];
assign N69 = N68 | data_masked[165];
assign N68 = data_masked[427] | data_masked[296];
assign data_o[35] = N71 | data_masked[35];
assign N71 = N70 | data_masked[166];
assign N70 = data_masked[428] | data_masked[297];
assign data_o[36] = N73 | data_masked[36];
assign N73 = N72 | data_masked[167];
assign N72 = data_masked[429] | data_masked[298];
assign data_o[37] = N75 | data_masked[37];
assign N75 = N74 | data_masked[168];
assign N74 = data_masked[430] | data_masked[299];
assign data_o[38] = N77 | data_masked[38];
assign N77 = N76 | data_masked[169];
assign N76 = data_masked[431] | data_masked[300];
assign data_o[39] = N79 | data_masked[39];
assign N79 = N78 | data_masked[170];
assign N78 = data_masked[432] | data_masked[301];
assign data_o[40] = N81 | data_masked[40];
assign N81 = N80 | data_masked[171];
assign N80 = data_masked[433] | data_masked[302];
assign data_o[41] = N83 | data_masked[41];
assign N83 = N82 | data_masked[172];
assign N82 = data_masked[434] | data_masked[303];
assign data_o[42] = N85 | data_masked[42];
assign N85 = N84 | data_masked[173];
assign N84 = data_masked[435] | data_masked[304];
assign data_o[43] = N87 | data_masked[43];
assign N87 = N86 | data_masked[174];
assign N86 = data_masked[436] | data_masked[305];
assign data_o[44] = N89 | data_masked[44];
assign N89 = N88 | data_masked[175];
assign N88 = data_masked[437] | data_masked[306];
assign data_o[45] = N91 | data_masked[45];
assign N91 = N90 | data_masked[176];
assign N90 = data_masked[438] | data_masked[307];
assign data_o[46] = N93 | data_masked[46];
assign N93 = N92 | data_masked[177];
assign N92 = data_masked[439] | data_masked[308];
assign data_o[47] = N95 | data_masked[47];
assign N95 = N94 | data_masked[178];
assign N94 = data_masked[440] | data_masked[309];
assign data_o[48] = N97 | data_masked[48];
assign N97 = N96 | data_masked[179];
assign N96 = data_masked[441] | data_masked[310];
assign data_o[49] = N99 | data_masked[49];
assign N99 = N98 | data_masked[180];
assign N98 = data_masked[442] | data_masked[311];
assign data_o[50] = N101 | data_masked[50];
assign N101 = N100 | data_masked[181];
assign N100 = data_masked[443] | data_masked[312];
assign data_o[51] = N103 | data_masked[51];
assign N103 = N102 | data_masked[182];
assign N102 = data_masked[444] | data_masked[313];
assign data_o[52] = N105 | data_masked[52];
assign N105 = N104 | data_masked[183];
assign N104 = data_masked[445] | data_masked[314];
assign data_o[53] = N107 | data_masked[53];
assign N107 = N106 | data_masked[184];
assign N106 = data_masked[446] | data_masked[315];
assign data_o[54] = N109 | data_masked[54];
assign N109 = N108 | data_masked[185];
assign N108 = data_masked[447] | data_masked[316];
assign data_o[55] = N111 | data_masked[55];
assign N111 = N110 | data_masked[186];
assign N110 = data_masked[448] | data_masked[317];
assign data_o[56] = N113 | data_masked[56];
assign N113 = N112 | data_masked[187];
assign N112 = data_masked[449] | data_masked[318];
assign data_o[57] = N115 | data_masked[57];
assign N115 = N114 | data_masked[188];
assign N114 = data_masked[450] | data_masked[319];
assign data_o[58] = N117 | data_masked[58];
assign N117 = N116 | data_masked[189];
assign N116 = data_masked[451] | data_masked[320];
assign data_o[59] = N119 | data_masked[59];
assign N119 = N118 | data_masked[190];
assign N118 = data_masked[452] | data_masked[321];
assign data_o[60] = N121 | data_masked[60];
assign N121 = N120 | data_masked[191];
assign N120 = data_masked[453] | data_masked[322];
assign data_o[61] = N123 | data_masked[61];
assign N123 = N122 | data_masked[192];
assign N122 = data_masked[454] | data_masked[323];
assign data_o[62] = N125 | data_masked[62];
assign N125 = N124 | data_masked[193];
assign N124 = data_masked[455] | data_masked[324];
assign data_o[63] = N127 | data_masked[63];
assign N127 = N126 | data_masked[194];
assign N126 = data_masked[456] | data_masked[325];
assign data_o[64] = N129 | data_masked[64];
assign N129 = N128 | data_masked[195];
assign N128 = data_masked[457] | data_masked[326];
assign data_o[65] = N131 | data_masked[65];
assign N131 = N130 | data_masked[196];
assign N130 = data_masked[458] | data_masked[327];
assign data_o[66] = N133 | data_masked[66];
assign N133 = N132 | data_masked[197];
assign N132 = data_masked[459] | data_masked[328];
assign data_o[67] = N135 | data_masked[67];
assign N135 = N134 | data_masked[198];
assign N134 = data_masked[460] | data_masked[329];
assign data_o[68] = N137 | data_masked[68];
assign N137 = N136 | data_masked[199];
assign N136 = data_masked[461] | data_masked[330];
assign data_o[69] = N139 | data_masked[69];
assign N139 = N138 | data_masked[200];
assign N138 = data_masked[462] | data_masked[331];
assign data_o[70] = N141 | data_masked[70];
assign N141 = N140 | data_masked[201];
assign N140 = data_masked[463] | data_masked[332];
assign data_o[71] = N143 | data_masked[71];
assign N143 = N142 | data_masked[202];
assign N142 = data_masked[464] | data_masked[333];
assign data_o[72] = N145 | data_masked[72];
assign N145 = N144 | data_masked[203];
assign N144 = data_masked[465] | data_masked[334];
assign data_o[73] = N147 | data_masked[73];
assign N147 = N146 | data_masked[204];
assign N146 = data_masked[466] | data_masked[335];
assign data_o[74] = N149 | data_masked[74];
assign N149 = N148 | data_masked[205];
assign N148 = data_masked[467] | data_masked[336];
assign data_o[75] = N151 | data_masked[75];
assign N151 = N150 | data_masked[206];
assign N150 = data_masked[468] | data_masked[337];
assign data_o[76] = N153 | data_masked[76];
assign N153 = N152 | data_masked[207];
assign N152 = data_masked[469] | data_masked[338];
assign data_o[77] = N155 | data_masked[77];
assign N155 = N154 | data_masked[208];
assign N154 = data_masked[470] | data_masked[339];
assign data_o[78] = N157 | data_masked[78];
assign N157 = N156 | data_masked[209];
assign N156 = data_masked[471] | data_masked[340];
assign data_o[79] = N159 | data_masked[79];
assign N159 = N158 | data_masked[210];
assign N158 = data_masked[472] | data_masked[341];
assign data_o[80] = N161 | data_masked[80];
assign N161 = N160 | data_masked[211];
assign N160 = data_masked[473] | data_masked[342];
assign data_o[81] = N163 | data_masked[81];
assign N163 = N162 | data_masked[212];
assign N162 = data_masked[474] | data_masked[343];
assign data_o[82] = N165 | data_masked[82];
assign N165 = N164 | data_masked[213];
assign N164 = data_masked[475] | data_masked[344];
assign data_o[83] = N167 | data_masked[83];
assign N167 = N166 | data_masked[214];
assign N166 = data_masked[476] | data_masked[345];
assign data_o[84] = N169 | data_masked[84];
assign N169 = N168 | data_masked[215];
assign N168 = data_masked[477] | data_masked[346];
assign data_o[85] = N171 | data_masked[85];
assign N171 = N170 | data_masked[216];
assign N170 = data_masked[478] | data_masked[347];
assign data_o[86] = N173 | data_masked[86];
assign N173 = N172 | data_masked[217];
assign N172 = data_masked[479] | data_masked[348];
assign data_o[87] = N175 | data_masked[87];
assign N175 = N174 | data_masked[218];
assign N174 = data_masked[480] | data_masked[349];
assign data_o[88] = N177 | data_masked[88];
assign N177 = N176 | data_masked[219];
assign N176 = data_masked[481] | data_masked[350];
assign data_o[89] = N179 | data_masked[89];
assign N179 = N178 | data_masked[220];
assign N178 = data_masked[482] | data_masked[351];
assign data_o[90] = N181 | data_masked[90];
assign N181 = N180 | data_masked[221];
assign N180 = data_masked[483] | data_masked[352];
assign data_o[91] = N183 | data_masked[91];
assign N183 = N182 | data_masked[222];
assign N182 = data_masked[484] | data_masked[353];
assign data_o[92] = N185 | data_masked[92];
assign N185 = N184 | data_masked[223];
assign N184 = data_masked[485] | data_masked[354];
assign data_o[93] = N187 | data_masked[93];
assign N187 = N186 | data_masked[224];
assign N186 = data_masked[486] | data_masked[355];
assign data_o[94] = N189 | data_masked[94];
assign N189 = N188 | data_masked[225];
assign N188 = data_masked[487] | data_masked[356];
assign data_o[95] = N191 | data_masked[95];
assign N191 = N190 | data_masked[226];
assign N190 = data_masked[488] | data_masked[357];
assign data_o[96] = N193 | data_masked[96];
assign N193 = N192 | data_masked[227];
assign N192 = data_masked[489] | data_masked[358];
assign data_o[97] = N195 | data_masked[97];
assign N195 = N194 | data_masked[228];
assign N194 = data_masked[490] | data_masked[359];
assign data_o[98] = N197 | data_masked[98];
assign N197 = N196 | data_masked[229];
assign N196 = data_masked[491] | data_masked[360];
assign data_o[99] = N199 | data_masked[99];
assign N199 = N198 | data_masked[230];
assign N198 = data_masked[492] | data_masked[361];
assign data_o[100] = N201 | data_masked[100];
assign N201 = N200 | data_masked[231];
assign N200 = data_masked[493] | data_masked[362];
assign data_o[101] = N203 | data_masked[101];
assign N203 = N202 | data_masked[232];
assign N202 = data_masked[494] | data_masked[363];
assign data_o[102] = N205 | data_masked[102];
assign N205 = N204 | data_masked[233];
assign N204 = data_masked[495] | data_masked[364];
assign data_o[103] = N207 | data_masked[103];
assign N207 = N206 | data_masked[234];
assign N206 = data_masked[496] | data_masked[365];
assign data_o[104] = N209 | data_masked[104];
assign N209 = N208 | data_masked[235];
assign N208 = data_masked[497] | data_masked[366];
assign data_o[105] = N211 | data_masked[105];
assign N211 = N210 | data_masked[236];
assign N210 = data_masked[498] | data_masked[367];
assign data_o[106] = N213 | data_masked[106];
assign N213 = N212 | data_masked[237];
assign N212 = data_masked[499] | data_masked[368];
assign data_o[107] = N215 | data_masked[107];
assign N215 = N214 | data_masked[238];
assign N214 = data_masked[500] | data_masked[369];
assign data_o[108] = N217 | data_masked[108];
assign N217 = N216 | data_masked[239];
assign N216 = data_masked[501] | data_masked[370];
assign data_o[109] = N219 | data_masked[109];
assign N219 = N218 | data_masked[240];
assign N218 = data_masked[502] | data_masked[371];
assign data_o[110] = N221 | data_masked[110];
assign N221 = N220 | data_masked[241];
assign N220 = data_masked[503] | data_masked[372];
assign data_o[111] = N223 | data_masked[111];
assign N223 = N222 | data_masked[242];
assign N222 = data_masked[504] | data_masked[373];
assign data_o[112] = N225 | data_masked[112];
assign N225 = N224 | data_masked[243];
assign N224 = data_masked[505] | data_masked[374];
assign data_o[113] = N227 | data_masked[113];
assign N227 = N226 | data_masked[244];
assign N226 = data_masked[506] | data_masked[375];
assign data_o[114] = N229 | data_masked[114];
assign N229 = N228 | data_masked[245];
assign N228 = data_masked[507] | data_masked[376];
assign data_o[115] = N231 | data_masked[115];
assign N231 = N230 | data_masked[246];
assign N230 = data_masked[508] | data_masked[377];
assign data_o[116] = N233 | data_masked[116];
assign N233 = N232 | data_masked[247];
assign N232 = data_masked[509] | data_masked[378];
assign data_o[117] = N235 | data_masked[117];
assign N235 = N234 | data_masked[248];
assign N234 = data_masked[510] | data_masked[379];
assign data_o[118] = N237 | data_masked[118];
assign N237 = N236 | data_masked[249];
assign N236 = data_masked[511] | data_masked[380];
assign data_o[119] = N239 | data_masked[119];
assign N239 = N238 | data_masked[250];
assign N238 = data_masked[512] | data_masked[381];
assign data_o[120] = N241 | data_masked[120];
assign N241 = N240 | data_masked[251];
assign N240 = data_masked[513] | data_masked[382];
assign data_o[121] = N243 | data_masked[121];
assign N243 = N242 | data_masked[252];
assign N242 = data_masked[514] | data_masked[383];
assign data_o[122] = N245 | data_masked[122];
assign N245 = N244 | data_masked[253];
assign N244 = data_masked[515] | data_masked[384];
assign data_o[123] = N247 | data_masked[123];
assign N247 = N246 | data_masked[254];
assign N246 = data_masked[516] | data_masked[385];
assign data_o[124] = N249 | data_masked[124];
assign N249 = N248 | data_masked[255];
assign N248 = data_masked[517] | data_masked[386];
assign data_o[125] = N251 | data_masked[125];
assign N251 = N250 | data_masked[256];
assign N250 = data_masked[518] | data_masked[387];
assign data_o[126] = N253 | data_masked[126];
assign N253 = N252 | data_masked[257];
assign N252 = data_masked[519] | data_masked[388];
assign data_o[127] = N255 | data_masked[127];
assign N255 = N254 | data_masked[258];
assign N254 = data_masked[520] | data_masked[389];
assign data_o[128] = N257 | data_masked[128];
assign N257 = N256 | data_masked[259];
assign N256 = data_masked[521] | data_masked[390];
assign data_o[129] = N259 | data_masked[129];
assign N259 = N258 | data_masked[260];
assign N258 = data_masked[522] | data_masked[391];
assign data_o[130] = N261 | data_masked[130];
assign N261 = N260 | data_masked[261];
assign N260 = data_masked[523] | data_masked[392];
endmodule |
module bsg_mem_1r1w_synth_width_p99_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [98:0] w_data_i;
input [0:0] r_addr_i;
output [98:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [98:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [197:0] mem;
assign r_data_o[98] = (N3)? mem[98] :
(N0)? mem[197] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[97] = (N3)? mem[97] :
(N0)? mem[196] : 1'b0;
assign r_data_o[96] = (N3)? mem[96] :
(N0)? mem[195] : 1'b0;
assign r_data_o[95] = (N3)? mem[95] :
(N0)? mem[194] : 1'b0;
assign r_data_o[94] = (N3)? mem[94] :
(N0)? mem[193] : 1'b0;
assign r_data_o[93] = (N3)? mem[93] :
(N0)? mem[192] : 1'b0;
assign r_data_o[92] = (N3)? mem[92] :
(N0)? mem[191] : 1'b0;
assign r_data_o[91] = (N3)? mem[91] :
(N0)? mem[190] : 1'b0;
assign r_data_o[90] = (N3)? mem[90] :
(N0)? mem[189] : 1'b0;
assign r_data_o[89] = (N3)? mem[89] :
(N0)? mem[188] : 1'b0;
assign r_data_o[88] = (N3)? mem[88] :
(N0)? mem[187] : 1'b0;
assign r_data_o[87] = (N3)? mem[87] :
(N0)? mem[186] : 1'b0;
assign r_data_o[86] = (N3)? mem[86] :
(N0)? mem[185] : 1'b0;
assign r_data_o[85] = (N3)? mem[85] :
(N0)? mem[184] : 1'b0;
assign r_data_o[84] = (N3)? mem[84] :
(N0)? mem[183] : 1'b0;
assign r_data_o[83] = (N3)? mem[83] :
(N0)? mem[182] : 1'b0;
assign r_data_o[82] = (N3)? mem[82] :
(N0)? mem[181] : 1'b0;
assign r_data_o[81] = (N3)? mem[81] :
(N0)? mem[180] : 1'b0;
assign r_data_o[80] = (N3)? mem[80] :
(N0)? mem[179] : 1'b0;
assign r_data_o[79] = (N3)? mem[79] :
(N0)? mem[178] : 1'b0;
assign r_data_o[78] = (N3)? mem[78] :
(N0)? mem[177] : 1'b0;
assign r_data_o[77] = (N3)? mem[77] :
(N0)? mem[176] : 1'b0;
assign r_data_o[76] = (N3)? mem[76] :
(N0)? mem[175] : 1'b0;
assign r_data_o[75] = (N3)? mem[75] :
(N0)? mem[174] : 1'b0;
assign r_data_o[74] = (N3)? mem[74] :
(N0)? mem[173] : 1'b0;
assign r_data_o[73] = (N3)? mem[73] :
(N0)? mem[172] : 1'b0;
assign r_data_o[72] = (N3)? mem[72] :
(N0)? mem[171] : 1'b0;
assign r_data_o[71] = (N3)? mem[71] :
(N0)? mem[170] : 1'b0;
assign r_data_o[70] = (N3)? mem[70] :
(N0)? mem[169] : 1'b0;
assign r_data_o[69] = (N3)? mem[69] :
(N0)? mem[168] : 1'b0;
assign r_data_o[68] = (N3)? mem[68] :
(N0)? mem[167] : 1'b0;
assign r_data_o[67] = (N3)? mem[67] :
(N0)? mem[166] : 1'b0;
assign r_data_o[66] = (N3)? mem[66] :
(N0)? mem[165] : 1'b0;
assign r_data_o[65] = (N3)? mem[65] :
(N0)? mem[164] : 1'b0;
assign r_data_o[64] = (N3)? mem[64] :
(N0)? mem[163] : 1'b0;
assign r_data_o[63] = (N3)? mem[63] :
(N0)? mem[162] : 1'b0;
assign r_data_o[62] = (N3)? mem[62] :
(N0)? mem[161] : 1'b0;
assign r_data_o[61] = (N3)? mem[61] :
(N0)? mem[160] : 1'b0;
assign r_data_o[60] = (N3)? mem[60] :
(N0)? mem[159] : 1'b0;
assign r_data_o[59] = (N3)? mem[59] :
(N0)? mem[158] : 1'b0;
assign r_data_o[58] = (N3)? mem[58] :
(N0)? mem[157] : 1'b0;
assign r_data_o[57] = (N3)? mem[57] :
(N0)? mem[156] : 1'b0;
assign r_data_o[56] = (N3)? mem[56] :
(N0)? mem[155] : 1'b0;
assign r_data_o[55] = (N3)? mem[55] :
(N0)? mem[154] : 1'b0;
assign r_data_o[54] = (N3)? mem[54] :
(N0)? mem[153] : 1'b0;
assign r_data_o[53] = (N3)? mem[53] :
(N0)? mem[152] : 1'b0;
assign r_data_o[52] = (N3)? mem[52] :
(N0)? mem[151] : 1'b0;
assign r_data_o[51] = (N3)? mem[51] :
(N0)? mem[150] : 1'b0;
assign r_data_o[50] = (N3)? mem[50] :
(N0)? mem[149] : 1'b0;
assign r_data_o[49] = (N3)? mem[49] :
(N0)? mem[148] : 1'b0;
assign r_data_o[48] = (N3)? mem[48] :
(N0)? mem[147] : 1'b0;
assign r_data_o[47] = (N3)? mem[47] :
(N0)? mem[146] : 1'b0;
assign r_data_o[46] = (N3)? mem[46] :
(N0)? mem[145] : 1'b0;
assign r_data_o[45] = (N3)? mem[45] :
(N0)? mem[144] : 1'b0;
assign r_data_o[44] = (N3)? mem[44] :
(N0)? mem[143] : 1'b0;
assign r_data_o[43] = (N3)? mem[43] :
(N0)? mem[142] : 1'b0;
assign r_data_o[42] = (N3)? mem[42] :
(N0)? mem[141] : 1'b0;
assign r_data_o[41] = (N3)? mem[41] :
(N0)? mem[140] : 1'b0;
assign r_data_o[40] = (N3)? mem[40] :
(N0)? mem[139] : 1'b0;
assign r_data_o[39] = (N3)? mem[39] :
(N0)? mem[138] : 1'b0;
assign r_data_o[38] = (N3)? mem[38] :
(N0)? mem[137] : 1'b0;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[136] : 1'b0;
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[135] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[134] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[133] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[132] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[131] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[130] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[129] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[128] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[127] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[126] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[125] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[124] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[123] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[122] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[121] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[120] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[119] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[118] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[117] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[116] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[115] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[114] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[113] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[112] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[111] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[110] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[109] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[108] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[107] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[106] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[105] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[104] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[103] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[102] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[101] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[100] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[99] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N8) begin
{ mem[197:99] } <= { w_data_i[98:0] };
end
if(N7) begin
{ mem[98:0] } <= { w_data_i[98:0] };
end
end
endmodule |
module bsg_circular_ptr_slots_p16_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [3:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
wire [3:0] genblk1_genblk1_ptr_r_p1;
reg [3:0] o;
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N7 = ~add_i[0];
assign N8 = N7 & N2;
assign N9 = ~N8;
always @(posedge clk) begin
if(N9) begin
{ o[3:0] } <= { N6, N5, N4, N3 };
end
end
endmodule |
module bp_be_dcache_lce_req_data_width_p64_paddr_width_p22_num_cce_p1_num_lce_p2_ways_p8
(
clk_i,
reset_i,
lce_id_i,
load_miss_i,
store_miss_i,
miss_addr_i,
lru_way_i,
dirty_i,
uncached_load_req_i,
uncached_store_req_i,
store_data_i,
size_op_i,
cache_miss_o,
miss_addr_o,
tr_data_received_i,
cce_data_received_i,
uncached_data_received_i,
set_tag_received_i,
set_tag_wakeup_received_i,
lce_req_o,
lce_req_v_o,
lce_req_ready_i,
lce_resp_o,
lce_resp_v_o,
lce_resp_yumi_i
);
input [0:0] lce_id_i;
input [21:0] miss_addr_i;
input [2:0] lru_way_i;
input [7:0] dirty_i;
input [63:0] store_data_i;
input [1:0] size_op_i;
output [21:0] miss_addr_o;
output [96:0] lce_req_o;
output [25:0] lce_resp_o;
input clk_i;
input reset_i;
input load_miss_i;
input store_miss_i;
input uncached_load_req_i;
input uncached_store_req_i;
input tr_data_received_i;
input cce_data_received_i;
input uncached_data_received_i;
input set_tag_received_i;
input set_tag_wakeup_received_i;
input lce_req_ready_i;
input lce_resp_yumi_i;
output cache_miss_o;
output lce_req_v_o;
output lce_resp_v_o;
wire [96:0] lce_req_o;
wire [25:0] lce_resp_o;
wire cache_miss_o,lce_req_v_o,lce_resp_v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,
tr_data_received,cce_data_received,set_tag_received,N12,N13,N14,N15,N16,N17,N18,N19,
N20,N21,N22,N23,N24,N25,N26,N27,N28,dirty_lru_flopped_n,tr_data_received_n,
cce_data_received_n,set_tag_received_n,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,
N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,
N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,
N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,
N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,
N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,
N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,
N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,
N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,
N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,
N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,
N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227,
N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,N242,N243,
N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256;
wire [2:0] state_n;
reg size_op_r,dirty_lru_flopped_r,tr_data_received_r,cce_data_received_r,
set_tag_received_r,load_not_store_r,dirty_r;
reg [2:0] state_r,lru_way_r;
reg [21:0] miss_addr_o;
assign lce_resp_o[23] = 1'b1;
assign lce_resp_o[25] = 1'b0;
assign lce_req_o[29] = 1'b0;
assign lce_req_o[32] = 1'b0;
assign lce_resp_o[21] = miss_addr_o[21];
assign lce_resp_o[20] = miss_addr_o[20];
assign lce_resp_o[19] = miss_addr_o[19];
assign lce_resp_o[18] = miss_addr_o[18];
assign lce_resp_o[17] = miss_addr_o[17];
assign lce_resp_o[16] = miss_addr_o[16];
assign lce_resp_o[15] = miss_addr_o[15];
assign lce_resp_o[14] = miss_addr_o[14];
assign lce_resp_o[13] = miss_addr_o[13];
assign lce_resp_o[12] = miss_addr_o[12];
assign lce_resp_o[11] = miss_addr_o[11];
assign lce_resp_o[10] = miss_addr_o[10];
assign lce_resp_o[9] = miss_addr_o[9];
assign lce_resp_o[8] = miss_addr_o[8];
assign lce_resp_o[7] = miss_addr_o[7];
assign lce_resp_o[6] = miss_addr_o[6];
assign lce_resp_o[5] = miss_addr_o[5];
assign lce_resp_o[4] = miss_addr_o[4];
assign lce_resp_o[3] = miss_addr_o[3];
assign lce_resp_o[2] = miss_addr_o[2];
assign lce_resp_o[1] = miss_addr_o[1];
assign lce_resp_o[0] = miss_addr_o[0];
assign lce_resp_o[24] = lce_id_i[0];
assign lce_req_o[31] = lce_id_i[0];
assign N28 = (N20)? dirty_i[0] :
(N22)? dirty_i[1] :
(N24)? dirty_i[2] :
(N26)? dirty_i[3] :
(N21)? dirty_i[4] :
(N23)? dirty_i[5] :
(N25)? dirty_i[6] :
(N27)? dirty_i[7] : 1'b0;
assign N32 = N29 & N30;
assign N33 = N32 & N31;
assign N34 = state_r[2] | state_r[1];
assign N35 = N34 | N31;
assign N37 = state_r[2] | N30;
assign N38 = N37 | state_r[0];
assign N40 = N29 | state_r[1];
assign N41 = N40 | N31;
assign N43 = state_r[2] | N30;
assign N44 = N43 | N31;
assign N46 = N29 | state_r[1];
assign N47 = N46 | state_r[0];
assign N49 = state_r[2] & state_r[1];
assign lce_req_o[6:4] = (N0)? lru_way_r :
(N1)? lru_way_i : 1'b0;
assign N0 = dirty_lru_flopped_r;
assign N1 = N12;
assign lce_req_o[3] = (N0)? dirty_r :
(N1)? N28 : 1'b0;
assign N57 = (N2)? 1'b1 :
(N167)? 1'b1 :
(N170)? N54 :
(N53)? 1'b0 : 1'b0;
assign N2 = N50;
assign { N59, N58 } = (N2)? { 1'b0, 1'b1 } :
(N167)? { 1'b1, 1'b0 } :
(N170)? { 1'b0, 1'b0 } :
(N53)? { 1'b0, 1'b0 } : 1'b0;
assign N60 = (N2)? 1'b0 :
(N167)? 1'b0 :
(N170)? 1'b1 :
(N53)? 1'b0 : 1'b0;
assign { N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61 } = (N2)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, miss_addr_o } :
(N167)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, miss_addr_o } :
(N170)? { store_data_i, miss_addr_i } :
(N53)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, miss_addr_o } : 1'b0;
assign { N158, N157, N156 } = (N3)? { 1'b0, 1'b1, 1'b1 } :
(N174)? { 1'b1, 1'b0, 1'b0 } :
(N155)? { 1'b1, 1'b0, 1'b1 } : 1'b0;
assign N3 = tr_data_received;
assign { N161, N160, N159 } = (N4)? { 1'b0, 1'b0, 1'b0 } :
(N172)? { N158, N157, N156 } :
(N153)? { 1'b1, 1'b0, 1'b1 } : 1'b0;
assign N4 = N151;
assign lce_req_o[1:0] = (N5)? { 1'b0, size_op_r } :
(N163)? size_op_i : 1'b0;
assign N5 = N39;
assign lce_req_o[2] = (N6)? N60 :
(N7)? 1'b0 :
(N5)? 1'b1 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b0 :
(N11)? 1'b0 : 1'b0;
assign N6 = N33;
assign N7 = N36;
assign N8 = N42;
assign N9 = N45;
assign N10 = N48;
assign N11 = N49;
assign { lce_req_o[96:33], lce_req_o[28:7] } = (N6)? { N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61 } :
(N165)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, miss_addr_o } : 1'b0;
assign lce_req_o[30] = (N7)? N147 :
(N166)? 1'b0 : 1'b0;
assign dirty_lru_flopped_n = (N6)? 1'b0 :
(N7)? 1'b1 : 1'b0;
assign tr_data_received_n = (N6)? 1'b0 :
(N8)? 1'b1 : 1'b0;
assign cce_data_received_n = (N6)? 1'b0 :
(N8)? 1'b1 : 1'b0;
assign set_tag_received_n = (N6)? 1'b0 :
(N8)? 1'b1 : 1'b0;
assign cache_miss_o = (N6)? N57 :
(N7)? 1'b1 :
(N5)? 1'b1 :
(N8)? 1'b1 :
(N9)? 1'b1 :
(N10)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign state_n = (N6)? { 1'b0, N59, N58 } :
(N7)? { lce_req_ready_i, 1'b0, 1'b1 } :
(N5)? { lce_req_ready_i, N54, lce_req_ready_i } :
(N8)? { N161, N160, N159 } :
(N9)? { 1'b0, N162, N162 } :
(N10)? { N162, 1'b0, 1'b0 } :
(N11)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign lce_req_v_o = (N6)? N60 :
(N7)? 1'b1 :
(N5)? 1'b1 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b0 :
(N11)? 1'b0 : 1'b0;
assign lce_resp_v_o = (N6)? 1'b0 :
(N7)? 1'b0 :
(N5)? 1'b0 :
(N8)? 1'b0 :
(N9)? 1'b1 :
(N10)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign lce_resp_o[22] = (N6)? 1'b0 :
(N7)? 1'b0 :
(N5)? 1'b0 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign tr_data_received = tr_data_received_r | tr_data_received_i;
assign cce_data_received = cce_data_received_r | cce_data_received_i;
assign set_tag_received = set_tag_received_r | set_tag_received_i;
assign N12 = ~dirty_lru_flopped_r;
assign N13 = ~lru_way_i[0];
assign N14 = ~lru_way_i[1];
assign N15 = N13 & N14;
assign N16 = N13 & lru_way_i[1];
assign N17 = lru_way_i[0] & N14;
assign N18 = lru_way_i[0] & lru_way_i[1];
assign N19 = ~lru_way_i[2];
assign N20 = N15 & N19;
assign N21 = N15 & lru_way_i[2];
assign N22 = N17 & N19;
assign N23 = N17 & lru_way_i[2];
assign N24 = N16 & N19;
assign N25 = N16 & lru_way_i[2];
assign N26 = N18 & N19;
assign N27 = N18 & lru_way_i[2];
assign N29 = ~state_r[2];
assign N30 = ~state_r[1];
assign N31 = ~state_r[0];
assign N36 = ~N35;
assign N39 = ~N38;
assign N42 = ~N41;
assign N45 = ~N44;
assign N48 = ~N47;
assign N50 = load_miss_i | store_miss_i;
assign N51 = uncached_load_req_i | N50;
assign N52 = uncached_store_req_i | N51;
assign N53 = ~N52;
assign N54 = ~lce_req_ready_i;
assign N55 = ~N51;
assign N56 = ~N50;
assign N147 = ~load_not_store_r;
assign N148 = ~tr_data_received_i;
assign N149 = ~cce_data_received_i;
assign N150 = ~set_tag_received_i;
assign N151 = set_tag_wakeup_received_i | uncached_data_received_i;
assign N152 = set_tag_received | N151;
assign N153 = ~N152;
assign N154 = cce_data_received | tr_data_received;
assign N155 = ~N154;
assign N162 = ~lce_resp_yumi_i;
assign N163 = N38;
assign N164 = ~N33;
assign N165 = N164;
assign N166 = N35;
assign N167 = uncached_load_req_i & N56;
assign N168 = ~uncached_load_req_i;
assign N169 = N56 & N168;
assign N170 = uncached_store_req_i & N169;
assign N171 = ~N151;
assign N172 = set_tag_received & N171;
assign N173 = ~tr_data_received;
assign N174 = cce_data_received & N173;
assign N175 = ~reset_i;
assign N176 = N33 & N175;
assign N177 = N50 & N176;
assign N178 = N55 & N176;
assign N179 = N177 | N178;
assign N180 = N36 & N175;
assign N181 = N179 | N180;
assign N182 = N39 & N175;
assign N183 = N181 | N182;
assign N184 = N42 & N175;
assign N185 = N183 | N184;
assign N186 = N45 & N175;
assign N187 = N185 | N186;
assign N188 = N48 & N175;
assign N189 = N187 | N188;
assign N190 = N49 & N175;
assign N191 = N189 | N190;
assign N192 = ~N191;
assign N193 = N175 & N192;
assign N194 = N56 & N33;
assign N195 = N194 | N39;
assign N196 = N195 | N42;
assign N197 = N196 | N45;
assign N198 = N197 | N48;
assign N199 = N198 | N49;
assign N200 = ~N199;
assign N201 = N55 & N33;
assign N202 = N201 | N36;
assign N203 = N202 | N39;
assign N204 = N148 & N42;
assign N205 = N203 | N204;
assign N206 = N205 | N45;
assign N207 = N206 | N48;
assign N208 = N207 | N49;
assign N209 = ~N208;
assign N210 = N149 & N42;
assign N211 = N203 | N210;
assign N212 = N211 | N45;
assign N213 = N212 | N48;
assign N214 = N213 | N49;
assign N215 = ~N214;
assign N216 = N150 & N42;
assign N217 = N203 | N216;
assign N218 = N217 | N45;
assign N219 = N218 | N48;
assign N220 = N219 | N49;
assign N221 = ~N220;
assign N222 = N56 & N176;
assign N223 = N222 | N180;
assign N224 = N223 | N182;
assign N225 = N224 | N184;
assign N226 = N225 | N186;
assign N227 = N226 | N188;
assign N228 = N227 | N190;
assign N229 = ~N228;
assign N230 = N175 & N229;
assign N231 = dirty_lru_flopped_r & N180;
assign N232 = N176 | N231;
assign N233 = N232 | N182;
assign N234 = N233 | N184;
assign N235 = N234 | N186;
assign N236 = N235 | N188;
assign N237 = N236 | N190;
assign N238 = ~N237;
assign N239 = N175 & N238;
assign N240 = dirty_lru_flopped_r & N180;
assign N241 = N176 | N240;
assign N242 = N241 | N182;
assign N243 = N242 | N184;
assign N244 = N243 | N186;
assign N245 = N244 | N188;
assign N246 = N245 | N190;
assign N247 = ~N246;
assign N248 = N175 & N247;
assign N249 = N178 | N180;
assign N250 = N249 | N182;
assign N251 = N250 | N184;
assign N252 = N251 | N186;
assign N253 = N252 | N188;
assign N254 = N253 | N190;
assign N255 = ~N254;
assign N256 = N175 & N255;
always @(posedge clk_i) begin
if(N193) begin
size_op_r <= size_op_i[0];
end
if(reset_i) begin
{ state_r[2:0] } <= { 1'b0, 1'b0, 1'b0 };
end else if(1'b1) begin
{ state_r[2:0] } <= { state_n[2:0] };
end
if(reset_i) begin
dirty_lru_flopped_r <= 1'b0;
end else if(N200) begin
dirty_lru_flopped_r <= dirty_lru_flopped_n;
end
if(reset_i) begin
tr_data_received_r <= 1'b0;
end else if(N209) begin
tr_data_received_r <= tr_data_received_n;
end
if(reset_i) begin
cce_data_received_r <= 1'b0;
end else if(N215) begin
cce_data_received_r <= cce_data_received_n;
end
if(reset_i) begin
set_tag_received_r <= 1'b0;
end else if(N221) begin
set_tag_received_r <= set_tag_received_n;
end
if(N230) begin
load_not_store_r <= load_miss_i;
end
if(N239) begin
{ lru_way_r[2:0] } <= { lru_way_i[2:0] };
end
if(N248) begin
dirty_r <= N28;
end
if(N256) begin
{ miss_addr_o[21:0] } <= { miss_addr_i[21:0] };
end
end
endmodule |
module bsg_dff_width_p45
(
clk_i,
data_i,
data_o
);
input [44:0] data_i;
output [44:0] data_o;
input clk_i;
reg [44:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[44:0] } <= { data_i[44:0] };
end
end
endmodule |
module bsg_circular_ptr_slots_p2_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [0:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6;
wire [0:0] genblk1_genblk1_ptr_r_p1;
reg [0:0] o;
assign genblk1_genblk1_ptr_r_p1[0] = o[0] ^ 1'b1;
assign N3 = (N0)? 1'b0 :
(N1)? genblk1_genblk1_ptr_r_p1[0] : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N4 = ~add_i[0];
assign N5 = N4 & N2;
assign N6 = ~N5;
always @(posedge clk) begin
if(N6) begin
{ o[0:0] } <= { N3 };
end
end
endmodule |
module bp_be_detector_vaddr_width_p39_paddr_width_p22_asid_width_p10_branch_metadata_fwd_width_p36_load_to_use_forwarding_p1
(
clk_i,
reset_i,
calc_status_i,
expected_npc_i,
mmu_cmd_ready_i,
chk_dispatch_v_o,
chk_roll_o,
chk_poison_isd_o,
chk_poison_ex1_o,
chk_poison_ex2_o,
chk_poison_ex3_o
);
input [306:0] calc_status_i;
input [63:0] expected_npc_i;
input clk_i;
input reset_i;
input mmu_cmd_ready_i;
output chk_dispatch_v_o;
output chk_roll_o;
output chk_poison_isd_o;
output chk_poison_ex1_o;
output chk_poison_ex2_o;
output chk_poison_ex3_o;
wire chk_dispatch_v_o,chk_roll_o,chk_poison_isd_o,chk_poison_ex1_o,chk_poison_ex2_o,
chk_poison_ex3_o,N0,N1,N2,N3,N4,N5,stall_haz_v,data_haz_v,struct_haz_v,N6,
mispredict_v,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,
N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,
N46,N47,N48,N49,N50,N51,N52;
wire [2:0] rs1_match_vector,rs2_match_vector,frs1_data_haz_v,frs2_data_haz_v;
wire [1:0] irs1_data_haz_v,irs2_data_haz_v;
assign chk_roll_o = calc_status_i[3];
assign N0 = calc_status_i[303:299] == calc_status_i[73:69];
assign N1 = calc_status_i[296:292] == calc_status_i[73:69];
assign N2 = calc_status_i[303:299] == calc_status_i[84:80];
assign N3 = calc_status_i[296:292] == calc_status_i[84:80];
assign N4 = calc_status_i[303:299] == calc_status_i[95:91];
assign N5 = calc_status_i[296:292] == calc_status_i[95:91];
assign N6 = calc_status_i[187:124] != expected_npc_i;
assign N7 = calc_status_i[302] | calc_status_i[303];
assign N8 = calc_status_i[301] | N7;
assign N9 = calc_status_i[300] | N8;
assign N10 = calc_status_i[299] | N9;
assign N11 = calc_status_i[295] | calc_status_i[296];
assign N12 = calc_status_i[294] | N11;
assign N13 = calc_status_i[293] | N12;
assign N14 = calc_status_i[292] | N13;
assign rs1_match_vector[0] = N10 & N0;
assign rs2_match_vector[0] = N14 & N1;
assign rs1_match_vector[1] = N10 & N2;
assign rs2_match_vector[1] = N14 & N3;
assign rs1_match_vector[2] = N10 & N4;
assign rs2_match_vector[2] = N14 & N5;
assign irs1_data_haz_v[0] = N15 & N16;
assign N15 = calc_status_i[305] & rs1_match_vector[0];
assign N16 = calc_status_i[78] | calc_status_i[77];
assign irs2_data_haz_v[0] = N17 & N18;
assign N17 = calc_status_i[298] & rs2_match_vector[0];
assign N18 = calc_status_i[78] | calc_status_i[77];
assign frs1_data_haz_v[0] = N19 & N20;
assign N19 = calc_status_i[304] & rs1_match_vector[0];
assign N20 = calc_status_i[76] | calc_status_i[75];
assign frs2_data_haz_v[0] = N21 & N22;
assign N21 = calc_status_i[297] & rs2_match_vector[0];
assign N22 = calc_status_i[76] | calc_status_i[75];
assign irs1_data_haz_v[1] = N23 & calc_status_i[88];
assign N23 = calc_status_i[305] & rs1_match_vector[1];
assign irs2_data_haz_v[1] = N24 & calc_status_i[88];
assign N24 = calc_status_i[298] & rs2_match_vector[1];
assign frs1_data_haz_v[1] = N25 & N26;
assign N25 = calc_status_i[304] & rs1_match_vector[1];
assign N26 = calc_status_i[87] | calc_status_i[86];
assign frs2_data_haz_v[1] = N27 & N28;
assign N27 = calc_status_i[297] & rs2_match_vector[1];
assign N28 = calc_status_i[87] | calc_status_i[86];
assign frs1_data_haz_v[2] = N29 & calc_status_i[97];
assign N29 = calc_status_i[304] & rs1_match_vector[2];
assign frs2_data_haz_v[2] = N30 & calc_status_i[97];
assign N30 = calc_status_i[297] & rs2_match_vector[2];
assign stall_haz_v = N32 | calc_status_i[107];
assign N32 = N31 | calc_status_i[96];
assign N31 = calc_status_i[74] | calc_status_i[85];
assign data_haz_v = N39 | N41;
assign N39 = N36 | N38;
assign N36 = N34 | N35;
assign N34 = stall_haz_v | N33;
assign N33 = irs1_data_haz_v[1] | irs1_data_haz_v[0];
assign N35 = irs2_data_haz_v[1] | irs2_data_haz_v[0];
assign N38 = N37 | frs1_data_haz_v[0];
assign N37 = frs1_data_haz_v[2] | frs1_data_haz_v[1];
assign N41 = N40 | frs2_data_haz_v[0];
assign N40 = frs2_data_haz_v[2] | frs2_data_haz_v[1];
assign struct_haz_v = ~mmu_cmd_ready_i;
assign mispredict_v = calc_status_i[188] & N6;
assign chk_dispatch_v_o = N43 | calc_status_i[3];
assign N43 = ~N42;
assign N42 = data_haz_v | struct_haz_v;
assign chk_poison_isd_o = N45 | calc_status_i[1];
assign N45 = N44 | calc_status_i[2];
assign N44 = reset_i | calc_status_i[3];
assign chk_poison_ex1_o = N48 | calc_status_i[1];
assign N48 = N47 | calc_status_i[2];
assign N47 = N46 | calc_status_i[3];
assign N46 = reset_i | mispredict_v;
assign chk_poison_ex2_o = N50 | calc_status_i[1];
assign N50 = N49 | calc_status_i[2];
assign N49 = reset_i | calc_status_i[3];
assign chk_poison_ex3_o = N52 | calc_status_i[1];
assign N52 = N51 | calc_status_i[2];
assign N51 = reset_i | calc_status_i[3];
endmodule |
module bsg_circular_ptr_slots_p16_max_add_p15
(
clk,
reset_i,
add_i,
o
);
input [3:0] add_i;
output [3:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6;
wire [3:0] ptr_n;
reg [3:0] o;
assign ptr_n = o + add_i;
assign { N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? ptr_n : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
always @(posedge clk) begin
if(1'b1) begin
{ o[3:0] } <= { N6, N5, N4, N3 };
end
end
endmodule |
module bsg_dff_width_p600
(
clk_i,
data_i,
data_o
);
input [599:0] data_i;
output [599:0] data_o;
input clk_i;
reg [599:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[599:0] } <= { data_i[599:0] };
end
end
endmodule |
module bsg_dff_width_p386
(
clk_i,
data_i,
data_o
);
input [385:0] data_i;
output [385:0] data_o;
input clk_i;
reg [385:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[385:0] } <= { data_i[385:0] };
end
end
endmodule |
module bsg_dff_en_width_p64
(
clk_i,
data_i,
en_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input en_i;
reg [63:0] data_o;
always @(posedge clk_i) begin
if(en_i) begin
{ data_o[63:0] } <= { data_i[63:0] };
end
end
endmodule |
module bsg_mem_1r1w_synth_width_p136_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [135:0] w_data_i;
input [0:0] r_addr_i;
output [135:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [135:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8,N9,N10;
reg [271:0] mem;
assign r_data_o[135] = (N3)? mem[135] :
(N0)? mem[271] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[134] = (N3)? mem[134] :
(N0)? mem[270] : 1'b0;
assign r_data_o[133] = (N3)? mem[133] :
(N0)? mem[269] : 1'b0;
assign r_data_o[132] = (N3)? mem[132] :
(N0)? mem[268] : 1'b0;
assign r_data_o[131] = (N3)? mem[131] :
(N0)? mem[267] : 1'b0;
assign r_data_o[130] = (N3)? mem[130] :
(N0)? mem[266] : 1'b0;
assign r_data_o[129] = (N3)? mem[129] :
(N0)? mem[265] : 1'b0;
assign r_data_o[128] = (N3)? mem[128] :
(N0)? mem[264] : 1'b0;
assign r_data_o[127] = (N3)? mem[127] :
(N0)? mem[263] : 1'b0;
assign r_data_o[126] = (N3)? mem[126] :
(N0)? mem[262] : 1'b0;
assign r_data_o[125] = (N3)? mem[125] :
(N0)? mem[261] : 1'b0;
assign r_data_o[124] = (N3)? mem[124] :
(N0)? mem[260] : 1'b0;
assign r_data_o[123] = (N3)? mem[123] :
(N0)? mem[259] : 1'b0;
assign r_data_o[122] = (N3)? mem[122] :
(N0)? mem[258] : 1'b0;
assign r_data_o[121] = (N3)? mem[121] :
(N0)? mem[257] : 1'b0;
assign r_data_o[120] = (N3)? mem[120] :
(N0)? mem[256] : 1'b0;
assign r_data_o[119] = (N3)? mem[119] :
(N0)? mem[255] : 1'b0;
assign r_data_o[118] = (N3)? mem[118] :
(N0)? mem[254] : 1'b0;
assign r_data_o[117] = (N3)? mem[117] :
(N0)? mem[253] : 1'b0;
assign r_data_o[116] = (N3)? mem[116] :
(N0)? mem[252] : 1'b0;
assign r_data_o[115] = (N3)? mem[115] :
(N0)? mem[251] : 1'b0;
assign r_data_o[114] = (N3)? mem[114] :
(N0)? mem[250] : 1'b0;
assign r_data_o[113] = (N3)? mem[113] :
(N0)? mem[249] : 1'b0;
assign r_data_o[112] = (N3)? mem[112] :
(N0)? mem[248] : 1'b0;
assign r_data_o[111] = (N3)? mem[111] :
(N0)? mem[247] : 1'b0;
assign r_data_o[110] = (N3)? mem[110] :
(N0)? mem[246] : 1'b0;
assign r_data_o[109] = (N3)? mem[109] :
(N0)? mem[245] : 1'b0;
assign r_data_o[108] = (N3)? mem[108] :
(N0)? mem[244] : 1'b0;
assign r_data_o[107] = (N3)? mem[107] :
(N0)? mem[243] : 1'b0;
assign r_data_o[106] = (N3)? mem[106] :
(N0)? mem[242] : 1'b0;
assign r_data_o[105] = (N3)? mem[105] :
(N0)? mem[241] : 1'b0;
assign r_data_o[104] = (N3)? mem[104] :
(N0)? mem[240] : 1'b0;
assign r_data_o[103] = (N3)? mem[103] :
(N0)? mem[239] : 1'b0;
assign r_data_o[102] = (N3)? mem[102] :
(N0)? mem[238] : 1'b0;
assign r_data_o[101] = (N3)? mem[101] :
(N0)? mem[237] : 1'b0;
assign r_data_o[100] = (N3)? mem[100] :
(N0)? mem[236] : 1'b0;
assign r_data_o[99] = (N3)? mem[99] :
(N0)? mem[235] : 1'b0;
assign r_data_o[98] = (N3)? mem[98] :
(N0)? mem[234] : 1'b0;
assign r_data_o[97] = (N3)? mem[97] :
(N0)? mem[233] : 1'b0;
assign r_data_o[96] = (N3)? mem[96] :
(N0)? mem[232] : 1'b0;
assign r_data_o[95] = (N3)? mem[95] :
(N0)? mem[231] : 1'b0;
assign r_data_o[94] = (N3)? mem[94] :
(N0)? mem[230] : 1'b0;
assign r_data_o[93] = (N3)? mem[93] :
(N0)? mem[229] : 1'b0;
assign r_data_o[92] = (N3)? mem[92] :
(N0)? mem[228] : 1'b0;
assign r_data_o[91] = (N3)? mem[91] :
(N0)? mem[227] : 1'b0;
assign r_data_o[90] = (N3)? mem[90] :
(N0)? mem[226] : 1'b0;
assign r_data_o[89] = (N3)? mem[89] :
(N0)? mem[225] : 1'b0;
assign r_data_o[88] = (N3)? mem[88] :
(N0)? mem[224] : 1'b0;
assign r_data_o[87] = (N3)? mem[87] :
(N0)? mem[223] : 1'b0;
assign r_data_o[86] = (N3)? mem[86] :
(N0)? mem[222] : 1'b0;
assign r_data_o[85] = (N3)? mem[85] :
(N0)? mem[221] : 1'b0;
assign r_data_o[84] = (N3)? mem[84] :
(N0)? mem[220] : 1'b0;
assign r_data_o[83] = (N3)? mem[83] :
(N0)? mem[219] : 1'b0;
assign r_data_o[82] = (N3)? mem[82] :
(N0)? mem[218] : 1'b0;
assign r_data_o[81] = (N3)? mem[81] :
(N0)? mem[217] : 1'b0;
assign r_data_o[80] = (N3)? mem[80] :
(N0)? mem[216] : 1'b0;
assign r_data_o[79] = (N3)? mem[79] :
(N0)? mem[215] : 1'b0;
assign r_data_o[78] = (N3)? mem[78] :
(N0)? mem[214] : 1'b0;
assign r_data_o[77] = (N3)? mem[77] :
(N0)? mem[213] : 1'b0;
assign r_data_o[76] = (N3)? mem[76] :
(N0)? mem[212] : 1'b0;
assign r_data_o[75] = (N3)? mem[75] :
(N0)? mem[211] : 1'b0;
assign r_data_o[74] = (N3)? mem[74] :
(N0)? mem[210] : 1'b0;
assign r_data_o[73] = (N3)? mem[73] :
(N0)? mem[209] : 1'b0;
assign r_data_o[72] = (N3)? mem[72] :
(N0)? mem[208] : 1'b0;
assign r_data_o[71] = (N3)? mem[71] :
(N0)? mem[207] : 1'b0;
assign r_data_o[70] = (N3)? mem[70] :
(N0)? mem[206] : 1'b0;
assign r_data_o[69] = (N3)? mem[69] :
(N0)? mem[205] : 1'b0;
assign r_data_o[68] = (N3)? mem[68] :
(N0)? mem[204] : 1'b0;
assign r_data_o[67] = (N3)? mem[67] :
(N0)? mem[203] : 1'b0;
assign r_data_o[66] = (N3)? mem[66] :
(N0)? mem[202] : 1'b0;
assign r_data_o[65] = (N3)? mem[65] :
(N0)? mem[201] : 1'b0;
assign r_data_o[64] = (N3)? mem[64] :
(N0)? mem[200] : 1'b0;
assign r_data_o[63] = (N3)? mem[63] :
(N0)? mem[199] : 1'b0;
assign r_data_o[62] = (N3)? mem[62] :
(N0)? mem[198] : 1'b0;
assign r_data_o[61] = (N3)? mem[61] :
(N0)? mem[197] : 1'b0;
assign r_data_o[60] = (N3)? mem[60] :
(N0)? mem[196] : 1'b0;
assign r_data_o[59] = (N3)? mem[59] :
(N0)? mem[195] : 1'b0;
assign r_data_o[58] = (N3)? mem[58] :
(N0)? mem[194] : 1'b0;
assign r_data_o[57] = (N3)? mem[57] :
(N0)? mem[193] : 1'b0;
assign r_data_o[56] = (N3)? mem[56] :
(N0)? mem[192] : 1'b0;
assign r_data_o[55] = (N3)? mem[55] :
(N0)? mem[191] : 1'b0;
assign r_data_o[54] = (N3)? mem[54] :
(N0)? mem[190] : 1'b0;
assign r_data_o[53] = (N3)? mem[53] :
(N0)? mem[189] : 1'b0;
assign r_data_o[52] = (N3)? mem[52] :
(N0)? mem[188] : 1'b0;
assign r_data_o[51] = (N3)? mem[51] :
(N0)? mem[187] : 1'b0;
assign r_data_o[50] = (N3)? mem[50] :
(N0)? mem[186] : 1'b0;
assign r_data_o[49] = (N3)? mem[49] :
(N0)? mem[185] : 1'b0;
assign r_data_o[48] = (N3)? mem[48] :
(N0)? mem[184] : 1'b0;
assign r_data_o[47] = (N3)? mem[47] :
(N0)? mem[183] : 1'b0;
assign r_data_o[46] = (N3)? mem[46] :
(N0)? mem[182] : 1'b0;
assign r_data_o[45] = (N3)? mem[45] :
(N0)? mem[181] : 1'b0;
assign r_data_o[44] = (N3)? mem[44] :
(N0)? mem[180] : 1'b0;
assign r_data_o[43] = (N3)? mem[43] :
(N0)? mem[179] : 1'b0;
assign r_data_o[42] = (N3)? mem[42] :
(N0)? mem[178] : 1'b0;
assign r_data_o[41] = (N3)? mem[41] :
(N0)? mem[177] : 1'b0;
assign r_data_o[40] = (N3)? mem[40] :
(N0)? mem[176] : 1'b0;
assign r_data_o[39] = (N3)? mem[39] :
(N0)? mem[175] : 1'b0;
assign r_data_o[38] = (N3)? mem[38] :
(N0)? mem[174] : 1'b0;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[173] : 1'b0;
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[172] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[171] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[170] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[169] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[168] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[167] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[166] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[165] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[164] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[163] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[162] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[161] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[160] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[159] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[158] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[157] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[156] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[155] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[154] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[153] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[152] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[151] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[150] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[149] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[148] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[147] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[146] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[145] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[144] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[143] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[142] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[141] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[140] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[139] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[138] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[137] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[136] : 1'b0;
assign N5 = ~w_addr_i[0];
assign { N10, N9, N8, N7 } = (N1)? { w_addr_i[0:0], w_addr_i[0:0], N5, N5 } :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
always @(posedge w_clk_i) begin
if(N9) begin
{ mem[271:173], mem[136:136] } <= { w_data_i[135:37], w_data_i[0:0] };
end
if(N10) begin
{ mem[172:137] } <= { w_data_i[36:1] };
end
if(N7) begin
{ mem[135:37], mem[0:0] } <= { w_data_i[135:37], w_data_i[0:0] };
end
if(N8) begin
{ mem[36:1] } <= { w_data_i[36:1] };
end
end
endmodule |
module bp_be_instr_decoder
(
instr_i,
decode_o,
illegal_instr_o,
ret_instr_o,
csr_instr_o
);
input [31:0] instr_i;
output [50:0] decode_o;
output illegal_instr_o;
output ret_instr_o;
output csr_instr_o;
wire [50:0] decode_o;
wire illegal_instr_o,ret_instr_o,csr_instr_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,
N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,
N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,
N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,
N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,
N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,
N142,N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,
N158,N159,N160,N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,
N174,N175,N176,N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,
N190,N191,N192,N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,
N206,N207,N208,N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,
N222,N223,N224,N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,
N238,N239,N240,N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,
N254,N255,N256,N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,
N270,N271,N272,N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,
N286,N287,N288,N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,
N302,N303,N304,N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,
N318,N319,N320,N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,
N334,N335,N336,N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,
N350,N351,N352,N353,N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,
N366,N367,N368,N369,N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,
N382,N383,N384,N385,N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,
N398,N399,N400,N401,N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,
N414,N415,N416,N417,N418,N419,N420,N421,N422,N423,N424,N425,N426,N427,N428,N429,
N430,N431,N432,N433,N434,N435,N436,N437,N438,N439,N440,N441,N442,N443,N444,N445,
N446,N447,N448,N449,N450,N451,N452,N453,N454,N455,N456,N457,N458;
assign decode_o[50] = 1'b1;
assign decode_o[26] = 1'b0;
assign decode_o[28] = 1'b0;
assign decode_o[40] = 1'b0;
assign decode_o[42] = 1'b0;
assign decode_o[44] = 1'b0;
assign decode_o[47] = 1'b0;
assign decode_o[48] = 1'b0;
assign decode_o[49] = 1'b0;
assign csr_instr_o = decode_o[39];
assign ret_instr_o = decode_o[27];
assign N65 = instr_i[1] & instr_i[0];
assign N67 = instr_i[6] | N427;
assign N68 = N428 | instr_i[3];
assign N69 = N67 | N68;
assign N70 = N69 | instr_i[2];
assign N71 = N428 | N429;
assign N72 = N67 | N71;
assign N73 = N72 | instr_i[2];
assign N75 = instr_i[6] | instr_i[5];
assign N76 = N75 | N68;
assign N77 = N76 | instr_i[2];
assign N78 = N75 | N71;
assign N79 = N78 | instr_i[2];
assign N81 = N69 | N97;
assign N83 = N76 | N97;
assign N85 = N96 | N427;
assign N86 = instr_i[4] | N429;
assign N87 = N85 | N86;
assign N88 = N87 | N97;
assign N90 = instr_i[4] | instr_i[3];
assign N91 = N85 | N90;
assign N92 = N91 | N97;
assign N94 = N91 | instr_i[2];
assign N98 = N96 & N427;
assign N99 = N428 & N429;
assign N100 = N98 & N99;
assign N101 = N100 & N97;
assign N102 = N67 | N90;
assign N103 = N102 | instr_i[2];
assign N105 = N75 | N86;
assign N106 = N105 | N97;
assign N108 = N85 | N68;
assign N109 = N108 | instr_i[2];
assign N111 = instr_i[6] & instr_i[4];
assign N112 = N111 & instr_i[2];
assign N113 = N111 & instr_i[3];
assign N114 = instr_i[4] & instr_i[3];
assign N115 = N114 & instr_i[2];
assign N116 = N96 & instr_i[5];
assign N117 = N428 & instr_i[2];
assign N118 = N116 & N117;
assign N119 = N96 & N428;
assign N120 = N429 & instr_i[2];
assign N121 = N119 & N120;
assign N122 = N427 & N428;
assign N123 = N122 & N120;
assign N124 = N428 & instr_i[3];
assign N125 = N124 & N97;
assign N126 = instr_i[6] & N427;
assign N132 = N128 & N129;
assign N133 = N130 & N303;
assign N134 = N131 & N304;
assign N135 = instr_i[4] & N97;
assign N136 = N132 & N133;
assign N137 = N134 & N116;
assign N138 = N135 & N65;
assign N139 = N136 & N137;
assign N140 = N139 & N138;
assign N142 = N163 & N294;
assign N143 = N142 & N429;
assign N144 = N142 & instr_i[3];
assign N146 = N175 & N294;
assign N147 = N146 & N429;
assign N148 = N146 & instr_i[3];
assign N150 = N163 & N295;
assign N151 = N150 & N429;
assign N152 = N150 & instr_i[3];
assign N154 = N168 & N295;
assign N155 = N154 & N429;
assign N156 = N154 & instr_i[3];
assign N158 = N181 & N295;
assign N159 = N158 & N429;
assign N160 = N158 & instr_i[3];
assign N163 = N162 & N260;
assign N164 = N163 & N296;
assign N165 = N164 & N429;
assign N166 = N163 & N297;
assign N167 = N166 & N429;
assign N168 = N162 & instr_i[14];
assign N169 = N168 & N294;
assign N170 = N169 & N429;
assign N171 = N168 & N296;
assign N172 = N171 & N429;
assign N173 = N168 & N297;
assign N174 = N173 & N429;
assign N175 = instr_i[30] & N260;
assign N176 = N175 & instr_i[12];
assign N177 = instr_i[14] & N293;
assign N178 = N177 & instr_i[3];
assign N179 = instr_i[13] & instr_i[3];
assign N180 = instr_i[30] & instr_i[13];
assign N181 = instr_i[30] & instr_i[14];
assign N182 = N181 & N293;
assign N194 = N98 & N135;
assign N195 = N194 & N65;
assign N197 = N251 & N225;
assign N198 = N293 & instr_i[3];
assign N199 = N251 & N198;
assign N201 = N214 & N251;
assign N202 = N207 & N201;
assign N203 = N202 & N227;
assign N204 = N202 & N219;
assign N206 = N128 & N162;
assign N207 = N206 & N213;
assign N208 = N207 & N216;
assign N209 = N208 & N227;
assign N210 = N208 & N219;
assign N212 = N128 & instr_i[30];
assign N213 = N129 & N130;
assign N214 = N303 & N131;
assign N215 = N212 & N213;
assign N216 = N214 & N254;
assign N217 = N215 & N216;
assign N218 = N217 & N227;
assign N219 = instr_i[12] & instr_i[3];
assign N220 = N217 & N219;
assign N222 = N261 & N225;
assign N223 = N261 & N227;
assign N224 = N254 & N225;
assign N225 = N293 & N429;
assign N226 = N257 & N225;
assign N227 = instr_i[12] & N429;
assign N228 = N257 & N227;
assign N247 = instr_i[2] | N430;
assign N248 = N247 | N431;
assign N249 = N91 | N248;
assign N251 = N260 & N292;
assign N252 = N251 & N293;
assign N253 = N251 & instr_i[12];
assign N254 = instr_i[14] & N292;
assign N255 = N254 & N293;
assign N256 = N254 & instr_i[12];
assign N257 = instr_i[14] & instr_i[13];
assign N258 = N257 & N293;
assign N259 = N257 & instr_i[12];
assign N261 = N260 & instr_i[13];
assign N272 = N75 | N90;
assign N273 = N272 | N248;
assign N275 = N261 & N293;
assign N276 = N261 & instr_i[12];
assign N285 = N260 & N96;
assign N286 = instr_i[5] & N428;
assign N287 = N429 & N97;
assign N288 = N285 & N286;
assign N289 = N287 & N65;
assign N290 = N288 & N289;
assign N294 = N292 & N293;
assign N295 = N292 & instr_i[12];
assign N296 = instr_i[13] & N293;
assign N297 = instr_i[13] & instr_i[12];
assign N306 = N303 & N304;
assign N307 = N306 & N305;
assign N310 = instr_i[26] | N309;
assign N311 = N322 | N349;
assign N312 = N310 | N329;
assign N313 = N311 | N312;
assign N314 = N313 | instr_i[20];
assign N316 = N319 | instr_i[20];
assign N318 = N350 | N342;
assign N319 = N324 | N318;
assign N320 = N319 | N338;
assign N322 = N128 | N162;
assign N323 = instr_i[29] | instr_i[28];
assign N324 = N322 | N323;
assign N325 = N324 | N353;
assign N326 = N325 | instr_i[20];
assign N329 = N328 | instr_i[21];
assign N330 = N350 | N329;
assign N331 = N352 | N330;
assign N332 = N331 | N338;
assign N334 = N341 | N351;
assign N335 = N352 | N334;
assign N336 = N335 | N338;
assign N339 = N344 | N338;
assign N341 = N131 | instr_i[24];
assign N342 = instr_i[22] | instr_i[21];
assign N343 = N341 | N342;
assign N344 = N352 | N343;
assign N345 = N344 | instr_i[20];
assign N348 = instr_i[31] | instr_i[30];
assign N349 = N129 | N130;
assign N350 = instr_i[26] | instr_i[24];
assign N351 = instr_i[22] | N347;
assign N352 = N348 | N349;
assign N353 = N350 | N351;
assign N354 = N352 | N353;
assign N355 = N354 | instr_i[20];
assign N427 = ~instr_i[5];
assign N428 = ~instr_i[4];
assign N429 = ~instr_i[3];
assign N430 = ~instr_i[1];
assign N431 = ~instr_i[0];
assign N432 = N427 | instr_i[6];
assign N433 = N428 | N432;
assign N434 = N429 | N433;
assign N435 = instr_i[2] | N434;
assign N436 = N430 | N435;
assign N437 = N431 | N436;
assign N438 = ~N437;
assign N439 = instr_i[5] | instr_i[6];
assign N440 = N428 | N439;
assign N441 = N429 | N440;
assign N442 = instr_i[2] | N441;
assign N443 = N430 | N442;
assign N444 = N431 | N443;
assign N445 = ~N444;
assign { N187, N186, N185, N184 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b1, 1'b0, 1'b1 } :
(N4)? { 1'b1, 1'b1, 1'b0, 1'b1 } :
(N5)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N7)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b1, 1'b1, 1'b0 } :
(N9)? { 1'b0, 1'b1, 1'b1, 1'b1 } :
(N10)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N145;
assign N1 = N149;
assign N2 = N153;
assign N3 = N157;
assign N4 = N161;
assign N5 = N165;
assign N6 = N167;
assign N7 = N170;
assign N8 = N172;
assign N9 = N174;
assign N10 = N183;
assign N188 = (N0)? 1'b0 :
(N1)? 1'b0 :
(N2)? 1'b0 :
(N3)? 1'b0 :
(N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b0 :
(N7)? 1'b0 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 : 1'b0;
assign { N192, N191, N190, N189 } = (N11)? { N187, N186, N185, N184 } :
(N141)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N11 = N140;
assign N193 = (N11)? N188 :
(N141)? 1'b1 : 1'b0;
assign { N240, N239, N238 } = (N12)? { 1'b0, 1'b0, 1'b0 } :
(N13)? { 1'b0, 1'b0, 1'b1 } :
(N14)? { 1'b1, 1'b0, 1'b1 } :
(N15)? { 1'b1, 1'b0, 1'b1 } :
(N16)? { 1'b0, 1'b1, 1'b0 } :
(N17)? { 1'b0, 1'b1, 1'b1 } :
(N18)? { 1'b1, 1'b0, 1'b0 } :
(N19)? { 1'b1, 1'b1, 1'b0 } :
(N20)? { 1'b1, 1'b1, 1'b1 } :
(N237)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N12 = N200;
assign N13 = N205;
assign N14 = N211;
assign N15 = N221;
assign N16 = N222;
assign N17 = N223;
assign N18 = N224;
assign N19 = N226;
assign N20 = N228;
assign N241 = (N12)? 1'b0 :
(N13)? 1'b0 :
(N14)? 1'b0 :
(N15)? 1'b0 :
(N16)? 1'b0 :
(N17)? 1'b0 :
(N18)? 1'b0 :
(N19)? 1'b0 :
(N20)? 1'b0 :
(N237)? 1'b1 : 1'b0;
assign { N245, N244, N243, N242 } = (N21)? { N221, N240, N239, N238 } :
(N196)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N21 = N195;
assign N246 = (N21)? N241 :
(N196)? 1'b1 : 1'b0;
assign { N265, N264, N263, N262 } = (N22)? { 1'b1, 1'b1, 1'b0, 1'b0 } :
(N23)? { 1'b1, 1'b1, 1'b1, 1'b0 } :
(N24)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1, 1'b0 } :
(N26)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b1, 1'b0, 1'b1, 1'b1 } :
(N28)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N22 = N252;
assign N23 = N253;
assign N24 = N255;
assign N25 = N256;
assign N26 = N258;
assign N27 = N259;
assign N28 = N261;
assign N266 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N27)? 1'b0 :
(N28)? 1'b1 : 1'b0;
assign { N270, N269, N268, N267 } = (N29)? { N265, N264, N263, N262 } :
(N30)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N29 = N250;
assign N30 = N249;
assign N271 = (N29)? N266 :
(N30)? 1'b1 : 1'b0;
assign { N279, N278, N277 } = (N22)? { 1'b0, 1'b0, 1'b0 } :
(N23)? { 1'b0, 1'b0, 1'b1 } :
(N31)? { 1'b0, 1'b1, 1'b0 } :
(N24)? { 1'b1, 1'b0, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1 } :
(N26)? { 1'b1, 1'b1, 1'b0 } :
(N32)? { 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N31 = N275;
assign N32 = N276;
assign N280 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N31)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N32)? 1'b0 :
(N27)? 1'b1 : 1'b0;
assign { N283, N282, N281 } = (N33)? { N279, N278, N277 } :
(N34)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N33 = N274;
assign N34 = N273;
assign N284 = (N33)? N280 :
(N34)? 1'b1 : 1'b0;
assign { N299, N298 } = (N35)? { 1'b0, 1'b0 } :
(N36)? { 1'b0, 1'b1 } :
(N37)? { 1'b1, 1'b0 } :
(N38)? { 1'b1, 1'b1 } : 1'b0;
assign N35 = N294;
assign N36 = N295;
assign N37 = N296;
assign N38 = N297;
assign { N301, N300 } = (N39)? { N299, N298 } :
(N291)? { 1'b0, 1'b0 } : 1'b0;
assign N39 = N290;
assign N302 = ~N290;
assign N366 = (N40)? 1'b1 :
(N41)? 1'b1 :
(N42)? 1'b1 :
(N43)? 1'b1 :
(N44)? 1'b1 :
(N45)? 1'b1 :
(N46)? 1'b1 :
(N47)? 1'b1 :
(N48)? 1'b0 :
(N365)? 1'b0 : 1'b0;
assign N40 = N315;
assign N41 = N317;
assign N42 = N321;
assign N43 = N327;
assign N44 = N333;
assign N45 = N337;
assign N46 = N340;
assign N47 = N346;
assign N48 = N356;
assign N367 = (N40)? 1'b0 :
(N41)? 1'b0 :
(N42)? 1'b0 :
(N43)? 1'b0 :
(N44)? 1'b0 :
(N45)? 1'b0 :
(N46)? 1'b0 :
(N47)? 1'b0 :
(N48)? 1'b0 :
(N365)? 1'b1 : 1'b0;
assign { N377, N376, N375, N374, N373, N372, N371, N370, N369, N368 } = (N49)? { N366, N315, N317, N321, N327, N333, N337, N340, N346, N356 } :
(N308)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N49 = N307;
assign N378 = (N49)? N367 :
(N308)? 1'b1 : 1'b0;
assign { N399, N398, N397, N385, N384, N383, N382, N381, N380, N379 } = (N50)? { 1'b1, 1'b0, 1'b1, N438, N192, N191, N190, N189, 1'b0, 1'b0 } :
(N51)? { 1'b1, 1'b0, 1'b1, N445, N245, N244, N243, N242, 1'b1, 1'b0 } :
(N52)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N53)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N54)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N55)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N56)? { 1'b1, 1'b0, 1'b0, 1'b0, N270, N269, N268, N267, 1'b0, 1'b0 } :
(N57)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, N283, N282, N281, 1'b0, 1'b0 } :
(N58)? { 1'b0, 1'b1, 1'b0, 1'b0, N290, 1'b0, N301, N300, 1'b0, 1'b0 } :
(N59)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N60)? { 1'b0, 1'b1, N377, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N50 = N74;
assign N51 = N80;
assign N52 = N82;
assign N53 = N84;
assign N54 = N89;
assign N55 = N93;
assign N56 = N95;
assign N57 = N101;
assign N58 = N104;
assign N59 = N107;
assign N60 = N110;
assign N61 = N127;
assign { N396, N395, N394, N393, N392, N391, N390, N389, N388, N387 } = (N60)? { N377, N376, N375, N374, N373, N372, N371, N370, N369, N368 } :
(N386)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N400 = (N50)? N193 :
(N51)? N246 :
(N52)? 1'b0 :
(N53)? 1'b0 :
(N54)? 1'b0 :
(N55)? 1'b0 :
(N56)? N271 :
(N57)? N284 :
(N58)? N302 :
(N59)? 1'b0 :
(N60)? N378 :
(N61)? 1'b1 : 1'b0;
assign { N425, N424, N423, N422, N421, N420, N419, N418, N417, N416, N415, N414, N413, N412, N411, N410, N409, N408, N407, N406, N405, N404, N403, N402, N401 } = (N62)? { N399, N398, N397, N396, N395, N394, N393, N392, N391, N390, N389, N388, N104, N101, N387, N95, N385, N384, N383, N382, N381, N84, N380, N93, N379 } :
(N66)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N62 = N65;
assign illegal_instr_o = (N62)? N400 :
(N66)? 1'b1 : 1'b0;
assign { decode_o[45:45], decode_o[43:43], decode_o[41:41], decode_o[39:29], decode_o[27:27], decode_o[25:0] } = (N63)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N64)? { N425, N424, N423, N422, N421, N420, N419, N418, N417, N416, N415, N414, N413, N412, N411, N401, N410, N409, N408, N407, N406, N405, instr_i[19:15], instr_i[24:20], instr_i[11:7], N404, N403, N402, N401 } : 1'b0;
assign N63 = decode_o[46];
assign N64 = N426;
assign N66 = ~N65;
assign N74 = N446 | N447;
assign N446 = ~N70;
assign N447 = ~N73;
assign N80 = N448 | N449;
assign N448 = ~N77;
assign N449 = ~N79;
assign N82 = ~N81;
assign N84 = ~N83;
assign N89 = ~N88;
assign N93 = ~N92;
assign N95 = ~N94;
assign N96 = ~instr_i[6];
assign N97 = ~instr_i[2];
assign N104 = ~N103;
assign N107 = ~N106;
assign N110 = ~N109;
assign N127 = N112 | N455;
assign N455 = N113 | N454;
assign N454 = N115 | N453;
assign N453 = N118 | N452;
assign N452 = N121 | N451;
assign N451 = N123 | N450;
assign N450 = N125 | N126;
assign N128 = ~instr_i[31];
assign N129 = ~instr_i[29];
assign N130 = ~instr_i[28];
assign N131 = ~instr_i[26];
assign N141 = ~N140;
assign N145 = N143 | N144;
assign N149 = N147 | N148;
assign N153 = N151 | N152;
assign N157 = N155 | N156;
assign N161 = N159 | N160;
assign N162 = ~instr_i[30];
assign N183 = N176 | N458;
assign N458 = N178 | N457;
assign N457 = N179 | N456;
assign N456 = N180 | N182;
assign N196 = ~N195;
assign N200 = N197 | N199;
assign N205 = N203 | N204;
assign N211 = N209 | N210;
assign N221 = N218 | N220;
assign N229 = N205 | N200;
assign N230 = N211 | N229;
assign N231 = N221 | N230;
assign N232 = N222 | N231;
assign N233 = N223 | N232;
assign N234 = N224 | N233;
assign N235 = N226 | N234;
assign N236 = N228 | N235;
assign N237 = ~N236;
assign N250 = ~N249;
assign N260 = ~instr_i[14];
assign N274 = ~N273;
assign N291 = ~N290;
assign N292 = ~instr_i[13];
assign N293 = ~instr_i[12];
assign N303 = ~instr_i[27];
assign N304 = ~instr_i[25];
assign N305 = ~instr_i[23];
assign N308 = ~N307;
assign N309 = ~instr_i[24];
assign N315 = ~N314;
assign N317 = ~N316;
assign N321 = ~N320;
assign N327 = ~N326;
assign N328 = ~instr_i[22];
assign N333 = ~N332;
assign N337 = ~N336;
assign N338 = ~instr_i[20];
assign N340 = ~N339;
assign N346 = ~N345;
assign N347 = ~instr_i[21];
assign N356 = ~N355;
assign N357 = N317 | N315;
assign N358 = N321 | N357;
assign N359 = N327 | N358;
assign N360 = N333 | N359;
assign N361 = N337 | N360;
assign N362 = N340 | N361;
assign N363 = N346 | N362;
assign N364 = N356 | N363;
assign N365 = ~N364;
assign N386 = N109;
assign N426 = ~illegal_instr_o;
assign decode_o[46] = illegal_instr_o;
endmodule |
module bsg_dff_width_p320
(
clk_i,
data_i,
data_o
);
input [319:0] data_i;
output [319:0] data_o;
input clk_i;
reg [319:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[319:0] } <= { data_i[319:0] };
end
end
endmodule |
Subsets and Splits