module
stringlengths 21
82.9k
|
|---|
module bsg_reduce_width_p5_and_p1_harden_p1
(
i,
o
);
input [4:0] i;
output o;
wire o,N0,N1,N2;
assign o = N2 & i[0];
assign N2 = N1 & i[1];
assign N1 = N0 & i[2];
assign N0 = i[4] & i[3];
endmodule |
module bsg_dff_reset_width_p48
(
clk_i,
reset_i,
data_i,
data_o
);
input [47:0] data_i;
output [47:0] data_o;
input clk_i;
input reset_i;
wire [47:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50;
reg data_o_47_sv2v_reg,data_o_46_sv2v_reg,data_o_45_sv2v_reg,data_o_44_sv2v_reg,
data_o_43_sv2v_reg,data_o_42_sv2v_reg,data_o_41_sv2v_reg,data_o_40_sv2v_reg,
data_o_39_sv2v_reg,data_o_38_sv2v_reg,data_o_37_sv2v_reg,data_o_36_sv2v_reg,
data_o_35_sv2v_reg,data_o_34_sv2v_reg,data_o_33_sv2v_reg,data_o_32_sv2v_reg,
data_o_31_sv2v_reg,data_o_30_sv2v_reg,data_o_29_sv2v_reg,data_o_28_sv2v_reg,data_o_27_sv2v_reg,
data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,
data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,
data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,
data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,
data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,
data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_47_sv2v_reg <= N50;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_46_sv2v_reg <= N49;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_45_sv2v_reg <= N48;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_44_sv2v_reg <= N47;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_43_sv2v_reg <= N46;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_42_sv2v_reg <= N45;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_41_sv2v_reg <= N44;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_40_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_39_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_38_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_round_robin_arb_04
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
sel_one_hot_o,
v_o,
tag_o,
yumi_i
);
input [3:0] reqs_i;
output [3:0] grants_o;
output [3:0] sel_one_hot_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [3:0] grants_o,sel_one_hot_o;
wire [1:0] tag_o,last_r;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103;
reg last_r_1_sv2v_reg,last_r_0_sv2v_reg;
assign last_r[1] = last_r_1_sv2v_reg;
assign last_r[0] = last_r_0_sv2v_reg;
always @(posedge clk_i) begin
if(N101) begin
last_r_1_sv2v_reg <= N99;
end
end
always @(posedge clk_i) begin
if(N101) begin
last_r_0_sv2v_reg <= N98;
end
end
assign N79 = N0 & N1 & (N2 & N3);
assign N0 = ~reqs_i[1];
assign N1 = ~reqs_i[2];
assign N2 = ~reqs_i[0];
assign N3 = ~reqs_i[3];
assign N80 = reqs_i[1] & N4 & N5;
assign N4 = ~last_r[0];
assign N5 = ~last_r[1];
assign N81 = N6 & reqs_i[2] & (N7 & N8);
assign N6 = ~reqs_i[1];
assign N7 = ~last_r[0];
assign N8 = ~last_r[1];
assign N82 = N9 & N10 & (reqs_i[3] & N11) & N12;
assign N9 = ~reqs_i[1];
assign N10 = ~reqs_i[2];
assign N11 = ~last_r[0];
assign N12 = ~last_r[1];
assign N13 = N17 & N18;
assign N14 = N13 & reqs_i[0];
assign N15 = N14 & N19;
assign N16 = N15 & N20;
assign N83 = N16 & N21;
assign N17 = ~reqs_i[1];
assign N18 = ~reqs_i[2];
assign N19 = ~reqs_i[3];
assign N20 = ~last_r[0];
assign N21 = ~last_r[1];
assign N84 = reqs_i[2] & last_r[0] & N22;
assign N22 = ~last_r[1];
assign N85 = N23 & reqs_i[3] & (last_r[0] & N24);
assign N23 = ~reqs_i[2];
assign N24 = ~last_r[1];
assign N86 = N25 & reqs_i[0] & (N26 & last_r[0]) & N27;
assign N25 = ~reqs_i[2];
assign N26 = ~reqs_i[3];
assign N27 = ~last_r[1];
assign N28 = reqs_i[1] & N32;
assign N29 = N28 & N33;
assign N30 = N29 & N34;
assign N31 = N30 & last_r[0];
assign N87 = N31 & N35;
assign N32 = ~reqs_i[2];
assign N33 = ~reqs_i[0];
assign N34 = ~reqs_i[3];
assign N35 = ~last_r[1];
assign N88 = reqs_i[3] & N36 & last_r[1];
assign N36 = ~last_r[0];
assign N89 = reqs_i[0] & N37 & (N38 & last_r[1]);
assign N37 = ~reqs_i[3];
assign N38 = ~last_r[0];
assign N90 = reqs_i[1] & N39 & (N40 & N41) & last_r[1];
assign N39 = ~reqs_i[0];
assign N40 = ~reqs_i[3];
assign N41 = ~last_r[0];
assign N42 = N46 & reqs_i[2];
assign N43 = N42 & N47;
assign N44 = N43 & N48;
assign N45 = N44 & N49;
assign N91 = N45 & last_r[1];
assign N46 = ~reqs_i[1];
assign N47 = ~reqs_i[0];
assign N48 = ~reqs_i[3];
assign N49 = ~last_r[0];
assign N92 = reqs_i[0] & last_r[0] & last_r[1];
assign N93 = reqs_i[1] & N50 & (last_r[0] & last_r[1]);
assign N50 = ~reqs_i[0];
assign N94 = N51 & reqs_i[2] & (N52 & last_r[0]) & last_r[1];
assign N51 = ~reqs_i[1];
assign N52 = ~reqs_i[0];
assign N53 = N57 & N58;
assign N54 = N53 & N59;
assign N55 = N54 & reqs_i[3];
assign N56 = N55 & last_r[0];
assign N95 = N56 & last_r[1];
assign N57 = ~reqs_i[1];
assign N58 = ~reqs_i[2];
assign N59 = ~reqs_i[0];
assign sel_one_hot_o = (N60)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N62)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N63)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N64)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N65)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N66)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N67)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N68)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N69)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N70)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N71)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N72)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N73)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N74)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N75)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N76)? { 1'b1, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N60 = N79;
assign N61 = N80;
assign N62 = N81;
assign N63 = N82;
assign N64 = N83;
assign N65 = N84;
assign N66 = N85;
assign N67 = N86;
assign N68 = N87;
assign N69 = N88;
assign N70 = N89;
assign N71 = N90;
assign N72 = N91;
assign N73 = N92;
assign N74 = N93;
assign N75 = N94;
assign N76 = N95;
assign tag_o = (N60)? { 1'b0, 1'b0 } :
(N61)? { 1'b0, 1'b1 } :
(N62)? { 1'b1, 1'b0 } :
(N63)? { 1'b1, 1'b1 } :
(N64)? { 1'b0, 1'b0 } :
(N65)? { 1'b1, 1'b0 } :
(N66)? { 1'b1, 1'b1 } :
(N67)? { 1'b0, 1'b0 } :
(N68)? { 1'b0, 1'b1 } :
(N69)? { 1'b1, 1'b1 } :
(N70)? { 1'b0, 1'b0 } :
(N71)? { 1'b0, 1'b1 } :
(N72)? { 1'b1, 1'b0 } :
(N73)? { 1'b0, 1'b0 } :
(N74)? { 1'b0, 1'b1 } :
(N75)? { 1'b1, 1'b0 } :
(N76)? { 1'b1, 1'b1 } : 1'b0;
assign { N99, N98 } = (N77)? { 1'b0, 1'b0 } :
(N78)? tag_o : 1'b0;
assign N77 = reset_i;
assign N78 = N97;
assign grants_o[3] = sel_one_hot_o[3] & grants_en_i;
assign grants_o[2] = sel_one_hot_o[2] & grants_en_i;
assign grants_o[1] = sel_one_hot_o[1] & grants_en_i;
assign grants_o[0] = sel_one_hot_o[0] & grants_en_i;
assign v_o = N103 | reqs_i[0];
assign N103 = N102 | reqs_i[1];
assign N102 = reqs_i[3] | reqs_i[2];
assign N96 = ~yumi_i;
assign N97 = ~reset_i;
assign N100 = N96 & N97;
assign N101 = ~N100;
endmodule |
module bsg_circular_ptr_slots_p16_max_add_p15
(
clk,
reset_i,
add_i,
o,
n_o
);
input [3:0] add_i;
output [3:0] o;
output [3:0] n_o;
input clk;
input reset_i;
wire [3:0] o,n_o;
reg o_3_sv2v_reg,o_2_sv2v_reg,o_1_sv2v_reg,o_0_sv2v_reg;
assign o[3] = o_3_sv2v_reg;
assign o[2] = o_2_sv2v_reg;
assign o[1] = o_1_sv2v_reg;
assign o[0] = o_0_sv2v_reg;
always @(posedge clk) begin
if(reset_i) begin
o_3_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_3_sv2v_reg <= n_o[3];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_2_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_2_sv2v_reg <= n_o[2];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_1_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_1_sv2v_reg <= n_o[1];
end
end
always @(posedge clk) begin
if(reset_i) begin
o_0_sv2v_reg <= 1'b0;
end else if(1'b1) begin
o_0_sv2v_reg <= n_o[0];
end
end
assign n_o = o + add_i;
endmodule |
module bp_me_cce_id_to_cord_05
(
cce_id_i,
cce_cord_o,
cce_cid_o
);
input [3:0] cce_id_i;
output [4:0] cce_cord_o;
output [1:0] cce_cid_o;
wire [4:0] cce_cord_o;
wire [1:0] cce_cid_o;
wire N0,N1,cce_cord_o_0_,N2,N3,N4,N5,N6;
assign cce_cord_o[1] = 1'b0;
assign cce_cid_o[0] = 1'b0;
assign cce_cid_o[1] = 1'b0;
assign cce_cord_o_0_ = cce_id_i[0];
assign cce_cord_o[0] = cce_cord_o_0_;
assign { N5, N4, N3 } = 1'b1 + cce_id_i[3:1];
assign cce_cord_o[4:2] = (N0)? { N5, N4, N3 } :
(N1)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N2;
assign N1 = N6;
assign N2 = ~N6;
assign N6 = cce_id_i[3] | cce_id_i[2];
endmodule |
module bsg_chip_swizzle_adapter
(
guts_ci_clk_o,
guts_ci_v_o,
guts_ci_data_o,
guts_ci_tkn_i,
guts_ci2_clk_o,
guts_ci2_v_o,
guts_ci2_data_o,
guts_ci2_tkn_i,
guts_co_clk_i,
guts_co_v_i,
guts_co_data_i,
guts_co_tkn_o,
guts_co2_clk_i,
guts_co2_v_i,
guts_co2_data_i,
guts_co2_tkn_o,
port_ci_clk_i,
port_ci_v_i,
port_ci_data_i,
port_ci_tkn_o,
port_co_clk_i,
port_co_v_i,
port_co_data_i,
port_co_tkn_o,
port_ci2_clk_o,
port_ci2_v_o,
port_ci2_data_o,
port_ci2_tkn_i,
port_co2_clk_o,
port_co2_v_o,
port_co2_data_o,
port_co2_tkn_i
);
output [8:0] guts_ci_data_o;
output [8:0] guts_ci2_data_o;
input [8:0] guts_co_data_i;
input [8:0] guts_co2_data_i;
input [8:0] port_ci_data_i;
input [8:0] port_co_data_i;
output [8:0] port_ci2_data_o;
output [8:0] port_co2_data_o;
input guts_ci_tkn_i;
input guts_ci2_tkn_i;
input guts_co_clk_i;
input guts_co_v_i;
input guts_co2_clk_i;
input guts_co2_v_i;
input port_ci_clk_i;
input port_ci_v_i;
input port_co_clk_i;
input port_co_v_i;
input port_ci2_tkn_i;
input port_co2_tkn_i;
output guts_ci_clk_o;
output guts_ci_v_o;
output guts_ci2_clk_o;
output guts_ci2_v_o;
output guts_co_tkn_o;
output guts_co2_tkn_o;
output port_ci_tkn_o;
output port_co_tkn_o;
output port_ci2_clk_o;
output port_ci2_v_o;
output port_co2_clk_o;
output port_co2_v_o;
wire [8:0] guts_ci_data_o,guts_ci2_data_o,port_ci2_data_o,port_co2_data_o;
wire guts_ci_clk_o,guts_ci_v_o,guts_ci2_clk_o,guts_ci2_v_o,guts_co_tkn_o,
guts_co2_tkn_o,port_ci_tkn_o,port_co_tkn_o,port_ci2_clk_o,port_ci2_v_o,port_co2_clk_o,
port_co2_v_o,guts_co_data_i_4_,guts_co2_data_i_4_;
assign guts_ci_clk_o = port_ci_clk_i;
assign guts_ci_v_o = port_ci_v_i;
assign guts_ci_data_o[8] = port_ci_data_i[8];
assign guts_ci_data_o[7] = port_ci_data_i[7];
assign guts_ci_data_o[6] = port_ci_data_i[6];
assign guts_ci_data_o[5] = port_ci_data_i[5];
assign guts_ci_data_o[4] = port_ci_data_i[4];
assign guts_ci_data_o[3] = port_ci_data_i[3];
assign guts_ci_data_o[2] = port_ci_data_i[2];
assign guts_ci_data_o[1] = port_ci_data_i[1];
assign guts_ci_data_o[0] = port_ci_data_i[0];
assign guts_ci2_clk_o = port_co_clk_i;
assign guts_ci2_v_o = port_co_v_i;
assign guts_ci2_data_o[8] = port_co_data_i[8];
assign guts_ci2_data_o[7] = port_co_data_i[7];
assign guts_ci2_data_o[6] = port_co_data_i[6];
assign guts_ci2_data_o[5] = port_co_data_i[5];
assign guts_ci2_data_o[4] = port_co_data_i[4];
assign guts_ci2_data_o[3] = port_co_data_i[3];
assign guts_ci2_data_o[2] = port_co_data_i[2];
assign guts_ci2_data_o[1] = port_co_data_i[1];
assign guts_ci2_data_o[0] = port_co_data_i[0];
assign guts_co_data_i_4_ = guts_co_data_i[4];
assign port_ci2_v_o = guts_co_data_i_4_;
assign guts_co_tkn_o = port_ci2_tkn_i;
assign guts_co2_data_i_4_ = guts_co2_data_i[4];
assign port_co2_v_o = guts_co2_data_i_4_;
assign guts_co2_tkn_o = port_co2_tkn_i;
assign port_ci_tkn_o = guts_ci_tkn_i;
assign port_co_tkn_o = guts_ci2_tkn_i;
assign port_ci2_clk_o = guts_co_clk_i;
assign port_ci2_data_o[8] = guts_co_data_i[0];
assign port_ci2_data_o[7] = guts_co_data_i[1];
assign port_ci2_data_o[6] = guts_co_data_i[2];
assign port_ci2_data_o[5] = guts_co_v_i;
assign port_ci2_data_o[4] = guts_co_data_i[3];
assign port_ci2_data_o[3] = guts_co_data_i[8];
assign port_ci2_data_o[2] = guts_co_data_i[7];
assign port_ci2_data_o[1] = guts_co_data_i[5];
assign port_ci2_data_o[0] = guts_co_data_i[6];
assign port_co2_clk_o = guts_co2_clk_i;
assign port_co2_data_o[8] = guts_co2_data_i[0];
assign port_co2_data_o[7] = guts_co2_data_i[1];
assign port_co2_data_o[6] = guts_co2_data_i[2];
assign port_co2_data_o[5] = guts_co2_data_i[3];
assign port_co2_data_o[4] = guts_co2_data_i[5];
assign port_co2_data_o[3] = guts_co2_data_i[6];
assign port_co2_data_o[2] = guts_co2_v_i;
assign port_co2_data_o[1] = guts_co2_data_i[7];
assign port_co2_data_o[0] = guts_co2_data_i[8];
endmodule |
module bsg_link_oddr_phy_width_p9
(
reset_i,
clk_i,
data_i,
ready_o,
data_r_o,
clk_r_o
);
input [17:0] data_i;
output [8:0] data_r_o;
input reset_i;
input clk_i;
output ready_o;
output clk_r_o;
wire [8:0] data_r_o;
wire ready_o,clk_r_o,N0,N1,N2,N3,N4,N5,odd_r,N6,N7,N8,reset_i_r,N9,N10,clk_r,N11,N12,
N13,N14,N15,N16,N17,N18,N19,N20,N21;
wire [17:0] data_i_r;
reg data_i_r_17_sv2v_reg,data_i_r_16_sv2v_reg,data_i_r_15_sv2v_reg,
data_i_r_14_sv2v_reg,data_i_r_13_sv2v_reg,data_i_r_12_sv2v_reg,data_i_r_11_sv2v_reg,
data_i_r_10_sv2v_reg,data_i_r_9_sv2v_reg,data_i_r_8_sv2v_reg,data_i_r_7_sv2v_reg,
data_i_r_6_sv2v_reg,data_i_r_5_sv2v_reg,data_i_r_4_sv2v_reg,data_i_r_3_sv2v_reg,
data_i_r_2_sv2v_reg,data_i_r_1_sv2v_reg,data_i_r_0_sv2v_reg,odd_r_sv2v_reg,
reset_i_r_sv2v_reg,clk_r_sv2v_reg,clk_r_o_sv2v_reg,data_r_o_8_sv2v_reg,data_r_o_7_sv2v_reg,
data_r_o_6_sv2v_reg,data_r_o_5_sv2v_reg,data_r_o_4_sv2v_reg,data_r_o_3_sv2v_reg,
data_r_o_2_sv2v_reg,data_r_o_1_sv2v_reg,data_r_o_0_sv2v_reg;
assign data_i_r[17] = data_i_r_17_sv2v_reg;
assign data_i_r[16] = data_i_r_16_sv2v_reg;
assign data_i_r[15] = data_i_r_15_sv2v_reg;
assign data_i_r[14] = data_i_r_14_sv2v_reg;
assign data_i_r[13] = data_i_r_13_sv2v_reg;
assign data_i_r[12] = data_i_r_12_sv2v_reg;
assign data_i_r[11] = data_i_r_11_sv2v_reg;
assign data_i_r[10] = data_i_r_10_sv2v_reg;
assign data_i_r[9] = data_i_r_9_sv2v_reg;
assign data_i_r[8] = data_i_r_8_sv2v_reg;
assign data_i_r[7] = data_i_r_7_sv2v_reg;
assign data_i_r[6] = data_i_r_6_sv2v_reg;
assign data_i_r[5] = data_i_r_5_sv2v_reg;
assign data_i_r[4] = data_i_r_4_sv2v_reg;
assign data_i_r[3] = data_i_r_3_sv2v_reg;
assign data_i_r[2] = data_i_r_2_sv2v_reg;
assign data_i_r[1] = data_i_r_1_sv2v_reg;
assign data_i_r[0] = data_i_r_0_sv2v_reg;
assign odd_r = odd_r_sv2v_reg;
assign reset_i_r = reset_i_r_sv2v_reg;
assign clk_r = clk_r_sv2v_reg;
assign clk_r_o = clk_r_o_sv2v_reg;
assign data_r_o[8] = data_r_o_8_sv2v_reg;
assign data_r_o[7] = data_r_o_7_sv2v_reg;
assign data_r_o[6] = data_r_o_6_sv2v_reg;
assign data_r_o[5] = data_r_o_5_sv2v_reg;
assign data_r_o[4] = data_r_o_4_sv2v_reg;
assign data_r_o[3] = data_r_o_3_sv2v_reg;
assign data_r_o[2] = data_r_o_2_sv2v_reg;
assign data_r_o[1] = data_r_o_1_sv2v_reg;
assign data_r_o[0] = data_r_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N6) begin
data_i_r_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(N6) begin
data_i_r_0_sv2v_reg <= data_i[0];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
odd_r_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
reset_i_r_sv2v_reg <= reset_i;
end
end
always @(posedge N9) begin
if(1'b1) begin
clk_r_sv2v_reg <= N12;
end
end
always @(posedge N9) begin
if(1'b1) begin
clk_r_o_sv2v_reg <= clk_r;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_8_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_7_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_6_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_5_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_4_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_3_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_2_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_1_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_r_o_0_sv2v_reg <= N13;
end
end
assign N8 = (N0)? 1'b0 :
(N1)? N6 : 1'b0;
assign N0 = reset_i;
assign N1 = N7;
assign N12 = (N2)? 1'b0 :
(N3)? N11 : 1'b0;
assign N2 = reset_i_r;
assign N3 = N10;
assign { N21, N20, N19, N18, N17, N16, N15, N14, N13 } = (N4)? data_i_r[8:0] :
(N5)? data_i_r[17:9] : 1'b0;
assign N4 = odd_r;
assign N5 = N6;
assign ready_o = ~odd_r;
assign N6 = ~odd_r;
assign N7 = ~reset_i;
assign N9 = ~clk_i;
assign N10 = ~reset_i_r;
assign N11 = ~clk_r;
endmodule |
module bsg_swap_width_p64
(
data_i,
swap_i,
data_o
);
input [127:0] data_i;
output [127:0] data_o;
input swap_i;
wire [127:0] data_o;
wire N0,N1,N2;
assign data_o = (N0)? { data_i[63:0], data_i[127:64] } :
(N1)? data_i : 1'b0;
assign N0 = swap_i;
assign N1 = N2;
assign N2 = ~swap_i;
endmodule |
module bsg_mux_one_hot_width_p128_els_p3
(
data_i,
sel_one_hot_i,
data_o
);
input [383:0] data_i;
input [2:0] sel_one_hot_i;
output [127:0] data_o;
wire [127:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127;
wire [383:0] data_masked;
assign data_masked[127] = data_i[127] & sel_one_hot_i[0];
assign data_masked[126] = data_i[126] & sel_one_hot_i[0];
assign data_masked[125] = data_i[125] & sel_one_hot_i[0];
assign data_masked[124] = data_i[124] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[0];
assign data_masked[122] = data_i[122] & sel_one_hot_i[0];
assign data_masked[121] = data_i[121] & sel_one_hot_i[0];
assign data_masked[120] = data_i[120] & sel_one_hot_i[0];
assign data_masked[119] = data_i[119] & sel_one_hot_i[0];
assign data_masked[118] = data_i[118] & sel_one_hot_i[0];
assign data_masked[117] = data_i[117] & sel_one_hot_i[0];
assign data_masked[116] = data_i[116] & sel_one_hot_i[0];
assign data_masked[115] = data_i[115] & sel_one_hot_i[0];
assign data_masked[114] = data_i[114] & sel_one_hot_i[0];
assign data_masked[113] = data_i[113] & sel_one_hot_i[0];
assign data_masked[112] = data_i[112] & sel_one_hot_i[0];
assign data_masked[111] = data_i[111] & sel_one_hot_i[0];
assign data_masked[110] = data_i[110] & sel_one_hot_i[0];
assign data_masked[109] = data_i[109] & sel_one_hot_i[0];
assign data_masked[108] = data_i[108] & sel_one_hot_i[0];
assign data_masked[107] = data_i[107] & sel_one_hot_i[0];
assign data_masked[106] = data_i[106] & sel_one_hot_i[0];
assign data_masked[105] = data_i[105] & sel_one_hot_i[0];
assign data_masked[104] = data_i[104] & sel_one_hot_i[0];
assign data_masked[103] = data_i[103] & sel_one_hot_i[0];
assign data_masked[102] = data_i[102] & sel_one_hot_i[0];
assign data_masked[101] = data_i[101] & sel_one_hot_i[0];
assign data_masked[100] = data_i[100] & sel_one_hot_i[0];
assign data_masked[99] = data_i[99] & sel_one_hot_i[0];
assign data_masked[98] = data_i[98] & sel_one_hot_i[0];
assign data_masked[97] = data_i[97] & sel_one_hot_i[0];
assign data_masked[96] = data_i[96] & sel_one_hot_i[0];
assign data_masked[95] = data_i[95] & sel_one_hot_i[0];
assign data_masked[94] = data_i[94] & sel_one_hot_i[0];
assign data_masked[93] = data_i[93] & sel_one_hot_i[0];
assign data_masked[92] = data_i[92] & sel_one_hot_i[0];
assign data_masked[91] = data_i[91] & sel_one_hot_i[0];
assign data_masked[90] = data_i[90] & sel_one_hot_i[0];
assign data_masked[89] = data_i[89] & sel_one_hot_i[0];
assign data_masked[88] = data_i[88] & sel_one_hot_i[0];
assign data_masked[87] = data_i[87] & sel_one_hot_i[0];
assign data_masked[86] = data_i[86] & sel_one_hot_i[0];
assign data_masked[85] = data_i[85] & sel_one_hot_i[0];
assign data_masked[84] = data_i[84] & sel_one_hot_i[0];
assign data_masked[83] = data_i[83] & sel_one_hot_i[0];
assign data_masked[82] = data_i[82] & sel_one_hot_i[0];
assign data_masked[81] = data_i[81] & sel_one_hot_i[0];
assign data_masked[80] = data_i[80] & sel_one_hot_i[0];
assign data_masked[79] = data_i[79] & sel_one_hot_i[0];
assign data_masked[78] = data_i[78] & sel_one_hot_i[0];
assign data_masked[77] = data_i[77] & sel_one_hot_i[0];
assign data_masked[76] = data_i[76] & sel_one_hot_i[0];
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[255] = data_i[255] & sel_one_hot_i[1];
assign data_masked[254] = data_i[254] & sel_one_hot_i[1];
assign data_masked[253] = data_i[253] & sel_one_hot_i[1];
assign data_masked[252] = data_i[252] & sel_one_hot_i[1];
assign data_masked[251] = data_i[251] & sel_one_hot_i[1];
assign data_masked[250] = data_i[250] & sel_one_hot_i[1];
assign data_masked[249] = data_i[249] & sel_one_hot_i[1];
assign data_masked[248] = data_i[248] & sel_one_hot_i[1];
assign data_masked[247] = data_i[247] & sel_one_hot_i[1];
assign data_masked[246] = data_i[246] & sel_one_hot_i[1];
assign data_masked[245] = data_i[245] & sel_one_hot_i[1];
assign data_masked[244] = data_i[244] & sel_one_hot_i[1];
assign data_masked[243] = data_i[243] & sel_one_hot_i[1];
assign data_masked[242] = data_i[242] & sel_one_hot_i[1];
assign data_masked[241] = data_i[241] & sel_one_hot_i[1];
assign data_masked[240] = data_i[240] & sel_one_hot_i[1];
assign data_masked[239] = data_i[239] & sel_one_hot_i[1];
assign data_masked[238] = data_i[238] & sel_one_hot_i[1];
assign data_masked[237] = data_i[237] & sel_one_hot_i[1];
assign data_masked[236] = data_i[236] & sel_one_hot_i[1];
assign data_masked[235] = data_i[235] & sel_one_hot_i[1];
assign data_masked[234] = data_i[234] & sel_one_hot_i[1];
assign data_masked[233] = data_i[233] & sel_one_hot_i[1];
assign data_masked[232] = data_i[232] & sel_one_hot_i[1];
assign data_masked[231] = data_i[231] & sel_one_hot_i[1];
assign data_masked[230] = data_i[230] & sel_one_hot_i[1];
assign data_masked[229] = data_i[229] & sel_one_hot_i[1];
assign data_masked[228] = data_i[228] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[1];
assign data_masked[226] = data_i[226] & sel_one_hot_i[1];
assign data_masked[225] = data_i[225] & sel_one_hot_i[1];
assign data_masked[224] = data_i[224] & sel_one_hot_i[1];
assign data_masked[223] = data_i[223] & sel_one_hot_i[1];
assign data_masked[222] = data_i[222] & sel_one_hot_i[1];
assign data_masked[221] = data_i[221] & sel_one_hot_i[1];
assign data_masked[220] = data_i[220] & sel_one_hot_i[1];
assign data_masked[219] = data_i[219] & sel_one_hot_i[1];
assign data_masked[218] = data_i[218] & sel_one_hot_i[1];
assign data_masked[217] = data_i[217] & sel_one_hot_i[1];
assign data_masked[216] = data_i[216] & sel_one_hot_i[1];
assign data_masked[215] = data_i[215] & sel_one_hot_i[1];
assign data_masked[214] = data_i[214] & sel_one_hot_i[1];
assign data_masked[213] = data_i[213] & sel_one_hot_i[1];
assign data_masked[212] = data_i[212] & sel_one_hot_i[1];
assign data_masked[211] = data_i[211] & sel_one_hot_i[1];
assign data_masked[210] = data_i[210] & sel_one_hot_i[1];
assign data_masked[209] = data_i[209] & sel_one_hot_i[1];
assign data_masked[208] = data_i[208] & sel_one_hot_i[1];
assign data_masked[207] = data_i[207] & sel_one_hot_i[1];
assign data_masked[206] = data_i[206] & sel_one_hot_i[1];
assign data_masked[205] = data_i[205] & sel_one_hot_i[1];
assign data_masked[204] = data_i[204] & sel_one_hot_i[1];
assign data_masked[203] = data_i[203] & sel_one_hot_i[1];
assign data_masked[202] = data_i[202] & sel_one_hot_i[1];
assign data_masked[201] = data_i[201] & sel_one_hot_i[1];
assign data_masked[200] = data_i[200] & sel_one_hot_i[1];
assign data_masked[199] = data_i[199] & sel_one_hot_i[1];
assign data_masked[198] = data_i[198] & sel_one_hot_i[1];
assign data_masked[197] = data_i[197] & sel_one_hot_i[1];
assign data_masked[196] = data_i[196] & sel_one_hot_i[1];
assign data_masked[195] = data_i[195] & sel_one_hot_i[1];
assign data_masked[194] = data_i[194] & sel_one_hot_i[1];
assign data_masked[193] = data_i[193] & sel_one_hot_i[1];
assign data_masked[192] = data_i[192] & sel_one_hot_i[1];
assign data_masked[191] = data_i[191] & sel_one_hot_i[1];
assign data_masked[190] = data_i[190] & sel_one_hot_i[1];
assign data_masked[189] = data_i[189] & sel_one_hot_i[1];
assign data_masked[188] = data_i[188] & sel_one_hot_i[1];
assign data_masked[187] = data_i[187] & sel_one_hot_i[1];
assign data_masked[186] = data_i[186] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[1];
assign data_masked[184] = data_i[184] & sel_one_hot_i[1];
assign data_masked[183] = data_i[183] & sel_one_hot_i[1];
assign data_masked[182] = data_i[182] & sel_one_hot_i[1];
assign data_masked[181] = data_i[181] & sel_one_hot_i[1];
assign data_masked[180] = data_i[180] & sel_one_hot_i[1];
assign data_masked[179] = data_i[179] & sel_one_hot_i[1];
assign data_masked[178] = data_i[178] & sel_one_hot_i[1];
assign data_masked[177] = data_i[177] & sel_one_hot_i[1];
assign data_masked[176] = data_i[176] & sel_one_hot_i[1];
assign data_masked[175] = data_i[175] & sel_one_hot_i[1];
assign data_masked[174] = data_i[174] & sel_one_hot_i[1];
assign data_masked[173] = data_i[173] & sel_one_hot_i[1];
assign data_masked[172] = data_i[172] & sel_one_hot_i[1];
assign data_masked[171] = data_i[171] & sel_one_hot_i[1];
assign data_masked[170] = data_i[170] & sel_one_hot_i[1];
assign data_masked[169] = data_i[169] & sel_one_hot_i[1];
assign data_masked[168] = data_i[168] & sel_one_hot_i[1];
assign data_masked[167] = data_i[167] & sel_one_hot_i[1];
assign data_masked[166] = data_i[166] & sel_one_hot_i[1];
assign data_masked[165] = data_i[165] & sel_one_hot_i[1];
assign data_masked[164] = data_i[164] & sel_one_hot_i[1];
assign data_masked[163] = data_i[163] & sel_one_hot_i[1];
assign data_masked[162] = data_i[162] & sel_one_hot_i[1];
assign data_masked[161] = data_i[161] & sel_one_hot_i[1];
assign data_masked[160] = data_i[160] & sel_one_hot_i[1];
assign data_masked[159] = data_i[159] & sel_one_hot_i[1];
assign data_masked[158] = data_i[158] & sel_one_hot_i[1];
assign data_masked[157] = data_i[157] & sel_one_hot_i[1];
assign data_masked[156] = data_i[156] & sel_one_hot_i[1];
assign data_masked[155] = data_i[155] & sel_one_hot_i[1];
assign data_masked[154] = data_i[154] & sel_one_hot_i[1];
assign data_masked[153] = data_i[153] & sel_one_hot_i[1];
assign data_masked[152] = data_i[152] & sel_one_hot_i[1];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_masked[383] = data_i[383] & sel_one_hot_i[2];
assign data_masked[382] = data_i[382] & sel_one_hot_i[2];
assign data_masked[381] = data_i[381] & sel_one_hot_i[2];
assign data_masked[380] = data_i[380] & sel_one_hot_i[2];
assign data_masked[379] = data_i[379] & sel_one_hot_i[2];
assign data_masked[378] = data_i[378] & sel_one_hot_i[2];
assign data_masked[377] = data_i[377] & sel_one_hot_i[2];
assign data_masked[376] = data_i[376] & sel_one_hot_i[2];
assign data_masked[375] = data_i[375] & sel_one_hot_i[2];
assign data_masked[374] = data_i[374] & sel_one_hot_i[2];
assign data_masked[373] = data_i[373] & sel_one_hot_i[2];
assign data_masked[372] = data_i[372] & sel_one_hot_i[2];
assign data_masked[371] = data_i[371] & sel_one_hot_i[2];
assign data_masked[370] = data_i[370] & sel_one_hot_i[2];
assign data_masked[369] = data_i[369] & sel_one_hot_i[2];
assign data_masked[368] = data_i[368] & sel_one_hot_i[2];
assign data_masked[367] = data_i[367] & sel_one_hot_i[2];
assign data_masked[366] = data_i[366] & sel_one_hot_i[2];
assign data_masked[365] = data_i[365] & sel_one_hot_i[2];
assign data_masked[364] = data_i[364] & sel_one_hot_i[2];
assign data_masked[363] = data_i[363] & sel_one_hot_i[2];
assign data_masked[362] = data_i[362] & sel_one_hot_i[2];
assign data_masked[361] = data_i[361] & sel_one_hot_i[2];
assign data_masked[360] = data_i[360] & sel_one_hot_i[2];
assign data_masked[359] = data_i[359] & sel_one_hot_i[2];
assign data_masked[358] = data_i[358] & sel_one_hot_i[2];
assign data_masked[357] = data_i[357] & sel_one_hot_i[2];
assign data_masked[356] = data_i[356] & sel_one_hot_i[2];
assign data_masked[355] = data_i[355] & sel_one_hot_i[2];
assign data_masked[354] = data_i[354] & sel_one_hot_i[2];
assign data_masked[353] = data_i[353] & sel_one_hot_i[2];
assign data_masked[352] = data_i[352] & sel_one_hot_i[2];
assign data_masked[351] = data_i[351] & sel_one_hot_i[2];
assign data_masked[350] = data_i[350] & sel_one_hot_i[2];
assign data_masked[349] = data_i[349] & sel_one_hot_i[2];
assign data_masked[348] = data_i[348] & sel_one_hot_i[2];
assign data_masked[347] = data_i[347] & sel_one_hot_i[2];
assign data_masked[346] = data_i[346] & sel_one_hot_i[2];
assign data_masked[345] = data_i[345] & sel_one_hot_i[2];
assign data_masked[344] = data_i[344] & sel_one_hot_i[2];
assign data_masked[343] = data_i[343] & sel_one_hot_i[2];
assign data_masked[342] = data_i[342] & sel_one_hot_i[2];
assign data_masked[341] = data_i[341] & sel_one_hot_i[2];
assign data_masked[340] = data_i[340] & sel_one_hot_i[2];
assign data_masked[339] = data_i[339] & sel_one_hot_i[2];
assign data_masked[338] = data_i[338] & sel_one_hot_i[2];
assign data_masked[337] = data_i[337] & sel_one_hot_i[2];
assign data_masked[336] = data_i[336] & sel_one_hot_i[2];
assign data_masked[335] = data_i[335] & sel_one_hot_i[2];
assign data_masked[334] = data_i[334] & sel_one_hot_i[2];
assign data_masked[333] = data_i[333] & sel_one_hot_i[2];
assign data_masked[332] = data_i[332] & sel_one_hot_i[2];
assign data_masked[331] = data_i[331] & sel_one_hot_i[2];
assign data_masked[330] = data_i[330] & sel_one_hot_i[2];
assign data_masked[329] = data_i[329] & sel_one_hot_i[2];
assign data_masked[328] = data_i[328] & sel_one_hot_i[2];
assign data_masked[327] = data_i[327] & sel_one_hot_i[2];
assign data_masked[326] = data_i[326] & sel_one_hot_i[2];
assign data_masked[325] = data_i[325] & sel_one_hot_i[2];
assign data_masked[324] = data_i[324] & sel_one_hot_i[2];
assign data_masked[323] = data_i[323] & sel_one_hot_i[2];
assign data_masked[322] = data_i[322] & sel_one_hot_i[2];
assign data_masked[321] = data_i[321] & sel_one_hot_i[2];
assign data_masked[320] = data_i[320] & sel_one_hot_i[2];
assign data_masked[319] = data_i[319] & sel_one_hot_i[2];
assign data_masked[318] = data_i[318] & sel_one_hot_i[2];
assign data_masked[317] = data_i[317] & sel_one_hot_i[2];
assign data_masked[316] = data_i[316] & sel_one_hot_i[2];
assign data_masked[315] = data_i[315] & sel_one_hot_i[2];
assign data_masked[314] = data_i[314] & sel_one_hot_i[2];
assign data_masked[313] = data_i[313] & sel_one_hot_i[2];
assign data_masked[312] = data_i[312] & sel_one_hot_i[2];
assign data_masked[311] = data_i[311] & sel_one_hot_i[2];
assign data_masked[310] = data_i[310] & sel_one_hot_i[2];
assign data_masked[309] = data_i[309] & sel_one_hot_i[2];
assign data_masked[308] = data_i[308] & sel_one_hot_i[2];
assign data_masked[307] = data_i[307] & sel_one_hot_i[2];
assign data_masked[306] = data_i[306] & sel_one_hot_i[2];
assign data_masked[305] = data_i[305] & sel_one_hot_i[2];
assign data_masked[304] = data_i[304] & sel_one_hot_i[2];
assign data_masked[303] = data_i[303] & sel_one_hot_i[2];
assign data_masked[302] = data_i[302] & sel_one_hot_i[2];
assign data_masked[301] = data_i[301] & sel_one_hot_i[2];
assign data_masked[300] = data_i[300] & sel_one_hot_i[2];
assign data_masked[299] = data_i[299] & sel_one_hot_i[2];
assign data_masked[298] = data_i[298] & sel_one_hot_i[2];
assign data_masked[297] = data_i[297] & sel_one_hot_i[2];
assign data_masked[296] = data_i[296] & sel_one_hot_i[2];
assign data_masked[295] = data_i[295] & sel_one_hot_i[2];
assign data_masked[294] = data_i[294] & sel_one_hot_i[2];
assign data_masked[293] = data_i[293] & sel_one_hot_i[2];
assign data_masked[292] = data_i[292] & sel_one_hot_i[2];
assign data_masked[291] = data_i[291] & sel_one_hot_i[2];
assign data_masked[290] = data_i[290] & sel_one_hot_i[2];
assign data_masked[289] = data_i[289] & sel_one_hot_i[2];
assign data_masked[288] = data_i[288] & sel_one_hot_i[2];
assign data_masked[287] = data_i[287] & sel_one_hot_i[2];
assign data_masked[286] = data_i[286] & sel_one_hot_i[2];
assign data_masked[285] = data_i[285] & sel_one_hot_i[2];
assign data_masked[284] = data_i[284] & sel_one_hot_i[2];
assign data_masked[283] = data_i[283] & sel_one_hot_i[2];
assign data_masked[282] = data_i[282] & sel_one_hot_i[2];
assign data_masked[281] = data_i[281] & sel_one_hot_i[2];
assign data_masked[280] = data_i[280] & sel_one_hot_i[2];
assign data_masked[279] = data_i[279] & sel_one_hot_i[2];
assign data_masked[278] = data_i[278] & sel_one_hot_i[2];
assign data_masked[277] = data_i[277] & sel_one_hot_i[2];
assign data_masked[276] = data_i[276] & sel_one_hot_i[2];
assign data_masked[275] = data_i[275] & sel_one_hot_i[2];
assign data_masked[274] = data_i[274] & sel_one_hot_i[2];
assign data_masked[273] = data_i[273] & sel_one_hot_i[2];
assign data_masked[272] = data_i[272] & sel_one_hot_i[2];
assign data_masked[271] = data_i[271] & sel_one_hot_i[2];
assign data_masked[270] = data_i[270] & sel_one_hot_i[2];
assign data_masked[269] = data_i[269] & sel_one_hot_i[2];
assign data_masked[268] = data_i[268] & sel_one_hot_i[2];
assign data_masked[267] = data_i[267] & sel_one_hot_i[2];
assign data_masked[266] = data_i[266] & sel_one_hot_i[2];
assign data_masked[265] = data_i[265] & sel_one_hot_i[2];
assign data_masked[264] = data_i[264] & sel_one_hot_i[2];
assign data_masked[263] = data_i[263] & sel_one_hot_i[2];
assign data_masked[262] = data_i[262] & sel_one_hot_i[2];
assign data_masked[261] = data_i[261] & sel_one_hot_i[2];
assign data_masked[260] = data_i[260] & sel_one_hot_i[2];
assign data_masked[259] = data_i[259] & sel_one_hot_i[2];
assign data_masked[258] = data_i[258] & sel_one_hot_i[2];
assign data_masked[257] = data_i[257] & sel_one_hot_i[2];
assign data_masked[256] = data_i[256] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[256] | data_masked[128];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[257] | data_masked[129];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[258] | data_masked[130];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[259] | data_masked[131];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[260] | data_masked[132];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[261] | data_masked[133];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[262] | data_masked[134];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[263] | data_masked[135];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[264] | data_masked[136];
assign data_o[9] = N9 | data_masked[9];
assign N9 = data_masked[265] | data_masked[137];
assign data_o[10] = N10 | data_masked[10];
assign N10 = data_masked[266] | data_masked[138];
assign data_o[11] = N11 | data_masked[11];
assign N11 = data_masked[267] | data_masked[139];
assign data_o[12] = N12 | data_masked[12];
assign N12 = data_masked[268] | data_masked[140];
assign data_o[13] = N13 | data_masked[13];
assign N13 = data_masked[269] | data_masked[141];
assign data_o[14] = N14 | data_masked[14];
assign N14 = data_masked[270] | data_masked[142];
assign data_o[15] = N15 | data_masked[15];
assign N15 = data_masked[271] | data_masked[143];
assign data_o[16] = N16 | data_masked[16];
assign N16 = data_masked[272] | data_masked[144];
assign data_o[17] = N17 | data_masked[17];
assign N17 = data_masked[273] | data_masked[145];
assign data_o[18] = N18 | data_masked[18];
assign N18 = data_masked[274] | data_masked[146];
assign data_o[19] = N19 | data_masked[19];
assign N19 = data_masked[275] | data_masked[147];
assign data_o[20] = N20 | data_masked[20];
assign N20 = data_masked[276] | data_masked[148];
assign data_o[21] = N21 | data_masked[21];
assign N21 = data_masked[277] | data_masked[149];
assign data_o[22] = N22 | data_masked[22];
assign N22 = data_masked[278] | data_masked[150];
assign data_o[23] = N23 | data_masked[23];
assign N23 = data_masked[279] | data_masked[151];
assign data_o[24] = N24 | data_masked[24];
assign N24 = data_masked[280] | data_masked[152];
assign data_o[25] = N25 | data_masked[25];
assign N25 = data_masked[281] | data_masked[153];
assign data_o[26] = N26 | data_masked[26];
assign N26 = data_masked[282] | data_masked[154];
assign data_o[27] = N27 | data_masked[27];
assign N27 = data_masked[283] | data_masked[155];
assign data_o[28] = N28 | data_masked[28];
assign N28 = data_masked[284] | data_masked[156];
assign data_o[29] = N29 | data_masked[29];
assign N29 = data_masked[285] | data_masked[157];
assign data_o[30] = N30 | data_masked[30];
assign N30 = data_masked[286] | data_masked[158];
assign data_o[31] = N31 | data_masked[31];
assign N31 = data_masked[287] | data_masked[159];
assign data_o[32] = N32 | data_masked[32];
assign N32 = data_masked[288] | data_masked[160];
assign data_o[33] = N33 | data_masked[33];
assign N33 = data_masked[289] | data_masked[161];
assign data_o[34] = N34 | data_masked[34];
assign N34 = data_masked[290] | data_masked[162];
assign data_o[35] = N35 | data_masked[35];
assign N35 = data_masked[291] | data_masked[163];
assign data_o[36] = N36 | data_masked[36];
assign N36 = data_masked[292] | data_masked[164];
assign data_o[37] = N37 | data_masked[37];
assign N37 = data_masked[293] | data_masked[165];
assign data_o[38] = N38 | data_masked[38];
assign N38 = data_masked[294] | data_masked[166];
assign data_o[39] = N39 | data_masked[39];
assign N39 = data_masked[295] | data_masked[167];
assign data_o[40] = N40 | data_masked[40];
assign N40 = data_masked[296] | data_masked[168];
assign data_o[41] = N41 | data_masked[41];
assign N41 = data_masked[297] | data_masked[169];
assign data_o[42] = N42 | data_masked[42];
assign N42 = data_masked[298] | data_masked[170];
assign data_o[43] = N43 | data_masked[43];
assign N43 = data_masked[299] | data_masked[171];
assign data_o[44] = N44 | data_masked[44];
assign N44 = data_masked[300] | data_masked[172];
assign data_o[45] = N45 | data_masked[45];
assign N45 = data_masked[301] | data_masked[173];
assign data_o[46] = N46 | data_masked[46];
assign N46 = data_masked[302] | data_masked[174];
assign data_o[47] = N47 | data_masked[47];
assign N47 = data_masked[303] | data_masked[175];
assign data_o[48] = N48 | data_masked[48];
assign N48 = data_masked[304] | data_masked[176];
assign data_o[49] = N49 | data_masked[49];
assign N49 = data_masked[305] | data_masked[177];
assign data_o[50] = N50 | data_masked[50];
assign N50 = data_masked[306] | data_masked[178];
assign data_o[51] = N51 | data_masked[51];
assign N51 = data_masked[307] | data_masked[179];
assign data_o[52] = N52 | data_masked[52];
assign N52 = data_masked[308] | data_masked[180];
assign data_o[53] = N53 | data_masked[53];
assign N53 = data_masked[309] | data_masked[181];
assign data_o[54] = N54 | data_masked[54];
assign N54 = data_masked[310] | data_masked[182];
assign data_o[55] = N55 | data_masked[55];
assign N55 = data_masked[311] | data_masked[183];
assign data_o[56] = N56 | data_masked[56];
assign N56 = data_masked[312] | data_masked[184];
assign data_o[57] = N57 | data_masked[57];
assign N57 = data_masked[313] | data_masked[185];
assign data_o[58] = N58 | data_masked[58];
assign N58 = data_masked[314] | data_masked[186];
assign data_o[59] = N59 | data_masked[59];
assign N59 = data_masked[315] | data_masked[187];
assign data_o[60] = N60 | data_masked[60];
assign N60 = data_masked[316] | data_masked[188];
assign data_o[61] = N61 | data_masked[61];
assign N61 = data_masked[317] | data_masked[189];
assign data_o[62] = N62 | data_masked[62];
assign N62 = data_masked[318] | data_masked[190];
assign data_o[63] = N63 | data_masked[63];
assign N63 = data_masked[319] | data_masked[191];
assign data_o[64] = N64 | data_masked[64];
assign N64 = data_masked[320] | data_masked[192];
assign data_o[65] = N65 | data_masked[65];
assign N65 = data_masked[321] | data_masked[193];
assign data_o[66] = N66 | data_masked[66];
assign N66 = data_masked[322] | data_masked[194];
assign data_o[67] = N67 | data_masked[67];
assign N67 = data_masked[323] | data_masked[195];
assign data_o[68] = N68 | data_masked[68];
assign N68 = data_masked[324] | data_masked[196];
assign data_o[69] = N69 | data_masked[69];
assign N69 = data_masked[325] | data_masked[197];
assign data_o[70] = N70 | data_masked[70];
assign N70 = data_masked[326] | data_masked[198];
assign data_o[71] = N71 | data_masked[71];
assign N71 = data_masked[327] | data_masked[199];
assign data_o[72] = N72 | data_masked[72];
assign N72 = data_masked[328] | data_masked[200];
assign data_o[73] = N73 | data_masked[73];
assign N73 = data_masked[329] | data_masked[201];
assign data_o[74] = N74 | data_masked[74];
assign N74 = data_masked[330] | data_masked[202];
assign data_o[75] = N75 | data_masked[75];
assign N75 = data_masked[331] | data_masked[203];
assign data_o[76] = N76 | data_masked[76];
assign N76 = data_masked[332] | data_masked[204];
assign data_o[77] = N77 | data_masked[77];
assign N77 = data_masked[333] | data_masked[205];
assign data_o[78] = N78 | data_masked[78];
assign N78 = data_masked[334] | data_masked[206];
assign data_o[79] = N79 | data_masked[79];
assign N79 = data_masked[335] | data_masked[207];
assign data_o[80] = N80 | data_masked[80];
assign N80 = data_masked[336] | data_masked[208];
assign data_o[81] = N81 | data_masked[81];
assign N81 = data_masked[337] | data_masked[209];
assign data_o[82] = N82 | data_masked[82];
assign N82 = data_masked[338] | data_masked[210];
assign data_o[83] = N83 | data_masked[83];
assign N83 = data_masked[339] | data_masked[211];
assign data_o[84] = N84 | data_masked[84];
assign N84 = data_masked[340] | data_masked[212];
assign data_o[85] = N85 | data_masked[85];
assign N85 = data_masked[341] | data_masked[213];
assign data_o[86] = N86 | data_masked[86];
assign N86 = data_masked[342] | data_masked[214];
assign data_o[87] = N87 | data_masked[87];
assign N87 = data_masked[343] | data_masked[215];
assign data_o[88] = N88 | data_masked[88];
assign N88 = data_masked[344] | data_masked[216];
assign data_o[89] = N89 | data_masked[89];
assign N89 = data_masked[345] | data_masked[217];
assign data_o[90] = N90 | data_masked[90];
assign N90 = data_masked[346] | data_masked[218];
assign data_o[91] = N91 | data_masked[91];
assign N91 = data_masked[347] | data_masked[219];
assign data_o[92] = N92 | data_masked[92];
assign N92 = data_masked[348] | data_masked[220];
assign data_o[93] = N93 | data_masked[93];
assign N93 = data_masked[349] | data_masked[221];
assign data_o[94] = N94 | data_masked[94];
assign N94 = data_masked[350] | data_masked[222];
assign data_o[95] = N95 | data_masked[95];
assign N95 = data_masked[351] | data_masked[223];
assign data_o[96] = N96 | data_masked[96];
assign N96 = data_masked[352] | data_masked[224];
assign data_o[97] = N97 | data_masked[97];
assign N97 = data_masked[353] | data_masked[225];
assign data_o[98] = N98 | data_masked[98];
assign N98 = data_masked[354] | data_masked[226];
assign data_o[99] = N99 | data_masked[99];
assign N99 = data_masked[355] | data_masked[227];
assign data_o[100] = N100 | data_masked[100];
assign N100 = data_masked[356] | data_masked[228];
assign data_o[101] = N101 | data_masked[101];
assign N101 = data_masked[357] | data_masked[229];
assign data_o[102] = N102 | data_masked[102];
assign N102 = data_masked[358] | data_masked[230];
assign data_o[103] = N103 | data_masked[103];
assign N103 = data_masked[359] | data_masked[231];
assign data_o[104] = N104 | data_masked[104];
assign N104 = data_masked[360] | data_masked[232];
assign data_o[105] = N105 | data_masked[105];
assign N105 = data_masked[361] | data_masked[233];
assign data_o[106] = N106 | data_masked[106];
assign N106 = data_masked[362] | data_masked[234];
assign data_o[107] = N107 | data_masked[107];
assign N107 = data_masked[363] | data_masked[235];
assign data_o[108] = N108 | data_masked[108];
assign N108 = data_masked[364] | data_masked[236];
assign data_o[109] = N109 | data_masked[109];
assign N109 = data_masked[365] | data_masked[237];
assign data_o[110] = N110 | data_masked[110];
assign N110 = data_masked[366] | data_masked[238];
assign data_o[111] = N111 | data_masked[111];
assign N111 = data_masked[367] | data_masked[239];
assign data_o[112] = N112 | data_masked[112];
assign N112 = data_masked[368] | data_masked[240];
assign data_o[113] = N113 | data_masked[113];
assign N113 = data_masked[369] | data_masked[241];
assign data_o[114] = N114 | data_masked[114];
assign N114 = data_masked[370] | data_masked[242];
assign data_o[115] = N115 | data_masked[115];
assign N115 = data_masked[371] | data_masked[243];
assign data_o[116] = N116 | data_masked[116];
assign N116 = data_masked[372] | data_masked[244];
assign data_o[117] = N117 | data_masked[117];
assign N117 = data_masked[373] | data_masked[245];
assign data_o[118] = N118 | data_masked[118];
assign N118 = data_masked[374] | data_masked[246];
assign data_o[119] = N119 | data_masked[119];
assign N119 = data_masked[375] | data_masked[247];
assign data_o[120] = N120 | data_masked[120];
assign N120 = data_masked[376] | data_masked[248];
assign data_o[121] = N121 | data_masked[121];
assign N121 = data_masked[377] | data_masked[249];
assign data_o[122] = N122 | data_masked[122];
assign N122 = data_masked[378] | data_masked[250];
assign data_o[123] = N123 | data_masked[123];
assign N123 = data_masked[379] | data_masked[251];
assign data_o[124] = N124 | data_masked[124];
assign N124 = data_masked[380] | data_masked[252];
assign data_o[125] = N125 | data_masked[125];
assign N125 = data_masked[381] | data_masked[253];
assign data_o[126] = N126 | data_masked[126];
assign N126 = data_masked[382] | data_masked[254];
assign data_o[127] = N127 | data_masked[127];
assign N127 = data_masked[383] | data_masked[255];
endmodule |
module bsg_transpose_width_p5_els_p5
(
i,
o
);
input [24:0] i;
output [24:0] o;
wire [24:0] o;
assign o[24] = i[24];
assign o[23] = i[19];
assign o[22] = i[14];
assign o[21] = i[9];
assign o[20] = i[4];
assign o[19] = i[23];
assign o[18] = i[18];
assign o[17] = i[13];
assign o[16] = i[8];
assign o[15] = i[3];
assign o[14] = i[22];
assign o[13] = i[17];
assign o[12] = i[12];
assign o[11] = i[7];
assign o[10] = i[2];
assign o[9] = i[21];
assign o[8] = i[16];
assign o[7] = i[11];
assign o[6] = i[6];
assign o[5] = i[1];
assign o[4] = i[20];
assign o[3] = i[15];
assign o[2] = i[10];
assign o[1] = i[5];
assign o[0] = i[0];
endmodule |
module bp_cce_alu_width_p48
(
v_i,
br_v_i,
opd_a_i,
opd_b_i,
alu_op_i,
br_op_i,
res_o,
branch_res_o
);
input [47:0] opd_a_i;
input [47:0] opd_b_i;
input [3:0] alu_op_i;
input [3:0] br_op_i;
output [47:0] res_o;
input v_i;
input br_v_i;
output branch_res_o;
wire [47:0] res_o;
wire branch_res_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,
N19,N20,N21,N22,N23,equal,less,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,
N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,
N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,
N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,
N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,
N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,
N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,
N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,
N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,
N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,
N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,
N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,
N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,
N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,
N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,
N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,
N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,
N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,
N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,
N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,
N353,N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,
N369,N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,N382,N383,N384,
N385,N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,N398,N399,N400,
N401,N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,N414,N415,N416,
N417,N418,N419,N420,N421,N422,N423,N424,N425,N426,N427,N428,N429,N430,N431,N432,
N433,N434,N435,N436,N437,N438,N439,N440,N441,N442,N443,N444,N445,N446,N447,N448,
N449,N450,N451,N452,N453,N454,N455,N456,N457,N458,N459,N460,N461,N462,N463,N464,
N465,N466,N467,N468,N469,N470,N471,N472,N473,N474,N475,N476,N477,N478,N479,N480,
N481,N482,N483,N484,N485,N486,N487,N488,N489,N490,N491,N492,N493,N494,N495,N496,
N497,N498,N499,N500,N501,N502,N503,N504,N505,N506,N507,N508,N509,N510,N511,N512,
N513,N514,N515,N516,N517,N518,N519,N520,N521,N522,N523,N524,N525,N526,N527,N528,
N529,N530,N531,N532,N533,N534,N535,N536,N537,N538,N539,N540,N541,N542,N543,N544,
N545,N546,N547,N548,N549,N550,N551,N552,N553,N554,N555,N556,N557,N558,N559;
assign equal = opd_a_i == opd_b_i;
assign less = opd_a_i < opd_b_i;
assign N29 = N26 & N27;
assign N30 = N29 & N28;
assign N31 = br_op_i[2] | br_op_i[1];
assign N32 = N31 | N28;
assign N34 = N26 | br_op_i[1];
assign N35 = N34 | br_op_i[0];
assign N37 = N34 | N28;
assign N39 = br_op_i[2] & br_op_i[1];
assign N40 = N39 & br_op_i[0];
assign N41 = br_op_i[2] | N27;
assign N42 = N41 | br_op_i[0];
assign N44 = N26 | N27;
assign N45 = N44 | br_op_i[0];
assign N47 = N41 | N28;
assign N57 = N67 & N74;
assign N58 = N57 & N71;
assign N59 = alu_op_i[2] | alu_op_i[1];
assign N60 = N59 | N71;
assign N62 = alu_op_i[2] | N74;
assign N63 = N62 | alu_op_i[0];
assign N65 = N62 | N71;
assign N68 = N67 | alu_op_i[1];
assign N69 = N68 | alu_op_i[0];
assign N72 = N68 | N71;
assign N75 = N67 | N74;
assign N76 = N75 | alu_op_i[0];
assign N78 = alu_op_i[2] & alu_op_i[1];
assign N79 = N78 & alu_op_i[0];
assign { N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176 } = opd_a_i << opd_b_i;
assign { N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224 } = opd_a_i >> opd_b_i;
assign { N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80 } = opd_a_i + opd_b_i;
assign { N175, N174, N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128 } = opd_a_i - opd_b_i;
assign N51 = (N0)? equal :
(N1)? N49 :
(N2)? less :
(N3)? N50 :
(N4)? 1'b1 :
(N5)? equal :
(N6)? equal :
(N7)? equal : 1'b0;
assign N0 = N30;
assign N1 = N33;
assign N2 = N36;
assign N3 = N38;
assign N4 = N40;
assign N5 = N43;
assign N6 = N46;
assign N7 = N48;
assign N52 = (N8)? N51 :
(N9)? 1'b0 : 1'b0;
assign N8 = N25;
assign N9 = br_op_i[3];
assign branch_res_o = (N10)? N52 :
(N11)? 1'b0 : 1'b0;
assign N10 = br_v_i;
assign N11 = N24;
assign { N511, N510, N509, N508, N507, N506, N505, N504, N503, N502, N501, N500, N499, N498, N497, N496, N495, N494, N493, N492, N491, N490, N489, N488, N487, N486, N485, N484, N483, N482, N481, N480, N479, N478, N477, N476, N475, N474, N473, N472, N471, N470, N469, N468, N467, N466, N465, N464 } = (N12)? { N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80 } :
(N13)? { N175, N174, N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N147, N146, N145, N144, N143, N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128 } :
(N14)? { N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176 } :
(N15)? { N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229, N228, N227, N226, N225, N224 } :
(N16)? { N272, N273, N274, N275, N276, N277, N278, N279, N280, N281, N282, N283, N284, N285, N286, N287, N288, N289, N290, N291, N292, N293, N294, N295, N296, N297, N298, N299, N300, N301, N302, N303, N304, N305, N306, N307, N308, N309, N310, N311, N312, N313, N314, N315, N316, N317, N318, N319 } :
(N17)? { N320, N321, N322, N323, N324, N325, N326, N327, N328, N329, N330, N331, N332, N333, N334, N335, N336, N337, N338, N339, N340, N341, N342, N343, N344, N345, N346, N347, N348, N349, N350, N351, N352, N353, N354, N355, N356, N357, N358, N359, N360, N361, N362, N363, N364, N365, N366, N367 } :
(N18)? { N368, N369, N370, N371, N372, N373, N374, N375, N376, N377, N378, N379, N380, N381, N382, N383, N384, N385, N386, N387, N388, N389, N390, N391, N392, N393, N394, N395, N396, N397, N398, N399, N400, N401, N402, N403, N404, N405, N406, N407, N408, N409, N410, N411, N412, N413, N414, N415 } :
(N19)? { N416, N417, N418, N419, N420, N421, N422, N423, N424, N425, N426, N427, N428, N429, N430, N431, N432, N433, N434, N435, N436, N437, N438, N439, N440, N441, N442, N443, N444, N445, N446, N447, N448, N449, N450, N451, N452, N453, N454, N455, N456, N457, N458, N459, N460, N461, N462, N463 } : 1'b0;
assign N12 = N58;
assign N13 = N61;
assign N14 = N64;
assign N15 = N66;
assign N16 = N70;
assign N17 = N73;
assign N18 = N77;
assign N19 = N79;
assign { N559, N558, N557, N556, N555, N554, N553, N552, N551, N550, N549, N548, N547, N546, N545, N544, N543, N542, N541, N540, N539, N538, N537, N536, N535, N534, N533, N532, N531, N530, N529, N528, N527, N526, N525, N524, N523, N522, N521, N520, N519, N518, N517, N516, N515, N514, N513, N512 } = (N20)? { N511, N510, N509, N508, N507, N506, N505, N504, N503, N502, N501, N500, N499, N498, N497, N496, N495, N494, N493, N492, N491, N490, N489, N488, N487, N486, N485, N484, N483, N482, N481, N480, N479, N478, N477, N476, N475, N474, N473, N472, N471, N470, N469, N468, N467, N466, N465, N464 } :
(N21)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N20 = N55;
assign N21 = alu_op_i[3];
assign res_o = (N22)? { N559, N558, N557, N556, N555, N554, N553, N552, N551, N550, N549, N548, N547, N546, N545, N544, N543, N542, N541, N540, N539, N538, N537, N536, N535, N534, N533, N532, N531, N530, N529, N528, N527, N526, N525, N524, N523, N522, N521, N520, N519, N518, N517, N516, N515, N514, N513, N512 } :
(N23)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N22 = v_i;
assign N23 = N53;
assign N24 = ~br_v_i;
assign N25 = ~br_op_i[3];
assign N26 = ~br_op_i[2];
assign N27 = ~br_op_i[1];
assign N28 = ~br_op_i[0];
assign N33 = ~N32;
assign N36 = ~N35;
assign N38 = ~N37;
assign N43 = ~N42;
assign N46 = ~N45;
assign N48 = ~N47;
assign N49 = ~equal;
assign N50 = less | equal;
assign N53 = ~v_i;
assign N54 = v_i;
assign N55 = ~alu_op_i[3];
assign N56 = N54 & N55;
assign N61 = ~N60;
assign N64 = ~N63;
assign N66 = ~N65;
assign N67 = ~alu_op_i[2];
assign N70 = ~N69;
assign N71 = ~alu_op_i[0];
assign N73 = ~N72;
assign N74 = ~alu_op_i[1];
assign N77 = ~N76;
assign N272 = opd_a_i[47] & opd_b_i[47];
assign N273 = opd_a_i[46] & opd_b_i[46];
assign N274 = opd_a_i[45] & opd_b_i[45];
assign N275 = opd_a_i[44] & opd_b_i[44];
assign N276 = opd_a_i[43] & opd_b_i[43];
assign N277 = opd_a_i[42] & opd_b_i[42];
assign N278 = opd_a_i[41] & opd_b_i[41];
assign N279 = opd_a_i[40] & opd_b_i[40];
assign N280 = opd_a_i[39] & opd_b_i[39];
assign N281 = opd_a_i[38] & opd_b_i[38];
assign N282 = opd_a_i[37] & opd_b_i[37];
assign N283 = opd_a_i[36] & opd_b_i[36];
assign N284 = opd_a_i[35] & opd_b_i[35];
assign N285 = opd_a_i[34] & opd_b_i[34];
assign N286 = opd_a_i[33] & opd_b_i[33];
assign N287 = opd_a_i[32] & opd_b_i[32];
assign N288 = opd_a_i[31] & opd_b_i[31];
assign N289 = opd_a_i[30] & opd_b_i[30];
assign N290 = opd_a_i[29] & opd_b_i[29];
assign N291 = opd_a_i[28] & opd_b_i[28];
assign N292 = opd_a_i[27] & opd_b_i[27];
assign N293 = opd_a_i[26] & opd_b_i[26];
assign N294 = opd_a_i[25] & opd_b_i[25];
assign N295 = opd_a_i[24] & opd_b_i[24];
assign N296 = opd_a_i[23] & opd_b_i[23];
assign N297 = opd_a_i[22] & opd_b_i[22];
assign N298 = opd_a_i[21] & opd_b_i[21];
assign N299 = opd_a_i[20] & opd_b_i[20];
assign N300 = opd_a_i[19] & opd_b_i[19];
assign N301 = opd_a_i[18] & opd_b_i[18];
assign N302 = opd_a_i[17] & opd_b_i[17];
assign N303 = opd_a_i[16] & opd_b_i[16];
assign N304 = opd_a_i[15] & opd_b_i[15];
assign N305 = opd_a_i[14] & opd_b_i[14];
assign N306 = opd_a_i[13] & opd_b_i[13];
assign N307 = opd_a_i[12] & opd_b_i[12];
assign N308 = opd_a_i[11] & opd_b_i[11];
assign N309 = opd_a_i[10] & opd_b_i[10];
assign N310 = opd_a_i[9] & opd_b_i[9];
assign N311 = opd_a_i[8] & opd_b_i[8];
assign N312 = opd_a_i[7] & opd_b_i[7];
assign N313 = opd_a_i[6] & opd_b_i[6];
assign N314 = opd_a_i[5] & opd_b_i[5];
assign N315 = opd_a_i[4] & opd_b_i[4];
assign N316 = opd_a_i[3] & opd_b_i[3];
assign N317 = opd_a_i[2] & opd_b_i[2];
assign N318 = opd_a_i[1] & opd_b_i[1];
assign N319 = opd_a_i[0] & opd_b_i[0];
assign N320 = opd_a_i[47] | opd_b_i[47];
assign N321 = opd_a_i[46] | opd_b_i[46];
assign N322 = opd_a_i[45] | opd_b_i[45];
assign N323 = opd_a_i[44] | opd_b_i[44];
assign N324 = opd_a_i[43] | opd_b_i[43];
assign N325 = opd_a_i[42] | opd_b_i[42];
assign N326 = opd_a_i[41] | opd_b_i[41];
assign N327 = opd_a_i[40] | opd_b_i[40];
assign N328 = opd_a_i[39] | opd_b_i[39];
assign N329 = opd_a_i[38] | opd_b_i[38];
assign N330 = opd_a_i[37] | opd_b_i[37];
assign N331 = opd_a_i[36] | opd_b_i[36];
assign N332 = opd_a_i[35] | opd_b_i[35];
assign N333 = opd_a_i[34] | opd_b_i[34];
assign N334 = opd_a_i[33] | opd_b_i[33];
assign N335 = opd_a_i[32] | opd_b_i[32];
assign N336 = opd_a_i[31] | opd_b_i[31];
assign N337 = opd_a_i[30] | opd_b_i[30];
assign N338 = opd_a_i[29] | opd_b_i[29];
assign N339 = opd_a_i[28] | opd_b_i[28];
assign N340 = opd_a_i[27] | opd_b_i[27];
assign N341 = opd_a_i[26] | opd_b_i[26];
assign N342 = opd_a_i[25] | opd_b_i[25];
assign N343 = opd_a_i[24] | opd_b_i[24];
assign N344 = opd_a_i[23] | opd_b_i[23];
assign N345 = opd_a_i[22] | opd_b_i[22];
assign N346 = opd_a_i[21] | opd_b_i[21];
assign N347 = opd_a_i[20] | opd_b_i[20];
assign N348 = opd_a_i[19] | opd_b_i[19];
assign N349 = opd_a_i[18] | opd_b_i[18];
assign N350 = opd_a_i[17] | opd_b_i[17];
assign N351 = opd_a_i[16] | opd_b_i[16];
assign N352 = opd_a_i[15] | opd_b_i[15];
assign N353 = opd_a_i[14] | opd_b_i[14];
assign N354 = opd_a_i[13] | opd_b_i[13];
assign N355 = opd_a_i[12] | opd_b_i[12];
assign N356 = opd_a_i[11] | opd_b_i[11];
assign N357 = opd_a_i[10] | opd_b_i[10];
assign N358 = opd_a_i[9] | opd_b_i[9];
assign N359 = opd_a_i[8] | opd_b_i[8];
assign N360 = opd_a_i[7] | opd_b_i[7];
assign N361 = opd_a_i[6] | opd_b_i[6];
assign N362 = opd_a_i[5] | opd_b_i[5];
assign N363 = opd_a_i[4] | opd_b_i[4];
assign N364 = opd_a_i[3] | opd_b_i[3];
assign N365 = opd_a_i[2] | opd_b_i[2];
assign N366 = opd_a_i[1] | opd_b_i[1];
assign N367 = opd_a_i[0] | opd_b_i[0];
assign N368 = opd_a_i[47] ^ opd_b_i[47];
assign N369 = opd_a_i[46] ^ opd_b_i[46];
assign N370 = opd_a_i[45] ^ opd_b_i[45];
assign N371 = opd_a_i[44] ^ opd_b_i[44];
assign N372 = opd_a_i[43] ^ opd_b_i[43];
assign N373 = opd_a_i[42] ^ opd_b_i[42];
assign N374 = opd_a_i[41] ^ opd_b_i[41];
assign N375 = opd_a_i[40] ^ opd_b_i[40];
assign N376 = opd_a_i[39] ^ opd_b_i[39];
assign N377 = opd_a_i[38] ^ opd_b_i[38];
assign N378 = opd_a_i[37] ^ opd_b_i[37];
assign N379 = opd_a_i[36] ^ opd_b_i[36];
assign N380 = opd_a_i[35] ^ opd_b_i[35];
assign N381 = opd_a_i[34] ^ opd_b_i[34];
assign N382 = opd_a_i[33] ^ opd_b_i[33];
assign N383 = opd_a_i[32] ^ opd_b_i[32];
assign N384 = opd_a_i[31] ^ opd_b_i[31];
assign N385 = opd_a_i[30] ^ opd_b_i[30];
assign N386 = opd_a_i[29] ^ opd_b_i[29];
assign N387 = opd_a_i[28] ^ opd_b_i[28];
assign N388 = opd_a_i[27] ^ opd_b_i[27];
assign N389 = opd_a_i[26] ^ opd_b_i[26];
assign N390 = opd_a_i[25] ^ opd_b_i[25];
assign N391 = opd_a_i[24] ^ opd_b_i[24];
assign N392 = opd_a_i[23] ^ opd_b_i[23];
assign N393 = opd_a_i[22] ^ opd_b_i[22];
assign N394 = opd_a_i[21] ^ opd_b_i[21];
assign N395 = opd_a_i[20] ^ opd_b_i[20];
assign N396 = opd_a_i[19] ^ opd_b_i[19];
assign N397 = opd_a_i[18] ^ opd_b_i[18];
assign N398 = opd_a_i[17] ^ opd_b_i[17];
assign N399 = opd_a_i[16] ^ opd_b_i[16];
assign N400 = opd_a_i[15] ^ opd_b_i[15];
assign N401 = opd_a_i[14] ^ opd_b_i[14];
assign N402 = opd_a_i[13] ^ opd_b_i[13];
assign N403 = opd_a_i[12] ^ opd_b_i[12];
assign N404 = opd_a_i[11] ^ opd_b_i[11];
assign N405 = opd_a_i[10] ^ opd_b_i[10];
assign N406 = opd_a_i[9] ^ opd_b_i[9];
assign N407 = opd_a_i[8] ^ opd_b_i[8];
assign N408 = opd_a_i[7] ^ opd_b_i[7];
assign N409 = opd_a_i[6] ^ opd_b_i[6];
assign N410 = opd_a_i[5] ^ opd_b_i[5];
assign N411 = opd_a_i[4] ^ opd_b_i[4];
assign N412 = opd_a_i[3] ^ opd_b_i[3];
assign N413 = opd_a_i[2] ^ opd_b_i[2];
assign N414 = opd_a_i[1] ^ opd_b_i[1];
assign N415 = opd_a_i[0] ^ opd_b_i[0];
assign N416 = ~opd_a_i[47];
assign N417 = ~opd_a_i[46];
assign N418 = ~opd_a_i[45];
assign N419 = ~opd_a_i[44];
assign N420 = ~opd_a_i[43];
assign N421 = ~opd_a_i[42];
assign N422 = ~opd_a_i[41];
assign N423 = ~opd_a_i[40];
assign N424 = ~opd_a_i[39];
assign N425 = ~opd_a_i[38];
assign N426 = ~opd_a_i[37];
assign N427 = ~opd_a_i[36];
assign N428 = ~opd_a_i[35];
assign N429 = ~opd_a_i[34];
assign N430 = ~opd_a_i[33];
assign N431 = ~opd_a_i[32];
assign N432 = ~opd_a_i[31];
assign N433 = ~opd_a_i[30];
assign N434 = ~opd_a_i[29];
assign N435 = ~opd_a_i[28];
assign N436 = ~opd_a_i[27];
assign N437 = ~opd_a_i[26];
assign N438 = ~opd_a_i[25];
assign N439 = ~opd_a_i[24];
assign N440 = ~opd_a_i[23];
assign N441 = ~opd_a_i[22];
assign N442 = ~opd_a_i[21];
assign N443 = ~opd_a_i[20];
assign N444 = ~opd_a_i[19];
assign N445 = ~opd_a_i[18];
assign N446 = ~opd_a_i[17];
assign N447 = ~opd_a_i[16];
assign N448 = ~opd_a_i[15];
assign N449 = ~opd_a_i[14];
assign N450 = ~opd_a_i[13];
assign N451 = ~opd_a_i[12];
assign N452 = ~opd_a_i[11];
assign N453 = ~opd_a_i[10];
assign N454 = ~opd_a_i[9];
assign N455 = ~opd_a_i[8];
assign N456 = ~opd_a_i[7];
assign N457 = ~opd_a_i[6];
assign N458 = ~opd_a_i[5];
assign N459 = ~opd_a_i[4];
assign N460 = ~opd_a_i[3];
assign N461 = ~opd_a_i[2];
assign N462 = ~opd_a_i[1];
assign N463 = ~opd_a_i[0];
endmodule |
module bsg_xnor_width_p5_harden_p1
(
a_i,
b_i,
o
);
input [4:0] a_i;
input [4:0] b_i;
output [4:0] o;
wire [4:0] o;
wire N0,N1,N2,N3,N4;
assign o[4] = ~N0;
assign N0 = a_i[4] ^ b_i[4];
assign o[3] = ~N1;
assign N1 = a_i[3] ^ b_i[3];
assign o[2] = ~N2;
assign N2 = a_i[2] ^ b_i[2];
assign o[1] = ~N3;
assign N3 = a_i[1] ^ b_i[1];
assign o[0] = ~N4;
assign N4 = a_i[0] ^ b_i[0];
endmodule |
module bsg_unconcentrate_static_03
(
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_1_,o_0_;
assign o[4] = 1'b0;
assign o[3] = 1'b0;
assign o[2] = 1'b0;
assign o_1_ = i[1];
assign o[1] = o_1_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_expand_bitmask_in_width_p2_expand_p4
(
i,
o
);
input [1:0] i;
output [7:0] o;
wire [7:0] o;
wire o_7_,o_3_;
assign o_7_ = i[1];
assign o[4] = o_7_;
assign o[5] = o_7_;
assign o[6] = o_7_;
assign o[7] = o_7_;
assign o_3_ = i[0];
assign o[0] = o_3_;
assign o[1] = o_3_;
assign o[2] = o_3_;
assign o[3] = o_3_;
endmodule |
module bsg_decode_num_out_p10
(
i,
o
);
input [3:0] i;
output [9:0] o;
wire [9:0] o;
assign o = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << i;
endmodule |
module bsg_dff_en_width_p78
(
clk_i,
data_i,
en_i,
data_o
);
input [77:0] data_i;
output [77:0] data_o;
input clk_i;
input en_i;
wire [77:0] data_o;
reg data_o_77_sv2v_reg,data_o_76_sv2v_reg,data_o_75_sv2v_reg,data_o_74_sv2v_reg,
data_o_73_sv2v_reg,data_o_72_sv2v_reg,data_o_71_sv2v_reg,data_o_70_sv2v_reg,
data_o_69_sv2v_reg,data_o_68_sv2v_reg,data_o_67_sv2v_reg,data_o_66_sv2v_reg,
data_o_65_sv2v_reg,data_o_64_sv2v_reg,data_o_63_sv2v_reg,data_o_62_sv2v_reg,
data_o_61_sv2v_reg,data_o_60_sv2v_reg,data_o_59_sv2v_reg,data_o_58_sv2v_reg,data_o_57_sv2v_reg,
data_o_56_sv2v_reg,data_o_55_sv2v_reg,data_o_54_sv2v_reg,data_o_53_sv2v_reg,
data_o_52_sv2v_reg,data_o_51_sv2v_reg,data_o_50_sv2v_reg,data_o_49_sv2v_reg,
data_o_48_sv2v_reg,data_o_47_sv2v_reg,data_o_46_sv2v_reg,data_o_45_sv2v_reg,
data_o_44_sv2v_reg,data_o_43_sv2v_reg,data_o_42_sv2v_reg,data_o_41_sv2v_reg,
data_o_40_sv2v_reg,data_o_39_sv2v_reg,data_o_38_sv2v_reg,data_o_37_sv2v_reg,data_o_36_sv2v_reg,
data_o_35_sv2v_reg,data_o_34_sv2v_reg,data_o_33_sv2v_reg,data_o_32_sv2v_reg,
data_o_31_sv2v_reg,data_o_30_sv2v_reg,data_o_29_sv2v_reg,data_o_28_sv2v_reg,
data_o_27_sv2v_reg,data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,
data_o_23_sv2v_reg,data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,
data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,
data_o_14_sv2v_reg,data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,
data_o_10_sv2v_reg,data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,
data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,
data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[77] = data_o_77_sv2v_reg;
assign data_o[76] = data_o_76_sv2v_reg;
assign data_o[75] = data_o_75_sv2v_reg;
assign data_o[74] = data_o_74_sv2v_reg;
assign data_o[73] = data_o_73_sv2v_reg;
assign data_o[72] = data_o_72_sv2v_reg;
assign data_o[71] = data_o_71_sv2v_reg;
assign data_o[70] = data_o_70_sv2v_reg;
assign data_o[69] = data_o_69_sv2v_reg;
assign data_o[68] = data_o_68_sv2v_reg;
assign data_o[67] = data_o_67_sv2v_reg;
assign data_o[66] = data_o_66_sv2v_reg;
assign data_o[65] = data_o_65_sv2v_reg;
assign data_o[64] = data_o_64_sv2v_reg;
assign data_o[63] = data_o_63_sv2v_reg;
assign data_o[62] = data_o_62_sv2v_reg;
assign data_o[61] = data_o_61_sv2v_reg;
assign data_o[60] = data_o_60_sv2v_reg;
assign data_o[59] = data_o_59_sv2v_reg;
assign data_o[58] = data_o_58_sv2v_reg;
assign data_o[57] = data_o_57_sv2v_reg;
assign data_o[56] = data_o_56_sv2v_reg;
assign data_o[55] = data_o_55_sv2v_reg;
assign data_o[54] = data_o_54_sv2v_reg;
assign data_o[53] = data_o_53_sv2v_reg;
assign data_o[52] = data_o_52_sv2v_reg;
assign data_o[51] = data_o_51_sv2v_reg;
assign data_o[50] = data_o_50_sv2v_reg;
assign data_o[49] = data_o_49_sv2v_reg;
assign data_o[48] = data_o_48_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(en_i) begin
data_o_77_sv2v_reg <= data_i[77];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_76_sv2v_reg <= data_i[76];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_75_sv2v_reg <= data_i[75];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_74_sv2v_reg <= data_i[74];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_73_sv2v_reg <= data_i[73];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_72_sv2v_reg <= data_i[72];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_71_sv2v_reg <= data_i[71];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_70_sv2v_reg <= data_i[70];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_69_sv2v_reg <= data_i[69];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_68_sv2v_reg <= data_i[68];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_67_sv2v_reg <= data_i[67];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_66_sv2v_reg <= data_i[66];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_65_sv2v_reg <= data_i[65];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_64_sv2v_reg <= data_i[64];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_63_sv2v_reg <= data_i[63];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_62_sv2v_reg <= data_i[62];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_61_sv2v_reg <= data_i[61];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_60_sv2v_reg <= data_i[60];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_59_sv2v_reg <= data_i[59];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_58_sv2v_reg <= data_i[58];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_57_sv2v_reg <= data_i[57];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_56_sv2v_reg <= data_i[56];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_55_sv2v_reg <= data_i[55];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_54_sv2v_reg <= data_i[54];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_53_sv2v_reg <= data_i[53];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_52_sv2v_reg <= data_i[52];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_51_sv2v_reg <= data_i[51];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_50_sv2v_reg <= data_i[50];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_49_sv2v_reg <= data_i[49];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_48_sv2v_reg <= data_i[48];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_47_sv2v_reg <= data_i[47];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_46_sv2v_reg <= data_i[46];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_45_sv2v_reg <= data_i[45];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_44_sv2v_reg <= data_i[44];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_43_sv2v_reg <= data_i[43];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_42_sv2v_reg <= data_i[42];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_41_sv2v_reg <= data_i[41];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_40_sv2v_reg <= data_i[40];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_39_sv2v_reg <= data_i[39];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_38_sv2v_reg <= data_i[38];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_37_sv2v_reg <= data_i[37];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_36_sv2v_reg <= data_i[36];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_35_sv2v_reg <= data_i[35];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_34_sv2v_reg <= data_i[34];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_33_sv2v_reg <= data_i[33];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_32_sv2v_reg <= data_i[32];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_31_sv2v_reg <= data_i[31];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_30_sv2v_reg <= data_i[30];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_29_sv2v_reg <= data_i[29];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_28_sv2v_reg <= data_i[28];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_27_sv2v_reg <= data_i[27];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_26_sv2v_reg <= data_i[26];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_25_sv2v_reg <= data_i[25];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_24_sv2v_reg <= data_i[24];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_23_sv2v_reg <= data_i[23];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_22_sv2v_reg <= data_i[22];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_21_sv2v_reg <= data_i[21];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_20_sv2v_reg <= data_i[20];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_19_sv2v_reg <= data_i[19];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_18_sv2v_reg <= data_i[18];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(en_i) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_counter_clear_up_max_val_p1_init_val_p0
(
clk_i,
reset_i,
clear_i,
up_i,
count_o
);
output [0:0] count_o;
input clk_i;
input reset_i;
input clear_i;
input up_i;
wire [0:0] count_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
reg count_o_0_sv2v_reg;
assign count_o[0] = count_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
count_o_0_sv2v_reg <= N8;
end
end
assign N6 = count_o[0] ^ up_i;
assign N7 = (N0)? up_i :
(N1)? N6 : 1'b0;
assign N0 = clear_i;
assign N1 = N5;
assign N8 = (N2)? 1'b0 :
(N3)? N7 : 1'b0;
assign N2 = reset_i;
assign N3 = N4;
assign N4 = ~reset_i;
assign N5 = ~clear_i;
endmodule |
module bsg_mux_width_p39_els_p2
(
data_i,
sel_i,
data_o
);
input [77:0] data_i;
input [0:0] sel_i;
output [38:0] data_o;
wire [38:0] data_o;
wire N0,N1;
assign data_o[38] = (N1)? data_i[38] :
(N0)? data_i[77] : 1'b0;
assign N0 = sel_i[0];
assign data_o[37] = (N1)? data_i[37] :
(N0)? data_i[76] : 1'b0;
assign data_o[36] = (N1)? data_i[36] :
(N0)? data_i[75] : 1'b0;
assign data_o[35] = (N1)? data_i[35] :
(N0)? data_i[74] : 1'b0;
assign data_o[34] = (N1)? data_i[34] :
(N0)? data_i[73] : 1'b0;
assign data_o[33] = (N1)? data_i[33] :
(N0)? data_i[72] : 1'b0;
assign data_o[32] = (N1)? data_i[32] :
(N0)? data_i[71] : 1'b0;
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[70] : 1'b0;
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[69] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[68] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[67] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[66] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[65] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[64] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[63] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[62] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[61] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[60] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[59] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[58] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[57] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[56] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[55] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[54] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[53] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[52] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[51] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[50] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[49] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[48] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[47] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[46] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[45] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[44] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[43] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[42] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[41] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[40] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[39] : 1'b0;
assign N1 = ~sel_i[0];
endmodule |
module bsg_concentrate_static_1d
(
i,
o
);
input [4:0] i;
output [3:0] o;
wire [3:0] o;
assign o[3] = i[4];
assign o[2] = i[3];
assign o[1] = i[2];
assign o[0] = i[0];
endmodule |
module bsg_cache_decode
(
opcode_i,
decode_o
);
input [5:0] opcode_i;
output [18:0] decode_o;
wire [18:0] decode_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N44,N45,N46,N48,N50,N51,N52,N53,N54,N56,N58,N59,N61,N63,N64,N65,N66,N68,N69,
N70,N71,N72,N73,N75,N76,N77,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,
N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,
N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,
N143,N144,N145,N146,N147,N148,N149;
assign N6 = N68 & N36;
assign N8 = opcode_i[3] | opcode_i[2];
assign N9 = N44 | N37;
assign N10 = N8 | N9;
assign N11 = N50 | opcode_i[2];
assign N12 = N11 | N9;
assign N13 = opcode_i[3] | N63;
assign N14 = N13 | N9;
assign N16 = N44 | opcode_i[0];
assign N17 = N8 | N16;
assign N18 = N11 | N16;
assign N19 = N13 | N16;
assign N21 = opcode_i[1] | N37;
assign N22 = N8 | N21;
assign N23 = N11 | N21;
assign N24 = N13 | N21;
assign N26 = N50 & N63;
assign N27 = N44 & N37;
assign N28 = N26 & N27;
assign N29 = opcode_i[1] | opcode_i[0];
assign N30 = N11 | N29;
assign N31 = N13 | N29;
assign N33 = opcode_i[3] & opcode_i[2];
assign N36 = ~opcode_i[4];
assign N37 = ~opcode_i[0];
assign N38 = N36 | opcode_i[5];
assign N39 = opcode_i[3] | N38;
assign N40 = opcode_i[2] | N39;
assign N41 = opcode_i[1] | N40;
assign N42 = N37 | N41;
assign decode_o[11] = ~N42;
assign N44 = ~opcode_i[1];
assign N45 = N44 | N40;
assign N46 = opcode_i[0] | N45;
assign decode_o[10] = ~N46;
assign N48 = N37 | N45;
assign decode_o[9] = ~N48;
assign N50 = ~opcode_i[3];
assign N51 = N50 | N38;
assign N52 = opcode_i[2] | N51;
assign N53 = opcode_i[1] | N52;
assign N54 = opcode_i[0] | N53;
assign decode_o[8] = ~N54;
assign N56 = N37 | N53;
assign decode_o[7] = ~N56;
assign N58 = N44 | N52;
assign N59 = opcode_i[0] | N58;
assign decode_o[6] = ~N59;
assign N61 = N37 | N58;
assign decode_o[5] = ~N61;
assign N63 = ~opcode_i[2];
assign N64 = N63 | N51;
assign N65 = opcode_i[1] | N64;
assign N66 = opcode_i[0] | N65;
assign decode_o[4] = ~N66;
assign N68 = ~opcode_i[5];
assign N69 = opcode_i[4] | N68;
assign N70 = opcode_i[3] | N69;
assign N71 = opcode_i[2] | N70;
assign N72 = opcode_i[1] | N71;
assign N73 = opcode_i[0] | N72;
assign decode_o[1] = ~N73;
assign N75 = N63 | N70;
assign N76 = opcode_i[1] | N75;
assign N77 = opcode_i[0] | N76;
assign decode_o[0] = ~N77;
assign N79 = opcode_i[4] | opcode_i[5];
assign N80 = opcode_i[3] | N79;
assign N81 = opcode_i[2] | N80;
assign N82 = opcode_i[1] | N81;
assign N83 = opcode_i[0] | N82;
assign N84 = ~N83;
assign N85 = N37 | N82;
assign N86 = ~N85;
assign N87 = N44 | N81;
assign N88 = opcode_i[0] | N87;
assign N89 = ~N88;
assign N90 = N37 | N87;
assign N91 = ~N90;
assign N92 = N50 | N79;
assign N93 = N63 | N92;
assign N94 = opcode_i[1] | N93;
assign N95 = opcode_i[0] | N94;
assign N96 = ~N95;
assign N97 = N37 | N94;
assign N98 = ~N97;
assign N99 = N63 | N80;
assign N100 = opcode_i[1] | N99;
assign N101 = opcode_i[0] | N100;
assign N102 = ~N101;
assign N103 = N37 | N100;
assign N104 = ~N103;
assign N105 = N44 | N99;
assign N106 = opcode_i[0] | N105;
assign N107 = ~N106;
assign N108 = N37 | N105;
assign N109 = ~N108;
assign N110 = opcode_i[2] | N92;
assign N111 = opcode_i[1] | N110;
assign N112 = opcode_i[0] | N111;
assign N113 = ~N112;
assign N114 = N37 | N111;
assign N115 = ~N114;
assign N116 = N44 | N110;
assign N117 = opcode_i[0] | N116;
assign N118 = ~N117;
assign N119 = N37 | N116;
assign N120 = ~N119;
assign N121 = opcode_i[0] | N41;
assign decode_o[12] = ~N121;
assign { N35, N34 } = (N0)? { 1'b1, 1'b1 } :
(N1)? { 1'b1, 1'b0 } :
(N2)? { 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign N0 = N15;
assign N1 = N20;
assign N2 = N25;
assign N3 = N32;
assign N4 = N33;
assign decode_o[18:17] = (N5)? { N35, N34 } :
(N7)? { 1'b0, 1'b0 } : 1'b0;
assign N5 = N6;
assign N7 = ~N6;
assign N15 = N125 | N126;
assign N125 = N123 | N124;
assign N123 = ~N10;
assign N124 = ~N12;
assign N126 = ~N14;
assign N20 = N129 | N130;
assign N129 = N127 | N128;
assign N127 = ~N17;
assign N128 = ~N18;
assign N130 = ~N19;
assign N25 = N133 | N134;
assign N133 = N131 | N132;
assign N131 = ~N22;
assign N132 = ~N23;
assign N134 = ~N24;
assign N32 = N136 | N137;
assign N136 = N28 | N135;
assign N135 = ~N30;
assign N137 = ~N31;
assign decode_o[15] = N96 | N98;
assign decode_o[16] = N139 | N91;
assign N139 = N138 | N89;
assign N138 = N84 | N86;
assign decode_o[14] = N146 | N96;
assign N146 = N145 | N109;
assign N145 = N144 | N107;
assign N144 = N143 | N104;
assign N143 = N142 | N102;
assign N142 = N141 | N91;
assign N141 = N140 | N89;
assign N140 = N84 | N86;
assign decode_o[13] = N149 | N98;
assign N149 = N148 | N120;
assign N148 = N147 | N118;
assign N147 = N113 | N115;
assign decode_o[3] = ~decode_o[12];
assign decode_o[2] = decode_o[1] | decode_o[0];
endmodule |
module bsg_mux_width_p1_els_p4
(
data_i,
sel_i,
data_o
);
input [3:0] data_i;
input [1:0] sel_i;
output [0:0] data_o;
wire [0:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[1] :
(N3)? data_i[2] :
(N5)? data_i[3] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule |
module bsg_expand_bitmask_in_width_p4_expand_p2
(
i,
o
);
input [3:0] i;
output [7:0] o;
wire [7:0] o;
wire o_7_,o_5_,o_3_,o_1_;
assign o_7_ = i[3];
assign o[6] = o_7_;
assign o[7] = o_7_;
assign o_5_ = i[2];
assign o[4] = o_5_;
assign o[5] = o_5_;
assign o_3_ = i[1];
assign o[2] = o_3_;
assign o[3] = o_3_;
assign o_1_ = i[0];
assign o[0] = o_1_;
assign o[1] = o_1_;
endmodule |
module bsg_launch_sync_sync_posedge_7_unit
(
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [6:0] iclk_data_i;
output [6:0] iclk_data_o;
output [6:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [6:0] iclk_data_o,oclk_data_o,bsg_SYNC_1_r;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
reg iclk_data_o_6_sv2v_reg,iclk_data_o_5_sv2v_reg,iclk_data_o_4_sv2v_reg,
iclk_data_o_3_sv2v_reg,iclk_data_o_2_sv2v_reg,iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,bsg_SYNC_1_r_6_sv2v_reg,bsg_SYNC_1_r_5_sv2v_reg,bsg_SYNC_1_r_4_sv2v_reg,
bsg_SYNC_1_r_3_sv2v_reg,bsg_SYNC_1_r_2_sv2v_reg,bsg_SYNC_1_r_1_sv2v_reg,
bsg_SYNC_1_r_0_sv2v_reg,oclk_data_o_6_sv2v_reg,oclk_data_o_5_sv2v_reg,oclk_data_o_4_sv2v_reg,
oclk_data_o_3_sv2v_reg,oclk_data_o_2_sv2v_reg,oclk_data_o_1_sv2v_reg,
oclk_data_o_0_sv2v_reg;
assign iclk_data_o[6] = iclk_data_o_6_sv2v_reg;
assign iclk_data_o[5] = iclk_data_o_5_sv2v_reg;
assign iclk_data_o[4] = iclk_data_o_4_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[6] = bsg_SYNC_1_r_6_sv2v_reg;
assign bsg_SYNC_1_r[5] = bsg_SYNC_1_r_5_sv2v_reg;
assign bsg_SYNC_1_r[4] = bsg_SYNC_1_r_4_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[6] = oclk_data_o_6_sv2v_reg;
assign oclk_data_o[5] = oclk_data_o_5_sv2v_reg;
assign oclk_data_o[4] = oclk_data_o_4_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_6_sv2v_reg <= N9;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_5_sv2v_reg <= N8;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_4_sv2v_reg <= N7;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_3_sv2v_reg <= N6;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_2_sv2v_reg <= N5;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_1_sv2v_reg <= N4;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_0_sv2v_reg <= N3;
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_6_sv2v_reg <= iclk_data_o[6];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_5_sv2v_reg <= iclk_data_o[5];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_4_sv2v_reg <= iclk_data_o[4];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_6_sv2v_reg <= bsg_SYNC_1_r[6];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_5_sv2v_reg <= bsg_SYNC_1_r[5];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_4_sv2v_reg <= bsg_SYNC_1_r[4];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign { N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? iclk_data_i : 1'b0;
assign N0 = iclk_reset_i;
assign N1 = N2;
assign N2 = ~iclk_reset_i;
endmodule |
module bsg_dff_reset_en_width_p64
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire [63:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69;
reg data_o_63_sv2v_reg,data_o_62_sv2v_reg,data_o_61_sv2v_reg,data_o_60_sv2v_reg,
data_o_59_sv2v_reg,data_o_58_sv2v_reg,data_o_57_sv2v_reg,data_o_56_sv2v_reg,
data_o_55_sv2v_reg,data_o_54_sv2v_reg,data_o_53_sv2v_reg,data_o_52_sv2v_reg,
data_o_51_sv2v_reg,data_o_50_sv2v_reg,data_o_49_sv2v_reg,data_o_48_sv2v_reg,
data_o_47_sv2v_reg,data_o_46_sv2v_reg,data_o_45_sv2v_reg,data_o_44_sv2v_reg,data_o_43_sv2v_reg,
data_o_42_sv2v_reg,data_o_41_sv2v_reg,data_o_40_sv2v_reg,data_o_39_sv2v_reg,
data_o_38_sv2v_reg,data_o_37_sv2v_reg,data_o_36_sv2v_reg,data_o_35_sv2v_reg,
data_o_34_sv2v_reg,data_o_33_sv2v_reg,data_o_32_sv2v_reg,data_o_31_sv2v_reg,
data_o_30_sv2v_reg,data_o_29_sv2v_reg,data_o_28_sv2v_reg,data_o_27_sv2v_reg,
data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,
data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,data_o_18_sv2v_reg,
data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,data_o_14_sv2v_reg,
data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,
data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,
data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[63] = data_o_63_sv2v_reg;
assign data_o[62] = data_o_62_sv2v_reg;
assign data_o[61] = data_o_61_sv2v_reg;
assign data_o[60] = data_o_60_sv2v_reg;
assign data_o[59] = data_o_59_sv2v_reg;
assign data_o[58] = data_o_58_sv2v_reg;
assign data_o[57] = data_o_57_sv2v_reg;
assign data_o[56] = data_o_56_sv2v_reg;
assign data_o[55] = data_o_55_sv2v_reg;
assign data_o[54] = data_o_54_sv2v_reg;
assign data_o[53] = data_o_53_sv2v_reg;
assign data_o[52] = data_o_52_sv2v_reg;
assign data_o[51] = data_o_51_sv2v_reg;
assign data_o[50] = data_o_50_sv2v_reg;
assign data_o[49] = data_o_49_sv2v_reg;
assign data_o[48] = data_o_48_sv2v_reg;
assign data_o[47] = data_o_47_sv2v_reg;
assign data_o[46] = data_o_46_sv2v_reg;
assign data_o[45] = data_o_45_sv2v_reg;
assign data_o[44] = data_o_44_sv2v_reg;
assign data_o[43] = data_o_43_sv2v_reg;
assign data_o[42] = data_o_42_sv2v_reg;
assign data_o[41] = data_o_41_sv2v_reg;
assign data_o[40] = data_o_40_sv2v_reg;
assign data_o[39] = data_o_39_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(N3) begin
data_o_63_sv2v_reg <= N67;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_62_sv2v_reg <= N66;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_61_sv2v_reg <= N65;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_60_sv2v_reg <= N64;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_59_sv2v_reg <= N63;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_58_sv2v_reg <= N62;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_57_sv2v_reg <= N61;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_56_sv2v_reg <= N60;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_55_sv2v_reg <= N59;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_54_sv2v_reg <= N58;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_53_sv2v_reg <= N57;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_52_sv2v_reg <= N56;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_51_sv2v_reg <= N55;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_50_sv2v_reg <= N54;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_49_sv2v_reg <= N53;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_48_sv2v_reg <= N52;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_47_sv2v_reg <= N51;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_46_sv2v_reg <= N50;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_45_sv2v_reg <= N49;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_44_sv2v_reg <= N48;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_43_sv2v_reg <= N47;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_42_sv2v_reg <= N46;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_41_sv2v_reg <= N45;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_40_sv2v_reg <= N44;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_39_sv2v_reg <= N43;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_38_sv2v_reg <= N42;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_37_sv2v_reg <= N41;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_36_sv2v_reg <= N40;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_35_sv2v_reg <= N39;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_34_sv2v_reg <= N38;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_33_sv2v_reg <= N37;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_32_sv2v_reg <= N36;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_31_sv2v_reg <= N35;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_30_sv2v_reg <= N34;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_29_sv2v_reg <= N33;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_28_sv2v_reg <= N32;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_27_sv2v_reg <= N31;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_26_sv2v_reg <= N30;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_25_sv2v_reg <= N29;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_24_sv2v_reg <= N28;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_23_sv2v_reg <= N27;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_22_sv2v_reg <= N26;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_21_sv2v_reg <= N25;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_20_sv2v_reg <= N24;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_19_sv2v_reg <= N23;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_18_sv2v_reg <= N22;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_17_sv2v_reg <= N21;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_16_sv2v_reg <= N20;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_15_sv2v_reg <= N19;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_14_sv2v_reg <= N18;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_13_sv2v_reg <= N17;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_12_sv2v_reg <= N16;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_11_sv2v_reg <= N15;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_10_sv2v_reg <= N14;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_9_sv2v_reg <= N13;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_8_sv2v_reg <= N12;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_7_sv2v_reg <= N11;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_6_sv2v_reg <= N10;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_5_sv2v_reg <= N9;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_4_sv2v_reg <= N8;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_3_sv2v_reg <= N7;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_2_sv2v_reg <= N6;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_1_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(N3) begin
data_o_0_sv2v_reg <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N69)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N69)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N68 = ~reset_i;
assign N69 = en_i & N68;
endmodule |
module bsg_expand_bitmask_in_width_p8_expand_p1
(
i,
o
);
input [7:0] i;
output [7:0] o;
wire [7:0] o;
assign o[7] = i[7];
assign o[6] = i[6];
assign o[5] = i[5];
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_unconcentrate_static_5
(
i,
o
);
input [1:0] i;
output [2:0] o;
wire [2:0] o;
wire o_2_,o_0_;
assign o[1] = 1'b0;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mux_width_p1_els_p4_harden_p1_balanced_p1
(
data_i,
sel_i,
data_o
);
input [3:0] data_i;
input [1:0] sel_i;
output [0:0] data_o;
wire [0:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[1] :
(N3)? data_i[2] :
(N5)? data_i[3] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule |
module bsg_unconcentrate_static_1d
(
i,
o
);
input [3:0] i;
output [4:0] o;
wire [4:0] o;
wire o_4_,o_3_,o_2_,o_0_;
assign o[1] = 1'b0;
assign o_4_ = i[3];
assign o[4] = o_4_;
assign o_3_ = i[2];
assign o[3] = o_3_;
assign o_2_ = i[1];
assign o[2] = o_2_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mem_1r1w_synth_width_p16_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [15:0] w_data_i;
input [0:0] r_addr_i;
output [15:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [15:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
wire [31:0] mem;
reg mem_31_sv2v_reg,mem_30_sv2v_reg,mem_29_sv2v_reg,mem_28_sv2v_reg,mem_27_sv2v_reg,
mem_26_sv2v_reg,mem_25_sv2v_reg,mem_24_sv2v_reg,mem_23_sv2v_reg,mem_22_sv2v_reg,
mem_21_sv2v_reg,mem_20_sv2v_reg,mem_19_sv2v_reg,mem_18_sv2v_reg,mem_17_sv2v_reg,
mem_16_sv2v_reg,mem_15_sv2v_reg,mem_14_sv2v_reg,mem_13_sv2v_reg,mem_12_sv2v_reg,
mem_11_sv2v_reg,mem_10_sv2v_reg,mem_9_sv2v_reg,mem_8_sv2v_reg,mem_7_sv2v_reg,
mem_6_sv2v_reg,mem_5_sv2v_reg,mem_4_sv2v_reg,mem_3_sv2v_reg,mem_2_sv2v_reg,
mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[31] = mem_31_sv2v_reg;
assign mem[30] = mem_30_sv2v_reg;
assign mem[29] = mem_29_sv2v_reg;
assign mem[28] = mem_28_sv2v_reg;
assign mem[27] = mem_27_sv2v_reg;
assign mem[26] = mem_26_sv2v_reg;
assign mem[25] = mem_25_sv2v_reg;
assign mem[24] = mem_24_sv2v_reg;
assign mem[23] = mem_23_sv2v_reg;
assign mem[22] = mem_22_sv2v_reg;
assign mem[21] = mem_21_sv2v_reg;
assign mem[20] = mem_20_sv2v_reg;
assign mem[19] = mem_19_sv2v_reg;
assign mem[18] = mem_18_sv2v_reg;
assign mem[17] = mem_17_sv2v_reg;
assign mem[16] = mem_16_sv2v_reg;
assign mem[15] = mem_15_sv2v_reg;
assign mem[14] = mem_14_sv2v_reg;
assign mem[13] = mem_13_sv2v_reg;
assign mem[12] = mem_12_sv2v_reg;
assign mem[11] = mem_11_sv2v_reg;
assign mem[10] = mem_10_sv2v_reg;
assign mem[9] = mem_9_sv2v_reg;
assign mem[8] = mem_8_sv2v_reg;
assign mem[7] = mem_7_sv2v_reg;
assign mem[6] = mem_6_sv2v_reg;
assign mem[5] = mem_5_sv2v_reg;
assign mem[4] = mem_4_sv2v_reg;
assign mem[3] = mem_3_sv2v_reg;
assign mem[2] = mem_2_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[31] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[30] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[29] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[28] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[27] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[26] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[25] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[24] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[23] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[22] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[21] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[20] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[19] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[18] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[17] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[16] : 1'b0;
always @(posedge w_clk_i) begin
if(N8) begin
mem_31_sv2v_reg <= w_data_i[15];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_30_sv2v_reg <= w_data_i[14];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_29_sv2v_reg <= w_data_i[13];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_28_sv2v_reg <= w_data_i[12];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_27_sv2v_reg <= w_data_i[11];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_26_sv2v_reg <= w_data_i[10];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_25_sv2v_reg <= w_data_i[9];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_24_sv2v_reg <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_23_sv2v_reg <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_22_sv2v_reg <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_21_sv2v_reg <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_20_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_19_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_18_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_17_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_16_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_15_sv2v_reg <= w_data_i[15];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_14_sv2v_reg <= w_data_i[14];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_13_sv2v_reg <= w_data_i[13];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_12_sv2v_reg <= w_data_i[12];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_11_sv2v_reg <= w_data_i[11];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_10_sv2v_reg <= w_data_i[10];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_9_sv2v_reg <= w_data_i[9];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_8_sv2v_reg <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_7_sv2v_reg <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_6_sv2v_reg <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_5_sv2v_reg <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_4_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_3_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_2_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_1_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
endmodule |
module bsg_launch_sync_sync_posedge_4_unit
(
iclk_i,
iclk_reset_i,
oclk_i,
iclk_data_i,
iclk_data_o,
oclk_data_o
);
input [3:0] iclk_data_i;
output [3:0] iclk_data_o;
output [3:0] oclk_data_o;
input iclk_i;
input iclk_reset_i;
input oclk_i;
wire [3:0] iclk_data_o,oclk_data_o,bsg_SYNC_1_r;
wire N0,N1,N2,N3,N4,N5,N6;
reg iclk_data_o_3_sv2v_reg,iclk_data_o_2_sv2v_reg,iclk_data_o_1_sv2v_reg,
iclk_data_o_0_sv2v_reg,bsg_SYNC_1_r_3_sv2v_reg,bsg_SYNC_1_r_2_sv2v_reg,
bsg_SYNC_1_r_1_sv2v_reg,bsg_SYNC_1_r_0_sv2v_reg,oclk_data_o_3_sv2v_reg,oclk_data_o_2_sv2v_reg,
oclk_data_o_1_sv2v_reg,oclk_data_o_0_sv2v_reg;
assign iclk_data_o[3] = iclk_data_o_3_sv2v_reg;
assign iclk_data_o[2] = iclk_data_o_2_sv2v_reg;
assign iclk_data_o[1] = iclk_data_o_1_sv2v_reg;
assign iclk_data_o[0] = iclk_data_o_0_sv2v_reg;
assign bsg_SYNC_1_r[3] = bsg_SYNC_1_r_3_sv2v_reg;
assign bsg_SYNC_1_r[2] = bsg_SYNC_1_r_2_sv2v_reg;
assign bsg_SYNC_1_r[1] = bsg_SYNC_1_r_1_sv2v_reg;
assign bsg_SYNC_1_r[0] = bsg_SYNC_1_r_0_sv2v_reg;
assign oclk_data_o[3] = oclk_data_o_3_sv2v_reg;
assign oclk_data_o[2] = oclk_data_o_2_sv2v_reg;
assign oclk_data_o[1] = oclk_data_o_1_sv2v_reg;
assign oclk_data_o[0] = oclk_data_o_0_sv2v_reg;
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_3_sv2v_reg <= N6;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_2_sv2v_reg <= N5;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_1_sv2v_reg <= N4;
end
end
always @(posedge iclk_i) begin
if(1'b1) begin
iclk_data_o_0_sv2v_reg <= N3;
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_3_sv2v_reg <= iclk_data_o[3];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_2_sv2v_reg <= iclk_data_o[2];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_1_sv2v_reg <= iclk_data_o[1];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
bsg_SYNC_1_r_0_sv2v_reg <= iclk_data_o[0];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_3_sv2v_reg <= bsg_SYNC_1_r[3];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_2_sv2v_reg <= bsg_SYNC_1_r[2];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_1_sv2v_reg <= bsg_SYNC_1_r[1];
end
end
always @(posedge oclk_i) begin
if(1'b1) begin
oclk_data_o_0_sv2v_reg <= bsg_SYNC_1_r[0];
end
end
assign { N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? iclk_data_i : 1'b0;
assign N0 = iclk_reset_i;
assign N1 = N2;
assign N2 = ~iclk_reset_i;
endmodule |
module bsg_dff_width_p2_harden_p1
(
clk_i,
data_i,
data_o
);
input [1:0] data_i;
output [1:0] data_o;
input clk_i;
wire [1:0] data_o;
reg data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_wormhole_router_decoder_dor_2_2_1
(
target_cord_i,
my_cord_i,
req_o
);
input [4:0] target_cord_i;
input [4:0] my_cord_i;
output [4:0] req_o;
wire [4:0] req_o;
wire N0,N1,N2,N3;
wire [1:0] eq;
wire [0:0] lt,gt;
assign eq[0] = target_cord_i[1:0] == my_cord_i[1:0];
assign lt[0] = target_cord_i[1:0] < my_cord_i[1:0];
assign eq[1] = target_cord_i[4:2] == my_cord_i[4:2];
assign req_o[3] = target_cord_i[4:2] < my_cord_i[4:2];
assign gt[0] = N0 & N1;
assign N0 = ~eq[0];
assign N1 = ~lt[0];
assign req_o[4] = N2 & N3;
assign N2 = ~eq[1];
assign N3 = ~req_o[3];
assign req_o[0] = eq[1] & eq[0];
assign req_o[1] = eq[1] & lt[0];
assign req_o[2] = eq[1] & gt[0];
endmodule |
module bsg_mux_one_hot_62_3
(
data_i,
sel_one_hot_i,
data_o
);
input [185:0] data_i;
input [2:0] sel_one_hot_i;
output [61:0] data_o;
wire [61:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61;
wire [185:0] data_masked;
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[2];
assign data_masked[150] = data_i[150] & sel_one_hot_i[2];
assign data_masked[149] = data_i[149] & sel_one_hot_i[2];
assign data_masked[148] = data_i[148] & sel_one_hot_i[2];
assign data_masked[147] = data_i[147] & sel_one_hot_i[2];
assign data_masked[146] = data_i[146] & sel_one_hot_i[2];
assign data_masked[145] = data_i[145] & sel_one_hot_i[2];
assign data_masked[144] = data_i[144] & sel_one_hot_i[2];
assign data_masked[143] = data_i[143] & sel_one_hot_i[2];
assign data_masked[142] = data_i[142] & sel_one_hot_i[2];
assign data_masked[141] = data_i[141] & sel_one_hot_i[2];
assign data_masked[140] = data_i[140] & sel_one_hot_i[2];
assign data_masked[139] = data_i[139] & sel_one_hot_i[2];
assign data_masked[138] = data_i[138] & sel_one_hot_i[2];
assign data_masked[137] = data_i[137] & sel_one_hot_i[2];
assign data_masked[136] = data_i[136] & sel_one_hot_i[2];
assign data_masked[135] = data_i[135] & sel_one_hot_i[2];
assign data_masked[134] = data_i[134] & sel_one_hot_i[2];
assign data_masked[133] = data_i[133] & sel_one_hot_i[2];
assign data_masked[132] = data_i[132] & sel_one_hot_i[2];
assign data_masked[131] = data_i[131] & sel_one_hot_i[2];
assign data_masked[130] = data_i[130] & sel_one_hot_i[2];
assign data_masked[129] = data_i[129] & sel_one_hot_i[2];
assign data_masked[128] = data_i[128] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[2];
assign data_masked[126] = data_i[126] & sel_one_hot_i[2];
assign data_masked[125] = data_i[125] & sel_one_hot_i[2];
assign data_masked[124] = data_i[124] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[124] | data_masked[62];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[125] | data_masked[63];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[126] | data_masked[64];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[127] | data_masked[65];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[128] | data_masked[66];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[129] | data_masked[67];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[130] | data_masked[68];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[131] | data_masked[69];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[132] | data_masked[70];
assign data_o[9] = N9 | data_masked[9];
assign N9 = data_masked[133] | data_masked[71];
assign data_o[10] = N10 | data_masked[10];
assign N10 = data_masked[134] | data_masked[72];
assign data_o[11] = N11 | data_masked[11];
assign N11 = data_masked[135] | data_masked[73];
assign data_o[12] = N12 | data_masked[12];
assign N12 = data_masked[136] | data_masked[74];
assign data_o[13] = N13 | data_masked[13];
assign N13 = data_masked[137] | data_masked[75];
assign data_o[14] = N14 | data_masked[14];
assign N14 = data_masked[138] | data_masked[76];
assign data_o[15] = N15 | data_masked[15];
assign N15 = data_masked[139] | data_masked[77];
assign data_o[16] = N16 | data_masked[16];
assign N16 = data_masked[140] | data_masked[78];
assign data_o[17] = N17 | data_masked[17];
assign N17 = data_masked[141] | data_masked[79];
assign data_o[18] = N18 | data_masked[18];
assign N18 = data_masked[142] | data_masked[80];
assign data_o[19] = N19 | data_masked[19];
assign N19 = data_masked[143] | data_masked[81];
assign data_o[20] = N20 | data_masked[20];
assign N20 = data_masked[144] | data_masked[82];
assign data_o[21] = N21 | data_masked[21];
assign N21 = data_masked[145] | data_masked[83];
assign data_o[22] = N22 | data_masked[22];
assign N22 = data_masked[146] | data_masked[84];
assign data_o[23] = N23 | data_masked[23];
assign N23 = data_masked[147] | data_masked[85];
assign data_o[24] = N24 | data_masked[24];
assign N24 = data_masked[148] | data_masked[86];
assign data_o[25] = N25 | data_masked[25];
assign N25 = data_masked[149] | data_masked[87];
assign data_o[26] = N26 | data_masked[26];
assign N26 = data_masked[150] | data_masked[88];
assign data_o[27] = N27 | data_masked[27];
assign N27 = data_masked[151] | data_masked[89];
assign data_o[28] = N28 | data_masked[28];
assign N28 = data_masked[152] | data_masked[90];
assign data_o[29] = N29 | data_masked[29];
assign N29 = data_masked[153] | data_masked[91];
assign data_o[30] = N30 | data_masked[30];
assign N30 = data_masked[154] | data_masked[92];
assign data_o[31] = N31 | data_masked[31];
assign N31 = data_masked[155] | data_masked[93];
assign data_o[32] = N32 | data_masked[32];
assign N32 = data_masked[156] | data_masked[94];
assign data_o[33] = N33 | data_masked[33];
assign N33 = data_masked[157] | data_masked[95];
assign data_o[34] = N34 | data_masked[34];
assign N34 = data_masked[158] | data_masked[96];
assign data_o[35] = N35 | data_masked[35];
assign N35 = data_masked[159] | data_masked[97];
assign data_o[36] = N36 | data_masked[36];
assign N36 = data_masked[160] | data_masked[98];
assign data_o[37] = N37 | data_masked[37];
assign N37 = data_masked[161] | data_masked[99];
assign data_o[38] = N38 | data_masked[38];
assign N38 = data_masked[162] | data_masked[100];
assign data_o[39] = N39 | data_masked[39];
assign N39 = data_masked[163] | data_masked[101];
assign data_o[40] = N40 | data_masked[40];
assign N40 = data_masked[164] | data_masked[102];
assign data_o[41] = N41 | data_masked[41];
assign N41 = data_masked[165] | data_masked[103];
assign data_o[42] = N42 | data_masked[42];
assign N42 = data_masked[166] | data_masked[104];
assign data_o[43] = N43 | data_masked[43];
assign N43 = data_masked[167] | data_masked[105];
assign data_o[44] = N44 | data_masked[44];
assign N44 = data_masked[168] | data_masked[106];
assign data_o[45] = N45 | data_masked[45];
assign N45 = data_masked[169] | data_masked[107];
assign data_o[46] = N46 | data_masked[46];
assign N46 = data_masked[170] | data_masked[108];
assign data_o[47] = N47 | data_masked[47];
assign N47 = data_masked[171] | data_masked[109];
assign data_o[48] = N48 | data_masked[48];
assign N48 = data_masked[172] | data_masked[110];
assign data_o[49] = N49 | data_masked[49];
assign N49 = data_masked[173] | data_masked[111];
assign data_o[50] = N50 | data_masked[50];
assign N50 = data_masked[174] | data_masked[112];
assign data_o[51] = N51 | data_masked[51];
assign N51 = data_masked[175] | data_masked[113];
assign data_o[52] = N52 | data_masked[52];
assign N52 = data_masked[176] | data_masked[114];
assign data_o[53] = N53 | data_masked[53];
assign N53 = data_masked[177] | data_masked[115];
assign data_o[54] = N54 | data_masked[54];
assign N54 = data_masked[178] | data_masked[116];
assign data_o[55] = N55 | data_masked[55];
assign N55 = data_masked[179] | data_masked[117];
assign data_o[56] = N56 | data_masked[56];
assign N56 = data_masked[180] | data_masked[118];
assign data_o[57] = N57 | data_masked[57];
assign N57 = data_masked[181] | data_masked[119];
assign data_o[58] = N58 | data_masked[58];
assign N58 = data_masked[182] | data_masked[120];
assign data_o[59] = N59 | data_masked[59];
assign N59 = data_masked[183] | data_masked[121];
assign data_o[60] = N60 | data_masked[60];
assign N60 = data_masked[184] | data_masked[122];
assign data_o[61] = N61 | data_masked[61];
assign N61 = data_masked[185] | data_masked[123];
endmodule |
module bsg_async_ptr_gray_lg_size_p4
(
w_clk_i,
w_reset_i,
w_inc_i,
r_clk_i,
w_ptr_binary_r_o,
w_ptr_gray_r_o,
w_ptr_gray_r_rsync_o
);
output [3:0] w_ptr_binary_r_o;
output [3:0] w_ptr_gray_r_o;
output [3:0] w_ptr_gray_r_rsync_o;
input w_clk_i;
input w_reset_i;
input w_inc_i;
input r_clk_i;
wire [3:0] w_ptr_binary_r_o,w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p1_r,w_ptr_p2,
w_ptr_gray_n;
wire N0,N1,N2,N3,N4,N5;
reg w_ptr_p1_r_3_sv2v_reg,w_ptr_p1_r_2_sv2v_reg,w_ptr_p1_r_1_sv2v_reg,
w_ptr_p1_r_0_sv2v_reg,w_ptr_binary_r_o_3_sv2v_reg,w_ptr_binary_r_o_2_sv2v_reg,
w_ptr_binary_r_o_1_sv2v_reg,w_ptr_binary_r_o_0_sv2v_reg;
assign w_ptr_p1_r[3] = w_ptr_p1_r_3_sv2v_reg;
assign w_ptr_p1_r[2] = w_ptr_p1_r_2_sv2v_reg;
assign w_ptr_p1_r[1] = w_ptr_p1_r_1_sv2v_reg;
assign w_ptr_p1_r[0] = w_ptr_p1_r_0_sv2v_reg;
assign w_ptr_binary_r_o[3] = w_ptr_binary_r_o_3_sv2v_reg;
assign w_ptr_binary_r_o[2] = w_ptr_binary_r_o_2_sv2v_reg;
assign w_ptr_binary_r_o[1] = w_ptr_binary_r_o_1_sv2v_reg;
assign w_ptr_binary_r_o[0] = w_ptr_binary_r_o_0_sv2v_reg;
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_3_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_3_sv2v_reg <= w_ptr_p2[3];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_2_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_2_sv2v_reg <= w_ptr_p2[2];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_1_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_1_sv2v_reg <= w_ptr_p2[1];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_0_sv2v_reg <= 1'b1;
end else if(w_inc_i) begin
w_ptr_p1_r_0_sv2v_reg <= w_ptr_p2[0];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_3_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_3_sv2v_reg <= w_ptr_p1_r[3];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_2_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_2_sv2v_reg <= w_ptr_p1_r[2];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_1_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_1_sv2v_reg <= w_ptr_p1_r[1];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_0_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_0_sv2v_reg <= w_ptr_p1_r[0];
end
end
bsg_launch_sync_sync_width_p4_use_negedge_for_launch_p0_use_async_reset_p0
ptr_sync
(
.iclk_i(w_clk_i),
.iclk_reset_i(w_reset_i),
.oclk_i(r_clk_i),
.iclk_data_i(w_ptr_gray_n),
.iclk_data_o(w_ptr_gray_r_o),
.oclk_data_o(w_ptr_gray_r_rsync_o)
);
assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[3:3], N3, N4, N5 } :
(N1)? w_ptr_gray_r_o : 1'b0;
assign N0 = w_inc_i;
assign N1 = N2;
assign N2 = ~w_inc_i;
assign N3 = w_ptr_p1_r[3] ^ w_ptr_p1_r[2];
assign N4 = w_ptr_p1_r[2] ^ w_ptr_p1_r[1];
assign N5 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];
endmodule |
module bsg_async_credit_counter_4_3_1_2_1_1
(
w_clk_i,
w_inc_token_i,
w_reset_i,
r_clk_i,
r_reset_i,
r_dec_credit_i,
r_infinite_credits_i,
r_credits_avail_o
);
input w_clk_i;
input w_inc_token_i;
input w_reset_i;
input r_clk_i;
input r_reset_i;
input r_dec_credit_i;
input r_infinite_credits_i;
output r_credits_avail_o;
wire r_credits_avail_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,r_counter_r_lo_bits_nonzero,N19,N20,N21,sv2v_dc_1,sv2v_dc_2,sv2v_dc_3,
sv2v_dc_4,sv2v_dc_5;
wire [7:0] r_counter_r;
wire [4:0] w_counter_gray_r,w_counter_gray_r_rsync;
wire [3:0] r_counter_r_hi_bits_gray;
reg r_counter_r_7_sv2v_reg,r_counter_r_6_sv2v_reg,r_counter_r_5_sv2v_reg,
r_counter_r_4_sv2v_reg,r_counter_r_3_sv2v_reg,r_counter_r_2_sv2v_reg,
r_counter_r_1_sv2v_reg,r_counter_r_0_sv2v_reg;
assign r_counter_r[7] = r_counter_r_7_sv2v_reg;
assign r_counter_r[6] = r_counter_r_6_sv2v_reg;
assign r_counter_r[5] = r_counter_r_5_sv2v_reg;
assign r_counter_r[4] = r_counter_r_4_sv2v_reg;
assign r_counter_r[3] = r_counter_r_3_sv2v_reg;
assign r_counter_r[2] = r_counter_r_2_sv2v_reg;
assign r_counter_r[1] = r_counter_r_1_sv2v_reg;
assign r_counter_r[0] = r_counter_r_0_sv2v_reg;
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_7_sv2v_reg <= N18;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_6_sv2v_reg <= N17;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_5_sv2v_reg <= N16;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_4_sv2v_reg <= N15;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_3_sv2v_reg <= N14;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_2_sv2v_reg <= N13;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_1_sv2v_reg <= N12;
end
end
always @(posedge r_clk_i) begin
if(1'b1) begin
r_counter_r_0_sv2v_reg <= N11;
end
end
bsg_async_ptr_gray_5_1_1
bapg
(
.w_clk_i(w_clk_i),
.w_reset_i(w_reset_i),
.w_inc_i(w_inc_token_i),
.r_clk_i(r_clk_i),
.w_ptr_binary_r_o({ sv2v_dc_1, sv2v_dc_2, sv2v_dc_3, sv2v_dc_4, sv2v_dc_5 }),
.w_ptr_gray_r_o(w_counter_gray_r),
.w_ptr_gray_r_rsync_o(w_counter_gray_r_rsync)
);
assign N19 = { r_counter_r[7:7], r_counter_r_hi_bits_gray } != w_counter_gray_r_rsync;
assign { N10, N9, N8, N7, N6, N5, N4, N3 } = r_counter_r + r_dec_credit_i;
assign { N18, N17, N16, N15, N14, N13, N12, N11 } = (N0)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N10, N9, N8, N7, N6, N5, N4, N3 } : 1'b0;
assign N0 = r_reset_i;
assign N1 = N2;
assign N2 = ~r_reset_i;
assign r_counter_r_lo_bits_nonzero = N20 | r_counter_r[0];
assign N20 = r_counter_r[2] | r_counter_r[1];
assign r_counter_r_hi_bits_gray[3] = r_counter_r[7] ^ r_counter_r[6];
assign r_counter_r_hi_bits_gray[2] = r_counter_r[6] ^ r_counter_r[5];
assign r_counter_r_hi_bits_gray[1] = r_counter_r[5] ^ r_counter_r[4];
assign r_counter_r_hi_bits_gray[0] = r_counter_r[4] ^ r_counter_r[3];
assign r_credits_avail_o = N21 | N19;
assign N21 = r_infinite_credits_i | r_counter_r_lo_bits_nonzero;
endmodule |
module bsg_dff_width_p25
(
clk_i,
data_i,
data_o
);
input [24:0] data_i;
output [24:0] data_o;
input clk_i;
wire [24:0] data_o;
reg data_o_24_sv2v_reg,data_o_23_sv2v_reg,data_o_22_sv2v_reg,data_o_21_sv2v_reg,
data_o_20_sv2v_reg,data_o_19_sv2v_reg,data_o_18_sv2v_reg,data_o_17_sv2v_reg,
data_o_16_sv2v_reg,data_o_15_sv2v_reg,data_o_14_sv2v_reg,data_o_13_sv2v_reg,
data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,data_o_9_sv2v_reg,
data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,data_o_4_sv2v_reg,
data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= data_i[24];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= data_i[23];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= data_i[22];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= data_i[21];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= data_i[20];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= data_i[19];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= data_i[18];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_async_ptr_gray_lg_size_p7
(
w_clk_i,
w_reset_i,
w_inc_i,
r_clk_i,
w_ptr_binary_r_o,
w_ptr_gray_r_o,
w_ptr_gray_r_rsync_o
);
output [6:0] w_ptr_binary_r_o;
output [6:0] w_ptr_gray_r_o;
output [6:0] w_ptr_gray_r_rsync_o;
input w_clk_i;
input w_reset_i;
input w_inc_i;
input r_clk_i;
wire [6:0] w_ptr_binary_r_o,w_ptr_gray_r_o,w_ptr_gray_r_rsync_o,w_ptr_p1_r,w_ptr_p2,
w_ptr_gray_n;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
reg w_ptr_p1_r_6_sv2v_reg,w_ptr_p1_r_5_sv2v_reg,w_ptr_p1_r_4_sv2v_reg,
w_ptr_p1_r_3_sv2v_reg,w_ptr_p1_r_2_sv2v_reg,w_ptr_p1_r_1_sv2v_reg,w_ptr_p1_r_0_sv2v_reg,
w_ptr_binary_r_o_6_sv2v_reg,w_ptr_binary_r_o_5_sv2v_reg,w_ptr_binary_r_o_4_sv2v_reg,
w_ptr_binary_r_o_3_sv2v_reg,w_ptr_binary_r_o_2_sv2v_reg,
w_ptr_binary_r_o_1_sv2v_reg,w_ptr_binary_r_o_0_sv2v_reg;
assign w_ptr_p1_r[6] = w_ptr_p1_r_6_sv2v_reg;
assign w_ptr_p1_r[5] = w_ptr_p1_r_5_sv2v_reg;
assign w_ptr_p1_r[4] = w_ptr_p1_r_4_sv2v_reg;
assign w_ptr_p1_r[3] = w_ptr_p1_r_3_sv2v_reg;
assign w_ptr_p1_r[2] = w_ptr_p1_r_2_sv2v_reg;
assign w_ptr_p1_r[1] = w_ptr_p1_r_1_sv2v_reg;
assign w_ptr_p1_r[0] = w_ptr_p1_r_0_sv2v_reg;
assign w_ptr_binary_r_o[6] = w_ptr_binary_r_o_6_sv2v_reg;
assign w_ptr_binary_r_o[5] = w_ptr_binary_r_o_5_sv2v_reg;
assign w_ptr_binary_r_o[4] = w_ptr_binary_r_o_4_sv2v_reg;
assign w_ptr_binary_r_o[3] = w_ptr_binary_r_o_3_sv2v_reg;
assign w_ptr_binary_r_o[2] = w_ptr_binary_r_o_2_sv2v_reg;
assign w_ptr_binary_r_o[1] = w_ptr_binary_r_o_1_sv2v_reg;
assign w_ptr_binary_r_o[0] = w_ptr_binary_r_o_0_sv2v_reg;
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_6_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_6_sv2v_reg <= w_ptr_p2[6];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_5_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_5_sv2v_reg <= w_ptr_p2[5];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_4_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_4_sv2v_reg <= w_ptr_p2[4];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_3_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_3_sv2v_reg <= w_ptr_p2[3];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_2_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_2_sv2v_reg <= w_ptr_p2[2];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_1_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_p1_r_1_sv2v_reg <= w_ptr_p2[1];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_p1_r_0_sv2v_reg <= 1'b1;
end else if(w_inc_i) begin
w_ptr_p1_r_0_sv2v_reg <= w_ptr_p2[0];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_6_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_6_sv2v_reg <= w_ptr_p1_r[6];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_5_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_5_sv2v_reg <= w_ptr_p1_r[5];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_4_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_4_sv2v_reg <= w_ptr_p1_r[4];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_3_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_3_sv2v_reg <= w_ptr_p1_r[3];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_2_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_2_sv2v_reg <= w_ptr_p1_r[2];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_1_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_1_sv2v_reg <= w_ptr_p1_r[1];
end
end
always @(posedge w_clk_i) begin
if(w_reset_i) begin
w_ptr_binary_r_o_0_sv2v_reg <= 1'b0;
end else if(w_inc_i) begin
w_ptr_binary_r_o_0_sv2v_reg <= w_ptr_p1_r[0];
end
end
bsg_launch_sync_sync_width_p7_use_negedge_for_launch_p0_use_async_reset_p0
ptr_sync
(
.iclk_i(w_clk_i),
.iclk_reset_i(w_reset_i),
.oclk_i(r_clk_i),
.iclk_data_i(w_ptr_gray_n),
.iclk_data_o(w_ptr_gray_r_o),
.oclk_data_o(w_ptr_gray_r_rsync_o)
);
assign w_ptr_p2 = w_ptr_p1_r + 1'b1;
assign w_ptr_gray_n = (N0)? { w_ptr_p1_r[6:6], N3, N4, N5, N6, N7, N8 } :
(N1)? w_ptr_gray_r_o : 1'b0;
assign N0 = w_inc_i;
assign N1 = N2;
assign N2 = ~w_inc_i;
assign N3 = w_ptr_p1_r[6] ^ w_ptr_p1_r[5];
assign N4 = w_ptr_p1_r[5] ^ w_ptr_p1_r[4];
assign N5 = w_ptr_p1_r[4] ^ w_ptr_p1_r[3];
assign N6 = w_ptr_p1_r[3] ^ w_ptr_p1_r[2];
assign N7 = w_ptr_p1_r[2] ^ w_ptr_p1_r[1];
assign N8 = w_ptr_p1_r[1] ^ w_ptr_p1_r[0];
endmodule |
module bsg_dff_width_p3_harden_p1
(
clk_i,
data_i,
data_o
);
input [2:0] data_i;
output [2:0] data_o;
input clk_i;
wire [2:0] data_o;
reg data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_dff_width_p9_harden_p1
(
clk_i,
data_i,
data_o
);
input [8:0] data_i;
output [8:0] data_o;
input clk_i;
wire [8:0] data_o;
reg data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,data_o_5_sv2v_reg,
data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_dff_reset_width_p3
(
clk_i,
reset_i,
data_i,
data_o
);
input [2:0] data_i;
output [2:0] data_o;
input clk_i;
input reset_i;
wire [2:0] data_o;
wire N0,N1,N2,N3,N4,N5;
reg data_o_2_sv2v_reg,data_o_1_sv2v_reg,data_o_0_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= N5;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= N4;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= N3;
end
end
assign { N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_mux_width_p16_els_p4
(
data_i,
sel_i,
data_o
);
input [63:0] data_i;
input [1:0] sel_i;
output [15:0] data_o;
wire [15:0] data_o;
wire N0,N1,N2,N3,N4,N5;
assign data_o[15] = (N2)? data_i[15] :
(N4)? data_i[31] :
(N3)? data_i[47] :
(N5)? data_i[63] : 1'b0;
assign data_o[14] = (N2)? data_i[14] :
(N4)? data_i[30] :
(N3)? data_i[46] :
(N5)? data_i[62] : 1'b0;
assign data_o[13] = (N2)? data_i[13] :
(N4)? data_i[29] :
(N3)? data_i[45] :
(N5)? data_i[61] : 1'b0;
assign data_o[12] = (N2)? data_i[12] :
(N4)? data_i[28] :
(N3)? data_i[44] :
(N5)? data_i[60] : 1'b0;
assign data_o[11] = (N2)? data_i[11] :
(N4)? data_i[27] :
(N3)? data_i[43] :
(N5)? data_i[59] : 1'b0;
assign data_o[10] = (N2)? data_i[10] :
(N4)? data_i[26] :
(N3)? data_i[42] :
(N5)? data_i[58] : 1'b0;
assign data_o[9] = (N2)? data_i[9] :
(N4)? data_i[25] :
(N3)? data_i[41] :
(N5)? data_i[57] : 1'b0;
assign data_o[8] = (N2)? data_i[8] :
(N4)? data_i[24] :
(N3)? data_i[40] :
(N5)? data_i[56] : 1'b0;
assign data_o[7] = (N2)? data_i[7] :
(N4)? data_i[23] :
(N3)? data_i[39] :
(N5)? data_i[55] : 1'b0;
assign data_o[6] = (N2)? data_i[6] :
(N4)? data_i[22] :
(N3)? data_i[38] :
(N5)? data_i[54] : 1'b0;
assign data_o[5] = (N2)? data_i[5] :
(N4)? data_i[21] :
(N3)? data_i[37] :
(N5)? data_i[53] : 1'b0;
assign data_o[4] = (N2)? data_i[4] :
(N4)? data_i[20] :
(N3)? data_i[36] :
(N5)? data_i[52] : 1'b0;
assign data_o[3] = (N2)? data_i[3] :
(N4)? data_i[19] :
(N3)? data_i[35] :
(N5)? data_i[51] : 1'b0;
assign data_o[2] = (N2)? data_i[2] :
(N4)? data_i[18] :
(N3)? data_i[34] :
(N5)? data_i[50] : 1'b0;
assign data_o[1] = (N2)? data_i[1] :
(N4)? data_i[17] :
(N3)? data_i[33] :
(N5)? data_i[49] : 1'b0;
assign data_o[0] = (N2)? data_i[0] :
(N4)? data_i[16] :
(N3)? data_i[32] :
(N5)? data_i[48] : 1'b0;
assign N0 = ~sel_i[0];
assign N1 = ~sel_i[1];
assign N2 = N0 & N1;
assign N3 = N0 & sel_i[1];
assign N4 = sel_i[0] & N1;
assign N5 = sel_i[0] & sel_i[1];
endmodule |
module bsg_unconcentrate_static_09
(
i,
o
);
input [1:0] i;
output [4:0] o;
wire [4:0] o;
wire o_3_,o_0_;
assign o[4] = 1'b0;
assign o[2] = 1'b0;
assign o[1] = 1'b0;
assign o_3_ = i[1];
assign o[3] = o_3_;
assign o_0_ = i[0];
assign o[0] = o_0_;
endmodule |
module bsg_mux_one_hot_width_p62_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [247:0] data_i;
input [3:0] sel_one_hot_i;
output [61:0] data_o;
wire [61:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123;
wire [247:0] data_masked;
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[75] = data_i[75] & sel_one_hot_i[1];
assign data_masked[74] = data_i[74] & sel_one_hot_i[1];
assign data_masked[73] = data_i[73] & sel_one_hot_i[1];
assign data_masked[72] = data_i[72] & sel_one_hot_i[1];
assign data_masked[71] = data_i[71] & sel_one_hot_i[1];
assign data_masked[70] = data_i[70] & sel_one_hot_i[1];
assign data_masked[69] = data_i[69] & sel_one_hot_i[1];
assign data_masked[68] = data_i[68] & sel_one_hot_i[1];
assign data_masked[67] = data_i[67] & sel_one_hot_i[1];
assign data_masked[66] = data_i[66] & sel_one_hot_i[1];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[151] = data_i[151] & sel_one_hot_i[2];
assign data_masked[150] = data_i[150] & sel_one_hot_i[2];
assign data_masked[149] = data_i[149] & sel_one_hot_i[2];
assign data_masked[148] = data_i[148] & sel_one_hot_i[2];
assign data_masked[147] = data_i[147] & sel_one_hot_i[2];
assign data_masked[146] = data_i[146] & sel_one_hot_i[2];
assign data_masked[145] = data_i[145] & sel_one_hot_i[2];
assign data_masked[144] = data_i[144] & sel_one_hot_i[2];
assign data_masked[143] = data_i[143] & sel_one_hot_i[2];
assign data_masked[142] = data_i[142] & sel_one_hot_i[2];
assign data_masked[141] = data_i[141] & sel_one_hot_i[2];
assign data_masked[140] = data_i[140] & sel_one_hot_i[2];
assign data_masked[139] = data_i[139] & sel_one_hot_i[2];
assign data_masked[138] = data_i[138] & sel_one_hot_i[2];
assign data_masked[137] = data_i[137] & sel_one_hot_i[2];
assign data_masked[136] = data_i[136] & sel_one_hot_i[2];
assign data_masked[135] = data_i[135] & sel_one_hot_i[2];
assign data_masked[134] = data_i[134] & sel_one_hot_i[2];
assign data_masked[133] = data_i[133] & sel_one_hot_i[2];
assign data_masked[132] = data_i[132] & sel_one_hot_i[2];
assign data_masked[131] = data_i[131] & sel_one_hot_i[2];
assign data_masked[130] = data_i[130] & sel_one_hot_i[2];
assign data_masked[129] = data_i[129] & sel_one_hot_i[2];
assign data_masked[128] = data_i[128] & sel_one_hot_i[2];
assign data_masked[127] = data_i[127] & sel_one_hot_i[2];
assign data_masked[126] = data_i[126] & sel_one_hot_i[2];
assign data_masked[125] = data_i[125] & sel_one_hot_i[2];
assign data_masked[124] = data_i[124] & sel_one_hot_i[2];
assign data_masked[247] = data_i[247] & sel_one_hot_i[3];
assign data_masked[246] = data_i[246] & sel_one_hot_i[3];
assign data_masked[245] = data_i[245] & sel_one_hot_i[3];
assign data_masked[244] = data_i[244] & sel_one_hot_i[3];
assign data_masked[243] = data_i[243] & sel_one_hot_i[3];
assign data_masked[242] = data_i[242] & sel_one_hot_i[3];
assign data_masked[241] = data_i[241] & sel_one_hot_i[3];
assign data_masked[240] = data_i[240] & sel_one_hot_i[3];
assign data_masked[239] = data_i[239] & sel_one_hot_i[3];
assign data_masked[238] = data_i[238] & sel_one_hot_i[3];
assign data_masked[237] = data_i[237] & sel_one_hot_i[3];
assign data_masked[236] = data_i[236] & sel_one_hot_i[3];
assign data_masked[235] = data_i[235] & sel_one_hot_i[3];
assign data_masked[234] = data_i[234] & sel_one_hot_i[3];
assign data_masked[233] = data_i[233] & sel_one_hot_i[3];
assign data_masked[232] = data_i[232] & sel_one_hot_i[3];
assign data_masked[231] = data_i[231] & sel_one_hot_i[3];
assign data_masked[230] = data_i[230] & sel_one_hot_i[3];
assign data_masked[229] = data_i[229] & sel_one_hot_i[3];
assign data_masked[228] = data_i[228] & sel_one_hot_i[3];
assign data_masked[227] = data_i[227] & sel_one_hot_i[3];
assign data_masked[226] = data_i[226] & sel_one_hot_i[3];
assign data_masked[225] = data_i[225] & sel_one_hot_i[3];
assign data_masked[224] = data_i[224] & sel_one_hot_i[3];
assign data_masked[223] = data_i[223] & sel_one_hot_i[3];
assign data_masked[222] = data_i[222] & sel_one_hot_i[3];
assign data_masked[221] = data_i[221] & sel_one_hot_i[3];
assign data_masked[220] = data_i[220] & sel_one_hot_i[3];
assign data_masked[219] = data_i[219] & sel_one_hot_i[3];
assign data_masked[218] = data_i[218] & sel_one_hot_i[3];
assign data_masked[217] = data_i[217] & sel_one_hot_i[3];
assign data_masked[216] = data_i[216] & sel_one_hot_i[3];
assign data_masked[215] = data_i[215] & sel_one_hot_i[3];
assign data_masked[214] = data_i[214] & sel_one_hot_i[3];
assign data_masked[213] = data_i[213] & sel_one_hot_i[3];
assign data_masked[212] = data_i[212] & sel_one_hot_i[3];
assign data_masked[211] = data_i[211] & sel_one_hot_i[3];
assign data_masked[210] = data_i[210] & sel_one_hot_i[3];
assign data_masked[209] = data_i[209] & sel_one_hot_i[3];
assign data_masked[208] = data_i[208] & sel_one_hot_i[3];
assign data_masked[207] = data_i[207] & sel_one_hot_i[3];
assign data_masked[206] = data_i[206] & sel_one_hot_i[3];
assign data_masked[205] = data_i[205] & sel_one_hot_i[3];
assign data_masked[204] = data_i[204] & sel_one_hot_i[3];
assign data_masked[203] = data_i[203] & sel_one_hot_i[3];
assign data_masked[202] = data_i[202] & sel_one_hot_i[3];
assign data_masked[201] = data_i[201] & sel_one_hot_i[3];
assign data_masked[200] = data_i[200] & sel_one_hot_i[3];
assign data_masked[199] = data_i[199] & sel_one_hot_i[3];
assign data_masked[198] = data_i[198] & sel_one_hot_i[3];
assign data_masked[197] = data_i[197] & sel_one_hot_i[3];
assign data_masked[196] = data_i[196] & sel_one_hot_i[3];
assign data_masked[195] = data_i[195] & sel_one_hot_i[3];
assign data_masked[194] = data_i[194] & sel_one_hot_i[3];
assign data_masked[193] = data_i[193] & sel_one_hot_i[3];
assign data_masked[192] = data_i[192] & sel_one_hot_i[3];
assign data_masked[191] = data_i[191] & sel_one_hot_i[3];
assign data_masked[190] = data_i[190] & sel_one_hot_i[3];
assign data_masked[189] = data_i[189] & sel_one_hot_i[3];
assign data_masked[188] = data_i[188] & sel_one_hot_i[3];
assign data_masked[187] = data_i[187] & sel_one_hot_i[3];
assign data_masked[186] = data_i[186] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[62];
assign N0 = data_masked[186] | data_masked[124];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[63];
assign N2 = data_masked[187] | data_masked[125];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[64];
assign N4 = data_masked[188] | data_masked[126];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[65];
assign N6 = data_masked[189] | data_masked[127];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[66];
assign N8 = data_masked[190] | data_masked[128];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[67];
assign N10 = data_masked[191] | data_masked[129];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[68];
assign N12 = data_masked[192] | data_masked[130];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[69];
assign N14 = data_masked[193] | data_masked[131];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[70];
assign N16 = data_masked[194] | data_masked[132];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[71];
assign N18 = data_masked[195] | data_masked[133];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[72];
assign N20 = data_masked[196] | data_masked[134];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[73];
assign N22 = data_masked[197] | data_masked[135];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[74];
assign N24 = data_masked[198] | data_masked[136];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[75];
assign N26 = data_masked[199] | data_masked[137];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[76];
assign N28 = data_masked[200] | data_masked[138];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[77];
assign N30 = data_masked[201] | data_masked[139];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[78];
assign N32 = data_masked[202] | data_masked[140];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[79];
assign N34 = data_masked[203] | data_masked[141];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[80];
assign N36 = data_masked[204] | data_masked[142];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[81];
assign N38 = data_masked[205] | data_masked[143];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[82];
assign N40 = data_masked[206] | data_masked[144];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[83];
assign N42 = data_masked[207] | data_masked[145];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[84];
assign N44 = data_masked[208] | data_masked[146];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[85];
assign N46 = data_masked[209] | data_masked[147];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[86];
assign N48 = data_masked[210] | data_masked[148];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[87];
assign N50 = data_masked[211] | data_masked[149];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[88];
assign N52 = data_masked[212] | data_masked[150];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[89];
assign N54 = data_masked[213] | data_masked[151];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[90];
assign N56 = data_masked[214] | data_masked[152];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[91];
assign N58 = data_masked[215] | data_masked[153];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[92];
assign N60 = data_masked[216] | data_masked[154];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[93];
assign N62 = data_masked[217] | data_masked[155];
assign data_o[32] = N65 | data_masked[32];
assign N65 = N64 | data_masked[94];
assign N64 = data_masked[218] | data_masked[156];
assign data_o[33] = N67 | data_masked[33];
assign N67 = N66 | data_masked[95];
assign N66 = data_masked[219] | data_masked[157];
assign data_o[34] = N69 | data_masked[34];
assign N69 = N68 | data_masked[96];
assign N68 = data_masked[220] | data_masked[158];
assign data_o[35] = N71 | data_masked[35];
assign N71 = N70 | data_masked[97];
assign N70 = data_masked[221] | data_masked[159];
assign data_o[36] = N73 | data_masked[36];
assign N73 = N72 | data_masked[98];
assign N72 = data_masked[222] | data_masked[160];
assign data_o[37] = N75 | data_masked[37];
assign N75 = N74 | data_masked[99];
assign N74 = data_masked[223] | data_masked[161];
assign data_o[38] = N77 | data_masked[38];
assign N77 = N76 | data_masked[100];
assign N76 = data_masked[224] | data_masked[162];
assign data_o[39] = N79 | data_masked[39];
assign N79 = N78 | data_masked[101];
assign N78 = data_masked[225] | data_masked[163];
assign data_o[40] = N81 | data_masked[40];
assign N81 = N80 | data_masked[102];
assign N80 = data_masked[226] | data_masked[164];
assign data_o[41] = N83 | data_masked[41];
assign N83 = N82 | data_masked[103];
assign N82 = data_masked[227] | data_masked[165];
assign data_o[42] = N85 | data_masked[42];
assign N85 = N84 | data_masked[104];
assign N84 = data_masked[228] | data_masked[166];
assign data_o[43] = N87 | data_masked[43];
assign N87 = N86 | data_masked[105];
assign N86 = data_masked[229] | data_masked[167];
assign data_o[44] = N89 | data_masked[44];
assign N89 = N88 | data_masked[106];
assign N88 = data_masked[230] | data_masked[168];
assign data_o[45] = N91 | data_masked[45];
assign N91 = N90 | data_masked[107];
assign N90 = data_masked[231] | data_masked[169];
assign data_o[46] = N93 | data_masked[46];
assign N93 = N92 | data_masked[108];
assign N92 = data_masked[232] | data_masked[170];
assign data_o[47] = N95 | data_masked[47];
assign N95 = N94 | data_masked[109];
assign N94 = data_masked[233] | data_masked[171];
assign data_o[48] = N97 | data_masked[48];
assign N97 = N96 | data_masked[110];
assign N96 = data_masked[234] | data_masked[172];
assign data_o[49] = N99 | data_masked[49];
assign N99 = N98 | data_masked[111];
assign N98 = data_masked[235] | data_masked[173];
assign data_o[50] = N101 | data_masked[50];
assign N101 = N100 | data_masked[112];
assign N100 = data_masked[236] | data_masked[174];
assign data_o[51] = N103 | data_masked[51];
assign N103 = N102 | data_masked[113];
assign N102 = data_masked[237] | data_masked[175];
assign data_o[52] = N105 | data_masked[52];
assign N105 = N104 | data_masked[114];
assign N104 = data_masked[238] | data_masked[176];
assign data_o[53] = N107 | data_masked[53];
assign N107 = N106 | data_masked[115];
assign N106 = data_masked[239] | data_masked[177];
assign data_o[54] = N109 | data_masked[54];
assign N109 = N108 | data_masked[116];
assign N108 = data_masked[240] | data_masked[178];
assign data_o[55] = N111 | data_masked[55];
assign N111 = N110 | data_masked[117];
assign N110 = data_masked[241] | data_masked[179];
assign data_o[56] = N113 | data_masked[56];
assign N113 = N112 | data_masked[118];
assign N112 = data_masked[242] | data_masked[180];
assign data_o[57] = N115 | data_masked[57];
assign N115 = N114 | data_masked[119];
assign N114 = data_masked[243] | data_masked[181];
assign data_o[58] = N117 | data_masked[58];
assign N117 = N116 | data_masked[120];
assign N116 = data_masked[244] | data_masked[182];
assign data_o[59] = N119 | data_masked[59];
assign N119 = N118 | data_masked[121];
assign N118 = data_masked[245] | data_masked[183];
assign data_o[60] = N121 | data_masked[60];
assign N121 = N120 | data_masked[122];
assign N120 = data_masked[246] | data_masked[184];
assign data_o[61] = N123 | data_masked[61];
assign N123 = N122 | data_masked[123];
assign N122 = data_masked[247] | data_masked[185];
endmodule |
module bsg_mem_1r1w_synth_width_p41_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [40:0] w_data_i;
input [0:0] r_addr_i;
output [40:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [40:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
wire [81:0] mem;
reg mem_81_sv2v_reg,mem_80_sv2v_reg,mem_79_sv2v_reg,mem_78_sv2v_reg,mem_77_sv2v_reg,
mem_76_sv2v_reg,mem_75_sv2v_reg,mem_74_sv2v_reg,mem_73_sv2v_reg,mem_72_sv2v_reg,
mem_71_sv2v_reg,mem_70_sv2v_reg,mem_69_sv2v_reg,mem_68_sv2v_reg,mem_67_sv2v_reg,
mem_66_sv2v_reg,mem_65_sv2v_reg,mem_64_sv2v_reg,mem_63_sv2v_reg,mem_62_sv2v_reg,
mem_61_sv2v_reg,mem_60_sv2v_reg,mem_59_sv2v_reg,mem_58_sv2v_reg,mem_57_sv2v_reg,
mem_56_sv2v_reg,mem_55_sv2v_reg,mem_54_sv2v_reg,mem_53_sv2v_reg,mem_52_sv2v_reg,
mem_51_sv2v_reg,mem_50_sv2v_reg,mem_49_sv2v_reg,mem_48_sv2v_reg,mem_47_sv2v_reg,
mem_46_sv2v_reg,mem_45_sv2v_reg,mem_44_sv2v_reg,mem_43_sv2v_reg,mem_42_sv2v_reg,
mem_41_sv2v_reg,mem_40_sv2v_reg,mem_39_sv2v_reg,mem_38_sv2v_reg,mem_37_sv2v_reg,
mem_36_sv2v_reg,mem_35_sv2v_reg,mem_34_sv2v_reg,mem_33_sv2v_reg,mem_32_sv2v_reg,
mem_31_sv2v_reg,mem_30_sv2v_reg,mem_29_sv2v_reg,mem_28_sv2v_reg,mem_27_sv2v_reg,
mem_26_sv2v_reg,mem_25_sv2v_reg,mem_24_sv2v_reg,mem_23_sv2v_reg,mem_22_sv2v_reg,
mem_21_sv2v_reg,mem_20_sv2v_reg,mem_19_sv2v_reg,mem_18_sv2v_reg,mem_17_sv2v_reg,
mem_16_sv2v_reg,mem_15_sv2v_reg,mem_14_sv2v_reg,mem_13_sv2v_reg,mem_12_sv2v_reg,
mem_11_sv2v_reg,mem_10_sv2v_reg,mem_9_sv2v_reg,mem_8_sv2v_reg,mem_7_sv2v_reg,
mem_6_sv2v_reg,mem_5_sv2v_reg,mem_4_sv2v_reg,mem_3_sv2v_reg,mem_2_sv2v_reg,
mem_1_sv2v_reg,mem_0_sv2v_reg;
assign mem[81] = mem_81_sv2v_reg;
assign mem[80] = mem_80_sv2v_reg;
assign mem[79] = mem_79_sv2v_reg;
assign mem[78] = mem_78_sv2v_reg;
assign mem[77] = mem_77_sv2v_reg;
assign mem[76] = mem_76_sv2v_reg;
assign mem[75] = mem_75_sv2v_reg;
assign mem[74] = mem_74_sv2v_reg;
assign mem[73] = mem_73_sv2v_reg;
assign mem[72] = mem_72_sv2v_reg;
assign mem[71] = mem_71_sv2v_reg;
assign mem[70] = mem_70_sv2v_reg;
assign mem[69] = mem_69_sv2v_reg;
assign mem[68] = mem_68_sv2v_reg;
assign mem[67] = mem_67_sv2v_reg;
assign mem[66] = mem_66_sv2v_reg;
assign mem[65] = mem_65_sv2v_reg;
assign mem[64] = mem_64_sv2v_reg;
assign mem[63] = mem_63_sv2v_reg;
assign mem[62] = mem_62_sv2v_reg;
assign mem[61] = mem_61_sv2v_reg;
assign mem[60] = mem_60_sv2v_reg;
assign mem[59] = mem_59_sv2v_reg;
assign mem[58] = mem_58_sv2v_reg;
assign mem[57] = mem_57_sv2v_reg;
assign mem[56] = mem_56_sv2v_reg;
assign mem[55] = mem_55_sv2v_reg;
assign mem[54] = mem_54_sv2v_reg;
assign mem[53] = mem_53_sv2v_reg;
assign mem[52] = mem_52_sv2v_reg;
assign mem[51] = mem_51_sv2v_reg;
assign mem[50] = mem_50_sv2v_reg;
assign mem[49] = mem_49_sv2v_reg;
assign mem[48] = mem_48_sv2v_reg;
assign mem[47] = mem_47_sv2v_reg;
assign mem[46] = mem_46_sv2v_reg;
assign mem[45] = mem_45_sv2v_reg;
assign mem[44] = mem_44_sv2v_reg;
assign mem[43] = mem_43_sv2v_reg;
assign mem[42] = mem_42_sv2v_reg;
assign mem[41] = mem_41_sv2v_reg;
assign mem[40] = mem_40_sv2v_reg;
assign mem[39] = mem_39_sv2v_reg;
assign mem[38] = mem_38_sv2v_reg;
assign mem[37] = mem_37_sv2v_reg;
assign mem[36] = mem_36_sv2v_reg;
assign mem[35] = mem_35_sv2v_reg;
assign mem[34] = mem_34_sv2v_reg;
assign mem[33] = mem_33_sv2v_reg;
assign mem[32] = mem_32_sv2v_reg;
assign mem[31] = mem_31_sv2v_reg;
assign mem[30] = mem_30_sv2v_reg;
assign mem[29] = mem_29_sv2v_reg;
assign mem[28] = mem_28_sv2v_reg;
assign mem[27] = mem_27_sv2v_reg;
assign mem[26] = mem_26_sv2v_reg;
assign mem[25] = mem_25_sv2v_reg;
assign mem[24] = mem_24_sv2v_reg;
assign mem[23] = mem_23_sv2v_reg;
assign mem[22] = mem_22_sv2v_reg;
assign mem[21] = mem_21_sv2v_reg;
assign mem[20] = mem_20_sv2v_reg;
assign mem[19] = mem_19_sv2v_reg;
assign mem[18] = mem_18_sv2v_reg;
assign mem[17] = mem_17_sv2v_reg;
assign mem[16] = mem_16_sv2v_reg;
assign mem[15] = mem_15_sv2v_reg;
assign mem[14] = mem_14_sv2v_reg;
assign mem[13] = mem_13_sv2v_reg;
assign mem[12] = mem_12_sv2v_reg;
assign mem[11] = mem_11_sv2v_reg;
assign mem[10] = mem_10_sv2v_reg;
assign mem[9] = mem_9_sv2v_reg;
assign mem[8] = mem_8_sv2v_reg;
assign mem[7] = mem_7_sv2v_reg;
assign mem[6] = mem_6_sv2v_reg;
assign mem[5] = mem_5_sv2v_reg;
assign mem[4] = mem_4_sv2v_reg;
assign mem[3] = mem_3_sv2v_reg;
assign mem[2] = mem_2_sv2v_reg;
assign mem[1] = mem_1_sv2v_reg;
assign mem[0] = mem_0_sv2v_reg;
assign r_data_o[40] = (N3)? mem[40] :
(N0)? mem[81] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[39] = (N3)? mem[39] :
(N0)? mem[80] : 1'b0;
assign r_data_o[38] = (N3)? mem[38] :
(N0)? mem[79] : 1'b0;
assign r_data_o[37] = (N3)? mem[37] :
(N0)? mem[78] : 1'b0;
assign r_data_o[36] = (N3)? mem[36] :
(N0)? mem[77] : 1'b0;
assign r_data_o[35] = (N3)? mem[35] :
(N0)? mem[76] : 1'b0;
assign r_data_o[34] = (N3)? mem[34] :
(N0)? mem[75] : 1'b0;
assign r_data_o[33] = (N3)? mem[33] :
(N0)? mem[74] : 1'b0;
assign r_data_o[32] = (N3)? mem[32] :
(N0)? mem[73] : 1'b0;
assign r_data_o[31] = (N3)? mem[31] :
(N0)? mem[72] : 1'b0;
assign r_data_o[30] = (N3)? mem[30] :
(N0)? mem[71] : 1'b0;
assign r_data_o[29] = (N3)? mem[29] :
(N0)? mem[70] : 1'b0;
assign r_data_o[28] = (N3)? mem[28] :
(N0)? mem[69] : 1'b0;
assign r_data_o[27] = (N3)? mem[27] :
(N0)? mem[68] : 1'b0;
assign r_data_o[26] = (N3)? mem[26] :
(N0)? mem[67] : 1'b0;
assign r_data_o[25] = (N3)? mem[25] :
(N0)? mem[66] : 1'b0;
assign r_data_o[24] = (N3)? mem[24] :
(N0)? mem[65] : 1'b0;
assign r_data_o[23] = (N3)? mem[23] :
(N0)? mem[64] : 1'b0;
assign r_data_o[22] = (N3)? mem[22] :
(N0)? mem[63] : 1'b0;
assign r_data_o[21] = (N3)? mem[21] :
(N0)? mem[62] : 1'b0;
assign r_data_o[20] = (N3)? mem[20] :
(N0)? mem[61] : 1'b0;
assign r_data_o[19] = (N3)? mem[19] :
(N0)? mem[60] : 1'b0;
assign r_data_o[18] = (N3)? mem[18] :
(N0)? mem[59] : 1'b0;
assign r_data_o[17] = (N3)? mem[17] :
(N0)? mem[58] : 1'b0;
assign r_data_o[16] = (N3)? mem[16] :
(N0)? mem[57] : 1'b0;
assign r_data_o[15] = (N3)? mem[15] :
(N0)? mem[56] : 1'b0;
assign r_data_o[14] = (N3)? mem[14] :
(N0)? mem[55] : 1'b0;
assign r_data_o[13] = (N3)? mem[13] :
(N0)? mem[54] : 1'b0;
assign r_data_o[12] = (N3)? mem[12] :
(N0)? mem[53] : 1'b0;
assign r_data_o[11] = (N3)? mem[11] :
(N0)? mem[52] : 1'b0;
assign r_data_o[10] = (N3)? mem[10] :
(N0)? mem[51] : 1'b0;
assign r_data_o[9] = (N3)? mem[9] :
(N0)? mem[50] : 1'b0;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[49] : 1'b0;
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[48] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[47] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[46] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[45] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[44] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[43] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[42] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[41] : 1'b0;
always @(posedge w_clk_i) begin
if(N8) begin
mem_81_sv2v_reg <= w_data_i[40];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_80_sv2v_reg <= w_data_i[39];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_79_sv2v_reg <= w_data_i[38];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_78_sv2v_reg <= w_data_i[37];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_77_sv2v_reg <= w_data_i[36];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_76_sv2v_reg <= w_data_i[35];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_75_sv2v_reg <= w_data_i[34];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_74_sv2v_reg <= w_data_i[33];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_73_sv2v_reg <= w_data_i[32];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_72_sv2v_reg <= w_data_i[31];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_71_sv2v_reg <= w_data_i[30];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_70_sv2v_reg <= w_data_i[29];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_69_sv2v_reg <= w_data_i[28];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_68_sv2v_reg <= w_data_i[27];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_67_sv2v_reg <= w_data_i[26];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_66_sv2v_reg <= w_data_i[25];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_65_sv2v_reg <= w_data_i[24];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_64_sv2v_reg <= w_data_i[23];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_63_sv2v_reg <= w_data_i[22];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_62_sv2v_reg <= w_data_i[21];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_61_sv2v_reg <= w_data_i[20];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_60_sv2v_reg <= w_data_i[19];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_59_sv2v_reg <= w_data_i[18];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_58_sv2v_reg <= w_data_i[17];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_57_sv2v_reg <= w_data_i[16];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_56_sv2v_reg <= w_data_i[15];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_55_sv2v_reg <= w_data_i[14];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_54_sv2v_reg <= w_data_i[13];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_53_sv2v_reg <= w_data_i[12];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_52_sv2v_reg <= w_data_i[11];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_51_sv2v_reg <= w_data_i[10];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_50_sv2v_reg <= w_data_i[9];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_49_sv2v_reg <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_48_sv2v_reg <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_47_sv2v_reg <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_46_sv2v_reg <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_45_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_44_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_43_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_42_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem_41_sv2v_reg <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_40_sv2v_reg <= w_data_i[40];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_39_sv2v_reg <= w_data_i[39];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_38_sv2v_reg <= w_data_i[38];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_37_sv2v_reg <= w_data_i[37];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_36_sv2v_reg <= w_data_i[36];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_35_sv2v_reg <= w_data_i[35];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_34_sv2v_reg <= w_data_i[34];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_33_sv2v_reg <= w_data_i[33];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_32_sv2v_reg <= w_data_i[32];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_31_sv2v_reg <= w_data_i[31];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_30_sv2v_reg <= w_data_i[30];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_29_sv2v_reg <= w_data_i[29];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_28_sv2v_reg <= w_data_i[28];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_27_sv2v_reg <= w_data_i[27];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_26_sv2v_reg <= w_data_i[26];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_25_sv2v_reg <= w_data_i[25];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_24_sv2v_reg <= w_data_i[24];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_23_sv2v_reg <= w_data_i[23];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_22_sv2v_reg <= w_data_i[22];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_21_sv2v_reg <= w_data_i[21];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_20_sv2v_reg <= w_data_i[20];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_19_sv2v_reg <= w_data_i[19];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_18_sv2v_reg <= w_data_i[18];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_17_sv2v_reg <= w_data_i[17];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_16_sv2v_reg <= w_data_i[16];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_15_sv2v_reg <= w_data_i[15];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_14_sv2v_reg <= w_data_i[14];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_13_sv2v_reg <= w_data_i[13];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_12_sv2v_reg <= w_data_i[12];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_11_sv2v_reg <= w_data_i[11];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_10_sv2v_reg <= w_data_i[10];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_9_sv2v_reg <= w_data_i[9];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_8_sv2v_reg <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_7_sv2v_reg <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_6_sv2v_reg <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_5_sv2v_reg <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_4_sv2v_reg <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_3_sv2v_reg <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_2_sv2v_reg <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_1_sv2v_reg <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem_0_sv2v_reg <= w_data_i[0];
end
end
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
endmodule |
module bsg_dff_width_p39
(
clk_i,
data_i,
data_o
);
input [38:0] data_i;
output [38:0] data_o;
input clk_i;
wire [38:0] data_o;
reg data_o_38_sv2v_reg,data_o_37_sv2v_reg,data_o_36_sv2v_reg,data_o_35_sv2v_reg,
data_o_34_sv2v_reg,data_o_33_sv2v_reg,data_o_32_sv2v_reg,data_o_31_sv2v_reg,
data_o_30_sv2v_reg,data_o_29_sv2v_reg,data_o_28_sv2v_reg,data_o_27_sv2v_reg,
data_o_26_sv2v_reg,data_o_25_sv2v_reg,data_o_24_sv2v_reg,data_o_23_sv2v_reg,
data_o_22_sv2v_reg,data_o_21_sv2v_reg,data_o_20_sv2v_reg,data_o_19_sv2v_reg,data_o_18_sv2v_reg,
data_o_17_sv2v_reg,data_o_16_sv2v_reg,data_o_15_sv2v_reg,data_o_14_sv2v_reg,
data_o_13_sv2v_reg,data_o_12_sv2v_reg,data_o_11_sv2v_reg,data_o_10_sv2v_reg,
data_o_9_sv2v_reg,data_o_8_sv2v_reg,data_o_7_sv2v_reg,data_o_6_sv2v_reg,
data_o_5_sv2v_reg,data_o_4_sv2v_reg,data_o_3_sv2v_reg,data_o_2_sv2v_reg,data_o_1_sv2v_reg,
data_o_0_sv2v_reg;
assign data_o[38] = data_o_38_sv2v_reg;
assign data_o[37] = data_o_37_sv2v_reg;
assign data_o[36] = data_o_36_sv2v_reg;
assign data_o[35] = data_o_35_sv2v_reg;
assign data_o[34] = data_o_34_sv2v_reg;
assign data_o[33] = data_o_33_sv2v_reg;
assign data_o[32] = data_o_32_sv2v_reg;
assign data_o[31] = data_o_31_sv2v_reg;
assign data_o[30] = data_o_30_sv2v_reg;
assign data_o[29] = data_o_29_sv2v_reg;
assign data_o[28] = data_o_28_sv2v_reg;
assign data_o[27] = data_o_27_sv2v_reg;
assign data_o[26] = data_o_26_sv2v_reg;
assign data_o[25] = data_o_25_sv2v_reg;
assign data_o[24] = data_o_24_sv2v_reg;
assign data_o[23] = data_o_23_sv2v_reg;
assign data_o[22] = data_o_22_sv2v_reg;
assign data_o[21] = data_o_21_sv2v_reg;
assign data_o[20] = data_o_20_sv2v_reg;
assign data_o[19] = data_o_19_sv2v_reg;
assign data_o[18] = data_o_18_sv2v_reg;
assign data_o[17] = data_o_17_sv2v_reg;
assign data_o[16] = data_o_16_sv2v_reg;
assign data_o[15] = data_o_15_sv2v_reg;
assign data_o[14] = data_o_14_sv2v_reg;
assign data_o[13] = data_o_13_sv2v_reg;
assign data_o[12] = data_o_12_sv2v_reg;
assign data_o[11] = data_o_11_sv2v_reg;
assign data_o[10] = data_o_10_sv2v_reg;
assign data_o[9] = data_o_9_sv2v_reg;
assign data_o[8] = data_o_8_sv2v_reg;
assign data_o[7] = data_o_7_sv2v_reg;
assign data_o[6] = data_o_6_sv2v_reg;
assign data_o[5] = data_o_5_sv2v_reg;
assign data_o[4] = data_o_4_sv2v_reg;
assign data_o[3] = data_o_3_sv2v_reg;
assign data_o[2] = data_o_2_sv2v_reg;
assign data_o[1] = data_o_1_sv2v_reg;
assign data_o[0] = data_o_0_sv2v_reg;
always @(posedge clk_i) begin
if(1'b1) begin
data_o_38_sv2v_reg <= data_i[38];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_37_sv2v_reg <= data_i[37];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_36_sv2v_reg <= data_i[36];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_35_sv2v_reg <= data_i[35];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_34_sv2v_reg <= data_i[34];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_33_sv2v_reg <= data_i[33];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_32_sv2v_reg <= data_i[32];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_31_sv2v_reg <= data_i[31];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_30_sv2v_reg <= data_i[30];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_29_sv2v_reg <= data_i[29];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_28_sv2v_reg <= data_i[28];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_27_sv2v_reg <= data_i[27];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_26_sv2v_reg <= data_i[26];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_25_sv2v_reg <= data_i[25];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_24_sv2v_reg <= data_i[24];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_23_sv2v_reg <= data_i[23];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_22_sv2v_reg <= data_i[22];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_21_sv2v_reg <= data_i[21];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_20_sv2v_reg <= data_i[20];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_19_sv2v_reg <= data_i[19];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_18_sv2v_reg <= data_i[18];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_17_sv2v_reg <= data_i[17];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_16_sv2v_reg <= data_i[16];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_15_sv2v_reg <= data_i[15];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_14_sv2v_reg <= data_i[14];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_13_sv2v_reg <= data_i[13];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_12_sv2v_reg <= data_i[12];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_11_sv2v_reg <= data_i[11];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_10_sv2v_reg <= data_i[10];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_9_sv2v_reg <= data_i[9];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_8_sv2v_reg <= data_i[8];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_7_sv2v_reg <= data_i[7];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_6_sv2v_reg <= data_i[6];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_5_sv2v_reg <= data_i[5];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_4_sv2v_reg <= data_i[4];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_3_sv2v_reg <= data_i[3];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_2_sv2v_reg <= data_i[2];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_1_sv2v_reg <= data_i[1];
end
end
always @(posedge clk_i) begin
if(1'b1) begin
data_o_0_sv2v_reg <= data_i[0];
end
end
endmodule |
module bsg_dff_en_width_p5
(
clk_i,
data_i,
en_i,
data_o
);
input [4:0] data_i;
output [4:0] data_o;
input clk_i;
input en_i;
reg [4:0] data_o;
always @(posedge clk_i) begin
if(en_i) begin
{ data_o[4:0] } <= { data_i[4:0] };
end
end
endmodule |
module bsg_dff_en_width_p36
(
clk_i,
data_i,
en_i,
data_o
);
input [35:0] data_i;
output [35:0] data_o;
input clk_i;
input en_i;
reg [35:0] data_o;
always @(posedge clk_i) begin
if(en_i) begin
{ data_o[35:0] } <= { data_i[35:0] };
end
end
endmodule |
module bsg_mux_segmented_segments_p5_segment_width_p128
(
data0_i,
data1_i,
sel_i,
data_o
);
input [639:0] data0_i;
input [639:0] data1_i;
input [4:0] sel_i;
output [639:0] data_o;
wire [639:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9;
assign data_o[127:0] = (N0)? data1_i[127:0] :
(N5)? data0_i[127:0] : 1'b0;
assign N0 = sel_i[0];
assign data_o[255:128] = (N1)? data1_i[255:128] :
(N6)? data0_i[255:128] : 1'b0;
assign N1 = sel_i[1];
assign data_o[383:256] = (N2)? data1_i[383:256] :
(N7)? data0_i[383:256] : 1'b0;
assign N2 = sel_i[2];
assign data_o[511:384] = (N3)? data1_i[511:384] :
(N8)? data0_i[511:384] : 1'b0;
assign N3 = sel_i[3];
assign data_o[639:512] = (N4)? data1_i[639:512] :
(N9)? data0_i[639:512] : 1'b0;
assign N4 = sel_i[4];
assign N5 = ~sel_i[0];
assign N6 = ~sel_i[1];
assign N7 = ~sel_i[2];
assign N8 = ~sel_i[3];
assign N9 = ~sel_i[4];
endmodule |
module bp_be_dcache_wbuf_queue_width_p97
(
clk_i,
data_i,
el0_en_i,
el1_en_i,
mux0_sel_i,
mux1_sel_i,
el0_snoop_o,
el1_snoop_o,
data_o
);
input [96:0] data_i;
output [96:0] el0_snoop_o;
output [96:0] el1_snoop_o;
output [96:0] data_o;
input clk_i;
input el0_en_i;
input el1_en_i;
input mux0_sel_i;
input mux1_sel_i;
wire [96:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102;
reg [96:0] el0_snoop_o,el1_snoop_o;
assign { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 } = (N0)? el0_snoop_o :
(N1)? data_i : 1'b0;
assign N0 = mux0_sel_i;
assign N1 = N4;
assign data_o = (N2)? el1_snoop_o :
(N3)? data_i : 1'b0;
assign N2 = mux1_sel_i;
assign N3 = N102;
assign N4 = ~mux0_sel_i;
assign N102 = ~mux1_sel_i;
always @(posedge clk_i) begin
if(el0_en_i) begin
{ el0_snoop_o[96:0] } <= { data_i[96:0] };
end
if(el1_en_i) begin
{ el1_snoop_o[96:0] } <= { N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5 };
end
end
endmodule |
module bsg_dff_width_p640
(
clk_i,
data_i,
data_o
);
input [639:0] data_i;
output [639:0] data_o;
input clk_i;
reg [639:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[639:0] } <= { data_i[639:0] };
end
end
endmodule |
module bsg_dff_reset_en_width_p8
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [7:0] data_i;
output [7:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
reg [7:0] data_o;
assign N3 = (N0)? 1'b1 :
(N13)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N13)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N12 = ~reset_i;
assign N13 = en_i & N12;
always @(posedge clk_i) begin
if(N3) begin
{ data_o[7:0] } <= { N11, N10, N9, N8, N7, N6, N5, N4 };
end
end
endmodule |
module bsg_dff_width_p1890
(
clk_i,
data_i,
data_o
);
input [1889:0] data_i;
output [1889:0] data_o;
input clk_i;
reg [1889:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[1889:0] } <= { data_i[1889:0] };
end
end
endmodule |
module bsg_dff_width_p35
(
clk_i,
data_i,
data_o
);
input [34:0] data_i;
output [34:0] data_o;
input clk_i;
reg [34:0] data_o;
always @(posedge clk_i) begin
if(1'b1) begin
{ data_o[34:0] } <= { data_i[34:0] };
end
end
endmodule |
module bsg_dff_reset_en_64_80000124
(
clk_i,
reset_i,
en_i,
data_i,
data_o
);
input [63:0] data_i;
output [63:0] data_o;
input clk_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69;
reg [63:0] data_o;
assign N3 = (N0)? 1'b1 :
(N69)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N69)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N68 = ~reset_i;
assign N69 = en_i & N68;
always @(posedge clk_i) begin
if(N3) begin
{ data_o[63:0] } <= { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 };
end
end
endmodule |
module bp_be_instr_decoder
(
instr_i,
fe_nop_v_i,
be_nop_v_i,
me_nop_v_i,
decode_o,
illegal_instr_o
);
input [31:0] instr_i;
output [42:0] decode_o;
input fe_nop_v_i;
input be_nop_v_i;
input me_nop_v_i;
output illegal_instr_o;
wire [42:0] decode_o;
wire illegal_instr_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,
N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,
N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,
N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,
N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,
N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,
N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,
N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,
N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,
N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,
N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,
N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,N241,
N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,N257,
N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,N273,
N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,N289,
N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,
N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,
N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,N335,N336,N337,
N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,N351,N352,N353,
N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,N367,N368,N369,
N370,N371,N372;
assign decode_o[26] = 1'b0;
assign decode_o[27] = 1'b0;
assign decode_o[28] = 1'b0;
assign decode_o[32] = 1'b0;
assign decode_o[34] = 1'b0;
assign decode_o[36] = 1'b0;
assign N54 = instr_i[1] & instr_i[0];
assign N56 = instr_i[6] | N339;
assign N57 = N340 | instr_i[3];
assign N58 = N56 | N57;
assign N59 = N58 | instr_i[2];
assign N60 = N340 | N341;
assign N61 = N56 | N60;
assign N62 = N61 | instr_i[2];
assign N64 = instr_i[6] | instr_i[5];
assign N65 = N64 | N57;
assign N66 = N65 | instr_i[2];
assign N67 = N64 | N60;
assign N68 = N67 | instr_i[2];
assign N70 = N58 | N86;
assign N72 = N65 | N86;
assign N74 = N85 | N339;
assign N75 = instr_i[4] | N341;
assign N76 = N74 | N75;
assign N77 = N76 | N86;
assign N79 = instr_i[4] | instr_i[3];
assign N80 = N74 | N79;
assign N81 = N80 | N86;
assign N83 = N80 | instr_i[2];
assign N87 = N85 & N339;
assign N88 = N340 & N341;
assign N89 = N87 & N88;
assign N90 = N89 & N86;
assign N91 = N56 | N79;
assign N92 = N91 | instr_i[2];
assign N94 = N64 | N75;
assign N95 = N94 | N86;
assign N97 = N74 | N57;
assign N98 = N97 | instr_i[2];
assign N100 = instr_i[6] & instr_i[4];
assign N101 = N100 & instr_i[2];
assign N102 = N100 & instr_i[3];
assign N103 = instr_i[4] & instr_i[3];
assign N104 = N103 & instr_i[2];
assign N105 = N85 & instr_i[5];
assign N106 = N340 & instr_i[2];
assign N107 = N105 & N106;
assign N108 = N85 & N340;
assign N109 = N341 & instr_i[2];
assign N110 = N108 & N109;
assign N111 = N339 & N340;
assign N112 = N111 & N109;
assign N113 = N340 & instr_i[3];
assign N114 = N113 & N86;
assign N115 = instr_i[6] & N339;
assign N123 = N117 & N118;
assign N124 = N119 & N120;
assign N125 = N121 & N122;
assign N126 = instr_i[4] & N86;
assign N127 = N123 & N124;
assign N128 = N125 & N105;
assign N129 = N126 & N54;
assign N130 = N127 & N128;
assign N131 = N130 & N129;
assign N133 = N154 & N285;
assign N134 = N133 & N341;
assign N135 = N133 & instr_i[3];
assign N137 = N166 & N285;
assign N138 = N137 & N341;
assign N139 = N137 & instr_i[3];
assign N141 = N154 & N286;
assign N142 = N141 & N341;
assign N143 = N141 & instr_i[3];
assign N145 = N159 & N286;
assign N146 = N145 & N341;
assign N147 = N145 & instr_i[3];
assign N149 = N172 & N286;
assign N150 = N149 & N341;
assign N151 = N149 & instr_i[3];
assign N154 = N153 & N251;
assign N155 = N154 & N287;
assign N156 = N155 & N341;
assign N157 = N154 & N288;
assign N158 = N157 & N341;
assign N159 = N153 & instr_i[14];
assign N160 = N159 & N285;
assign N161 = N160 & N341;
assign N162 = N159 & N287;
assign N163 = N162 & N341;
assign N164 = N159 & N288;
assign N165 = N164 & N341;
assign N166 = instr_i[30] & N251;
assign N167 = N166 & instr_i[12];
assign N168 = instr_i[14] & N284;
assign N169 = N168 & instr_i[3];
assign N170 = instr_i[13] & instr_i[3];
assign N171 = instr_i[30] & instr_i[13];
assign N172 = instr_i[30] & instr_i[14];
assign N173 = N172 & N284;
assign N185 = N87 & N126;
assign N186 = N185 & N54;
assign N188 = N242 & N216;
assign N189 = N284 & instr_i[3];
assign N190 = N242 & N189;
assign N192 = N205 & N242;
assign N193 = N198 & N192;
assign N194 = N193 & N218;
assign N195 = N193 & N210;
assign N197 = N117 & N153;
assign N198 = N197 & N204;
assign N199 = N198 & N207;
assign N200 = N199 & N218;
assign N201 = N199 & N210;
assign N203 = N117 & instr_i[30];
assign N204 = N118 & N119;
assign N205 = N120 & N121;
assign N206 = N203 & N204;
assign N207 = N205 & N245;
assign N208 = N206 & N207;
assign N209 = N208 & N218;
assign N210 = instr_i[12] & instr_i[3];
assign N211 = N208 & N210;
assign N213 = N252 & N216;
assign N214 = N252 & N218;
assign N215 = N245 & N216;
assign N216 = N284 & N341;
assign N217 = N248 & N216;
assign N218 = instr_i[12] & N341;
assign N219 = N248 & N218;
assign N238 = instr_i[2] | N342;
assign N239 = N238 | N343;
assign N240 = N80 | N239;
assign N242 = N251 & N283;
assign N243 = N242 & N284;
assign N244 = N242 & instr_i[12];
assign N245 = instr_i[14] & N283;
assign N246 = N245 & N284;
assign N247 = N245 & instr_i[12];
assign N248 = instr_i[14] & instr_i[13];
assign N249 = N248 & N284;
assign N250 = N248 & instr_i[12];
assign N252 = N251 & instr_i[13];
assign N263 = N64 | N79;
assign N264 = N263 | N239;
assign N266 = N252 & N284;
assign N267 = N252 & instr_i[12];
assign N276 = N251 & N85;
assign N277 = instr_i[5] & N340;
assign N278 = N341 & N86;
assign N279 = N276 & N277;
assign N280 = N278 & N54;
assign N281 = N279 & N280;
assign N285 = N283 & N284;
assign N286 = N283 & instr_i[12];
assign N287 = instr_i[13] & N284;
assign N288 = instr_i[13] & instr_i[12];
assign N296 = N117 | N153;
assign N297 = N118 | N119;
assign N298 = instr_i[27] | instr_i[26];
assign N299 = instr_i[25] | N294;
assign N300 = instr_i[23] | N295;
assign N301 = instr_i[21] | instr_i[20];
assign N302 = N296 | N297;
assign N303 = N298 | N299;
assign N304 = N300 | N301;
assign N305 = N302 | N303;
assign N306 = N305 | N304;
assign N339 = ~instr_i[5];
assign N340 = ~instr_i[4];
assign N341 = ~instr_i[3];
assign N342 = ~instr_i[1];
assign N343 = ~instr_i[0];
assign N344 = N339 | instr_i[6];
assign N345 = N340 | N344;
assign N346 = N341 | N345;
assign N347 = instr_i[2] | N346;
assign N348 = N342 | N347;
assign N349 = N343 | N348;
assign N350 = ~N349;
assign N351 = instr_i[5] | instr_i[6];
assign N352 = N340 | N351;
assign N353 = N341 | N352;
assign N354 = instr_i[2] | N353;
assign N355 = N342 | N354;
assign N356 = N343 | N355;
assign N357 = ~N356;
assign { N178, N177, N176, N175 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b1, 1'b0, 1'b1 } :
(N4)? { 1'b1, 1'b1, 1'b0, 1'b1 } :
(N5)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N7)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N8)? { 1'b0, 1'b1, 1'b1, 1'b0 } :
(N9)? { 1'b0, 1'b1, 1'b1, 1'b1 } :
(N10)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N0 = N136;
assign N1 = N140;
assign N2 = N144;
assign N3 = N148;
assign N4 = N152;
assign N5 = N156;
assign N6 = N158;
assign N7 = N161;
assign N8 = N163;
assign N9 = N165;
assign N10 = N174;
assign N179 = (N0)? 1'b0 :
(N1)? 1'b0 :
(N2)? 1'b0 :
(N3)? 1'b0 :
(N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b0 :
(N7)? 1'b0 :
(N8)? 1'b0 :
(N9)? 1'b0 :
(N10)? 1'b1 : 1'b0;
assign { N183, N182, N181, N180 } = (N11)? { N178, N177, N176, N175 } :
(N132)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N11 = N131;
assign N184 = (N11)? N179 :
(N132)? 1'b1 : 1'b0;
assign { N231, N230, N229 } = (N12)? { 1'b0, 1'b0, 1'b0 } :
(N13)? { 1'b0, 1'b0, 1'b1 } :
(N14)? { 1'b1, 1'b0, 1'b1 } :
(N15)? { 1'b1, 1'b0, 1'b1 } :
(N16)? { 1'b0, 1'b1, 1'b0 } :
(N17)? { 1'b0, 1'b1, 1'b1 } :
(N18)? { 1'b1, 1'b0, 1'b0 } :
(N19)? { 1'b1, 1'b1, 1'b0 } :
(N20)? { 1'b1, 1'b1, 1'b1 } :
(N228)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N12 = N191;
assign N13 = N196;
assign N14 = N202;
assign N15 = N212;
assign N16 = N213;
assign N17 = N214;
assign N18 = N215;
assign N19 = N217;
assign N20 = N219;
assign N232 = (N12)? 1'b0 :
(N13)? 1'b0 :
(N14)? 1'b0 :
(N15)? 1'b0 :
(N16)? 1'b0 :
(N17)? 1'b0 :
(N18)? 1'b0 :
(N19)? 1'b0 :
(N20)? 1'b0 :
(N228)? 1'b1 : 1'b0;
assign { N236, N235, N234, N233 } = (N21)? { N212, N231, N230, N229 } :
(N187)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N21 = N186;
assign N237 = (N21)? N232 :
(N187)? 1'b1 : 1'b0;
assign { N256, N255, N254, N253 } = (N22)? { 1'b1, 1'b1, 1'b0, 1'b0 } :
(N23)? { 1'b1, 1'b1, 1'b1, 1'b0 } :
(N24)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1, 1'b0 } :
(N26)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b1, 1'b0, 1'b1, 1'b1 } :
(N28)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N22 = N243;
assign N23 = N244;
assign N24 = N246;
assign N25 = N247;
assign N26 = N249;
assign N27 = N250;
assign N28 = N252;
assign N257 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N27)? 1'b0 :
(N28)? 1'b1 : 1'b0;
assign { N261, N260, N259, N258 } = (N29)? { N256, N255, N254, N253 } :
(N30)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N29 = N241;
assign N30 = N240;
assign N262 = (N29)? N257 :
(N30)? 1'b1 : 1'b0;
assign { N270, N269, N268 } = (N22)? { 1'b0, 1'b0, 1'b0 } :
(N23)? { 1'b0, 1'b0, 1'b1 } :
(N31)? { 1'b0, 1'b1, 1'b0 } :
(N24)? { 1'b1, 1'b0, 1'b0 } :
(N25)? { 1'b1, 1'b0, 1'b1 } :
(N26)? { 1'b1, 1'b1, 1'b0 } :
(N32)? { 1'b0, 1'b1, 1'b1 } :
(N27)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N31 = N266;
assign N32 = N267;
assign N271 = (N22)? 1'b0 :
(N23)? 1'b0 :
(N31)? 1'b0 :
(N24)? 1'b0 :
(N25)? 1'b0 :
(N26)? 1'b0 :
(N32)? 1'b0 :
(N27)? 1'b1 : 1'b0;
assign { N274, N273, N272 } = (N33)? { N270, N269, N268 } :
(N34)? { 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N33 = N265;
assign N34 = N264;
assign N275 = (N33)? N271 :
(N34)? 1'b1 : 1'b0;
assign { N290, N289 } = (N35)? { 1'b0, 1'b0 } :
(N36)? { 1'b0, 1'b1 } :
(N37)? { 1'b1, 1'b0 } :
(N38)? { 1'b1, 1'b1 } : 1'b0;
assign N35 = N285;
assign N36 = N286;
assign N37 = N287;
assign N38 = N288;
assign { N292, N291 } = (N39)? { N290, N289 } :
(N282)? { 1'b0, 1'b0 } : 1'b0;
assign N39 = N281;
assign N293 = ~N281;
assign { N319, N318, N317, N314, N313, N312, N311, N310, N309, N308 } = (N40)? { 1'b1, 1'b0, 1'b1, N350, N183, N182, N181, N180, 1'b0, 1'b0 } :
(N41)? { 1'b1, 1'b0, 1'b1, N357, N236, N235, N234, N233, 1'b1, 1'b0 } :
(N42)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N43)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N44)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N45)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N46)? { 1'b1, 1'b0, 1'b0, 1'b0, N261, N260, N259, N258, 1'b0, 1'b0 } :
(N47)? { 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, N274, N273, N272, 1'b0, 1'b0 } :
(N48)? { 1'b0, 1'b1, 1'b0, 1'b0, N281, 1'b0, N292, N291, 1'b0, 1'b0 } :
(N49)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N50)? { 1'b1, 1'b0, N307, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N51)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N40 = N63;
assign N41 = N69;
assign N42 = N71;
assign N43 = N73;
assign N44 = N78;
assign N45 = N82;
assign N46 = N84;
assign N47 = N90;
assign N48 = N93;
assign N49 = N96;
assign N50 = N99;
assign N51 = N116;
assign N316 = (N50)? N307 :
(N315)? 1'b0 : 1'b0;
assign N320 = (N40)? N184 :
(N41)? N237 :
(N42)? 1'b0 :
(N43)? 1'b0 :
(N44)? 1'b0 :
(N45)? 1'b0 :
(N46)? N262 :
(N47)? N275 :
(N48)? N293 :
(N49)? 1'b0 :
(N50)? N306 :
(N51)? 1'b1 : 1'b0;
assign { N336, N335, N334, N333, N332, N331, N330, N329, N328, N327, N326, N325, N324, N323, N322, N321 } = (N52)? { N319, N318, N317, N316, N93, N90, N84, N314, N313, N312, N311, N310, N73, N309, N82, N308 } :
(N55)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N52 = N54;
assign illegal_instr_o = (N52)? N320 :
(N55)? 1'b1 : 1'b0;
assign decode_o[42] = ~decode_o[38];
assign { decode_o[41:39], decode_o[37:37], decode_o[35:35], decode_o[33:33], decode_o[31:29], decode_o[25:0] } = (N53)? { fe_nop_v_i, be_nop_v_i, me_nop_v_i, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N338)? { 1'b0, 1'b0, 1'b0, N336, N335, N334, N333, N332, N331, N321, N330, N329, N328, N327, N326, N325, instr_i[19:15], instr_i[24:20], instr_i[11:7], N324, N323, N322, N321 } : 1'b0;
assign N53 = decode_o[38];
assign N55 = ~N54;
assign N63 = N358 | N359;
assign N358 = ~N59;
assign N359 = ~N62;
assign N69 = N360 | N361;
assign N360 = ~N66;
assign N361 = ~N68;
assign N71 = ~N70;
assign N73 = ~N72;
assign N78 = ~N77;
assign N82 = ~N81;
assign N84 = ~N83;
assign N85 = ~instr_i[6];
assign N86 = ~instr_i[2];
assign N93 = ~N92;
assign N96 = ~N95;
assign N99 = ~N98;
assign N116 = N101 | N367;
assign N367 = N102 | N366;
assign N366 = N104 | N365;
assign N365 = N107 | N364;
assign N364 = N110 | N363;
assign N363 = N112 | N362;
assign N362 = N114 | N115;
assign N117 = ~instr_i[31];
assign N118 = ~instr_i[29];
assign N119 = ~instr_i[28];
assign N120 = ~instr_i[27];
assign N121 = ~instr_i[26];
assign N122 = ~instr_i[25];
assign N132 = ~N131;
assign N136 = N134 | N135;
assign N140 = N138 | N139;
assign N144 = N142 | N143;
assign N148 = N146 | N147;
assign N152 = N150 | N151;
assign N153 = ~instr_i[30];
assign N174 = N167 | N370;
assign N370 = N169 | N369;
assign N369 = N170 | N368;
assign N368 = N171 | N173;
assign N187 = ~N186;
assign N191 = N188 | N190;
assign N196 = N194 | N195;
assign N202 = N200 | N201;
assign N212 = N209 | N211;
assign N220 = N196 | N191;
assign N221 = N202 | N220;
assign N222 = N212 | N221;
assign N223 = N213 | N222;
assign N224 = N214 | N223;
assign N225 = N215 | N224;
assign N226 = N217 | N225;
assign N227 = N219 | N226;
assign N228 = ~N227;
assign N241 = ~N240;
assign N251 = ~instr_i[14];
assign N265 = ~N264;
assign N282 = ~N281;
assign N283 = ~instr_i[13];
assign N284 = ~instr_i[12];
assign N294 = ~instr_i[24];
assign N295 = ~instr_i[22];
assign N307 = ~N306;
assign N315 = N98;
assign N337 = N372 | illegal_instr_o;
assign N372 = N371 | me_nop_v_i;
assign N371 = fe_nop_v_i | be_nop_v_i;
assign decode_o[38] = N337;
assign N338 = ~decode_o[38];
endmodule |
module Element(
input clock,
input [63:0] io_ins_down,
input [63:0] io_ins_right,
input [63:0] io_ins_up,
input [63:0] io_ins_left,
output [63:0] io_outs_down,
output [63:0] io_outs_right,
output [63:0] io_outs_up,
output [63:0] io_outs_left,
input io_lsbIns_1,
input io_lsbIns_2,
input io_lsbIns_3,
input io_lsbIns_4,
input io_lsbIns_5,
input io_lsbIns_6,
input io_lsbIns_7,
output io_lsbOuts_0,
output io_lsbOuts_1,
output io_lsbOuts_2,
output io_lsbOuts_3,
output io_lsbOuts_4,
output io_lsbOuts_5,
output io_lsbOuts_6,
output io_lsbOuts_7
);
reg [63:0] REG;
reg [63:0] REG_1;
reg [63:0] REG_2;
reg [63:0] REG_3;
assign io_outs_down = REG_3;
assign io_outs_right = REG_2;
assign io_outs_up = REG_1;
assign io_outs_left = REG;
assign io_lsbOuts_0 = io_lsbIns_1;
assign io_lsbOuts_1 = io_lsbIns_2;
assign io_lsbOuts_2 = io_lsbIns_3;
assign io_lsbOuts_3 = io_lsbIns_4;
assign io_lsbOuts_4 = io_lsbIns_5;
assign io_lsbOuts_5 = io_lsbIns_6;
assign io_lsbOuts_6 = io_lsbIns_7;
assign io_lsbOuts_7 = io_outs_left[0];
always @(posedge clock) begin
REG <= io_ins_down;
REG_1 <= io_ins_right;
REG_2 <= io_ins_up;
REG_3 <= io_ins_left;
end
endmodule |
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
input Clk;
input Reset;
input [3:0] Data;
input Enable;
input Initialize;
output [31:0] Crc;
output CrcError;
reg [31:0] Crc;
wire [31:0] CrcNext;
assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
assign CrcNext[20] = Crc[16];
assign CrcNext[21] = Crc[17];
assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
assign CrcNext[30] = Crc[26];
assign CrcNext[31] = Crc[27];
always @ (posedge Clk or posedge Reset)
begin
if (Reset)
Crc <= 32'hffffffff;
else
if(Initialize)
Crc <= 32'hffffffff;
else
Crc <= CrcNext;
end
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
endmodule |
module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
);
input MTxClk;
input Reset;
input ExcessiveDefer;
input CarrierSense;
input [6:0] NibCnt;
input [6:0] IPGT;
input [6:0] IPGR1;
input [6:0] IPGR2;
input FullD;
input TxStartFrm;
input TxEndFrm;
input TxUnderRun;
input Collision;
input UnderRun;
input StartTxDone;
input TooBig;
input NibCntEq7;
input NibCntEq15;
input MaxFrame;
input Pad;
input CrcEn;
input NibbleMinFl;
input RandomEq0;
input ColWindow;
input RetryMax;
input NoBckof;
input RandomEqByteCnt;
output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
reg StateIdle;
reg StateIPG;
reg StatePreamble;
reg [1:0] StateData;
reg StatePAD;
reg StateFCS;
reg StateJam;
reg StateJam_q;
reg StateBackOff;
reg StateDefer;
reg Rule1;
// Defining the next state
assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
| ~Collision & StatePAD & NibbleMinFl & CrcEn;
assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
| StateIdle & CarrierSense
| StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
| StateBackOff & (TxUnderRun | RandomEqByteCnt)
| StartTxDone | TooBig;
assign DeferIndication = StateIdle & CarrierSense;
// Tx State Machine
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
StateIPG <= 1'b0;
StateIdle <= 1'b0;
StatePreamble <= 1'b0;
StateData[1:0] <= 2'b0;
StatePAD <= 1'b0;
StateFCS <= 1'b0;
StateJam <= 1'b0;
StateJam_q <= 1'b0;
StateBackOff <= 1'b0;
StateDefer <= 1'b1;
end
else
begin
StateData[1:0] <= StartData[1:0];
StateJam_q <= StateJam;
if(StartDefer | StartIdle)
StateIPG <= 1'b0;
else
if(StartIPG)
StateIPG <= 1'b1;
if(StartDefer | StartPreamble)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartData[0] | StartJam)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartFCS | StartJam)
StatePAD <= 1'b0;
else
if(StartPAD)
StatePAD <= 1'b1;
if(StartJam | StartDefer)
StateFCS <= 1'b0;
else
if(StartFCS)
StateFCS <= 1'b1;
if(StartBackoff | StartDefer)
StateJam <= 1'b0;
else
if(StartJam)
StateJam <= 1'b1;
if(StartDefer)
StateBackOff <= 1'b0;
else
if(StartBackoff)
StateBackOff <= 1'b1;
if(StartIPG)
StateDefer <= 1'b0;
else
if(StartDefer)
StateDefer <= 1'b1;
end
end
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= 1'b1;
end
end
endmodule |
module eth_macstatus(
MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
r_FullD
);
input MRxClk;
input Reset;
input RxCrcError;
input MRxErr;
input MRxDV;
input RxStateSFD;
input [1:0] RxStateData;
input RxStatePreamble;
input RxStateIdle;
input Transmitting;
input [15:0] RxByteCnt;
input RxByteCntEq0;
input RxByteCntGreat2;
input RxByteCntMaxFrame;
input [3:0] MRxD;
input Collision;
input [5:0] CollValid;
input r_RecSmall;
input [15:0] r_MinFL;
input [15:0] r_MaxFL;
input r_HugEn;
input StartTxDone;
input StartTxAbort;
input [3:0] RetryCnt;
input MTxClk;
input MaxCollisionOccured;
input LateCollision;
input DeferIndication;
input TxStartFrm;
input StatePreamble;
input [1:0] StateData;
input CarrierSense;
input TxUsedData;
input Loopback;
input r_FullD;
output ReceivedLengthOK;
output ReceiveEnd;
output ReceivedPacketGood;
output InvalidSymbol;
output LatchedCrcError;
output RxLateCollision;
output ShortFrame;
output DribbleNibble;
output ReceivedPacketTooBig;
output LoadRxStatus;
output [3:0] RetryCntLatched;
output RetryLimit;
output LateCollLatched;
output DeferLatched;
input RstDeferLatched;
output CarrierSenseLost;
output LatchedMRxErr;
reg ReceiveEnd;
reg LatchedCrcError;
reg LatchedMRxErr;
reg LoadRxStatus;
reg InvalidSymbol;
reg [3:0] RetryCntLatched;
reg RetryLimit;
reg LateCollLatched;
reg DeferLatched;
reg CarrierSenseLost;
wire TakeSample;
wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedCrcError <= 1'b0;
else
if(RxStateSFD)
LatchedCrcError <= 1'b0;
else
if(RxStateData[0])
LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
end
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedMRxErr <= 1'b0;
else
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
LatchedMRxErr <= 1'b1;
else
LatchedMRxErr <= 1'b0;
end
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
// Time to take a sample
//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
assign TakeSample = (|RxStateData) & (~MRxDV) |
RxStateData[0] & MRxDV & RxByteCntMaxFrame;
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LoadRxStatus <= 1'b0;
else
LoadRxStatus <= TakeSample;
end
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceiveEnd <= 1'b0;
else
ReceiveEnd <= LoadRxStatus;
end
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
InvalidSymbol <= 1'b0;
else
if(LoadRxStatus & ~SetInvalidSymbol)
InvalidSymbol <= 1'b0;
else
if(SetInvalidSymbol)
InvalidSymbol <= 1'b1;
end
// Late Collision
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxLateCollision <= 1'b0;
else
if(LoadRxStatus)
RxLateCollision <= 1'b0;
else
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
RxLateCollision <= 1'b1;
end
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxColWindow <= 1'b1;
else
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
RxColWindow <= 1'b0;
else
if(RxStateIdle)
RxColWindow <= 1'b1;
end
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShortFrame <= 1'b0;
else
if(LoadRxStatus)
ShortFrame <= 1'b0;
else
if(TakeSample)
ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
end
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DribbleNibble <= 1'b0;
else
if(RxStateSFD)
DribbleNibble <= 1'b0;
else
if(~MRxDV & RxStateData[1])
DribbleNibble <= 1'b1;
end
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ReceivedPacketTooBig <= 1'b0;
else
if(LoadRxStatus)
ReceivedPacketTooBig <= 1'b0;
else
if(TakeSample)
ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCntLatched <= 4'h0;
else
if(StartTxDone | StartTxAbort)
RetryCntLatched <= RetryCnt;
end
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryLimit <= 1'h0;
else
if(StartTxDone | StartTxAbort)
RetryLimit <= MaxCollisionOccured;
end
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LateCollLatched <= 1'b0;
else
if(StartTxDone | StartTxAbort)
LateCollLatched <= LateCollision;
end
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DeferLatched <= 1'b0;
else
if(DeferIndication)
DeferLatched <= 1'b1;
else
if(RstDeferLatched)
DeferLatched <= 1'b0;
end
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
CarrierSenseLost <= 1'b0;
else
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
CarrierSenseLost <= 1'b1;
else
if(TxStartFrm)
CarrierSenseLost <= 1'b0;
end
endmodule |
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
RandomEq0, RandomEqByteCnt);
input MTxClk;
input Reset;
input StateJam;
input StateJam_q;
input [3:0] RetryCnt;
input [15:0] NibCnt;
input [9:0] ByteCnt;
output RandomEq0;
output RandomEqByteCnt;
wire Feedback;
reg [9:0] x;
wire [9:0] Random;
reg [9:0] RandomLatched;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
x[9:0] <= 0;
else
x[9:0] <= {x[8:0], Feedback};
end
assign Feedback = ~(x[2] ^ x[9]);
assign Random [0] = x[0];
assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RandomLatched <= 10'h000;
else
begin
if(StateJam & StateJam_q)
RandomLatched <= Random;
end
end
// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
assign RandomEq0 = RandomLatched == 10'h0;
assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
endmodule |
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
output Mdc; // Output clock
output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
reg Mdc;
reg [7:0] Counter;
wire CountEq0;
wire [7:0] CounterPreset;
wire [7:0] TempDivider;
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
// Counter counts half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Counter[7:0] <= 8'h1;
else
begin
if(CountEq0)
begin
Counter[7:0] <= CounterPreset[7:0];
end
else
Counter[7:0] <= Counter - 8'h1;
end
end
// Mdc is asserted every other half period
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Mdc <= 1'b0;
else
begin
if(CountEq0)
Mdc <= ~Mdc;
end
end
assign CountEq0 = Counter == 8'h0;
assign MdcEn = CountEq0 & ~Mdc;
assign MdcEn_n = CountEq0 & Mdc;
endmodule |
module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
LatchByte, ShiftedBit, Prsd, LinkFail);
input Clk; // Input clock (Host clock)
input Reset; // Reset signal
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
input Mdi; // MII input data
input [4:0] Fiad; // PHY address
input [4:0] Rgad; // Register address (within the selected PHY)
input [15:0]CtrlData; // Control data (data to be written to the PHY)
input WriteOp; // The current operation is a PHY register write operation
input [3:0] ByteSelect; // Byte select
input [1:0] LatchByte; // Byte select for latching (read operation)
output ShiftedBit; // Bit shifted out of the shift register
output[15:0]Prsd; // Read Status Data (data read from the PHY)
output LinkFail; // Link Integrity Signal
reg [7:0] ShiftReg; // Shift register for shifting the data in and out
reg [15:0]Prsd;
reg LinkFail;
// ShiftReg[7:0] :: Shift Register Data
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
ShiftReg[7:0] <= 8'h0;
Prsd[15:0] <= 16'h0;
LinkFail <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
if(|ByteSelect)
begin
/* verilator lint_off CASEINCOMPLETE */
/*case (ByteSelect[3:0]) // synopsys parallel_case full_case*/
case (ByteSelect[3:0])
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
endcase // case (ByteSelect[3:0])
/* verilator lint_on CASEINCOMPLETE */
end
else
begin
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
if(LatchByte[0])
begin
Prsd[7:0] <= {ShiftReg[6:0], Mdi};
if(Rgad == 5'h01)
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
end
else
begin
if(LatchByte[1])
Prsd[15:8] <= {ShiftReg[6:0], Mdi};
end
end
end
end
end
assign ShiftedBit = ShiftReg[7];
endmodule |
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
input Clk; // Host Clock
input Reset; // General Reset
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
input NoPre; // No Preamble (no 32-bit preamble)
input InProgress; // Operation in progress
input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
input [6:0] BitCounter; // Bit Counter
input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
wire SerialEn;
reg MdoEn_2d;
reg MdoEn_d;
reg MdoEn;
reg Mdo_2d;
reg Mdo_d;
reg Mdo; // MII Management Data Output
// Generation of the Serial Enable signal (enables the serialization of the data)
assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
| ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
// Generation of the MdoEn signal
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
MdoEn_2d <= 1'b0;
MdoEn_d <= 1'b0;
MdoEn <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
MdoEn_d <= MdoEn_2d;
MdoEn <= MdoEn_d;
end
end
end
// Generation of the Mdo signal.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
Mdo_2d <= 1'b0;
Mdo_d <= 1'b0;
Mdo <= 1'b0;
end
else
begin
if(MdcEn_n)
begin
Mdo_2d <= ~SerialEn & BitCounter<32;
Mdo_d <= ShiftedBit | Mdo_2d;
Mdo <= Mdo_d;
end
end
end
endmodule |
module eth_rxcounters
(
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
endmodule |
module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
StateDrop
);
input MRxClk;
input Reset;
input MRxDV;
input ByteCntEq0;
input ByteCntGreat2;
input MRxDEq5;
input Transmitting;
input MRxDEqD;
input IFGCounterEq24;
input ByteCntMaxFrame;
output [1:0] StateData;
output StateIdle;
output StateDrop;
output StatePreamble;
output StateSFD;
reg StateData0;
reg StateData1;
reg StateIdle;
reg StateDrop;
reg StatePreamble;
reg StateSFD;
wire StartIdle;
wire StartDrop;
wire StartData0;
wire StartData1;
wire StartPreamble;
wire StartSFD;
// Defining the next state
assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
StateIdle <= 1'b0;
StateDrop <= 1'b1;
StatePreamble <= 1'b0;
StateSFD <= 1'b0;
StateData0 <= 1'b0;
StateData1 <= 1'b0;
end
else
begin
if(StartPreamble | StartSFD | StartDrop)
StateIdle <= 1'b0;
else
if(StartIdle)
StateIdle <= 1'b1;
if(StartIdle)
StateDrop <= 1'b0;
else
if(StartDrop)
StateDrop <= 1'b1;
if(StartSFD | StartIdle | StartDrop)
StatePreamble <= 1'b0;
else
if(StartPreamble)
StatePreamble <= 1'b1;
if(StartPreamble | StartIdle | StartData0 | StartDrop)
StateSFD <= 1'b0;
else
if(StartSFD)
StateSFD <= 1'b1;
if(StartIdle | StartData1 | StartDrop)
StateData0 <= 1'b0;
else
if(StartData0)
StateData0 <= 1'b1;
if(StartIdle | StartData0 | StartDrop)
StateData1 <= 1'b0;
else
if(StartData1)
StateData1 <= 1'b1;
end
end
assign StateData[1:0] = {StateData1, StateData0};
endmodule |
module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
);
input MTxClk;
input MRxClk;
input TxReset;
input RxReset;
input [7:0] RxData;
input RxValid;
input RxStartFrm;
input RxEndFrm;
input RxFlow;
input ReceiveEnd;
input [47:0]MAC;
input DlyCrcEn;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmOut;
input ReceivedLengthOK;
input ReceivedPacketGood;
input TxUsedDataOutDetected;
input RxStatusWriteLatched_sync2;
input r_PassAll;
output Pause;
output ReceivedPauseFrm;
output AddressOK;
output SetPauseTimer;
reg Pause;
reg AddressOK; // Multicast or unicast address detected
reg TypeLengthOK; // Type/Length field contains 0x8808
reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
reg OpCodeOK; // PAUSE opcode detected (0x0001)
reg [2:0] DlyCrcCnt;
reg [4:0] ByteCnt;
reg [15:0] AssembledTimerValue;
reg [15:0] LatchedTimerValue;
reg ReceivedPauseFrm;
reg ReceivedPauseFrmWAddr;
reg PauseTimerEq0_sync1;
reg PauseTimerEq0_sync2;
reg [15:0] PauseTimer;
reg Divider2;
reg [5:0] SlotTimer;
wire [47:0] ReservedMulticast; // 0x0180C2000001
wire [15:0] TypeLength; // 0x8808
wire ResetByteCnt; //
wire IncrementByteCnt; //
wire ByteCntEq0; // ByteCnt = 0
wire ByteCntEq1; // ByteCnt = 1
wire ByteCntEq2; // ByteCnt = 2
wire ByteCntEq3; // ByteCnt = 3
wire ByteCntEq4; // ByteCnt = 4
wire ByteCntEq5; // ByteCnt = 5
wire ByteCntEq12; // ByteCnt = 12
wire ByteCntEq13; // ByteCnt = 13
wire ByteCntEq14; // ByteCnt = 14
wire ByteCntEq15; // ByteCnt = 15
wire ByteCntEq16; // ByteCnt = 16
wire ByteCntEq17; // ByteCnt = 17
wire ByteCntEq18; // ByteCnt = 18
wire DecrementPauseTimer; //
wire PauseTimerEq0; //
wire ResetSlotTimer; //
wire IncrementSlotTimer; //
wire SlotFinished; //
// Reserved multicast address and Type/Length for PAUSE control
assign ReservedMulticast = 48'h0180C2000001;
assign TypeLength = 16'h8808;
// Address Detection (Multicast or unicast)
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
AddressOK <= 1'b0;
else
if(DetectionWindow & ByteCntEq0)
AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
else
if(DetectionWindow & ByteCntEq1)
AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
else
if(DetectionWindow & ByteCntEq2)
AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
else
if(DetectionWindow & ByteCntEq3)
AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
else
if(DetectionWindow & ByteCntEq4)
AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
else
if(DetectionWindow & ByteCntEq5)
AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
else
if(ReceiveEnd)
AddressOK <= 1'b0;
end
// TypeLengthOK (Type/Length Control frame detected)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
TypeLengthOK <= 1'b0;
else
if(DetectionWindow & ByteCntEq12)
TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
else
if(DetectionWindow & ByteCntEq13)
TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
else
if(ReceiveEnd)
TypeLengthOK <= 1'b0;
end
// Latch Control Frame Opcode
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
OpCodeOK <= 1'b0;
else
if(ByteCntEq16)
OpCodeOK <= 1'b0;
else
begin
if(DetectionWindow & ByteCntEq14)
OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00;
if(DetectionWindow & ByteCntEq15)
OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
end
end
// ReceivedPauseFrmWAddr (+Address Check)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
ReceivedPauseFrmWAddr <= 1'b0;
else
if(ReceiveEnd)
ReceivedPauseFrmWAddr <= 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
ReceivedPauseFrmWAddr <= 1'b1;
end
// Assembling 16-bit timer value from two 8-bit data
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
AssembledTimerValue[15:0] <= 16'h0;
else
if(RxStartFrm)
AssembledTimerValue[15:0] <= 16'h0;
else
begin
if(DetectionWindow & ByteCntEq16)
AssembledTimerValue[15:8] <= RxData[7:0];
if(DetectionWindow & ByteCntEq17)
AssembledTimerValue[7:0] <= RxData[7:0];
end
end
// Detection window (while PAUSE detection is possible)
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
DetectionWindow <= 1'b1;
else
if(ByteCntEq18)
DetectionWindow <= 1'b0;
else
if(ReceiveEnd)
DetectionWindow <= 1'b1;
end
// Latching Timer Value
always @ (posedge MRxClk or posedge RxReset )
begin
if(RxReset)
LatchedTimerValue[15:0] <= 16'h0;
else
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
LatchedTimerValue[15:0] <= AssembledTimerValue[15:0];
else
if(ReceiveEnd)
LatchedTimerValue[15:0] <= 16'h0;
end
// Delayed CEC counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
DlyCrcCnt <= 3'h0;
else
if(RxValid & RxEndFrm)
DlyCrcCnt <= 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &
(~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
// Byte counter
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ByteCnt[4:0] <= 5'h0;
else
if(ResetByteCnt)
ByteCnt[4:0] <= 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;
end
assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
assign DecrementPauseTimer = SlotFinished & |PauseTimer;
// PauseTimer[15:0]
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
PauseTimer[15:0] <= 16'h0;
else
if(SetPauseTimer)
PauseTimer[15:0] <= LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;
end
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
// Synchronization of the pause timer
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
PauseTimerEq0_sync1 <= 1'b1;
PauseTimerEq0_sync2 <= 1'b1;
end
else
begin
PauseTimerEq0_sync1 <= PauseTimerEq0;
PauseTimerEq0_sync2 <= PauseTimerEq0_sync1;
end
end
// Pause signal generation
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
Pause <= 1'b0;
else
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
Pause <= RxFlow & ~PauseTimerEq0_sync2;
end
// Divider2 is used for incrementing the Slot timer every other clock
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
Divider2 <= 1'b0;
else
if(|PauseTimer[15:0] & RxFlow)
Divider2 <= ~Divider2;
else
Divider2 <= 1'b0;
end
assign ResetSlotTimer = RxReset;
assign IncrementSlotTimer = Pause & RxFlow & Divider2;
// SlotTimer
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
SlotTimer[5:0] <= 6'h0;
else
if(ResetSlotTimer)
SlotTimer[5:0] <= 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;
end
assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
// Pause Frame received
always @ (posedge MRxClk or posedge RxReset)
begin
if(RxReset)
ReceivedPauseFrm <= 1'b0;
else
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
ReceivedPauseFrm <= 1'b0;
else
if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
ReceivedPauseFrm <= 1'b1;
end
endmodule |
module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
ByteCntEq6, ByteCntEq7, HASH0, HASH1, ByteCntEq0,
CrcHash, CrcHashGood, StateData, RxEndFrm,
Multicast, MAC, RxAbort, AddressMiss, PassAll,
ControlFrmAddressOK
);
input MRxClk;
input Reset;
input [7:0] RxData;
input Broadcast;
input r_Bro;
input r_Pro;
input ByteCntEq0;
input ByteCntEq2;
input ByteCntEq3;
input ByteCntEq4;
input ByteCntEq5;
input ByteCntEq6;
input ByteCntEq7;
input [31:0] HASH0;
input [31:0] HASH1;
input [5:0] CrcHash;
input CrcHashGood;
input Multicast;
input [47:0] MAC;
input [1:0] StateData;
input RxEndFrm;
input PassAll;
input ControlFrmAddressOK;
output RxAbort;
output AddressMiss;
wire BroadcastOK;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire RxAddressInvalid;
wire RxCheckEn;
wire HashBit;
wire [31:0] IntHash;
reg [7:0] ByteHash;
reg MulticastOK;
reg UnicastOK;
reg RxAbort;
reg AddressMiss;
assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
assign BroadcastOK = Broadcast & ~r_Bro;
assign RxCheckEn = | StateData;
// Address Error Reported at end of address cycle
// RxAbort clears after one cycle
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbort <= 1'b0;
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
RxAbort <= 1'b1;
else
RxAbort <= 1'b0;
end
// This ff holds the "Address Miss" information that is written to the RX BD status.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
AddressMiss <= 1'b0;
else if(ByteCntEq0)
AddressMiss <= 1'b0;
else if(ByteCntEq7 & RxCheckEn)
AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
end
// Hash Address Check, Multicast
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
MulticastOK <= 1'b0;
else if(RxEndFrm | RxAbort)
MulticastOK <= 1'b0;
else if(CrcHashGood & Multicast)
MulticastOK <= HashBit;
end
// Address Detection (unicast)
// start with ByteCntEq2 due to delay of addres from RxData
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
UnicastOK <= 1'b0;
else
if(RxCheckEn & ByteCntEq2)
UnicastOK <= RxData[7:0] == MAC[47:40];
else
if(RxCheckEn & ByteCntEq3)
UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq4)
UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq5)
UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq6)
UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK;
else
if(RxCheckEn & ByteCntEq7)
UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK;
else
if(RxEndFrm | RxAbort)
UnicastOK <= 1'b0;
end
assign IntHash = (CrcHash[5])? HASH1 : HASH0;
always@(CrcHash or IntHash)
begin
case(CrcHash[4:3])
2'b00: ByteHash = IntHash[7:0];
2'b01: ByteHash = IntHash[15:8];
2'b10: ByteHash = IntHash[23:16];
2'b11: ByteHash = IntHash[31:24];
endcase
end
assign HashBit = ByteHash[CrcHash[2:0]];
endmodule |
module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
ControlData, WillSendControlFrame, BlockTxDone
);
input MTxClk;
input TxReset;
input TxUsedDataIn;
input TxUsedDataOut;
input TxDoneIn;
input TxAbortIn;
input TxStartFrmIn;
input TPauseRq;
input TxUsedDataOutDetected;
input TxFlow;
input DlyCrcEn;
input [15:0] TxPauseTV;
input [47:0] MAC;
output TxCtrlStartFrm;
output TxCtrlEndFrm;
output SendingCtrlFrm;
output CtrlMux;
output [7:0] ControlData;
output WillSendControlFrame;
output BlockTxDone;
reg SendingCtrlFrm;
reg CtrlMux;
reg WillSendControlFrame;
reg [3:0] DlyCrcCnt;
reg [5:0] ByteCnt;
reg ControlEnd_q;
reg [7:0] MuxedCtrlData;
reg TxCtrlStartFrm;
reg TxCtrlStartFrm_q;
reg TxCtrlEndFrm;
reg [7:0] ControlData;
reg TxUsedDataIn_q;
reg BlockTxDone;
wire IncrementDlyCrcCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ControlEnd;
wire IncrementByteCntBy2;
wire EnableCnt;
// A command for Sending the control frame is active (latched)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
WillSendControlFrame <= 1'b0;
else
if(TxCtrlEndFrm & CtrlMux)
WillSendControlFrame <= 1'b0;
else
if(TPauseRq & TxFlow)
WillSendControlFrame <= 1'b1;
end
// Generation of the transmit control packet start frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlStartFrm <= 1'b0;
else
if(TxUsedDataIn_q & CtrlMux)
TxCtrlStartFrm <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
TxCtrlStartFrm <= 1'b1;
end
// Generation of the transmit control packet end frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxCtrlEndFrm <= 1'b0;
else
if(ControlEnd | ControlEnd_q)
TxCtrlEndFrm <= 1'b1;
else
TxCtrlEndFrm <= 1'b0;
end
// Generation of the multiplexer signal (controls muxes for switching between
// normal and control packets)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
CtrlMux <= 1'b0;
else
if(WillSendControlFrame & ~TxUsedDataOut)
CtrlMux <= 1'b1;
else
if(TxDoneIn)
CtrlMux <= 1'b0;
end
// Generation of the Sending Control Frame signal (enables padding and CRC)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
SendingCtrlFrm <= 1'b0;
else
if(WillSendControlFrame & TxCtrlStartFrm)
SendingCtrlFrm <= 1'b1;
else
if(TxDoneIn)
SendingCtrlFrm <= 1'b0;
end
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataIn_q <= 1'b0;
else
TxUsedDataIn_q <= TxUsedDataIn;
end
// Generation of the signal that will block sending the Done signal to the eth_wishbone module
// While sending the control frame
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
BlockTxDone <= 1'b0;
else
if(TxCtrlStartFrm)
BlockTxDone <= 1'b1;
else
if(TxStartFrmIn)
BlockTxDone <= 1'b0;
end
always @ (posedge MTxClk)
begin
ControlEnd_q <= ControlEnd;
TxCtrlStartFrm_q <= TxCtrlStartFrm;
end
assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
// Delayed CRC counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
DlyCrcCnt <= 4'h0;
else
if(ResetByteCnt)
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
// Byte counter
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ByteCnt <= 6'h0;
else
if(ResetByteCnt)
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
assign ControlEnd = ByteCnt[5:0] == 6'h22;
// Control data generation (goes to the TxEthMAC module)
always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
begin
case(ByteCnt)
6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
else
MuxedCtrlData[7:0] = 8'h0;
6'h2: MuxedCtrlData[7:0] = 8'h80;
6'h4: MuxedCtrlData[7:0] = 8'hC2;
6'h6: MuxedCtrlData[7:0] = 8'h00;
6'h8: MuxedCtrlData[7:0] = 8'h00;
6'hA: MuxedCtrlData[7:0] = 8'h01;
6'hC: MuxedCtrlData[7:0] = MAC[47:40];
6'hE: MuxedCtrlData[7:0] = MAC[39:32];
6'h10: MuxedCtrlData[7:0] = MAC[31:24];
6'h12: MuxedCtrlData[7:0] = MAC[23:16];
6'h14: MuxedCtrlData[7:0] = MAC[15:8];
6'h16: MuxedCtrlData[7:0] = MAC[7:0];
6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
6'h1A: MuxedCtrlData[7:0] = 8'h08;
6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
6'h1E: MuxedCtrlData[7:0] = 8'h01;
6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
default: MuxedCtrlData[7:0] = 8'h0;
endcase
end
// Latched Control data
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
ControlData[7:0] <= 8'h0;
else
if(~ByteCnt[0])
ControlData[7:0] <= MuxedCtrlData[7:0];
end
endmodule |
module ROM (clk, en, address, instr);
input wire [30:0] address;
input wire clk;
input wire en;
output wire [31:0] instr;
assign instr = (address == 31'h0000_0000) ? 32'h8000_0337 :
(address == 31'h0000_0004) ? 32'h0003_03E7 :
32'h0000_0000;
//always_ff @(posedge clk)
//always@(*)
// if (en)
// begin
// case (address)
// //{31'h0}: instr <= 32'h37030080;
// {31'h0}: instr <= 32'h80000337;
// //{31'h4}: instr <= 32'hE7030300;
// {31'h4}: instr <= 32'h000303E7;
// default: instr <= 32'h0;
// endcase // case (address)
// end
endmodule |
module wishbone_debug_master(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, \wb_in.dat , \wb_in.ack , \wb_in.stall , dmi_dout, dmi_ack, \wb_out.adr , \wb_out.dat , \wb_out.sel , \wb_out.cyc , \wb_out.stb , \wb_out.we );
wire _00_;
wire _01_;
wire _02_;
wire [63:0] _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire [3:0] _08_;
wire [63:0] _09_;
wire _10_;
wire _11_;
wire _12_;
wire [10:0] _13_;
wire [63:0] _14_;
wire [10:0] _15_;
wire _16_;
wire [10:0] _17_;
wire [63:0] _18_;
wire [10:0] _19_;
wire [63:0] _20_;
wire [10:0] _21_;
reg [63:0] _22_;
reg [10:0] _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [63:0] _34_;
reg [63:0] _35_;
wire _36_;
wire _37_;
wire _38_;
wire [1:0] _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire [1:0] _44_;
wire _45_;
wire _46_;
wire _47_;
wire [1:0] _48_;
wire _49_;
wire _50_;
wire [1:0] _51_;
wire _52_;
wire _53_;
wire [1:0] _54_;
wire _55_;
reg _56_;
reg [1:0] _57_;
reg _58_;
input clk;
wire clk;
wire [63:0] data_latch;
output dmi_ack;
wire dmi_ack;
input [1:0] dmi_addr;
wire [1:0] dmi_addr;
input [63:0] dmi_din;
wire [63:0] dmi_din;
output [63:0] dmi_dout;
wire [63:0] dmi_dout;
input dmi_req;
wire dmi_req;
input dmi_wr;
wire dmi_wr;
wire do_inc;
wire [63:0] reg_addr;
wire [10:0] reg_ctrl;
wire [63:0] reg_ctrl_out;
input rst;
wire rst;
wire [1:0] state;
input \wb_in.ack ;
wire \wb_in.ack ;
input [63:0] \wb_in.dat ;
wire [63:0] \wb_in.dat ;
input \wb_in.stall ;
wire \wb_in.stall ;
output [28:0] \wb_out.adr ;
wire [28:0] \wb_out.adr ;
output \wb_out.cyc ;
wire \wb_out.cyc ;
output [63:0] \wb_out.dat ;
wire [63:0] \wb_out.dat ;
output [7:0] \wb_out.sel ;
wire [7:0] \wb_out.sel ;
output \wb_out.stb ;
wire \wb_out.stb ;
output \wb_out.we ;
wire \wb_out.we ;
assign _00_ = dmi_addr == 2'h0;
assign _01_ = dmi_addr == 2'h1;
assign _02_ = dmi_addr == 2'h2;
function [63:0] \5977 ;
input [63:0] a;
input [191:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\5977 = b[63:0];
3'b?1?:
\5977 = b[127:64];
3'b1??:
\5977 = b[191:128];
default:
\5977 = a;
endcase
endfunction
assign _03_ = \5977 (64'h0000000000000000, { reg_ctrl_out, data_latch, reg_addr }, { _02_, _01_, _00_ });
assign _04_ = reg_ctrl[10:9] == 2'h0;
assign _05_ = reg_ctrl[10:9] == 2'h1;
assign _06_ = reg_ctrl[10:9] == 2'h2;
assign _07_ = reg_ctrl[10:9] == 2'h3;
function [3:0] \6000 ;
input [3:0] a;
input [15:0] b;
input [3:0] s;
(* parallel_case *)
casez (s)
4'b???1:
\6000 = b[3:0];
4'b??1?:
\6000 = b[7:4];
4'b?1??:
\6000 = b[11:8];
4'b1???:
\6000 = b[15:12];
default:
\6000 = a;
endcase
endfunction
assign _08_ = \6000 (4'h8, 16'h8421, { _07_, _06_, _05_, _04_ });
assign _09_ = reg_addr + { 60'h000000000000000, _08_ };
assign _10_ = dmi_req & dmi_wr;
assign _11_ = dmi_addr == 2'h0;
assign _12_ = dmi_addr == 2'h2;
assign _13_ = _12_ ? dmi_din[10:0] : reg_ctrl;
assign _14_ = _16_ ? dmi_din : reg_addr;
assign _15_ = _11_ ? reg_ctrl : _13_;
assign _16_ = _10_ & _11_;
assign _17_ = _10_ ? _15_ : reg_ctrl;
assign _18_ = do_inc ? _09_ : _14_;
assign _19_ = do_inc ? reg_ctrl : _17_;
assign _20_ = rst ? 64'h0000000000000000 : _18_;
assign _21_ = rst ? 11'h000 : _19_;
always @(posedge clk)
_22_ <= _20_;
always @(posedge clk)
_23_ <= _21_;
assign _24_ = dmi_addr != 2'h1;
assign _25_ = state == 2'h2;
assign _26_ = _24_ | _25_;
assign _27_ = _26_ ? dmi_req : 1'h0;
assign _28_ = state == 2'h1;
assign _29_ = _28_ ? 1'h1 : 1'h0;
assign _30_ = state == 2'h1;
assign _31_ = _30_ & \wb_in.ack ;
assign _32_ = ~ dmi_wr;
assign _33_ = _31_ & _32_;
assign _34_ = _33_ ? \wb_in.dat : data_latch;
always @(posedge clk)
_35_ <= _34_;
assign _36_ = dmi_addr == 2'h1;
assign _37_ = dmi_req & _36_;
assign _38_ = _37_ ? 1'h1 : _56_;
assign _39_ = _37_ ? 2'h1 : state;
assign _40_ = state == 2'h0;
assign _41_ = ~ \wb_in.stall ;
assign _42_ = _41_ ? 1'h0 : _56_;
assign _43_ = \wb_in.ack ? 1'h0 : _42_;
assign _44_ = \wb_in.ack ? 2'h2 : state;
assign _45_ = \wb_in.ack ? reg_ctrl[8] : do_inc;
assign _46_ = state == 2'h1;
assign _47_ = ~ dmi_req;
assign _48_ = _47_ ? 2'h0 : state;
assign _49_ = state == 2'h2;
function [0:0] \6089 ;
input [0:0] a;
input [2:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\6089 = b[0:0];
3'b?1?:
\6089 = b[1:1];
3'b1??:
\6089 = b[2:2];
default:
\6089 = a;
endcase
endfunction
assign _50_ = \6089 (1'hx, { _56_, _43_, _38_ }, { _49_, _46_, _40_ });
function [1:0] \6091 ;
input [1:0] a;
input [5:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\6091 = b[1:0];
3'b?1?:
\6091 = b[3:2];
3'b1??:
\6091 = b[5:4];
default:
\6091 = a;
endcase
endfunction
assign _51_ = \6091 (2'hx, { _48_, _44_, _39_ }, { _49_, _46_, _40_ });
function [0:0] \6094 ;
input [0:0] a;
input [2:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\6094 = b[0:0];
3'b?1?:
\6094 = b[1:1];
3'b1??:
\6094 = b[2:2];
default:
\6094 = a;
endcase
endfunction
assign _52_ = \6094 (1'hx, { 1'h0, _45_, do_inc }, { _49_, _46_, _40_ });
assign _53_ = rst ? 1'h0 : _50_;
assign _54_ = rst ? 2'h0 : _51_;
assign _55_ = rst ? 1'h0 : _52_;
always @(posedge clk)
_56_ <= _53_;
always @(posedge clk)
_57_ <= _54_;
always @(posedge clk)
_58_ <= _55_;
assign reg_addr = _22_;
assign reg_ctrl_out = { 53'h00000000000000, reg_ctrl };
assign reg_ctrl = _23_;
assign data_latch = _35_;
assign state = _57_;
assign do_inc = _58_;
assign dmi_dout = _03_;
assign dmi_ack = _27_;
assign \wb_out.adr = reg_addr[31:3];
assign \wb_out.dat = dmi_din;
assign \wb_out.sel = reg_ctrl[7:0];
assign \wb_out.cyc = _29_;
assign \wb_out.stb = _56_;
assign \wb_out.we = dmi_wr;
endmodule |
module syscon_100000000_4096_0_0_0_589433b711fb88bdee7cbb7d486960b51e4c8efd(clk, rst, \wishbone_in.adr , \wishbone_in.dat , \wishbone_in.sel , \wishbone_in.cyc , \wishbone_in.stb , \wishbone_in.we , \wishbone_out.dat , \wishbone_out.ack , \wishbone_out.stall , dram_at_0, core_reset, soc_reset);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire [63:0] _08_;
wire [63:0] _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire [63:0] _22_;
wire [31:0] _23_;
reg [33:0] _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire _34_;
wire _35_;
wire [2:0] _36_;
reg [2:0] _37_;
input clk;
wire clk;
output core_reset;
wire core_reset;
output dram_at_0;
wire dram_at_0;
wire [39:0] info_clk;
wire [31:0] info_fl_off;
wire info_has_bram;
wire info_has_dram;
wire info_has_leth;
wire info_has_lsdc;
wire info_has_spif;
wire info_has_uart;
wire info_has_urt1;
wire [63:0] reg_braminfo;
wire [63:0] reg_clkinfo;
wire [2:0] reg_ctrl;
wire [63:0] reg_ctrl_out;
wire [63:0] reg_dramiinfo;
wire [63:0] reg_draminfo;
wire [63:0] reg_info;
wire [63:0] reg_out;
wire [63:0] reg_spiinfo;
wire [63:0] reg_uart0info;
wire [63:0] reg_uart1info;
input rst;
wire rst;
output soc_reset;
wire soc_reset;
wire uinfo_16550;
wire [31:0] uinfo_freq;
wire [33:0] wb_rsp;
input [29:0] \wishbone_in.adr ;
wire [29:0] \wishbone_in.adr ;
input \wishbone_in.cyc ;
wire \wishbone_in.cyc ;
input [31:0] \wishbone_in.dat ;
wire [31:0] \wishbone_in.dat ;
input [3:0] \wishbone_in.sel ;
wire [3:0] \wishbone_in.sel ;
input \wishbone_in.stb ;
wire \wishbone_in.stb ;
input \wishbone_in.we ;
wire \wishbone_in.we ;
output \wishbone_out.ack ;
wire \wishbone_out.ack ;
output [31:0] \wishbone_out.dat ;
wire [31:0] \wishbone_out.dat ;
output \wishbone_out.stall ;
wire \wishbone_out.stall ;
assign _00_ = 1'h0 ? 1'h1 : reg_ctrl[0];
assign _01_ = 1'h1 ? 1'h1 : 1'h0;
assign _02_ = 1'h1 ? 1'h1 : 1'h0;
assign _03_ = 1'h1 ? 1'h1 : 1'h0;
assign _04_ = 1'h1 ? 1'h1 : 1'h0;
assign _05_ = 1'h0 ? 1'h1 : 1'h0;
assign _06_ = 1'h0 ? 1'h1 : 1'h0;
assign _07_ = 1'h0 ? 1'h1 : 1'h0;
assign _08_ = 1'h1 ? 64'h0000000000000000 : 64'h0000000000000000;
assign _09_ = 1'h1 ? 64'h0000000000000000 : 64'h0000000000000000;
assign _10_ = 1'h1 ? 1'h1 : 1'h0;
assign _11_ = \wishbone_in.cyc & \wishbone_in.stb ;
assign _12_ = \wishbone_in.adr [6:1] == 6'h00;
assign _13_ = \wishbone_in.adr [6:1] == 6'h01;
assign _14_ = \wishbone_in.adr [6:1] == 6'h02;
assign _15_ = \wishbone_in.adr [6:1] == 6'h03;
assign _16_ = \wishbone_in.adr [6:1] == 6'h06;
assign _17_ = \wishbone_in.adr [6:1] == 6'h04;
assign _18_ = \wishbone_in.adr [6:1] == 6'h05;
assign _19_ = \wishbone_in.adr [6:1] == 6'h07;
assign _20_ = \wishbone_in.adr [6:1] == 6'h08;
assign _21_ = \wishbone_in.adr [6:1] == 6'h09;
function [63:0] \1971 ;
input [63:0] a;
input [639:0] b;
input [9:0] s;
(* parallel_case *)
casez (s)
10'b?????????1:
\1971 = b[63:0];
10'b????????1?:
\1971 = b[127:64];
10'b???????1??:
\1971 = b[191:128];
10'b??????1???:
\1971 = b[255:192];
10'b?????1????:
\1971 = b[319:256];
10'b????1?????:
\1971 = b[383:320];
10'b???1??????:
\1971 = b[447:384];
10'b??1???????:
\1971 = b[511:448];
10'b?1????????:
\1971 = b[575:512];
10'b1?????????:
\1971 = b[639:576];
default:
\1971 = a;
endcase
endfunction
assign _22_ = \1971 (64'h0000000000000000, { reg_uart1info, reg_uart0info, reg_spiinfo, reg_ctrl_out, reg_clkinfo, reg_dramiinfo, reg_draminfo, reg_braminfo, reg_info, 64'hf00daa5500010001 }, { _21_, _20_, _19_, _18_, _17_, _16_, _15_, _14_, _13_, _12_ });
assign _23_ = \wishbone_in.adr [0] ? reg_out[63:32] : reg_out[31:0];
always @(posedge clk)
_24_ <= wb_rsp;
assign _25_ = \wishbone_in.cyc & \wishbone_in.stb ;
assign _26_ = _25_ & \wishbone_in.we ;
assign _27_ = \wishbone_in.adr [6:1] == 6'h05;
assign _28_ = ~ \wishbone_in.adr [0];
assign _29_ = _27_ & _28_;
assign _30_ = _26_ & _29_;
assign _31_ = _30_ ? \wishbone_in.dat [2] : reg_ctrl[2];
assign _32_ = reg_ctrl[2] ? 1'h0 : _31_;
assign _33_ = _30_ ? \wishbone_in.dat [1] : reg_ctrl[1];
assign _34_ = reg_ctrl[1] ? 1'h0 : _33_;
assign _35_ = _30_ ? \wishbone_in.dat [0] : reg_ctrl[0];
assign _36_ = rst ? 3'h0 : { _32_, _34_, _35_ };
always @(posedge clk)
_37_ <= _36_;
assign reg_out = _22_;
assign reg_ctrl = _37_;
assign reg_ctrl_out = { 61'h0000000000000000, reg_ctrl };
assign reg_info = { 55'h00000000000000, info_has_lsdc, 1'h0, info_has_urt1, 1'h1, info_has_leth, info_has_spif, info_has_bram, info_has_dram, info_has_uart };
assign reg_braminfo = 64'h0000000000001000;
assign reg_draminfo = _08_;
assign reg_dramiinfo = _09_;
assign reg_clkinfo = { 24'h000000, info_clk };
assign reg_spiinfo = { 32'h00000000, info_fl_off };
assign reg_uart0info = { 31'h00000000, uinfo_16550, uinfo_freq };
assign reg_uart1info = { 32'h00000001, uinfo_freq };
assign info_has_dram = _02_;
assign info_has_bram = _03_;
assign info_has_uart = _01_;
assign info_has_spif = _04_;
assign info_has_leth = _05_;
assign info_has_lsdc = _06_;
assign info_has_urt1 = _07_;
assign info_clk = 40'h0005f5e100;
assign info_fl_off = 32'd0;
assign uinfo_16550 = _10_;
assign uinfo_freq = 32'd100000000;
assign wb_rsp = { 1'h0, _11_, _23_ };
assign \wishbone_out.dat = _24_[31:0];
assign \wishbone_out.ack = _24_[32];
assign \wishbone_out.stall = _24_[33];
assign dram_at_0 = _00_;
assign core_reset = reg_ctrl[1];
assign soc_reset = reg_ctrl[2];
endmodule |
module random(clk, data, raw, err);
input clk;
wire clk;
output [63:0] data;
wire [63:0] data;
output err;
wire err;
output [63:0] raw;
wire [63:0] raw;
assign data = 64'hffffffffffffffff;
assign raw = 64'hffffffffffffffff;
assign err = 1'h1;
endmodule |
module xics_icp(clk, rst, \wb_in.adr , \wb_in.dat , \wb_in.sel , \wb_in.cyc , \wb_in.stb , \wb_in.we , \ics_in.src , \ics_in.pri , \wb_out.dat , \wb_out.ack , \wb_out.stall , core_irq_out);
reg _00_;
reg [73:0] _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire [7:0] _06_;
wire [7:0] _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire [23:0] _14_;
wire [7:0] _15_;
wire _16_;
wire [31:0] _17_;
wire _18_;
wire _19_;
wire _20_;
wire [31:0] _21_;
wire _22_;
wire [23:0] _23_;
wire [7:0] _24_;
wire _25_;
wire [23:0] _26_;
wire [7:0] _27_;
wire [7:0] _28_;
wire [7:0] _29_;
wire [7:0] _30_;
wire _31_;
wire _32_;
wire [73:0] _33_;
input clk;
wire clk;
output core_irq_out;
wire core_irq_out;
input [7:0] \ics_in.pri ;
wire [7:0] \ics_in.pri ;
input [3:0] \ics_in.src ;
wire [3:0] \ics_in.src ;
wire [73:0] r;
wire [73:0] r_next;
input rst;
wire rst;
input [29:0] \wb_in.adr ;
wire [29:0] \wb_in.adr ;
input \wb_in.cyc ;
wire \wb_in.cyc ;
input [31:0] \wb_in.dat ;
wire [31:0] \wb_in.dat ;
input [3:0] \wb_in.sel ;
wire [3:0] \wb_in.sel ;
input \wb_in.stb ;
wire \wb_in.stb ;
input \wb_in.we ;
wire \wb_in.we ;
output \wb_out.ack ;
wire \wb_out.ack ;
output [31:0] \wb_out.dat ;
wire [31:0] \wb_out.dat ;
output \wb_out.stall ;
wire \wb_out.stall ;
always @(posedge clk)
_00_ <= r[40];
always @(posedge clk)
_01_ <= r_next;
assign _02_ = \wb_in.cyc & \wb_in.stb ;
assign _03_ = { \wb_in.adr [5:0], 2'h0 } == 8'h00;
assign _04_ = { \wb_in.adr [5:0], 2'h0 } == 8'h04;
assign _05_ = { \wb_in.adr [5:0], 2'h0 } == 8'h0c;
function [7:0] \2970 ;
input [7:0] a;
input [23:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\2970 = b[7:0];
3'b?1?:
\2970 = b[15:8];
3'b1??:
\2970 = b[23:16];
default:
\2970 = a;
endcase
endfunction
assign _06_ = \2970 (r[31:24], { r[31:24], \wb_in.dat [7:0], \wb_in.dat [7:0] }, { _05_, _04_, _03_ });
function [7:0] \2972 ;
input [7:0] a;
input [23:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\2972 = b[7:0];
3'b?1?:
\2972 = b[15:8];
3'b1??:
\2972 = b[23:16];
default:
\2972 = a;
endcase
endfunction
assign _07_ = \2972 (r[39:32], { \wb_in.dat [7:0], r[39:32], r[39:32] }, { _05_, _04_, _03_ });
assign _08_ = { \wb_in.adr [5:0], 2'h0 } == 8'h00;
assign _09_ = \wb_in.sel == 4'hf;
assign _10_ = _09_ ? 1'h1 : 1'h0;
assign _11_ = { \wb_in.adr [5:0], 2'h0 } == 8'h04;
assign _12_ = { \wb_in.adr [5:0], 2'h0 } == 8'h0c;
function [0:0] \2997 ;
input [0:0] a;
input [2:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\2997 = b[0:0];
3'b?1?:
\2997 = b[1:1];
3'b1??:
\2997 = b[2:2];
default:
\2997 = a;
endcase
endfunction
assign _13_ = \2997 (1'h0, { 1'h0, _10_, 1'h0 }, { _12_, _11_, _08_ });
function [23:0] \3001 ;
input [23:0] a;
input [71:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\3001 = b[23:0];
3'b?1?:
\3001 = b[47:24];
3'b1??:
\3001 = b[71:48];
default:
\3001 = a;
endcase
endfunction
assign _14_ = \3001 (24'h000000, { 24'h000000, r[23:0], r[23:0] }, { _12_, _11_, _08_ });
function [7:0] \3005 ;
input [7:0] a;
input [23:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\3005 = b[7:0];
3'b?1?:
\3005 = b[15:8];
3'b1??:
\3005 = b[23:16];
default:
\3005 = a;
endcase
endfunction
assign _15_ = \3005 (8'h00, { r[39:24], r[31:24] }, { _12_, _11_, _08_ });
assign _16_ = \wb_in.we ? 1'h0 : _13_;
assign _17_ = \wb_in.we ? 32'd0 : { _15_, _14_ };
assign _18_ = _02_ & \wb_in.we ;
assign _19_ = _02_ ? 1'h1 : 1'h0;
assign _20_ = _02_ ? _16_ : 1'h0;
assign _21_ = _02_ ? _17_ : 32'd0;
assign _22_ = \ics_in.pri != 8'hff;
assign _23_ = _22_ ? { 20'h00001, \ics_in.src } : 24'h000000;
assign _24_ = _22_ ? \ics_in.pri : 8'hff;
assign _25_ = r[39:32] < _24_;
assign _26_ = _25_ ? 24'h000002 : _23_;
assign _27_ = _25_ ? r[39:32] : _24_;
assign _28_ = _18_ ? _06_ : r[31:24];
assign _29_ = _20_ ? _27_ : _28_;
assign _30_ = _18_ ? _07_ : r[39:32];
assign _31_ = _27_ < _29_;
assign _32_ = _31_ ? 1'h1 : 1'h0;
assign _33_ = rst ? 74'h000000000ff00000000 : { _19_, _21_[7:0], _21_[15:8], _21_[23:16], _21_[31:24], _32_, _30_, _29_, _26_ };
assign r = _01_;
assign r_next = _33_;
assign \wb_out.dat = r[72:41];
assign \wb_out.ack = r[73];
assign \wb_out.stall = 1'h0;
assign core_irq_out = _00_;
endmodule |
module core_debug_0(clk, rst, dmi_addr, dmi_din, dmi_req, dmi_wr, terminate, core_stopped, nia, msr, dbg_gpr_ack, dbg_gpr_data, log_data, log_read_addr, dmi_dout, dmi_ack, core_stop, core_rst, icache_rst, dbg_gpr_req, dbg_gpr_addr, log_read_data, log_write_addr, terminated_out);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire [63:0] _11_;
wire _12_;
wire _13_;
wire _14_;
wire [31:0] _15_;
wire _16_;
wire [7:0] _17_;
wire _18_;
wire [7:0] _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
wire _26_;
wire _27_;
wire _28_;
wire _29_;
wire _30_;
wire _31_;
wire _32_;
wire _33_;
wire [63:0] _34_;
wire [31:0] _35_;
wire [63:0] _36_;
wire [6:0] _37_;
wire [31:0] _38_;
wire [63:0] _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire _44_;
wire [6:0] _45_;
wire [31:0] _46_;
wire [63:0] _47_;
wire _48_;
wire _49_;
wire _50_;
wire _51_;
wire _52_;
wire [6:0] _53_;
wire [31:0] _54_;
wire [63:0] _55_;
wire _56_;
wire _57_;
wire [1:0] _58_;
wire [1:0] _59_;
wire _60_;
wire _61_;
wire _62_;
wire _63_;
wire _64_;
wire _65_;
wire [1:0] _66_;
wire [29:0] _67_;
wire [63:0] _68_;
wire _69_;
wire _70_;
wire _71_;
wire _72_;
wire _73_;
wire _74_;
wire _75_;
wire _76_;
wire _77_;
wire _78_;
wire _79_;
wire [6:0] _80_;
wire [31:0] _81_;
wire [63:0] _82_;
wire _83_;
wire _84_;
wire [7:0] _85_;
reg _86_;
reg _87_;
reg _88_;
reg _89_;
reg _90_;
reg _91_;
reg [6:0] _92_;
reg [31:0] _93_ = 32'd0;
reg [63:0] _94_ = 64'h0000000000000000;
reg _95_;
reg _96_;
reg [7:0] _97_ = 8'h00;
wire _98_;
wire _99_;
input clk;
wire clk;
output core_rst;
wire core_rst;
output core_stop;
wire core_stop;
input core_stopped;
wire core_stopped;
input dbg_gpr_ack;
wire dbg_gpr_ack;
output [6:0] dbg_gpr_addr;
wire [6:0] dbg_gpr_addr;
input [63:0] dbg_gpr_data;
wire [63:0] dbg_gpr_data;
output dbg_gpr_req;
wire dbg_gpr_req;
output dmi_ack;
wire dmi_ack;
input [3:0] dmi_addr;
wire [3:0] dmi_addr;
input [63:0] dmi_din;
wire [63:0] dmi_din;
output [63:0] dmi_dout;
wire [63:0] dmi_dout;
wire dmi_read_log_data;
wire dmi_read_log_data_1;
input dmi_req;
wire dmi_req;
wire dmi_req_1;
input dmi_wr;
wire dmi_wr;
wire do_icreset;
wire do_log_trigger;
wire do_reset;
wire do_step;
wire [6:0] gspr_index;
output icache_rst;
wire icache_rst;
input [255:0] log_data;
wire [255:0] log_data;
wire [31:0] log_dmi_addr;
wire [63:0] log_dmi_data;
wire [63:0] log_dmi_trigger;
input [31:0] log_read_addr;
wire [31:0] log_read_addr;
output [63:0] log_read_data;
wire [63:0] log_read_data;
wire [7:0] log_trigger_delay;
output [31:0] log_write_addr;
wire [31:0] log_write_addr;
input [63:0] msr;
wire [63:0] msr;
input [63:0] nia;
wire [63:0] nia;
input rst;
wire rst;
wire [63:0] stat_reg;
wire stopping;
input terminate;
wire terminate;
wire terminated;
output terminated_out;
wire terminated_out;
assign _00_ = dmi_addr != 4'h5;
assign _01_ = _00_ ? dmi_req : dbg_gpr_ack;
assign _02_ = dmi_addr == 4'h5;
assign _03_ = _02_ ? dmi_req : 1'h0;
assign _04_ = dmi_addr == 4'h1;
assign _05_ = dmi_addr == 4'h2;
assign _06_ = dmi_addr == 4'h3;
assign _07_ = dmi_addr == 4'h5;
assign _08_ = dmi_addr == 4'h6;
assign _09_ = dmi_addr == 4'h7;
assign _10_ = dmi_addr == 4'h8;
function [63:0] \26470 ;
input [63:0] a;
input [447:0] b;
input [6:0] s;
(* parallel_case *)
casez (s)
7'b??????1:
\26470 = b[63:0];
7'b?????1?:
\26470 = b[127:64];
7'b????1??:
\26470 = b[191:128];
7'b???1???:
\26470 = b[255:192];
7'b??1????:
\26470 = b[319:256];
7'b?1?????:
\26470 = b[383:320];
7'b1??????:
\26470 = b[447:384];
default:
\26470 = a;
endcase
endfunction
assign _11_ = \26470 (64'h0000000000000000, { log_dmi_trigger, log_dmi_data, 32'h00000001, log_dmi_addr, dbg_gpr_data, msr, nia, stat_reg }, { _10_, _09_, _08_, _07_, _06_, _05_, _04_ });
assign _12_ = { 24'h000000, log_trigger_delay } != 32'd0;
assign _13_ = do_log_trigger | _12_;
assign _14_ = { 24'h000000, log_trigger_delay } == 32'd255;
assign _15_ = { 24'h000000, log_trigger_delay } + 32'd1;
assign _16_ = _18_ ? 1'h1 : log_dmi_trigger[1];
assign _17_ = _14_ ? 8'h00 : _15_[7:0];
assign _18_ = _13_ & _14_;
assign _19_ = _13_ ? _17_ : log_trigger_delay;
assign _20_ = ~ dmi_req_1;
assign _21_ = dmi_req & _20_;
assign _22_ = dmi_addr == 4'h0;
assign _23_ = dmi_din[1] ? 1'h1 : 1'h0;
assign _24_ = dmi_din[1] ? 1'h0 : terminated;
assign _25_ = dmi_din[0] ? 1'h1 : stopping;
assign _26_ = dmi_din[3] ? 1'h1 : 1'h0;
assign _27_ = dmi_din[3] ? 1'h0 : _24_;
assign _28_ = dmi_din[2] ? 1'h1 : 1'h0;
assign _29_ = dmi_din[4] ? 1'h0 : _25_;
assign _30_ = dmi_din[4] ? 1'h0 : _27_;
assign _31_ = dmi_addr == 4'h4;
assign _32_ = dmi_addr == 4'h6;
assign _33_ = dmi_addr == 4'h8;
assign _34_ = _33_ ? dmi_din : { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] };
assign _35_ = _32_ ? dmi_din[31:0] : log_dmi_addr;
assign _36_ = _32_ ? { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] } : _34_;
assign _37_ = _31_ ? dmi_din[6:0] : gspr_index;
assign _38_ = _31_ ? log_dmi_addr : _35_;
assign _39_ = _31_ ? { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] } : _36_;
assign _40_ = _60_ ? _29_ : stopping;
assign _41_ = _22_ ? _26_ : 1'h0;
assign _42_ = _22_ ? _23_ : 1'h0;
assign _43_ = _22_ ? _28_ : 1'h0;
assign _44_ = _64_ ? _30_ : terminated;
assign _45_ = _22_ ? gspr_index : _37_;
assign _46_ = _22_ ? log_dmi_addr : _38_;
assign _47_ = _22_ ? { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] } : _39_;
assign _48_ = dmi_wr & _22_;
assign _49_ = dmi_wr ? _41_ : 1'h0;
assign _50_ = dmi_wr ? _42_ : 1'h0;
assign _51_ = dmi_wr ? _43_ : 1'h0;
assign _52_ = dmi_wr & _22_;
assign _53_ = _65_ ? _45_ : gspr_index;
assign _54_ = dmi_wr ? _46_ : log_dmi_addr;
assign _55_ = dmi_wr ? _47_ : { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] };
assign _56_ = ~ dmi_read_log_data;
assign _57_ = _56_ & dmi_read_log_data_1;
assign _58_ = log_dmi_addr[1:0] + 2'h1;
assign _59_ = _57_ ? _58_ : log_dmi_addr[1:0];
assign _60_ = _21_ & _48_;
assign _61_ = _21_ ? _49_ : 1'h0;
assign _62_ = _21_ ? _50_ : 1'h0;
assign _63_ = _21_ ? _51_ : 1'h0;
assign _64_ = _21_ & _52_;
assign _65_ = _21_ & dmi_wr;
assign _66_ = _21_ ? _54_[1:0] : _59_;
assign _67_ = _21_ ? _54_[31:2] : log_dmi_addr[31:2];
assign _68_ = _21_ ? _55_ : { log_dmi_trigger[63:2], _16_, log_dmi_trigger[0] };
assign _69_ = dmi_addr == 4'h7;
assign _70_ = dmi_req & _69_;
assign _71_ = _70_ ? 1'h1 : 1'h0;
assign _72_ = terminate ? 1'h1 : _40_;
assign _73_ = terminate ? 1'h1 : _44_;
assign _74_ = rst ? dmi_req_1 : dmi_req;
assign _75_ = rst ? 1'h0 : _72_;
assign _76_ = rst ? 1'h0 : _61_;
assign _77_ = rst ? 1'h0 : _62_;
assign _78_ = rst ? 1'h0 : _63_;
assign _79_ = rst ? 1'h0 : _73_;
assign _80_ = rst ? gspr_index : _53_;
assign _81_ = rst ? log_dmi_addr : { _67_, _66_ };
assign _82_ = rst ? log_dmi_trigger : _68_;
assign _83_ = rst ? dmi_read_log_data : _71_;
assign _84_ = rst ? dmi_read_log_data_1 : dmi_read_log_data;
assign _85_ = rst ? 8'h00 : _19_;
always @(posedge clk)
_86_ <= _74_;
always @(posedge clk)
_87_ <= _75_;
always @(posedge clk)
_88_ <= _76_;
always @(posedge clk)
_89_ <= _77_;
always @(posedge clk)
_90_ <= _78_;
always @(posedge clk)
_91_ <= _79_;
always @(posedge clk)
_92_ <= _80_;
always @(posedge clk)
_93_ <= _81_;
always @(posedge clk)
_94_ <= _82_;
always @(posedge clk)
_95_ <= _83_;
always @(posedge clk)
_96_ <= _84_;
always @(posedge clk)
_97_ <= _85_;
assign _98_ = ~ do_step;
assign _99_ = stopping & _98_;
assign dmi_req_1 = _86_;
assign stat_reg = { 61'h0000000000000000, terminated, core_stopped, stopping };
assign stopping = _87_;
assign do_step = _88_;
assign do_reset = _89_;
assign do_icreset = _90_;
assign terminated = _91_;
assign gspr_index = _92_;
assign log_dmi_addr = _93_;
assign log_dmi_data = 64'h0000000000000000;
assign log_dmi_trigger = _94_;
assign do_log_trigger = 1'h0;
assign dmi_read_log_data = _95_;
assign dmi_read_log_data_1 = _96_;
assign log_trigger_delay = _97_;
assign dmi_dout = _11_;
assign dmi_ack = _01_;
assign core_stop = _99_;
assign core_rst = do_reset;
assign icache_rst = do_icreset;
assign dbg_gpr_req = _03_;
assign dbg_gpr_addr = gspr_index;
assign log_read_data = 64'h0000000000000000;
assign log_write_addr = 32'd1;
assign terminated_out = terminated;
endmodule |
module bit_counter(clk, rs, count_right, do_popcnt, is_32bit, datalen, result);
reg [63:0] _000_;
reg [64:0] _001_;
wire _002_;
wire _003_;
wire [63:0] _004_;
wire _005_;
wire [31:0] _006_;
wire [63:0] _007_;
wire [63:0] _008_;
wire [64:0] _009_;
wire [63:0] _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire [63:0] _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire _294_;
wire _295_;
wire _296_;
wire _297_;
wire _298_;
wire _299_;
wire _300_;
wire _301_;
wire _302_;
wire _303_;
wire _304_;
wire _305_;
wire _306_;
wire _307_;
wire _308_;
wire _309_;
wire _310_;
wire _311_;
wire _312_;
wire _313_;
wire _314_;
wire _315_;
wire _316_;
wire _317_;
wire _318_;
wire _319_;
wire _320_;
wire _321_;
wire _322_;
wire _323_;
wire _324_;
wire _325_;
wire _326_;
reg [3:0] _327_;
reg _328_;
reg [31:0] _329_;
wire [1:0] _330_;
wire [1:0] _331_;
wire [1:0] _332_;
wire [1:0] _333_;
wire [1:0] _334_;
wire [1:0] _335_;
wire [1:0] _336_;
wire [1:0] _337_;
wire [1:0] _338_;
wire [1:0] _339_;
wire [1:0] _340_;
wire [1:0] _341_;
wire [1:0] _342_;
wire [1:0] _343_;
wire [1:0] _344_;
wire [1:0] _345_;
wire [1:0] _346_;
wire [1:0] _347_;
wire [1:0] _348_;
wire [1:0] _349_;
wire [1:0] _350_;
wire [1:0] _351_;
wire [1:0] _352_;
wire [1:0] _353_;
wire [1:0] _354_;
wire [1:0] _355_;
wire [1:0] _356_;
wire [1:0] _357_;
wire [1:0] _358_;
wire [1:0] _359_;
wire [1:0] _360_;
wire [1:0] _361_;
wire [2:0] _362_;
wire [2:0] _363_;
wire [2:0] _364_;
wire [2:0] _365_;
wire [2:0] _366_;
wire [2:0] _367_;
wire [2:0] _368_;
wire [2:0] _369_;
wire [2:0] _370_;
wire [2:0] _371_;
wire [2:0] _372_;
wire [2:0] _373_;
wire [2:0] _374_;
wire [2:0] _375_;
wire [2:0] _376_;
wire [2:0] _377_;
wire [3:0] _378_;
wire [3:0] _379_;
wire [3:0] _380_;
wire [3:0] _381_;
wire [3:0] _382_;
wire [3:0] _383_;
wire [3:0] _384_;
wire [3:0] _385_;
wire [5:0] _386_;
wire [5:0] _387_;
wire [5:0] _388_;
wire [5:0] _389_;
wire [5:0] _390_;
wire [5:0] _391_;
wire _392_;
wire _393_;
wire [6:0] _394_;
wire [5:0] _395_;
wire _396_;
wire [5:0] _397_;
wire [3:0] _398_;
wire [2:0] _399_;
wire [3:0] _400_;
wire [3:0] _401_;
wire [3:0] _402_;
wire [3:0] _403_;
wire [1:0] _404_;
wire [3:0] _405_;
wire [3:0] _406_;
wire [3:0] _407_;
wire _408_;
wire [63:0] _409_;
wire [5:0] bitnum;
input clk;
wire clk;
wire [63:0] cntz;
input count_right;
wire count_right;
input [3:0] datalen;
wire [3:0] datalen;
wire [3:0] dlen_r;
input do_popcnt;
wire do_popcnt;
wire [63:0] \edge ;
wire [63:0] inp;
wire [63:0] inp_r;
input is_32bit;
wire is_32bit;
wire [63:0] onehot;
wire [63:0] pc2;
wire [11:0] pc32;
wire [47:0] pc4;
wire [31:0] pc8;
wire [31:0] pc8_r;
wire pcnt_r;
wire [63:0] popcnt;
output [63:0] result;
wire [63:0] result;
input [63:0] rs;
wire [63:0] rs;
wire [64:0] sum;
wire [64:0] sum_r;
always @(posedge clk)
_000_ <= inp;
always @(posedge clk)
_001_ <= sum;
assign _002_ = ~ is_32bit;
assign _003_ = ~ count_right;
assign _004_ = _003_ ? { rs[0], rs[1], rs[2], rs[3], rs[4], rs[5], rs[6], rs[7], rs[8], rs[9], rs[10], rs[11], rs[12], rs[13], rs[14], rs[15], rs[16], rs[17], rs[18], rs[19], rs[20], rs[21], rs[22], rs[23], rs[24], rs[25], rs[26], rs[27], rs[28], rs[29], rs[30], rs[31], rs[32], rs[33], rs[34], rs[35], rs[36], rs[37], rs[38], rs[39], rs[40], rs[41], rs[42], rs[43], rs[44], rs[45], rs[46], rs[47], rs[48], rs[49], rs[50], rs[51], rs[52], rs[53], rs[54], rs[55], rs[56], rs[57], rs[58], rs[59], rs[60], rs[61], rs[62], rs[63] } : rs;
assign _005_ = ~ count_right;
assign _006_ = _005_ ? { rs[0], rs[1], rs[2], rs[3], rs[4], rs[5], rs[6], rs[7], rs[8], rs[9], rs[10], rs[11], rs[12], rs[13], rs[14], rs[15], rs[16], rs[17], rs[18], rs[19], rs[20], rs[21], rs[22], rs[23], rs[24], rs[25], rs[26], rs[27], rs[28], rs[29], rs[30], rs[31] } : rs[31:0];
assign _007_ = _002_ ? _004_ : { 32'hffffffff, _006_ };
assign _008_ = ~ inp;
assign _009_ = { 1'h0, _008_ } + 65'h00000000000000001;
assign _010_ = sum_r[63:0] | inp_r;
assign _011_ = ~ \edge [0];
assign _012_ = \edge [1] & _011_;
assign _013_ = 1'h0 | _012_;
assign _014_ = ~ \edge [2];
assign _015_ = \edge [3] & _014_;
assign _016_ = _013_ | _015_;
assign _017_ = ~ \edge [4];
assign _018_ = \edge [5] & _017_;
assign _019_ = _016_ | _018_;
assign _020_ = ~ \edge [6];
assign _021_ = \edge [7] & _020_;
assign _022_ = _019_ | _021_;
assign _023_ = ~ \edge [8];
assign _024_ = \edge [9] & _023_;
assign _025_ = _022_ | _024_;
assign _026_ = ~ \edge [10];
assign _027_ = \edge [11] & _026_;
assign _028_ = _025_ | _027_;
assign _029_ = ~ \edge [12];
assign _030_ = \edge [13] & _029_;
assign _031_ = _028_ | _030_;
assign _032_ = ~ \edge [14];
assign _033_ = \edge [15] & _032_;
assign _034_ = _031_ | _033_;
assign _035_ = ~ \edge [16];
assign _036_ = \edge [17] & _035_;
assign _037_ = _034_ | _036_;
assign _038_ = ~ \edge [18];
assign _039_ = \edge [19] & _038_;
assign _040_ = _037_ | _039_;
assign _041_ = ~ \edge [20];
assign _042_ = \edge [21] & _041_;
assign _043_ = _040_ | _042_;
assign _044_ = ~ \edge [22];
assign _045_ = \edge [23] & _044_;
assign _046_ = _043_ | _045_;
assign _047_ = ~ \edge [24];
assign _048_ = \edge [25] & _047_;
assign _049_ = _046_ | _048_;
assign _050_ = ~ \edge [26];
assign _051_ = \edge [27] & _050_;
assign _052_ = _049_ | _051_;
assign _053_ = ~ \edge [28];
assign _054_ = \edge [29] & _053_;
assign _055_ = _052_ | _054_;
assign _056_ = ~ \edge [30];
assign _057_ = \edge [31] & _056_;
assign _058_ = _055_ | _057_;
assign _059_ = ~ \edge [32];
assign _060_ = \edge [33] & _059_;
assign _061_ = _058_ | _060_;
assign _062_ = ~ \edge [34];
assign _063_ = \edge [35] & _062_;
assign _064_ = _061_ | _063_;
assign _065_ = ~ \edge [36];
assign _066_ = \edge [37] & _065_;
assign _067_ = _064_ | _066_;
assign _068_ = ~ \edge [38];
assign _069_ = \edge [39] & _068_;
assign _070_ = _067_ | _069_;
assign _071_ = ~ \edge [40];
assign _072_ = \edge [41] & _071_;
assign _073_ = _070_ | _072_;
assign _074_ = ~ \edge [42];
assign _075_ = \edge [43] & _074_;
assign _076_ = _073_ | _075_;
assign _077_ = ~ \edge [44];
assign _078_ = \edge [45] & _077_;
assign _079_ = _076_ | _078_;
assign _080_ = ~ \edge [46];
assign _081_ = \edge [47] & _080_;
assign _082_ = _079_ | _081_;
assign _083_ = ~ \edge [48];
assign _084_ = \edge [49] & _083_;
assign _085_ = _082_ | _084_;
assign _086_ = ~ \edge [50];
assign _087_ = \edge [51] & _086_;
assign _088_ = _085_ | _087_;
assign _089_ = ~ \edge [52];
assign _090_ = \edge [53] & _089_;
assign _091_ = _088_ | _090_;
assign _092_ = ~ \edge [54];
assign _093_ = \edge [55] & _092_;
assign _094_ = _091_ | _093_;
assign _095_ = ~ \edge [56];
assign _096_ = \edge [57] & _095_;
assign _097_ = _094_ | _096_;
assign _098_ = ~ \edge [58];
assign _099_ = \edge [59] & _098_;
assign _100_ = _097_ | _099_;
assign _101_ = ~ \edge [60];
assign _102_ = \edge [61] & _101_;
assign _103_ = _100_ | _102_;
assign _104_ = ~ \edge [62];
assign _105_ = \edge [63] & _104_;
assign _106_ = _103_ | _105_;
assign _107_ = ~ \edge [1];
assign _108_ = \edge [3] & _107_;
assign _109_ = 1'h0 | _108_;
assign _110_ = ~ \edge [5];
assign _111_ = \edge [7] & _110_;
assign _112_ = _109_ | _111_;
assign _113_ = ~ \edge [9];
assign _114_ = \edge [11] & _113_;
assign _115_ = _112_ | _114_;
assign _116_ = ~ \edge [13];
assign _117_ = \edge [15] & _116_;
assign _118_ = _115_ | _117_;
assign _119_ = ~ \edge [17];
assign _120_ = \edge [19] & _119_;
assign _121_ = _118_ | _120_;
assign _122_ = ~ \edge [21];
assign _123_ = \edge [23] & _122_;
assign _124_ = _121_ | _123_;
assign _125_ = ~ \edge [25];
assign _126_ = \edge [27] & _125_;
assign _127_ = _124_ | _126_;
assign _128_ = ~ \edge [29];
assign _129_ = \edge [31] & _128_;
assign _130_ = _127_ | _129_;
assign _131_ = ~ \edge [33];
assign _132_ = \edge [35] & _131_;
assign _133_ = _130_ | _132_;
assign _134_ = ~ \edge [37];
assign _135_ = \edge [39] & _134_;
assign _136_ = _133_ | _135_;
assign _137_ = ~ \edge [41];
assign _138_ = \edge [43] & _137_;
assign _139_ = _136_ | _138_;
assign _140_ = ~ \edge [45];
assign _141_ = \edge [47] & _140_;
assign _142_ = _139_ | _141_;
assign _143_ = ~ \edge [49];
assign _144_ = \edge [51] & _143_;
assign _145_ = _142_ | _144_;
assign _146_ = ~ \edge [53];
assign _147_ = \edge [55] & _146_;
assign _148_ = _145_ | _147_;
assign _149_ = ~ \edge [57];
assign _150_ = \edge [59] & _149_;
assign _151_ = _148_ | _150_;
assign _152_ = ~ \edge [61];
assign _153_ = \edge [63] & _152_;
assign _154_ = _151_ | _153_;
assign _155_ = ~ \edge [3];
assign _156_ = \edge [7] & _155_;
assign _157_ = 1'h0 | _156_;
assign _158_ = ~ \edge [11];
assign _159_ = \edge [15] & _158_;
assign _160_ = _157_ | _159_;
assign _161_ = ~ \edge [19];
assign _162_ = \edge [23] & _161_;
assign _163_ = _160_ | _162_;
assign _164_ = ~ \edge [27];
assign _165_ = \edge [31] & _164_;
assign _166_ = _163_ | _165_;
assign _167_ = ~ \edge [35];
assign _168_ = \edge [39] & _167_;
assign _169_ = _166_ | _168_;
assign _170_ = ~ \edge [43];
assign _171_ = \edge [47] & _170_;
assign _172_ = _169_ | _171_;
assign _173_ = ~ \edge [51];
assign _174_ = \edge [55] & _173_;
assign _175_ = _172_ | _174_;
assign _176_ = ~ \edge [59];
assign _177_ = \edge [63] & _176_;
assign _178_ = _175_ | _177_;
assign _179_ = ~ \edge [7];
assign _180_ = \edge [15] & _179_;
assign _181_ = 1'h0 | _180_;
assign _182_ = ~ \edge [23];
assign _183_ = \edge [31] & _182_;
assign _184_ = _181_ | _183_;
assign _185_ = ~ \edge [39];
assign _186_ = \edge [47] & _185_;
assign _187_ = _184_ | _186_;
assign _188_ = ~ \edge [55];
assign _189_ = \edge [63] & _188_;
assign _190_ = _187_ | _189_;
assign _191_ = ~ \edge [15];
assign _192_ = \edge [31] & _191_;
assign _193_ = 1'h0 | _192_;
assign _194_ = ~ \edge [47];
assign _195_ = \edge [63] & _194_;
assign _196_ = _193_ | _195_;
assign _197_ = ~ \edge [31];
assign _198_ = \edge [63] & _197_;
assign _199_ = 1'h0 | _198_;
assign _200_ = sum_r[63:0] & inp_r;
assign _201_ = | onehot[1];
assign _202_ = 1'h0 | _201_;
assign _203_ = | onehot[3];
assign _204_ = _202_ | _203_;
assign _205_ = | onehot[5];
assign _206_ = _204_ | _205_;
assign _207_ = | onehot[7];
assign _208_ = _206_ | _207_;
assign _209_ = | onehot[9];
assign _210_ = _208_ | _209_;
assign _211_ = | onehot[11];
assign _212_ = _210_ | _211_;
assign _213_ = | onehot[13];
assign _214_ = _212_ | _213_;
assign _215_ = | onehot[15];
assign _216_ = _214_ | _215_;
assign _217_ = | onehot[17];
assign _218_ = _216_ | _217_;
assign _219_ = | onehot[19];
assign _220_ = _218_ | _219_;
assign _221_ = | onehot[21];
assign _222_ = _220_ | _221_;
assign _223_ = | onehot[23];
assign _224_ = _222_ | _223_;
assign _225_ = | onehot[25];
assign _226_ = _224_ | _225_;
assign _227_ = | onehot[27];
assign _228_ = _226_ | _227_;
assign _229_ = | onehot[29];
assign _230_ = _228_ | _229_;
assign _231_ = | onehot[31];
assign _232_ = _230_ | _231_;
assign _233_ = | onehot[33];
assign _234_ = _232_ | _233_;
assign _235_ = | onehot[35];
assign _236_ = _234_ | _235_;
assign _237_ = | onehot[37];
assign _238_ = _236_ | _237_;
assign _239_ = | onehot[39];
assign _240_ = _238_ | _239_;
assign _241_ = | onehot[41];
assign _242_ = _240_ | _241_;
assign _243_ = | onehot[43];
assign _244_ = _242_ | _243_;
assign _245_ = | onehot[45];
assign _246_ = _244_ | _245_;
assign _247_ = | onehot[47];
assign _248_ = _246_ | _247_;
assign _249_ = | onehot[49];
assign _250_ = _248_ | _249_;
assign _251_ = | onehot[51];
assign _252_ = _250_ | _251_;
assign _253_ = | onehot[53];
assign _254_ = _252_ | _253_;
assign _255_ = | onehot[55];
assign _256_ = _254_ | _255_;
assign _257_ = | onehot[57];
assign _258_ = _256_ | _257_;
assign _259_ = | onehot[59];
assign _260_ = _258_ | _259_;
assign _261_ = | onehot[61];
assign _262_ = _260_ | _261_;
assign _263_ = | onehot[63];
assign _264_ = _262_ | _263_;
assign _265_ = | onehot[3:2];
assign _266_ = 1'h0 | _265_;
assign _267_ = | onehot[7:6];
assign _268_ = _266_ | _267_;
assign _269_ = | onehot[11:10];
assign _270_ = _268_ | _269_;
assign _271_ = | onehot[15:14];
assign _272_ = _270_ | _271_;
assign _273_ = | onehot[19:18];
assign _274_ = _272_ | _273_;
assign _275_ = | onehot[23:22];
assign _276_ = _274_ | _275_;
assign _277_ = | onehot[27:26];
assign _278_ = _276_ | _277_;
assign _279_ = | onehot[31:30];
assign _280_ = _278_ | _279_;
assign _281_ = | onehot[35:34];
assign _282_ = _280_ | _281_;
assign _283_ = | onehot[39:38];
assign _284_ = _282_ | _283_;
assign _285_ = | onehot[43:42];
assign _286_ = _284_ | _285_;
assign _287_ = | onehot[47:46];
assign _288_ = _286_ | _287_;
assign _289_ = | onehot[51:50];
assign _290_ = _288_ | _289_;
assign _291_ = | onehot[55:54];
assign _292_ = _290_ | _291_;
assign _293_ = | onehot[59:58];
assign _294_ = _292_ | _293_;
assign _295_ = | onehot[63:62];
assign _296_ = _294_ | _295_;
assign _297_ = | onehot[7:4];
assign _298_ = 1'h0 | _297_;
assign _299_ = | onehot[15:12];
assign _300_ = _298_ | _299_;
assign _301_ = | onehot[23:20];
assign _302_ = _300_ | _301_;
assign _303_ = | onehot[31:28];
assign _304_ = _302_ | _303_;
assign _305_ = | onehot[39:36];
assign _306_ = _304_ | _305_;
assign _307_ = | onehot[47:44];
assign _308_ = _306_ | _307_;
assign _309_ = | onehot[55:52];
assign _310_ = _308_ | _309_;
assign _311_ = | onehot[63:60];
assign _312_ = _310_ | _311_;
assign _313_ = | onehot[15:8];
assign _314_ = 1'h0 | _313_;
assign _315_ = | onehot[31:24];
assign _316_ = _314_ | _315_;
assign _317_ = | onehot[47:40];
assign _318_ = _316_ | _317_;
assign _319_ = | onehot[63:56];
assign _320_ = _318_ | _319_;
assign _321_ = | onehot[31:16];
assign _322_ = 1'h0 | _321_;
assign _323_ = | onehot[63:48];
assign _324_ = _322_ | _323_;
assign _325_ = | onehot[63:32];
assign _326_ = 1'h0 | _325_;
always @(posedge clk)
_327_ <= datalen;
always @(posedge clk)
_328_ <= do_popcnt;
always @(posedge clk)
_329_ <= pc8;
assign _330_ = { 1'h0, rs[0] } + { 1'h0, rs[1] };
assign _331_ = { 1'h0, rs[2] } + { 1'h0, rs[3] };
assign _332_ = { 1'h0, rs[4] } + { 1'h0, rs[5] };
assign _333_ = { 1'h0, rs[6] } + { 1'h0, rs[7] };
assign _334_ = { 1'h0, rs[8] } + { 1'h0, rs[9] };
assign _335_ = { 1'h0, rs[10] } + { 1'h0, rs[11] };
assign _336_ = { 1'h0, rs[12] } + { 1'h0, rs[13] };
assign _337_ = { 1'h0, rs[14] } + { 1'h0, rs[15] };
assign _338_ = { 1'h0, rs[16] } + { 1'h0, rs[17] };
assign _339_ = { 1'h0, rs[18] } + { 1'h0, rs[19] };
assign _340_ = { 1'h0, rs[20] } + { 1'h0, rs[21] };
assign _341_ = { 1'h0, rs[22] } + { 1'h0, rs[23] };
assign _342_ = { 1'h0, rs[24] } + { 1'h0, rs[25] };
assign _343_ = { 1'h0, rs[26] } + { 1'h0, rs[27] };
assign _344_ = { 1'h0, rs[28] } + { 1'h0, rs[29] };
assign _345_ = { 1'h0, rs[30] } + { 1'h0, rs[31] };
assign _346_ = { 1'h0, rs[32] } + { 1'h0, rs[33] };
assign _347_ = { 1'h0, rs[34] } + { 1'h0, rs[35] };
assign _348_ = { 1'h0, rs[36] } + { 1'h0, rs[37] };
assign _349_ = { 1'h0, rs[38] } + { 1'h0, rs[39] };
assign _350_ = { 1'h0, rs[40] } + { 1'h0, rs[41] };
assign _351_ = { 1'h0, rs[42] } + { 1'h0, rs[43] };
assign _352_ = { 1'h0, rs[44] } + { 1'h0, rs[45] };
assign _353_ = { 1'h0, rs[46] } + { 1'h0, rs[47] };
assign _354_ = { 1'h0, rs[48] } + { 1'h0, rs[49] };
assign _355_ = { 1'h0, rs[50] } + { 1'h0, rs[51] };
assign _356_ = { 1'h0, rs[52] } + { 1'h0, rs[53] };
assign _357_ = { 1'h0, rs[54] } + { 1'h0, rs[55] };
assign _358_ = { 1'h0, rs[56] } + { 1'h0, rs[57] };
assign _359_ = { 1'h0, rs[58] } + { 1'h0, rs[59] };
assign _360_ = { 1'h0, rs[60] } + { 1'h0, rs[61] };
assign _361_ = { 1'h0, rs[62] } + { 1'h0, rs[63] };
assign _362_ = { 1'h0, pc2[63:62] } + { 1'h0, pc2[61:60] };
assign _363_ = { 1'h0, pc2[59:58] } + { 1'h0, pc2[57:56] };
assign _364_ = { 1'h0, pc2[55:54] } + { 1'h0, pc2[53:52] };
assign _365_ = { 1'h0, pc2[51:50] } + { 1'h0, pc2[49:48] };
assign _366_ = { 1'h0, pc2[47:46] } + { 1'h0, pc2[45:44] };
assign _367_ = { 1'h0, pc2[43:42] } + { 1'h0, pc2[41:40] };
assign _368_ = { 1'h0, pc2[39:38] } + { 1'h0, pc2[37:36] };
assign _369_ = { 1'h0, pc2[35:34] } + { 1'h0, pc2[33:32] };
assign _370_ = { 1'h0, pc2[31:30] } + { 1'h0, pc2[29:28] };
assign _371_ = { 1'h0, pc2[27:26] } + { 1'h0, pc2[25:24] };
assign _372_ = { 1'h0, pc2[23:22] } + { 1'h0, pc2[21:20] };
assign _373_ = { 1'h0, pc2[19:18] } + { 1'h0, pc2[17:16] };
assign _374_ = { 1'h0, pc2[15:14] } + { 1'h0, pc2[13:12] };
assign _375_ = { 1'h0, pc2[11:10] } + { 1'h0, pc2[9:8] };
assign _376_ = { 1'h0, pc2[7:6] } + { 1'h0, pc2[5:4] };
assign _377_ = { 1'h0, pc2[3:2] } + { 1'h0, pc2[1:0] };
assign _378_ = { 1'h0, pc4[47:45] } + { 1'h0, pc4[44:42] };
assign _379_ = { 1'h0, pc4[41:39] } + { 1'h0, pc4[38:36] };
assign _380_ = { 1'h0, pc4[35:33] } + { 1'h0, pc4[32:30] };
assign _381_ = { 1'h0, pc4[29:27] } + { 1'h0, pc4[26:24] };
assign _382_ = { 1'h0, pc4[23:21] } + { 1'h0, pc4[20:18] };
assign _383_ = { 1'h0, pc4[17:15] } + { 1'h0, pc4[14:12] };
assign _384_ = { 1'h0, pc4[11:9] } + { 1'h0, pc4[8:6] };
assign _385_ = { 1'h0, pc4[5:3] } + { 1'h0, pc4[2:0] };
assign _386_ = { 2'h0, pc8_r[31:28] } + { 2'h0, pc8_r[27:24] };
assign _387_ = _386_ + { 2'h0, pc8_r[23:20] };
assign _388_ = _387_ + { 2'h0, pc8_r[19:16] };
assign _389_ = { 2'h0, pc8_r[15:12] } + { 2'h0, pc8_r[11:8] };
assign _390_ = _389_ + { 2'h0, pc8_r[7:4] };
assign _391_ = _390_ + { 2'h0, pc8_r[3:0] };
assign _392_ = dlen_r[3:2] == 2'h0;
assign _393_ = ~ dlen_r[3];
assign _394_ = { 1'h0, pc32[11:6] } + { 1'h0, pc32[5:0] };
assign _395_ = _393_ ? pc32[11:6] : _394_[5:0];
assign _396_ = _393_ ? 1'h0 : _394_[6];
assign _397_ = _393_ ? pc32[5:0] : 6'h00;
assign _398_ = _392_ ? pc8_r[31:28] : _395_[3:0];
assign _399_ = _392_ ? 3'h0 : { _396_, _395_[5:4] };
assign _400_ = _392_ ? pc8_r[27:24] : 4'h0;
assign _401_ = _392_ ? pc8_r[23:20] : 4'h0;
assign _402_ = _392_ ? pc8_r[19:16] : 4'h0;
assign _403_ = _392_ ? pc8_r[15:12] : _397_[3:0];
assign _404_ = _392_ ? 2'h0 : _397_[5:4];
assign _405_ = _392_ ? pc8_r[11:8] : 4'h0;
assign _406_ = _392_ ? pc8_r[7:4] : 4'h0;
assign _407_ = _392_ ? pc8_r[3:0] : 4'h0;
assign _408_ = ~ pcnt_r;
assign _409_ = _408_ ? cntz : popcnt;
assign inp = _007_;
assign inp_r = _000_;
assign sum = _009_;
assign sum_r = _001_;
assign onehot = _200_;
assign \edge = _010_;
assign bitnum = { _199_, _196_, _190_, _178_, _296_, _264_ };
assign cntz = { 57'h000000000000000, sum_r[64], bitnum };
assign dlen_r = _327_;
assign pcnt_r = _328_;
assign pc2 = { _330_, _331_, _332_, _333_, _334_, _335_, _336_, _337_, _338_, _339_, _340_, _341_, _342_, _343_, _344_, _345_, _346_, _347_, _348_, _349_, _350_, _351_, _352_, _353_, _354_, _355_, _356_, _357_, _358_, _359_, _360_, _361_ };
assign pc4 = { _362_, _363_, _364_, _365_, _366_, _367_, _368_, _369_, _370_, _371_, _372_, _373_, _374_, _375_, _376_, _377_ };
assign pc8 = { _378_, _379_, _380_, _381_, _382_, _383_, _384_, _385_ };
assign pc8_r = _329_;
assign pc32 = { _388_, _391_ };
assign popcnt = { 4'h0, _407_, 4'h0, _406_, 4'h0, _405_, 2'h0, _404_, _403_, 4'h0, _402_, 4'h0, _401_, 4'h0, _400_, 1'h0, _399_, _398_ };
assign result = _409_;
endmodule |
module pmu(clk, rst, \p_in.mfspr , \p_in.mtspr , \p_in.spr_num , \p_in.spr_val , \p_in.tbbits , \p_in.pmm_msr , \p_in.pr_msr , \p_in.run , \p_in.nia , \p_in.addr , \p_in.addr_v , \p_in.occur , \p_out.spr_val , \p_out.intr );
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire [63:0] _015_;
wire _016_;
wire _017_;
wire [31:0] _018_;
wire [31:0] _019_;
wire [31:0] _020_;
wire _021_;
wire _022_;
wire [31:0] _023_;
wire [31:0] _024_;
wire [31:0] _025_;
wire _026_;
wire _027_;
wire [31:0] _028_;
wire [31:0] _029_;
wire [31:0] _030_;
wire _031_;
wire _032_;
wire [31:0] _033_;
wire [31:0] _034_;
wire [31:0] _035_;
wire _036_;
wire _037_;
wire [31:0] _038_;
wire [31:0] _039_;
wire [31:0] _040_;
wire _041_;
wire _042_;
wire [31:0] _043_;
wire [31:0] _044_;
wire [31:0] _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire [6:0] _058_;
wire _059_;
wire [2:0] _060_;
wire _061_;
wire _062_;
wire _063_;
wire [11:0] _064_;
wire _065_;
wire [3:0] _066_;
wire _067_;
wire _068_;
wire _069_;
wire [63:0] _070_;
wire _071_;
wire _072_;
wire [63:0] _073_;
wire _074_;
wire _075_;
wire [63:0] _076_;
wire _077_;
wire _078_;
wire [63:0] _079_;
wire [63:0] _080_;
wire _081_;
wire _082_;
wire [63:0] _083_;
wire [63:0] _084_;
wire _085_;
wire _086_;
wire [63:0] _087_;
wire [63:0] _088_;
wire [191:0] _089_;
wire [31:0] _090_;
wire [63:0] _091_;
wire [63:0] _092_;
wire [63:0] _093_;
wire [63:0] _094_;
wire [63:0] _095_;
wire [63:0] _096_;
reg [191:0] _097_;
reg [31:0] _098_;
reg [63:0] _099_;
reg [63:0] _100_;
reg [63:0] _101_;
reg [63:0] _102_;
reg [63:0] _103_;
reg [63:0] _104_;
reg [3:0] _105_;
wire [3:0] _106_;
wire [3:0] _107_;
wire [31:0] _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire [2:0] _190_;
wire _191_;
wire [1:0] _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire [1:0] _254_;
wire _255_;
wire _256_;
input clk;
wire clk;
wire doalert;
wire doevent;
wire [5:0] doinc;
wire [31:0] mmcr0;
wire [63:0] mmcr1;
wire [63:0] mmcr2;
wire [63:0] mmcra;
input [63:0] \p_in.addr ;
wire [63:0] \p_in.addr ;
input \p_in.addr_v ;
wire \p_in.addr_v ;
input \p_in.mfspr ;
wire \p_in.mfspr ;
input \p_in.mtspr ;
wire \p_in.mtspr ;
input [63:0] \p_in.nia ;
wire [63:0] \p_in.nia ;
input [20:0] \p_in.occur ;
wire [20:0] \p_in.occur ;
input \p_in.pmm_msr ;
wire \p_in.pmm_msr ;
input \p_in.pr_msr ;
wire \p_in.pr_msr ;
input \p_in.run ;
wire \p_in.run ;
input [4:0] \p_in.spr_num ;
wire [4:0] \p_in.spr_num ;
input [63:0] \p_in.spr_val ;
wire [63:0] \p_in.spr_val ;
input [3:0] \p_in.tbbits ;
wire [3:0] \p_in.tbbits ;
output \p_out.intr ;
wire \p_out.intr ;
output [63:0] \p_out.spr_val ;
wire [63:0] \p_out.spr_val ;
wire [191:0] pmcs;
wire [3:0] prev_tb;
input rst;
wire rst;
wire [63:0] sdar;
wire [63:0] siar;
wire [63:0] sier;
assign _000_ = _108_[0] ? _107_[1] : _107_[0];
assign _001_ = _108_[0] ? _107_[3] : _107_[2];
assign _256_ = _108_[1] ? _001_ : _000_;
assign _002_ = \p_in.spr_num [3:0] == 4'h3;
assign _003_ = \p_in.spr_num [3:0] == 4'h4;
assign _004_ = \p_in.spr_num [3:0] == 4'h5;
assign _005_ = \p_in.spr_num [3:0] == 4'h6;
assign _006_ = \p_in.spr_num [3:0] == 4'h7;
assign _007_ = \p_in.spr_num [3:0] == 4'h8;
assign _008_ = \p_in.spr_num [3:0] == 4'hb;
assign _009_ = \p_in.spr_num [3:0] == 4'he;
assign _010_ = \p_in.spr_num [3:0] == 4'h1;
assign _011_ = \p_in.spr_num [3:0] == 4'h2;
assign _012_ = \p_in.spr_num [3:0] == 4'hc;
assign _013_ = \p_in.spr_num [3:0] == 4'hd;
assign _014_ = \p_in.spr_num [3:0] == 4'h0;
function [63:0] \33004 ;
input [63:0] a;
input [831:0] b;
input [12:0] s;
(* parallel_case *)
casez (s)
13'b????????????1:
\33004 = b[63:0];
13'b???????????1?:
\33004 = b[127:64];
13'b??????????1??:
\33004 = b[191:128];
13'b?????????1???:
\33004 = b[255:192];
13'b????????1????:
\33004 = b[319:256];
13'b???????1?????:
\33004 = b[383:320];
13'b??????1??????:
\33004 = b[447:384];
13'b?????1???????:
\33004 = b[511:448];
13'b????1????????:
\33004 = b[575:512];
13'b???1?????????:
\33004 = b[639:576];
13'b??1??????????:
\33004 = b[703:640];
13'b?1???????????:
\33004 = b[767:704];
13'b1????????????:
\33004 = b[831:768];
default:
\33004 = a;
endcase
endfunction
assign _015_ = \33004 (64'h0000000000000000, { sier, sdar, siar, mmcra, mmcr2, mmcr1, 32'h00000000, mmcr0, 32'h00000000, pmcs[31:0], 32'h00000000, pmcs[63:32], 32'h00000000, pmcs[95:64], 32'h00000000, pmcs[127:96], 32'h00000000, pmcs[159:128], 32'h00000000, pmcs[191:160] }, { _014_, _013_, _012_, _011_, _010_, _009_, _008_, _007_, _006_, _005_, _004_, _003_, _002_ });
assign _016_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd3;
assign _017_ = \p_in.mtspr & _016_;
assign _018_ = pmcs[191:160] + 32'd1;
assign _019_ = doinc[5] ? _018_ : pmcs[191:160];
assign _020_ = _017_ ? \p_in.spr_val [31:0] : _019_;
assign _021_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd4;
assign _022_ = \p_in.mtspr & _021_;
assign _023_ = pmcs[159:128] + 32'd1;
assign _024_ = doinc[4] ? _023_ : pmcs[159:128];
assign _025_ = _022_ ? \p_in.spr_val [31:0] : _024_;
assign _026_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd5;
assign _027_ = \p_in.mtspr & _026_;
assign _028_ = pmcs[127:96] + 32'd1;
assign _029_ = doinc[3] ? _028_ : pmcs[127:96];
assign _030_ = _027_ ? \p_in.spr_val [31:0] : _029_;
assign _031_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd6;
assign _032_ = \p_in.mtspr & _031_;
assign _033_ = pmcs[95:64] + 32'd1;
assign _034_ = doinc[2] ? _033_ : pmcs[95:64];
assign _035_ = _032_ ? \p_in.spr_val [31:0] : _034_;
assign _036_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd7;
assign _037_ = \p_in.mtspr & _036_;
assign _038_ = pmcs[63:32] + 32'd1;
assign _039_ = doinc[1] ? _038_ : pmcs[63:32];
assign _040_ = _037_ ? \p_in.spr_val [31:0] : _039_;
assign _041_ = { 28'h0000000, \p_in.spr_num [3:0] } == 32'd8;
assign _042_ = \p_in.mtspr & _041_;
assign _043_ = pmcs[31:0] + 32'd1;
assign _044_ = doinc[0] ? _043_ : pmcs[31:0];
assign _045_ = _042_ ? \p_in.spr_val [31:0] : _044_;
assign _046_ = \p_in.spr_num [3:0] == 4'hb;
assign _047_ = \p_in.mtspr & _046_;
assign _048_ = doalert ? 1'h1 : mmcr0[7];
assign _049_ = doalert ? 1'h0 : mmcr0[11];
assign _050_ = doalert ? 1'h0 : mmcr0[26];
assign _051_ = doevent & mmcr0[25];
assign _052_ = ~ mmcr0[13];
assign _053_ = _051_ & _052_;
assign _054_ = _053_ ? 1'h1 : mmcr0[31];
assign _055_ = doevent | pmcs[191];
assign _056_ = _055_ & mmcr0[13];
assign _057_ = _056_ ? 1'h0 : mmcr0[13];
assign _058_ = _047_ ? \p_in.spr_val [6:0] : mmcr0[6:0];
assign _059_ = _047_ ? \p_in.spr_val [7] : _048_;
assign _060_ = _047_ ? \p_in.spr_val [10:8] : mmcr0[10:8];
assign _061_ = _047_ ? \p_in.spr_val [11] : _049_;
assign _062_ = _047_ ? \p_in.spr_val [12] : mmcr0[12];
assign _063_ = _047_ ? \p_in.spr_val [13] : _057_;
assign _064_ = _047_ ? { \p_in.spr_val [25:22], 2'h0, \p_in.spr_val [19:14] } : mmcr0[25:14];
assign _065_ = _047_ ? \p_in.spr_val [26] : _050_;
assign _066_ = _047_ ? \p_in.spr_val [30:27] : mmcr0[30:27];
assign _067_ = _047_ ? \p_in.spr_val [31] : _054_;
assign _068_ = \p_in.spr_num [3:0] == 4'he;
assign _069_ = \p_in.mtspr & _068_;
assign _070_ = _069_ ? \p_in.spr_val : mmcr1;
assign _071_ = \p_in.spr_num [3:0] == 4'h1;
assign _072_ = \p_in.mtspr & _071_;
assign _073_ = _072_ ? \p_in.spr_val : mmcr2;
assign _074_ = \p_in.spr_num [3:0] == 4'h2;
assign _075_ = \p_in.mtspr & _074_;
assign _076_ = _075_ ? { \p_in.spr_val [63:1], 1'h0 } : mmcra;
assign _077_ = \p_in.spr_num [3:0] == 4'hc;
assign _078_ = \p_in.mtspr & _077_;
assign _079_ = doalert ? \p_in.nia : siar;
assign _080_ = _078_ ? \p_in.spr_val : _079_;
assign _081_ = \p_in.spr_num [3:0] == 4'hd;
assign _082_ = \p_in.mtspr & _081_;
assign _083_ = doalert ? \p_in.addr : sdar;
assign _084_ = _082_ ? \p_in.spr_val : _083_;
assign _085_ = \p_in.spr_num [3:0] == 4'h0;
assign _086_ = \p_in.mtspr & _085_;
assign _087_ = doalert ? { 38'h0000000000, \p_in.pr_msr , 3'h1, \p_in.addr_v , 21'h000000 } : sier;
assign _088_ = _086_ ? \p_in.spr_val : _087_;
assign _089_ = rst ? pmcs : { _020_, _025_, _030_, _035_, _040_, _045_ };
assign _090_ = rst ? 32'd2147483648 : { _067_, _066_, _065_, _064_, _063_, _062_, _061_, _060_, _059_, _058_ };
assign _091_ = rst ? mmcr1 : _070_;
assign _092_ = rst ? mmcr2 : _073_;
assign _093_ = rst ? mmcra : _076_;
assign _094_ = rst ? siar : _080_;
assign _095_ = rst ? sdar : _084_;
assign _096_ = rst ? sier : _088_;
always @(posedge clk)
_097_ <= _089_;
always @(posedge clk)
_098_ <= _090_;
always @(posedge clk)
_099_ <= _091_;
always @(posedge clk)
_100_ <= _092_;
always @(posedge clk)
_101_ <= _093_;
always @(posedge clk)
_102_ <= _094_;
always @(posedge clk)
_103_ <= _095_;
always @(posedge clk)
_104_ <= _096_;
always @(posedge clk)
_105_ <= \p_in.tbbits ;
assign _106_ = ~ prev_tb;
assign _107_ = \p_in.tbbits & _106_;
assign _108_ = 32'd3 - { 30'h00000000, mmcr0[24:23] };
assign _109_ = _256_ & mmcr0[22];
assign _110_ = _109_ ? 1'h1 : 1'h0;
assign _111_ = mmcr0[15] & pmcs[191];
assign _112_ = _111_ ? 1'h1 : _110_;
assign _113_ = pmcs[159] | pmcs[127];
assign _114_ = _113_ | pmcs[95];
assign _115_ = mmcr0[14] & _114_;
assign _116_ = _115_ ? 1'h1 : _112_;
assign _117_ = mmcr0[19:18] != 2'h3;
assign _118_ = mmcr0[14] & _117_;
assign _119_ = pmcs[63] | pmcs[31];
assign _120_ = _118_ & _119_;
assign _121_ = _120_ ? 1'h1 : _116_;
assign _122_ = mmcr1[31:24] == 8'hf0;
assign _123_ = mmcr1[31:24] == 8'hf2;
assign _124_ = mmcr1[31:24] == 8'hfe;
assign _125_ = _123_ | _124_;
assign _126_ = mmcr1[31:24] == 8'hf4;
assign _127_ = mmcr1[31:24] == 8'hf6;
assign _128_ = mmcr1[31:24] == 8'hf8;
assign _129_ = mmcr1[31:24] == 8'hfa;
assign _130_ = mmcr1[31:24] == 8'hfc;
function [0:0] \33332 ;
input [0:0] a;
input [6:0] b;
input [6:0] s;
(* parallel_case *)
casez (s)
7'b??????1:
\33332 = b[0:0];
7'b?????1?:
\33332 = b[1:1];
7'b????1??:
\33332 = b[2:2];
7'b???1???:
\33332 = b[3:3];
7'b??1????:
\33332 = b[4:4];
7'b?1?????:
\33332 = b[5:5];
7'b1??????:
\33332 = b[6:6];
default:
\33332 = a;
endcase
endfunction
assign _131_ = \33332 (1'h0, { \p_in.occur [5], \p_in.run , \p_in.occur [0], \p_in.occur [10], \p_in.occur [4:3], 1'h1 }, { _130_, _129_, _128_, _127_, _126_, _125_, _122_ });
function [0:0] \33337 ;
input [0:0] a;
input [6:0] b;
input [6:0] s;
(* parallel_case *)
casez (s)
7'b??????1:
\33337 = b[0:0];
7'b?????1?:
\33337 = b[1:1];
7'b????1??:
\33337 = b[2:2];
7'b???1???:
\33337 = b[3:3];
7'b??1????:
\33337 = b[4:4];
7'b?1?????:
\33337 = b[5:5];
7'b1??????:
\33337 = b[6:6];
default:
\33337 = a;
endcase
endfunction
assign _132_ = \33337 (1'h0, 7'h01, { _130_, _129_, _128_, _127_, _126_, _125_, _122_ });
assign _133_ = mmcr1[23:16] == 8'hf0;
assign _134_ = mmcr1[23:16] == 8'hf2;
assign _135_ = mmcr1[23:16] == 8'hf4;
assign _136_ = mmcr1[23:16] == 8'hf6;
assign _137_ = mmcr1[23:16] == 8'hf8;
assign _138_ = mmcr1[23:16] == 8'hfa;
assign _139_ = mmcr1[23:16] == 8'hfc;
assign _140_ = mmcr1[23:16] == 8'hfe;
function [0:0] \33373 ;
input [0:0] a;
input [7:0] b;
input [7:0] s;
(* parallel_case *)
casez (s)
8'b???????1:
\33373 = b[0:0];
8'b??????1?:
\33373 = b[1:1];
8'b?????1??:
\33373 = b[2:2];
8'b????1???:
\33373 = b[3:3];
8'b???1????:
\33373 = b[4:4];
8'b??1?????:
\33373 = b[5:5];
8'b?1??????:
\33373 = b[6:6];
8'b1???????:
\33373 = b[7:7];
default:
\33373 = a;
endcase
endfunction
assign _141_ = \33373 (1'h0, { \p_in.occur [13:12], \p_in.occur [7], \p_in.occur [2], \p_in.occur [18], \p_in.run , \p_in.occur [1], \p_in.occur [6] }, { _140_, _139_, _138_, _137_, _136_, _135_, _134_, _133_ });
assign _142_ = mmcr1[15:8] == 8'hf0;
assign _143_ = mmcr1[15:8] == 8'hf2;
assign _144_ = \p_in.occur [3] & \p_in.run ;
assign _145_ = mmcr1[15:8] == 8'hf4;
assign _146_ = mmcr1[15:8] == 8'hf6;
assign _147_ = mmcr1[15:8] == 8'hf8;
assign _148_ = mmcr1[15:8] == 8'hfe;
function [0:0] \33402 ;
input [0:0] a;
input [5:0] b;
input [5:0] s;
(* parallel_case *)
casez (s)
6'b?????1:
\33402 = b[0:0];
6'b????1?:
\33402 = b[1:1];
6'b???1??:
\33402 = b[2:2];
6'b??1???:
\33402 = b[3:3];
6'b?1????:
\33402 = b[4:4];
6'b1?????:
\33402 = b[5:5];
default:
\33402 = a;
endcase
endfunction
assign _149_ = \33402 (1'h0, { \p_in.occur [17], _256_, \p_in.occur [15], _144_, \p_in.occur [1], \p_in.occur [16] }, { _148_, _147_, _146_, _145_, _143_, _142_ });
assign _150_ = mmcr1[7:0] == 8'hf0;
assign _151_ = mmcr1[7:0] == 8'hf2;
assign _152_ = mmcr1[7:0] == 8'hf4;
assign _153_ = mmcr1[7:0] == 8'hf6;
assign _154_ = mmcr1[7:0] == 8'hf8;
assign _155_ = \p_in.occur [3] & \p_in.run ;
assign _156_ = mmcr1[7:0] == 8'hfa;
assign _157_ = mmcr1[7:0] == 8'hfc;
assign _158_ = mmcr1[7:0] == 8'hfe;
function [0:0] \33440 ;
input [0:0] a;
input [7:0] b;
input [7:0] s;
(* parallel_case *)
casez (s)
8'b???????1:
\33440 = b[0:0];
8'b??????1?:
\33440 = b[1:1];
8'b?????1??:
\33440 = b[2:2];
8'b????1???:
\33440 = b[3:3];
8'b???1????:
\33440 = b[4:4];
8'b??1?????:
\33440 = b[5:5];
8'b?1??????:
\33440 = b[6:6];
8'b1???????:
\33440 = b[7:7];
default:
\33440 = a;
endcase
endfunction
assign _159_ = \33440 (1'h0, { \p_in.occur [19], \p_in.occur [11], _155_, \p_in.occur [9:8], \p_in.run , \p_in.occur [1], \p_in.occur [14] }, { _158_, _157_, _156_, _154_, _153_, _152_, _151_, _150_ });
assign _160_ = mmcr0[8] | \p_in.run ;
assign _161_ = _160_ & \p_in.occur [3];
assign _162_ = mmcr0[8] | \p_in.run ;
assign _163_ = ~ \p_in.pr_msr ;
assign _164_ = mmcr0[30] & _163_;
assign _165_ = mmcr0[31] | _164_;
assign _166_ = ~ mmcr0[12];
assign _167_ = mmcr0[29] & _166_;
assign _168_ = _167_ & \p_in.pr_msr ;
assign _169_ = _165_ | _168_;
assign _170_ = ~ mmcr0[29];
assign _171_ = _170_ & mmcr0[12];
assign _172_ = _171_ & \p_in.pr_msr ;
assign _173_ = _169_ | _172_;
assign _174_ = mmcr0[28] & \p_in.pmm_msr ;
assign _175_ = _173_ | _174_;
assign _176_ = ~ \p_in.pmm_msr ;
assign _177_ = mmcr0[27] & _176_;
assign _178_ = _175_ | _177_;
assign _179_ = _178_ | mmcr0[5];
assign _180_ = ~ \p_in.run ;
assign _181_ = mmcr0[1] & _180_;
assign _182_ = ~ _132_;
assign _183_ = _181_ & _182_;
assign _184_ = _179_ | _183_;
assign _185_ = _184_ ? 1'h0 : _131_;
assign _186_ = _178_ | mmcr0[5];
assign _187_ = ~ \p_in.run ;
assign _188_ = mmcr0[1] & _187_;
assign _189_ = _186_ | _188_;
assign _190_ = _189_ ? 3'h0 : { _141_, _149_, _159_ };
assign _191_ = _178_ | mmcr0[4];
assign _192_ = _191_ ? 2'h0 : { _161_, _162_ };
assign _193_ = ~ \p_in.pr_msr ;
assign _194_ = mmcr2[63] & _193_;
assign _195_ = mmcr2[62] & \p_in.pr_msr ;
assign _196_ = _194_ | _195_;
assign _197_ = mmcr2[60] & \p_in.pmm_msr ;
assign _198_ = _196_ | _197_;
assign _199_ = mmcr2[60] & \p_in.pmm_msr ;
assign _200_ = _198_ | _199_;
assign _201_ = _200_ ? 1'h0 : _185_;
assign _202_ = ~ \p_in.pr_msr ;
assign _203_ = mmcr2[54] & _202_;
assign _204_ = mmcr2[53] & \p_in.pr_msr ;
assign _205_ = _203_ | _204_;
assign _206_ = mmcr2[51] & \p_in.pmm_msr ;
assign _207_ = _205_ | _206_;
assign _208_ = mmcr2[51] & \p_in.pmm_msr ;
assign _209_ = _207_ | _208_;
assign _210_ = mmcr0[13] ? 1'h0 : _190_[2];
assign _211_ = _209_ ? 1'h0 : _210_;
assign _212_ = ~ \p_in.pr_msr ;
assign _213_ = mmcr2[45] & _212_;
assign _214_ = mmcr2[44] & \p_in.pr_msr ;
assign _215_ = _213_ | _214_;
assign _216_ = mmcr2[42] & \p_in.pmm_msr ;
assign _217_ = _215_ | _216_;
assign _218_ = mmcr2[42] & \p_in.pmm_msr ;
assign _219_ = _217_ | _218_;
assign _220_ = mmcr0[13] ? 1'h0 : _190_[1];
assign _221_ = _219_ ? 1'h0 : _220_;
assign _222_ = ~ \p_in.pr_msr ;
assign _223_ = mmcr2[36] & _222_;
assign _224_ = mmcr2[35] & \p_in.pr_msr ;
assign _225_ = _223_ | _224_;
assign _226_ = mmcr2[33] & \p_in.pmm_msr ;
assign _227_ = _225_ | _226_;
assign _228_ = mmcr2[33] & \p_in.pmm_msr ;
assign _229_ = _227_ | _228_;
assign _230_ = mmcr0[13] ? 1'h0 : _190_[0];
assign _231_ = _229_ ? 1'h0 : _230_;
assign _232_ = ~ \p_in.pr_msr ;
assign _233_ = mmcr2[27] & _232_;
assign _234_ = mmcr2[26] & \p_in.pr_msr ;
assign _235_ = _233_ | _234_;
assign _236_ = mmcr2[24] & \p_in.pmm_msr ;
assign _237_ = _235_ | _236_;
assign _238_ = mmcr2[24] & \p_in.pmm_msr ;
assign _239_ = _237_ | _238_;
assign _240_ = mmcr0[13] ? 1'h0 : _192_[1];
assign _241_ = _239_ ? 1'h0 : _240_;
assign _242_ = mmcr0[13] ? 1'h0 : _192_[0];
assign _243_ = ~ \p_in.pr_msr ;
assign _244_ = mmcr2[18] & _243_;
assign _245_ = mmcr2[17] & \p_in.pr_msr ;
assign _246_ = _244_ | _245_;
assign _247_ = mmcr2[15] & \p_in.pmm_msr ;
assign _248_ = _246_ | _247_;
assign _249_ = mmcr2[15] & \p_in.pmm_msr ;
assign _250_ = _248_ | _249_;
assign _251_ = _250_ ? 1'h0 : _242_;
assign _252_ = mmcr0[19:18] == 2'h3;
assign _253_ = \p_in.run & \p_in.occur [3];
assign _254_ = _252_ ? { _253_, \p_in.run } : { _241_, _251_ };
assign _255_ = _121_ & mmcr0[26];
assign pmcs = _097_;
assign mmcr0 = _098_;
assign mmcr1 = _099_;
assign mmcr2 = _100_;
assign mmcra = _101_;
assign siar = _102_;
assign sdar = _103_;
assign sier = _104_;
assign doinc = { _201_, _211_, _221_, _231_, _254_ };
assign doalert = _255_;
assign doevent = _121_;
assign prev_tb = _105_;
assign \p_out.spr_val = _015_;
assign \p_out.intr = mmcr0[7];
endmodule |
module cr_file_0_5ba93c9db0cff93f52b521d7420e43f6eda2784f(clk, \d_in.read , \w_in.write_cr_enable , \w_in.write_cr_mask , \w_in.write_cr_data , \w_in.write_xerc_enable , \w_in.write_xerc_data , sim_dump, \d_out.read_cr_data , \d_out.read_xerc_data , log_out);
wire [3:0] _00_;
wire [3:0] _01_;
wire [3:0] _02_;
wire [3:0] _03_;
wire [3:0] _04_;
wire [3:0] _05_;
wire [3:0] _06_;
wire [3:0] _07_;
wire [4:0] _08_;
wire [31:0] _09_;
reg [31:0] _10_ = 32'd0;
wire [4:0] _11_;
reg [4:0] _12_ = 5'h00;
input clk;
wire clk;
wire [31:0] crs;
wire [31:0] crs_updated;
input \d_in.read ;
wire \d_in.read ;
output [31:0] \d_out.read_cr_data ;
wire [31:0] \d_out.read_cr_data ;
output [4:0] \d_out.read_xerc_data ;
wire [4:0] \d_out.read_xerc_data ;
output [12:0] log_out;
wire [12:0] log_out;
input sim_dump;
wire sim_dump;
input [31:0] \w_in.write_cr_data ;
wire [31:0] \w_in.write_cr_data ;
input \w_in.write_cr_enable ;
wire \w_in.write_cr_enable ;
input [7:0] \w_in.write_cr_mask ;
wire [7:0] \w_in.write_cr_mask ;
input [4:0] \w_in.write_xerc_data ;
wire [4:0] \w_in.write_xerc_data ;
input \w_in.write_xerc_enable ;
wire \w_in.write_xerc_enable ;
wire [4:0] xerc;
wire [4:0] xerc_updated;
assign _00_ = \w_in.write_cr_mask [0] ? \w_in.write_cr_data [3:0] : crs[3:0];
assign _01_ = \w_in.write_cr_mask [1] ? \w_in.write_cr_data [7:4] : crs[7:4];
assign _02_ = \w_in.write_cr_mask [2] ? \w_in.write_cr_data [11:8] : crs[11:8];
assign _03_ = \w_in.write_cr_mask [3] ? \w_in.write_cr_data [15:12] : crs[15:12];
assign _04_ = \w_in.write_cr_mask [4] ? \w_in.write_cr_data [19:16] : crs[19:16];
assign _05_ = \w_in.write_cr_mask [5] ? \w_in.write_cr_data [23:20] : crs[23:20];
assign _06_ = \w_in.write_cr_mask [6] ? \w_in.write_cr_data [27:24] : crs[27:24];
assign _07_ = \w_in.write_cr_mask [7] ? \w_in.write_cr_data [31:28] : crs[31:28];
assign _08_ = \w_in.write_xerc_enable ? \w_in.write_xerc_data : xerc;
assign _09_ = \w_in.write_cr_enable ? crs_updated : crs;
always @(posedge clk)
_10_ <= _09_;
assign _11_ = \w_in.write_xerc_enable ? xerc_updated : xerc;
always @(posedge clk)
_12_ <= _11_;
assign crs = _10_;
assign crs_updated = { _07_, _06_, _05_, _04_, _03_, _02_, _01_, _00_ };
assign xerc = _12_;
assign xerc_updated = _08_;
assign \d_out.read_cr_data = crs_updated;
assign \d_out.read_xerc_data = xerc_updated;
assign log_out = 13'hzzzz;
endmodule |
module fetch1_1e2926114d55612f17be0ce20b92717fa98c0d5f(clk, rst, stall_in, flush_in, inval_btc, stop_in, alt_reset_in, \w_in.redirect , \w_in.virt_mode , \w_in.priv_mode , \w_in.big_endian , \w_in.mode_32bit , \w_in.redirect_nia , \w_in.br_nia , \w_in.br_last , \w_in.br_taken , \d_in.redirect , \d_in.redirect_nia , \i_out.req , \i_out.virt_mode , \i_out.priv_mode , \i_out.big_endian , \i_out.stop_mark , \i_out.predicted , \i_out.pred_ntaken , \i_out.nia , log_out);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire [2:0] _04_;
wire _05_;
wire [65:0] _06_;
wire [66:0] _07_;
wire _08_;
reg [70:0] _09_;
reg [67:0] _10_;
reg [42:0] _11_;
wire [63:0] _12_;
wire [31:0] _13_;
wire [31:0] _14_;
wire [63:0] _15_;
wire [31:0] _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire [1:0] _21_;
wire _22_;
wire _23_;
wire [63:0] _24_;
wire [2:0] _25_;
wire [1:0] _26_;
wire [63:0] _27_;
wire [2:0] _28_;
wire [2:0] _29_;
wire [1:0] _30_;
wire [63:0] _31_;
wire _32_;
wire [2:0] _33_;
wire [2:0] _34_;
wire [1:0] _35_;
wire [63:0] _36_;
wire _37_;
wire [2:0] _38_;
wire _39_;
wire _40_;
wire _41_;
wire _42_;
wire _43_;
wire _44_;
wire advance_nia;
input alt_reset_in;
wire alt_reset_in;
wire [114:0] btc_rd_data;
wire btc_rd_valid;
input clk;
wire clk;
input \d_in.redirect ;
wire \d_in.redirect ;
input [63:0] \d_in.redirect_nia ;
wire [63:0] \d_in.redirect_nia ;
input flush_in;
wire flush_in;
output \i_out.big_endian ;
wire \i_out.big_endian ;
output [63:0] \i_out.nia ;
wire [63:0] \i_out.nia ;
output \i_out.pred_ntaken ;
wire \i_out.pred_ntaken ;
output \i_out.predicted ;
wire \i_out.predicted ;
output \i_out.priv_mode ;
wire \i_out.priv_mode ;
output \i_out.req ;
wire \i_out.req ;
output \i_out.stop_mark ;
wire \i_out.stop_mark ;
output \i_out.virt_mode ;
wire \i_out.virt_mode ;
input inval_btc;
wire inval_btc;
wire [42:0] log_nia;
output [42:0] log_out;
wire [42:0] log_out;
wire [70:0] r;
wire [67:0] r_int;
wire [70:0] r_next;
wire [67:0] r_next_int;
input rst;
wire rst;
input stall_in;
wire stall_in;
input stop_in;
wire stop_in;
input \w_in.big_endian ;
wire \w_in.big_endian ;
input \w_in.br_last ;
wire \w_in.br_last ;
input [63:0] \w_in.br_nia ;
wire [63:0] \w_in.br_nia ;
input \w_in.br_taken ;
wire \w_in.br_taken ;
input \w_in.mode_32bit ;
wire \w_in.mode_32bit ;
input \w_in.priv_mode ;
wire \w_in.priv_mode ;
input \w_in.redirect ;
wire \w_in.redirect ;
input [63:0] \w_in.redirect_nia ;
wire [63:0] \w_in.redirect_nia ;
input \w_in.virt_mode ;
wire \w_in.virt_mode ;
assign _00_ = rst | \w_in.redirect ;
assign _01_ = _00_ | \d_in.redirect ;
assign _02_ = ~ stall_in;
assign _03_ = _01_ | _02_;
assign _04_ = _03_ ? r_next[3:1] : r[3:1];
assign _05_ = _03_ ? r_next_int[0] : r_int[0];
assign _06_ = advance_nia ? r_next[70:5] : r[70:5];
assign _07_ = advance_nia ? r_next_int[67:1] : r_int[67:1];
assign _08_ = ~ rst;
always @(posedge clk)
_09_ <= { _06_, stop_in, _04_, _08_ };
always @(posedge clk)
_10_ <= { _07_, _05_ };
always @(posedge clk)
_11_ <= { r[70], r[50:9] };
assign _12_ = alt_reset_in ? 64'hfffffffff0000000 : 64'h0000000000000000;
assign _13_ = \w_in.mode_32bit ? 32'd0 : \w_in.redirect_nia [63:32];
assign _14_ = r_int[0] ? 32'd0 : \d_in.redirect_nia [63:32];
assign _15_ = r[70:7] + 64'h0000000000000004;
assign _16_ = r_int[0] ? 32'd0 : _15_[63:32];
assign _17_ = btc_rd_valid & r_int[1];
assign _18_ = btc_rd_data[113:62] == { _16_, _15_[31:12] };
assign _19_ = _17_ & _18_;
assign _20_ = ~ btc_rd_data[114];
assign _21_ = _19_ ? { _20_, btc_rd_data[114] } : 2'h0;
assign _22_ = r_int[2] ? 1'h1 : 1'h0;
assign _23_ = r_int[2] ? 1'h0 : r_int[3];
assign _24_ = r_int[2] ? r_int[67:4] : { _16_, _15_[31:0] };
assign _25_ = r_int[2] ? 3'h0 : { _21_, 1'h1 };
assign _26_ = \d_in.redirect ? 2'h0 : { _23_, _22_ };
assign _27_ = \d_in.redirect ? { _14_, \d_in.redirect_nia [31:2], 2'h0 } : _24_;
assign _28_ = \d_in.redirect ? 3'h0 : _25_;
assign _29_ = \w_in.redirect ? { \w_in.big_endian , \w_in.priv_mode , \w_in.virt_mode } : r[3:1];
assign _30_ = \w_in.redirect ? 2'h0 : _26_;
assign _31_ = \w_in.redirect ? { _13_, \w_in.redirect_nia [31:2], 2'h0 } : _27_;
assign _32_ = \w_in.redirect ? \w_in.mode_32bit : r_int[0];
assign _33_ = \w_in.redirect ? 3'h0 : _28_;
assign _34_ = rst ? 3'h2 : _29_;
assign _35_ = rst ? 2'h0 : _30_;
assign _36_ = rst ? _12_ : _31_;
assign _37_ = rst ? 1'h0 : _32_;
assign _38_ = rst ? 3'h0 : _33_;
assign _39_ = rst | \w_in.redirect ;
assign _40_ = _39_ | \d_in.redirect ;
assign _41_ = ~ r[4];
assign _42_ = ~ stall_in;
assign _43_ = _41_ & _42_;
assign _44_ = _40_ | _43_;
assign r = _09_;
assign r_next = { _36_, _35_, r[4], _34_, r[0] };
assign r_int = _10_;
assign r_next_int = { btc_rd_data[61:0], 2'h0, _38_, _37_ };
assign advance_nia = _44_;
assign log_nia = _11_;
assign btc_rd_data = 115'h00000000000000000000000000000;
assign btc_rd_valid = 1'h0;
assign \i_out.req = r[0];
assign \i_out.virt_mode = r[1];
assign \i_out.priv_mode = r[2];
assign \i_out.big_endian = r[3];
assign \i_out.stop_mark = r[4];
assign \i_out.predicted = r[5];
assign \i_out.pred_ntaken = r[6];
assign \i_out.nia = r[70:7];
assign log_out = log_nia;
endmodule |
module control_3_bf8b4530d8d246dd74ac53a13471bba17941dff7(clk, rst, \complete_in.tag , \complete_in.valid , valid_in, repeated, flush_in, busy_in, deferred, sgl_pipe_in, stop_mark_in, gpr_write_valid_in, gpr_write_in, gpr_a_read_valid_in, gpr_a_read_in, gpr_b_read_valid_in, gpr_b_read_in, gpr_c_read_valid_in, gpr_c_read_in, \execute_next_tag.tag , \execute_next_tag.valid , \execute_next_cr_tag.tag , \execute_next_cr_tag.valid , cr_read_in, cr_write_in, valid_out, stall_out, stopped_out, gpr_bypass_a, gpr_bypass_b, gpr_bypass_c, cr_bypass, \instr_tag_out.tag , \instr_tag_out.valid );
wire [9:0] _000_;
wire [9:0] _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire [9:0] _012_;
wire _013_;
wire [7:0] _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire [9:0] _026_;
wire _027_;
wire [7:0] _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire [9:0] _040_;
wire _041_;
wire [7:0] _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire [9:0] _054_;
wire _055_;
wire [7:0] _056_;
wire _057_;
wire [1:0] _058_;
wire [1:0] _059_;
wire [1:0] _060_;
reg [5:0] _061_ = 6'h00;
reg [39:0] _062_;
reg [1:0] _063_;
reg [1:0] _064_;
wire _065_;
wire _066_;
wire _067_;
wire [2:0] _068_;
wire _069_;
wire _070_;
wire _071_;
wire [2:0] _072_;
wire _073_;
wire _074_;
wire _075_;
wire [2:0] _076_;
wire _077_;
wire _078_;
wire _079_;
wire [2:0] _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire [1:0] _089_;
wire [1:0] _090_;
wire [1:0] _091_;
wire [1:0] _092_;
wire _093_;
wire _094_;
wire _095_;
wire [2:0] _096_;
wire _097_;
wire _098_;
wire _099_;
wire [2:0] _100_;
wire _101_;
wire _102_;
wire _103_;
wire [2:0] _104_;
wire _105_;
wire _106_;
wire _107_;
wire [2:0] _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire [1:0] _117_;
wire [1:0] _118_;
wire [1:0] _119_;
wire [1:0] _120_;
wire _121_;
wire _122_;
wire _123_;
wire [2:0] _124_;
wire _125_;
wire _126_;
wire _127_;
wire [2:0] _128_;
wire _129_;
wire _130_;
wire _131_;
wire [2:0] _132_;
wire _133_;
wire _134_;
wire _135_;
wire [2:0] _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire [1:0] _145_;
wire [1:0] _146_;
wire [1:0] _147_;
wire [1:0] _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire [31:0] _174_;
wire [1:0] _175_;
wire [1:0] _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire [31:0] _191_;
wire [3:0] _192_;
wire [3:0] _193_;
wire _194_;
wire _195_;
wire _196_;
wire [5:0] _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire [1:0] _203_;
wire _204_;
wire _205_;
wire [1:0] _206_;
wire [1:0] _207_;
wire _208_;
wire [1:0] _209_;
wire [1:0] _210_;
wire _211_;
wire _212_;
wire _213_;
wire [1:0] _214_;
wire [1:0] _215_;
wire _216_;
wire _217_;
wire _218_;
wire [3:0] _219_;
wire _220_;
wire [1:0] _221_;
wire _222_;
wire _223_;
wire [1:0] _224_;
wire _225_;
wire _226_;
wire _227_;
wire [1:0] _228_;
wire [1:0] _229_;
wire _230_;
wire _231_;
wire [1:0] _232_;
wire [3:0] _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire [31:0] _240_;
wire [3:0] _241_;
wire _242_;
wire [9:0] _243_;
input busy_in;
wire busy_in;
input clk;
wire clk;
input [1:0] \complete_in.tag ;
wire [1:0] \complete_in.tag ;
input \complete_in.valid ;
wire \complete_in.valid ;
output cr_bypass;
wire cr_bypass;
input cr_read_in;
wire cr_read_in;
wire cr_tag_stall;
input cr_write_in;
wire cr_write_in;
wire cr_write_valid;
wire [1:0] curr_cr_tag;
wire [1:0] curr_tag;
input deferred;
wire deferred;
input [1:0] \execute_next_cr_tag.tag ;
wire [1:0] \execute_next_cr_tag.tag ;
input \execute_next_cr_tag.valid ;
wire \execute_next_cr_tag.valid ;
input [1:0] \execute_next_tag.tag ;
wire [1:0] \execute_next_tag.tag ;
input \execute_next_tag.valid ;
wire \execute_next_tag.valid ;
input flush_in;
wire flush_in;
input [6:0] gpr_a_read_in;
wire [6:0] gpr_a_read_in;
input gpr_a_read_valid_in;
wire gpr_a_read_valid_in;
input [6:0] gpr_b_read_in;
wire [6:0] gpr_b_read_in;
input gpr_b_read_valid_in;
wire gpr_b_read_valid_in;
output gpr_bypass_a;
wire gpr_bypass_a;
output gpr_bypass_b;
wire gpr_bypass_b;
output gpr_bypass_c;
wire gpr_bypass_c;
input [6:0] gpr_c_read_in;
wire [6:0] gpr_c_read_in;
input gpr_c_read_valid_in;
wire gpr_c_read_valid_in;
wire gpr_tag_stall;
input [6:0] gpr_write_in;
wire [6:0] gpr_write_in;
wire gpr_write_valid;
input gpr_write_valid_in;
wire gpr_write_valid_in;
wire [2:0] instr_tag;
output [1:0] \instr_tag_out.tag ;
wire [1:0] \instr_tag_out.tag ;
output \instr_tag_out.valid ;
wire \instr_tag_out.valid ;
wire [1:0] next_tag;
wire [5:0] r_int;
input repeated;
wire repeated;
wire [5:0] rin_int;
input rst;
wire rst;
input sgl_pipe_in;
wire sgl_pipe_in;
output stall_out;
wire stall_out;
input stop_mark_in;
wire stop_mark_in;
output stopped_out;
wire stopped_out;
wire [39:0] tag_regs;
input valid_in;
wire valid_in;
output valid_out;
wire valid_out;
assign _000_ = _176_[0] ? tag_regs[19:10] : tag_regs[9:0];
assign _001_ = _176_[0] ? tag_regs[39:30] : tag_regs[29:20];
assign _243_ = _176_[1] ? _001_ : _000_;
assign _002_ = rst | flush_in;
assign _003_ = 32'd0 == { 30'h00000000, \complete_in.tag };
assign _004_ = \complete_in.valid & _003_;
assign _005_ = _004_ ? 1'h0 : tag_regs[30];
assign _006_ = _004_ ? 1'h0 : tag_regs[39];
assign _007_ = tag_regs[37:31] == gpr_write_in;
assign _008_ = gpr_write_valid & _007_;
assign _009_ = _008_ ? 1'h0 : tag_regs[38];
assign _010_ = 32'd0 == { 30'h00000000, instr_tag[1:0] };
assign _011_ = instr_tag[2] & _010_;
assign _012_ = _011_ ? { cr_write_valid, gpr_write_valid, gpr_write_in, gpr_write_valid } : { _006_, _009_, tag_regs[37:31], _005_ };
assign _013_ = _002_ ? 1'h0 : _012_[0];
assign _014_ = _002_ ? tag_regs[38:31] : _012_[8:1];
assign _015_ = _002_ ? 1'h0 : _012_[9];
assign _016_ = rst | flush_in;
assign _017_ = 32'd1 == { 30'h00000000, \complete_in.tag };
assign _018_ = \complete_in.valid & _017_;
assign _019_ = _018_ ? 1'h0 : tag_regs[20];
assign _020_ = _018_ ? 1'h0 : tag_regs[29];
assign _021_ = tag_regs[27:21] == gpr_write_in;
assign _022_ = gpr_write_valid & _021_;
assign _023_ = _022_ ? 1'h0 : tag_regs[28];
assign _024_ = 32'd1 == { 30'h00000000, instr_tag[1:0] };
assign _025_ = instr_tag[2] & _024_;
assign _026_ = _025_ ? { cr_write_valid, gpr_write_valid, gpr_write_in, gpr_write_valid } : { _020_, _023_, tag_regs[27:21], _019_ };
assign _027_ = _016_ ? 1'h0 : _026_[0];
assign _028_ = _016_ ? tag_regs[28:21] : _026_[8:1];
assign _029_ = _016_ ? 1'h0 : _026_[9];
assign _030_ = rst | flush_in;
assign _031_ = 32'd2 == { 30'h00000000, \complete_in.tag };
assign _032_ = \complete_in.valid & _031_;
assign _033_ = _032_ ? 1'h0 : tag_regs[10];
assign _034_ = _032_ ? 1'h0 : tag_regs[19];
assign _035_ = tag_regs[17:11] == gpr_write_in;
assign _036_ = gpr_write_valid & _035_;
assign _037_ = _036_ ? 1'h0 : tag_regs[18];
assign _038_ = 32'd2 == { 30'h00000000, instr_tag[1:0] };
assign _039_ = instr_tag[2] & _038_;
assign _040_ = _039_ ? { cr_write_valid, gpr_write_valid, gpr_write_in, gpr_write_valid } : { _034_, _037_, tag_regs[17:11], _033_ };
assign _041_ = _030_ ? 1'h0 : _040_[0];
assign _042_ = _030_ ? tag_regs[18:11] : _040_[8:1];
assign _043_ = _030_ ? 1'h0 : _040_[9];
assign _044_ = rst | flush_in;
assign _045_ = 32'd3 == { 30'h00000000, \complete_in.tag };
assign _046_ = \complete_in.valid & _045_;
assign _047_ = _046_ ? 1'h0 : tag_regs[0];
assign _048_ = _046_ ? 1'h0 : tag_regs[9];
assign _049_ = tag_regs[7:1] == gpr_write_in;
assign _050_ = gpr_write_valid & _049_;
assign _051_ = _050_ ? 1'h0 : tag_regs[8];
assign _052_ = 32'd3 == { 30'h00000000, instr_tag[1:0] };
assign _053_ = instr_tag[2] & _052_;
assign _054_ = _053_ ? { cr_write_valid, gpr_write_valid, gpr_write_in, gpr_write_valid } : { _048_, _051_, tag_regs[7:1], _047_ };
assign _055_ = _044_ ? 1'h0 : _054_[0];
assign _056_ = _044_ ? tag_regs[8:1] : _054_[8:1];
assign _057_ = _044_ ? 1'h0 : _054_[9];
assign _058_ = cr_write_valid ? instr_tag[1:0] : curr_cr_tag;
assign _059_ = rst ? 2'h0 : next_tag;
assign _060_ = rst ? 2'h0 : _058_;
always @(posedge clk)
_061_ <= rin_int;
always @(posedge clk)
_062_ <= { _015_, _014_, _013_, _029_, _028_, _027_, _043_, _042_, _041_, _057_, _056_, _055_ };
always @(posedge clk)
_063_ <= _059_;
always @(posedge clk)
_064_ <= _060_;
assign _065_ = tag_regs[30] & tag_regs[38];
assign _066_ = tag_regs[37:31] == gpr_a_read_in;
assign _067_ = _065_ & _066_;
assign _068_ = _067_ ? { gpr_a_read_valid_in, 2'h0 } : 3'h0;
assign _069_ = tag_regs[20] & tag_regs[28];
assign _070_ = tag_regs[27:21] == gpr_a_read_in;
assign _071_ = _069_ & _070_;
assign _072_ = _071_ ? { gpr_a_read_valid_in, 2'h1 } : _068_;
assign _073_ = tag_regs[10] & tag_regs[18];
assign _074_ = tag_regs[17:11] == gpr_a_read_in;
assign _075_ = _073_ & _074_;
assign _076_ = _075_ ? { gpr_a_read_valid_in, 2'h2 } : _072_;
assign _077_ = tag_regs[0] & tag_regs[8];
assign _078_ = tag_regs[7:1] == gpr_a_read_in;
assign _079_ = _077_ & _078_;
assign _080_ = _079_ ? { gpr_a_read_valid_in, 2'h3 } : _076_;
assign _081_ = _080_[2] & \complete_in.valid ;
assign _082_ = { 30'h00000000, _080_[1:0] } == { 30'h00000000, \complete_in.tag };
assign _083_ = _081_ & _082_;
assign _084_ = _067_ ? gpr_a_read_valid_in : 1'h0;
assign _085_ = _071_ ? gpr_a_read_valid_in : _084_;
assign _086_ = _075_ ? gpr_a_read_valid_in : _085_;
assign _087_ = _079_ ? gpr_a_read_valid_in : _086_;
assign _088_ = _083_ ? 1'h0 : _087_;
assign _089_ = _067_ ? 2'h0 : 2'h0;
assign _090_ = _071_ ? 2'h1 : _089_;
assign _091_ = _075_ ? 2'h2 : _090_;
assign _092_ = _079_ ? 2'h3 : _091_;
assign _093_ = tag_regs[30] & tag_regs[38];
assign _094_ = tag_regs[37:31] == gpr_b_read_in;
assign _095_ = _093_ & _094_;
assign _096_ = _095_ ? { gpr_b_read_valid_in, 2'h0 } : 3'h0;
assign _097_ = tag_regs[20] & tag_regs[28];
assign _098_ = tag_regs[27:21] == gpr_b_read_in;
assign _099_ = _097_ & _098_;
assign _100_ = _099_ ? { gpr_b_read_valid_in, 2'h1 } : _096_;
assign _101_ = tag_regs[10] & tag_regs[18];
assign _102_ = tag_regs[17:11] == gpr_b_read_in;
assign _103_ = _101_ & _102_;
assign _104_ = _103_ ? { gpr_b_read_valid_in, 2'h2 } : _100_;
assign _105_ = tag_regs[0] & tag_regs[8];
assign _106_ = tag_regs[7:1] == gpr_b_read_in;
assign _107_ = _105_ & _106_;
assign _108_ = _107_ ? { gpr_b_read_valid_in, 2'h3 } : _104_;
assign _109_ = _108_[2] & \complete_in.valid ;
assign _110_ = { 30'h00000000, _108_[1:0] } == { 30'h00000000, \complete_in.tag };
assign _111_ = _109_ & _110_;
assign _112_ = _095_ ? gpr_b_read_valid_in : 1'h0;
assign _113_ = _099_ ? gpr_b_read_valid_in : _112_;
assign _114_ = _103_ ? gpr_b_read_valid_in : _113_;
assign _115_ = _107_ ? gpr_b_read_valid_in : _114_;
assign _116_ = _111_ ? 1'h0 : _115_;
assign _117_ = _095_ ? 2'h0 : 2'h0;
assign _118_ = _099_ ? 2'h1 : _117_;
assign _119_ = _103_ ? 2'h2 : _118_;
assign _120_ = _107_ ? 2'h3 : _119_;
assign _121_ = tag_regs[30] & tag_regs[38];
assign _122_ = tag_regs[37:31] == gpr_c_read_in;
assign _123_ = _121_ & _122_;
assign _124_ = _123_ ? { gpr_c_read_valid_in, 2'h0 } : 3'h0;
assign _125_ = tag_regs[20] & tag_regs[28];
assign _126_ = tag_regs[27:21] == gpr_c_read_in;
assign _127_ = _125_ & _126_;
assign _128_ = _127_ ? { gpr_c_read_valid_in, 2'h1 } : _124_;
assign _129_ = tag_regs[10] & tag_regs[18];
assign _130_ = tag_regs[17:11] == gpr_c_read_in;
assign _131_ = _129_ & _130_;
assign _132_ = _131_ ? { gpr_c_read_valid_in, 2'h2 } : _128_;
assign _133_ = tag_regs[0] & tag_regs[8];
assign _134_ = tag_regs[7:1] == gpr_c_read_in;
assign _135_ = _133_ & _134_;
assign _136_ = _135_ ? { gpr_c_read_valid_in, 2'h3 } : _132_;
assign _137_ = _136_[2] & \complete_in.valid ;
assign _138_ = { 30'h00000000, _136_[1:0] } == { 30'h00000000, \complete_in.tag };
assign _139_ = _137_ & _138_;
assign _140_ = _123_ ? gpr_c_read_valid_in : 1'h0;
assign _141_ = _127_ ? gpr_c_read_valid_in : _140_;
assign _142_ = _131_ ? gpr_c_read_valid_in : _141_;
assign _143_ = _135_ ? gpr_c_read_valid_in : _142_;
assign _144_ = _139_ ? 1'h0 : _143_;
assign _145_ = _123_ ? 2'h0 : 2'h0;
assign _146_ = _127_ ? 2'h1 : _145_;
assign _147_ = _131_ ? 2'h2 : _146_;
assign _148_ = _135_ ? 2'h3 : _147_;
assign _149_ = \execute_next_tag.valid & _088_;
assign _150_ = { 30'h00000000, \execute_next_tag.tag } == { 30'h00000000, _092_ };
assign _151_ = _149_ & _150_;
assign _152_ = 1'h1 & _151_;
assign _153_ = _152_ ? 1'h1 : 1'h0;
assign _154_ = \execute_next_tag.valid & _116_;
assign _155_ = { 30'h00000000, \execute_next_tag.tag } == { 30'h00000000, _120_ };
assign _156_ = _154_ & _155_;
assign _157_ = 1'h1 & _156_;
assign _158_ = _157_ ? 1'h1 : 1'h0;
assign _159_ = \execute_next_tag.valid & _144_;
assign _160_ = { 30'h00000000, \execute_next_tag.tag } == { 30'h00000000, _148_ };
assign _161_ = _159_ & _160_;
assign _162_ = 1'h1 & _161_;
assign _163_ = _162_ ? 1'h1 : 1'h0;
assign _164_ = ~ _153_;
assign _165_ = _088_ & _164_;
assign _166_ = ~ _158_;
assign _167_ = _116_ & _166_;
assign _168_ = _165_ | _167_;
assign _169_ = ~ _163_;
assign _170_ = _144_ & _169_;
assign _171_ = _168_ | _170_;
assign _172_ = ~ deferred;
assign _173_ = _235_ & _172_;
assign _174_ = { 30'h00000000, curr_tag } + 32'd1;
assign _175_ = instr_tag[2] ? _174_[1:0] : curr_tag;
assign _176_ = 2'h3 - curr_cr_tag;
assign _177_ = cr_read_in & _243_[9];
assign _178_ = _177_ & \complete_in.valid ;
assign _179_ = { 30'h00000000, curr_cr_tag } == { 30'h00000000, \complete_in.tag };
assign _180_ = _178_ & _179_;
assign _181_ = _180_ ? 1'h0 : _177_;
assign _182_ = \execute_next_cr_tag.valid & _181_;
assign _183_ = { 30'h00000000, \execute_next_cr_tag.tag } == { 30'h00000000, curr_cr_tag };
assign _184_ = _182_ & _183_;
assign _185_ = 1'h1 & _184_;
assign _186_ = _185_ ? 1'h1 : 1'h0;
assign _187_ = ~ _186_;
assign _188_ = _181_ & _187_;
assign _189_ = ~ flush_in;
assign _190_ = valid_in & _189_;
assign _191_ = { r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5:2] } - 32'd1;
assign _192_ = \complete_in.valid ? _191_[3:0] : r_int[5:2];
assign _193_ = flush_in ? 4'h0 : _192_;
assign _194_ = $signed({ r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5], r_int[5:2] }) >= $signed(32'd4);
assign _195_ = _194_ ? 1'h0 : _190_;
assign _196_ = _194_ ? 1'h1 : 1'h0;
assign _197_ = rst ? 6'h00 : { _193_, r_int[1:0] };
assign _198_ = rst ? 1'h0 : _195_;
assign _199_ = { _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5:2] } == 32'd0;
assign _200_ = stop_mark_in & _199_;
assign _201_ = _200_ ? 1'h1 : 1'h0;
assign _202_ = { _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5:2] } != 32'd0;
assign _203_ = _202_ ? 2'h1 : 2'h2;
assign _204_ = _202_ ? 1'h1 : _196_;
assign _205_ = gpr_tag_stall | cr_tag_stall;
assign _206_ = rst ? 2'h0 : r_int[1:0];
assign _207_ = sgl_pipe_in ? _203_ : _206_;
assign _208_ = sgl_pipe_in ? _204_ : _205_;
assign _209_ = rst ? 2'h0 : r_int[1:0];
assign _210_ = _198_ ? _207_ : _209_;
assign _211_ = _198_ ? _208_ : _196_;
assign _212_ = r_int[1:0] == 2'h0;
assign _213_ = { _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5:2] } == 32'd0;
assign _214_ = rst ? 2'h0 : r_int[1:0];
assign _215_ = _213_ ? 2'h2 : _214_;
assign _216_ = _213_ ? _196_ : 1'h1;
assign _217_ = r_int[1:0] == 2'h1;
assign _218_ = { _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5], _197_[5:2] } == 32'd0;
assign _219_ = rst ? 4'h0 : _193_;
assign _220_ = { _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_[3], _219_ } != 32'd0;
assign _221_ = _220_ ? 2'h1 : 2'h2;
assign _222_ = _220_ ? 1'h1 : _196_;
assign _223_ = gpr_tag_stall | cr_tag_stall;
assign _224_ = _226_ ? _221_ : 2'h0;
assign _225_ = sgl_pipe_in ? _222_ : _223_;
assign _226_ = _198_ & sgl_pipe_in;
assign _227_ = _198_ ? _225_ : _196_;
assign _228_ = rst ? 2'h0 : r_int[1:0];
assign _229_ = _218_ ? _224_ : _228_;
assign _230_ = _218_ ? _227_ : 1'h1;
assign _231_ = r_int[1:0] == 2'h2;
function [1:0] \27760 ;
input [1:0] a;
input [5:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\27760 = b[1:0];
3'b?1?:
\27760 = b[3:2];
3'b1??:
\27760 = b[5:4];
default:
\27760 = a;
endcase
endfunction
assign _232_ = \27760 (2'hx, { _229_, _215_, _210_ }, { _231_, _217_, _212_ });
assign _233_ = rst ? 4'h0 : _193_;
function [0:0] \27765 ;
input [0:0] a;
input [2:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\27765 = b[0:0];
3'b?1?:
\27765 = b[1:1];
3'b1??:
\27765 = b[2:2];
default:
\27765 = a;
endcase
endfunction
assign _234_ = \27765 (1'hx, { _230_, _216_, _211_ }, { _231_, _217_, _212_ });
assign _235_ = _234_ ? 1'h0 : _198_;
assign _236_ = gpr_write_valid_in & _235_;
assign _237_ = cr_write_in & _235_;
assign _238_ = ~ deferred;
assign _239_ = _235_ & _238_;
assign _240_ = { _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_[3], _233_ } + 32'd1;
assign _241_ = _239_ ? _240_[3:0] : _233_;
assign _242_ = _234_ | deferred;
assign r_int = _061_;
assign rin_int = { _241_, _232_ };
assign gpr_write_valid = _236_;
assign cr_write_valid = _237_;
assign tag_regs = _062_;
assign instr_tag = { _173_, curr_tag };
assign gpr_tag_stall = _171_;
assign cr_tag_stall = _188_;
assign curr_tag = _063_;
assign next_tag = _175_;
assign curr_cr_tag = _064_;
assign valid_out = _235_;
assign stall_out = _242_;
assign stopped_out = _201_;
assign gpr_bypass_a = _153_;
assign gpr_bypass_b = _158_;
assign gpr_bypass_c = _163_;
assign cr_bypass = _186_;
assign \instr_tag_out.tag = instr_tag[1:0];
assign \instr_tag_out.valid = instr_tag[2];
endmodule |
module wishbone_arbiter_4(clk, rst, wb_masters_in, \wb_slave_in.dat , \wb_slave_in.ack , \wb_slave_in.stall , wb_masters_out, \wb_slave_out.adr , \wb_slave_out.dat , \wb_slave_out.sel , \wb_slave_out.cyc , \wb_slave_out.stb , \wb_slave_out.we );
wire [103:0] _00_;
wire [103:0] _01_;
wire [103:0] _02_;
wire [103:0] _03_;
wire [1:0] _04_;
wire _05_;
wire [1:0] _06_;
wire [1:0] _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire [1:0] _24_;
wire [1:0] _25_;
wire [1:0] _26_;
wire [1:0] _27_;
wire _28_;
wire [1:0] _29_;
wire [1:0] _30_;
reg [1:0] _31_;
wire [103:0] _32_;
wire [103:0] _33_;
wire busy;
wire [1:0] candidate;
input clk;
wire clk;
input rst;
wire rst;
wire [1:0] selected;
input [415:0] wb_masters_in;
wire [415:0] wb_masters_in;
output [263:0] wb_masters_out;
wire [263:0] wb_masters_out;
input \wb_slave_in.ack ;
wire \wb_slave_in.ack ;
input [63:0] \wb_slave_in.dat ;
wire [63:0] \wb_slave_in.dat ;
input \wb_slave_in.stall ;
wire \wb_slave_in.stall ;
output [28:0] \wb_slave_out.adr ;
wire [28:0] \wb_slave_out.adr ;
output \wb_slave_out.cyc ;
wire \wb_slave_out.cyc ;
output [63:0] \wb_slave_out.dat ;
wire [63:0] \wb_slave_out.dat ;
output [7:0] \wb_slave_out.sel ;
wire [7:0] \wb_slave_out.sel ;
output \wb_slave_out.stb ;
wire \wb_slave_out.stb ;
output \wb_slave_out.we ;
wire \wb_slave_out.we ;
assign _00_ = _04_[0] ? wb_masters_in[207:104] : wb_masters_in[103:0];
assign _01_ = _07_[0] ? wb_masters_in[207:104] : wb_masters_in[103:0];
assign _02_ = _04_[0] ? wb_masters_in[415:312] : wb_masters_in[311:208];
assign _03_ = _07_[0] ? wb_masters_in[415:312] : wb_masters_in[311:208];
assign _32_ = _04_[1] ? _02_ : _00_;
assign _33_ = _07_[1] ? _03_ : _01_;
assign _04_ = 2'h3 - selected;
assign _05_ = ~ busy;
assign _06_ = _05_ ? candidate : selected;
assign _07_ = 2'h3 - _06_;
assign _08_ = { 30'h00000000, _06_ } == 32'd0;
assign _09_ = _08_ ? \wb_slave_in.ack : 1'h0;
assign _10_ = { 30'h00000000, _06_ } == 32'd0;
assign _11_ = _10_ ? \wb_slave_in.stall : 1'h1;
assign _12_ = { 30'h00000000, _06_ } == 32'd1;
assign _13_ = _12_ ? \wb_slave_in.ack : 1'h0;
assign _14_ = { 30'h00000000, _06_ } == 32'd1;
assign _15_ = _14_ ? \wb_slave_in.stall : 1'h1;
assign _16_ = { 30'h00000000, _06_ } == 32'd2;
assign _17_ = _16_ ? \wb_slave_in.ack : 1'h0;
assign _18_ = { 30'h00000000, _06_ } == 32'd2;
assign _19_ = _18_ ? \wb_slave_in.stall : 1'h1;
assign _20_ = { 30'h00000000, _06_ } == 32'd3;
assign _21_ = _20_ ? \wb_slave_in.ack : 1'h0;
assign _22_ = { 30'h00000000, _06_ } == 32'd3;
assign _23_ = _22_ ? \wb_slave_in.stall : 1'h1;
assign _24_ = wb_masters_in[101] ? 2'h3 : selected;
assign _25_ = wb_masters_in[205] ? 2'h2 : _24_;
assign _26_ = wb_masters_in[309] ? 2'h1 : _25_;
assign _27_ = wb_masters_in[413] ? 2'h0 : _26_;
assign _28_ = ~ busy;
assign _29_ = _28_ ? candidate : selected;
assign _30_ = rst ? 2'h0 : _29_;
always @(posedge clk)
_31_ <= _30_;
assign candidate = _27_;
assign selected = _31_;
assign busy = _32_[101];
assign wb_masters_out = { _11_, _09_, \wb_slave_in.dat , _15_, _13_, \wb_slave_in.dat , _19_, _17_, \wb_slave_in.dat , _23_, _21_, \wb_slave_in.dat };
assign \wb_slave_out.adr = _33_[28:0];
assign \wb_slave_out.dat = _33_[92:29];
assign \wb_slave_out.sel = _33_[100:93];
assign \wb_slave_out.cyc = _33_[101];
assign \wb_slave_out.stb = _33_[102];
assign \wb_slave_out.we = _33_[103];
endmodule |
module divider(clk, rst, \d_in.valid , \d_in.dividend , \d_in.divisor , \d_in.is_signed , \d_in.is_32bit , \d_in.is_extended , \d_in.is_modulus , \d_in.neg_result , \d_out.valid , \d_out.write_reg_data , \d_out.overflow );
wire [128:0] _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire [63:0] _06_;
wire [6:0] _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire [6:0] _12_;
wire _13_;
wire [6:0] _14_;
wire [128:0] _15_;
wire [63:0] _16_;
wire [6:0] _17_;
wire _18_;
wire [128:0] _19_;
wire [63:0] _20_;
wire [6:0] _21_;
wire _22_;
wire [128:0] _23_;
wire [63:0] _24_;
wire _25_;
wire [6:0] _26_;
wire _27_;
wire _28_;
wire [128:0] _29_;
wire [63:0] _30_;
wire [63:0] _31_;
wire _32_;
wire [6:0] _33_;
wire _34_;
wire _35_;
wire _36_;
wire _37_;
wire _38_;
wire _39_;
wire [128:0] _40_;
wire [63:0] _41_;
wire [63:0] _42_;
wire _43_;
wire [6:0] _44_;
wire _45_;
wire _46_;
wire _47_;
wire _48_;
wire _49_;
wire _50_;
reg [128:0] _51_;
reg [63:0] _52_;
reg [63:0] _53_;
reg _54_;
reg [6:0] _55_;
reg _56_;
reg _57_;
reg _58_;
reg _59_;
reg _60_;
reg _61_;
wire [63:0] _62_;
wire [64:0] _63_;
wire [64:0] _64_;
wire _65_;
wire _66_;
wire _67_;
wire _68_;
wire _69_;
wire _70_;
wire _71_;
wire _72_;
wire _73_;
wire _74_;
wire _75_;
wire [63:0] _76_;
wire [63:0] _77_;
wire _78_;
wire _79_;
reg [65:0] _80_;
input clk;
wire clk;
wire [6:0] count;
input [63:0] \d_in.dividend ;
wire [63:0] \d_in.dividend ;
input [63:0] \d_in.divisor ;
wire [63:0] \d_in.divisor ;
input \d_in.is_32bit ;
wire \d_in.is_32bit ;
input \d_in.is_extended ;
wire \d_in.is_extended ;
input \d_in.is_modulus ;
wire \d_in.is_modulus ;
input \d_in.is_signed ;
wire \d_in.is_signed ;
input \d_in.neg_result ;
wire \d_in.neg_result ;
input \d_in.valid ;
wire \d_in.valid ;
output \d_out.overflow ;
wire \d_out.overflow ;
output \d_out.valid ;
wire \d_out.valid ;
output [63:0] \d_out.write_reg_data ;
wire [63:0] \d_out.write_reg_data ;
wire [128:0] dend;
wire did_ovf;
wire [63:0] div;
wire is_32bit;
wire is_modulus;
wire is_signed;
wire neg_result;
wire [63:0] oresult;
wire overflow;
wire ovf32;
wire [63:0] quot;
wire [63:0] result;
input rst;
wire rst;
wire running;
wire [64:0] sresult;
assign _00_ = \d_in.is_extended ? { 1'h0, \d_in.dividend , 64'h0000000000000000 } : { 65'h00000000000000000, \d_in.dividend };
assign _01_ = count == 7'h3f;
assign _02_ = _25_ ? 1'h0 : running;
assign _03_ = dend[127:64] >= div;
assign _04_ = dend[128] | _03_;
assign _05_ = ovf32 | quot[31];
assign _06_ = dend[127:64] - div;
assign _07_ = count + 7'h01;
assign _08_ = dend[128:57] == 72'h000000000000000000;
assign _09_ = count[6:3] != 4'h7;
assign _10_ = _08_ & _09_;
assign _11_ = | { ovf32, quot[31:24] };
assign _12_ = count + 7'h08;
assign _13_ = ovf32 | quot[31];
assign _14_ = count + 7'h01;
assign _15_ = _10_ ? { dend[120:0], 8'h00 } : { dend[127:0], 1'h0 };
assign _16_ = _10_ ? { quot[55:0], 8'h00 } : { quot[62:0], 1'h0 };
assign _17_ = _10_ ? _12_ : _14_;
assign _18_ = _10_ ? _11_ : _13_;
assign _19_ = _04_ ? { _06_, dend[63:0], 1'h0 } : _15_;
assign _20_ = _04_ ? { quot[62:0], 1'h1 } : _16_;
assign _21_ = _04_ ? _07_ : _17_;
assign _22_ = _04_ ? _05_ : _18_;
assign _23_ = running ? _19_ : dend;
assign _24_ = running ? _20_ : quot;
assign _25_ = running & _01_;
assign _26_ = running ? _21_ : 7'h00;
assign _27_ = running ? quot[63] : overflow;
assign _28_ = running ? _22_ : ovf32;
assign _29_ = \d_in.valid ? _00_ : _23_;
assign _30_ = \d_in.valid ? \d_in.divisor : div;
assign _31_ = \d_in.valid ? 64'h0000000000000000 : _24_;
assign _32_ = \d_in.valid ? 1'h1 : _02_;
assign _33_ = \d_in.valid ? 7'h7f : _26_;
assign _34_ = \d_in.valid ? \d_in.neg_result : neg_result;
assign _35_ = \d_in.valid ? \d_in.is_modulus : is_modulus;
assign _36_ = \d_in.valid ? \d_in.is_32bit : is_32bit;
assign _37_ = \d_in.valid ? \d_in.is_signed : is_signed;
assign _38_ = \d_in.valid ? 1'h0 : _27_;
assign _39_ = \d_in.valid ? 1'h0 : _28_;
assign _40_ = rst ? 129'h000000000000000000000000000000000 : _29_;
assign _41_ = rst ? 64'h0000000000000000 : _30_;
assign _42_ = rst ? 64'h0000000000000000 : _31_;
assign _43_ = rst ? 1'h0 : _32_;
assign _44_ = rst ? 7'h00 : _33_;
assign _45_ = rst ? neg_result : _34_;
assign _46_ = rst ? is_modulus : _35_;
assign _47_ = rst ? is_32bit : _36_;
assign _48_ = rst ? is_signed : _37_;
assign _49_ = rst ? overflow : _38_;
assign _50_ = rst ? ovf32 : _39_;
always @(posedge clk)
_51_ <= _40_;
always @(posedge clk)
_52_ <= _41_;
always @(posedge clk)
_53_ <= _42_;
always @(posedge clk)
_54_ <= _43_;
always @(posedge clk)
_55_ <= _44_;
always @(posedge clk)
_56_ <= _45_;
always @(posedge clk)
_57_ <= _46_;
always @(posedge clk)
_58_ <= _47_;
always @(posedge clk)
_59_ <= _48_;
always @(posedge clk)
_60_ <= _49_;
always @(posedge clk)
_61_ <= _50_;
assign _62_ = is_modulus ? dend[128:65] : quot;
assign _63_ = - $signed({ 1'h0, result });
assign _64_ = neg_result ? _63_ : { 1'h0, result };
assign _65_ = ~ is_32bit;
assign _66_ = sresult[64] ^ sresult[63];
assign _67_ = is_signed & _66_;
assign _68_ = overflow | _67_;
assign _69_ = sresult[32] != sresult[31];
assign _70_ = ovf32 | _69_;
assign _71_ = _70_ ? 1'h1 : 1'h0;
assign _72_ = is_signed ? _71_ : ovf32;
assign _73_ = _65_ ? _68_ : _72_;
assign _74_ = ~ is_modulus;
assign _75_ = is_32bit & _74_;
assign _76_ = _75_ ? { 32'h00000000, sresult[31:0] } : sresult[63:0];
assign _77_ = did_ovf ? 64'h0000000000000000 : _76_;
assign _78_ = count == 7'h40;
assign _79_ = _78_ ? 1'h1 : 1'h0;
always @(posedge clk)
_80_ <= { did_ovf, oresult, _79_ };
assign dend = _51_;
assign div = _52_;
assign quot = _53_;
assign result = _62_;
assign sresult = _64_;
assign oresult = _77_;
assign running = _54_;
assign count = _55_;
assign neg_result = _56_;
assign is_modulus = _57_;
assign is_32bit = _58_;
assign is_signed = _59_;
assign overflow = _60_;
assign ovf32 = _61_;
assign did_ovf = _73_;
assign \d_out.valid = _80_[0];
assign \d_out.write_reg_data = _80_[64:1];
assign \d_out.overflow = _80_[65];
endmodule |
module bridge(wb__dat_w, wb__dat_r, wb__sel, wb__cyc, wb__stb, wb__we, wb__ack, rst, clk, csr__addr, csr__r_stb, csr__w_stb, csr__w_data, csr__r_data, wb__adr);
reg \$auto$verilog_backend.cc:2083:dump_module$1 = 0;
wire \$1 ;
wire \$11 ;
wire \$13 ;
wire \$15 ;
wire \$17 ;
wire \$3 ;
wire \$5 ;
wire \$7 ;
wire \$9 ;
input clk;
wire clk;
output csr__addr;
wire csr__addr;
input [31:0] csr__r_data;
wire [31:0] csr__r_data;
output csr__r_stb;
reg csr__r_stb;
output [31:0] csr__w_data;
reg [31:0] csr__w_data;
output csr__w_stb;
reg csr__w_stb;
reg cycle = 1'h0;
reg \cycle$next ;
input rst;
wire rst;
output wb__ack;
reg wb__ack = 1'h0;
reg \wb__ack$next ;
input wb__adr;
wire wb__adr;
input wb__cyc;
wire wb__cyc;
output [31:0] wb__dat_r;
reg [31:0] wb__dat_r = 32'd0;
reg [31:0] \wb__dat_r$next ;
input [31:0] wb__dat_w;
wire [31:0] wb__dat_w;
input wb__sel;
wire wb__sel;
input wb__stb;
wire wb__stb;
input wb__we;
wire wb__we;
assign \$9 = wb__cyc & wb__stb;
assign \$11 = wb__sel & wb__we;
assign \$13 = wb__cyc & wb__stb;
assign \$15 = wb__cyc & wb__stb;
assign \$17 = wb__cyc & wb__stb;
always @(posedge clk)
cycle <= \cycle$next ;
assign \$1 = wb__cyc & wb__stb;
always @(posedge clk)
wb__dat_r <= \wb__dat_r$next ;
always @(posedge clk)
wb__ack <= \wb__ack$next ;
assign \$3 = ~ wb__we;
assign \$5 = wb__sel & \$3 ;
assign \$7 = wb__cyc & wb__stb;
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
csr__r_stb = 1'h0;
casez (\$1 )
1'h1:
casez (cycle)
1'h0:
csr__r_stb = \$5 ;
endcase
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
csr__w_data = 32'd0;
casez (\$7 )
1'h1:
casez (cycle)
1'h0:
csr__w_data = wb__dat_w;
endcase
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
csr__w_stb = 1'h0;
casez (\$9 )
1'h1:
casez (cycle)
1'h0:
csr__w_stb = \$11 ;
endcase
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\cycle$next = cycle;
casez (\$13 )
1'h1:
casez (cycle)
1'h0:
\cycle$next = 1'h1;
endcase
endcase
casez (wb__ack)
1'h1:
\cycle$next = 1'h0;
endcase
casez (rst)
1'h1:
\cycle$next = 1'h0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\wb__dat_r$next = wb__dat_r;
casez (\$15 )
1'h1:
(* full_case = 32'd1 *)
casez (cycle)
1'h0:
/* empty */;
default:
\wb__dat_r$next = csr__r_data;
endcase
endcase
casez (rst)
1'h1:
\wb__dat_r$next = 32'd0;
endcase
end
always @* begin
if (\$auto$verilog_backend.cc:2083:dump_module$1 ) begin end
\wb__ack$next = wb__ack;
casez (\$17 )
1'h1:
(* full_case = 32'd1 *)
casez (cycle)
1'h0:
/* empty */;
default:
\wb__ack$next = 1'h1;
endcase
endcase
casez (wb__ack)
1'h1:
\wb__ack$next = 1'h0;
endcase
casez (rst)
1'h1:
\wb__ack$next = 1'h0;
endcase
end
assign csr__addr = wb__adr;
endmodule |
module rotator(rs, ra, shift, insn, is_32bit, right_shift, arith, clear_left, clear_right, sign_ext_rs, result, carry_out);
wire [31:0] _000_;
wire [31:0] _001_;
wire [5:0] _002_;
wire [5:0] _003_;
wire _004_;
wire _005_;
wire _006_;
wire [63:0] _007_;
wire _008_;
wire _009_;
wire _010_;
wire [63:0] _011_;
wire _012_;
wire _013_;
wire _014_;
wire [63:0] _015_;
wire _016_;
wire _017_;
wire [6:0] _018_;
wire _019_;
wire [6:0] _020_;
wire [6:0] _021_;
wire [6:0] _022_;
wire _023_;
wire _024_;
wire _025_;
wire [5:0] _026_;
wire [6:0] _027_;
wire [6:0] _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
wire _059_;
wire _060_;
wire _061_;
wire _062_;
wire _063_;
wire _064_;
wire _065_;
wire _066_;
wire _067_;
wire _068_;
wire _069_;
wire _070_;
wire _071_;
wire _072_;
wire _073_;
wire _074_;
wire _075_;
wire _076_;
wire _077_;
wire _078_;
wire _079_;
wire _080_;
wire _081_;
wire _082_;
wire _083_;
wire _084_;
wire _085_;
wire _086_;
wire _087_;
wire _088_;
wire _089_;
wire _090_;
wire _091_;
wire _092_;
wire _093_;
wire _094_;
wire _095_;
wire _096_;
wire _097_;
wire _098_;
wire _099_;
wire _100_;
wire _101_;
wire _102_;
wire _103_;
wire _104_;
wire _105_;
wire _106_;
wire _107_;
wire _108_;
wire _109_;
wire _110_;
wire _111_;
wire _112_;
wire _113_;
wire _114_;
wire _115_;
wire _116_;
wire _117_;
wire _118_;
wire _119_;
wire _120_;
wire _121_;
wire _122_;
wire _123_;
wire _124_;
wire _125_;
wire _126_;
wire _127_;
wire _128_;
wire _129_;
wire _130_;
wire _131_;
wire _132_;
wire _133_;
wire _134_;
wire _135_;
wire _136_;
wire _137_;
wire _138_;
wire _139_;
wire _140_;
wire _141_;
wire _142_;
wire _143_;
wire _144_;
wire _145_;
wire _146_;
wire _147_;
wire _148_;
wire _149_;
wire _150_;
wire _151_;
wire _152_;
wire _153_;
wire _154_;
wire _155_;
wire _156_;
wire _157_;
wire _158_;
wire _159_;
wire _160_;
wire _161_;
wire _162_;
wire _163_;
wire _164_;
wire _165_;
wire _166_;
wire _167_;
wire _168_;
wire _169_;
wire _170_;
wire _171_;
wire _172_;
wire _173_;
wire _174_;
wire _175_;
wire _176_;
wire _177_;
wire _178_;
wire _179_;
wire _180_;
wire _181_;
wire _182_;
wire _183_;
wire _184_;
wire _185_;
wire _186_;
wire _187_;
wire _188_;
wire _189_;
wire _190_;
wire _191_;
wire _192_;
wire _193_;
wire _194_;
wire _195_;
wire _196_;
wire _197_;
wire _198_;
wire _199_;
wire _200_;
wire _201_;
wire _202_;
wire _203_;
wire _204_;
wire _205_;
wire _206_;
wire _207_;
wire _208_;
wire _209_;
wire _210_;
wire _211_;
wire _212_;
wire _213_;
wire _214_;
wire _215_;
wire _216_;
wire _217_;
wire _218_;
wire _219_;
wire _220_;
wire _221_;
wire _222_;
wire _223_;
wire _224_;
wire _225_;
wire _226_;
wire _227_;
wire _228_;
wire _229_;
wire _230_;
wire _231_;
wire _232_;
wire _233_;
wire _234_;
wire _235_;
wire _236_;
wire _237_;
wire _238_;
wire _239_;
wire _240_;
wire _241_;
wire _242_;
wire _243_;
wire _244_;
wire _245_;
wire _246_;
wire _247_;
wire _248_;
wire _249_;
wire _250_;
wire _251_;
wire _252_;
wire _253_;
wire _254_;
wire _255_;
wire _256_;
wire _257_;
wire _258_;
wire _259_;
wire _260_;
wire _261_;
wire _262_;
wire _263_;
wire _264_;
wire _265_;
wire _266_;
wire _267_;
wire _268_;
wire _269_;
wire _270_;
wire _271_;
wire _272_;
wire _273_;
wire _274_;
wire _275_;
wire _276_;
wire _277_;
wire _278_;
wire _279_;
wire _280_;
wire _281_;
wire _282_;
wire _283_;
wire _284_;
wire _285_;
wire [63:0] _286_;
wire _287_;
wire _288_;
wire _289_;
wire _290_;
wire _291_;
wire _292_;
wire _293_;
wire [1:0] _294_;
wire [63:0] _295_;
wire [63:0] _296_;
wire [63:0] _297_;
wire [63:0] _298_;
wire [63:0] _299_;
wire [63:0] _300_;
wire _301_;
wire [63:0] _302_;
wire [63:0] _303_;
wire [63:0] _304_;
wire [63:0] _305_;
wire [63:0] _306_;
wire [63:0] _307_;
wire _308_;
wire [63:0] _309_;
wire _310_;
wire [63:0] _311_;
wire [63:0] _312_;
wire [63:0] _313_;
wire _314_;
wire [63:0] _315_;
wire [63:0] _316_;
wire _317_;
wire _318_;
input arith;
wire arith;
output carry_out;
wire carry_out;
input clear_left;
wire clear_left;
input clear_right;
wire clear_right;
input [31:0] insn;
wire [31:0] insn;
input is_32bit;
wire is_32bit;
wire [6:0] mb;
wire [6:0] me;
wire [63:0] ml;
wire [63:0] mr;
wire [1:0] output_mode;
input [63:0] ra;
wire [63:0] ra;
wire [63:0] repl32;
output [63:0] result;
wire [63:0] result;
input right_shift;
wire right_shift;
wire [63:0] rot;
wire [63:0] rot1;
wire [63:0] rot2;
wire [5:0] rot_count;
input [63:0] rs;
wire [63:0] rs;
wire [6:0] sh;
input [6:0] shift;
wire [6:0] shift;
input sign_ext_rs;
wire sign_ext_rs;
assign _000_ = sign_ext_rs ? { rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31], rs[31] } : rs[63:32];
assign _001_ = is_32bit ? rs[31:0] : _000_;
assign _002_ = - $signed(shift[5:0]);
assign _003_ = right_shift ? _002_ : shift[5:0];
assign _004_ = rot_count[1:0] == 2'h0;
assign _005_ = rot_count[1:0] == 2'h1;
assign _006_ = rot_count[1:0] == 2'h2;
function [63:0] \27865 ;
input [63:0] a;
input [191:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\27865 = b[63:0];
3'b?1?:
\27865 = b[127:64];
3'b1??:
\27865 = b[191:128];
default:
\27865 = a;
endcase
endfunction
assign _007_ = \27865 ({ repl32[60:0], repl32[63:61] }, { repl32[61:0], repl32[63:62], repl32[62:0], repl32[63], repl32 }, { _006_, _005_, _004_ });
assign _008_ = rot_count[3:2] == 2'h0;
assign _009_ = rot_count[3:2] == 2'h1;
assign _010_ = rot_count[3:2] == 2'h2;
function [63:0] \27883 ;
input [63:0] a;
input [191:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\27883 = b[63:0];
3'b?1?:
\27883 = b[127:64];
3'b1??:
\27883 = b[191:128];
default:
\27883 = a;
endcase
endfunction
assign _011_ = \27883 ({ rot1[51:0], rot1[63:52] }, { rot1[55:0], rot1[63:56], rot1[59:0], rot1[63:60], rot1 }, { _010_, _009_, _008_ });
assign _012_ = rot_count[5:4] == 2'h0;
assign _013_ = rot_count[5:4] == 2'h1;
assign _014_ = rot_count[5:4] == 2'h2;
function [63:0] \27901 ;
input [63:0] a;
input [191:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\27901 = b[63:0];
3'b?1?:
\27901 = b[127:64];
3'b1??:
\27901 = b[191:128];
default:
\27901 = a;
endcase
endfunction
assign _015_ = \27901 ({ rot2[15:0], rot2[63:16] }, { rot2[31:0], rot2[63:32], rot2[47:0], rot2[63:48], rot2 }, { _014_, _013_, _012_ });
assign _016_ = ~ is_32bit;
assign _017_ = shift[6] & _016_;
assign _018_ = is_32bit ? { 2'h1, insn[10:6] } : { 1'h0, insn[5], insn[10:6] };
assign _019_ = ~ sh[5];
assign _020_ = is_32bit ? { sh[5], _019_, sh[4:0] } : sh;
assign _021_ = right_shift ? _020_ : { 1'h0, is_32bit, 5'h00 };
assign _022_ = clear_left ? _018_ : _021_;
assign _023_ = clear_right & is_32bit;
assign _024_ = ~ clear_left;
assign _025_ = clear_right & _024_;
assign _026_ = ~ sh[5:0];
assign _027_ = _025_ ? { 1'h0, insn[5], insn[10:6] } : { sh[6], _026_ };
assign _028_ = _023_ ? { 2'h1, insn[5:1] } : _027_;
assign _029_ = $signed(32'd0) >= $signed({ 25'h0000000, mb });
assign _030_ = _029_ ? 1'h1 : 1'h0;
assign _031_ = $signed(32'd1) >= $signed({ 25'h0000000, mb });
assign _032_ = _031_ ? 1'h1 : 1'h0;
assign _033_ = $signed(32'd2) >= $signed({ 25'h0000000, mb });
assign _034_ = _033_ ? 1'h1 : 1'h0;
assign _035_ = $signed(32'd3) >= $signed({ 25'h0000000, mb });
assign _036_ = _035_ ? 1'h1 : 1'h0;
assign _037_ = $signed(32'd4) >= $signed({ 25'h0000000, mb });
assign _038_ = _037_ ? 1'h1 : 1'h0;
assign _039_ = $signed(32'd5) >= $signed({ 25'h0000000, mb });
assign _040_ = _039_ ? 1'h1 : 1'h0;
assign _041_ = $signed(32'd6) >= $signed({ 25'h0000000, mb });
assign _042_ = _041_ ? 1'h1 : 1'h0;
assign _043_ = $signed(32'd7) >= $signed({ 25'h0000000, mb });
assign _044_ = _043_ ? 1'h1 : 1'h0;
assign _045_ = $signed(32'd8) >= $signed({ 25'h0000000, mb });
assign _046_ = _045_ ? 1'h1 : 1'h0;
assign _047_ = $signed(32'd9) >= $signed({ 25'h0000000, mb });
assign _048_ = _047_ ? 1'h1 : 1'h0;
assign _049_ = $signed(32'd10) >= $signed({ 25'h0000000, mb });
assign _050_ = _049_ ? 1'h1 : 1'h0;
assign _051_ = $signed(32'd11) >= $signed({ 25'h0000000, mb });
assign _052_ = _051_ ? 1'h1 : 1'h0;
assign _053_ = $signed(32'd12) >= $signed({ 25'h0000000, mb });
assign _054_ = _053_ ? 1'h1 : 1'h0;
assign _055_ = $signed(32'd13) >= $signed({ 25'h0000000, mb });
assign _056_ = _055_ ? 1'h1 : 1'h0;
assign _057_ = $signed(32'd14) >= $signed({ 25'h0000000, mb });
assign _058_ = _057_ ? 1'h1 : 1'h0;
assign _059_ = $signed(32'd15) >= $signed({ 25'h0000000, mb });
assign _060_ = _059_ ? 1'h1 : 1'h0;
assign _061_ = $signed(32'd16) >= $signed({ 25'h0000000, mb });
assign _062_ = _061_ ? 1'h1 : 1'h0;
assign _063_ = $signed(32'd17) >= $signed({ 25'h0000000, mb });
assign _064_ = _063_ ? 1'h1 : 1'h0;
assign _065_ = $signed(32'd18) >= $signed({ 25'h0000000, mb });
assign _066_ = _065_ ? 1'h1 : 1'h0;
assign _067_ = $signed(32'd19) >= $signed({ 25'h0000000, mb });
assign _068_ = _067_ ? 1'h1 : 1'h0;
assign _069_ = $signed(32'd20) >= $signed({ 25'h0000000, mb });
assign _070_ = _069_ ? 1'h1 : 1'h0;
assign _071_ = $signed(32'd21) >= $signed({ 25'h0000000, mb });
assign _072_ = _071_ ? 1'h1 : 1'h0;
assign _073_ = $signed(32'd22) >= $signed({ 25'h0000000, mb });
assign _074_ = _073_ ? 1'h1 : 1'h0;
assign _075_ = $signed(32'd23) >= $signed({ 25'h0000000, mb });
assign _076_ = _075_ ? 1'h1 : 1'h0;
assign _077_ = $signed(32'd24) >= $signed({ 25'h0000000, mb });
assign _078_ = _077_ ? 1'h1 : 1'h0;
assign _079_ = $signed(32'd25) >= $signed({ 25'h0000000, mb });
assign _080_ = _079_ ? 1'h1 : 1'h0;
assign _081_ = $signed(32'd26) >= $signed({ 25'h0000000, mb });
assign _082_ = _081_ ? 1'h1 : 1'h0;
assign _083_ = $signed(32'd27) >= $signed({ 25'h0000000, mb });
assign _084_ = _083_ ? 1'h1 : 1'h0;
assign _085_ = $signed(32'd28) >= $signed({ 25'h0000000, mb });
assign _086_ = _085_ ? 1'h1 : 1'h0;
assign _087_ = $signed(32'd29) >= $signed({ 25'h0000000, mb });
assign _088_ = _087_ ? 1'h1 : 1'h0;
assign _089_ = $signed(32'd30) >= $signed({ 25'h0000000, mb });
assign _090_ = _089_ ? 1'h1 : 1'h0;
assign _091_ = $signed(32'd31) >= $signed({ 25'h0000000, mb });
assign _092_ = _091_ ? 1'h1 : 1'h0;
assign _093_ = $signed(32'd32) >= $signed({ 25'h0000000, mb });
assign _094_ = _093_ ? 1'h1 : 1'h0;
assign _095_ = $signed(32'd33) >= $signed({ 25'h0000000, mb });
assign _096_ = _095_ ? 1'h1 : 1'h0;
assign _097_ = $signed(32'd34) >= $signed({ 25'h0000000, mb });
assign _098_ = _097_ ? 1'h1 : 1'h0;
assign _099_ = $signed(32'd35) >= $signed({ 25'h0000000, mb });
assign _100_ = _099_ ? 1'h1 : 1'h0;
assign _101_ = $signed(32'd36) >= $signed({ 25'h0000000, mb });
assign _102_ = _101_ ? 1'h1 : 1'h0;
assign _103_ = $signed(32'd37) >= $signed({ 25'h0000000, mb });
assign _104_ = _103_ ? 1'h1 : 1'h0;
assign _105_ = $signed(32'd38) >= $signed({ 25'h0000000, mb });
assign _106_ = _105_ ? 1'h1 : 1'h0;
assign _107_ = $signed(32'd39) >= $signed({ 25'h0000000, mb });
assign _108_ = _107_ ? 1'h1 : 1'h0;
assign _109_ = $signed(32'd40) >= $signed({ 25'h0000000, mb });
assign _110_ = _109_ ? 1'h1 : 1'h0;
assign _111_ = $signed(32'd41) >= $signed({ 25'h0000000, mb });
assign _112_ = _111_ ? 1'h1 : 1'h0;
assign _113_ = $signed(32'd42) >= $signed({ 25'h0000000, mb });
assign _114_ = _113_ ? 1'h1 : 1'h0;
assign _115_ = $signed(32'd43) >= $signed({ 25'h0000000, mb });
assign _116_ = _115_ ? 1'h1 : 1'h0;
assign _117_ = $signed(32'd44) >= $signed({ 25'h0000000, mb });
assign _118_ = _117_ ? 1'h1 : 1'h0;
assign _119_ = $signed(32'd45) >= $signed({ 25'h0000000, mb });
assign _120_ = _119_ ? 1'h1 : 1'h0;
assign _121_ = $signed(32'd46) >= $signed({ 25'h0000000, mb });
assign _122_ = _121_ ? 1'h1 : 1'h0;
assign _123_ = $signed(32'd47) >= $signed({ 25'h0000000, mb });
assign _124_ = _123_ ? 1'h1 : 1'h0;
assign _125_ = $signed(32'd48) >= $signed({ 25'h0000000, mb });
assign _126_ = _125_ ? 1'h1 : 1'h0;
assign _127_ = $signed(32'd49) >= $signed({ 25'h0000000, mb });
assign _128_ = _127_ ? 1'h1 : 1'h0;
assign _129_ = $signed(32'd50) >= $signed({ 25'h0000000, mb });
assign _130_ = _129_ ? 1'h1 : 1'h0;
assign _131_ = $signed(32'd51) >= $signed({ 25'h0000000, mb });
assign _132_ = _131_ ? 1'h1 : 1'h0;
assign _133_ = $signed(32'd52) >= $signed({ 25'h0000000, mb });
assign _134_ = _133_ ? 1'h1 : 1'h0;
assign _135_ = $signed(32'd53) >= $signed({ 25'h0000000, mb });
assign _136_ = _135_ ? 1'h1 : 1'h0;
assign _137_ = $signed(32'd54) >= $signed({ 25'h0000000, mb });
assign _138_ = _137_ ? 1'h1 : 1'h0;
assign _139_ = $signed(32'd55) >= $signed({ 25'h0000000, mb });
assign _140_ = _139_ ? 1'h1 : 1'h0;
assign _141_ = $signed(32'd56) >= $signed({ 25'h0000000, mb });
assign _142_ = _141_ ? 1'h1 : 1'h0;
assign _143_ = $signed(32'd57) >= $signed({ 25'h0000000, mb });
assign _144_ = _143_ ? 1'h1 : 1'h0;
assign _145_ = $signed(32'd58) >= $signed({ 25'h0000000, mb });
assign _146_ = _145_ ? 1'h1 : 1'h0;
assign _147_ = $signed(32'd59) >= $signed({ 25'h0000000, mb });
assign _148_ = _147_ ? 1'h1 : 1'h0;
assign _149_ = $signed(32'd60) >= $signed({ 25'h0000000, mb });
assign _150_ = _149_ ? 1'h1 : 1'h0;
assign _151_ = $signed(32'd61) >= $signed({ 25'h0000000, mb });
assign _152_ = _151_ ? 1'h1 : 1'h0;
assign _153_ = $signed(32'd62) >= $signed({ 25'h0000000, mb });
assign _154_ = _153_ ? 1'h1 : 1'h0;
assign _155_ = $signed(32'd63) >= $signed({ 25'h0000000, mb });
assign _156_ = _155_ ? 1'h1 : 1'h0;
assign _157_ = ~ me[6];
assign _158_ = $signed(32'd0) <= $signed({ 25'h0000000, me });
assign _159_ = _158_ ? 1'h1 : 1'h0;
assign _160_ = $signed(32'd1) <= $signed({ 25'h0000000, me });
assign _161_ = _160_ ? 1'h1 : 1'h0;
assign _162_ = $signed(32'd2) <= $signed({ 25'h0000000, me });
assign _163_ = _162_ ? 1'h1 : 1'h0;
assign _164_ = $signed(32'd3) <= $signed({ 25'h0000000, me });
assign _165_ = _164_ ? 1'h1 : 1'h0;
assign _166_ = $signed(32'd4) <= $signed({ 25'h0000000, me });
assign _167_ = _166_ ? 1'h1 : 1'h0;
assign _168_ = $signed(32'd5) <= $signed({ 25'h0000000, me });
assign _169_ = _168_ ? 1'h1 : 1'h0;
assign _170_ = $signed(32'd6) <= $signed({ 25'h0000000, me });
assign _171_ = _170_ ? 1'h1 : 1'h0;
assign _172_ = $signed(32'd7) <= $signed({ 25'h0000000, me });
assign _173_ = _172_ ? 1'h1 : 1'h0;
assign _174_ = $signed(32'd8) <= $signed({ 25'h0000000, me });
assign _175_ = _174_ ? 1'h1 : 1'h0;
assign _176_ = $signed(32'd9) <= $signed({ 25'h0000000, me });
assign _177_ = _176_ ? 1'h1 : 1'h0;
assign _178_ = $signed(32'd10) <= $signed({ 25'h0000000, me });
assign _179_ = _178_ ? 1'h1 : 1'h0;
assign _180_ = $signed(32'd11) <= $signed({ 25'h0000000, me });
assign _181_ = _180_ ? 1'h1 : 1'h0;
assign _182_ = $signed(32'd12) <= $signed({ 25'h0000000, me });
assign _183_ = _182_ ? 1'h1 : 1'h0;
assign _184_ = $signed(32'd13) <= $signed({ 25'h0000000, me });
assign _185_ = _184_ ? 1'h1 : 1'h0;
assign _186_ = $signed(32'd14) <= $signed({ 25'h0000000, me });
assign _187_ = _186_ ? 1'h1 : 1'h0;
assign _188_ = $signed(32'd15) <= $signed({ 25'h0000000, me });
assign _189_ = _188_ ? 1'h1 : 1'h0;
assign _190_ = $signed(32'd16) <= $signed({ 25'h0000000, me });
assign _191_ = _190_ ? 1'h1 : 1'h0;
assign _192_ = $signed(32'd17) <= $signed({ 25'h0000000, me });
assign _193_ = _192_ ? 1'h1 : 1'h0;
assign _194_ = $signed(32'd18) <= $signed({ 25'h0000000, me });
assign _195_ = _194_ ? 1'h1 : 1'h0;
assign _196_ = $signed(32'd19) <= $signed({ 25'h0000000, me });
assign _197_ = _196_ ? 1'h1 : 1'h0;
assign _198_ = $signed(32'd20) <= $signed({ 25'h0000000, me });
assign _199_ = _198_ ? 1'h1 : 1'h0;
assign _200_ = $signed(32'd21) <= $signed({ 25'h0000000, me });
assign _201_ = _200_ ? 1'h1 : 1'h0;
assign _202_ = $signed(32'd22) <= $signed({ 25'h0000000, me });
assign _203_ = _202_ ? 1'h1 : 1'h0;
assign _204_ = $signed(32'd23) <= $signed({ 25'h0000000, me });
assign _205_ = _204_ ? 1'h1 : 1'h0;
assign _206_ = $signed(32'd24) <= $signed({ 25'h0000000, me });
assign _207_ = _206_ ? 1'h1 : 1'h0;
assign _208_ = $signed(32'd25) <= $signed({ 25'h0000000, me });
assign _209_ = _208_ ? 1'h1 : 1'h0;
assign _210_ = $signed(32'd26) <= $signed({ 25'h0000000, me });
assign _211_ = _210_ ? 1'h1 : 1'h0;
assign _212_ = $signed(32'd27) <= $signed({ 25'h0000000, me });
assign _213_ = _212_ ? 1'h1 : 1'h0;
assign _214_ = $signed(32'd28) <= $signed({ 25'h0000000, me });
assign _215_ = _214_ ? 1'h1 : 1'h0;
assign _216_ = $signed(32'd29) <= $signed({ 25'h0000000, me });
assign _217_ = _216_ ? 1'h1 : 1'h0;
assign _218_ = $signed(32'd30) <= $signed({ 25'h0000000, me });
assign _219_ = _218_ ? 1'h1 : 1'h0;
assign _220_ = $signed(32'd31) <= $signed({ 25'h0000000, me });
assign _221_ = _220_ ? 1'h1 : 1'h0;
assign _222_ = $signed(32'd32) <= $signed({ 25'h0000000, me });
assign _223_ = _222_ ? 1'h1 : 1'h0;
assign _224_ = $signed(32'd33) <= $signed({ 25'h0000000, me });
assign _225_ = _224_ ? 1'h1 : 1'h0;
assign _226_ = $signed(32'd34) <= $signed({ 25'h0000000, me });
assign _227_ = _226_ ? 1'h1 : 1'h0;
assign _228_ = $signed(32'd35) <= $signed({ 25'h0000000, me });
assign _229_ = _228_ ? 1'h1 : 1'h0;
assign _230_ = $signed(32'd36) <= $signed({ 25'h0000000, me });
assign _231_ = _230_ ? 1'h1 : 1'h0;
assign _232_ = $signed(32'd37) <= $signed({ 25'h0000000, me });
assign _233_ = _232_ ? 1'h1 : 1'h0;
assign _234_ = $signed(32'd38) <= $signed({ 25'h0000000, me });
assign _235_ = _234_ ? 1'h1 : 1'h0;
assign _236_ = $signed(32'd39) <= $signed({ 25'h0000000, me });
assign _237_ = _236_ ? 1'h1 : 1'h0;
assign _238_ = $signed(32'd40) <= $signed({ 25'h0000000, me });
assign _239_ = _238_ ? 1'h1 : 1'h0;
assign _240_ = $signed(32'd41) <= $signed({ 25'h0000000, me });
assign _241_ = _240_ ? 1'h1 : 1'h0;
assign _242_ = $signed(32'd42) <= $signed({ 25'h0000000, me });
assign _243_ = _242_ ? 1'h1 : 1'h0;
assign _244_ = $signed(32'd43) <= $signed({ 25'h0000000, me });
assign _245_ = _244_ ? 1'h1 : 1'h0;
assign _246_ = $signed(32'd44) <= $signed({ 25'h0000000, me });
assign _247_ = _246_ ? 1'h1 : 1'h0;
assign _248_ = $signed(32'd45) <= $signed({ 25'h0000000, me });
assign _249_ = _248_ ? 1'h1 : 1'h0;
assign _250_ = $signed(32'd46) <= $signed({ 25'h0000000, me });
assign _251_ = _250_ ? 1'h1 : 1'h0;
assign _252_ = $signed(32'd47) <= $signed({ 25'h0000000, me });
assign _253_ = _252_ ? 1'h1 : 1'h0;
assign _254_ = $signed(32'd48) <= $signed({ 25'h0000000, me });
assign _255_ = _254_ ? 1'h1 : 1'h0;
assign _256_ = $signed(32'd49) <= $signed({ 25'h0000000, me });
assign _257_ = _256_ ? 1'h1 : 1'h0;
assign _258_ = $signed(32'd50) <= $signed({ 25'h0000000, me });
assign _259_ = _258_ ? 1'h1 : 1'h0;
assign _260_ = $signed(32'd51) <= $signed({ 25'h0000000, me });
assign _261_ = _260_ ? 1'h1 : 1'h0;
assign _262_ = $signed(32'd52) <= $signed({ 25'h0000000, me });
assign _263_ = _262_ ? 1'h1 : 1'h0;
assign _264_ = $signed(32'd53) <= $signed({ 25'h0000000, me });
assign _265_ = _264_ ? 1'h1 : 1'h0;
assign _266_ = $signed(32'd54) <= $signed({ 25'h0000000, me });
assign _267_ = _266_ ? 1'h1 : 1'h0;
assign _268_ = $signed(32'd55) <= $signed({ 25'h0000000, me });
assign _269_ = _268_ ? 1'h1 : 1'h0;
assign _270_ = $signed(32'd56) <= $signed({ 25'h0000000, me });
assign _271_ = _270_ ? 1'h1 : 1'h0;
assign _272_ = $signed(32'd57) <= $signed({ 25'h0000000, me });
assign _273_ = _272_ ? 1'h1 : 1'h0;
assign _274_ = $signed(32'd58) <= $signed({ 25'h0000000, me });
assign _275_ = _274_ ? 1'h1 : 1'h0;
assign _276_ = $signed(32'd59) <= $signed({ 25'h0000000, me });
assign _277_ = _276_ ? 1'h1 : 1'h0;
assign _278_ = $signed(32'd60) <= $signed({ 25'h0000000, me });
assign _279_ = _278_ ? 1'h1 : 1'h0;
assign _280_ = $signed(32'd61) <= $signed({ 25'h0000000, me });
assign _281_ = _280_ ? 1'h1 : 1'h0;
assign _282_ = $signed(32'd62) <= $signed({ 25'h0000000, me });
assign _283_ = _282_ ? 1'h1 : 1'h0;
assign _284_ = $signed(32'd63) <= $signed({ 25'h0000000, me });
assign _285_ = _284_ ? 1'h1 : 1'h0;
assign _286_ = _157_ ? { _159_, _161_, _163_, _165_, _167_, _169_, _171_, _173_, _175_, _177_, _179_, _181_, _183_, _185_, _187_, _189_, _191_, _193_, _195_, _197_, _199_, _201_, _203_, _205_, _207_, _209_, _211_, _213_, _215_, _217_, _219_, _221_, _223_, _225_, _227_, _229_, _231_, _233_, _235_, _237_, _239_, _241_, _243_, _245_, _247_, _249_, _251_, _253_, _255_, _257_, _259_, _261_, _263_, _265_, _267_, _269_, _271_, _273_, _275_, _277_, _279_, _281_, _283_, _285_ } : 64'h0000000000000000;
assign _287_ = ~ clear_right;
assign _288_ = clear_left & _287_;
assign _289_ = _288_ | right_shift;
assign _290_ = arith & repl32[63];
assign _291_ = mb[5:0] > me[5:0];
assign _292_ = clear_right & _291_;
assign _293_ = _292_ ? 1'h1 : 1'h0;
assign _294_ = _289_ ? { 1'h1, _290_ } : { 1'h0, _293_ };
assign _295_ = mr & ml;
assign _296_ = rot & _295_;
assign _297_ = mr & ml;
assign _298_ = ~ _297_;
assign _299_ = ra & _298_;
assign _300_ = _296_ | _299_;
assign _301_ = output_mode == 2'h0;
assign _302_ = mr | ml;
assign _303_ = rot & _302_;
assign _304_ = mr | ml;
assign _305_ = ~ _304_;
assign _306_ = ra & _305_;
assign _307_ = _303_ | _306_;
assign _308_ = output_mode == 2'h1;
assign _309_ = rot & mr;
assign _310_ = output_mode == 2'h2;
assign _311_ = ~ mr;
assign _312_ = rot | _311_;
function [63:0] \28963 ;
input [63:0] a;
input [191:0] b;
input [2:0] s;
(* parallel_case *)
casez (s)
3'b??1:
\28963 = b[63:0];
3'b?1?:
\28963 = b[127:64];
3'b1??:
\28963 = b[191:128];
default:
\28963 = a;
endcase
endfunction
assign _313_ = \28963 (_312_, { _309_, _307_, _300_ }, { _310_, _308_, _301_ });
assign _314_ = output_mode == 2'h3;
assign _315_ = ~ ml;
assign _316_ = rs & _315_;
assign _317_ = | _316_;
assign _318_ = _314_ ? _317_ : 1'h0;
assign repl32 = { _001_, rs[31:0] };
assign rot_count = _003_;
assign rot1 = _007_;
assign rot2 = _011_;
assign rot = _015_;
assign sh = { _017_, shift[5:0] };
assign mb = _022_;
assign me = _028_;
assign mr = { _030_, _032_, _034_, _036_, _038_, _040_, _042_, _044_, _046_, _048_, _050_, _052_, _054_, _056_, _058_, _060_, _062_, _064_, _066_, _068_, _070_, _072_, _074_, _076_, _078_, _080_, _082_, _084_, _086_, _088_, _090_, _092_, _094_, _096_, _098_, _100_, _102_, _104_, _106_, _108_, _110_, _112_, _114_, _116_, _118_, _120_, _122_, _124_, _126_, _128_, _130_, _132_, _134_, _136_, _138_, _140_, _142_, _144_, _146_, _148_, _150_, _152_, _154_, _156_ };
assign ml = _286_;
assign output_mode = _294_;
assign result = _313_;
assign carry_out = _318_;
endmodule |
module FPUDecoder
(
io_inst,
io_sigs_cmd,
io_sigs_ldst,
io_sigs_wen,
io_sigs_ren1,
io_sigs_ren2,
io_sigs_ren3,
io_sigs_swap12,
io_sigs_swap23,
io_sigs_single,
io_sigs_fromint,
io_sigs_toint,
io_sigs_fastpipe,
io_sigs_fma,
io_sigs_div,
io_sigs_sqrt,
io_sigs_round,
io_sigs_wflags
);
input [31:0] io_inst;
output [4:0] io_sigs_cmd;
output io_sigs_ldst;
output io_sigs_wen;
output io_sigs_ren1;
output io_sigs_ren2;
output io_sigs_ren3;
output io_sigs_swap12;
output io_sigs_swap23;
output io_sigs_single;
output io_sigs_fromint;
output io_sigs_toint;
output io_sigs_fastpipe;
output io_sigs_fma;
output io_sigs_div;
output io_sigs_sqrt;
output io_sigs_round;
output io_sigs_wflags;
wire [4:0] io_sigs_cmd;
wire io_sigs_ldst,io_sigs_wen,io_sigs_ren1,io_sigs_ren2,io_sigs_ren3,io_sigs_swap12,
io_sigs_swap23,io_sigs_single,io_sigs_fromint,io_sigs_toint,io_sigs_fastpipe,
io_sigs_fma,io_sigs_div,io_sigs_sqrt,io_sigs_round,io_sigs_wflags,T3,T6,T14,T20,T50,
T54,T62,N1,N2,N4,N5,N6,N8,N9,N10,N12,N13,N14,N16,N17,N18,N19,N20,N21,N22,N23,
N24,N25,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,
N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,
N65,N66,N67,N68,N69;
assign io_sigs_cmd[4] = ~io_inst[4];
assign N1 = io_inst[28] | io_inst[29];
assign N2 = io_sigs_cmd[4] | N1;
assign io_sigs_swap23 = ~N2;
assign N4 = ~io_inst[31];
assign N5 = N18 | N4;
assign N6 = io_sigs_cmd[4] | N5;
assign io_sigs_fromint = ~N6;
assign N8 = N18 | io_inst[30];
assign N9 = N21 | N8;
assign N10 = io_sigs_cmd[4] | N9;
assign io_sigs_div = ~N10;
assign N12 = N16 | io_inst[31];
assign N13 = N18 | N12;
assign N14 = io_sigs_cmd[4] | N13;
assign io_sigs_sqrt = ~N14;
assign N16 = ~io_inst[30];
assign N17 = ~io_inst[29];
assign N18 = ~io_inst[28];
assign N19 = io_sigs_cmd[4] | N18;
assign N20 = ~N19;
assign N21 = ~io_inst[27];
assign N22 = io_sigs_cmd[4] | N21;
assign N23 = ~N22;
assign N24 = io_inst[5] | N18;
assign N25 = ~N24;
assign io_sigs_ldst = ~io_inst[6];
assign N27 = N18 | N16;
assign N28 = io_sigs_cmd[4] | N27;
assign N29 = ~N28;
assign N30 = io_inst[6] | io_inst[12];
assign N31 = ~N30;
assign N32 = io_sigs_ldst | io_inst[25];
assign N33 = ~N32;
assign N34 = io_inst[28] | N4;
assign N35 = io_sigs_cmd[4] | N34;
assign N36 = ~N35;
assign N37 = N17 | io_inst[31];
assign N38 = io_sigs_cmd[4] | N37;
assign N39 = ~N38;
assign N40 = io_inst[28] | N12;
assign N41 = io_sigs_cmd[4] | N40;
assign N42 = ~N41;
assign N43 = io_inst[13] | N16;
assign N44 = ~N43;
assign N45 = io_inst[30] | N4;
assign N46 = io_inst[2] | N45;
assign N47 = ~N46;
assign N48 = io_inst[5] | io_inst[31];
assign N49 = ~N48;
assign N50 = io_inst[4] | io_inst[5];
assign N51 = ~N50;
assign N52 = io_inst[2] | io_inst[31];
assign N53 = ~N52;
assign N54 = io_inst[2] | io_inst[28];
assign N55 = ~N54;
assign N56 = io_inst[2] | io_inst[30];
assign N57 = ~N56;
assign N58 = io_inst[29] | io_inst[30];
assign N59 = io_inst[28] | N58;
assign N60 = io_inst[2] | N59;
assign N61 = ~N60;
assign N62 = io_inst[27] | N58;
assign N63 = io_inst[2] | N62;
assign N64 = ~N63;
assign N65 = io_inst[13] | N21;
assign N66 = ~N65;
assign N67 = io_inst[2] | io_inst[29];
assign N68 = ~N67;
assign N69 = io_inst[4] | io_sigs_ldst;
assign io_sigs_ren3 = ~N69;
assign io_sigs_wflags = T3 | N47;
assign T3 = T6 | N66;
assign T6 = N68 | io_sigs_ren3;
assign io_sigs_round = T14 | N44;
assign T14 = N68 | io_sigs_ren3;
assign io_sigs_fma = T20 | io_sigs_ren3;
assign T20 = N61 | N64;
assign io_sigs_fastpipe = N39 | N42;
assign io_sigs_toint = io_inst[5] | N36;
assign io_sigs_single = N31 | N33;
assign io_sigs_swap12 = io_sigs_ldst | N29;
assign io_sigs_ren2 = T50 | io_sigs_ren3;
assign T50 = N57 | io_inst[5];
assign io_sigs_ren1 = T54 | io_sigs_ren3;
assign T54 = N53 | N55;
assign io_sigs_wen = T62 | N25;
assign T62 = N49 | N51;
assign io_sigs_cmd[0] = io_inst[2] | N23;
assign io_sigs_cmd[1] = io_inst[3] | N20;
assign io_sigs_cmd[2] = io_sigs_ldst | io_inst[29];
assign io_sigs_cmd[3] = io_sigs_ldst | io_inst[30];
endmodule |
module Queue_11
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_addr,
io_enq_bits_tag,
io_enq_bits_cmd,
io_enq_bits_typ,
io_enq_bits_kill,
io_enq_bits_phys,
io_enq_bits_data,
io_deq_ready,
io_deq_valid,
io_deq_bits_addr,
io_deq_bits_tag,
io_deq_bits_cmd,
io_deq_bits_typ,
io_deq_bits_kill,
io_deq_bits_phys,
io_deq_bits_data,
io_count
);
input [39:0] io_enq_bits_addr;
input [9:0] io_enq_bits_tag;
input [4:0] io_enq_bits_cmd;
input [2:0] io_enq_bits_typ;
input [63:0] io_enq_bits_data;
output [39:0] io_deq_bits_addr;
output [9:0] io_deq_bits_tag;
output [4:0] io_deq_bits_cmd;
output [2:0] io_deq_bits_typ;
output [63:0] io_deq_bits_data;
input clk;
input reset;
input io_enq_valid;
input io_enq_bits_kill;
input io_enq_bits_phys;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
output io_deq_bits_kill;
output io_deq_bits_phys;
output io_count;
wire io_enq_ready,io_deq_valid,io_count,N0,T2,do_enq,do_deq,empty,N1,N2,N3,N4,N5,N6;
reg [1:1] T0;
reg [39:0] io_deq_bits_addr;
reg [9:0] io_deq_bits_tag;
reg [4:0] io_deq_bits_cmd;
reg [2:0] io_deq_bits_typ;
reg io_deq_bits_kill,io_deq_bits_phys;
reg [63:0] io_deq_bits_data;
assign io_count = 1'b0;
assign T2 = do_enq ^ do_deq;
always @(posedge clk) begin
if(N3) begin
T0[1] <= N4;
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[39] <= io_enq_bits_addr[39];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[38] <= io_enq_bits_addr[38];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[37] <= io_enq_bits_addr[37];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[36] <= io_enq_bits_addr[36];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[35] <= io_enq_bits_addr[35];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[34] <= io_enq_bits_addr[34];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[33] <= io_enq_bits_addr[33];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[32] <= io_enq_bits_addr[32];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[31] <= io_enq_bits_addr[31];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[30] <= io_enq_bits_addr[30];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[29] <= io_enq_bits_addr[29];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[28] <= io_enq_bits_addr[28];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[27] <= io_enq_bits_addr[27];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[26] <= io_enq_bits_addr[26];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[25] <= io_enq_bits_addr[25];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[24] <= io_enq_bits_addr[24];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[23] <= io_enq_bits_addr[23];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[22] <= io_enq_bits_addr[22];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[21] <= io_enq_bits_addr[21];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[20] <= io_enq_bits_addr[20];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[19] <= io_enq_bits_addr[19];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[18] <= io_enq_bits_addr[18];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[17] <= io_enq_bits_addr[17];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[16] <= io_enq_bits_addr[16];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[15] <= io_enq_bits_addr[15];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[14] <= io_enq_bits_addr[14];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[13] <= io_enq_bits_addr[13];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[12] <= io_enq_bits_addr[12];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[11] <= io_enq_bits_addr[11];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[10] <= io_enq_bits_addr[10];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[9] <= io_enq_bits_addr[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[8] <= io_enq_bits_addr[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[7] <= io_enq_bits_addr[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[6] <= io_enq_bits_addr[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[5] <= io_enq_bits_addr[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[4] <= io_enq_bits_addr[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[3] <= io_enq_bits_addr[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[2] <= io_enq_bits_addr[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[1] <= io_enq_bits_addr[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[0] <= io_enq_bits_addr[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[9] <= io_enq_bits_tag[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[8] <= io_enq_bits_tag[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[7] <= io_enq_bits_tag[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[6] <= io_enq_bits_tag[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[5] <= io_enq_bits_tag[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[4] <= io_enq_bits_tag[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_tag[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cmd[4] <= io_enq_bits_cmd[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cmd[3] <= io_enq_bits_cmd[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cmd[2] <= io_enq_bits_cmd[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cmd[1] <= io_enq_bits_cmd[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cmd[0] <= io_enq_bits_cmd[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_typ[2] <= io_enq_bits_typ[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_typ[1] <= io_enq_bits_typ[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_typ[0] <= io_enq_bits_typ[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_kill <= io_enq_bits_kill;
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_phys <= io_enq_bits_phys;
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[63] <= io_enq_bits_data[63];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[62] <= io_enq_bits_data[62];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[61] <= io_enq_bits_data[61];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[60] <= io_enq_bits_data[60];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[59] <= io_enq_bits_data[59];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[58] <= io_enq_bits_data[58];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[57] <= io_enq_bits_data[57];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[56] <= io_enq_bits_data[56];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[55] <= io_enq_bits_data[55];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[54] <= io_enq_bits_data[54];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[53] <= io_enq_bits_data[53];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[52] <= io_enq_bits_data[52];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[51] <= io_enq_bits_data[51];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[50] <= io_enq_bits_data[50];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[49] <= io_enq_bits_data[49];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[48] <= io_enq_bits_data[48];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[47] <= io_enq_bits_data[47];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[46] <= io_enq_bits_data[46];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[45] <= io_enq_bits_data[45];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[44] <= io_enq_bits_data[44];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[43] <= io_enq_bits_data[43];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[42] <= io_enq_bits_data[42];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[41] <= io_enq_bits_data[41];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[40] <= io_enq_bits_data[40];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[39] <= io_enq_bits_data[39];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[38] <= io_enq_bits_data[38];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[37] <= io_enq_bits_data[37];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[36] <= io_enq_bits_data[36];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[35] <= io_enq_bits_data[35];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[34] <= io_enq_bits_data[34];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[33] <= io_enq_bits_data[33];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[32] <= io_enq_bits_data[32];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[31] <= io_enq_bits_data[31];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[30] <= io_enq_bits_data[30];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[29] <= io_enq_bits_data[29];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[28] <= io_enq_bits_data[28];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[27] <= io_enq_bits_data[27];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[26] <= io_enq_bits_data[26];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[25] <= io_enq_bits_data[25];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[24] <= io_enq_bits_data[24];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[23] <= io_enq_bits_data[23];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[22] <= io_enq_bits_data[22];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[21] <= io_enq_bits_data[21];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[20] <= io_enq_bits_data[20];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[19] <= io_enq_bits_data[19];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[18] <= io_enq_bits_data[18];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[17] <= io_enq_bits_data[17];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[16] <= io_enq_bits_data[16];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[15] <= io_enq_bits_data[15];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[14] <= io_enq_bits_data[14];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[13] <= io_enq_bits_data[13];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[12] <= io_enq_bits_data[12];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[11] <= io_enq_bits_data[11];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[10] <= io_enq_bits_data[10];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[9] <= io_enq_bits_data[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[8] <= io_enq_bits_data[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[7] <= io_enq_bits_data[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[6] <= io_enq_bits_data[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[5] <= io_enq_bits_data[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[4] <= io_enq_bits_data[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[3] <= io_enq_bits_data[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[2] <= io_enq_bits_data[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[1] <= io_enq_bits_data[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_data[0] <= io_enq_bits_data[0];
end
end
assign N3 = (N0)? 1'b1 :
(N6)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset;
assign N4 = (N0)? 1'b0 :
(N6)? do_enq : 1'b0;
assign do_enq = io_enq_ready & io_enq_valid;
assign do_deq = io_deq_ready & io_deq_valid;
assign io_deq_valid = ~empty;
assign empty = ~T0[1];
assign io_enq_ready = ~T0[1];
assign N1 = T2 | reset;
assign N2 = ~N1;
assign N5 = ~reset;
assign N6 = T2 & N5;
endmodule |
module Arbiter_2
(
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_way_en,
io_in_3_bits_addr,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_way_en,
io_in_2_bits_addr,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_way_en,
io_in_1_bits_addr,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_way_en,
io_in_0_bits_addr,
io_out_ready,
io_out_valid,
io_out_bits_way_en,
io_out_bits_addr,
io_chosen
);
input [3:0] io_in_3_bits_way_en;
input [11:0] io_in_3_bits_addr;
input [3:0] io_in_2_bits_way_en;
input [11:0] io_in_2_bits_addr;
input [3:0] io_in_1_bits_way_en;
input [11:0] io_in_1_bits_addr;
input [3:0] io_in_0_bits_way_en;
input [11:0] io_in_0_bits_addr;
output [3:0] io_out_bits_way_en;
output [11:0] io_out_bits_addr;
output [1:0] io_chosen;
input io_in_3_valid;
input io_in_2_valid;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
wire [3:0] io_out_bits_way_en,T12,T10;
wire [11:0] io_out_bits_addr,T6,T3;
wire [1:0] io_chosen,T0;
wire io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,N0,N1,N2,
N3,N4,N5,N6,N7,io_out_ready,N8,N9,N10,N11,N12,T18,T16,T22,T24,T25,T27,T28,T29;
wire [0:0] T1;
assign io_in_0_ready = io_out_ready;
assign io_chosen = (N0)? { 1'b0, 1'b0 } :
(N1)? T0 : 1'b0;
assign N0 = io_in_0_valid;
assign N1 = N8;
assign T0[0] = (N2)? 1'b1 :
(N3)? T1[0] : 1'b0;
assign N2 = io_in_1_valid;
assign N3 = T0[1];
assign io_out_bits_addr = (N4)? T6 :
(N5)? T3 : 1'b0;
assign N4 = io_chosen[1];
assign N5 = N11;
assign T3 = (N6)? io_in_1_bits_addr :
(N7)? io_in_0_bits_addr : 1'b0;
assign N6 = io_chosen[0];
assign N7 = N12;
assign T6 = (N6)? io_in_3_bits_addr :
(N7)? io_in_2_bits_addr : 1'b0;
assign io_out_bits_way_en = (N4)? T12 :
(N5)? T10 : 1'b0;
assign T10 = (N6)? io_in_1_bits_way_en :
(N7)? io_in_0_bits_way_en : 1'b0;
assign T12 = (N6)? io_in_3_bits_way_en :
(N7)? io_in_2_bits_way_en : 1'b0;
assign io_out_valid = (N4)? T18 :
(N5)? T16 : 1'b0;
assign T16 = (N6)? io_in_1_valid :
(N7)? io_in_0_valid : 1'b0;
assign T18 = (N6)? io_in_3_valid :
(N7)? io_in_2_valid : 1'b0;
assign N8 = ~io_in_0_valid;
assign N9 = ~io_in_1_valid;
assign T0[1] = N9;
assign N10 = ~io_in_2_valid;
assign T1[0] = N10;
assign N11 = ~io_chosen[1];
assign N12 = ~io_chosen[0];
assign io_in_1_ready = T22 & io_out_ready;
assign T22 = ~io_in_0_valid;
assign io_in_2_ready = T24 & io_out_ready;
assign T24 = ~T25;
assign T25 = io_in_0_valid | io_in_1_valid;
assign io_in_3_ready = T27 & io_out_ready;
assign T27 = ~T28;
assign T28 = T29 | io_in_2_valid;
assign T29 = io_in_0_valid | io_in_1_valid;
endmodule |
module SmiIONastiWriteIOConverter_0
(
clk,
reset,
io_aw_ready,
io_aw_valid,
io_aw_bits_addr,
io_aw_bits_len,
io_aw_bits_size,
io_aw_bits_burst,
io_aw_bits_lock,
io_aw_bits_cache,
io_aw_bits_prot,
io_aw_bits_qos,
io_aw_bits_region,
io_aw_bits_id,
io_aw_bits_user,
io_w_ready,
io_w_valid,
io_w_bits_data,
io_w_bits_last,
io_w_bits_strb,
io_w_bits_user,
io_b_ready,
io_b_valid,
io_b_bits_resp,
io_b_bits_id,
io_b_bits_user,
io_smi_req_ready,
io_smi_req_valid,
io_smi_req_bits_rw,
io_smi_req_bits_addr,
io_smi_req_bits_data,
io_smi_resp_ready,
io_smi_resp_valid,
io_smi_resp_bits
);
input [31:0] io_aw_bits_addr;
input [7:0] io_aw_bits_len;
input [2:0] io_aw_bits_size;
input [1:0] io_aw_bits_burst;
input [3:0] io_aw_bits_cache;
input [2:0] io_aw_bits_prot;
input [3:0] io_aw_bits_qos;
input [3:0] io_aw_bits_region;
input [5:0] io_aw_bits_id;
input [63:0] io_w_bits_data;
input [7:0] io_w_bits_strb;
output [1:0] io_b_bits_resp;
output [5:0] io_b_bits_id;
output [11:0] io_smi_req_bits_addr;
output [63:0] io_smi_req_bits_data;
input [63:0] io_smi_resp_bits;
input clk;
input reset;
input io_aw_valid;
input io_aw_bits_lock;
input io_aw_bits_user;
input io_w_valid;
input io_w_bits_last;
input io_w_bits_user;
input io_b_ready;
input io_smi_req_ready;
input io_smi_resp_valid;
output io_aw_ready;
output io_w_ready;
output io_b_valid;
output io_b_bits_user;
output io_smi_req_valid;
output io_smi_req_bits_rw;
output io_smi_resp_ready;
wire [1:0] io_b_bits_resp;
wire io_aw_ready,io_w_ready,io_b_valid,io_b_bits_user,io_smi_req_valid,
io_smi_req_bits_rw,io_smi_resp_ready,N0,N1,N2,T35,T34,T16,T12,T11,T28,T29,T32,T30,T31,N3,N4,
N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,
N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,
N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,
N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,
N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,
N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,
N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N136,N137,
N138,N140,N141,N142,N143,N144,N145,N147,N148,N149;
wire [1:1] T13;
wire [0:0] T22,T23,T24;
wire [7:0] T25;
wire [11:0] T42;
reg [2:0] state,size;
reg last,strb;
reg [63:0] io_smi_req_bits_data;
reg [11:0] io_smi_req_bits_addr;
reg [5:0] io_b_bits_id;
assign io_smi_req_bits_rw = 1'b1;
assign io_b_bits_resp[0] = 1'b0;
assign io_b_bits_resp[1] = 1'b0;
assign io_b_bits_user = 1'b0;
assign T25 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << size;
always @(posedge clk) begin
if(N9) begin
state[2] <= N12;
end
end
always @(posedge clk) begin
if(N9) begin
state[1] <= N11;
end
end
always @(posedge clk) begin
if(N9) begin
state[0] <= N10;
end
end
always @(posedge clk) begin
if(N15) begin
last <= N16;
end
end
always @(posedge clk) begin
if(N19) begin
strb <= N20;
end
end
always @(posedge clk) begin
if(T11) begin
size[2] <= io_aw_bits_size[2];
end
end
always @(posedge clk) begin
if(T11) begin
size[1] <= io_aw_bits_size[1];
end
end
always @(posedge clk) begin
if(T11) begin
size[0] <= io_aw_bits_size[0];
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[63] <= N87;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[62] <= N86;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[61] <= N85;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[60] <= N84;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[59] <= N83;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[58] <= N82;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[57] <= N81;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[56] <= N80;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[55] <= N79;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[54] <= N78;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[53] <= N77;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[52] <= N76;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[51] <= N75;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[50] <= N74;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[49] <= N73;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[48] <= N72;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[47] <= N71;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[46] <= N70;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[45] <= N69;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[44] <= N68;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[43] <= N67;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[42] <= N66;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[41] <= N65;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[40] <= N64;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[39] <= N63;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[38] <= N62;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[37] <= N61;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[36] <= N60;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[35] <= N59;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[34] <= N58;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[33] <= N57;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[32] <= N56;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[31] <= N55;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[30] <= N54;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[29] <= N53;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[28] <= N52;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[27] <= N51;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[26] <= N50;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[25] <= N49;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[24] <= N48;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[23] <= N47;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[22] <= N46;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[21] <= N45;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[20] <= N44;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[19] <= N43;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[18] <= N42;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[17] <= N41;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[16] <= N40;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[15] <= N39;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[14] <= N38;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[13] <= N37;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[12] <= N36;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[11] <= N35;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[10] <= N34;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[9] <= N33;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[8] <= N32;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[7] <= N31;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[6] <= N30;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[5] <= N29;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[4] <= N28;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[3] <= N27;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[2] <= N26;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[1] <= N25;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_data[0] <= N24;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[11] <= N102;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[10] <= N101;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[9] <= N100;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[8] <= N99;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[7] <= N98;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[6] <= N97;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[5] <= N96;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[4] <= N95;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[3] <= N94;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[2] <= N93;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[1] <= N92;
end
end
always @(posedge clk) begin
if(N90) begin
io_smi_req_bits_addr[0] <= N91;
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[5] <= io_aw_bits_id[5];
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[4] <= io_aw_bits_id[4];
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[3] <= io_aw_bits_id[3];
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[2] <= io_aw_bits_id[2];
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[1] <= io_aw_bits_id[1];
end
end
always @(posedge clk) begin
if(T11) begin
io_b_bits_id[0] <= io_aw_bits_id[0];
end
end
assign N122 = ~state[1];
assign N123 = N122 | state[2];
assign N124 = state[0] | N123;
assign N125 = ~N124;
assign N133 = state[1] | state[2];
assign N134 = state[0] | N133;
assign io_aw_ready = ~N134;
assign N136 = ~state[0];
assign N137 = state[1] | state[2];
assign N138 = N136 | N137;
assign io_w_ready = ~N138;
assign N140 = N122 | state[2];
assign N141 = state[0] | N140;
assign N142 = ~N141;
assign N143 = ~strb;
assign N144 = N122 | state[2];
assign N145 = N136 | N144;
assign io_smi_resp_ready = ~N145;
assign N147 = ~state[2];
assign N148 = state[1] | N147;
assign N149 = state[0] | N148;
assign io_b_valid = ~N149;
assign T42 = io_smi_req_bits_addr + 1'b1;
assign T23[0] = T24[0] ^ 1'b1;
assign N9 = (N0)? 1'b1 :
(N104)? 1'b1 :
(N107)? 1'b1 :
(N110)? 1'b1 :
(N113)? 1'b1 :
(N116)? 1'b1 :
(N8)? 1'b0 : 1'b0;
assign N0 = reset;
assign { N12, N11, N10 } = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N104)? { 1'b0, 1'b0, 1'b0 } :
(N107)? { 1'b1, 1'b0, 1'b0 } :
(N110)? { 1'b0, T13[1:1], 1'b1 } :
(N113)? { 1'b0, 1'b1, 1'b0 } :
(N116)? { 1'b0, 1'b0, 1'b1 } : 1'b0;
assign N15 = (N1)? 1'b1 :
(N117)? 1'b1 :
(N14)? 1'b0 : 1'b0;
assign N1 = T12;
assign N16 = (N1)? io_w_bits_last :
(N117)? 1'b0 : 1'b0;
assign N19 = (N2)? 1'b1 :
(N119)? 1'b1 :
(N18)? 1'b0 : 1'b0;
assign N2 = T28;
assign N20 = (N2)? 1'b0 :
(N119)? T22[0] : 1'b0;
assign N23 = (N2)? 1'b1 :
(N120)? 1'b1 :
(N22)? 1'b0 : 1'b0;
assign { N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24 } = (N2)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N120)? io_w_bits_data : 1'b0;
assign N90 = (N2)? 1'b1 :
(N121)? 1'b1 :
(N89)? 1'b0 : 1'b0;
assign { N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91 } = (N2)? T42 :
(N121)? io_aw_bits_addr[14:3] : 1'b0;
assign T11 = io_aw_ready & io_aw_valid;
assign T12 = io_w_ready & io_w_valid;
assign T13[1] = last;
assign T16 = N142 & N143;
assign T22[0] = T23[0] & io_w_bits_strb[0];
assign T28 = N142 & T29;
assign T29 = T32 & T30;
assign T30 = io_smi_req_ready | T31;
assign T31 = ~strb;
assign T32 = ~N143;
assign T34 = io_smi_resp_ready & io_smi_resp_valid;
assign T35 = io_b_ready & io_b_valid;
assign io_smi_req_valid = N125 & strb;
assign N3 = T35 | reset;
assign N4 = T34 | N3;
assign N5 = T16 | N4;
assign N6 = T12 | N5;
assign N7 = T11 | N6;
assign N8 = ~N7;
assign N13 = T11 | T12;
assign N14 = ~N13;
assign N17 = T12 | T28;
assign N18 = ~N17;
assign N21 = T12 | T28;
assign N22 = ~N21;
assign N88 = T11 | T28;
assign N89 = ~N88;
assign N103 = ~reset;
assign N104 = T35 & N103;
assign N105 = ~T35;
assign N106 = N103 & N105;
assign N107 = T34 & N106;
assign N108 = ~T34;
assign N109 = N106 & N108;
assign N110 = T16 & N109;
assign N111 = ~T16;
assign N112 = N109 & N111;
assign N113 = T12 & N112;
assign N114 = ~T12;
assign N115 = N112 & N114;
assign N116 = T11 & N115;
assign N117 = T11 & N114;
assign N118 = ~T28;
assign N119 = T12 & N118;
assign N120 = T12 & N118;
assign N121 = T11 & N118;
assign N126 = T25[7] | T25[6];
assign N127 = N126 | T25[5];
assign N128 = N127 | T25[4];
assign N129 = N128 | T25[3];
assign N130 = N129 | T25[2];
assign N131 = N130 | T25[1];
assign N132 = N131 | T25[0];
assign T24[0] = ~N132;
endmodule |
module Arbiter_7
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_idx,
io_in_1_bits_tag,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_idx,
io_in_0_bits_tag,
io_out_ready,
io_out_valid,
io_out_bits_idx,
io_out_bits_tag,
io_chosen
);
input [5:0] io_in_1_bits_idx;
input [19:0] io_in_1_bits_tag;
input [5:0] io_in_0_bits_idx;
input [19:0] io_in_0_bits_tag;
output [5:0] io_out_bits_idx;
output [19:0] io_out_bits_tag;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_chosen;
wire [5:0] io_out_bits_idx;
wire [19:0] io_out_bits_tag;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T5;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_tag = (N0)? io_in_1_bits_tag :
(N1)? io_in_0_bits_tag : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_idx = (N0)? io_in_1_bits_idx :
(N1)? io_in_0_bits_idx : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T5 & io_out_ready;
assign T5 = ~io_in_0_valid;
endmodule |
module SmiIONastiReadIOConverter_1
(
clk,
reset,
io_ar_ready,
io_ar_valid,
io_ar_bits_addr,
io_ar_bits_len,
io_ar_bits_size,
io_ar_bits_burst,
io_ar_bits_lock,
io_ar_bits_cache,
io_ar_bits_prot,
io_ar_bits_qos,
io_ar_bits_region,
io_ar_bits_id,
io_ar_bits_user,
io_r_ready,
io_r_valid,
io_r_bits_resp,
io_r_bits_data,
io_r_bits_last,
io_r_bits_id,
io_r_bits_user,
io_smi_req_ready,
io_smi_req_valid,
io_smi_req_bits_rw,
io_smi_req_bits_addr,
io_smi_resp_ready,
io_smi_resp_valid,
io_smi_resp_bits
);
input [31:0] io_ar_bits_addr;
input [7:0] io_ar_bits_len;
input [2:0] io_ar_bits_size;
input [1:0] io_ar_bits_burst;
input [3:0] io_ar_bits_cache;
input [2:0] io_ar_bits_prot;
input [3:0] io_ar_bits_qos;
input [3:0] io_ar_bits_region;
input [5:0] io_ar_bits_id;
output [1:0] io_r_bits_resp;
output [63:0] io_r_bits_data;
output [5:0] io_r_bits_id;
output [5:0] io_smi_req_bits_addr;
input [63:0] io_smi_resp_bits;
input clk;
input reset;
input io_ar_valid;
input io_ar_bits_lock;
input io_ar_bits_user;
input io_r_ready;
input io_smi_req_ready;
input io_smi_resp_valid;
output io_ar_ready;
output io_r_valid;
output io_r_bits_last;
output io_r_bits_user;
output io_smi_req_valid;
output io_smi_req_bits_rw;
output io_smi_resp_ready;
wire [1:0] io_r_bits_resp;
wire io_ar_ready,io_r_valid,io_r_bits_last,io_r_bits_user,io_smi_req_valid,
io_smi_req_bits_rw,io_smi_resp_ready,N0,N1,N2,N3,N4,N5,N6,T21,T5,T4,T19,T6,T14,N7,T9,N8,
T10,T15,T18,T26,T28,T31,T34,T53,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,
N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,
N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,
N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N162,N163,N164,N165,
N167,N168,N170;
wire [0:0] T20,T7,T11,T12,T55;
wire [2:0] T13;
wire [5:0] T25;
wire [7:0] T43;
wire [63:0] T48;
reg [1:0] state;
reg nWords,T56,sendDone,sendInd;
reg [5:0] io_smi_req_bits_addr,io_r_bits_id;
reg [7:0] nBeats;
reg [63:0] io_r_bits_data;
reg [5:3] T49;
assign io_r_bits_resp[0] = 1'b0;
assign io_r_bits_resp[1] = 1'b0;
assign io_r_bits_user = 1'b0;
assign io_smi_req_bits_rw = 1'b0;
assign N0 = T56 ^ nWords;
assign T6 = ~N0;
assign T10 = io_ar_bits_size < { 1'b1, 1'b1 };
assign N1 = sendInd ^ nWords;
assign T31 = ~N1;
assign T48 = io_smi_resp_bits >> { T49, 1'b0, 1'b0, 1'b0 };
always @(posedge clk) begin
if(N13) begin
state[1] <= N15;
end
end
always @(posedge clk) begin
if(N13) begin
state[0] <= N14;
end
end
always @(posedge clk) begin
if(N151) begin
nWords <= T7[0];
end
end
always @(posedge clk) begin
if(N19) begin
T56 <= N20;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[5] <= N29;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[4] <= N28;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[3] <= N27;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[2] <= N26;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[1] <= N25;
end
end
always @(posedge clk) begin
if(N23) begin
io_smi_req_bits_addr[0] <= N24;
end
end
always @(posedge clk) begin
if(N33) begin
sendDone <= N34;
end
end
always @(posedge clk) begin
if(N38) begin
sendInd <= N39;
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[5] <= io_ar_bits_id[5];
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[4] <= io_ar_bits_id[4];
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[3] <= io_ar_bits_id[3];
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[2] <= io_ar_bits_id[2];
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[1] <= io_ar_bits_id[1];
end
end
always @(posedge clk) begin
if(T4) begin
io_r_bits_id[0] <= io_ar_bits_id[0];
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[7] <= N50;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[6] <= N49;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[5] <= N48;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[4] <= N47;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[3] <= N46;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[2] <= N45;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[1] <= N44;
end
end
always @(posedge clk) begin
if(N42) begin
nBeats[0] <= N43;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[63] <= N118;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[62] <= N117;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[61] <= N116;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[60] <= N115;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[59] <= N114;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[58] <= N113;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[57] <= N112;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[56] <= N111;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[55] <= N110;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[54] <= N109;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[53] <= N108;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[52] <= N107;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[51] <= N106;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[50] <= N105;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[49] <= N104;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[48] <= N103;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[47] <= N102;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[46] <= N101;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[45] <= N100;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[44] <= N99;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[43] <= N98;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[42] <= N97;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[41] <= N96;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[40] <= N95;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[39] <= N94;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[38] <= N93;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[37] <= N92;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[36] <= N91;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[35] <= N90;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[34] <= N89;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[33] <= N88;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[32] <= N87;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[31] <= N86;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[30] <= N85;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[29] <= N84;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[28] <= N83;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[27] <= N82;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[26] <= N81;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[25] <= N80;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[24] <= N79;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[23] <= N78;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[22] <= N77;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[21] <= N76;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[20] <= N75;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[19] <= N74;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[18] <= N73;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[17] <= N72;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[16] <= N71;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[15] <= N70;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[14] <= N69;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[13] <= N68;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[12] <= N67;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[11] <= N66;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[10] <= N65;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[9] <= N64;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[8] <= N63;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[7] <= N62;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[6] <= N61;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[5] <= N60;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[4] <= N59;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[3] <= N58;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[2] <= N57;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[1] <= N56;
end
end
always @(posedge clk) begin
if(N54) begin
io_r_bits_data[0] <= N55;
end
end
always @(posedge clk) begin
if(N121) begin
T49[5] <= N124;
end
end
always @(posedge clk) begin
if(N121) begin
T49[4] <= N123;
end
end
always @(posedge clk) begin
if(N121) begin
T49[3] <= N122;
end
end
assign N154 = nBeats[6] | nBeats[7];
assign N155 = nBeats[5] | N154;
assign N156 = nBeats[4] | N155;
assign N157 = nBeats[3] | N156;
assign N158 = nBeats[2] | N157;
assign N159 = nBeats[1] | N158;
assign N160 = nBeats[0] | N159;
assign io_r_bits_last = ~N160;
assign N162 = ~state[0];
assign N163 = N162 | state[1];
assign N164 = ~N163;
assign N165 = state[0] | state[1];
assign io_ar_ready = ~N165;
assign N167 = ~state[1];
assign N168 = state[0] | N167;
assign io_r_valid = ~N168;
assign N170 = N162 | state[1];
assign io_smi_resp_ready = ~N170;
assign T13 = io_ar_bits_size - { 1'b1, 1'b1 };
assign T18 = T56 ^ 1'b1;
assign T25 = io_smi_req_bits_addr + 1'b1;
assign T34 = sendInd ^ 1'b1;
assign T43 = nBeats - 1'b1;
assign T11[0] = T12[0] ^ 1'b1;
assign T7[0] = (N2)? T11[0] :
(N3)? 1'b0 : 1'b0;
assign N2 = T14;
assign N3 = N7;
assign N13 = (N4)? 1'b1 :
(N126)? 1'b1 :
(N129)? 1'b1 :
(N132)? 1'b1 :
(N12)? 1'b0 : 1'b0;
assign N4 = reset;
assign { N15, N14 } = (N4)? { 1'b0, 1'b0 } :
(N126)? { 1'b0, T20[0:0] } :
(N129)? { 1'b1, 1'b0 } :
(N132)? { 1'b0, 1'b1 } : 1'b0;
assign N19 = (N4)? 1'b1 :
(N133)? 1'b1 :
(N135)? 1'b1 :
(N18)? 1'b0 : 1'b0;
assign N20 = (N4)? 1'b0 :
(N133)? 1'b0 :
(N135)? T18 : 1'b0;
assign N23 = (N5)? 1'b1 :
(N137)? 1'b1 :
(N22)? 1'b0 : 1'b0;
assign N5 = T26;
assign { N29, N28, N27, N26, N25, N24 } = (N5)? T25 :
(N137)? io_ar_bits_addr[8:3] : 1'b0;
assign N33 = (N4)? 1'b1 :
(N138)? 1'b1 :
(N140)? 1'b1 :
(N32)? 1'b0 : 1'b0;
assign N34 = (N4)? 1'b0 :
(N138)? 1'b0 :
(N140)? T31 : 1'b0;
assign N38 = (N4)? 1'b1 :
(N141)? 1'b1 :
(N143)? 1'b1 :
(N37)? 1'b0 : 1'b0;
assign N39 = (N4)? 1'b0 :
(N141)? 1'b0 :
(N143)? T34 : 1'b0;
assign N42 = (N6)? 1'b1 :
(N144)? 1'b1 :
(N41)? 1'b0 : 1'b0;
assign N6 = T21;
assign { N50, N49, N48, N47, N46, N45, N44, N43 } = (N6)? T43 :
(N144)? io_ar_bits_len : 1'b0;
assign N54 = (N4)? 1'b1 :
(N145)? 1'b1 :
(N147)? 1'b1 :
(N53)? 1'b0 : 1'b0;
assign { N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55 } = (N4)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N145)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N147)? T48 : 1'b0;
assign N121 = (N2)? 1'b1 :
(N149)? 1'b1 :
(N120)? 1'b0 : 1'b0;
assign { N124, N123, N122 } = (N2)? { 1'b0, 1'b0, 1'b0 } :
(N149)? io_ar_bits_addr[2:0] : 1'b0;
assign T4 = io_ar_ready & io_ar_valid;
assign T5 = T19 & T6;
assign N7 = ~T14;
assign N8 = ~T9;
assign T9 = T4 & T10;
assign T14 = T4 & T15;
assign T15 = ~T10;
assign T19 = io_smi_resp_ready & io_smi_resp_valid;
assign T20[0] = N160;
assign T21 = io_r_ready & io_r_valid;
assign T26 = io_smi_req_ready & io_smi_req_valid;
assign io_smi_req_valid = N164 & T28;
assign T28 = ~sendDone;
assign T53 = T19 & T55[0];
assign N9 = T21 | reset;
assign N10 = T5 | N9;
assign N11 = T4 | N10;
assign N12 = ~N11;
assign N16 = T21 | reset;
assign N17 = T19 | N16;
assign N18 = ~N17;
assign N21 = T4 | T26;
assign N22 = ~N21;
assign N30 = T21 | reset;
assign N31 = T26 | N30;
assign N32 = ~N31;
assign N35 = T21 | reset;
assign N36 = T26 | N35;
assign N37 = ~N36;
assign N40 = T4 | T21;
assign N41 = ~N40;
assign N51 = T21 | reset;
assign N52 = T53 | N51;
assign N53 = ~N52;
assign N119 = T9 | T14;
assign N120 = ~N119;
assign N125 = ~reset;
assign N126 = T21 & N125;
assign N127 = ~T21;
assign N128 = N125 & N127;
assign N129 = T5 & N128;
assign N130 = ~T5;
assign N131 = N128 & N130;
assign N132 = T4 & N131;
assign N133 = T21 & N125;
assign N134 = N125 & N127;
assign N135 = T19 & N134;
assign N136 = ~T26;
assign N137 = T4 & N136;
assign N138 = T21 & N125;
assign N139 = N125 & N127;
assign N140 = T26 & N139;
assign N141 = T21 & N125;
assign N142 = N125 & N127;
assign N143 = T26 & N142;
assign N144 = T4 & N127;
assign N145 = T21 & N125;
assign N146 = N125 & N127;
assign N147 = T53 & N146;
assign N148 = ~T14;
assign N149 = T9 & N148;
assign N150 = N8 & N7;
assign N151 = ~N150;
assign N152 = T13[2] | T13[1];
assign N153 = N152 | T13[0];
assign T12[0] = ~N153;
assign T55[0] = ~T56;
endmodule |
module Queue_7
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_addr,
io_enq_bits_len,
io_enq_bits_size,
io_enq_bits_burst,
io_enq_bits_lock,
io_enq_bits_cache,
io_enq_bits_prot,
io_enq_bits_qos,
io_enq_bits_region,
io_enq_bits_id,
io_enq_bits_user,
io_deq_ready,
io_deq_valid,
io_deq_bits_addr,
io_deq_bits_len,
io_deq_bits_size,
io_deq_bits_burst,
io_deq_bits_lock,
io_deq_bits_cache,
io_deq_bits_prot,
io_deq_bits_qos,
io_deq_bits_region,
io_deq_bits_id,
io_deq_bits_user,
io_count
);
input [31:0] io_enq_bits_addr;
input [7:0] io_enq_bits_len;
input [2:0] io_enq_bits_size;
input [1:0] io_enq_bits_burst;
input [3:0] io_enq_bits_cache;
input [2:0] io_enq_bits_prot;
input [3:0] io_enq_bits_qos;
input [3:0] io_enq_bits_region;
input [5:0] io_enq_bits_id;
output [31:0] io_deq_bits_addr;
output [7:0] io_deq_bits_len;
output [2:0] io_deq_bits_size;
output [1:0] io_deq_bits_burst;
output [3:0] io_deq_bits_cache;
output [2:0] io_deq_bits_prot;
output [3:0] io_deq_bits_qos;
output [3:0] io_deq_bits_region;
output [5:0] io_deq_bits_id;
input clk;
input reset;
input io_enq_valid;
input io_enq_bits_lock;
input io_enq_bits_user;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
output io_deq_bits_lock;
output io_deq_bits_user;
output io_count;
wire io_enq_ready,io_deq_valid,io_count,N0,T2,do_enq,do_deq,empty,N1,N2,N3,N4,N5,N6;
reg [1:1] T0;
reg [31:0] io_deq_bits_addr;
reg [7:0] io_deq_bits_len;
reg [2:0] io_deq_bits_size,io_deq_bits_prot;
reg [1:0] io_deq_bits_burst;
reg io_deq_bits_lock,io_deq_bits_user;
reg [3:0] io_deq_bits_cache,io_deq_bits_qos,io_deq_bits_region;
reg [5:0] io_deq_bits_id;
assign io_count = 1'b0;
assign T2 = do_enq ^ do_deq;
always @(posedge clk) begin
if(N3) begin
T0[1] <= N4;
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[31] <= io_enq_bits_addr[31];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[30] <= io_enq_bits_addr[30];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[29] <= io_enq_bits_addr[29];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[28] <= io_enq_bits_addr[28];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[27] <= io_enq_bits_addr[27];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[26] <= io_enq_bits_addr[26];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[25] <= io_enq_bits_addr[25];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[24] <= io_enq_bits_addr[24];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[23] <= io_enq_bits_addr[23];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[22] <= io_enq_bits_addr[22];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[21] <= io_enq_bits_addr[21];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[20] <= io_enq_bits_addr[20];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[19] <= io_enq_bits_addr[19];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[18] <= io_enq_bits_addr[18];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[17] <= io_enq_bits_addr[17];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[16] <= io_enq_bits_addr[16];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[15] <= io_enq_bits_addr[15];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[14] <= io_enq_bits_addr[14];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[13] <= io_enq_bits_addr[13];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[12] <= io_enq_bits_addr[12];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[11] <= io_enq_bits_addr[11];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[10] <= io_enq_bits_addr[10];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[9] <= io_enq_bits_addr[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[8] <= io_enq_bits_addr[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[7] <= io_enq_bits_addr[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[6] <= io_enq_bits_addr[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[5] <= io_enq_bits_addr[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[4] <= io_enq_bits_addr[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[3] <= io_enq_bits_addr[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[2] <= io_enq_bits_addr[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[1] <= io_enq_bits_addr[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_addr[0] <= io_enq_bits_addr[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[7] <= io_enq_bits_len[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[6] <= io_enq_bits_len[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[5] <= io_enq_bits_len[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[4] <= io_enq_bits_len[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[3] <= io_enq_bits_len[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[2] <= io_enq_bits_len[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[1] <= io_enq_bits_len[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_len[0] <= io_enq_bits_len[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_size[2] <= io_enq_bits_size[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_size[1] <= io_enq_bits_size[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_size[0] <= io_enq_bits_size[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_burst[1] <= io_enq_bits_burst[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_burst[0] <= io_enq_bits_burst[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_lock <= io_enq_bits_lock;
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cache[3] <= io_enq_bits_cache[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cache[2] <= io_enq_bits_cache[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cache[1] <= io_enq_bits_cache[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_cache[0] <= io_enq_bits_cache[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_prot[2] <= io_enq_bits_prot[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_prot[1] <= io_enq_bits_prot[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_prot[0] <= io_enq_bits_prot[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_qos[3] <= io_enq_bits_qos[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_qos[2] <= io_enq_bits_qos[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_qos[1] <= io_enq_bits_qos[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_qos[0] <= io_enq_bits_qos[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_region[3] <= io_enq_bits_region[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_region[2] <= io_enq_bits_region[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_region[1] <= io_enq_bits_region[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_region[0] <= io_enq_bits_region[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[5] <= io_enq_bits_id[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[4] <= io_enq_bits_id[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[3] <= io_enq_bits_id[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[2] <= io_enq_bits_id[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[1] <= io_enq_bits_id[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_id[0] <= io_enq_bits_id[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
io_deq_bits_user <= io_enq_bits_user;
end
end
assign N3 = (N0)? 1'b1 :
(N6)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset;
assign N4 = (N0)? 1'b0 :
(N6)? do_enq : 1'b0;
assign do_enq = io_enq_ready & io_enq_valid;
assign do_deq = io_deq_ready & io_deq_valid;
assign io_deq_valid = ~empty;
assign empty = ~T0[1];
assign io_enq_ready = ~T0[1];
assign N1 = T2 | reset;
assign N2 = ~N1;
assign N5 = ~reset;
assign N6 = T2 & N5;
endmodule |
module CompareRecFN
(
io_a,
io_b,
io_signaling,
io_lt,
io_eq,
io_gt,
io_exceptionFlags
);
input [64:0] io_a;
input [64:0] io_b;
output [4:0] io_exceptionFlags;
input io_signaling;
output io_lt;
output io_eq;
output io_gt;
wire [4:0] io_exceptionFlags;
wire io_lt,io_eq,io_gt,N0,T15,T1,T2,ordered,T9,T3,rawB_isNaN,rawA_isNaN,T22,T16,T17,
T23,T50,T29,ordered_eq,bothZeros,T30,T43,T31,bothInfs,common_eqMags,eqExps,T32,
rawA_isInf,rawB_isInf,T38,T41,T51,ordered_lt,T67,T52,T65,T53,T64,T54,T60,T55,T59,
common_ltMags,T58,T56,T57,T62,T61,T63,T66,N1,N2,N3,N4,N5,N6,N7,N8;
assign io_exceptionFlags[0] = 1'b0;
assign io_exceptionFlags[1] = 1'b0;
assign io_exceptionFlags[2] = 1'b0;
assign io_exceptionFlags[3] = 1'b0;
assign T32 = { 1'b0, 1'b1, io_a[51:0], 1'b0, 1'b0 } == { 1'b0, 1'b1, io_b[51:0], 1'b0, 1'b0 };
assign eqExps = { 1'b0, io_a[63:52] } == { 1'b0, io_b[63:52] };
assign N0 = io_a[64] ^ io_b[64];
assign T43 = ~N0;
assign T57 = { 1'b0, 1'b1, io_a[51:0], 1'b0, 1'b0 } < { 1'b0, 1'b1, io_b[51:0], 1'b0, 1'b0 };
assign T58 = $signed({ 1'b0, io_a[63:52] }) < $signed({ 1'b0, io_b[63:52] });
assign N1 = io_a[62] | io_a[63];
assign N2 = io_a[61] | N1;
assign N3 = ~N2;
assign N4 = io_b[62] | io_b[63];
assign N5 = io_b[61] | N4;
assign N6 = ~N5;
assign N7 = io_a[62] & io_a[63];
assign N8 = io_b[62] & io_b[63];
assign io_exceptionFlags[4] = T15 | T1;
assign T1 = io_signaling & T2;
assign T2 = ~ordered;
assign ordered = T9 & T3;
assign T3 = ~rawB_isNaN;
assign rawB_isNaN = N8 & io_b[61];
assign T9 = ~rawA_isNaN;
assign rawA_isNaN = N7 & io_a[61];
assign T15 = T22 | T16;
assign T16 = rawB_isNaN & T17;
assign T17 = ~io_b[51];
assign T22 = rawA_isNaN & T23;
assign T23 = ~io_a[51];
assign io_gt = T50 & T29;
assign T29 = ~ordered_eq;
assign ordered_eq = bothZeros | T30;
assign T30 = T43 & T31;
assign T31 = bothInfs | common_eqMags;
assign common_eqMags = eqExps & T32;
assign bothInfs = rawA_isInf & rawB_isInf;
assign rawB_isInf = N8 & T38;
assign T38 = ~io_b[61];
assign rawA_isInf = N7 & T41;
assign T41 = ~io_a[61];
assign bothZeros = N3 & N6;
assign T50 = ordered & T51;
assign T51 = ~ordered_lt;
assign ordered_lt = T67 & T52;
assign T52 = T65 | T53;
assign T53 = T64 & T54;
assign T54 = T60 | T55;
assign T55 = T59 & common_ltMags;
assign common_ltMags = T58 | T56;
assign T56 = eqExps & T57;
assign T59 = ~io_b[64];
assign T60 = T62 & T61;
assign T61 = ~common_eqMags;
assign T62 = io_a[64] & T63;
assign T63 = ~common_ltMags;
assign T64 = ~bothInfs;
assign T65 = io_a[64] & T66;
assign T66 = ~io_b[64];
assign T67 = ~bothZeros;
assign io_eq = ordered & ordered_eq;
assign io_lt = ordered & ordered_lt;
endmodule |
module bsg_round_robin_arb_inputs_p3
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
v_o,
tag_o,
yumi_i
);
input [2:0] reqs_i;
output [2:0] grants_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [2:0] grants_o;
wire [1:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75;
reg [1:0] last_r;
assign N10 = grants_en_i & N8;
assign N11 = N9 & N46;
assign N12 = N10 & N11;
assign N15 = grants_en_i & N13;
assign N16 = N14 & reqs_i[1];
assign N17 = N15 & N16;
assign N18 = N7 | last_r[1];
assign N19 = last_r[0] | N8;
assign N20 = N18 | N19;
assign N21 = N20 | reqs_i[1];
assign N23 = N7 | last_r[1];
assign N24 = last_r[0] | reqs_i[2];
assign N25 = reqs_i[1] | N46;
assign N26 = N23 | N24;
assign N27 = N26 | N25;
assign N29 = N7 | last_r[1];
assign N30 = N14 | N8;
assign N31 = N29 | N30;
assign N33 = grants_en_i & N13;
assign N34 = last_r[0] & N8;
assign N35 = N33 & N34;
assign N36 = N35 & reqs_i[0];
assign N37 = N7 | last_r[1];
assign N38 = N14 | reqs_i[2];
assign N39 = N9 | reqs_i[0];
assign N40 = N37 | N38;
assign N41 = N40 | N39;
assign N43 = grants_en_i & last_r[1];
assign N44 = N14 & reqs_i[0];
assign N45 = N43 & N44;
assign N47 = grants_en_i & last_r[1];
assign N48 = N14 & reqs_i[1];
assign N49 = N47 & N48;
assign N50 = N49 & N46;
assign N51 = N7 | N13;
assign N52 = last_r[0] | N8;
assign N53 = reqs_i[1] | reqs_i[0];
assign N54 = N51 | N52;
assign N55 = N54 | N53;
assign N57 = grants_en_i & last_r[1];
assign N58 = last_r[0] & reqs_i[2];
assign N59 = N57 & N58;
assign N60 = grants_en_i & last_r[1];
assign N61 = last_r[0] & reqs_i[0];
assign N62 = N60 & N61;
assign N63 = grants_en_i & last_r[1];
assign N64 = last_r[0] & reqs_i[1];
assign N65 = N63 & N64;
always @(posedge clk_i) begin
if(N72) begin
last_r[1] <= N70;
end
end
always @(posedge clk_i) begin
if(N72) begin
last_r[0] <= N69;
end
end
assign grants_o = (N7)? { 1'b0, 1'b0, 1'b0 } :
(N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1, 1'b0 } :
(N22)? { 1'b1, 1'b0, 1'b0 } :
(N28)? { 1'b0, 1'b0, 1'b1 } :
(N32)? { 1'b1, 1'b0, 1'b0 } :
(N2)? { 1'b0, 1'b0, 1'b1 } :
(N42)? { 1'b0, 1'b1, 1'b0 } :
(N3)? { 1'b0, 1'b0, 1'b1 } :
(N4)? { 1'b0, 1'b1, 1'b0 } :
(N56)? { 1'b1, 1'b0, 1'b0 } : 1'b0;
assign N0 = N12;
assign N1 = N17;
assign N2 = N36;
assign N3 = N45;
assign N4 = N50;
assign tag_o = (N7)? { 1'b0, 1'b0 } :
(N0)? { 1'b0, 1'b0 } :
(N1)? { 1'b0, 1'b1 } :
(N22)? { 1'b1, 1'b0 } :
(N28)? { 1'b0, 1'b0 } :
(N32)? { 1'b1, 1'b0 } :
(N2)? { 1'b0, 1'b0 } :
(N42)? { 1'b0, 1'b1 } :
(N3)? { 1'b0, 1'b0 } :
(N4)? { 1'b0, 1'b1 } :
(N56)? { 1'b1, 1'b0 } :
(N66)? { 1'b0, 1'b0 } : 1'b0;
assign { N70, N69 } = (N5)? { 1'b0, 1'b0 } :
(N6)? tag_o : 1'b0;
assign N5 = reset_i;
assign N6 = N68;
assign N7 = ~grants_en_i;
assign N8 = ~reqs_i[2];
assign N9 = ~reqs_i[1];
assign N13 = ~last_r[1];
assign N14 = ~last_r[0];
assign N22 = ~N21;
assign N28 = ~N27;
assign N32 = ~N31;
assign N42 = ~N41;
assign N46 = ~reqs_i[0];
assign N56 = ~N55;
assign N66 = N59 | N73;
assign N73 = N62 | N65;
assign v_o = N75 & grants_en_i;
assign N75 = N74 | reqs_i[0];
assign N74 = reqs_i[2] | reqs_i[1];
assign N67 = ~yumi_i;
assign N68 = ~reset_i;
assign N71 = N67 & N68;
assign N72 = ~N71;
endmodule |
module LockingRRArbiter_2
(
clk,
reset,
io_in_7_ready,
io_in_7_valid,
io_in_7_bits_addr_beat,
io_in_7_bits_client_xact_id,
io_in_7_bits_manager_xact_id,
io_in_7_bits_is_builtin_type,
io_in_7_bits_g_type,
io_in_7_bits_data,
io_in_7_bits_client_id,
io_in_6_ready,
io_in_6_valid,
io_in_6_bits_addr_beat,
io_in_6_bits_client_xact_id,
io_in_6_bits_manager_xact_id,
io_in_6_bits_is_builtin_type,
io_in_6_bits_g_type,
io_in_6_bits_data,
io_in_6_bits_client_id,
io_in_5_ready,
io_in_5_valid,
io_in_5_bits_addr_beat,
io_in_5_bits_client_xact_id,
io_in_5_bits_manager_xact_id,
io_in_5_bits_is_builtin_type,
io_in_5_bits_g_type,
io_in_5_bits_data,
io_in_5_bits_client_id,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_addr_beat,
io_in_4_bits_client_xact_id,
io_in_4_bits_manager_xact_id,
io_in_4_bits_is_builtin_type,
io_in_4_bits_g_type,
io_in_4_bits_data,
io_in_4_bits_client_id,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_addr_beat,
io_in_3_bits_client_xact_id,
io_in_3_bits_manager_xact_id,
io_in_3_bits_is_builtin_type,
io_in_3_bits_g_type,
io_in_3_bits_data,
io_in_3_bits_client_id,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_addr_beat,
io_in_2_bits_client_xact_id,
io_in_2_bits_manager_xact_id,
io_in_2_bits_is_builtin_type,
io_in_2_bits_g_type,
io_in_2_bits_data,
io_in_2_bits_client_id,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_beat,
io_in_1_bits_client_xact_id,
io_in_1_bits_manager_xact_id,
io_in_1_bits_is_builtin_type,
io_in_1_bits_g_type,
io_in_1_bits_data,
io_in_1_bits_client_id,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_beat,
io_in_0_bits_client_xact_id,
io_in_0_bits_manager_xact_id,
io_in_0_bits_is_builtin_type,
io_in_0_bits_g_type,
io_in_0_bits_data,
io_in_0_bits_client_id,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_client_xact_id,
io_out_bits_manager_xact_id,
io_out_bits_is_builtin_type,
io_out_bits_g_type,
io_out_bits_data,
io_out_bits_client_id,
io_chosen
);
input [1:0] io_in_7_bits_addr_beat;
input [5:0] io_in_7_bits_client_xact_id;
input [3:0] io_in_7_bits_manager_xact_id;
input [3:0] io_in_7_bits_g_type;
input [127:0] io_in_7_bits_data;
input [1:0] io_in_7_bits_client_id;
input [1:0] io_in_6_bits_addr_beat;
input [5:0] io_in_6_bits_client_xact_id;
input [3:0] io_in_6_bits_manager_xact_id;
input [3:0] io_in_6_bits_g_type;
input [127:0] io_in_6_bits_data;
input [1:0] io_in_6_bits_client_id;
input [1:0] io_in_5_bits_addr_beat;
input [5:0] io_in_5_bits_client_xact_id;
input [3:0] io_in_5_bits_manager_xact_id;
input [3:0] io_in_5_bits_g_type;
input [127:0] io_in_5_bits_data;
input [1:0] io_in_5_bits_client_id;
input [1:0] io_in_4_bits_addr_beat;
input [5:0] io_in_4_bits_client_xact_id;
input [3:0] io_in_4_bits_manager_xact_id;
input [3:0] io_in_4_bits_g_type;
input [127:0] io_in_4_bits_data;
input [1:0] io_in_4_bits_client_id;
input [1:0] io_in_3_bits_addr_beat;
input [5:0] io_in_3_bits_client_xact_id;
input [3:0] io_in_3_bits_manager_xact_id;
input [3:0] io_in_3_bits_g_type;
input [127:0] io_in_3_bits_data;
input [1:0] io_in_3_bits_client_id;
input [1:0] io_in_2_bits_addr_beat;
input [5:0] io_in_2_bits_client_xact_id;
input [3:0] io_in_2_bits_manager_xact_id;
input [3:0] io_in_2_bits_g_type;
input [127:0] io_in_2_bits_data;
input [1:0] io_in_2_bits_client_id;
input [1:0] io_in_1_bits_addr_beat;
input [5:0] io_in_1_bits_client_xact_id;
input [3:0] io_in_1_bits_manager_xact_id;
input [3:0] io_in_1_bits_g_type;
input [127:0] io_in_1_bits_data;
input [1:0] io_in_1_bits_client_id;
input [1:0] io_in_0_bits_addr_beat;
input [5:0] io_in_0_bits_client_xact_id;
input [3:0] io_in_0_bits_manager_xact_id;
input [3:0] io_in_0_bits_g_type;
input [127:0] io_in_0_bits_data;
input [1:0] io_in_0_bits_client_id;
output [1:0] io_out_bits_addr_beat;
output [5:0] io_out_bits_client_xact_id;
output [3:0] io_out_bits_manager_xact_id;
output [3:0] io_out_bits_g_type;
output [127:0] io_out_bits_data;
output [1:0] io_out_bits_client_id;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_7_valid;
input io_in_7_bits_is_builtin_type;
input io_in_6_valid;
input io_in_6_bits_is_builtin_type;
input io_in_5_valid;
input io_in_5_bits_is_builtin_type;
input io_in_4_valid;
input io_in_4_bits_is_builtin_type;
input io_in_3_valid;
input io_in_3_bits_is_builtin_type;
input io_in_2_valid;
input io_in_2_bits_is_builtin_type;
input io_in_1_valid;
input io_in_1_bits_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_is_builtin_type;
input io_out_ready;
output io_in_7_ready;
output io_in_6_ready;
output io_in_5_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_is_builtin_type;
wire [1:0] io_out_bits_addr_beat,io_out_bits_client_id,T11,T12,T35,T36,T58,T71,T64,T68,T65,
T74,T72,T155,T149,T152,T150,T158,T156;
wire [5:0] io_out_bits_client_xact_id,T141,T135,T138,T136,T144,T142;
wire [3:0] io_out_bits_manager_xact_id,io_out_bits_g_type,T99,T93,T96,T94,T102,T100,T127,
T121,T124,T122,T130,T128;
wire [127:0] io_out_bits_data,T85,T79,T82,T80,T88,T86;
wire [2:0] io_chosen,choose,T1,T2,T3,T4,T5,T6,T7,T8,T9,T10,T31,T32,T33,T34;
wire io_in_7_ready,io_in_6_ready,io_in_5_ready,io_in_4_ready,io_in_3_ready,
io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_is_builtin_type,N0,N1,
N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,
N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,
N44,N45,N46,N47,N48,N49,T28,N50,T26,N51,T24,N52,T22,N53,T20,N54,T18,N55,T14,N56,
N57,N58,N59,N60,N61,N62,N63,T15,T17,T19,T21,T23,T25,T27,T29,T45,T44,N64,T43,N65,
T42,N66,T41,N67,T40,N68,T39,N69,T38,N70,T47,T46,T53,T48,N71,T49,T61,T56,T57,T62,
N72,N73,N74,T113,T107,T110,T108,T116,T114,T169,T163,T166,T164,T172,T170,T177,
T178,T203,T179,T180,T183,T181,T182,T186,T184,T185,T189,T187,T188,T192,T190,T191,
T195,T193,T194,T198,T196,T197,T201,T199,T200,T202,T206,T207,T217,T208,T209,T210,
T211,T212,T213,T214,T215,T216,T219,T218,T222,T223,T234,T224,T225,T226,T227,T228,
T229,T230,T231,T232,T233,T236,T235,T237,T240,T241,T253,T242,T243,T244,T245,T246,
T247,T248,T249,T250,T251,T252,T255,T254,T256,T257,T260,T261,T274,T262,T263,T264,
T265,T266,T267,T268,T269,T270,T271,T272,T273,T276,T275,T277,T278,T279,T282,T283,
T297,T284,T285,T286,T287,T288,T289,T290,T291,T292,T293,T294,T295,T296,T299,T298,
T300,T301,T302,T303,T306,T307,T322,T308,T309,T310,T311,T312,T313,T314,T315,T316,
T317,T318,T319,T320,T321,T324,T323,T325,T326,T327,T328,T329,T332,T333,T349,T334,
T335,T336,T337,T338,T339,T340,T341,T342,T343,T344,T345,T346,T347,T348,T351,T350,
T352,T353,T354,T355,T356,T357,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,
N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,
N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,
N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,
N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153;
wire [0:0] T13,T37;
reg [2:0] last_grant,lockIdx;
reg locked;
reg [1:0] R59;
assign T15 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T19 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T21 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T25 = last_grant < { 1'b1, 1'b1 };
assign T57 = T58 == 1'b0;
assign T182 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T185 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T188 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T194 = last_grant < { 1'b1, 1'b1 };
assign T202 = last_grant < 1'b0;
assign T203 = last_grant < 1'b0;
assign T254 = last_grant < { 1'b1, 1'b1 };
assign T298 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T323 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T350 = last_grant < { 1'b1, 1'b1, 1'b1 };
always @(posedge clk) begin
if(N77) begin
last_grant[2] <= N80;
end
end
always @(posedge clk) begin
if(N77) begin
last_grant[1] <= N79;
end
end
always @(posedge clk) begin
if(N77) begin
last_grant[0] <= N78;
end
end
always @(posedge clk) begin
if(N83) begin
lockIdx[2] <= N86;
end
end
always @(posedge clk) begin
if(N83) begin
lockIdx[1] <= N85;
end
end
always @(posedge clk) begin
if(N83) begin
lockIdx[0] <= N84;
end
end
always @(posedge clk) begin
if(N90) begin
locked <= N91;
end
end
always @(posedge clk) begin
if(N94) begin
R59[1] <= N96;
end
end
always @(posedge clk) begin
if(N94) begin
R59[0] <= N95;
end
end
assign N105 = lockIdx[1] & lockIdx[2];
assign N106 = lockIdx[0] & N105;
assign N107 = lockIdx[1] | lockIdx[2];
assign N108 = lockIdx[0] | N107;
assign N109 = ~N108;
assign N110 = ~lockIdx[0];
assign N111 = lockIdx[1] | lockIdx[2];
assign N112 = N110 | N111;
assign N113 = ~N112;
assign N114 = ~io_out_bits_g_type[2];
assign N115 = ~io_out_bits_g_type[0];
assign N116 = N114 | io_out_bits_g_type[3];
assign N117 = io_out_bits_g_type[1] | N116;
assign N118 = N115 | N117;
assign N119 = ~N118;
assign N120 = ~lockIdx[1];
assign N121 = N120 | lockIdx[2];
assign N122 = lockIdx[0] | N121;
assign N123 = ~N122;
assign N124 = io_out_bits_g_type[2] | io_out_bits_g_type[3];
assign N125 = io_out_bits_g_type[1] | N124;
assign N126 = io_out_bits_g_type[0] | N125;
assign N127 = ~N126;
assign N128 = io_out_bits_g_type[2] | io_out_bits_g_type[3];
assign N129 = io_out_bits_g_type[1] | N128;
assign N130 = N115 | N129;
assign N131 = ~N130;
assign N132 = N120 | lockIdx[2];
assign N133 = N110 | N132;
assign N134 = ~N133;
assign N135 = ~lockIdx[2];
assign N136 = lockIdx[1] | N135;
assign N137 = lockIdx[0] | N136;
assign N138 = ~N137;
assign N139 = lockIdx[1] | N135;
assign N140 = N110 | N139;
assign N141 = ~N140;
assign N142 = N120 | N135;
assign N143 = lockIdx[0] | N142;
assign N144 = ~N143;
assign T58 = R59 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N49;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T28;
assign N3 = N50;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T26;
assign N5 = N51;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T24;
assign N7 = N52;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T22;
assign N9 = N53;
assign T4 = (N10)? { 1'b1, 1'b0, 1'b1 } :
(N11)? T5 : 1'b0;
assign N10 = T20;
assign N11 = N54;
assign T5 = (N12)? { 1'b1, 1'b1, 1'b0 } :
(N13)? T6 : 1'b0;
assign N12 = T18;
assign N13 = N55;
assign T6 = (N14)? { 1'b1, 1'b1, 1'b1 } :
(N15)? T7 : 1'b0;
assign N14 = T14;
assign N15 = N56;
assign T7 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T8 : 1'b0;
assign N16 = io_in_0_valid;
assign N17 = N57;
assign T8 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T9 : 1'b0;
assign N18 = io_in_1_valid;
assign N19 = N58;
assign T9 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? T10 : 1'b0;
assign N20 = io_in_2_valid;
assign N21 = N59;
assign T10[1:0] = (N22)? { 1'b1, 1'b1 } :
(N23)? T11 : 1'b0;
assign N22 = io_in_3_valid;
assign N23 = T10[2];
assign T11 = (N24)? { 1'b0, 1'b0 } :
(N25)? T12 : 1'b0;
assign N24 = io_in_4_valid;
assign N25 = N61;
assign T12[0] = (N26)? 1'b1 :
(N27)? T13[0] : 1'b0;
assign N26 = io_in_5_valid;
assign N27 = T12[1];
assign T31 = (N28)? { 1'b0, 1'b0, 1'b0 } :
(N29)? T32 : 1'b0;
assign N28 = T44;
assign N29 = N64;
assign T32 = (N30)? { 1'b0, 1'b0, 1'b1 } :
(N31)? T33 : 1'b0;
assign N30 = T43;
assign N31 = N65;
assign T33 = (N32)? { 1'b0, 1'b1, 1'b0 } :
(N33)? T34 : 1'b0;
assign N32 = T42;
assign N33 = N66;
assign T34[1:0] = (N34)? { 1'b1, 1'b1 } :
(N35)? T35 : 1'b0;
assign N34 = T41;
assign N35 = T34[2];
assign T35 = (N36)? { 1'b0, 1'b0 } :
(N37)? T36 : 1'b0;
assign N36 = T40;
assign N37 = N68;
assign T36[0] = (N38)? 1'b1 :
(N39)? T37[0] : 1'b0;
assign N38 = T39;
assign N39 = T36[1];
assign T48 = (N40)? N119 :
(N41)? T49 : 1'b0;
assign N40 = io_out_bits_is_builtin_type;
assign N41 = N71;
assign io_out_bits_client_id = (N42)? T71 :
(N43)? T64 : 1'b0;
assign N42 = io_chosen[2];
assign N43 = N72;
assign T64 = (N44)? T68 :
(N45)? T65 : 1'b0;
assign N44 = io_chosen[1];
assign N45 = N73;
assign T65 = (N46)? io_in_1_bits_client_id :
(N47)? io_in_0_bits_client_id : 1'b0;
assign N46 = io_chosen[0];
assign N47 = N74;
assign T68 = (N46)? io_in_3_bits_client_id :
(N47)? io_in_2_bits_client_id : 1'b0;
assign T71 = (N44)? T74 :
(N45)? T72 : 1'b0;
assign T72 = (N46)? io_in_5_bits_client_id :
(N47)? io_in_4_bits_client_id : 1'b0;
assign T74 = (N46)? io_in_7_bits_client_id :
(N47)? io_in_6_bits_client_id : 1'b0;
assign io_out_bits_data = (N42)? T85 :
(N43)? T79 : 1'b0;
assign T79 = (N44)? T82 :
(N45)? T80 : 1'b0;
assign T80 = (N46)? io_in_1_bits_data :
(N47)? io_in_0_bits_data : 1'b0;
assign T82 = (N46)? io_in_3_bits_data :
(N47)? io_in_2_bits_data : 1'b0;
assign T85 = (N44)? T88 :
(N45)? T86 : 1'b0;
assign T86 = (N46)? io_in_5_bits_data :
(N47)? io_in_4_bits_data : 1'b0;
assign T88 = (N46)? io_in_7_bits_data :
(N47)? io_in_6_bits_data : 1'b0;
assign io_out_bits_g_type = (N42)? T99 :
(N43)? T93 : 1'b0;
assign T93 = (N44)? T96 :
(N45)? T94 : 1'b0;
assign T94 = (N46)? io_in_1_bits_g_type :
(N47)? io_in_0_bits_g_type : 1'b0;
assign T96 = (N46)? io_in_3_bits_g_type :
(N47)? io_in_2_bits_g_type : 1'b0;
assign T99 = (N44)? T102 :
(N45)? T100 : 1'b0;
assign T100 = (N46)? io_in_5_bits_g_type :
(N47)? io_in_4_bits_g_type : 1'b0;
assign T102 = (N46)? io_in_7_bits_g_type :
(N47)? io_in_6_bits_g_type : 1'b0;
assign io_out_bits_is_builtin_type = (N42)? T113 :
(N43)? T107 : 1'b0;
assign T107 = (N44)? T110 :
(N45)? T108 : 1'b0;
assign T108 = (N46)? io_in_1_bits_is_builtin_type :
(N47)? io_in_0_bits_is_builtin_type : 1'b0;
assign T110 = (N46)? io_in_3_bits_is_builtin_type :
(N47)? io_in_2_bits_is_builtin_type : 1'b0;
assign T113 = (N44)? T116 :
(N45)? T114 : 1'b0;
assign T114 = (N46)? io_in_5_bits_is_builtin_type :
(N47)? io_in_4_bits_is_builtin_type : 1'b0;
assign T116 = (N46)? io_in_7_bits_is_builtin_type :
(N47)? io_in_6_bits_is_builtin_type : 1'b0;
assign io_out_bits_manager_xact_id = (N42)? T127 :
(N43)? T121 : 1'b0;
assign T121 = (N44)? T124 :
(N45)? T122 : 1'b0;
assign T122 = (N46)? io_in_1_bits_manager_xact_id :
(N47)? io_in_0_bits_manager_xact_id : 1'b0;
assign T124 = (N46)? io_in_3_bits_manager_xact_id :
(N47)? io_in_2_bits_manager_xact_id : 1'b0;
assign T127 = (N44)? T130 :
(N45)? T128 : 1'b0;
assign T128 = (N46)? io_in_5_bits_manager_xact_id :
(N47)? io_in_4_bits_manager_xact_id : 1'b0;
assign T130 = (N46)? io_in_7_bits_manager_xact_id :
(N47)? io_in_6_bits_manager_xact_id : 1'b0;
assign io_out_bits_client_xact_id = (N42)? T141 :
(N43)? T135 : 1'b0;
assign T135 = (N44)? T138 :
(N45)? T136 : 1'b0;
assign T136 = (N46)? io_in_1_bits_client_xact_id :
(N47)? io_in_0_bits_client_xact_id : 1'b0;
assign T138 = (N46)? io_in_3_bits_client_xact_id :
(N47)? io_in_2_bits_client_xact_id : 1'b0;
assign T141 = (N44)? T144 :
(N45)? T142 : 1'b0;
assign T142 = (N46)? io_in_5_bits_client_xact_id :
(N47)? io_in_4_bits_client_xact_id : 1'b0;
assign T144 = (N46)? io_in_7_bits_client_xact_id :
(N47)? io_in_6_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_beat = (N42)? T155 :
(N43)? T149 : 1'b0;
assign T149 = (N44)? T152 :
(N45)? T150 : 1'b0;
assign T150 = (N46)? io_in_1_bits_addr_beat :
(N47)? io_in_0_bits_addr_beat : 1'b0;
assign T152 = (N46)? io_in_3_bits_addr_beat :
(N47)? io_in_2_bits_addr_beat : 1'b0;
assign T155 = (N44)? T158 :
(N45)? T156 : 1'b0;
assign T156 = (N46)? io_in_5_bits_addr_beat :
(N47)? io_in_4_bits_addr_beat : 1'b0;
assign T158 = (N46)? io_in_7_bits_addr_beat :
(N47)? io_in_6_bits_addr_beat : 1'b0;
assign io_out_valid = (N42)? T169 :
(N43)? T163 : 1'b0;
assign T163 = (N44)? T166 :
(N45)? T164 : 1'b0;
assign T164 = (N46)? io_in_1_valid :
(N47)? io_in_0_valid : 1'b0;
assign T166 = (N46)? io_in_3_valid :
(N47)? io_in_2_valid : 1'b0;
assign T169 = (N44)? T172 :
(N45)? T170 : 1'b0;
assign T170 = (N46)? io_in_5_valid :
(N47)? io_in_4_valid : 1'b0;
assign T172 = (N46)? io_in_7_valid :
(N47)? io_in_6_valid : 1'b0;
assign T177 = (N0)? N109 :
(N1)? T178 : 1'b0;
assign T206 = (N0)? N113 :
(N1)? T207 : 1'b0;
assign T222 = (N0)? N123 :
(N1)? T223 : 1'b0;
assign T240 = (N0)? N134 :
(N1)? T241 : 1'b0;
assign T260 = (N0)? N138 :
(N1)? T261 : 1'b0;
assign T282 = (N0)? N141 :
(N1)? T283 : 1'b0;
assign T306 = (N0)? N144 :
(N1)? T307 : 1'b0;
assign T332 = (N0)? N106 :
(N1)? T333 : 1'b0;
assign N77 = (N48)? 1'b1 :
(N98)? 1'b1 :
(N76)? 1'b0 : 1'b0;
assign N48 = reset;
assign { N80, N79, N78 } = (N48)? { 1'b0, 1'b0, 1'b0 } :
(N98)? io_chosen : 1'b0;
assign N83 = (N48)? 1'b1 :
(N99)? 1'b1 :
(N82)? 1'b0 : 1'b0;
assign { N86, N85, N84 } = (N48)? { 1'b1, 1'b1, 1'b1 } :
(N99)? T31 : 1'b0;
assign N90 = (N48)? 1'b1 :
(N100)? 1'b1 :
(N103)? 1'b1 :
(N89)? 1'b0 : 1'b0;
assign N91 = (N48)? 1'b0 :
(N100)? 1'b0 :
(N103)? T56 : 1'b0;
assign N94 = (N48)? 1'b1 :
(N104)? 1'b1 :
(N93)? 1'b0 : 1'b0;
assign { N96, N95 } = (N48)? { 1'b0, 1'b0 } :
(N104)? T58 : 1'b0;
assign N49 = ~locked;
assign N50 = ~T28;
assign N51 = ~T26;
assign N52 = ~T24;
assign N53 = ~T22;
assign N54 = ~T20;
assign N55 = ~T18;
assign N56 = ~T14;
assign N57 = ~io_in_0_valid;
assign N58 = ~io_in_1_valid;
assign N59 = ~io_in_2_valid;
assign N60 = ~io_in_3_valid;
assign T10[2] = N60;
assign N61 = ~io_in_4_valid;
assign N62 = ~io_in_5_valid;
assign T12[1] = N62;
assign N63 = ~io_in_6_valid;
assign T13[0] = N63;
assign T14 = io_in_7_valid & T15;
assign T17 = io_out_ready & io_out_valid;
assign T18 = io_in_6_valid & T19;
assign T20 = io_in_5_valid & T21;
assign T22 = io_in_4_valid & T23;
assign T23 = ~last_grant[2];
assign T24 = io_in_3_valid & T25;
assign T26 = io_in_2_valid & T27;
assign T27 = ~N145;
assign N145 = last_grant[2] | last_grant[1];
assign T28 = io_in_1_valid & T29;
assign T29 = ~N147;
assign N147 = N146 | last_grant[0];
assign N146 = last_grant[2] | last_grant[1];
assign N64 = ~T44;
assign N65 = ~T43;
assign N66 = ~T42;
assign N67 = ~T41;
assign T34[2] = N67;
assign N68 = ~T40;
assign N69 = ~T39;
assign T36[1] = N69;
assign N70 = ~T38;
assign T37[0] = N70;
assign T38 = io_in_6_ready & io_in_6_valid;
assign T39 = io_in_5_ready & io_in_5_valid;
assign T40 = io_in_4_ready & io_in_4_valid;
assign T41 = io_in_3_ready & io_in_3_valid;
assign T42 = io_in_2_ready & io_in_2_valid;
assign T43 = io_in_1_ready & io_in_1_valid;
assign T44 = io_in_0_ready & io_in_0_valid;
assign T45 = T47 & T46;
assign T46 = ~locked;
assign T47 = T53 & T48;
assign N71 = ~io_out_bits_is_builtin_type;
assign T49 = N127 | N131;
assign T53 = io_out_valid & io_out_ready;
assign T56 = ~T57;
assign T61 = T53 & T62;
assign T62 = ~T48;
assign N72 = ~io_chosen[2];
assign N73 = ~io_chosen[1];
assign N74 = ~io_chosen[0];
assign io_in_0_ready = T177 & io_out_ready;
assign T178 = T203 | T179;
assign T179 = ~T180;
assign T180 = T183 | T181;
assign T181 = io_in_7_valid & T182;
assign T183 = T186 | T184;
assign T184 = io_in_6_valid & T185;
assign T186 = T189 | T187;
assign T187 = io_in_5_valid & T188;
assign T189 = T192 | T190;
assign T190 = io_in_4_valid & T191;
assign T191 = ~last_grant[2];
assign T192 = T195 | T193;
assign T193 = io_in_3_valid & T194;
assign T195 = T198 | T196;
assign T196 = io_in_2_valid & T197;
assign T197 = ~N148;
assign N148 = last_grant[2] | last_grant[1];
assign T198 = T201 | T199;
assign T199 = io_in_1_valid & T200;
assign T200 = ~N150;
assign N150 = N149 | last_grant[0];
assign N149 = last_grant[2] | last_grant[1];
assign T201 = io_in_0_valid & T202;
assign io_in_1_ready = T206 & io_out_ready;
assign T207 = T217 | T208;
assign T208 = ~T209;
assign T209 = T210 | io_in_0_valid;
assign T210 = T211 | T181;
assign T211 = T212 | T184;
assign T212 = T213 | T187;
assign T213 = T214 | T190;
assign T214 = T215 | T193;
assign T215 = T216 | T196;
assign T216 = T201 | T199;
assign T217 = T219 & T218;
assign T218 = ~N152;
assign N152 = N151 | last_grant[0];
assign N151 = last_grant[2] | last_grant[1];
assign T219 = ~T201;
assign io_in_2_ready = T222 & io_out_ready;
assign T223 = T234 | T224;
assign T224 = ~T225;
assign T225 = T226 | io_in_1_valid;
assign T226 = T227 | io_in_0_valid;
assign T227 = T228 | T181;
assign T228 = T229 | T184;
assign T229 = T230 | T187;
assign T230 = T231 | T190;
assign T231 = T232 | T193;
assign T232 = T233 | T196;
assign T233 = T201 | T199;
assign T234 = T236 & T235;
assign T235 = ~N153;
assign N153 = last_grant[2] | last_grant[1];
assign T236 = ~T237;
assign T237 = T201 | T199;
assign io_in_3_ready = T240 & io_out_ready;
assign T241 = T253 | T242;
assign T242 = ~T243;
assign T243 = T244 | io_in_2_valid;
assign T244 = T245 | io_in_1_valid;
assign T245 = T246 | io_in_0_valid;
assign T246 = T247 | T181;
assign T247 = T248 | T184;
assign T248 = T249 | T187;
assign T249 = T250 | T190;
assign T250 = T251 | T193;
assign T251 = T252 | T196;
assign T252 = T201 | T199;
assign T253 = T255 & T254;
assign T255 = ~T256;
assign T256 = T257 | T196;
assign T257 = T201 | T199;
assign io_in_4_ready = T260 & io_out_ready;
assign T261 = T274 | T262;
assign T262 = ~T263;
assign T263 = T264 | io_in_3_valid;
assign T264 = T265 | io_in_2_valid;
assign T265 = T266 | io_in_1_valid;
assign T266 = T267 | io_in_0_valid;
assign T267 = T268 | T181;
assign T268 = T269 | T184;
assign T269 = T270 | T187;
assign T270 = T271 | T190;
assign T271 = T272 | T193;
assign T272 = T273 | T196;
assign T273 = T201 | T199;
assign T274 = T276 & T275;
assign T275 = ~last_grant[2];
assign T276 = ~T277;
assign T277 = T278 | T193;
assign T278 = T279 | T196;
assign T279 = T201 | T199;
assign io_in_5_ready = T282 & io_out_ready;
assign T283 = T297 | T284;
assign T284 = ~T285;
assign T285 = T286 | io_in_4_valid;
assign T286 = T287 | io_in_3_valid;
assign T287 = T288 | io_in_2_valid;
assign T288 = T289 | io_in_1_valid;
assign T289 = T290 | io_in_0_valid;
assign T290 = T291 | T181;
assign T291 = T292 | T184;
assign T292 = T293 | T187;
assign T293 = T294 | T190;
assign T294 = T295 | T193;
assign T295 = T296 | T196;
assign T296 = T201 | T199;
assign T297 = T299 & T298;
assign T299 = ~T300;
assign T300 = T301 | T190;
assign T301 = T302 | T193;
assign T302 = T303 | T196;
assign T303 = T201 | T199;
assign io_in_6_ready = T306 & io_out_ready;
assign T307 = T322 | T308;
assign T308 = ~T309;
assign T309 = T310 | io_in_5_valid;
assign T310 = T311 | io_in_4_valid;
assign T311 = T312 | io_in_3_valid;
assign T312 = T313 | io_in_2_valid;
assign T313 = T314 | io_in_1_valid;
assign T314 = T315 | io_in_0_valid;
assign T315 = T316 | T181;
assign T316 = T317 | T184;
assign T317 = T318 | T187;
assign T318 = T319 | T190;
assign T319 = T320 | T193;
assign T320 = T321 | T196;
assign T321 = T201 | T199;
assign T322 = T324 & T323;
assign T324 = ~T325;
assign T325 = T326 | T187;
assign T326 = T327 | T190;
assign T327 = T328 | T193;
assign T328 = T329 | T196;
assign T329 = T201 | T199;
assign io_in_7_ready = T332 & io_out_ready;
assign T333 = T349 | T334;
assign T334 = ~T335;
assign T335 = T336 | io_in_6_valid;
assign T336 = T337 | io_in_5_valid;
assign T337 = T338 | io_in_4_valid;
assign T338 = T339 | io_in_3_valid;
assign T339 = T340 | io_in_2_valid;
assign T340 = T341 | io_in_1_valid;
assign T341 = T342 | io_in_0_valid;
assign T342 = T343 | T181;
assign T343 = T344 | T184;
assign T344 = T345 | T187;
assign T345 = T346 | T190;
assign T346 = T347 | T193;
assign T347 = T348 | T196;
assign T348 = T201 | T199;
assign T349 = T351 & T350;
assign T351 = ~T352;
assign T352 = T353 | T184;
assign T353 = T354 | T187;
assign T354 = T355 | T190;
assign T355 = T356 | T193;
assign T356 = T357 | T196;
assign T357 = T201 | T199;
assign N75 = T17 | reset;
assign N76 = ~N75;
assign N81 = T45 | reset;
assign N82 = ~N81;
assign N87 = T61 | reset;
assign N88 = T47 | N87;
assign N89 = ~N88;
assign N92 = T47 | reset;
assign N93 = ~N92;
assign N97 = ~reset;
assign N98 = T17 & N97;
assign N99 = T45 & N97;
assign N100 = T61 & N97;
assign N101 = ~T61;
assign N102 = N97 & N101;
assign N103 = T47 & N102;
assign N104 = T47 & N97;
endmodule |
module Arbiter_8
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr,
io_in_1_bits_tag,
io_in_1_bits_cmd,
io_in_1_bits_typ,
io_in_1_bits_kill,
io_in_1_bits_phys,
io_in_1_bits_sdq_id,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_tag,
io_in_0_bits_cmd,
io_in_0_bits_typ,
io_in_0_bits_kill,
io_in_0_bits_phys,
io_in_0_bits_sdq_id,
io_out_ready,
io_out_valid,
io_out_bits_addr,
io_out_bits_tag,
io_out_bits_cmd,
io_out_bits_typ,
io_out_bits_kill,
io_out_bits_phys,
io_out_bits_sdq_id,
io_chosen
);
input [39:0] io_in_1_bits_addr;
input [9:0] io_in_1_bits_tag;
input [4:0] io_in_1_bits_cmd;
input [2:0] io_in_1_bits_typ;
input [4:0] io_in_1_bits_sdq_id;
input [39:0] io_in_0_bits_addr;
input [9:0] io_in_0_bits_tag;
input [4:0] io_in_0_bits_cmd;
input [2:0] io_in_0_bits_typ;
input [4:0] io_in_0_bits_sdq_id;
output [39:0] io_out_bits_addr;
output [9:0] io_out_bits_tag;
output [4:0] io_out_bits_cmd;
output [2:0] io_out_bits_typ;
output [4:0] io_out_bits_sdq_id;
input io_in_1_valid;
input io_in_1_bits_kill;
input io_in_1_bits_phys;
input io_in_0_valid;
input io_in_0_bits_kill;
input io_in_0_bits_phys;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_kill;
output io_out_bits_phys;
output io_chosen;
wire [39:0] io_out_bits_addr;
wire [9:0] io_out_bits_tag;
wire [4:0] io_out_bits_cmd,io_out_bits_sdq_id;
wire [2:0] io_out_bits_typ;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_kill,io_out_bits_phys,
io_chosen,N0,N1,io_out_ready,T10;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_sdq_id = (N0)? io_in_1_bits_sdq_id :
(N1)? io_in_0_bits_sdq_id : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_phys = (N0)? io_in_1_bits_phys :
(N1)? io_in_0_bits_phys : 1'b0;
assign io_out_bits_kill = (N0)? io_in_1_bits_kill :
(N1)? io_in_0_bits_kill : 1'b0;
assign io_out_bits_typ = (N0)? io_in_1_bits_typ :
(N1)? io_in_0_bits_typ : 1'b0;
assign io_out_bits_cmd = (N0)? io_in_1_bits_cmd :
(N1)? io_in_0_bits_cmd : 1'b0;
assign io_out_bits_tag = (N0)? io_in_1_bits_tag :
(N1)? io_in_0_bits_tag : 1'b0;
assign io_out_bits_addr = (N0)? io_in_1_bits_addr :
(N1)? io_in_0_bits_addr : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T10 & io_out_ready;
assign T10 = ~io_in_0_valid;
endmodule |
module AMOALU
(
io_addr,
io_cmd,
io_typ,
io_lhs,
io_rhs,
io_out
);
input [5:0] io_addr;
input [4:0] io_cmd;
input [2:0] io_typ;
input [63:0] io_lhs;
input [63:0] io_rhs;
output [63:0] io_out;
wire [63:0] io_out,T49,T1,T2,out,adder_out,T50,T111,T51,T109,T52,T107,T53,T54,T116,T113,
mask;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,wmask_63,wmask_48,wmask_47,wmask_40,
wmask_39,wmask_32,wmask_31,wmask_24,wmask_23,wmask_16,wmask_15,wmask_8,wmask_7,
wmask_0,N33,N34,T16,T28,T69,N35,T55_63_,T55_62_,T55_61_,T55_60_,T55_59_,T55_58_,
T55_57_,T55_56_,T55_55_,T55_54_,T55_53_,T55_52_,T55_51_,T55_50_,T55_49_,T55_48_,
T55_47_,T55_46_,T55_45_,T55_44_,T55_43_,T55_42_,T55_41_,T55_40_,T55_39_,T55_38_,
T55_37_,T55_36_,T55_35_,T55_34_,T55_33_,T55_32_,T55_31_,T55_30_,T55_29_,T55_28_,
T55_27_,T55_26_,T55_25_,T55_24_,T55_23_,T55_22_,T55_21_,T55_20_,T55_19_,T55_18_,
T55_17_,T55_16_,less,N36,min,max,T106,N37,lt,T74,sgned,N38,cmp_lhs,cmp_rhs,T80,N39,
word,T81,T84,T86,T91,N40,T92,N41,T104,T96,lt_hi,T97,eq_hi,lt_lo,N42,N43,N44,N45,
N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,
N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,
N86,N87,N88,N89,N90;
wire [56:55] wmask;
wire [0:0] T119;
wire [7:1] T8;
wire [3:0] T10,T29;
wire [1:1] T12,T21;
wire [1:0] T23;
wire [3:3] T27;
wire [63:32] T56,rhs;
assign T28 = { 1'b1, 1'b1 } <= io_typ[1:0];
assign lt_lo = io_lhs[31:0] < io_rhs[31:0];
assign eq_hi = io_lhs[63:32] == rhs;
assign lt_hi = io_lhs[63:32] < rhs;
assign N0 = cmp_lhs ^ cmp_rhs;
assign T106 = ~N0;
assign N42 = ~io_cmd[3];
assign N43 = N42 | io_cmd[4];
assign N44 = io_cmd[2] | N43;
assign N45 = io_cmd[1] | N44;
assign N46 = io_cmd[0] | N45;
assign N47 = ~N46;
assign N48 = ~io_cmd[1];
assign N49 = ~io_cmd[0];
assign N50 = N48 | N44;
assign N51 = N49 | N50;
assign N52 = ~N51;
assign N53 = io_cmd[0] | N50;
assign N54 = ~N53;
assign N55 = ~io_addr[0];
assign N56 = N49 | N45;
assign N57 = ~N56;
assign N58 = io_typ[0] | io_typ[1];
assign N59 = ~N58;
assign N60 = ~io_typ[0];
assign N61 = N60 | io_typ[1];
assign N62 = ~N61;
assign N63 = ~io_cmd[2];
assign N64 = N63 | N43;
assign N65 = io_cmd[1] | N64;
assign N66 = io_cmd[0] | N65;
assign N67 = ~N66;
assign N68 = N48 | N64;
assign N69 = io_cmd[0] | N68;
assign N70 = ~N69;
assign N71 = N49 | N65;
assign N72 = ~N71;
assign N73 = N49 | N68;
assign N74 = ~N73;
assign N75 = ~io_typ[1];
assign N76 = io_typ[0] | N75;
assign N77 = ~N76;
assign N78 = ~io_typ[2];
assign N79 = io_typ[1] | N78;
assign N80 = io_typ[0] | N79;
assign N81 = ~N80;
assign N82 = io_typ[1] | io_typ[2];
assign N83 = io_typ[0] | N82;
assign N84 = ~N83;
assign N85 = N75 | io_typ[2];
assign N86 = io_typ[0] | N85;
assign N87 = ~N86;
assign N88 = N75 | N78;
assign N89 = io_typ[0] | N88;
assign N90 = ~N89;
assign adder_out = T116 + T113;
assign { wmask_7, wmask_0 } = 1'b0 - T119[0];
assign { wmask_15, wmask_8 } = 1'b0 - T8[1];
assign { wmask_23, wmask_16 } = 1'b0 - T8[2];
assign { wmask_31, wmask_24 } = 1'b0 - T8[3];
assign { wmask_39, wmask_32 } = 1'b0 - T8[4];
assign { wmask_47, wmask_40 } = 1'b0 - T8[5];
assign { wmask[55:55], wmask_48 } = 1'b0 - T8[6];
assign { wmask_63, wmask[56:56] } = 1'b0 - T8[7];
assign { T8[3:1], T119[0:0] } = (N1)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N2)? T10 : 1'b0;
assign N1 = io_addr[2];
assign N2 = N33;
assign T10[1:0] = (N3)? { 1'b0, 1'b0 } :
(N4)? { T12[1:1], N55 } : 1'b0;
assign N3 = io_addr[1];
assign N4 = N34;
assign T23 = (N3)? { T12[1:1], N55 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign T29 = (N1)? T10 :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign out = (N5)? adder_out :
(N6)? T50 : 1'b0;
assign N5 = N47;
assign N6 = N46;
assign T50 = (N7)? T111 :
(N8)? T51 : 1'b0;
assign N7 = N52;
assign N8 = N51;
assign T51 = (N9)? T109 :
(N10)? T52 : 1'b0;
assign N9 = N54;
assign N10 = N53;
assign T52 = (N11)? T107 :
(N12)? T53 : 1'b0;
assign N11 = N57;
assign N12 = N56;
assign T53 = (N13)? io_lhs :
(N14)? T54 : 1'b0;
assign N13 = T69;
assign N14 = N35;
assign T54 = (N15)? { io_rhs[7:0], io_rhs[7:0], io_rhs[7:0], io_rhs[7:0], io_rhs[7:0], io_rhs[7:0], io_rhs[7:0], io_rhs[7:0] } :
(N16)? { T55_63_, T55_62_, T55_61_, T55_60_, T55_59_, T55_58_, T55_57_, T55_56_, T55_55_, T55_54_, T55_53_, T55_52_, T55_51_, T55_50_, T55_49_, T55_48_, T55_47_, T55_46_, T55_45_, T55_44_, T55_43_, T55_42_, T55_41_, T55_40_, T55_39_, T55_38_, T55_37_, T55_36_, T55_35_, T55_34_, T55_33_, T55_32_, T55_31_, T55_30_, T55_29_, T55_28_, T55_27_, T55_26_, T55_25_, T55_24_, T55_23_, T55_22_, T55_21_, T55_20_, T55_19_, T55_18_, T55_17_, T55_16_, io_rhs[15:0] } : 1'b0;
assign N15 = N59;
assign N16 = N58;
assign { T55_63_, T55_62_, T55_61_, T55_60_, T55_59_, T55_58_, T55_57_, T55_56_, T55_55_, T55_54_, T55_53_, T55_52_, T55_51_, T55_50_, T55_49_, T55_48_, T55_47_, T55_46_, T55_45_, T55_44_, T55_43_, T55_42_, T55_41_, T55_40_, T55_39_, T55_38_, T55_37_, T55_36_, T55_35_, T55_34_, T55_33_, T55_32_, T55_31_, T55_30_, T55_29_, T55_28_, T55_27_, T55_26_, T55_25_, T55_24_, T55_23_, T55_22_, T55_21_, T55_20_, T55_19_, T55_18_, T55_17_, T55_16_ } = (N17)? { io_rhs[15:0], io_rhs[15:0], io_rhs[15:0] } :
(N18)? { T56, io_rhs[31:16] } : 1'b0;
assign N17 = N62;
assign N18 = N61;
assign T56 = (N19)? io_rhs[31:0] :
(N20)? io_rhs[63:32] : 1'b0;
assign N19 = N77;
assign N20 = N76;
assign T69 = (N21)? min :
(N22)? max : 1'b0;
assign N21 = less;
assign N22 = N36;
assign less = (N23)? lt :
(N24)? T74 : 1'b0;
assign N23 = T106;
assign N24 = N37;
assign T74 = (N25)? cmp_lhs :
(N26)? cmp_rhs : 1'b0;
assign N25 = sgned;
assign N26 = N38;
assign cmp_rhs = (N27)? io_rhs[31] :
(N28)? rhs[63] : 1'b0;
assign N27 = T80;
assign N28 = N39;
assign rhs = (N19)? io_rhs[31:0] :
(N20)? io_rhs[63:32] : 1'b0;
assign cmp_lhs = (N29)? io_lhs[31] :
(N30)? io_lhs[63] : 1'b0;
assign N29 = T91;
assign N30 = N40;
assign lt = (N31)? T104 :
(N32)? T96 : 1'b0;
assign N31 = word;
assign N32 = N41;
assign T104 = (N1)? lt_hi :
(N2)? lt_lo : 1'b0;
assign io_out[63] = T49[63] | T1[63];
assign io_out[62] = T49[62] | T1[62];
assign io_out[61] = T49[61] | T1[61];
assign io_out[60] = T49[60] | T1[60];
assign io_out[59] = T49[59] | T1[59];
assign io_out[58] = T49[58] | T1[58];
assign io_out[57] = T49[57] | T1[57];
assign io_out[56] = T49[56] | T1[56];
assign io_out[55] = T49[55] | T1[55];
assign io_out[54] = T49[54] | T1[54];
assign io_out[53] = T49[53] | T1[53];
assign io_out[52] = T49[52] | T1[52];
assign io_out[51] = T49[51] | T1[51];
assign io_out[50] = T49[50] | T1[50];
assign io_out[49] = T49[49] | T1[49];
assign io_out[48] = T49[48] | T1[48];
assign io_out[47] = T49[47] | T1[47];
assign io_out[46] = T49[46] | T1[46];
assign io_out[45] = T49[45] | T1[45];
assign io_out[44] = T49[44] | T1[44];
assign io_out[43] = T49[43] | T1[43];
assign io_out[42] = T49[42] | T1[42];
assign io_out[41] = T49[41] | T1[41];
assign io_out[40] = T49[40] | T1[40];
assign io_out[39] = T49[39] | T1[39];
assign io_out[38] = T49[38] | T1[38];
assign io_out[37] = T49[37] | T1[37];
assign io_out[36] = T49[36] | T1[36];
assign io_out[35] = T49[35] | T1[35];
assign io_out[34] = T49[34] | T1[34];
assign io_out[33] = T49[33] | T1[33];
assign io_out[32] = T49[32] | T1[32];
assign io_out[31] = T49[31] | T1[31];
assign io_out[30] = T49[30] | T1[30];
assign io_out[29] = T49[29] | T1[29];
assign io_out[28] = T49[28] | T1[28];
assign io_out[27] = T49[27] | T1[27];
assign io_out[26] = T49[26] | T1[26];
assign io_out[25] = T49[25] | T1[25];
assign io_out[24] = T49[24] | T1[24];
assign io_out[23] = T49[23] | T1[23];
assign io_out[22] = T49[22] | T1[22];
assign io_out[21] = T49[21] | T1[21];
assign io_out[20] = T49[20] | T1[20];
assign io_out[19] = T49[19] | T1[19];
assign io_out[18] = T49[18] | T1[18];
assign io_out[17] = T49[17] | T1[17];
assign io_out[16] = T49[16] | T1[16];
assign io_out[15] = T49[15] | T1[15];
assign io_out[14] = T49[14] | T1[14];
assign io_out[13] = T49[13] | T1[13];
assign io_out[12] = T49[12] | T1[12];
assign io_out[11] = T49[11] | T1[11];
assign io_out[10] = T49[10] | T1[10];
assign io_out[9] = T49[9] | T1[9];
assign io_out[8] = T49[8] | T1[8];
assign io_out[7] = T49[7] | T1[7];
assign io_out[6] = T49[6] | T1[6];
assign io_out[5] = T49[5] | T1[5];
assign io_out[4] = T49[4] | T1[4];
assign io_out[3] = T49[3] | T1[3];
assign io_out[2] = T49[2] | T1[2];
assign io_out[1] = T49[1] | T1[1];
assign io_out[0] = T49[0] | T1[0];
assign T1[63] = T2[63] & io_lhs[63];
assign T1[62] = T2[62] & io_lhs[62];
assign T1[61] = T2[61] & io_lhs[61];
assign T1[60] = T2[60] & io_lhs[60];
assign T1[59] = T2[59] & io_lhs[59];
assign T1[58] = T2[58] & io_lhs[58];
assign T1[57] = T2[57] & io_lhs[57];
assign T1[56] = T2[56] & io_lhs[56];
assign T1[55] = T2[55] & io_lhs[55];
assign T1[54] = T2[54] & io_lhs[54];
assign T1[53] = T2[53] & io_lhs[53];
assign T1[52] = T2[52] & io_lhs[52];
assign T1[51] = T2[51] & io_lhs[51];
assign T1[50] = T2[50] & io_lhs[50];
assign T1[49] = T2[49] & io_lhs[49];
assign T1[48] = T2[48] & io_lhs[48];
assign T1[47] = T2[47] & io_lhs[47];
assign T1[46] = T2[46] & io_lhs[46];
assign T1[45] = T2[45] & io_lhs[45];
assign T1[44] = T2[44] & io_lhs[44];
assign T1[43] = T2[43] & io_lhs[43];
assign T1[42] = T2[42] & io_lhs[42];
assign T1[41] = T2[41] & io_lhs[41];
assign T1[40] = T2[40] & io_lhs[40];
assign T1[39] = T2[39] & io_lhs[39];
assign T1[38] = T2[38] & io_lhs[38];
assign T1[37] = T2[37] & io_lhs[37];
assign T1[36] = T2[36] & io_lhs[36];
assign T1[35] = T2[35] & io_lhs[35];
assign T1[34] = T2[34] & io_lhs[34];
assign T1[33] = T2[33] & io_lhs[33];
assign T1[32] = T2[32] & io_lhs[32];
assign T1[31] = T2[31] & io_lhs[31];
assign T1[30] = T2[30] & io_lhs[30];
assign T1[29] = T2[29] & io_lhs[29];
assign T1[28] = T2[28] & io_lhs[28];
assign T1[27] = T2[27] & io_lhs[27];
assign T1[26] = T2[26] & io_lhs[26];
assign T1[25] = T2[25] & io_lhs[25];
assign T1[24] = T2[24] & io_lhs[24];
assign T1[23] = T2[23] & io_lhs[23];
assign T1[22] = T2[22] & io_lhs[22];
assign T1[21] = T2[21] & io_lhs[21];
assign T1[20] = T2[20] & io_lhs[20];
assign T1[19] = T2[19] & io_lhs[19];
assign T1[18] = T2[18] & io_lhs[18];
assign T1[17] = T2[17] & io_lhs[17];
assign T1[16] = T2[16] & io_lhs[16];
assign T1[15] = T2[15] & io_lhs[15];
assign T1[14] = T2[14] & io_lhs[14];
assign T1[13] = T2[13] & io_lhs[13];
assign T1[12] = T2[12] & io_lhs[12];
assign T1[11] = T2[11] & io_lhs[11];
assign T1[10] = T2[10] & io_lhs[10];
assign T1[9] = T2[9] & io_lhs[9];
assign T1[8] = T2[8] & io_lhs[8];
assign T1[7] = T2[7] & io_lhs[7];
assign T1[6] = T2[6] & io_lhs[6];
assign T1[5] = T2[5] & io_lhs[5];
assign T1[4] = T2[4] & io_lhs[4];
assign T1[3] = T2[3] & io_lhs[3];
assign T1[2] = T2[2] & io_lhs[2];
assign T1[1] = T2[1] & io_lhs[1];
assign T1[0] = T2[0] & io_lhs[0];
assign T2[63] = ~wmask_63;
assign T2[62] = ~wmask_63;
assign T2[61] = ~wmask_63;
assign T2[60] = ~wmask_63;
assign T2[59] = ~wmask_63;
assign T2[58] = ~wmask_63;
assign T2[57] = ~wmask_63;
assign T2[56] = ~wmask[56];
assign T2[55] = ~wmask[55];
assign T2[54] = ~wmask[55];
assign T2[53] = ~wmask[55];
assign T2[52] = ~wmask[55];
assign T2[51] = ~wmask[55];
assign T2[50] = ~wmask[55];
assign T2[49] = ~wmask[55];
assign T2[48] = ~wmask_48;
assign T2[47] = ~wmask_47;
assign T2[46] = ~wmask_47;
assign T2[45] = ~wmask_47;
assign T2[44] = ~wmask_47;
assign T2[43] = ~wmask_47;
assign T2[42] = ~wmask_47;
assign T2[41] = ~wmask_47;
assign T2[40] = ~wmask_40;
assign T2[39] = ~wmask_39;
assign T2[38] = ~wmask_39;
assign T2[37] = ~wmask_39;
assign T2[36] = ~wmask_39;
assign T2[35] = ~wmask_39;
assign T2[34] = ~wmask_39;
assign T2[33] = ~wmask_39;
assign T2[32] = ~wmask_32;
assign T2[31] = ~wmask_31;
assign T2[30] = ~wmask_31;
assign T2[29] = ~wmask_31;
assign T2[28] = ~wmask_31;
assign T2[27] = ~wmask_31;
assign T2[26] = ~wmask_31;
assign T2[25] = ~wmask_31;
assign T2[24] = ~wmask_24;
assign T2[23] = ~wmask_23;
assign T2[22] = ~wmask_23;
assign T2[21] = ~wmask_23;
assign T2[20] = ~wmask_23;
assign T2[19] = ~wmask_23;
assign T2[18] = ~wmask_23;
assign T2[17] = ~wmask_23;
assign T2[16] = ~wmask_16;
assign T2[15] = ~wmask_15;
assign T2[14] = ~wmask_15;
assign T2[13] = ~wmask_15;
assign T2[12] = ~wmask_15;
assign T2[11] = ~wmask_15;
assign T2[10] = ~wmask_15;
assign T2[9] = ~wmask_15;
assign T2[8] = ~wmask_8;
assign T2[7] = ~wmask_7;
assign T2[6] = ~wmask_7;
assign T2[5] = ~wmask_7;
assign T2[4] = ~wmask_7;
assign T2[3] = ~wmask_7;
assign T2[2] = ~wmask_7;
assign T2[1] = ~wmask_7;
assign T2[0] = ~wmask_0;
assign N33 = ~io_addr[2];
assign N34 = ~io_addr[1];
assign T12[1] = io_addr[0] | T16;
assign T16 = io_typ[1] | io_typ[0];
assign T10[3] = T23[1] | T21[1];
assign T10[2] = T23[0] | T21[1];
assign T21[1] = io_typ[1];
assign T8[7] = T29[3] | T27[3];
assign T8[6] = T29[2] | T27[3];
assign T8[5] = T29[1] | T27[3];
assign T8[4] = T29[0] | T27[3];
assign T27[3] = T28;
assign T49[63] = wmask_63 & out[63];
assign T49[62] = wmask_63 & out[62];
assign T49[61] = wmask_63 & out[61];
assign T49[60] = wmask_63 & out[60];
assign T49[59] = wmask_63 & out[59];
assign T49[58] = wmask_63 & out[58];
assign T49[57] = wmask_63 & out[57];
assign T49[56] = wmask[56] & out[56];
assign T49[55] = wmask[55] & out[55];
assign T49[54] = wmask[55] & out[54];
assign T49[53] = wmask[55] & out[53];
assign T49[52] = wmask[55] & out[52];
assign T49[51] = wmask[55] & out[51];
assign T49[50] = wmask[55] & out[50];
assign T49[49] = wmask[55] & out[49];
assign T49[48] = wmask_48 & out[48];
assign T49[47] = wmask_47 & out[47];
assign T49[46] = wmask_47 & out[46];
assign T49[45] = wmask_47 & out[45];
assign T49[44] = wmask_47 & out[44];
assign T49[43] = wmask_47 & out[43];
assign T49[42] = wmask_47 & out[42];
assign T49[41] = wmask_47 & out[41];
assign T49[40] = wmask_40 & out[40];
assign T49[39] = wmask_39 & out[39];
assign T49[38] = wmask_39 & out[38];
assign T49[37] = wmask_39 & out[37];
assign T49[36] = wmask_39 & out[36];
assign T49[35] = wmask_39 & out[35];
assign T49[34] = wmask_39 & out[34];
assign T49[33] = wmask_39 & out[33];
assign T49[32] = wmask_32 & out[32];
assign T49[31] = wmask_31 & out[31];
assign T49[30] = wmask_31 & out[30];
assign T49[29] = wmask_31 & out[29];
assign T49[28] = wmask_31 & out[28];
assign T49[27] = wmask_31 & out[27];
assign T49[26] = wmask_31 & out[26];
assign T49[25] = wmask_31 & out[25];
assign T49[24] = wmask_24 & out[24];
assign T49[23] = wmask_23 & out[23];
assign T49[22] = wmask_23 & out[22];
assign T49[21] = wmask_23 & out[21];
assign T49[20] = wmask_23 & out[20];
assign T49[19] = wmask_23 & out[19];
assign T49[18] = wmask_23 & out[18];
assign T49[17] = wmask_23 & out[17];
assign T49[16] = wmask_16 & out[16];
assign T49[15] = wmask_15 & out[15];
assign T49[14] = wmask_15 & out[14];
assign T49[13] = wmask_15 & out[13];
assign T49[12] = wmask_15 & out[12];
assign T49[11] = wmask_15 & out[11];
assign T49[10] = wmask_15 & out[10];
assign T49[9] = wmask_15 & out[9];
assign T49[8] = wmask_8 & out[8];
assign T49[7] = wmask_7 & out[7];
assign T49[6] = wmask_7 & out[6];
assign T49[5] = wmask_7 & out[5];
assign T49[4] = wmask_7 & out[4];
assign T49[3] = wmask_7 & out[3];
assign T49[2] = wmask_7 & out[2];
assign T49[1] = wmask_7 & out[1];
assign T49[0] = wmask_0 & out[0];
assign N35 = ~T69;
assign N36 = ~less;
assign max = N72 | N74;
assign min = N67 | N70;
assign N37 = ~T106;
assign N38 = ~sgned;
assign N39 = ~T80;
assign T80 = word & T81;
assign T81 = ~io_addr[2];
assign word = T84 | N81;
assign T84 = T86 | N84;
assign T86 = N87 | N90;
assign N40 = ~T91;
assign T91 = word & T92;
assign T92 = ~io_addr[2];
assign sgned = N67 | N72;
assign N41 = ~word;
assign T96 = lt_hi | T97;
assign T97 = eq_hi & lt_lo;
assign T107[63] = io_lhs[63] ^ rhs[63];
assign T107[62] = io_lhs[62] ^ rhs[62];
assign T107[61] = io_lhs[61] ^ rhs[61];
assign T107[60] = io_lhs[60] ^ rhs[60];
assign T107[59] = io_lhs[59] ^ rhs[59];
assign T107[58] = io_lhs[58] ^ rhs[58];
assign T107[57] = io_lhs[57] ^ rhs[57];
assign T107[56] = io_lhs[56] ^ rhs[56];
assign T107[55] = io_lhs[55] ^ rhs[55];
assign T107[54] = io_lhs[54] ^ rhs[54];
assign T107[53] = io_lhs[53] ^ rhs[53];
assign T107[52] = io_lhs[52] ^ rhs[52];
assign T107[51] = io_lhs[51] ^ rhs[51];
assign T107[50] = io_lhs[50] ^ rhs[50];
assign T107[49] = io_lhs[49] ^ rhs[49];
assign T107[48] = io_lhs[48] ^ rhs[48];
assign T107[47] = io_lhs[47] ^ rhs[47];
assign T107[46] = io_lhs[46] ^ rhs[46];
assign T107[45] = io_lhs[45] ^ rhs[45];
assign T107[44] = io_lhs[44] ^ rhs[44];
assign T107[43] = io_lhs[43] ^ rhs[43];
assign T107[42] = io_lhs[42] ^ rhs[42];
assign T107[41] = io_lhs[41] ^ rhs[41];
assign T107[40] = io_lhs[40] ^ rhs[40];
assign T107[39] = io_lhs[39] ^ rhs[39];
assign T107[38] = io_lhs[38] ^ rhs[38];
assign T107[37] = io_lhs[37] ^ rhs[37];
assign T107[36] = io_lhs[36] ^ rhs[36];
assign T107[35] = io_lhs[35] ^ rhs[35];
assign T107[34] = io_lhs[34] ^ rhs[34];
assign T107[33] = io_lhs[33] ^ rhs[33];
assign T107[32] = io_lhs[32] ^ rhs[32];
assign T107[31] = io_lhs[31] ^ io_rhs[31];
assign T107[30] = io_lhs[30] ^ io_rhs[30];
assign T107[29] = io_lhs[29] ^ io_rhs[29];
assign T107[28] = io_lhs[28] ^ io_rhs[28];
assign T107[27] = io_lhs[27] ^ io_rhs[27];
assign T107[26] = io_lhs[26] ^ io_rhs[26];
assign T107[25] = io_lhs[25] ^ io_rhs[25];
assign T107[24] = io_lhs[24] ^ io_rhs[24];
assign T107[23] = io_lhs[23] ^ io_rhs[23];
assign T107[22] = io_lhs[22] ^ io_rhs[22];
assign T107[21] = io_lhs[21] ^ io_rhs[21];
assign T107[20] = io_lhs[20] ^ io_rhs[20];
assign T107[19] = io_lhs[19] ^ io_rhs[19];
assign T107[18] = io_lhs[18] ^ io_rhs[18];
assign T107[17] = io_lhs[17] ^ io_rhs[17];
assign T107[16] = io_lhs[16] ^ io_rhs[16];
assign T107[15] = io_lhs[15] ^ io_rhs[15];
assign T107[14] = io_lhs[14] ^ io_rhs[14];
assign T107[13] = io_lhs[13] ^ io_rhs[13];
assign T107[12] = io_lhs[12] ^ io_rhs[12];
assign T107[11] = io_lhs[11] ^ io_rhs[11];
assign T107[10] = io_lhs[10] ^ io_rhs[10];
assign T107[9] = io_lhs[9] ^ io_rhs[9];
assign T107[8] = io_lhs[8] ^ io_rhs[8];
assign T107[7] = io_lhs[7] ^ io_rhs[7];
assign T107[6] = io_lhs[6] ^ io_rhs[6];
assign T107[5] = io_lhs[5] ^ io_rhs[5];
assign T107[4] = io_lhs[4] ^ io_rhs[4];
assign T107[3] = io_lhs[3] ^ io_rhs[3];
assign T107[2] = io_lhs[2] ^ io_rhs[2];
assign T107[1] = io_lhs[1] ^ io_rhs[1];
assign T107[0] = io_lhs[0] ^ io_rhs[0];
assign T109[63] = io_lhs[63] | rhs[63];
assign T109[62] = io_lhs[62] | rhs[62];
assign T109[61] = io_lhs[61] | rhs[61];
assign T109[60] = io_lhs[60] | rhs[60];
assign T109[59] = io_lhs[59] | rhs[59];
assign T109[58] = io_lhs[58] | rhs[58];
assign T109[57] = io_lhs[57] | rhs[57];
assign T109[56] = io_lhs[56] | rhs[56];
assign T109[55] = io_lhs[55] | rhs[55];
assign T109[54] = io_lhs[54] | rhs[54];
assign T109[53] = io_lhs[53] | rhs[53];
assign T109[52] = io_lhs[52] | rhs[52];
assign T109[51] = io_lhs[51] | rhs[51];
assign T109[50] = io_lhs[50] | rhs[50];
assign T109[49] = io_lhs[49] | rhs[49];
assign T109[48] = io_lhs[48] | rhs[48];
assign T109[47] = io_lhs[47] | rhs[47];
assign T109[46] = io_lhs[46] | rhs[46];
assign T109[45] = io_lhs[45] | rhs[45];
assign T109[44] = io_lhs[44] | rhs[44];
assign T109[43] = io_lhs[43] | rhs[43];
assign T109[42] = io_lhs[42] | rhs[42];
assign T109[41] = io_lhs[41] | rhs[41];
assign T109[40] = io_lhs[40] | rhs[40];
assign T109[39] = io_lhs[39] | rhs[39];
assign T109[38] = io_lhs[38] | rhs[38];
assign T109[37] = io_lhs[37] | rhs[37];
assign T109[36] = io_lhs[36] | rhs[36];
assign T109[35] = io_lhs[35] | rhs[35];
assign T109[34] = io_lhs[34] | rhs[34];
assign T109[33] = io_lhs[33] | rhs[33];
assign T109[32] = io_lhs[32] | rhs[32];
assign T109[31] = io_lhs[31] | io_rhs[31];
assign T109[30] = io_lhs[30] | io_rhs[30];
assign T109[29] = io_lhs[29] | io_rhs[29];
assign T109[28] = io_lhs[28] | io_rhs[28];
assign T109[27] = io_lhs[27] | io_rhs[27];
assign T109[26] = io_lhs[26] | io_rhs[26];
assign T109[25] = io_lhs[25] | io_rhs[25];
assign T109[24] = io_lhs[24] | io_rhs[24];
assign T109[23] = io_lhs[23] | io_rhs[23];
assign T109[22] = io_lhs[22] | io_rhs[22];
assign T109[21] = io_lhs[21] | io_rhs[21];
assign T109[20] = io_lhs[20] | io_rhs[20];
assign T109[19] = io_lhs[19] | io_rhs[19];
assign T109[18] = io_lhs[18] | io_rhs[18];
assign T109[17] = io_lhs[17] | io_rhs[17];
assign T109[16] = io_lhs[16] | io_rhs[16];
assign T109[15] = io_lhs[15] | io_rhs[15];
assign T109[14] = io_lhs[14] | io_rhs[14];
assign T109[13] = io_lhs[13] | io_rhs[13];
assign T109[12] = io_lhs[12] | io_rhs[12];
assign T109[11] = io_lhs[11] | io_rhs[11];
assign T109[10] = io_lhs[10] | io_rhs[10];
assign T109[9] = io_lhs[9] | io_rhs[9];
assign T109[8] = io_lhs[8] | io_rhs[8];
assign T109[7] = io_lhs[7] | io_rhs[7];
assign T109[6] = io_lhs[6] | io_rhs[6];
assign T109[5] = io_lhs[5] | io_rhs[5];
assign T109[4] = io_lhs[4] | io_rhs[4];
assign T109[3] = io_lhs[3] | io_rhs[3];
assign T109[2] = io_lhs[2] | io_rhs[2];
assign T109[1] = io_lhs[1] | io_rhs[1];
assign T109[0] = io_lhs[0] | io_rhs[0];
assign T111[63] = io_lhs[63] & rhs[63];
assign T111[62] = io_lhs[62] & rhs[62];
assign T111[61] = io_lhs[61] & rhs[61];
assign T111[60] = io_lhs[60] & rhs[60];
assign T111[59] = io_lhs[59] & rhs[59];
assign T111[58] = io_lhs[58] & rhs[58];
assign T111[57] = io_lhs[57] & rhs[57];
assign T111[56] = io_lhs[56] & rhs[56];
assign T111[55] = io_lhs[55] & rhs[55];
assign T111[54] = io_lhs[54] & rhs[54];
assign T111[53] = io_lhs[53] & rhs[53];
assign T111[52] = io_lhs[52] & rhs[52];
assign T111[51] = io_lhs[51] & rhs[51];
assign T111[50] = io_lhs[50] & rhs[50];
assign T111[49] = io_lhs[49] & rhs[49];
assign T111[48] = io_lhs[48] & rhs[48];
assign T111[47] = io_lhs[47] & rhs[47];
assign T111[46] = io_lhs[46] & rhs[46];
assign T111[45] = io_lhs[45] & rhs[45];
assign T111[44] = io_lhs[44] & rhs[44];
assign T111[43] = io_lhs[43] & rhs[43];
assign T111[42] = io_lhs[42] & rhs[42];
assign T111[41] = io_lhs[41] & rhs[41];
assign T111[40] = io_lhs[40] & rhs[40];
assign T111[39] = io_lhs[39] & rhs[39];
assign T111[38] = io_lhs[38] & rhs[38];
assign T111[37] = io_lhs[37] & rhs[37];
assign T111[36] = io_lhs[36] & rhs[36];
assign T111[35] = io_lhs[35] & rhs[35];
assign T111[34] = io_lhs[34] & rhs[34];
assign T111[33] = io_lhs[33] & rhs[33];
assign T111[32] = io_lhs[32] & rhs[32];
assign T111[31] = io_lhs[31] & io_rhs[31];
assign T111[30] = io_lhs[30] & io_rhs[30];
assign T111[29] = io_lhs[29] & io_rhs[29];
assign T111[28] = io_lhs[28] & io_rhs[28];
assign T111[27] = io_lhs[27] & io_rhs[27];
assign T111[26] = io_lhs[26] & io_rhs[26];
assign T111[25] = io_lhs[25] & io_rhs[25];
assign T111[24] = io_lhs[24] & io_rhs[24];
assign T111[23] = io_lhs[23] & io_rhs[23];
assign T111[22] = io_lhs[22] & io_rhs[22];
assign T111[21] = io_lhs[21] & io_rhs[21];
assign T111[20] = io_lhs[20] & io_rhs[20];
assign T111[19] = io_lhs[19] & io_rhs[19];
assign T111[18] = io_lhs[18] & io_rhs[18];
assign T111[17] = io_lhs[17] & io_rhs[17];
assign T111[16] = io_lhs[16] & io_rhs[16];
assign T111[15] = io_lhs[15] & io_rhs[15];
assign T111[14] = io_lhs[14] & io_rhs[14];
assign T111[13] = io_lhs[13] & io_rhs[13];
assign T111[12] = io_lhs[12] & io_rhs[12];
assign T111[11] = io_lhs[11] & io_rhs[11];
assign T111[10] = io_lhs[10] & io_rhs[10];
assign T111[9] = io_lhs[9] & io_rhs[9];
assign T111[8] = io_lhs[8] & io_rhs[8];
assign T111[7] = io_lhs[7] & io_rhs[7];
assign T111[6] = io_lhs[6] & io_rhs[6];
assign T111[5] = io_lhs[5] & io_rhs[5];
assign T111[4] = io_lhs[4] & io_rhs[4];
assign T111[3] = io_lhs[3] & io_rhs[3];
assign T111[2] = io_lhs[2] & io_rhs[2];
assign T111[1] = io_lhs[1] & io_rhs[1];
assign T111[0] = io_lhs[0] & io_rhs[0];
assign T113[63] = rhs[63] & mask[63];
assign T113[62] = rhs[62] & mask[62];
assign T113[61] = rhs[61] & mask[61];
assign T113[60] = rhs[60] & mask[60];
assign T113[59] = rhs[59] & mask[59];
assign T113[58] = rhs[58] & mask[58];
assign T113[57] = rhs[57] & mask[57];
assign T113[56] = rhs[56] & mask[56];
assign T113[55] = rhs[55] & mask[55];
assign T113[54] = rhs[54] & mask[54];
assign T113[53] = rhs[53] & mask[53];
assign T113[52] = rhs[52] & mask[52];
assign T113[51] = rhs[51] & mask[51];
assign T113[50] = rhs[50] & mask[50];
assign T113[49] = rhs[49] & mask[49];
assign T113[48] = rhs[48] & mask[48];
assign T113[47] = rhs[47] & mask[47];
assign T113[46] = rhs[46] & mask[46];
assign T113[45] = rhs[45] & mask[45];
assign T113[44] = rhs[44] & mask[44];
assign T113[43] = rhs[43] & mask[43];
assign T113[42] = rhs[42] & mask[42];
assign T113[41] = rhs[41] & mask[41];
assign T113[40] = rhs[40] & mask[40];
assign T113[39] = rhs[39] & mask[39];
assign T113[38] = rhs[38] & mask[38];
assign T113[37] = rhs[37] & mask[37];
assign T113[36] = rhs[36] & mask[36];
assign T113[35] = rhs[35] & mask[35];
assign T113[34] = rhs[34] & mask[34];
assign T113[33] = rhs[33] & mask[33];
assign T113[32] = rhs[32] & mask[32];
assign T113[31] = io_rhs[31] & mask[31];
assign T113[30] = io_rhs[30] & mask[30];
assign T113[29] = io_rhs[29] & mask[29];
assign T113[28] = io_rhs[28] & mask[28];
assign T113[27] = io_rhs[27] & mask[27];
assign T113[26] = io_rhs[26] & mask[26];
assign T113[25] = io_rhs[25] & mask[25];
assign T113[24] = io_rhs[24] & mask[24];
assign T113[23] = io_rhs[23] & mask[23];
assign T113[22] = io_rhs[22] & mask[22];
assign T113[21] = io_rhs[21] & mask[21];
assign T113[20] = io_rhs[20] & mask[20];
assign T113[19] = io_rhs[19] & mask[19];
assign T113[18] = io_rhs[18] & mask[18];
assign T113[17] = io_rhs[17] & mask[17];
assign T113[16] = io_rhs[16] & mask[16];
assign T113[15] = io_rhs[15] & mask[15];
assign T113[14] = io_rhs[14] & mask[14];
assign T113[13] = io_rhs[13] & mask[13];
assign T113[12] = io_rhs[12] & mask[12];
assign T113[11] = io_rhs[11] & mask[11];
assign T113[10] = io_rhs[10] & mask[10];
assign T113[9] = io_rhs[9] & mask[9];
assign T113[8] = io_rhs[8] & mask[8];
assign T113[7] = io_rhs[7] & mask[7];
assign T113[6] = io_rhs[6] & mask[6];
assign T113[5] = io_rhs[5] & mask[5];
assign T113[4] = io_rhs[4] & mask[4];
assign T113[3] = io_rhs[3] & mask[3];
assign T113[2] = io_rhs[2] & mask[2];
assign T113[1] = io_rhs[1] & mask[1];
assign T113[0] = io_rhs[0] & mask[0];
assign mask[63] = ~1'b0;
assign mask[62] = ~1'b0;
assign mask[61] = ~1'b0;
assign mask[60] = ~1'b0;
assign mask[59] = ~1'b0;
assign mask[58] = ~1'b0;
assign mask[57] = ~1'b0;
assign mask[56] = ~1'b0;
assign mask[55] = ~1'b0;
assign mask[54] = ~1'b0;
assign mask[53] = ~1'b0;
assign mask[52] = ~1'b0;
assign mask[51] = ~1'b0;
assign mask[50] = ~1'b0;
assign mask[49] = ~1'b0;
assign mask[48] = ~1'b0;
assign mask[47] = ~1'b0;
assign mask[46] = ~1'b0;
assign mask[45] = ~1'b0;
assign mask[44] = ~1'b0;
assign mask[43] = ~1'b0;
assign mask[42] = ~1'b0;
assign mask[41] = ~1'b0;
assign mask[40] = ~1'b0;
assign mask[39] = ~1'b0;
assign mask[38] = ~1'b0;
assign mask[37] = ~1'b0;
assign mask[36] = ~1'b0;
assign mask[35] = ~1'b0;
assign mask[34] = ~1'b0;
assign mask[33] = ~1'b0;
assign mask[32] = ~1'b0;
assign mask[31] = ~io_addr[2];
assign mask[30] = ~1'b0;
assign mask[29] = ~1'b0;
assign mask[28] = ~1'b0;
assign mask[27] = ~1'b0;
assign mask[26] = ~1'b0;
assign mask[25] = ~1'b0;
assign mask[24] = ~1'b0;
assign mask[23] = ~1'b0;
assign mask[22] = ~1'b0;
assign mask[21] = ~1'b0;
assign mask[20] = ~1'b0;
assign mask[19] = ~1'b0;
assign mask[18] = ~1'b0;
assign mask[17] = ~1'b0;
assign mask[16] = ~1'b0;
assign mask[15] = ~1'b0;
assign mask[14] = ~1'b0;
assign mask[13] = ~1'b0;
assign mask[12] = ~1'b0;
assign mask[11] = ~1'b0;
assign mask[10] = ~1'b0;
assign mask[9] = ~1'b0;
assign mask[8] = ~1'b0;
assign mask[7] = ~1'b0;
assign mask[6] = ~1'b0;
assign mask[5] = ~1'b0;
assign mask[4] = ~1'b0;
assign mask[3] = ~1'b0;
assign mask[2] = ~1'b0;
assign mask[1] = ~1'b0;
assign mask[0] = ~1'b0;
assign T116[63] = io_lhs[63] & mask[63];
assign T116[62] = io_lhs[62] & mask[62];
assign T116[61] = io_lhs[61] & mask[61];
assign T116[60] = io_lhs[60] & mask[60];
assign T116[59] = io_lhs[59] & mask[59];
assign T116[58] = io_lhs[58] & mask[58];
assign T116[57] = io_lhs[57] & mask[57];
assign T116[56] = io_lhs[56] & mask[56];
assign T116[55] = io_lhs[55] & mask[55];
assign T116[54] = io_lhs[54] & mask[54];
assign T116[53] = io_lhs[53] & mask[53];
assign T116[52] = io_lhs[52] & mask[52];
assign T116[51] = io_lhs[51] & mask[51];
assign T116[50] = io_lhs[50] & mask[50];
assign T116[49] = io_lhs[49] & mask[49];
assign T116[48] = io_lhs[48] & mask[48];
assign T116[47] = io_lhs[47] & mask[47];
assign T116[46] = io_lhs[46] & mask[46];
assign T116[45] = io_lhs[45] & mask[45];
assign T116[44] = io_lhs[44] & mask[44];
assign T116[43] = io_lhs[43] & mask[43];
assign T116[42] = io_lhs[42] & mask[42];
assign T116[41] = io_lhs[41] & mask[41];
assign T116[40] = io_lhs[40] & mask[40];
assign T116[39] = io_lhs[39] & mask[39];
assign T116[38] = io_lhs[38] & mask[38];
assign T116[37] = io_lhs[37] & mask[37];
assign T116[36] = io_lhs[36] & mask[36];
assign T116[35] = io_lhs[35] & mask[35];
assign T116[34] = io_lhs[34] & mask[34];
assign T116[33] = io_lhs[33] & mask[33];
assign T116[32] = io_lhs[32] & mask[32];
assign T116[31] = io_lhs[31] & mask[31];
assign T116[30] = io_lhs[30] & mask[30];
assign T116[29] = io_lhs[29] & mask[29];
assign T116[28] = io_lhs[28] & mask[28];
assign T116[27] = io_lhs[27] & mask[27];
assign T116[26] = io_lhs[26] & mask[26];
assign T116[25] = io_lhs[25] & mask[25];
assign T116[24] = io_lhs[24] & mask[24];
assign T116[23] = io_lhs[23] & mask[23];
assign T116[22] = io_lhs[22] & mask[22];
assign T116[21] = io_lhs[21] & mask[21];
assign T116[20] = io_lhs[20] & mask[20];
assign T116[19] = io_lhs[19] & mask[19];
assign T116[18] = io_lhs[18] & mask[18];
assign T116[17] = io_lhs[17] & mask[17];
assign T116[16] = io_lhs[16] & mask[16];
assign T116[15] = io_lhs[15] & mask[15];
assign T116[14] = io_lhs[14] & mask[14];
assign T116[13] = io_lhs[13] & mask[13];
assign T116[12] = io_lhs[12] & mask[12];
assign T116[11] = io_lhs[11] & mask[11];
assign T116[10] = io_lhs[10] & mask[10];
assign T116[9] = io_lhs[9] & mask[9];
assign T116[8] = io_lhs[8] & mask[8];
assign T116[7] = io_lhs[7] & mask[7];
assign T116[6] = io_lhs[6] & mask[6];
assign T116[5] = io_lhs[5] & mask[5];
assign T116[4] = io_lhs[4] & mask[4];
assign T116[3] = io_lhs[3] & mask[3];
assign T116[2] = io_lhs[2] & mask[2];
assign T116[1] = io_lhs[1] & mask[1];
assign T116[0] = io_lhs[0] & mask[0];
endmodule |
module RecFNToIN_1
(
io_in,
io_roundingMode,
io_signedOut,
io_out,
io_intExceptionFlags
);
input [64:0] io_in;
input [1:0] io_roundingMode;
output [31:0] io_out;
output [2:0] io_intExceptionFlags;
input io_signedOut;
wire [31:0] io_out,excValue,roundedInt,T62,onesCompUnroundedInt,T61,T66;
wire [2:0] io_intExceptionFlags;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,T3,T2,roundInexact,T4,T5,N12,
overflow_signed,overflow_unsigned,T36,T15,roundIncr,T20,T16,T17,T18,T24,T21,T22,
roundIncr_nearestEven,T30,T25,N13,T33,T43,T37,T40,roundCarryBut2,T38,T44,N14,T45,T50,T46,T47,
T49,T58,T51,T52,T53,T56,T54,T74,N15,T63,N16,N17,T65,T68,T69,excSign,T70,isNaN,
T73,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N37,
N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,
N58,N59,N60,N61,N62,N63,N64,N65,N66;
wire [0:0] T8;
wire [50:0] T10;
wire [83:51] shiftedSig;
wire [4:0] T11;
wire [31:31] T64,T72;
wire [30:30] T75;
assign T8[0] = T10 != 1'b0;
assign { shiftedSig, T10 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, io_in[63:63], io_in[51:0] } << T11;
assign T33 = shiftedSig[52:51] == { 1'b1, 1'b1 };
assign T38 = shiftedSig[81:52] == { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
assign T54 = shiftedSig[82:52] != 1'b0;
assign N18 = ~io_in[56];
assign N19 = ~io_in[55];
assign N20 = ~io_in[54];
assign N21 = ~io_in[53];
assign N22 = ~io_in[52];
assign N23 = io_in[61] | io_in[62];
assign N24 = io_in[60] | N23;
assign N25 = io_in[59] | N24;
assign N26 = io_in[58] | N25;
assign N27 = io_in[57] | N26;
assign N28 = N18 | N27;
assign N29 = N19 | N28;
assign N30 = N20 | N29;
assign N31 = N21 | N30;
assign N32 = N22 | N31;
assign N33 = ~N32;
assign N34 = io_in[52] | N31;
assign N35 = ~N34;
assign io_intExceptionFlags[2] = io_in[62] & io_in[63];
assign N37 = io_roundingMode[0] & io_roundingMode[1];
assign N38 = io_roundingMode[0] | io_roundingMode[1];
assign N39 = ~N38;
assign N40 = ~io_roundingMode[1];
assign N41 = io_roundingMode[0] | N40;
assign N42 = ~N41;
assign N43 = T8[0] & shiftedSig[51];
assign N44 = T8[0] | shiftedSig[51];
assign N45 = T8[0] | shiftedSig[51];
assign N46 = io_in[62] | io_in[63];
assign N47 = io_in[61] | N46;
assign N48 = ~N47;
assign N49 = io_in[61] & io_in[62];
assign N50 = io_in[60] & N49;
assign N51 = io_in[59] & N50;
assign N52 = io_in[58] & N51;
assign N53 = io_in[57] & N52;
assign N54 = io_in[56] & N53;
assign N55 = io_in[55] & N54;
assign N56 = io_in[54] & N55;
assign N57 = io_in[53] & N56;
assign N58 = io_in[52] & N57;
assign T62 = onesCompUnroundedInt + 1'b1;
assign roundInexact = (N0)? N45 :
(N1)? T5 : 1'b0;
assign N0 = io_in[63];
assign N1 = N14;
assign T11 = (N0)? io_in[56:52] :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign io_intExceptionFlags[1] = (N2)? overflow_signed :
(N3)? overflow_unsigned : 1'b0;
assign N2 = io_signedOut;
assign N3 = N12;
assign overflow_unsigned = (N0)? T36 :
(N1)? T15 : 1'b0;
assign roundIncr_nearestEven = (N0)? T30 :
(N1)? T25 : 1'b0;
assign T25 = (N4)? N44 :
(N5)? 1'b0 : 1'b0;
assign N4 = N58;
assign N5 = N13;
assign overflow_signed = (N0)? T45 :
(N1)? 1'b0 : 1'b0;
assign io_out = (N6)? excValue :
(N7)? roundedInt : 1'b0;
assign N6 = T74;
assign N7 = N15;
assign roundedInt = (N8)? T62 :
(N9)? onesCompUnroundedInt : 1'b0;
assign N8 = T63;
assign N9 = N16;
assign onesCompUnroundedInt = (N10)? T61 :
(N11)? shiftedSig[83:52] : 1'b0;
assign N10 = io_in[64];
assign N11 = N17;
assign io_intExceptionFlags[0] = T3 & T2;
assign T2 = ~io_intExceptionFlags[1];
assign T3 = roundInexact & T4;
assign T4 = ~io_intExceptionFlags[2];
assign T5 = ~N48;
assign N12 = ~io_signedOut;
assign T15 = io_in[64] & roundIncr;
assign roundIncr = T20 | T16;
assign T16 = N37 & T17;
assign T17 = T18 & roundInexact;
assign T18 = ~io_in[64];
assign T20 = T24 | T21;
assign T21 = N42 & T22;
assign T22 = io_in[64] & roundInexact;
assign T24 = N39 & roundIncr_nearestEven;
assign N13 = ~N58;
assign T30 = T33 | N43;
assign T36 = T43 | T37;
assign T37 = T40 & roundCarryBut2;
assign roundCarryBut2 = T38 & roundIncr;
assign T40 = N33 & shiftedSig[82];
assign T43 = io_in[64] | T44;
assign T44 = N62 | io_in[57];
assign N62 = N61 | io_in[58];
assign N61 = N60 | io_in[59];
assign N60 = N59 | io_in[60];
assign N59 = io_in[62] | io_in[61];
assign N14 = ~io_in[63];
assign T45 = T50 | T46;
assign T46 = T47 & roundCarryBut2;
assign T47 = T49 & N35;
assign T49 = ~io_in[64];
assign T50 = T58 | T51;
assign T51 = N33 & T52;
assign T52 = T53 | roundIncr;
assign T53 = T56 | T54;
assign T56 = ~io_in[64];
assign T58 = N66 | io_in[57];
assign N66 = N65 | io_in[58];
assign N65 = N64 | io_in[59];
assign N64 = N63 | io_in[60];
assign N63 = io_in[62] | io_in[61];
assign N15 = ~T74;
assign N16 = ~T63;
assign N17 = ~io_in[64];
assign T61[31] = ~shiftedSig[83];
assign T61[30] = ~shiftedSig[82];
assign T61[29] = ~shiftedSig[81];
assign T61[28] = ~shiftedSig[80];
assign T61[27] = ~shiftedSig[79];
assign T61[26] = ~shiftedSig[78];
assign T61[25] = ~shiftedSig[77];
assign T61[24] = ~shiftedSig[76];
assign T61[23] = ~shiftedSig[75];
assign T61[22] = ~shiftedSig[74];
assign T61[21] = ~shiftedSig[73];
assign T61[20] = ~shiftedSig[72];
assign T61[19] = ~shiftedSig[71];
assign T61[18] = ~shiftedSig[70];
assign T61[17] = ~shiftedSig[69];
assign T61[16] = ~shiftedSig[68];
assign T61[15] = ~shiftedSig[67];
assign T61[14] = ~shiftedSig[66];
assign T61[13] = ~shiftedSig[65];
assign T61[12] = ~shiftedSig[64];
assign T61[11] = ~shiftedSig[63];
assign T61[10] = ~shiftedSig[62];
assign T61[9] = ~shiftedSig[61];
assign T61[8] = ~shiftedSig[60];
assign T61[7] = ~shiftedSig[59];
assign T61[6] = ~shiftedSig[58];
assign T61[5] = ~shiftedSig[57];
assign T61[4] = ~shiftedSig[56];
assign T61[3] = ~shiftedSig[55];
assign T61[2] = ~shiftedSig[54];
assign T61[1] = ~shiftedSig[53];
assign T61[0] = ~shiftedSig[52];
assign T63 = roundIncr ^ io_in[64];
assign excValue[31] = T66[31] | T64[31];
assign excValue[30] = T66[30] | T64[31];
assign excValue[29] = T66[29] | T64[31];
assign excValue[28] = T66[28] | T64[31];
assign excValue[27] = T66[27] | T64[31];
assign excValue[26] = T66[26] | T64[31];
assign excValue[25] = T66[25] | T64[31];
assign excValue[24] = T66[24] | T64[31];
assign excValue[23] = T66[23] | T64[31];
assign excValue[22] = T66[22] | T64[31];
assign excValue[21] = T66[21] | T64[31];
assign excValue[20] = T66[20] | T64[31];
assign excValue[19] = T66[19] | T64[31];
assign excValue[18] = T66[18] | T64[31];
assign excValue[17] = T66[17] | T64[31];
assign excValue[16] = T66[16] | T64[31];
assign excValue[15] = T66[15] | T64[31];
assign excValue[14] = T66[14] | T64[31];
assign excValue[13] = T66[13] | T64[31];
assign excValue[12] = T66[12] | T64[31];
assign excValue[11] = T66[11] | T64[31];
assign excValue[10] = T66[10] | T64[31];
assign excValue[9] = T66[9] | T64[31];
assign excValue[8] = T66[8] | T64[31];
assign excValue[7] = T66[7] | T64[31];
assign excValue[6] = T66[6] | T64[31];
assign excValue[5] = T66[5] | T64[31];
assign excValue[4] = T66[4] | T64[31];
assign excValue[3] = T66[3] | T64[31];
assign excValue[2] = T66[2] | T64[31];
assign excValue[1] = T66[1] | T64[31];
assign excValue[0] = T66[0] | T64[31];
assign T64[31] = T65;
assign T65 = ~io_signedOut;
assign T66[31] = T72[31] | 1'b0;
assign T66[30] = 1'b0 | T75[30];
assign T66[29] = 1'b0 | T75[30];
assign T66[28] = 1'b0 | T75[30];
assign T66[27] = 1'b0 | T75[30];
assign T66[26] = 1'b0 | T75[30];
assign T66[25] = 1'b0 | T75[30];
assign T66[24] = 1'b0 | T75[30];
assign T66[23] = 1'b0 | T75[30];
assign T66[22] = 1'b0 | T75[30];
assign T66[21] = 1'b0 | T75[30];
assign T66[20] = 1'b0 | T75[30];
assign T66[19] = 1'b0 | T75[30];
assign T66[18] = 1'b0 | T75[30];
assign T66[17] = 1'b0 | T75[30];
assign T66[16] = 1'b0 | T75[30];
assign T66[15] = 1'b0 | T75[30];
assign T66[14] = 1'b0 | T75[30];
assign T66[13] = 1'b0 | T75[30];
assign T66[12] = 1'b0 | T75[30];
assign T66[11] = 1'b0 | T75[30];
assign T66[10] = 1'b0 | T75[30];
assign T66[9] = 1'b0 | T75[30];
assign T66[8] = 1'b0 | T75[30];
assign T66[7] = 1'b0 | T75[30];
assign T66[6] = 1'b0 | T75[30];
assign T66[5] = 1'b0 | T75[30];
assign T66[4] = 1'b0 | T75[30];
assign T66[3] = 1'b0 | T75[30];
assign T66[2] = 1'b0 | T75[30];
assign T66[1] = 1'b0 | T75[30];
assign T66[0] = 1'b0 | T75[30];
assign T75[30] = T68;
assign T68 = io_signedOut & T69;
assign T69 = ~excSign;
assign excSign = io_in[64] & T70;
assign T70 = ~isNaN;
assign isNaN = io_intExceptionFlags[2] & io_in[61];
assign T72[31] = T73;
assign T73 = io_signedOut & excSign;
assign T74 = io_intExceptionFlags[2] | io_intExceptionFlags[1];
endmodule |
module RRArbiter_1
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_rw,
io_in_1_bits_addr,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_rw,
io_in_0_bits_addr,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_rw,
io_out_bits_addr,
io_out_bits_data,
io_chosen
);
input [11:0] io_in_1_bits_addr;
input [63:0] io_in_1_bits_data;
input [11:0] io_in_0_bits_addr;
input [63:0] io_in_0_bits_data;
output [11:0] io_out_bits_addr;
output [63:0] io_out_bits_data;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_rw;
input io_in_0_valid;
input io_in_0_bits_rw;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_rw;
output io_chosen;
wire [11:0] io_out_bits_addr;
wire [63:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_rw,io_chosen,N0,N1,N2,N3,
N4,N5,N6,T1,N7,T2,T4,N8,T11,T18,T12,T13,T16,T14,T15,T17,T20,T24,T21,T22,T23,T26,
T25,N9,N10,N11,N12,N13,N14,N15;
reg last_grant;
assign T17 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T18 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N11) begin
last_grant <= N12;
end
end
assign N15 = ~io_in_0_valid;
assign io_chosen = (N2)? 1'b1 :
(N3)? N15 : 1'b0;
assign N2 = T1;
assign N3 = N7;
assign io_out_bits_data = (N4)? io_in_1_bits_data :
(N5)? io_in_0_bits_data : 1'b0;
assign N4 = io_chosen;
assign N5 = N8;
assign io_out_bits_addr = (N4)? io_in_1_bits_addr :
(N5)? io_in_0_bits_addr : 1'b0;
assign io_out_bits_rw = (N4)? io_in_1_bits_rw :
(N5)? io_in_0_bits_rw : 1'b0;
assign io_out_valid = (N4)? io_in_1_valid :
(N5)? io_in_0_valid : 1'b0;
assign N11 = (N6)? 1'b1 :
(N14)? 1'b1 :
(N10)? 1'b0 : 1'b0;
assign N6 = reset;
assign N12 = (N6)? 1'b0 :
(N14)? io_chosen : 1'b0;
assign N7 = ~T1;
assign T1 = io_in_1_valid & T2;
assign T2 = ~last_grant;
assign T4 = io_out_ready & io_out_valid;
assign N8 = ~io_chosen;
assign io_in_0_ready = T11 & io_out_ready;
assign T11 = T18 | T12;
assign T12 = ~T13;
assign T13 = T16 | T14;
assign T14 = io_in_1_valid & T15;
assign T15 = ~last_grant;
assign T16 = io_in_0_valid & T17;
assign io_in_1_ready = T20 & io_out_ready;
assign T20 = T24 | T21;
assign T21 = ~T22;
assign T22 = T23 | io_in_0_valid;
assign T23 = T16 | T14;
assign T24 = T26 & T25;
assign T25 = ~last_grant;
assign T26 = ~T16;
assign N9 = T4 | reset;
assign N10 = ~N9;
assign N13 = ~reset;
assign N14 = T4 & N13;
endmodule |
module Queue_13
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_header_src,
io_enq_bits_header_dst,
io_enq_bits_payload_addr_block,
io_enq_bits_payload_p_type,
io_deq_ready,
io_deq_valid,
io_deq_bits_header_src,
io_deq_bits_header_dst,
io_deq_bits_payload_addr_block,
io_deq_bits_payload_p_type,
io_count
);
input [2:0] io_enq_bits_header_src;
input [2:0] io_enq_bits_header_dst;
input [25:0] io_enq_bits_payload_addr_block;
input [1:0] io_enq_bits_payload_p_type;
output [2:0] io_deq_bits_header_src;
output [2:0] io_deq_bits_header_dst;
output [25:0] io_deq_bits_payload_addr_block;
output [1:0] io_deq_bits_payload_p_type;
output [1:0] io_count;
input clk;
input reset;
input io_enq_valid;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
wire [2:0] io_deq_bits_header_src,io_deq_bits_header_dst;
wire [25:0] io_deq_bits_payload_addr_block;
wire [1:0] io_deq_bits_payload_p_type,io_count;
wire io_enq_ready,io_deq_valid,N0,N1,N2,N3,N4,do_deq,T3,do_enq,T6,ptr_match,T9,N5,
empty,T21,full,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N21,N22,N23,N24,
N25,N26;
reg R1,N20,maybe_full;
reg [67:0] ram;
assign N0 = N20 ^ R1;
assign ptr_match = ~N0;
assign T9 = do_enq ^ do_deq;
assign io_deq_bits_header_src[2] = (N5)? ram[33] :
(N1)? ram[67] : 1'b0;
assign N1 = R1;
assign io_deq_bits_header_src[1] = (N5)? ram[32] :
(N1)? ram[66] : 1'b0;
assign io_deq_bits_header_src[0] = (N5)? ram[31] :
(N1)? ram[65] : 1'b0;
assign io_deq_bits_header_dst[2] = (N5)? ram[30] :
(N1)? ram[64] : 1'b0;
assign io_deq_bits_header_dst[1] = (N5)? ram[29] :
(N1)? ram[63] : 1'b0;
assign io_deq_bits_header_dst[0] = (N5)? ram[28] :
(N1)? ram[62] : 1'b0;
assign io_deq_bits_payload_addr_block[25] = (N5)? ram[27] :
(N1)? ram[61] : 1'b0;
assign io_deq_bits_payload_addr_block[24] = (N5)? ram[26] :
(N1)? ram[60] : 1'b0;
assign io_deq_bits_payload_addr_block[23] = (N5)? ram[25] :
(N1)? ram[59] : 1'b0;
assign io_deq_bits_payload_addr_block[22] = (N5)? ram[24] :
(N1)? ram[58] : 1'b0;
assign io_deq_bits_payload_addr_block[21] = (N5)? ram[23] :
(N1)? ram[57] : 1'b0;
assign io_deq_bits_payload_addr_block[20] = (N5)? ram[22] :
(N1)? ram[56] : 1'b0;
assign io_deq_bits_payload_addr_block[19] = (N5)? ram[21] :
(N1)? ram[55] : 1'b0;
assign io_deq_bits_payload_addr_block[18] = (N5)? ram[20] :
(N1)? ram[54] : 1'b0;
assign io_deq_bits_payload_addr_block[17] = (N5)? ram[19] :
(N1)? ram[53] : 1'b0;
assign io_deq_bits_payload_addr_block[16] = (N5)? ram[18] :
(N1)? ram[52] : 1'b0;
assign io_deq_bits_payload_addr_block[15] = (N5)? ram[17] :
(N1)? ram[51] : 1'b0;
assign io_deq_bits_payload_addr_block[14] = (N5)? ram[16] :
(N1)? ram[50] : 1'b0;
assign io_deq_bits_payload_addr_block[13] = (N5)? ram[15] :
(N1)? ram[49] : 1'b0;
assign io_deq_bits_payload_addr_block[12] = (N5)? ram[14] :
(N1)? ram[48] : 1'b0;
assign io_deq_bits_payload_addr_block[11] = (N5)? ram[13] :
(N1)? ram[47] : 1'b0;
assign io_deq_bits_payload_addr_block[10] = (N5)? ram[12] :
(N1)? ram[46] : 1'b0;
assign io_deq_bits_payload_addr_block[9] = (N5)? ram[11] :
(N1)? ram[45] : 1'b0;
assign io_deq_bits_payload_addr_block[8] = (N5)? ram[10] :
(N1)? ram[44] : 1'b0;
assign io_deq_bits_payload_addr_block[7] = (N5)? ram[9] :
(N1)? ram[43] : 1'b0;
assign io_deq_bits_payload_addr_block[6] = (N5)? ram[8] :
(N1)? ram[42] : 1'b0;
assign io_deq_bits_payload_addr_block[5] = (N5)? ram[7] :
(N1)? ram[41] : 1'b0;
assign io_deq_bits_payload_addr_block[4] = (N5)? ram[6] :
(N1)? ram[40] : 1'b0;
assign io_deq_bits_payload_addr_block[3] = (N5)? ram[5] :
(N1)? ram[39] : 1'b0;
assign io_deq_bits_payload_addr_block[2] = (N5)? ram[4] :
(N1)? ram[38] : 1'b0;
assign io_deq_bits_payload_addr_block[1] = (N5)? ram[3] :
(N1)? ram[37] : 1'b0;
assign io_deq_bits_payload_addr_block[0] = (N5)? ram[2] :
(N1)? ram[36] : 1'b0;
assign io_deq_bits_payload_p_type[1] = (N5)? ram[1] :
(N1)? ram[35] : 1'b0;
assign io_deq_bits_payload_p_type[0] = (N5)? ram[0] :
(N1)? ram[34] : 1'b0;
always @(posedge clk) begin
if(N8) begin
R1 <= N9;
end
end
always @(posedge clk) begin
if(N12) begin
N20 <= N13;
end
end
always @(posedge clk) begin
if(N16) begin
maybe_full <= N17;
end
end
always @(posedge clk) begin
if(N22) begin
ram[67] <= io_enq_bits_header_src[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[66] <= io_enq_bits_header_src[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[65] <= io_enq_bits_header_src[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[64] <= io_enq_bits_header_dst[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[63] <= io_enq_bits_header_dst[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[62] <= io_enq_bits_header_dst[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[61] <= io_enq_bits_payload_addr_block[25];
end
end
always @(posedge clk) begin
if(N22) begin
ram[60] <= io_enq_bits_payload_addr_block[24];
end
end
always @(posedge clk) begin
if(N22) begin
ram[59] <= io_enq_bits_payload_addr_block[23];
end
end
always @(posedge clk) begin
if(N22) begin
ram[58] <= io_enq_bits_payload_addr_block[22];
end
end
always @(posedge clk) begin
if(N22) begin
ram[57] <= io_enq_bits_payload_addr_block[21];
end
end
always @(posedge clk) begin
if(N22) begin
ram[56] <= io_enq_bits_payload_addr_block[20];
end
end
always @(posedge clk) begin
if(N22) begin
ram[55] <= io_enq_bits_payload_addr_block[19];
end
end
always @(posedge clk) begin
if(N22) begin
ram[54] <= io_enq_bits_payload_addr_block[18];
end
end
always @(posedge clk) begin
if(N22) begin
ram[53] <= io_enq_bits_payload_addr_block[17];
end
end
always @(posedge clk) begin
if(N22) begin
ram[52] <= io_enq_bits_payload_addr_block[16];
end
end
always @(posedge clk) begin
if(N22) begin
ram[51] <= io_enq_bits_payload_addr_block[15];
end
end
always @(posedge clk) begin
if(N22) begin
ram[50] <= io_enq_bits_payload_addr_block[14];
end
end
always @(posedge clk) begin
if(N22) begin
ram[49] <= io_enq_bits_payload_addr_block[13];
end
end
always @(posedge clk) begin
if(N22) begin
ram[48] <= io_enq_bits_payload_addr_block[12];
end
end
always @(posedge clk) begin
if(N22) begin
ram[47] <= io_enq_bits_payload_addr_block[11];
end
end
always @(posedge clk) begin
if(N22) begin
ram[46] <= io_enq_bits_payload_addr_block[10];
end
end
always @(posedge clk) begin
if(N22) begin
ram[45] <= io_enq_bits_payload_addr_block[9];
end
end
always @(posedge clk) begin
if(N22) begin
ram[44] <= io_enq_bits_payload_addr_block[8];
end
end
always @(posedge clk) begin
if(N22) begin
ram[43] <= io_enq_bits_payload_addr_block[7];
end
end
always @(posedge clk) begin
if(N22) begin
ram[42] <= io_enq_bits_payload_addr_block[6];
end
end
always @(posedge clk) begin
if(N22) begin
ram[41] <= io_enq_bits_payload_addr_block[5];
end
end
always @(posedge clk) begin
if(N22) begin
ram[40] <= io_enq_bits_payload_addr_block[4];
end
end
always @(posedge clk) begin
if(N22) begin
ram[39] <= io_enq_bits_payload_addr_block[3];
end
end
always @(posedge clk) begin
if(N22) begin
ram[38] <= io_enq_bits_payload_addr_block[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[37] <= io_enq_bits_payload_addr_block[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[36] <= io_enq_bits_payload_addr_block[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[35] <= io_enq_bits_payload_p_type[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[34] <= io_enq_bits_payload_p_type[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[33] <= io_enq_bits_header_src[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[32] <= io_enq_bits_header_src[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[31] <= io_enq_bits_header_src[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[30] <= io_enq_bits_header_dst[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[29] <= io_enq_bits_header_dst[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[28] <= io_enq_bits_header_dst[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[27] <= io_enq_bits_payload_addr_block[25];
end
end
always @(posedge clk) begin
if(N21) begin
ram[26] <= io_enq_bits_payload_addr_block[24];
end
end
always @(posedge clk) begin
if(N21) begin
ram[25] <= io_enq_bits_payload_addr_block[23];
end
end
always @(posedge clk) begin
if(N21) begin
ram[24] <= io_enq_bits_payload_addr_block[22];
end
end
always @(posedge clk) begin
if(N21) begin
ram[23] <= io_enq_bits_payload_addr_block[21];
end
end
always @(posedge clk) begin
if(N21) begin
ram[22] <= io_enq_bits_payload_addr_block[20];
end
end
always @(posedge clk) begin
if(N21) begin
ram[21] <= io_enq_bits_payload_addr_block[19];
end
end
always @(posedge clk) begin
if(N21) begin
ram[20] <= io_enq_bits_payload_addr_block[18];
end
end
always @(posedge clk) begin
if(N21) begin
ram[19] <= io_enq_bits_payload_addr_block[17];
end
end
always @(posedge clk) begin
if(N21) begin
ram[18] <= io_enq_bits_payload_addr_block[16];
end
end
always @(posedge clk) begin
if(N21) begin
ram[17] <= io_enq_bits_payload_addr_block[15];
end
end
always @(posedge clk) begin
if(N21) begin
ram[16] <= io_enq_bits_payload_addr_block[14];
end
end
always @(posedge clk) begin
if(N21) begin
ram[15] <= io_enq_bits_payload_addr_block[13];
end
end
always @(posedge clk) begin
if(N21) begin
ram[14] <= io_enq_bits_payload_addr_block[12];
end
end
always @(posedge clk) begin
if(N21) begin
ram[13] <= io_enq_bits_payload_addr_block[11];
end
end
always @(posedge clk) begin
if(N21) begin
ram[12] <= io_enq_bits_payload_addr_block[10];
end
end
always @(posedge clk) begin
if(N21) begin
ram[11] <= io_enq_bits_payload_addr_block[9];
end
end
always @(posedge clk) begin
if(N21) begin
ram[10] <= io_enq_bits_payload_addr_block[8];
end
end
always @(posedge clk) begin
if(N21) begin
ram[9] <= io_enq_bits_payload_addr_block[7];
end
end
always @(posedge clk) begin
if(N21) begin
ram[8] <= io_enq_bits_payload_addr_block[6];
end
end
always @(posedge clk) begin
if(N21) begin
ram[7] <= io_enq_bits_payload_addr_block[5];
end
end
always @(posedge clk) begin
if(N21) begin
ram[6] <= io_enq_bits_payload_addr_block[4];
end
end
always @(posedge clk) begin
if(N21) begin
ram[5] <= io_enq_bits_payload_addr_block[3];
end
end
always @(posedge clk) begin
if(N21) begin
ram[4] <= io_enq_bits_payload_addr_block[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[3] <= io_enq_bits_payload_addr_block[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[2] <= io_enq_bits_payload_addr_block[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[1] <= io_enq_bits_payload_p_type[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[0] <= io_enq_bits_payload_p_type[0];
end
end
assign io_count[0] = N20 ^ R1;
assign T3 = R1 ^ 1'b1;
assign T6 = N20 ^ 1'b1;
assign N19 = ~N20;
assign N8 = (N2)? 1'b1 :
(N24)? 1'b1 :
(N7)? 1'b0 : 1'b0;
assign N2 = reset;
assign N9 = (N2)? 1'b0 :
(N24)? T3 : 1'b0;
assign N12 = (N2)? 1'b1 :
(N25)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign N13 = (N2)? 1'b0 :
(N25)? T6 : 1'b0;
assign N16 = (N2)? 1'b1 :
(N26)? 1'b1 :
(N15)? 1'b0 : 1'b0;
assign N17 = (N2)? 1'b0 :
(N26)? do_enq : 1'b0;
assign { N22, N21 } = (N3)? { N20, N19 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign N3 = do_enq;
assign N4 = N18;
assign do_deq = io_deq_ready & io_deq_valid;
assign do_enq = io_enq_ready & io_enq_valid;
assign io_count[1] = maybe_full & ptr_match;
assign N5 = ~R1;
assign io_deq_valid = ~empty;
assign empty = ptr_match & T21;
assign T21 = ~maybe_full;
assign io_enq_ready = ~full;
assign full = ptr_match & maybe_full;
assign N6 = do_deq | reset;
assign N7 = ~N6;
assign N10 = do_enq | reset;
assign N11 = ~N10;
assign N14 = T9 | reset;
assign N15 = ~N14;
assign N18 = ~do_enq;
assign N23 = ~reset;
assign N24 = do_deq & N23;
assign N25 = do_enq & N23;
assign N26 = T9 & N23;
endmodule |
module Queue_18
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits,
io_deq_ready,
io_deq_valid,
io_deq_bits,
io_count
);
input [5:0] io_enq_bits;
output [5:0] io_deq_bits;
output [1:0] io_count;
input clk;
input reset;
input io_enq_valid;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
wire [5:0] io_deq_bits;
wire [1:0] io_count;
wire io_enq_ready,io_deq_valid,N0,N1,N2,N3,N4,do_deq,T3,do_enq,T6,ptr_match,T9,N5,
empty,T13,full,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N21,N22,N23,N24,
N25,N26;
reg R1,N20,maybe_full;
reg [11:0] ram;
assign N0 = N20 ^ R1;
assign ptr_match = ~N0;
assign T9 = do_enq ^ do_deq;
assign io_deq_bits[5] = (N5)? ram[5] :
(N1)? ram[11] : 1'b0;
assign N1 = R1;
assign io_deq_bits[4] = (N5)? ram[4] :
(N1)? ram[10] : 1'b0;
assign io_deq_bits[3] = (N5)? ram[3] :
(N1)? ram[9] : 1'b0;
assign io_deq_bits[2] = (N5)? ram[2] :
(N1)? ram[8] : 1'b0;
assign io_deq_bits[1] = (N5)? ram[1] :
(N1)? ram[7] : 1'b0;
assign io_deq_bits[0] = (N5)? ram[0] :
(N1)? ram[6] : 1'b0;
always @(posedge clk) begin
if(N8) begin
R1 <= N9;
end
end
always @(posedge clk) begin
if(N12) begin
N20 <= N13;
end
end
always @(posedge clk) begin
if(N16) begin
maybe_full <= N17;
end
end
always @(posedge clk) begin
if(N22) begin
ram[11] <= io_enq_bits[5];
end
end
always @(posedge clk) begin
if(N22) begin
ram[10] <= io_enq_bits[4];
end
end
always @(posedge clk) begin
if(N22) begin
ram[9] <= io_enq_bits[3];
end
end
always @(posedge clk) begin
if(N22) begin
ram[8] <= io_enq_bits[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[7] <= io_enq_bits[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[6] <= io_enq_bits[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[5] <= io_enq_bits[5];
end
end
always @(posedge clk) begin
if(N21) begin
ram[4] <= io_enq_bits[4];
end
end
always @(posedge clk) begin
if(N21) begin
ram[3] <= io_enq_bits[3];
end
end
always @(posedge clk) begin
if(N21) begin
ram[2] <= io_enq_bits[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[1] <= io_enq_bits[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[0] <= io_enq_bits[0];
end
end
assign io_count[0] = N20 ^ R1;
assign T3 = R1 ^ 1'b1;
assign T6 = N20 ^ 1'b1;
assign N19 = ~N20;
assign N8 = (N2)? 1'b1 :
(N24)? 1'b1 :
(N7)? 1'b0 : 1'b0;
assign N2 = reset;
assign N9 = (N2)? 1'b0 :
(N24)? T3 : 1'b0;
assign N12 = (N2)? 1'b1 :
(N25)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign N13 = (N2)? 1'b0 :
(N25)? T6 : 1'b0;
assign N16 = (N2)? 1'b1 :
(N26)? 1'b1 :
(N15)? 1'b0 : 1'b0;
assign N17 = (N2)? 1'b0 :
(N26)? do_enq : 1'b0;
assign { N22, N21 } = (N3)? { N20, N19 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign N3 = do_enq;
assign N4 = N18;
assign do_deq = io_deq_ready & io_deq_valid;
assign do_enq = io_enq_ready & io_enq_valid;
assign io_count[1] = maybe_full & ptr_match;
assign N5 = ~R1;
assign io_deq_valid = ~empty;
assign empty = ptr_match & T13;
assign T13 = ~maybe_full;
assign io_enq_ready = ~full;
assign full = ptr_match & maybe_full;
assign N6 = do_deq | reset;
assign N7 = ~N6;
assign N10 = do_enq | reset;
assign N11 = ~N10;
assign N14 = T9 | reset;
assign N15 = ~N14;
assign N18 = ~do_enq;
assign N23 = ~reset;
assign N24 = do_deq & N23;
assign N25 = do_enq & N23;
assign N26 = T9 & N23;
endmodule |
module JunctionsPeekingArbiter_1
(
clk,
reset,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_resp,
io_in_3_bits_data,
io_in_3_bits_last,
io_in_3_bits_id,
io_in_3_bits_user,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_resp,
io_in_2_bits_data,
io_in_2_bits_last,
io_in_2_bits_id,
io_in_2_bits_user,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_resp,
io_in_1_bits_data,
io_in_1_bits_last,
io_in_1_bits_id,
io_in_1_bits_user,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_resp,
io_in_0_bits_data,
io_in_0_bits_last,
io_in_0_bits_id,
io_in_0_bits_user,
io_out_ready,
io_out_valid,
io_out_bits_resp,
io_out_bits_data,
io_out_bits_last,
io_out_bits_id,
io_out_bits_user
);
input [1:0] io_in_3_bits_resp;
input [63:0] io_in_3_bits_data;
input [5:0] io_in_3_bits_id;
input [1:0] io_in_2_bits_resp;
input [63:0] io_in_2_bits_data;
input [5:0] io_in_2_bits_id;
input [1:0] io_in_1_bits_resp;
input [63:0] io_in_1_bits_data;
input [5:0] io_in_1_bits_id;
input [1:0] io_in_0_bits_resp;
input [63:0] io_in_0_bits_data;
input [5:0] io_in_0_bits_id;
output [1:0] io_out_bits_resp;
output [63:0] io_out_bits_data;
output [5:0] io_out_bits_id;
input clk;
input reset;
input io_in_3_valid;
input io_in_3_bits_last;
input io_in_3_bits_user;
input io_in_2_valid;
input io_in_2_bits_last;
input io_in_2_bits_user;
input io_in_1_valid;
input io_in_1_bits_last;
input io_in_1_bits_user;
input io_in_0_valid;
input io_in_0_bits_last;
input io_in_0_bits_user;
input io_out_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_last;
output io_out_bits_user;
wire [1:0] io_out_bits_resp,T3,choice,T63,T4,T39,T5,T14,T6,T11,T7,T9,T12,T17,T15,T16,T18,
T24,T33,T42,T40,T41,T43,T49,T57,T66,T64,T135,T73,T118,T116;
wire [63:0] io_out_bits_data,T112,T110;
wire [5:0] io_out_bits_id,T100,T98;
wire io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,
io_out_bits_last,io_out_bits_user,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,
N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,
N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,
N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,
N76,N77,N78,T94,T1,N79,T69,N80,T45,N81,T20,N82,T13,N83,N84,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N97,N98,N99,T19,N100,N101,N102,N103,N104,N105,N106,N107,
N108,N109,N110,N111,N112,N113,N114,N115,N116,T38,N117,T30,T21,N118,T27,T22,N119,
N120,T35,T31,N121,T44,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,
N133,N134,N135,N136,N137,N138,T62,N139,T54,T46,N140,T51,T47,N141,N142,T59,T55,N143,
T68,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,
T86,N159,T78,T70,N160,T75,T71,N161,T83,T79,T88,T90,T89,T93,T106,T104,T124,T122,
N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,
N178,N179,N180,N181,N182,N183,N184,N185,N186,N187;
reg [1:0] lockIdx;
reg locked;
assign N86 = N84 & N85;
assign N87 = T9[1] | N85;
assign N89 = N84 | T9[0];
assign N91 = T9[1] & T9[0];
assign N94 = N92 & N93;
assign N95 = T12[1] | N93;
assign N97 = N92 | T12[0];
assign N99 = T12[1] & T12[0];
assign N103 = N101 & N102;
assign N104 = T16[1] | N102;
assign N106 = N101 | T16[0];
assign N108 = T16[1] & T16[0];
assign N111 = N109 & N110;
assign N112 = T18[1] | N110;
assign N114 = N109 | T18[0];
assign N116 = T18[1] & T18[0];
assign N125 = N123 & N124;
assign N126 = T41[1] | N124;
assign N128 = N123 | T41[0];
assign N130 = T41[1] & T41[0];
assign N133 = N131 & N132;
assign N134 = T43[1] | N132;
assign N136 = N131 | T43[0];
assign N138 = T43[1] & T43[0];
assign T44 = T135 < { 1'b1, 1'b1 };
assign T62 = T73 < { 1'b1, 1'b1 };
assign N147 = N145 & N146;
assign N148 = T135[1] | N146;
assign N150 = N145 | T135[0];
assign N152 = T135[1] & T135[0];
assign N153 = N145 & N146;
assign N154 = T135[1] | N146;
assign N156 = N145 | T135[0];
assign N158 = T135[1] & T135[0];
always @(posedge clk) begin
if(N164) begin
lockIdx[1] <= N166;
end
end
always @(posedge clk) begin
if(N164) begin
lockIdx[0] <= N165;
end
end
always @(posedge clk) begin
if(N170) begin
locked <= N171;
end
end
assign N178 = T3[0] & T3[1];
assign N179 = ~T3[1];
assign N180 = T3[0] | N179;
assign N181 = ~N180;
assign N182 = ~T3[0];
assign N183 = N182 | T3[1];
assign N184 = ~N183;
assign N185 = T3[0] | T3[1];
assign N186 = ~N185;
assign T135 = lockIdx + 1'b1;
assign T73 = lockIdx + 1'b1;
assign T9 = T135 - 1'b1;
assign T12 = { 1'b1, 1'b1 } + T135;
assign T16 = T135 - { 1'b1, 1'b0 };
assign T18 = { 1'b1, 1'b0 } + T135;
assign T41 = T135 - { 1'b1, 1'b1 };
assign T43 = 1'b1 + T135;
assign T24 = T73 - { 1'b1, 1'b0 };
assign T33 = { 1'b1, 1'b0 } + T73;
assign T49 = T73 - { 1'b1, 1'b1 };
assign T57 = 1'b1 + T73;
assign io_out_bits_user = (N0)? T94 :
(N1)? T1 : 1'b0;
assign N0 = T3[1];
assign N1 = N179;
assign T1 = (N2)? io_in_1_bits_user :
(N3)? io_in_0_bits_user : 1'b0;
assign N2 = T3[0];
assign N3 = N182;
assign T3 = (N4)? lockIdx :
(N5)? choice : 1'b0;
assign N4 = locked;
assign N5 = N79;
assign choice = (N6)? T63 :
(N7)? T4 : 1'b0;
assign N6 = T69;
assign N7 = N80;
assign T4 = (N8)? T39 :
(N9)? T5 : 1'b0;
assign N8 = T45;
assign N9 = N81;
assign T5 = (N10)? T14 :
(N11)? T6 : 1'b0;
assign N10 = T20;
assign N11 = N82;
assign T6 = (N12)? T11 :
(N13)? T7 : 1'b0;
assign N12 = T13;
assign N13 = N83;
assign T7 = (N14)? { 1'b0, 1'b0 } :
(N15)? { 1'b0, 1'b1 } :
(N16)? { 1'b1, 1'b0 } :
(N17)? { 1'b1, 1'b1 } : 1'b0;
assign N14 = N86;
assign N15 = N88;
assign N16 = N90;
assign N17 = N91;
assign T11 = (N18)? { 1'b0, 1'b0 } :
(N19)? { 1'b0, 1'b1 } :
(N20)? { 1'b1, 1'b0 } :
(N21)? { 1'b1, 1'b1 } : 1'b0;
assign N18 = N94;
assign N19 = N96;
assign N20 = N98;
assign N21 = N99;
assign T14 = (N22)? T17 :
(N23)? T15 : 1'b0;
assign N22 = T19;
assign N23 = N100;
assign T15 = (N24)? { 1'b0, 1'b0 } :
(N25)? { 1'b0, 1'b1 } :
(N26)? { 1'b1, 1'b0 } :
(N27)? { 1'b1, 1'b1 } : 1'b0;
assign N24 = N103;
assign N25 = N105;
assign N26 = N107;
assign N27 = N108;
assign T17 = (N28)? { 1'b0, 1'b0 } :
(N29)? { 1'b0, 1'b1 } :
(N30)? { 1'b1, 1'b0 } :
(N31)? { 1'b1, 1'b1 } : 1'b0;
assign N28 = N111;
assign N29 = N113;
assign N30 = N115;
assign N31 = N116;
assign T20 = (N32)? T30 :
(N33)? T21 : 1'b0;
assign N32 = T38;
assign N33 = N117;
assign T21 = (N34)? T27 :
(N35)? T22 : 1'b0;
assign N34 = T24[1];
assign N35 = N118;
assign T22 = (N36)? io_in_1_valid :
(N37)? io_in_0_valid : 1'b0;
assign N36 = T24[0];
assign N37 = N119;
assign T27 = (N36)? io_in_3_valid :
(N37)? io_in_2_valid : 1'b0;
assign T30 = (N38)? T35 :
(N39)? T31 : 1'b0;
assign N38 = T33[1];
assign N39 = N120;
assign T31 = (N40)? io_in_1_valid :
(N41)? io_in_0_valid : 1'b0;
assign N40 = T33[0];
assign N41 = N121;
assign T35 = (N40)? io_in_3_valid :
(N41)? io_in_2_valid : 1'b0;
assign T39 = (N42)? T42 :
(N43)? T40 : 1'b0;
assign N42 = T44;
assign N43 = N122;
assign T40 = (N44)? { 1'b0, 1'b0 } :
(N45)? { 1'b0, 1'b1 } :
(N46)? { 1'b1, 1'b0 } :
(N47)? { 1'b1, 1'b1 } : 1'b0;
assign N44 = N125;
assign N45 = N127;
assign N46 = N129;
assign N47 = N130;
assign T42 = (N48)? { 1'b0, 1'b0 } :
(N49)? { 1'b0, 1'b1 } :
(N50)? { 1'b1, 1'b0 } :
(N51)? { 1'b1, 1'b1 } : 1'b0;
assign N48 = N133;
assign N49 = N135;
assign N50 = N137;
assign N51 = N138;
assign T45 = (N52)? T54 :
(N53)? T46 : 1'b0;
assign N52 = T62;
assign N53 = N139;
assign T46 = (N54)? T51 :
(N55)? T47 : 1'b0;
assign N54 = T49[1];
assign N55 = N140;
assign T47 = (N56)? io_in_1_valid :
(N57)? io_in_0_valid : 1'b0;
assign N56 = T49[0];
assign N57 = N141;
assign T51 = (N56)? io_in_3_valid :
(N57)? io_in_2_valid : 1'b0;
assign T54 = (N58)? T59 :
(N59)? T55 : 1'b0;
assign N58 = T57[1];
assign N59 = N142;
assign T55 = (N60)? io_in_1_valid :
(N61)? io_in_0_valid : 1'b0;
assign N60 = T57[0];
assign N61 = N143;
assign T59 = (N60)? io_in_3_valid :
(N61)? io_in_2_valid : 1'b0;
assign T63 = (N62)? T66 :
(N63)? T64 : 1'b0;
assign N62 = T68;
assign N63 = N144;
assign T64 = (N64)? { 1'b0, 1'b0 } :
(N65)? { 1'b0, 1'b1 } :
(N66)? { 1'b1, 1'b0 } :
(N67)? { 1'b1, 1'b1 } : 1'b0;
assign N64 = N147;
assign N65 = N149;
assign N66 = N151;
assign N67 = N152;
assign T66 = (N68)? { 1'b0, 1'b0 } :
(N69)? { 1'b0, 1'b1 } :
(N70)? { 1'b1, 1'b0 } :
(N71)? { 1'b1, 1'b1 } : 1'b0;
assign N68 = N153;
assign N69 = N155;
assign N70 = N157;
assign N71 = N158;
assign T69 = (N72)? T78 :
(N73)? T70 : 1'b0;
assign N72 = T86;
assign N73 = N159;
assign T70 = (N74)? T75 :
(N75)? T71 : 1'b0;
assign N74 = T73[1];
assign N75 = N160;
assign T71 = (N76)? io_in_1_valid :
(N77)? io_in_0_valid : 1'b0;
assign N76 = T73[0];
assign N77 = N161;
assign T75 = (N76)? io_in_3_valid :
(N77)? io_in_2_valid : 1'b0;
assign T78 = (N74)? T83 :
(N75)? T79 : 1'b0;
assign T79 = (N76)? io_in_1_valid :
(N77)? io_in_0_valid : 1'b0;
assign T83 = (N76)? io_in_3_valid :
(N77)? io_in_2_valid : 1'b0;
assign T94 = (N2)? io_in_3_bits_user :
(N3)? io_in_2_bits_user : 1'b0;
assign io_out_bits_id = (N0)? T100 :
(N1)? T98 : 1'b0;
assign T98 = (N2)? io_in_1_bits_id :
(N3)? io_in_0_bits_id : 1'b0;
assign T100 = (N2)? io_in_3_bits_id :
(N3)? io_in_2_bits_id : 1'b0;
assign io_out_bits_last = (N0)? T106 :
(N1)? T104 : 1'b0;
assign T104 = (N2)? io_in_1_bits_last :
(N3)? io_in_0_bits_last : 1'b0;
assign T106 = (N2)? io_in_3_bits_last :
(N3)? io_in_2_bits_last : 1'b0;
assign io_out_bits_data = (N0)? T112 :
(N1)? T110 : 1'b0;
assign T110 = (N2)? io_in_1_bits_data :
(N3)? io_in_0_bits_data : 1'b0;
assign T112 = (N2)? io_in_3_bits_data :
(N3)? io_in_2_bits_data : 1'b0;
assign io_out_bits_resp = (N0)? T118 :
(N1)? T116 : 1'b0;
assign T116 = (N2)? io_in_1_bits_resp :
(N3)? io_in_0_bits_resp : 1'b0;
assign T118 = (N2)? io_in_3_bits_resp :
(N3)? io_in_2_bits_resp : 1'b0;
assign io_out_valid = (N0)? T124 :
(N1)? T122 : 1'b0;
assign T122 = (N2)? io_in_1_valid :
(N3)? io_in_0_valid : 1'b0;
assign T124 = (N2)? io_in_3_valid :
(N3)? io_in_2_valid : 1'b0;
assign N164 = (N78)? 1'b1 :
(N173)? 1'b1 :
(N163)? 1'b0 : 1'b0;
assign N78 = reset;
assign { N166, N165 } = (N78)? { 1'b0, 1'b0 } :
(N173)? choice : 1'b0;
assign N170 = (N78)? 1'b1 :
(N174)? 1'b1 :
(N177)? 1'b1 :
(N169)? 1'b0 : 1'b0;
assign N171 = (N78)? 1'b0 :
(N174)? 1'b0 :
(N177)? 1'b1 : 1'b0;
assign N79 = ~locked;
assign N80 = ~T69;
assign N81 = ~T45;
assign N82 = ~T20;
assign N83 = ~T13;
assign N84 = ~T9[1];
assign N85 = ~T9[0];
assign N88 = ~N87;
assign N90 = ~N89;
assign N92 = ~T12[1];
assign N93 = ~T12[0];
assign N96 = ~N95;
assign N98 = ~N97;
assign T13 = ~N187;
assign N187 = T135[1] | T135[0];
assign N100 = ~T19;
assign N101 = ~T16[1];
assign N102 = ~T16[0];
assign N105 = ~N104;
assign N107 = ~N106;
assign N109 = ~T18[1];
assign N110 = ~T18[0];
assign N113 = ~N112;
assign N115 = ~N114;
assign T19 = ~T135[1];
assign N117 = ~T38;
assign N118 = ~T24[1];
assign N119 = ~T24[0];
assign N120 = ~T33[1];
assign N121 = ~T33[0];
assign T38 = ~T73[1];
assign N122 = ~T44;
assign N123 = ~T41[1];
assign N124 = ~T41[0];
assign N127 = ~N126;
assign N129 = ~N128;
assign N131 = ~T43[1];
assign N132 = ~T43[0];
assign N135 = ~N134;
assign N137 = ~N136;
assign N139 = ~T62;
assign N140 = ~T49[1];
assign N141 = ~T49[0];
assign N142 = ~T57[1];
assign N143 = ~T57[0];
assign N144 = ~T68;
assign N145 = ~T135[1];
assign N146 = ~T135[0];
assign N149 = ~N148;
assign N151 = ~N150;
assign N155 = ~N154;
assign N157 = ~N156;
assign T68 = ~1'b0;
assign N159 = ~T86;
assign N160 = ~T73[1];
assign N161 = ~T73[0];
assign T86 = ~1'b0;
assign T88 = T90 & T89;
assign T89 = ~locked;
assign T90 = io_out_ready & io_out_valid;
assign T93 = T90 & io_out_bits_last;
assign io_in_0_ready = io_out_ready & N186;
assign io_in_1_ready = io_out_ready & N184;
assign io_in_2_ready = io_out_ready & N181;
assign io_in_3_ready = io_out_ready & N178;
assign N162 = T88 | reset;
assign N163 = ~N162;
assign N167 = T93 | reset;
assign N168 = T88 | N167;
assign N169 = ~N168;
assign N172 = ~reset;
assign N173 = T88 & N172;
assign N174 = T93 & N172;
assign N175 = ~T93;
assign N176 = N172 & N175;
assign N177 = T88 & N176;
endmodule |
Subsets and Splits