module
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module RTC
(
clk,
reset,
io_aw_ready,
io_aw_valid,
io_aw_bits_addr,
io_aw_bits_len,
io_aw_bits_size,
io_aw_bits_burst,
io_aw_bits_lock,
io_aw_bits_cache,
io_aw_bits_prot,
io_aw_bits_qos,
io_aw_bits_region,
io_aw_bits_id,
io_aw_bits_user,
io_w_ready,
io_w_valid,
io_w_bits_data,
io_w_bits_last,
io_w_bits_strb,
io_w_bits_user,
io_b_ready,
io_b_valid,
io_b_bits_resp,
io_b_bits_id,
io_b_bits_user,
io_ar_ready,
io_ar_valid,
io_r_ready,
io_r_valid,
io_r_bits_resp,
io_r_bits_data,
io_r_bits_last,
io_r_bits_id,
io_r_bits_user
);
output [31:0] io_aw_bits_addr;
output [7:0] io_aw_bits_len;
output [2:0] io_aw_bits_size;
output [1:0] io_aw_bits_burst;
output [3:0] io_aw_bits_cache;
output [2:0] io_aw_bits_prot;
output [3:0] io_aw_bits_qos;
output [3:0] io_aw_bits_region;
output [5:0] io_aw_bits_id;
output [63:0] io_w_bits_data;
output [7:0] io_w_bits_strb;
input [1:0] io_b_bits_resp;
input [5:0] io_b_bits_id;
input [1:0] io_r_bits_resp;
input [63:0] io_r_bits_data;
input [5:0] io_r_bits_id;
input clk;
input reset;
input io_aw_ready;
input io_w_ready;
input io_b_valid;
input io_b_bits_user;
input io_ar_ready;
input io_r_valid;
input io_r_bits_last;
input io_r_bits_user;
output io_aw_valid;
output io_aw_bits_lock;
output io_aw_bits_user;
output io_w_valid;
output io_w_bits_last;
output io_w_bits_user;
output io_b_ready;
output io_ar_valid;
output io_r_ready;
wire [31:0] io_aw_bits_addr;
wire [7:0] io_aw_bits_len,io_w_bits_strb;
wire [2:0] io_aw_bits_size,io_aw_bits_prot;
wire [1:0] io_aw_bits_burst;
wire [3:0] io_aw_bits_cache,io_aw_bits_qos,io_aw_bits_region;
wire [5:0] io_aw_bits_id;
wire io_aw_bits_lock,io_aw_bits_user,io_w_bits_last,io_w_bits_user,io_b_ready,
io_ar_valid,io_r_ready,N0,T43,T42,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,
N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,
N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,
N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,
N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,
N96,N97,N98,N99,N100,N101,N102,N103,N104;
wire [6:0] T12;
wire [63:0] T24;
reg [6:0] R10;
reg [63:0] io_w_bits_data;
reg io_w_valid,io_aw_valid;
assign io_aw_bits_size[0] = 1'b1;
assign io_aw_bits_size[1] = 1'b1;
assign io_aw_bits_burst[0] = 1'b1;
assign io_w_bits_last = 1'b1;
assign io_w_bits_strb[0] = 1'b1;
assign io_w_bits_strb[1] = 1'b1;
assign io_w_bits_strb[2] = 1'b1;
assign io_w_bits_strb[3] = 1'b1;
assign io_w_bits_strb[4] = 1'b1;
assign io_w_bits_strb[5] = 1'b1;
assign io_w_bits_strb[6] = 1'b1;
assign io_w_bits_strb[7] = 1'b1;
assign io_b_ready = 1'b1;
assign io_aw_bits_addr[31] = 1'b0;
assign io_aw_bits_len[0] = 1'b0;
assign io_aw_bits_len[1] = 1'b0;
assign io_aw_bits_len[2] = 1'b0;
assign io_aw_bits_len[3] = 1'b0;
assign io_aw_bits_len[4] = 1'b0;
assign io_aw_bits_len[5] = 1'b0;
assign io_aw_bits_len[6] = 1'b0;
assign io_aw_bits_len[7] = 1'b0;
assign io_aw_bits_size[2] = 1'b0;
assign io_aw_bits_burst[1] = 1'b0;
assign io_aw_bits_lock = 1'b0;
assign io_aw_bits_cache[0] = 1'b0;
assign io_aw_bits_cache[1] = 1'b0;
assign io_aw_bits_cache[2] = 1'b0;
assign io_aw_bits_cache[3] = 1'b0;
assign io_aw_bits_prot[0] = 1'b0;
assign io_aw_bits_prot[1] = 1'b0;
assign io_aw_bits_prot[2] = 1'b0;
assign io_aw_bits_qos[0] = 1'b0;
assign io_aw_bits_qos[1] = 1'b0;
assign io_aw_bits_qos[2] = 1'b0;
assign io_aw_bits_qos[3] = 1'b0;
assign io_aw_bits_region[0] = 1'b0;
assign io_aw_bits_region[1] = 1'b0;
assign io_aw_bits_region[2] = 1'b0;
assign io_aw_bits_region[3] = 1'b0;
assign io_aw_bits_id[0] = 1'b0;
assign io_aw_bits_id[1] = 1'b0;
assign io_aw_bits_id[2] = 1'b0;
assign io_aw_bits_id[3] = 1'b0;
assign io_aw_bits_id[4] = 1'b0;
assign io_aw_bits_id[5] = 1'b0;
assign io_aw_bits_user = 1'b0;
assign io_w_bits_user = 1'b0;
assign io_ar_valid = 1'b0;
assign io_r_ready = 1'b0;
assign io_aw_bits_addr[30] = 1'b1;
assign io_aw_bits_addr[29] = 1'b0;
assign io_aw_bits_addr[28] = 1'b0;
assign io_aw_bits_addr[27] = 1'b0;
assign io_aw_bits_addr[26] = 1'b0;
assign io_aw_bits_addr[25] = 1'b0;
assign io_aw_bits_addr[24] = 1'b0;
assign io_aw_bits_addr[23] = 1'b0;
assign io_aw_bits_addr[22] = 1'b0;
assign io_aw_bits_addr[21] = 1'b0;
assign io_aw_bits_addr[20] = 1'b0;
assign io_aw_bits_addr[19] = 1'b0;
assign io_aw_bits_addr[18] = 1'b0;
assign io_aw_bits_addr[17] = 1'b0;
assign io_aw_bits_addr[16] = 1'b0;
assign io_aw_bits_addr[15] = 1'b1;
assign io_aw_bits_addr[14] = 1'b0;
assign io_aw_bits_addr[13] = 1'b1;
assign io_aw_bits_addr[12] = 1'b1;
assign io_aw_bits_addr[11] = 1'b1;
assign io_aw_bits_addr[10] = 1'b0;
assign io_aw_bits_addr[9] = 1'b0;
assign io_aw_bits_addr[8] = 1'b0;
assign io_aw_bits_addr[7] = 1'b0;
assign io_aw_bits_addr[6] = 1'b0;
assign io_aw_bits_addr[5] = 1'b0;
assign io_aw_bits_addr[4] = 1'b0;
assign io_aw_bits_addr[3] = 1'b1;
assign io_aw_bits_addr[2] = 1'b0;
assign io_aw_bits_addr[1] = 1'b0;
assign io_aw_bits_addr[0] = 1'b0;
always @(posedge clk) begin
if(1'b1) begin
R10[6] <= N9;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[5] <= N8;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[4] <= N7;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[3] <= N6;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[2] <= N5;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[1] <= N4;
end
end
always @(posedge clk) begin
if(1'b1) begin
R10[0] <= N3;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[63] <= N76;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[62] <= N75;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[61] <= N74;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[60] <= N73;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[59] <= N72;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[58] <= N71;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[57] <= N70;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[56] <= N69;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[55] <= N68;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[54] <= N67;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[53] <= N66;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[52] <= N65;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[51] <= N64;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[50] <= N63;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[49] <= N62;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[48] <= N61;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[47] <= N60;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[46] <= N59;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[45] <= N58;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[44] <= N57;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[43] <= N56;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[42] <= N55;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[41] <= N54;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[40] <= N53;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[39] <= N52;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[38] <= N51;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[37] <= N50;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[36] <= N49;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[35] <= N48;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[34] <= N47;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[33] <= N46;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[32] <= N45;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[31] <= N44;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[30] <= N43;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[29] <= N42;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[28] <= N41;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[27] <= N40;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[26] <= N39;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[25] <= N38;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[24] <= N37;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[23] <= N36;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[22] <= N35;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[21] <= N34;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[20] <= N33;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[19] <= N32;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[18] <= N31;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[17] <= N30;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[16] <= N29;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[15] <= N28;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[14] <= N27;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[13] <= N26;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[12] <= N25;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[11] <= N24;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[10] <= N23;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[9] <= N22;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[8] <= N21;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[7] <= N20;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[6] <= N19;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[5] <= N18;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[4] <= N17;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[3] <= N16;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[2] <= N15;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[1] <= N14;
end
end
always @(posedge clk) begin
if(N12) begin
io_w_bits_data[0] <= N13;
end
end
always @(posedge clk) begin
if(N77) begin
io_w_valid <= N78;
end
end
always @(posedge clk) begin
if(N83) begin
io_aw_valid <= N84;
end
end
assign N94 = ~R10[6];
assign N95 = ~R10[5];
assign N96 = ~R10[1];
assign N97 = ~R10[0];
assign N98 = N95 | N94;
assign N99 = R10[4] | N98;
assign N100 = R10[3] | N99;
assign N101 = R10[2] | N100;
assign N102 = N96 | N101;
assign N103 = N97 | N102;
assign N104 = ~N103;
assign T12 = R10 + 1'b1;
assign T24 = io_w_bits_data + 1'b1;
assign { N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N78)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N2)? T12 : 1'b0;
assign N0 = reset;
assign N12 = (N0)? 1'b1 :
(N86)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign { N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N86)? T24 : 1'b0;
assign N77 = (N0)? 1'b1 :
(N78)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N83 = (N0)? 1'b1 :
(N87)? 1'b1 :
(N90)? 1'b1 :
(N93)? 1'b1 :
(N82)? 1'b0 : 1'b0;
assign N84 = (N0)? 1'b0 :
(N87)? 1'b0 :
(N90)? 1'b0 :
(N93)? 1'b1 : 1'b0;
assign T42 = io_aw_ready & io_aw_valid;
assign T43 = io_w_ready & io_w_valid;
assign N1 = N104 | reset;
assign N2 = ~N1;
assign N10 = N104 | reset;
assign N11 = ~N10;
assign N79 = T43 | reset;
assign N80 = T42 | N79;
assign N81 = N104 | N80;
assign N82 = ~N81;
assign N85 = ~reset;
assign N78 = N104 & N85;
assign N86 = N104 & N85;
assign N87 = T43 & N85;
assign N88 = ~T43;
assign N89 = N85 & N88;
assign N90 = T42 & N89;
assign N91 = ~T42;
assign N92 = N89 & N91;
assign N93 = N104 & N92;
endmodule |
module LockingRRArbiter_8
(
clk,
reset,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_header_src,
io_in_4_bits_header_dst,
io_in_4_bits_payload_addr_beat,
io_in_4_bits_payload_client_xact_id,
io_in_4_bits_payload_manager_xact_id,
io_in_4_bits_payload_is_builtin_type,
io_in_4_bits_payload_g_type,
io_in_4_bits_payload_data,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_header_src,
io_in_3_bits_header_dst,
io_in_3_bits_payload_addr_beat,
io_in_3_bits_payload_client_xact_id,
io_in_3_bits_payload_manager_xact_id,
io_in_3_bits_payload_is_builtin_type,
io_in_3_bits_payload_g_type,
io_in_3_bits_payload_data,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_header_src,
io_in_2_bits_header_dst,
io_in_2_bits_payload_addr_beat,
io_in_2_bits_payload_client_xact_id,
io_in_2_bits_payload_manager_xact_id,
io_in_2_bits_payload_is_builtin_type,
io_in_2_bits_payload_g_type,
io_in_2_bits_payload_data,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_header_src,
io_in_1_bits_header_dst,
io_in_1_bits_payload_addr_beat,
io_in_1_bits_payload_client_xact_id,
io_in_1_bits_payload_manager_xact_id,
io_in_1_bits_payload_is_builtin_type,
io_in_1_bits_payload_g_type,
io_in_1_bits_payload_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_header_src,
io_in_0_bits_header_dst,
io_in_0_bits_payload_addr_beat,
io_in_0_bits_payload_client_xact_id,
io_in_0_bits_payload_manager_xact_id,
io_in_0_bits_payload_is_builtin_type,
io_in_0_bits_payload_g_type,
io_in_0_bits_payload_data,
io_out_ready,
io_out_valid,
io_out_bits_header_src,
io_out_bits_header_dst,
io_out_bits_payload_addr_beat,
io_out_bits_payload_client_xact_id,
io_out_bits_payload_manager_xact_id,
io_out_bits_payload_is_builtin_type,
io_out_bits_payload_g_type,
io_out_bits_payload_data,
io_chosen
);
input [2:0] io_in_4_bits_header_src;
input [2:0] io_in_4_bits_header_dst;
input [1:0] io_in_4_bits_payload_addr_beat;
input [5:0] io_in_4_bits_payload_client_xact_id;
input [3:0] io_in_4_bits_payload_manager_xact_id;
input [3:0] io_in_4_bits_payload_g_type;
input [127:0] io_in_4_bits_payload_data;
input [2:0] io_in_3_bits_header_src;
input [2:0] io_in_3_bits_header_dst;
input [1:0] io_in_3_bits_payload_addr_beat;
input [5:0] io_in_3_bits_payload_client_xact_id;
input [3:0] io_in_3_bits_payload_manager_xact_id;
input [3:0] io_in_3_bits_payload_g_type;
input [127:0] io_in_3_bits_payload_data;
input [2:0] io_in_2_bits_header_src;
input [2:0] io_in_2_bits_header_dst;
input [1:0] io_in_2_bits_payload_addr_beat;
input [5:0] io_in_2_bits_payload_client_xact_id;
input [3:0] io_in_2_bits_payload_manager_xact_id;
input [3:0] io_in_2_bits_payload_g_type;
input [127:0] io_in_2_bits_payload_data;
input [2:0] io_in_1_bits_header_src;
input [2:0] io_in_1_bits_header_dst;
input [1:0] io_in_1_bits_payload_addr_beat;
input [5:0] io_in_1_bits_payload_client_xact_id;
input [3:0] io_in_1_bits_payload_manager_xact_id;
input [3:0] io_in_1_bits_payload_g_type;
input [127:0] io_in_1_bits_payload_data;
input [2:0] io_in_0_bits_header_src;
input [2:0] io_in_0_bits_header_dst;
input [1:0] io_in_0_bits_payload_addr_beat;
input [5:0] io_in_0_bits_payload_client_xact_id;
input [3:0] io_in_0_bits_payload_manager_xact_id;
input [3:0] io_in_0_bits_payload_g_type;
input [127:0] io_in_0_bits_payload_data;
output [2:0] io_out_bits_header_src;
output [2:0] io_out_bits_header_dst;
output [1:0] io_out_bits_payload_addr_beat;
output [5:0] io_out_bits_payload_client_xact_id;
output [3:0] io_out_bits_payload_manager_xact_id;
output [3:0] io_out_bits_payload_g_type;
output [127:0] io_out_bits_payload_data;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_4_valid;
input io_in_4_bits_payload_is_builtin_type;
input io_in_3_valid;
input io_in_3_bits_payload_is_builtin_type;
input io_in_2_valid;
input io_in_2_bits_payload_is_builtin_type;
input io_in_1_valid;
input io_in_1_bits_payload_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_payload_is_builtin_type;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_payload_is_builtin_type;
wire [2:0] io_out_bits_header_src,io_out_bits_header_dst,io_chosen,choose,T1,T2,T3,T4,T5,
T6,T19,T20,T21,T95,T98,T96,T103,T106,T104;
wire [1:0] io_out_bits_payload_addr_beat,T40,T87,T90,T88;
wire [5:0] io_out_bits_payload_client_xact_id,T79,T82,T80;
wire [3:0] io_out_bits_payload_manager_xact_id,io_out_bits_payload_g_type,T55,T58,T56,T71,
T74,T72;
wire [127:0] io_out_bits_payload_data,T46,T50,T47;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,io_out_bits_payload_is_builtin_type,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
T16,N32,T14,N33,T12,N34,T8,N35,N36,N37,N38,N39,T9,T11,T13,T15,T17,T27,T26,N40,T25,
N41,T24,N42,T23,N43,T29,T28,T35,T30,N44,T31,T43,T38,T39,T44,N45,N46,N47,T63,T66,
T64,T111,T114,T112,T119,T120,T136,T121,T122,T125,T123,T124,T128,T126,T127,T131,
T129,T130,T134,T132,T133,T135,T139,T140,T147,T141,T142,T143,T144,T145,T146,T149,
T148,T152,T153,T161,T154,T155,T156,T157,T158,T159,T160,T163,T162,T164,T167,T168,
T177,T169,T170,T171,T172,T173,T174,T175,T176,T179,T178,T180,T181,T184,T185,T195,
T186,T187,T188,T189,T190,T191,T192,T193,T194,T197,T196,T198,T199,T200,N48,N49,N50,
N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,
N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,
N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,
N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118;
wire [2:1] T7,T22;
reg [2:0] last_grant,lockIdx;
reg locked;
reg [1:0] R41;
assign T13 = last_grant < { 1'b1, 1'b1 };
assign T39 = T40 == 1'b0;
assign T127 = last_grant < { 1'b1, 1'b1 };
assign T135 = last_grant < 1'b0;
assign T136 = last_grant < 1'b0;
assign T178 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N50) begin
last_grant[2] <= N53;
end
end
always @(posedge clk) begin
if(N50) begin
last_grant[1] <= N52;
end
end
always @(posedge clk) begin
if(N50) begin
last_grant[0] <= N51;
end
end
always @(posedge clk) begin
if(N56) begin
lockIdx[2] <= N59;
end
end
always @(posedge clk) begin
if(N56) begin
lockIdx[1] <= N58;
end
end
always @(posedge clk) begin
if(N56) begin
lockIdx[0] <= N57;
end
end
always @(posedge clk) begin
if(N63) begin
locked <= N64;
end
end
always @(posedge clk) begin
if(N67) begin
R41[1] <= N69;
end
end
always @(posedge clk) begin
if(N67) begin
R41[0] <= N68;
end
end
assign N78 = ~lockIdx[2];
assign N79 = lockIdx[1] | N78;
assign N80 = lockIdx[0] | N79;
assign N81 = ~N80;
assign N82 = lockIdx[1] | lockIdx[2];
assign N83 = lockIdx[0] | N82;
assign N84 = ~N83;
assign N85 = ~lockIdx[0];
assign N86 = lockIdx[1] | lockIdx[2];
assign N87 = N85 | N86;
assign N88 = ~N87;
assign N89 = ~io_out_bits_payload_g_type[2];
assign N90 = ~io_out_bits_payload_g_type[0];
assign N91 = N89 | io_out_bits_payload_g_type[3];
assign N92 = io_out_bits_payload_g_type[1] | N91;
assign N93 = N90 | N92;
assign N94 = ~N93;
assign N95 = ~lockIdx[1];
assign N96 = N95 | lockIdx[2];
assign N97 = lockIdx[0] | N96;
assign N98 = ~N97;
assign N99 = io_out_bits_payload_g_type[2] | io_out_bits_payload_g_type[3];
assign N100 = io_out_bits_payload_g_type[1] | N99;
assign N101 = io_out_bits_payload_g_type[0] | N100;
assign N102 = ~N101;
assign N103 = io_out_bits_payload_g_type[2] | io_out_bits_payload_g_type[3];
assign N104 = io_out_bits_payload_g_type[1] | N103;
assign N105 = N90 | N104;
assign N106 = ~N105;
assign N107 = N95 | lockIdx[2];
assign N108 = N85 | N107;
assign N109 = ~N108;
assign T40 = R41 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N31;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T16;
assign N3 = N32;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T14;
assign N5 = N33;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T12;
assign N7 = N34;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T8;
assign N9 = N35;
assign T4 = (N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? T5 : 1'b0;
assign N10 = io_in_0_valid;
assign N11 = N36;
assign T5 = (N12)? { 1'b0, 1'b0, 1'b1 } :
(N13)? T6 : 1'b0;
assign N12 = io_in_1_valid;
assign N13 = N37;
assign T6 = (N14)? { 1'b0, 1'b1, 1'b0 } :
(N15)? { T7, T7[1:1] } : 1'b0;
assign N14 = io_in_2_valid;
assign N15 = N38;
assign T19 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T20 : 1'b0;
assign N16 = T26;
assign N17 = N40;
assign T20 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T21 : 1'b0;
assign N18 = T25;
assign N19 = N41;
assign T21 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? { T22, T22[1:1] } : 1'b0;
assign N20 = T24;
assign N21 = N42;
assign T30 = (N22)? N94 :
(N23)? T31 : 1'b0;
assign N22 = io_out_bits_payload_is_builtin_type;
assign N23 = N44;
assign io_out_bits_payload_data = (N24)? io_in_4_bits_payload_data :
(N25)? T46 : 1'b0;
assign N24 = io_chosen[2];
assign N25 = N45;
assign T46 = (N26)? T50 :
(N27)? T47 : 1'b0;
assign N26 = io_chosen[1];
assign N27 = N46;
assign T47 = (N28)? io_in_1_bits_payload_data :
(N29)? io_in_0_bits_payload_data : 1'b0;
assign N28 = io_chosen[0];
assign N29 = N47;
assign T50 = (N28)? io_in_3_bits_payload_data :
(N29)? io_in_2_bits_payload_data : 1'b0;
assign io_out_bits_payload_g_type = (N24)? io_in_4_bits_payload_g_type :
(N25)? T55 : 1'b0;
assign T55 = (N26)? T58 :
(N27)? T56 : 1'b0;
assign T56 = (N28)? io_in_1_bits_payload_g_type :
(N29)? io_in_0_bits_payload_g_type : 1'b0;
assign T58 = (N28)? io_in_3_bits_payload_g_type :
(N29)? io_in_2_bits_payload_g_type : 1'b0;
assign io_out_bits_payload_is_builtin_type = (N24)? io_in_4_bits_payload_is_builtin_type :
(N25)? T63 : 1'b0;
assign T63 = (N26)? T66 :
(N27)? T64 : 1'b0;
assign T64 = (N28)? io_in_1_bits_payload_is_builtin_type :
(N29)? io_in_0_bits_payload_is_builtin_type : 1'b0;
assign T66 = (N28)? io_in_3_bits_payload_is_builtin_type :
(N29)? io_in_2_bits_payload_is_builtin_type : 1'b0;
assign io_out_bits_payload_manager_xact_id = (N24)? io_in_4_bits_payload_manager_xact_id :
(N25)? T71 : 1'b0;
assign T71 = (N26)? T74 :
(N27)? T72 : 1'b0;
assign T72 = (N28)? io_in_1_bits_payload_manager_xact_id :
(N29)? io_in_0_bits_payload_manager_xact_id : 1'b0;
assign T74 = (N28)? io_in_3_bits_payload_manager_xact_id :
(N29)? io_in_2_bits_payload_manager_xact_id : 1'b0;
assign io_out_bits_payload_client_xact_id = (N24)? io_in_4_bits_payload_client_xact_id :
(N25)? T79 : 1'b0;
assign T79 = (N26)? T82 :
(N27)? T80 : 1'b0;
assign T80 = (N28)? io_in_1_bits_payload_client_xact_id :
(N29)? io_in_0_bits_payload_client_xact_id : 1'b0;
assign T82 = (N28)? io_in_3_bits_payload_client_xact_id :
(N29)? io_in_2_bits_payload_client_xact_id : 1'b0;
assign io_out_bits_payload_addr_beat = (N24)? io_in_4_bits_payload_addr_beat :
(N25)? T87 : 1'b0;
assign T87 = (N26)? T90 :
(N27)? T88 : 1'b0;
assign T88 = (N28)? io_in_1_bits_payload_addr_beat :
(N29)? io_in_0_bits_payload_addr_beat : 1'b0;
assign T90 = (N28)? io_in_3_bits_payload_addr_beat :
(N29)? io_in_2_bits_payload_addr_beat : 1'b0;
assign io_out_bits_header_dst = (N24)? io_in_4_bits_header_dst :
(N25)? T95 : 1'b0;
assign T95 = (N26)? T98 :
(N27)? T96 : 1'b0;
assign T96 = (N28)? io_in_1_bits_header_dst :
(N29)? io_in_0_bits_header_dst : 1'b0;
assign T98 = (N28)? io_in_3_bits_header_dst :
(N29)? io_in_2_bits_header_dst : 1'b0;
assign io_out_bits_header_src = (N24)? io_in_4_bits_header_src :
(N25)? T103 : 1'b0;
assign T103 = (N26)? T106 :
(N27)? T104 : 1'b0;
assign T104 = (N28)? io_in_1_bits_header_src :
(N29)? io_in_0_bits_header_src : 1'b0;
assign T106 = (N28)? io_in_3_bits_header_src :
(N29)? io_in_2_bits_header_src : 1'b0;
assign io_out_valid = (N24)? io_in_4_valid :
(N25)? T111 : 1'b0;
assign T111 = (N26)? T114 :
(N27)? T112 : 1'b0;
assign T112 = (N28)? io_in_1_valid :
(N29)? io_in_0_valid : 1'b0;
assign T114 = (N28)? io_in_3_valid :
(N29)? io_in_2_valid : 1'b0;
assign T119 = (N0)? N84 :
(N1)? T120 : 1'b0;
assign T139 = (N0)? N88 :
(N1)? T140 : 1'b0;
assign T152 = (N0)? N98 :
(N1)? T153 : 1'b0;
assign T167 = (N0)? N109 :
(N1)? T168 : 1'b0;
assign T184 = (N0)? N81 :
(N1)? T185 : 1'b0;
assign N50 = (N30)? 1'b1 :
(N71)? 1'b1 :
(N49)? 1'b0 : 1'b0;
assign N30 = reset;
assign { N53, N52, N51 } = (N30)? { 1'b0, 1'b0, 1'b0 } :
(N71)? io_chosen : 1'b0;
assign N56 = (N30)? 1'b1 :
(N72)? 1'b1 :
(N55)? 1'b0 : 1'b0;
assign { N59, N58, N57 } = (N30)? { 1'b1, 1'b0, 1'b0 } :
(N72)? T19 : 1'b0;
assign N63 = (N30)? 1'b1 :
(N73)? 1'b1 :
(N76)? 1'b1 :
(N62)? 1'b0 : 1'b0;
assign N64 = (N30)? 1'b0 :
(N73)? 1'b0 :
(N76)? T38 : 1'b0;
assign N67 = (N30)? 1'b1 :
(N77)? 1'b1 :
(N66)? 1'b0 : 1'b0;
assign { N69, N68 } = (N30)? { 1'b0, 1'b0 } :
(N77)? T40 : 1'b0;
assign N31 = ~locked;
assign N32 = ~T16;
assign N33 = ~T14;
assign N34 = ~T12;
assign N35 = ~T8;
assign N36 = ~io_in_0_valid;
assign N37 = ~io_in_1_valid;
assign N38 = ~io_in_2_valid;
assign N39 = ~io_in_3_valid;
assign T7[1] = io_in_3_valid;
assign T7[2] = N39;
assign T8 = io_in_4_valid & T9;
assign T9 = ~last_grant[2];
assign T11 = io_out_ready & io_out_valid;
assign T12 = io_in_3_valid & T13;
assign T14 = io_in_2_valid & T15;
assign T15 = ~N110;
assign N110 = last_grant[2] | last_grant[1];
assign T16 = io_in_1_valid & T17;
assign T17 = ~N112;
assign N112 = N111 | last_grant[0];
assign N111 = last_grant[2] | last_grant[1];
assign N40 = ~T26;
assign N41 = ~T25;
assign N42 = ~T24;
assign N43 = ~T23;
assign T22[1] = T23;
assign T22[2] = N43;
assign T23 = io_in_3_ready & io_in_3_valid;
assign T24 = io_in_2_ready & io_in_2_valid;
assign T25 = io_in_1_ready & io_in_1_valid;
assign T26 = io_in_0_ready & io_in_0_valid;
assign T27 = T29 & T28;
assign T28 = ~locked;
assign T29 = T35 & T30;
assign N44 = ~io_out_bits_payload_is_builtin_type;
assign T31 = N102 | N106;
assign T35 = io_out_valid & io_out_ready;
assign T38 = ~T39;
assign T43 = T35 & T44;
assign T44 = ~T30;
assign N45 = ~io_chosen[2];
assign N46 = ~io_chosen[1];
assign N47 = ~io_chosen[0];
assign io_in_0_ready = T119 & io_out_ready;
assign T120 = T136 | T121;
assign T121 = ~T122;
assign T122 = T125 | T123;
assign T123 = io_in_4_valid & T124;
assign T124 = ~last_grant[2];
assign T125 = T128 | T126;
assign T126 = io_in_3_valid & T127;
assign T128 = T131 | T129;
assign T129 = io_in_2_valid & T130;
assign T130 = ~N113;
assign N113 = last_grant[2] | last_grant[1];
assign T131 = T134 | T132;
assign T132 = io_in_1_valid & T133;
assign T133 = ~N115;
assign N115 = N114 | last_grant[0];
assign N114 = last_grant[2] | last_grant[1];
assign T134 = io_in_0_valid & T135;
assign io_in_1_ready = T139 & io_out_ready;
assign T140 = T147 | T141;
assign T141 = ~T142;
assign T142 = T143 | io_in_0_valid;
assign T143 = T144 | T123;
assign T144 = T145 | T126;
assign T145 = T146 | T129;
assign T146 = T134 | T132;
assign T147 = T149 & T148;
assign T148 = ~N117;
assign N117 = N116 | last_grant[0];
assign N116 = last_grant[2] | last_grant[1];
assign T149 = ~T134;
assign io_in_2_ready = T152 & io_out_ready;
assign T153 = T161 | T154;
assign T154 = ~T155;
assign T155 = T156 | io_in_1_valid;
assign T156 = T157 | io_in_0_valid;
assign T157 = T158 | T123;
assign T158 = T159 | T126;
assign T159 = T160 | T129;
assign T160 = T134 | T132;
assign T161 = T163 & T162;
assign T162 = ~N118;
assign N118 = last_grant[2] | last_grant[1];
assign T163 = ~T164;
assign T164 = T134 | T132;
assign io_in_3_ready = T167 & io_out_ready;
assign T168 = T177 | T169;
assign T169 = ~T170;
assign T170 = T171 | io_in_2_valid;
assign T171 = T172 | io_in_1_valid;
assign T172 = T173 | io_in_0_valid;
assign T173 = T174 | T123;
assign T174 = T175 | T126;
assign T175 = T176 | T129;
assign T176 = T134 | T132;
assign T177 = T179 & T178;
assign T179 = ~T180;
assign T180 = T181 | T129;
assign T181 = T134 | T132;
assign io_in_4_ready = T184 & io_out_ready;
assign T185 = T195 | T186;
assign T186 = ~T187;
assign T187 = T188 | io_in_3_valid;
assign T188 = T189 | io_in_2_valid;
assign T189 = T190 | io_in_1_valid;
assign T190 = T191 | io_in_0_valid;
assign T191 = T192 | T123;
assign T192 = T193 | T126;
assign T193 = T194 | T129;
assign T194 = T134 | T132;
assign T195 = T197 & T196;
assign T196 = ~last_grant[2];
assign T197 = ~T198;
assign T198 = T199 | T126;
assign T199 = T200 | T129;
assign T200 = T134 | T132;
assign N48 = T11 | reset;
assign N49 = ~N48;
assign N54 = T27 | reset;
assign N55 = ~N54;
assign N60 = T43 | reset;
assign N61 = T29 | N60;
assign N62 = ~N61;
assign N65 = T29 | reset;
assign N66 = ~N65;
assign N70 = ~reset;
assign N71 = T11 & N70;
assign N72 = T27 & N70;
assign N73 = T43 & N70;
assign N74 = ~T43;
assign N75 = N70 & N74;
assign N76 = T29 & N75;
assign N77 = T29 & N70;
endmodule |
module LockingArbiter_0
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_beat,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_voluntary,
io_in_1_bits_r_type,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_beat,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_voluntary,
io_in_0_bits_r_type,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_voluntary,
io_out_bits_r_type,
io_out_bits_data,
io_chosen
);
input [1:0] io_in_1_bits_addr_beat;
input [25:0] io_in_1_bits_addr_block;
input [5:0] io_in_1_bits_client_xact_id;
input [2:0] io_in_1_bits_r_type;
input [127:0] io_in_1_bits_data;
input [1:0] io_in_0_bits_addr_beat;
input [25:0] io_in_0_bits_addr_block;
input [5:0] io_in_0_bits_client_xact_id;
input [2:0] io_in_0_bits_r_type;
input [127:0] io_in_0_bits_data;
output [1:0] io_out_bits_addr_beat;
output [25:0] io_out_bits_addr_block;
output [5:0] io_out_bits_client_xact_id;
output [2:0] io_out_bits_r_type;
output [127:0] io_out_bits_data;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_voluntary;
input io_in_0_valid;
input io_in_0_bits_voluntary;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_voluntary;
output io_chosen;
wire [1:0] io_out_bits_addr_beat,T17;
wire [25:0] io_out_bits_addr_block;
wire [5:0] io_out_bits_client_xact_id;
wire [2:0] io_out_bits_r_type;
wire [127:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_voluntary,io_chosen,N0,N1,
N2,N3,N4,N5,T4,T3,T6,T5,T12,T7,T9,T20,T15,T16,T21,N6,T31,T34,T35,N7,N8,N9,N10,
N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41;
reg lockIdx,locked;
reg [1:0] R18;
assign T16 = T17 == 1'b0;
always @(posedge clk) begin
if(N9) begin
lockIdx <= N10;
end
end
always @(posedge clk) begin
if(N14) begin
locked <= N15;
end
end
always @(posedge clk) begin
if(N18) begin
R18[1] <= N20;
end
end
always @(posedge clk) begin
if(N18) begin
R18[0] <= N19;
end
end
assign N28 = ~T3;
assign N29 = ~lockIdx;
assign N30 = ~io_out_bits_r_type[1];
assign N31 = N30 | io_out_bits_r_type[2];
assign N32 = io_out_bits_r_type[0] | N31;
assign N33 = ~N32;
assign N34 = io_out_bits_r_type[1] | io_out_bits_r_type[2];
assign N35 = io_out_bits_r_type[0] | N34;
assign N36 = ~N35;
assign N37 = ~io_out_bits_r_type[0];
assign N38 = io_out_bits_r_type[1] | io_out_bits_r_type[2];
assign N39 = N37 | N38;
assign N40 = ~N39;
assign N41 = ~io_in_0_valid;
assign T17 = R18 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? N41 : 1'b0;
assign N0 = locked;
assign N1 = N5;
assign io_out_bits_data = (N2)? io_in_1_bits_data :
(N3)? io_in_0_bits_data : 1'b0;
assign N2 = io_chosen;
assign N3 = N6;
assign io_out_bits_r_type = (N2)? io_in_1_bits_r_type :
(N3)? io_in_0_bits_r_type : 1'b0;
assign io_out_bits_voluntary = (N2)? io_in_1_bits_voluntary :
(N3)? io_in_0_bits_voluntary : 1'b0;
assign io_out_bits_client_xact_id = (N2)? io_in_1_bits_client_xact_id :
(N3)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N2)? io_in_1_bits_addr_block :
(N3)? io_in_0_bits_addr_block : 1'b0;
assign io_out_bits_addr_beat = (N2)? io_in_1_bits_addr_beat :
(N3)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_valid = (N2)? io_in_1_valid :
(N3)? io_in_0_valid : 1'b0;
assign T31 = (N0)? N29 :
(N1)? 1'b1 : 1'b0;
assign T34 = (N0)? lockIdx :
(N1)? T35 : 1'b0;
assign N9 = (N4)? 1'b1 :
(N22)? 1'b1 :
(N8)? 1'b0 : 1'b0;
assign N4 = reset;
assign N10 = (N4)? 1'b1 :
(N22)? N28 : 1'b0;
assign N14 = (N4)? 1'b1 :
(N23)? 1'b1 :
(N26)? 1'b1 :
(N13)? 1'b0 : 1'b0;
assign N15 = (N4)? 1'b0 :
(N23)? 1'b0 :
(N26)? T15 : 1'b0;
assign N18 = (N4)? 1'b1 :
(N27)? 1'b1 :
(N17)? 1'b0 : 1'b0;
assign { N20, N19 } = (N4)? { 1'b0, 1'b0 } :
(N27)? T17 : 1'b0;
assign N5 = ~locked;
assign T3 = io_in_0_ready & io_in_0_valid;
assign T4 = T6 & T5;
assign T5 = ~locked;
assign T6 = T12 & T7;
assign T7 = T9 | N33;
assign T9 = N36 | N40;
assign T12 = io_out_valid & io_out_ready;
assign T15 = ~T16;
assign T20 = T12 & T21;
assign T21 = ~T7;
assign N6 = ~io_chosen;
assign io_in_0_ready = T31 & io_out_ready;
assign io_in_1_ready = T34 & io_out_ready;
assign T35 = ~io_in_0_valid;
assign N7 = T4 | reset;
assign N8 = ~N7;
assign N11 = T20 | reset;
assign N12 = T6 | N11;
assign N13 = ~N12;
assign N16 = T6 | reset;
assign N17 = ~N16;
assign N21 = ~reset;
assign N22 = T4 & N21;
assign N23 = T20 & N21;
assign N24 = ~T20;
assign N25 = N21 & N24;
assign N26 = T6 & N25;
assign N27 = T6 & N21;
endmodule |
module Arbiter_4
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_beat,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_voluntary,
io_in_1_bits_r_type,
io_in_1_bits_data,
io_in_1_bits_way_en,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_beat,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_voluntary,
io_in_0_bits_r_type,
io_in_0_bits_data,
io_in_0_bits_way_en,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_voluntary,
io_out_bits_r_type,
io_out_bits_data,
io_out_bits_way_en,
io_chosen
);
input [1:0] io_in_1_bits_addr_beat;
input [25:0] io_in_1_bits_addr_block;
input [5:0] io_in_1_bits_client_xact_id;
input [2:0] io_in_1_bits_r_type;
input [127:0] io_in_1_bits_data;
input [3:0] io_in_1_bits_way_en;
input [1:0] io_in_0_bits_addr_beat;
input [25:0] io_in_0_bits_addr_block;
input [5:0] io_in_0_bits_client_xact_id;
input [2:0] io_in_0_bits_r_type;
input [127:0] io_in_0_bits_data;
input [3:0] io_in_0_bits_way_en;
output [1:0] io_out_bits_addr_beat;
output [25:0] io_out_bits_addr_block;
output [5:0] io_out_bits_client_xact_id;
output [2:0] io_out_bits_r_type;
output [127:0] io_out_bits_data;
output [3:0] io_out_bits_way_en;
input io_in_1_valid;
input io_in_1_bits_voluntary;
input io_in_0_valid;
input io_in_0_bits_voluntary;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_voluntary;
output io_chosen;
wire [1:0] io_out_bits_addr_beat;
wire [25:0] io_out_bits_addr_block;
wire [5:0] io_out_bits_client_xact_id;
wire [2:0] io_out_bits_r_type;
wire [127:0] io_out_bits_data;
wire [3:0] io_out_bits_way_en;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_voluntary,io_chosen,N0,N1,
io_out_ready,T10;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en :
(N1)? io_in_0_bits_way_en : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_data = (N0)? io_in_1_bits_data :
(N1)? io_in_0_bits_data : 1'b0;
assign io_out_bits_r_type = (N0)? io_in_1_bits_r_type :
(N1)? io_in_0_bits_r_type : 1'b0;
assign io_out_bits_voluntary = (N0)? io_in_1_bits_voluntary :
(N1)? io_in_0_bits_voluntary : 1'b0;
assign io_out_bits_client_xact_id = (N0)? io_in_1_bits_client_xact_id :
(N1)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N0)? io_in_1_bits_addr_block :
(N1)? io_in_0_bits_addr_block : 1'b0;
assign io_out_bits_addr_beat = (N0)? io_in_1_bits_addr_beat :
(N1)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T10 & io_out_ready;
assign T10 = ~io_in_0_valid;
endmodule |
module SCRFile
(
clk,
reset,
io_smi_req_ready,
io_smi_req_valid,
io_smi_req_bits_rw,
io_smi_req_bits_addr,
io_smi_req_bits_data,
io_smi_resp_ready,
io_smi_resp_valid,
io_smi_resp_bits,
io_scr_rdata_63,
io_scr_rdata_62,
io_scr_rdata_61,
io_scr_rdata_60,
io_scr_rdata_59,
io_scr_rdata_58,
io_scr_rdata_57,
io_scr_rdata_56,
io_scr_rdata_55,
io_scr_rdata_54,
io_scr_rdata_53,
io_scr_rdata_52,
io_scr_rdata_51,
io_scr_rdata_50,
io_scr_rdata_49,
io_scr_rdata_48,
io_scr_rdata_47,
io_scr_rdata_46,
io_scr_rdata_45,
io_scr_rdata_44,
io_scr_rdata_43,
io_scr_rdata_42,
io_scr_rdata_41,
io_scr_rdata_40,
io_scr_rdata_39,
io_scr_rdata_38,
io_scr_rdata_37,
io_scr_rdata_36,
io_scr_rdata_35,
io_scr_rdata_34,
io_scr_rdata_33,
io_scr_rdata_32,
io_scr_rdata_31,
io_scr_rdata_30,
io_scr_rdata_29,
io_scr_rdata_28,
io_scr_rdata_27,
io_scr_rdata_26,
io_scr_rdata_25,
io_scr_rdata_24,
io_scr_rdata_23,
io_scr_rdata_22,
io_scr_rdata_21,
io_scr_rdata_20,
io_scr_rdata_19,
io_scr_rdata_18,
io_scr_rdata_17,
io_scr_rdata_16,
io_scr_rdata_15,
io_scr_rdata_14,
io_scr_rdata_13,
io_scr_rdata_12,
io_scr_rdata_11,
io_scr_rdata_10,
io_scr_rdata_9,
io_scr_rdata_8,
io_scr_rdata_7,
io_scr_rdata_6,
io_scr_rdata_5,
io_scr_rdata_4,
io_scr_rdata_3,
io_scr_rdata_2,
io_scr_rdata_1,
io_scr_rdata_0,
io_scr_wen,
io_scr_waddr,
io_scr_wdata
);
input [5:0] io_smi_req_bits_addr;
input [63:0] io_smi_req_bits_data;
output [63:0] io_smi_resp_bits;
input [63:0] io_scr_rdata_63;
input [63:0] io_scr_rdata_62;
input [63:0] io_scr_rdata_61;
input [63:0] io_scr_rdata_60;
input [63:0] io_scr_rdata_59;
input [63:0] io_scr_rdata_58;
input [63:0] io_scr_rdata_57;
input [63:0] io_scr_rdata_56;
input [63:0] io_scr_rdata_55;
input [63:0] io_scr_rdata_54;
input [63:0] io_scr_rdata_53;
input [63:0] io_scr_rdata_52;
input [63:0] io_scr_rdata_51;
input [63:0] io_scr_rdata_50;
input [63:0] io_scr_rdata_49;
input [63:0] io_scr_rdata_48;
input [63:0] io_scr_rdata_47;
input [63:0] io_scr_rdata_46;
input [63:0] io_scr_rdata_45;
input [63:0] io_scr_rdata_44;
input [63:0] io_scr_rdata_43;
input [63:0] io_scr_rdata_42;
input [63:0] io_scr_rdata_41;
input [63:0] io_scr_rdata_40;
input [63:0] io_scr_rdata_39;
input [63:0] io_scr_rdata_38;
input [63:0] io_scr_rdata_37;
input [63:0] io_scr_rdata_36;
input [63:0] io_scr_rdata_35;
input [63:0] io_scr_rdata_34;
input [63:0] io_scr_rdata_33;
input [63:0] io_scr_rdata_32;
input [63:0] io_scr_rdata_31;
input [63:0] io_scr_rdata_30;
input [63:0] io_scr_rdata_29;
input [63:0] io_scr_rdata_28;
input [63:0] io_scr_rdata_27;
input [63:0] io_scr_rdata_26;
input [63:0] io_scr_rdata_25;
input [63:0] io_scr_rdata_24;
input [63:0] io_scr_rdata_23;
input [63:0] io_scr_rdata_22;
input [63:0] io_scr_rdata_21;
input [63:0] io_scr_rdata_20;
input [63:0] io_scr_rdata_19;
input [63:0] io_scr_rdata_18;
input [63:0] io_scr_rdata_17;
input [63:0] io_scr_rdata_16;
input [63:0] io_scr_rdata_15;
input [63:0] io_scr_rdata_14;
input [63:0] io_scr_rdata_13;
input [63:0] io_scr_rdata_12;
input [63:0] io_scr_rdata_11;
input [63:0] io_scr_rdata_10;
input [63:0] io_scr_rdata_9;
input [63:0] io_scr_rdata_8;
input [63:0] io_scr_rdata_7;
input [63:0] io_scr_rdata_6;
input [63:0] io_scr_rdata_5;
input [63:0] io_scr_rdata_4;
input [63:0] io_scr_rdata_3;
input [63:0] io_scr_rdata_2;
input [63:0] io_scr_rdata_1;
input [63:0] io_scr_rdata_0;
output [5:0] io_scr_waddr;
output [63:0] io_scr_wdata;
input clk;
input reset;
input io_smi_req_valid;
input io_smi_req_bits_rw;
input io_smi_resp_ready;
output io_smi_req_ready;
output io_smi_resp_valid;
output io_scr_wen;
wire [63:0] io_smi_resp_bits,io_scr_wdata,T68,T3,T37,T4,T22,T5,T15,T6,T12,T7,T18,T16,T29,
T23,T26,T24,T32,T30,T52,T38,T45,T39,T42,T40,T48,T46,T59,T53,T56,T54,T62,T60,T99,
T69,T84,T70,T77,T71,T74,T72,T80,T78,T91,T85,T88,T86,T94,T92,T114,T100,T107,T101,
T104,T102,T110,T108,T121,T115,T118,T116,T124,T122;
wire [5:0] io_scr_waddr;
wire io_smi_req_ready,io_scr_wen,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,T1,N13,
N14,N15,N16,N17,N18,T11,T133,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
N32,N33,N34,N35,N36,N37,N38;
reg [5:0] T9;
reg io_smi_resp_valid;
assign io_scr_waddr[5] = io_smi_req_bits_addr[5];
assign io_scr_waddr[4] = io_smi_req_bits_addr[4];
assign io_scr_waddr[3] = io_smi_req_bits_addr[3];
assign io_scr_waddr[2] = io_smi_req_bits_addr[2];
assign io_scr_waddr[1] = io_smi_req_bits_addr[1];
assign io_scr_waddr[0] = io_smi_req_bits_addr[0];
assign io_scr_wdata[63] = io_smi_req_bits_data[63];
assign io_scr_wdata[62] = io_smi_req_bits_data[62];
assign io_scr_wdata[61] = io_smi_req_bits_data[61];
assign io_scr_wdata[60] = io_smi_req_bits_data[60];
assign io_scr_wdata[59] = io_smi_req_bits_data[59];
assign io_scr_wdata[58] = io_smi_req_bits_data[58];
assign io_scr_wdata[57] = io_smi_req_bits_data[57];
assign io_scr_wdata[56] = io_smi_req_bits_data[56];
assign io_scr_wdata[55] = io_smi_req_bits_data[55];
assign io_scr_wdata[54] = io_smi_req_bits_data[54];
assign io_scr_wdata[53] = io_smi_req_bits_data[53];
assign io_scr_wdata[52] = io_smi_req_bits_data[52];
assign io_scr_wdata[51] = io_smi_req_bits_data[51];
assign io_scr_wdata[50] = io_smi_req_bits_data[50];
assign io_scr_wdata[49] = io_smi_req_bits_data[49];
assign io_scr_wdata[48] = io_smi_req_bits_data[48];
assign io_scr_wdata[47] = io_smi_req_bits_data[47];
assign io_scr_wdata[46] = io_smi_req_bits_data[46];
assign io_scr_wdata[45] = io_smi_req_bits_data[45];
assign io_scr_wdata[44] = io_smi_req_bits_data[44];
assign io_scr_wdata[43] = io_smi_req_bits_data[43];
assign io_scr_wdata[42] = io_smi_req_bits_data[42];
assign io_scr_wdata[41] = io_smi_req_bits_data[41];
assign io_scr_wdata[40] = io_smi_req_bits_data[40];
assign io_scr_wdata[39] = io_smi_req_bits_data[39];
assign io_scr_wdata[38] = io_smi_req_bits_data[38];
assign io_scr_wdata[37] = io_smi_req_bits_data[37];
assign io_scr_wdata[36] = io_smi_req_bits_data[36];
assign io_scr_wdata[35] = io_smi_req_bits_data[35];
assign io_scr_wdata[34] = io_smi_req_bits_data[34];
assign io_scr_wdata[33] = io_smi_req_bits_data[33];
assign io_scr_wdata[32] = io_smi_req_bits_data[32];
assign io_scr_wdata[31] = io_smi_req_bits_data[31];
assign io_scr_wdata[30] = io_smi_req_bits_data[30];
assign io_scr_wdata[29] = io_smi_req_bits_data[29];
assign io_scr_wdata[28] = io_smi_req_bits_data[28];
assign io_scr_wdata[27] = io_smi_req_bits_data[27];
assign io_scr_wdata[26] = io_smi_req_bits_data[26];
assign io_scr_wdata[25] = io_smi_req_bits_data[25];
assign io_scr_wdata[24] = io_smi_req_bits_data[24];
assign io_scr_wdata[23] = io_smi_req_bits_data[23];
assign io_scr_wdata[22] = io_smi_req_bits_data[22];
assign io_scr_wdata[21] = io_smi_req_bits_data[21];
assign io_scr_wdata[20] = io_smi_req_bits_data[20];
assign io_scr_wdata[19] = io_smi_req_bits_data[19];
assign io_scr_wdata[18] = io_smi_req_bits_data[18];
assign io_scr_wdata[17] = io_smi_req_bits_data[17];
assign io_scr_wdata[16] = io_smi_req_bits_data[16];
assign io_scr_wdata[15] = io_smi_req_bits_data[15];
assign io_scr_wdata[14] = io_smi_req_bits_data[14];
assign io_scr_wdata[13] = io_smi_req_bits_data[13];
assign io_scr_wdata[12] = io_smi_req_bits_data[12];
assign io_scr_wdata[11] = io_smi_req_bits_data[11];
assign io_scr_wdata[10] = io_smi_req_bits_data[10];
assign io_scr_wdata[9] = io_smi_req_bits_data[9];
assign io_scr_wdata[8] = io_smi_req_bits_data[8];
assign io_scr_wdata[7] = io_smi_req_bits_data[7];
assign io_scr_wdata[6] = io_smi_req_bits_data[6];
assign io_scr_wdata[5] = io_smi_req_bits_data[5];
assign io_scr_wdata[4] = io_smi_req_bits_data[4];
assign io_scr_wdata[3] = io_smi_req_bits_data[3];
assign io_scr_wdata[2] = io_smi_req_bits_data[2];
assign io_scr_wdata[1] = io_smi_req_bits_data[1];
assign io_scr_wdata[0] = io_smi_req_bits_data[0];
always @(posedge clk) begin
if(N21) begin
T9[5] <= N27;
end
end
always @(posedge clk) begin
if(N21) begin
T9[4] <= N26;
end
end
always @(posedge clk) begin
if(N21) begin
T9[3] <= N25;
end
end
always @(posedge clk) begin
if(N21) begin
T9[2] <= N24;
end
end
always @(posedge clk) begin
if(N21) begin
T9[1] <= N23;
end
end
always @(posedge clk) begin
if(N21) begin
T9[0] <= N22;
end
end
always @(posedge clk) begin
if(N31) begin
io_smi_resp_valid <= N32;
end
end
assign io_smi_resp_bits = (N0)? T68 :
(N1)? T3 : 1'b0;
assign N0 = T9[5];
assign N1 = N13;
assign T3 = (N2)? T37 :
(N3)? T4 : 1'b0;
assign N2 = T9[4];
assign N3 = N14;
assign T4 = (N4)? T22 :
(N5)? T5 : 1'b0;
assign N4 = T9[3];
assign N5 = N15;
assign T5 = (N6)? T15 :
(N7)? T6 : 1'b0;
assign N6 = T9[2];
assign N7 = N16;
assign T6 = (N8)? T12 :
(N9)? T7 : 1'b0;
assign N8 = T9[1];
assign N9 = N17;
assign T7 = (N10)? io_scr_rdata_1 :
(N11)? io_scr_rdata_0 : 1'b0;
assign N10 = T9[0];
assign N11 = N18;
assign T12 = (N10)? io_scr_rdata_3 :
(N11)? io_scr_rdata_2 : 1'b0;
assign T15 = (N8)? T18 :
(N9)? T16 : 1'b0;
assign T16 = (N10)? io_scr_rdata_5 :
(N11)? io_scr_rdata_4 : 1'b0;
assign T18 = (N10)? io_scr_rdata_7 :
(N11)? io_scr_rdata_6 : 1'b0;
assign T22 = (N6)? T29 :
(N7)? T23 : 1'b0;
assign T23 = (N8)? T26 :
(N9)? T24 : 1'b0;
assign T24 = (N10)? io_scr_rdata_9 :
(N11)? io_scr_rdata_8 : 1'b0;
assign T26 = (N10)? io_scr_rdata_11 :
(N11)? io_scr_rdata_10 : 1'b0;
assign T29 = (N8)? T32 :
(N9)? T30 : 1'b0;
assign T30 = (N10)? io_scr_rdata_13 :
(N11)? io_scr_rdata_12 : 1'b0;
assign T32 = (N10)? io_scr_rdata_15 :
(N11)? io_scr_rdata_14 : 1'b0;
assign T37 = (N4)? T52 :
(N5)? T38 : 1'b0;
assign T38 = (N6)? T45 :
(N7)? T39 : 1'b0;
assign T39 = (N8)? T42 :
(N9)? T40 : 1'b0;
assign T40 = (N10)? io_scr_rdata_17 :
(N11)? io_scr_rdata_16 : 1'b0;
assign T42 = (N10)? io_scr_rdata_19 :
(N11)? io_scr_rdata_18 : 1'b0;
assign T45 = (N8)? T48 :
(N9)? T46 : 1'b0;
assign T46 = (N10)? io_scr_rdata_21 :
(N11)? io_scr_rdata_20 : 1'b0;
assign T48 = (N10)? io_scr_rdata_23 :
(N11)? io_scr_rdata_22 : 1'b0;
assign T52 = (N6)? T59 :
(N7)? T53 : 1'b0;
assign T53 = (N8)? T56 :
(N9)? T54 : 1'b0;
assign T54 = (N10)? io_scr_rdata_25 :
(N11)? io_scr_rdata_24 : 1'b0;
assign T56 = (N10)? io_scr_rdata_27 :
(N11)? io_scr_rdata_26 : 1'b0;
assign T59 = (N8)? T62 :
(N9)? T60 : 1'b0;
assign T60 = (N10)? io_scr_rdata_29 :
(N11)? io_scr_rdata_28 : 1'b0;
assign T62 = (N10)? io_scr_rdata_31 :
(N11)? io_scr_rdata_30 : 1'b0;
assign T68 = (N2)? T99 :
(N3)? T69 : 1'b0;
assign T69 = (N4)? T84 :
(N5)? T70 : 1'b0;
assign T70 = (N6)? T77 :
(N7)? T71 : 1'b0;
assign T71 = (N8)? T74 :
(N9)? T72 : 1'b0;
assign T72 = (N10)? io_scr_rdata_33 :
(N11)? io_scr_rdata_32 : 1'b0;
assign T74 = (N10)? io_scr_rdata_35 :
(N11)? io_scr_rdata_34 : 1'b0;
assign T77 = (N8)? T80 :
(N9)? T78 : 1'b0;
assign T78 = (N10)? io_scr_rdata_37 :
(N11)? io_scr_rdata_36 : 1'b0;
assign T80 = (N10)? io_scr_rdata_39 :
(N11)? io_scr_rdata_38 : 1'b0;
assign T84 = (N6)? T91 :
(N7)? T85 : 1'b0;
assign T85 = (N8)? T88 :
(N9)? T86 : 1'b0;
assign T86 = (N10)? io_scr_rdata_41 :
(N11)? io_scr_rdata_40 : 1'b0;
assign T88 = (N10)? io_scr_rdata_43 :
(N11)? io_scr_rdata_42 : 1'b0;
assign T91 = (N8)? T94 :
(N9)? T92 : 1'b0;
assign T92 = (N10)? io_scr_rdata_45 :
(N11)? io_scr_rdata_44 : 1'b0;
assign T94 = (N10)? io_scr_rdata_47 :
(N11)? io_scr_rdata_46 : 1'b0;
assign T99 = (N4)? T114 :
(N5)? T100 : 1'b0;
assign T100 = (N6)? T107 :
(N7)? T101 : 1'b0;
assign T101 = (N8)? T104 :
(N9)? T102 : 1'b0;
assign T102 = (N10)? io_scr_rdata_49 :
(N11)? io_scr_rdata_48 : 1'b0;
assign T104 = (N10)? io_scr_rdata_51 :
(N11)? io_scr_rdata_50 : 1'b0;
assign T107 = (N8)? T110 :
(N9)? T108 : 1'b0;
assign T108 = (N10)? io_scr_rdata_53 :
(N11)? io_scr_rdata_52 : 1'b0;
assign T110 = (N10)? io_scr_rdata_55 :
(N11)? io_scr_rdata_54 : 1'b0;
assign T114 = (N6)? T121 :
(N7)? T115 : 1'b0;
assign T115 = (N8)? T118 :
(N9)? T116 : 1'b0;
assign T116 = (N10)? io_scr_rdata_57 :
(N11)? io_scr_rdata_56 : 1'b0;
assign T118 = (N10)? io_scr_rdata_59 :
(N11)? io_scr_rdata_58 : 1'b0;
assign T121 = (N8)? T124 :
(N9)? T122 : 1'b0;
assign T122 = (N10)? io_scr_rdata_61 :
(N11)? io_scr_rdata_60 : 1'b0;
assign T124 = (N10)? io_scr_rdata_63 :
(N11)? io_scr_rdata_62 : 1'b0;
assign N21 = (N12)? 1'b1 :
(N34)? 1'b1 :
(N20)? 1'b0 : 1'b0;
assign N12 = reset;
assign { N27, N26, N25, N24, N23, N22 } = (N12)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N34)? io_smi_req_bits_addr : 1'b0;
assign N31 = (N12)? 1'b1 :
(N35)? 1'b1 :
(N38)? 1'b1 :
(N30)? 1'b0 : 1'b0;
assign N32 = (N12)? 1'b0 :
(N35)? 1'b0 :
(N38)? 1'b1 : 1'b0;
assign io_scr_wen = T1 & io_smi_req_bits_rw;
assign T1 = io_smi_req_ready & io_smi_req_valid;
assign N13 = ~T9[5];
assign N14 = ~T9[4];
assign N15 = ~T9[3];
assign N16 = ~T9[2];
assign N17 = ~T9[1];
assign N18 = ~T9[0];
assign T11 = io_smi_req_ready & io_smi_req_valid;
assign T133 = io_smi_resp_ready & io_smi_resp_valid;
assign io_smi_req_ready = ~io_smi_resp_valid;
assign N19 = T11 | reset;
assign N20 = ~N19;
assign N28 = T133 | reset;
assign N29 = T11 | N28;
assign N30 = ~N29;
assign N33 = ~reset;
assign N34 = T11 & N33;
assign N35 = T133 & N33;
assign N36 = ~T133;
assign N37 = N33 & N36;
assign N38 = T11 & N37;
endmodule |
module Arbiter_6
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_beat,
io_in_1_bits_client_xact_id,
io_in_1_bits_manager_xact_id,
io_in_1_bits_is_builtin_type,
io_in_1_bits_g_type,
io_in_1_bits_data,
io_in_1_bits_client_id,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_beat,
io_in_0_bits_client_xact_id,
io_in_0_bits_manager_xact_id,
io_in_0_bits_is_builtin_type,
io_in_0_bits_g_type,
io_in_0_bits_data,
io_in_0_bits_client_id,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_client_xact_id,
io_out_bits_manager_xact_id,
io_out_bits_is_builtin_type,
io_out_bits_g_type,
io_out_bits_data,
io_out_bits_client_id,
io_chosen
);
input [2:0] io_in_1_bits_addr_beat;
input [3:0] io_in_1_bits_client_xact_id;
input [3:0] io_in_1_bits_g_type;
input [63:0] io_in_1_bits_data;
input [2:0] io_in_0_bits_addr_beat;
input [3:0] io_in_0_bits_client_xact_id;
input [3:0] io_in_0_bits_g_type;
input [63:0] io_in_0_bits_data;
output [2:0] io_out_bits_addr_beat;
output [3:0] io_out_bits_client_xact_id;
output [3:0] io_out_bits_g_type;
output [63:0] io_out_bits_data;
input io_in_1_valid;
input io_in_1_bits_manager_xact_id;
input io_in_1_bits_is_builtin_type;
input io_in_1_bits_client_id;
input io_in_0_valid;
input io_in_0_bits_manager_xact_id;
input io_in_0_bits_is_builtin_type;
input io_in_0_bits_client_id;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_manager_xact_id;
output io_out_bits_is_builtin_type;
output io_out_bits_client_id;
output io_chosen;
wire [2:0] io_out_bits_addr_beat;
wire [3:0] io_out_bits_client_xact_id,io_out_bits_g_type;
wire [63:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_manager_xact_id,
io_out_bits_is_builtin_type,io_out_bits_client_id,io_chosen,N0,N1,io_out_ready,T10;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_client_id = (N0)? io_in_1_bits_client_id :
(N1)? io_in_0_bits_client_id : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_data = (N0)? io_in_1_bits_data :
(N1)? io_in_0_bits_data : 1'b0;
assign io_out_bits_g_type = (N0)? io_in_1_bits_g_type :
(N1)? io_in_0_bits_g_type : 1'b0;
assign io_out_bits_is_builtin_type = (N0)? io_in_1_bits_is_builtin_type :
(N1)? io_in_0_bits_is_builtin_type : 1'b0;
assign io_out_bits_manager_xact_id = (N0)? io_in_1_bits_manager_xact_id :
(N1)? io_in_0_bits_manager_xact_id : 1'b0;
assign io_out_bits_client_xact_id = (N0)? io_in_1_bits_client_xact_id :
(N1)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_beat = (N0)? io_in_1_bits_addr_beat :
(N1)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T10 & io_out_ready;
assign T10 = ~io_in_0_valid;
endmodule |
module ClientTileLinkIOWrapper_0
(
io_in_acquire_ready,
io_in_acquire_valid,
io_in_acquire_bits_addr_block,
io_in_acquire_bits_client_xact_id,
io_in_acquire_bits_addr_beat,
io_in_acquire_bits_is_builtin_type,
io_in_acquire_bits_a_type,
io_in_acquire_bits_union,
io_in_acquire_bits_data,
io_in_grant_ready,
io_in_grant_valid,
io_in_grant_bits_addr_beat,
io_in_grant_bits_client_xact_id,
io_in_grant_bits_manager_xact_id,
io_in_grant_bits_is_builtin_type,
io_in_grant_bits_g_type,
io_in_grant_bits_data,
io_out_acquire_ready,
io_out_acquire_valid,
io_out_acquire_bits_addr_block,
io_out_acquire_bits_client_xact_id,
io_out_acquire_bits_addr_beat,
io_out_acquire_bits_is_builtin_type,
io_out_acquire_bits_a_type,
io_out_acquire_bits_union,
io_out_acquire_bits_data,
io_out_grant_ready,
io_out_grant_valid,
io_out_grant_bits_addr_beat,
io_out_grant_bits_client_xact_id,
io_out_grant_bits_manager_xact_id,
io_out_grant_bits_is_builtin_type,
io_out_grant_bits_g_type,
io_out_grant_bits_data,
io_out_probe_ready,
io_out_probe_valid,
io_out_probe_bits_addr_block,
io_out_probe_bits_p_type,
io_out_release_ready,
io_out_release_valid
);
input [25:0] io_in_acquire_bits_addr_block;
input [5:0] io_in_acquire_bits_client_xact_id;
input [1:0] io_in_acquire_bits_addr_beat;
input [2:0] io_in_acquire_bits_a_type;
input [16:0] io_in_acquire_bits_union;
input [127:0] io_in_acquire_bits_data;
output [1:0] io_in_grant_bits_addr_beat;
output [5:0] io_in_grant_bits_client_xact_id;
output [3:0] io_in_grant_bits_manager_xact_id;
output [3:0] io_in_grant_bits_g_type;
output [127:0] io_in_grant_bits_data;
output [25:0] io_out_acquire_bits_addr_block;
output [5:0] io_out_acquire_bits_client_xact_id;
output [1:0] io_out_acquire_bits_addr_beat;
output [2:0] io_out_acquire_bits_a_type;
output [16:0] io_out_acquire_bits_union;
output [127:0] io_out_acquire_bits_data;
input [1:0] io_out_grant_bits_addr_beat;
input [5:0] io_out_grant_bits_client_xact_id;
input [3:0] io_out_grant_bits_manager_xact_id;
input [3:0] io_out_grant_bits_g_type;
input [127:0] io_out_grant_bits_data;
input [25:0] io_out_probe_bits_addr_block;
input [1:0] io_out_probe_bits_p_type;
input io_in_acquire_valid;
input io_in_acquire_bits_is_builtin_type;
input io_in_grant_ready;
input io_out_acquire_ready;
input io_out_grant_valid;
input io_out_grant_bits_is_builtin_type;
input io_out_probe_valid;
input io_out_release_ready;
output io_in_acquire_ready;
output io_in_grant_valid;
output io_in_grant_bits_is_builtin_type;
output io_out_acquire_valid;
output io_out_acquire_bits_is_builtin_type;
output io_out_grant_ready;
output io_out_probe_ready;
output io_out_release_valid;
wire [1:0] io_in_grant_bits_addr_beat,io_out_acquire_bits_addr_beat;
wire [5:0] io_in_grant_bits_client_xact_id,io_out_acquire_bits_client_xact_id;
wire [3:0] io_in_grant_bits_manager_xact_id,io_in_grant_bits_g_type;
wire [127:0] io_in_grant_bits_data,io_out_acquire_bits_data;
wire [25:0] io_out_acquire_bits_addr_block;
wire [2:0] io_out_acquire_bits_a_type;
wire [16:0] io_out_acquire_bits_union;
wire io_in_acquire_ready,io_in_grant_valid,io_in_grant_bits_is_builtin_type,
io_out_acquire_valid,io_out_acquire_bits_is_builtin_type,io_out_grant_ready,
io_out_probe_ready,io_out_release_valid,io_out_acquire_ready,io_out_grant_valid,
io_out_grant_bits_is_builtin_type,io_in_acquire_valid,io_in_acquire_bits_is_builtin_type,
io_in_grant_ready;
assign io_out_probe_ready = 1'b1;
assign io_out_release_valid = 1'b0;
assign io_in_acquire_ready = io_out_acquire_ready;
assign io_in_grant_valid = io_out_grant_valid;
assign io_in_grant_bits_addr_beat[1] = io_out_grant_bits_addr_beat[1];
assign io_in_grant_bits_addr_beat[0] = io_out_grant_bits_addr_beat[0];
assign io_in_grant_bits_client_xact_id[5] = io_out_grant_bits_client_xact_id[5];
assign io_in_grant_bits_client_xact_id[4] = io_out_grant_bits_client_xact_id[4];
assign io_in_grant_bits_client_xact_id[3] = io_out_grant_bits_client_xact_id[3];
assign io_in_grant_bits_client_xact_id[2] = io_out_grant_bits_client_xact_id[2];
assign io_in_grant_bits_client_xact_id[1] = io_out_grant_bits_client_xact_id[1];
assign io_in_grant_bits_client_xact_id[0] = io_out_grant_bits_client_xact_id[0];
assign io_in_grant_bits_manager_xact_id[3] = io_out_grant_bits_manager_xact_id[3];
assign io_in_grant_bits_manager_xact_id[2] = io_out_grant_bits_manager_xact_id[2];
assign io_in_grant_bits_manager_xact_id[1] = io_out_grant_bits_manager_xact_id[1];
assign io_in_grant_bits_manager_xact_id[0] = io_out_grant_bits_manager_xact_id[0];
assign io_in_grant_bits_is_builtin_type = io_out_grant_bits_is_builtin_type;
assign io_in_grant_bits_g_type[3] = io_out_grant_bits_g_type[3];
assign io_in_grant_bits_g_type[2] = io_out_grant_bits_g_type[2];
assign io_in_grant_bits_g_type[1] = io_out_grant_bits_g_type[1];
assign io_in_grant_bits_g_type[0] = io_out_grant_bits_g_type[0];
assign io_in_grant_bits_data[127] = io_out_grant_bits_data[127];
assign io_in_grant_bits_data[126] = io_out_grant_bits_data[126];
assign io_in_grant_bits_data[125] = io_out_grant_bits_data[125];
assign io_in_grant_bits_data[124] = io_out_grant_bits_data[124];
assign io_in_grant_bits_data[123] = io_out_grant_bits_data[123];
assign io_in_grant_bits_data[122] = io_out_grant_bits_data[122];
assign io_in_grant_bits_data[121] = io_out_grant_bits_data[121];
assign io_in_grant_bits_data[120] = io_out_grant_bits_data[120];
assign io_in_grant_bits_data[119] = io_out_grant_bits_data[119];
assign io_in_grant_bits_data[118] = io_out_grant_bits_data[118];
assign io_in_grant_bits_data[117] = io_out_grant_bits_data[117];
assign io_in_grant_bits_data[116] = io_out_grant_bits_data[116];
assign io_in_grant_bits_data[115] = io_out_grant_bits_data[115];
assign io_in_grant_bits_data[114] = io_out_grant_bits_data[114];
assign io_in_grant_bits_data[113] = io_out_grant_bits_data[113];
assign io_in_grant_bits_data[112] = io_out_grant_bits_data[112];
assign io_in_grant_bits_data[111] = io_out_grant_bits_data[111];
assign io_in_grant_bits_data[110] = io_out_grant_bits_data[110];
assign io_in_grant_bits_data[109] = io_out_grant_bits_data[109];
assign io_in_grant_bits_data[108] = io_out_grant_bits_data[108];
assign io_in_grant_bits_data[107] = io_out_grant_bits_data[107];
assign io_in_grant_bits_data[106] = io_out_grant_bits_data[106];
assign io_in_grant_bits_data[105] = io_out_grant_bits_data[105];
assign io_in_grant_bits_data[104] = io_out_grant_bits_data[104];
assign io_in_grant_bits_data[103] = io_out_grant_bits_data[103];
assign io_in_grant_bits_data[102] = io_out_grant_bits_data[102];
assign io_in_grant_bits_data[101] = io_out_grant_bits_data[101];
assign io_in_grant_bits_data[100] = io_out_grant_bits_data[100];
assign io_in_grant_bits_data[99] = io_out_grant_bits_data[99];
assign io_in_grant_bits_data[98] = io_out_grant_bits_data[98];
assign io_in_grant_bits_data[97] = io_out_grant_bits_data[97];
assign io_in_grant_bits_data[96] = io_out_grant_bits_data[96];
assign io_in_grant_bits_data[95] = io_out_grant_bits_data[95];
assign io_in_grant_bits_data[94] = io_out_grant_bits_data[94];
assign io_in_grant_bits_data[93] = io_out_grant_bits_data[93];
assign io_in_grant_bits_data[92] = io_out_grant_bits_data[92];
assign io_in_grant_bits_data[91] = io_out_grant_bits_data[91];
assign io_in_grant_bits_data[90] = io_out_grant_bits_data[90];
assign io_in_grant_bits_data[89] = io_out_grant_bits_data[89];
assign io_in_grant_bits_data[88] = io_out_grant_bits_data[88];
assign io_in_grant_bits_data[87] = io_out_grant_bits_data[87];
assign io_in_grant_bits_data[86] = io_out_grant_bits_data[86];
assign io_in_grant_bits_data[85] = io_out_grant_bits_data[85];
assign io_in_grant_bits_data[84] = io_out_grant_bits_data[84];
assign io_in_grant_bits_data[83] = io_out_grant_bits_data[83];
assign io_in_grant_bits_data[82] = io_out_grant_bits_data[82];
assign io_in_grant_bits_data[81] = io_out_grant_bits_data[81];
assign io_in_grant_bits_data[80] = io_out_grant_bits_data[80];
assign io_in_grant_bits_data[79] = io_out_grant_bits_data[79];
assign io_in_grant_bits_data[78] = io_out_grant_bits_data[78];
assign io_in_grant_bits_data[77] = io_out_grant_bits_data[77];
assign io_in_grant_bits_data[76] = io_out_grant_bits_data[76];
assign io_in_grant_bits_data[75] = io_out_grant_bits_data[75];
assign io_in_grant_bits_data[74] = io_out_grant_bits_data[74];
assign io_in_grant_bits_data[73] = io_out_grant_bits_data[73];
assign io_in_grant_bits_data[72] = io_out_grant_bits_data[72];
assign io_in_grant_bits_data[71] = io_out_grant_bits_data[71];
assign io_in_grant_bits_data[70] = io_out_grant_bits_data[70];
assign io_in_grant_bits_data[69] = io_out_grant_bits_data[69];
assign io_in_grant_bits_data[68] = io_out_grant_bits_data[68];
assign io_in_grant_bits_data[67] = io_out_grant_bits_data[67];
assign io_in_grant_bits_data[66] = io_out_grant_bits_data[66];
assign io_in_grant_bits_data[65] = io_out_grant_bits_data[65];
assign io_in_grant_bits_data[64] = io_out_grant_bits_data[64];
assign io_in_grant_bits_data[63] = io_out_grant_bits_data[63];
assign io_in_grant_bits_data[62] = io_out_grant_bits_data[62];
assign io_in_grant_bits_data[61] = io_out_grant_bits_data[61];
assign io_in_grant_bits_data[60] = io_out_grant_bits_data[60];
assign io_in_grant_bits_data[59] = io_out_grant_bits_data[59];
assign io_in_grant_bits_data[58] = io_out_grant_bits_data[58];
assign io_in_grant_bits_data[57] = io_out_grant_bits_data[57];
assign io_in_grant_bits_data[56] = io_out_grant_bits_data[56];
assign io_in_grant_bits_data[55] = io_out_grant_bits_data[55];
assign io_in_grant_bits_data[54] = io_out_grant_bits_data[54];
assign io_in_grant_bits_data[53] = io_out_grant_bits_data[53];
assign io_in_grant_bits_data[52] = io_out_grant_bits_data[52];
assign io_in_grant_bits_data[51] = io_out_grant_bits_data[51];
assign io_in_grant_bits_data[50] = io_out_grant_bits_data[50];
assign io_in_grant_bits_data[49] = io_out_grant_bits_data[49];
assign io_in_grant_bits_data[48] = io_out_grant_bits_data[48];
assign io_in_grant_bits_data[47] = io_out_grant_bits_data[47];
assign io_in_grant_bits_data[46] = io_out_grant_bits_data[46];
assign io_in_grant_bits_data[45] = io_out_grant_bits_data[45];
assign io_in_grant_bits_data[44] = io_out_grant_bits_data[44];
assign io_in_grant_bits_data[43] = io_out_grant_bits_data[43];
assign io_in_grant_bits_data[42] = io_out_grant_bits_data[42];
assign io_in_grant_bits_data[41] = io_out_grant_bits_data[41];
assign io_in_grant_bits_data[40] = io_out_grant_bits_data[40];
assign io_in_grant_bits_data[39] = io_out_grant_bits_data[39];
assign io_in_grant_bits_data[38] = io_out_grant_bits_data[38];
assign io_in_grant_bits_data[37] = io_out_grant_bits_data[37];
assign io_in_grant_bits_data[36] = io_out_grant_bits_data[36];
assign io_in_grant_bits_data[35] = io_out_grant_bits_data[35];
assign io_in_grant_bits_data[34] = io_out_grant_bits_data[34];
assign io_in_grant_bits_data[33] = io_out_grant_bits_data[33];
assign io_in_grant_bits_data[32] = io_out_grant_bits_data[32];
assign io_in_grant_bits_data[31] = io_out_grant_bits_data[31];
assign io_in_grant_bits_data[30] = io_out_grant_bits_data[30];
assign io_in_grant_bits_data[29] = io_out_grant_bits_data[29];
assign io_in_grant_bits_data[28] = io_out_grant_bits_data[28];
assign io_in_grant_bits_data[27] = io_out_grant_bits_data[27];
assign io_in_grant_bits_data[26] = io_out_grant_bits_data[26];
assign io_in_grant_bits_data[25] = io_out_grant_bits_data[25];
assign io_in_grant_bits_data[24] = io_out_grant_bits_data[24];
assign io_in_grant_bits_data[23] = io_out_grant_bits_data[23];
assign io_in_grant_bits_data[22] = io_out_grant_bits_data[22];
assign io_in_grant_bits_data[21] = io_out_grant_bits_data[21];
assign io_in_grant_bits_data[20] = io_out_grant_bits_data[20];
assign io_in_grant_bits_data[19] = io_out_grant_bits_data[19];
assign io_in_grant_bits_data[18] = io_out_grant_bits_data[18];
assign io_in_grant_bits_data[17] = io_out_grant_bits_data[17];
assign io_in_grant_bits_data[16] = io_out_grant_bits_data[16];
assign io_in_grant_bits_data[15] = io_out_grant_bits_data[15];
assign io_in_grant_bits_data[14] = io_out_grant_bits_data[14];
assign io_in_grant_bits_data[13] = io_out_grant_bits_data[13];
assign io_in_grant_bits_data[12] = io_out_grant_bits_data[12];
assign io_in_grant_bits_data[11] = io_out_grant_bits_data[11];
assign io_in_grant_bits_data[10] = io_out_grant_bits_data[10];
assign io_in_grant_bits_data[9] = io_out_grant_bits_data[9];
assign io_in_grant_bits_data[8] = io_out_grant_bits_data[8];
assign io_in_grant_bits_data[7] = io_out_grant_bits_data[7];
assign io_in_grant_bits_data[6] = io_out_grant_bits_data[6];
assign io_in_grant_bits_data[5] = io_out_grant_bits_data[5];
assign io_in_grant_bits_data[4] = io_out_grant_bits_data[4];
assign io_in_grant_bits_data[3] = io_out_grant_bits_data[3];
assign io_in_grant_bits_data[2] = io_out_grant_bits_data[2];
assign io_in_grant_bits_data[1] = io_out_grant_bits_data[1];
assign io_in_grant_bits_data[0] = io_out_grant_bits_data[0];
assign io_out_acquire_valid = io_in_acquire_valid;
assign io_out_acquire_bits_addr_block[25] = io_in_acquire_bits_addr_block[25];
assign io_out_acquire_bits_addr_block[24] = io_in_acquire_bits_addr_block[24];
assign io_out_acquire_bits_addr_block[23] = io_in_acquire_bits_addr_block[23];
assign io_out_acquire_bits_addr_block[22] = io_in_acquire_bits_addr_block[22];
assign io_out_acquire_bits_addr_block[21] = io_in_acquire_bits_addr_block[21];
assign io_out_acquire_bits_addr_block[20] = io_in_acquire_bits_addr_block[20];
assign io_out_acquire_bits_addr_block[19] = io_in_acquire_bits_addr_block[19];
assign io_out_acquire_bits_addr_block[18] = io_in_acquire_bits_addr_block[18];
assign io_out_acquire_bits_addr_block[17] = io_in_acquire_bits_addr_block[17];
assign io_out_acquire_bits_addr_block[16] = io_in_acquire_bits_addr_block[16];
assign io_out_acquire_bits_addr_block[15] = io_in_acquire_bits_addr_block[15];
assign io_out_acquire_bits_addr_block[14] = io_in_acquire_bits_addr_block[14];
assign io_out_acquire_bits_addr_block[13] = io_in_acquire_bits_addr_block[13];
assign io_out_acquire_bits_addr_block[12] = io_in_acquire_bits_addr_block[12];
assign io_out_acquire_bits_addr_block[11] = io_in_acquire_bits_addr_block[11];
assign io_out_acquire_bits_addr_block[10] = io_in_acquire_bits_addr_block[10];
assign io_out_acquire_bits_addr_block[9] = io_in_acquire_bits_addr_block[9];
assign io_out_acquire_bits_addr_block[8] = io_in_acquire_bits_addr_block[8];
assign io_out_acquire_bits_addr_block[7] = io_in_acquire_bits_addr_block[7];
assign io_out_acquire_bits_addr_block[6] = io_in_acquire_bits_addr_block[6];
assign io_out_acquire_bits_addr_block[5] = io_in_acquire_bits_addr_block[5];
assign io_out_acquire_bits_addr_block[4] = io_in_acquire_bits_addr_block[4];
assign io_out_acquire_bits_addr_block[3] = io_in_acquire_bits_addr_block[3];
assign io_out_acquire_bits_addr_block[2] = io_in_acquire_bits_addr_block[2];
assign io_out_acquire_bits_addr_block[1] = io_in_acquire_bits_addr_block[1];
assign io_out_acquire_bits_addr_block[0] = io_in_acquire_bits_addr_block[0];
assign io_out_acquire_bits_client_xact_id[5] = io_in_acquire_bits_client_xact_id[5];
assign io_out_acquire_bits_client_xact_id[4] = io_in_acquire_bits_client_xact_id[4];
assign io_out_acquire_bits_client_xact_id[3] = io_in_acquire_bits_client_xact_id[3];
assign io_out_acquire_bits_client_xact_id[2] = io_in_acquire_bits_client_xact_id[2];
assign io_out_acquire_bits_client_xact_id[1] = io_in_acquire_bits_client_xact_id[1];
assign io_out_acquire_bits_client_xact_id[0] = io_in_acquire_bits_client_xact_id[0];
assign io_out_acquire_bits_addr_beat[1] = io_in_acquire_bits_addr_beat[1];
assign io_out_acquire_bits_addr_beat[0] = io_in_acquire_bits_addr_beat[0];
assign io_out_acquire_bits_is_builtin_type = io_in_acquire_bits_is_builtin_type;
assign io_out_acquire_bits_a_type[2] = io_in_acquire_bits_a_type[2];
assign io_out_acquire_bits_a_type[1] = io_in_acquire_bits_a_type[1];
assign io_out_acquire_bits_a_type[0] = io_in_acquire_bits_a_type[0];
assign io_out_acquire_bits_union[16] = io_in_acquire_bits_union[16];
assign io_out_acquire_bits_union[15] = io_in_acquire_bits_union[15];
assign io_out_acquire_bits_union[14] = io_in_acquire_bits_union[14];
assign io_out_acquire_bits_union[13] = io_in_acquire_bits_union[13];
assign io_out_acquire_bits_union[12] = io_in_acquire_bits_union[12];
assign io_out_acquire_bits_union[11] = io_in_acquire_bits_union[11];
assign io_out_acquire_bits_union[10] = io_in_acquire_bits_union[10];
assign io_out_acquire_bits_union[9] = io_in_acquire_bits_union[9];
assign io_out_acquire_bits_union[8] = io_in_acquire_bits_union[8];
assign io_out_acquire_bits_union[7] = io_in_acquire_bits_union[7];
assign io_out_acquire_bits_union[6] = io_in_acquire_bits_union[6];
assign io_out_acquire_bits_union[5] = io_in_acquire_bits_union[5];
assign io_out_acquire_bits_union[4] = io_in_acquire_bits_union[4];
assign io_out_acquire_bits_union[3] = io_in_acquire_bits_union[3];
assign io_out_acquire_bits_union[2] = io_in_acquire_bits_union[2];
assign io_out_acquire_bits_union[1] = io_in_acquire_bits_union[1];
assign io_out_acquire_bits_union[0] = io_in_acquire_bits_union[0];
assign io_out_acquire_bits_data[127] = io_in_acquire_bits_data[127];
assign io_out_acquire_bits_data[126] = io_in_acquire_bits_data[126];
assign io_out_acquire_bits_data[125] = io_in_acquire_bits_data[125];
assign io_out_acquire_bits_data[124] = io_in_acquire_bits_data[124];
assign io_out_acquire_bits_data[123] = io_in_acquire_bits_data[123];
assign io_out_acquire_bits_data[122] = io_in_acquire_bits_data[122];
assign io_out_acquire_bits_data[121] = io_in_acquire_bits_data[121];
assign io_out_acquire_bits_data[120] = io_in_acquire_bits_data[120];
assign io_out_acquire_bits_data[119] = io_in_acquire_bits_data[119];
assign io_out_acquire_bits_data[118] = io_in_acquire_bits_data[118];
assign io_out_acquire_bits_data[117] = io_in_acquire_bits_data[117];
assign io_out_acquire_bits_data[116] = io_in_acquire_bits_data[116];
assign io_out_acquire_bits_data[115] = io_in_acquire_bits_data[115];
assign io_out_acquire_bits_data[114] = io_in_acquire_bits_data[114];
assign io_out_acquire_bits_data[113] = io_in_acquire_bits_data[113];
assign io_out_acquire_bits_data[112] = io_in_acquire_bits_data[112];
assign io_out_acquire_bits_data[111] = io_in_acquire_bits_data[111];
assign io_out_acquire_bits_data[110] = io_in_acquire_bits_data[110];
assign io_out_acquire_bits_data[109] = io_in_acquire_bits_data[109];
assign io_out_acquire_bits_data[108] = io_in_acquire_bits_data[108];
assign io_out_acquire_bits_data[107] = io_in_acquire_bits_data[107];
assign io_out_acquire_bits_data[106] = io_in_acquire_bits_data[106];
assign io_out_acquire_bits_data[105] = io_in_acquire_bits_data[105];
assign io_out_acquire_bits_data[104] = io_in_acquire_bits_data[104];
assign io_out_acquire_bits_data[103] = io_in_acquire_bits_data[103];
assign io_out_acquire_bits_data[102] = io_in_acquire_bits_data[102];
assign io_out_acquire_bits_data[101] = io_in_acquire_bits_data[101];
assign io_out_acquire_bits_data[100] = io_in_acquire_bits_data[100];
assign io_out_acquire_bits_data[99] = io_in_acquire_bits_data[99];
assign io_out_acquire_bits_data[98] = io_in_acquire_bits_data[98];
assign io_out_acquire_bits_data[97] = io_in_acquire_bits_data[97];
assign io_out_acquire_bits_data[96] = io_in_acquire_bits_data[96];
assign io_out_acquire_bits_data[95] = io_in_acquire_bits_data[95];
assign io_out_acquire_bits_data[94] = io_in_acquire_bits_data[94];
assign io_out_acquire_bits_data[93] = io_in_acquire_bits_data[93];
assign io_out_acquire_bits_data[92] = io_in_acquire_bits_data[92];
assign io_out_acquire_bits_data[91] = io_in_acquire_bits_data[91];
assign io_out_acquire_bits_data[90] = io_in_acquire_bits_data[90];
assign io_out_acquire_bits_data[89] = io_in_acquire_bits_data[89];
assign io_out_acquire_bits_data[88] = io_in_acquire_bits_data[88];
assign io_out_acquire_bits_data[87] = io_in_acquire_bits_data[87];
assign io_out_acquire_bits_data[86] = io_in_acquire_bits_data[86];
assign io_out_acquire_bits_data[85] = io_in_acquire_bits_data[85];
assign io_out_acquire_bits_data[84] = io_in_acquire_bits_data[84];
assign io_out_acquire_bits_data[83] = io_in_acquire_bits_data[83];
assign io_out_acquire_bits_data[82] = io_in_acquire_bits_data[82];
assign io_out_acquire_bits_data[81] = io_in_acquire_bits_data[81];
assign io_out_acquire_bits_data[80] = io_in_acquire_bits_data[80];
assign io_out_acquire_bits_data[79] = io_in_acquire_bits_data[79];
assign io_out_acquire_bits_data[78] = io_in_acquire_bits_data[78];
assign io_out_acquire_bits_data[77] = io_in_acquire_bits_data[77];
assign io_out_acquire_bits_data[76] = io_in_acquire_bits_data[76];
assign io_out_acquire_bits_data[75] = io_in_acquire_bits_data[75];
assign io_out_acquire_bits_data[74] = io_in_acquire_bits_data[74];
assign io_out_acquire_bits_data[73] = io_in_acquire_bits_data[73];
assign io_out_acquire_bits_data[72] = io_in_acquire_bits_data[72];
assign io_out_acquire_bits_data[71] = io_in_acquire_bits_data[71];
assign io_out_acquire_bits_data[70] = io_in_acquire_bits_data[70];
assign io_out_acquire_bits_data[69] = io_in_acquire_bits_data[69];
assign io_out_acquire_bits_data[68] = io_in_acquire_bits_data[68];
assign io_out_acquire_bits_data[67] = io_in_acquire_bits_data[67];
assign io_out_acquire_bits_data[66] = io_in_acquire_bits_data[66];
assign io_out_acquire_bits_data[65] = io_in_acquire_bits_data[65];
assign io_out_acquire_bits_data[64] = io_in_acquire_bits_data[64];
assign io_out_acquire_bits_data[63] = io_in_acquire_bits_data[63];
assign io_out_acquire_bits_data[62] = io_in_acquire_bits_data[62];
assign io_out_acquire_bits_data[61] = io_in_acquire_bits_data[61];
assign io_out_acquire_bits_data[60] = io_in_acquire_bits_data[60];
assign io_out_acquire_bits_data[59] = io_in_acquire_bits_data[59];
assign io_out_acquire_bits_data[58] = io_in_acquire_bits_data[58];
assign io_out_acquire_bits_data[57] = io_in_acquire_bits_data[57];
assign io_out_acquire_bits_data[56] = io_in_acquire_bits_data[56];
assign io_out_acquire_bits_data[55] = io_in_acquire_bits_data[55];
assign io_out_acquire_bits_data[54] = io_in_acquire_bits_data[54];
assign io_out_acquire_bits_data[53] = io_in_acquire_bits_data[53];
assign io_out_acquire_bits_data[52] = io_in_acquire_bits_data[52];
assign io_out_acquire_bits_data[51] = io_in_acquire_bits_data[51];
assign io_out_acquire_bits_data[50] = io_in_acquire_bits_data[50];
assign io_out_acquire_bits_data[49] = io_in_acquire_bits_data[49];
assign io_out_acquire_bits_data[48] = io_in_acquire_bits_data[48];
assign io_out_acquire_bits_data[47] = io_in_acquire_bits_data[47];
assign io_out_acquire_bits_data[46] = io_in_acquire_bits_data[46];
assign io_out_acquire_bits_data[45] = io_in_acquire_bits_data[45];
assign io_out_acquire_bits_data[44] = io_in_acquire_bits_data[44];
assign io_out_acquire_bits_data[43] = io_in_acquire_bits_data[43];
assign io_out_acquire_bits_data[42] = io_in_acquire_bits_data[42];
assign io_out_acquire_bits_data[41] = io_in_acquire_bits_data[41];
assign io_out_acquire_bits_data[40] = io_in_acquire_bits_data[40];
assign io_out_acquire_bits_data[39] = io_in_acquire_bits_data[39];
assign io_out_acquire_bits_data[38] = io_in_acquire_bits_data[38];
assign io_out_acquire_bits_data[37] = io_in_acquire_bits_data[37];
assign io_out_acquire_bits_data[36] = io_in_acquire_bits_data[36];
assign io_out_acquire_bits_data[35] = io_in_acquire_bits_data[35];
assign io_out_acquire_bits_data[34] = io_in_acquire_bits_data[34];
assign io_out_acquire_bits_data[33] = io_in_acquire_bits_data[33];
assign io_out_acquire_bits_data[32] = io_in_acquire_bits_data[32];
assign io_out_acquire_bits_data[31] = io_in_acquire_bits_data[31];
assign io_out_acquire_bits_data[30] = io_in_acquire_bits_data[30];
assign io_out_acquire_bits_data[29] = io_in_acquire_bits_data[29];
assign io_out_acquire_bits_data[28] = io_in_acquire_bits_data[28];
assign io_out_acquire_bits_data[27] = io_in_acquire_bits_data[27];
assign io_out_acquire_bits_data[26] = io_in_acquire_bits_data[26];
assign io_out_acquire_bits_data[25] = io_in_acquire_bits_data[25];
assign io_out_acquire_bits_data[24] = io_in_acquire_bits_data[24];
assign io_out_acquire_bits_data[23] = io_in_acquire_bits_data[23];
assign io_out_acquire_bits_data[22] = io_in_acquire_bits_data[22];
assign io_out_acquire_bits_data[21] = io_in_acquire_bits_data[21];
assign io_out_acquire_bits_data[20] = io_in_acquire_bits_data[20];
assign io_out_acquire_bits_data[19] = io_in_acquire_bits_data[19];
assign io_out_acquire_bits_data[18] = io_in_acquire_bits_data[18];
assign io_out_acquire_bits_data[17] = io_in_acquire_bits_data[17];
assign io_out_acquire_bits_data[16] = io_in_acquire_bits_data[16];
assign io_out_acquire_bits_data[15] = io_in_acquire_bits_data[15];
assign io_out_acquire_bits_data[14] = io_in_acquire_bits_data[14];
assign io_out_acquire_bits_data[13] = io_in_acquire_bits_data[13];
assign io_out_acquire_bits_data[12] = io_in_acquire_bits_data[12];
assign io_out_acquire_bits_data[11] = io_in_acquire_bits_data[11];
assign io_out_acquire_bits_data[10] = io_in_acquire_bits_data[10];
assign io_out_acquire_bits_data[9] = io_in_acquire_bits_data[9];
assign io_out_acquire_bits_data[8] = io_in_acquire_bits_data[8];
assign io_out_acquire_bits_data[7] = io_in_acquire_bits_data[7];
assign io_out_acquire_bits_data[6] = io_in_acquire_bits_data[6];
assign io_out_acquire_bits_data[5] = io_in_acquire_bits_data[5];
assign io_out_acquire_bits_data[4] = io_in_acquire_bits_data[4];
assign io_out_acquire_bits_data[3] = io_in_acquire_bits_data[3];
assign io_out_acquire_bits_data[2] = io_in_acquire_bits_data[2];
assign io_out_acquire_bits_data[1] = io_in_acquire_bits_data[1];
assign io_out_acquire_bits_data[0] = io_in_acquire_bits_data[0];
assign io_out_grant_ready = io_in_grant_ready;
endmodule |
module INToRecFN_1
(
io_signedIn,
io_in,
io_roundingMode,
io_out,
io_exceptionFlags
);
input [63:0] io_in;
input [1:0] io_roundingMode;
output [64:0] io_out;
output [4:0] io_exceptionFlags;
input io_signedIn;
wire [64:0] io_out;
wire [4:0] io_exceptionFlags,T69,T70,T71,T72,T73,T74,T75,T76,T77,T78,T79,T80,T81,T82,T83,
T84;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,
round,N197,T16_53,T21,T17,N198,T18,T19,T25,T22,T23,T26,T29,N199,N201,N202,N203,N204,
N205,N206,SV2V_UNCONNECTED_1;
wire [0:0] T2;
wire [9:0] T4;
wire [62:10] normAbsIn;
wire [5:0] normCount,T37,T38,T39,T40,T41,T42,T43,T44,T45,T46,T47,T48,T49,T50,T51,T52,T53,
T54,T55,T56,T57,T58,T59,T60,T61,T62,T63,T64,T65,T66,T67,T68,T34;
wire [3:0] T85,T86,T87,T88,T89,T90,T91,T92;
wire [2:0] T93,T94,T95,T96;
wire [1:0] T97,T98;
wire [63:0] T7,T9;
wire [53:53] roundedNorm;
wire [51:0] T16;
assign io_out[62] = 1'b0;
assign io_out[61] = 1'b0;
assign io_out[60] = 1'b0;
assign io_out[59] = 1'b0;
assign io_exceptionFlags[1] = 1'b0;
assign io_exceptionFlags[2] = 1'b0;
assign io_exceptionFlags[3] = 1'b0;
assign io_exceptionFlags[4] = 1'b0;
assign T2[0] = T4 != 1'b0;
assign T29 = normAbsIn[11:10] == { 1'b1, 1'b1 };
assign N199 = T2[0] & normAbsIn[10];
assign io_exceptionFlags[0] = T2[0] | normAbsIn[10];
assign N201 = io_roundingMode[0] & io_roundingMode[1];
assign N202 = io_roundingMode[0] | io_roundingMode[1];
assign N203 = ~N202;
assign N204 = ~io_roundingMode[1];
assign N205 = io_roundingMode[0] | N204;
assign N206 = ~N205;
assign { io_out[63:63], normAbsIn, T4 } = T7 << normCount;
assign T9 = 1'b0 - io_in;
assign { T16_53, SV2V_UNCONNECTED_1, T16 } = { io_out[63:63], normAbsIn[62:11] } + 1'b1;
assign io_out[58:52] = T34 + roundedNorm[53];
assign T37 = (N0)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 } :
(N1)? T38 : 1'b0;
assign N0 = T7[63];
assign N1 = N134;
assign T38 = (N2)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N3)? T39 : 1'b0;
assign N2 = T7[62];
assign N3 = N135;
assign T39 = (N4)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1 } :
(N5)? T40 : 1'b0;
assign N4 = T7[61];
assign N5 = N136;
assign T40 = (N6)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b0, 1'b0 } :
(N7)? T41 : 1'b0;
assign N6 = T7[60];
assign N7 = N137;
assign T41 = (N8)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N9)? T42 : 1'b0;
assign N8 = T7[59];
assign N9 = N138;
assign T42 = (N10)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0 } :
(N11)? T43 : 1'b0;
assign N10 = T7[58];
assign N11 = N139;
assign T43 = (N12)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N13)? T44 : 1'b0;
assign N12 = T7[57];
assign N13 = N140;
assign T44 = (N14)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N15)? T45 : 1'b0;
assign N14 = T7[56];
assign N15 = N141;
assign T45 = (N16)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 } :
(N17)? T46 : 1'b0;
assign N16 = T7[55];
assign N17 = N142;
assign T46 = (N18)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0 } :
(N19)? T47 : 1'b0;
assign N18 = T7[54];
assign N19 = N143;
assign T47 = (N20)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N21)? T48 : 1'b0;
assign N20 = T7[53];
assign N21 = N144;
assign T48 = (N22)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N23)? T49 : 1'b0;
assign N22 = T7[52];
assign N23 = N145;
assign T49 = (N24)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N25)? T50 : 1'b0;
assign N24 = T7[51];
assign N25 = N146;
assign T50 = (N26)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N27)? T51 : 1'b0;
assign N26 = T7[50];
assign N27 = N147;
assign T51 = (N28)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N29)? T52 : 1'b0;
assign N28 = T7[49];
assign N29 = N148;
assign T52 = (N30)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N31)? T53 : 1'b0;
assign N30 = T7[48];
assign N31 = N149;
assign T53 = (N32)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1 } :
(N33)? T54 : 1'b0;
assign N32 = T7[47];
assign N33 = N150;
assign T54 = (N34)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N35)? T55 : 1'b0;
assign N34 = T7[46];
assign N35 = N151;
assign T55 = (N36)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b1 } :
(N37)? T56 : 1'b0;
assign N36 = T7[45];
assign N37 = N152;
assign T56 = (N38)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0 } :
(N39)? T57 : 1'b0;
assign N38 = T7[44];
assign N39 = N153;
assign T57 = (N40)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N41)? T58 : 1'b0;
assign N40 = T7[43];
assign N41 = N154;
assign T58 = (N42)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0 } :
(N43)? T59 : 1'b0;
assign N42 = T7[42];
assign N43 = N155;
assign T59 = (N44)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N45)? T60 : 1'b0;
assign N44 = T7[41];
assign N45 = N156;
assign T60 = (N46)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N47)? T61 : 1'b0;
assign N46 = T7[40];
assign N47 = N157;
assign T61 = (N48)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 } :
(N49)? T62 : 1'b0;
assign N48 = T7[39];
assign N49 = N158;
assign T62 = (N50)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 } :
(N51)? T63 : 1'b0;
assign N50 = T7[38];
assign N51 = N159;
assign T63 = (N52)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N53)? T64 : 1'b0;
assign N52 = T7[37];
assign N53 = N160;
assign T64 = (N54)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N55)? T65 : 1'b0;
assign N54 = T7[36];
assign N55 = N161;
assign T65 = (N56)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N57)? T66 : 1'b0;
assign N56 = T7[35];
assign N57 = N162;
assign T66 = (N58)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N59)? T67 : 1'b0;
assign N58 = T7[34];
assign N59 = N163;
assign T67 = (N60)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N61)? T68 : 1'b0;
assign N60 = T7[33];
assign N61 = N164;
assign T68[4:0] = (N62)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N63)? T69 : 1'b0;
assign N62 = T68[5];
assign N63 = N165;
assign T69 = (N64)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 } :
(N65)? T70 : 1'b0;
assign N64 = T7[31];
assign N65 = N166;
assign T70 = (N66)? { 1'b1, 1'b1, 1'b1, 1'b1, 1'b0 } :
(N67)? T71 : 1'b0;
assign N66 = T7[30];
assign N67 = N167;
assign T71 = (N68)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b1 } :
(N69)? T72 : 1'b0;
assign N68 = T7[29];
assign N69 = N168;
assign T72 = (N70)? { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0 } :
(N71)? T73 : 1'b0;
assign N70 = T7[28];
assign N71 = N169;
assign T73 = (N72)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N73)? T74 : 1'b0;
assign N72 = T7[27];
assign N73 = N170;
assign T74 = (N74)? { 1'b1, 1'b1, 1'b0, 1'b1, 1'b0 } :
(N75)? T75 : 1'b0;
assign N74 = T7[26];
assign N75 = N171;
assign T75 = (N76)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1 } :
(N77)? T76 : 1'b0;
assign N76 = T7[25];
assign N77 = N172;
assign T76 = (N78)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N79)? T77 : 1'b0;
assign N78 = T7[24];
assign N79 = N173;
assign T77 = (N80)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b1 } :
(N81)? T78 : 1'b0;
assign N80 = T7[23];
assign N81 = N174;
assign T78 = (N82)? { 1'b1, 1'b0, 1'b1, 1'b1, 1'b0 } :
(N83)? T79 : 1'b0;
assign N82 = T7[22];
assign N83 = N175;
assign T79 = (N84)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N85)? T80 : 1'b0;
assign N84 = T7[21];
assign N85 = N176;
assign T80 = (N86)? { 1'b1, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N87)? T81 : 1'b0;
assign N86 = T7[20];
assign N87 = N177;
assign T81 = (N88)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N89)? T82 : 1'b0;
assign N88 = T7[19];
assign N89 = N178;
assign T82 = (N90)? { 1'b1, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N91)? T83 : 1'b0;
assign N90 = T7[18];
assign N91 = N179;
assign T83 = (N92)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b1 } :
(N93)? T84 : 1'b0;
assign N92 = T7[17];
assign N93 = N180;
assign T84[3:0] = (N94)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N95)? T85 : 1'b0;
assign N94 = T84[4];
assign N95 = N181;
assign T85 = (N96)? { 1'b1, 1'b1, 1'b1, 1'b1 } :
(N97)? T86 : 1'b0;
assign N96 = T7[15];
assign N97 = N182;
assign T86 = (N98)? { 1'b1, 1'b1, 1'b1, 1'b0 } :
(N99)? T87 : 1'b0;
assign N98 = T7[14];
assign N99 = N183;
assign T87 = (N100)? { 1'b1, 1'b1, 1'b0, 1'b1 } :
(N101)? T88 : 1'b0;
assign N100 = T7[13];
assign N101 = N184;
assign T88 = (N102)? { 1'b1, 1'b1, 1'b0, 1'b0 } :
(N103)? T89 : 1'b0;
assign N102 = T7[12];
assign N103 = N185;
assign T89 = (N104)? { 1'b1, 1'b0, 1'b1, 1'b1 } :
(N105)? T90 : 1'b0;
assign N104 = T7[11];
assign N105 = N186;
assign T90 = (N106)? { 1'b1, 1'b0, 1'b1, 1'b0 } :
(N107)? T91 : 1'b0;
assign N106 = T7[10];
assign N107 = N187;
assign T91 = (N108)? { 1'b1, 1'b0, 1'b0, 1'b1 } :
(N109)? T92 : 1'b0;
assign N108 = T7[9];
assign N109 = N188;
assign T92[2:0] = (N110)? { 1'b0, 1'b0, 1'b0 } :
(N111)? T93 : 1'b0;
assign N110 = T92[3];
assign N111 = N189;
assign T93 = (N112)? { 1'b1, 1'b1, 1'b1 } :
(N113)? T94 : 1'b0;
assign N112 = T7[7];
assign N113 = N190;
assign T94 = (N114)? { 1'b1, 1'b1, 1'b0 } :
(N115)? T95 : 1'b0;
assign N114 = T7[6];
assign N115 = N191;
assign T95 = (N116)? { 1'b1, 1'b0, 1'b1 } :
(N117)? T96 : 1'b0;
assign N116 = T7[5];
assign N117 = N192;
assign T96[1:0] = (N118)? { 1'b0, 1'b0 } :
(N119)? T97 : 1'b0;
assign N118 = T96[2];
assign N119 = N193;
assign T97 = (N120)? { 1'b1, 1'b1 } :
(N121)? T98 : 1'b0;
assign N120 = T7[3];
assign N121 = N194;
assign T98[0] = (N122)? 1'b0 :
(N123)? T7[1] : 1'b0;
assign N122 = T98[1];
assign N123 = N195;
assign T7 = (N124)? T9 :
(N125)? io_in : 1'b0;
assign N124 = io_out[64];
assign N125 = N196;
assign { roundedNorm[53:53], io_out[51:0] } = (N126)? { T16_53, T16 } :
(N127)? { 1'b0, normAbsIn[62:11] } : 1'b0;
assign N126 = round;
assign N127 = N197;
assign T17 = (N128)? T18 :
(N129)? 1'b0 : 1'b0;
assign N128 = N201;
assign N129 = N198;
assign T22 = (N130)? T23 :
(N131)? 1'b0 : 1'b0;
assign N130 = N206;
assign N131 = N205;
assign T25 = (N132)? T26 :
(N133)? 1'b0 : 1'b0;
assign N132 = N203;
assign N133 = N202;
assign normCount[5] = ~T37[5];
assign normCount[4] = ~T37[4];
assign normCount[3] = ~T37[3];
assign normCount[2] = ~T37[2];
assign normCount[1] = ~T37[1];
assign normCount[0] = ~T37[0];
assign N134 = ~T7[63];
assign N135 = ~T7[62];
assign N136 = ~T7[61];
assign N137 = ~T7[60];
assign N138 = ~T7[59];
assign N139 = ~T7[58];
assign N140 = ~T7[57];
assign N141 = ~T7[56];
assign N142 = ~T7[55];
assign N143 = ~T7[54];
assign N144 = ~T7[53];
assign N145 = ~T7[52];
assign N146 = ~T7[51];
assign N147 = ~T7[50];
assign N148 = ~T7[49];
assign N149 = ~T7[48];
assign N150 = ~T7[47];
assign N151 = ~T7[46];
assign N152 = ~T7[45];
assign N153 = ~T7[44];
assign N154 = ~T7[43];
assign N155 = ~T7[42];
assign N156 = ~T7[41];
assign N157 = ~T7[40];
assign N158 = ~T7[39];
assign N159 = ~T7[38];
assign N160 = ~T7[37];
assign N161 = ~T7[36];
assign N162 = ~T7[35];
assign N163 = ~T7[34];
assign N164 = ~T7[33];
assign N165 = ~T7[32];
assign T68[5] = T7[32];
assign N166 = ~T7[31];
assign N167 = ~T7[30];
assign N168 = ~T7[29];
assign N169 = ~T7[28];
assign N170 = ~T7[27];
assign N171 = ~T7[26];
assign N172 = ~T7[25];
assign N173 = ~T7[24];
assign N174 = ~T7[23];
assign N175 = ~T7[22];
assign N176 = ~T7[21];
assign N177 = ~T7[20];
assign N178 = ~T7[19];
assign N179 = ~T7[18];
assign N180 = ~T7[17];
assign N181 = ~T7[16];
assign T84[4] = T7[16];
assign N182 = ~T7[15];
assign N183 = ~T7[14];
assign N184 = ~T7[13];
assign N185 = ~T7[12];
assign N186 = ~T7[11];
assign N187 = ~T7[10];
assign N188 = ~T7[9];
assign N189 = ~T7[8];
assign T92[3] = T7[8];
assign N190 = ~T7[7];
assign N191 = ~T7[6];
assign N192 = ~T7[5];
assign N193 = ~T7[4];
assign T96[2] = T7[4];
assign N194 = ~T7[3];
assign N195 = ~T7[2];
assign T98[1] = T7[2];
assign N196 = ~io_out[64];
assign io_out[64] = io_signedIn & io_in[63];
assign N197 = ~round;
assign round = T21 | T17;
assign N198 = ~N201;
assign T18 = T19 & io_exceptionFlags[0];
assign T19 = ~io_out[64];
assign T21 = T25 | T22;
assign T23 = io_out[64] & io_exceptionFlags[0];
assign T26 = T29 | N199;
assign T34[5] = ~normCount[5];
assign T34[4] = ~normCount[4];
assign T34[3] = ~normCount[3];
assign T34[2] = ~normCount[2];
assign T34[1] = ~normCount[1];
assign T34[0] = ~normCount[0];
endmodule |
module Arbiter_10
(
io_in_0_ready,
io_in_0_valid,
io_in_0_bits,
io_out_ready,
io_out_valid,
io_out_bits,
io_chosen
);
input io_in_0_valid;
input io_in_0_bits;
input io_out_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits;
output io_chosen;
wire io_in_0_ready,io_out_valid,io_out_bits,io_chosen,io_out_ready,io_in_0_valid,
io_in_0_bits;
assign io_chosen = 1'b0;
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
assign io_out_bits = io_in_0_bits;
endmodule |
module Arbiter_9
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits,
io_out_ready,
io_out_valid,
io_out_bits,
io_chosen
);
input io_in_1_valid;
input io_in_1_bits;
input io_in_0_valid;
input io_in_0_bits;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits;
output io_chosen;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits,io_chosen,N0,N1,
io_out_ready,T4;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits = (N0)? io_in_1_bits :
(N1)? io_in_0_bits : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T4 & io_out_ready;
assign T4 = ~io_in_0_valid;
endmodule |
module LockingArbiter_1
(
clk,
reset,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_addr_block,
io_in_2_bits_client_xact_id,
io_in_2_bits_addr_beat,
io_in_2_bits_is_builtin_type,
io_in_2_bits_a_type,
io_in_2_bits_union,
io_in_2_bits_data,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_addr_beat,
io_in_1_bits_is_builtin_type,
io_in_1_bits_a_type,
io_in_1_bits_union,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_addr_beat,
io_in_0_bits_is_builtin_type,
io_in_0_bits_a_type,
io_in_0_bits_union,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_addr_beat,
io_out_bits_is_builtin_type,
io_out_bits_a_type,
io_out_bits_union,
io_out_bits_data,
io_chosen
);
input [25:0] io_in_2_bits_addr_block;
input [5:0] io_in_2_bits_client_xact_id;
input [1:0] io_in_2_bits_addr_beat;
input [2:0] io_in_2_bits_a_type;
input [16:0] io_in_2_bits_union;
input [127:0] io_in_2_bits_data;
input [25:0] io_in_1_bits_addr_block;
input [5:0] io_in_1_bits_client_xact_id;
input [1:0] io_in_1_bits_addr_beat;
input [2:0] io_in_1_bits_a_type;
input [16:0] io_in_1_bits_union;
input [127:0] io_in_1_bits_data;
input [25:0] io_in_0_bits_addr_block;
input [5:0] io_in_0_bits_client_xact_id;
input [1:0] io_in_0_bits_addr_beat;
input [2:0] io_in_0_bits_a_type;
input [16:0] io_in_0_bits_union;
input [127:0] io_in_0_bits_data;
output [25:0] io_out_bits_addr_block;
output [5:0] io_out_bits_client_xact_id;
output [1:0] io_out_bits_addr_beat;
output [2:0] io_out_bits_a_type;
output [16:0] io_out_bits_union;
output [127:0] io_out_bits_data;
output [1:0] io_chosen;
input clk;
input reset;
input io_in_2_valid;
input io_in_2_bits_is_builtin_type;
input io_in_1_valid;
input io_in_1_bits_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_is_builtin_type;
input io_out_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_is_builtin_type;
wire [25:0] io_out_bits_addr_block,T48;
wire [5:0] io_out_bits_client_xact_id,T44;
wire [1:0] io_out_bits_addr_beat,io_chosen,choose,T1,T3,T4,T17,T40;
wire [2:0] io_out_bits_a_type,T32;
wire [16:0] io_out_bits_union,T28;
wire [127:0] io_out_bits_data,T23;
wire io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,
io_out_bits_is_builtin_type,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,T7,T6,N14,T5,N15,T9,T8,T12,T10,
T20,T15,T16,T21,N16,N17,T36,T52,T56,T59,T60,T63,T64,T65,N18,N19,N20,N21,N22,N23,
N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,
N44,N45,N46,N47,N48,N49,N50,N51,N52;
reg [1:0] lockIdx,R18;
reg locked;
assign T16 = T17 == 1'b0;
always @(posedge clk) begin
if(N20) begin
lockIdx[1] <= N22;
end
end
always @(posedge clk) begin
if(N20) begin
lockIdx[0] <= N21;
end
end
always @(posedge clk) begin
if(N26) begin
locked <= N27;
end
end
always @(posedge clk) begin
if(N30) begin
R18[1] <= N32;
end
end
always @(posedge clk) begin
if(N30) begin
R18[0] <= N31;
end
end
assign N40 = ~lockIdx[1];
assign N41 = lockIdx[0] | N40;
assign N42 = ~N41;
assign N43 = lockIdx[0] | lockIdx[1];
assign N44 = ~N43;
assign N45 = ~lockIdx[0];
assign N46 = N45 | lockIdx[1];
assign N47 = ~N46;
assign N48 = ~io_out_bits_a_type[1];
assign N49 = ~io_out_bits_a_type[0];
assign N50 = N48 | io_out_bits_a_type[2];
assign N51 = N49 | N50;
assign N52 = ~N51;
assign T17 = R18 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N11;
assign choose = (N2)? { 1'b0, 1'b0 } :
(N3)? T1 : 1'b0;
assign N2 = io_in_0_valid;
assign N3 = N12;
assign T3 = (N4)? { 1'b0, 1'b0 } :
(N5)? T4 : 1'b0;
assign N4 = T6;
assign N5 = N14;
assign io_out_bits_data = (N6)? io_in_2_bits_data :
(N7)? T23 : 1'b0;
assign N6 = io_chosen[1];
assign N7 = N16;
assign T23 = (N8)? io_in_1_bits_data :
(N9)? io_in_0_bits_data : 1'b0;
assign N8 = io_chosen[0];
assign N9 = N17;
assign io_out_bits_union = (N6)? io_in_2_bits_union :
(N7)? T28 : 1'b0;
assign T28 = (N8)? io_in_1_bits_union :
(N9)? io_in_0_bits_union : 1'b0;
assign io_out_bits_a_type = (N6)? io_in_2_bits_a_type :
(N7)? T32 : 1'b0;
assign T32 = (N8)? io_in_1_bits_a_type :
(N9)? io_in_0_bits_a_type : 1'b0;
assign io_out_bits_is_builtin_type = (N6)? io_in_2_bits_is_builtin_type :
(N7)? T36 : 1'b0;
assign T36 = (N8)? io_in_1_bits_is_builtin_type :
(N9)? io_in_0_bits_is_builtin_type : 1'b0;
assign io_out_bits_addr_beat = (N6)? io_in_2_bits_addr_beat :
(N7)? T40 : 1'b0;
assign T40 = (N8)? io_in_1_bits_addr_beat :
(N9)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_bits_client_xact_id = (N6)? io_in_2_bits_client_xact_id :
(N7)? T44 : 1'b0;
assign T44 = (N8)? io_in_1_bits_client_xact_id :
(N9)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N6)? io_in_2_bits_addr_block :
(N7)? T48 : 1'b0;
assign T48 = (N8)? io_in_1_bits_addr_block :
(N9)? io_in_0_bits_addr_block : 1'b0;
assign io_out_valid = (N6)? io_in_2_valid :
(N7)? T52 : 1'b0;
assign T52 = (N8)? io_in_1_valid :
(N9)? io_in_0_valid : 1'b0;
assign T56 = (N0)? N44 :
(N1)? 1'b1 : 1'b0;
assign T59 = (N0)? N47 :
(N1)? T60 : 1'b0;
assign T63 = (N0)? N42 :
(N1)? T64 : 1'b0;
assign N20 = (N10)? 1'b1 :
(N34)? 1'b1 :
(N19)? 1'b0 : 1'b0;
assign N10 = reset;
assign { N22, N21 } = (N10)? { 1'b1, 1'b0 } :
(N34)? T3 : 1'b0;
assign N26 = (N10)? 1'b1 :
(N35)? 1'b1 :
(N38)? 1'b1 :
(N25)? 1'b0 : 1'b0;
assign N27 = (N10)? 1'b0 :
(N35)? 1'b0 :
(N38)? T15 : 1'b0;
assign N30 = (N10)? 1'b1 :
(N39)? 1'b1 :
(N29)? 1'b0 : 1'b0;
assign { N32, N31 } = (N10)? { 1'b0, 1'b0 } :
(N39)? T17 : 1'b0;
assign N11 = ~locked;
assign N12 = ~io_in_0_valid;
assign N13 = ~io_in_1_valid;
assign T1[0] = io_in_1_valid;
assign T1[1] = N13;
assign N14 = ~T6;
assign N15 = ~T5;
assign T4[0] = T5;
assign T4[1] = N15;
assign T5 = io_in_1_ready & io_in_1_valid;
assign T6 = io_in_0_ready & io_in_0_valid;
assign T7 = T9 & T8;
assign T8 = ~locked;
assign T9 = T12 & T10;
assign T10 = io_out_bits_is_builtin_type & N52;
assign T12 = io_out_valid & io_out_ready;
assign T15 = ~T16;
assign T20 = T12 & T21;
assign T21 = ~T10;
assign N16 = ~io_chosen[1];
assign N17 = ~io_chosen[0];
assign io_in_0_ready = T56 & io_out_ready;
assign io_in_1_ready = T59 & io_out_ready;
assign T60 = ~io_in_0_valid;
assign io_in_2_ready = T63 & io_out_ready;
assign T64 = ~T65;
assign T65 = io_in_0_valid | io_in_1_valid;
assign N18 = T7 | reset;
assign N19 = ~N18;
assign N23 = T20 | reset;
assign N24 = T9 | N23;
assign N25 = ~N24;
assign N28 = T9 | reset;
assign N29 = ~N28;
assign N33 = ~reset;
assign N34 = T7 & N33;
assign N35 = T20 & N33;
assign N36 = ~T20;
assign N37 = N33 & N36;
assign N38 = T9 & N37;
assign N39 = T9 & N33;
endmodule |
module FlowThroughSerializer
(
io_in_ready,
io_in_valid,
io_in_bits_addr_beat,
io_in_bits_client_xact_id,
io_in_bits_manager_xact_id,
io_in_bits_is_builtin_type,
io_in_bits_g_type,
io_in_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_client_xact_id,
io_out_bits_manager_xact_id,
io_out_bits_is_builtin_type,
io_out_bits_g_type,
io_out_bits_data,
io_cnt,
io_done
);
input [1:0] io_in_bits_addr_beat;
input [5:0] io_in_bits_client_xact_id;
input [3:0] io_in_bits_manager_xact_id;
input [3:0] io_in_bits_g_type;
input [127:0] io_in_bits_data;
output [1:0] io_out_bits_addr_beat;
output [5:0] io_out_bits_client_xact_id;
output [3:0] io_out_bits_manager_xact_id;
output [3:0] io_out_bits_g_type;
output [127:0] io_out_bits_data;
input io_in_valid;
input io_in_bits_is_builtin_type;
input io_out_ready;
output io_in_ready;
output io_out_valid;
output io_out_bits_is_builtin_type;
output io_cnt;
output io_done;
wire [1:0] io_out_bits_addr_beat;
wire [5:0] io_out_bits_client_xact_id;
wire [3:0] io_out_bits_manager_xact_id,io_out_bits_g_type;
wire [127:0] io_out_bits_data;
wire io_in_ready,io_out_valid,io_out_bits_is_builtin_type,io_cnt,io_done,
io_out_ready,io_in_valid,io_in_bits_is_builtin_type;
assign io_done = 1'b1;
assign io_cnt = 1'b0;
assign io_in_ready = io_out_ready;
assign io_out_valid = io_in_valid;
assign io_out_bits_addr_beat[1] = io_in_bits_addr_beat[1];
assign io_out_bits_addr_beat[0] = io_in_bits_addr_beat[0];
assign io_out_bits_client_xact_id[5] = io_in_bits_client_xact_id[5];
assign io_out_bits_client_xact_id[4] = io_in_bits_client_xact_id[4];
assign io_out_bits_client_xact_id[3] = io_in_bits_client_xact_id[3];
assign io_out_bits_client_xact_id[2] = io_in_bits_client_xact_id[2];
assign io_out_bits_client_xact_id[1] = io_in_bits_client_xact_id[1];
assign io_out_bits_client_xact_id[0] = io_in_bits_client_xact_id[0];
assign io_out_bits_manager_xact_id[3] = io_in_bits_manager_xact_id[3];
assign io_out_bits_manager_xact_id[2] = io_in_bits_manager_xact_id[2];
assign io_out_bits_manager_xact_id[1] = io_in_bits_manager_xact_id[1];
assign io_out_bits_manager_xact_id[0] = io_in_bits_manager_xact_id[0];
assign io_out_bits_is_builtin_type = io_in_bits_is_builtin_type;
assign io_out_bits_g_type[3] = io_in_bits_g_type[3];
assign io_out_bits_g_type[2] = io_in_bits_g_type[2];
assign io_out_bits_g_type[1] = io_in_bits_g_type[1];
assign io_out_bits_g_type[0] = io_in_bits_g_type[0];
assign io_out_bits_data[127] = io_in_bits_data[127];
assign io_out_bits_data[126] = io_in_bits_data[126];
assign io_out_bits_data[125] = io_in_bits_data[125];
assign io_out_bits_data[124] = io_in_bits_data[124];
assign io_out_bits_data[123] = io_in_bits_data[123];
assign io_out_bits_data[122] = io_in_bits_data[122];
assign io_out_bits_data[121] = io_in_bits_data[121];
assign io_out_bits_data[120] = io_in_bits_data[120];
assign io_out_bits_data[119] = io_in_bits_data[119];
assign io_out_bits_data[118] = io_in_bits_data[118];
assign io_out_bits_data[117] = io_in_bits_data[117];
assign io_out_bits_data[116] = io_in_bits_data[116];
assign io_out_bits_data[115] = io_in_bits_data[115];
assign io_out_bits_data[114] = io_in_bits_data[114];
assign io_out_bits_data[113] = io_in_bits_data[113];
assign io_out_bits_data[112] = io_in_bits_data[112];
assign io_out_bits_data[111] = io_in_bits_data[111];
assign io_out_bits_data[110] = io_in_bits_data[110];
assign io_out_bits_data[109] = io_in_bits_data[109];
assign io_out_bits_data[108] = io_in_bits_data[108];
assign io_out_bits_data[107] = io_in_bits_data[107];
assign io_out_bits_data[106] = io_in_bits_data[106];
assign io_out_bits_data[105] = io_in_bits_data[105];
assign io_out_bits_data[104] = io_in_bits_data[104];
assign io_out_bits_data[103] = io_in_bits_data[103];
assign io_out_bits_data[102] = io_in_bits_data[102];
assign io_out_bits_data[101] = io_in_bits_data[101];
assign io_out_bits_data[100] = io_in_bits_data[100];
assign io_out_bits_data[99] = io_in_bits_data[99];
assign io_out_bits_data[98] = io_in_bits_data[98];
assign io_out_bits_data[97] = io_in_bits_data[97];
assign io_out_bits_data[96] = io_in_bits_data[96];
assign io_out_bits_data[95] = io_in_bits_data[95];
assign io_out_bits_data[94] = io_in_bits_data[94];
assign io_out_bits_data[93] = io_in_bits_data[93];
assign io_out_bits_data[92] = io_in_bits_data[92];
assign io_out_bits_data[91] = io_in_bits_data[91];
assign io_out_bits_data[90] = io_in_bits_data[90];
assign io_out_bits_data[89] = io_in_bits_data[89];
assign io_out_bits_data[88] = io_in_bits_data[88];
assign io_out_bits_data[87] = io_in_bits_data[87];
assign io_out_bits_data[86] = io_in_bits_data[86];
assign io_out_bits_data[85] = io_in_bits_data[85];
assign io_out_bits_data[84] = io_in_bits_data[84];
assign io_out_bits_data[83] = io_in_bits_data[83];
assign io_out_bits_data[82] = io_in_bits_data[82];
assign io_out_bits_data[81] = io_in_bits_data[81];
assign io_out_bits_data[80] = io_in_bits_data[80];
assign io_out_bits_data[79] = io_in_bits_data[79];
assign io_out_bits_data[78] = io_in_bits_data[78];
assign io_out_bits_data[77] = io_in_bits_data[77];
assign io_out_bits_data[76] = io_in_bits_data[76];
assign io_out_bits_data[75] = io_in_bits_data[75];
assign io_out_bits_data[74] = io_in_bits_data[74];
assign io_out_bits_data[73] = io_in_bits_data[73];
assign io_out_bits_data[72] = io_in_bits_data[72];
assign io_out_bits_data[71] = io_in_bits_data[71];
assign io_out_bits_data[70] = io_in_bits_data[70];
assign io_out_bits_data[69] = io_in_bits_data[69];
assign io_out_bits_data[68] = io_in_bits_data[68];
assign io_out_bits_data[67] = io_in_bits_data[67];
assign io_out_bits_data[66] = io_in_bits_data[66];
assign io_out_bits_data[65] = io_in_bits_data[65];
assign io_out_bits_data[64] = io_in_bits_data[64];
assign io_out_bits_data[63] = io_in_bits_data[63];
assign io_out_bits_data[62] = io_in_bits_data[62];
assign io_out_bits_data[61] = io_in_bits_data[61];
assign io_out_bits_data[60] = io_in_bits_data[60];
assign io_out_bits_data[59] = io_in_bits_data[59];
assign io_out_bits_data[58] = io_in_bits_data[58];
assign io_out_bits_data[57] = io_in_bits_data[57];
assign io_out_bits_data[56] = io_in_bits_data[56];
assign io_out_bits_data[55] = io_in_bits_data[55];
assign io_out_bits_data[54] = io_in_bits_data[54];
assign io_out_bits_data[53] = io_in_bits_data[53];
assign io_out_bits_data[52] = io_in_bits_data[52];
assign io_out_bits_data[51] = io_in_bits_data[51];
assign io_out_bits_data[50] = io_in_bits_data[50];
assign io_out_bits_data[49] = io_in_bits_data[49];
assign io_out_bits_data[48] = io_in_bits_data[48];
assign io_out_bits_data[47] = io_in_bits_data[47];
assign io_out_bits_data[46] = io_in_bits_data[46];
assign io_out_bits_data[45] = io_in_bits_data[45];
assign io_out_bits_data[44] = io_in_bits_data[44];
assign io_out_bits_data[43] = io_in_bits_data[43];
assign io_out_bits_data[42] = io_in_bits_data[42];
assign io_out_bits_data[41] = io_in_bits_data[41];
assign io_out_bits_data[40] = io_in_bits_data[40];
assign io_out_bits_data[39] = io_in_bits_data[39];
assign io_out_bits_data[38] = io_in_bits_data[38];
assign io_out_bits_data[37] = io_in_bits_data[37];
assign io_out_bits_data[36] = io_in_bits_data[36];
assign io_out_bits_data[35] = io_in_bits_data[35];
assign io_out_bits_data[34] = io_in_bits_data[34];
assign io_out_bits_data[33] = io_in_bits_data[33];
assign io_out_bits_data[32] = io_in_bits_data[32];
assign io_out_bits_data[31] = io_in_bits_data[31];
assign io_out_bits_data[30] = io_in_bits_data[30];
assign io_out_bits_data[29] = io_in_bits_data[29];
assign io_out_bits_data[28] = io_in_bits_data[28];
assign io_out_bits_data[27] = io_in_bits_data[27];
assign io_out_bits_data[26] = io_in_bits_data[26];
assign io_out_bits_data[25] = io_in_bits_data[25];
assign io_out_bits_data[24] = io_in_bits_data[24];
assign io_out_bits_data[23] = io_in_bits_data[23];
assign io_out_bits_data[22] = io_in_bits_data[22];
assign io_out_bits_data[21] = io_in_bits_data[21];
assign io_out_bits_data[20] = io_in_bits_data[20];
assign io_out_bits_data[19] = io_in_bits_data[19];
assign io_out_bits_data[18] = io_in_bits_data[18];
assign io_out_bits_data[17] = io_in_bits_data[17];
assign io_out_bits_data[16] = io_in_bits_data[16];
assign io_out_bits_data[15] = io_in_bits_data[15];
assign io_out_bits_data[14] = io_in_bits_data[14];
assign io_out_bits_data[13] = io_in_bits_data[13];
assign io_out_bits_data[12] = io_in_bits_data[12];
assign io_out_bits_data[11] = io_in_bits_data[11];
assign io_out_bits_data[10] = io_in_bits_data[10];
assign io_out_bits_data[9] = io_in_bits_data[9];
assign io_out_bits_data[8] = io_in_bits_data[8];
assign io_out_bits_data[7] = io_in_bits_data[7];
assign io_out_bits_data[6] = io_in_bits_data[6];
assign io_out_bits_data[5] = io_in_bits_data[5];
assign io_out_bits_data[4] = io_in_bits_data[4];
assign io_out_bits_data[3] = io_in_bits_data[3];
assign io_out_bits_data[2] = io_in_bits_data[2];
assign io_out_bits_data[1] = io_in_bits_data[1];
assign io_out_bits_data[0] = io_in_bits_data[0];
endmodule |
module LockingRRArbiter_5
(
clk,
reset,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_header_src,
io_in_4_bits_header_dst,
io_in_4_bits_payload_addr_block,
io_in_4_bits_payload_client_xact_id,
io_in_4_bits_payload_addr_beat,
io_in_4_bits_payload_is_builtin_type,
io_in_4_bits_payload_a_type,
io_in_4_bits_payload_union,
io_in_4_bits_payload_data,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_header_src,
io_in_3_bits_header_dst,
io_in_3_bits_payload_addr_block,
io_in_3_bits_payload_client_xact_id,
io_in_3_bits_payload_addr_beat,
io_in_3_bits_payload_is_builtin_type,
io_in_3_bits_payload_a_type,
io_in_3_bits_payload_union,
io_in_3_bits_payload_data,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_header_src,
io_in_2_bits_header_dst,
io_in_2_bits_payload_addr_block,
io_in_2_bits_payload_client_xact_id,
io_in_2_bits_payload_addr_beat,
io_in_2_bits_payload_is_builtin_type,
io_in_2_bits_payload_a_type,
io_in_2_bits_payload_union,
io_in_2_bits_payload_data,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_header_src,
io_in_1_bits_header_dst,
io_in_1_bits_payload_addr_block,
io_in_1_bits_payload_client_xact_id,
io_in_1_bits_payload_addr_beat,
io_in_1_bits_payload_is_builtin_type,
io_in_1_bits_payload_a_type,
io_in_1_bits_payload_union,
io_in_1_bits_payload_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_header_src,
io_in_0_bits_header_dst,
io_in_0_bits_payload_addr_block,
io_in_0_bits_payload_client_xact_id,
io_in_0_bits_payload_addr_beat,
io_in_0_bits_payload_is_builtin_type,
io_in_0_bits_payload_a_type,
io_in_0_bits_payload_union,
io_in_0_bits_payload_data,
io_out_ready,
io_out_valid,
io_out_bits_header_src,
io_out_bits_header_dst,
io_out_bits_payload_addr_block,
io_out_bits_payload_client_xact_id,
io_out_bits_payload_addr_beat,
io_out_bits_payload_is_builtin_type,
io_out_bits_payload_a_type,
io_out_bits_payload_union,
io_out_bits_payload_data,
io_chosen
);
input [2:0] io_in_4_bits_header_src;
input [2:0] io_in_4_bits_header_dst;
input [25:0] io_in_4_bits_payload_addr_block;
input [5:0] io_in_4_bits_payload_client_xact_id;
input [1:0] io_in_4_bits_payload_addr_beat;
input [2:0] io_in_4_bits_payload_a_type;
input [16:0] io_in_4_bits_payload_union;
input [127:0] io_in_4_bits_payload_data;
input [2:0] io_in_3_bits_header_src;
input [2:0] io_in_3_bits_header_dst;
input [25:0] io_in_3_bits_payload_addr_block;
input [5:0] io_in_3_bits_payload_client_xact_id;
input [1:0] io_in_3_bits_payload_addr_beat;
input [2:0] io_in_3_bits_payload_a_type;
input [16:0] io_in_3_bits_payload_union;
input [127:0] io_in_3_bits_payload_data;
input [2:0] io_in_2_bits_header_src;
input [2:0] io_in_2_bits_header_dst;
input [25:0] io_in_2_bits_payload_addr_block;
input [5:0] io_in_2_bits_payload_client_xact_id;
input [1:0] io_in_2_bits_payload_addr_beat;
input [2:0] io_in_2_bits_payload_a_type;
input [16:0] io_in_2_bits_payload_union;
input [127:0] io_in_2_bits_payload_data;
input [2:0] io_in_1_bits_header_src;
input [2:0] io_in_1_bits_header_dst;
input [25:0] io_in_1_bits_payload_addr_block;
input [5:0] io_in_1_bits_payload_client_xact_id;
input [1:0] io_in_1_bits_payload_addr_beat;
input [2:0] io_in_1_bits_payload_a_type;
input [16:0] io_in_1_bits_payload_union;
input [127:0] io_in_1_bits_payload_data;
input [2:0] io_in_0_bits_header_src;
input [2:0] io_in_0_bits_header_dst;
input [25:0] io_in_0_bits_payload_addr_block;
input [5:0] io_in_0_bits_payload_client_xact_id;
input [1:0] io_in_0_bits_payload_addr_beat;
input [2:0] io_in_0_bits_payload_a_type;
input [16:0] io_in_0_bits_payload_union;
input [127:0] io_in_0_bits_payload_data;
output [2:0] io_out_bits_header_src;
output [2:0] io_out_bits_header_dst;
output [25:0] io_out_bits_payload_addr_block;
output [5:0] io_out_bits_payload_client_xact_id;
output [1:0] io_out_bits_payload_addr_beat;
output [2:0] io_out_bits_payload_a_type;
output [16:0] io_out_bits_payload_union;
output [127:0] io_out_bits_payload_data;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_4_valid;
input io_in_4_bits_payload_is_builtin_type;
input io_in_3_valid;
input io_in_3_bits_payload_is_builtin_type;
input io_in_2_valid;
input io_in_2_bits_payload_is_builtin_type;
input io_in_1_valid;
input io_in_1_bits_payload_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_payload_is_builtin_type;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_payload_is_builtin_type;
wire [2:0] io_out_bits_header_src,io_out_bits_header_dst,io_out_bits_payload_a_type,
io_chosen,choose,T1,T2,T3,T4,T5,T6,T19,T20,T21,T60,T63,T61,T100,T103,T101,T108,T111,
T109;
wire [25:0] io_out_bits_payload_addr_block,T92,T95,T93;
wire [5:0] io_out_bits_payload_client_xact_id,T84,T87,T85;
wire [1:0] io_out_bits_payload_addr_beat,T37,T76,T79,T77;
wire [16:0] io_out_bits_payload_union,T52,T55,T53;
wire [127:0] io_out_bits_payload_data,T43,T47,T44;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,io_out_bits_payload_is_builtin_type,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,T16,N30,
T14,N31,T12,N32,T8,N33,N34,N35,N36,N37,T9,T11,T13,T15,T17,T27,T26,N38,T25,N39,T24,
N40,T23,N41,T29,T28,T32,T30,T40,T35,T36,T41,N42,N43,N44,T68,T71,T69,T116,T119,
T117,T124,T125,T141,T126,T127,T130,T128,T129,T133,T131,T132,T136,T134,T135,T139,
T137,T138,T140,T144,T145,T152,T146,T147,T148,T149,T150,T151,T154,T153,T157,T158,
T166,T159,T160,T161,T162,T163,T164,T165,T168,T167,T169,T172,T173,T182,T174,T175,
T176,T177,T178,T179,T180,T181,T184,T183,T185,T186,T189,T190,T200,T191,T192,T193,
T194,T195,T196,T197,T198,T199,T202,T201,T203,T204,T205,N45,N46,N47,N48,N49,N50,N51,
N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,
N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,
N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106;
wire [2:1] T7,T22;
reg [2:0] last_grant,lockIdx;
reg locked;
reg [1:0] R38;
assign T13 = last_grant < { 1'b1, 1'b1 };
assign T36 = T37 == 1'b0;
assign T132 = last_grant < { 1'b1, 1'b1 };
assign T140 = last_grant < 1'b0;
assign T141 = last_grant < 1'b0;
assign T183 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N47) begin
last_grant[2] <= N50;
end
end
always @(posedge clk) begin
if(N47) begin
last_grant[1] <= N49;
end
end
always @(posedge clk) begin
if(N47) begin
last_grant[0] <= N48;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[2] <= N56;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[1] <= N55;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[0] <= N54;
end
end
always @(posedge clk) begin
if(N60) begin
locked <= N61;
end
end
always @(posedge clk) begin
if(N64) begin
R38[1] <= N66;
end
end
always @(posedge clk) begin
if(N64) begin
R38[0] <= N65;
end
end
assign N75 = ~lockIdx[2];
assign N76 = lockIdx[1] | N75;
assign N77 = lockIdx[0] | N76;
assign N78 = ~N77;
assign N79 = lockIdx[1] | lockIdx[2];
assign N80 = lockIdx[0] | N79;
assign N81 = ~N80;
assign N82 = ~lockIdx[0];
assign N83 = lockIdx[1] | lockIdx[2];
assign N84 = N82 | N83;
assign N85 = ~N84;
assign N86 = ~io_out_bits_payload_a_type[1];
assign N87 = ~io_out_bits_payload_a_type[0];
assign N88 = N86 | io_out_bits_payload_a_type[2];
assign N89 = N87 | N88;
assign N90 = ~N89;
assign N91 = ~lockIdx[1];
assign N92 = N91 | lockIdx[2];
assign N93 = lockIdx[0] | N92;
assign N94 = ~N93;
assign N95 = N91 | lockIdx[2];
assign N96 = N82 | N95;
assign N97 = ~N96;
assign T37 = R38 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N29;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T16;
assign N3 = N30;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T14;
assign N5 = N31;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T12;
assign N7 = N32;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T8;
assign N9 = N33;
assign T4 = (N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? T5 : 1'b0;
assign N10 = io_in_0_valid;
assign N11 = N34;
assign T5 = (N12)? { 1'b0, 1'b0, 1'b1 } :
(N13)? T6 : 1'b0;
assign N12 = io_in_1_valid;
assign N13 = N35;
assign T6 = (N14)? { 1'b0, 1'b1, 1'b0 } :
(N15)? { T7, T7[1:1] } : 1'b0;
assign N14 = io_in_2_valid;
assign N15 = N36;
assign T19 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T20 : 1'b0;
assign N16 = T26;
assign N17 = N38;
assign T20 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T21 : 1'b0;
assign N18 = T25;
assign N19 = N39;
assign T21 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? { T22, T22[1:1] } : 1'b0;
assign N20 = T24;
assign N21 = N40;
assign io_out_bits_payload_data = (N22)? io_in_4_bits_payload_data :
(N23)? T43 : 1'b0;
assign N22 = io_chosen[2];
assign N23 = N42;
assign T43 = (N24)? T47 :
(N25)? T44 : 1'b0;
assign N24 = io_chosen[1];
assign N25 = N43;
assign T44 = (N26)? io_in_1_bits_payload_data :
(N27)? io_in_0_bits_payload_data : 1'b0;
assign N26 = io_chosen[0];
assign N27 = N44;
assign T47 = (N26)? io_in_3_bits_payload_data :
(N27)? io_in_2_bits_payload_data : 1'b0;
assign io_out_bits_payload_union = (N22)? io_in_4_bits_payload_union :
(N23)? T52 : 1'b0;
assign T52 = (N24)? T55 :
(N25)? T53 : 1'b0;
assign T53 = (N26)? io_in_1_bits_payload_union :
(N27)? io_in_0_bits_payload_union : 1'b0;
assign T55 = (N26)? io_in_3_bits_payload_union :
(N27)? io_in_2_bits_payload_union : 1'b0;
assign io_out_bits_payload_a_type = (N22)? io_in_4_bits_payload_a_type :
(N23)? T60 : 1'b0;
assign T60 = (N24)? T63 :
(N25)? T61 : 1'b0;
assign T61 = (N26)? io_in_1_bits_payload_a_type :
(N27)? io_in_0_bits_payload_a_type : 1'b0;
assign T63 = (N26)? io_in_3_bits_payload_a_type :
(N27)? io_in_2_bits_payload_a_type : 1'b0;
assign io_out_bits_payload_is_builtin_type = (N22)? io_in_4_bits_payload_is_builtin_type :
(N23)? T68 : 1'b0;
assign T68 = (N24)? T71 :
(N25)? T69 : 1'b0;
assign T69 = (N26)? io_in_1_bits_payload_is_builtin_type :
(N27)? io_in_0_bits_payload_is_builtin_type : 1'b0;
assign T71 = (N26)? io_in_3_bits_payload_is_builtin_type :
(N27)? io_in_2_bits_payload_is_builtin_type : 1'b0;
assign io_out_bits_payload_addr_beat = (N22)? io_in_4_bits_payload_addr_beat :
(N23)? T76 : 1'b0;
assign T76 = (N24)? T79 :
(N25)? T77 : 1'b0;
assign T77 = (N26)? io_in_1_bits_payload_addr_beat :
(N27)? io_in_0_bits_payload_addr_beat : 1'b0;
assign T79 = (N26)? io_in_3_bits_payload_addr_beat :
(N27)? io_in_2_bits_payload_addr_beat : 1'b0;
assign io_out_bits_payload_client_xact_id = (N22)? io_in_4_bits_payload_client_xact_id :
(N23)? T84 : 1'b0;
assign T84 = (N24)? T87 :
(N25)? T85 : 1'b0;
assign T85 = (N26)? io_in_1_bits_payload_client_xact_id :
(N27)? io_in_0_bits_payload_client_xact_id : 1'b0;
assign T87 = (N26)? io_in_3_bits_payload_client_xact_id :
(N27)? io_in_2_bits_payload_client_xact_id : 1'b0;
assign io_out_bits_payload_addr_block = (N22)? io_in_4_bits_payload_addr_block :
(N23)? T92 : 1'b0;
assign T92 = (N24)? T95 :
(N25)? T93 : 1'b0;
assign T93 = (N26)? io_in_1_bits_payload_addr_block :
(N27)? io_in_0_bits_payload_addr_block : 1'b0;
assign T95 = (N26)? io_in_3_bits_payload_addr_block :
(N27)? io_in_2_bits_payload_addr_block : 1'b0;
assign io_out_bits_header_dst = (N22)? io_in_4_bits_header_dst :
(N23)? T100 : 1'b0;
assign T100 = (N24)? T103 :
(N25)? T101 : 1'b0;
assign T101 = (N26)? io_in_1_bits_header_dst :
(N27)? io_in_0_bits_header_dst : 1'b0;
assign T103 = (N26)? io_in_3_bits_header_dst :
(N27)? io_in_2_bits_header_dst : 1'b0;
assign io_out_bits_header_src = (N22)? io_in_4_bits_header_src :
(N23)? T108 : 1'b0;
assign T108 = (N24)? T111 :
(N25)? T109 : 1'b0;
assign T109 = (N26)? io_in_1_bits_header_src :
(N27)? io_in_0_bits_header_src : 1'b0;
assign T111 = (N26)? io_in_3_bits_header_src :
(N27)? io_in_2_bits_header_src : 1'b0;
assign io_out_valid = (N22)? io_in_4_valid :
(N23)? T116 : 1'b0;
assign T116 = (N24)? T119 :
(N25)? T117 : 1'b0;
assign T117 = (N26)? io_in_1_valid :
(N27)? io_in_0_valid : 1'b0;
assign T119 = (N26)? io_in_3_valid :
(N27)? io_in_2_valid : 1'b0;
assign T124 = (N0)? N81 :
(N1)? T125 : 1'b0;
assign T144 = (N0)? N85 :
(N1)? T145 : 1'b0;
assign T157 = (N0)? N94 :
(N1)? T158 : 1'b0;
assign T172 = (N0)? N97 :
(N1)? T173 : 1'b0;
assign T189 = (N0)? N78 :
(N1)? T190 : 1'b0;
assign N47 = (N28)? 1'b1 :
(N68)? 1'b1 :
(N46)? 1'b0 : 1'b0;
assign N28 = reset;
assign { N50, N49, N48 } = (N28)? { 1'b0, 1'b0, 1'b0 } :
(N68)? io_chosen : 1'b0;
assign N53 = (N28)? 1'b1 :
(N69)? 1'b1 :
(N52)? 1'b0 : 1'b0;
assign { N56, N55, N54 } = (N28)? { 1'b1, 1'b0, 1'b0 } :
(N69)? T19 : 1'b0;
assign N60 = (N28)? 1'b1 :
(N70)? 1'b1 :
(N73)? 1'b1 :
(N59)? 1'b0 : 1'b0;
assign N61 = (N28)? 1'b0 :
(N70)? 1'b0 :
(N73)? T35 : 1'b0;
assign N64 = (N28)? 1'b1 :
(N74)? 1'b1 :
(N63)? 1'b0 : 1'b0;
assign { N66, N65 } = (N28)? { 1'b0, 1'b0 } :
(N74)? T37 : 1'b0;
assign N29 = ~locked;
assign N30 = ~T16;
assign N31 = ~T14;
assign N32 = ~T12;
assign N33 = ~T8;
assign N34 = ~io_in_0_valid;
assign N35 = ~io_in_1_valid;
assign N36 = ~io_in_2_valid;
assign N37 = ~io_in_3_valid;
assign T7[1] = io_in_3_valid;
assign T7[2] = N37;
assign T8 = io_in_4_valid & T9;
assign T9 = ~last_grant[2];
assign T11 = io_out_ready & io_out_valid;
assign T12 = io_in_3_valid & T13;
assign T14 = io_in_2_valid & T15;
assign T15 = ~N98;
assign N98 = last_grant[2] | last_grant[1];
assign T16 = io_in_1_valid & T17;
assign T17 = ~N100;
assign N100 = N99 | last_grant[0];
assign N99 = last_grant[2] | last_grant[1];
assign N38 = ~T26;
assign N39 = ~T25;
assign N40 = ~T24;
assign N41 = ~T23;
assign T22[1] = T23;
assign T22[2] = N41;
assign T23 = io_in_3_ready & io_in_3_valid;
assign T24 = io_in_2_ready & io_in_2_valid;
assign T25 = io_in_1_ready & io_in_1_valid;
assign T26 = io_in_0_ready & io_in_0_valid;
assign T27 = T29 & T28;
assign T28 = ~locked;
assign T29 = T32 & T30;
assign T30 = io_out_bits_payload_is_builtin_type & N90;
assign T32 = io_out_valid & io_out_ready;
assign T35 = ~T36;
assign T40 = T32 & T41;
assign T41 = ~T30;
assign N42 = ~io_chosen[2];
assign N43 = ~io_chosen[1];
assign N44 = ~io_chosen[0];
assign io_in_0_ready = T124 & io_out_ready;
assign T125 = T141 | T126;
assign T126 = ~T127;
assign T127 = T130 | T128;
assign T128 = io_in_4_valid & T129;
assign T129 = ~last_grant[2];
assign T130 = T133 | T131;
assign T131 = io_in_3_valid & T132;
assign T133 = T136 | T134;
assign T134 = io_in_2_valid & T135;
assign T135 = ~N101;
assign N101 = last_grant[2] | last_grant[1];
assign T136 = T139 | T137;
assign T137 = io_in_1_valid & T138;
assign T138 = ~N103;
assign N103 = N102 | last_grant[0];
assign N102 = last_grant[2] | last_grant[1];
assign T139 = io_in_0_valid & T140;
assign io_in_1_ready = T144 & io_out_ready;
assign T145 = T152 | T146;
assign T146 = ~T147;
assign T147 = T148 | io_in_0_valid;
assign T148 = T149 | T128;
assign T149 = T150 | T131;
assign T150 = T151 | T134;
assign T151 = T139 | T137;
assign T152 = T154 & T153;
assign T153 = ~N105;
assign N105 = N104 | last_grant[0];
assign N104 = last_grant[2] | last_grant[1];
assign T154 = ~T139;
assign io_in_2_ready = T157 & io_out_ready;
assign T158 = T166 | T159;
assign T159 = ~T160;
assign T160 = T161 | io_in_1_valid;
assign T161 = T162 | io_in_0_valid;
assign T162 = T163 | T128;
assign T163 = T164 | T131;
assign T164 = T165 | T134;
assign T165 = T139 | T137;
assign T166 = T168 & T167;
assign T167 = ~N106;
assign N106 = last_grant[2] | last_grant[1];
assign T168 = ~T169;
assign T169 = T139 | T137;
assign io_in_3_ready = T172 & io_out_ready;
assign T173 = T182 | T174;
assign T174 = ~T175;
assign T175 = T176 | io_in_2_valid;
assign T176 = T177 | io_in_1_valid;
assign T177 = T178 | io_in_0_valid;
assign T178 = T179 | T128;
assign T179 = T180 | T131;
assign T180 = T181 | T134;
assign T181 = T139 | T137;
assign T182 = T184 & T183;
assign T184 = ~T185;
assign T185 = T186 | T134;
assign T186 = T139 | T137;
assign io_in_4_ready = T189 & io_out_ready;
assign T190 = T200 | T191;
assign T191 = ~T192;
assign T192 = T193 | io_in_3_valid;
assign T193 = T194 | io_in_2_valid;
assign T194 = T195 | io_in_1_valid;
assign T195 = T196 | io_in_0_valid;
assign T196 = T197 | T128;
assign T197 = T198 | T131;
assign T198 = T199 | T134;
assign T199 = T139 | T137;
assign T200 = T202 & T201;
assign T201 = ~last_grant[2];
assign T202 = ~T203;
assign T203 = T204 | T131;
assign T204 = T205 | T134;
assign T205 = T139 | T137;
assign N45 = T11 | reset;
assign N46 = ~N45;
assign N51 = T27 | reset;
assign N52 = ~N51;
assign N57 = T40 | reset;
assign N58 = T29 | N57;
assign N59 = ~N58;
assign N62 = T29 | reset;
assign N63 = ~N62;
assign N67 = ~reset;
assign N68 = T11 & N67;
assign N69 = T27 & N67;
assign N70 = T40 & N67;
assign N71 = ~T40;
assign N72 = N67 & N71;
assign N73 = T29 & N72;
assign N74 = T29 & N67;
endmodule |
module ProbeUnit
(
clk,
reset,
io_req_ready,
io_req_valid,
io_req_bits_addr_block,
io_req_bits_p_type,
io_rep_ready,
io_rep_valid,
io_rep_bits_addr_beat,
io_rep_bits_addr_block,
io_rep_bits_client_xact_id,
io_rep_bits_voluntary,
io_rep_bits_r_type,
io_rep_bits_data,
io_meta_read_ready,
io_meta_read_valid,
io_meta_read_bits_idx,
io_meta_read_bits_tag,
io_meta_write_ready,
io_meta_write_valid,
io_meta_write_bits_idx,
io_meta_write_bits_way_en,
io_meta_write_bits_data_tag,
io_meta_write_bits_data_coh_state,
io_wb_req_ready,
io_wb_req_valid,
io_wb_req_bits_addr_beat,
io_wb_req_bits_addr_block,
io_wb_req_bits_client_xact_id,
io_wb_req_bits_voluntary,
io_wb_req_bits_r_type,
io_wb_req_bits_data,
io_wb_req_bits_way_en,
io_way_en,
io_mshr_rdy,
io_block_state_state
);
input [25:0] io_req_bits_addr_block;
input [1:0] io_req_bits_p_type;
output [1:0] io_rep_bits_addr_beat;
output [25:0] io_rep_bits_addr_block;
output [5:0] io_rep_bits_client_xact_id;
output [2:0] io_rep_bits_r_type;
output [127:0] io_rep_bits_data;
output [5:0] io_meta_read_bits_idx;
output [19:0] io_meta_read_bits_tag;
output [5:0] io_meta_write_bits_idx;
output [3:0] io_meta_write_bits_way_en;
output [19:0] io_meta_write_bits_data_tag;
output [1:0] io_meta_write_bits_data_coh_state;
output [1:0] io_wb_req_bits_addr_beat;
output [25:0] io_wb_req_bits_addr_block;
output [5:0] io_wb_req_bits_client_xact_id;
output [2:0] io_wb_req_bits_r_type;
output [127:0] io_wb_req_bits_data;
output [3:0] io_wb_req_bits_way_en;
input [3:0] io_way_en;
input [1:0] io_block_state_state;
input clk;
input reset;
input io_req_valid;
input io_rep_ready;
input io_meta_read_ready;
input io_meta_write_ready;
input io_wb_req_ready;
input io_mshr_rdy;
output io_req_ready;
output io_rep_valid;
output io_rep_bits_voluntary;
output io_meta_read_valid;
output io_meta_write_valid;
output io_wb_req_valid;
output io_wb_req_bits_voluntary;
wire [1:0] io_rep_bits_addr_beat,io_meta_write_bits_data_coh_state,
io_wb_req_bits_addr_beat,T27,T44,T57;
wire [25:0] io_rep_bits_addr_block;
wire [5:0] io_rep_bits_client_xact_id,io_meta_read_bits_idx,io_meta_write_bits_idx,
io_wb_req_bits_client_xact_id;
wire [2:0] io_rep_bits_r_type,io_wb_req_bits_r_type,T40,T41;
wire [127:0] io_rep_bits_data,io_wb_req_bits_data;
wire [19:0] io_meta_read_bits_tag,io_meta_write_bits_data_tag;
wire [3:0] io_meta_write_bits_way_en;
wire io_req_ready,io_rep_valid,io_rep_bits_voluntary,io_meta_read_valid,
io_meta_write_valid,io_wb_req_valid,io_wb_req_bits_voluntary,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,
N10,N11,N12,T38,T36,T35,T33,T25,T23,T22,T26,T28,N13,N14,T47_0,N15,N16,N17,N18,N19,
N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,
N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,
N60,N61,N62,N63,N64,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N85,N86,N87,N88,N89,N90,N91,N92,N93,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N114,N115,N116,N117,N118,
N119,N120,N121;
wire [3:3] T32;
wire [1:1] T50;
wire [2:2] T47;
wire [2:1] T42;
reg [3:0] io_wb_req_bits_way_en,state;
reg [1:0] T58,req_p_type;
reg [25:0] io_wb_req_bits_addr_block;
assign io_rep_bits_addr_beat[0] = 1'b0;
assign io_rep_bits_addr_beat[1] = 1'b0;
assign io_rep_bits_client_xact_id[0] = 1'b0;
assign io_rep_bits_client_xact_id[1] = 1'b0;
assign io_rep_bits_client_xact_id[2] = 1'b0;
assign io_rep_bits_client_xact_id[3] = 1'b0;
assign io_rep_bits_client_xact_id[4] = 1'b0;
assign io_rep_bits_client_xact_id[5] = 1'b0;
assign io_rep_bits_voluntary = 1'b0;
assign io_rep_bits_data[0] = 1'b0;
assign io_rep_bits_data[1] = 1'b0;
assign io_rep_bits_data[2] = 1'b0;
assign io_rep_bits_data[3] = 1'b0;
assign io_rep_bits_data[4] = 1'b0;
assign io_rep_bits_data[5] = 1'b0;
assign io_rep_bits_data[6] = 1'b0;
assign io_rep_bits_data[7] = 1'b0;
assign io_rep_bits_data[8] = 1'b0;
assign io_rep_bits_data[9] = 1'b0;
assign io_rep_bits_data[10] = 1'b0;
assign io_rep_bits_data[11] = 1'b0;
assign io_rep_bits_data[12] = 1'b0;
assign io_rep_bits_data[13] = 1'b0;
assign io_rep_bits_data[14] = 1'b0;
assign io_rep_bits_data[15] = 1'b0;
assign io_rep_bits_data[16] = 1'b0;
assign io_rep_bits_data[17] = 1'b0;
assign io_rep_bits_data[18] = 1'b0;
assign io_rep_bits_data[19] = 1'b0;
assign io_rep_bits_data[20] = 1'b0;
assign io_rep_bits_data[21] = 1'b0;
assign io_rep_bits_data[22] = 1'b0;
assign io_rep_bits_data[23] = 1'b0;
assign io_rep_bits_data[24] = 1'b0;
assign io_rep_bits_data[25] = 1'b0;
assign io_rep_bits_data[26] = 1'b0;
assign io_rep_bits_data[27] = 1'b0;
assign io_rep_bits_data[28] = 1'b0;
assign io_rep_bits_data[29] = 1'b0;
assign io_rep_bits_data[30] = 1'b0;
assign io_rep_bits_data[31] = 1'b0;
assign io_rep_bits_data[32] = 1'b0;
assign io_rep_bits_data[33] = 1'b0;
assign io_rep_bits_data[34] = 1'b0;
assign io_rep_bits_data[35] = 1'b0;
assign io_rep_bits_data[36] = 1'b0;
assign io_rep_bits_data[37] = 1'b0;
assign io_rep_bits_data[38] = 1'b0;
assign io_rep_bits_data[39] = 1'b0;
assign io_rep_bits_data[40] = 1'b0;
assign io_rep_bits_data[41] = 1'b0;
assign io_rep_bits_data[42] = 1'b0;
assign io_rep_bits_data[43] = 1'b0;
assign io_rep_bits_data[44] = 1'b0;
assign io_rep_bits_data[45] = 1'b0;
assign io_rep_bits_data[46] = 1'b0;
assign io_rep_bits_data[47] = 1'b0;
assign io_rep_bits_data[48] = 1'b0;
assign io_rep_bits_data[49] = 1'b0;
assign io_rep_bits_data[50] = 1'b0;
assign io_rep_bits_data[51] = 1'b0;
assign io_rep_bits_data[52] = 1'b0;
assign io_rep_bits_data[53] = 1'b0;
assign io_rep_bits_data[54] = 1'b0;
assign io_rep_bits_data[55] = 1'b0;
assign io_rep_bits_data[56] = 1'b0;
assign io_rep_bits_data[57] = 1'b0;
assign io_rep_bits_data[58] = 1'b0;
assign io_rep_bits_data[59] = 1'b0;
assign io_rep_bits_data[60] = 1'b0;
assign io_rep_bits_data[61] = 1'b0;
assign io_rep_bits_data[62] = 1'b0;
assign io_rep_bits_data[63] = 1'b0;
assign io_rep_bits_data[64] = 1'b0;
assign io_rep_bits_data[65] = 1'b0;
assign io_rep_bits_data[66] = 1'b0;
assign io_rep_bits_data[67] = 1'b0;
assign io_rep_bits_data[68] = 1'b0;
assign io_rep_bits_data[69] = 1'b0;
assign io_rep_bits_data[70] = 1'b0;
assign io_rep_bits_data[71] = 1'b0;
assign io_rep_bits_data[72] = 1'b0;
assign io_rep_bits_data[73] = 1'b0;
assign io_rep_bits_data[74] = 1'b0;
assign io_rep_bits_data[75] = 1'b0;
assign io_rep_bits_data[76] = 1'b0;
assign io_rep_bits_data[77] = 1'b0;
assign io_rep_bits_data[78] = 1'b0;
assign io_rep_bits_data[79] = 1'b0;
assign io_rep_bits_data[80] = 1'b0;
assign io_rep_bits_data[81] = 1'b0;
assign io_rep_bits_data[82] = 1'b0;
assign io_rep_bits_data[83] = 1'b0;
assign io_rep_bits_data[84] = 1'b0;
assign io_rep_bits_data[85] = 1'b0;
assign io_rep_bits_data[86] = 1'b0;
assign io_rep_bits_data[87] = 1'b0;
assign io_rep_bits_data[88] = 1'b0;
assign io_rep_bits_data[89] = 1'b0;
assign io_rep_bits_data[90] = 1'b0;
assign io_rep_bits_data[91] = 1'b0;
assign io_rep_bits_data[92] = 1'b0;
assign io_rep_bits_data[93] = 1'b0;
assign io_rep_bits_data[94] = 1'b0;
assign io_rep_bits_data[95] = 1'b0;
assign io_rep_bits_data[96] = 1'b0;
assign io_rep_bits_data[97] = 1'b0;
assign io_rep_bits_data[98] = 1'b0;
assign io_rep_bits_data[99] = 1'b0;
assign io_rep_bits_data[100] = 1'b0;
assign io_rep_bits_data[101] = 1'b0;
assign io_rep_bits_data[102] = 1'b0;
assign io_rep_bits_data[103] = 1'b0;
assign io_rep_bits_data[104] = 1'b0;
assign io_rep_bits_data[105] = 1'b0;
assign io_rep_bits_data[106] = 1'b0;
assign io_rep_bits_data[107] = 1'b0;
assign io_rep_bits_data[108] = 1'b0;
assign io_rep_bits_data[109] = 1'b0;
assign io_rep_bits_data[110] = 1'b0;
assign io_rep_bits_data[111] = 1'b0;
assign io_rep_bits_data[112] = 1'b0;
assign io_rep_bits_data[113] = 1'b0;
assign io_rep_bits_data[114] = 1'b0;
assign io_rep_bits_data[115] = 1'b0;
assign io_rep_bits_data[116] = 1'b0;
assign io_rep_bits_data[117] = 1'b0;
assign io_rep_bits_data[118] = 1'b0;
assign io_rep_bits_data[119] = 1'b0;
assign io_rep_bits_data[120] = 1'b0;
assign io_rep_bits_data[121] = 1'b0;
assign io_rep_bits_data[122] = 1'b0;
assign io_rep_bits_data[123] = 1'b0;
assign io_rep_bits_data[124] = 1'b0;
assign io_rep_bits_data[125] = 1'b0;
assign io_rep_bits_data[126] = 1'b0;
assign io_rep_bits_data[127] = 1'b0;
assign io_wb_req_bits_addr_beat[0] = 1'b0;
assign io_wb_req_bits_addr_beat[1] = 1'b0;
assign io_wb_req_bits_client_xact_id[0] = 1'b0;
assign io_wb_req_bits_client_xact_id[1] = 1'b0;
assign io_wb_req_bits_client_xact_id[2] = 1'b0;
assign io_wb_req_bits_client_xact_id[3] = 1'b0;
assign io_wb_req_bits_client_xact_id[4] = 1'b0;
assign io_wb_req_bits_client_xact_id[5] = 1'b0;
assign io_wb_req_bits_voluntary = 1'b0;
assign io_wb_req_bits_data[0] = 1'b0;
assign io_wb_req_bits_data[1] = 1'b0;
assign io_wb_req_bits_data[2] = 1'b0;
assign io_wb_req_bits_data[3] = 1'b0;
assign io_wb_req_bits_data[4] = 1'b0;
assign io_wb_req_bits_data[5] = 1'b0;
assign io_wb_req_bits_data[6] = 1'b0;
assign io_wb_req_bits_data[7] = 1'b0;
assign io_wb_req_bits_data[8] = 1'b0;
assign io_wb_req_bits_data[9] = 1'b0;
assign io_wb_req_bits_data[10] = 1'b0;
assign io_wb_req_bits_data[11] = 1'b0;
assign io_wb_req_bits_data[12] = 1'b0;
assign io_wb_req_bits_data[13] = 1'b0;
assign io_wb_req_bits_data[14] = 1'b0;
assign io_wb_req_bits_data[15] = 1'b0;
assign io_wb_req_bits_data[16] = 1'b0;
assign io_wb_req_bits_data[17] = 1'b0;
assign io_wb_req_bits_data[18] = 1'b0;
assign io_wb_req_bits_data[19] = 1'b0;
assign io_wb_req_bits_data[20] = 1'b0;
assign io_wb_req_bits_data[21] = 1'b0;
assign io_wb_req_bits_data[22] = 1'b0;
assign io_wb_req_bits_data[23] = 1'b0;
assign io_wb_req_bits_data[24] = 1'b0;
assign io_wb_req_bits_data[25] = 1'b0;
assign io_wb_req_bits_data[26] = 1'b0;
assign io_wb_req_bits_data[27] = 1'b0;
assign io_wb_req_bits_data[28] = 1'b0;
assign io_wb_req_bits_data[29] = 1'b0;
assign io_wb_req_bits_data[30] = 1'b0;
assign io_wb_req_bits_data[31] = 1'b0;
assign io_wb_req_bits_data[32] = 1'b0;
assign io_wb_req_bits_data[33] = 1'b0;
assign io_wb_req_bits_data[34] = 1'b0;
assign io_wb_req_bits_data[35] = 1'b0;
assign io_wb_req_bits_data[36] = 1'b0;
assign io_wb_req_bits_data[37] = 1'b0;
assign io_wb_req_bits_data[38] = 1'b0;
assign io_wb_req_bits_data[39] = 1'b0;
assign io_wb_req_bits_data[40] = 1'b0;
assign io_wb_req_bits_data[41] = 1'b0;
assign io_wb_req_bits_data[42] = 1'b0;
assign io_wb_req_bits_data[43] = 1'b0;
assign io_wb_req_bits_data[44] = 1'b0;
assign io_wb_req_bits_data[45] = 1'b0;
assign io_wb_req_bits_data[46] = 1'b0;
assign io_wb_req_bits_data[47] = 1'b0;
assign io_wb_req_bits_data[48] = 1'b0;
assign io_wb_req_bits_data[49] = 1'b0;
assign io_wb_req_bits_data[50] = 1'b0;
assign io_wb_req_bits_data[51] = 1'b0;
assign io_wb_req_bits_data[52] = 1'b0;
assign io_wb_req_bits_data[53] = 1'b0;
assign io_wb_req_bits_data[54] = 1'b0;
assign io_wb_req_bits_data[55] = 1'b0;
assign io_wb_req_bits_data[56] = 1'b0;
assign io_wb_req_bits_data[57] = 1'b0;
assign io_wb_req_bits_data[58] = 1'b0;
assign io_wb_req_bits_data[59] = 1'b0;
assign io_wb_req_bits_data[60] = 1'b0;
assign io_wb_req_bits_data[61] = 1'b0;
assign io_wb_req_bits_data[62] = 1'b0;
assign io_wb_req_bits_data[63] = 1'b0;
assign io_wb_req_bits_data[64] = 1'b0;
assign io_wb_req_bits_data[65] = 1'b0;
assign io_wb_req_bits_data[66] = 1'b0;
assign io_wb_req_bits_data[67] = 1'b0;
assign io_wb_req_bits_data[68] = 1'b0;
assign io_wb_req_bits_data[69] = 1'b0;
assign io_wb_req_bits_data[70] = 1'b0;
assign io_wb_req_bits_data[71] = 1'b0;
assign io_wb_req_bits_data[72] = 1'b0;
assign io_wb_req_bits_data[73] = 1'b0;
assign io_wb_req_bits_data[74] = 1'b0;
assign io_wb_req_bits_data[75] = 1'b0;
assign io_wb_req_bits_data[76] = 1'b0;
assign io_wb_req_bits_data[77] = 1'b0;
assign io_wb_req_bits_data[78] = 1'b0;
assign io_wb_req_bits_data[79] = 1'b0;
assign io_wb_req_bits_data[80] = 1'b0;
assign io_wb_req_bits_data[81] = 1'b0;
assign io_wb_req_bits_data[82] = 1'b0;
assign io_wb_req_bits_data[83] = 1'b0;
assign io_wb_req_bits_data[84] = 1'b0;
assign io_wb_req_bits_data[85] = 1'b0;
assign io_wb_req_bits_data[86] = 1'b0;
assign io_wb_req_bits_data[87] = 1'b0;
assign io_wb_req_bits_data[88] = 1'b0;
assign io_wb_req_bits_data[89] = 1'b0;
assign io_wb_req_bits_data[90] = 1'b0;
assign io_wb_req_bits_data[91] = 1'b0;
assign io_wb_req_bits_data[92] = 1'b0;
assign io_wb_req_bits_data[93] = 1'b0;
assign io_wb_req_bits_data[94] = 1'b0;
assign io_wb_req_bits_data[95] = 1'b0;
assign io_wb_req_bits_data[96] = 1'b0;
assign io_wb_req_bits_data[97] = 1'b0;
assign io_wb_req_bits_data[98] = 1'b0;
assign io_wb_req_bits_data[99] = 1'b0;
assign io_wb_req_bits_data[100] = 1'b0;
assign io_wb_req_bits_data[101] = 1'b0;
assign io_wb_req_bits_data[102] = 1'b0;
assign io_wb_req_bits_data[103] = 1'b0;
assign io_wb_req_bits_data[104] = 1'b0;
assign io_wb_req_bits_data[105] = 1'b0;
assign io_wb_req_bits_data[106] = 1'b0;
assign io_wb_req_bits_data[107] = 1'b0;
assign io_wb_req_bits_data[108] = 1'b0;
assign io_wb_req_bits_data[109] = 1'b0;
assign io_wb_req_bits_data[110] = 1'b0;
assign io_wb_req_bits_data[111] = 1'b0;
assign io_wb_req_bits_data[112] = 1'b0;
assign io_wb_req_bits_data[113] = 1'b0;
assign io_wb_req_bits_data[114] = 1'b0;
assign io_wb_req_bits_data[115] = 1'b0;
assign io_wb_req_bits_data[116] = 1'b0;
assign io_wb_req_bits_data[117] = 1'b0;
assign io_wb_req_bits_data[118] = 1'b0;
assign io_wb_req_bits_data[119] = 1'b0;
assign io_wb_req_bits_data[120] = 1'b0;
assign io_wb_req_bits_data[121] = 1'b0;
assign io_wb_req_bits_data[122] = 1'b0;
assign io_wb_req_bits_data[123] = 1'b0;
assign io_wb_req_bits_data[124] = 1'b0;
assign io_wb_req_bits_data[125] = 1'b0;
assign io_wb_req_bits_data[126] = 1'b0;
assign io_wb_req_bits_data[127] = 1'b0;
assign io_rep_bits_addr_block[25] = io_wb_req_bits_addr_block[25];
assign io_meta_read_bits_tag[19] = io_wb_req_bits_addr_block[25];
assign io_meta_write_bits_data_tag[19] = io_wb_req_bits_addr_block[25];
assign io_rep_bits_addr_block[24] = io_wb_req_bits_addr_block[24];
assign io_meta_read_bits_tag[18] = io_wb_req_bits_addr_block[24];
assign io_meta_write_bits_data_tag[18] = io_wb_req_bits_addr_block[24];
assign io_rep_bits_addr_block[23] = io_wb_req_bits_addr_block[23];
assign io_meta_read_bits_tag[17] = io_wb_req_bits_addr_block[23];
assign io_meta_write_bits_data_tag[17] = io_wb_req_bits_addr_block[23];
assign io_rep_bits_addr_block[22] = io_wb_req_bits_addr_block[22];
assign io_meta_read_bits_tag[16] = io_wb_req_bits_addr_block[22];
assign io_meta_write_bits_data_tag[16] = io_wb_req_bits_addr_block[22];
assign io_rep_bits_addr_block[21] = io_wb_req_bits_addr_block[21];
assign io_meta_read_bits_tag[15] = io_wb_req_bits_addr_block[21];
assign io_meta_write_bits_data_tag[15] = io_wb_req_bits_addr_block[21];
assign io_rep_bits_addr_block[20] = io_wb_req_bits_addr_block[20];
assign io_meta_read_bits_tag[14] = io_wb_req_bits_addr_block[20];
assign io_meta_write_bits_data_tag[14] = io_wb_req_bits_addr_block[20];
assign io_rep_bits_addr_block[19] = io_wb_req_bits_addr_block[19];
assign io_meta_read_bits_tag[13] = io_wb_req_bits_addr_block[19];
assign io_meta_write_bits_data_tag[13] = io_wb_req_bits_addr_block[19];
assign io_rep_bits_addr_block[18] = io_wb_req_bits_addr_block[18];
assign io_meta_read_bits_tag[12] = io_wb_req_bits_addr_block[18];
assign io_meta_write_bits_data_tag[12] = io_wb_req_bits_addr_block[18];
assign io_rep_bits_addr_block[17] = io_wb_req_bits_addr_block[17];
assign io_meta_read_bits_tag[11] = io_wb_req_bits_addr_block[17];
assign io_meta_write_bits_data_tag[11] = io_wb_req_bits_addr_block[17];
assign io_rep_bits_addr_block[16] = io_wb_req_bits_addr_block[16];
assign io_meta_read_bits_tag[10] = io_wb_req_bits_addr_block[16];
assign io_meta_write_bits_data_tag[10] = io_wb_req_bits_addr_block[16];
assign io_rep_bits_addr_block[15] = io_wb_req_bits_addr_block[15];
assign io_meta_read_bits_tag[9] = io_wb_req_bits_addr_block[15];
assign io_meta_write_bits_data_tag[9] = io_wb_req_bits_addr_block[15];
assign io_rep_bits_addr_block[14] = io_wb_req_bits_addr_block[14];
assign io_meta_read_bits_tag[8] = io_wb_req_bits_addr_block[14];
assign io_meta_write_bits_data_tag[8] = io_wb_req_bits_addr_block[14];
assign io_rep_bits_addr_block[13] = io_wb_req_bits_addr_block[13];
assign io_meta_read_bits_tag[7] = io_wb_req_bits_addr_block[13];
assign io_meta_write_bits_data_tag[7] = io_wb_req_bits_addr_block[13];
assign io_rep_bits_addr_block[12] = io_wb_req_bits_addr_block[12];
assign io_meta_read_bits_tag[6] = io_wb_req_bits_addr_block[12];
assign io_meta_write_bits_data_tag[6] = io_wb_req_bits_addr_block[12];
assign io_rep_bits_addr_block[11] = io_wb_req_bits_addr_block[11];
assign io_meta_read_bits_tag[5] = io_wb_req_bits_addr_block[11];
assign io_meta_write_bits_data_tag[5] = io_wb_req_bits_addr_block[11];
assign io_rep_bits_addr_block[10] = io_wb_req_bits_addr_block[10];
assign io_meta_read_bits_tag[4] = io_wb_req_bits_addr_block[10];
assign io_meta_write_bits_data_tag[4] = io_wb_req_bits_addr_block[10];
assign io_rep_bits_addr_block[9] = io_wb_req_bits_addr_block[9];
assign io_meta_read_bits_tag[3] = io_wb_req_bits_addr_block[9];
assign io_meta_write_bits_data_tag[3] = io_wb_req_bits_addr_block[9];
assign io_rep_bits_addr_block[8] = io_wb_req_bits_addr_block[8];
assign io_meta_read_bits_tag[2] = io_wb_req_bits_addr_block[8];
assign io_meta_write_bits_data_tag[2] = io_wb_req_bits_addr_block[8];
assign io_rep_bits_addr_block[7] = io_wb_req_bits_addr_block[7];
assign io_meta_read_bits_tag[1] = io_wb_req_bits_addr_block[7];
assign io_meta_write_bits_data_tag[1] = io_wb_req_bits_addr_block[7];
assign io_rep_bits_addr_block[6] = io_wb_req_bits_addr_block[6];
assign io_meta_read_bits_tag[0] = io_wb_req_bits_addr_block[6];
assign io_meta_write_bits_data_tag[0] = io_wb_req_bits_addr_block[6];
assign io_rep_bits_addr_block[5] = io_wb_req_bits_addr_block[5];
assign io_meta_read_bits_idx[5] = io_wb_req_bits_addr_block[5];
assign io_meta_write_bits_idx[5] = io_wb_req_bits_addr_block[5];
assign io_rep_bits_addr_block[4] = io_wb_req_bits_addr_block[4];
assign io_meta_read_bits_idx[4] = io_wb_req_bits_addr_block[4];
assign io_meta_write_bits_idx[4] = io_wb_req_bits_addr_block[4];
assign io_rep_bits_addr_block[3] = io_wb_req_bits_addr_block[3];
assign io_meta_read_bits_idx[3] = io_wb_req_bits_addr_block[3];
assign io_meta_write_bits_idx[3] = io_wb_req_bits_addr_block[3];
assign io_rep_bits_addr_block[2] = io_wb_req_bits_addr_block[2];
assign io_meta_read_bits_idx[2] = io_wb_req_bits_addr_block[2];
assign io_meta_write_bits_idx[2] = io_wb_req_bits_addr_block[2];
assign io_rep_bits_addr_block[1] = io_wb_req_bits_addr_block[1];
assign io_meta_read_bits_idx[1] = io_wb_req_bits_addr_block[1];
assign io_meta_write_bits_idx[1] = io_wb_req_bits_addr_block[1];
assign io_rep_bits_addr_block[0] = io_wb_req_bits_addr_block[0];
assign io_meta_read_bits_idx[0] = io_wb_req_bits_addr_block[0];
assign io_meta_write_bits_idx[0] = io_wb_req_bits_addr_block[0];
assign io_rep_bits_r_type[2] = io_wb_req_bits_r_type[2];
assign io_rep_bits_r_type[1] = io_wb_req_bits_r_type[1];
assign io_rep_bits_r_type[0] = io_wb_req_bits_r_type[0];
assign io_meta_write_bits_way_en[3] = io_wb_req_bits_way_en[3];
assign io_meta_write_bits_way_en[2] = io_wb_req_bits_way_en[2];
assign io_meta_write_bits_way_en[1] = io_wb_req_bits_way_en[1];
assign io_meta_write_bits_way_en[0] = io_wb_req_bits_way_en[0];
always @(posedge clk) begin
if(N105) begin
io_wb_req_bits_way_en[3] <= io_way_en[3];
end
end
always @(posedge clk) begin
if(N105) begin
io_wb_req_bits_way_en[2] <= io_way_en[2];
end
end
always @(posedge clk) begin
if(N105) begin
io_wb_req_bits_way_en[1] <= io_way_en[1];
end
end
always @(posedge clk) begin
if(N105) begin
io_wb_req_bits_way_en[0] <= io_way_en[0];
end
end
always @(posedge clk) begin
if(N29) begin
state[3] <= N33;
end
end
always @(posedge clk) begin
if(N29) begin
state[2] <= N32;
end
end
always @(posedge clk) begin
if(N29) begin
state[1] <= N31;
end
end
always @(posedge clk) begin
if(N29) begin
state[0] <= N30;
end
end
always @(posedge clk) begin
if(N105) begin
T58[1] <= io_block_state_state[1];
end
end
always @(posedge clk) begin
if(N105) begin
T58[0] <= io_block_state_state[0];
end
end
always @(posedge clk) begin
if(T22) begin
req_p_type[1] <= io_req_bits_p_type[1];
end
end
always @(posedge clk) begin
if(T22) begin
req_p_type[0] <= io_req_bits_p_type[0];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[25] <= io_req_bits_addr_block[25];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[24] <= io_req_bits_addr_block[24];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[23] <= io_req_bits_addr_block[23];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[22] <= io_req_bits_addr_block[22];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[21] <= io_req_bits_addr_block[21];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[20] <= io_req_bits_addr_block[20];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[19] <= io_req_bits_addr_block[19];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[18] <= io_req_bits_addr_block[18];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[17] <= io_req_bits_addr_block[17];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[16] <= io_req_bits_addr_block[16];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[15] <= io_req_bits_addr_block[15];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[14] <= io_req_bits_addr_block[14];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[13] <= io_req_bits_addr_block[13];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[12] <= io_req_bits_addr_block[12];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[11] <= io_req_bits_addr_block[11];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[10] <= io_req_bits_addr_block[10];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[9] <= io_req_bits_addr_block[9];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[8] <= io_req_bits_addr_block[8];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[7] <= io_req_bits_addr_block[7];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[6] <= io_req_bits_addr_block[6];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[5] <= io_req_bits_addr_block[5];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[4] <= io_req_bits_addr_block[4];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[3] <= io_req_bits_addr_block[3];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[2] <= io_req_bits_addr_block[2];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[1] <= io_req_bits_addr_block[1];
end
end
always @(posedge clk) begin
if(T22) begin
io_wb_req_bits_addr_block[0] <= io_req_bits_addr_block[0];
end
end
assign N60 = ~state[2];
assign N61 = ~state[0];
assign N62 = N60 | state[3];
assign N63 = state[1] | N62;
assign N64 = N61 | N63;
assign io_rep_valid = ~N64;
assign N66 = req_p_type[0] | req_p_type[1];
assign N67 = ~N66;
assign N68 = req_p_type[0] | req_p_type[1];
assign N69 = ~N68;
assign N70 = T44[0] & T44[1];
assign N71 = ~req_p_type[0];
assign N72 = N71 | req_p_type[1];
assign N73 = ~N72;
assign N74 = N71 | req_p_type[1];
assign N75 = ~N74;
assign N76 = T44[0] & T44[1];
assign N77 = ~req_p_type[1];
assign N78 = req_p_type[0] | N77;
assign N79 = ~N78;
assign N80 = T44[0] & T44[1];
assign N81 = state[2] | state[3];
assign N82 = state[1] | N81;
assign N83 = state[0] | N82;
assign io_req_ready = ~N83;
assign N85 = T58[0] & T58[1];
assign N86 = ~state[1];
assign N87 = state[2] | state[3];
assign N88 = N86 | N87;
assign N89 = state[0] | N88;
assign N90 = ~N89;
assign N91 = state[2] | state[3];
assign N92 = state[1] | N91;
assign N93 = N61 | N92;
assign io_meta_read_valid = ~N93;
assign N95 = io_wb_req_bits_way_en[2] | io_wb_req_bits_way_en[3];
assign N96 = io_wb_req_bits_way_en[1] | N95;
assign N97 = io_wb_req_bits_way_en[0] | N96;
assign N98 = N60 | state[3];
assign N99 = state[1] | N98;
assign N100 = state[0] | N99;
assign N101 = ~N100;
assign N102 = state[2] | state[3];
assign N103 = N86 | N102;
assign N104 = N61 | N103;
assign N105 = ~N104;
assign N106 = N60 | state[3];
assign N107 = state[1] | N106;
assign N108 = N61 | N107;
assign N109 = ~N108;
assign N110 = N60 | state[3];
assign N111 = N86 | N110;
assign N112 = state[0] | N111;
assign io_wb_req_valid = ~N112;
assign N114 = N60 | state[3];
assign N115 = N86 | N114;
assign N116 = N61 | N115;
assign N117 = ~N116;
assign N118 = ~state[3];
assign N119 = state[2] | N118;
assign N120 = state[1] | N119;
assign N121 = state[0] | N120;
assign io_meta_write_valid = ~N121;
assign io_wb_req_bits_r_type = (N0)? { 1'b0, T50[1:1], T50[1:1] } :
(N1)? T40 : 1'b0;
assign N0 = N67;
assign N1 = N66;
assign T40 = (N2)? { T47[2:2], 1'b0, T47_0 } :
(N3)? T41 : 1'b0;
assign N2 = N73;
assign N3 = N72;
assign T41 = (N4)? { T42, T42[2:2] } :
(N5)? { 1'b0, 1'b1, 1'b1 } : 1'b0;
assign N4 = N79;
assign N5 = N78;
assign T44 = (N6)? T58 :
(N7)? { 1'b0, 1'b0 } : 1'b0;
assign N6 = T32[3];
assign N7 = N14;
assign io_meta_write_bits_data_coh_state = (N8)? { 1'b0, 1'b0 } :
(N9)? T57 : 1'b0;
assign N8 = N69;
assign N9 = N68;
assign T57 = (N10)? { 1'b0, 1'b1 } :
(N11)? T58 : 1'b0;
assign N10 = N75;
assign N11 = N74;
assign N29 = (N12)? 1'b1 :
(N35)? 1'b1 :
(N38)? 1'b1 :
(N41)? 1'b1 :
(N44)? 1'b1 :
(N47)? 1'b1 :
(N49)? 1'b1 :
(N52)? 1'b1 :
(N54)? 1'b1 :
(N56)? 1'b1 :
(N59)? 1'b1 :
(N28)? 1'b0 : 1'b0;
assign N12 = reset;
assign { N33, N32, N31, N30 } = (N12)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N35)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N38)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N41)? { 1'b0, 1'b1, 1'b1, 1'b1 } :
(N44)? { T32[3:3], 1'b0, 1'b0, 1'b0 } :
(N47)? { 1'b0, 1'b1, T27 } :
(N49)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N52)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N54)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N56)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N59)? { 1'b0, 1'b0, 1'b0, 1'b1 } : 1'b0;
assign T22 = io_req_ready & io_req_valid;
assign T23 = io_meta_read_ready & io_meta_read_valid;
assign T25 = N105 & T26;
assign T26 = ~io_mshr_rdy;
assign N13 = ~T28;
assign T27[1] = T28;
assign T27[0] = N13;
assign T28 = N97 & N85;
assign N14 = ~N97;
assign T32[3] = N97;
assign T33 = N109 & io_rep_ready;
assign T35 = io_wb_req_ready & io_wb_req_valid;
assign T36 = N117 & io_wb_req_ready;
assign T38 = io_meta_write_ready & io_meta_write_valid;
assign N15 = ~N80;
assign T42[1] = N80;
assign T42[2] = N15;
assign N16 = ~N76;
assign T47_0 = N76;
assign T47[2] = N16;
assign N17 = ~N70;
assign T50[1] = N17;
assign N18 = T38 | reset;
assign N19 = T36 | N18;
assign N20 = T35 | N19;
assign N21 = T33 | N20;
assign N22 = N101 | N21;
assign N23 = T25 | N22;
assign N24 = N105 | N23;
assign N25 = N90 | N24;
assign N26 = T23 | N25;
assign N27 = T22 | N26;
assign N28 = ~N27;
assign N34 = ~reset;
assign N35 = T38 & N34;
assign N36 = ~T38;
assign N37 = N34 & N36;
assign N38 = T36 & N37;
assign N39 = ~T36;
assign N40 = N37 & N39;
assign N41 = T35 & N40;
assign N42 = ~T35;
assign N43 = N40 & N42;
assign N44 = T33 & N43;
assign N45 = ~T33;
assign N46 = N43 & N45;
assign N47 = N101 & N46;
assign N48 = N46 & N100;
assign N49 = T25 & N48;
assign N50 = ~T25;
assign N51 = N48 & N50;
assign N52 = N105 & N51;
assign N53 = N51 & N104;
assign N54 = N90 & N53;
assign N55 = N53 & N89;
assign N56 = T23 & N55;
assign N57 = ~T23;
assign N58 = N55 & N57;
assign N59 = T22 & N58;
endmodule |
module LockingRRArbiter_9
(
clk,
reset,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_header_src,
io_in_4_bits_header_dst,
io_in_4_bits_payload_manager_xact_id,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_header_src,
io_in_3_bits_header_dst,
io_in_3_bits_payload_manager_xact_id,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_header_src,
io_in_2_bits_header_dst,
io_in_2_bits_payload_manager_xact_id,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_header_src,
io_in_1_bits_header_dst,
io_in_1_bits_payload_manager_xact_id,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_header_src,
io_in_0_bits_header_dst,
io_in_0_bits_payload_manager_xact_id,
io_out_ready,
io_out_valid,
io_out_bits_header_src,
io_out_bits_header_dst,
io_out_bits_payload_manager_xact_id,
io_chosen
);
input [2:0] io_in_4_bits_header_src;
input [2:0] io_in_4_bits_header_dst;
input [3:0] io_in_4_bits_payload_manager_xact_id;
input [2:0] io_in_3_bits_header_src;
input [2:0] io_in_3_bits_header_dst;
input [3:0] io_in_3_bits_payload_manager_xact_id;
input [2:0] io_in_2_bits_header_src;
input [2:0] io_in_2_bits_header_dst;
input [3:0] io_in_2_bits_payload_manager_xact_id;
input [2:0] io_in_1_bits_header_src;
input [2:0] io_in_1_bits_header_dst;
input [3:0] io_in_1_bits_payload_manager_xact_id;
input [2:0] io_in_0_bits_header_src;
input [2:0] io_in_0_bits_header_dst;
input [3:0] io_in_0_bits_payload_manager_xact_id;
output [2:0] io_out_bits_header_src;
output [2:0] io_out_bits_header_dst;
output [3:0] io_out_bits_payload_manager_xact_id;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_4_valid;
input io_in_3_valid;
input io_in_2_valid;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
wire [2:0] io_out_bits_header_src,io_out_bits_header_dst,io_chosen,T0,T1,T2,T3,T4,T5,T27,
T30,T28,T35,T38,T36;
wire [3:0] io_out_bits_payload_manager_xact_id,T18,T22,T19;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
T15,N21,T13,N22,T11,N23,T7,N24,N25,N26,N27,N28,T8,T10,T12,T14,T16,N29,N30,N31,T43,
T46,T44,T51,T67,T52,T53,T56,T54,T55,T59,T57,T58,T62,T60,T61,T65,T63,T64,T66,T69,
T76,T70,T71,T72,T73,T74,T75,T78,T77,T80,T88,T81,T82,T83,T84,T85,T86,T87,T90,T89,
T91,T93,T102,T94,T95,T96,T97,T98,T99,T100,T101,T104,T103,T105,T106,T108,T118,
T109,T110,T111,T112,T113,T114,T115,T116,T117,T120,T119,T121,T122,T123,N32,N33,N34,
N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48;
wire [2:1] T6;
reg [2:0] last_grant;
assign T12 = last_grant < { 1'b1, 1'b1 };
assign T58 = last_grant < { 1'b1, 1'b1 };
assign T66 = last_grant < 1'b0;
assign T67 = last_grant < 1'b0;
assign T103 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N34) begin
last_grant[2] <= N37;
end
end
always @(posedge clk) begin
if(N34) begin
last_grant[1] <= N36;
end
end
always @(posedge clk) begin
if(N34) begin
last_grant[0] <= N35;
end
end
assign io_chosen = (N0)? { 1'b0, 1'b0, 1'b1 } :
(N1)? T0 : 1'b0;
assign N0 = T15;
assign N1 = N21;
assign T0 = (N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? T1 : 1'b0;
assign N2 = T13;
assign N3 = N22;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b1 } :
(N5)? T2 : 1'b0;
assign N4 = T11;
assign N5 = N23;
assign T2 = (N6)? { 1'b1, 1'b0, 1'b0 } :
(N7)? T3 : 1'b0;
assign N6 = T7;
assign N7 = N24;
assign T3 = (N8)? { 1'b0, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = io_in_0_valid;
assign N9 = N25;
assign T4 = (N10)? { 1'b0, 1'b0, 1'b1 } :
(N11)? T5 : 1'b0;
assign N10 = io_in_1_valid;
assign N11 = N26;
assign T5 = (N12)? { 1'b0, 1'b1, 1'b0 } :
(N13)? { T6, T6[1:1] } : 1'b0;
assign N12 = io_in_2_valid;
assign N13 = N27;
assign io_out_bits_payload_manager_xact_id = (N14)? io_in_4_bits_payload_manager_xact_id :
(N15)? T18 : 1'b0;
assign N14 = io_chosen[2];
assign N15 = N29;
assign T18 = (N16)? T22 :
(N17)? T19 : 1'b0;
assign N16 = io_chosen[1];
assign N17 = N30;
assign T19 = (N18)? io_in_1_bits_payload_manager_xact_id :
(N19)? io_in_0_bits_payload_manager_xact_id : 1'b0;
assign N18 = io_chosen[0];
assign N19 = N31;
assign T22 = (N18)? io_in_3_bits_payload_manager_xact_id :
(N19)? io_in_2_bits_payload_manager_xact_id : 1'b0;
assign io_out_bits_header_dst = (N14)? io_in_4_bits_header_dst :
(N15)? T27 : 1'b0;
assign T27 = (N16)? T30 :
(N17)? T28 : 1'b0;
assign T28 = (N18)? io_in_1_bits_header_dst :
(N19)? io_in_0_bits_header_dst : 1'b0;
assign T30 = (N18)? io_in_3_bits_header_dst :
(N19)? io_in_2_bits_header_dst : 1'b0;
assign io_out_bits_header_src = (N14)? io_in_4_bits_header_src :
(N15)? T35 : 1'b0;
assign T35 = (N16)? T38 :
(N17)? T36 : 1'b0;
assign T36 = (N18)? io_in_1_bits_header_src :
(N19)? io_in_0_bits_header_src : 1'b0;
assign T38 = (N18)? io_in_3_bits_header_src :
(N19)? io_in_2_bits_header_src : 1'b0;
assign io_out_valid = (N14)? io_in_4_valid :
(N15)? T43 : 1'b0;
assign T43 = (N16)? T46 :
(N17)? T44 : 1'b0;
assign T44 = (N18)? io_in_1_valid :
(N19)? io_in_0_valid : 1'b0;
assign T46 = (N18)? io_in_3_valid :
(N19)? io_in_2_valid : 1'b0;
assign N34 = (N20)? 1'b1 :
(N39)? 1'b1 :
(N33)? 1'b0 : 1'b0;
assign N20 = reset;
assign { N37, N36, N35 } = (N20)? { 1'b0, 1'b0, 1'b0 } :
(N39)? io_chosen : 1'b0;
assign N21 = ~T15;
assign N22 = ~T13;
assign N23 = ~T11;
assign N24 = ~T7;
assign N25 = ~io_in_0_valid;
assign N26 = ~io_in_1_valid;
assign N27 = ~io_in_2_valid;
assign N28 = ~io_in_3_valid;
assign T6[1] = io_in_3_valid;
assign T6[2] = N28;
assign T7 = io_in_4_valid & T8;
assign T8 = ~last_grant[2];
assign T10 = io_out_ready & io_out_valid;
assign T11 = io_in_3_valid & T12;
assign T13 = io_in_2_valid & T14;
assign T14 = ~N40;
assign N40 = last_grant[2] | last_grant[1];
assign T15 = io_in_1_valid & T16;
assign T16 = ~N42;
assign N42 = N41 | last_grant[0];
assign N41 = last_grant[2] | last_grant[1];
assign N29 = ~io_chosen[2];
assign N30 = ~io_chosen[1];
assign N31 = ~io_chosen[0];
assign io_in_0_ready = T51 & io_out_ready;
assign T51 = T67 | T52;
assign T52 = ~T53;
assign T53 = T56 | T54;
assign T54 = io_in_4_valid & T55;
assign T55 = ~last_grant[2];
assign T56 = T59 | T57;
assign T57 = io_in_3_valid & T58;
assign T59 = T62 | T60;
assign T60 = io_in_2_valid & T61;
assign T61 = ~N43;
assign N43 = last_grant[2] | last_grant[1];
assign T62 = T65 | T63;
assign T63 = io_in_1_valid & T64;
assign T64 = ~N45;
assign N45 = N44 | last_grant[0];
assign N44 = last_grant[2] | last_grant[1];
assign T65 = io_in_0_valid & T66;
assign io_in_1_ready = T69 & io_out_ready;
assign T69 = T76 | T70;
assign T70 = ~T71;
assign T71 = T72 | io_in_0_valid;
assign T72 = T73 | T54;
assign T73 = T74 | T57;
assign T74 = T75 | T60;
assign T75 = T65 | T63;
assign T76 = T78 & T77;
assign T77 = ~N47;
assign N47 = N46 | last_grant[0];
assign N46 = last_grant[2] | last_grant[1];
assign T78 = ~T65;
assign io_in_2_ready = T80 & io_out_ready;
assign T80 = T88 | T81;
assign T81 = ~T82;
assign T82 = T83 | io_in_1_valid;
assign T83 = T84 | io_in_0_valid;
assign T84 = T85 | T54;
assign T85 = T86 | T57;
assign T86 = T87 | T60;
assign T87 = T65 | T63;
assign T88 = T90 & T89;
assign T89 = ~N48;
assign N48 = last_grant[2] | last_grant[1];
assign T90 = ~T91;
assign T91 = T65 | T63;
assign io_in_3_ready = T93 & io_out_ready;
assign T93 = T102 | T94;
assign T94 = ~T95;
assign T95 = T96 | io_in_2_valid;
assign T96 = T97 | io_in_1_valid;
assign T97 = T98 | io_in_0_valid;
assign T98 = T99 | T54;
assign T99 = T100 | T57;
assign T100 = T101 | T60;
assign T101 = T65 | T63;
assign T102 = T104 & T103;
assign T104 = ~T105;
assign T105 = T106 | T60;
assign T106 = T65 | T63;
assign io_in_4_ready = T108 & io_out_ready;
assign T108 = T118 | T109;
assign T109 = ~T110;
assign T110 = T111 | io_in_3_valid;
assign T111 = T112 | io_in_2_valid;
assign T112 = T113 | io_in_1_valid;
assign T113 = T114 | io_in_0_valid;
assign T114 = T115 | T54;
assign T115 = T116 | T57;
assign T116 = T117 | T60;
assign T117 = T65 | T63;
assign T118 = T120 & T119;
assign T119 = ~last_grant[2];
assign T120 = ~T121;
assign T121 = T122 | T57;
assign T122 = T123 | T60;
assign T123 = T65 | T63;
assign N32 = T10 | reset;
assign N33 = ~N32;
assign N38 = ~reset;
assign N39 = T10 & N38;
endmodule |
module ClientTileLinkEnqueuer
(
io_inner_acquire_ready,
io_inner_acquire_valid,
io_inner_acquire_bits_addr_block,
io_inner_acquire_bits_client_xact_id,
io_inner_acquire_bits_addr_beat,
io_inner_acquire_bits_is_builtin_type,
io_inner_acquire_bits_a_type,
io_inner_acquire_bits_union,
io_inner_acquire_bits_data,
io_inner_grant_ready,
io_inner_grant_valid,
io_inner_grant_bits_addr_beat,
io_inner_grant_bits_client_xact_id,
io_inner_grant_bits_manager_xact_id,
io_inner_grant_bits_is_builtin_type,
io_inner_grant_bits_g_type,
io_inner_grant_bits_data,
io_inner_probe_ready,
io_inner_probe_valid,
io_inner_probe_bits_addr_block,
io_inner_probe_bits_p_type,
io_inner_release_ready,
io_inner_release_valid,
io_inner_release_bits_addr_beat,
io_inner_release_bits_addr_block,
io_inner_release_bits_client_xact_id,
io_inner_release_bits_voluntary,
io_inner_release_bits_r_type,
io_inner_release_bits_data,
io_outer_acquire_ready,
io_outer_acquire_valid,
io_outer_acquire_bits_addr_block,
io_outer_acquire_bits_client_xact_id,
io_outer_acquire_bits_addr_beat,
io_outer_acquire_bits_is_builtin_type,
io_outer_acquire_bits_a_type,
io_outer_acquire_bits_union,
io_outer_acquire_bits_data,
io_outer_grant_ready,
io_outer_grant_valid,
io_outer_grant_bits_addr_beat,
io_outer_grant_bits_client_xact_id,
io_outer_grant_bits_manager_xact_id,
io_outer_grant_bits_is_builtin_type,
io_outer_grant_bits_g_type,
io_outer_grant_bits_data,
io_outer_probe_ready,
io_outer_probe_valid,
io_outer_probe_bits_addr_block,
io_outer_probe_bits_p_type,
io_outer_release_ready,
io_outer_release_valid,
io_outer_release_bits_addr_beat,
io_outer_release_bits_addr_block,
io_outer_release_bits_client_xact_id,
io_outer_release_bits_voluntary,
io_outer_release_bits_r_type,
io_outer_release_bits_data
);
input [25:0] io_inner_acquire_bits_addr_block;
input [3:0] io_inner_acquire_bits_client_xact_id;
input [1:0] io_inner_acquire_bits_addr_beat;
input [2:0] io_inner_acquire_bits_a_type;
input [16:0] io_inner_acquire_bits_union;
input [127:0] io_inner_acquire_bits_data;
output [1:0] io_inner_grant_bits_addr_beat;
output [3:0] io_inner_grant_bits_client_xact_id;
output [3:0] io_inner_grant_bits_g_type;
output [127:0] io_inner_grant_bits_data;
output [25:0] io_inner_probe_bits_addr_block;
output [1:0] io_inner_probe_bits_p_type;
input [1:0] io_inner_release_bits_addr_beat;
input [25:0] io_inner_release_bits_addr_block;
input [3:0] io_inner_release_bits_client_xact_id;
input [2:0] io_inner_release_bits_r_type;
input [127:0] io_inner_release_bits_data;
output [25:0] io_outer_acquire_bits_addr_block;
output [3:0] io_outer_acquire_bits_client_xact_id;
output [1:0] io_outer_acquire_bits_addr_beat;
output [2:0] io_outer_acquire_bits_a_type;
output [16:0] io_outer_acquire_bits_union;
output [127:0] io_outer_acquire_bits_data;
input [1:0] io_outer_grant_bits_addr_beat;
input [3:0] io_outer_grant_bits_client_xact_id;
input [3:0] io_outer_grant_bits_g_type;
input [127:0] io_outer_grant_bits_data;
input [25:0] io_outer_probe_bits_addr_block;
input [1:0] io_outer_probe_bits_p_type;
output [1:0] io_outer_release_bits_addr_beat;
output [25:0] io_outer_release_bits_addr_block;
output [3:0] io_outer_release_bits_client_xact_id;
output [2:0] io_outer_release_bits_r_type;
output [127:0] io_outer_release_bits_data;
input io_inner_acquire_valid;
input io_inner_acquire_bits_is_builtin_type;
input io_inner_grant_ready;
input io_inner_probe_ready;
input io_inner_release_valid;
input io_inner_release_bits_voluntary;
input io_outer_acquire_ready;
input io_outer_grant_valid;
input io_outer_grant_bits_manager_xact_id;
input io_outer_grant_bits_is_builtin_type;
input io_outer_probe_valid;
input io_outer_release_ready;
output io_inner_acquire_ready;
output io_inner_grant_valid;
output io_inner_grant_bits_manager_xact_id;
output io_inner_grant_bits_is_builtin_type;
output io_inner_probe_valid;
output io_inner_release_ready;
output io_outer_acquire_valid;
output io_outer_acquire_bits_is_builtin_type;
output io_outer_grant_ready;
output io_outer_probe_ready;
output io_outer_release_valid;
output io_outer_release_bits_voluntary;
wire [1:0] io_inner_grant_bits_addr_beat,io_inner_probe_bits_p_type,
io_outer_acquire_bits_addr_beat,io_outer_release_bits_addr_beat;
wire [3:0] io_inner_grant_bits_client_xact_id,io_inner_grant_bits_g_type,
io_outer_acquire_bits_client_xact_id,io_outer_release_bits_client_xact_id;
wire [127:0] io_inner_grant_bits_data,io_outer_acquire_bits_data,io_outer_release_bits_data;
wire [25:0] io_inner_probe_bits_addr_block,io_outer_acquire_bits_addr_block,
io_outer_release_bits_addr_block;
wire [2:0] io_outer_acquire_bits_a_type,io_outer_release_bits_r_type;
wire [16:0] io_outer_acquire_bits_union;
wire io_inner_acquire_ready,io_inner_grant_valid,io_inner_grant_bits_manager_xact_id,
io_inner_grant_bits_is_builtin_type,io_inner_probe_valid,io_inner_release_ready,
io_outer_acquire_valid,io_outer_acquire_bits_is_builtin_type,
io_outer_grant_ready,io_outer_probe_ready,io_outer_release_valid,io_outer_release_bits_voluntary,
io_outer_acquire_ready,io_outer_grant_valid,io_outer_grant_bits_manager_xact_id,
io_outer_grant_bits_is_builtin_type,io_outer_probe_valid,io_outer_release_ready,
io_inner_acquire_valid,io_inner_acquire_bits_is_builtin_type,io_inner_grant_ready,
io_inner_probe_ready,io_inner_release_valid,io_inner_release_bits_voluntary;
assign io_inner_acquire_ready = io_outer_acquire_ready;
assign io_inner_grant_valid = io_outer_grant_valid;
assign io_inner_grant_bits_addr_beat[1] = io_outer_grant_bits_addr_beat[1];
assign io_inner_grant_bits_addr_beat[0] = io_outer_grant_bits_addr_beat[0];
assign io_inner_grant_bits_client_xact_id[3] = io_outer_grant_bits_client_xact_id[3];
assign io_inner_grant_bits_client_xact_id[2] = io_outer_grant_bits_client_xact_id[2];
assign io_inner_grant_bits_client_xact_id[1] = io_outer_grant_bits_client_xact_id[1];
assign io_inner_grant_bits_client_xact_id[0] = io_outer_grant_bits_client_xact_id[0];
assign io_inner_grant_bits_manager_xact_id = io_outer_grant_bits_manager_xact_id;
assign io_inner_grant_bits_is_builtin_type = io_outer_grant_bits_is_builtin_type;
assign io_inner_grant_bits_g_type[3] = io_outer_grant_bits_g_type[3];
assign io_inner_grant_bits_g_type[2] = io_outer_grant_bits_g_type[2];
assign io_inner_grant_bits_g_type[1] = io_outer_grant_bits_g_type[1];
assign io_inner_grant_bits_g_type[0] = io_outer_grant_bits_g_type[0];
assign io_inner_grant_bits_data[127] = io_outer_grant_bits_data[127];
assign io_inner_grant_bits_data[126] = io_outer_grant_bits_data[126];
assign io_inner_grant_bits_data[125] = io_outer_grant_bits_data[125];
assign io_inner_grant_bits_data[124] = io_outer_grant_bits_data[124];
assign io_inner_grant_bits_data[123] = io_outer_grant_bits_data[123];
assign io_inner_grant_bits_data[122] = io_outer_grant_bits_data[122];
assign io_inner_grant_bits_data[121] = io_outer_grant_bits_data[121];
assign io_inner_grant_bits_data[120] = io_outer_grant_bits_data[120];
assign io_inner_grant_bits_data[119] = io_outer_grant_bits_data[119];
assign io_inner_grant_bits_data[118] = io_outer_grant_bits_data[118];
assign io_inner_grant_bits_data[117] = io_outer_grant_bits_data[117];
assign io_inner_grant_bits_data[116] = io_outer_grant_bits_data[116];
assign io_inner_grant_bits_data[115] = io_outer_grant_bits_data[115];
assign io_inner_grant_bits_data[114] = io_outer_grant_bits_data[114];
assign io_inner_grant_bits_data[113] = io_outer_grant_bits_data[113];
assign io_inner_grant_bits_data[112] = io_outer_grant_bits_data[112];
assign io_inner_grant_bits_data[111] = io_outer_grant_bits_data[111];
assign io_inner_grant_bits_data[110] = io_outer_grant_bits_data[110];
assign io_inner_grant_bits_data[109] = io_outer_grant_bits_data[109];
assign io_inner_grant_bits_data[108] = io_outer_grant_bits_data[108];
assign io_inner_grant_bits_data[107] = io_outer_grant_bits_data[107];
assign io_inner_grant_bits_data[106] = io_outer_grant_bits_data[106];
assign io_inner_grant_bits_data[105] = io_outer_grant_bits_data[105];
assign io_inner_grant_bits_data[104] = io_outer_grant_bits_data[104];
assign io_inner_grant_bits_data[103] = io_outer_grant_bits_data[103];
assign io_inner_grant_bits_data[102] = io_outer_grant_bits_data[102];
assign io_inner_grant_bits_data[101] = io_outer_grant_bits_data[101];
assign io_inner_grant_bits_data[100] = io_outer_grant_bits_data[100];
assign io_inner_grant_bits_data[99] = io_outer_grant_bits_data[99];
assign io_inner_grant_bits_data[98] = io_outer_grant_bits_data[98];
assign io_inner_grant_bits_data[97] = io_outer_grant_bits_data[97];
assign io_inner_grant_bits_data[96] = io_outer_grant_bits_data[96];
assign io_inner_grant_bits_data[95] = io_outer_grant_bits_data[95];
assign io_inner_grant_bits_data[94] = io_outer_grant_bits_data[94];
assign io_inner_grant_bits_data[93] = io_outer_grant_bits_data[93];
assign io_inner_grant_bits_data[92] = io_outer_grant_bits_data[92];
assign io_inner_grant_bits_data[91] = io_outer_grant_bits_data[91];
assign io_inner_grant_bits_data[90] = io_outer_grant_bits_data[90];
assign io_inner_grant_bits_data[89] = io_outer_grant_bits_data[89];
assign io_inner_grant_bits_data[88] = io_outer_grant_bits_data[88];
assign io_inner_grant_bits_data[87] = io_outer_grant_bits_data[87];
assign io_inner_grant_bits_data[86] = io_outer_grant_bits_data[86];
assign io_inner_grant_bits_data[85] = io_outer_grant_bits_data[85];
assign io_inner_grant_bits_data[84] = io_outer_grant_bits_data[84];
assign io_inner_grant_bits_data[83] = io_outer_grant_bits_data[83];
assign io_inner_grant_bits_data[82] = io_outer_grant_bits_data[82];
assign io_inner_grant_bits_data[81] = io_outer_grant_bits_data[81];
assign io_inner_grant_bits_data[80] = io_outer_grant_bits_data[80];
assign io_inner_grant_bits_data[79] = io_outer_grant_bits_data[79];
assign io_inner_grant_bits_data[78] = io_outer_grant_bits_data[78];
assign io_inner_grant_bits_data[77] = io_outer_grant_bits_data[77];
assign io_inner_grant_bits_data[76] = io_outer_grant_bits_data[76];
assign io_inner_grant_bits_data[75] = io_outer_grant_bits_data[75];
assign io_inner_grant_bits_data[74] = io_outer_grant_bits_data[74];
assign io_inner_grant_bits_data[73] = io_outer_grant_bits_data[73];
assign io_inner_grant_bits_data[72] = io_outer_grant_bits_data[72];
assign io_inner_grant_bits_data[71] = io_outer_grant_bits_data[71];
assign io_inner_grant_bits_data[70] = io_outer_grant_bits_data[70];
assign io_inner_grant_bits_data[69] = io_outer_grant_bits_data[69];
assign io_inner_grant_bits_data[68] = io_outer_grant_bits_data[68];
assign io_inner_grant_bits_data[67] = io_outer_grant_bits_data[67];
assign io_inner_grant_bits_data[66] = io_outer_grant_bits_data[66];
assign io_inner_grant_bits_data[65] = io_outer_grant_bits_data[65];
assign io_inner_grant_bits_data[64] = io_outer_grant_bits_data[64];
assign io_inner_grant_bits_data[63] = io_outer_grant_bits_data[63];
assign io_inner_grant_bits_data[62] = io_outer_grant_bits_data[62];
assign io_inner_grant_bits_data[61] = io_outer_grant_bits_data[61];
assign io_inner_grant_bits_data[60] = io_outer_grant_bits_data[60];
assign io_inner_grant_bits_data[59] = io_outer_grant_bits_data[59];
assign io_inner_grant_bits_data[58] = io_outer_grant_bits_data[58];
assign io_inner_grant_bits_data[57] = io_outer_grant_bits_data[57];
assign io_inner_grant_bits_data[56] = io_outer_grant_bits_data[56];
assign io_inner_grant_bits_data[55] = io_outer_grant_bits_data[55];
assign io_inner_grant_bits_data[54] = io_outer_grant_bits_data[54];
assign io_inner_grant_bits_data[53] = io_outer_grant_bits_data[53];
assign io_inner_grant_bits_data[52] = io_outer_grant_bits_data[52];
assign io_inner_grant_bits_data[51] = io_outer_grant_bits_data[51];
assign io_inner_grant_bits_data[50] = io_outer_grant_bits_data[50];
assign io_inner_grant_bits_data[49] = io_outer_grant_bits_data[49];
assign io_inner_grant_bits_data[48] = io_outer_grant_bits_data[48];
assign io_inner_grant_bits_data[47] = io_outer_grant_bits_data[47];
assign io_inner_grant_bits_data[46] = io_outer_grant_bits_data[46];
assign io_inner_grant_bits_data[45] = io_outer_grant_bits_data[45];
assign io_inner_grant_bits_data[44] = io_outer_grant_bits_data[44];
assign io_inner_grant_bits_data[43] = io_outer_grant_bits_data[43];
assign io_inner_grant_bits_data[42] = io_outer_grant_bits_data[42];
assign io_inner_grant_bits_data[41] = io_outer_grant_bits_data[41];
assign io_inner_grant_bits_data[40] = io_outer_grant_bits_data[40];
assign io_inner_grant_bits_data[39] = io_outer_grant_bits_data[39];
assign io_inner_grant_bits_data[38] = io_outer_grant_bits_data[38];
assign io_inner_grant_bits_data[37] = io_outer_grant_bits_data[37];
assign io_inner_grant_bits_data[36] = io_outer_grant_bits_data[36];
assign io_inner_grant_bits_data[35] = io_outer_grant_bits_data[35];
assign io_inner_grant_bits_data[34] = io_outer_grant_bits_data[34];
assign io_inner_grant_bits_data[33] = io_outer_grant_bits_data[33];
assign io_inner_grant_bits_data[32] = io_outer_grant_bits_data[32];
assign io_inner_grant_bits_data[31] = io_outer_grant_bits_data[31];
assign io_inner_grant_bits_data[30] = io_outer_grant_bits_data[30];
assign io_inner_grant_bits_data[29] = io_outer_grant_bits_data[29];
assign io_inner_grant_bits_data[28] = io_outer_grant_bits_data[28];
assign io_inner_grant_bits_data[27] = io_outer_grant_bits_data[27];
assign io_inner_grant_bits_data[26] = io_outer_grant_bits_data[26];
assign io_inner_grant_bits_data[25] = io_outer_grant_bits_data[25];
assign io_inner_grant_bits_data[24] = io_outer_grant_bits_data[24];
assign io_inner_grant_bits_data[23] = io_outer_grant_bits_data[23];
assign io_inner_grant_bits_data[22] = io_outer_grant_bits_data[22];
assign io_inner_grant_bits_data[21] = io_outer_grant_bits_data[21];
assign io_inner_grant_bits_data[20] = io_outer_grant_bits_data[20];
assign io_inner_grant_bits_data[19] = io_outer_grant_bits_data[19];
assign io_inner_grant_bits_data[18] = io_outer_grant_bits_data[18];
assign io_inner_grant_bits_data[17] = io_outer_grant_bits_data[17];
assign io_inner_grant_bits_data[16] = io_outer_grant_bits_data[16];
assign io_inner_grant_bits_data[15] = io_outer_grant_bits_data[15];
assign io_inner_grant_bits_data[14] = io_outer_grant_bits_data[14];
assign io_inner_grant_bits_data[13] = io_outer_grant_bits_data[13];
assign io_inner_grant_bits_data[12] = io_outer_grant_bits_data[12];
assign io_inner_grant_bits_data[11] = io_outer_grant_bits_data[11];
assign io_inner_grant_bits_data[10] = io_outer_grant_bits_data[10];
assign io_inner_grant_bits_data[9] = io_outer_grant_bits_data[9];
assign io_inner_grant_bits_data[8] = io_outer_grant_bits_data[8];
assign io_inner_grant_bits_data[7] = io_outer_grant_bits_data[7];
assign io_inner_grant_bits_data[6] = io_outer_grant_bits_data[6];
assign io_inner_grant_bits_data[5] = io_outer_grant_bits_data[5];
assign io_inner_grant_bits_data[4] = io_outer_grant_bits_data[4];
assign io_inner_grant_bits_data[3] = io_outer_grant_bits_data[3];
assign io_inner_grant_bits_data[2] = io_outer_grant_bits_data[2];
assign io_inner_grant_bits_data[1] = io_outer_grant_bits_data[1];
assign io_inner_grant_bits_data[0] = io_outer_grant_bits_data[0];
assign io_inner_probe_valid = io_outer_probe_valid;
assign io_inner_probe_bits_addr_block[25] = io_outer_probe_bits_addr_block[25];
assign io_inner_probe_bits_addr_block[24] = io_outer_probe_bits_addr_block[24];
assign io_inner_probe_bits_addr_block[23] = io_outer_probe_bits_addr_block[23];
assign io_inner_probe_bits_addr_block[22] = io_outer_probe_bits_addr_block[22];
assign io_inner_probe_bits_addr_block[21] = io_outer_probe_bits_addr_block[21];
assign io_inner_probe_bits_addr_block[20] = io_outer_probe_bits_addr_block[20];
assign io_inner_probe_bits_addr_block[19] = io_outer_probe_bits_addr_block[19];
assign io_inner_probe_bits_addr_block[18] = io_outer_probe_bits_addr_block[18];
assign io_inner_probe_bits_addr_block[17] = io_outer_probe_bits_addr_block[17];
assign io_inner_probe_bits_addr_block[16] = io_outer_probe_bits_addr_block[16];
assign io_inner_probe_bits_addr_block[15] = io_outer_probe_bits_addr_block[15];
assign io_inner_probe_bits_addr_block[14] = io_outer_probe_bits_addr_block[14];
assign io_inner_probe_bits_addr_block[13] = io_outer_probe_bits_addr_block[13];
assign io_inner_probe_bits_addr_block[12] = io_outer_probe_bits_addr_block[12];
assign io_inner_probe_bits_addr_block[11] = io_outer_probe_bits_addr_block[11];
assign io_inner_probe_bits_addr_block[10] = io_outer_probe_bits_addr_block[10];
assign io_inner_probe_bits_addr_block[9] = io_outer_probe_bits_addr_block[9];
assign io_inner_probe_bits_addr_block[8] = io_outer_probe_bits_addr_block[8];
assign io_inner_probe_bits_addr_block[7] = io_outer_probe_bits_addr_block[7];
assign io_inner_probe_bits_addr_block[6] = io_outer_probe_bits_addr_block[6];
assign io_inner_probe_bits_addr_block[5] = io_outer_probe_bits_addr_block[5];
assign io_inner_probe_bits_addr_block[4] = io_outer_probe_bits_addr_block[4];
assign io_inner_probe_bits_addr_block[3] = io_outer_probe_bits_addr_block[3];
assign io_inner_probe_bits_addr_block[2] = io_outer_probe_bits_addr_block[2];
assign io_inner_probe_bits_addr_block[1] = io_outer_probe_bits_addr_block[1];
assign io_inner_probe_bits_addr_block[0] = io_outer_probe_bits_addr_block[0];
assign io_inner_probe_bits_p_type[1] = io_outer_probe_bits_p_type[1];
assign io_inner_probe_bits_p_type[0] = io_outer_probe_bits_p_type[0];
assign io_inner_release_ready = io_outer_release_ready;
assign io_outer_acquire_valid = io_inner_acquire_valid;
assign io_outer_acquire_bits_addr_block[25] = io_inner_acquire_bits_addr_block[25];
assign io_outer_acquire_bits_addr_block[24] = io_inner_acquire_bits_addr_block[24];
assign io_outer_acquire_bits_addr_block[23] = io_inner_acquire_bits_addr_block[23];
assign io_outer_acquire_bits_addr_block[22] = io_inner_acquire_bits_addr_block[22];
assign io_outer_acquire_bits_addr_block[21] = io_inner_acquire_bits_addr_block[21];
assign io_outer_acquire_bits_addr_block[20] = io_inner_acquire_bits_addr_block[20];
assign io_outer_acquire_bits_addr_block[19] = io_inner_acquire_bits_addr_block[19];
assign io_outer_acquire_bits_addr_block[18] = io_inner_acquire_bits_addr_block[18];
assign io_outer_acquire_bits_addr_block[17] = io_inner_acquire_bits_addr_block[17];
assign io_outer_acquire_bits_addr_block[16] = io_inner_acquire_bits_addr_block[16];
assign io_outer_acquire_bits_addr_block[15] = io_inner_acquire_bits_addr_block[15];
assign io_outer_acquire_bits_addr_block[14] = io_inner_acquire_bits_addr_block[14];
assign io_outer_acquire_bits_addr_block[13] = io_inner_acquire_bits_addr_block[13];
assign io_outer_acquire_bits_addr_block[12] = io_inner_acquire_bits_addr_block[12];
assign io_outer_acquire_bits_addr_block[11] = io_inner_acquire_bits_addr_block[11];
assign io_outer_acquire_bits_addr_block[10] = io_inner_acquire_bits_addr_block[10];
assign io_outer_acquire_bits_addr_block[9] = io_inner_acquire_bits_addr_block[9];
assign io_outer_acquire_bits_addr_block[8] = io_inner_acquire_bits_addr_block[8];
assign io_outer_acquire_bits_addr_block[7] = io_inner_acquire_bits_addr_block[7];
assign io_outer_acquire_bits_addr_block[6] = io_inner_acquire_bits_addr_block[6];
assign io_outer_acquire_bits_addr_block[5] = io_inner_acquire_bits_addr_block[5];
assign io_outer_acquire_bits_addr_block[4] = io_inner_acquire_bits_addr_block[4];
assign io_outer_acquire_bits_addr_block[3] = io_inner_acquire_bits_addr_block[3];
assign io_outer_acquire_bits_addr_block[2] = io_inner_acquire_bits_addr_block[2];
assign io_outer_acquire_bits_addr_block[1] = io_inner_acquire_bits_addr_block[1];
assign io_outer_acquire_bits_addr_block[0] = io_inner_acquire_bits_addr_block[0];
assign io_outer_acquire_bits_client_xact_id[3] = io_inner_acquire_bits_client_xact_id[3];
assign io_outer_acquire_bits_client_xact_id[2] = io_inner_acquire_bits_client_xact_id[2];
assign io_outer_acquire_bits_client_xact_id[1] = io_inner_acquire_bits_client_xact_id[1];
assign io_outer_acquire_bits_client_xact_id[0] = io_inner_acquire_bits_client_xact_id[0];
assign io_outer_acquire_bits_addr_beat[1] = io_inner_acquire_bits_addr_beat[1];
assign io_outer_acquire_bits_addr_beat[0] = io_inner_acquire_bits_addr_beat[0];
assign io_outer_acquire_bits_is_builtin_type = io_inner_acquire_bits_is_builtin_type;
assign io_outer_acquire_bits_a_type[2] = io_inner_acquire_bits_a_type[2];
assign io_outer_acquire_bits_a_type[1] = io_inner_acquire_bits_a_type[1];
assign io_outer_acquire_bits_a_type[0] = io_inner_acquire_bits_a_type[0];
assign io_outer_acquire_bits_union[16] = io_inner_acquire_bits_union[16];
assign io_outer_acquire_bits_union[15] = io_inner_acquire_bits_union[15];
assign io_outer_acquire_bits_union[14] = io_inner_acquire_bits_union[14];
assign io_outer_acquire_bits_union[13] = io_inner_acquire_bits_union[13];
assign io_outer_acquire_bits_union[12] = io_inner_acquire_bits_union[12];
assign io_outer_acquire_bits_union[11] = io_inner_acquire_bits_union[11];
assign io_outer_acquire_bits_union[10] = io_inner_acquire_bits_union[10];
assign io_outer_acquire_bits_union[9] = io_inner_acquire_bits_union[9];
assign io_outer_acquire_bits_union[8] = io_inner_acquire_bits_union[8];
assign io_outer_acquire_bits_union[7] = io_inner_acquire_bits_union[7];
assign io_outer_acquire_bits_union[6] = io_inner_acquire_bits_union[6];
assign io_outer_acquire_bits_union[5] = io_inner_acquire_bits_union[5];
assign io_outer_acquire_bits_union[4] = io_inner_acquire_bits_union[4];
assign io_outer_acquire_bits_union[3] = io_inner_acquire_bits_union[3];
assign io_outer_acquire_bits_union[2] = io_inner_acquire_bits_union[2];
assign io_outer_acquire_bits_union[1] = io_inner_acquire_bits_union[1];
assign io_outer_acquire_bits_union[0] = io_inner_acquire_bits_union[0];
assign io_outer_acquire_bits_data[127] = io_inner_acquire_bits_data[127];
assign io_outer_acquire_bits_data[126] = io_inner_acquire_bits_data[126];
assign io_outer_acquire_bits_data[125] = io_inner_acquire_bits_data[125];
assign io_outer_acquire_bits_data[124] = io_inner_acquire_bits_data[124];
assign io_outer_acquire_bits_data[123] = io_inner_acquire_bits_data[123];
assign io_outer_acquire_bits_data[122] = io_inner_acquire_bits_data[122];
assign io_outer_acquire_bits_data[121] = io_inner_acquire_bits_data[121];
assign io_outer_acquire_bits_data[120] = io_inner_acquire_bits_data[120];
assign io_outer_acquire_bits_data[119] = io_inner_acquire_bits_data[119];
assign io_outer_acquire_bits_data[118] = io_inner_acquire_bits_data[118];
assign io_outer_acquire_bits_data[117] = io_inner_acquire_bits_data[117];
assign io_outer_acquire_bits_data[116] = io_inner_acquire_bits_data[116];
assign io_outer_acquire_bits_data[115] = io_inner_acquire_bits_data[115];
assign io_outer_acquire_bits_data[114] = io_inner_acquire_bits_data[114];
assign io_outer_acquire_bits_data[113] = io_inner_acquire_bits_data[113];
assign io_outer_acquire_bits_data[112] = io_inner_acquire_bits_data[112];
assign io_outer_acquire_bits_data[111] = io_inner_acquire_bits_data[111];
assign io_outer_acquire_bits_data[110] = io_inner_acquire_bits_data[110];
assign io_outer_acquire_bits_data[109] = io_inner_acquire_bits_data[109];
assign io_outer_acquire_bits_data[108] = io_inner_acquire_bits_data[108];
assign io_outer_acquire_bits_data[107] = io_inner_acquire_bits_data[107];
assign io_outer_acquire_bits_data[106] = io_inner_acquire_bits_data[106];
assign io_outer_acquire_bits_data[105] = io_inner_acquire_bits_data[105];
assign io_outer_acquire_bits_data[104] = io_inner_acquire_bits_data[104];
assign io_outer_acquire_bits_data[103] = io_inner_acquire_bits_data[103];
assign io_outer_acquire_bits_data[102] = io_inner_acquire_bits_data[102];
assign io_outer_acquire_bits_data[101] = io_inner_acquire_bits_data[101];
assign io_outer_acquire_bits_data[100] = io_inner_acquire_bits_data[100];
assign io_outer_acquire_bits_data[99] = io_inner_acquire_bits_data[99];
assign io_outer_acquire_bits_data[98] = io_inner_acquire_bits_data[98];
assign io_outer_acquire_bits_data[97] = io_inner_acquire_bits_data[97];
assign io_outer_acquire_bits_data[96] = io_inner_acquire_bits_data[96];
assign io_outer_acquire_bits_data[95] = io_inner_acquire_bits_data[95];
assign io_outer_acquire_bits_data[94] = io_inner_acquire_bits_data[94];
assign io_outer_acquire_bits_data[93] = io_inner_acquire_bits_data[93];
assign io_outer_acquire_bits_data[92] = io_inner_acquire_bits_data[92];
assign io_outer_acquire_bits_data[91] = io_inner_acquire_bits_data[91];
assign io_outer_acquire_bits_data[90] = io_inner_acquire_bits_data[90];
assign io_outer_acquire_bits_data[89] = io_inner_acquire_bits_data[89];
assign io_outer_acquire_bits_data[88] = io_inner_acquire_bits_data[88];
assign io_outer_acquire_bits_data[87] = io_inner_acquire_bits_data[87];
assign io_outer_acquire_bits_data[86] = io_inner_acquire_bits_data[86];
assign io_outer_acquire_bits_data[85] = io_inner_acquire_bits_data[85];
assign io_outer_acquire_bits_data[84] = io_inner_acquire_bits_data[84];
assign io_outer_acquire_bits_data[83] = io_inner_acquire_bits_data[83];
assign io_outer_acquire_bits_data[82] = io_inner_acquire_bits_data[82];
assign io_outer_acquire_bits_data[81] = io_inner_acquire_bits_data[81];
assign io_outer_acquire_bits_data[80] = io_inner_acquire_bits_data[80];
assign io_outer_acquire_bits_data[79] = io_inner_acquire_bits_data[79];
assign io_outer_acquire_bits_data[78] = io_inner_acquire_bits_data[78];
assign io_outer_acquire_bits_data[77] = io_inner_acquire_bits_data[77];
assign io_outer_acquire_bits_data[76] = io_inner_acquire_bits_data[76];
assign io_outer_acquire_bits_data[75] = io_inner_acquire_bits_data[75];
assign io_outer_acquire_bits_data[74] = io_inner_acquire_bits_data[74];
assign io_outer_acquire_bits_data[73] = io_inner_acquire_bits_data[73];
assign io_outer_acquire_bits_data[72] = io_inner_acquire_bits_data[72];
assign io_outer_acquire_bits_data[71] = io_inner_acquire_bits_data[71];
assign io_outer_acquire_bits_data[70] = io_inner_acquire_bits_data[70];
assign io_outer_acquire_bits_data[69] = io_inner_acquire_bits_data[69];
assign io_outer_acquire_bits_data[68] = io_inner_acquire_bits_data[68];
assign io_outer_acquire_bits_data[67] = io_inner_acquire_bits_data[67];
assign io_outer_acquire_bits_data[66] = io_inner_acquire_bits_data[66];
assign io_outer_acquire_bits_data[65] = io_inner_acquire_bits_data[65];
assign io_outer_acquire_bits_data[64] = io_inner_acquire_bits_data[64];
assign io_outer_acquire_bits_data[63] = io_inner_acquire_bits_data[63];
assign io_outer_acquire_bits_data[62] = io_inner_acquire_bits_data[62];
assign io_outer_acquire_bits_data[61] = io_inner_acquire_bits_data[61];
assign io_outer_acquire_bits_data[60] = io_inner_acquire_bits_data[60];
assign io_outer_acquire_bits_data[59] = io_inner_acquire_bits_data[59];
assign io_outer_acquire_bits_data[58] = io_inner_acquire_bits_data[58];
assign io_outer_acquire_bits_data[57] = io_inner_acquire_bits_data[57];
assign io_outer_acquire_bits_data[56] = io_inner_acquire_bits_data[56];
assign io_outer_acquire_bits_data[55] = io_inner_acquire_bits_data[55];
assign io_outer_acquire_bits_data[54] = io_inner_acquire_bits_data[54];
assign io_outer_acquire_bits_data[53] = io_inner_acquire_bits_data[53];
assign io_outer_acquire_bits_data[52] = io_inner_acquire_bits_data[52];
assign io_outer_acquire_bits_data[51] = io_inner_acquire_bits_data[51];
assign io_outer_acquire_bits_data[50] = io_inner_acquire_bits_data[50];
assign io_outer_acquire_bits_data[49] = io_inner_acquire_bits_data[49];
assign io_outer_acquire_bits_data[48] = io_inner_acquire_bits_data[48];
assign io_outer_acquire_bits_data[47] = io_inner_acquire_bits_data[47];
assign io_outer_acquire_bits_data[46] = io_inner_acquire_bits_data[46];
assign io_outer_acquire_bits_data[45] = io_inner_acquire_bits_data[45];
assign io_outer_acquire_bits_data[44] = io_inner_acquire_bits_data[44];
assign io_outer_acquire_bits_data[43] = io_inner_acquire_bits_data[43];
assign io_outer_acquire_bits_data[42] = io_inner_acquire_bits_data[42];
assign io_outer_acquire_bits_data[41] = io_inner_acquire_bits_data[41];
assign io_outer_acquire_bits_data[40] = io_inner_acquire_bits_data[40];
assign io_outer_acquire_bits_data[39] = io_inner_acquire_bits_data[39];
assign io_outer_acquire_bits_data[38] = io_inner_acquire_bits_data[38];
assign io_outer_acquire_bits_data[37] = io_inner_acquire_bits_data[37];
assign io_outer_acquire_bits_data[36] = io_inner_acquire_bits_data[36];
assign io_outer_acquire_bits_data[35] = io_inner_acquire_bits_data[35];
assign io_outer_acquire_bits_data[34] = io_inner_acquire_bits_data[34];
assign io_outer_acquire_bits_data[33] = io_inner_acquire_bits_data[33];
assign io_outer_acquire_bits_data[32] = io_inner_acquire_bits_data[32];
assign io_outer_acquire_bits_data[31] = io_inner_acquire_bits_data[31];
assign io_outer_acquire_bits_data[30] = io_inner_acquire_bits_data[30];
assign io_outer_acquire_bits_data[29] = io_inner_acquire_bits_data[29];
assign io_outer_acquire_bits_data[28] = io_inner_acquire_bits_data[28];
assign io_outer_acquire_bits_data[27] = io_inner_acquire_bits_data[27];
assign io_outer_acquire_bits_data[26] = io_inner_acquire_bits_data[26];
assign io_outer_acquire_bits_data[25] = io_inner_acquire_bits_data[25];
assign io_outer_acquire_bits_data[24] = io_inner_acquire_bits_data[24];
assign io_outer_acquire_bits_data[23] = io_inner_acquire_bits_data[23];
assign io_outer_acquire_bits_data[22] = io_inner_acquire_bits_data[22];
assign io_outer_acquire_bits_data[21] = io_inner_acquire_bits_data[21];
assign io_outer_acquire_bits_data[20] = io_inner_acquire_bits_data[20];
assign io_outer_acquire_bits_data[19] = io_inner_acquire_bits_data[19];
assign io_outer_acquire_bits_data[18] = io_inner_acquire_bits_data[18];
assign io_outer_acquire_bits_data[17] = io_inner_acquire_bits_data[17];
assign io_outer_acquire_bits_data[16] = io_inner_acquire_bits_data[16];
assign io_outer_acquire_bits_data[15] = io_inner_acquire_bits_data[15];
assign io_outer_acquire_bits_data[14] = io_inner_acquire_bits_data[14];
assign io_outer_acquire_bits_data[13] = io_inner_acquire_bits_data[13];
assign io_outer_acquire_bits_data[12] = io_inner_acquire_bits_data[12];
assign io_outer_acquire_bits_data[11] = io_inner_acquire_bits_data[11];
assign io_outer_acquire_bits_data[10] = io_inner_acquire_bits_data[10];
assign io_outer_acquire_bits_data[9] = io_inner_acquire_bits_data[9];
assign io_outer_acquire_bits_data[8] = io_inner_acquire_bits_data[8];
assign io_outer_acquire_bits_data[7] = io_inner_acquire_bits_data[7];
assign io_outer_acquire_bits_data[6] = io_inner_acquire_bits_data[6];
assign io_outer_acquire_bits_data[5] = io_inner_acquire_bits_data[5];
assign io_outer_acquire_bits_data[4] = io_inner_acquire_bits_data[4];
assign io_outer_acquire_bits_data[3] = io_inner_acquire_bits_data[3];
assign io_outer_acquire_bits_data[2] = io_inner_acquire_bits_data[2];
assign io_outer_acquire_bits_data[1] = io_inner_acquire_bits_data[1];
assign io_outer_acquire_bits_data[0] = io_inner_acquire_bits_data[0];
assign io_outer_grant_ready = io_inner_grant_ready;
assign io_outer_probe_ready = io_inner_probe_ready;
assign io_outer_release_valid = io_inner_release_valid;
assign io_outer_release_bits_addr_beat[1] = io_inner_release_bits_addr_beat[1];
assign io_outer_release_bits_addr_beat[0] = io_inner_release_bits_addr_beat[0];
assign io_outer_release_bits_addr_block[25] = io_inner_release_bits_addr_block[25];
assign io_outer_release_bits_addr_block[24] = io_inner_release_bits_addr_block[24];
assign io_outer_release_bits_addr_block[23] = io_inner_release_bits_addr_block[23];
assign io_outer_release_bits_addr_block[22] = io_inner_release_bits_addr_block[22];
assign io_outer_release_bits_addr_block[21] = io_inner_release_bits_addr_block[21];
assign io_outer_release_bits_addr_block[20] = io_inner_release_bits_addr_block[20];
assign io_outer_release_bits_addr_block[19] = io_inner_release_bits_addr_block[19];
assign io_outer_release_bits_addr_block[18] = io_inner_release_bits_addr_block[18];
assign io_outer_release_bits_addr_block[17] = io_inner_release_bits_addr_block[17];
assign io_outer_release_bits_addr_block[16] = io_inner_release_bits_addr_block[16];
assign io_outer_release_bits_addr_block[15] = io_inner_release_bits_addr_block[15];
assign io_outer_release_bits_addr_block[14] = io_inner_release_bits_addr_block[14];
assign io_outer_release_bits_addr_block[13] = io_inner_release_bits_addr_block[13];
assign io_outer_release_bits_addr_block[12] = io_inner_release_bits_addr_block[12];
assign io_outer_release_bits_addr_block[11] = io_inner_release_bits_addr_block[11];
assign io_outer_release_bits_addr_block[10] = io_inner_release_bits_addr_block[10];
assign io_outer_release_bits_addr_block[9] = io_inner_release_bits_addr_block[9];
assign io_outer_release_bits_addr_block[8] = io_inner_release_bits_addr_block[8];
assign io_outer_release_bits_addr_block[7] = io_inner_release_bits_addr_block[7];
assign io_outer_release_bits_addr_block[6] = io_inner_release_bits_addr_block[6];
assign io_outer_release_bits_addr_block[5] = io_inner_release_bits_addr_block[5];
assign io_outer_release_bits_addr_block[4] = io_inner_release_bits_addr_block[4];
assign io_outer_release_bits_addr_block[3] = io_inner_release_bits_addr_block[3];
assign io_outer_release_bits_addr_block[2] = io_inner_release_bits_addr_block[2];
assign io_outer_release_bits_addr_block[1] = io_inner_release_bits_addr_block[1];
assign io_outer_release_bits_addr_block[0] = io_inner_release_bits_addr_block[0];
assign io_outer_release_bits_client_xact_id[3] = io_inner_release_bits_client_xact_id[3];
assign io_outer_release_bits_client_xact_id[2] = io_inner_release_bits_client_xact_id[2];
assign io_outer_release_bits_client_xact_id[1] = io_inner_release_bits_client_xact_id[1];
assign io_outer_release_bits_client_xact_id[0] = io_inner_release_bits_client_xact_id[0];
assign io_outer_release_bits_voluntary = io_inner_release_bits_voluntary;
assign io_outer_release_bits_r_type[2] = io_inner_release_bits_r_type[2];
assign io_outer_release_bits_r_type[1] = io_inner_release_bits_r_type[1];
assign io_outer_release_bits_r_type[0] = io_inner_release_bits_r_type[0];
assign io_outer_release_bits_data[127] = io_inner_release_bits_data[127];
assign io_outer_release_bits_data[126] = io_inner_release_bits_data[126];
assign io_outer_release_bits_data[125] = io_inner_release_bits_data[125];
assign io_outer_release_bits_data[124] = io_inner_release_bits_data[124];
assign io_outer_release_bits_data[123] = io_inner_release_bits_data[123];
assign io_outer_release_bits_data[122] = io_inner_release_bits_data[122];
assign io_outer_release_bits_data[121] = io_inner_release_bits_data[121];
assign io_outer_release_bits_data[120] = io_inner_release_bits_data[120];
assign io_outer_release_bits_data[119] = io_inner_release_bits_data[119];
assign io_outer_release_bits_data[118] = io_inner_release_bits_data[118];
assign io_outer_release_bits_data[117] = io_inner_release_bits_data[117];
assign io_outer_release_bits_data[116] = io_inner_release_bits_data[116];
assign io_outer_release_bits_data[115] = io_inner_release_bits_data[115];
assign io_outer_release_bits_data[114] = io_inner_release_bits_data[114];
assign io_outer_release_bits_data[113] = io_inner_release_bits_data[113];
assign io_outer_release_bits_data[112] = io_inner_release_bits_data[112];
assign io_outer_release_bits_data[111] = io_inner_release_bits_data[111];
assign io_outer_release_bits_data[110] = io_inner_release_bits_data[110];
assign io_outer_release_bits_data[109] = io_inner_release_bits_data[109];
assign io_outer_release_bits_data[108] = io_inner_release_bits_data[108];
assign io_outer_release_bits_data[107] = io_inner_release_bits_data[107];
assign io_outer_release_bits_data[106] = io_inner_release_bits_data[106];
assign io_outer_release_bits_data[105] = io_inner_release_bits_data[105];
assign io_outer_release_bits_data[104] = io_inner_release_bits_data[104];
assign io_outer_release_bits_data[103] = io_inner_release_bits_data[103];
assign io_outer_release_bits_data[102] = io_inner_release_bits_data[102];
assign io_outer_release_bits_data[101] = io_inner_release_bits_data[101];
assign io_outer_release_bits_data[100] = io_inner_release_bits_data[100];
assign io_outer_release_bits_data[99] = io_inner_release_bits_data[99];
assign io_outer_release_bits_data[98] = io_inner_release_bits_data[98];
assign io_outer_release_bits_data[97] = io_inner_release_bits_data[97];
assign io_outer_release_bits_data[96] = io_inner_release_bits_data[96];
assign io_outer_release_bits_data[95] = io_inner_release_bits_data[95];
assign io_outer_release_bits_data[94] = io_inner_release_bits_data[94];
assign io_outer_release_bits_data[93] = io_inner_release_bits_data[93];
assign io_outer_release_bits_data[92] = io_inner_release_bits_data[92];
assign io_outer_release_bits_data[91] = io_inner_release_bits_data[91];
assign io_outer_release_bits_data[90] = io_inner_release_bits_data[90];
assign io_outer_release_bits_data[89] = io_inner_release_bits_data[89];
assign io_outer_release_bits_data[88] = io_inner_release_bits_data[88];
assign io_outer_release_bits_data[87] = io_inner_release_bits_data[87];
assign io_outer_release_bits_data[86] = io_inner_release_bits_data[86];
assign io_outer_release_bits_data[85] = io_inner_release_bits_data[85];
assign io_outer_release_bits_data[84] = io_inner_release_bits_data[84];
assign io_outer_release_bits_data[83] = io_inner_release_bits_data[83];
assign io_outer_release_bits_data[82] = io_inner_release_bits_data[82];
assign io_outer_release_bits_data[81] = io_inner_release_bits_data[81];
assign io_outer_release_bits_data[80] = io_inner_release_bits_data[80];
assign io_outer_release_bits_data[79] = io_inner_release_bits_data[79];
assign io_outer_release_bits_data[78] = io_inner_release_bits_data[78];
assign io_outer_release_bits_data[77] = io_inner_release_bits_data[77];
assign io_outer_release_bits_data[76] = io_inner_release_bits_data[76];
assign io_outer_release_bits_data[75] = io_inner_release_bits_data[75];
assign io_outer_release_bits_data[74] = io_inner_release_bits_data[74];
assign io_outer_release_bits_data[73] = io_inner_release_bits_data[73];
assign io_outer_release_bits_data[72] = io_inner_release_bits_data[72];
assign io_outer_release_bits_data[71] = io_inner_release_bits_data[71];
assign io_outer_release_bits_data[70] = io_inner_release_bits_data[70];
assign io_outer_release_bits_data[69] = io_inner_release_bits_data[69];
assign io_outer_release_bits_data[68] = io_inner_release_bits_data[68];
assign io_outer_release_bits_data[67] = io_inner_release_bits_data[67];
assign io_outer_release_bits_data[66] = io_inner_release_bits_data[66];
assign io_outer_release_bits_data[65] = io_inner_release_bits_data[65];
assign io_outer_release_bits_data[64] = io_inner_release_bits_data[64];
assign io_outer_release_bits_data[63] = io_inner_release_bits_data[63];
assign io_outer_release_bits_data[62] = io_inner_release_bits_data[62];
assign io_outer_release_bits_data[61] = io_inner_release_bits_data[61];
assign io_outer_release_bits_data[60] = io_inner_release_bits_data[60];
assign io_outer_release_bits_data[59] = io_inner_release_bits_data[59];
assign io_outer_release_bits_data[58] = io_inner_release_bits_data[58];
assign io_outer_release_bits_data[57] = io_inner_release_bits_data[57];
assign io_outer_release_bits_data[56] = io_inner_release_bits_data[56];
assign io_outer_release_bits_data[55] = io_inner_release_bits_data[55];
assign io_outer_release_bits_data[54] = io_inner_release_bits_data[54];
assign io_outer_release_bits_data[53] = io_inner_release_bits_data[53];
assign io_outer_release_bits_data[52] = io_inner_release_bits_data[52];
assign io_outer_release_bits_data[51] = io_inner_release_bits_data[51];
assign io_outer_release_bits_data[50] = io_inner_release_bits_data[50];
assign io_outer_release_bits_data[49] = io_inner_release_bits_data[49];
assign io_outer_release_bits_data[48] = io_inner_release_bits_data[48];
assign io_outer_release_bits_data[47] = io_inner_release_bits_data[47];
assign io_outer_release_bits_data[46] = io_inner_release_bits_data[46];
assign io_outer_release_bits_data[45] = io_inner_release_bits_data[45];
assign io_outer_release_bits_data[44] = io_inner_release_bits_data[44];
assign io_outer_release_bits_data[43] = io_inner_release_bits_data[43];
assign io_outer_release_bits_data[42] = io_inner_release_bits_data[42];
assign io_outer_release_bits_data[41] = io_inner_release_bits_data[41];
assign io_outer_release_bits_data[40] = io_inner_release_bits_data[40];
assign io_outer_release_bits_data[39] = io_inner_release_bits_data[39];
assign io_outer_release_bits_data[38] = io_inner_release_bits_data[38];
assign io_outer_release_bits_data[37] = io_inner_release_bits_data[37];
assign io_outer_release_bits_data[36] = io_inner_release_bits_data[36];
assign io_outer_release_bits_data[35] = io_inner_release_bits_data[35];
assign io_outer_release_bits_data[34] = io_inner_release_bits_data[34];
assign io_outer_release_bits_data[33] = io_inner_release_bits_data[33];
assign io_outer_release_bits_data[32] = io_inner_release_bits_data[32];
assign io_outer_release_bits_data[31] = io_inner_release_bits_data[31];
assign io_outer_release_bits_data[30] = io_inner_release_bits_data[30];
assign io_outer_release_bits_data[29] = io_inner_release_bits_data[29];
assign io_outer_release_bits_data[28] = io_inner_release_bits_data[28];
assign io_outer_release_bits_data[27] = io_inner_release_bits_data[27];
assign io_outer_release_bits_data[26] = io_inner_release_bits_data[26];
assign io_outer_release_bits_data[25] = io_inner_release_bits_data[25];
assign io_outer_release_bits_data[24] = io_inner_release_bits_data[24];
assign io_outer_release_bits_data[23] = io_inner_release_bits_data[23];
assign io_outer_release_bits_data[22] = io_inner_release_bits_data[22];
assign io_outer_release_bits_data[21] = io_inner_release_bits_data[21];
assign io_outer_release_bits_data[20] = io_inner_release_bits_data[20];
assign io_outer_release_bits_data[19] = io_inner_release_bits_data[19];
assign io_outer_release_bits_data[18] = io_inner_release_bits_data[18];
assign io_outer_release_bits_data[17] = io_inner_release_bits_data[17];
assign io_outer_release_bits_data[16] = io_inner_release_bits_data[16];
assign io_outer_release_bits_data[15] = io_inner_release_bits_data[15];
assign io_outer_release_bits_data[14] = io_inner_release_bits_data[14];
assign io_outer_release_bits_data[13] = io_inner_release_bits_data[13];
assign io_outer_release_bits_data[12] = io_inner_release_bits_data[12];
assign io_outer_release_bits_data[11] = io_inner_release_bits_data[11];
assign io_outer_release_bits_data[10] = io_inner_release_bits_data[10];
assign io_outer_release_bits_data[9] = io_inner_release_bits_data[9];
assign io_outer_release_bits_data[8] = io_inner_release_bits_data[8];
assign io_outer_release_bits_data[7] = io_inner_release_bits_data[7];
assign io_outer_release_bits_data[6] = io_inner_release_bits_data[6];
assign io_outer_release_bits_data[5] = io_inner_release_bits_data[5];
assign io_outer_release_bits_data[4] = io_inner_release_bits_data[4];
assign io_outer_release_bits_data[3] = io_inner_release_bits_data[3];
assign io_outer_release_bits_data[2] = io_inner_release_bits_data[2];
assign io_outer_release_bits_data[1] = io_inner_release_bits_data[1];
assign io_outer_release_bits_data[0] = io_inner_release_bits_data[0];
endmodule |
module ReorderQueue_0
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_data,
io_enq_bits_tag,
io_deq_valid,
io_deq_tag,
io_deq_data,
io_deq_matches
);
input [3:0] io_enq_bits_tag;
input [3:0] io_deq_tag;
input clk;
input reset;
input io_enq_valid;
input io_enq_bits_data;
input io_deq_valid;
output io_enq_ready;
output io_deq_data;
output io_deq_matches;
wire io_enq_ready,io_deq_data,io_deq_matches,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
N32,N33,N34,N35,N36,T121,roq_matches_8,T117,T1,T115,T4,T114,N37,N38,N39,N40,N41,
N42,N43,N44,T19,T17,roq_matches_0,N45,roq_matches_1,N46,roq_matches_2,N47,
roq_matches_3,N48,roq_matches_4,N49,roq_matches_5,N50,roq_matches_6,N51,roq_matches_7,
N52,T31,T30,T33,T38,T37,T40,T43,T42,T45,T48,T47,T50,T53,T52,T55,T58,T57,T60,T63,
T62,T65,T68,T67,T70,T76,T74,T82,T80,T88,T86,T94,T92,T100,T98,T106,T104,T112,T110,
T119,T122,T123,T124,T125,T126,T127,N53,T129,N54,T151,T130,N55,T142,T131,N56,T133,
T138,T144,T147,T160,T152,T154,T157,T162,T165,T171,T175,T176,T177,T178,T179,T180,
T181,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,
N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,
N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,
N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,
N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138;
wire [8:0] T6,T21,T35,T135;
wire [3:0] T7,T8,T9,T10,T11,T12,T13,T22,T23,T24,T25,T26,T27,T28;
wire [3:2] T14,T29;
reg roq_free_8,roq_free_7,roq_free_6,roq_free_5,roq_free_4,roq_free_3,roq_free_2,
roq_free_1,roq_free_0,roq_data_0,roq_data_1,roq_data_2,roq_data_3,roq_data_4,
roq_data_5,roq_data_6,roq_data_7,roq_data_8;
reg [3:0] roq_tags_7,roq_tags_6,roq_tags_5,roq_tags_4,roq_tags_3,roq_tags_2,roq_tags_1,
roq_tags_0,roq_tags_8;
assign T31 = roq_tags_7 == io_deq_tag;
assign T38 = roq_tags_6 == io_deq_tag;
assign T43 = roq_tags_5 == io_deq_tag;
assign T48 = roq_tags_4 == io_deq_tag;
assign T53 = roq_tags_3 == io_deq_tag;
assign T58 = roq_tags_2 == io_deq_tag;
assign T63 = roq_tags_1 == io_deq_tag;
assign T68 = roq_tags_0 == io_deq_tag;
assign T117 = roq_tags_8 == io_deq_tag;
always @(posedge clk) begin
if(N60) begin
roq_free_8 <= N61;
end
end
always @(posedge clk) begin
if(N65) begin
roq_free_7 <= N66;
end
end
always @(posedge clk) begin
if(T33) begin
roq_tags_7[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T33) begin
roq_tags_7[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T33) begin
roq_tags_7[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T33) begin
roq_tags_7[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T40) begin
roq_tags_6[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T40) begin
roq_tags_6[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T40) begin
roq_tags_6[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T40) begin
roq_tags_6[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T45) begin
roq_tags_5[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T45) begin
roq_tags_5[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T45) begin
roq_tags_5[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T45) begin
roq_tags_5[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T50) begin
roq_tags_4[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T50) begin
roq_tags_4[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T50) begin
roq_tags_4[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T50) begin
roq_tags_4[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T55) begin
roq_tags_3[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T55) begin
roq_tags_3[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T55) begin
roq_tags_3[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T55) begin
roq_tags_3[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T60) begin
roq_tags_2[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T60) begin
roq_tags_2[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T60) begin
roq_tags_2[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T60) begin
roq_tags_2[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T65) begin
roq_tags_1[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T65) begin
roq_tags_1[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T65) begin
roq_tags_1[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T65) begin
roq_tags_1[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T70) begin
roq_tags_0[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T70) begin
roq_tags_0[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T70) begin
roq_tags_0[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T70) begin
roq_tags_0[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(N70) begin
roq_free_6 <= N71;
end
end
always @(posedge clk) begin
if(N75) begin
roq_free_5 <= N76;
end
end
always @(posedge clk) begin
if(N80) begin
roq_free_4 <= N81;
end
end
always @(posedge clk) begin
if(N85) begin
roq_free_3 <= N86;
end
end
always @(posedge clk) begin
if(N90) begin
roq_free_2 <= N91;
end
end
always @(posedge clk) begin
if(N95) begin
roq_free_1 <= N96;
end
end
always @(posedge clk) begin
if(N100) begin
roq_free_0 <= N101;
end
end
always @(posedge clk) begin
if(T119) begin
roq_tags_8[3] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(T119) begin
roq_tags_8[2] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(T119) begin
roq_tags_8[1] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(T119) begin
roq_tags_8[0] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(T133) begin
roq_data_0 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T138) begin
roq_data_1 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T144) begin
roq_data_2 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T147) begin
roq_data_3 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T154) begin
roq_data_4 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T157) begin
roq_data_5 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T162) begin
roq_data_6 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T165) begin
roq_data_7 <= io_enq_bits_data;
end
end
always @(posedge clk) begin
if(T171) begin
roq_data_8 <= io_enq_bits_data;
end
end
assign T35 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << T7;
assign T135 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << T7;
assign T6 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << T7;
assign T21 = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1 } << T22;
assign T7 = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? T8 : 1'b0;
assign N0 = roq_free_0;
assign N1 = N37;
assign T8 = (N2)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N3)? T9 : 1'b0;
assign N2 = roq_free_1;
assign N3 = N38;
assign T9 = (N4)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N5)? T10 : 1'b0;
assign N4 = roq_free_2;
assign N5 = N39;
assign T10 = (N6)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N7)? T11 : 1'b0;
assign N6 = roq_free_3;
assign N7 = N40;
assign T11 = (N8)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N9)? T12 : 1'b0;
assign N8 = roq_free_4;
assign N9 = N41;
assign T12 = (N10)? { 1'b0, 1'b1, 1'b0, 1'b1 } :
(N11)? T13 : 1'b0;
assign N10 = roq_free_5;
assign N11 = N42;
assign T13 = (N12)? { 1'b0, 1'b1, 1'b1, 1'b0 } :
(N13)? { T14, T14[2:2], T14[2:2] } : 1'b0;
assign N12 = roq_free_6;
assign N13 = N43;
assign T22 = (N14)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N15)? T23 : 1'b0;
assign N14 = roq_matches_0;
assign N15 = N45;
assign T23 = (N16)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N17)? T24 : 1'b0;
assign N16 = roq_matches_1;
assign N17 = N46;
assign T24 = (N18)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N19)? T25 : 1'b0;
assign N18 = roq_matches_2;
assign N19 = N47;
assign T25 = (N20)? { 1'b0, 1'b0, 1'b1, 1'b1 } :
(N21)? T26 : 1'b0;
assign N20 = roq_matches_3;
assign N21 = N48;
assign T26 = (N22)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N23)? T27 : 1'b0;
assign N22 = roq_matches_4;
assign N23 = N49;
assign T27 = (N24)? { 1'b0, 1'b1, 1'b0, 1'b1 } :
(N25)? T28 : 1'b0;
assign N24 = roq_matches_5;
assign N25 = N50;
assign T28 = (N26)? { 1'b0, 1'b1, 1'b1, 1'b0 } :
(N27)? { T29, T29[2:2], T29[2:2] } : 1'b0;
assign N26 = roq_matches_6;
assign N27 = N51;
assign io_deq_data = (N28)? roq_data_8 :
(N29)? T129 : 1'b0;
assign N28 = T22[3];
assign N29 = N53;
assign T129 = (N30)? T151 :
(N31)? T130 : 1'b0;
assign N30 = T22[2];
assign N31 = N54;
assign T130 = (N32)? T142 :
(N33)? T131 : 1'b0;
assign N32 = T22[1];
assign N33 = N55;
assign T131 = (N34)? roq_data_1 :
(N35)? roq_data_0 : 1'b0;
assign N34 = T22[0];
assign N35 = N56;
assign T142 = (N34)? roq_data_3 :
(N35)? roq_data_2 : 1'b0;
assign T151 = (N32)? T160 :
(N33)? T152 : 1'b0;
assign T152 = (N34)? roq_data_5 :
(N35)? roq_data_4 : 1'b0;
assign T160 = (N34)? roq_data_7 :
(N35)? roq_data_6 : 1'b0;
assign N60 = (N36)? 1'b1 :
(N103)? 1'b1 :
(N106)? 1'b1 :
(N59)? 1'b0 : 1'b0;
assign N36 = reset;
assign N61 = (N36)? 1'b1 :
(N103)? 1'b1 :
(N106)? 1'b0 : 1'b0;
assign N65 = (N36)? 1'b1 :
(N107)? 1'b1 :
(N110)? 1'b1 :
(N64)? 1'b0 : 1'b0;
assign N66 = (N36)? 1'b1 :
(N107)? 1'b1 :
(N110)? 1'b0 : 1'b0;
assign N70 = (N36)? 1'b1 :
(N111)? 1'b1 :
(N114)? 1'b1 :
(N69)? 1'b0 : 1'b0;
assign N71 = (N36)? 1'b1 :
(N111)? 1'b1 :
(N114)? 1'b0 : 1'b0;
assign N75 = (N36)? 1'b1 :
(N115)? 1'b1 :
(N118)? 1'b1 :
(N74)? 1'b0 : 1'b0;
assign N76 = (N36)? 1'b1 :
(N115)? 1'b1 :
(N118)? 1'b0 : 1'b0;
assign N80 = (N36)? 1'b1 :
(N119)? 1'b1 :
(N122)? 1'b1 :
(N79)? 1'b0 : 1'b0;
assign N81 = (N36)? 1'b1 :
(N119)? 1'b1 :
(N122)? 1'b0 : 1'b0;
assign N85 = (N36)? 1'b1 :
(N123)? 1'b1 :
(N126)? 1'b1 :
(N84)? 1'b0 : 1'b0;
assign N86 = (N36)? 1'b1 :
(N123)? 1'b1 :
(N126)? 1'b0 : 1'b0;
assign N90 = (N36)? 1'b1 :
(N127)? 1'b1 :
(N130)? 1'b1 :
(N89)? 1'b0 : 1'b0;
assign N91 = (N36)? 1'b1 :
(N127)? 1'b1 :
(N130)? 1'b0 : 1'b0;
assign N95 = (N36)? 1'b1 :
(N131)? 1'b1 :
(N134)? 1'b1 :
(N94)? 1'b0 : 1'b0;
assign N96 = (N36)? 1'b1 :
(N131)? 1'b1 :
(N134)? 1'b0 : 1'b0;
assign N100 = (N36)? 1'b1 :
(N135)? 1'b1 :
(N138)? 1'b1 :
(N99)? 1'b0 : 1'b0;
assign N101 = (N36)? 1'b1 :
(N135)? 1'b1 :
(N138)? 1'b0 : 1'b0;
assign io_deq_matches = T121 | roq_matches_8;
assign roq_matches_8 = T117 & T1;
assign T1 = ~roq_free_8;
assign T4 = T114 & T6[8];
assign N37 = ~roq_free_0;
assign N38 = ~roq_free_1;
assign N39 = ~roq_free_2;
assign N40 = ~roq_free_3;
assign N41 = ~roq_free_4;
assign N42 = ~roq_free_5;
assign N43 = ~roq_free_6;
assign N44 = ~roq_free_7;
assign T14[2] = roq_free_7;
assign T14[3] = N44;
assign T17 = T114 & T6[7];
assign T19 = io_deq_valid & T21[7];
assign N45 = ~roq_matches_0;
assign N46 = ~roq_matches_1;
assign N47 = ~roq_matches_2;
assign N48 = ~roq_matches_3;
assign N49 = ~roq_matches_4;
assign N50 = ~roq_matches_5;
assign N51 = ~roq_matches_6;
assign N52 = ~roq_matches_7;
assign T29[2] = roq_matches_7;
assign T29[3] = N52;
assign roq_matches_7 = T31 & T30;
assign T30 = ~roq_free_7;
assign T33 = T114 & T35[7];
assign roq_matches_6 = T38 & T37;
assign T37 = ~roq_free_6;
assign T40 = T114 & T35[6];
assign roq_matches_5 = T43 & T42;
assign T42 = ~roq_free_5;
assign T45 = T114 & T35[5];
assign roq_matches_4 = T48 & T47;
assign T47 = ~roq_free_4;
assign T50 = T114 & T35[4];
assign roq_matches_3 = T53 & T52;
assign T52 = ~roq_free_3;
assign T55 = T114 & T35[3];
assign roq_matches_2 = T58 & T57;
assign T57 = ~roq_free_2;
assign T60 = T114 & T35[2];
assign roq_matches_1 = T63 & T62;
assign T62 = ~roq_free_1;
assign T65 = T114 & T35[1];
assign roq_matches_0 = T68 & T67;
assign T67 = ~roq_free_0;
assign T70 = T114 & T35[0];
assign T74 = T114 & T6[6];
assign T76 = io_deq_valid & T21[6];
assign T80 = T114 & T6[5];
assign T82 = io_deq_valid & T21[5];
assign T86 = T114 & T6[4];
assign T88 = io_deq_valid & T21[4];
assign T92 = T114 & T6[3];
assign T94 = io_deq_valid & T21[3];
assign T98 = T114 & T6[2];
assign T100 = io_deq_valid & T21[2];
assign T104 = T114 & T6[1];
assign T106 = io_deq_valid & T21[1];
assign T110 = T114 & T6[0];
assign T112 = io_deq_valid & T21[0];
assign T114 = io_enq_valid & io_enq_ready;
assign T115 = io_deq_valid & T21[8];
assign T119 = T114 & T35[8];
assign T121 = T122 | roq_matches_7;
assign T122 = T123 | roq_matches_6;
assign T123 = T124 | roq_matches_5;
assign T124 = T125 | roq_matches_4;
assign T125 = T126 | roq_matches_3;
assign T126 = T127 | roq_matches_2;
assign T127 = roq_matches_0 | roq_matches_1;
assign N53 = ~T22[3];
assign N54 = ~T22[2];
assign N55 = ~T22[1];
assign N56 = ~T22[0];
assign T133 = T114 & T135[0];
assign T138 = T114 & T135[1];
assign T144 = T114 & T135[2];
assign T147 = T114 & T135[3];
assign T154 = T114 & T135[4];
assign T157 = T114 & T135[5];
assign T162 = T114 & T135[6];
assign T165 = T114 & T135[7];
assign T171 = T114 & T135[8];
assign io_enq_ready = T175 | roq_free_8;
assign T175 = T176 | roq_free_7;
assign T176 = T177 | roq_free_6;
assign T177 = T178 | roq_free_5;
assign T178 = T179 | roq_free_4;
assign T179 = T180 | roq_free_3;
assign T180 = T181 | roq_free_2;
assign T181 = roq_free_0 | roq_free_1;
assign N57 = T115 | reset;
assign N58 = T4 | N57;
assign N59 = ~N58;
assign N62 = T19 | reset;
assign N63 = T17 | N62;
assign N64 = ~N63;
assign N67 = T76 | reset;
assign N68 = T74 | N67;
assign N69 = ~N68;
assign N72 = T82 | reset;
assign N73 = T80 | N72;
assign N74 = ~N73;
assign N77 = T88 | reset;
assign N78 = T86 | N77;
assign N79 = ~N78;
assign N82 = T94 | reset;
assign N83 = T92 | N82;
assign N84 = ~N83;
assign N87 = T100 | reset;
assign N88 = T98 | N87;
assign N89 = ~N88;
assign N92 = T106 | reset;
assign N93 = T104 | N92;
assign N94 = ~N93;
assign N97 = T112 | reset;
assign N98 = T110 | N97;
assign N99 = ~N98;
assign N102 = ~reset;
assign N103 = T115 & N102;
assign N104 = ~T115;
assign N105 = N102 & N104;
assign N106 = T4 & N105;
assign N107 = T19 & N102;
assign N108 = ~T19;
assign N109 = N102 & N108;
assign N110 = T17 & N109;
assign N111 = T76 & N102;
assign N112 = ~T76;
assign N113 = N102 & N112;
assign N114 = T74 & N113;
assign N115 = T82 & N102;
assign N116 = ~T82;
assign N117 = N102 & N116;
assign N118 = T80 & N117;
assign N119 = T88 & N102;
assign N120 = ~T88;
assign N121 = N102 & N120;
assign N122 = T86 & N121;
assign N123 = T94 & N102;
assign N124 = ~T94;
assign N125 = N102 & N124;
assign N126 = T92 & N125;
assign N127 = T100 & N102;
assign N128 = ~T100;
assign N129 = N102 & N128;
assign N130 = T98 & N129;
assign N131 = T106 & N102;
assign N132 = ~T106;
assign N133 = N102 & N132;
assign N134 = T104 & N133;
assign N135 = T112 & N102;
assign N136 = ~T112;
assign N137 = N102 & N136;
assign N138 = T110 & N137;
endmodule |
module ManagerTileLinkNetworkPort_0
(
io_manager_acquire_ready,
io_manager_acquire_valid,
io_manager_acquire_bits_addr_block,
io_manager_acquire_bits_client_xact_id,
io_manager_acquire_bits_addr_beat,
io_manager_acquire_bits_is_builtin_type,
io_manager_acquire_bits_a_type,
io_manager_acquire_bits_union,
io_manager_acquire_bits_data,
io_manager_acquire_bits_client_id,
io_manager_grant_ready,
io_manager_grant_valid,
io_manager_grant_bits_addr_beat,
io_manager_grant_bits_client_xact_id,
io_manager_grant_bits_manager_xact_id,
io_manager_grant_bits_is_builtin_type,
io_manager_grant_bits_g_type,
io_manager_grant_bits_data,
io_manager_grant_bits_client_id,
io_manager_finish_ready,
io_manager_finish_valid,
io_manager_finish_bits_manager_xact_id,
io_manager_probe_ready,
io_manager_probe_valid,
io_manager_probe_bits_addr_block,
io_manager_probe_bits_p_type,
io_manager_probe_bits_client_id,
io_manager_release_ready,
io_manager_release_valid,
io_manager_release_bits_addr_beat,
io_manager_release_bits_addr_block,
io_manager_release_bits_client_xact_id,
io_manager_release_bits_voluntary,
io_manager_release_bits_r_type,
io_manager_release_bits_data,
io_manager_release_bits_client_id,
io_network_acquire_ready,
io_network_acquire_valid,
io_network_acquire_bits_header_src,
io_network_acquire_bits_header_dst,
io_network_acquire_bits_payload_addr_block,
io_network_acquire_bits_payload_client_xact_id,
io_network_acquire_bits_payload_addr_beat,
io_network_acquire_bits_payload_is_builtin_type,
io_network_acquire_bits_payload_a_type,
io_network_acquire_bits_payload_union,
io_network_acquire_bits_payload_data,
io_network_grant_ready,
io_network_grant_valid,
io_network_grant_bits_header_src,
io_network_grant_bits_header_dst,
io_network_grant_bits_payload_addr_beat,
io_network_grant_bits_payload_client_xact_id,
io_network_grant_bits_payload_manager_xact_id,
io_network_grant_bits_payload_is_builtin_type,
io_network_grant_bits_payload_g_type,
io_network_grant_bits_payload_data,
io_network_finish_ready,
io_network_finish_valid,
io_network_finish_bits_header_src,
io_network_finish_bits_header_dst,
io_network_finish_bits_payload_manager_xact_id,
io_network_probe_ready,
io_network_probe_valid,
io_network_probe_bits_header_src,
io_network_probe_bits_header_dst,
io_network_probe_bits_payload_addr_block,
io_network_probe_bits_payload_p_type,
io_network_release_ready,
io_network_release_valid,
io_network_release_bits_header_src,
io_network_release_bits_header_dst,
io_network_release_bits_payload_addr_beat,
io_network_release_bits_payload_addr_block,
io_network_release_bits_payload_client_xact_id,
io_network_release_bits_payload_voluntary,
io_network_release_bits_payload_r_type,
io_network_release_bits_payload_data
);
output [25:0] io_manager_acquire_bits_addr_block;
output [5:0] io_manager_acquire_bits_client_xact_id;
output [1:0] io_manager_acquire_bits_addr_beat;
output [2:0] io_manager_acquire_bits_a_type;
output [16:0] io_manager_acquire_bits_union;
output [127:0] io_manager_acquire_bits_data;
output [1:0] io_manager_acquire_bits_client_id;
input [1:0] io_manager_grant_bits_addr_beat;
input [5:0] io_manager_grant_bits_client_xact_id;
input [3:0] io_manager_grant_bits_manager_xact_id;
input [3:0] io_manager_grant_bits_g_type;
input [127:0] io_manager_grant_bits_data;
input [1:0] io_manager_grant_bits_client_id;
output [3:0] io_manager_finish_bits_manager_xact_id;
input [25:0] io_manager_probe_bits_addr_block;
input [1:0] io_manager_probe_bits_p_type;
input [1:0] io_manager_probe_bits_client_id;
output [1:0] io_manager_release_bits_addr_beat;
output [25:0] io_manager_release_bits_addr_block;
output [5:0] io_manager_release_bits_client_xact_id;
output [2:0] io_manager_release_bits_r_type;
output [127:0] io_manager_release_bits_data;
output [1:0] io_manager_release_bits_client_id;
input [2:0] io_network_acquire_bits_header_src;
input [2:0] io_network_acquire_bits_header_dst;
input [25:0] io_network_acquire_bits_payload_addr_block;
input [5:0] io_network_acquire_bits_payload_client_xact_id;
input [1:0] io_network_acquire_bits_payload_addr_beat;
input [2:0] io_network_acquire_bits_payload_a_type;
input [16:0] io_network_acquire_bits_payload_union;
input [127:0] io_network_acquire_bits_payload_data;
output [2:0] io_network_grant_bits_header_src;
output [2:0] io_network_grant_bits_header_dst;
output [1:0] io_network_grant_bits_payload_addr_beat;
output [5:0] io_network_grant_bits_payload_client_xact_id;
output [3:0] io_network_grant_bits_payload_manager_xact_id;
output [3:0] io_network_grant_bits_payload_g_type;
output [127:0] io_network_grant_bits_payload_data;
input [2:0] io_network_finish_bits_header_src;
input [2:0] io_network_finish_bits_header_dst;
input [3:0] io_network_finish_bits_payload_manager_xact_id;
output [2:0] io_network_probe_bits_header_src;
output [2:0] io_network_probe_bits_header_dst;
output [25:0] io_network_probe_bits_payload_addr_block;
output [1:0] io_network_probe_bits_payload_p_type;
input [2:0] io_network_release_bits_header_src;
input [2:0] io_network_release_bits_header_dst;
input [1:0] io_network_release_bits_payload_addr_beat;
input [25:0] io_network_release_bits_payload_addr_block;
input [5:0] io_network_release_bits_payload_client_xact_id;
input [2:0] io_network_release_bits_payload_r_type;
input [127:0] io_network_release_bits_payload_data;
input io_manager_acquire_ready;
input io_manager_grant_valid;
input io_manager_grant_bits_is_builtin_type;
input io_manager_finish_ready;
input io_manager_probe_valid;
input io_manager_release_ready;
input io_network_acquire_valid;
input io_network_acquire_bits_payload_is_builtin_type;
input io_network_grant_ready;
input io_network_finish_valid;
input io_network_probe_ready;
input io_network_release_valid;
input io_network_release_bits_payload_voluntary;
output io_manager_acquire_valid;
output io_manager_acquire_bits_is_builtin_type;
output io_manager_grant_ready;
output io_manager_finish_valid;
output io_manager_probe_ready;
output io_manager_release_valid;
output io_manager_release_bits_voluntary;
output io_network_acquire_ready;
output io_network_grant_valid;
output io_network_grant_bits_payload_is_builtin_type;
output io_network_finish_ready;
output io_network_probe_valid;
output io_network_release_ready;
wire [25:0] io_manager_acquire_bits_addr_block,io_manager_release_bits_addr_block,
io_network_probe_bits_payload_addr_block;
wire [5:0] io_manager_acquire_bits_client_xact_id,io_manager_release_bits_client_xact_id,
io_network_grant_bits_payload_client_xact_id;
wire [1:0] io_manager_acquire_bits_addr_beat,io_manager_acquire_bits_client_id,
io_manager_release_bits_addr_beat,io_manager_release_bits_client_id,
io_network_grant_bits_payload_addr_beat,io_network_probe_bits_payload_p_type;
wire [2:0] io_manager_acquire_bits_a_type,io_manager_release_bits_r_type,
io_network_grant_bits_header_src,io_network_grant_bits_header_dst,
io_network_probe_bits_header_src,io_network_probe_bits_header_dst;
wire [16:0] io_manager_acquire_bits_union;
wire [127:0] io_manager_acquire_bits_data,io_manager_release_bits_data,
io_network_grant_bits_payload_data;
wire [3:0] io_manager_finish_bits_manager_xact_id,
io_network_grant_bits_payload_manager_xact_id,io_network_grant_bits_payload_g_type;
wire io_manager_acquire_valid,io_manager_acquire_bits_is_builtin_type,
io_manager_grant_ready,io_manager_finish_valid,io_manager_probe_ready,io_manager_release_valid,
io_manager_release_bits_voluntary,io_network_acquire_ready,
io_network_grant_valid,io_network_grant_bits_payload_is_builtin_type,io_network_finish_ready,
io_network_probe_valid,io_network_release_ready,io_network_acquire_valid,
io_network_acquire_bits_payload_is_builtin_type,io_network_grant_ready,io_network_finish_valid,
io_network_probe_ready,io_network_release_valid,
io_network_release_bits_payload_voluntary,io_manager_acquire_ready,io_manager_grant_valid,
io_manager_grant_bits_is_builtin_type,io_manager_finish_ready,io_manager_probe_valid,
io_manager_release_ready;
assign io_network_grant_bits_header_src[0] = 1'b0;
assign io_network_grant_bits_header_src[1] = 1'b0;
assign io_network_grant_bits_header_src[2] = 1'b0;
assign io_network_grant_bits_header_dst[2] = 1'b0;
assign io_network_probe_bits_header_src[0] = 1'b0;
assign io_network_probe_bits_header_src[1] = 1'b0;
assign io_network_probe_bits_header_src[2] = 1'b0;
assign io_network_probe_bits_header_dst[2] = 1'b0;
assign io_manager_acquire_valid = io_network_acquire_valid;
assign io_manager_acquire_bits_addr_block[25] = io_network_acquire_bits_payload_addr_block[25];
assign io_manager_acquire_bits_addr_block[24] = io_network_acquire_bits_payload_addr_block[24];
assign io_manager_acquire_bits_addr_block[23] = io_network_acquire_bits_payload_addr_block[23];
assign io_manager_acquire_bits_addr_block[22] = io_network_acquire_bits_payload_addr_block[22];
assign io_manager_acquire_bits_addr_block[21] = io_network_acquire_bits_payload_addr_block[21];
assign io_manager_acquire_bits_addr_block[20] = io_network_acquire_bits_payload_addr_block[20];
assign io_manager_acquire_bits_addr_block[19] = io_network_acquire_bits_payload_addr_block[19];
assign io_manager_acquire_bits_addr_block[18] = io_network_acquire_bits_payload_addr_block[18];
assign io_manager_acquire_bits_addr_block[17] = io_network_acquire_bits_payload_addr_block[17];
assign io_manager_acquire_bits_addr_block[16] = io_network_acquire_bits_payload_addr_block[16];
assign io_manager_acquire_bits_addr_block[15] = io_network_acquire_bits_payload_addr_block[15];
assign io_manager_acquire_bits_addr_block[14] = io_network_acquire_bits_payload_addr_block[14];
assign io_manager_acquire_bits_addr_block[13] = io_network_acquire_bits_payload_addr_block[13];
assign io_manager_acquire_bits_addr_block[12] = io_network_acquire_bits_payload_addr_block[12];
assign io_manager_acquire_bits_addr_block[11] = io_network_acquire_bits_payload_addr_block[11];
assign io_manager_acquire_bits_addr_block[10] = io_network_acquire_bits_payload_addr_block[10];
assign io_manager_acquire_bits_addr_block[9] = io_network_acquire_bits_payload_addr_block[9];
assign io_manager_acquire_bits_addr_block[8] = io_network_acquire_bits_payload_addr_block[8];
assign io_manager_acquire_bits_addr_block[7] = io_network_acquire_bits_payload_addr_block[7];
assign io_manager_acquire_bits_addr_block[6] = io_network_acquire_bits_payload_addr_block[6];
assign io_manager_acquire_bits_addr_block[5] = io_network_acquire_bits_payload_addr_block[5];
assign io_manager_acquire_bits_addr_block[4] = io_network_acquire_bits_payload_addr_block[4];
assign io_manager_acquire_bits_addr_block[3] = io_network_acquire_bits_payload_addr_block[3];
assign io_manager_acquire_bits_addr_block[2] = io_network_acquire_bits_payload_addr_block[2];
assign io_manager_acquire_bits_addr_block[1] = io_network_acquire_bits_payload_addr_block[1];
assign io_manager_acquire_bits_addr_block[0] = io_network_acquire_bits_payload_addr_block[0];
assign io_manager_acquire_bits_client_xact_id[5] = io_network_acquire_bits_payload_client_xact_id[5];
assign io_manager_acquire_bits_client_xact_id[4] = io_network_acquire_bits_payload_client_xact_id[4];
assign io_manager_acquire_bits_client_xact_id[3] = io_network_acquire_bits_payload_client_xact_id[3];
assign io_manager_acquire_bits_client_xact_id[2] = io_network_acquire_bits_payload_client_xact_id[2];
assign io_manager_acquire_bits_client_xact_id[1] = io_network_acquire_bits_payload_client_xact_id[1];
assign io_manager_acquire_bits_client_xact_id[0] = io_network_acquire_bits_payload_client_xact_id[0];
assign io_manager_acquire_bits_addr_beat[1] = io_network_acquire_bits_payload_addr_beat[1];
assign io_manager_acquire_bits_addr_beat[0] = io_network_acquire_bits_payload_addr_beat[0];
assign io_manager_acquire_bits_is_builtin_type = io_network_acquire_bits_payload_is_builtin_type;
assign io_manager_acquire_bits_a_type[2] = io_network_acquire_bits_payload_a_type[2];
assign io_manager_acquire_bits_a_type[1] = io_network_acquire_bits_payload_a_type[1];
assign io_manager_acquire_bits_a_type[0] = io_network_acquire_bits_payload_a_type[0];
assign io_manager_acquire_bits_union[16] = io_network_acquire_bits_payload_union[16];
assign io_manager_acquire_bits_union[15] = io_network_acquire_bits_payload_union[15];
assign io_manager_acquire_bits_union[14] = io_network_acquire_bits_payload_union[14];
assign io_manager_acquire_bits_union[13] = io_network_acquire_bits_payload_union[13];
assign io_manager_acquire_bits_union[12] = io_network_acquire_bits_payload_union[12];
assign io_manager_acquire_bits_union[11] = io_network_acquire_bits_payload_union[11];
assign io_manager_acquire_bits_union[10] = io_network_acquire_bits_payload_union[10];
assign io_manager_acquire_bits_union[9] = io_network_acquire_bits_payload_union[9];
assign io_manager_acquire_bits_union[8] = io_network_acquire_bits_payload_union[8];
assign io_manager_acquire_bits_union[7] = io_network_acquire_bits_payload_union[7];
assign io_manager_acquire_bits_union[6] = io_network_acquire_bits_payload_union[6];
assign io_manager_acquire_bits_union[5] = io_network_acquire_bits_payload_union[5];
assign io_manager_acquire_bits_union[4] = io_network_acquire_bits_payload_union[4];
assign io_manager_acquire_bits_union[3] = io_network_acquire_bits_payload_union[3];
assign io_manager_acquire_bits_union[2] = io_network_acquire_bits_payload_union[2];
assign io_manager_acquire_bits_union[1] = io_network_acquire_bits_payload_union[1];
assign io_manager_acquire_bits_union[0] = io_network_acquire_bits_payload_union[0];
assign io_manager_acquire_bits_data[127] = io_network_acquire_bits_payload_data[127];
assign io_manager_acquire_bits_data[126] = io_network_acquire_bits_payload_data[126];
assign io_manager_acquire_bits_data[125] = io_network_acquire_bits_payload_data[125];
assign io_manager_acquire_bits_data[124] = io_network_acquire_bits_payload_data[124];
assign io_manager_acquire_bits_data[123] = io_network_acquire_bits_payload_data[123];
assign io_manager_acquire_bits_data[122] = io_network_acquire_bits_payload_data[122];
assign io_manager_acquire_bits_data[121] = io_network_acquire_bits_payload_data[121];
assign io_manager_acquire_bits_data[120] = io_network_acquire_bits_payload_data[120];
assign io_manager_acquire_bits_data[119] = io_network_acquire_bits_payload_data[119];
assign io_manager_acquire_bits_data[118] = io_network_acquire_bits_payload_data[118];
assign io_manager_acquire_bits_data[117] = io_network_acquire_bits_payload_data[117];
assign io_manager_acquire_bits_data[116] = io_network_acquire_bits_payload_data[116];
assign io_manager_acquire_bits_data[115] = io_network_acquire_bits_payload_data[115];
assign io_manager_acquire_bits_data[114] = io_network_acquire_bits_payload_data[114];
assign io_manager_acquire_bits_data[113] = io_network_acquire_bits_payload_data[113];
assign io_manager_acquire_bits_data[112] = io_network_acquire_bits_payload_data[112];
assign io_manager_acquire_bits_data[111] = io_network_acquire_bits_payload_data[111];
assign io_manager_acquire_bits_data[110] = io_network_acquire_bits_payload_data[110];
assign io_manager_acquire_bits_data[109] = io_network_acquire_bits_payload_data[109];
assign io_manager_acquire_bits_data[108] = io_network_acquire_bits_payload_data[108];
assign io_manager_acquire_bits_data[107] = io_network_acquire_bits_payload_data[107];
assign io_manager_acquire_bits_data[106] = io_network_acquire_bits_payload_data[106];
assign io_manager_acquire_bits_data[105] = io_network_acquire_bits_payload_data[105];
assign io_manager_acquire_bits_data[104] = io_network_acquire_bits_payload_data[104];
assign io_manager_acquire_bits_data[103] = io_network_acquire_bits_payload_data[103];
assign io_manager_acquire_bits_data[102] = io_network_acquire_bits_payload_data[102];
assign io_manager_acquire_bits_data[101] = io_network_acquire_bits_payload_data[101];
assign io_manager_acquire_bits_data[100] = io_network_acquire_bits_payload_data[100];
assign io_manager_acquire_bits_data[99] = io_network_acquire_bits_payload_data[99];
assign io_manager_acquire_bits_data[98] = io_network_acquire_bits_payload_data[98];
assign io_manager_acquire_bits_data[97] = io_network_acquire_bits_payload_data[97];
assign io_manager_acquire_bits_data[96] = io_network_acquire_bits_payload_data[96];
assign io_manager_acquire_bits_data[95] = io_network_acquire_bits_payload_data[95];
assign io_manager_acquire_bits_data[94] = io_network_acquire_bits_payload_data[94];
assign io_manager_acquire_bits_data[93] = io_network_acquire_bits_payload_data[93];
assign io_manager_acquire_bits_data[92] = io_network_acquire_bits_payload_data[92];
assign io_manager_acquire_bits_data[91] = io_network_acquire_bits_payload_data[91];
assign io_manager_acquire_bits_data[90] = io_network_acquire_bits_payload_data[90];
assign io_manager_acquire_bits_data[89] = io_network_acquire_bits_payload_data[89];
assign io_manager_acquire_bits_data[88] = io_network_acquire_bits_payload_data[88];
assign io_manager_acquire_bits_data[87] = io_network_acquire_bits_payload_data[87];
assign io_manager_acquire_bits_data[86] = io_network_acquire_bits_payload_data[86];
assign io_manager_acquire_bits_data[85] = io_network_acquire_bits_payload_data[85];
assign io_manager_acquire_bits_data[84] = io_network_acquire_bits_payload_data[84];
assign io_manager_acquire_bits_data[83] = io_network_acquire_bits_payload_data[83];
assign io_manager_acquire_bits_data[82] = io_network_acquire_bits_payload_data[82];
assign io_manager_acquire_bits_data[81] = io_network_acquire_bits_payload_data[81];
assign io_manager_acquire_bits_data[80] = io_network_acquire_bits_payload_data[80];
assign io_manager_acquire_bits_data[79] = io_network_acquire_bits_payload_data[79];
assign io_manager_acquire_bits_data[78] = io_network_acquire_bits_payload_data[78];
assign io_manager_acquire_bits_data[77] = io_network_acquire_bits_payload_data[77];
assign io_manager_acquire_bits_data[76] = io_network_acquire_bits_payload_data[76];
assign io_manager_acquire_bits_data[75] = io_network_acquire_bits_payload_data[75];
assign io_manager_acquire_bits_data[74] = io_network_acquire_bits_payload_data[74];
assign io_manager_acquire_bits_data[73] = io_network_acquire_bits_payload_data[73];
assign io_manager_acquire_bits_data[72] = io_network_acquire_bits_payload_data[72];
assign io_manager_acquire_bits_data[71] = io_network_acquire_bits_payload_data[71];
assign io_manager_acquire_bits_data[70] = io_network_acquire_bits_payload_data[70];
assign io_manager_acquire_bits_data[69] = io_network_acquire_bits_payload_data[69];
assign io_manager_acquire_bits_data[68] = io_network_acquire_bits_payload_data[68];
assign io_manager_acquire_bits_data[67] = io_network_acquire_bits_payload_data[67];
assign io_manager_acquire_bits_data[66] = io_network_acquire_bits_payload_data[66];
assign io_manager_acquire_bits_data[65] = io_network_acquire_bits_payload_data[65];
assign io_manager_acquire_bits_data[64] = io_network_acquire_bits_payload_data[64];
assign io_manager_acquire_bits_data[63] = io_network_acquire_bits_payload_data[63];
assign io_manager_acquire_bits_data[62] = io_network_acquire_bits_payload_data[62];
assign io_manager_acquire_bits_data[61] = io_network_acquire_bits_payload_data[61];
assign io_manager_acquire_bits_data[60] = io_network_acquire_bits_payload_data[60];
assign io_manager_acquire_bits_data[59] = io_network_acquire_bits_payload_data[59];
assign io_manager_acquire_bits_data[58] = io_network_acquire_bits_payload_data[58];
assign io_manager_acquire_bits_data[57] = io_network_acquire_bits_payload_data[57];
assign io_manager_acquire_bits_data[56] = io_network_acquire_bits_payload_data[56];
assign io_manager_acquire_bits_data[55] = io_network_acquire_bits_payload_data[55];
assign io_manager_acquire_bits_data[54] = io_network_acquire_bits_payload_data[54];
assign io_manager_acquire_bits_data[53] = io_network_acquire_bits_payload_data[53];
assign io_manager_acquire_bits_data[52] = io_network_acquire_bits_payload_data[52];
assign io_manager_acquire_bits_data[51] = io_network_acquire_bits_payload_data[51];
assign io_manager_acquire_bits_data[50] = io_network_acquire_bits_payload_data[50];
assign io_manager_acquire_bits_data[49] = io_network_acquire_bits_payload_data[49];
assign io_manager_acquire_bits_data[48] = io_network_acquire_bits_payload_data[48];
assign io_manager_acquire_bits_data[47] = io_network_acquire_bits_payload_data[47];
assign io_manager_acquire_bits_data[46] = io_network_acquire_bits_payload_data[46];
assign io_manager_acquire_bits_data[45] = io_network_acquire_bits_payload_data[45];
assign io_manager_acquire_bits_data[44] = io_network_acquire_bits_payload_data[44];
assign io_manager_acquire_bits_data[43] = io_network_acquire_bits_payload_data[43];
assign io_manager_acquire_bits_data[42] = io_network_acquire_bits_payload_data[42];
assign io_manager_acquire_bits_data[41] = io_network_acquire_bits_payload_data[41];
assign io_manager_acquire_bits_data[40] = io_network_acquire_bits_payload_data[40];
assign io_manager_acquire_bits_data[39] = io_network_acquire_bits_payload_data[39];
assign io_manager_acquire_bits_data[38] = io_network_acquire_bits_payload_data[38];
assign io_manager_acquire_bits_data[37] = io_network_acquire_bits_payload_data[37];
assign io_manager_acquire_bits_data[36] = io_network_acquire_bits_payload_data[36];
assign io_manager_acquire_bits_data[35] = io_network_acquire_bits_payload_data[35];
assign io_manager_acquire_bits_data[34] = io_network_acquire_bits_payload_data[34];
assign io_manager_acquire_bits_data[33] = io_network_acquire_bits_payload_data[33];
assign io_manager_acquire_bits_data[32] = io_network_acquire_bits_payload_data[32];
assign io_manager_acquire_bits_data[31] = io_network_acquire_bits_payload_data[31];
assign io_manager_acquire_bits_data[30] = io_network_acquire_bits_payload_data[30];
assign io_manager_acquire_bits_data[29] = io_network_acquire_bits_payload_data[29];
assign io_manager_acquire_bits_data[28] = io_network_acquire_bits_payload_data[28];
assign io_manager_acquire_bits_data[27] = io_network_acquire_bits_payload_data[27];
assign io_manager_acquire_bits_data[26] = io_network_acquire_bits_payload_data[26];
assign io_manager_acquire_bits_data[25] = io_network_acquire_bits_payload_data[25];
assign io_manager_acquire_bits_data[24] = io_network_acquire_bits_payload_data[24];
assign io_manager_acquire_bits_data[23] = io_network_acquire_bits_payload_data[23];
assign io_manager_acquire_bits_data[22] = io_network_acquire_bits_payload_data[22];
assign io_manager_acquire_bits_data[21] = io_network_acquire_bits_payload_data[21];
assign io_manager_acquire_bits_data[20] = io_network_acquire_bits_payload_data[20];
assign io_manager_acquire_bits_data[19] = io_network_acquire_bits_payload_data[19];
assign io_manager_acquire_bits_data[18] = io_network_acquire_bits_payload_data[18];
assign io_manager_acquire_bits_data[17] = io_network_acquire_bits_payload_data[17];
assign io_manager_acquire_bits_data[16] = io_network_acquire_bits_payload_data[16];
assign io_manager_acquire_bits_data[15] = io_network_acquire_bits_payload_data[15];
assign io_manager_acquire_bits_data[14] = io_network_acquire_bits_payload_data[14];
assign io_manager_acquire_bits_data[13] = io_network_acquire_bits_payload_data[13];
assign io_manager_acquire_bits_data[12] = io_network_acquire_bits_payload_data[12];
assign io_manager_acquire_bits_data[11] = io_network_acquire_bits_payload_data[11];
assign io_manager_acquire_bits_data[10] = io_network_acquire_bits_payload_data[10];
assign io_manager_acquire_bits_data[9] = io_network_acquire_bits_payload_data[9];
assign io_manager_acquire_bits_data[8] = io_network_acquire_bits_payload_data[8];
assign io_manager_acquire_bits_data[7] = io_network_acquire_bits_payload_data[7];
assign io_manager_acquire_bits_data[6] = io_network_acquire_bits_payload_data[6];
assign io_manager_acquire_bits_data[5] = io_network_acquire_bits_payload_data[5];
assign io_manager_acquire_bits_data[4] = io_network_acquire_bits_payload_data[4];
assign io_manager_acquire_bits_data[3] = io_network_acquire_bits_payload_data[3];
assign io_manager_acquire_bits_data[2] = io_network_acquire_bits_payload_data[2];
assign io_manager_acquire_bits_data[1] = io_network_acquire_bits_payload_data[1];
assign io_manager_acquire_bits_data[0] = io_network_acquire_bits_payload_data[0];
assign io_manager_acquire_bits_client_id[1] = io_network_acquire_bits_header_src[1];
assign io_manager_acquire_bits_client_id[0] = io_network_acquire_bits_header_src[0];
assign io_manager_grant_ready = io_network_grant_ready;
assign io_manager_finish_valid = io_network_finish_valid;
assign io_manager_finish_bits_manager_xact_id[3] = io_network_finish_bits_payload_manager_xact_id[3];
assign io_manager_finish_bits_manager_xact_id[2] = io_network_finish_bits_payload_manager_xact_id[2];
assign io_manager_finish_bits_manager_xact_id[1] = io_network_finish_bits_payload_manager_xact_id[1];
assign io_manager_finish_bits_manager_xact_id[0] = io_network_finish_bits_payload_manager_xact_id[0];
assign io_manager_probe_ready = io_network_probe_ready;
assign io_manager_release_valid = io_network_release_valid;
assign io_manager_release_bits_addr_beat[1] = io_network_release_bits_payload_addr_beat[1];
assign io_manager_release_bits_addr_beat[0] = io_network_release_bits_payload_addr_beat[0];
assign io_manager_release_bits_addr_block[25] = io_network_release_bits_payload_addr_block[25];
assign io_manager_release_bits_addr_block[24] = io_network_release_bits_payload_addr_block[24];
assign io_manager_release_bits_addr_block[23] = io_network_release_bits_payload_addr_block[23];
assign io_manager_release_bits_addr_block[22] = io_network_release_bits_payload_addr_block[22];
assign io_manager_release_bits_addr_block[21] = io_network_release_bits_payload_addr_block[21];
assign io_manager_release_bits_addr_block[20] = io_network_release_bits_payload_addr_block[20];
assign io_manager_release_bits_addr_block[19] = io_network_release_bits_payload_addr_block[19];
assign io_manager_release_bits_addr_block[18] = io_network_release_bits_payload_addr_block[18];
assign io_manager_release_bits_addr_block[17] = io_network_release_bits_payload_addr_block[17];
assign io_manager_release_bits_addr_block[16] = io_network_release_bits_payload_addr_block[16];
assign io_manager_release_bits_addr_block[15] = io_network_release_bits_payload_addr_block[15];
assign io_manager_release_bits_addr_block[14] = io_network_release_bits_payload_addr_block[14];
assign io_manager_release_bits_addr_block[13] = io_network_release_bits_payload_addr_block[13];
assign io_manager_release_bits_addr_block[12] = io_network_release_bits_payload_addr_block[12];
assign io_manager_release_bits_addr_block[11] = io_network_release_bits_payload_addr_block[11];
assign io_manager_release_bits_addr_block[10] = io_network_release_bits_payload_addr_block[10];
assign io_manager_release_bits_addr_block[9] = io_network_release_bits_payload_addr_block[9];
assign io_manager_release_bits_addr_block[8] = io_network_release_bits_payload_addr_block[8];
assign io_manager_release_bits_addr_block[7] = io_network_release_bits_payload_addr_block[7];
assign io_manager_release_bits_addr_block[6] = io_network_release_bits_payload_addr_block[6];
assign io_manager_release_bits_addr_block[5] = io_network_release_bits_payload_addr_block[5];
assign io_manager_release_bits_addr_block[4] = io_network_release_bits_payload_addr_block[4];
assign io_manager_release_bits_addr_block[3] = io_network_release_bits_payload_addr_block[3];
assign io_manager_release_bits_addr_block[2] = io_network_release_bits_payload_addr_block[2];
assign io_manager_release_bits_addr_block[1] = io_network_release_bits_payload_addr_block[1];
assign io_manager_release_bits_addr_block[0] = io_network_release_bits_payload_addr_block[0];
assign io_manager_release_bits_client_xact_id[5] = io_network_release_bits_payload_client_xact_id[5];
assign io_manager_release_bits_client_xact_id[4] = io_network_release_bits_payload_client_xact_id[4];
assign io_manager_release_bits_client_xact_id[3] = io_network_release_bits_payload_client_xact_id[3];
assign io_manager_release_bits_client_xact_id[2] = io_network_release_bits_payload_client_xact_id[2];
assign io_manager_release_bits_client_xact_id[1] = io_network_release_bits_payload_client_xact_id[1];
assign io_manager_release_bits_client_xact_id[0] = io_network_release_bits_payload_client_xact_id[0];
assign io_manager_release_bits_voluntary = io_network_release_bits_payload_voluntary;
assign io_manager_release_bits_r_type[2] = io_network_release_bits_payload_r_type[2];
assign io_manager_release_bits_r_type[1] = io_network_release_bits_payload_r_type[1];
assign io_manager_release_bits_r_type[0] = io_network_release_bits_payload_r_type[0];
assign io_manager_release_bits_data[127] = io_network_release_bits_payload_data[127];
assign io_manager_release_bits_data[126] = io_network_release_bits_payload_data[126];
assign io_manager_release_bits_data[125] = io_network_release_bits_payload_data[125];
assign io_manager_release_bits_data[124] = io_network_release_bits_payload_data[124];
assign io_manager_release_bits_data[123] = io_network_release_bits_payload_data[123];
assign io_manager_release_bits_data[122] = io_network_release_bits_payload_data[122];
assign io_manager_release_bits_data[121] = io_network_release_bits_payload_data[121];
assign io_manager_release_bits_data[120] = io_network_release_bits_payload_data[120];
assign io_manager_release_bits_data[119] = io_network_release_bits_payload_data[119];
assign io_manager_release_bits_data[118] = io_network_release_bits_payload_data[118];
assign io_manager_release_bits_data[117] = io_network_release_bits_payload_data[117];
assign io_manager_release_bits_data[116] = io_network_release_bits_payload_data[116];
assign io_manager_release_bits_data[115] = io_network_release_bits_payload_data[115];
assign io_manager_release_bits_data[114] = io_network_release_bits_payload_data[114];
assign io_manager_release_bits_data[113] = io_network_release_bits_payload_data[113];
assign io_manager_release_bits_data[112] = io_network_release_bits_payload_data[112];
assign io_manager_release_bits_data[111] = io_network_release_bits_payload_data[111];
assign io_manager_release_bits_data[110] = io_network_release_bits_payload_data[110];
assign io_manager_release_bits_data[109] = io_network_release_bits_payload_data[109];
assign io_manager_release_bits_data[108] = io_network_release_bits_payload_data[108];
assign io_manager_release_bits_data[107] = io_network_release_bits_payload_data[107];
assign io_manager_release_bits_data[106] = io_network_release_bits_payload_data[106];
assign io_manager_release_bits_data[105] = io_network_release_bits_payload_data[105];
assign io_manager_release_bits_data[104] = io_network_release_bits_payload_data[104];
assign io_manager_release_bits_data[103] = io_network_release_bits_payload_data[103];
assign io_manager_release_bits_data[102] = io_network_release_bits_payload_data[102];
assign io_manager_release_bits_data[101] = io_network_release_bits_payload_data[101];
assign io_manager_release_bits_data[100] = io_network_release_bits_payload_data[100];
assign io_manager_release_bits_data[99] = io_network_release_bits_payload_data[99];
assign io_manager_release_bits_data[98] = io_network_release_bits_payload_data[98];
assign io_manager_release_bits_data[97] = io_network_release_bits_payload_data[97];
assign io_manager_release_bits_data[96] = io_network_release_bits_payload_data[96];
assign io_manager_release_bits_data[95] = io_network_release_bits_payload_data[95];
assign io_manager_release_bits_data[94] = io_network_release_bits_payload_data[94];
assign io_manager_release_bits_data[93] = io_network_release_bits_payload_data[93];
assign io_manager_release_bits_data[92] = io_network_release_bits_payload_data[92];
assign io_manager_release_bits_data[91] = io_network_release_bits_payload_data[91];
assign io_manager_release_bits_data[90] = io_network_release_bits_payload_data[90];
assign io_manager_release_bits_data[89] = io_network_release_bits_payload_data[89];
assign io_manager_release_bits_data[88] = io_network_release_bits_payload_data[88];
assign io_manager_release_bits_data[87] = io_network_release_bits_payload_data[87];
assign io_manager_release_bits_data[86] = io_network_release_bits_payload_data[86];
assign io_manager_release_bits_data[85] = io_network_release_bits_payload_data[85];
assign io_manager_release_bits_data[84] = io_network_release_bits_payload_data[84];
assign io_manager_release_bits_data[83] = io_network_release_bits_payload_data[83];
assign io_manager_release_bits_data[82] = io_network_release_bits_payload_data[82];
assign io_manager_release_bits_data[81] = io_network_release_bits_payload_data[81];
assign io_manager_release_bits_data[80] = io_network_release_bits_payload_data[80];
assign io_manager_release_bits_data[79] = io_network_release_bits_payload_data[79];
assign io_manager_release_bits_data[78] = io_network_release_bits_payload_data[78];
assign io_manager_release_bits_data[77] = io_network_release_bits_payload_data[77];
assign io_manager_release_bits_data[76] = io_network_release_bits_payload_data[76];
assign io_manager_release_bits_data[75] = io_network_release_bits_payload_data[75];
assign io_manager_release_bits_data[74] = io_network_release_bits_payload_data[74];
assign io_manager_release_bits_data[73] = io_network_release_bits_payload_data[73];
assign io_manager_release_bits_data[72] = io_network_release_bits_payload_data[72];
assign io_manager_release_bits_data[71] = io_network_release_bits_payload_data[71];
assign io_manager_release_bits_data[70] = io_network_release_bits_payload_data[70];
assign io_manager_release_bits_data[69] = io_network_release_bits_payload_data[69];
assign io_manager_release_bits_data[68] = io_network_release_bits_payload_data[68];
assign io_manager_release_bits_data[67] = io_network_release_bits_payload_data[67];
assign io_manager_release_bits_data[66] = io_network_release_bits_payload_data[66];
assign io_manager_release_bits_data[65] = io_network_release_bits_payload_data[65];
assign io_manager_release_bits_data[64] = io_network_release_bits_payload_data[64];
assign io_manager_release_bits_data[63] = io_network_release_bits_payload_data[63];
assign io_manager_release_bits_data[62] = io_network_release_bits_payload_data[62];
assign io_manager_release_bits_data[61] = io_network_release_bits_payload_data[61];
assign io_manager_release_bits_data[60] = io_network_release_bits_payload_data[60];
assign io_manager_release_bits_data[59] = io_network_release_bits_payload_data[59];
assign io_manager_release_bits_data[58] = io_network_release_bits_payload_data[58];
assign io_manager_release_bits_data[57] = io_network_release_bits_payload_data[57];
assign io_manager_release_bits_data[56] = io_network_release_bits_payload_data[56];
assign io_manager_release_bits_data[55] = io_network_release_bits_payload_data[55];
assign io_manager_release_bits_data[54] = io_network_release_bits_payload_data[54];
assign io_manager_release_bits_data[53] = io_network_release_bits_payload_data[53];
assign io_manager_release_bits_data[52] = io_network_release_bits_payload_data[52];
assign io_manager_release_bits_data[51] = io_network_release_bits_payload_data[51];
assign io_manager_release_bits_data[50] = io_network_release_bits_payload_data[50];
assign io_manager_release_bits_data[49] = io_network_release_bits_payload_data[49];
assign io_manager_release_bits_data[48] = io_network_release_bits_payload_data[48];
assign io_manager_release_bits_data[47] = io_network_release_bits_payload_data[47];
assign io_manager_release_bits_data[46] = io_network_release_bits_payload_data[46];
assign io_manager_release_bits_data[45] = io_network_release_bits_payload_data[45];
assign io_manager_release_bits_data[44] = io_network_release_bits_payload_data[44];
assign io_manager_release_bits_data[43] = io_network_release_bits_payload_data[43];
assign io_manager_release_bits_data[42] = io_network_release_bits_payload_data[42];
assign io_manager_release_bits_data[41] = io_network_release_bits_payload_data[41];
assign io_manager_release_bits_data[40] = io_network_release_bits_payload_data[40];
assign io_manager_release_bits_data[39] = io_network_release_bits_payload_data[39];
assign io_manager_release_bits_data[38] = io_network_release_bits_payload_data[38];
assign io_manager_release_bits_data[37] = io_network_release_bits_payload_data[37];
assign io_manager_release_bits_data[36] = io_network_release_bits_payload_data[36];
assign io_manager_release_bits_data[35] = io_network_release_bits_payload_data[35];
assign io_manager_release_bits_data[34] = io_network_release_bits_payload_data[34];
assign io_manager_release_bits_data[33] = io_network_release_bits_payload_data[33];
assign io_manager_release_bits_data[32] = io_network_release_bits_payload_data[32];
assign io_manager_release_bits_data[31] = io_network_release_bits_payload_data[31];
assign io_manager_release_bits_data[30] = io_network_release_bits_payload_data[30];
assign io_manager_release_bits_data[29] = io_network_release_bits_payload_data[29];
assign io_manager_release_bits_data[28] = io_network_release_bits_payload_data[28];
assign io_manager_release_bits_data[27] = io_network_release_bits_payload_data[27];
assign io_manager_release_bits_data[26] = io_network_release_bits_payload_data[26];
assign io_manager_release_bits_data[25] = io_network_release_bits_payload_data[25];
assign io_manager_release_bits_data[24] = io_network_release_bits_payload_data[24];
assign io_manager_release_bits_data[23] = io_network_release_bits_payload_data[23];
assign io_manager_release_bits_data[22] = io_network_release_bits_payload_data[22];
assign io_manager_release_bits_data[21] = io_network_release_bits_payload_data[21];
assign io_manager_release_bits_data[20] = io_network_release_bits_payload_data[20];
assign io_manager_release_bits_data[19] = io_network_release_bits_payload_data[19];
assign io_manager_release_bits_data[18] = io_network_release_bits_payload_data[18];
assign io_manager_release_bits_data[17] = io_network_release_bits_payload_data[17];
assign io_manager_release_bits_data[16] = io_network_release_bits_payload_data[16];
assign io_manager_release_bits_data[15] = io_network_release_bits_payload_data[15];
assign io_manager_release_bits_data[14] = io_network_release_bits_payload_data[14];
assign io_manager_release_bits_data[13] = io_network_release_bits_payload_data[13];
assign io_manager_release_bits_data[12] = io_network_release_bits_payload_data[12];
assign io_manager_release_bits_data[11] = io_network_release_bits_payload_data[11];
assign io_manager_release_bits_data[10] = io_network_release_bits_payload_data[10];
assign io_manager_release_bits_data[9] = io_network_release_bits_payload_data[9];
assign io_manager_release_bits_data[8] = io_network_release_bits_payload_data[8];
assign io_manager_release_bits_data[7] = io_network_release_bits_payload_data[7];
assign io_manager_release_bits_data[6] = io_network_release_bits_payload_data[6];
assign io_manager_release_bits_data[5] = io_network_release_bits_payload_data[5];
assign io_manager_release_bits_data[4] = io_network_release_bits_payload_data[4];
assign io_manager_release_bits_data[3] = io_network_release_bits_payload_data[3];
assign io_manager_release_bits_data[2] = io_network_release_bits_payload_data[2];
assign io_manager_release_bits_data[1] = io_network_release_bits_payload_data[1];
assign io_manager_release_bits_data[0] = io_network_release_bits_payload_data[0];
assign io_manager_release_bits_client_id[1] = io_network_release_bits_header_src[1];
assign io_manager_release_bits_client_id[0] = io_network_release_bits_header_src[0];
assign io_network_acquire_ready = io_manager_acquire_ready;
assign io_network_grant_valid = io_manager_grant_valid;
assign io_network_grant_bits_header_dst[1] = io_manager_grant_bits_client_id[1];
assign io_network_grant_bits_header_dst[0] = io_manager_grant_bits_client_id[0];
assign io_network_grant_bits_payload_addr_beat[1] = io_manager_grant_bits_addr_beat[1];
assign io_network_grant_bits_payload_addr_beat[0] = io_manager_grant_bits_addr_beat[0];
assign io_network_grant_bits_payload_client_xact_id[5] = io_manager_grant_bits_client_xact_id[5];
assign io_network_grant_bits_payload_client_xact_id[4] = io_manager_grant_bits_client_xact_id[4];
assign io_network_grant_bits_payload_client_xact_id[3] = io_manager_grant_bits_client_xact_id[3];
assign io_network_grant_bits_payload_client_xact_id[2] = io_manager_grant_bits_client_xact_id[2];
assign io_network_grant_bits_payload_client_xact_id[1] = io_manager_grant_bits_client_xact_id[1];
assign io_network_grant_bits_payload_client_xact_id[0] = io_manager_grant_bits_client_xact_id[0];
assign io_network_grant_bits_payload_manager_xact_id[3] = io_manager_grant_bits_manager_xact_id[3];
assign io_network_grant_bits_payload_manager_xact_id[2] = io_manager_grant_bits_manager_xact_id[2];
assign io_network_grant_bits_payload_manager_xact_id[1] = io_manager_grant_bits_manager_xact_id[1];
assign io_network_grant_bits_payload_manager_xact_id[0] = io_manager_grant_bits_manager_xact_id[0];
assign io_network_grant_bits_payload_is_builtin_type = io_manager_grant_bits_is_builtin_type;
assign io_network_grant_bits_payload_g_type[3] = io_manager_grant_bits_g_type[3];
assign io_network_grant_bits_payload_g_type[2] = io_manager_grant_bits_g_type[2];
assign io_network_grant_bits_payload_g_type[1] = io_manager_grant_bits_g_type[1];
assign io_network_grant_bits_payload_g_type[0] = io_manager_grant_bits_g_type[0];
assign io_network_grant_bits_payload_data[127] = io_manager_grant_bits_data[127];
assign io_network_grant_bits_payload_data[126] = io_manager_grant_bits_data[126];
assign io_network_grant_bits_payload_data[125] = io_manager_grant_bits_data[125];
assign io_network_grant_bits_payload_data[124] = io_manager_grant_bits_data[124];
assign io_network_grant_bits_payload_data[123] = io_manager_grant_bits_data[123];
assign io_network_grant_bits_payload_data[122] = io_manager_grant_bits_data[122];
assign io_network_grant_bits_payload_data[121] = io_manager_grant_bits_data[121];
assign io_network_grant_bits_payload_data[120] = io_manager_grant_bits_data[120];
assign io_network_grant_bits_payload_data[119] = io_manager_grant_bits_data[119];
assign io_network_grant_bits_payload_data[118] = io_manager_grant_bits_data[118];
assign io_network_grant_bits_payload_data[117] = io_manager_grant_bits_data[117];
assign io_network_grant_bits_payload_data[116] = io_manager_grant_bits_data[116];
assign io_network_grant_bits_payload_data[115] = io_manager_grant_bits_data[115];
assign io_network_grant_bits_payload_data[114] = io_manager_grant_bits_data[114];
assign io_network_grant_bits_payload_data[113] = io_manager_grant_bits_data[113];
assign io_network_grant_bits_payload_data[112] = io_manager_grant_bits_data[112];
assign io_network_grant_bits_payload_data[111] = io_manager_grant_bits_data[111];
assign io_network_grant_bits_payload_data[110] = io_manager_grant_bits_data[110];
assign io_network_grant_bits_payload_data[109] = io_manager_grant_bits_data[109];
assign io_network_grant_bits_payload_data[108] = io_manager_grant_bits_data[108];
assign io_network_grant_bits_payload_data[107] = io_manager_grant_bits_data[107];
assign io_network_grant_bits_payload_data[106] = io_manager_grant_bits_data[106];
assign io_network_grant_bits_payload_data[105] = io_manager_grant_bits_data[105];
assign io_network_grant_bits_payload_data[104] = io_manager_grant_bits_data[104];
assign io_network_grant_bits_payload_data[103] = io_manager_grant_bits_data[103];
assign io_network_grant_bits_payload_data[102] = io_manager_grant_bits_data[102];
assign io_network_grant_bits_payload_data[101] = io_manager_grant_bits_data[101];
assign io_network_grant_bits_payload_data[100] = io_manager_grant_bits_data[100];
assign io_network_grant_bits_payload_data[99] = io_manager_grant_bits_data[99];
assign io_network_grant_bits_payload_data[98] = io_manager_grant_bits_data[98];
assign io_network_grant_bits_payload_data[97] = io_manager_grant_bits_data[97];
assign io_network_grant_bits_payload_data[96] = io_manager_grant_bits_data[96];
assign io_network_grant_bits_payload_data[95] = io_manager_grant_bits_data[95];
assign io_network_grant_bits_payload_data[94] = io_manager_grant_bits_data[94];
assign io_network_grant_bits_payload_data[93] = io_manager_grant_bits_data[93];
assign io_network_grant_bits_payload_data[92] = io_manager_grant_bits_data[92];
assign io_network_grant_bits_payload_data[91] = io_manager_grant_bits_data[91];
assign io_network_grant_bits_payload_data[90] = io_manager_grant_bits_data[90];
assign io_network_grant_bits_payload_data[89] = io_manager_grant_bits_data[89];
assign io_network_grant_bits_payload_data[88] = io_manager_grant_bits_data[88];
assign io_network_grant_bits_payload_data[87] = io_manager_grant_bits_data[87];
assign io_network_grant_bits_payload_data[86] = io_manager_grant_bits_data[86];
assign io_network_grant_bits_payload_data[85] = io_manager_grant_bits_data[85];
assign io_network_grant_bits_payload_data[84] = io_manager_grant_bits_data[84];
assign io_network_grant_bits_payload_data[83] = io_manager_grant_bits_data[83];
assign io_network_grant_bits_payload_data[82] = io_manager_grant_bits_data[82];
assign io_network_grant_bits_payload_data[81] = io_manager_grant_bits_data[81];
assign io_network_grant_bits_payload_data[80] = io_manager_grant_bits_data[80];
assign io_network_grant_bits_payload_data[79] = io_manager_grant_bits_data[79];
assign io_network_grant_bits_payload_data[78] = io_manager_grant_bits_data[78];
assign io_network_grant_bits_payload_data[77] = io_manager_grant_bits_data[77];
assign io_network_grant_bits_payload_data[76] = io_manager_grant_bits_data[76];
assign io_network_grant_bits_payload_data[75] = io_manager_grant_bits_data[75];
assign io_network_grant_bits_payload_data[74] = io_manager_grant_bits_data[74];
assign io_network_grant_bits_payload_data[73] = io_manager_grant_bits_data[73];
assign io_network_grant_bits_payload_data[72] = io_manager_grant_bits_data[72];
assign io_network_grant_bits_payload_data[71] = io_manager_grant_bits_data[71];
assign io_network_grant_bits_payload_data[70] = io_manager_grant_bits_data[70];
assign io_network_grant_bits_payload_data[69] = io_manager_grant_bits_data[69];
assign io_network_grant_bits_payload_data[68] = io_manager_grant_bits_data[68];
assign io_network_grant_bits_payload_data[67] = io_manager_grant_bits_data[67];
assign io_network_grant_bits_payload_data[66] = io_manager_grant_bits_data[66];
assign io_network_grant_bits_payload_data[65] = io_manager_grant_bits_data[65];
assign io_network_grant_bits_payload_data[64] = io_manager_grant_bits_data[64];
assign io_network_grant_bits_payload_data[63] = io_manager_grant_bits_data[63];
assign io_network_grant_bits_payload_data[62] = io_manager_grant_bits_data[62];
assign io_network_grant_bits_payload_data[61] = io_manager_grant_bits_data[61];
assign io_network_grant_bits_payload_data[60] = io_manager_grant_bits_data[60];
assign io_network_grant_bits_payload_data[59] = io_manager_grant_bits_data[59];
assign io_network_grant_bits_payload_data[58] = io_manager_grant_bits_data[58];
assign io_network_grant_bits_payload_data[57] = io_manager_grant_bits_data[57];
assign io_network_grant_bits_payload_data[56] = io_manager_grant_bits_data[56];
assign io_network_grant_bits_payload_data[55] = io_manager_grant_bits_data[55];
assign io_network_grant_bits_payload_data[54] = io_manager_grant_bits_data[54];
assign io_network_grant_bits_payload_data[53] = io_manager_grant_bits_data[53];
assign io_network_grant_bits_payload_data[52] = io_manager_grant_bits_data[52];
assign io_network_grant_bits_payload_data[51] = io_manager_grant_bits_data[51];
assign io_network_grant_bits_payload_data[50] = io_manager_grant_bits_data[50];
assign io_network_grant_bits_payload_data[49] = io_manager_grant_bits_data[49];
assign io_network_grant_bits_payload_data[48] = io_manager_grant_bits_data[48];
assign io_network_grant_bits_payload_data[47] = io_manager_grant_bits_data[47];
assign io_network_grant_bits_payload_data[46] = io_manager_grant_bits_data[46];
assign io_network_grant_bits_payload_data[45] = io_manager_grant_bits_data[45];
assign io_network_grant_bits_payload_data[44] = io_manager_grant_bits_data[44];
assign io_network_grant_bits_payload_data[43] = io_manager_grant_bits_data[43];
assign io_network_grant_bits_payload_data[42] = io_manager_grant_bits_data[42];
assign io_network_grant_bits_payload_data[41] = io_manager_grant_bits_data[41];
assign io_network_grant_bits_payload_data[40] = io_manager_grant_bits_data[40];
assign io_network_grant_bits_payload_data[39] = io_manager_grant_bits_data[39];
assign io_network_grant_bits_payload_data[38] = io_manager_grant_bits_data[38];
assign io_network_grant_bits_payload_data[37] = io_manager_grant_bits_data[37];
assign io_network_grant_bits_payload_data[36] = io_manager_grant_bits_data[36];
assign io_network_grant_bits_payload_data[35] = io_manager_grant_bits_data[35];
assign io_network_grant_bits_payload_data[34] = io_manager_grant_bits_data[34];
assign io_network_grant_bits_payload_data[33] = io_manager_grant_bits_data[33];
assign io_network_grant_bits_payload_data[32] = io_manager_grant_bits_data[32];
assign io_network_grant_bits_payload_data[31] = io_manager_grant_bits_data[31];
assign io_network_grant_bits_payload_data[30] = io_manager_grant_bits_data[30];
assign io_network_grant_bits_payload_data[29] = io_manager_grant_bits_data[29];
assign io_network_grant_bits_payload_data[28] = io_manager_grant_bits_data[28];
assign io_network_grant_bits_payload_data[27] = io_manager_grant_bits_data[27];
assign io_network_grant_bits_payload_data[26] = io_manager_grant_bits_data[26];
assign io_network_grant_bits_payload_data[25] = io_manager_grant_bits_data[25];
assign io_network_grant_bits_payload_data[24] = io_manager_grant_bits_data[24];
assign io_network_grant_bits_payload_data[23] = io_manager_grant_bits_data[23];
assign io_network_grant_bits_payload_data[22] = io_manager_grant_bits_data[22];
assign io_network_grant_bits_payload_data[21] = io_manager_grant_bits_data[21];
assign io_network_grant_bits_payload_data[20] = io_manager_grant_bits_data[20];
assign io_network_grant_bits_payload_data[19] = io_manager_grant_bits_data[19];
assign io_network_grant_bits_payload_data[18] = io_manager_grant_bits_data[18];
assign io_network_grant_bits_payload_data[17] = io_manager_grant_bits_data[17];
assign io_network_grant_bits_payload_data[16] = io_manager_grant_bits_data[16];
assign io_network_grant_bits_payload_data[15] = io_manager_grant_bits_data[15];
assign io_network_grant_bits_payload_data[14] = io_manager_grant_bits_data[14];
assign io_network_grant_bits_payload_data[13] = io_manager_grant_bits_data[13];
assign io_network_grant_bits_payload_data[12] = io_manager_grant_bits_data[12];
assign io_network_grant_bits_payload_data[11] = io_manager_grant_bits_data[11];
assign io_network_grant_bits_payload_data[10] = io_manager_grant_bits_data[10];
assign io_network_grant_bits_payload_data[9] = io_manager_grant_bits_data[9];
assign io_network_grant_bits_payload_data[8] = io_manager_grant_bits_data[8];
assign io_network_grant_bits_payload_data[7] = io_manager_grant_bits_data[7];
assign io_network_grant_bits_payload_data[6] = io_manager_grant_bits_data[6];
assign io_network_grant_bits_payload_data[5] = io_manager_grant_bits_data[5];
assign io_network_grant_bits_payload_data[4] = io_manager_grant_bits_data[4];
assign io_network_grant_bits_payload_data[3] = io_manager_grant_bits_data[3];
assign io_network_grant_bits_payload_data[2] = io_manager_grant_bits_data[2];
assign io_network_grant_bits_payload_data[1] = io_manager_grant_bits_data[1];
assign io_network_grant_bits_payload_data[0] = io_manager_grant_bits_data[0];
assign io_network_finish_ready = io_manager_finish_ready;
assign io_network_probe_valid = io_manager_probe_valid;
assign io_network_probe_bits_header_dst[1] = io_manager_probe_bits_client_id[1];
assign io_network_probe_bits_header_dst[0] = io_manager_probe_bits_client_id[0];
assign io_network_probe_bits_payload_addr_block[25] = io_manager_probe_bits_addr_block[25];
assign io_network_probe_bits_payload_addr_block[24] = io_manager_probe_bits_addr_block[24];
assign io_network_probe_bits_payload_addr_block[23] = io_manager_probe_bits_addr_block[23];
assign io_network_probe_bits_payload_addr_block[22] = io_manager_probe_bits_addr_block[22];
assign io_network_probe_bits_payload_addr_block[21] = io_manager_probe_bits_addr_block[21];
assign io_network_probe_bits_payload_addr_block[20] = io_manager_probe_bits_addr_block[20];
assign io_network_probe_bits_payload_addr_block[19] = io_manager_probe_bits_addr_block[19];
assign io_network_probe_bits_payload_addr_block[18] = io_manager_probe_bits_addr_block[18];
assign io_network_probe_bits_payload_addr_block[17] = io_manager_probe_bits_addr_block[17];
assign io_network_probe_bits_payload_addr_block[16] = io_manager_probe_bits_addr_block[16];
assign io_network_probe_bits_payload_addr_block[15] = io_manager_probe_bits_addr_block[15];
assign io_network_probe_bits_payload_addr_block[14] = io_manager_probe_bits_addr_block[14];
assign io_network_probe_bits_payload_addr_block[13] = io_manager_probe_bits_addr_block[13];
assign io_network_probe_bits_payload_addr_block[12] = io_manager_probe_bits_addr_block[12];
assign io_network_probe_bits_payload_addr_block[11] = io_manager_probe_bits_addr_block[11];
assign io_network_probe_bits_payload_addr_block[10] = io_manager_probe_bits_addr_block[10];
assign io_network_probe_bits_payload_addr_block[9] = io_manager_probe_bits_addr_block[9];
assign io_network_probe_bits_payload_addr_block[8] = io_manager_probe_bits_addr_block[8];
assign io_network_probe_bits_payload_addr_block[7] = io_manager_probe_bits_addr_block[7];
assign io_network_probe_bits_payload_addr_block[6] = io_manager_probe_bits_addr_block[6];
assign io_network_probe_bits_payload_addr_block[5] = io_manager_probe_bits_addr_block[5];
assign io_network_probe_bits_payload_addr_block[4] = io_manager_probe_bits_addr_block[4];
assign io_network_probe_bits_payload_addr_block[3] = io_manager_probe_bits_addr_block[3];
assign io_network_probe_bits_payload_addr_block[2] = io_manager_probe_bits_addr_block[2];
assign io_network_probe_bits_payload_addr_block[1] = io_manager_probe_bits_addr_block[1];
assign io_network_probe_bits_payload_addr_block[0] = io_manager_probe_bits_addr_block[0];
assign io_network_probe_bits_payload_p_type[1] = io_manager_probe_bits_p_type[1];
assign io_network_probe_bits_payload_p_type[0] = io_manager_probe_bits_p_type[0];
assign io_network_release_ready = io_manager_release_ready;
endmodule |
module bsg_nasti_client_resp
(
clk_i,
reset_i,
nasti_r_valid_o,
nasti_r_data_o,
nasti_r_ready_i,
resp_valid_i,
resp_data_i,
resp_yumi_o
);
output [72:0] nasti_r_data_o;
input [72:0] resp_data_i;
input clk_i;
input reset_i;
input nasti_r_ready_i;
input resp_valid_i;
output nasti_r_valid_o;
output resp_yumi_o;
wire [72:0] nasti_r_data_o;
wire nasti_r_valid_o,resp_yumi_o,resp_valid_i;
assign nasti_r_data_o[71] = 1'b0;
assign nasti_r_data_o[72] = 1'b0;
assign nasti_r_valid_o = resp_valid_i;
assign nasti_r_data_o[70] = resp_data_i[69];
assign nasti_r_data_o[69] = resp_data_i[68];
assign nasti_r_data_o[68] = resp_data_i[67];
assign nasti_r_data_o[67] = resp_data_i[66];
assign nasti_r_data_o[66] = resp_data_i[65];
assign nasti_r_data_o[65] = resp_data_i[64];
assign nasti_r_data_o[64] = resp_data_i[63];
assign nasti_r_data_o[63] = resp_data_i[62];
assign nasti_r_data_o[62] = resp_data_i[61];
assign nasti_r_data_o[61] = resp_data_i[60];
assign nasti_r_data_o[60] = resp_data_i[59];
assign nasti_r_data_o[59] = resp_data_i[58];
assign nasti_r_data_o[58] = resp_data_i[57];
assign nasti_r_data_o[57] = resp_data_i[56];
assign nasti_r_data_o[56] = resp_data_i[55];
assign nasti_r_data_o[55] = resp_data_i[54];
assign nasti_r_data_o[54] = resp_data_i[53];
assign nasti_r_data_o[53] = resp_data_i[52];
assign nasti_r_data_o[52] = resp_data_i[51];
assign nasti_r_data_o[51] = resp_data_i[50];
assign nasti_r_data_o[50] = resp_data_i[49];
assign nasti_r_data_o[49] = resp_data_i[48];
assign nasti_r_data_o[48] = resp_data_i[47];
assign nasti_r_data_o[47] = resp_data_i[46];
assign nasti_r_data_o[46] = resp_data_i[45];
assign nasti_r_data_o[45] = resp_data_i[44];
assign nasti_r_data_o[44] = resp_data_i[43];
assign nasti_r_data_o[43] = resp_data_i[42];
assign nasti_r_data_o[42] = resp_data_i[41];
assign nasti_r_data_o[41] = resp_data_i[40];
assign nasti_r_data_o[40] = resp_data_i[39];
assign nasti_r_data_o[39] = resp_data_i[38];
assign nasti_r_data_o[38] = resp_data_i[37];
assign nasti_r_data_o[37] = resp_data_i[36];
assign nasti_r_data_o[36] = resp_data_i[35];
assign nasti_r_data_o[35] = resp_data_i[34];
assign nasti_r_data_o[34] = resp_data_i[33];
assign nasti_r_data_o[33] = resp_data_i[32];
assign nasti_r_data_o[32] = resp_data_i[31];
assign nasti_r_data_o[31] = resp_data_i[30];
assign nasti_r_data_o[30] = resp_data_i[29];
assign nasti_r_data_o[29] = resp_data_i[28];
assign nasti_r_data_o[28] = resp_data_i[27];
assign nasti_r_data_o[27] = resp_data_i[26];
assign nasti_r_data_o[26] = resp_data_i[25];
assign nasti_r_data_o[25] = resp_data_i[24];
assign nasti_r_data_o[24] = resp_data_i[23];
assign nasti_r_data_o[23] = resp_data_i[22];
assign nasti_r_data_o[22] = resp_data_i[21];
assign nasti_r_data_o[21] = resp_data_i[20];
assign nasti_r_data_o[20] = resp_data_i[19];
assign nasti_r_data_o[19] = resp_data_i[18];
assign nasti_r_data_o[18] = resp_data_i[17];
assign nasti_r_data_o[17] = resp_data_i[16];
assign nasti_r_data_o[16] = resp_data_i[15];
assign nasti_r_data_o[15] = resp_data_i[14];
assign nasti_r_data_o[14] = resp_data_i[13];
assign nasti_r_data_o[13] = resp_data_i[12];
assign nasti_r_data_o[12] = resp_data_i[11];
assign nasti_r_data_o[11] = resp_data_i[10];
assign nasti_r_data_o[10] = resp_data_i[9];
assign nasti_r_data_o[9] = resp_data_i[8];
assign nasti_r_data_o[8] = resp_data_i[7];
assign nasti_r_data_o[7] = resp_data_i[6];
assign nasti_r_data_o[6] = resp_data_i[70];
assign nasti_r_data_o[5] = resp_data_i[5];
assign nasti_r_data_o[4] = resp_data_i[4];
assign nasti_r_data_o[3] = resp_data_i[3];
assign nasti_r_data_o[2] = resp_data_i[2];
assign nasti_r_data_o[1] = resp_data_i[1];
assign nasti_r_data_o[0] = resp_data_i[0];
assign resp_yumi_o = resp_valid_i & nasti_r_ready_i;
endmodule |
module RRArbiter_4
(
clk,
reset,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_resp,
io_in_2_bits_id,
io_in_2_bits_user,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_resp,
io_in_1_bits_id,
io_in_1_bits_user,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_resp,
io_in_0_bits_id,
io_in_0_bits_user,
io_out_ready,
io_out_valid,
io_out_bits_resp,
io_out_bits_id,
io_out_bits_user,
io_chosen
);
input [1:0] io_in_2_bits_resp;
input [5:0] io_in_2_bits_id;
input [1:0] io_in_1_bits_resp;
input [5:0] io_in_1_bits_id;
input [1:0] io_in_0_bits_resp;
input [5:0] io_in_0_bits_id;
output [1:0] io_out_bits_resp;
output [5:0] io_out_bits_id;
output [1:0] io_chosen;
input clk;
input reset;
input io_in_2_valid;
input io_in_2_bits_user;
input io_in_1_valid;
input io_in_1_bits_user;
input io_in_0_valid;
input io_in_0_bits_user;
input io_out_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_user;
wire [1:0] io_out_bits_resp,io_chosen,T0,T1,T2,T19;
wire [5:0] io_out_bits_id,T15;
wire io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_user,N0,N1,
N2,N3,N4,N5,N6,N7,N8,N9,N10,T7,N11,T3,N12,N13,N14,T4,T6,T8,N15,T10,N16,T23,T27,
T37,T28,T29,T32,T30,T31,T35,T33,T34,T36,T39,T44,T40,T41,T42,T43,T46,T45,T48,T54,
T49,T50,T51,T52,T53,T56,T55,T57,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26;
reg [1:0] last_grant;
assign T36 = last_grant < 1'b0;
assign T37 = last_grant < 1'b0;
always @(posedge clk) begin
if(N19) begin
last_grant[1] <= N21;
end
end
always @(posedge clk) begin
if(N19) begin
last_grant[0] <= N20;
end
end
assign io_chosen = (N0)? { 1'b0, 1'b1 } :
(N1)? T0 : 1'b0;
assign N0 = T7;
assign N1 = N11;
assign T0 = (N2)? { 1'b1, 1'b0 } :
(N3)? T1 : 1'b0;
assign N2 = T3;
assign N3 = N12;
assign T1 = (N4)? { 1'b0, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = io_in_0_valid;
assign N5 = N13;
assign io_out_bits_user = (N6)? io_in_2_bits_user :
(N7)? T10 : 1'b0;
assign N6 = io_chosen[1];
assign N7 = N15;
assign T10 = (N8)? io_in_1_bits_user :
(N9)? io_in_0_bits_user : 1'b0;
assign N8 = io_chosen[0];
assign N9 = N16;
assign io_out_bits_id = (N6)? io_in_2_bits_id :
(N7)? T15 : 1'b0;
assign T15 = (N8)? io_in_1_bits_id :
(N9)? io_in_0_bits_id : 1'b0;
assign io_out_bits_resp = (N6)? io_in_2_bits_resp :
(N7)? T19 : 1'b0;
assign T19 = (N8)? io_in_1_bits_resp :
(N9)? io_in_0_bits_resp : 1'b0;
assign io_out_valid = (N6)? io_in_2_valid :
(N7)? T23 : 1'b0;
assign T23 = (N8)? io_in_1_valid :
(N9)? io_in_0_valid : 1'b0;
assign N19 = (N10)? 1'b1 :
(N23)? 1'b1 :
(N18)? 1'b0 : 1'b0;
assign N10 = reset;
assign { N21, N20 } = (N10)? { 1'b0, 1'b0 } :
(N23)? io_chosen : 1'b0;
assign N11 = ~T7;
assign N12 = ~T3;
assign N13 = ~io_in_0_valid;
assign N14 = ~io_in_1_valid;
assign T2[0] = io_in_1_valid;
assign T2[1] = N14;
assign T3 = io_in_2_valid & T4;
assign T4 = ~last_grant[1];
assign T6 = io_out_ready & io_out_valid;
assign T7 = io_in_1_valid & T8;
assign T8 = ~N24;
assign N24 = last_grant[1] | last_grant[0];
assign N15 = ~io_chosen[1];
assign N16 = ~io_chosen[0];
assign io_in_0_ready = T27 & io_out_ready;
assign T27 = T37 | T28;
assign T28 = ~T29;
assign T29 = T32 | T30;
assign T30 = io_in_2_valid & T31;
assign T31 = ~last_grant[1];
assign T32 = T35 | T33;
assign T33 = io_in_1_valid & T34;
assign T34 = ~N25;
assign N25 = last_grant[1] | last_grant[0];
assign T35 = io_in_0_valid & T36;
assign io_in_1_ready = T39 & io_out_ready;
assign T39 = T44 | T40;
assign T40 = ~T41;
assign T41 = T42 | io_in_0_valid;
assign T42 = T43 | T30;
assign T43 = T35 | T33;
assign T44 = T46 & T45;
assign T45 = ~N26;
assign N26 = last_grant[1] | last_grant[0];
assign T46 = ~T35;
assign io_in_2_ready = T48 & io_out_ready;
assign T48 = T54 | T49;
assign T49 = ~T50;
assign T50 = T51 | io_in_1_valid;
assign T51 = T52 | io_in_0_valid;
assign T52 = T53 | T30;
assign T53 = T35 | T33;
assign T54 = T56 & T55;
assign T55 = ~last_grant[1];
assign T56 = ~T57;
assign T57 = T35 | T33;
assign N17 = T6 | reset;
assign N18 = ~N17;
assign N22 = ~reset;
assign N23 = T6 & N22;
endmodule |
module Arbiter_0
(
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_idx,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_idx,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_idx,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_idx,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_idx,
io_out_ready,
io_out_valid,
io_out_bits_idx,
io_chosen
);
input [5:0] io_in_4_bits_idx;
input [5:0] io_in_3_bits_idx;
input [5:0] io_in_2_bits_idx;
input [5:0] io_in_1_bits_idx;
input [5:0] io_in_0_bits_idx;
output [5:0] io_out_bits_idx;
output [2:0] io_chosen;
input io_in_4_valid;
input io_in_3_valid;
input io_in_2_valid;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
wire [5:0] io_out_bits_idx,T4,T8,T5;
wire [2:0] io_chosen,T0,T1;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,io_out_ready,N12,N13,N14,N15,N16,N17,
N18,T13,T16,T14,T21,T23,T24,T26,T27,T28,T30,T31,T32,T33;
wire [2:1] T2;
assign io_in_0_ready = io_out_ready;
assign io_chosen = (N0)? { 1'b0, 1'b0, 1'b0 } :
(N1)? T0 : 1'b0;
assign N0 = io_in_0_valid;
assign N1 = N12;
assign T0 = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = io_in_1_valid;
assign N3 = N13;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? { T2, T2[1:1] } : 1'b0;
assign N4 = io_in_2_valid;
assign N5 = N14;
assign io_out_bits_idx = (N6)? io_in_4_bits_idx :
(N7)? T4 : 1'b0;
assign N6 = io_chosen[2];
assign N7 = N16;
assign T4 = (N8)? T8 :
(N9)? T5 : 1'b0;
assign N8 = io_chosen[1];
assign N9 = N17;
assign T5 = (N10)? io_in_1_bits_idx :
(N11)? io_in_0_bits_idx : 1'b0;
assign N10 = io_chosen[0];
assign N11 = N18;
assign T8 = (N10)? io_in_3_bits_idx :
(N11)? io_in_2_bits_idx : 1'b0;
assign io_out_valid = (N6)? io_in_4_valid :
(N7)? T13 : 1'b0;
assign T13 = (N8)? T16 :
(N9)? T14 : 1'b0;
assign T14 = (N10)? io_in_1_valid :
(N11)? io_in_0_valid : 1'b0;
assign T16 = (N10)? io_in_3_valid :
(N11)? io_in_2_valid : 1'b0;
assign N12 = ~io_in_0_valid;
assign N13 = ~io_in_1_valid;
assign N14 = ~io_in_2_valid;
assign N15 = ~io_in_3_valid;
assign T2[1] = io_in_3_valid;
assign T2[2] = N15;
assign N16 = ~io_chosen[2];
assign N17 = ~io_chosen[1];
assign N18 = ~io_chosen[0];
assign io_in_1_ready = T21 & io_out_ready;
assign T21 = ~io_in_0_valid;
assign io_in_2_ready = T23 & io_out_ready;
assign T23 = ~T24;
assign T24 = io_in_0_valid | io_in_1_valid;
assign io_in_3_ready = T26 & io_out_ready;
assign T26 = ~T27;
assign T27 = T28 | io_in_2_valid;
assign T28 = io_in_0_valid | io_in_1_valid;
assign io_in_4_ready = T30 & io_out_ready;
assign T30 = ~T31;
assign T31 = T32 | io_in_3_valid;
assign T32 = T33 | io_in_2_valid;
assign T33 = io_in_0_valid | io_in_1_valid;
endmodule |
module LockingRRArbiter_3
(
clk,
reset,
io_in_7_ready,
io_in_7_valid,
io_in_7_bits_addr_block,
io_in_7_bits_p_type,
io_in_7_bits_client_id,
io_in_6_ready,
io_in_6_valid,
io_in_6_bits_addr_block,
io_in_6_bits_p_type,
io_in_6_bits_client_id,
io_in_5_ready,
io_in_5_valid,
io_in_5_bits_addr_block,
io_in_5_bits_p_type,
io_in_5_bits_client_id,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_addr_block,
io_in_4_bits_p_type,
io_in_4_bits_client_id,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_addr_block,
io_in_3_bits_p_type,
io_in_3_bits_client_id,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_addr_block,
io_in_2_bits_p_type,
io_in_2_bits_client_id,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_block,
io_in_1_bits_p_type,
io_in_1_bits_client_id,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_block,
io_in_0_bits_p_type,
io_in_0_bits_client_id,
io_out_ready,
io_out_valid,
io_out_bits_addr_block,
io_out_bits_p_type,
io_out_bits_client_id,
io_chosen
);
input [25:0] io_in_7_bits_addr_block;
input [1:0] io_in_7_bits_p_type;
input [1:0] io_in_7_bits_client_id;
input [25:0] io_in_6_bits_addr_block;
input [1:0] io_in_6_bits_p_type;
input [1:0] io_in_6_bits_client_id;
input [25:0] io_in_5_bits_addr_block;
input [1:0] io_in_5_bits_p_type;
input [1:0] io_in_5_bits_client_id;
input [25:0] io_in_4_bits_addr_block;
input [1:0] io_in_4_bits_p_type;
input [1:0] io_in_4_bits_client_id;
input [25:0] io_in_3_bits_addr_block;
input [1:0] io_in_3_bits_p_type;
input [1:0] io_in_3_bits_client_id;
input [25:0] io_in_2_bits_addr_block;
input [1:0] io_in_2_bits_p_type;
input [1:0] io_in_2_bits_client_id;
input [25:0] io_in_1_bits_addr_block;
input [1:0] io_in_1_bits_p_type;
input [1:0] io_in_1_bits_client_id;
input [25:0] io_in_0_bits_addr_block;
input [1:0] io_in_0_bits_p_type;
input [1:0] io_in_0_bits_client_id;
output [25:0] io_out_bits_addr_block;
output [1:0] io_out_bits_p_type;
output [1:0] io_out_bits_client_id;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_7_valid;
input io_in_6_valid;
input io_in_5_valid;
input io_in_4_valid;
input io_in_3_valid;
input io_in_2_valid;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_7_ready;
output io_in_6_ready;
output io_in_5_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
wire [25:0] io_out_bits_addr_block,T68,T62,T65,T63,T71,T69;
wire [1:0] io_out_bits_p_type,io_out_bits_client_id,T11,T12,T40,T33,T37,T34,T43,T41,T54,
T48,T51,T49,T57,T55;
wire [2:0] io_chosen,choose,T1,T2,T3,T4,T5,T6,T7,T8,T9,T10;
wire io_in_7_ready,io_in_6_ready,io_in_5_ready,io_in_4_ready,io_in_3_ready,
io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,
N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,
N31,N32,N33,N34,N35,T28,N36,T26,N37,T24,N38,T22,N39,T20,N40,T18,N41,T14,N42,N43,
N44,N45,N46,N47,N48,N49,T15,T17,T19,T21,T23,T25,T27,T29,T31,N50,N51,N52,T82,T76,
T79,T77,T85,T83,T90,T91,T116,T92,T93,T96,T94,T95,T99,T97,T98,T102,T100,T101,T105,
T103,T104,T108,T106,T107,T111,T109,T110,T114,T112,T113,T115,T119,T120,T130,T121,
T122,T123,T124,T125,T126,T127,T128,T129,T132,T131,T135,T136,T147,T137,T138,T139,
T140,T141,T142,T143,T144,T145,T146,T149,T148,T150,T153,T154,T166,T155,T156,T157,
T158,T159,T160,T161,T162,T163,T164,T165,T168,T167,T169,T170,T173,T174,T187,T175,
T176,T177,T178,T179,T180,T181,T182,T183,T184,T185,T186,T189,T188,T190,T191,T192,
T195,T196,T210,T197,T198,T199,T200,T201,T202,T203,T204,T205,T206,T207,T208,T209,
T212,T211,T213,T214,T215,T216,T219,T220,T235,T221,T222,T223,T224,T225,T226,T227,
T228,T229,T230,T231,T232,T233,T234,T237,T236,T238,T239,T240,T241,T242,T245,T246,
T262,T247,T248,T249,T250,T251,T252,T253,T254,T255,T256,T257,T258,T259,T260,T261,
T264,T263,T265,T266,T267,T268,T269,T270,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,
N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,
N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99;
wire [0:0] T13;
reg [2:0] last_grant,lockIdx;
reg locked;
assign T15 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T19 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T21 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T25 = last_grant < { 1'b1, 1'b1 };
assign T95 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T98 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T101 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T107 = last_grant < { 1'b1, 1'b1 };
assign T115 = last_grant < 1'b0;
assign T116 = last_grant < 1'b0;
assign T167 = last_grant < { 1'b1, 1'b1 };
assign T211 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T236 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T263 = last_grant < { 1'b1, 1'b1, 1'b1 };
always @(posedge clk) begin
if(N55) begin
last_grant[2] <= N58;
end
end
always @(posedge clk) begin
if(N55) begin
last_grant[1] <= N57;
end
end
always @(posedge clk) begin
if(N55) begin
last_grant[0] <= N56;
end
end
always @(posedge clk) begin
if(reset) begin
lockIdx[2] <= 1'b1;
end
end
always @(posedge clk) begin
if(reset) begin
lockIdx[1] <= 1'b1;
end
end
always @(posedge clk) begin
if(reset) begin
lockIdx[0] <= 1'b1;
end
end
always @(posedge clk) begin
if(N61) begin
locked <= 1'b0;
end
end
assign N65 = lockIdx[1] & lockIdx[2];
assign N66 = lockIdx[0] & N65;
assign N67 = ~lockIdx[2];
assign N68 = ~lockIdx[1];
assign N69 = N68 | N67;
assign N70 = lockIdx[0] | N69;
assign N71 = ~N70;
assign N72 = ~lockIdx[0];
assign N73 = lockIdx[1] | N67;
assign N74 = N72 | N73;
assign N75 = ~N74;
assign N76 = lockIdx[1] | N67;
assign N77 = lockIdx[0] | N76;
assign N78 = ~N77;
assign N79 = N68 | lockIdx[2];
assign N80 = N72 | N79;
assign N81 = ~N80;
assign N82 = N68 | lockIdx[2];
assign N83 = lockIdx[0] | N82;
assign N84 = ~N83;
assign N85 = lockIdx[1] | lockIdx[2];
assign N86 = N72 | N85;
assign N87 = ~N86;
assign N88 = lockIdx[1] | lockIdx[2];
assign N89 = lockIdx[0] | N88;
assign N90 = ~N89;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N35;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T28;
assign N3 = N36;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T26;
assign N5 = N37;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T24;
assign N7 = N38;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T22;
assign N9 = N39;
assign T4 = (N10)? { 1'b1, 1'b0, 1'b1 } :
(N11)? T5 : 1'b0;
assign N10 = T20;
assign N11 = N40;
assign T5 = (N12)? { 1'b1, 1'b1, 1'b0 } :
(N13)? T6 : 1'b0;
assign N12 = T18;
assign N13 = N41;
assign T6 = (N14)? { 1'b1, 1'b1, 1'b1 } :
(N15)? T7 : 1'b0;
assign N14 = T14;
assign N15 = N42;
assign T7 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T8 : 1'b0;
assign N16 = io_in_0_valid;
assign N17 = N43;
assign T8 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T9 : 1'b0;
assign N18 = io_in_1_valid;
assign N19 = N44;
assign T9 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? T10 : 1'b0;
assign N20 = io_in_2_valid;
assign N21 = N45;
assign T10[1:0] = (N22)? { 1'b1, 1'b1 } :
(N23)? T11 : 1'b0;
assign N22 = io_in_3_valid;
assign N23 = T10[2];
assign T11 = (N24)? { 1'b0, 1'b0 } :
(N25)? T12 : 1'b0;
assign N24 = io_in_4_valid;
assign N25 = N47;
assign T12[0] = (N26)? 1'b1 :
(N27)? T13[0] : 1'b0;
assign N26 = io_in_5_valid;
assign N27 = T12[1];
assign io_out_bits_client_id = (N28)? T40 :
(N29)? T33 : 1'b0;
assign N28 = io_chosen[2];
assign N29 = N50;
assign T33 = (N30)? T37 :
(N31)? T34 : 1'b0;
assign N30 = io_chosen[1];
assign N31 = N51;
assign T34 = (N32)? io_in_1_bits_client_id :
(N33)? io_in_0_bits_client_id : 1'b0;
assign N32 = io_chosen[0];
assign N33 = N52;
assign T37 = (N32)? io_in_3_bits_client_id :
(N33)? io_in_2_bits_client_id : 1'b0;
assign T40 = (N30)? T43 :
(N31)? T41 : 1'b0;
assign T41 = (N32)? io_in_5_bits_client_id :
(N33)? io_in_4_bits_client_id : 1'b0;
assign T43 = (N32)? io_in_7_bits_client_id :
(N33)? io_in_6_bits_client_id : 1'b0;
assign io_out_bits_p_type = (N28)? T54 :
(N29)? T48 : 1'b0;
assign T48 = (N30)? T51 :
(N31)? T49 : 1'b0;
assign T49 = (N32)? io_in_1_bits_p_type :
(N33)? io_in_0_bits_p_type : 1'b0;
assign T51 = (N32)? io_in_3_bits_p_type :
(N33)? io_in_2_bits_p_type : 1'b0;
assign T54 = (N30)? T57 :
(N31)? T55 : 1'b0;
assign T55 = (N32)? io_in_5_bits_p_type :
(N33)? io_in_4_bits_p_type : 1'b0;
assign T57 = (N32)? io_in_7_bits_p_type :
(N33)? io_in_6_bits_p_type : 1'b0;
assign io_out_bits_addr_block = (N28)? T68 :
(N29)? T62 : 1'b0;
assign T62 = (N30)? T65 :
(N31)? T63 : 1'b0;
assign T63 = (N32)? io_in_1_bits_addr_block :
(N33)? io_in_0_bits_addr_block : 1'b0;
assign T65 = (N32)? io_in_3_bits_addr_block :
(N33)? io_in_2_bits_addr_block : 1'b0;
assign T68 = (N30)? T71 :
(N31)? T69 : 1'b0;
assign T69 = (N32)? io_in_5_bits_addr_block :
(N33)? io_in_4_bits_addr_block : 1'b0;
assign T71 = (N32)? io_in_7_bits_addr_block :
(N33)? io_in_6_bits_addr_block : 1'b0;
assign io_out_valid = (N28)? T82 :
(N29)? T76 : 1'b0;
assign T76 = (N30)? T79 :
(N31)? T77 : 1'b0;
assign T77 = (N32)? io_in_1_valid :
(N33)? io_in_0_valid : 1'b0;
assign T79 = (N32)? io_in_3_valid :
(N33)? io_in_2_valid : 1'b0;
assign T82 = (N30)? T85 :
(N31)? T83 : 1'b0;
assign T83 = (N32)? io_in_5_valid :
(N33)? io_in_4_valid : 1'b0;
assign T85 = (N32)? io_in_7_valid :
(N33)? io_in_6_valid : 1'b0;
assign T90 = (N0)? N90 :
(N1)? T91 : 1'b0;
assign T119 = (N0)? N87 :
(N1)? T120 : 1'b0;
assign T135 = (N0)? N84 :
(N1)? T136 : 1'b0;
assign T153 = (N0)? N81 :
(N1)? T154 : 1'b0;
assign T173 = (N0)? N78 :
(N1)? T174 : 1'b0;
assign T195 = (N0)? N75 :
(N1)? T196 : 1'b0;
assign T219 = (N0)? N71 :
(N1)? T220 : 1'b0;
assign T245 = (N0)? N66 :
(N1)? T246 : 1'b0;
assign N55 = (N34)? 1'b1 :
(N63)? 1'b1 :
(N54)? 1'b0 : 1'b0;
assign N34 = reset;
assign { N58, N57, N56 } = (N34)? { 1'b0, 1'b0, 1'b0 } :
(N63)? io_chosen : 1'b0;
assign N61 = (N34)? 1'b1 :
(N64)? 1'b1 :
(N60)? 1'b0 : 1'b0;
assign N35 = ~locked;
assign N36 = ~T28;
assign N37 = ~T26;
assign N38 = ~T24;
assign N39 = ~T22;
assign N40 = ~T20;
assign N41 = ~T18;
assign N42 = ~T14;
assign N43 = ~io_in_0_valid;
assign N44 = ~io_in_1_valid;
assign N45 = ~io_in_2_valid;
assign N46 = ~io_in_3_valid;
assign T10[2] = N46;
assign N47 = ~io_in_4_valid;
assign N48 = ~io_in_5_valid;
assign T12[1] = N48;
assign N49 = ~io_in_6_valid;
assign T13[0] = N49;
assign T14 = io_in_7_valid & T15;
assign T17 = io_out_ready & io_out_valid;
assign T18 = io_in_6_valid & T19;
assign T20 = io_in_5_valid & T21;
assign T22 = io_in_4_valid & T23;
assign T23 = ~last_grant[2];
assign T24 = io_in_3_valid & T25;
assign T26 = io_in_2_valid & T27;
assign T27 = ~N91;
assign N91 = last_grant[2] | last_grant[1];
assign T28 = io_in_1_valid & T29;
assign T29 = ~N93;
assign N93 = N92 | last_grant[0];
assign N92 = last_grant[2] | last_grant[1];
assign T31 = io_out_valid & io_out_ready;
assign N50 = ~io_chosen[2];
assign N51 = ~io_chosen[1];
assign N52 = ~io_chosen[0];
assign io_in_0_ready = T90 & io_out_ready;
assign T91 = T116 | T92;
assign T92 = ~T93;
assign T93 = T96 | T94;
assign T94 = io_in_7_valid & T95;
assign T96 = T99 | T97;
assign T97 = io_in_6_valid & T98;
assign T99 = T102 | T100;
assign T100 = io_in_5_valid & T101;
assign T102 = T105 | T103;
assign T103 = io_in_4_valid & T104;
assign T104 = ~last_grant[2];
assign T105 = T108 | T106;
assign T106 = io_in_3_valid & T107;
assign T108 = T111 | T109;
assign T109 = io_in_2_valid & T110;
assign T110 = ~N94;
assign N94 = last_grant[2] | last_grant[1];
assign T111 = T114 | T112;
assign T112 = io_in_1_valid & T113;
assign T113 = ~N96;
assign N96 = N95 | last_grant[0];
assign N95 = last_grant[2] | last_grant[1];
assign T114 = io_in_0_valid & T115;
assign io_in_1_ready = T119 & io_out_ready;
assign T120 = T130 | T121;
assign T121 = ~T122;
assign T122 = T123 | io_in_0_valid;
assign T123 = T124 | T94;
assign T124 = T125 | T97;
assign T125 = T126 | T100;
assign T126 = T127 | T103;
assign T127 = T128 | T106;
assign T128 = T129 | T109;
assign T129 = T114 | T112;
assign T130 = T132 & T131;
assign T131 = ~N98;
assign N98 = N97 | last_grant[0];
assign N97 = last_grant[2] | last_grant[1];
assign T132 = ~T114;
assign io_in_2_ready = T135 & io_out_ready;
assign T136 = T147 | T137;
assign T137 = ~T138;
assign T138 = T139 | io_in_1_valid;
assign T139 = T140 | io_in_0_valid;
assign T140 = T141 | T94;
assign T141 = T142 | T97;
assign T142 = T143 | T100;
assign T143 = T144 | T103;
assign T144 = T145 | T106;
assign T145 = T146 | T109;
assign T146 = T114 | T112;
assign T147 = T149 & T148;
assign T148 = ~N99;
assign N99 = last_grant[2] | last_grant[1];
assign T149 = ~T150;
assign T150 = T114 | T112;
assign io_in_3_ready = T153 & io_out_ready;
assign T154 = T166 | T155;
assign T155 = ~T156;
assign T156 = T157 | io_in_2_valid;
assign T157 = T158 | io_in_1_valid;
assign T158 = T159 | io_in_0_valid;
assign T159 = T160 | T94;
assign T160 = T161 | T97;
assign T161 = T162 | T100;
assign T162 = T163 | T103;
assign T163 = T164 | T106;
assign T164 = T165 | T109;
assign T165 = T114 | T112;
assign T166 = T168 & T167;
assign T168 = ~T169;
assign T169 = T170 | T109;
assign T170 = T114 | T112;
assign io_in_4_ready = T173 & io_out_ready;
assign T174 = T187 | T175;
assign T175 = ~T176;
assign T176 = T177 | io_in_3_valid;
assign T177 = T178 | io_in_2_valid;
assign T178 = T179 | io_in_1_valid;
assign T179 = T180 | io_in_0_valid;
assign T180 = T181 | T94;
assign T181 = T182 | T97;
assign T182 = T183 | T100;
assign T183 = T184 | T103;
assign T184 = T185 | T106;
assign T185 = T186 | T109;
assign T186 = T114 | T112;
assign T187 = T189 & T188;
assign T188 = ~last_grant[2];
assign T189 = ~T190;
assign T190 = T191 | T106;
assign T191 = T192 | T109;
assign T192 = T114 | T112;
assign io_in_5_ready = T195 & io_out_ready;
assign T196 = T210 | T197;
assign T197 = ~T198;
assign T198 = T199 | io_in_4_valid;
assign T199 = T200 | io_in_3_valid;
assign T200 = T201 | io_in_2_valid;
assign T201 = T202 | io_in_1_valid;
assign T202 = T203 | io_in_0_valid;
assign T203 = T204 | T94;
assign T204 = T205 | T97;
assign T205 = T206 | T100;
assign T206 = T207 | T103;
assign T207 = T208 | T106;
assign T208 = T209 | T109;
assign T209 = T114 | T112;
assign T210 = T212 & T211;
assign T212 = ~T213;
assign T213 = T214 | T103;
assign T214 = T215 | T106;
assign T215 = T216 | T109;
assign T216 = T114 | T112;
assign io_in_6_ready = T219 & io_out_ready;
assign T220 = T235 | T221;
assign T221 = ~T222;
assign T222 = T223 | io_in_5_valid;
assign T223 = T224 | io_in_4_valid;
assign T224 = T225 | io_in_3_valid;
assign T225 = T226 | io_in_2_valid;
assign T226 = T227 | io_in_1_valid;
assign T227 = T228 | io_in_0_valid;
assign T228 = T229 | T94;
assign T229 = T230 | T97;
assign T230 = T231 | T100;
assign T231 = T232 | T103;
assign T232 = T233 | T106;
assign T233 = T234 | T109;
assign T234 = T114 | T112;
assign T235 = T237 & T236;
assign T237 = ~T238;
assign T238 = T239 | T100;
assign T239 = T240 | T103;
assign T240 = T241 | T106;
assign T241 = T242 | T109;
assign T242 = T114 | T112;
assign io_in_7_ready = T245 & io_out_ready;
assign T246 = T262 | T247;
assign T247 = ~T248;
assign T248 = T249 | io_in_6_valid;
assign T249 = T250 | io_in_5_valid;
assign T250 = T251 | io_in_4_valid;
assign T251 = T252 | io_in_3_valid;
assign T252 = T253 | io_in_2_valid;
assign T253 = T254 | io_in_1_valid;
assign T254 = T255 | io_in_0_valid;
assign T255 = T256 | T94;
assign T256 = T257 | T97;
assign T257 = T258 | T100;
assign T258 = T259 | T103;
assign T259 = T260 | T106;
assign T260 = T261 | T109;
assign T261 = T114 | T112;
assign T262 = T264 & T263;
assign T264 = ~T265;
assign T265 = T266 | T97;
assign T266 = T267 | T100;
assign T267 = T268 | T103;
assign T268 = T269 | T106;
assign T269 = T270 | T109;
assign T270 = T114 | T112;
assign N53 = T17 | reset;
assign N54 = ~N53;
assign N59 = T31 | reset;
assign N60 = ~N59;
assign N62 = ~reset;
assign N63 = T17 & N62;
assign N64 = T31 & N62;
endmodule |
module LockingRRArbiter_0
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_addr_beat,
io_in_1_bits_is_builtin_type,
io_in_1_bits_a_type,
io_in_1_bits_union,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_addr_beat,
io_in_0_bits_is_builtin_type,
io_in_0_bits_a_type,
io_in_0_bits_union,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_addr_beat,
io_out_bits_is_builtin_type,
io_out_bits_a_type,
io_out_bits_union,
io_out_bits_data,
io_chosen
);
input [25:0] io_in_1_bits_addr_block;
input [5:0] io_in_1_bits_client_xact_id;
input [1:0] io_in_1_bits_addr_beat;
input [2:0] io_in_1_bits_a_type;
input [16:0] io_in_1_bits_union;
input [127:0] io_in_1_bits_data;
input [25:0] io_in_0_bits_addr_block;
input [5:0] io_in_0_bits_client_xact_id;
input [1:0] io_in_0_bits_addr_beat;
input [2:0] io_in_0_bits_a_type;
input [16:0] io_in_0_bits_union;
input [127:0] io_in_0_bits_data;
output [25:0] io_out_bits_addr_block;
output [5:0] io_out_bits_client_xact_id;
output [1:0] io_out_bits_addr_beat;
output [2:0] io_out_bits_a_type;
output [16:0] io_out_bits_union;
output [127:0] io_out_bits_data;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_is_builtin_type;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_is_builtin_type;
output io_chosen;
wire [25:0] io_out_bits_addr_block;
wire [5:0] io_out_bits_client_xact_id;
wire [1:0] io_out_bits_addr_beat,T19;
wire [2:0] io_out_bits_a_type;
wire [16:0] io_out_bits_union;
wire [127:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_is_builtin_type,io_chosen,
N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,choose,T2,N10,T3,T5,T9,T8,T11,T10,T14,T12,T22,T17,
T18,T23,N11,T34,T35,T42,T36,T37,T40,T38,T39,T41,T45,T46,T50,T47,T48,T49,T52,T51,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45;
reg last_grant,lockIdx,locked;
reg [1:0] R20;
assign T18 = T19 == 1'b0;
assign T41 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T42 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N14) begin
last_grant <= N15;
end
end
always @(posedge clk) begin
if(N18) begin
lockIdx <= N19;
end
end
always @(posedge clk) begin
if(N23) begin
locked <= N24;
end
end
always @(posedge clk) begin
if(N27) begin
R20[1] <= N29;
end
end
always @(posedge clk) begin
if(N27) begin
R20[0] <= N28;
end
end
assign N38 = ~T8;
assign N39 = ~lockIdx;
assign N40 = ~io_out_bits_a_type[1];
assign N41 = ~io_out_bits_a_type[0];
assign N42 = N40 | io_out_bits_a_type[2];
assign N43 = N41 | N42;
assign N44 = ~N43;
assign N45 = ~io_in_0_valid;
assign T19 = R20 + 1'b1;
assign io_chosen = (N2)? lockIdx :
(N3)? choose : 1'b0;
assign N2 = locked;
assign N3 = N9;
assign choose = (N4)? 1'b1 :
(N5)? N45 : 1'b0;
assign N4 = T2;
assign N5 = N10;
assign io_out_bits_data = (N6)? io_in_1_bits_data :
(N7)? io_in_0_bits_data : 1'b0;
assign N6 = io_chosen;
assign N7 = N11;
assign io_out_bits_union = (N6)? io_in_1_bits_union :
(N7)? io_in_0_bits_union : 1'b0;
assign io_out_bits_a_type = (N6)? io_in_1_bits_a_type :
(N7)? io_in_0_bits_a_type : 1'b0;
assign io_out_bits_is_builtin_type = (N6)? io_in_1_bits_is_builtin_type :
(N7)? io_in_0_bits_is_builtin_type : 1'b0;
assign io_out_bits_addr_beat = (N6)? io_in_1_bits_addr_beat :
(N7)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_bits_client_xact_id = (N6)? io_in_1_bits_client_xact_id :
(N7)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N6)? io_in_1_bits_addr_block :
(N7)? io_in_0_bits_addr_block : 1'b0;
assign io_out_valid = (N6)? io_in_1_valid :
(N7)? io_in_0_valid : 1'b0;
assign T34 = (N2)? N39 :
(N3)? T35 : 1'b0;
assign T45 = (N2)? lockIdx :
(N3)? T46 : 1'b0;
assign N14 = (N8)? 1'b1 :
(N31)? 1'b1 :
(N13)? 1'b0 : 1'b0;
assign N8 = reset;
assign N15 = (N8)? 1'b0 :
(N31)? io_chosen : 1'b0;
assign N18 = (N8)? 1'b1 :
(N32)? 1'b1 :
(N17)? 1'b0 : 1'b0;
assign N19 = (N8)? 1'b1 :
(N32)? N38 : 1'b0;
assign N23 = (N8)? 1'b1 :
(N33)? 1'b1 :
(N36)? 1'b1 :
(N22)? 1'b0 : 1'b0;
assign N24 = (N8)? 1'b0 :
(N33)? 1'b0 :
(N36)? T17 : 1'b0;
assign N27 = (N8)? 1'b1 :
(N37)? 1'b1 :
(N26)? 1'b0 : 1'b0;
assign { N29, N28 } = (N8)? { 1'b0, 1'b0 } :
(N37)? T19 : 1'b0;
assign N9 = ~locked;
assign N10 = ~T2;
assign T2 = io_in_1_valid & T3;
assign T3 = ~last_grant;
assign T5 = io_out_ready & io_out_valid;
assign T8 = io_in_0_ready & io_in_0_valid;
assign T9 = T11 & T10;
assign T10 = ~locked;
assign T11 = T14 & T12;
assign T12 = io_out_bits_is_builtin_type & N44;
assign T14 = io_out_valid & io_out_ready;
assign T17 = ~T18;
assign T22 = T14 & T23;
assign T23 = ~T12;
assign N11 = ~io_chosen;
assign io_in_0_ready = T34 & io_out_ready;
assign T35 = T42 | T36;
assign T36 = ~T37;
assign T37 = T40 | T38;
assign T38 = io_in_1_valid & T39;
assign T39 = ~last_grant;
assign T40 = io_in_0_valid & T41;
assign io_in_1_ready = T45 & io_out_ready;
assign T46 = T50 | T47;
assign T47 = ~T48;
assign T48 = T49 | io_in_0_valid;
assign T49 = T40 | T38;
assign T50 = T52 & T51;
assign T51 = ~last_grant;
assign T52 = ~T40;
assign N12 = T5 | reset;
assign N13 = ~N12;
assign N16 = T9 | reset;
assign N17 = ~N16;
assign N20 = T22 | reset;
assign N21 = T11 | N20;
assign N22 = ~N21;
assign N25 = T11 | reset;
assign N26 = ~N25;
assign N30 = ~reset;
assign N31 = T5 & N30;
assign N32 = T9 & N30;
assign N33 = T22 & N30;
assign N34 = ~T22;
assign N35 = N30 & N34;
assign N36 = T11 & N35;
assign N37 = T11 & N30;
endmodule |
module Arbiter_1
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_idx,
io_in_1_bits_way_en,
io_in_1_bits_data_tag,
io_in_1_bits_data_coh_state,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_idx,
io_in_0_bits_way_en,
io_in_0_bits_data_tag,
io_in_0_bits_data_coh_state,
io_out_ready,
io_out_valid,
io_out_bits_idx,
io_out_bits_way_en,
io_out_bits_data_tag,
io_out_bits_data_coh_state,
io_chosen
);
input [5:0] io_in_1_bits_idx;
input [3:0] io_in_1_bits_way_en;
input [19:0] io_in_1_bits_data_tag;
input [1:0] io_in_1_bits_data_coh_state;
input [5:0] io_in_0_bits_idx;
input [3:0] io_in_0_bits_way_en;
input [19:0] io_in_0_bits_data_tag;
input [1:0] io_in_0_bits_data_coh_state;
output [5:0] io_out_bits_idx;
output [3:0] io_out_bits_way_en;
output [19:0] io_out_bits_data_tag;
output [1:0] io_out_bits_data_coh_state;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_chosen;
wire [5:0] io_out_bits_idx;
wire [3:0] io_out_bits_way_en;
wire [19:0] io_out_bits_data_tag;
wire [1:0] io_out_bits_data_coh_state;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T7;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_data_coh_state = (N0)? io_in_1_bits_data_coh_state :
(N1)? io_in_0_bits_data_coh_state : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_data_tag = (N0)? io_in_1_bits_data_tag :
(N1)? io_in_0_bits_data_tag : 1'b0;
assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en :
(N1)? io_in_0_bits_way_en : 1'b0;
assign io_out_bits_idx = (N0)? io_in_1_bits_idx :
(N1)? io_in_0_bits_idx : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T7 & io_out_ready;
assign T7 = ~io_in_0_valid;
endmodule |
module bsg_circular_ptr_slots_p128_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [6:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12;
wire [6:0] genblk1_genblk1_ptr_r_p1;
reg [6:0] o;
always @(posedge clk) begin
if(N12) begin
o[6] <= N9;
end
end
always @(posedge clk) begin
if(N12) begin
o[5] <= N8;
end
end
always @(posedge clk) begin
if(N12) begin
o[4] <= N7;
end
end
always @(posedge clk) begin
if(N12) begin
o[3] <= N6;
end
end
always @(posedge clk) begin
if(N12) begin
o[2] <= N5;
end
end
always @(posedge clk) begin
if(N12) begin
o[1] <= N4;
end
end
always @(posedge clk) begin
if(N12) begin
o[0] <= N3;
end
end
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N10 = ~add_i[0];
assign N11 = N10 & N2;
assign N12 = ~N11;
endmodule |
module RRArbiter_0
(
clk,
reset,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_rd,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_rd,
io_out_bits_data,
io_chosen
);
input [4:0] io_in_0_bits_rd;
input [63:0] io_in_0_bits_data;
output [4:0] io_out_bits_rd;
output [63:0] io_out_bits_data;
input clk;
input reset;
input io_in_0_valid;
input io_out_ready;
output io_in_0_ready;
output io_out_valid;
output io_chosen;
wire [4:0] io_out_bits_rd;
wire [63:0] io_out_bits_data;
wire io_in_0_ready,io_out_valid,io_chosen,N0,N1,N2,io_in_0_valid,T1,T7,T2,T3,T4,T6,
N3,N4,N5,N6,N7;
reg last_grant;
assign io_chosen = 1'b0;
assign io_out_valid = io_in_0_valid;
assign io_out_bits_rd[4] = io_in_0_bits_rd[4];
assign io_out_bits_rd[3] = io_in_0_bits_rd[3];
assign io_out_bits_rd[2] = io_in_0_bits_rd[2];
assign io_out_bits_rd[1] = io_in_0_bits_rd[1];
assign io_out_bits_rd[0] = io_in_0_bits_rd[0];
assign io_out_bits_data[63] = io_in_0_bits_data[63];
assign io_out_bits_data[62] = io_in_0_bits_data[62];
assign io_out_bits_data[61] = io_in_0_bits_data[61];
assign io_out_bits_data[60] = io_in_0_bits_data[60];
assign io_out_bits_data[59] = io_in_0_bits_data[59];
assign io_out_bits_data[58] = io_in_0_bits_data[58];
assign io_out_bits_data[57] = io_in_0_bits_data[57];
assign io_out_bits_data[56] = io_in_0_bits_data[56];
assign io_out_bits_data[55] = io_in_0_bits_data[55];
assign io_out_bits_data[54] = io_in_0_bits_data[54];
assign io_out_bits_data[53] = io_in_0_bits_data[53];
assign io_out_bits_data[52] = io_in_0_bits_data[52];
assign io_out_bits_data[51] = io_in_0_bits_data[51];
assign io_out_bits_data[50] = io_in_0_bits_data[50];
assign io_out_bits_data[49] = io_in_0_bits_data[49];
assign io_out_bits_data[48] = io_in_0_bits_data[48];
assign io_out_bits_data[47] = io_in_0_bits_data[47];
assign io_out_bits_data[46] = io_in_0_bits_data[46];
assign io_out_bits_data[45] = io_in_0_bits_data[45];
assign io_out_bits_data[44] = io_in_0_bits_data[44];
assign io_out_bits_data[43] = io_in_0_bits_data[43];
assign io_out_bits_data[42] = io_in_0_bits_data[42];
assign io_out_bits_data[41] = io_in_0_bits_data[41];
assign io_out_bits_data[40] = io_in_0_bits_data[40];
assign io_out_bits_data[39] = io_in_0_bits_data[39];
assign io_out_bits_data[38] = io_in_0_bits_data[38];
assign io_out_bits_data[37] = io_in_0_bits_data[37];
assign io_out_bits_data[36] = io_in_0_bits_data[36];
assign io_out_bits_data[35] = io_in_0_bits_data[35];
assign io_out_bits_data[34] = io_in_0_bits_data[34];
assign io_out_bits_data[33] = io_in_0_bits_data[33];
assign io_out_bits_data[32] = io_in_0_bits_data[32];
assign io_out_bits_data[31] = io_in_0_bits_data[31];
assign io_out_bits_data[30] = io_in_0_bits_data[30];
assign io_out_bits_data[29] = io_in_0_bits_data[29];
assign io_out_bits_data[28] = io_in_0_bits_data[28];
assign io_out_bits_data[27] = io_in_0_bits_data[27];
assign io_out_bits_data[26] = io_in_0_bits_data[26];
assign io_out_bits_data[25] = io_in_0_bits_data[25];
assign io_out_bits_data[24] = io_in_0_bits_data[24];
assign io_out_bits_data[23] = io_in_0_bits_data[23];
assign io_out_bits_data[22] = io_in_0_bits_data[22];
assign io_out_bits_data[21] = io_in_0_bits_data[21];
assign io_out_bits_data[20] = io_in_0_bits_data[20];
assign io_out_bits_data[19] = io_in_0_bits_data[19];
assign io_out_bits_data[18] = io_in_0_bits_data[18];
assign io_out_bits_data[17] = io_in_0_bits_data[17];
assign io_out_bits_data[16] = io_in_0_bits_data[16];
assign io_out_bits_data[15] = io_in_0_bits_data[15];
assign io_out_bits_data[14] = io_in_0_bits_data[14];
assign io_out_bits_data[13] = io_in_0_bits_data[13];
assign io_out_bits_data[12] = io_in_0_bits_data[12];
assign io_out_bits_data[11] = io_in_0_bits_data[11];
assign io_out_bits_data[10] = io_in_0_bits_data[10];
assign io_out_bits_data[9] = io_in_0_bits_data[9];
assign io_out_bits_data[8] = io_in_0_bits_data[8];
assign io_out_bits_data[7] = io_in_0_bits_data[7];
assign io_out_bits_data[6] = io_in_0_bits_data[6];
assign io_out_bits_data[5] = io_in_0_bits_data[5];
assign io_out_bits_data[4] = io_in_0_bits_data[4];
assign io_out_bits_data[3] = io_in_0_bits_data[3];
assign io_out_bits_data[2] = io_in_0_bits_data[2];
assign io_out_bits_data[1] = io_in_0_bits_data[1];
assign io_out_bits_data[0] = io_in_0_bits_data[0];
assign T4 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T7 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N5) begin
last_grant <= 1'b0;
end
end
assign N5 = (N2)? 1'b1 :
(N7)? 1'b1 :
(N4)? 1'b0 : 1'b0;
assign N2 = reset;
assign io_in_0_ready = T1 & io_out_ready;
assign T1 = T7 | T2;
assign T2 = ~T3;
assign T3 = io_in_0_valid & T4;
assign T6 = io_out_ready & io_in_0_valid;
assign N3 = T6 | reset;
assign N4 = ~N3;
assign N6 = ~reset;
assign N7 = T6 & N6;
endmodule |
module JunctionsPeekingArbiter_0
(
clk,
reset,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_resp,
io_in_2_bits_data,
io_in_2_bits_last,
io_in_2_bits_id,
io_in_2_bits_user,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_resp,
io_in_1_bits_data,
io_in_1_bits_last,
io_in_1_bits_id,
io_in_1_bits_user,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_resp,
io_in_0_bits_data,
io_in_0_bits_last,
io_in_0_bits_id,
io_in_0_bits_user,
io_out_ready,
io_out_valid,
io_out_bits_resp,
io_out_bits_data,
io_out_bits_last,
io_out_bits_id,
io_out_bits_user
);
input [1:0] io_in_2_bits_resp;
input [63:0] io_in_2_bits_data;
input [5:0] io_in_2_bits_id;
input [1:0] io_in_1_bits_resp;
input [63:0] io_in_1_bits_data;
input [5:0] io_in_1_bits_id;
input [1:0] io_in_0_bits_resp;
input [63:0] io_in_0_bits_data;
input [5:0] io_in_0_bits_id;
output [1:0] io_out_bits_resp;
output [63:0] io_out_bits_data;
output [5:0] io_out_bits_id;
input clk;
input reset;
input io_in_2_valid;
input io_in_2_bits_last;
input io_in_2_bits_user;
input io_in_1_valid;
input io_in_1_bits_last;
input io_in_1_bits_user;
input io_in_0_valid;
input io_in_0_bits_last;
input io_in_0_bits_user;
input io_out_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_last;
output io_out_bits_user;
wire [1:0] io_out_bits_resp,T3,choice,T34,T4,T13,T5,T10,T6,T8,T9,T11,T16,T14,T15,T17,T23,
T25,T30,T37,T35,T36,T44,T75;
wire [63:0] io_out_bits_data,T71;
wire [5:0] io_out_bits_id,T63;
wire io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_last,
io_out_bits_user,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,
N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,
N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,
N60,N61,N62,N63,N64,N65,N66,T1,N67,T40,N68,T19,N69,T12,N70,N71,N72,T18,N73,N74,
N75,T33,N76,T27,T20,N77,T21,N78,N79,T28,N80,T39,N81,N82,N83,T53,N84,T47,T41,N85,
T42,N86,N87,T48,N88,T55,T57,T56,T60,T67,T79,N89,N90,N91,N92,N93,N94,N95,N96,N97,
N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113;
reg [1:0] lockIdx;
reg locked;
assign T39 = T9 < { 1'b1, 1'b1 };
assign T53 = T25 < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N91) begin
lockIdx[1] <= N93;
end
end
always @(posedge clk) begin
if(N91) begin
lockIdx[0] <= N92;
end
end
always @(posedge clk) begin
if(N97) begin
locked <= N98;
end
end
assign N105 = ~T3[1];
assign N106 = T3[0] | N105;
assign N107 = ~N106;
assign N108 = ~T3[0];
assign N109 = N108 | T3[1];
assign N110 = ~N109;
assign N111 = T3[0] | T3[1];
assign N112 = ~N111;
assign T9 = lockIdx + 1'b1;
assign T25 = lockIdx + 1'b1;
assign T8 = T9 - 1'b1;
assign T11 = { 1'b1, 1'b0 } + T9;
assign T15 = T9 - { 1'b1, 1'b0 };
assign T17 = 1'b1 + T9;
assign T36 = T9 - { 1'b1, 1'b1 };
assign T23 = T25 - { 1'b1, 1'b0 };
assign T30 = 1'b1 + T25;
assign T44 = T25 - { 1'b1, 1'b1 };
assign N71 = N0 & N1;
assign N0 = ~T8[1];
assign N1 = ~T8[0];
assign N72 = N2 & N3;
assign N2 = ~T11[1];
assign N3 = ~T11[0];
assign N74 = N4 & N5;
assign N4 = ~T15[1];
assign N5 = ~T15[0];
assign N75 = N6 & N7;
assign N6 = ~T17[1];
assign N7 = ~T17[0];
assign N82 = N8 & N9;
assign N8 = ~T36[1];
assign N9 = ~T36[0];
assign N83 = N10 & N11;
assign N10 = ~T9[1];
assign N11 = ~T9[0];
assign io_out_bits_user = (N12)? io_in_2_bits_user :
(N13)? T1 : 1'b0;
assign N12 = T3[1];
assign N13 = N105;
assign T1 = (N14)? io_in_1_bits_user :
(N15)? io_in_0_bits_user : 1'b0;
assign N14 = T3[0];
assign N15 = N108;
assign T3 = (N16)? lockIdx :
(N17)? choice : 1'b0;
assign N16 = locked;
assign N17 = N67;
assign choice = (N18)? T34 :
(N19)? T4 : 1'b0;
assign N18 = T40;
assign N19 = N68;
assign T4 = (N20)? T13 :
(N21)? T5 : 1'b0;
assign N20 = T19;
assign N21 = N69;
assign T5 = (N22)? T10 :
(N23)? T6 : 1'b0;
assign N22 = T12;
assign N23 = N70;
assign T6 = (N24)? { 1'b0, 1'b0 } :
(N25)? { 1'b0, 1'b1 } :
(N26)? { 1'b1, 1'b0 } : 1'b0;
assign N24 = N71;
assign N25 = T8[0];
assign N26 = T8[1];
assign T10 = (N27)? { 1'b0, 1'b0 } :
(N28)? { 1'b0, 1'b1 } :
(N29)? { 1'b1, 1'b0 } : 1'b0;
assign N27 = N72;
assign N28 = T11[0];
assign N29 = T11[1];
assign T13 = (N30)? T16 :
(N31)? T14 : 1'b0;
assign N30 = T18;
assign N31 = N73;
assign T14 = (N32)? { 1'b0, 1'b0 } :
(N33)? { 1'b0, 1'b1 } :
(N34)? { 1'b1, 1'b0 } : 1'b0;
assign N32 = N74;
assign N33 = T15[0];
assign N34 = T15[1];
assign T16 = (N35)? { 1'b0, 1'b0 } :
(N36)? { 1'b0, 1'b1 } :
(N37)? { 1'b1, 1'b0 } : 1'b0;
assign N35 = N75;
assign N36 = T17[0];
assign N37 = T17[1];
assign T19 = (N38)? T27 :
(N39)? T20 : 1'b0;
assign N38 = T33;
assign N39 = N76;
assign T20 = (N40)? io_in_2_valid :
(N41)? T21 : 1'b0;
assign N40 = T23[1];
assign N41 = N77;
assign T21 = (N42)? io_in_1_valid :
(N43)? io_in_0_valid : 1'b0;
assign N42 = T23[0];
assign N43 = N78;
assign T27 = (N44)? io_in_2_valid :
(N45)? T28 : 1'b0;
assign N44 = T30[1];
assign N45 = N79;
assign T28 = (N46)? io_in_1_valid :
(N47)? io_in_0_valid : 1'b0;
assign N46 = T30[0];
assign N47 = N80;
assign T34 = (N48)? T37 :
(N49)? T35 : 1'b0;
assign N48 = T39;
assign N49 = N81;
assign T35 = (N50)? { 1'b0, 1'b0 } :
(N51)? { 1'b0, 1'b1 } :
(N52)? { 1'b1, 1'b0 } : 1'b0;
assign N50 = N82;
assign N51 = T36[0];
assign N52 = T36[1];
assign T37 = (N53)? { 1'b0, 1'b0 } :
(N54)? { 1'b0, 1'b1 } :
(N55)? { 1'b1, 1'b0 } : 1'b0;
assign N53 = N83;
assign N54 = T9[0];
assign N55 = T9[1];
assign T40 = (N56)? T47 :
(N57)? T41 : 1'b0;
assign N56 = T53;
assign N57 = N84;
assign T41 = (N58)? io_in_2_valid :
(N59)? T42 : 1'b0;
assign N58 = T44[1];
assign N59 = N85;
assign T42 = (N60)? io_in_1_valid :
(N61)? io_in_0_valid : 1'b0;
assign N60 = T44[0];
assign N61 = N86;
assign T47 = (N62)? io_in_2_valid :
(N63)? T48 : 1'b0;
assign N62 = T25[1];
assign N63 = N87;
assign T48 = (N64)? io_in_1_valid :
(N65)? io_in_0_valid : 1'b0;
assign N64 = T25[0];
assign N65 = N88;
assign io_out_bits_id = (N12)? io_in_2_bits_id :
(N13)? T63 : 1'b0;
assign T63 = (N14)? io_in_1_bits_id :
(N15)? io_in_0_bits_id : 1'b0;
assign io_out_bits_last = (N12)? io_in_2_bits_last :
(N13)? T67 : 1'b0;
assign T67 = (N14)? io_in_1_bits_last :
(N15)? io_in_0_bits_last : 1'b0;
assign io_out_bits_data = (N12)? io_in_2_bits_data :
(N13)? T71 : 1'b0;
assign T71 = (N14)? io_in_1_bits_data :
(N15)? io_in_0_bits_data : 1'b0;
assign io_out_bits_resp = (N12)? io_in_2_bits_resp :
(N13)? T75 : 1'b0;
assign T75 = (N14)? io_in_1_bits_resp :
(N15)? io_in_0_bits_resp : 1'b0;
assign io_out_valid = (N12)? io_in_2_valid :
(N13)? T79 : 1'b0;
assign T79 = (N14)? io_in_1_valid :
(N15)? io_in_0_valid : 1'b0;
assign N91 = (N66)? 1'b1 :
(N100)? 1'b1 :
(N90)? 1'b0 : 1'b0;
assign N66 = reset;
assign { N93, N92 } = (N66)? { 1'b0, 1'b0 } :
(N100)? choice : 1'b0;
assign N97 = (N66)? 1'b1 :
(N101)? 1'b1 :
(N104)? 1'b1 :
(N96)? 1'b0 : 1'b0;
assign N98 = (N66)? 1'b0 :
(N101)? 1'b0 :
(N104)? 1'b1 : 1'b0;
assign N67 = ~locked;
assign N68 = ~T40;
assign N69 = ~T19;
assign N70 = ~T12;
assign T12 = ~N113;
assign N113 = T9[1] | T9[0];
assign N73 = ~T18;
assign T18 = ~T9[1];
assign N76 = ~T33;
assign N77 = ~T23[1];
assign N78 = ~T23[0];
assign N79 = ~T30[1];
assign N80 = ~T30[0];
assign T33 = ~T25[1];
assign N81 = ~T39;
assign N84 = ~T53;
assign N85 = ~T44[1];
assign N86 = ~T44[0];
assign N87 = ~T25[1];
assign N88 = ~T25[0];
assign T55 = T57 & T56;
assign T56 = ~locked;
assign T57 = io_out_ready & io_out_valid;
assign T60 = T57 & io_out_bits_last;
assign io_in_0_ready = io_out_ready & N112;
assign io_in_1_ready = io_out_ready & N110;
assign io_in_2_ready = io_out_ready & N107;
assign N89 = T55 | reset;
assign N90 = ~N89;
assign N94 = T60 | reset;
assign N95 = T55 | N94;
assign N96 = ~N95;
assign N99 = ~reset;
assign N100 = T55 & N99;
assign N101 = T60 & N99;
assign N102 = ~T60;
assign N103 = N99 & N102;
assign N104 = T55 & N103;
endmodule |
module bsg_counter_up_down_variable_max_val_p128_init_val_p128_max_step_p128
(
clk_i,
reset_i,
up_i,
down_i,
count_o
);
input [7:0] up_i;
input [7:0] down_i;
output [7:0] count_o;
input clk_i;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26;
reg [7:0] count_o;
always @(posedge clk_i) begin
if(1'b1) begin
count_o[7] <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[6] <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[5] <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[4] <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[3] <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[2] <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[1] <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[0] <= N19;
end
end
assign { N10, N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i;
assign { N18, N17, N16, N15, N14, N13, N12, N11 } = { N10, N9, N8, N7, N6, N5, N4, N3 } + up_i;
assign { N26, N25, N24, N23, N22, N21, N20, N19 } = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? { N18, N17, N16, N15, N14, N13, N12, N11 } : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module LockingRRArbiter_1
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_beat,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_voluntary,
io_in_1_bits_r_type,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_beat,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_voluntary,
io_in_0_bits_r_type,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_beat,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_voluntary,
io_out_bits_r_type,
io_out_bits_data,
io_chosen
);
input [1:0] io_in_1_bits_addr_beat;
input [25:0] io_in_1_bits_addr_block;
input [5:0] io_in_1_bits_client_xact_id;
input [2:0] io_in_1_bits_r_type;
input [127:0] io_in_1_bits_data;
input [1:0] io_in_0_bits_addr_beat;
input [25:0] io_in_0_bits_addr_block;
input [5:0] io_in_0_bits_client_xact_id;
input [2:0] io_in_0_bits_r_type;
input [127:0] io_in_0_bits_data;
output [1:0] io_out_bits_addr_beat;
output [25:0] io_out_bits_addr_block;
output [5:0] io_out_bits_client_xact_id;
output [2:0] io_out_bits_r_type;
output [127:0] io_out_bits_data;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_voluntary;
input io_in_0_valid;
input io_in_0_bits_voluntary;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_voluntary;
output io_chosen;
wire [1:0] io_out_bits_addr_beat,T22;
wire [25:0] io_out_bits_addr_block;
wire [5:0] io_out_bits_client_xact_id;
wire [2:0] io_out_bits_r_type;
wire [127:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_voluntary,io_chosen,N0,N1,
N2,N3,N4,N5,N6,N7,N8,N9,choose,T2,N10,T3,T5,T9,T8,T11,T10,T17,T12,T14,T25,T20,
T21,T26,N11,T36,T37,T44,T38,T39,T42,T40,T41,T43,T47,T48,T52,T49,T50,T51,T54,T53,
N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,
N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51;
reg last_grant,lockIdx,locked;
reg [1:0] R23;
assign T21 = T22 == 1'b0;
assign T43 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T44 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N14) begin
last_grant <= N15;
end
end
always @(posedge clk) begin
if(N18) begin
lockIdx <= N19;
end
end
always @(posedge clk) begin
if(N23) begin
locked <= N24;
end
end
always @(posedge clk) begin
if(N27) begin
R23[1] <= N29;
end
end
always @(posedge clk) begin
if(N27) begin
R23[0] <= N28;
end
end
assign N38 = ~T8;
assign N39 = ~lockIdx;
assign N40 = ~io_out_bits_r_type[1];
assign N41 = N40 | io_out_bits_r_type[2];
assign N42 = io_out_bits_r_type[0] | N41;
assign N43 = ~N42;
assign N44 = io_out_bits_r_type[1] | io_out_bits_r_type[2];
assign N45 = io_out_bits_r_type[0] | N44;
assign N46 = ~N45;
assign N47 = ~io_out_bits_r_type[0];
assign N48 = io_out_bits_r_type[1] | io_out_bits_r_type[2];
assign N49 = N47 | N48;
assign N50 = ~N49;
assign N51 = ~io_in_0_valid;
assign T22 = R23 + 1'b1;
assign io_chosen = (N2)? lockIdx :
(N3)? choose : 1'b0;
assign N2 = locked;
assign N3 = N9;
assign choose = (N4)? 1'b1 :
(N5)? N51 : 1'b0;
assign N4 = T2;
assign N5 = N10;
assign io_out_bits_data = (N6)? io_in_1_bits_data :
(N7)? io_in_0_bits_data : 1'b0;
assign N6 = io_chosen;
assign N7 = N11;
assign io_out_bits_r_type = (N6)? io_in_1_bits_r_type :
(N7)? io_in_0_bits_r_type : 1'b0;
assign io_out_bits_voluntary = (N6)? io_in_1_bits_voluntary :
(N7)? io_in_0_bits_voluntary : 1'b0;
assign io_out_bits_client_xact_id = (N6)? io_in_1_bits_client_xact_id :
(N7)? io_in_0_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N6)? io_in_1_bits_addr_block :
(N7)? io_in_0_bits_addr_block : 1'b0;
assign io_out_bits_addr_beat = (N6)? io_in_1_bits_addr_beat :
(N7)? io_in_0_bits_addr_beat : 1'b0;
assign io_out_valid = (N6)? io_in_1_valid :
(N7)? io_in_0_valid : 1'b0;
assign T36 = (N2)? N39 :
(N3)? T37 : 1'b0;
assign T47 = (N2)? lockIdx :
(N3)? T48 : 1'b0;
assign N14 = (N8)? 1'b1 :
(N31)? 1'b1 :
(N13)? 1'b0 : 1'b0;
assign N8 = reset;
assign N15 = (N8)? 1'b0 :
(N31)? io_chosen : 1'b0;
assign N18 = (N8)? 1'b1 :
(N32)? 1'b1 :
(N17)? 1'b0 : 1'b0;
assign N19 = (N8)? 1'b1 :
(N32)? N38 : 1'b0;
assign N23 = (N8)? 1'b1 :
(N33)? 1'b1 :
(N36)? 1'b1 :
(N22)? 1'b0 : 1'b0;
assign N24 = (N8)? 1'b0 :
(N33)? 1'b0 :
(N36)? T20 : 1'b0;
assign N27 = (N8)? 1'b1 :
(N37)? 1'b1 :
(N26)? 1'b0 : 1'b0;
assign { N29, N28 } = (N8)? { 1'b0, 1'b0 } :
(N37)? T22 : 1'b0;
assign N9 = ~locked;
assign N10 = ~T2;
assign T2 = io_in_1_valid & T3;
assign T3 = ~last_grant;
assign T5 = io_out_ready & io_out_valid;
assign T8 = io_in_0_ready & io_in_0_valid;
assign T9 = T11 & T10;
assign T10 = ~locked;
assign T11 = T17 & T12;
assign T12 = T14 | N43;
assign T14 = N46 | N50;
assign T17 = io_out_valid & io_out_ready;
assign T20 = ~T21;
assign T25 = T17 & T26;
assign T26 = ~T12;
assign N11 = ~io_chosen;
assign io_in_0_ready = T36 & io_out_ready;
assign T37 = T44 | T38;
assign T38 = ~T39;
assign T39 = T42 | T40;
assign T40 = io_in_1_valid & T41;
assign T41 = ~last_grant;
assign T42 = io_in_0_valid & T43;
assign io_in_1_ready = T47 & io_out_ready;
assign T48 = T52 | T49;
assign T49 = ~T50;
assign T50 = T51 | io_in_0_valid;
assign T51 = T42 | T40;
assign T52 = T54 & T53;
assign T53 = ~last_grant;
assign T54 = ~T42;
assign N12 = T5 | reset;
assign N13 = ~N12;
assign N16 = T9 | reset;
assign N17 = ~N16;
assign N20 = T25 | reset;
assign N21 = T11 | N20;
assign N22 = ~N21;
assign N25 = T11 | reset;
assign N26 = ~N25;
assign N30 = ~reset;
assign N31 = T5 & N30;
assign N32 = T9 & N30;
assign N33 = T25 & N30;
assign N34 = ~T25;
assign N35 = N30 & N34;
assign N36 = T11 & N35;
assign N37 = T11 & N30;
endmodule |
module Arbiter_3
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_way_en,
io_in_1_bits_addr,
io_in_1_bits_wmask,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_way_en,
io_in_0_bits_addr,
io_in_0_bits_wmask,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_way_en,
io_out_bits_addr,
io_out_bits_wmask,
io_out_bits_data,
io_chosen
);
input [3:0] io_in_1_bits_way_en;
input [11:0] io_in_1_bits_addr;
input [1:0] io_in_1_bits_wmask;
input [127:0] io_in_1_bits_data;
input [3:0] io_in_0_bits_way_en;
input [11:0] io_in_0_bits_addr;
input [1:0] io_in_0_bits_wmask;
input [127:0] io_in_0_bits_data;
output [3:0] io_out_bits_way_en;
output [11:0] io_out_bits_addr;
output [1:0] io_out_bits_wmask;
output [127:0] io_out_bits_data;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_chosen;
wire [3:0] io_out_bits_way_en;
wire [11:0] io_out_bits_addr;
wire [1:0] io_out_bits_wmask;
wire [127:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_chosen,N0,N1,io_out_ready,T7;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_data = (N0)? io_in_1_bits_data :
(N1)? io_in_0_bits_data : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_wmask = (N0)? io_in_1_bits_wmask :
(N1)? io_in_0_bits_wmask : 1'b0;
assign io_out_bits_addr = (N0)? io_in_1_bits_addr :
(N1)? io_in_0_bits_addr : 1'b0;
assign io_out_bits_way_en = (N0)? io_in_1_bits_way_en :
(N1)? io_in_0_bits_way_en : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T7 & io_out_ready;
assign T7 = ~io_in_0_valid;
endmodule |
module Arbiter_5
(
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr,
io_in_1_bits_tag,
io_in_1_bits_cmd,
io_in_1_bits_typ,
io_in_1_bits_kill,
io_in_1_bits_phys,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_tag,
io_in_0_bits_cmd,
io_in_0_bits_typ,
io_in_0_bits_kill,
io_in_0_bits_phys,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr,
io_out_bits_tag,
io_out_bits_cmd,
io_out_bits_typ,
io_out_bits_kill,
io_out_bits_phys,
io_out_bits_data,
io_chosen
);
input [39:0] io_in_1_bits_addr;
input [9:0] io_in_1_bits_tag;
input [4:0] io_in_1_bits_cmd;
input [2:0] io_in_1_bits_typ;
input [63:0] io_in_1_bits_data;
input [39:0] io_in_0_bits_addr;
input [9:0] io_in_0_bits_tag;
input [4:0] io_in_0_bits_cmd;
input [2:0] io_in_0_bits_typ;
input [63:0] io_in_0_bits_data;
output [39:0] io_out_bits_addr;
output [9:0] io_out_bits_tag;
output [4:0] io_out_bits_cmd;
output [2:0] io_out_bits_typ;
output [63:0] io_out_bits_data;
input io_in_1_valid;
input io_in_1_bits_kill;
input io_in_1_bits_phys;
input io_in_0_valid;
input io_in_0_bits_kill;
input io_in_0_bits_phys;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_kill;
output io_out_bits_phys;
output io_chosen;
wire [39:0] io_out_bits_addr;
wire [9:0] io_out_bits_tag;
wire [4:0] io_out_bits_cmd;
wire [2:0] io_out_bits_typ;
wire [63:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_kill,io_out_bits_phys,
io_chosen,N0,N1,io_out_ready,T10;
assign io_in_0_ready = io_out_ready;
assign io_chosen = ~io_in_0_valid;
assign io_out_bits_data = (N0)? io_in_1_bits_data :
(N1)? io_in_0_bits_data : 1'b0;
assign N0 = io_chosen;
assign N1 = io_in_0_valid;
assign io_out_bits_phys = (N0)? io_in_1_bits_phys :
(N1)? io_in_0_bits_phys : 1'b0;
assign io_out_bits_kill = (N0)? io_in_1_bits_kill :
(N1)? io_in_0_bits_kill : 1'b0;
assign io_out_bits_typ = (N0)? io_in_1_bits_typ :
(N1)? io_in_0_bits_typ : 1'b0;
assign io_out_bits_cmd = (N0)? io_in_1_bits_cmd :
(N1)? io_in_0_bits_cmd : 1'b0;
assign io_out_bits_tag = (N0)? io_in_1_bits_tag :
(N1)? io_in_0_bits_tag : 1'b0;
assign io_out_bits_addr = (N0)? io_in_1_bits_addr :
(N1)? io_in_0_bits_addr : 1'b0;
assign io_out_valid = (N0)? io_in_1_valid :
(N1)? io_in_0_valid : 1'b0;
assign io_in_1_ready = T10 & io_out_ready;
assign T10 = ~io_in_0_valid;
endmodule |
module LockingRRArbiter_10
(
clk,
reset,
io_in_7_ready,
io_in_7_valid,
io_in_7_bits_addr_block,
io_in_7_bits_client_xact_id,
io_in_7_bits_addr_beat,
io_in_7_bits_is_builtin_type,
io_in_7_bits_a_type,
io_in_7_bits_union,
io_in_7_bits_data,
io_in_6_ready,
io_in_6_valid,
io_in_6_bits_addr_block,
io_in_6_bits_client_xact_id,
io_in_6_bits_addr_beat,
io_in_6_bits_is_builtin_type,
io_in_6_bits_a_type,
io_in_6_bits_union,
io_in_6_bits_data,
io_in_5_ready,
io_in_5_valid,
io_in_5_bits_addr_block,
io_in_5_bits_client_xact_id,
io_in_5_bits_addr_beat,
io_in_5_bits_is_builtin_type,
io_in_5_bits_a_type,
io_in_5_bits_union,
io_in_5_bits_data,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_addr_block,
io_in_4_bits_client_xact_id,
io_in_4_bits_addr_beat,
io_in_4_bits_is_builtin_type,
io_in_4_bits_a_type,
io_in_4_bits_union,
io_in_4_bits_data,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_addr_block,
io_in_3_bits_client_xact_id,
io_in_3_bits_addr_beat,
io_in_3_bits_is_builtin_type,
io_in_3_bits_a_type,
io_in_3_bits_union,
io_in_3_bits_data,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_addr_block,
io_in_2_bits_client_xact_id,
io_in_2_bits_addr_beat,
io_in_2_bits_is_builtin_type,
io_in_2_bits_a_type,
io_in_2_bits_union,
io_in_2_bits_data,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr_block,
io_in_1_bits_client_xact_id,
io_in_1_bits_addr_beat,
io_in_1_bits_is_builtin_type,
io_in_1_bits_a_type,
io_in_1_bits_union,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr_block,
io_in_0_bits_client_xact_id,
io_in_0_bits_addr_beat,
io_in_0_bits_is_builtin_type,
io_in_0_bits_a_type,
io_in_0_bits_union,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_addr_block,
io_out_bits_client_xact_id,
io_out_bits_addr_beat,
io_out_bits_is_builtin_type,
io_out_bits_a_type,
io_out_bits_union,
io_out_bits_data,
io_chosen
);
input [25:0] io_in_7_bits_addr_block;
input [3:0] io_in_7_bits_client_xact_id;
input [1:0] io_in_7_bits_addr_beat;
input [2:0] io_in_7_bits_a_type;
input [16:0] io_in_7_bits_union;
input [3:0] io_in_7_bits_data;
input [25:0] io_in_6_bits_addr_block;
input [3:0] io_in_6_bits_client_xact_id;
input [1:0] io_in_6_bits_addr_beat;
input [2:0] io_in_6_bits_a_type;
input [16:0] io_in_6_bits_union;
input [3:0] io_in_6_bits_data;
input [25:0] io_in_5_bits_addr_block;
input [3:0] io_in_5_bits_client_xact_id;
input [1:0] io_in_5_bits_addr_beat;
input [2:0] io_in_5_bits_a_type;
input [16:0] io_in_5_bits_union;
input [3:0] io_in_5_bits_data;
input [25:0] io_in_4_bits_addr_block;
input [3:0] io_in_4_bits_client_xact_id;
input [1:0] io_in_4_bits_addr_beat;
input [2:0] io_in_4_bits_a_type;
input [16:0] io_in_4_bits_union;
input [3:0] io_in_4_bits_data;
input [25:0] io_in_3_bits_addr_block;
input [3:0] io_in_3_bits_client_xact_id;
input [1:0] io_in_3_bits_addr_beat;
input [2:0] io_in_3_bits_a_type;
input [16:0] io_in_3_bits_union;
input [3:0] io_in_3_bits_data;
input [25:0] io_in_2_bits_addr_block;
input [3:0] io_in_2_bits_client_xact_id;
input [1:0] io_in_2_bits_addr_beat;
input [2:0] io_in_2_bits_a_type;
input [16:0] io_in_2_bits_union;
input [3:0] io_in_2_bits_data;
input [25:0] io_in_1_bits_addr_block;
input [3:0] io_in_1_bits_client_xact_id;
input [1:0] io_in_1_bits_addr_beat;
input [2:0] io_in_1_bits_a_type;
input [16:0] io_in_1_bits_union;
input [3:0] io_in_1_bits_data;
input [25:0] io_in_0_bits_addr_block;
input [3:0] io_in_0_bits_client_xact_id;
input [1:0] io_in_0_bits_addr_beat;
input [2:0] io_in_0_bits_a_type;
input [16:0] io_in_0_bits_union;
input [3:0] io_in_0_bits_data;
output [25:0] io_out_bits_addr_block;
output [3:0] io_out_bits_client_xact_id;
output [1:0] io_out_bits_addr_beat;
output [2:0] io_out_bits_a_type;
output [16:0] io_out_bits_union;
output [3:0] io_out_bits_data;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_7_valid;
input io_in_7_bits_is_builtin_type;
input io_in_6_valid;
input io_in_6_bits_is_builtin_type;
input io_in_5_valid;
input io_in_5_bits_is_builtin_type;
input io_in_4_valid;
input io_in_4_bits_is_builtin_type;
input io_in_3_valid;
input io_in_3_bits_is_builtin_type;
input io_in_2_valid;
input io_in_2_bits_is_builtin_type;
input io_in_1_valid;
input io_in_1_bits_is_builtin_type;
input io_in_0_valid;
input io_in_0_bits_is_builtin_type;
input io_out_ready;
output io_in_7_ready;
output io_in_6_ready;
output io_in_5_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_is_builtin_type;
wire [25:0] io_out_bits_addr_block,T152,T146,T149,T147,T155,T153;
wire [3:0] io_out_bits_client_xact_id,io_out_bits_data,T68,T61,T65,T62,T71,T69,T138,T132,
T135,T133,T141,T139;
wire [1:0] io_out_bits_addr_beat,T11,T12,T35,T36,T55,T124,T118,T121,T119,T127,T125;
wire [2:0] io_out_bits_a_type,io_chosen,choose,T1,T2,T3,T4,T5,T6,T7,T8,T9,T10,T31,T32,T33,
T34,T96,T90,T93,T91,T99,T97;
wire [16:0] io_out_bits_union,T82,T76,T79,T77,T85,T83;
wire io_in_7_ready,io_in_6_ready,io_in_5_ready,io_in_4_ready,io_in_3_ready,
io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_is_builtin_type,N0,N1,
N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,
N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,
N44,N45,N46,N47,T28,N48,T26,N49,T24,N50,T22,N51,T20,N52,T18,N53,T14,N54,N55,N56,
N57,N58,N59,N60,N61,T15,T17,T19,T21,T23,T25,T27,T29,T45,T44,N62,T43,N63,T42,N64,
T41,N65,T40,N66,T39,N67,T38,N68,T47,T46,T50,T48,T58,T53,T54,T59,N69,N70,N71,T110,
T104,T107,T105,T113,T111,T166,T160,T163,T161,T169,T167,T174,T175,T200,T176,T177,
T180,T178,T179,T183,T181,T182,T186,T184,T185,T189,T187,T188,T192,T190,T191,T195,
T193,T194,T198,T196,T197,T199,T203,T204,T214,T205,T206,T207,T208,T209,T210,T211,
T212,T213,T216,T215,T219,T220,T231,T221,T222,T223,T224,T225,T226,T227,T228,T229,
T230,T233,T232,T234,T237,T238,T250,T239,T240,T241,T242,T243,T244,T245,T246,T247,
T248,T249,T252,T251,T253,T254,T257,T258,T271,T259,T260,T261,T262,T263,T264,T265,
T266,T267,T268,T269,T270,T273,T272,T274,T275,T276,T279,T280,T294,T281,T282,T283,
T284,T285,T286,T287,T288,T289,T290,T291,T292,T293,T296,T295,T297,T298,T299,T300,
T303,T304,T319,T305,T306,T307,T308,T309,T310,T311,T312,T313,T314,T315,T316,T317,
T318,T321,T320,T322,T323,T324,T325,T326,T329,T330,T346,T331,T332,T333,T334,T335,
T336,T337,T338,T339,T340,T341,T342,T343,T344,T345,T348,T347,T349,T350,T351,T352,
T353,T354,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,
N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,
N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,
N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,
N139,N140,N141;
wire [0:0] T13,T37;
reg [2:0] last_grant,lockIdx;
reg locked;
reg [1:0] R56;
assign T15 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T19 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T21 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T25 = last_grant < { 1'b1, 1'b1 };
assign T54 = T55 == 1'b0;
assign T179 = last_grant < { 1'b1, 1'b1, 1'b1 };
assign T182 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T185 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T191 = last_grant < { 1'b1, 1'b1 };
assign T199 = last_grant < 1'b0;
assign T200 = last_grant < 1'b0;
assign T251 = last_grant < { 1'b1, 1'b1 };
assign T295 = last_grant < { 1'b1, 1'b0, 1'b1 };
assign T320 = last_grant < { 1'b1, 1'b1, 1'b0 };
assign T347 = last_grant < { 1'b1, 1'b1, 1'b1 };
always @(posedge clk) begin
if(N74) begin
last_grant[2] <= N77;
end
end
always @(posedge clk) begin
if(N74) begin
last_grant[1] <= N76;
end
end
always @(posedge clk) begin
if(N74) begin
last_grant[0] <= N75;
end
end
always @(posedge clk) begin
if(N80) begin
lockIdx[2] <= N83;
end
end
always @(posedge clk) begin
if(N80) begin
lockIdx[1] <= N82;
end
end
always @(posedge clk) begin
if(N80) begin
lockIdx[0] <= N81;
end
end
always @(posedge clk) begin
if(N87) begin
locked <= N88;
end
end
always @(posedge clk) begin
if(N91) begin
R56[1] <= N93;
end
end
always @(posedge clk) begin
if(N91) begin
R56[0] <= N92;
end
end
assign N102 = lockIdx[1] & lockIdx[2];
assign N103 = lockIdx[0] & N102;
assign N104 = lockIdx[1] | lockIdx[2];
assign N105 = lockIdx[0] | N104;
assign N106 = ~N105;
assign N107 = ~lockIdx[0];
assign N108 = lockIdx[1] | lockIdx[2];
assign N109 = N107 | N108;
assign N110 = ~N109;
assign N111 = ~io_out_bits_a_type[1];
assign N112 = ~io_out_bits_a_type[0];
assign N113 = N111 | io_out_bits_a_type[2];
assign N114 = N112 | N113;
assign N115 = ~N114;
assign N116 = ~lockIdx[1];
assign N117 = N116 | lockIdx[2];
assign N118 = lockIdx[0] | N117;
assign N119 = ~N118;
assign N120 = N116 | lockIdx[2];
assign N121 = N107 | N120;
assign N122 = ~N121;
assign N123 = ~lockIdx[2];
assign N124 = lockIdx[1] | N123;
assign N125 = lockIdx[0] | N124;
assign N126 = ~N125;
assign N127 = lockIdx[1] | N123;
assign N128 = N107 | N127;
assign N129 = ~N128;
assign N130 = N116 | N123;
assign N131 = lockIdx[0] | N130;
assign N132 = ~N131;
assign T55 = R56 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N47;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T28;
assign N3 = N48;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T26;
assign N5 = N49;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T24;
assign N7 = N50;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T22;
assign N9 = N51;
assign T4 = (N10)? { 1'b1, 1'b0, 1'b1 } :
(N11)? T5 : 1'b0;
assign N10 = T20;
assign N11 = N52;
assign T5 = (N12)? { 1'b1, 1'b1, 1'b0 } :
(N13)? T6 : 1'b0;
assign N12 = T18;
assign N13 = N53;
assign T6 = (N14)? { 1'b1, 1'b1, 1'b1 } :
(N15)? T7 : 1'b0;
assign N14 = T14;
assign N15 = N54;
assign T7 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T8 : 1'b0;
assign N16 = io_in_0_valid;
assign N17 = N55;
assign T8 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T9 : 1'b0;
assign N18 = io_in_1_valid;
assign N19 = N56;
assign T9 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? T10 : 1'b0;
assign N20 = io_in_2_valid;
assign N21 = N57;
assign T10[1:0] = (N22)? { 1'b1, 1'b1 } :
(N23)? T11 : 1'b0;
assign N22 = io_in_3_valid;
assign N23 = T10[2];
assign T11 = (N24)? { 1'b0, 1'b0 } :
(N25)? T12 : 1'b0;
assign N24 = io_in_4_valid;
assign N25 = N59;
assign T12[0] = (N26)? 1'b1 :
(N27)? T13[0] : 1'b0;
assign N26 = io_in_5_valid;
assign N27 = T12[1];
assign T31 = (N28)? { 1'b0, 1'b0, 1'b0 } :
(N29)? T32 : 1'b0;
assign N28 = T44;
assign N29 = N62;
assign T32 = (N30)? { 1'b0, 1'b0, 1'b1 } :
(N31)? T33 : 1'b0;
assign N30 = T43;
assign N31 = N63;
assign T33 = (N32)? { 1'b0, 1'b1, 1'b0 } :
(N33)? T34 : 1'b0;
assign N32 = T42;
assign N33 = N64;
assign T34[1:0] = (N34)? { 1'b1, 1'b1 } :
(N35)? T35 : 1'b0;
assign N34 = T41;
assign N35 = T34[2];
assign T35 = (N36)? { 1'b0, 1'b0 } :
(N37)? T36 : 1'b0;
assign N36 = T40;
assign N37 = N66;
assign T36[0] = (N38)? 1'b1 :
(N39)? T37[0] : 1'b0;
assign N38 = T39;
assign N39 = T36[1];
assign io_out_bits_data = (N40)? T68 :
(N41)? T61 : 1'b0;
assign N40 = io_chosen[2];
assign N41 = N69;
assign T61 = (N42)? T65 :
(N43)? T62 : 1'b0;
assign N42 = io_chosen[1];
assign N43 = N70;
assign T62 = (N44)? io_in_1_bits_data :
(N45)? io_in_0_bits_data : 1'b0;
assign N44 = io_chosen[0];
assign N45 = N71;
assign T65 = (N44)? io_in_3_bits_data :
(N45)? io_in_2_bits_data : 1'b0;
assign T68 = (N42)? T71 :
(N43)? T69 : 1'b0;
assign T69 = (N44)? io_in_5_bits_data :
(N45)? io_in_4_bits_data : 1'b0;
assign T71 = (N44)? io_in_7_bits_data :
(N45)? io_in_6_bits_data : 1'b0;
assign io_out_bits_union = (N40)? T82 :
(N41)? T76 : 1'b0;
assign T76 = (N42)? T79 :
(N43)? T77 : 1'b0;
assign T77 = (N44)? io_in_1_bits_union :
(N45)? io_in_0_bits_union : 1'b0;
assign T79 = (N44)? io_in_3_bits_union :
(N45)? io_in_2_bits_union : 1'b0;
assign T82 = (N42)? T85 :
(N43)? T83 : 1'b0;
assign T83 = (N44)? io_in_5_bits_union :
(N45)? io_in_4_bits_union : 1'b0;
assign T85 = (N44)? io_in_7_bits_union :
(N45)? io_in_6_bits_union : 1'b0;
assign io_out_bits_a_type = (N40)? T96 :
(N41)? T90 : 1'b0;
assign T90 = (N42)? T93 :
(N43)? T91 : 1'b0;
assign T91 = (N44)? io_in_1_bits_a_type :
(N45)? io_in_0_bits_a_type : 1'b0;
assign T93 = (N44)? io_in_3_bits_a_type :
(N45)? io_in_2_bits_a_type : 1'b0;
assign T96 = (N42)? T99 :
(N43)? T97 : 1'b0;
assign T97 = (N44)? io_in_5_bits_a_type :
(N45)? io_in_4_bits_a_type : 1'b0;
assign T99 = (N44)? io_in_7_bits_a_type :
(N45)? io_in_6_bits_a_type : 1'b0;
assign io_out_bits_is_builtin_type = (N40)? T110 :
(N41)? T104 : 1'b0;
assign T104 = (N42)? T107 :
(N43)? T105 : 1'b0;
assign T105 = (N44)? io_in_1_bits_is_builtin_type :
(N45)? io_in_0_bits_is_builtin_type : 1'b0;
assign T107 = (N44)? io_in_3_bits_is_builtin_type :
(N45)? io_in_2_bits_is_builtin_type : 1'b0;
assign T110 = (N42)? T113 :
(N43)? T111 : 1'b0;
assign T111 = (N44)? io_in_5_bits_is_builtin_type :
(N45)? io_in_4_bits_is_builtin_type : 1'b0;
assign T113 = (N44)? io_in_7_bits_is_builtin_type :
(N45)? io_in_6_bits_is_builtin_type : 1'b0;
assign io_out_bits_addr_beat = (N40)? T124 :
(N41)? T118 : 1'b0;
assign T118 = (N42)? T121 :
(N43)? T119 : 1'b0;
assign T119 = (N44)? io_in_1_bits_addr_beat :
(N45)? io_in_0_bits_addr_beat : 1'b0;
assign T121 = (N44)? io_in_3_bits_addr_beat :
(N45)? io_in_2_bits_addr_beat : 1'b0;
assign T124 = (N42)? T127 :
(N43)? T125 : 1'b0;
assign T125 = (N44)? io_in_5_bits_addr_beat :
(N45)? io_in_4_bits_addr_beat : 1'b0;
assign T127 = (N44)? io_in_7_bits_addr_beat :
(N45)? io_in_6_bits_addr_beat : 1'b0;
assign io_out_bits_client_xact_id = (N40)? T138 :
(N41)? T132 : 1'b0;
assign T132 = (N42)? T135 :
(N43)? T133 : 1'b0;
assign T133 = (N44)? io_in_1_bits_client_xact_id :
(N45)? io_in_0_bits_client_xact_id : 1'b0;
assign T135 = (N44)? io_in_3_bits_client_xact_id :
(N45)? io_in_2_bits_client_xact_id : 1'b0;
assign T138 = (N42)? T141 :
(N43)? T139 : 1'b0;
assign T139 = (N44)? io_in_5_bits_client_xact_id :
(N45)? io_in_4_bits_client_xact_id : 1'b0;
assign T141 = (N44)? io_in_7_bits_client_xact_id :
(N45)? io_in_6_bits_client_xact_id : 1'b0;
assign io_out_bits_addr_block = (N40)? T152 :
(N41)? T146 : 1'b0;
assign T146 = (N42)? T149 :
(N43)? T147 : 1'b0;
assign T147 = (N44)? io_in_1_bits_addr_block :
(N45)? io_in_0_bits_addr_block : 1'b0;
assign T149 = (N44)? io_in_3_bits_addr_block :
(N45)? io_in_2_bits_addr_block : 1'b0;
assign T152 = (N42)? T155 :
(N43)? T153 : 1'b0;
assign T153 = (N44)? io_in_5_bits_addr_block :
(N45)? io_in_4_bits_addr_block : 1'b0;
assign T155 = (N44)? io_in_7_bits_addr_block :
(N45)? io_in_6_bits_addr_block : 1'b0;
assign io_out_valid = (N40)? T166 :
(N41)? T160 : 1'b0;
assign T160 = (N42)? T163 :
(N43)? T161 : 1'b0;
assign T161 = (N44)? io_in_1_valid :
(N45)? io_in_0_valid : 1'b0;
assign T163 = (N44)? io_in_3_valid :
(N45)? io_in_2_valid : 1'b0;
assign T166 = (N42)? T169 :
(N43)? T167 : 1'b0;
assign T167 = (N44)? io_in_5_valid :
(N45)? io_in_4_valid : 1'b0;
assign T169 = (N44)? io_in_7_valid :
(N45)? io_in_6_valid : 1'b0;
assign T174 = (N0)? N106 :
(N1)? T175 : 1'b0;
assign T203 = (N0)? N110 :
(N1)? T204 : 1'b0;
assign T219 = (N0)? N119 :
(N1)? T220 : 1'b0;
assign T237 = (N0)? N122 :
(N1)? T238 : 1'b0;
assign T257 = (N0)? N126 :
(N1)? T258 : 1'b0;
assign T279 = (N0)? N129 :
(N1)? T280 : 1'b0;
assign T303 = (N0)? N132 :
(N1)? T304 : 1'b0;
assign T329 = (N0)? N103 :
(N1)? T330 : 1'b0;
assign N74 = (N46)? 1'b1 :
(N95)? 1'b1 :
(N73)? 1'b0 : 1'b0;
assign N46 = reset;
assign { N77, N76, N75 } = (N46)? { 1'b0, 1'b0, 1'b0 } :
(N95)? io_chosen : 1'b0;
assign N80 = (N46)? 1'b1 :
(N96)? 1'b1 :
(N79)? 1'b0 : 1'b0;
assign { N83, N82, N81 } = (N46)? { 1'b1, 1'b1, 1'b1 } :
(N96)? T31 : 1'b0;
assign N87 = (N46)? 1'b1 :
(N97)? 1'b1 :
(N100)? 1'b1 :
(N86)? 1'b0 : 1'b0;
assign N88 = (N46)? 1'b0 :
(N97)? 1'b0 :
(N100)? T53 : 1'b0;
assign N91 = (N46)? 1'b1 :
(N101)? 1'b1 :
(N90)? 1'b0 : 1'b0;
assign { N93, N92 } = (N46)? { 1'b0, 1'b0 } :
(N101)? T55 : 1'b0;
assign N47 = ~locked;
assign N48 = ~T28;
assign N49 = ~T26;
assign N50 = ~T24;
assign N51 = ~T22;
assign N52 = ~T20;
assign N53 = ~T18;
assign N54 = ~T14;
assign N55 = ~io_in_0_valid;
assign N56 = ~io_in_1_valid;
assign N57 = ~io_in_2_valid;
assign N58 = ~io_in_3_valid;
assign T10[2] = N58;
assign N59 = ~io_in_4_valid;
assign N60 = ~io_in_5_valid;
assign T12[1] = N60;
assign N61 = ~io_in_6_valid;
assign T13[0] = N61;
assign T14 = io_in_7_valid & T15;
assign T17 = io_out_ready & io_out_valid;
assign T18 = io_in_6_valid & T19;
assign T20 = io_in_5_valid & T21;
assign T22 = io_in_4_valid & T23;
assign T23 = ~last_grant[2];
assign T24 = io_in_3_valid & T25;
assign T26 = io_in_2_valid & T27;
assign T27 = ~N133;
assign N133 = last_grant[2] | last_grant[1];
assign T28 = io_in_1_valid & T29;
assign T29 = ~N135;
assign N135 = N134 | last_grant[0];
assign N134 = last_grant[2] | last_grant[1];
assign N62 = ~T44;
assign N63 = ~T43;
assign N64 = ~T42;
assign N65 = ~T41;
assign T34[2] = N65;
assign N66 = ~T40;
assign N67 = ~T39;
assign T36[1] = N67;
assign N68 = ~T38;
assign T37[0] = N68;
assign T38 = io_in_6_ready & io_in_6_valid;
assign T39 = io_in_5_ready & io_in_5_valid;
assign T40 = io_in_4_ready & io_in_4_valid;
assign T41 = io_in_3_ready & io_in_3_valid;
assign T42 = io_in_2_ready & io_in_2_valid;
assign T43 = io_in_1_ready & io_in_1_valid;
assign T44 = io_in_0_ready & io_in_0_valid;
assign T45 = T47 & T46;
assign T46 = ~locked;
assign T47 = T50 & T48;
assign T48 = io_out_bits_is_builtin_type & N115;
assign T50 = io_out_valid & io_out_ready;
assign T53 = ~T54;
assign T58 = T50 & T59;
assign T59 = ~T48;
assign N69 = ~io_chosen[2];
assign N70 = ~io_chosen[1];
assign N71 = ~io_chosen[0];
assign io_in_0_ready = T174 & io_out_ready;
assign T175 = T200 | T176;
assign T176 = ~T177;
assign T177 = T180 | T178;
assign T178 = io_in_7_valid & T179;
assign T180 = T183 | T181;
assign T181 = io_in_6_valid & T182;
assign T183 = T186 | T184;
assign T184 = io_in_5_valid & T185;
assign T186 = T189 | T187;
assign T187 = io_in_4_valid & T188;
assign T188 = ~last_grant[2];
assign T189 = T192 | T190;
assign T190 = io_in_3_valid & T191;
assign T192 = T195 | T193;
assign T193 = io_in_2_valid & T194;
assign T194 = ~N136;
assign N136 = last_grant[2] | last_grant[1];
assign T195 = T198 | T196;
assign T196 = io_in_1_valid & T197;
assign T197 = ~N138;
assign N138 = N137 | last_grant[0];
assign N137 = last_grant[2] | last_grant[1];
assign T198 = io_in_0_valid & T199;
assign io_in_1_ready = T203 & io_out_ready;
assign T204 = T214 | T205;
assign T205 = ~T206;
assign T206 = T207 | io_in_0_valid;
assign T207 = T208 | T178;
assign T208 = T209 | T181;
assign T209 = T210 | T184;
assign T210 = T211 | T187;
assign T211 = T212 | T190;
assign T212 = T213 | T193;
assign T213 = T198 | T196;
assign T214 = T216 & T215;
assign T215 = ~N140;
assign N140 = N139 | last_grant[0];
assign N139 = last_grant[2] | last_grant[1];
assign T216 = ~T198;
assign io_in_2_ready = T219 & io_out_ready;
assign T220 = T231 | T221;
assign T221 = ~T222;
assign T222 = T223 | io_in_1_valid;
assign T223 = T224 | io_in_0_valid;
assign T224 = T225 | T178;
assign T225 = T226 | T181;
assign T226 = T227 | T184;
assign T227 = T228 | T187;
assign T228 = T229 | T190;
assign T229 = T230 | T193;
assign T230 = T198 | T196;
assign T231 = T233 & T232;
assign T232 = ~N141;
assign N141 = last_grant[2] | last_grant[1];
assign T233 = ~T234;
assign T234 = T198 | T196;
assign io_in_3_ready = T237 & io_out_ready;
assign T238 = T250 | T239;
assign T239 = ~T240;
assign T240 = T241 | io_in_2_valid;
assign T241 = T242 | io_in_1_valid;
assign T242 = T243 | io_in_0_valid;
assign T243 = T244 | T178;
assign T244 = T245 | T181;
assign T245 = T246 | T184;
assign T246 = T247 | T187;
assign T247 = T248 | T190;
assign T248 = T249 | T193;
assign T249 = T198 | T196;
assign T250 = T252 & T251;
assign T252 = ~T253;
assign T253 = T254 | T193;
assign T254 = T198 | T196;
assign io_in_4_ready = T257 & io_out_ready;
assign T258 = T271 | T259;
assign T259 = ~T260;
assign T260 = T261 | io_in_3_valid;
assign T261 = T262 | io_in_2_valid;
assign T262 = T263 | io_in_1_valid;
assign T263 = T264 | io_in_0_valid;
assign T264 = T265 | T178;
assign T265 = T266 | T181;
assign T266 = T267 | T184;
assign T267 = T268 | T187;
assign T268 = T269 | T190;
assign T269 = T270 | T193;
assign T270 = T198 | T196;
assign T271 = T273 & T272;
assign T272 = ~last_grant[2];
assign T273 = ~T274;
assign T274 = T275 | T190;
assign T275 = T276 | T193;
assign T276 = T198 | T196;
assign io_in_5_ready = T279 & io_out_ready;
assign T280 = T294 | T281;
assign T281 = ~T282;
assign T282 = T283 | io_in_4_valid;
assign T283 = T284 | io_in_3_valid;
assign T284 = T285 | io_in_2_valid;
assign T285 = T286 | io_in_1_valid;
assign T286 = T287 | io_in_0_valid;
assign T287 = T288 | T178;
assign T288 = T289 | T181;
assign T289 = T290 | T184;
assign T290 = T291 | T187;
assign T291 = T292 | T190;
assign T292 = T293 | T193;
assign T293 = T198 | T196;
assign T294 = T296 & T295;
assign T296 = ~T297;
assign T297 = T298 | T187;
assign T298 = T299 | T190;
assign T299 = T300 | T193;
assign T300 = T198 | T196;
assign io_in_6_ready = T303 & io_out_ready;
assign T304 = T319 | T305;
assign T305 = ~T306;
assign T306 = T307 | io_in_5_valid;
assign T307 = T308 | io_in_4_valid;
assign T308 = T309 | io_in_3_valid;
assign T309 = T310 | io_in_2_valid;
assign T310 = T311 | io_in_1_valid;
assign T311 = T312 | io_in_0_valid;
assign T312 = T313 | T178;
assign T313 = T314 | T181;
assign T314 = T315 | T184;
assign T315 = T316 | T187;
assign T316 = T317 | T190;
assign T317 = T318 | T193;
assign T318 = T198 | T196;
assign T319 = T321 & T320;
assign T321 = ~T322;
assign T322 = T323 | T184;
assign T323 = T324 | T187;
assign T324 = T325 | T190;
assign T325 = T326 | T193;
assign T326 = T198 | T196;
assign io_in_7_ready = T329 & io_out_ready;
assign T330 = T346 | T331;
assign T331 = ~T332;
assign T332 = T333 | io_in_6_valid;
assign T333 = T334 | io_in_5_valid;
assign T334 = T335 | io_in_4_valid;
assign T335 = T336 | io_in_3_valid;
assign T336 = T337 | io_in_2_valid;
assign T337 = T338 | io_in_1_valid;
assign T338 = T339 | io_in_0_valid;
assign T339 = T340 | T178;
assign T340 = T341 | T181;
assign T341 = T342 | T184;
assign T342 = T343 | T187;
assign T343 = T344 | T190;
assign T344 = T345 | T193;
assign T345 = T198 | T196;
assign T346 = T348 & T347;
assign T348 = ~T349;
assign T349 = T350 | T181;
assign T350 = T351 | T184;
assign T351 = T352 | T187;
assign T352 = T353 | T190;
assign T353 = T354 | T193;
assign T354 = T198 | T196;
assign N72 = T17 | reset;
assign N73 = ~N72;
assign N78 = T45 | reset;
assign N79 = ~N78;
assign N84 = T58 | reset;
assign N85 = T47 | N84;
assign N86 = ~N85;
assign N89 = T47 | reset;
assign N90 = ~N89;
assign N94 = ~reset;
assign N95 = T17 & N94;
assign N96 = T45 & N94;
assign N97 = T58 & N94;
assign N98 = ~T58;
assign N99 = N94 & N98;
assign N100 = T47 & N99;
assign N101 = T47 & N94;
endmodule |
module LockingRRArbiter_6
(
clk,
reset,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_header_src,
io_in_4_bits_header_dst,
io_in_4_bits_payload_addr_beat,
io_in_4_bits_payload_addr_block,
io_in_4_bits_payload_client_xact_id,
io_in_4_bits_payload_voluntary,
io_in_4_bits_payload_r_type,
io_in_4_bits_payload_data,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_header_src,
io_in_3_bits_header_dst,
io_in_3_bits_payload_addr_beat,
io_in_3_bits_payload_addr_block,
io_in_3_bits_payload_client_xact_id,
io_in_3_bits_payload_voluntary,
io_in_3_bits_payload_r_type,
io_in_3_bits_payload_data,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_header_src,
io_in_2_bits_header_dst,
io_in_2_bits_payload_addr_beat,
io_in_2_bits_payload_addr_block,
io_in_2_bits_payload_client_xact_id,
io_in_2_bits_payload_voluntary,
io_in_2_bits_payload_r_type,
io_in_2_bits_payload_data,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_header_src,
io_in_1_bits_header_dst,
io_in_1_bits_payload_addr_beat,
io_in_1_bits_payload_addr_block,
io_in_1_bits_payload_client_xact_id,
io_in_1_bits_payload_voluntary,
io_in_1_bits_payload_r_type,
io_in_1_bits_payload_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_header_src,
io_in_0_bits_header_dst,
io_in_0_bits_payload_addr_beat,
io_in_0_bits_payload_addr_block,
io_in_0_bits_payload_client_xact_id,
io_in_0_bits_payload_voluntary,
io_in_0_bits_payload_r_type,
io_in_0_bits_payload_data,
io_out_ready,
io_out_valid,
io_out_bits_header_src,
io_out_bits_header_dst,
io_out_bits_payload_addr_beat,
io_out_bits_payload_addr_block,
io_out_bits_payload_client_xact_id,
io_out_bits_payload_voluntary,
io_out_bits_payload_r_type,
io_out_bits_payload_data,
io_chosen
);
input [2:0] io_in_4_bits_header_src;
input [2:0] io_in_4_bits_header_dst;
input [1:0] io_in_4_bits_payload_addr_beat;
input [25:0] io_in_4_bits_payload_addr_block;
input [5:0] io_in_4_bits_payload_client_xact_id;
input [2:0] io_in_4_bits_payload_r_type;
input [127:0] io_in_4_bits_payload_data;
input [2:0] io_in_3_bits_header_src;
input [2:0] io_in_3_bits_header_dst;
input [1:0] io_in_3_bits_payload_addr_beat;
input [25:0] io_in_3_bits_payload_addr_block;
input [5:0] io_in_3_bits_payload_client_xact_id;
input [2:0] io_in_3_bits_payload_r_type;
input [127:0] io_in_3_bits_payload_data;
input [2:0] io_in_2_bits_header_src;
input [2:0] io_in_2_bits_header_dst;
input [1:0] io_in_2_bits_payload_addr_beat;
input [25:0] io_in_2_bits_payload_addr_block;
input [5:0] io_in_2_bits_payload_client_xact_id;
input [2:0] io_in_2_bits_payload_r_type;
input [127:0] io_in_2_bits_payload_data;
input [2:0] io_in_1_bits_header_src;
input [2:0] io_in_1_bits_header_dst;
input [1:0] io_in_1_bits_payload_addr_beat;
input [25:0] io_in_1_bits_payload_addr_block;
input [5:0] io_in_1_bits_payload_client_xact_id;
input [2:0] io_in_1_bits_payload_r_type;
input [127:0] io_in_1_bits_payload_data;
input [2:0] io_in_0_bits_header_src;
input [2:0] io_in_0_bits_header_dst;
input [1:0] io_in_0_bits_payload_addr_beat;
input [25:0] io_in_0_bits_payload_addr_block;
input [5:0] io_in_0_bits_payload_client_xact_id;
input [2:0] io_in_0_bits_payload_r_type;
input [127:0] io_in_0_bits_payload_data;
output [2:0] io_out_bits_header_src;
output [2:0] io_out_bits_header_dst;
output [1:0] io_out_bits_payload_addr_beat;
output [25:0] io_out_bits_payload_addr_block;
output [5:0] io_out_bits_payload_client_xact_id;
output [2:0] io_out_bits_payload_r_type;
output [127:0] io_out_bits_payload_data;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_4_valid;
input io_in_4_bits_payload_voluntary;
input io_in_3_valid;
input io_in_3_bits_payload_voluntary;
input io_in_2_valid;
input io_in_2_bits_payload_voluntary;
input io_in_1_valid;
input io_in_1_bits_payload_voluntary;
input io_in_0_valid;
input io_in_0_bits_payload_voluntary;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_payload_voluntary;
wire [2:0] io_out_bits_header_src,io_out_bits_header_dst,io_out_bits_payload_r_type,
io_chosen,choose,T1,T2,T3,T4,T5,T6,T19,T20,T21,T55,T58,T56,T95,T98,T96,T103,T106,T104;
wire [1:0] io_out_bits_payload_addr_beat,T40,T87,T90,T88;
wire [25:0] io_out_bits_payload_addr_block,T79,T82,T80;
wire [5:0] io_out_bits_payload_client_xact_id,T71,T74,T72;
wire [127:0] io_out_bits_payload_data,T46,T50,T47;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,io_out_bits_payload_voluntary,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,
N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,T16,N30,T14,N31,
T12,N32,T8,N33,N34,N35,N36,N37,T9,T11,T13,T15,T17,T27,T26,N38,T25,N39,T24,N40,
T23,N41,T29,T28,T35,T30,T32,T43,T38,T39,T44,N42,N43,N44,T63,T66,T64,T111,T114,T112,
T119,T120,T136,T121,T122,T125,T123,T124,T128,T126,T127,T131,T129,T130,T134,T132,
T133,T135,T139,T140,T147,T141,T142,T143,T144,T145,T146,T149,T148,T152,T153,T161,
T154,T155,T156,T157,T158,T159,T160,T163,T162,T164,T167,T168,T177,T169,T170,T171,
T172,T173,T174,T175,T176,T179,T178,T180,T181,T184,T185,T195,T186,T187,T188,T189,
T190,T191,T192,T193,T194,T197,T196,T198,T199,T200,N45,N46,N47,N48,N49,N50,N51,
N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,
N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,
N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,
N110,N111,N112;
wire [2:1] T7,T22;
reg [2:0] last_grant,lockIdx;
reg locked;
reg [1:0] R41;
assign T13 = last_grant < { 1'b1, 1'b1 };
assign T39 = T40 == 1'b0;
assign T127 = last_grant < { 1'b1, 1'b1 };
assign T135 = last_grant < 1'b0;
assign T136 = last_grant < 1'b0;
assign T178 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N47) begin
last_grant[2] <= N50;
end
end
always @(posedge clk) begin
if(N47) begin
last_grant[1] <= N49;
end
end
always @(posedge clk) begin
if(N47) begin
last_grant[0] <= N48;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[2] <= N56;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[1] <= N55;
end
end
always @(posedge clk) begin
if(N53) begin
lockIdx[0] <= N54;
end
end
always @(posedge clk) begin
if(N60) begin
locked <= N61;
end
end
always @(posedge clk) begin
if(N64) begin
R41[1] <= N66;
end
end
always @(posedge clk) begin
if(N64) begin
R41[0] <= N65;
end
end
assign N75 = ~lockIdx[2];
assign N76 = lockIdx[1] | N75;
assign N77 = lockIdx[0] | N76;
assign N78 = ~N77;
assign N79 = lockIdx[1] | lockIdx[2];
assign N80 = lockIdx[0] | N79;
assign N81 = ~N80;
assign N82 = ~lockIdx[0];
assign N83 = lockIdx[1] | lockIdx[2];
assign N84 = N82 | N83;
assign N85 = ~N84;
assign N86 = ~io_out_bits_payload_r_type[1];
assign N87 = N86 | io_out_bits_payload_r_type[2];
assign N88 = io_out_bits_payload_r_type[0] | N87;
assign N89 = ~N88;
assign N90 = ~lockIdx[1];
assign N91 = N90 | lockIdx[2];
assign N92 = lockIdx[0] | N91;
assign N93 = ~N92;
assign N94 = io_out_bits_payload_r_type[1] | io_out_bits_payload_r_type[2];
assign N95 = io_out_bits_payload_r_type[0] | N94;
assign N96 = ~N95;
assign N97 = ~io_out_bits_payload_r_type[0];
assign N98 = io_out_bits_payload_r_type[1] | io_out_bits_payload_r_type[2];
assign N99 = N97 | N98;
assign N100 = ~N99;
assign N101 = N90 | lockIdx[2];
assign N102 = N82 | N101;
assign N103 = ~N102;
assign T40 = R41 + 1'b1;
assign io_chosen = (N0)? lockIdx :
(N1)? choose : 1'b0;
assign N0 = locked;
assign N1 = N29;
assign choose = (N2)? { 1'b0, 1'b0, 1'b1 } :
(N3)? T1 : 1'b0;
assign N2 = T16;
assign N3 = N30;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b0 } :
(N5)? T2 : 1'b0;
assign N4 = T14;
assign N5 = N31;
assign T2 = (N6)? { 1'b0, 1'b1, 1'b1 } :
(N7)? T3 : 1'b0;
assign N6 = T12;
assign N7 = N32;
assign T3 = (N8)? { 1'b1, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = T8;
assign N9 = N33;
assign T4 = (N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? T5 : 1'b0;
assign N10 = io_in_0_valid;
assign N11 = N34;
assign T5 = (N12)? { 1'b0, 1'b0, 1'b1 } :
(N13)? T6 : 1'b0;
assign N12 = io_in_1_valid;
assign N13 = N35;
assign T6 = (N14)? { 1'b0, 1'b1, 1'b0 } :
(N15)? { T7, T7[1:1] } : 1'b0;
assign N14 = io_in_2_valid;
assign N15 = N36;
assign T19 = (N16)? { 1'b0, 1'b0, 1'b0 } :
(N17)? T20 : 1'b0;
assign N16 = T26;
assign N17 = N38;
assign T20 = (N18)? { 1'b0, 1'b0, 1'b1 } :
(N19)? T21 : 1'b0;
assign N18 = T25;
assign N19 = N39;
assign T21 = (N20)? { 1'b0, 1'b1, 1'b0 } :
(N21)? { T22, T22[1:1] } : 1'b0;
assign N20 = T24;
assign N21 = N40;
assign io_out_bits_payload_data = (N22)? io_in_4_bits_payload_data :
(N23)? T46 : 1'b0;
assign N22 = io_chosen[2];
assign N23 = N42;
assign T46 = (N24)? T50 :
(N25)? T47 : 1'b0;
assign N24 = io_chosen[1];
assign N25 = N43;
assign T47 = (N26)? io_in_1_bits_payload_data :
(N27)? io_in_0_bits_payload_data : 1'b0;
assign N26 = io_chosen[0];
assign N27 = N44;
assign T50 = (N26)? io_in_3_bits_payload_data :
(N27)? io_in_2_bits_payload_data : 1'b0;
assign io_out_bits_payload_r_type = (N22)? io_in_4_bits_payload_r_type :
(N23)? T55 : 1'b0;
assign T55 = (N24)? T58 :
(N25)? T56 : 1'b0;
assign T56 = (N26)? io_in_1_bits_payload_r_type :
(N27)? io_in_0_bits_payload_r_type : 1'b0;
assign T58 = (N26)? io_in_3_bits_payload_r_type :
(N27)? io_in_2_bits_payload_r_type : 1'b0;
assign io_out_bits_payload_voluntary = (N22)? io_in_4_bits_payload_voluntary :
(N23)? T63 : 1'b0;
assign T63 = (N24)? T66 :
(N25)? T64 : 1'b0;
assign T64 = (N26)? io_in_1_bits_payload_voluntary :
(N27)? io_in_0_bits_payload_voluntary : 1'b0;
assign T66 = (N26)? io_in_3_bits_payload_voluntary :
(N27)? io_in_2_bits_payload_voluntary : 1'b0;
assign io_out_bits_payload_client_xact_id = (N22)? io_in_4_bits_payload_client_xact_id :
(N23)? T71 : 1'b0;
assign T71 = (N24)? T74 :
(N25)? T72 : 1'b0;
assign T72 = (N26)? io_in_1_bits_payload_client_xact_id :
(N27)? io_in_0_bits_payload_client_xact_id : 1'b0;
assign T74 = (N26)? io_in_3_bits_payload_client_xact_id :
(N27)? io_in_2_bits_payload_client_xact_id : 1'b0;
assign io_out_bits_payload_addr_block = (N22)? io_in_4_bits_payload_addr_block :
(N23)? T79 : 1'b0;
assign T79 = (N24)? T82 :
(N25)? T80 : 1'b0;
assign T80 = (N26)? io_in_1_bits_payload_addr_block :
(N27)? io_in_0_bits_payload_addr_block : 1'b0;
assign T82 = (N26)? io_in_3_bits_payload_addr_block :
(N27)? io_in_2_bits_payload_addr_block : 1'b0;
assign io_out_bits_payload_addr_beat = (N22)? io_in_4_bits_payload_addr_beat :
(N23)? T87 : 1'b0;
assign T87 = (N24)? T90 :
(N25)? T88 : 1'b0;
assign T88 = (N26)? io_in_1_bits_payload_addr_beat :
(N27)? io_in_0_bits_payload_addr_beat : 1'b0;
assign T90 = (N26)? io_in_3_bits_payload_addr_beat :
(N27)? io_in_2_bits_payload_addr_beat : 1'b0;
assign io_out_bits_header_dst = (N22)? io_in_4_bits_header_dst :
(N23)? T95 : 1'b0;
assign T95 = (N24)? T98 :
(N25)? T96 : 1'b0;
assign T96 = (N26)? io_in_1_bits_header_dst :
(N27)? io_in_0_bits_header_dst : 1'b0;
assign T98 = (N26)? io_in_3_bits_header_dst :
(N27)? io_in_2_bits_header_dst : 1'b0;
assign io_out_bits_header_src = (N22)? io_in_4_bits_header_src :
(N23)? T103 : 1'b0;
assign T103 = (N24)? T106 :
(N25)? T104 : 1'b0;
assign T104 = (N26)? io_in_1_bits_header_src :
(N27)? io_in_0_bits_header_src : 1'b0;
assign T106 = (N26)? io_in_3_bits_header_src :
(N27)? io_in_2_bits_header_src : 1'b0;
assign io_out_valid = (N22)? io_in_4_valid :
(N23)? T111 : 1'b0;
assign T111 = (N24)? T114 :
(N25)? T112 : 1'b0;
assign T112 = (N26)? io_in_1_valid :
(N27)? io_in_0_valid : 1'b0;
assign T114 = (N26)? io_in_3_valid :
(N27)? io_in_2_valid : 1'b0;
assign T119 = (N0)? N81 :
(N1)? T120 : 1'b0;
assign T139 = (N0)? N85 :
(N1)? T140 : 1'b0;
assign T152 = (N0)? N93 :
(N1)? T153 : 1'b0;
assign T167 = (N0)? N103 :
(N1)? T168 : 1'b0;
assign T184 = (N0)? N78 :
(N1)? T185 : 1'b0;
assign N47 = (N28)? 1'b1 :
(N68)? 1'b1 :
(N46)? 1'b0 : 1'b0;
assign N28 = reset;
assign { N50, N49, N48 } = (N28)? { 1'b0, 1'b0, 1'b0 } :
(N68)? io_chosen : 1'b0;
assign N53 = (N28)? 1'b1 :
(N69)? 1'b1 :
(N52)? 1'b0 : 1'b0;
assign { N56, N55, N54 } = (N28)? { 1'b1, 1'b0, 1'b0 } :
(N69)? T19 : 1'b0;
assign N60 = (N28)? 1'b1 :
(N70)? 1'b1 :
(N73)? 1'b1 :
(N59)? 1'b0 : 1'b0;
assign N61 = (N28)? 1'b0 :
(N70)? 1'b0 :
(N73)? T38 : 1'b0;
assign N64 = (N28)? 1'b1 :
(N74)? 1'b1 :
(N63)? 1'b0 : 1'b0;
assign { N66, N65 } = (N28)? { 1'b0, 1'b0 } :
(N74)? T40 : 1'b0;
assign N29 = ~locked;
assign N30 = ~T16;
assign N31 = ~T14;
assign N32 = ~T12;
assign N33 = ~T8;
assign N34 = ~io_in_0_valid;
assign N35 = ~io_in_1_valid;
assign N36 = ~io_in_2_valid;
assign N37 = ~io_in_3_valid;
assign T7[1] = io_in_3_valid;
assign T7[2] = N37;
assign T8 = io_in_4_valid & T9;
assign T9 = ~last_grant[2];
assign T11 = io_out_ready & io_out_valid;
assign T12 = io_in_3_valid & T13;
assign T14 = io_in_2_valid & T15;
assign T15 = ~N104;
assign N104 = last_grant[2] | last_grant[1];
assign T16 = io_in_1_valid & T17;
assign T17 = ~N106;
assign N106 = N105 | last_grant[0];
assign N105 = last_grant[2] | last_grant[1];
assign N38 = ~T26;
assign N39 = ~T25;
assign N40 = ~T24;
assign N41 = ~T23;
assign T22[1] = T23;
assign T22[2] = N41;
assign T23 = io_in_3_ready & io_in_3_valid;
assign T24 = io_in_2_ready & io_in_2_valid;
assign T25 = io_in_1_ready & io_in_1_valid;
assign T26 = io_in_0_ready & io_in_0_valid;
assign T27 = T29 & T28;
assign T28 = ~locked;
assign T29 = T35 & T30;
assign T30 = T32 | N89;
assign T32 = N96 | N100;
assign T35 = io_out_valid & io_out_ready;
assign T38 = ~T39;
assign T43 = T35 & T44;
assign T44 = ~T30;
assign N42 = ~io_chosen[2];
assign N43 = ~io_chosen[1];
assign N44 = ~io_chosen[0];
assign io_in_0_ready = T119 & io_out_ready;
assign T120 = T136 | T121;
assign T121 = ~T122;
assign T122 = T125 | T123;
assign T123 = io_in_4_valid & T124;
assign T124 = ~last_grant[2];
assign T125 = T128 | T126;
assign T126 = io_in_3_valid & T127;
assign T128 = T131 | T129;
assign T129 = io_in_2_valid & T130;
assign T130 = ~N107;
assign N107 = last_grant[2] | last_grant[1];
assign T131 = T134 | T132;
assign T132 = io_in_1_valid & T133;
assign T133 = ~N109;
assign N109 = N108 | last_grant[0];
assign N108 = last_grant[2] | last_grant[1];
assign T134 = io_in_0_valid & T135;
assign io_in_1_ready = T139 & io_out_ready;
assign T140 = T147 | T141;
assign T141 = ~T142;
assign T142 = T143 | io_in_0_valid;
assign T143 = T144 | T123;
assign T144 = T145 | T126;
assign T145 = T146 | T129;
assign T146 = T134 | T132;
assign T147 = T149 & T148;
assign T148 = ~N111;
assign N111 = N110 | last_grant[0];
assign N110 = last_grant[2] | last_grant[1];
assign T149 = ~T134;
assign io_in_2_ready = T152 & io_out_ready;
assign T153 = T161 | T154;
assign T154 = ~T155;
assign T155 = T156 | io_in_1_valid;
assign T156 = T157 | io_in_0_valid;
assign T157 = T158 | T123;
assign T158 = T159 | T126;
assign T159 = T160 | T129;
assign T160 = T134 | T132;
assign T161 = T163 & T162;
assign T162 = ~N112;
assign N112 = last_grant[2] | last_grant[1];
assign T163 = ~T164;
assign T164 = T134 | T132;
assign io_in_3_ready = T167 & io_out_ready;
assign T168 = T177 | T169;
assign T169 = ~T170;
assign T170 = T171 | io_in_2_valid;
assign T171 = T172 | io_in_1_valid;
assign T172 = T173 | io_in_0_valid;
assign T173 = T174 | T123;
assign T174 = T175 | T126;
assign T175 = T176 | T129;
assign T176 = T134 | T132;
assign T177 = T179 & T178;
assign T179 = ~T180;
assign T180 = T181 | T129;
assign T181 = T134 | T132;
assign io_in_4_ready = T184 & io_out_ready;
assign T185 = T195 | T186;
assign T186 = ~T187;
assign T187 = T188 | io_in_3_valid;
assign T188 = T189 | io_in_2_valid;
assign T189 = T190 | io_in_1_valid;
assign T190 = T191 | io_in_0_valid;
assign T191 = T192 | T123;
assign T192 = T193 | T126;
assign T193 = T194 | T129;
assign T194 = T134 | T132;
assign T195 = T197 & T196;
assign T196 = ~last_grant[2];
assign T197 = ~T198;
assign T198 = T199 | T126;
assign T199 = T200 | T129;
assign T200 = T134 | T132;
assign N45 = T11 | reset;
assign N46 = ~N45;
assign N51 = T27 | reset;
assign N52 = ~N51;
assign N57 = T43 | reset;
assign N58 = T29 | N57;
assign N59 = ~N58;
assign N62 = T29 | reset;
assign N63 = ~N62;
assign N67 = ~reset;
assign N68 = T11 & N67;
assign N69 = T27 & N67;
assign N70 = T43 & N67;
assign N71 = ~T43;
assign N72 = N67 & N71;
assign N73 = T29 & N72;
assign N74 = T29 & N67;
endmodule |
module Queue_10
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_addr,
io_enq_bits_tag,
io_enq_bits_cmd,
io_enq_bits_typ,
io_enq_bits_kill,
io_enq_bits_phys,
io_enq_bits_data,
io_deq_ready,
io_deq_valid,
io_deq_bits_addr,
io_deq_bits_tag,
io_deq_bits_cmd,
io_deq_bits_typ,
io_deq_bits_kill,
io_deq_bits_phys,
io_deq_bits_data,
io_count
);
input [39:0] io_enq_bits_addr;
input [9:0] io_enq_bits_tag;
input [4:0] io_enq_bits_cmd;
input [2:0] io_enq_bits_typ;
input [63:0] io_enq_bits_data;
output [39:0] io_deq_bits_addr;
output [9:0] io_deq_bits_tag;
output [4:0] io_deq_bits_cmd;
output [2:0] io_deq_bits_typ;
output [63:0] io_deq_bits_data;
input clk;
input reset;
input io_enq_valid;
input io_enq_bits_kill;
input io_enq_bits_phys;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
output io_deq_bits_kill;
output io_deq_bits_phys;
output io_count;
wire [39:0] io_deq_bits_addr;
wire [9:0] io_deq_bits_tag;
wire [4:0] io_deq_bits_cmd;
wire [2:0] io_deq_bits_typ;
wire [63:0] io_deq_bits_data;
wire io_enq_ready,io_deq_valid,io_deq_bits_kill,io_deq_bits_phys,io_count,N0,N1,N2,
T4,do_enq,T3,T2,do_flow,empty,do_deq,T6,T5,N3,T31,N4,N5,N6,N7,N8,N9;
reg [1:1] T0;
reg [123:64] T9;
reg [63:0] T8;
assign io_count = 1'b0;
assign T4 = do_enq ^ do_deq;
always @(posedge clk) begin
if(N6) begin
T0[1] <= N7;
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[123] <= io_enq_bits_addr[39];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[122] <= io_enq_bits_addr[38];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[121] <= io_enq_bits_addr[37];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[120] <= io_enq_bits_addr[36];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[119] <= io_enq_bits_addr[35];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[118] <= io_enq_bits_addr[34];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[117] <= io_enq_bits_addr[33];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[116] <= io_enq_bits_addr[32];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[115] <= io_enq_bits_addr[31];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[114] <= io_enq_bits_addr[30];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[113] <= io_enq_bits_addr[29];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[112] <= io_enq_bits_addr[28];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[111] <= io_enq_bits_addr[27];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[110] <= io_enq_bits_addr[26];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[109] <= io_enq_bits_addr[25];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[108] <= io_enq_bits_addr[24];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[107] <= io_enq_bits_addr[23];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[106] <= io_enq_bits_addr[22];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[105] <= io_enq_bits_addr[21];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[104] <= io_enq_bits_addr[20];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[103] <= io_enq_bits_addr[19];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[102] <= io_enq_bits_addr[18];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[101] <= io_enq_bits_addr[17];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[100] <= io_enq_bits_addr[16];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[99] <= io_enq_bits_addr[15];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[98] <= io_enq_bits_addr[14];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[97] <= io_enq_bits_addr[13];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[96] <= io_enq_bits_addr[12];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[95] <= io_enq_bits_addr[11];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[94] <= io_enq_bits_addr[10];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[93] <= io_enq_bits_addr[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[92] <= io_enq_bits_addr[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[91] <= io_enq_bits_addr[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[90] <= io_enq_bits_addr[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[89] <= io_enq_bits_addr[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[88] <= io_enq_bits_addr[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[87] <= io_enq_bits_addr[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[86] <= io_enq_bits_addr[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[85] <= io_enq_bits_addr[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[84] <= io_enq_bits_addr[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[83] <= io_enq_bits_tag[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[82] <= io_enq_bits_tag[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[81] <= io_enq_bits_tag[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[80] <= io_enq_bits_tag[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[79] <= io_enq_bits_tag[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[78] <= io_enq_bits_tag[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[77] <= io_enq_bits_tag[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[76] <= io_enq_bits_tag[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[75] <= io_enq_bits_tag[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[74] <= io_enq_bits_tag[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[73] <= io_enq_bits_cmd[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[72] <= io_enq_bits_cmd[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[71] <= io_enq_bits_cmd[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[70] <= io_enq_bits_cmd[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[69] <= io_enq_bits_cmd[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[68] <= io_enq_bits_typ[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[67] <= io_enq_bits_typ[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[66] <= io_enq_bits_typ[0];
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[65] <= io_enq_bits_kill;
end
end
always @(posedge clk) begin
if(do_enq) begin
T9[64] <= io_enq_bits_phys;
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[63] <= io_enq_bits_data[63];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[62] <= io_enq_bits_data[62];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[61] <= io_enq_bits_data[61];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[60] <= io_enq_bits_data[60];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[59] <= io_enq_bits_data[59];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[58] <= io_enq_bits_data[58];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[57] <= io_enq_bits_data[57];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[56] <= io_enq_bits_data[56];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[55] <= io_enq_bits_data[55];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[54] <= io_enq_bits_data[54];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[53] <= io_enq_bits_data[53];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[52] <= io_enq_bits_data[52];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[51] <= io_enq_bits_data[51];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[50] <= io_enq_bits_data[50];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[49] <= io_enq_bits_data[49];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[48] <= io_enq_bits_data[48];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[47] <= io_enq_bits_data[47];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[46] <= io_enq_bits_data[46];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[45] <= io_enq_bits_data[45];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[44] <= io_enq_bits_data[44];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[43] <= io_enq_bits_data[43];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[42] <= io_enq_bits_data[42];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[41] <= io_enq_bits_data[41];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[40] <= io_enq_bits_data[40];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[39] <= io_enq_bits_data[39];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[38] <= io_enq_bits_data[38];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[37] <= io_enq_bits_data[37];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[36] <= io_enq_bits_data[36];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[35] <= io_enq_bits_data[35];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[34] <= io_enq_bits_data[34];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[33] <= io_enq_bits_data[33];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[32] <= io_enq_bits_data[32];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[31] <= io_enq_bits_data[31];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[30] <= io_enq_bits_data[30];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[29] <= io_enq_bits_data[29];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[28] <= io_enq_bits_data[28];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[27] <= io_enq_bits_data[27];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[26] <= io_enq_bits_data[26];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[25] <= io_enq_bits_data[25];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[24] <= io_enq_bits_data[24];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[23] <= io_enq_bits_data[23];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[22] <= io_enq_bits_data[22];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[21] <= io_enq_bits_data[21];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[20] <= io_enq_bits_data[20];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[19] <= io_enq_bits_data[19];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[18] <= io_enq_bits_data[18];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[17] <= io_enq_bits_data[17];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[16] <= io_enq_bits_data[16];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[15] <= io_enq_bits_data[15];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[14] <= io_enq_bits_data[14];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[13] <= io_enq_bits_data[13];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[12] <= io_enq_bits_data[12];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[11] <= io_enq_bits_data[11];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[10] <= io_enq_bits_data[10];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[9] <= io_enq_bits_data[9];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[8] <= io_enq_bits_data[8];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[7] <= io_enq_bits_data[7];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[6] <= io_enq_bits_data[6];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[5] <= io_enq_bits_data[5];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[4] <= io_enq_bits_data[4];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[3] <= io_enq_bits_data[3];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[2] <= io_enq_bits_data[2];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[1] <= io_enq_bits_data[1];
end
end
always @(posedge clk) begin
if(do_enq) begin
T8[0] <= io_enq_bits_data[0];
end
end
assign io_deq_bits_data = (N0)? io_enq_bits_data :
(N1)? T8 : 1'b0;
assign N0 = empty;
assign N1 = N3;
assign io_deq_bits_phys = (N0)? io_enq_bits_phys :
(N1)? T9[64] : 1'b0;
assign io_deq_bits_kill = (N0)? io_enq_bits_kill :
(N1)? T9[65] : 1'b0;
assign io_deq_bits_typ = (N0)? io_enq_bits_typ :
(N1)? T9[68:66] : 1'b0;
assign io_deq_bits_cmd = (N0)? io_enq_bits_cmd :
(N1)? T9[73:69] : 1'b0;
assign io_deq_bits_tag = (N0)? io_enq_bits_tag :
(N1)? T9[83:74] : 1'b0;
assign io_deq_bits_addr = (N0)? io_enq_bits_addr :
(N1)? T9[123:84] : 1'b0;
assign N6 = (N2)? 1'b1 :
(N9)? 1'b1 :
(N5)? 1'b0 : 1'b0;
assign N2 = reset;
assign N7 = (N2)? 1'b0 :
(N9)? do_enq : 1'b0;
assign do_enq = T3 & T2;
assign T2 = ~do_flow;
assign do_flow = empty & io_deq_ready;
assign empty = ~T0[1];
assign T3 = io_enq_ready & io_enq_valid;
assign do_deq = T6 & T5;
assign T5 = ~do_flow;
assign T6 = io_deq_ready & io_deq_valid;
assign N3 = ~empty;
assign io_deq_valid = T31 | io_enq_valid;
assign T31 = ~empty;
assign io_enq_ready = ~T0[1];
assign N4 = T4 | reset;
assign N5 = ~N4;
assign N8 = ~reset;
assign N9 = T4 & N8;
endmodule |
module Queue_5
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_resp,
io_enq_bits_id,
io_enq_bits_user,
io_deq_ready,
io_deq_valid,
io_deq_bits_resp,
io_deq_bits_id,
io_deq_bits_user,
io_count
);
input [1:0] io_enq_bits_resp;
input [5:0] io_enq_bits_id;
output [1:0] io_deq_bits_resp;
output [5:0] io_deq_bits_id;
output [1:0] io_count;
input clk;
input reset;
input io_enq_valid;
input io_enq_bits_user;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
output io_deq_bits_user;
wire [1:0] io_deq_bits_resp,io_count;
wire [5:0] io_deq_bits_id;
wire io_enq_ready,io_deq_valid,io_deq_bits_user,N0,N1,N2,N3,N4,do_deq,T3,do_enq,T6,
ptr_match,T9,N5,empty,T19,full,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,
N19,N21,N22,N23,N24,N25,N26;
reg R1,N20,maybe_full;
reg [17:0] ram;
assign N0 = N20 ^ R1;
assign ptr_match = ~N0;
assign T9 = do_enq ^ do_deq;
assign io_deq_bits_resp[1] = (N5)? ram[8] :
(N1)? ram[17] : 1'b0;
assign N1 = R1;
assign io_deq_bits_resp[0] = (N5)? ram[7] :
(N1)? ram[16] : 1'b0;
assign io_deq_bits_id[5] = (N5)? ram[6] :
(N1)? ram[15] : 1'b0;
assign io_deq_bits_id[4] = (N5)? ram[5] :
(N1)? ram[14] : 1'b0;
assign io_deq_bits_id[3] = (N5)? ram[4] :
(N1)? ram[13] : 1'b0;
assign io_deq_bits_id[2] = (N5)? ram[3] :
(N1)? ram[12] : 1'b0;
assign io_deq_bits_id[1] = (N5)? ram[2] :
(N1)? ram[11] : 1'b0;
assign io_deq_bits_id[0] = (N5)? ram[1] :
(N1)? ram[10] : 1'b0;
assign io_deq_bits_user = (N5)? ram[0] :
(N1)? ram[9] : 1'b0;
always @(posedge clk) begin
if(N8) begin
R1 <= N9;
end
end
always @(posedge clk) begin
if(N12) begin
N20 <= N13;
end
end
always @(posedge clk) begin
if(N16) begin
maybe_full <= N17;
end
end
always @(posedge clk) begin
if(N22) begin
ram[17] <= io_enq_bits_resp[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[16] <= io_enq_bits_resp[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[15] <= io_enq_bits_id[5];
end
end
always @(posedge clk) begin
if(N22) begin
ram[14] <= io_enq_bits_id[4];
end
end
always @(posedge clk) begin
if(N22) begin
ram[13] <= io_enq_bits_id[3];
end
end
always @(posedge clk) begin
if(N22) begin
ram[12] <= io_enq_bits_id[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[11] <= io_enq_bits_id[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[10] <= io_enq_bits_id[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[9] <= io_enq_bits_user;
end
end
always @(posedge clk) begin
if(N21) begin
ram[8] <= io_enq_bits_resp[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[7] <= io_enq_bits_resp[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[6] <= io_enq_bits_id[5];
end
end
always @(posedge clk) begin
if(N21) begin
ram[5] <= io_enq_bits_id[4];
end
end
always @(posedge clk) begin
if(N21) begin
ram[4] <= io_enq_bits_id[3];
end
end
always @(posedge clk) begin
if(N21) begin
ram[3] <= io_enq_bits_id[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[2] <= io_enq_bits_id[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[1] <= io_enq_bits_id[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[0] <= io_enq_bits_user;
end
end
assign io_count[0] = N20 ^ R1;
assign T3 = R1 ^ 1'b1;
assign T6 = N20 ^ 1'b1;
assign N19 = ~N20;
assign N8 = (N2)? 1'b1 :
(N24)? 1'b1 :
(N7)? 1'b0 : 1'b0;
assign N2 = reset;
assign N9 = (N2)? 1'b0 :
(N24)? T3 : 1'b0;
assign N12 = (N2)? 1'b1 :
(N25)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign N13 = (N2)? 1'b0 :
(N25)? T6 : 1'b0;
assign N16 = (N2)? 1'b1 :
(N26)? 1'b1 :
(N15)? 1'b0 : 1'b0;
assign N17 = (N2)? 1'b0 :
(N26)? do_enq : 1'b0;
assign { N22, N21 } = (N3)? { N20, N19 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign N3 = do_enq;
assign N4 = N18;
assign do_deq = io_deq_ready & io_deq_valid;
assign do_enq = io_enq_ready & io_enq_valid;
assign io_count[1] = maybe_full & ptr_match;
assign N5 = ~R1;
assign io_deq_valid = ~empty;
assign empty = ptr_match & T19;
assign T19 = ~maybe_full;
assign io_enq_ready = ~full;
assign full = ptr_match & maybe_full;
assign N6 = do_deq | reset;
assign N7 = ~N6;
assign N10 = do_enq | reset;
assign N11 = ~N10;
assign N14 = T9 | reset;
assign N15 = ~N14;
assign N18 = ~do_enq;
assign N23 = ~reset;
assign N24 = do_deq & N23;
assign N25 = do_enq & N23;
assign N26 = T9 & N23;
endmodule |
module RRArbiter_6
(
clk,
reset,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_resp,
io_in_3_bits_id,
io_in_3_bits_user,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_resp,
io_in_2_bits_id,
io_in_2_bits_user,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_resp,
io_in_1_bits_id,
io_in_1_bits_user,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_resp,
io_in_0_bits_id,
io_in_0_bits_user,
io_out_ready,
io_out_valid,
io_out_bits_resp,
io_out_bits_id,
io_out_bits_user,
io_chosen
);
input [1:0] io_in_3_bits_resp;
input [5:0] io_in_3_bits_id;
input [1:0] io_in_2_bits_resp;
input [5:0] io_in_2_bits_id;
input [1:0] io_in_1_bits_resp;
input [5:0] io_in_1_bits_id;
input [1:0] io_in_0_bits_resp;
input [5:0] io_in_0_bits_id;
output [1:0] io_out_bits_resp;
output [5:0] io_out_bits_id;
output [1:0] io_chosen;
input clk;
input reset;
input io_in_3_valid;
input io_in_3_bits_user;
input io_in_2_valid;
input io_in_2_bits_user;
input io_in_1_valid;
input io_in_1_bits_user;
input io_in_0_valid;
input io_in_0_bits_user;
input io_out_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_user;
wire [1:0] io_out_bits_resp,io_chosen,T0,T1,T2,T3,T29,T27;
wire [5:0] io_out_bits_id,T23,T21;
wire io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,io_out_valid,
io_out_bits_user,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,T11,N15,T9,N16,T5,N17,
N18,N19,N20,T6,T8,T10,T12,N21,T17,T14,N22,T35,T33,T39,T52,T40,T41,T44,T42,T43,T47,
T45,T46,T50,T48,T49,T51,T54,T60,T55,T56,T57,T58,T59,T62,T61,T64,T71,T65,T66,T67,
T68,T69,T70,T73,T72,T74,T76,T84,T77,T78,T79,T80,T81,T82,T83,T86,T85,T87,T88,N23,
N24,N25,N26,N27,N28,N29,N30,N31,N32;
wire [0:0] T4;
reg [1:0] last_grant;
assign T6 = last_grant < { 1'b1, 1'b1 };
assign T43 = last_grant < { 1'b1, 1'b1 };
assign T51 = last_grant < 1'b0;
assign T52 = last_grant < 1'b0;
assign T85 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N25) begin
last_grant[1] <= N27;
end
end
always @(posedge clk) begin
if(N25) begin
last_grant[0] <= N26;
end
end
assign io_chosen = (N0)? { 1'b0, 1'b1 } :
(N1)? T0 : 1'b0;
assign N0 = T11;
assign N1 = N15;
assign T0 = (N2)? { 1'b1, 1'b0 } :
(N3)? T1 : 1'b0;
assign N2 = T9;
assign N3 = N16;
assign T1 = (N4)? { 1'b1, 1'b1 } :
(N5)? T2 : 1'b0;
assign N4 = T5;
assign N5 = N17;
assign T2 = (N6)? { 1'b0, 1'b0 } :
(N7)? T3 : 1'b0;
assign N6 = io_in_0_valid;
assign N7 = N18;
assign T3[0] = (N8)? 1'b1 :
(N9)? T4[0] : 1'b0;
assign N8 = io_in_1_valid;
assign N9 = T3[1];
assign io_out_bits_user = (N10)? T17 :
(N11)? T14 : 1'b0;
assign N10 = io_chosen[1];
assign N11 = N21;
assign T14 = (N12)? io_in_1_bits_user :
(N13)? io_in_0_bits_user : 1'b0;
assign N12 = io_chosen[0];
assign N13 = N22;
assign T17 = (N12)? io_in_3_bits_user :
(N13)? io_in_2_bits_user : 1'b0;
assign io_out_bits_id = (N10)? T23 :
(N11)? T21 : 1'b0;
assign T21 = (N12)? io_in_1_bits_id :
(N13)? io_in_0_bits_id : 1'b0;
assign T23 = (N12)? io_in_3_bits_id :
(N13)? io_in_2_bits_id : 1'b0;
assign io_out_bits_resp = (N10)? T29 :
(N11)? T27 : 1'b0;
assign T27 = (N12)? io_in_1_bits_resp :
(N13)? io_in_0_bits_resp : 1'b0;
assign T29 = (N12)? io_in_3_bits_resp :
(N13)? io_in_2_bits_resp : 1'b0;
assign io_out_valid = (N10)? T35 :
(N11)? T33 : 1'b0;
assign T33 = (N12)? io_in_1_valid :
(N13)? io_in_0_valid : 1'b0;
assign T35 = (N12)? io_in_3_valid :
(N13)? io_in_2_valid : 1'b0;
assign N25 = (N14)? 1'b1 :
(N29)? 1'b1 :
(N24)? 1'b0 : 1'b0;
assign N14 = reset;
assign { N27, N26 } = (N14)? { 1'b0, 1'b0 } :
(N29)? io_chosen : 1'b0;
assign N15 = ~T11;
assign N16 = ~T9;
assign N17 = ~T5;
assign N18 = ~io_in_0_valid;
assign N19 = ~io_in_1_valid;
assign T3[1] = N19;
assign N20 = ~io_in_2_valid;
assign T4[0] = N20;
assign T5 = io_in_3_valid & T6;
assign T8 = io_out_ready & io_out_valid;
assign T9 = io_in_2_valid & T10;
assign T10 = ~last_grant[1];
assign T11 = io_in_1_valid & T12;
assign T12 = ~N30;
assign N30 = last_grant[1] | last_grant[0];
assign N21 = ~io_chosen[1];
assign N22 = ~io_chosen[0];
assign io_in_0_ready = T39 & io_out_ready;
assign T39 = T52 | T40;
assign T40 = ~T41;
assign T41 = T44 | T42;
assign T42 = io_in_3_valid & T43;
assign T44 = T47 | T45;
assign T45 = io_in_2_valid & T46;
assign T46 = ~last_grant[1];
assign T47 = T50 | T48;
assign T48 = io_in_1_valid & T49;
assign T49 = ~N31;
assign N31 = last_grant[1] | last_grant[0];
assign T50 = io_in_0_valid & T51;
assign io_in_1_ready = T54 & io_out_ready;
assign T54 = T60 | T55;
assign T55 = ~T56;
assign T56 = T57 | io_in_0_valid;
assign T57 = T58 | T42;
assign T58 = T59 | T45;
assign T59 = T50 | T48;
assign T60 = T62 & T61;
assign T61 = ~N32;
assign N32 = last_grant[1] | last_grant[0];
assign T62 = ~T50;
assign io_in_2_ready = T64 & io_out_ready;
assign T64 = T71 | T65;
assign T65 = ~T66;
assign T66 = T67 | io_in_1_valid;
assign T67 = T68 | io_in_0_valid;
assign T68 = T69 | T42;
assign T69 = T70 | T45;
assign T70 = T50 | T48;
assign T71 = T73 & T72;
assign T72 = ~last_grant[1];
assign T73 = ~T74;
assign T74 = T50 | T48;
assign io_in_3_ready = T76 & io_out_ready;
assign T76 = T84 | T77;
assign T77 = ~T78;
assign T78 = T79 | io_in_2_valid;
assign T79 = T80 | io_in_1_valid;
assign T80 = T81 | io_in_0_valid;
assign T81 = T82 | T42;
assign T82 = T83 | T45;
assign T83 = T50 | T48;
assign T84 = T86 & T85;
assign T86 = ~T87;
assign T87 = T88 | T45;
assign T88 = T50 | T48;
assign N23 = T8 | reset;
assign N24 = ~N23;
assign N28 = ~reset;
assign N29 = T8 & N28;
endmodule |
module BroadcastVoluntaryReleaseTracker
(
clk,
reset,
io_inner_acquire_ready,
io_inner_acquire_valid,
io_inner_acquire_bits_addr_block,
io_inner_acquire_bits_client_xact_id,
io_inner_acquire_bits_addr_beat,
io_inner_acquire_bits_is_builtin_type,
io_inner_acquire_bits_a_type,
io_inner_acquire_bits_union,
io_inner_acquire_bits_data,
io_inner_acquire_bits_client_id,
io_inner_grant_ready,
io_inner_grant_valid,
io_inner_grant_bits_addr_beat,
io_inner_grant_bits_client_xact_id,
io_inner_grant_bits_manager_xact_id,
io_inner_grant_bits_is_builtin_type,
io_inner_grant_bits_g_type,
io_inner_grant_bits_data,
io_inner_grant_bits_client_id,
io_inner_finish_ready,
io_inner_finish_valid,
io_inner_finish_bits_manager_xact_id,
io_inner_probe_ready,
io_inner_probe_valid,
io_inner_release_ready,
io_inner_release_valid,
io_inner_release_bits_addr_beat,
io_inner_release_bits_addr_block,
io_inner_release_bits_client_xact_id,
io_inner_release_bits_voluntary,
io_inner_release_bits_r_type,
io_inner_release_bits_data,
io_inner_release_bits_client_id,
io_incoherent_0,
io_outer_acquire_ready,
io_outer_acquire_valid,
io_outer_acquire_bits_addr_block,
io_outer_acquire_bits_client_xact_id,
io_outer_acquire_bits_addr_beat,
io_outer_acquire_bits_is_builtin_type,
io_outer_acquire_bits_a_type,
io_outer_acquire_bits_union,
io_outer_acquire_bits_data,
io_outer_grant_ready,
io_outer_grant_valid,
io_outer_grant_bits_addr_beat,
io_outer_grant_bits_client_xact_id,
io_outer_grant_bits_manager_xact_id,
io_outer_grant_bits_is_builtin_type,
io_outer_grant_bits_g_type,
io_outer_grant_bits_data,
io_has_acquire_conflict,
io_has_acquire_match
);
input [25:0] io_inner_acquire_bits_addr_block;
input [5:0] io_inner_acquire_bits_client_xact_id;
input [1:0] io_inner_acquire_bits_addr_beat;
input [2:0] io_inner_acquire_bits_a_type;
input [16:0] io_inner_acquire_bits_union;
input [3:0] io_inner_acquire_bits_data;
input [1:0] io_inner_acquire_bits_client_id;
output [1:0] io_inner_grant_bits_addr_beat;
output [5:0] io_inner_grant_bits_client_xact_id;
output [3:0] io_inner_grant_bits_manager_xact_id;
output [3:0] io_inner_grant_bits_g_type;
output [3:0] io_inner_grant_bits_data;
output [1:0] io_inner_grant_bits_client_id;
input [3:0] io_inner_finish_bits_manager_xact_id;
input [1:0] io_inner_release_bits_addr_beat;
input [25:0] io_inner_release_bits_addr_block;
input [5:0] io_inner_release_bits_client_xact_id;
input [2:0] io_inner_release_bits_r_type;
input [3:0] io_inner_release_bits_data;
input [1:0] io_inner_release_bits_client_id;
output [25:0] io_outer_acquire_bits_addr_block;
output [3:0] io_outer_acquire_bits_client_xact_id;
output [1:0] io_outer_acquire_bits_addr_beat;
output [2:0] io_outer_acquire_bits_a_type;
output [16:0] io_outer_acquire_bits_union;
output [3:0] io_outer_acquire_bits_data;
input [1:0] io_outer_grant_bits_addr_beat;
input [3:0] io_outer_grant_bits_client_xact_id;
input [3:0] io_outer_grant_bits_g_type;
input [3:0] io_outer_grant_bits_data;
input clk;
input reset;
input io_inner_acquire_valid;
input io_inner_acquire_bits_is_builtin_type;
input io_inner_grant_ready;
input io_inner_finish_valid;
input io_inner_probe_ready;
input io_inner_release_valid;
input io_inner_release_bits_voluntary;
input io_incoherent_0;
input io_outer_acquire_ready;
input io_outer_grant_valid;
input io_outer_grant_bits_manager_xact_id;
input io_outer_grant_bits_is_builtin_type;
output io_inner_acquire_ready;
output io_inner_grant_valid;
output io_inner_grant_bits_is_builtin_type;
output io_inner_finish_ready;
output io_inner_probe_valid;
output io_inner_release_ready;
output io_outer_acquire_valid;
output io_outer_acquire_bits_is_builtin_type;
output io_outer_grant_ready;
output io_has_acquire_conflict;
output io_has_acquire_match;
wire [1:0] io_inner_grant_bits_addr_beat,io_outer_acquire_bits_addr_beat,T158;
wire [3:0] io_inner_grant_bits_manager_xact_id,io_inner_grant_bits_g_type,
io_inner_grant_bits_data,io_outer_acquire_bits_client_xact_id,io_outer_acquire_bits_data,T46,T21,
T32,T22,T23,T33,T36,T34,T35,T47,T72,T59,T60,T63,T61,T62,T75,T73,T74,T109,T97,
T101;
wire [2:0] io_outer_acquire_bits_a_type;
wire [16:0] io_outer_acquire_bits_union;
wire io_inner_acquire_ready,io_inner_grant_valid,io_inner_grant_bits_is_builtin_type,
io_inner_finish_ready,io_inner_probe_valid,io_inner_release_ready,
io_outer_acquire_valid,io_outer_acquire_bits_is_builtin_type,io_outer_grant_ready,
io_has_acquire_conflict,io_has_acquire_match,N0,N1,N2,N3,N4,N5,N6,N7,N8,T13,T10,T11,
all_pending_done,T14,T18,T17,T24_0,T31,T26,T28,T37_0,T45,T39,T40,T42,T48_0,T55,T50,T52,
T90,T84,T64_0,T71,T66,T68,T76_0,T83,T78,T80,T85,T87,T91,N9,N10,T99,T103,T105,N11,
N12,N13,T111,T114,T132,T144,T146,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,
N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,
N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,
N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77;
wire [3:3] T24,T37,T48,T64,T76;
wire [0:0] T151,T152,T153,T155,T156,T159;
reg state,pending_ignt;
reg [3:0] pending_writes,pending_irels,xact_data_buffer_0,xact_data_buffer_1,
xact_data_buffer_2,xact_data_buffer_3;
reg [25:0] io_outer_acquire_bits_addr_block;
reg [1:0] io_inner_grant_bits_client_id;
reg [5:0] io_inner_grant_bits_client_xact_id;
assign io_inner_grant_bits_is_builtin_type = 1'b1;
assign io_outer_acquire_bits_is_builtin_type = 1'b1;
assign io_outer_acquire_bits_a_type[0] = 1'b1;
assign io_outer_acquire_bits_a_type[1] = 1'b1;
assign io_outer_acquire_bits_union[0] = 1'b1;
assign io_outer_acquire_bits_union[1] = 1'b1;
assign io_outer_acquire_bits_union[2] = 1'b1;
assign io_outer_acquire_bits_union[3] = 1'b1;
assign io_outer_acquire_bits_union[4] = 1'b1;
assign io_outer_acquire_bits_union[5] = 1'b1;
assign io_outer_acquire_bits_union[6] = 1'b1;
assign io_outer_acquire_bits_union[7] = 1'b1;
assign io_outer_acquire_bits_union[8] = 1'b1;
assign io_outer_acquire_bits_union[9] = 1'b1;
assign io_outer_acquire_bits_union[10] = 1'b1;
assign io_outer_acquire_bits_union[11] = 1'b1;
assign io_outer_acquire_bits_union[12] = 1'b1;
assign io_outer_acquire_bits_union[13] = 1'b1;
assign io_outer_acquire_bits_union[14] = 1'b1;
assign io_outer_acquire_bits_union[15] = 1'b1;
assign io_outer_acquire_bits_union[16] = 1'b1;
assign io_inner_acquire_ready = 1'b0;
assign io_inner_grant_bits_addr_beat[0] = 1'b0;
assign io_inner_grant_bits_addr_beat[1] = 1'b0;
assign io_inner_grant_bits_manager_xact_id[0] = 1'b0;
assign io_inner_grant_bits_manager_xact_id[1] = 1'b0;
assign io_inner_grant_bits_manager_xact_id[2] = 1'b0;
assign io_inner_grant_bits_manager_xact_id[3] = 1'b0;
assign io_inner_grant_bits_g_type[0] = 1'b0;
assign io_inner_grant_bits_g_type[1] = 1'b0;
assign io_inner_grant_bits_g_type[2] = 1'b0;
assign io_inner_grant_bits_g_type[3] = 1'b0;
assign io_inner_grant_bits_data[0] = 1'b0;
assign io_inner_grant_bits_data[1] = 1'b0;
assign io_inner_grant_bits_data[2] = 1'b0;
assign io_inner_grant_bits_data[3] = 1'b0;
assign io_inner_finish_ready = 1'b0;
assign io_inner_probe_valid = 1'b0;
assign io_outer_acquire_bits_client_xact_id[0] = 1'b0;
assign io_outer_acquire_bits_client_xact_id[1] = 1'b0;
assign io_outer_acquire_bits_client_xact_id[2] = 1'b0;
assign io_outer_acquire_bits_client_xact_id[3] = 1'b0;
assign io_outer_acquire_bits_a_type[2] = 1'b0;
assign io_has_acquire_conflict = 1'b0;
assign io_has_acquire_match = 1'b0;
assign T23 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_inner_release_bits_addr_beat;
assign T35 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_outer_acquire_bits_addr_beat;
assign T47 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_inner_release_bits_addr_beat;
assign T62 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_inner_release_bits_addr_beat;
assign T74 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_inner_release_bits_addr_beat;
assign T101 = { 1'b0, 1'b0, 1'b0, 1'b1 } << io_inner_release_bits_addr_beat;
always @(posedge clk) begin
if(N17) begin
state <= N18;
end
end
always @(posedge clk) begin
if(N22) begin
pending_ignt <= N23;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_writes[3] <= N29;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_writes[2] <= N28;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_writes[1] <= N27;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_writes[0] <= N26;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_irels[3] <= N36;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_irels[2] <= N35;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_irels[1] <= N34;
end
end
always @(posedge clk) begin
if(1'b1) begin
pending_irels[0] <= N33;
end
end
always @(posedge clk) begin
if(T99) begin
xact_data_buffer_0[3] <= io_inner_release_bits_data[3];
end
end
always @(posedge clk) begin
if(T99) begin
xact_data_buffer_0[2] <= io_inner_release_bits_data[2];
end
end
always @(posedge clk) begin
if(T99) begin
xact_data_buffer_0[1] <= io_inner_release_bits_data[1];
end
end
always @(posedge clk) begin
if(T99) begin
xact_data_buffer_0[0] <= io_inner_release_bits_data[0];
end
end
always @(posedge clk) begin
if(T105) begin
xact_data_buffer_1[3] <= io_inner_release_bits_data[3];
end
end
always @(posedge clk) begin
if(T105) begin
xact_data_buffer_1[2] <= io_inner_release_bits_data[2];
end
end
always @(posedge clk) begin
if(T105) begin
xact_data_buffer_1[1] <= io_inner_release_bits_data[1];
end
end
always @(posedge clk) begin
if(T105) begin
xact_data_buffer_1[0] <= io_inner_release_bits_data[0];
end
end
always @(posedge clk) begin
if(T111) begin
xact_data_buffer_2[3] <= io_inner_release_bits_data[3];
end
end
always @(posedge clk) begin
if(T111) begin
xact_data_buffer_2[2] <= io_inner_release_bits_data[2];
end
end
always @(posedge clk) begin
if(T111) begin
xact_data_buffer_2[1] <= io_inner_release_bits_data[1];
end
end
always @(posedge clk) begin
if(T111) begin
xact_data_buffer_2[0] <= io_inner_release_bits_data[0];
end
end
always @(posedge clk) begin
if(T114) begin
xact_data_buffer_3[3] <= io_inner_release_bits_data[3];
end
end
always @(posedge clk) begin
if(T114) begin
xact_data_buffer_3[2] <= io_inner_release_bits_data[2];
end
end
always @(posedge clk) begin
if(T114) begin
xact_data_buffer_3[1] <= io_inner_release_bits_data[1];
end
end
always @(posedge clk) begin
if(T114) begin
xact_data_buffer_3[0] <= io_inner_release_bits_data[0];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[25] <= io_inner_release_bits_addr_block[25];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[24] <= io_inner_release_bits_addr_block[24];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[23] <= io_inner_release_bits_addr_block[23];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[22] <= io_inner_release_bits_addr_block[22];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[21] <= io_inner_release_bits_addr_block[21];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[20] <= io_inner_release_bits_addr_block[20];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[19] <= io_inner_release_bits_addr_block[19];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[18] <= io_inner_release_bits_addr_block[18];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[17] <= io_inner_release_bits_addr_block[17];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[16] <= io_inner_release_bits_addr_block[16];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[15] <= io_inner_release_bits_addr_block[15];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[14] <= io_inner_release_bits_addr_block[14];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[13] <= io_inner_release_bits_addr_block[13];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[12] <= io_inner_release_bits_addr_block[12];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[11] <= io_inner_release_bits_addr_block[11];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[10] <= io_inner_release_bits_addr_block[10];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[9] <= io_inner_release_bits_addr_block[9];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[8] <= io_inner_release_bits_addr_block[8];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[7] <= io_inner_release_bits_addr_block[7];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[6] <= io_inner_release_bits_addr_block[6];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[5] <= io_inner_release_bits_addr_block[5];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[4] <= io_inner_release_bits_addr_block[4];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[3] <= io_inner_release_bits_addr_block[3];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[2] <= io_inner_release_bits_addr_block[2];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[1] <= io_inner_release_bits_addr_block[1];
end
end
always @(posedge clk) begin
if(T10) begin
io_outer_acquire_bits_addr_block[0] <= io_inner_release_bits_addr_block[0];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_id[1] <= io_inner_release_bits_client_id[1];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_id[0] <= io_inner_release_bits_client_id[0];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[5] <= io_inner_release_bits_client_xact_id[5];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[4] <= io_inner_release_bits_client_xact_id[4];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[3] <= io_inner_release_bits_client_xact_id[3];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[2] <= io_inner_release_bits_client_xact_id[2];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[1] <= io_inner_release_bits_client_xact_id[1];
end
end
always @(posedge clk) begin
if(T10) begin
io_inner_grant_bits_client_xact_id[0] <= io_inner_release_bits_client_xact_id[0];
end
end
assign N51 = ~io_inner_release_bits_r_type[1];
assign N52 = N51 | io_inner_release_bits_r_type[2];
assign N53 = io_inner_release_bits_r_type[0] | N52;
assign N54 = ~N53;
assign N55 = io_inner_release_bits_r_type[1] | io_inner_release_bits_r_type[2];
assign N56 = io_inner_release_bits_r_type[0] | N55;
assign N57 = ~N56;
assign N58 = ~io_inner_release_bits_r_type[0];
assign N59 = N58 | N55;
assign N60 = ~N59;
assign N61 = pending_irels[2] | pending_irels[3];
assign N62 = pending_irels[1] | N61;
assign N63 = pending_irels[0] | N62;
assign N64 = ~N63;
assign N65 = ~state;
assign N66 = pending_irels[2] | pending_irels[3];
assign N67 = pending_irels[1] | N66;
assign N68 = pending_irels[0] | N67;
assign N69 = pending_writes[2] | pending_writes[3];
assign N70 = pending_writes[1] | N69;
assign N71 = pending_writes[0] | N70;
assign N72 = pending_writes[2] | pending_writes[3];
assign N73 = pending_writes[1] | N72;
assign N74 = pending_writes[0] | N73;
assign N75 = pending_irels[2] | pending_irels[3];
assign N76 = pending_irels[1] | N75;
assign N77 = pending_irels[0] | N76;
assign { T37[3:3], T37_0 } = 1'b0 - T152[0];
assign { T24[3:3], T24_0 } = 1'b0 - T151[0];
assign { T48[3:3], T48_0 } = 1'b0 - T153[0];
assign { T64[3:3], T64_0 } = 1'b0 - T155[0];
assign { T76[3:3], T76_0 } = 1'b0 - T156[0];
assign io_outer_acquire_bits_data = (N0)? T109 :
(N1)? T97 : 1'b0;
assign N0 = io_outer_acquire_bits_addr_beat[1];
assign N1 = N9;
assign T97 = (N2)? xact_data_buffer_1 :
(N3)? xact_data_buffer_0 : 1'b0;
assign N2 = io_outer_acquire_bits_addr_beat[0];
assign N3 = N10;
assign io_outer_acquire_bits_addr_beat = (N4)? { 1'b0, 1'b0 } :
(N5)? T158 : 1'b0;
assign N4 = pending_writes[0];
assign N5 = N11;
assign T158[0] = (N6)? 1'b1 :
(N7)? T159[0] : 1'b0;
assign N6 = pending_writes[1];
assign N7 = T158[1];
assign T109 = (N2)? xact_data_buffer_3 :
(N3)? xact_data_buffer_2 : 1'b0;
assign N17 = (N8)? 1'b1 :
(N37)? 1'b1 :
(N40)? 1'b1 :
(N16)? 1'b0 : 1'b0;
assign N8 = reset;
assign N18 = (N8)? 1'b0 :
(N37)? 1'b0 :
(N40)? 1'b1 : 1'b0;
assign N22 = (N8)? 1'b1 :
(N41)? 1'b1 :
(N44)? 1'b1 :
(N21)? 1'b0 : 1'b0;
assign N23 = (N8)? 1'b0 :
(N41)? 1'b1 :
(N44)? 1'b0 : 1'b0;
assign { N29, N28, N27, N26 } = (N8)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N46)? T46 :
(N25)? T21 : 1'b0;
assign { N36, N35, N34, N33 } = (N8)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N47)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N50)? T72 :
(N32)? T59 : 1'b0;
assign T10 = N65 & T11;
assign T11 = io_inner_release_ready & io_inner_release_valid;
assign T13 = state & all_pending_done;
assign all_pending_done = ~T14;
assign T14 = T18 | pending_ignt;
assign T17 = io_inner_grant_ready & io_inner_grant_valid;
assign T18 = N68 | N71;
assign T21[3] = T32[3] | T22[3];
assign T21[2] = T32[2] | T22[2];
assign T21[1] = T32[1] | T22[1];
assign T21[0] = T32[0] | T22[0];
assign T22[3] = T24[3] & T23[3];
assign T22[2] = T24[3] & T23[2];
assign T22[1] = T24[3] & T23[1];
assign T22[0] = T24_0 & T23[0];
assign T151[0] = T31 & T26;
assign T26 = T28 | N54;
assign T28 = N57 | N60;
assign T31 = io_inner_release_ready & io_inner_release_valid;
assign T32[3] = pending_writes[3] & T33[3];
assign T32[2] = pending_writes[2] & T33[2];
assign T32[1] = pending_writes[1] & T33[1];
assign T32[0] = pending_writes[0] & T33[0];
assign T33[3] = T36[3] | T34[3];
assign T33[2] = T36[2] | T34[2];
assign T33[1] = T36[1] | T34[1];
assign T33[0] = T36[0] | T34[0];
assign T34[3] = ~T35[3];
assign T34[2] = ~T35[2];
assign T34[1] = ~T35[1];
assign T34[0] = ~T35[0];
assign T36[3] = ~T37[3];
assign T36[2] = ~T37[3];
assign T36[1] = ~T37[3];
assign T36[0] = ~T37_0;
assign T152[0] = T45 & T39;
assign T39 = 1'b1 & T40;
assign T40 = T42 | 1'b0;
assign T42 = 1'b0 | 1'b1;
assign T45 = io_outer_acquire_ready & io_outer_acquire_valid;
assign T46[3] = T48[3] & T47[3];
assign T46[2] = T48[3] & T47[2];
assign T46[1] = T48[3] & T47[1];
assign T46[0] = T48_0 & T47[0];
assign T153[0] = T55 & T50;
assign T50 = T52 | N54;
assign T52 = N57 | N60;
assign T55 = io_inner_release_ready & io_inner_release_valid;
assign T59[3] = pending_irels[3] & T60[3];
assign T59[2] = pending_irels[2] & T60[2];
assign T59[1] = pending_irels[1] & T60[1];
assign T59[0] = pending_irels[0] & T60[0];
assign T60[3] = T63[3] | T61[3];
assign T60[2] = T63[2] | T61[2];
assign T60[1] = T63[1] | T61[1];
assign T60[0] = T63[0] | T61[0];
assign T61[3] = ~T62[3];
assign T61[2] = ~T62[2];
assign T61[1] = ~T62[1];
assign T61[0] = ~T62[0];
assign T63[3] = ~T64[3];
assign T63[2] = ~T64[3];
assign T63[1] = ~T64[3];
assign T63[0] = ~T64_0;
assign T155[0] = T71 & T66;
assign T66 = T68 | N54;
assign T68 = N57 | N60;
assign T71 = io_inner_release_ready & io_inner_release_valid;
assign T72[3] = T75[3] | T73[3];
assign T72[2] = T75[2] | T73[2];
assign T72[1] = T75[1] | T73[1];
assign T72[0] = T75[0] | T73[0];
assign T73[3] = ~T74[3];
assign T73[2] = ~T74[2];
assign T73[1] = ~T74[1];
assign T73[0] = ~T74[0];
assign T75[3] = ~T76[3];
assign T75[2] = ~T76[3];
assign T75[1] = ~T76[3];
assign T75[0] = ~T76_0;
assign T156[0] = T83 & T78;
assign T78 = T80 | N54;
assign T80 = N57 | N60;
assign T83 = io_inner_release_ready & io_inner_release_valid;
assign T84 = T10 & T85;
assign T85 = T87 | N54;
assign T87 = N57 | N60;
assign T90 = T10 & T91;
assign T91 = ~T85;
assign io_outer_grant_ready = state & io_inner_grant_ready;
assign N9 = ~io_outer_acquire_bits_addr_beat[1];
assign N10 = ~io_outer_acquire_bits_addr_beat[0];
assign T99 = T103 & T101[0];
assign T103 = io_inner_release_ready & io_inner_release_valid;
assign T105 = T103 & T101[1];
assign N11 = ~pending_writes[0];
assign N12 = ~pending_writes[1];
assign T158[1] = N12;
assign N13 = ~pending_writes[2];
assign T159[0] = N13;
assign T111 = T103 & T101[2];
assign T114 = T103 & T101[3];
assign io_outer_acquire_valid = state & N74;
assign io_inner_release_ready = T132 | N77;
assign T132 = N65 & io_inner_release_bits_voluntary;
assign io_inner_grant_valid = T144 & io_outer_grant_valid;
assign T144 = T146 & N64;
assign T146 = state & pending_ignt;
assign N14 = T13 | reset;
assign N15 = T10 | N14;
assign N16 = ~N15;
assign N19 = T10 | reset;
assign N20 = T17 | N19;
assign N21 = ~N20;
assign N24 = T10 | reset;
assign N25 = ~N24;
assign N30 = T90 | reset;
assign N31 = T84 | N30;
assign N32 = ~N31;
assign N37 = T13 & N45;
assign N38 = ~T13;
assign N39 = N45 & N38;
assign N40 = T10 & N39;
assign N41 = T10 & N45;
assign N42 = ~T10;
assign N43 = N45 & N42;
assign N44 = T17 & N43;
assign N45 = ~reset;
assign N46 = T10 & N45;
assign N47 = T90 & N45;
assign N48 = ~T90;
assign N49 = N45 & N48;
assign N50 = T84 & N49;
endmodule |
module Arbiter_11
(
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_tag,
io_in_0_bits_cmd,
io_in_0_bits_typ,
io_in_0_bits_data,
io_in_0_bits_nack,
io_in_0_bits_replay,
io_in_0_bits_has_data,
io_in_0_bits_data_word_bypass,
io_in_0_bits_store_data,
io_out_ready,
io_out_valid,
io_out_bits_addr,
io_out_bits_tag,
io_out_bits_cmd,
io_out_bits_typ,
io_out_bits_data,
io_out_bits_nack,
io_out_bits_replay,
io_out_bits_has_data,
io_out_bits_data_word_bypass,
io_out_bits_store_data,
io_chosen
);
input [39:0] io_in_0_bits_addr;
input [9:0] io_in_0_bits_tag;
input [4:0] io_in_0_bits_cmd;
input [2:0] io_in_0_bits_typ;
input [63:0] io_in_0_bits_data;
input [63:0] io_in_0_bits_data_word_bypass;
input [63:0] io_in_0_bits_store_data;
output [39:0] io_out_bits_addr;
output [9:0] io_out_bits_tag;
output [4:0] io_out_bits_cmd;
output [2:0] io_out_bits_typ;
output [63:0] io_out_bits_data;
output [63:0] io_out_bits_data_word_bypass;
output [63:0] io_out_bits_store_data;
input io_in_0_valid;
input io_in_0_bits_nack;
input io_in_0_bits_replay;
input io_in_0_bits_has_data;
input io_out_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_nack;
output io_out_bits_replay;
output io_out_bits_has_data;
output io_chosen;
wire [39:0] io_out_bits_addr;
wire [9:0] io_out_bits_tag;
wire [4:0] io_out_bits_cmd;
wire [2:0] io_out_bits_typ;
wire [63:0] io_out_bits_data,io_out_bits_data_word_bypass,io_out_bits_store_data;
wire io_in_0_ready,io_out_valid,io_out_bits_nack,io_out_bits_replay,
io_out_bits_has_data,io_chosen,io_out_ready,io_in_0_valid,io_in_0_bits_nack,io_in_0_bits_replay,
io_in_0_bits_has_data;
assign io_chosen = 1'b0;
assign io_in_0_ready = io_out_ready;
assign io_out_valid = io_in_0_valid;
assign io_out_bits_addr[39] = io_in_0_bits_addr[39];
assign io_out_bits_addr[38] = io_in_0_bits_addr[38];
assign io_out_bits_addr[37] = io_in_0_bits_addr[37];
assign io_out_bits_addr[36] = io_in_0_bits_addr[36];
assign io_out_bits_addr[35] = io_in_0_bits_addr[35];
assign io_out_bits_addr[34] = io_in_0_bits_addr[34];
assign io_out_bits_addr[33] = io_in_0_bits_addr[33];
assign io_out_bits_addr[32] = io_in_0_bits_addr[32];
assign io_out_bits_addr[31] = io_in_0_bits_addr[31];
assign io_out_bits_addr[30] = io_in_0_bits_addr[30];
assign io_out_bits_addr[29] = io_in_0_bits_addr[29];
assign io_out_bits_addr[28] = io_in_0_bits_addr[28];
assign io_out_bits_addr[27] = io_in_0_bits_addr[27];
assign io_out_bits_addr[26] = io_in_0_bits_addr[26];
assign io_out_bits_addr[25] = io_in_0_bits_addr[25];
assign io_out_bits_addr[24] = io_in_0_bits_addr[24];
assign io_out_bits_addr[23] = io_in_0_bits_addr[23];
assign io_out_bits_addr[22] = io_in_0_bits_addr[22];
assign io_out_bits_addr[21] = io_in_0_bits_addr[21];
assign io_out_bits_addr[20] = io_in_0_bits_addr[20];
assign io_out_bits_addr[19] = io_in_0_bits_addr[19];
assign io_out_bits_addr[18] = io_in_0_bits_addr[18];
assign io_out_bits_addr[17] = io_in_0_bits_addr[17];
assign io_out_bits_addr[16] = io_in_0_bits_addr[16];
assign io_out_bits_addr[15] = io_in_0_bits_addr[15];
assign io_out_bits_addr[14] = io_in_0_bits_addr[14];
assign io_out_bits_addr[13] = io_in_0_bits_addr[13];
assign io_out_bits_addr[12] = io_in_0_bits_addr[12];
assign io_out_bits_addr[11] = io_in_0_bits_addr[11];
assign io_out_bits_addr[10] = io_in_0_bits_addr[10];
assign io_out_bits_addr[9] = io_in_0_bits_addr[9];
assign io_out_bits_addr[8] = io_in_0_bits_addr[8];
assign io_out_bits_addr[7] = io_in_0_bits_addr[7];
assign io_out_bits_addr[6] = io_in_0_bits_addr[6];
assign io_out_bits_addr[5] = io_in_0_bits_addr[5];
assign io_out_bits_addr[4] = io_in_0_bits_addr[4];
assign io_out_bits_addr[3] = io_in_0_bits_addr[3];
assign io_out_bits_addr[2] = io_in_0_bits_addr[2];
assign io_out_bits_addr[1] = io_in_0_bits_addr[1];
assign io_out_bits_addr[0] = io_in_0_bits_addr[0];
assign io_out_bits_tag[9] = io_in_0_bits_tag[9];
assign io_out_bits_tag[8] = io_in_0_bits_tag[8];
assign io_out_bits_tag[7] = io_in_0_bits_tag[7];
assign io_out_bits_tag[6] = io_in_0_bits_tag[6];
assign io_out_bits_tag[5] = io_in_0_bits_tag[5];
assign io_out_bits_tag[4] = io_in_0_bits_tag[4];
assign io_out_bits_tag[3] = io_in_0_bits_tag[3];
assign io_out_bits_tag[2] = io_in_0_bits_tag[2];
assign io_out_bits_tag[1] = io_in_0_bits_tag[1];
assign io_out_bits_tag[0] = io_in_0_bits_tag[0];
assign io_out_bits_cmd[4] = io_in_0_bits_cmd[4];
assign io_out_bits_cmd[3] = io_in_0_bits_cmd[3];
assign io_out_bits_cmd[2] = io_in_0_bits_cmd[2];
assign io_out_bits_cmd[1] = io_in_0_bits_cmd[1];
assign io_out_bits_cmd[0] = io_in_0_bits_cmd[0];
assign io_out_bits_typ[2] = io_in_0_bits_typ[2];
assign io_out_bits_typ[1] = io_in_0_bits_typ[1];
assign io_out_bits_typ[0] = io_in_0_bits_typ[0];
assign io_out_bits_data[63] = io_in_0_bits_data[63];
assign io_out_bits_data[62] = io_in_0_bits_data[62];
assign io_out_bits_data[61] = io_in_0_bits_data[61];
assign io_out_bits_data[60] = io_in_0_bits_data[60];
assign io_out_bits_data[59] = io_in_0_bits_data[59];
assign io_out_bits_data[58] = io_in_0_bits_data[58];
assign io_out_bits_data[57] = io_in_0_bits_data[57];
assign io_out_bits_data[56] = io_in_0_bits_data[56];
assign io_out_bits_data[55] = io_in_0_bits_data[55];
assign io_out_bits_data[54] = io_in_0_bits_data[54];
assign io_out_bits_data[53] = io_in_0_bits_data[53];
assign io_out_bits_data[52] = io_in_0_bits_data[52];
assign io_out_bits_data[51] = io_in_0_bits_data[51];
assign io_out_bits_data[50] = io_in_0_bits_data[50];
assign io_out_bits_data[49] = io_in_0_bits_data[49];
assign io_out_bits_data[48] = io_in_0_bits_data[48];
assign io_out_bits_data[47] = io_in_0_bits_data[47];
assign io_out_bits_data[46] = io_in_0_bits_data[46];
assign io_out_bits_data[45] = io_in_0_bits_data[45];
assign io_out_bits_data[44] = io_in_0_bits_data[44];
assign io_out_bits_data[43] = io_in_0_bits_data[43];
assign io_out_bits_data[42] = io_in_0_bits_data[42];
assign io_out_bits_data[41] = io_in_0_bits_data[41];
assign io_out_bits_data[40] = io_in_0_bits_data[40];
assign io_out_bits_data[39] = io_in_0_bits_data[39];
assign io_out_bits_data[38] = io_in_0_bits_data[38];
assign io_out_bits_data[37] = io_in_0_bits_data[37];
assign io_out_bits_data[36] = io_in_0_bits_data[36];
assign io_out_bits_data[35] = io_in_0_bits_data[35];
assign io_out_bits_data[34] = io_in_0_bits_data[34];
assign io_out_bits_data[33] = io_in_0_bits_data[33];
assign io_out_bits_data[32] = io_in_0_bits_data[32];
assign io_out_bits_data[31] = io_in_0_bits_data[31];
assign io_out_bits_data[30] = io_in_0_bits_data[30];
assign io_out_bits_data[29] = io_in_0_bits_data[29];
assign io_out_bits_data[28] = io_in_0_bits_data[28];
assign io_out_bits_data[27] = io_in_0_bits_data[27];
assign io_out_bits_data[26] = io_in_0_bits_data[26];
assign io_out_bits_data[25] = io_in_0_bits_data[25];
assign io_out_bits_data[24] = io_in_0_bits_data[24];
assign io_out_bits_data[23] = io_in_0_bits_data[23];
assign io_out_bits_data[22] = io_in_0_bits_data[22];
assign io_out_bits_data[21] = io_in_0_bits_data[21];
assign io_out_bits_data[20] = io_in_0_bits_data[20];
assign io_out_bits_data[19] = io_in_0_bits_data[19];
assign io_out_bits_data[18] = io_in_0_bits_data[18];
assign io_out_bits_data[17] = io_in_0_bits_data[17];
assign io_out_bits_data[16] = io_in_0_bits_data[16];
assign io_out_bits_data[15] = io_in_0_bits_data[15];
assign io_out_bits_data[14] = io_in_0_bits_data[14];
assign io_out_bits_data[13] = io_in_0_bits_data[13];
assign io_out_bits_data[12] = io_in_0_bits_data[12];
assign io_out_bits_data[11] = io_in_0_bits_data[11];
assign io_out_bits_data[10] = io_in_0_bits_data[10];
assign io_out_bits_data[9] = io_in_0_bits_data[9];
assign io_out_bits_data[8] = io_in_0_bits_data[8];
assign io_out_bits_data[7] = io_in_0_bits_data[7];
assign io_out_bits_data[6] = io_in_0_bits_data[6];
assign io_out_bits_data[5] = io_in_0_bits_data[5];
assign io_out_bits_data[4] = io_in_0_bits_data[4];
assign io_out_bits_data[3] = io_in_0_bits_data[3];
assign io_out_bits_data[2] = io_in_0_bits_data[2];
assign io_out_bits_data[1] = io_in_0_bits_data[1];
assign io_out_bits_data[0] = io_in_0_bits_data[0];
assign io_out_bits_nack = io_in_0_bits_nack;
assign io_out_bits_replay = io_in_0_bits_replay;
assign io_out_bits_has_data = io_in_0_bits_has_data;
assign io_out_bits_data_word_bypass[63] = io_in_0_bits_data_word_bypass[63];
assign io_out_bits_data_word_bypass[62] = io_in_0_bits_data_word_bypass[62];
assign io_out_bits_data_word_bypass[61] = io_in_0_bits_data_word_bypass[61];
assign io_out_bits_data_word_bypass[60] = io_in_0_bits_data_word_bypass[60];
assign io_out_bits_data_word_bypass[59] = io_in_0_bits_data_word_bypass[59];
assign io_out_bits_data_word_bypass[58] = io_in_0_bits_data_word_bypass[58];
assign io_out_bits_data_word_bypass[57] = io_in_0_bits_data_word_bypass[57];
assign io_out_bits_data_word_bypass[56] = io_in_0_bits_data_word_bypass[56];
assign io_out_bits_data_word_bypass[55] = io_in_0_bits_data_word_bypass[55];
assign io_out_bits_data_word_bypass[54] = io_in_0_bits_data_word_bypass[54];
assign io_out_bits_data_word_bypass[53] = io_in_0_bits_data_word_bypass[53];
assign io_out_bits_data_word_bypass[52] = io_in_0_bits_data_word_bypass[52];
assign io_out_bits_data_word_bypass[51] = io_in_0_bits_data_word_bypass[51];
assign io_out_bits_data_word_bypass[50] = io_in_0_bits_data_word_bypass[50];
assign io_out_bits_data_word_bypass[49] = io_in_0_bits_data_word_bypass[49];
assign io_out_bits_data_word_bypass[48] = io_in_0_bits_data_word_bypass[48];
assign io_out_bits_data_word_bypass[47] = io_in_0_bits_data_word_bypass[47];
assign io_out_bits_data_word_bypass[46] = io_in_0_bits_data_word_bypass[46];
assign io_out_bits_data_word_bypass[45] = io_in_0_bits_data_word_bypass[45];
assign io_out_bits_data_word_bypass[44] = io_in_0_bits_data_word_bypass[44];
assign io_out_bits_data_word_bypass[43] = io_in_0_bits_data_word_bypass[43];
assign io_out_bits_data_word_bypass[42] = io_in_0_bits_data_word_bypass[42];
assign io_out_bits_data_word_bypass[41] = io_in_0_bits_data_word_bypass[41];
assign io_out_bits_data_word_bypass[40] = io_in_0_bits_data_word_bypass[40];
assign io_out_bits_data_word_bypass[39] = io_in_0_bits_data_word_bypass[39];
assign io_out_bits_data_word_bypass[38] = io_in_0_bits_data_word_bypass[38];
assign io_out_bits_data_word_bypass[37] = io_in_0_bits_data_word_bypass[37];
assign io_out_bits_data_word_bypass[36] = io_in_0_bits_data_word_bypass[36];
assign io_out_bits_data_word_bypass[35] = io_in_0_bits_data_word_bypass[35];
assign io_out_bits_data_word_bypass[34] = io_in_0_bits_data_word_bypass[34];
assign io_out_bits_data_word_bypass[33] = io_in_0_bits_data_word_bypass[33];
assign io_out_bits_data_word_bypass[32] = io_in_0_bits_data_word_bypass[32];
assign io_out_bits_data_word_bypass[31] = io_in_0_bits_data_word_bypass[31];
assign io_out_bits_data_word_bypass[30] = io_in_0_bits_data_word_bypass[30];
assign io_out_bits_data_word_bypass[29] = io_in_0_bits_data_word_bypass[29];
assign io_out_bits_data_word_bypass[28] = io_in_0_bits_data_word_bypass[28];
assign io_out_bits_data_word_bypass[27] = io_in_0_bits_data_word_bypass[27];
assign io_out_bits_data_word_bypass[26] = io_in_0_bits_data_word_bypass[26];
assign io_out_bits_data_word_bypass[25] = io_in_0_bits_data_word_bypass[25];
assign io_out_bits_data_word_bypass[24] = io_in_0_bits_data_word_bypass[24];
assign io_out_bits_data_word_bypass[23] = io_in_0_bits_data_word_bypass[23];
assign io_out_bits_data_word_bypass[22] = io_in_0_bits_data_word_bypass[22];
assign io_out_bits_data_word_bypass[21] = io_in_0_bits_data_word_bypass[21];
assign io_out_bits_data_word_bypass[20] = io_in_0_bits_data_word_bypass[20];
assign io_out_bits_data_word_bypass[19] = io_in_0_bits_data_word_bypass[19];
assign io_out_bits_data_word_bypass[18] = io_in_0_bits_data_word_bypass[18];
assign io_out_bits_data_word_bypass[17] = io_in_0_bits_data_word_bypass[17];
assign io_out_bits_data_word_bypass[16] = io_in_0_bits_data_word_bypass[16];
assign io_out_bits_data_word_bypass[15] = io_in_0_bits_data_word_bypass[15];
assign io_out_bits_data_word_bypass[14] = io_in_0_bits_data_word_bypass[14];
assign io_out_bits_data_word_bypass[13] = io_in_0_bits_data_word_bypass[13];
assign io_out_bits_data_word_bypass[12] = io_in_0_bits_data_word_bypass[12];
assign io_out_bits_data_word_bypass[11] = io_in_0_bits_data_word_bypass[11];
assign io_out_bits_data_word_bypass[10] = io_in_0_bits_data_word_bypass[10];
assign io_out_bits_data_word_bypass[9] = io_in_0_bits_data_word_bypass[9];
assign io_out_bits_data_word_bypass[8] = io_in_0_bits_data_word_bypass[8];
assign io_out_bits_data_word_bypass[7] = io_in_0_bits_data_word_bypass[7];
assign io_out_bits_data_word_bypass[6] = io_in_0_bits_data_word_bypass[6];
assign io_out_bits_data_word_bypass[5] = io_in_0_bits_data_word_bypass[5];
assign io_out_bits_data_word_bypass[4] = io_in_0_bits_data_word_bypass[4];
assign io_out_bits_data_word_bypass[3] = io_in_0_bits_data_word_bypass[3];
assign io_out_bits_data_word_bypass[2] = io_in_0_bits_data_word_bypass[2];
assign io_out_bits_data_word_bypass[1] = io_in_0_bits_data_word_bypass[1];
assign io_out_bits_data_word_bypass[0] = io_in_0_bits_data_word_bypass[0];
assign io_out_bits_store_data[63] = io_in_0_bits_store_data[63];
assign io_out_bits_store_data[62] = io_in_0_bits_store_data[62];
assign io_out_bits_store_data[61] = io_in_0_bits_store_data[61];
assign io_out_bits_store_data[60] = io_in_0_bits_store_data[60];
assign io_out_bits_store_data[59] = io_in_0_bits_store_data[59];
assign io_out_bits_store_data[58] = io_in_0_bits_store_data[58];
assign io_out_bits_store_data[57] = io_in_0_bits_store_data[57];
assign io_out_bits_store_data[56] = io_in_0_bits_store_data[56];
assign io_out_bits_store_data[55] = io_in_0_bits_store_data[55];
assign io_out_bits_store_data[54] = io_in_0_bits_store_data[54];
assign io_out_bits_store_data[53] = io_in_0_bits_store_data[53];
assign io_out_bits_store_data[52] = io_in_0_bits_store_data[52];
assign io_out_bits_store_data[51] = io_in_0_bits_store_data[51];
assign io_out_bits_store_data[50] = io_in_0_bits_store_data[50];
assign io_out_bits_store_data[49] = io_in_0_bits_store_data[49];
assign io_out_bits_store_data[48] = io_in_0_bits_store_data[48];
assign io_out_bits_store_data[47] = io_in_0_bits_store_data[47];
assign io_out_bits_store_data[46] = io_in_0_bits_store_data[46];
assign io_out_bits_store_data[45] = io_in_0_bits_store_data[45];
assign io_out_bits_store_data[44] = io_in_0_bits_store_data[44];
assign io_out_bits_store_data[43] = io_in_0_bits_store_data[43];
assign io_out_bits_store_data[42] = io_in_0_bits_store_data[42];
assign io_out_bits_store_data[41] = io_in_0_bits_store_data[41];
assign io_out_bits_store_data[40] = io_in_0_bits_store_data[40];
assign io_out_bits_store_data[39] = io_in_0_bits_store_data[39];
assign io_out_bits_store_data[38] = io_in_0_bits_store_data[38];
assign io_out_bits_store_data[37] = io_in_0_bits_store_data[37];
assign io_out_bits_store_data[36] = io_in_0_bits_store_data[36];
assign io_out_bits_store_data[35] = io_in_0_bits_store_data[35];
assign io_out_bits_store_data[34] = io_in_0_bits_store_data[34];
assign io_out_bits_store_data[33] = io_in_0_bits_store_data[33];
assign io_out_bits_store_data[32] = io_in_0_bits_store_data[32];
assign io_out_bits_store_data[31] = io_in_0_bits_store_data[31];
assign io_out_bits_store_data[30] = io_in_0_bits_store_data[30];
assign io_out_bits_store_data[29] = io_in_0_bits_store_data[29];
assign io_out_bits_store_data[28] = io_in_0_bits_store_data[28];
assign io_out_bits_store_data[27] = io_in_0_bits_store_data[27];
assign io_out_bits_store_data[26] = io_in_0_bits_store_data[26];
assign io_out_bits_store_data[25] = io_in_0_bits_store_data[25];
assign io_out_bits_store_data[24] = io_in_0_bits_store_data[24];
assign io_out_bits_store_data[23] = io_in_0_bits_store_data[23];
assign io_out_bits_store_data[22] = io_in_0_bits_store_data[22];
assign io_out_bits_store_data[21] = io_in_0_bits_store_data[21];
assign io_out_bits_store_data[20] = io_in_0_bits_store_data[20];
assign io_out_bits_store_data[19] = io_in_0_bits_store_data[19];
assign io_out_bits_store_data[18] = io_in_0_bits_store_data[18];
assign io_out_bits_store_data[17] = io_in_0_bits_store_data[17];
assign io_out_bits_store_data[16] = io_in_0_bits_store_data[16];
assign io_out_bits_store_data[15] = io_in_0_bits_store_data[15];
assign io_out_bits_store_data[14] = io_in_0_bits_store_data[14];
assign io_out_bits_store_data[13] = io_in_0_bits_store_data[13];
assign io_out_bits_store_data[12] = io_in_0_bits_store_data[12];
assign io_out_bits_store_data[11] = io_in_0_bits_store_data[11];
assign io_out_bits_store_data[10] = io_in_0_bits_store_data[10];
assign io_out_bits_store_data[9] = io_in_0_bits_store_data[9];
assign io_out_bits_store_data[8] = io_in_0_bits_store_data[8];
assign io_out_bits_store_data[7] = io_in_0_bits_store_data[7];
assign io_out_bits_store_data[6] = io_in_0_bits_store_data[6];
assign io_out_bits_store_data[5] = io_in_0_bits_store_data[5];
assign io_out_bits_store_data[4] = io_in_0_bits_store_data[4];
assign io_out_bits_store_data[3] = io_in_0_bits_store_data[3];
assign io_out_bits_store_data[2] = io_in_0_bits_store_data[2];
assign io_out_bits_store_data[1] = io_in_0_bits_store_data[1];
assign io_out_bits_store_data[0] = io_in_0_bits_store_data[0];
endmodule |
module RRArbiter_3
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr,
io_in_1_bits_prv,
io_in_1_bits_store,
io_in_1_bits_fetch,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_prv,
io_in_0_bits_store,
io_in_0_bits_fetch,
io_out_ready,
io_out_valid,
io_out_bits_addr,
io_out_bits_prv,
io_out_bits_store,
io_out_bits_fetch,
io_chosen
);
input [26:0] io_in_1_bits_addr;
input [1:0] io_in_1_bits_prv;
input [26:0] io_in_0_bits_addr;
input [1:0] io_in_0_bits_prv;
output [26:0] io_out_bits_addr;
output [1:0] io_out_bits_prv;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_store;
input io_in_1_bits_fetch;
input io_in_0_valid;
input io_in_0_bits_store;
input io_in_0_bits_fetch;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_store;
output io_out_bits_fetch;
output io_chosen;
wire [26:0] io_out_bits_addr;
wire [1:0] io_out_bits_prv;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_store,io_out_bits_fetch,
io_chosen,N0,N1,N2,N3,N4,N5,N6,T1,N7,T2,T4,N8,T12,T19,T13,T14,T17,T15,T16,T18,T21,
T25,T22,T23,T24,T27,T26,N9,N10,N11,N12,N13,N14,N15;
reg last_grant;
assign T18 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T19 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N11) begin
last_grant <= N12;
end
end
assign N15 = ~io_in_0_valid;
assign io_chosen = (N2)? 1'b1 :
(N3)? N15 : 1'b0;
assign N2 = T1;
assign N3 = N7;
assign io_out_bits_fetch = (N4)? io_in_1_bits_fetch :
(N5)? io_in_0_bits_fetch : 1'b0;
assign N4 = io_chosen;
assign N5 = N8;
assign io_out_bits_store = (N4)? io_in_1_bits_store :
(N5)? io_in_0_bits_store : 1'b0;
assign io_out_bits_prv = (N4)? io_in_1_bits_prv :
(N5)? io_in_0_bits_prv : 1'b0;
assign io_out_bits_addr = (N4)? io_in_1_bits_addr :
(N5)? io_in_0_bits_addr : 1'b0;
assign io_out_valid = (N4)? io_in_1_valid :
(N5)? io_in_0_valid : 1'b0;
assign N11 = (N6)? 1'b1 :
(N14)? 1'b1 :
(N10)? 1'b0 : 1'b0;
assign N6 = reset;
assign N12 = (N6)? 1'b0 :
(N14)? io_chosen : 1'b0;
assign N7 = ~T1;
assign T1 = io_in_1_valid & T2;
assign T2 = ~last_grant;
assign T4 = io_out_ready & io_out_valid;
assign N8 = ~io_chosen;
assign io_in_0_ready = T12 & io_out_ready;
assign T12 = T19 | T13;
assign T13 = ~T14;
assign T14 = T17 | T15;
assign T15 = io_in_1_valid & T16;
assign T16 = ~last_grant;
assign T17 = io_in_0_valid & T18;
assign io_in_1_ready = T21 & io_out_ready;
assign T21 = T25 | T22;
assign T22 = ~T23;
assign T23 = T24 | io_in_0_valid;
assign T24 = T17 | T15;
assign T25 = T27 & T26;
assign T26 = ~last_grant;
assign T27 = ~T17;
assign N9 = T4 | reset;
assign N10 = ~N9;
assign N13 = ~reset;
assign N14 = T4 & N13;
endmodule |
module RecFNToRecFN
(
io_in,
io_roundingMode,
io_out,
io_exceptionFlags
);
input [32:0] io_in;
input [1:0] io_roundingMode;
output [64:0] io_out;
output [4:0] io_exceptionFlags;
wire [64:0] io_out;
wire [4:0] io_exceptionFlags;
wire N0,N1,outRawFloat_isNaN,T1,N2,outRawFloat_isInf,T24,T29,T42,N3,N4,N5,N6;
wire [11:0] T20,T26,T33,T27,T36,T34;
wire [11:11] T19,T21,T35,T46;
wire [9:9] T28;
assign io_out[28] = 1'b0;
assign io_out[27] = 1'b0;
assign io_out[26] = 1'b0;
assign io_out[25] = 1'b0;
assign io_out[24] = 1'b0;
assign io_out[23] = 1'b0;
assign io_out[22] = 1'b0;
assign io_out[21] = 1'b0;
assign io_out[20] = 1'b0;
assign io_out[19] = 1'b0;
assign io_out[18] = 1'b0;
assign io_out[17] = 1'b0;
assign io_out[16] = 1'b0;
assign io_out[15] = 1'b0;
assign io_out[14] = 1'b0;
assign io_out[13] = 1'b0;
assign io_out[12] = 1'b0;
assign io_out[11] = 1'b0;
assign io_out[10] = 1'b0;
assign io_out[9] = 1'b0;
assign io_out[8] = 1'b0;
assign io_out[7] = 1'b0;
assign io_out[6] = 1'b0;
assign io_out[5] = 1'b0;
assign io_out[4] = 1'b0;
assign io_out[3] = 1'b0;
assign io_out[2] = 1'b0;
assign io_out[1] = 1'b0;
assign io_out[0] = 1'b0;
assign io_exceptionFlags[0] = 1'b0;
assign io_exceptionFlags[1] = 1'b0;
assign io_exceptionFlags[2] = 1'b0;
assign io_exceptionFlags[3] = 1'b0;
assign N3 = io_in[30] | io_in[31];
assign N4 = io_in[29] | N3;
assign N5 = ~N4;
assign N6 = io_in[30] & io_in[31];
assign T36 = { T46[11:11], T46[11:11], 1'b0, io_in[31:23] } + { 1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
assign io_out[51:29] = (N0)? { 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? io_in[22:0] : 1'b0;
assign N0 = outRawFloat_isNaN;
assign N1 = N2;
assign io_exceptionFlags[4] = outRawFloat_isNaN & T1;
assign T1 = ~io_in[22];
assign outRawFloat_isNaN = N6 & io_in[29];
assign N2 = ~outRawFloat_isNaN;
assign io_out[63] = T20[11] | T19[11];
assign io_out[62] = T20[10] | T19[11];
assign io_out[61] = T20[9] | T19[11];
assign io_out[60] = T20[8] | 1'b0;
assign io_out[59] = T20[7] | 1'b0;
assign io_out[58] = T20[6] | 1'b0;
assign io_out[57] = T20[5] | 1'b0;
assign io_out[56] = T20[4] | 1'b0;
assign io_out[55] = T20[3] | 1'b0;
assign io_out[54] = T20[2] | 1'b0;
assign io_out[53] = T20[1] | 1'b0;
assign io_out[52] = T20[0] | 1'b0;
assign T19[11] = outRawFloat_isNaN;
assign T20[11] = T26[11] | T21[11];
assign T20[10] = T26[10] | T21[11];
assign T20[9] = T26[9] | 1'b0;
assign T20[8] = T26[8] | 1'b0;
assign T20[7] = T26[7] | 1'b0;
assign T20[6] = T26[6] | 1'b0;
assign T20[5] = T26[5] | 1'b0;
assign T20[4] = T26[4] | 1'b0;
assign T20[3] = T26[3] | 1'b0;
assign T20[2] = T26[2] | 1'b0;
assign T20[1] = T26[1] | 1'b0;
assign T20[0] = T26[0] | 1'b0;
assign T21[11] = outRawFloat_isInf;
assign outRawFloat_isInf = N6 & T24;
assign T24 = ~io_in[29];
assign T26[11] = T33[11] & T27[11];
assign T26[10] = T33[10] & T27[10];
assign T26[9] = T33[9] & T27[9];
assign T26[8] = T33[8] & T27[8];
assign T26[7] = T33[7] & T27[7];
assign T26[6] = T33[6] & T27[6];
assign T26[5] = T33[5] & T27[5];
assign T26[4] = T33[4] & T27[4];
assign T26[3] = T33[3] & T27[3];
assign T26[2] = T33[2] & T27[2];
assign T26[1] = T33[1] & T27[1];
assign T26[0] = T33[0] & T27[0];
assign T27[11] = ~1'b0;
assign T27[10] = ~1'b0;
assign T27[9] = ~T28[9];
assign T27[8] = ~1'b0;
assign T27[7] = ~1'b0;
assign T27[6] = ~1'b0;
assign T27[5] = ~1'b0;
assign T27[4] = ~1'b0;
assign T27[3] = ~1'b0;
assign T27[2] = ~1'b0;
assign T27[1] = ~1'b0;
assign T27[0] = ~1'b0;
assign T28[9] = T29;
assign T29 = N5 | outRawFloat_isInf;
assign T33[11] = T36[11] & T34[11];
assign T33[10] = T36[10] & T34[10];
assign T33[9] = T36[9] & T34[9];
assign T33[8] = T36[8] & T34[8];
assign T33[7] = T36[7] & T34[7];
assign T33[6] = T36[6] & T34[6];
assign T33[5] = T36[5] & T34[5];
assign T33[4] = T36[4] & T34[4];
assign T33[3] = T36[3] & T34[3];
assign T33[2] = T36[2] & T34[2];
assign T33[1] = T36[1] & T34[1];
assign T33[0] = T36[0] & T34[0];
assign T34[11] = ~T35[11];
assign T34[10] = ~T35[11];
assign T34[9] = ~1'b0;
assign T34[8] = ~1'b0;
assign T34[7] = ~1'b0;
assign T34[6] = ~1'b0;
assign T34[5] = ~1'b0;
assign T34[4] = ~1'b0;
assign T34[3] = ~1'b0;
assign T34[2] = ~1'b0;
assign T34[1] = ~1'b0;
assign T34[0] = ~1'b0;
assign T35[11] = N5;
assign T46[11] = 1'b0;
assign io_out[64] = io_in[32] & T42;
assign T42 = ~outRawFloat_isNaN;
endmodule |
module RecFNToIN_0
(
io_in,
io_roundingMode,
io_signedOut,
io_out,
io_intExceptionFlags
);
input [64:0] io_in;
input [1:0] io_roundingMode;
output [63:0] io_out;
output [2:0] io_intExceptionFlags;
input io_signedOut;
wire [63:0] io_out,excValue,roundedInt,T62,onesCompUnroundedInt,T61,T66;
wire [2:0] io_intExceptionFlags;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,T3,T2,roundInexact,T4,T5,N12,
overflow_signed,overflow_unsigned,T36,T15,roundIncr,T20,T16,T17,T18,T24,T21,T22,
roundIncr_nearestEven,T30,T25,N13,T33,T43,T37,T40,roundCarryBut2,T38,T44,N14,T45,T50,T46,T47,
T49,T58,T51,T52,T53,T56,T54,T74,N15,T63,N16,N17,T65,T68,T69,excSign,T70,isNaN,
T73,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,
N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,
N58,N59,N60,N61,N62,N63,N64,N65;
wire [0:0] T8;
wire [50:0] T10;
wire [115:51] shiftedSig;
wire [5:0] T11;
wire [63:63] T64,T72;
wire [62:62] T75;
assign T8[0] = T10 != 1'b0;
assign { shiftedSig, T10 } = { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, io_in[63:63], io_in[51:0] } << T11;
assign T33 = shiftedSig[52:51] == { 1'b1, 1'b1 };
assign T38 = shiftedSig[113:52] == { 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1 };
assign T54 = shiftedSig[114:52] != 1'b0;
assign N18 = ~io_in[57];
assign N19 = ~io_in[56];
assign N20 = ~io_in[55];
assign N21 = ~io_in[54];
assign N22 = ~io_in[53];
assign N23 = ~io_in[52];
assign N24 = io_in[61] | io_in[62];
assign N25 = io_in[60] | N24;
assign N26 = io_in[59] | N25;
assign N27 = io_in[58] | N26;
assign N28 = N18 | N27;
assign N29 = N19 | N28;
assign N30 = N20 | N29;
assign N31 = N21 | N30;
assign N32 = N22 | N31;
assign N33 = N23 | N32;
assign N34 = ~N33;
assign N35 = io_in[52] | N32;
assign N36 = ~N35;
assign io_intExceptionFlags[2] = io_in[62] & io_in[63];
assign N38 = io_roundingMode[0] & io_roundingMode[1];
assign N39 = io_roundingMode[0] | io_roundingMode[1];
assign N40 = ~N39;
assign N41 = ~io_roundingMode[1];
assign N42 = io_roundingMode[0] | N41;
assign N43 = ~N42;
assign N44 = T8[0] & shiftedSig[51];
assign N45 = T8[0] | shiftedSig[51];
assign N46 = T8[0] | shiftedSig[51];
assign N47 = io_in[62] | io_in[63];
assign N48 = io_in[61] | N47;
assign N49 = ~N48;
assign N50 = io_in[61] & io_in[62];
assign N51 = io_in[60] & N50;
assign N52 = io_in[59] & N51;
assign N53 = io_in[58] & N52;
assign N54 = io_in[57] & N53;
assign N55 = io_in[56] & N54;
assign N56 = io_in[55] & N55;
assign N57 = io_in[54] & N56;
assign N58 = io_in[53] & N57;
assign N59 = io_in[52] & N58;
assign T62 = onesCompUnroundedInt + 1'b1;
assign roundInexact = (N0)? N46 :
(N1)? T5 : 1'b0;
assign N0 = io_in[63];
assign N1 = N14;
assign T11 = (N0)? io_in[57:52] :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign io_intExceptionFlags[1] = (N2)? overflow_signed :
(N3)? overflow_unsigned : 1'b0;
assign N2 = io_signedOut;
assign N3 = N12;
assign overflow_unsigned = (N0)? T36 :
(N1)? T15 : 1'b0;
assign roundIncr_nearestEven = (N0)? T30 :
(N1)? T25 : 1'b0;
assign T25 = (N4)? N45 :
(N5)? 1'b0 : 1'b0;
assign N4 = N59;
assign N5 = N13;
assign overflow_signed = (N0)? T45 :
(N1)? 1'b0 : 1'b0;
assign io_out = (N6)? excValue :
(N7)? roundedInt : 1'b0;
assign N6 = T74;
assign N7 = N15;
assign roundedInt = (N8)? T62 :
(N9)? onesCompUnroundedInt : 1'b0;
assign N8 = T63;
assign N9 = N16;
assign onesCompUnroundedInt = (N10)? T61 :
(N11)? shiftedSig[115:52] : 1'b0;
assign N10 = io_in[64];
assign N11 = N17;
assign io_intExceptionFlags[0] = T3 & T2;
assign T2 = ~io_intExceptionFlags[1];
assign T3 = roundInexact & T4;
assign T4 = ~io_intExceptionFlags[2];
assign T5 = ~N49;
assign N12 = ~io_signedOut;
assign T15 = io_in[64] & roundIncr;
assign roundIncr = T20 | T16;
assign T16 = N38 & T17;
assign T17 = T18 & roundInexact;
assign T18 = ~io_in[64];
assign T20 = T24 | T21;
assign T21 = N43 & T22;
assign T22 = io_in[64] & roundInexact;
assign T24 = N40 & roundIncr_nearestEven;
assign N13 = ~N59;
assign T30 = T33 | N44;
assign T36 = T43 | T37;
assign T37 = T40 & roundCarryBut2;
assign roundCarryBut2 = T38 & roundIncr;
assign T40 = N34 & shiftedSig[114];
assign T43 = io_in[64] | T44;
assign T44 = N62 | io_in[58];
assign N62 = N61 | io_in[59];
assign N61 = N60 | io_in[60];
assign N60 = io_in[62] | io_in[61];
assign N14 = ~io_in[63];
assign T45 = T50 | T46;
assign T46 = T47 & roundCarryBut2;
assign T47 = T49 & N36;
assign T49 = ~io_in[64];
assign T50 = T58 | T51;
assign T51 = N34 & T52;
assign T52 = T53 | roundIncr;
assign T53 = T56 | T54;
assign T56 = ~io_in[64];
assign T58 = N65 | io_in[58];
assign N65 = N64 | io_in[59];
assign N64 = N63 | io_in[60];
assign N63 = io_in[62] | io_in[61];
assign N15 = ~T74;
assign N16 = ~T63;
assign N17 = ~io_in[64];
assign T61[63] = ~shiftedSig[115];
assign T61[62] = ~shiftedSig[114];
assign T61[61] = ~shiftedSig[113];
assign T61[60] = ~shiftedSig[112];
assign T61[59] = ~shiftedSig[111];
assign T61[58] = ~shiftedSig[110];
assign T61[57] = ~shiftedSig[109];
assign T61[56] = ~shiftedSig[108];
assign T61[55] = ~shiftedSig[107];
assign T61[54] = ~shiftedSig[106];
assign T61[53] = ~shiftedSig[105];
assign T61[52] = ~shiftedSig[104];
assign T61[51] = ~shiftedSig[103];
assign T61[50] = ~shiftedSig[102];
assign T61[49] = ~shiftedSig[101];
assign T61[48] = ~shiftedSig[100];
assign T61[47] = ~shiftedSig[99];
assign T61[46] = ~shiftedSig[98];
assign T61[45] = ~shiftedSig[97];
assign T61[44] = ~shiftedSig[96];
assign T61[43] = ~shiftedSig[95];
assign T61[42] = ~shiftedSig[94];
assign T61[41] = ~shiftedSig[93];
assign T61[40] = ~shiftedSig[92];
assign T61[39] = ~shiftedSig[91];
assign T61[38] = ~shiftedSig[90];
assign T61[37] = ~shiftedSig[89];
assign T61[36] = ~shiftedSig[88];
assign T61[35] = ~shiftedSig[87];
assign T61[34] = ~shiftedSig[86];
assign T61[33] = ~shiftedSig[85];
assign T61[32] = ~shiftedSig[84];
assign T61[31] = ~shiftedSig[83];
assign T61[30] = ~shiftedSig[82];
assign T61[29] = ~shiftedSig[81];
assign T61[28] = ~shiftedSig[80];
assign T61[27] = ~shiftedSig[79];
assign T61[26] = ~shiftedSig[78];
assign T61[25] = ~shiftedSig[77];
assign T61[24] = ~shiftedSig[76];
assign T61[23] = ~shiftedSig[75];
assign T61[22] = ~shiftedSig[74];
assign T61[21] = ~shiftedSig[73];
assign T61[20] = ~shiftedSig[72];
assign T61[19] = ~shiftedSig[71];
assign T61[18] = ~shiftedSig[70];
assign T61[17] = ~shiftedSig[69];
assign T61[16] = ~shiftedSig[68];
assign T61[15] = ~shiftedSig[67];
assign T61[14] = ~shiftedSig[66];
assign T61[13] = ~shiftedSig[65];
assign T61[12] = ~shiftedSig[64];
assign T61[11] = ~shiftedSig[63];
assign T61[10] = ~shiftedSig[62];
assign T61[9] = ~shiftedSig[61];
assign T61[8] = ~shiftedSig[60];
assign T61[7] = ~shiftedSig[59];
assign T61[6] = ~shiftedSig[58];
assign T61[5] = ~shiftedSig[57];
assign T61[4] = ~shiftedSig[56];
assign T61[3] = ~shiftedSig[55];
assign T61[2] = ~shiftedSig[54];
assign T61[1] = ~shiftedSig[53];
assign T61[0] = ~shiftedSig[52];
assign T63 = roundIncr ^ io_in[64];
assign excValue[63] = T66[63] | T64[63];
assign excValue[62] = T66[62] | T64[63];
assign excValue[61] = T66[61] | T64[63];
assign excValue[60] = T66[60] | T64[63];
assign excValue[59] = T66[59] | T64[63];
assign excValue[58] = T66[58] | T64[63];
assign excValue[57] = T66[57] | T64[63];
assign excValue[56] = T66[56] | T64[63];
assign excValue[55] = T66[55] | T64[63];
assign excValue[54] = T66[54] | T64[63];
assign excValue[53] = T66[53] | T64[63];
assign excValue[52] = T66[52] | T64[63];
assign excValue[51] = T66[51] | T64[63];
assign excValue[50] = T66[50] | T64[63];
assign excValue[49] = T66[49] | T64[63];
assign excValue[48] = T66[48] | T64[63];
assign excValue[47] = T66[47] | T64[63];
assign excValue[46] = T66[46] | T64[63];
assign excValue[45] = T66[45] | T64[63];
assign excValue[44] = T66[44] | T64[63];
assign excValue[43] = T66[43] | T64[63];
assign excValue[42] = T66[42] | T64[63];
assign excValue[41] = T66[41] | T64[63];
assign excValue[40] = T66[40] | T64[63];
assign excValue[39] = T66[39] | T64[63];
assign excValue[38] = T66[38] | T64[63];
assign excValue[37] = T66[37] | T64[63];
assign excValue[36] = T66[36] | T64[63];
assign excValue[35] = T66[35] | T64[63];
assign excValue[34] = T66[34] | T64[63];
assign excValue[33] = T66[33] | T64[63];
assign excValue[32] = T66[32] | T64[63];
assign excValue[31] = T66[31] | T64[63];
assign excValue[30] = T66[30] | T64[63];
assign excValue[29] = T66[29] | T64[63];
assign excValue[28] = T66[28] | T64[63];
assign excValue[27] = T66[27] | T64[63];
assign excValue[26] = T66[26] | T64[63];
assign excValue[25] = T66[25] | T64[63];
assign excValue[24] = T66[24] | T64[63];
assign excValue[23] = T66[23] | T64[63];
assign excValue[22] = T66[22] | T64[63];
assign excValue[21] = T66[21] | T64[63];
assign excValue[20] = T66[20] | T64[63];
assign excValue[19] = T66[19] | T64[63];
assign excValue[18] = T66[18] | T64[63];
assign excValue[17] = T66[17] | T64[63];
assign excValue[16] = T66[16] | T64[63];
assign excValue[15] = T66[15] | T64[63];
assign excValue[14] = T66[14] | T64[63];
assign excValue[13] = T66[13] | T64[63];
assign excValue[12] = T66[12] | T64[63];
assign excValue[11] = T66[11] | T64[63];
assign excValue[10] = T66[10] | T64[63];
assign excValue[9] = T66[9] | T64[63];
assign excValue[8] = T66[8] | T64[63];
assign excValue[7] = T66[7] | T64[63];
assign excValue[6] = T66[6] | T64[63];
assign excValue[5] = T66[5] | T64[63];
assign excValue[4] = T66[4] | T64[63];
assign excValue[3] = T66[3] | T64[63];
assign excValue[2] = T66[2] | T64[63];
assign excValue[1] = T66[1] | T64[63];
assign excValue[0] = T66[0] | T64[63];
assign T64[63] = T65;
assign T65 = ~io_signedOut;
assign T66[63] = T72[63] | 1'b0;
assign T66[62] = 1'b0 | T75[62];
assign T66[61] = 1'b0 | T75[62];
assign T66[60] = 1'b0 | T75[62];
assign T66[59] = 1'b0 | T75[62];
assign T66[58] = 1'b0 | T75[62];
assign T66[57] = 1'b0 | T75[62];
assign T66[56] = 1'b0 | T75[62];
assign T66[55] = 1'b0 | T75[62];
assign T66[54] = 1'b0 | T75[62];
assign T66[53] = 1'b0 | T75[62];
assign T66[52] = 1'b0 | T75[62];
assign T66[51] = 1'b0 | T75[62];
assign T66[50] = 1'b0 | T75[62];
assign T66[49] = 1'b0 | T75[62];
assign T66[48] = 1'b0 | T75[62];
assign T66[47] = 1'b0 | T75[62];
assign T66[46] = 1'b0 | T75[62];
assign T66[45] = 1'b0 | T75[62];
assign T66[44] = 1'b0 | T75[62];
assign T66[43] = 1'b0 | T75[62];
assign T66[42] = 1'b0 | T75[62];
assign T66[41] = 1'b0 | T75[62];
assign T66[40] = 1'b0 | T75[62];
assign T66[39] = 1'b0 | T75[62];
assign T66[38] = 1'b0 | T75[62];
assign T66[37] = 1'b0 | T75[62];
assign T66[36] = 1'b0 | T75[62];
assign T66[35] = 1'b0 | T75[62];
assign T66[34] = 1'b0 | T75[62];
assign T66[33] = 1'b0 | T75[62];
assign T66[32] = 1'b0 | T75[62];
assign T66[31] = 1'b0 | T75[62];
assign T66[30] = 1'b0 | T75[62];
assign T66[29] = 1'b0 | T75[62];
assign T66[28] = 1'b0 | T75[62];
assign T66[27] = 1'b0 | T75[62];
assign T66[26] = 1'b0 | T75[62];
assign T66[25] = 1'b0 | T75[62];
assign T66[24] = 1'b0 | T75[62];
assign T66[23] = 1'b0 | T75[62];
assign T66[22] = 1'b0 | T75[62];
assign T66[21] = 1'b0 | T75[62];
assign T66[20] = 1'b0 | T75[62];
assign T66[19] = 1'b0 | T75[62];
assign T66[18] = 1'b0 | T75[62];
assign T66[17] = 1'b0 | T75[62];
assign T66[16] = 1'b0 | T75[62];
assign T66[15] = 1'b0 | T75[62];
assign T66[14] = 1'b0 | T75[62];
assign T66[13] = 1'b0 | T75[62];
assign T66[12] = 1'b0 | T75[62];
assign T66[11] = 1'b0 | T75[62];
assign T66[10] = 1'b0 | T75[62];
assign T66[9] = 1'b0 | T75[62];
assign T66[8] = 1'b0 | T75[62];
assign T66[7] = 1'b0 | T75[62];
assign T66[6] = 1'b0 | T75[62];
assign T66[5] = 1'b0 | T75[62];
assign T66[4] = 1'b0 | T75[62];
assign T66[3] = 1'b0 | T75[62];
assign T66[2] = 1'b0 | T75[62];
assign T66[1] = 1'b0 | T75[62];
assign T66[0] = 1'b0 | T75[62];
assign T75[62] = T68;
assign T68 = io_signedOut & T69;
assign T69 = ~excSign;
assign excSign = io_in[64] & T70;
assign T70 = ~isNaN;
assign isNaN = io_intExceptionFlags[2] & io_in[61];
assign T72[63] = T73;
assign T73 = io_signedOut & excSign;
assign T74 = io_intExceptionFlags[2] | io_intExceptionFlags[1];
endmodule |
module Queue_16
(
clk,
reset,
io_enq_ready,
io_enq_valid,
io_enq_bits_header_src,
io_enq_bits_header_dst,
io_enq_bits_payload_manager_xact_id,
io_deq_ready,
io_deq_valid,
io_deq_bits_header_src,
io_deq_bits_header_dst,
io_deq_bits_payload_manager_xact_id,
io_count
);
input [2:0] io_enq_bits_header_src;
input [2:0] io_enq_bits_header_dst;
input [3:0] io_enq_bits_payload_manager_xact_id;
output [2:0] io_deq_bits_header_src;
output [2:0] io_deq_bits_header_dst;
output [3:0] io_deq_bits_payload_manager_xact_id;
output [1:0] io_count;
input clk;
input reset;
input io_enq_valid;
input io_deq_ready;
output io_enq_ready;
output io_deq_valid;
wire [2:0] io_deq_bits_header_src,io_deq_bits_header_dst;
wire [3:0] io_deq_bits_payload_manager_xact_id;
wire [1:0] io_count;
wire io_enq_ready,io_deq_valid,N0,N1,N2,N3,N4,do_deq,T3,do_enq,T6,ptr_match,T9,N5,
empty,T19,full,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N21,N22,N23,N24,
N25,N26;
reg R1,N20,maybe_full;
reg [19:0] ram;
assign N0 = N20 ^ R1;
assign ptr_match = ~N0;
assign T9 = do_enq ^ do_deq;
assign io_deq_bits_header_src[2] = (N5)? ram[9] :
(N1)? ram[19] : 1'b0;
assign N1 = R1;
assign io_deq_bits_header_src[1] = (N5)? ram[8] :
(N1)? ram[18] : 1'b0;
assign io_deq_bits_header_src[0] = (N5)? ram[7] :
(N1)? ram[17] : 1'b0;
assign io_deq_bits_header_dst[2] = (N5)? ram[6] :
(N1)? ram[16] : 1'b0;
assign io_deq_bits_header_dst[1] = (N5)? ram[5] :
(N1)? ram[15] : 1'b0;
assign io_deq_bits_header_dst[0] = (N5)? ram[4] :
(N1)? ram[14] : 1'b0;
assign io_deq_bits_payload_manager_xact_id[3] = (N5)? ram[3] :
(N1)? ram[13] : 1'b0;
assign io_deq_bits_payload_manager_xact_id[2] = (N5)? ram[2] :
(N1)? ram[12] : 1'b0;
assign io_deq_bits_payload_manager_xact_id[1] = (N5)? ram[1] :
(N1)? ram[11] : 1'b0;
assign io_deq_bits_payload_manager_xact_id[0] = (N5)? ram[0] :
(N1)? ram[10] : 1'b0;
always @(posedge clk) begin
if(N8) begin
R1 <= N9;
end
end
always @(posedge clk) begin
if(N12) begin
N20 <= N13;
end
end
always @(posedge clk) begin
if(N16) begin
maybe_full <= N17;
end
end
always @(posedge clk) begin
if(N22) begin
ram[19] <= io_enq_bits_header_src[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[18] <= io_enq_bits_header_src[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[17] <= io_enq_bits_header_src[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[16] <= io_enq_bits_header_dst[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[15] <= io_enq_bits_header_dst[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[14] <= io_enq_bits_header_dst[0];
end
end
always @(posedge clk) begin
if(N22) begin
ram[13] <= io_enq_bits_payload_manager_xact_id[3];
end
end
always @(posedge clk) begin
if(N22) begin
ram[12] <= io_enq_bits_payload_manager_xact_id[2];
end
end
always @(posedge clk) begin
if(N22) begin
ram[11] <= io_enq_bits_payload_manager_xact_id[1];
end
end
always @(posedge clk) begin
if(N22) begin
ram[10] <= io_enq_bits_payload_manager_xact_id[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[9] <= io_enq_bits_header_src[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[8] <= io_enq_bits_header_src[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[7] <= io_enq_bits_header_src[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[6] <= io_enq_bits_header_dst[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[5] <= io_enq_bits_header_dst[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[4] <= io_enq_bits_header_dst[0];
end
end
always @(posedge clk) begin
if(N21) begin
ram[3] <= io_enq_bits_payload_manager_xact_id[3];
end
end
always @(posedge clk) begin
if(N21) begin
ram[2] <= io_enq_bits_payload_manager_xact_id[2];
end
end
always @(posedge clk) begin
if(N21) begin
ram[1] <= io_enq_bits_payload_manager_xact_id[1];
end
end
always @(posedge clk) begin
if(N21) begin
ram[0] <= io_enq_bits_payload_manager_xact_id[0];
end
end
assign io_count[0] = N20 ^ R1;
assign T3 = R1 ^ 1'b1;
assign T6 = N20 ^ 1'b1;
assign N19 = ~N20;
assign N8 = (N2)? 1'b1 :
(N24)? 1'b1 :
(N7)? 1'b0 : 1'b0;
assign N2 = reset;
assign N9 = (N2)? 1'b0 :
(N24)? T3 : 1'b0;
assign N12 = (N2)? 1'b1 :
(N25)? 1'b1 :
(N11)? 1'b0 : 1'b0;
assign N13 = (N2)? 1'b0 :
(N25)? T6 : 1'b0;
assign N16 = (N2)? 1'b1 :
(N26)? 1'b1 :
(N15)? 1'b0 : 1'b0;
assign N17 = (N2)? 1'b0 :
(N26)? do_enq : 1'b0;
assign { N22, N21 } = (N3)? { N20, N19 } :
(N4)? { 1'b0, 1'b0 } : 1'b0;
assign N3 = do_enq;
assign N4 = N18;
assign do_deq = io_deq_ready & io_deq_valid;
assign do_enq = io_enq_ready & io_enq_valid;
assign io_count[1] = maybe_full & ptr_match;
assign N5 = ~R1;
assign io_deq_valid = ~empty;
assign empty = ptr_match & T19;
assign T19 = ~maybe_full;
assign io_enq_ready = ~full;
assign full = ptr_match & maybe_full;
assign N6 = do_deq | reset;
assign N7 = ~N6;
assign N10 = do_enq | reset;
assign N11 = ~N10;
assign N14 = T9 | reset;
assign N15 = ~N14;
assign N18 = ~do_enq;
assign N23 = ~reset;
assign N24 = do_deq & N23;
assign N25 = do_enq & N23;
assign N26 = T9 & N23;
endmodule |
module RRArbiter_5
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_addr,
io_in_1_bits_len,
io_in_1_bits_size,
io_in_1_bits_burst,
io_in_1_bits_lock,
io_in_1_bits_cache,
io_in_1_bits_prot,
io_in_1_bits_qos,
io_in_1_bits_region,
io_in_1_bits_id,
io_in_1_bits_user,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_addr,
io_in_0_bits_len,
io_in_0_bits_size,
io_in_0_bits_burst,
io_in_0_bits_lock,
io_in_0_bits_cache,
io_in_0_bits_prot,
io_in_0_bits_qos,
io_in_0_bits_region,
io_in_0_bits_id,
io_in_0_bits_user,
io_out_ready,
io_out_valid,
io_out_bits_addr,
io_out_bits_len,
io_out_bits_size,
io_out_bits_burst,
io_out_bits_lock,
io_out_bits_cache,
io_out_bits_prot,
io_out_bits_qos,
io_out_bits_region,
io_out_bits_id,
io_out_bits_user,
io_chosen
);
input [31:0] io_in_1_bits_addr;
input [7:0] io_in_1_bits_len;
input [2:0] io_in_1_bits_size;
input [1:0] io_in_1_bits_burst;
input [3:0] io_in_1_bits_cache;
input [2:0] io_in_1_bits_prot;
input [3:0] io_in_1_bits_qos;
input [3:0] io_in_1_bits_region;
input [5:0] io_in_1_bits_id;
input [31:0] io_in_0_bits_addr;
input [7:0] io_in_0_bits_len;
input [2:0] io_in_0_bits_size;
input [1:0] io_in_0_bits_burst;
input [3:0] io_in_0_bits_cache;
input [2:0] io_in_0_bits_prot;
input [3:0] io_in_0_bits_qos;
input [3:0] io_in_0_bits_region;
input [5:0] io_in_0_bits_id;
output [31:0] io_out_bits_addr;
output [7:0] io_out_bits_len;
output [2:0] io_out_bits_size;
output [1:0] io_out_bits_burst;
output [3:0] io_out_bits_cache;
output [2:0] io_out_bits_prot;
output [3:0] io_out_bits_qos;
output [3:0] io_out_bits_region;
output [5:0] io_out_bits_id;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_lock;
input io_in_1_bits_user;
input io_in_0_valid;
input io_in_0_bits_lock;
input io_in_0_bits_user;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_lock;
output io_out_bits_user;
output io_chosen;
wire [31:0] io_out_bits_addr;
wire [7:0] io_out_bits_len;
wire [2:0] io_out_bits_size,io_out_bits_prot;
wire [1:0] io_out_bits_burst;
wire [3:0] io_out_bits_cache,io_out_bits_qos,io_out_bits_region;
wire [5:0] io_out_bits_id;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_lock,io_out_bits_user,
io_chosen,N0,N1,N2,N3,N4,N5,N6,T1,N7,T2,T4,N8,T19,T26,T20,T21,T24,T22,T23,T25,T28,
T32,T29,T30,T31,T34,T33,N9,N10,N11,N12,N13,N14,N15;
reg last_grant;
assign T25 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T26 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N11) begin
last_grant <= N12;
end
end
assign N15 = ~io_in_0_valid;
assign io_chosen = (N2)? 1'b1 :
(N3)? N15 : 1'b0;
assign N2 = T1;
assign N3 = N7;
assign io_out_bits_user = (N4)? io_in_1_bits_user :
(N5)? io_in_0_bits_user : 1'b0;
assign N4 = io_chosen;
assign N5 = N8;
assign io_out_bits_id = (N4)? io_in_1_bits_id :
(N5)? io_in_0_bits_id : 1'b0;
assign io_out_bits_region = (N4)? io_in_1_bits_region :
(N5)? io_in_0_bits_region : 1'b0;
assign io_out_bits_qos = (N4)? io_in_1_bits_qos :
(N5)? io_in_0_bits_qos : 1'b0;
assign io_out_bits_prot = (N4)? io_in_1_bits_prot :
(N5)? io_in_0_bits_prot : 1'b0;
assign io_out_bits_cache = (N4)? io_in_1_bits_cache :
(N5)? io_in_0_bits_cache : 1'b0;
assign io_out_bits_lock = (N4)? io_in_1_bits_lock :
(N5)? io_in_0_bits_lock : 1'b0;
assign io_out_bits_burst = (N4)? io_in_1_bits_burst :
(N5)? io_in_0_bits_burst : 1'b0;
assign io_out_bits_size = (N4)? io_in_1_bits_size :
(N5)? io_in_0_bits_size : 1'b0;
assign io_out_bits_len = (N4)? io_in_1_bits_len :
(N5)? io_in_0_bits_len : 1'b0;
assign io_out_bits_addr = (N4)? io_in_1_bits_addr :
(N5)? io_in_0_bits_addr : 1'b0;
assign io_out_valid = (N4)? io_in_1_valid :
(N5)? io_in_0_valid : 1'b0;
assign N11 = (N6)? 1'b1 :
(N14)? 1'b1 :
(N10)? 1'b0 : 1'b0;
assign N6 = reset;
assign N12 = (N6)? 1'b0 :
(N14)? io_chosen : 1'b0;
assign N7 = ~T1;
assign T1 = io_in_1_valid & T2;
assign T2 = ~last_grant;
assign T4 = io_out_ready & io_out_valid;
assign N8 = ~io_chosen;
assign io_in_0_ready = T19 & io_out_ready;
assign T19 = T26 | T20;
assign T20 = ~T21;
assign T21 = T24 | T22;
assign T22 = io_in_1_valid & T23;
assign T23 = ~last_grant;
assign T24 = io_in_0_valid & T25;
assign io_in_1_ready = T28 & io_out_ready;
assign T28 = T32 | T29;
assign T29 = ~T30;
assign T30 = T31 | io_in_0_valid;
assign T31 = T24 | T22;
assign T32 = T34 & T33;
assign T33 = ~last_grant;
assign T34 = ~T24;
assign N9 = T4 | reset;
assign N10 = ~N9;
assign N13 = ~reset;
assign N14 = T4 & N13;
endmodule |
module NastiArbiter
(
io_master_0_aw_ready,
io_master_0_aw_valid,
io_master_0_aw_bits_addr,
io_master_0_aw_bits_len,
io_master_0_aw_bits_size,
io_master_0_aw_bits_burst,
io_master_0_aw_bits_lock,
io_master_0_aw_bits_cache,
io_master_0_aw_bits_prot,
io_master_0_aw_bits_qos,
io_master_0_aw_bits_region,
io_master_0_aw_bits_id,
io_master_0_aw_bits_user,
io_master_0_w_ready,
io_master_0_w_valid,
io_master_0_w_bits_data,
io_master_0_w_bits_last,
io_master_0_w_bits_strb,
io_master_0_w_bits_user,
io_master_0_b_ready,
io_master_0_b_valid,
io_master_0_b_bits_resp,
io_master_0_b_bits_id,
io_master_0_b_bits_user,
io_master_0_ar_ready,
io_master_0_ar_valid,
io_master_0_ar_bits_addr,
io_master_0_ar_bits_len,
io_master_0_ar_bits_size,
io_master_0_ar_bits_burst,
io_master_0_ar_bits_lock,
io_master_0_ar_bits_cache,
io_master_0_ar_bits_prot,
io_master_0_ar_bits_qos,
io_master_0_ar_bits_region,
io_master_0_ar_bits_id,
io_master_0_ar_bits_user,
io_master_0_r_ready,
io_master_0_r_valid,
io_master_0_r_bits_resp,
io_master_0_r_bits_data,
io_master_0_r_bits_last,
io_master_0_r_bits_id,
io_master_0_r_bits_user,
io_slave_aw_ready,
io_slave_aw_valid,
io_slave_aw_bits_addr,
io_slave_aw_bits_len,
io_slave_aw_bits_size,
io_slave_aw_bits_burst,
io_slave_aw_bits_lock,
io_slave_aw_bits_cache,
io_slave_aw_bits_prot,
io_slave_aw_bits_qos,
io_slave_aw_bits_region,
io_slave_aw_bits_id,
io_slave_aw_bits_user,
io_slave_w_ready,
io_slave_w_valid,
io_slave_w_bits_data,
io_slave_w_bits_last,
io_slave_w_bits_strb,
io_slave_w_bits_user,
io_slave_b_ready,
io_slave_b_valid,
io_slave_b_bits_resp,
io_slave_b_bits_id,
io_slave_b_bits_user,
io_slave_ar_ready,
io_slave_ar_valid,
io_slave_ar_bits_addr,
io_slave_ar_bits_len,
io_slave_ar_bits_size,
io_slave_ar_bits_burst,
io_slave_ar_bits_lock,
io_slave_ar_bits_cache,
io_slave_ar_bits_prot,
io_slave_ar_bits_qos,
io_slave_ar_bits_region,
io_slave_ar_bits_id,
io_slave_ar_bits_user,
io_slave_r_ready,
io_slave_r_valid,
io_slave_r_bits_resp,
io_slave_r_bits_data,
io_slave_r_bits_last,
io_slave_r_bits_id,
io_slave_r_bits_user
);
input [31:0] io_master_0_aw_bits_addr;
input [7:0] io_master_0_aw_bits_len;
input [2:0] io_master_0_aw_bits_size;
input [1:0] io_master_0_aw_bits_burst;
input [3:0] io_master_0_aw_bits_cache;
input [2:0] io_master_0_aw_bits_prot;
input [3:0] io_master_0_aw_bits_qos;
input [3:0] io_master_0_aw_bits_region;
input [5:0] io_master_0_aw_bits_id;
input [63:0] io_master_0_w_bits_data;
input [7:0] io_master_0_w_bits_strb;
output [1:0] io_master_0_b_bits_resp;
output [5:0] io_master_0_b_bits_id;
input [31:0] io_master_0_ar_bits_addr;
input [7:0] io_master_0_ar_bits_len;
input [2:0] io_master_0_ar_bits_size;
input [1:0] io_master_0_ar_bits_burst;
input [3:0] io_master_0_ar_bits_cache;
input [2:0] io_master_0_ar_bits_prot;
input [3:0] io_master_0_ar_bits_qos;
input [3:0] io_master_0_ar_bits_region;
input [5:0] io_master_0_ar_bits_id;
output [1:0] io_master_0_r_bits_resp;
output [63:0] io_master_0_r_bits_data;
output [5:0] io_master_0_r_bits_id;
output [31:0] io_slave_aw_bits_addr;
output [7:0] io_slave_aw_bits_len;
output [2:0] io_slave_aw_bits_size;
output [1:0] io_slave_aw_bits_burst;
output [3:0] io_slave_aw_bits_cache;
output [2:0] io_slave_aw_bits_prot;
output [3:0] io_slave_aw_bits_qos;
output [3:0] io_slave_aw_bits_region;
output [5:0] io_slave_aw_bits_id;
output [63:0] io_slave_w_bits_data;
output [7:0] io_slave_w_bits_strb;
input [1:0] io_slave_b_bits_resp;
input [5:0] io_slave_b_bits_id;
output [31:0] io_slave_ar_bits_addr;
output [7:0] io_slave_ar_bits_len;
output [2:0] io_slave_ar_bits_size;
output [1:0] io_slave_ar_bits_burst;
output [3:0] io_slave_ar_bits_cache;
output [2:0] io_slave_ar_bits_prot;
output [3:0] io_slave_ar_bits_qos;
output [3:0] io_slave_ar_bits_region;
output [5:0] io_slave_ar_bits_id;
input [1:0] io_slave_r_bits_resp;
input [63:0] io_slave_r_bits_data;
input [5:0] io_slave_r_bits_id;
input io_master_0_aw_valid;
input io_master_0_aw_bits_lock;
input io_master_0_aw_bits_user;
input io_master_0_w_valid;
input io_master_0_w_bits_last;
input io_master_0_w_bits_user;
input io_master_0_b_ready;
input io_master_0_ar_valid;
input io_master_0_ar_bits_lock;
input io_master_0_ar_bits_user;
input io_master_0_r_ready;
input io_slave_aw_ready;
input io_slave_w_ready;
input io_slave_b_valid;
input io_slave_b_bits_user;
input io_slave_ar_ready;
input io_slave_r_valid;
input io_slave_r_bits_last;
input io_slave_r_bits_user;
output io_master_0_aw_ready;
output io_master_0_w_ready;
output io_master_0_b_valid;
output io_master_0_b_bits_user;
output io_master_0_ar_ready;
output io_master_0_r_valid;
output io_master_0_r_bits_last;
output io_master_0_r_bits_user;
output io_slave_aw_valid;
output io_slave_aw_bits_lock;
output io_slave_aw_bits_user;
output io_slave_w_valid;
output io_slave_w_bits_last;
output io_slave_w_bits_user;
output io_slave_b_ready;
output io_slave_ar_valid;
output io_slave_ar_bits_lock;
output io_slave_ar_bits_user;
output io_slave_r_ready;
wire [1:0] io_master_0_b_bits_resp,io_master_0_r_bits_resp,io_slave_aw_bits_burst,
io_slave_ar_bits_burst;
wire [5:0] io_master_0_b_bits_id,io_master_0_r_bits_id,io_slave_aw_bits_id,
io_slave_ar_bits_id;
wire [63:0] io_master_0_r_bits_data,io_slave_w_bits_data;
wire [31:0] io_slave_aw_bits_addr,io_slave_ar_bits_addr;
wire [7:0] io_slave_aw_bits_len,io_slave_w_bits_strb,io_slave_ar_bits_len;
wire [2:0] io_slave_aw_bits_size,io_slave_aw_bits_prot,io_slave_ar_bits_size,
io_slave_ar_bits_prot;
wire [3:0] io_slave_aw_bits_cache,io_slave_aw_bits_qos,io_slave_aw_bits_region,
io_slave_ar_bits_cache,io_slave_ar_bits_qos,io_slave_ar_bits_region;
wire io_master_0_aw_ready,io_master_0_w_ready,io_master_0_b_valid,
io_master_0_b_bits_user,io_master_0_ar_ready,io_master_0_r_valid,io_master_0_r_bits_last,
io_master_0_r_bits_user,io_slave_aw_valid,io_slave_aw_bits_lock,io_slave_aw_bits_user,
io_slave_w_valid,io_slave_w_bits_last,io_slave_w_bits_user,io_slave_b_ready,
io_slave_ar_valid,io_slave_ar_bits_lock,io_slave_ar_bits_user,io_slave_r_ready,
io_slave_aw_ready,io_slave_w_ready,io_slave_b_valid,io_slave_b_bits_user,
io_slave_ar_ready,io_slave_r_valid,io_slave_r_bits_last,io_slave_r_bits_user,
io_master_0_aw_valid,io_master_0_aw_bits_lock,io_master_0_aw_bits_user,io_master_0_w_valid,
io_master_0_w_bits_last,io_master_0_w_bits_user,io_master_0_b_ready,
io_master_0_ar_valid,io_master_0_ar_bits_lock,io_master_0_ar_bits_user,io_master_0_r_ready;
assign io_master_0_aw_ready = io_slave_aw_ready;
assign io_master_0_w_ready = io_slave_w_ready;
assign io_master_0_b_valid = io_slave_b_valid;
assign io_master_0_b_bits_resp[1] = io_slave_b_bits_resp[1];
assign io_master_0_b_bits_resp[0] = io_slave_b_bits_resp[0];
assign io_master_0_b_bits_id[5] = io_slave_b_bits_id[5];
assign io_master_0_b_bits_id[4] = io_slave_b_bits_id[4];
assign io_master_0_b_bits_id[3] = io_slave_b_bits_id[3];
assign io_master_0_b_bits_id[2] = io_slave_b_bits_id[2];
assign io_master_0_b_bits_id[1] = io_slave_b_bits_id[1];
assign io_master_0_b_bits_id[0] = io_slave_b_bits_id[0];
assign io_master_0_b_bits_user = io_slave_b_bits_user;
assign io_master_0_ar_ready = io_slave_ar_ready;
assign io_master_0_r_valid = io_slave_r_valid;
assign io_master_0_r_bits_resp[1] = io_slave_r_bits_resp[1];
assign io_master_0_r_bits_resp[0] = io_slave_r_bits_resp[0];
assign io_master_0_r_bits_data[63] = io_slave_r_bits_data[63];
assign io_master_0_r_bits_data[62] = io_slave_r_bits_data[62];
assign io_master_0_r_bits_data[61] = io_slave_r_bits_data[61];
assign io_master_0_r_bits_data[60] = io_slave_r_bits_data[60];
assign io_master_0_r_bits_data[59] = io_slave_r_bits_data[59];
assign io_master_0_r_bits_data[58] = io_slave_r_bits_data[58];
assign io_master_0_r_bits_data[57] = io_slave_r_bits_data[57];
assign io_master_0_r_bits_data[56] = io_slave_r_bits_data[56];
assign io_master_0_r_bits_data[55] = io_slave_r_bits_data[55];
assign io_master_0_r_bits_data[54] = io_slave_r_bits_data[54];
assign io_master_0_r_bits_data[53] = io_slave_r_bits_data[53];
assign io_master_0_r_bits_data[52] = io_slave_r_bits_data[52];
assign io_master_0_r_bits_data[51] = io_slave_r_bits_data[51];
assign io_master_0_r_bits_data[50] = io_slave_r_bits_data[50];
assign io_master_0_r_bits_data[49] = io_slave_r_bits_data[49];
assign io_master_0_r_bits_data[48] = io_slave_r_bits_data[48];
assign io_master_0_r_bits_data[47] = io_slave_r_bits_data[47];
assign io_master_0_r_bits_data[46] = io_slave_r_bits_data[46];
assign io_master_0_r_bits_data[45] = io_slave_r_bits_data[45];
assign io_master_0_r_bits_data[44] = io_slave_r_bits_data[44];
assign io_master_0_r_bits_data[43] = io_slave_r_bits_data[43];
assign io_master_0_r_bits_data[42] = io_slave_r_bits_data[42];
assign io_master_0_r_bits_data[41] = io_slave_r_bits_data[41];
assign io_master_0_r_bits_data[40] = io_slave_r_bits_data[40];
assign io_master_0_r_bits_data[39] = io_slave_r_bits_data[39];
assign io_master_0_r_bits_data[38] = io_slave_r_bits_data[38];
assign io_master_0_r_bits_data[37] = io_slave_r_bits_data[37];
assign io_master_0_r_bits_data[36] = io_slave_r_bits_data[36];
assign io_master_0_r_bits_data[35] = io_slave_r_bits_data[35];
assign io_master_0_r_bits_data[34] = io_slave_r_bits_data[34];
assign io_master_0_r_bits_data[33] = io_slave_r_bits_data[33];
assign io_master_0_r_bits_data[32] = io_slave_r_bits_data[32];
assign io_master_0_r_bits_data[31] = io_slave_r_bits_data[31];
assign io_master_0_r_bits_data[30] = io_slave_r_bits_data[30];
assign io_master_0_r_bits_data[29] = io_slave_r_bits_data[29];
assign io_master_0_r_bits_data[28] = io_slave_r_bits_data[28];
assign io_master_0_r_bits_data[27] = io_slave_r_bits_data[27];
assign io_master_0_r_bits_data[26] = io_slave_r_bits_data[26];
assign io_master_0_r_bits_data[25] = io_slave_r_bits_data[25];
assign io_master_0_r_bits_data[24] = io_slave_r_bits_data[24];
assign io_master_0_r_bits_data[23] = io_slave_r_bits_data[23];
assign io_master_0_r_bits_data[22] = io_slave_r_bits_data[22];
assign io_master_0_r_bits_data[21] = io_slave_r_bits_data[21];
assign io_master_0_r_bits_data[20] = io_slave_r_bits_data[20];
assign io_master_0_r_bits_data[19] = io_slave_r_bits_data[19];
assign io_master_0_r_bits_data[18] = io_slave_r_bits_data[18];
assign io_master_0_r_bits_data[17] = io_slave_r_bits_data[17];
assign io_master_0_r_bits_data[16] = io_slave_r_bits_data[16];
assign io_master_0_r_bits_data[15] = io_slave_r_bits_data[15];
assign io_master_0_r_bits_data[14] = io_slave_r_bits_data[14];
assign io_master_0_r_bits_data[13] = io_slave_r_bits_data[13];
assign io_master_0_r_bits_data[12] = io_slave_r_bits_data[12];
assign io_master_0_r_bits_data[11] = io_slave_r_bits_data[11];
assign io_master_0_r_bits_data[10] = io_slave_r_bits_data[10];
assign io_master_0_r_bits_data[9] = io_slave_r_bits_data[9];
assign io_master_0_r_bits_data[8] = io_slave_r_bits_data[8];
assign io_master_0_r_bits_data[7] = io_slave_r_bits_data[7];
assign io_master_0_r_bits_data[6] = io_slave_r_bits_data[6];
assign io_master_0_r_bits_data[5] = io_slave_r_bits_data[5];
assign io_master_0_r_bits_data[4] = io_slave_r_bits_data[4];
assign io_master_0_r_bits_data[3] = io_slave_r_bits_data[3];
assign io_master_0_r_bits_data[2] = io_slave_r_bits_data[2];
assign io_master_0_r_bits_data[1] = io_slave_r_bits_data[1];
assign io_master_0_r_bits_data[0] = io_slave_r_bits_data[0];
assign io_master_0_r_bits_last = io_slave_r_bits_last;
assign io_master_0_r_bits_id[5] = io_slave_r_bits_id[5];
assign io_master_0_r_bits_id[4] = io_slave_r_bits_id[4];
assign io_master_0_r_bits_id[3] = io_slave_r_bits_id[3];
assign io_master_0_r_bits_id[2] = io_slave_r_bits_id[2];
assign io_master_0_r_bits_id[1] = io_slave_r_bits_id[1];
assign io_master_0_r_bits_id[0] = io_slave_r_bits_id[0];
assign io_master_0_r_bits_user = io_slave_r_bits_user;
assign io_slave_aw_valid = io_master_0_aw_valid;
assign io_slave_aw_bits_addr[31] = io_master_0_aw_bits_addr[31];
assign io_slave_aw_bits_addr[30] = io_master_0_aw_bits_addr[30];
assign io_slave_aw_bits_addr[29] = io_master_0_aw_bits_addr[29];
assign io_slave_aw_bits_addr[28] = io_master_0_aw_bits_addr[28];
assign io_slave_aw_bits_addr[27] = io_master_0_aw_bits_addr[27];
assign io_slave_aw_bits_addr[26] = io_master_0_aw_bits_addr[26];
assign io_slave_aw_bits_addr[25] = io_master_0_aw_bits_addr[25];
assign io_slave_aw_bits_addr[24] = io_master_0_aw_bits_addr[24];
assign io_slave_aw_bits_addr[23] = io_master_0_aw_bits_addr[23];
assign io_slave_aw_bits_addr[22] = io_master_0_aw_bits_addr[22];
assign io_slave_aw_bits_addr[21] = io_master_0_aw_bits_addr[21];
assign io_slave_aw_bits_addr[20] = io_master_0_aw_bits_addr[20];
assign io_slave_aw_bits_addr[19] = io_master_0_aw_bits_addr[19];
assign io_slave_aw_bits_addr[18] = io_master_0_aw_bits_addr[18];
assign io_slave_aw_bits_addr[17] = io_master_0_aw_bits_addr[17];
assign io_slave_aw_bits_addr[16] = io_master_0_aw_bits_addr[16];
assign io_slave_aw_bits_addr[15] = io_master_0_aw_bits_addr[15];
assign io_slave_aw_bits_addr[14] = io_master_0_aw_bits_addr[14];
assign io_slave_aw_bits_addr[13] = io_master_0_aw_bits_addr[13];
assign io_slave_aw_bits_addr[12] = io_master_0_aw_bits_addr[12];
assign io_slave_aw_bits_addr[11] = io_master_0_aw_bits_addr[11];
assign io_slave_aw_bits_addr[10] = io_master_0_aw_bits_addr[10];
assign io_slave_aw_bits_addr[9] = io_master_0_aw_bits_addr[9];
assign io_slave_aw_bits_addr[8] = io_master_0_aw_bits_addr[8];
assign io_slave_aw_bits_addr[7] = io_master_0_aw_bits_addr[7];
assign io_slave_aw_bits_addr[6] = io_master_0_aw_bits_addr[6];
assign io_slave_aw_bits_addr[5] = io_master_0_aw_bits_addr[5];
assign io_slave_aw_bits_addr[4] = io_master_0_aw_bits_addr[4];
assign io_slave_aw_bits_addr[3] = io_master_0_aw_bits_addr[3];
assign io_slave_aw_bits_addr[2] = io_master_0_aw_bits_addr[2];
assign io_slave_aw_bits_addr[1] = io_master_0_aw_bits_addr[1];
assign io_slave_aw_bits_addr[0] = io_master_0_aw_bits_addr[0];
assign io_slave_aw_bits_len[7] = io_master_0_aw_bits_len[7];
assign io_slave_aw_bits_len[6] = io_master_0_aw_bits_len[6];
assign io_slave_aw_bits_len[5] = io_master_0_aw_bits_len[5];
assign io_slave_aw_bits_len[4] = io_master_0_aw_bits_len[4];
assign io_slave_aw_bits_len[3] = io_master_0_aw_bits_len[3];
assign io_slave_aw_bits_len[2] = io_master_0_aw_bits_len[2];
assign io_slave_aw_bits_len[1] = io_master_0_aw_bits_len[1];
assign io_slave_aw_bits_len[0] = io_master_0_aw_bits_len[0];
assign io_slave_aw_bits_size[2] = io_master_0_aw_bits_size[2];
assign io_slave_aw_bits_size[1] = io_master_0_aw_bits_size[1];
assign io_slave_aw_bits_size[0] = io_master_0_aw_bits_size[0];
assign io_slave_aw_bits_burst[1] = io_master_0_aw_bits_burst[1];
assign io_slave_aw_bits_burst[0] = io_master_0_aw_bits_burst[0];
assign io_slave_aw_bits_lock = io_master_0_aw_bits_lock;
assign io_slave_aw_bits_cache[3] = io_master_0_aw_bits_cache[3];
assign io_slave_aw_bits_cache[2] = io_master_0_aw_bits_cache[2];
assign io_slave_aw_bits_cache[1] = io_master_0_aw_bits_cache[1];
assign io_slave_aw_bits_cache[0] = io_master_0_aw_bits_cache[0];
assign io_slave_aw_bits_prot[2] = io_master_0_aw_bits_prot[2];
assign io_slave_aw_bits_prot[1] = io_master_0_aw_bits_prot[1];
assign io_slave_aw_bits_prot[0] = io_master_0_aw_bits_prot[0];
assign io_slave_aw_bits_qos[3] = io_master_0_aw_bits_qos[3];
assign io_slave_aw_bits_qos[2] = io_master_0_aw_bits_qos[2];
assign io_slave_aw_bits_qos[1] = io_master_0_aw_bits_qos[1];
assign io_slave_aw_bits_qos[0] = io_master_0_aw_bits_qos[0];
assign io_slave_aw_bits_region[3] = io_master_0_aw_bits_region[3];
assign io_slave_aw_bits_region[2] = io_master_0_aw_bits_region[2];
assign io_slave_aw_bits_region[1] = io_master_0_aw_bits_region[1];
assign io_slave_aw_bits_region[0] = io_master_0_aw_bits_region[0];
assign io_slave_aw_bits_id[5] = io_master_0_aw_bits_id[5];
assign io_slave_aw_bits_id[4] = io_master_0_aw_bits_id[4];
assign io_slave_aw_bits_id[3] = io_master_0_aw_bits_id[3];
assign io_slave_aw_bits_id[2] = io_master_0_aw_bits_id[2];
assign io_slave_aw_bits_id[1] = io_master_0_aw_bits_id[1];
assign io_slave_aw_bits_id[0] = io_master_0_aw_bits_id[0];
assign io_slave_aw_bits_user = io_master_0_aw_bits_user;
assign io_slave_w_valid = io_master_0_w_valid;
assign io_slave_w_bits_data[63] = io_master_0_w_bits_data[63];
assign io_slave_w_bits_data[62] = io_master_0_w_bits_data[62];
assign io_slave_w_bits_data[61] = io_master_0_w_bits_data[61];
assign io_slave_w_bits_data[60] = io_master_0_w_bits_data[60];
assign io_slave_w_bits_data[59] = io_master_0_w_bits_data[59];
assign io_slave_w_bits_data[58] = io_master_0_w_bits_data[58];
assign io_slave_w_bits_data[57] = io_master_0_w_bits_data[57];
assign io_slave_w_bits_data[56] = io_master_0_w_bits_data[56];
assign io_slave_w_bits_data[55] = io_master_0_w_bits_data[55];
assign io_slave_w_bits_data[54] = io_master_0_w_bits_data[54];
assign io_slave_w_bits_data[53] = io_master_0_w_bits_data[53];
assign io_slave_w_bits_data[52] = io_master_0_w_bits_data[52];
assign io_slave_w_bits_data[51] = io_master_0_w_bits_data[51];
assign io_slave_w_bits_data[50] = io_master_0_w_bits_data[50];
assign io_slave_w_bits_data[49] = io_master_0_w_bits_data[49];
assign io_slave_w_bits_data[48] = io_master_0_w_bits_data[48];
assign io_slave_w_bits_data[47] = io_master_0_w_bits_data[47];
assign io_slave_w_bits_data[46] = io_master_0_w_bits_data[46];
assign io_slave_w_bits_data[45] = io_master_0_w_bits_data[45];
assign io_slave_w_bits_data[44] = io_master_0_w_bits_data[44];
assign io_slave_w_bits_data[43] = io_master_0_w_bits_data[43];
assign io_slave_w_bits_data[42] = io_master_0_w_bits_data[42];
assign io_slave_w_bits_data[41] = io_master_0_w_bits_data[41];
assign io_slave_w_bits_data[40] = io_master_0_w_bits_data[40];
assign io_slave_w_bits_data[39] = io_master_0_w_bits_data[39];
assign io_slave_w_bits_data[38] = io_master_0_w_bits_data[38];
assign io_slave_w_bits_data[37] = io_master_0_w_bits_data[37];
assign io_slave_w_bits_data[36] = io_master_0_w_bits_data[36];
assign io_slave_w_bits_data[35] = io_master_0_w_bits_data[35];
assign io_slave_w_bits_data[34] = io_master_0_w_bits_data[34];
assign io_slave_w_bits_data[33] = io_master_0_w_bits_data[33];
assign io_slave_w_bits_data[32] = io_master_0_w_bits_data[32];
assign io_slave_w_bits_data[31] = io_master_0_w_bits_data[31];
assign io_slave_w_bits_data[30] = io_master_0_w_bits_data[30];
assign io_slave_w_bits_data[29] = io_master_0_w_bits_data[29];
assign io_slave_w_bits_data[28] = io_master_0_w_bits_data[28];
assign io_slave_w_bits_data[27] = io_master_0_w_bits_data[27];
assign io_slave_w_bits_data[26] = io_master_0_w_bits_data[26];
assign io_slave_w_bits_data[25] = io_master_0_w_bits_data[25];
assign io_slave_w_bits_data[24] = io_master_0_w_bits_data[24];
assign io_slave_w_bits_data[23] = io_master_0_w_bits_data[23];
assign io_slave_w_bits_data[22] = io_master_0_w_bits_data[22];
assign io_slave_w_bits_data[21] = io_master_0_w_bits_data[21];
assign io_slave_w_bits_data[20] = io_master_0_w_bits_data[20];
assign io_slave_w_bits_data[19] = io_master_0_w_bits_data[19];
assign io_slave_w_bits_data[18] = io_master_0_w_bits_data[18];
assign io_slave_w_bits_data[17] = io_master_0_w_bits_data[17];
assign io_slave_w_bits_data[16] = io_master_0_w_bits_data[16];
assign io_slave_w_bits_data[15] = io_master_0_w_bits_data[15];
assign io_slave_w_bits_data[14] = io_master_0_w_bits_data[14];
assign io_slave_w_bits_data[13] = io_master_0_w_bits_data[13];
assign io_slave_w_bits_data[12] = io_master_0_w_bits_data[12];
assign io_slave_w_bits_data[11] = io_master_0_w_bits_data[11];
assign io_slave_w_bits_data[10] = io_master_0_w_bits_data[10];
assign io_slave_w_bits_data[9] = io_master_0_w_bits_data[9];
assign io_slave_w_bits_data[8] = io_master_0_w_bits_data[8];
assign io_slave_w_bits_data[7] = io_master_0_w_bits_data[7];
assign io_slave_w_bits_data[6] = io_master_0_w_bits_data[6];
assign io_slave_w_bits_data[5] = io_master_0_w_bits_data[5];
assign io_slave_w_bits_data[4] = io_master_0_w_bits_data[4];
assign io_slave_w_bits_data[3] = io_master_0_w_bits_data[3];
assign io_slave_w_bits_data[2] = io_master_0_w_bits_data[2];
assign io_slave_w_bits_data[1] = io_master_0_w_bits_data[1];
assign io_slave_w_bits_data[0] = io_master_0_w_bits_data[0];
assign io_slave_w_bits_last = io_master_0_w_bits_last;
assign io_slave_w_bits_strb[7] = io_master_0_w_bits_strb[7];
assign io_slave_w_bits_strb[6] = io_master_0_w_bits_strb[6];
assign io_slave_w_bits_strb[5] = io_master_0_w_bits_strb[5];
assign io_slave_w_bits_strb[4] = io_master_0_w_bits_strb[4];
assign io_slave_w_bits_strb[3] = io_master_0_w_bits_strb[3];
assign io_slave_w_bits_strb[2] = io_master_0_w_bits_strb[2];
assign io_slave_w_bits_strb[1] = io_master_0_w_bits_strb[1];
assign io_slave_w_bits_strb[0] = io_master_0_w_bits_strb[0];
assign io_slave_w_bits_user = io_master_0_w_bits_user;
assign io_slave_b_ready = io_master_0_b_ready;
assign io_slave_ar_valid = io_master_0_ar_valid;
assign io_slave_ar_bits_addr[31] = io_master_0_ar_bits_addr[31];
assign io_slave_ar_bits_addr[30] = io_master_0_ar_bits_addr[30];
assign io_slave_ar_bits_addr[29] = io_master_0_ar_bits_addr[29];
assign io_slave_ar_bits_addr[28] = io_master_0_ar_bits_addr[28];
assign io_slave_ar_bits_addr[27] = io_master_0_ar_bits_addr[27];
assign io_slave_ar_bits_addr[26] = io_master_0_ar_bits_addr[26];
assign io_slave_ar_bits_addr[25] = io_master_0_ar_bits_addr[25];
assign io_slave_ar_bits_addr[24] = io_master_0_ar_bits_addr[24];
assign io_slave_ar_bits_addr[23] = io_master_0_ar_bits_addr[23];
assign io_slave_ar_bits_addr[22] = io_master_0_ar_bits_addr[22];
assign io_slave_ar_bits_addr[21] = io_master_0_ar_bits_addr[21];
assign io_slave_ar_bits_addr[20] = io_master_0_ar_bits_addr[20];
assign io_slave_ar_bits_addr[19] = io_master_0_ar_bits_addr[19];
assign io_slave_ar_bits_addr[18] = io_master_0_ar_bits_addr[18];
assign io_slave_ar_bits_addr[17] = io_master_0_ar_bits_addr[17];
assign io_slave_ar_bits_addr[16] = io_master_0_ar_bits_addr[16];
assign io_slave_ar_bits_addr[15] = io_master_0_ar_bits_addr[15];
assign io_slave_ar_bits_addr[14] = io_master_0_ar_bits_addr[14];
assign io_slave_ar_bits_addr[13] = io_master_0_ar_bits_addr[13];
assign io_slave_ar_bits_addr[12] = io_master_0_ar_bits_addr[12];
assign io_slave_ar_bits_addr[11] = io_master_0_ar_bits_addr[11];
assign io_slave_ar_bits_addr[10] = io_master_0_ar_bits_addr[10];
assign io_slave_ar_bits_addr[9] = io_master_0_ar_bits_addr[9];
assign io_slave_ar_bits_addr[8] = io_master_0_ar_bits_addr[8];
assign io_slave_ar_bits_addr[7] = io_master_0_ar_bits_addr[7];
assign io_slave_ar_bits_addr[6] = io_master_0_ar_bits_addr[6];
assign io_slave_ar_bits_addr[5] = io_master_0_ar_bits_addr[5];
assign io_slave_ar_bits_addr[4] = io_master_0_ar_bits_addr[4];
assign io_slave_ar_bits_addr[3] = io_master_0_ar_bits_addr[3];
assign io_slave_ar_bits_addr[2] = io_master_0_ar_bits_addr[2];
assign io_slave_ar_bits_addr[1] = io_master_0_ar_bits_addr[1];
assign io_slave_ar_bits_addr[0] = io_master_0_ar_bits_addr[0];
assign io_slave_ar_bits_len[7] = io_master_0_ar_bits_len[7];
assign io_slave_ar_bits_len[6] = io_master_0_ar_bits_len[6];
assign io_slave_ar_bits_len[5] = io_master_0_ar_bits_len[5];
assign io_slave_ar_bits_len[4] = io_master_0_ar_bits_len[4];
assign io_slave_ar_bits_len[3] = io_master_0_ar_bits_len[3];
assign io_slave_ar_bits_len[2] = io_master_0_ar_bits_len[2];
assign io_slave_ar_bits_len[1] = io_master_0_ar_bits_len[1];
assign io_slave_ar_bits_len[0] = io_master_0_ar_bits_len[0];
assign io_slave_ar_bits_size[2] = io_master_0_ar_bits_size[2];
assign io_slave_ar_bits_size[1] = io_master_0_ar_bits_size[1];
assign io_slave_ar_bits_size[0] = io_master_0_ar_bits_size[0];
assign io_slave_ar_bits_burst[1] = io_master_0_ar_bits_burst[1];
assign io_slave_ar_bits_burst[0] = io_master_0_ar_bits_burst[0];
assign io_slave_ar_bits_lock = io_master_0_ar_bits_lock;
assign io_slave_ar_bits_cache[3] = io_master_0_ar_bits_cache[3];
assign io_slave_ar_bits_cache[2] = io_master_0_ar_bits_cache[2];
assign io_slave_ar_bits_cache[1] = io_master_0_ar_bits_cache[1];
assign io_slave_ar_bits_cache[0] = io_master_0_ar_bits_cache[0];
assign io_slave_ar_bits_prot[2] = io_master_0_ar_bits_prot[2];
assign io_slave_ar_bits_prot[1] = io_master_0_ar_bits_prot[1];
assign io_slave_ar_bits_prot[0] = io_master_0_ar_bits_prot[0];
assign io_slave_ar_bits_qos[3] = io_master_0_ar_bits_qos[3];
assign io_slave_ar_bits_qos[2] = io_master_0_ar_bits_qos[2];
assign io_slave_ar_bits_qos[1] = io_master_0_ar_bits_qos[1];
assign io_slave_ar_bits_qos[0] = io_master_0_ar_bits_qos[0];
assign io_slave_ar_bits_region[3] = io_master_0_ar_bits_region[3];
assign io_slave_ar_bits_region[2] = io_master_0_ar_bits_region[2];
assign io_slave_ar_bits_region[1] = io_master_0_ar_bits_region[1];
assign io_slave_ar_bits_region[0] = io_master_0_ar_bits_region[0];
assign io_slave_ar_bits_id[5] = io_master_0_ar_bits_id[5];
assign io_slave_ar_bits_id[4] = io_master_0_ar_bits_id[4];
assign io_slave_ar_bits_id[3] = io_master_0_ar_bits_id[3];
assign io_slave_ar_bits_id[2] = io_master_0_ar_bits_id[2];
assign io_slave_ar_bits_id[1] = io_master_0_ar_bits_id[1];
assign io_slave_ar_bits_id[0] = io_master_0_ar_bits_id[0];
assign io_slave_ar_bits_user = io_master_0_ar_bits_user;
assign io_slave_r_ready = io_master_0_r_ready;
endmodule |
module RRArbiter_2
(
clk,
reset,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_rw,
io_in_1_bits_addr,
io_in_1_bits_data,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_rw,
io_in_0_bits_addr,
io_in_0_bits_data,
io_out_ready,
io_out_valid,
io_out_bits_rw,
io_out_bits_addr,
io_out_bits_data,
io_chosen
);
input [5:0] io_in_1_bits_addr;
input [63:0] io_in_1_bits_data;
input [5:0] io_in_0_bits_addr;
input [63:0] io_in_0_bits_data;
output [5:0] io_out_bits_addr;
output [63:0] io_out_bits_data;
input clk;
input reset;
input io_in_1_valid;
input io_in_1_bits_rw;
input io_in_0_valid;
input io_in_0_bits_rw;
input io_out_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
output io_out_bits_rw;
output io_chosen;
wire [5:0] io_out_bits_addr;
wire [63:0] io_out_bits_data;
wire io_in_1_ready,io_in_0_ready,io_out_valid,io_out_bits_rw,io_chosen,N0,N1,N2,N3,
N4,N5,N6,T1,N7,T2,T4,N8,T11,T18,T12,T13,T16,T14,T15,T17,T20,T24,T21,T22,T23,T26,
T25,N9,N10,N11,N12,N13,N14,N15;
reg last_grant;
assign T17 = N0 & 1'b0;
assign N0 = ~last_grant;
assign T18 = N1 & 1'b0;
assign N1 = ~last_grant;
always @(posedge clk) begin
if(N11) begin
last_grant <= N12;
end
end
assign N15 = ~io_in_0_valid;
assign io_chosen = (N2)? 1'b1 :
(N3)? N15 : 1'b0;
assign N2 = T1;
assign N3 = N7;
assign io_out_bits_data = (N4)? io_in_1_bits_data :
(N5)? io_in_0_bits_data : 1'b0;
assign N4 = io_chosen;
assign N5 = N8;
assign io_out_bits_addr = (N4)? io_in_1_bits_addr :
(N5)? io_in_0_bits_addr : 1'b0;
assign io_out_bits_rw = (N4)? io_in_1_bits_rw :
(N5)? io_in_0_bits_rw : 1'b0;
assign io_out_valid = (N4)? io_in_1_valid :
(N5)? io_in_0_valid : 1'b0;
assign N11 = (N6)? 1'b1 :
(N14)? 1'b1 :
(N10)? 1'b0 : 1'b0;
assign N6 = reset;
assign N12 = (N6)? 1'b0 :
(N14)? io_chosen : 1'b0;
assign N7 = ~T1;
assign T1 = io_in_1_valid & T2;
assign T2 = ~last_grant;
assign T4 = io_out_ready & io_out_valid;
assign N8 = ~io_chosen;
assign io_in_0_ready = T11 & io_out_ready;
assign T11 = T18 | T12;
assign T12 = ~T13;
assign T13 = T16 | T14;
assign T14 = io_in_1_valid & T15;
assign T15 = ~last_grant;
assign T16 = io_in_0_valid & T17;
assign io_in_1_ready = T20 & io_out_ready;
assign T20 = T24 | T21;
assign T21 = ~T22;
assign T22 = T23 | io_in_0_valid;
assign T23 = T16 | T14;
assign T24 = T26 & T25;
assign T25 = ~last_grant;
assign T26 = ~T16;
assign N9 = T4 | reset;
assign N10 = ~N9;
assign N13 = ~reset;
assign N14 = T4 & N13;
endmodule |
module LockingRRArbiter_7
(
clk,
reset,
io_in_4_ready,
io_in_4_valid,
io_in_4_bits_header_src,
io_in_4_bits_header_dst,
io_in_4_bits_payload_addr_block,
io_in_4_bits_payload_p_type,
io_in_3_ready,
io_in_3_valid,
io_in_3_bits_header_src,
io_in_3_bits_header_dst,
io_in_3_bits_payload_addr_block,
io_in_3_bits_payload_p_type,
io_in_2_ready,
io_in_2_valid,
io_in_2_bits_header_src,
io_in_2_bits_header_dst,
io_in_2_bits_payload_addr_block,
io_in_2_bits_payload_p_type,
io_in_1_ready,
io_in_1_valid,
io_in_1_bits_header_src,
io_in_1_bits_header_dst,
io_in_1_bits_payload_addr_block,
io_in_1_bits_payload_p_type,
io_in_0_ready,
io_in_0_valid,
io_in_0_bits_header_src,
io_in_0_bits_header_dst,
io_in_0_bits_payload_addr_block,
io_in_0_bits_payload_p_type,
io_out_ready,
io_out_valid,
io_out_bits_header_src,
io_out_bits_header_dst,
io_out_bits_payload_addr_block,
io_out_bits_payload_p_type,
io_chosen
);
input [2:0] io_in_4_bits_header_src;
input [2:0] io_in_4_bits_header_dst;
input [25:0] io_in_4_bits_payload_addr_block;
input [1:0] io_in_4_bits_payload_p_type;
input [2:0] io_in_3_bits_header_src;
input [2:0] io_in_3_bits_header_dst;
input [25:0] io_in_3_bits_payload_addr_block;
input [1:0] io_in_3_bits_payload_p_type;
input [2:0] io_in_2_bits_header_src;
input [2:0] io_in_2_bits_header_dst;
input [25:0] io_in_2_bits_payload_addr_block;
input [1:0] io_in_2_bits_payload_p_type;
input [2:0] io_in_1_bits_header_src;
input [2:0] io_in_1_bits_header_dst;
input [25:0] io_in_1_bits_payload_addr_block;
input [1:0] io_in_1_bits_payload_p_type;
input [2:0] io_in_0_bits_header_src;
input [2:0] io_in_0_bits_header_dst;
input [25:0] io_in_0_bits_payload_addr_block;
input [1:0] io_in_0_bits_payload_p_type;
output [2:0] io_out_bits_header_src;
output [2:0] io_out_bits_header_dst;
output [25:0] io_out_bits_payload_addr_block;
output [1:0] io_out_bits_payload_p_type;
output [2:0] io_chosen;
input clk;
input reset;
input io_in_4_valid;
input io_in_3_valid;
input io_in_2_valid;
input io_in_1_valid;
input io_in_0_valid;
input io_out_ready;
output io_in_4_ready;
output io_in_3_ready;
output io_in_2_ready;
output io_in_1_ready;
output io_in_0_ready;
output io_out_valid;
wire [2:0] io_out_bits_header_src,io_out_bits_header_dst,io_chosen,T0,T1,T2,T3,T4,T5,T35,
T38,T36,T43,T46,T44;
wire [25:0] io_out_bits_payload_addr_block,T27,T30,T28;
wire [1:0] io_out_bits_payload_p_type,T18,T22,T19;
wire io_in_4_ready,io_in_3_ready,io_in_2_ready,io_in_1_ready,io_in_0_ready,
io_out_valid,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
T15,N21,T13,N22,T11,N23,T7,N24,N25,N26,N27,N28,T8,T10,T12,T14,T16,N29,N30,N31,T51,
T54,T52,T59,T75,T60,T61,T64,T62,T63,T67,T65,T66,T70,T68,T69,T73,T71,T72,T74,T77,
T84,T78,T79,T80,T81,T82,T83,T86,T85,T88,T96,T89,T90,T91,T92,T93,T94,T95,T98,T97,
T99,T101,T110,T102,T103,T104,T105,T106,T107,T108,T109,T112,T111,T113,T114,T116,
T126,T117,T118,T119,T120,T121,T122,T123,T124,T125,T128,T127,T129,T130,T131,N32,
N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48;
wire [2:1] T6;
reg [2:0] last_grant;
assign T12 = last_grant < { 1'b1, 1'b1 };
assign T66 = last_grant < { 1'b1, 1'b1 };
assign T74 = last_grant < 1'b0;
assign T75 = last_grant < 1'b0;
assign T111 = last_grant < { 1'b1, 1'b1 };
always @(posedge clk) begin
if(N34) begin
last_grant[2] <= N37;
end
end
always @(posedge clk) begin
if(N34) begin
last_grant[1] <= N36;
end
end
always @(posedge clk) begin
if(N34) begin
last_grant[0] <= N35;
end
end
assign io_chosen = (N0)? { 1'b0, 1'b0, 1'b1 } :
(N1)? T0 : 1'b0;
assign N0 = T15;
assign N1 = N21;
assign T0 = (N2)? { 1'b0, 1'b1, 1'b0 } :
(N3)? T1 : 1'b0;
assign N2 = T13;
assign N3 = N22;
assign T1 = (N4)? { 1'b0, 1'b1, 1'b1 } :
(N5)? T2 : 1'b0;
assign N4 = T11;
assign N5 = N23;
assign T2 = (N6)? { 1'b1, 1'b0, 1'b0 } :
(N7)? T3 : 1'b0;
assign N6 = T7;
assign N7 = N24;
assign T3 = (N8)? { 1'b0, 1'b0, 1'b0 } :
(N9)? T4 : 1'b0;
assign N8 = io_in_0_valid;
assign N9 = N25;
assign T4 = (N10)? { 1'b0, 1'b0, 1'b1 } :
(N11)? T5 : 1'b0;
assign N10 = io_in_1_valid;
assign N11 = N26;
assign T5 = (N12)? { 1'b0, 1'b1, 1'b0 } :
(N13)? { T6, T6[1:1] } : 1'b0;
assign N12 = io_in_2_valid;
assign N13 = N27;
assign io_out_bits_payload_p_type = (N14)? io_in_4_bits_payload_p_type :
(N15)? T18 : 1'b0;
assign N14 = io_chosen[2];
assign N15 = N29;
assign T18 = (N16)? T22 :
(N17)? T19 : 1'b0;
assign N16 = io_chosen[1];
assign N17 = N30;
assign T19 = (N18)? io_in_1_bits_payload_p_type :
(N19)? io_in_0_bits_payload_p_type : 1'b0;
assign N18 = io_chosen[0];
assign N19 = N31;
assign T22 = (N18)? io_in_3_bits_payload_p_type :
(N19)? io_in_2_bits_payload_p_type : 1'b0;
assign io_out_bits_payload_addr_block = (N14)? io_in_4_bits_payload_addr_block :
(N15)? T27 : 1'b0;
assign T27 = (N16)? T30 :
(N17)? T28 : 1'b0;
assign T28 = (N18)? io_in_1_bits_payload_addr_block :
(N19)? io_in_0_bits_payload_addr_block : 1'b0;
assign T30 = (N18)? io_in_3_bits_payload_addr_block :
(N19)? io_in_2_bits_payload_addr_block : 1'b0;
assign io_out_bits_header_dst = (N14)? io_in_4_bits_header_dst :
(N15)? T35 : 1'b0;
assign T35 = (N16)? T38 :
(N17)? T36 : 1'b0;
assign T36 = (N18)? io_in_1_bits_header_dst :
(N19)? io_in_0_bits_header_dst : 1'b0;
assign T38 = (N18)? io_in_3_bits_header_dst :
(N19)? io_in_2_bits_header_dst : 1'b0;
assign io_out_bits_header_src = (N14)? io_in_4_bits_header_src :
(N15)? T43 : 1'b0;
assign T43 = (N16)? T46 :
(N17)? T44 : 1'b0;
assign T44 = (N18)? io_in_1_bits_header_src :
(N19)? io_in_0_bits_header_src : 1'b0;
assign T46 = (N18)? io_in_3_bits_header_src :
(N19)? io_in_2_bits_header_src : 1'b0;
assign io_out_valid = (N14)? io_in_4_valid :
(N15)? T51 : 1'b0;
assign T51 = (N16)? T54 :
(N17)? T52 : 1'b0;
assign T52 = (N18)? io_in_1_valid :
(N19)? io_in_0_valid : 1'b0;
assign T54 = (N18)? io_in_3_valid :
(N19)? io_in_2_valid : 1'b0;
assign N34 = (N20)? 1'b1 :
(N39)? 1'b1 :
(N33)? 1'b0 : 1'b0;
assign N20 = reset;
assign { N37, N36, N35 } = (N20)? { 1'b0, 1'b0, 1'b0 } :
(N39)? io_chosen : 1'b0;
assign N21 = ~T15;
assign N22 = ~T13;
assign N23 = ~T11;
assign N24 = ~T7;
assign N25 = ~io_in_0_valid;
assign N26 = ~io_in_1_valid;
assign N27 = ~io_in_2_valid;
assign N28 = ~io_in_3_valid;
assign T6[1] = io_in_3_valid;
assign T6[2] = N28;
assign T7 = io_in_4_valid & T8;
assign T8 = ~last_grant[2];
assign T10 = io_out_ready & io_out_valid;
assign T11 = io_in_3_valid & T12;
assign T13 = io_in_2_valid & T14;
assign T14 = ~N40;
assign N40 = last_grant[2] | last_grant[1];
assign T15 = io_in_1_valid & T16;
assign T16 = ~N42;
assign N42 = N41 | last_grant[0];
assign N41 = last_grant[2] | last_grant[1];
assign N29 = ~io_chosen[2];
assign N30 = ~io_chosen[1];
assign N31 = ~io_chosen[0];
assign io_in_0_ready = T59 & io_out_ready;
assign T59 = T75 | T60;
assign T60 = ~T61;
assign T61 = T64 | T62;
assign T62 = io_in_4_valid & T63;
assign T63 = ~last_grant[2];
assign T64 = T67 | T65;
assign T65 = io_in_3_valid & T66;
assign T67 = T70 | T68;
assign T68 = io_in_2_valid & T69;
assign T69 = ~N43;
assign N43 = last_grant[2] | last_grant[1];
assign T70 = T73 | T71;
assign T71 = io_in_1_valid & T72;
assign T72 = ~N45;
assign N45 = N44 | last_grant[0];
assign N44 = last_grant[2] | last_grant[1];
assign T73 = io_in_0_valid & T74;
assign io_in_1_ready = T77 & io_out_ready;
assign T77 = T84 | T78;
assign T78 = ~T79;
assign T79 = T80 | io_in_0_valid;
assign T80 = T81 | T62;
assign T81 = T82 | T65;
assign T82 = T83 | T68;
assign T83 = T73 | T71;
assign T84 = T86 & T85;
assign T85 = ~N47;
assign N47 = N46 | last_grant[0];
assign N46 = last_grant[2] | last_grant[1];
assign T86 = ~T73;
assign io_in_2_ready = T88 & io_out_ready;
assign T88 = T96 | T89;
assign T89 = ~T90;
assign T90 = T91 | io_in_1_valid;
assign T91 = T92 | io_in_0_valid;
assign T92 = T93 | T62;
assign T93 = T94 | T65;
assign T94 = T95 | T68;
assign T95 = T73 | T71;
assign T96 = T98 & T97;
assign T97 = ~N48;
assign N48 = last_grant[2] | last_grant[1];
assign T98 = ~T99;
assign T99 = T73 | T71;
assign io_in_3_ready = T101 & io_out_ready;
assign T101 = T110 | T102;
assign T102 = ~T103;
assign T103 = T104 | io_in_2_valid;
assign T104 = T105 | io_in_1_valid;
assign T105 = T106 | io_in_0_valid;
assign T106 = T107 | T62;
assign T107 = T108 | T65;
assign T108 = T109 | T68;
assign T109 = T73 | T71;
assign T110 = T112 & T111;
assign T112 = ~T113;
assign T113 = T114 | T68;
assign T114 = T73 | T71;
assign io_in_4_ready = T116 & io_out_ready;
assign T116 = T126 | T117;
assign T117 = ~T118;
assign T118 = T119 | io_in_3_valid;
assign T119 = T120 | io_in_2_valid;
assign T120 = T121 | io_in_1_valid;
assign T121 = T122 | io_in_0_valid;
assign T122 = T123 | T62;
assign T123 = T124 | T65;
assign T124 = T125 | T68;
assign T125 = T73 | T71;
assign T126 = T128 & T127;
assign T127 = ~last_grant[2];
assign T128 = ~T129;
assign T129 = T130 | T65;
assign T130 = T131 | T68;
assign T131 = T73 | T71;
assign N32 = T10 | reset;
assign N33 = ~N32;
assign N38 = ~reset;
assign N39 = T10 & N38;
endmodule |
module bsg_mux_one_hot_width_p9_els_p3
(
data_i,
sel_one_hot_i,
data_o
);
input [26:0] data_i;
input [2:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
wire [26:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[18] | data_masked[9];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[19] | data_masked[10];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[20] | data_masked[11];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[21] | data_masked[12];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[22] | data_masked[13];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[23] | data_masked[14];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[24] | data_masked[15];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[25] | data_masked[16];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[26] | data_masked[17];
endmodule |
module cl_decode
(
instruction_i,
decode_o_op_writes_rf_,
decode_o_is_load_op_,
decode_o_is_store_op_,
decode_o_is_mem_op_,
decode_o_is_byte_op_,
decode_o_is_hex_op_,
decode_o_is_load_unsigned_,
decode_o_is_branch_op_,
decode_o_is_jump_op_,
decode_o_op_reads_rf1_,
decode_o_op_reads_rf2_,
decode_o_op_is_auipc_,
decode_o_is_md_instr_,
decode_o_is_fence_op_,
decode_o_is_fence_i_op_,
decode_o_op_is_load_reservation_,
decode_o_op_is_lr_acq_
);
input [31:0] instruction_i;
output decode_o_op_writes_rf_;
output decode_o_is_load_op_;
output decode_o_is_store_op_;
output decode_o_is_mem_op_;
output decode_o_is_byte_op_;
output decode_o_is_hex_op_;
output decode_o_is_load_unsigned_;
output decode_o_is_branch_op_;
output decode_o_is_jump_op_;
output decode_o_op_reads_rf1_;
output decode_o_op_reads_rf2_;
output decode_o_op_is_auipc_;
output decode_o_is_md_instr_;
output decode_o_is_fence_op_;
output decode_o_is_fence_i_op_;
output decode_o_op_is_load_reservation_;
output decode_o_op_is_lr_acq_;
wire decode_o_op_writes_rf_,decode_o_is_load_op_,decode_o_is_store_op_,
decode_o_is_mem_op_,decode_o_is_byte_op_,decode_o_is_hex_op_,decode_o_is_load_unsigned_,
decode_o_is_branch_op_,decode_o_is_jump_op_,decode_o_op_reads_rf1_,
decode_o_op_reads_rf2_,decode_o_op_is_auipc_,decode_o_is_md_instr_,decode_o_is_fence_op_,
decode_o_is_fence_i_op_,decode_o_op_is_load_reservation_,decode_o_op_is_lr_acq_,N0,N1,N2,
N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,
N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,
N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,
N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,
N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,
N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,N118,N119,
N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,N134,N135,
N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,N150,N151,
N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,N166,N167,
N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,N182,N183,
N184,N185,N186,N187,N188,N189,N190;
assign N9 = instruction_i[1] & instruction_i[0];
assign N11 = instruction_i[6] | N89;
assign N12 = N90 | instruction_i[3];
assign N13 = N11 | N12;
assign N14 = N13 | N106;
assign N15 = instruction_i[6] | instruction_i[5];
assign N16 = N15 | N12;
assign N17 = N16 | N106;
assign N18 = N84 | N89;
assign N19 = instruction_i[4] | N105;
assign N20 = N18 | N19;
assign N21 = N20 | N106;
assign N22 = instruction_i[4] | instruction_i[3];
assign N23 = N18 | N22;
assign N24 = N23 | N106;
assign N25 = N84 & N89;
assign N26 = N90 & N105;
assign N27 = N25 & N26;
assign N28 = N27 & N106;
assign N29 = N13 | instruction_i[2];
assign N30 = N16 | instruction_i[2];
assign N31 = N11 | N19;
assign N32 = N31 | N106;
assign N34 = N84 & N90;
assign N35 = N34 & N9;
assign N37 = N89 & N105;
assign N38 = N37 & N106;
assign N39 = N89 | instruction_i[3];
assign N40 = N39 | instruction_i[2];
assign N41 = instruction_i[5] & instruction_i[3];
assign N42 = N41 & instruction_i[2];
assign N45 = N44 & N131;
assign N47 = instruction_i[13] | N131;
assign N51 = N11 | N22;
assign N52 = N55 | N92;
assign N53 = N51 | N52;
assign N55 = instruction_i[2] | N91;
assign N56 = N23 | N55;
assign N58 = instruction_i[6] & instruction_i[5];
assign N59 = N90 & instruction_i[2];
assign N60 = N58 & N59;
assign N61 = N60 & N9;
assign N62 = N106 | N92;
assign N63 = N23 | N62;
assign N64 = N58 & N26;
assign N65 = N64 & N106;
assign N66 = instruction_i[2] | N92;
assign N67 = N15 | N22;
assign N68 = N67 | N66;
assign N69 = N51 | N66;
assign N70 = N13 | N66;
assign N71 = N16 | N66;
assign N72 = N31 | N62;
assign N74 = instruction_i[5] & N105;
assign N75 = N106 & instruction_i[1];
assign N76 = N74 & N75;
assign N78 = instruction_i[6] & N90;
assign N79 = instruction_i[6] | instruction_i[4];
assign N80 = N79 | N92;
assign N81 = instruction_i[6] | N90;
assign N82 = N81 | N92;
assign N85 = N106 | N91;
assign N86 = N85 | N92;
assign N87 = N16 | N86;
assign N89 = ~instruction_i[5];
assign N90 = ~instruction_i[4];
assign N91 = ~instruction_i[1];
assign N92 = ~instruction_i[0];
assign N93 = N89 | instruction_i[6];
assign N94 = N90 | N93;
assign N95 = instruction_i[3] | N94;
assign N96 = instruction_i[2] | N95;
assign N97 = N91 | N96;
assign N98 = N92 | N97;
assign N99 = ~N98;
assign N100 = ~instruction_i[25];
assign N101 = instruction_i[27] | N129;
assign N102 = instruction_i[26] | N101;
assign N103 = N100 | N102;
assign N104 = ~N103;
assign N105 = ~instruction_i[3];
assign N106 = ~instruction_i[2];
assign N107 = instruction_i[5] | instruction_i[6];
assign N108 = instruction_i[4] | N107;
assign N109 = N105 | N108;
assign N110 = N106 | N109;
assign N111 = N91 | N110;
assign N112 = N92 | N111;
assign N113 = ~N112;
assign N114 = instruction_i[13] | instruction_i[14];
assign N115 = instruction_i[12] | N114;
assign N116 = ~N115;
assign N117 = instruction_i[18] | instruction_i[19];
assign N118 = instruction_i[17] | N117;
assign N119 = instruction_i[16] | N118;
assign N120 = instruction_i[15] | N119;
assign N121 = ~N120;
assign N122 = instruction_i[10] | instruction_i[11];
assign N123 = instruction_i[9] | N122;
assign N124 = instruction_i[8] | N123;
assign N125 = instruction_i[7] | N124;
assign N126 = ~N125;
assign N127 = instruction_i[30] | instruction_i[31];
assign N128 = instruction_i[29] | N127;
assign N129 = instruction_i[28] | N128;
assign N130 = ~N129;
assign N131 = ~instruction_i[12];
assign N132 = N131 | N114;
assign N133 = ~N132;
assign N134 = instruction_i[25] | N102;
assign N135 = instruction_i[24] | N134;
assign N136 = instruction_i[23] | N135;
assign N137 = instruction_i[22] | N136;
assign N138 = instruction_i[21] | N137;
assign N139 = instruction_i[20] | N138;
assign N140 = ~N139;
assign decode_o_op_writes_rf_ = (N0)? N33 :
(N10)? 1'b0 : 1'b0;
assign N0 = N9;
assign decode_o_is_mem_op_ = (N1)? N43 :
(N36)? 1'b0 : 1'b0;
assign N1 = N35;
assign decode_o_is_byte_op_ = (N2)? decode_o_is_mem_op_ :
(N46)? 1'b0 : 1'b0;
assign N2 = N45;
assign decode_o_is_hex_op_ = (N3)? decode_o_is_mem_op_ :
(N4)? 1'b0 : 1'b0;
assign N3 = N48;
assign N4 = N47;
assign decode_o_is_load_op_ = (N1)? N49 :
(N36)? 1'b0 : 1'b0;
assign decode_o_is_load_unsigned_ = (N5)? decode_o_is_load_op_ :
(N50)? 1'b0 : 1'b0;
assign N5 = instruction_i[14];
assign decode_o_op_reads_rf1_ = (N6)? N73 :
(N7)? 1'b0 : 1'b0;
assign N6 = instruction_i[1];
assign N7 = N91;
assign decode_o_op_reads_rf2_ = (N8)? N83 :
(N77)? 1'b0 : 1'b0;
assign N8 = N76;
assign N10 = ~N9;
assign N33 = N152 | N153;
assign N152 = N150 | N151;
assign N150 = N148 | N149;
assign N148 = N147 | N28;
assign N147 = N145 | N146;
assign N145 = N143 | N144;
assign N143 = N141 | N142;
assign N141 = ~N14;
assign N142 = ~N17;
assign N144 = ~N21;
assign N146 = ~N24;
assign N149 = ~N29;
assign N151 = ~N30;
assign N153 = ~N32;
assign N36 = ~N35;
assign N43 = N155 | N42;
assign N155 = N38 | N154;
assign N154 = ~N40;
assign N44 = ~instruction_i[13];
assign N46 = ~N45;
assign N48 = ~N47;
assign N49 = N38 | N42;
assign N50 = ~instruction_i[14];
assign N54 = ~N53;
assign decode_o_is_store_op_ = N54;
assign N57 = ~N56;
assign decode_o_is_branch_op_ = N57;
assign decode_o_is_jump_op_ = N61;
assign N73 = N165 | N166;
assign N165 = N163 | N164;
assign N163 = N161 | N162;
assign N161 = N159 | N160;
assign N159 = N157 | N158;
assign N157 = N156 | N65;
assign N156 = ~N63;
assign N158 = ~N68;
assign N160 = ~N69;
assign N162 = ~N70;
assign N164 = ~N71;
assign N166 = ~N72;
assign N77 = ~N76;
assign N83 = N168 | N169;
assign N168 = N78 | N167;
assign N167 = ~N80;
assign N169 = ~N82;
assign N84 = ~instruction_i[6];
assign N88 = ~N87;
assign decode_o_op_is_auipc_ = N88;
assign decode_o_is_md_instr_ = N99 & N104;
assign decode_o_op_is_load_reservation_ = ~N184;
assign N184 = N183 | N92;
assign N183 = N182 | N91;
assign N182 = N181 | N106;
assign N181 = N180 | N105;
assign N180 = N179 | instruction_i[4];
assign N179 = N178 | N89;
assign N178 = N177 | instruction_i[6];
assign N177 = N176 | instruction_i[12];
assign N176 = N175 | N44;
assign N175 = N174 | instruction_i[14];
assign N174 = N173 | instruction_i[27];
assign N173 = N171 | N172;
assign N171 = N170 | instruction_i[29];
assign N170 = instruction_i[31] | instruction_i[30];
assign N172 = ~instruction_i[28];
assign decode_o_op_is_lr_acq_ = decode_o_op_is_load_reservation_ & instruction_i[26];
assign decode_o_is_fence_op_ = N187 & N130;
assign N187 = N186 & N126;
assign N186 = N185 & N121;
assign N185 = N113 & N116;
assign decode_o_is_fence_i_op_ = N190 & N140;
assign N190 = N189 & N126;
assign N189 = N188 & N121;
assign N188 = N113 & N133;
endmodule |
module cl_state_machine
(
instruction_i,
state_i,
net_pc_write_cmd_idle_i,
stall_i,
state_o
);
input [31:0] instruction_i;
input [1:0] state_i;
output [1:0] state_o;
input net_pc_write_cmd_idle_i;
input stall_i;
wire [1:0] state_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11;
assign N6 = N4 & N5;
assign N7 = state_i[1] | N5;
assign N9 = state_i[1] & state_i[0];
assign N10 = N4 | state_i[0];
assign state_o = (N0)? { 1'b0, net_pc_write_cmd_idle_i } :
(N1)? { 1'b0, 1'b1 } :
(N2)? { 1'b1, 1'b1 } :
(N3)? { 1'b1, 1'b1 } : 1'b0;
assign N0 = N6;
assign N1 = N8;
assign N2 = N9;
assign N3 = N11;
assign N4 = ~state_i[1];
assign N5 = ~state_i[0];
assign N8 = ~N7;
assign N11 = ~N10;
endmodule |
module bsg_round_robin_arb_inputs_p4
(
clk_i,
reset_i,
grants_en_i,
reqs_i,
grants_o,
v_o,
tag_o,
yumi_i
);
input [3:0] reqs_i;
output [3:0] grants_o;
output [1:0] tag_o;
input clk_i;
input reset_i;
input grants_en_i;
input yumi_i;
output v_o;
wire [3:0] grants_o;
wire [1:0] tag_o;
wire v_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,
N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,
N117,N118,N119,N120,N121,N122,N123,N124,N125,N126;
reg [1:0] last_r;
always @(posedge clk_i) begin
if(N123) begin
last_r[1] <= N121;
end
end
always @(posedge clk_i) begin
if(N123) begin
last_r[0] <= N120;
end
end
assign N100 = ~grants_en_i;
assign N101 = grants_en_i & N0 & (N1 & N2) & N3;
assign N0 = ~reqs_i[0];
assign N1 = ~reqs_i[1];
assign N2 = ~reqs_i[2];
assign N3 = ~reqs_i[3];
assign N102 = grants_en_i & reqs_i[1] & (N4 & N5);
assign N4 = ~last_r[0];
assign N5 = ~last_r[1];
assign N103 = grants_en_i & N6 & (N7 & reqs_i[2]) & N8;
assign N6 = ~reqs_i[1];
assign N7 = ~last_r[0];
assign N8 = ~last_r[1];
assign N9 = grants_en_i & N13;
assign N10 = N9 & N14;
assign N11 = N10 & N15;
assign N12 = N11 & N16;
assign N104 = N12 & reqs_i[3];
assign N13 = ~reqs_i[1];
assign N14 = ~last_r[0];
assign N15 = ~reqs_i[2];
assign N16 = ~last_r[1];
assign N17 = grants_en_i & reqs_i[0];
assign N18 = N17 & N22;
assign N19 = N18 & N23;
assign N20 = N19 & N24;
assign N21 = N20 & N25;
assign N105 = N21 & N26;
assign N22 = ~reqs_i[1];
assign N23 = ~last_r[0];
assign N24 = ~reqs_i[2];
assign N25 = ~last_r[1];
assign N26 = ~reqs_i[3];
assign N106 = grants_en_i & last_r[0] & (reqs_i[2] & N27);
assign N27 = ~last_r[1];
assign N107 = grants_en_i & last_r[0] & (N28 & N29) & reqs_i[3];
assign N28 = ~reqs_i[2];
assign N29 = ~last_r[1];
assign N30 = grants_en_i & reqs_i[0];
assign N31 = N30 & last_r[0];
assign N32 = N31 & N34;
assign N33 = N32 & N35;
assign N108 = N33 & N36;
assign N34 = ~reqs_i[2];
assign N35 = ~last_r[1];
assign N36 = ~reqs_i[3];
assign N37 = grants_en_i & N42;
assign N38 = N37 & reqs_i[1];
assign N39 = N38 & last_r[0];
assign N40 = N39 & N43;
assign N41 = N40 & N44;
assign N109 = N41 & N45;
assign N42 = ~reqs_i[0];
assign N43 = ~reqs_i[2];
assign N44 = ~last_r[1];
assign N45 = ~reqs_i[3];
assign N110 = grants_en_i & N46 & (last_r[1] & reqs_i[3]);
assign N46 = ~last_r[0];
assign N111 = grants_en_i & reqs_i[0] & (N47 & last_r[1]) & N48;
assign N47 = ~last_r[0];
assign N48 = ~reqs_i[3];
assign N49 = grants_en_i & N53;
assign N50 = N49 & reqs_i[1];
assign N51 = N50 & N54;
assign N52 = N51 & last_r[1];
assign N112 = N52 & N55;
assign N53 = ~reqs_i[0];
assign N54 = ~last_r[0];
assign N55 = ~reqs_i[3];
assign N56 = grants_en_i & N61;
assign N57 = N56 & N62;
assign N58 = N57 & N63;
assign N59 = N58 & reqs_i[2];
assign N60 = N59 & last_r[1];
assign N113 = N60 & N64;
assign N61 = ~reqs_i[0];
assign N62 = ~reqs_i[1];
assign N63 = ~last_r[0];
assign N64 = ~reqs_i[3];
assign N114 = grants_en_i & reqs_i[0] & (last_r[0] & last_r[1]);
assign N115 = grants_en_i & N65 & (reqs_i[1] & last_r[0]) & last_r[1];
assign N65 = ~reqs_i[0];
assign N66 = grants_en_i & N70;
assign N67 = N66 & N71;
assign N68 = N67 & last_r[0];
assign N69 = N68 & reqs_i[2];
assign N116 = N69 & last_r[1];
assign N70 = ~reqs_i[0];
assign N71 = ~reqs_i[1];
assign N72 = grants_en_i & N77;
assign N73 = N72 & N78;
assign N74 = N73 & last_r[0];
assign N75 = N74 & N79;
assign N76 = N75 & last_r[1];
assign N117 = N76 & reqs_i[3];
assign N77 = ~reqs_i[0];
assign N78 = ~reqs_i[1];
assign N79 = ~reqs_i[2];
assign grants_o = (N80)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N81)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N82)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N83)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N84)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N85)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N86)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N87)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N88)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N89)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N90)? { 1'b1, 1'b0, 1'b0, 1'b0 } :
(N91)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N92)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N93)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N94)? { 1'b0, 1'b0, 1'b0, 1'b1 } :
(N95)? { 1'b0, 1'b0, 1'b1, 1'b0 } :
(N96)? { 1'b0, 1'b1, 1'b0, 1'b0 } :
(N97)? { 1'b1, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N80 = N100;
assign N81 = N101;
assign N82 = N102;
assign N83 = N103;
assign N84 = N104;
assign N85 = N105;
assign N86 = N106;
assign N87 = N107;
assign N88 = N108;
assign N89 = N109;
assign N90 = N110;
assign N91 = N111;
assign N92 = N112;
assign N93 = N113;
assign N94 = N114;
assign N95 = N115;
assign N96 = N116;
assign N97 = N117;
assign tag_o = (N80)? { 1'b0, 1'b0 } :
(N81)? { 1'b0, 1'b0 } :
(N82)? { 1'b0, 1'b1 } :
(N83)? { 1'b1, 1'b0 } :
(N84)? { 1'b1, 1'b1 } :
(N85)? { 1'b0, 1'b0 } :
(N86)? { 1'b1, 1'b0 } :
(N87)? { 1'b1, 1'b1 } :
(N88)? { 1'b0, 1'b0 } :
(N89)? { 1'b0, 1'b1 } :
(N90)? { 1'b1, 1'b1 } :
(N91)? { 1'b0, 1'b0 } :
(N92)? { 1'b0, 1'b1 } :
(N93)? { 1'b1, 1'b0 } :
(N94)? { 1'b0, 1'b0 } :
(N95)? { 1'b0, 1'b1 } :
(N96)? { 1'b1, 1'b0 } :
(N97)? { 1'b1, 1'b1 } : 1'b0;
assign { N121, N120 } = (N98)? { 1'b0, 1'b0 } :
(N99)? tag_o : 1'b0;
assign N98 = reset_i;
assign N99 = N119;
assign v_o = N126 & grants_en_i;
assign N126 = N125 | reqs_i[0];
assign N125 = N124 | reqs_i[1];
assign N124 = reqs_i[3] | reqs_i[2];
assign N118 = ~yumi_i;
assign N119 = ~reset_i;
assign N122 = N118 & N119;
assign N123 = ~N122;
endmodule |
module bsg_mux_one_hot_width_p9_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [44:0] data_i;
input [4:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26;
wire [44:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_masked[35] = data_i[35] & sel_one_hot_i[3];
assign data_masked[34] = data_i[34] & sel_one_hot_i[3];
assign data_masked[33] = data_i[33] & sel_one_hot_i[3];
assign data_masked[32] = data_i[32] & sel_one_hot_i[3];
assign data_masked[31] = data_i[31] & sel_one_hot_i[3];
assign data_masked[30] = data_i[30] & sel_one_hot_i[3];
assign data_masked[29] = data_i[29] & sel_one_hot_i[3];
assign data_masked[28] = data_i[28] & sel_one_hot_i[3];
assign data_masked[27] = data_i[27] & sel_one_hot_i[3];
assign data_masked[44] = data_i[44] & sel_one_hot_i[4];
assign data_masked[43] = data_i[43] & sel_one_hot_i[4];
assign data_masked[42] = data_i[42] & sel_one_hot_i[4];
assign data_masked[41] = data_i[41] & sel_one_hot_i[4];
assign data_masked[40] = data_i[40] & sel_one_hot_i[4];
assign data_masked[39] = data_i[39] & sel_one_hot_i[4];
assign data_masked[38] = data_i[38] & sel_one_hot_i[4];
assign data_masked[37] = data_i[37] & sel_one_hot_i[4];
assign data_masked[36] = data_i[36] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[9];
assign N1 = N0 | data_masked[18];
assign N0 = data_masked[36] | data_masked[27];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[10];
assign N4 = N3 | data_masked[19];
assign N3 = data_masked[37] | data_masked[28];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[11];
assign N7 = N6 | data_masked[20];
assign N6 = data_masked[38] | data_masked[29];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[12];
assign N10 = N9 | data_masked[21];
assign N9 = data_masked[39] | data_masked[30];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[13];
assign N13 = N12 | data_masked[22];
assign N12 = data_masked[40] | data_masked[31];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[14];
assign N16 = N15 | data_masked[23];
assign N15 = data_masked[41] | data_masked[32];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[15];
assign N19 = N18 | data_masked[24];
assign N18 = data_masked[42] | data_masked[33];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[16];
assign N22 = N21 | data_masked[25];
assign N21 = data_masked[43] | data_masked[34];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[17];
assign N25 = N24 | data_masked[26];
assign N24 = data_masked[44] | data_masked[35];
endmodule |
module bsg_mux_one_hot_width_p1_els_p1
(
data_i,
sel_one_hot_i,
data_o
);
input [0:0] data_i;
input [0:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule |
module bsg_counter_up_down_max_val_p200_init_val_p200
(
clk_i,
reset_i,
up_i,
down_i,
count_o
);
output [7:0] count_o;
input clk_i;
input reset_i;
input up_i;
input down_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26;
reg [7:0] count_o;
always @(posedge clk_i) begin
if(1'b1) begin
count_o[7] <= N26;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[6] <= N25;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[5] <= N24;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[4] <= N23;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[3] <= N22;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[2] <= N21;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[1] <= N20;
end
end
always @(posedge clk_i) begin
if(1'b1) begin
count_o[0] <= N19;
end
end
assign { N10, N9, N8, N7, N6, N5, N4, N3 } = count_o - down_i;
assign { N18, N17, N16, N15, N14, N13, N12, N11 } = { N10, N9, N8, N7, N6, N5, N4, N3 } + up_i;
assign { N26, N25, N24, N23, N22, N21, N20, N19 } = (N0)? { 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0 } :
(N1)? { N18, N17, N16, N15, N14, N13, N12, N11 } : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_mux_one_hot_width_p76_els_p5
(
data_i,
sel_one_hot_i,
data_o
);
input [379:0] data_i;
input [4:0] sel_one_hot_i;
output [75:0] data_o;
wire [75:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,N162,N163,N164,N165,
N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,N178,N179,N180,N181,
N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,N194,N195,N196,N197,
N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,N210,N211,N212,N213,
N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,N226,N227;
wire [379:0] data_masked;
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_masked[127] = data_i[127] & sel_one_hot_i[1];
assign data_masked[126] = data_i[126] & sel_one_hot_i[1];
assign data_masked[125] = data_i[125] & sel_one_hot_i[1];
assign data_masked[124] = data_i[124] & sel_one_hot_i[1];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[2];
assign data_masked[226] = data_i[226] & sel_one_hot_i[2];
assign data_masked[225] = data_i[225] & sel_one_hot_i[2];
assign data_masked[224] = data_i[224] & sel_one_hot_i[2];
assign data_masked[223] = data_i[223] & sel_one_hot_i[2];
assign data_masked[222] = data_i[222] & sel_one_hot_i[2];
assign data_masked[221] = data_i[221] & sel_one_hot_i[2];
assign data_masked[220] = data_i[220] & sel_one_hot_i[2];
assign data_masked[219] = data_i[219] & sel_one_hot_i[2];
assign data_masked[218] = data_i[218] & sel_one_hot_i[2];
assign data_masked[217] = data_i[217] & sel_one_hot_i[2];
assign data_masked[216] = data_i[216] & sel_one_hot_i[2];
assign data_masked[215] = data_i[215] & sel_one_hot_i[2];
assign data_masked[214] = data_i[214] & sel_one_hot_i[2];
assign data_masked[213] = data_i[213] & sel_one_hot_i[2];
assign data_masked[212] = data_i[212] & sel_one_hot_i[2];
assign data_masked[211] = data_i[211] & sel_one_hot_i[2];
assign data_masked[210] = data_i[210] & sel_one_hot_i[2];
assign data_masked[209] = data_i[209] & sel_one_hot_i[2];
assign data_masked[208] = data_i[208] & sel_one_hot_i[2];
assign data_masked[207] = data_i[207] & sel_one_hot_i[2];
assign data_masked[206] = data_i[206] & sel_one_hot_i[2];
assign data_masked[205] = data_i[205] & sel_one_hot_i[2];
assign data_masked[204] = data_i[204] & sel_one_hot_i[2];
assign data_masked[203] = data_i[203] & sel_one_hot_i[2];
assign data_masked[202] = data_i[202] & sel_one_hot_i[2];
assign data_masked[201] = data_i[201] & sel_one_hot_i[2];
assign data_masked[200] = data_i[200] & sel_one_hot_i[2];
assign data_masked[199] = data_i[199] & sel_one_hot_i[2];
assign data_masked[198] = data_i[198] & sel_one_hot_i[2];
assign data_masked[197] = data_i[197] & sel_one_hot_i[2];
assign data_masked[196] = data_i[196] & sel_one_hot_i[2];
assign data_masked[195] = data_i[195] & sel_one_hot_i[2];
assign data_masked[194] = data_i[194] & sel_one_hot_i[2];
assign data_masked[193] = data_i[193] & sel_one_hot_i[2];
assign data_masked[192] = data_i[192] & sel_one_hot_i[2];
assign data_masked[191] = data_i[191] & sel_one_hot_i[2];
assign data_masked[190] = data_i[190] & sel_one_hot_i[2];
assign data_masked[189] = data_i[189] & sel_one_hot_i[2];
assign data_masked[188] = data_i[188] & sel_one_hot_i[2];
assign data_masked[187] = data_i[187] & sel_one_hot_i[2];
assign data_masked[186] = data_i[186] & sel_one_hot_i[2];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[303] = data_i[303] & sel_one_hot_i[3];
assign data_masked[302] = data_i[302] & sel_one_hot_i[3];
assign data_masked[301] = data_i[301] & sel_one_hot_i[3];
assign data_masked[300] = data_i[300] & sel_one_hot_i[3];
assign data_masked[299] = data_i[299] & sel_one_hot_i[3];
assign data_masked[298] = data_i[298] & sel_one_hot_i[3];
assign data_masked[297] = data_i[297] & sel_one_hot_i[3];
assign data_masked[296] = data_i[296] & sel_one_hot_i[3];
assign data_masked[295] = data_i[295] & sel_one_hot_i[3];
assign data_masked[294] = data_i[294] & sel_one_hot_i[3];
assign data_masked[293] = data_i[293] & sel_one_hot_i[3];
assign data_masked[292] = data_i[292] & sel_one_hot_i[3];
assign data_masked[291] = data_i[291] & sel_one_hot_i[3];
assign data_masked[290] = data_i[290] & sel_one_hot_i[3];
assign data_masked[289] = data_i[289] & sel_one_hot_i[3];
assign data_masked[288] = data_i[288] & sel_one_hot_i[3];
assign data_masked[287] = data_i[287] & sel_one_hot_i[3];
assign data_masked[286] = data_i[286] & sel_one_hot_i[3];
assign data_masked[285] = data_i[285] & sel_one_hot_i[3];
assign data_masked[284] = data_i[284] & sel_one_hot_i[3];
assign data_masked[283] = data_i[283] & sel_one_hot_i[3];
assign data_masked[282] = data_i[282] & sel_one_hot_i[3];
assign data_masked[281] = data_i[281] & sel_one_hot_i[3];
assign data_masked[280] = data_i[280] & sel_one_hot_i[3];
assign data_masked[279] = data_i[279] & sel_one_hot_i[3];
assign data_masked[278] = data_i[278] & sel_one_hot_i[3];
assign data_masked[277] = data_i[277] & sel_one_hot_i[3];
assign data_masked[276] = data_i[276] & sel_one_hot_i[3];
assign data_masked[275] = data_i[275] & sel_one_hot_i[3];
assign data_masked[274] = data_i[274] & sel_one_hot_i[3];
assign data_masked[273] = data_i[273] & sel_one_hot_i[3];
assign data_masked[272] = data_i[272] & sel_one_hot_i[3];
assign data_masked[271] = data_i[271] & sel_one_hot_i[3];
assign data_masked[270] = data_i[270] & sel_one_hot_i[3];
assign data_masked[269] = data_i[269] & sel_one_hot_i[3];
assign data_masked[268] = data_i[268] & sel_one_hot_i[3];
assign data_masked[267] = data_i[267] & sel_one_hot_i[3];
assign data_masked[266] = data_i[266] & sel_one_hot_i[3];
assign data_masked[265] = data_i[265] & sel_one_hot_i[3];
assign data_masked[264] = data_i[264] & sel_one_hot_i[3];
assign data_masked[263] = data_i[263] & sel_one_hot_i[3];
assign data_masked[262] = data_i[262] & sel_one_hot_i[3];
assign data_masked[261] = data_i[261] & sel_one_hot_i[3];
assign data_masked[260] = data_i[260] & sel_one_hot_i[3];
assign data_masked[259] = data_i[259] & sel_one_hot_i[3];
assign data_masked[258] = data_i[258] & sel_one_hot_i[3];
assign data_masked[257] = data_i[257] & sel_one_hot_i[3];
assign data_masked[256] = data_i[256] & sel_one_hot_i[3];
assign data_masked[255] = data_i[255] & sel_one_hot_i[3];
assign data_masked[254] = data_i[254] & sel_one_hot_i[3];
assign data_masked[253] = data_i[253] & sel_one_hot_i[3];
assign data_masked[252] = data_i[252] & sel_one_hot_i[3];
assign data_masked[251] = data_i[251] & sel_one_hot_i[3];
assign data_masked[250] = data_i[250] & sel_one_hot_i[3];
assign data_masked[249] = data_i[249] & sel_one_hot_i[3];
assign data_masked[248] = data_i[248] & sel_one_hot_i[3];
assign data_masked[247] = data_i[247] & sel_one_hot_i[3];
assign data_masked[246] = data_i[246] & sel_one_hot_i[3];
assign data_masked[245] = data_i[245] & sel_one_hot_i[3];
assign data_masked[244] = data_i[244] & sel_one_hot_i[3];
assign data_masked[243] = data_i[243] & sel_one_hot_i[3];
assign data_masked[242] = data_i[242] & sel_one_hot_i[3];
assign data_masked[241] = data_i[241] & sel_one_hot_i[3];
assign data_masked[240] = data_i[240] & sel_one_hot_i[3];
assign data_masked[239] = data_i[239] & sel_one_hot_i[3];
assign data_masked[238] = data_i[238] & sel_one_hot_i[3];
assign data_masked[237] = data_i[237] & sel_one_hot_i[3];
assign data_masked[236] = data_i[236] & sel_one_hot_i[3];
assign data_masked[235] = data_i[235] & sel_one_hot_i[3];
assign data_masked[234] = data_i[234] & sel_one_hot_i[3];
assign data_masked[233] = data_i[233] & sel_one_hot_i[3];
assign data_masked[232] = data_i[232] & sel_one_hot_i[3];
assign data_masked[231] = data_i[231] & sel_one_hot_i[3];
assign data_masked[230] = data_i[230] & sel_one_hot_i[3];
assign data_masked[229] = data_i[229] & sel_one_hot_i[3];
assign data_masked[228] = data_i[228] & sel_one_hot_i[3];
assign data_masked[379] = data_i[379] & sel_one_hot_i[4];
assign data_masked[378] = data_i[378] & sel_one_hot_i[4];
assign data_masked[377] = data_i[377] & sel_one_hot_i[4];
assign data_masked[376] = data_i[376] & sel_one_hot_i[4];
assign data_masked[375] = data_i[375] & sel_one_hot_i[4];
assign data_masked[374] = data_i[374] & sel_one_hot_i[4];
assign data_masked[373] = data_i[373] & sel_one_hot_i[4];
assign data_masked[372] = data_i[372] & sel_one_hot_i[4];
assign data_masked[371] = data_i[371] & sel_one_hot_i[4];
assign data_masked[370] = data_i[370] & sel_one_hot_i[4];
assign data_masked[369] = data_i[369] & sel_one_hot_i[4];
assign data_masked[368] = data_i[368] & sel_one_hot_i[4];
assign data_masked[367] = data_i[367] & sel_one_hot_i[4];
assign data_masked[366] = data_i[366] & sel_one_hot_i[4];
assign data_masked[365] = data_i[365] & sel_one_hot_i[4];
assign data_masked[364] = data_i[364] & sel_one_hot_i[4];
assign data_masked[363] = data_i[363] & sel_one_hot_i[4];
assign data_masked[362] = data_i[362] & sel_one_hot_i[4];
assign data_masked[361] = data_i[361] & sel_one_hot_i[4];
assign data_masked[360] = data_i[360] & sel_one_hot_i[4];
assign data_masked[359] = data_i[359] & sel_one_hot_i[4];
assign data_masked[358] = data_i[358] & sel_one_hot_i[4];
assign data_masked[357] = data_i[357] & sel_one_hot_i[4];
assign data_masked[356] = data_i[356] & sel_one_hot_i[4];
assign data_masked[355] = data_i[355] & sel_one_hot_i[4];
assign data_masked[354] = data_i[354] & sel_one_hot_i[4];
assign data_masked[353] = data_i[353] & sel_one_hot_i[4];
assign data_masked[352] = data_i[352] & sel_one_hot_i[4];
assign data_masked[351] = data_i[351] & sel_one_hot_i[4];
assign data_masked[350] = data_i[350] & sel_one_hot_i[4];
assign data_masked[349] = data_i[349] & sel_one_hot_i[4];
assign data_masked[348] = data_i[348] & sel_one_hot_i[4];
assign data_masked[347] = data_i[347] & sel_one_hot_i[4];
assign data_masked[346] = data_i[346] & sel_one_hot_i[4];
assign data_masked[345] = data_i[345] & sel_one_hot_i[4];
assign data_masked[344] = data_i[344] & sel_one_hot_i[4];
assign data_masked[343] = data_i[343] & sel_one_hot_i[4];
assign data_masked[342] = data_i[342] & sel_one_hot_i[4];
assign data_masked[341] = data_i[341] & sel_one_hot_i[4];
assign data_masked[340] = data_i[340] & sel_one_hot_i[4];
assign data_masked[339] = data_i[339] & sel_one_hot_i[4];
assign data_masked[338] = data_i[338] & sel_one_hot_i[4];
assign data_masked[337] = data_i[337] & sel_one_hot_i[4];
assign data_masked[336] = data_i[336] & sel_one_hot_i[4];
assign data_masked[335] = data_i[335] & sel_one_hot_i[4];
assign data_masked[334] = data_i[334] & sel_one_hot_i[4];
assign data_masked[333] = data_i[333] & sel_one_hot_i[4];
assign data_masked[332] = data_i[332] & sel_one_hot_i[4];
assign data_masked[331] = data_i[331] & sel_one_hot_i[4];
assign data_masked[330] = data_i[330] & sel_one_hot_i[4];
assign data_masked[329] = data_i[329] & sel_one_hot_i[4];
assign data_masked[328] = data_i[328] & sel_one_hot_i[4];
assign data_masked[327] = data_i[327] & sel_one_hot_i[4];
assign data_masked[326] = data_i[326] & sel_one_hot_i[4];
assign data_masked[325] = data_i[325] & sel_one_hot_i[4];
assign data_masked[324] = data_i[324] & sel_one_hot_i[4];
assign data_masked[323] = data_i[323] & sel_one_hot_i[4];
assign data_masked[322] = data_i[322] & sel_one_hot_i[4];
assign data_masked[321] = data_i[321] & sel_one_hot_i[4];
assign data_masked[320] = data_i[320] & sel_one_hot_i[4];
assign data_masked[319] = data_i[319] & sel_one_hot_i[4];
assign data_masked[318] = data_i[318] & sel_one_hot_i[4];
assign data_masked[317] = data_i[317] & sel_one_hot_i[4];
assign data_masked[316] = data_i[316] & sel_one_hot_i[4];
assign data_masked[315] = data_i[315] & sel_one_hot_i[4];
assign data_masked[314] = data_i[314] & sel_one_hot_i[4];
assign data_masked[313] = data_i[313] & sel_one_hot_i[4];
assign data_masked[312] = data_i[312] & sel_one_hot_i[4];
assign data_masked[311] = data_i[311] & sel_one_hot_i[4];
assign data_masked[310] = data_i[310] & sel_one_hot_i[4];
assign data_masked[309] = data_i[309] & sel_one_hot_i[4];
assign data_masked[308] = data_i[308] & sel_one_hot_i[4];
assign data_masked[307] = data_i[307] & sel_one_hot_i[4];
assign data_masked[306] = data_i[306] & sel_one_hot_i[4];
assign data_masked[305] = data_i[305] & sel_one_hot_i[4];
assign data_masked[304] = data_i[304] & sel_one_hot_i[4];
assign data_o[0] = N2 | data_masked[0];
assign N2 = N1 | data_masked[76];
assign N1 = N0 | data_masked[152];
assign N0 = data_masked[304] | data_masked[228];
assign data_o[1] = N5 | data_masked[1];
assign N5 = N4 | data_masked[77];
assign N4 = N3 | data_masked[153];
assign N3 = data_masked[305] | data_masked[229];
assign data_o[2] = N8 | data_masked[2];
assign N8 = N7 | data_masked[78];
assign N7 = N6 | data_masked[154];
assign N6 = data_masked[306] | data_masked[230];
assign data_o[3] = N11 | data_masked[3];
assign N11 = N10 | data_masked[79];
assign N10 = N9 | data_masked[155];
assign N9 = data_masked[307] | data_masked[231];
assign data_o[4] = N14 | data_masked[4];
assign N14 = N13 | data_masked[80];
assign N13 = N12 | data_masked[156];
assign N12 = data_masked[308] | data_masked[232];
assign data_o[5] = N17 | data_masked[5];
assign N17 = N16 | data_masked[81];
assign N16 = N15 | data_masked[157];
assign N15 = data_masked[309] | data_masked[233];
assign data_o[6] = N20 | data_masked[6];
assign N20 = N19 | data_masked[82];
assign N19 = N18 | data_masked[158];
assign N18 = data_masked[310] | data_masked[234];
assign data_o[7] = N23 | data_masked[7];
assign N23 = N22 | data_masked[83];
assign N22 = N21 | data_masked[159];
assign N21 = data_masked[311] | data_masked[235];
assign data_o[8] = N26 | data_masked[8];
assign N26 = N25 | data_masked[84];
assign N25 = N24 | data_masked[160];
assign N24 = data_masked[312] | data_masked[236];
assign data_o[9] = N29 | data_masked[9];
assign N29 = N28 | data_masked[85];
assign N28 = N27 | data_masked[161];
assign N27 = data_masked[313] | data_masked[237];
assign data_o[10] = N32 | data_masked[10];
assign N32 = N31 | data_masked[86];
assign N31 = N30 | data_masked[162];
assign N30 = data_masked[314] | data_masked[238];
assign data_o[11] = N35 | data_masked[11];
assign N35 = N34 | data_masked[87];
assign N34 = N33 | data_masked[163];
assign N33 = data_masked[315] | data_masked[239];
assign data_o[12] = N38 | data_masked[12];
assign N38 = N37 | data_masked[88];
assign N37 = N36 | data_masked[164];
assign N36 = data_masked[316] | data_masked[240];
assign data_o[13] = N41 | data_masked[13];
assign N41 = N40 | data_masked[89];
assign N40 = N39 | data_masked[165];
assign N39 = data_masked[317] | data_masked[241];
assign data_o[14] = N44 | data_masked[14];
assign N44 = N43 | data_masked[90];
assign N43 = N42 | data_masked[166];
assign N42 = data_masked[318] | data_masked[242];
assign data_o[15] = N47 | data_masked[15];
assign N47 = N46 | data_masked[91];
assign N46 = N45 | data_masked[167];
assign N45 = data_masked[319] | data_masked[243];
assign data_o[16] = N50 | data_masked[16];
assign N50 = N49 | data_masked[92];
assign N49 = N48 | data_masked[168];
assign N48 = data_masked[320] | data_masked[244];
assign data_o[17] = N53 | data_masked[17];
assign N53 = N52 | data_masked[93];
assign N52 = N51 | data_masked[169];
assign N51 = data_masked[321] | data_masked[245];
assign data_o[18] = N56 | data_masked[18];
assign N56 = N55 | data_masked[94];
assign N55 = N54 | data_masked[170];
assign N54 = data_masked[322] | data_masked[246];
assign data_o[19] = N59 | data_masked[19];
assign N59 = N58 | data_masked[95];
assign N58 = N57 | data_masked[171];
assign N57 = data_masked[323] | data_masked[247];
assign data_o[20] = N62 | data_masked[20];
assign N62 = N61 | data_masked[96];
assign N61 = N60 | data_masked[172];
assign N60 = data_masked[324] | data_masked[248];
assign data_o[21] = N65 | data_masked[21];
assign N65 = N64 | data_masked[97];
assign N64 = N63 | data_masked[173];
assign N63 = data_masked[325] | data_masked[249];
assign data_o[22] = N68 | data_masked[22];
assign N68 = N67 | data_masked[98];
assign N67 = N66 | data_masked[174];
assign N66 = data_masked[326] | data_masked[250];
assign data_o[23] = N71 | data_masked[23];
assign N71 = N70 | data_masked[99];
assign N70 = N69 | data_masked[175];
assign N69 = data_masked[327] | data_masked[251];
assign data_o[24] = N74 | data_masked[24];
assign N74 = N73 | data_masked[100];
assign N73 = N72 | data_masked[176];
assign N72 = data_masked[328] | data_masked[252];
assign data_o[25] = N77 | data_masked[25];
assign N77 = N76 | data_masked[101];
assign N76 = N75 | data_masked[177];
assign N75 = data_masked[329] | data_masked[253];
assign data_o[26] = N80 | data_masked[26];
assign N80 = N79 | data_masked[102];
assign N79 = N78 | data_masked[178];
assign N78 = data_masked[330] | data_masked[254];
assign data_o[27] = N83 | data_masked[27];
assign N83 = N82 | data_masked[103];
assign N82 = N81 | data_masked[179];
assign N81 = data_masked[331] | data_masked[255];
assign data_o[28] = N86 | data_masked[28];
assign N86 = N85 | data_masked[104];
assign N85 = N84 | data_masked[180];
assign N84 = data_masked[332] | data_masked[256];
assign data_o[29] = N89 | data_masked[29];
assign N89 = N88 | data_masked[105];
assign N88 = N87 | data_masked[181];
assign N87 = data_masked[333] | data_masked[257];
assign data_o[30] = N92 | data_masked[30];
assign N92 = N91 | data_masked[106];
assign N91 = N90 | data_masked[182];
assign N90 = data_masked[334] | data_masked[258];
assign data_o[31] = N95 | data_masked[31];
assign N95 = N94 | data_masked[107];
assign N94 = N93 | data_masked[183];
assign N93 = data_masked[335] | data_masked[259];
assign data_o[32] = N98 | data_masked[32];
assign N98 = N97 | data_masked[108];
assign N97 = N96 | data_masked[184];
assign N96 = data_masked[336] | data_masked[260];
assign data_o[33] = N101 | data_masked[33];
assign N101 = N100 | data_masked[109];
assign N100 = N99 | data_masked[185];
assign N99 = data_masked[337] | data_masked[261];
assign data_o[34] = N104 | data_masked[34];
assign N104 = N103 | data_masked[110];
assign N103 = N102 | data_masked[186];
assign N102 = data_masked[338] | data_masked[262];
assign data_o[35] = N107 | data_masked[35];
assign N107 = N106 | data_masked[111];
assign N106 = N105 | data_masked[187];
assign N105 = data_masked[339] | data_masked[263];
assign data_o[36] = N110 | data_masked[36];
assign N110 = N109 | data_masked[112];
assign N109 = N108 | data_masked[188];
assign N108 = data_masked[340] | data_masked[264];
assign data_o[37] = N113 | data_masked[37];
assign N113 = N112 | data_masked[113];
assign N112 = N111 | data_masked[189];
assign N111 = data_masked[341] | data_masked[265];
assign data_o[38] = N116 | data_masked[38];
assign N116 = N115 | data_masked[114];
assign N115 = N114 | data_masked[190];
assign N114 = data_masked[342] | data_masked[266];
assign data_o[39] = N119 | data_masked[39];
assign N119 = N118 | data_masked[115];
assign N118 = N117 | data_masked[191];
assign N117 = data_masked[343] | data_masked[267];
assign data_o[40] = N122 | data_masked[40];
assign N122 = N121 | data_masked[116];
assign N121 = N120 | data_masked[192];
assign N120 = data_masked[344] | data_masked[268];
assign data_o[41] = N125 | data_masked[41];
assign N125 = N124 | data_masked[117];
assign N124 = N123 | data_masked[193];
assign N123 = data_masked[345] | data_masked[269];
assign data_o[42] = N128 | data_masked[42];
assign N128 = N127 | data_masked[118];
assign N127 = N126 | data_masked[194];
assign N126 = data_masked[346] | data_masked[270];
assign data_o[43] = N131 | data_masked[43];
assign N131 = N130 | data_masked[119];
assign N130 = N129 | data_masked[195];
assign N129 = data_masked[347] | data_masked[271];
assign data_o[44] = N134 | data_masked[44];
assign N134 = N133 | data_masked[120];
assign N133 = N132 | data_masked[196];
assign N132 = data_masked[348] | data_masked[272];
assign data_o[45] = N137 | data_masked[45];
assign N137 = N136 | data_masked[121];
assign N136 = N135 | data_masked[197];
assign N135 = data_masked[349] | data_masked[273];
assign data_o[46] = N140 | data_masked[46];
assign N140 = N139 | data_masked[122];
assign N139 = N138 | data_masked[198];
assign N138 = data_masked[350] | data_masked[274];
assign data_o[47] = N143 | data_masked[47];
assign N143 = N142 | data_masked[123];
assign N142 = N141 | data_masked[199];
assign N141 = data_masked[351] | data_masked[275];
assign data_o[48] = N146 | data_masked[48];
assign N146 = N145 | data_masked[124];
assign N145 = N144 | data_masked[200];
assign N144 = data_masked[352] | data_masked[276];
assign data_o[49] = N149 | data_masked[49];
assign N149 = N148 | data_masked[125];
assign N148 = N147 | data_masked[201];
assign N147 = data_masked[353] | data_masked[277];
assign data_o[50] = N152 | data_masked[50];
assign N152 = N151 | data_masked[126];
assign N151 = N150 | data_masked[202];
assign N150 = data_masked[354] | data_masked[278];
assign data_o[51] = N155 | data_masked[51];
assign N155 = N154 | data_masked[127];
assign N154 = N153 | data_masked[203];
assign N153 = data_masked[355] | data_masked[279];
assign data_o[52] = N158 | data_masked[52];
assign N158 = N157 | data_masked[128];
assign N157 = N156 | data_masked[204];
assign N156 = data_masked[356] | data_masked[280];
assign data_o[53] = N161 | data_masked[53];
assign N161 = N160 | data_masked[129];
assign N160 = N159 | data_masked[205];
assign N159 = data_masked[357] | data_masked[281];
assign data_o[54] = N164 | data_masked[54];
assign N164 = N163 | data_masked[130];
assign N163 = N162 | data_masked[206];
assign N162 = data_masked[358] | data_masked[282];
assign data_o[55] = N167 | data_masked[55];
assign N167 = N166 | data_masked[131];
assign N166 = N165 | data_masked[207];
assign N165 = data_masked[359] | data_masked[283];
assign data_o[56] = N170 | data_masked[56];
assign N170 = N169 | data_masked[132];
assign N169 = N168 | data_masked[208];
assign N168 = data_masked[360] | data_masked[284];
assign data_o[57] = N173 | data_masked[57];
assign N173 = N172 | data_masked[133];
assign N172 = N171 | data_masked[209];
assign N171 = data_masked[361] | data_masked[285];
assign data_o[58] = N176 | data_masked[58];
assign N176 = N175 | data_masked[134];
assign N175 = N174 | data_masked[210];
assign N174 = data_masked[362] | data_masked[286];
assign data_o[59] = N179 | data_masked[59];
assign N179 = N178 | data_masked[135];
assign N178 = N177 | data_masked[211];
assign N177 = data_masked[363] | data_masked[287];
assign data_o[60] = N182 | data_masked[60];
assign N182 = N181 | data_masked[136];
assign N181 = N180 | data_masked[212];
assign N180 = data_masked[364] | data_masked[288];
assign data_o[61] = N185 | data_masked[61];
assign N185 = N184 | data_masked[137];
assign N184 = N183 | data_masked[213];
assign N183 = data_masked[365] | data_masked[289];
assign data_o[62] = N188 | data_masked[62];
assign N188 = N187 | data_masked[138];
assign N187 = N186 | data_masked[214];
assign N186 = data_masked[366] | data_masked[290];
assign data_o[63] = N191 | data_masked[63];
assign N191 = N190 | data_masked[139];
assign N190 = N189 | data_masked[215];
assign N189 = data_masked[367] | data_masked[291];
assign data_o[64] = N194 | data_masked[64];
assign N194 = N193 | data_masked[140];
assign N193 = N192 | data_masked[216];
assign N192 = data_masked[368] | data_masked[292];
assign data_o[65] = N197 | data_masked[65];
assign N197 = N196 | data_masked[141];
assign N196 = N195 | data_masked[217];
assign N195 = data_masked[369] | data_masked[293];
assign data_o[66] = N200 | data_masked[66];
assign N200 = N199 | data_masked[142];
assign N199 = N198 | data_masked[218];
assign N198 = data_masked[370] | data_masked[294];
assign data_o[67] = N203 | data_masked[67];
assign N203 = N202 | data_masked[143];
assign N202 = N201 | data_masked[219];
assign N201 = data_masked[371] | data_masked[295];
assign data_o[68] = N206 | data_masked[68];
assign N206 = N205 | data_masked[144];
assign N205 = N204 | data_masked[220];
assign N204 = data_masked[372] | data_masked[296];
assign data_o[69] = N209 | data_masked[69];
assign N209 = N208 | data_masked[145];
assign N208 = N207 | data_masked[221];
assign N207 = data_masked[373] | data_masked[297];
assign data_o[70] = N212 | data_masked[70];
assign N212 = N211 | data_masked[146];
assign N211 = N210 | data_masked[222];
assign N210 = data_masked[374] | data_masked[298];
assign data_o[71] = N215 | data_masked[71];
assign N215 = N214 | data_masked[147];
assign N214 = N213 | data_masked[223];
assign N213 = data_masked[375] | data_masked[299];
assign data_o[72] = N218 | data_masked[72];
assign N218 = N217 | data_masked[148];
assign N217 = N216 | data_masked[224];
assign N216 = data_masked[376] | data_masked[300];
assign data_o[73] = N221 | data_masked[73];
assign N221 = N220 | data_masked[149];
assign N220 = N219 | data_masked[225];
assign N219 = data_masked[377] | data_masked[301];
assign data_o[74] = N224 | data_masked[74];
assign N224 = N223 | data_masked[150];
assign N223 = N222 | data_masked[226];
assign N222 = data_masked[378] | data_masked[302];
assign data_o[75] = N227 | data_masked[75];
assign N227 = N226 | data_masked[151];
assign N226 = N225 | data_masked[227];
assign N225 = data_masked[379] | data_masked[303];
endmodule |
module bsg_transpose_width_p1_els_p2
(
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_mux_one_hot_width_p76_els_p3
(
data_i,
sel_one_hot_i,
data_o
);
input [227:0] data_i;
input [2:0] sel_one_hot_i;
output [75:0] data_o;
wire [75:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75;
wire [227:0] data_masked;
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_masked[127] = data_i[127] & sel_one_hot_i[1];
assign data_masked[126] = data_i[126] & sel_one_hot_i[1];
assign data_masked[125] = data_i[125] & sel_one_hot_i[1];
assign data_masked[124] = data_i[124] & sel_one_hot_i[1];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[2];
assign data_masked[226] = data_i[226] & sel_one_hot_i[2];
assign data_masked[225] = data_i[225] & sel_one_hot_i[2];
assign data_masked[224] = data_i[224] & sel_one_hot_i[2];
assign data_masked[223] = data_i[223] & sel_one_hot_i[2];
assign data_masked[222] = data_i[222] & sel_one_hot_i[2];
assign data_masked[221] = data_i[221] & sel_one_hot_i[2];
assign data_masked[220] = data_i[220] & sel_one_hot_i[2];
assign data_masked[219] = data_i[219] & sel_one_hot_i[2];
assign data_masked[218] = data_i[218] & sel_one_hot_i[2];
assign data_masked[217] = data_i[217] & sel_one_hot_i[2];
assign data_masked[216] = data_i[216] & sel_one_hot_i[2];
assign data_masked[215] = data_i[215] & sel_one_hot_i[2];
assign data_masked[214] = data_i[214] & sel_one_hot_i[2];
assign data_masked[213] = data_i[213] & sel_one_hot_i[2];
assign data_masked[212] = data_i[212] & sel_one_hot_i[2];
assign data_masked[211] = data_i[211] & sel_one_hot_i[2];
assign data_masked[210] = data_i[210] & sel_one_hot_i[2];
assign data_masked[209] = data_i[209] & sel_one_hot_i[2];
assign data_masked[208] = data_i[208] & sel_one_hot_i[2];
assign data_masked[207] = data_i[207] & sel_one_hot_i[2];
assign data_masked[206] = data_i[206] & sel_one_hot_i[2];
assign data_masked[205] = data_i[205] & sel_one_hot_i[2];
assign data_masked[204] = data_i[204] & sel_one_hot_i[2];
assign data_masked[203] = data_i[203] & sel_one_hot_i[2];
assign data_masked[202] = data_i[202] & sel_one_hot_i[2];
assign data_masked[201] = data_i[201] & sel_one_hot_i[2];
assign data_masked[200] = data_i[200] & sel_one_hot_i[2];
assign data_masked[199] = data_i[199] & sel_one_hot_i[2];
assign data_masked[198] = data_i[198] & sel_one_hot_i[2];
assign data_masked[197] = data_i[197] & sel_one_hot_i[2];
assign data_masked[196] = data_i[196] & sel_one_hot_i[2];
assign data_masked[195] = data_i[195] & sel_one_hot_i[2];
assign data_masked[194] = data_i[194] & sel_one_hot_i[2];
assign data_masked[193] = data_i[193] & sel_one_hot_i[2];
assign data_masked[192] = data_i[192] & sel_one_hot_i[2];
assign data_masked[191] = data_i[191] & sel_one_hot_i[2];
assign data_masked[190] = data_i[190] & sel_one_hot_i[2];
assign data_masked[189] = data_i[189] & sel_one_hot_i[2];
assign data_masked[188] = data_i[188] & sel_one_hot_i[2];
assign data_masked[187] = data_i[187] & sel_one_hot_i[2];
assign data_masked[186] = data_i[186] & sel_one_hot_i[2];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[152] | data_masked[76];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[153] | data_masked[77];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[154] | data_masked[78];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[155] | data_masked[79];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[156] | data_masked[80];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[157] | data_masked[81];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[158] | data_masked[82];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[159] | data_masked[83];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[160] | data_masked[84];
assign data_o[9] = N9 | data_masked[9];
assign N9 = data_masked[161] | data_masked[85];
assign data_o[10] = N10 | data_masked[10];
assign N10 = data_masked[162] | data_masked[86];
assign data_o[11] = N11 | data_masked[11];
assign N11 = data_masked[163] | data_masked[87];
assign data_o[12] = N12 | data_masked[12];
assign N12 = data_masked[164] | data_masked[88];
assign data_o[13] = N13 | data_masked[13];
assign N13 = data_masked[165] | data_masked[89];
assign data_o[14] = N14 | data_masked[14];
assign N14 = data_masked[166] | data_masked[90];
assign data_o[15] = N15 | data_masked[15];
assign N15 = data_masked[167] | data_masked[91];
assign data_o[16] = N16 | data_masked[16];
assign N16 = data_masked[168] | data_masked[92];
assign data_o[17] = N17 | data_masked[17];
assign N17 = data_masked[169] | data_masked[93];
assign data_o[18] = N18 | data_masked[18];
assign N18 = data_masked[170] | data_masked[94];
assign data_o[19] = N19 | data_masked[19];
assign N19 = data_masked[171] | data_masked[95];
assign data_o[20] = N20 | data_masked[20];
assign N20 = data_masked[172] | data_masked[96];
assign data_o[21] = N21 | data_masked[21];
assign N21 = data_masked[173] | data_masked[97];
assign data_o[22] = N22 | data_masked[22];
assign N22 = data_masked[174] | data_masked[98];
assign data_o[23] = N23 | data_masked[23];
assign N23 = data_masked[175] | data_masked[99];
assign data_o[24] = N24 | data_masked[24];
assign N24 = data_masked[176] | data_masked[100];
assign data_o[25] = N25 | data_masked[25];
assign N25 = data_masked[177] | data_masked[101];
assign data_o[26] = N26 | data_masked[26];
assign N26 = data_masked[178] | data_masked[102];
assign data_o[27] = N27 | data_masked[27];
assign N27 = data_masked[179] | data_masked[103];
assign data_o[28] = N28 | data_masked[28];
assign N28 = data_masked[180] | data_masked[104];
assign data_o[29] = N29 | data_masked[29];
assign N29 = data_masked[181] | data_masked[105];
assign data_o[30] = N30 | data_masked[30];
assign N30 = data_masked[182] | data_masked[106];
assign data_o[31] = N31 | data_masked[31];
assign N31 = data_masked[183] | data_masked[107];
assign data_o[32] = N32 | data_masked[32];
assign N32 = data_masked[184] | data_masked[108];
assign data_o[33] = N33 | data_masked[33];
assign N33 = data_masked[185] | data_masked[109];
assign data_o[34] = N34 | data_masked[34];
assign N34 = data_masked[186] | data_masked[110];
assign data_o[35] = N35 | data_masked[35];
assign N35 = data_masked[187] | data_masked[111];
assign data_o[36] = N36 | data_masked[36];
assign N36 = data_masked[188] | data_masked[112];
assign data_o[37] = N37 | data_masked[37];
assign N37 = data_masked[189] | data_masked[113];
assign data_o[38] = N38 | data_masked[38];
assign N38 = data_masked[190] | data_masked[114];
assign data_o[39] = N39 | data_masked[39];
assign N39 = data_masked[191] | data_masked[115];
assign data_o[40] = N40 | data_masked[40];
assign N40 = data_masked[192] | data_masked[116];
assign data_o[41] = N41 | data_masked[41];
assign N41 = data_masked[193] | data_masked[117];
assign data_o[42] = N42 | data_masked[42];
assign N42 = data_masked[194] | data_masked[118];
assign data_o[43] = N43 | data_masked[43];
assign N43 = data_masked[195] | data_masked[119];
assign data_o[44] = N44 | data_masked[44];
assign N44 = data_masked[196] | data_masked[120];
assign data_o[45] = N45 | data_masked[45];
assign N45 = data_masked[197] | data_masked[121];
assign data_o[46] = N46 | data_masked[46];
assign N46 = data_masked[198] | data_masked[122];
assign data_o[47] = N47 | data_masked[47];
assign N47 = data_masked[199] | data_masked[123];
assign data_o[48] = N48 | data_masked[48];
assign N48 = data_masked[200] | data_masked[124];
assign data_o[49] = N49 | data_masked[49];
assign N49 = data_masked[201] | data_masked[125];
assign data_o[50] = N50 | data_masked[50];
assign N50 = data_masked[202] | data_masked[126];
assign data_o[51] = N51 | data_masked[51];
assign N51 = data_masked[203] | data_masked[127];
assign data_o[52] = N52 | data_masked[52];
assign N52 = data_masked[204] | data_masked[128];
assign data_o[53] = N53 | data_masked[53];
assign N53 = data_masked[205] | data_masked[129];
assign data_o[54] = N54 | data_masked[54];
assign N54 = data_masked[206] | data_masked[130];
assign data_o[55] = N55 | data_masked[55];
assign N55 = data_masked[207] | data_masked[131];
assign data_o[56] = N56 | data_masked[56];
assign N56 = data_masked[208] | data_masked[132];
assign data_o[57] = N57 | data_masked[57];
assign N57 = data_masked[209] | data_masked[133];
assign data_o[58] = N58 | data_masked[58];
assign N58 = data_masked[210] | data_masked[134];
assign data_o[59] = N59 | data_masked[59];
assign N59 = data_masked[211] | data_masked[135];
assign data_o[60] = N60 | data_masked[60];
assign N60 = data_masked[212] | data_masked[136];
assign data_o[61] = N61 | data_masked[61];
assign N61 = data_masked[213] | data_masked[137];
assign data_o[62] = N62 | data_masked[62];
assign N62 = data_masked[214] | data_masked[138];
assign data_o[63] = N63 | data_masked[63];
assign N63 = data_masked[215] | data_masked[139];
assign data_o[64] = N64 | data_masked[64];
assign N64 = data_masked[216] | data_masked[140];
assign data_o[65] = N65 | data_masked[65];
assign N65 = data_masked[217] | data_masked[141];
assign data_o[66] = N66 | data_masked[66];
assign N66 = data_masked[218] | data_masked[142];
assign data_o[67] = N67 | data_masked[67];
assign N67 = data_masked[219] | data_masked[143];
assign data_o[68] = N68 | data_masked[68];
assign N68 = data_masked[220] | data_masked[144];
assign data_o[69] = N69 | data_masked[69];
assign N69 = data_masked[221] | data_masked[145];
assign data_o[70] = N70 | data_masked[70];
assign N70 = data_masked[222] | data_masked[146];
assign data_o[71] = N71 | data_masked[71];
assign N71 = data_masked[223] | data_masked[147];
assign data_o[72] = N72 | data_masked[72];
assign N72 = data_masked[224] | data_masked[148];
assign data_o[73] = N73 | data_masked[73];
assign N73 = data_masked[225] | data_masked[149];
assign data_o[74] = N74 | data_masked[74];
assign N74 = data_masked[226] | data_masked[150];
assign data_o[75] = N75 | data_masked[75];
assign N75 = data_masked[227] | data_masked[151];
endmodule |
module alu_imem_addr_width_p10
(
rs1_i,
rs2_i,
pc_plus4_i,
op_i,
result_o,
jalr_addr_o,
jump_now_o
);
input [31:0] rs1_i;
input [31:0] rs2_i;
input [31:0] pc_plus4_i;
input [31:0] op_i;
output [31:0] result_o;
output [9:0] jalr_addr_o;
output jump_now_o;
wire [31:0] result_o,op2,adder_input,shr_out,shl_out,xor_out,and_out,or_out;
wire [9:0] jalr_addr_o;
wire jump_now_o,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,
N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,is_imm_op,N37,sub_not_add,N38,N39,N40,
N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,
N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,
N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,
N101,N102,N103,N104,carry,sign_ex_or_zero,N105,N106,N107,N108,N109,N110,N111,N112,
N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,
N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,
N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,
N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,
N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,
N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,
N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,
N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239,N240,
N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,N255,N256,
N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,N271,N272,
N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,N287,N288,
N289,N290,N291,N292,N293,rs1_eq_rs2,rs1_lt_rs2_unsigned,rs1_lt_rs2_signed,N294,
N295,N296,N297,N298,N299,N300,N301,N302,N303,N304,N305,N306,N307,N308,N309,N310,
N311,N312,N313,N314,N315,N316,N317,N318,N319,N320,N321,N322,N323,N324,N325,N326,
N327,N328,N329,N330,N331,N332,N333,N334,N335,SV2V_UNCONNECTED_1;
wire [4:0] sh_amount;
wire [32:0] sum;
assign { SV2V_UNCONNECTED_1, shr_out } = $signed({ sign_ex_or_zero, rs1_i }) >>> sh_amount;
assign shl_out = rs1_i << sh_amount;
assign N106 = N326 & op_i[5];
assign N107 = op_i[4] & N105;
assign N108 = op_i[2] & op_i[1];
assign N109 = N106 & N107;
assign N110 = N108 & op_i[0];
assign N111 = N109 & N110;
assign N112 = N326 & N327;
assign N113 = N112 & N107;
assign N114 = N113 & N110;
assign N115 = N301 & N147;
assign N116 = N115 & N152;
assign N117 = N116 & N150;
assign N118 = N193 & N167;
assign N119 = N118 & op_i[0];
assign N125 = N121 & N122;
assign N126 = N123 & op_i[28];
assign N127 = N124 & N310;
assign N128 = op_i[13] & N300;
assign N129 = N125 & N126;
assign N130 = N127 & N128;
assign N131 = N106 & N226;
assign N132 = N129 & N130;
assign N133 = N131 & N110;
assign N134 = N132 & N133;
assign N135 = N311 & N147;
assign N136 = N135 & N152;
assign N137 = N136 & N150;
assign N138 = N193 & N175;
assign N139 = N138 & op_i[0];
assign N141 = N311 & N179;
assign N142 = N141 & N152;
assign N143 = N142 & N150;
assign N144 = N193 & N185;
assign N145 = N144 & op_i[0];
assign N147 = N300 & N326;
assign N148 = N327 & op_i[4];
assign N149 = N105 & N331;
assign N150 = op_i[1] & op_i[0];
assign N151 = N304 & N147;
assign N152 = N148 & N149;
assign N153 = N151 & N152;
assign N154 = N153 & N150;
assign N158 = N123 & N155;
assign N159 = N124 & N156;
assign N160 = N157 & op_i[14];
assign N161 = N299 & N300;
assign N162 = N125 & N158;
assign N163 = N159 & N160;
assign N164 = N161 & N106;
assign N165 = N107 & N295;
assign N166 = N162 & N163;
assign N167 = N164 & N165;
assign N168 = N166 & N167;
assign N169 = N168 & op_i[0];
assign N171 = N307 & N147;
assign N172 = N171 & N152;
assign N173 = N172 & N150;
assign N174 = N128 & N106;
assign N175 = N174 & N165;
assign N176 = N166 & N175;
assign N177 = N176 & op_i[0];
assign N179 = op_i[12] & N326;
assign N180 = N307 & N179;
assign N181 = N180 & N152;
assign N182 = N181 & N150;
assign N183 = op_i[13] & op_i[12];
assign N184 = N183 & N106;
assign N185 = N184 & N165;
assign N186 = N166 & N185;
assign N187 = N186 & op_i[0];
assign N189 = N157 & N310;
assign N190 = N299 & op_i[12];
assign N191 = N159 & N189;
assign N192 = N190 & N112;
assign N193 = N162 & N191;
assign N194 = N192 & N165;
assign N195 = N193 & N194;
assign N196 = N195 & op_i[0];
assign N197 = N190 & N106;
assign N198 = N197 & N165;
assign N199 = N193 & N198;
assign N200 = N199 & op_i[0];
assign N202 = N166 & N194;
assign N203 = N202 & op_i[0];
assign N204 = N166 & N198;
assign N205 = N204 & op_i[0];
assign N207 = N121 & op_i[30];
assign N208 = N207 & N158;
assign N209 = N208 & N163;
assign N210 = N209 & N194;
assign N211 = N210 & op_i[0];
assign N212 = N209 & N198;
assign N213 = N212 & op_i[0];
assign N215 = N208 & N191;
assign N216 = N215 & N167;
assign N217 = N216 & op_i[0];
assign N218 = N300 & op_i[6];
assign N219 = op_i[5] & N317;
assign N220 = N105 & op_i[2];
assign N221 = N301 & N218;
assign N222 = N219 & N220;
assign N223 = N221 & N222;
assign N224 = N223 & N150;
assign N225 = op_i[6] & op_i[5];
assign N226 = N317 & op_i[3];
assign N227 = N225 & N226;
assign N228 = N227 & N110;
assign rs1_eq_rs2 = rs1_i == rs2_i;
assign rs1_lt_rs2_unsigned = rs1_i < rs2_i;
assign rs1_lt_rs2_signed = $signed(rs1_i) < $signed(rs2_i);
assign N294 = N317 & N105;
assign N295 = N331 & op_i[1];
assign N296 = N225 & N294;
assign N297 = N296 & N295;
assign N301 = N310 & N299;
assign N302 = N301 & N300;
assign N303 = N301 & op_i[12];
assign N304 = op_i[14] & N299;
assign N305 = N304 & N300;
assign N306 = N304 & op_i[12];
assign N307 = op_i[14] & op_i[13];
assign N308 = N307 & N300;
assign N309 = N307 & op_i[12];
assign N311 = N310 & op_i[13];
assign { N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229 } = { op_i[31:12], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } + pc_plus4_i;
assign { N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261 } = { N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232, N231, N230, N229 } - { 1'b1, 1'b0, 1'b0 };
assign { N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } = { rs1_i[31:31], rs1_i } + { adder_input[31:31], adder_input };
assign { carry, sum } = { N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71 } + sub_not_add;
assign jalr_addr_o[0] = sum[2];
assign jalr_addr_o[1] = sum[3];
assign jalr_addr_o[2] = sum[4];
assign jalr_addr_o[3] = sum[5];
assign jalr_addr_o[4] = sum[6];
assign jalr_addr_o[5] = sum[7];
assign jalr_addr_o[6] = sum[8];
assign jalr_addr_o[7] = sum[9];
assign jalr_addr_o[8] = sum[10];
assign jalr_addr_o[9] = sum[11];
assign op2 = (N10)? { op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:31], op_i[31:20] } :
(N11)? rs2_i : 1'b0;
assign N10 = is_imm_op;
assign N11 = N37;
assign adder_input = (N12)? { N39, N40, N41, N42, N43, N44, N45, N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, N57, N58, N59, N60, N61, N62, N63, N64, N65, N66, N67, N68, N69, N70 } :
(N13)? op2 : 1'b0;
assign N12 = sub_not_add;
assign N13 = N38;
assign sh_amount = (N10)? op_i[24:20] :
(N11)? rs2_i[4:0] : 1'b0;
assign result_o = (N14)? { op_i[31:12], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N15)? { N292, N291, N290, N289, N288, N287, N286, N285, N284, N283, N282, N281, N280, N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N264, N263, N262, N261 } :
(N16)? sum[31:0] :
(N17)? rs1_i :
(N18)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, sum[32:32] } :
(N19)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, N293 } :
(N20)? xor_out :
(N21)? or_out :
(N22)? and_out :
(N23)? shl_out :
(N24)? shr_out :
(N25)? shr_out :
(N26)? sum[31:0] :
(N27)? pc_plus4_i :
(N28)? pc_plus4_i : 1'b0;
assign N14 = N111;
assign N15 = N114;
assign N16 = N120;
assign N17 = N134;
assign N18 = N140;
assign N19 = N146;
assign N20 = N170;
assign N21 = N178;
assign N22 = N188;
assign N23 = N201;
assign N24 = N206;
assign N25 = N214;
assign N26 = N217;
assign N27 = N224;
assign N28 = N228;
assign sub_not_add = (N16)? 1'b0 :
(N18)? 1'b1 :
(N19)? 1'b1 :
(N26)? 1'b1 :
(N27)? 1'b0 : 1'b0;
assign sign_ex_or_zero = (N24)? 1'b0 :
(N25)? rs1_i[31] : 1'b0;
assign N315 = (N29)? rs1_eq_rs2 :
(N30)? N312 :
(N31)? rs1_lt_rs2_signed :
(N32)? N313 :
(N33)? rs1_lt_rs2_unsigned :
(N34)? N314 :
(N35)? 1'b0 : 1'b0;
assign N29 = N302;
assign N30 = N303;
assign N31 = N305;
assign N32 = N306;
assign N33 = N308;
assign N34 = N309;
assign N35 = N311;
assign jump_now_o = (N36)? N315 :
(N298)? 1'b0 : 1'b0;
assign N36 = N297;
assign is_imm_op = N325 | N335;
assign N325 = ~N324;
assign N324 = N322 | N323;
assign N322 = N320 | N321;
assign N320 = N319 | op_i[2];
assign N319 = N318 | op_i[3];
assign N318 = N316 | N317;
assign N316 = op_i[6] | op_i[5];
assign N317 = ~op_i[4];
assign N321 = ~op_i[1];
assign N323 = ~op_i[0];
assign N335 = ~N334;
assign N334 = N333 | N323;
assign N333 = N332 | N321;
assign N332 = N330 | N331;
assign N330 = N329 | op_i[3];
assign N329 = N328 | op_i[4];
assign N328 = N326 | N327;
assign N326 = ~op_i[6];
assign N327 = ~op_i[5];
assign N331 = ~op_i[2];
assign N37 = ~is_imm_op;
assign N38 = ~sub_not_add;
assign N39 = ~op2[31];
assign N40 = ~op2[30];
assign N41 = ~op2[29];
assign N42 = ~op2[28];
assign N43 = ~op2[27];
assign N44 = ~op2[26];
assign N45 = ~op2[25];
assign N46 = ~op2[24];
assign N47 = ~op2[23];
assign N48 = ~op2[22];
assign N49 = ~op2[21];
assign N50 = ~op2[20];
assign N51 = ~op2[19];
assign N52 = ~op2[18];
assign N53 = ~op2[17];
assign N54 = ~op2[16];
assign N55 = ~op2[15];
assign N56 = ~op2[14];
assign N57 = ~op2[13];
assign N58 = ~op2[12];
assign N59 = ~op2[11];
assign N60 = ~op2[10];
assign N61 = ~op2[9];
assign N62 = ~op2[8];
assign N63 = ~op2[7];
assign N64 = ~op2[6];
assign N65 = ~op2[5];
assign N66 = ~op2[4];
assign N67 = ~op2[3];
assign N68 = ~op2[2];
assign N69 = ~op2[1];
assign N70 = ~op2[0];
assign xor_out[31] = rs1_i[31] ^ op2[31];
assign xor_out[30] = rs1_i[30] ^ op2[30];
assign xor_out[29] = rs1_i[29] ^ op2[29];
assign xor_out[28] = rs1_i[28] ^ op2[28];
assign xor_out[27] = rs1_i[27] ^ op2[27];
assign xor_out[26] = rs1_i[26] ^ op2[26];
assign xor_out[25] = rs1_i[25] ^ op2[25];
assign xor_out[24] = rs1_i[24] ^ op2[24];
assign xor_out[23] = rs1_i[23] ^ op2[23];
assign xor_out[22] = rs1_i[22] ^ op2[22];
assign xor_out[21] = rs1_i[21] ^ op2[21];
assign xor_out[20] = rs1_i[20] ^ op2[20];
assign xor_out[19] = rs1_i[19] ^ op2[19];
assign xor_out[18] = rs1_i[18] ^ op2[18];
assign xor_out[17] = rs1_i[17] ^ op2[17];
assign xor_out[16] = rs1_i[16] ^ op2[16];
assign xor_out[15] = rs1_i[15] ^ op2[15];
assign xor_out[14] = rs1_i[14] ^ op2[14];
assign xor_out[13] = rs1_i[13] ^ op2[13];
assign xor_out[12] = rs1_i[12] ^ op2[12];
assign xor_out[11] = rs1_i[11] ^ op2[11];
assign xor_out[10] = rs1_i[10] ^ op2[10];
assign xor_out[9] = rs1_i[9] ^ op2[9];
assign xor_out[8] = rs1_i[8] ^ op2[8];
assign xor_out[7] = rs1_i[7] ^ op2[7];
assign xor_out[6] = rs1_i[6] ^ op2[6];
assign xor_out[5] = rs1_i[5] ^ op2[5];
assign xor_out[4] = rs1_i[4] ^ op2[4];
assign xor_out[3] = rs1_i[3] ^ op2[3];
assign xor_out[2] = rs1_i[2] ^ op2[2];
assign xor_out[1] = rs1_i[1] ^ op2[1];
assign xor_out[0] = rs1_i[0] ^ op2[0];
assign and_out[31] = rs1_i[31] & op2[31];
assign and_out[30] = rs1_i[30] & op2[30];
assign and_out[29] = rs1_i[29] & op2[29];
assign and_out[28] = rs1_i[28] & op2[28];
assign and_out[27] = rs1_i[27] & op2[27];
assign and_out[26] = rs1_i[26] & op2[26];
assign and_out[25] = rs1_i[25] & op2[25];
assign and_out[24] = rs1_i[24] & op2[24];
assign and_out[23] = rs1_i[23] & op2[23];
assign and_out[22] = rs1_i[22] & op2[22];
assign and_out[21] = rs1_i[21] & op2[21];
assign and_out[20] = rs1_i[20] & op2[20];
assign and_out[19] = rs1_i[19] & op2[19];
assign and_out[18] = rs1_i[18] & op2[18];
assign and_out[17] = rs1_i[17] & op2[17];
assign and_out[16] = rs1_i[16] & op2[16];
assign and_out[15] = rs1_i[15] & op2[15];
assign and_out[14] = rs1_i[14] & op2[14];
assign and_out[13] = rs1_i[13] & op2[13];
assign and_out[12] = rs1_i[12] & op2[12];
assign and_out[11] = rs1_i[11] & op2[11];
assign and_out[10] = rs1_i[10] & op2[10];
assign and_out[9] = rs1_i[9] & op2[9];
assign and_out[8] = rs1_i[8] & op2[8];
assign and_out[7] = rs1_i[7] & op2[7];
assign and_out[6] = rs1_i[6] & op2[6];
assign and_out[5] = rs1_i[5] & op2[5];
assign and_out[4] = rs1_i[4] & op2[4];
assign and_out[3] = rs1_i[3] & op2[3];
assign and_out[2] = rs1_i[2] & op2[2];
assign and_out[1] = rs1_i[1] & op2[1];
assign and_out[0] = rs1_i[0] & op2[0];
assign or_out[31] = rs1_i[31] | op2[31];
assign or_out[30] = rs1_i[30] | op2[30];
assign or_out[29] = rs1_i[29] | op2[29];
assign or_out[28] = rs1_i[28] | op2[28];
assign or_out[27] = rs1_i[27] | op2[27];
assign or_out[26] = rs1_i[26] | op2[26];
assign or_out[25] = rs1_i[25] | op2[25];
assign or_out[24] = rs1_i[24] | op2[24];
assign or_out[23] = rs1_i[23] | op2[23];
assign or_out[22] = rs1_i[22] | op2[22];
assign or_out[21] = rs1_i[21] | op2[21];
assign or_out[20] = rs1_i[20] | op2[20];
assign or_out[19] = rs1_i[19] | op2[19];
assign or_out[18] = rs1_i[18] | op2[18];
assign or_out[17] = rs1_i[17] | op2[17];
assign or_out[16] = rs1_i[16] | op2[16];
assign or_out[15] = rs1_i[15] | op2[15];
assign or_out[14] = rs1_i[14] | op2[14];
assign or_out[13] = rs1_i[13] | op2[13];
assign or_out[12] = rs1_i[12] | op2[12];
assign or_out[11] = rs1_i[11] | op2[11];
assign or_out[10] = rs1_i[10] | op2[10];
assign or_out[9] = rs1_i[9] | op2[9];
assign or_out[8] = rs1_i[8] | op2[8];
assign or_out[7] = rs1_i[7] | op2[7];
assign or_out[6] = rs1_i[6] | op2[6];
assign or_out[5] = rs1_i[5] | op2[5];
assign or_out[4] = rs1_i[4] | op2[4];
assign or_out[3] = rs1_i[3] | op2[3];
assign or_out[2] = rs1_i[2] | op2[2];
assign or_out[1] = rs1_i[1] | op2[1];
assign or_out[0] = rs1_i[0] | op2[0];
assign N105 = ~op_i[3];
assign N120 = N117 | N119;
assign N121 = ~op_i[31];
assign N122 = ~op_i[30];
assign N123 = ~op_i[29];
assign N124 = ~op_i[27];
assign N140 = N137 | N139;
assign N146 = N143 | N145;
assign N155 = ~op_i[28];
assign N156 = ~op_i[26];
assign N157 = ~op_i[25];
assign N170 = N154 | N169;
assign N178 = N173 | N177;
assign N188 = N182 | N187;
assign N201 = N196 | N200;
assign N206 = N203 | N205;
assign N214 = N211 | N213;
assign N293 = ~carry;
assign N298 = ~N297;
assign N299 = ~op_i[13];
assign N300 = ~op_i[12];
assign N310 = ~op_i[14];
assign N312 = ~rs1_eq_rs2;
assign N313 = ~rs1_lt_rs2_signed;
assign N314 = ~rs1_lt_rs2_unsigned;
endmodule |
module bsg_xnor_width_p33
(
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] ^ b_i[32];
assign o[31] = ~N1;
assign N1 = a_i[31] ^ b_i[31];
assign o[30] = ~N2;
assign N2 = a_i[30] ^ b_i[30];
assign o[29] = ~N3;
assign N3 = a_i[29] ^ b_i[29];
assign o[28] = ~N4;
assign N4 = a_i[28] ^ b_i[28];
assign o[27] = ~N5;
assign N5 = a_i[27] ^ b_i[27];
assign o[26] = ~N6;
assign N6 = a_i[26] ^ b_i[26];
assign o[25] = ~N7;
assign N7 = a_i[25] ^ b_i[25];
assign o[24] = ~N8;
assign N8 = a_i[24] ^ b_i[24];
assign o[23] = ~N9;
assign N9 = a_i[23] ^ b_i[23];
assign o[22] = ~N10;
assign N10 = a_i[22] ^ b_i[22];
assign o[21] = ~N11;
assign N11 = a_i[21] ^ b_i[21];
assign o[20] = ~N12;
assign N12 = a_i[20] ^ b_i[20];
assign o[19] = ~N13;
assign N13 = a_i[19] ^ b_i[19];
assign o[18] = ~N14;
assign N14 = a_i[18] ^ b_i[18];
assign o[17] = ~N15;
assign N15 = a_i[17] ^ b_i[17];
assign o[16] = ~N16;
assign N16 = a_i[16] ^ b_i[16];
assign o[15] = ~N17;
assign N17 = a_i[15] ^ b_i[15];
assign o[14] = ~N18;
assign N18 = a_i[14] ^ b_i[14];
assign o[13] = ~N19;
assign N19 = a_i[13] ^ b_i[13];
assign o[12] = ~N20;
assign N20 = a_i[12] ^ b_i[12];
assign o[11] = ~N21;
assign N21 = a_i[11] ^ b_i[11];
assign o[10] = ~N22;
assign N22 = a_i[10] ^ b_i[10];
assign o[9] = ~N23;
assign N23 = a_i[9] ^ b_i[9];
assign o[8] = ~N24;
assign N24 = a_i[8] ^ b_i[8];
assign o[7] = ~N25;
assign N25 = a_i[7] ^ b_i[7];
assign o[6] = ~N26;
assign N26 = a_i[6] ^ b_i[6];
assign o[5] = ~N27;
assign N27 = a_i[5] ^ b_i[5];
assign o[4] = ~N28;
assign N28 = a_i[4] ^ b_i[4];
assign o[3] = ~N29;
assign N29 = a_i[3] ^ b_i[3];
assign o[2] = ~N30;
assign N30 = a_i[2] ^ b_i[2];
assign o[1] = ~N31;
assign N31 = a_i[1] ^ b_i[1];
assign o[0] = ~N32;
assign N32 = a_i[0] ^ b_i[0];
endmodule |
module bsg_scan_2_1_1
(
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[0] = i[0] | 1'b0;
assign o[1] = i[1] | i[0];
endmodule |
module bsg_mux_one_hot_width_p32_els_p1
(
data_i,
sel_one_hot_i,
data_o
);
input [31:0] data_i;
input [0:0] sel_one_hot_i;
output [31:0] data_o;
wire [31:0] data_o;
assign data_o[31] = data_i[31] & sel_one_hot_i[0];
assign data_o[30] = data_i[30] & sel_one_hot_i[0];
assign data_o[29] = data_i[29] & sel_one_hot_i[0];
assign data_o[28] = data_i[28] & sel_one_hot_i[0];
assign data_o[27] = data_i[27] & sel_one_hot_i[0];
assign data_o[26] = data_i[26] & sel_one_hot_i[0];
assign data_o[25] = data_i[25] & sel_one_hot_i[0];
assign data_o[24] = data_i[24] & sel_one_hot_i[0];
assign data_o[23] = data_i[23] & sel_one_hot_i[0];
assign data_o[22] = data_i[22] & sel_one_hot_i[0];
assign data_o[21] = data_i[21] & sel_one_hot_i[0];
assign data_o[20] = data_i[20] & sel_one_hot_i[0];
assign data_o[19] = data_i[19] & sel_one_hot_i[0];
assign data_o[18] = data_i[18] & sel_one_hot_i[0];
assign data_o[17] = data_i[17] & sel_one_hot_i[0];
assign data_o[16] = data_i[16] & sel_one_hot_i[0];
assign data_o[15] = data_i[15] & sel_one_hot_i[0];
assign data_o[14] = data_i[14] & sel_one_hot_i[0];
assign data_o[13] = data_i[13] & sel_one_hot_i[0];
assign data_o[12] = data_i[12] & sel_one_hot_i[0];
assign data_o[11] = data_i[11] & sel_one_hot_i[0];
assign data_o[10] = data_i[10] & sel_one_hot_i[0];
assign data_o[9] = data_i[9] & sel_one_hot_i[0];
assign data_o[8] = data_i[8] & sel_one_hot_i[0];
assign data_o[7] = data_i[7] & sel_one_hot_i[0];
assign data_o[6] = data_i[6] & sel_one_hot_i[0];
assign data_o[5] = data_i[5] & sel_one_hot_i[0];
assign data_o[4] = data_i[4] & sel_one_hot_i[0];
assign data_o[3] = data_i[3] & sel_one_hot_i[0];
assign data_o[2] = data_i[2] & sel_one_hot_i[0];
assign data_o[1] = data_i[1] & sel_one_hot_i[0];
assign data_o[0] = data_i[0] & sel_one_hot_i[0];
endmodule |
module bsg_nor2_width_p33
(
a_i,
b_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign o[32] = ~N0;
assign N0 = a_i[32] | b_i[32];
assign o[31] = ~N1;
assign N1 = a_i[31] | b_i[31];
assign o[30] = ~N2;
assign N2 = a_i[30] | b_i[30];
assign o[29] = ~N3;
assign N3 = a_i[29] | b_i[29];
assign o[28] = ~N4;
assign N4 = a_i[28] | b_i[28];
assign o[27] = ~N5;
assign N5 = a_i[27] | b_i[27];
assign o[26] = ~N6;
assign N6 = a_i[26] | b_i[26];
assign o[25] = ~N7;
assign N7 = a_i[25] | b_i[25];
assign o[24] = ~N8;
assign N8 = a_i[24] | b_i[24];
assign o[23] = ~N9;
assign N9 = a_i[23] | b_i[23];
assign o[22] = ~N10;
assign N10 = a_i[22] | b_i[22];
assign o[21] = ~N11;
assign N11 = a_i[21] | b_i[21];
assign o[20] = ~N12;
assign N12 = a_i[20] | b_i[20];
assign o[19] = ~N13;
assign N13 = a_i[19] | b_i[19];
assign o[18] = ~N14;
assign N14 = a_i[18] | b_i[18];
assign o[17] = ~N15;
assign N15 = a_i[17] | b_i[17];
assign o[16] = ~N16;
assign N16 = a_i[16] | b_i[16];
assign o[15] = ~N17;
assign N17 = a_i[15] | b_i[15];
assign o[14] = ~N18;
assign N18 = a_i[14] | b_i[14];
assign o[13] = ~N19;
assign N19 = a_i[13] | b_i[13];
assign o[12] = ~N20;
assign N20 = a_i[12] | b_i[12];
assign o[11] = ~N21;
assign N21 = a_i[11] | b_i[11];
assign o[10] = ~N22;
assign N22 = a_i[10] | b_i[10];
assign o[9] = ~N23;
assign N23 = a_i[9] | b_i[9];
assign o[8] = ~N24;
assign N24 = a_i[8] | b_i[8];
assign o[7] = ~N25;
assign N25 = a_i[7] | b_i[7];
assign o[6] = ~N26;
assign N26 = a_i[6] | b_i[6];
assign o[5] = ~N27;
assign N27 = a_i[5] | b_i[5];
assign o[4] = ~N28;
assign N28 = a_i[4] | b_i[4];
assign o[3] = ~N29;
assign N29 = a_i[3] | b_i[3];
assign o[2] = ~N30;
assign N30 = a_i[2] | b_i[2];
assign o[1] = ~N31;
assign N31 = a_i[1] | b_i[1];
assign o[0] = ~N32;
assign N32 = a_i[0] | b_i[0];
endmodule |
module bsg_buf_ctrl_width_p33
(
i,
o
);
output [32:0] o;
input i;
wire [32:0] o;
wire i;
assign o[0] = i;
assign o[1] = i;
assign o[2] = i;
assign o[3] = i;
assign o[4] = i;
assign o[5] = i;
assign o[6] = i;
assign o[7] = i;
assign o[8] = i;
assign o[9] = i;
assign o[10] = i;
assign o[11] = i;
assign o[12] = i;
assign o[13] = i;
assign o[14] = i;
assign o[15] = i;
assign o[16] = i;
assign o[17] = i;
assign o[18] = i;
assign o[19] = i;
assign o[20] = i;
assign o[21] = i;
assign o[22] = i;
assign o[23] = i;
assign o[24] = i;
assign o[25] = i;
assign o[26] = i;
assign o[27] = i;
assign o[28] = i;
assign o[29] = i;
assign o[30] = i;
assign o[31] = i;
assign o[32] = i;
endmodule |
module bsg_mux_one_hot_width_p4_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [7:0] data_i;
input [1:0] sel_one_hot_i;
output [3:0] data_o;
wire [3:0] data_o;
wire [7:0] data_masked;
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[1];
assign data_masked[6] = data_i[6] & sel_one_hot_i[1];
assign data_masked[5] = data_i[5] & sel_one_hot_i[1];
assign data_masked[4] = data_i[4] & sel_one_hot_i[1];
assign data_o[0] = data_masked[4] | data_masked[0];
assign data_o[1] = data_masked[5] | data_masked[1];
assign data_o[2] = data_masked[6] | data_masked[2];
assign data_o[3] = data_masked[7] | data_masked[3];
endmodule |
module bsg_transpose_width_p2_els_p1
(
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_dff_reset_width_p32_harden_p1
(
clock_i,
data_i,
reset_i,
data_o
);
input [31:0] data_i;
output [31:0] data_o;
input clock_i;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34;
reg [31:0] data_o;
always @(posedge clock_i) begin
if(1'b1) begin
data_o[31] <= N34;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[30] <= N33;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[29] <= N32;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[28] <= N31;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[27] <= N30;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[26] <= N29;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[25] <= N28;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[24] <= N27;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[23] <= N26;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[22] <= N25;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[21] <= N24;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[20] <= N23;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[19] <= N22;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[18] <= N21;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[17] <= N20;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[16] <= N19;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[15] <= N18;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[14] <= N17;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[13] <= N16;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[12] <= N15;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[11] <= N14;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[10] <= N13;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[9] <= N12;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[8] <= N11;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[7] <= N10;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[6] <= N9;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[5] <= N8;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[4] <= N7;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[3] <= N6;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[2] <= N5;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[1] <= N4;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[0] <= N3;
end
end
assign { N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_mesh_router_dor_decoder_4_5_5_1
(
clk_i,
v_i,
x_dirs_i,
y_dirs_i,
my_x_i,
my_y_i,
req_o
);
input [4:0] v_i;
input [19:0] x_dirs_i;
input [24:0] y_dirs_i;
input [3:0] my_x_i;
input [4:0] my_y_i;
output [24:0] req_o;
input clk_i;
wire [24:0] req_o;
wire x_eq_4,x_gt_0,NS_req_4__weird_route,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,
N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
wire [2:0] x_eq,y_gt,y_lt;
wire [4:0] y_eq;
wire [4:3] x_gt;
wire [0:0] x_lt;
assign req_o[24] = 1'b0;
assign req_o[18] = 1'b0;
assign req_o[12] = 1'b0;
assign req_o[6] = 1'b0;
assign x_eq[0] = x_dirs_i[3:0] == my_x_i;
assign y_eq[0] = y_dirs_i[4:0] == my_y_i;
assign x_gt_0 = x_dirs_i[3:0] > my_x_i;
assign y_gt[0] = y_dirs_i[4:0] > my_y_i;
assign x_eq[1] = x_dirs_i[7:4] == my_x_i;
assign y_eq[1] = y_dirs_i[9:5] == my_y_i;
assign y_gt[1] = y_dirs_i[9:5] > my_y_i;
assign x_eq[2] = x_dirs_i[11:8] == my_x_i;
assign y_eq[2] = y_dirs_i[14:10] == my_y_i;
assign y_gt[2] = y_dirs_i[14:10] > my_y_i;
assign y_eq[3] = y_dirs_i[19:15] == my_y_i;
assign x_gt[3] = x_dirs_i[15:12] > my_x_i;
assign x_eq_4 = x_dirs_i[19:16] == my_x_i;
assign y_eq[4] = y_dirs_i[24:20] == my_y_i;
assign x_gt[4] = x_dirs_i[19:16] > my_x_i;
assign x_lt[0] = N0 & N1;
assign N0 = ~x_gt_0;
assign N1 = ~x_eq[0];
assign y_lt[0] = N2 & N3;
assign N2 = ~y_gt[0];
assign N3 = ~y_eq[0];
assign y_lt[1] = N4 & N5;
assign N4 = ~y_gt[1];
assign N5 = ~y_eq[1];
assign y_lt[2] = N6 & N7;
assign N6 = ~y_gt[2];
assign N7 = ~y_eq[2];
assign req_o[7] = v_i[1] & N8;
assign N8 = ~x_eq[1];
assign req_o[5] = N9 & y_eq[1];
assign N9 = v_i[1] & x_eq[1];
assign req_o[9] = N10 & y_gt[1];
assign N10 = v_i[1] & x_eq[1];
assign req_o[8] = N11 & y_lt[1];
assign N11 = v_i[1] & x_eq[1];
assign req_o[11] = v_i[2] & N12;
assign N12 = ~x_eq[2];
assign req_o[10] = N13 & y_eq[2];
assign N13 = v_i[2] & x_eq[2];
assign req_o[14] = N14 & y_gt[2];
assign N14 = v_i[2] & x_eq[2];
assign req_o[13] = N15 & y_lt[2];
assign N15 = v_i[2] & x_eq[2];
assign req_o[19] = N17 & N18;
assign N17 = v_i[3] & N16;
assign N16 = ~y_eq[3];
assign N18 = ~1'b0;
assign req_o[15] = N19 & N18;
assign N19 = v_i[3] & y_eq[3];
assign req_o[16] = N20 & N21;
assign N20 = v_i[3] & 1'b0;
assign N21 = ~x_gt[3];
assign req_o[17] = N22 & x_gt[3];
assign N22 = v_i[3] & 1'b0;
assign NS_req_4__weird_route = ~x_eq_4;
assign req_o[23] = N24 & N25;
assign N24 = v_i[4] & N23;
assign N23 = ~y_eq[4];
assign N25 = ~NS_req_4__weird_route;
assign req_o[20] = N26 & N25;
assign N26 = v_i[4] & y_eq[4];
assign req_o[21] = N27 & N28;
assign N27 = v_i[4] & NS_req_4__weird_route;
assign N28 = ~x_gt[4];
assign req_o[22] = N29 & x_gt[4];
assign N29 = v_i[4] & NS_req_4__weird_route;
assign req_o[2] = v_i[0] & x_gt_0;
assign req_o[1] = v_i[0] & x_lt[0];
assign req_o[4] = N30 & y_gt[0];
assign N30 = v_i[0] & x_eq[0];
assign req_o[3] = N31 & y_lt[0];
assign N31 = v_i[0] & x_eq[0];
assign req_o[0] = N32 & y_eq[0];
assign N32 = v_i[0] & x_eq[0];
endmodule |
module bsg_mux_one_hot_width_p10_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [19:0] data_i;
input [1:0] sel_one_hot_i;
output [9:0] data_o;
wire [9:0] data_o;
wire [19:0] data_masked;
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[1];
assign data_masked[18] = data_i[18] & sel_one_hot_i[1];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_o[0] = data_masked[10] | data_masked[0];
assign data_o[1] = data_masked[11] | data_masked[1];
assign data_o[2] = data_masked[12] | data_masked[2];
assign data_o[3] = data_masked[13] | data_masked[3];
assign data_o[4] = data_masked[14] | data_masked[4];
assign data_o[5] = data_masked[15] | data_masked[5];
assign data_o[6] = data_masked[16] | data_masked[6];
assign data_o[7] = data_masked[17] | data_masked[7];
assign data_o[8] = data_masked[18] | data_masked[8];
assign data_o[9] = data_masked[19] | data_masked[9];
endmodule |
module bsg_circular_ptr_slots_p4_max_add_p1
(
clk,
reset_i,
add_i,
o
);
input [0:0] add_i;
output [1:0] o;
input clk;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7;
wire [1:0] genblk1_genblk1_ptr_r_p1;
reg [1:0] o;
always @(posedge clk) begin
if(N7) begin
o[1] <= N4;
end
end
always @(posedge clk) begin
if(N7) begin
o[0] <= N3;
end
end
assign genblk1_genblk1_ptr_r_p1 = o + 1'b1;
assign { N4, N3 } = (N0)? { 1'b0, 1'b0 } :
(N1)? genblk1_genblk1_ptr_r_p1 : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
assign N5 = ~add_i[0];
assign N6 = N5 & N2;
assign N7 = ~N6;
endmodule |
module bsg_dff_en_width_p1
(
clock_i,
data_i,
en_i,
data_o
);
input [0:0] data_i;
output [0:0] data_o;
input clock_i;
input en_i;
reg [0:0] data_o;
always @(posedge clock_i) begin
if(en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule |
module bsg_mux_one_hot_width_p1_els_p2
(
data_i,
sel_one_hot_i,
data_o
);
input [1:0] data_i;
input [1:0] sel_one_hot_i;
output [0:0] data_o;
wire [0:0] data_o;
wire [1:0] data_masked;
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[1];
assign data_o[0] = data_masked[1] | data_masked[0];
endmodule |
module bsg_mux_one_hot_width_p76_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [303:0] data_i;
input [3:0] sel_one_hot_i;
output [75:0] data_o;
wire [75:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,N78,N79,N80,N81,
N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,N98,N99,N100,N101,
N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,N114,N115,N116,N117,
N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,N130,N131,N132,N133,
N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,N146,N147,N148,N149,
N150,N151;
wire [303:0] data_masked;
assign data_masked[75] = data_i[75] & sel_one_hot_i[0];
assign data_masked[74] = data_i[74] & sel_one_hot_i[0];
assign data_masked[73] = data_i[73] & sel_one_hot_i[0];
assign data_masked[72] = data_i[72] & sel_one_hot_i[0];
assign data_masked[71] = data_i[71] & sel_one_hot_i[0];
assign data_masked[70] = data_i[70] & sel_one_hot_i[0];
assign data_masked[69] = data_i[69] & sel_one_hot_i[0];
assign data_masked[68] = data_i[68] & sel_one_hot_i[0];
assign data_masked[67] = data_i[67] & sel_one_hot_i[0];
assign data_masked[66] = data_i[66] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[0];
assign data_masked[64] = data_i[64] & sel_one_hot_i[0];
assign data_masked[63] = data_i[63] & sel_one_hot_i[0];
assign data_masked[62] = data_i[62] & sel_one_hot_i[0];
assign data_masked[61] = data_i[61] & sel_one_hot_i[0];
assign data_masked[60] = data_i[60] & sel_one_hot_i[0];
assign data_masked[59] = data_i[59] & sel_one_hot_i[0];
assign data_masked[58] = data_i[58] & sel_one_hot_i[0];
assign data_masked[57] = data_i[57] & sel_one_hot_i[0];
assign data_masked[56] = data_i[56] & sel_one_hot_i[0];
assign data_masked[55] = data_i[55] & sel_one_hot_i[0];
assign data_masked[54] = data_i[54] & sel_one_hot_i[0];
assign data_masked[53] = data_i[53] & sel_one_hot_i[0];
assign data_masked[52] = data_i[52] & sel_one_hot_i[0];
assign data_masked[51] = data_i[51] & sel_one_hot_i[0];
assign data_masked[50] = data_i[50] & sel_one_hot_i[0];
assign data_masked[49] = data_i[49] & sel_one_hot_i[0];
assign data_masked[48] = data_i[48] & sel_one_hot_i[0];
assign data_masked[47] = data_i[47] & sel_one_hot_i[0];
assign data_masked[46] = data_i[46] & sel_one_hot_i[0];
assign data_masked[45] = data_i[45] & sel_one_hot_i[0];
assign data_masked[44] = data_i[44] & sel_one_hot_i[0];
assign data_masked[43] = data_i[43] & sel_one_hot_i[0];
assign data_masked[42] = data_i[42] & sel_one_hot_i[0];
assign data_masked[41] = data_i[41] & sel_one_hot_i[0];
assign data_masked[40] = data_i[40] & sel_one_hot_i[0];
assign data_masked[39] = data_i[39] & sel_one_hot_i[0];
assign data_masked[38] = data_i[38] & sel_one_hot_i[0];
assign data_masked[37] = data_i[37] & sel_one_hot_i[0];
assign data_masked[36] = data_i[36] & sel_one_hot_i[0];
assign data_masked[35] = data_i[35] & sel_one_hot_i[0];
assign data_masked[34] = data_i[34] & sel_one_hot_i[0];
assign data_masked[33] = data_i[33] & sel_one_hot_i[0];
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[151] = data_i[151] & sel_one_hot_i[1];
assign data_masked[150] = data_i[150] & sel_one_hot_i[1];
assign data_masked[149] = data_i[149] & sel_one_hot_i[1];
assign data_masked[148] = data_i[148] & sel_one_hot_i[1];
assign data_masked[147] = data_i[147] & sel_one_hot_i[1];
assign data_masked[146] = data_i[146] & sel_one_hot_i[1];
assign data_masked[145] = data_i[145] & sel_one_hot_i[1];
assign data_masked[144] = data_i[144] & sel_one_hot_i[1];
assign data_masked[143] = data_i[143] & sel_one_hot_i[1];
assign data_masked[142] = data_i[142] & sel_one_hot_i[1];
assign data_masked[141] = data_i[141] & sel_one_hot_i[1];
assign data_masked[140] = data_i[140] & sel_one_hot_i[1];
assign data_masked[139] = data_i[139] & sel_one_hot_i[1];
assign data_masked[138] = data_i[138] & sel_one_hot_i[1];
assign data_masked[137] = data_i[137] & sel_one_hot_i[1];
assign data_masked[136] = data_i[136] & sel_one_hot_i[1];
assign data_masked[135] = data_i[135] & sel_one_hot_i[1];
assign data_masked[134] = data_i[134] & sel_one_hot_i[1];
assign data_masked[133] = data_i[133] & sel_one_hot_i[1];
assign data_masked[132] = data_i[132] & sel_one_hot_i[1];
assign data_masked[131] = data_i[131] & sel_one_hot_i[1];
assign data_masked[130] = data_i[130] & sel_one_hot_i[1];
assign data_masked[129] = data_i[129] & sel_one_hot_i[1];
assign data_masked[128] = data_i[128] & sel_one_hot_i[1];
assign data_masked[127] = data_i[127] & sel_one_hot_i[1];
assign data_masked[126] = data_i[126] & sel_one_hot_i[1];
assign data_masked[125] = data_i[125] & sel_one_hot_i[1];
assign data_masked[124] = data_i[124] & sel_one_hot_i[1];
assign data_masked[123] = data_i[123] & sel_one_hot_i[1];
assign data_masked[122] = data_i[122] & sel_one_hot_i[1];
assign data_masked[121] = data_i[121] & sel_one_hot_i[1];
assign data_masked[120] = data_i[120] & sel_one_hot_i[1];
assign data_masked[119] = data_i[119] & sel_one_hot_i[1];
assign data_masked[118] = data_i[118] & sel_one_hot_i[1];
assign data_masked[117] = data_i[117] & sel_one_hot_i[1];
assign data_masked[116] = data_i[116] & sel_one_hot_i[1];
assign data_masked[115] = data_i[115] & sel_one_hot_i[1];
assign data_masked[114] = data_i[114] & sel_one_hot_i[1];
assign data_masked[113] = data_i[113] & sel_one_hot_i[1];
assign data_masked[112] = data_i[112] & sel_one_hot_i[1];
assign data_masked[111] = data_i[111] & sel_one_hot_i[1];
assign data_masked[110] = data_i[110] & sel_one_hot_i[1];
assign data_masked[109] = data_i[109] & sel_one_hot_i[1];
assign data_masked[108] = data_i[108] & sel_one_hot_i[1];
assign data_masked[107] = data_i[107] & sel_one_hot_i[1];
assign data_masked[106] = data_i[106] & sel_one_hot_i[1];
assign data_masked[105] = data_i[105] & sel_one_hot_i[1];
assign data_masked[104] = data_i[104] & sel_one_hot_i[1];
assign data_masked[103] = data_i[103] & sel_one_hot_i[1];
assign data_masked[102] = data_i[102] & sel_one_hot_i[1];
assign data_masked[101] = data_i[101] & sel_one_hot_i[1];
assign data_masked[100] = data_i[100] & sel_one_hot_i[1];
assign data_masked[99] = data_i[99] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[1];
assign data_masked[97] = data_i[97] & sel_one_hot_i[1];
assign data_masked[96] = data_i[96] & sel_one_hot_i[1];
assign data_masked[95] = data_i[95] & sel_one_hot_i[1];
assign data_masked[94] = data_i[94] & sel_one_hot_i[1];
assign data_masked[93] = data_i[93] & sel_one_hot_i[1];
assign data_masked[92] = data_i[92] & sel_one_hot_i[1];
assign data_masked[91] = data_i[91] & sel_one_hot_i[1];
assign data_masked[90] = data_i[90] & sel_one_hot_i[1];
assign data_masked[89] = data_i[89] & sel_one_hot_i[1];
assign data_masked[88] = data_i[88] & sel_one_hot_i[1];
assign data_masked[87] = data_i[87] & sel_one_hot_i[1];
assign data_masked[86] = data_i[86] & sel_one_hot_i[1];
assign data_masked[85] = data_i[85] & sel_one_hot_i[1];
assign data_masked[84] = data_i[84] & sel_one_hot_i[1];
assign data_masked[83] = data_i[83] & sel_one_hot_i[1];
assign data_masked[82] = data_i[82] & sel_one_hot_i[1];
assign data_masked[81] = data_i[81] & sel_one_hot_i[1];
assign data_masked[80] = data_i[80] & sel_one_hot_i[1];
assign data_masked[79] = data_i[79] & sel_one_hot_i[1];
assign data_masked[78] = data_i[78] & sel_one_hot_i[1];
assign data_masked[77] = data_i[77] & sel_one_hot_i[1];
assign data_masked[76] = data_i[76] & sel_one_hot_i[1];
assign data_masked[227] = data_i[227] & sel_one_hot_i[2];
assign data_masked[226] = data_i[226] & sel_one_hot_i[2];
assign data_masked[225] = data_i[225] & sel_one_hot_i[2];
assign data_masked[224] = data_i[224] & sel_one_hot_i[2];
assign data_masked[223] = data_i[223] & sel_one_hot_i[2];
assign data_masked[222] = data_i[222] & sel_one_hot_i[2];
assign data_masked[221] = data_i[221] & sel_one_hot_i[2];
assign data_masked[220] = data_i[220] & sel_one_hot_i[2];
assign data_masked[219] = data_i[219] & sel_one_hot_i[2];
assign data_masked[218] = data_i[218] & sel_one_hot_i[2];
assign data_masked[217] = data_i[217] & sel_one_hot_i[2];
assign data_masked[216] = data_i[216] & sel_one_hot_i[2];
assign data_masked[215] = data_i[215] & sel_one_hot_i[2];
assign data_masked[214] = data_i[214] & sel_one_hot_i[2];
assign data_masked[213] = data_i[213] & sel_one_hot_i[2];
assign data_masked[212] = data_i[212] & sel_one_hot_i[2];
assign data_masked[211] = data_i[211] & sel_one_hot_i[2];
assign data_masked[210] = data_i[210] & sel_one_hot_i[2];
assign data_masked[209] = data_i[209] & sel_one_hot_i[2];
assign data_masked[208] = data_i[208] & sel_one_hot_i[2];
assign data_masked[207] = data_i[207] & sel_one_hot_i[2];
assign data_masked[206] = data_i[206] & sel_one_hot_i[2];
assign data_masked[205] = data_i[205] & sel_one_hot_i[2];
assign data_masked[204] = data_i[204] & sel_one_hot_i[2];
assign data_masked[203] = data_i[203] & sel_one_hot_i[2];
assign data_masked[202] = data_i[202] & sel_one_hot_i[2];
assign data_masked[201] = data_i[201] & sel_one_hot_i[2];
assign data_masked[200] = data_i[200] & sel_one_hot_i[2];
assign data_masked[199] = data_i[199] & sel_one_hot_i[2];
assign data_masked[198] = data_i[198] & sel_one_hot_i[2];
assign data_masked[197] = data_i[197] & sel_one_hot_i[2];
assign data_masked[196] = data_i[196] & sel_one_hot_i[2];
assign data_masked[195] = data_i[195] & sel_one_hot_i[2];
assign data_masked[194] = data_i[194] & sel_one_hot_i[2];
assign data_masked[193] = data_i[193] & sel_one_hot_i[2];
assign data_masked[192] = data_i[192] & sel_one_hot_i[2];
assign data_masked[191] = data_i[191] & sel_one_hot_i[2];
assign data_masked[190] = data_i[190] & sel_one_hot_i[2];
assign data_masked[189] = data_i[189] & sel_one_hot_i[2];
assign data_masked[188] = data_i[188] & sel_one_hot_i[2];
assign data_masked[187] = data_i[187] & sel_one_hot_i[2];
assign data_masked[186] = data_i[186] & sel_one_hot_i[2];
assign data_masked[185] = data_i[185] & sel_one_hot_i[2];
assign data_masked[184] = data_i[184] & sel_one_hot_i[2];
assign data_masked[183] = data_i[183] & sel_one_hot_i[2];
assign data_masked[182] = data_i[182] & sel_one_hot_i[2];
assign data_masked[181] = data_i[181] & sel_one_hot_i[2];
assign data_masked[180] = data_i[180] & sel_one_hot_i[2];
assign data_masked[179] = data_i[179] & sel_one_hot_i[2];
assign data_masked[178] = data_i[178] & sel_one_hot_i[2];
assign data_masked[177] = data_i[177] & sel_one_hot_i[2];
assign data_masked[176] = data_i[176] & sel_one_hot_i[2];
assign data_masked[175] = data_i[175] & sel_one_hot_i[2];
assign data_masked[174] = data_i[174] & sel_one_hot_i[2];
assign data_masked[173] = data_i[173] & sel_one_hot_i[2];
assign data_masked[172] = data_i[172] & sel_one_hot_i[2];
assign data_masked[171] = data_i[171] & sel_one_hot_i[2];
assign data_masked[170] = data_i[170] & sel_one_hot_i[2];
assign data_masked[169] = data_i[169] & sel_one_hot_i[2];
assign data_masked[168] = data_i[168] & sel_one_hot_i[2];
assign data_masked[167] = data_i[167] & sel_one_hot_i[2];
assign data_masked[166] = data_i[166] & sel_one_hot_i[2];
assign data_masked[165] = data_i[165] & sel_one_hot_i[2];
assign data_masked[164] = data_i[164] & sel_one_hot_i[2];
assign data_masked[163] = data_i[163] & sel_one_hot_i[2];
assign data_masked[162] = data_i[162] & sel_one_hot_i[2];
assign data_masked[161] = data_i[161] & sel_one_hot_i[2];
assign data_masked[160] = data_i[160] & sel_one_hot_i[2];
assign data_masked[159] = data_i[159] & sel_one_hot_i[2];
assign data_masked[158] = data_i[158] & sel_one_hot_i[2];
assign data_masked[157] = data_i[157] & sel_one_hot_i[2];
assign data_masked[156] = data_i[156] & sel_one_hot_i[2];
assign data_masked[155] = data_i[155] & sel_one_hot_i[2];
assign data_masked[154] = data_i[154] & sel_one_hot_i[2];
assign data_masked[153] = data_i[153] & sel_one_hot_i[2];
assign data_masked[152] = data_i[152] & sel_one_hot_i[2];
assign data_masked[303] = data_i[303] & sel_one_hot_i[3];
assign data_masked[302] = data_i[302] & sel_one_hot_i[3];
assign data_masked[301] = data_i[301] & sel_one_hot_i[3];
assign data_masked[300] = data_i[300] & sel_one_hot_i[3];
assign data_masked[299] = data_i[299] & sel_one_hot_i[3];
assign data_masked[298] = data_i[298] & sel_one_hot_i[3];
assign data_masked[297] = data_i[297] & sel_one_hot_i[3];
assign data_masked[296] = data_i[296] & sel_one_hot_i[3];
assign data_masked[295] = data_i[295] & sel_one_hot_i[3];
assign data_masked[294] = data_i[294] & sel_one_hot_i[3];
assign data_masked[293] = data_i[293] & sel_one_hot_i[3];
assign data_masked[292] = data_i[292] & sel_one_hot_i[3];
assign data_masked[291] = data_i[291] & sel_one_hot_i[3];
assign data_masked[290] = data_i[290] & sel_one_hot_i[3];
assign data_masked[289] = data_i[289] & sel_one_hot_i[3];
assign data_masked[288] = data_i[288] & sel_one_hot_i[3];
assign data_masked[287] = data_i[287] & sel_one_hot_i[3];
assign data_masked[286] = data_i[286] & sel_one_hot_i[3];
assign data_masked[285] = data_i[285] & sel_one_hot_i[3];
assign data_masked[284] = data_i[284] & sel_one_hot_i[3];
assign data_masked[283] = data_i[283] & sel_one_hot_i[3];
assign data_masked[282] = data_i[282] & sel_one_hot_i[3];
assign data_masked[281] = data_i[281] & sel_one_hot_i[3];
assign data_masked[280] = data_i[280] & sel_one_hot_i[3];
assign data_masked[279] = data_i[279] & sel_one_hot_i[3];
assign data_masked[278] = data_i[278] & sel_one_hot_i[3];
assign data_masked[277] = data_i[277] & sel_one_hot_i[3];
assign data_masked[276] = data_i[276] & sel_one_hot_i[3];
assign data_masked[275] = data_i[275] & sel_one_hot_i[3];
assign data_masked[274] = data_i[274] & sel_one_hot_i[3];
assign data_masked[273] = data_i[273] & sel_one_hot_i[3];
assign data_masked[272] = data_i[272] & sel_one_hot_i[3];
assign data_masked[271] = data_i[271] & sel_one_hot_i[3];
assign data_masked[270] = data_i[270] & sel_one_hot_i[3];
assign data_masked[269] = data_i[269] & sel_one_hot_i[3];
assign data_masked[268] = data_i[268] & sel_one_hot_i[3];
assign data_masked[267] = data_i[267] & sel_one_hot_i[3];
assign data_masked[266] = data_i[266] & sel_one_hot_i[3];
assign data_masked[265] = data_i[265] & sel_one_hot_i[3];
assign data_masked[264] = data_i[264] & sel_one_hot_i[3];
assign data_masked[263] = data_i[263] & sel_one_hot_i[3];
assign data_masked[262] = data_i[262] & sel_one_hot_i[3];
assign data_masked[261] = data_i[261] & sel_one_hot_i[3];
assign data_masked[260] = data_i[260] & sel_one_hot_i[3];
assign data_masked[259] = data_i[259] & sel_one_hot_i[3];
assign data_masked[258] = data_i[258] & sel_one_hot_i[3];
assign data_masked[257] = data_i[257] & sel_one_hot_i[3];
assign data_masked[256] = data_i[256] & sel_one_hot_i[3];
assign data_masked[255] = data_i[255] & sel_one_hot_i[3];
assign data_masked[254] = data_i[254] & sel_one_hot_i[3];
assign data_masked[253] = data_i[253] & sel_one_hot_i[3];
assign data_masked[252] = data_i[252] & sel_one_hot_i[3];
assign data_masked[251] = data_i[251] & sel_one_hot_i[3];
assign data_masked[250] = data_i[250] & sel_one_hot_i[3];
assign data_masked[249] = data_i[249] & sel_one_hot_i[3];
assign data_masked[248] = data_i[248] & sel_one_hot_i[3];
assign data_masked[247] = data_i[247] & sel_one_hot_i[3];
assign data_masked[246] = data_i[246] & sel_one_hot_i[3];
assign data_masked[245] = data_i[245] & sel_one_hot_i[3];
assign data_masked[244] = data_i[244] & sel_one_hot_i[3];
assign data_masked[243] = data_i[243] & sel_one_hot_i[3];
assign data_masked[242] = data_i[242] & sel_one_hot_i[3];
assign data_masked[241] = data_i[241] & sel_one_hot_i[3];
assign data_masked[240] = data_i[240] & sel_one_hot_i[3];
assign data_masked[239] = data_i[239] & sel_one_hot_i[3];
assign data_masked[238] = data_i[238] & sel_one_hot_i[3];
assign data_masked[237] = data_i[237] & sel_one_hot_i[3];
assign data_masked[236] = data_i[236] & sel_one_hot_i[3];
assign data_masked[235] = data_i[235] & sel_one_hot_i[3];
assign data_masked[234] = data_i[234] & sel_one_hot_i[3];
assign data_masked[233] = data_i[233] & sel_one_hot_i[3];
assign data_masked[232] = data_i[232] & sel_one_hot_i[3];
assign data_masked[231] = data_i[231] & sel_one_hot_i[3];
assign data_masked[230] = data_i[230] & sel_one_hot_i[3];
assign data_masked[229] = data_i[229] & sel_one_hot_i[3];
assign data_masked[228] = data_i[228] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[76];
assign N0 = data_masked[228] | data_masked[152];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[77];
assign N2 = data_masked[229] | data_masked[153];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[78];
assign N4 = data_masked[230] | data_masked[154];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[79];
assign N6 = data_masked[231] | data_masked[155];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[80];
assign N8 = data_masked[232] | data_masked[156];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[81];
assign N10 = data_masked[233] | data_masked[157];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[82];
assign N12 = data_masked[234] | data_masked[158];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[83];
assign N14 = data_masked[235] | data_masked[159];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[84];
assign N16 = data_masked[236] | data_masked[160];
assign data_o[9] = N19 | data_masked[9];
assign N19 = N18 | data_masked[85];
assign N18 = data_masked[237] | data_masked[161];
assign data_o[10] = N21 | data_masked[10];
assign N21 = N20 | data_masked[86];
assign N20 = data_masked[238] | data_masked[162];
assign data_o[11] = N23 | data_masked[11];
assign N23 = N22 | data_masked[87];
assign N22 = data_masked[239] | data_masked[163];
assign data_o[12] = N25 | data_masked[12];
assign N25 = N24 | data_masked[88];
assign N24 = data_masked[240] | data_masked[164];
assign data_o[13] = N27 | data_masked[13];
assign N27 = N26 | data_masked[89];
assign N26 = data_masked[241] | data_masked[165];
assign data_o[14] = N29 | data_masked[14];
assign N29 = N28 | data_masked[90];
assign N28 = data_masked[242] | data_masked[166];
assign data_o[15] = N31 | data_masked[15];
assign N31 = N30 | data_masked[91];
assign N30 = data_masked[243] | data_masked[167];
assign data_o[16] = N33 | data_masked[16];
assign N33 = N32 | data_masked[92];
assign N32 = data_masked[244] | data_masked[168];
assign data_o[17] = N35 | data_masked[17];
assign N35 = N34 | data_masked[93];
assign N34 = data_masked[245] | data_masked[169];
assign data_o[18] = N37 | data_masked[18];
assign N37 = N36 | data_masked[94];
assign N36 = data_masked[246] | data_masked[170];
assign data_o[19] = N39 | data_masked[19];
assign N39 = N38 | data_masked[95];
assign N38 = data_masked[247] | data_masked[171];
assign data_o[20] = N41 | data_masked[20];
assign N41 = N40 | data_masked[96];
assign N40 = data_masked[248] | data_masked[172];
assign data_o[21] = N43 | data_masked[21];
assign N43 = N42 | data_masked[97];
assign N42 = data_masked[249] | data_masked[173];
assign data_o[22] = N45 | data_masked[22];
assign N45 = N44 | data_masked[98];
assign N44 = data_masked[250] | data_masked[174];
assign data_o[23] = N47 | data_masked[23];
assign N47 = N46 | data_masked[99];
assign N46 = data_masked[251] | data_masked[175];
assign data_o[24] = N49 | data_masked[24];
assign N49 = N48 | data_masked[100];
assign N48 = data_masked[252] | data_masked[176];
assign data_o[25] = N51 | data_masked[25];
assign N51 = N50 | data_masked[101];
assign N50 = data_masked[253] | data_masked[177];
assign data_o[26] = N53 | data_masked[26];
assign N53 = N52 | data_masked[102];
assign N52 = data_masked[254] | data_masked[178];
assign data_o[27] = N55 | data_masked[27];
assign N55 = N54 | data_masked[103];
assign N54 = data_masked[255] | data_masked[179];
assign data_o[28] = N57 | data_masked[28];
assign N57 = N56 | data_masked[104];
assign N56 = data_masked[256] | data_masked[180];
assign data_o[29] = N59 | data_masked[29];
assign N59 = N58 | data_masked[105];
assign N58 = data_masked[257] | data_masked[181];
assign data_o[30] = N61 | data_masked[30];
assign N61 = N60 | data_masked[106];
assign N60 = data_masked[258] | data_masked[182];
assign data_o[31] = N63 | data_masked[31];
assign N63 = N62 | data_masked[107];
assign N62 = data_masked[259] | data_masked[183];
assign data_o[32] = N65 | data_masked[32];
assign N65 = N64 | data_masked[108];
assign N64 = data_masked[260] | data_masked[184];
assign data_o[33] = N67 | data_masked[33];
assign N67 = N66 | data_masked[109];
assign N66 = data_masked[261] | data_masked[185];
assign data_o[34] = N69 | data_masked[34];
assign N69 = N68 | data_masked[110];
assign N68 = data_masked[262] | data_masked[186];
assign data_o[35] = N71 | data_masked[35];
assign N71 = N70 | data_masked[111];
assign N70 = data_masked[263] | data_masked[187];
assign data_o[36] = N73 | data_masked[36];
assign N73 = N72 | data_masked[112];
assign N72 = data_masked[264] | data_masked[188];
assign data_o[37] = N75 | data_masked[37];
assign N75 = N74 | data_masked[113];
assign N74 = data_masked[265] | data_masked[189];
assign data_o[38] = N77 | data_masked[38];
assign N77 = N76 | data_masked[114];
assign N76 = data_masked[266] | data_masked[190];
assign data_o[39] = N79 | data_masked[39];
assign N79 = N78 | data_masked[115];
assign N78 = data_masked[267] | data_masked[191];
assign data_o[40] = N81 | data_masked[40];
assign N81 = N80 | data_masked[116];
assign N80 = data_masked[268] | data_masked[192];
assign data_o[41] = N83 | data_masked[41];
assign N83 = N82 | data_masked[117];
assign N82 = data_masked[269] | data_masked[193];
assign data_o[42] = N85 | data_masked[42];
assign N85 = N84 | data_masked[118];
assign N84 = data_masked[270] | data_masked[194];
assign data_o[43] = N87 | data_masked[43];
assign N87 = N86 | data_masked[119];
assign N86 = data_masked[271] | data_masked[195];
assign data_o[44] = N89 | data_masked[44];
assign N89 = N88 | data_masked[120];
assign N88 = data_masked[272] | data_masked[196];
assign data_o[45] = N91 | data_masked[45];
assign N91 = N90 | data_masked[121];
assign N90 = data_masked[273] | data_masked[197];
assign data_o[46] = N93 | data_masked[46];
assign N93 = N92 | data_masked[122];
assign N92 = data_masked[274] | data_masked[198];
assign data_o[47] = N95 | data_masked[47];
assign N95 = N94 | data_masked[123];
assign N94 = data_masked[275] | data_masked[199];
assign data_o[48] = N97 | data_masked[48];
assign N97 = N96 | data_masked[124];
assign N96 = data_masked[276] | data_masked[200];
assign data_o[49] = N99 | data_masked[49];
assign N99 = N98 | data_masked[125];
assign N98 = data_masked[277] | data_masked[201];
assign data_o[50] = N101 | data_masked[50];
assign N101 = N100 | data_masked[126];
assign N100 = data_masked[278] | data_masked[202];
assign data_o[51] = N103 | data_masked[51];
assign N103 = N102 | data_masked[127];
assign N102 = data_masked[279] | data_masked[203];
assign data_o[52] = N105 | data_masked[52];
assign N105 = N104 | data_masked[128];
assign N104 = data_masked[280] | data_masked[204];
assign data_o[53] = N107 | data_masked[53];
assign N107 = N106 | data_masked[129];
assign N106 = data_masked[281] | data_masked[205];
assign data_o[54] = N109 | data_masked[54];
assign N109 = N108 | data_masked[130];
assign N108 = data_masked[282] | data_masked[206];
assign data_o[55] = N111 | data_masked[55];
assign N111 = N110 | data_masked[131];
assign N110 = data_masked[283] | data_masked[207];
assign data_o[56] = N113 | data_masked[56];
assign N113 = N112 | data_masked[132];
assign N112 = data_masked[284] | data_masked[208];
assign data_o[57] = N115 | data_masked[57];
assign N115 = N114 | data_masked[133];
assign N114 = data_masked[285] | data_masked[209];
assign data_o[58] = N117 | data_masked[58];
assign N117 = N116 | data_masked[134];
assign N116 = data_masked[286] | data_masked[210];
assign data_o[59] = N119 | data_masked[59];
assign N119 = N118 | data_masked[135];
assign N118 = data_masked[287] | data_masked[211];
assign data_o[60] = N121 | data_masked[60];
assign N121 = N120 | data_masked[136];
assign N120 = data_masked[288] | data_masked[212];
assign data_o[61] = N123 | data_masked[61];
assign N123 = N122 | data_masked[137];
assign N122 = data_masked[289] | data_masked[213];
assign data_o[62] = N125 | data_masked[62];
assign N125 = N124 | data_masked[138];
assign N124 = data_masked[290] | data_masked[214];
assign data_o[63] = N127 | data_masked[63];
assign N127 = N126 | data_masked[139];
assign N126 = data_masked[291] | data_masked[215];
assign data_o[64] = N129 | data_masked[64];
assign N129 = N128 | data_masked[140];
assign N128 = data_masked[292] | data_masked[216];
assign data_o[65] = N131 | data_masked[65];
assign N131 = N130 | data_masked[141];
assign N130 = data_masked[293] | data_masked[217];
assign data_o[66] = N133 | data_masked[66];
assign N133 = N132 | data_masked[142];
assign N132 = data_masked[294] | data_masked[218];
assign data_o[67] = N135 | data_masked[67];
assign N135 = N134 | data_masked[143];
assign N134 = data_masked[295] | data_masked[219];
assign data_o[68] = N137 | data_masked[68];
assign N137 = N136 | data_masked[144];
assign N136 = data_masked[296] | data_masked[220];
assign data_o[69] = N139 | data_masked[69];
assign N139 = N138 | data_masked[145];
assign N138 = data_masked[297] | data_masked[221];
assign data_o[70] = N141 | data_masked[70];
assign N141 = N140 | data_masked[146];
assign N140 = data_masked[298] | data_masked[222];
assign data_o[71] = N143 | data_masked[71];
assign N143 = N142 | data_masked[147];
assign N142 = data_masked[299] | data_masked[223];
assign data_o[72] = N145 | data_masked[72];
assign N145 = N144 | data_masked[148];
assign N144 = data_masked[300] | data_masked[224];
assign data_o[73] = N147 | data_masked[73];
assign N147 = N146 | data_masked[149];
assign N146 = data_masked[301] | data_masked[225];
assign data_o[74] = N149 | data_masked[74];
assign N149 = N148 | data_masked[150];
assign N148 = data_masked[302] | data_masked[226];
assign data_o[75] = N151 | data_masked[75];
assign N151 = N150 | data_masked[151];
assign N150 = data_masked[303] | data_masked[227];
endmodule |
module bsg_mem_1r1w_synth_width_p9_els_p2_read_write_same_addr_p0_harden_p0
(
w_clk_i,
w_reset_i,
w_v_i,
w_addr_i,
w_data_i,
r_v_i,
r_addr_i,
r_data_o
);
input [0:0] w_addr_i;
input [8:0] w_data_i;
input [0:0] r_addr_i;
output [8:0] r_data_o;
input w_clk_i;
input w_reset_i;
input w_v_i;
input r_v_i;
wire [8:0] r_data_o;
wire N0,N1,N2,N3,N4,N5,N7,N8;
reg [17:0] mem;
assign r_data_o[8] = (N3)? mem[8] :
(N0)? mem[17] : 1'b0;
assign N0 = r_addr_i[0];
assign r_data_o[7] = (N3)? mem[7] :
(N0)? mem[16] : 1'b0;
assign r_data_o[6] = (N3)? mem[6] :
(N0)? mem[15] : 1'b0;
assign r_data_o[5] = (N3)? mem[5] :
(N0)? mem[14] : 1'b0;
assign r_data_o[4] = (N3)? mem[4] :
(N0)? mem[13] : 1'b0;
assign r_data_o[3] = (N3)? mem[3] :
(N0)? mem[12] : 1'b0;
assign r_data_o[2] = (N3)? mem[2] :
(N0)? mem[11] : 1'b0;
assign r_data_o[1] = (N3)? mem[1] :
(N0)? mem[10] : 1'b0;
assign r_data_o[0] = (N3)? mem[0] :
(N0)? mem[9] : 1'b0;
always @(posedge w_clk_i) begin
if(N8) begin
mem[17] <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[16] <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[15] <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[14] <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[13] <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[12] <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[11] <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[10] <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N8) begin
mem[9] <= w_data_i[0];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[8] <= w_data_i[8];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[7] <= w_data_i[7];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[6] <= w_data_i[6];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[5] <= w_data_i[5];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[4] <= w_data_i[4];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[3] <= w_data_i[3];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[2] <= w_data_i[2];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[1] <= w_data_i[1];
end
end
always @(posedge w_clk_i) begin
if(N7) begin
mem[0] <= w_data_i[0];
end
end
assign N5 = ~w_addr_i[0];
assign { N8, N7 } = (N1)? { w_addr_i[0:0], N5 } :
(N2)? { 1'b0, 1'b0 } : 1'b0;
assign N1 = w_v_i;
assign N2 = N4;
assign N3 = ~r_addr_i[0];
assign N4 = ~w_v_i;
endmodule |
module bsg_adder_cin_width_p33
(
a_i,
b_i,
cin_i,
o
);
input [32:0] a_i;
input [32:0] b_i;
output [32:0] o;
input cin_i;
wire [32:0] o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
assign { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } = a_i + b_i;
assign o = { N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3, N2, N1, N0 } + cin_i;
endmodule |
module bsg_buf_width_p32
(
i,
o
);
input [31:0] i;
output [31:0] o;
wire [31:0] o;
assign o[31] = i[31];
assign o[30] = i[30];
assign o[29] = i[29];
assign o[28] = i[28];
assign o[27] = i[27];
assign o[26] = i[26];
assign o[25] = i[25];
assign o[24] = i[24];
assign o[23] = i[23];
assign o[22] = i[22];
assign o[21] = i[21];
assign o[20] = i[20];
assign o[19] = i[19];
assign o[18] = i[18];
assign o[17] = i[17];
assign o[16] = i[16];
assign o[15] = i[15];
assign o[14] = i[14];
assign o[13] = i[13];
assign o[12] = i[12];
assign o[11] = i[11];
assign o[10] = i[10];
assign o[9] = i[9];
assign o[8] = i[8];
assign o[7] = i[7];
assign o[6] = i[6];
assign o[5] = i[5];
assign o[4] = i[4];
assign o[3] = i[3];
assign o[2] = i[2];
assign o[1] = i[1];
assign o[0] = i[0];
endmodule |
module bsg_manycore_pkt_encode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20
(
clk_i,
v_i,
addr_i,
data_i,
mask_i,
we_i,
my_x_i,
my_y_i,
v_o,
data_o
);
input [31:0] addr_i;
input [31:0] data_i;
input [3:0] mask_i;
input [3:0] my_x_i;
input [4:0] my_y_i;
output [75:0] data_o;
input clk_i;
input v_i;
input we_i;
output v_o;
wire [75:0] data_o;
wire v_o,N0;
assign data_o[75] = 1'b0;
assign data_o[74] = addr_i[20];
assign data_o[73] = addr_i[19];
assign data_o[72] = addr_i[18];
assign data_o[71] = addr_i[17];
assign data_o[70] = addr_i[16];
assign data_o[69] = addr_i[15];
assign data_o[68] = addr_i[14];
assign data_o[67] = addr_i[13];
assign data_o[66] = addr_i[12];
assign data_o[65] = addr_i[11];
assign data_o[64] = addr_i[10];
assign data_o[63] = addr_i[9];
assign data_o[62] = addr_i[8];
assign data_o[61] = addr_i[7];
assign data_o[60] = addr_i[6];
assign data_o[59] = addr_i[5];
assign data_o[58] = addr_i[4];
assign data_o[57] = addr_i[3];
assign data_o[56] = addr_i[2];
assign data_o[8] = addr_i[30];
assign data_o[7] = addr_i[29];
assign data_o[6] = addr_i[28];
assign data_o[5] = addr_i[27];
assign data_o[4] = addr_i[26];
assign data_o[3] = addr_i[25];
assign data_o[2] = addr_i[24];
assign data_o[1] = addr_i[23];
assign data_o[0] = addr_i[22];
assign data_o[53] = mask_i[3];
assign data_o[52] = mask_i[2];
assign data_o[51] = mask_i[1];
assign data_o[50] = mask_i[0];
assign data_o[49] = data_i[31];
assign data_o[48] = data_i[30];
assign data_o[47] = data_i[29];
assign data_o[46] = data_i[28];
assign data_o[45] = data_i[27];
assign data_o[44] = data_i[26];
assign data_o[43] = data_i[25];
assign data_o[42] = data_i[24];
assign data_o[41] = data_i[23];
assign data_o[40] = data_i[22];
assign data_o[39] = data_i[21];
assign data_o[38] = data_i[20];
assign data_o[37] = data_i[19];
assign data_o[36] = data_i[18];
assign data_o[35] = data_i[17];
assign data_o[34] = data_i[16];
assign data_o[33] = data_i[15];
assign data_o[32] = data_i[14];
assign data_o[31] = data_i[13];
assign data_o[30] = data_i[12];
assign data_o[29] = data_i[11];
assign data_o[28] = data_i[10];
assign data_o[27] = data_i[9];
assign data_o[26] = data_i[8];
assign data_o[25] = data_i[7];
assign data_o[24] = data_i[6];
assign data_o[23] = data_i[5];
assign data_o[22] = data_i[4];
assign data_o[21] = data_i[3];
assign data_o[20] = data_i[2];
assign data_o[19] = data_i[1];
assign data_o[18] = data_i[0];
assign data_o[17] = my_y_i[4];
assign data_o[16] = my_y_i[3];
assign data_o[15] = my_y_i[2];
assign data_o[14] = my_y_i[1];
assign data_o[13] = my_y_i[0];
assign data_o[12] = my_x_i[3];
assign data_o[11] = my_x_i[2];
assign data_o[10] = my_x_i[1];
assign data_o[9] = my_x_i[0];
assign data_o[54] = ~data_o[55];
assign data_o[55] = addr_i[21];
assign v_o = N0 & v_i;
assign N0 = addr_i[31] & we_i;
endmodule |
module bsg_mux_one_hot_width_p33_els_p3
(
data_i,
sel_one_hot_i,
data_o
);
input [98:0] data_i;
input [2:0] sel_one_hot_i;
output [32:0] data_o;
wire [32:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32;
wire [98:0] data_masked;
assign data_masked[32] = data_i[32] & sel_one_hot_i[0];
assign data_masked[31] = data_i[31] & sel_one_hot_i[0];
assign data_masked[30] = data_i[30] & sel_one_hot_i[0];
assign data_masked[29] = data_i[29] & sel_one_hot_i[0];
assign data_masked[28] = data_i[28] & sel_one_hot_i[0];
assign data_masked[27] = data_i[27] & sel_one_hot_i[0];
assign data_masked[26] = data_i[26] & sel_one_hot_i[0];
assign data_masked[25] = data_i[25] & sel_one_hot_i[0];
assign data_masked[24] = data_i[24] & sel_one_hot_i[0];
assign data_masked[23] = data_i[23] & sel_one_hot_i[0];
assign data_masked[22] = data_i[22] & sel_one_hot_i[0];
assign data_masked[21] = data_i[21] & sel_one_hot_i[0];
assign data_masked[20] = data_i[20] & sel_one_hot_i[0];
assign data_masked[19] = data_i[19] & sel_one_hot_i[0];
assign data_masked[18] = data_i[18] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[0];
assign data_masked[16] = data_i[16] & sel_one_hot_i[0];
assign data_masked[15] = data_i[15] & sel_one_hot_i[0];
assign data_masked[14] = data_i[14] & sel_one_hot_i[0];
assign data_masked[13] = data_i[13] & sel_one_hot_i[0];
assign data_masked[12] = data_i[12] & sel_one_hot_i[0];
assign data_masked[11] = data_i[11] & sel_one_hot_i[0];
assign data_masked[10] = data_i[10] & sel_one_hot_i[0];
assign data_masked[9] = data_i[9] & sel_one_hot_i[0];
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[65] = data_i[65] & sel_one_hot_i[1];
assign data_masked[64] = data_i[64] & sel_one_hot_i[1];
assign data_masked[63] = data_i[63] & sel_one_hot_i[1];
assign data_masked[62] = data_i[62] & sel_one_hot_i[1];
assign data_masked[61] = data_i[61] & sel_one_hot_i[1];
assign data_masked[60] = data_i[60] & sel_one_hot_i[1];
assign data_masked[59] = data_i[59] & sel_one_hot_i[1];
assign data_masked[58] = data_i[58] & sel_one_hot_i[1];
assign data_masked[57] = data_i[57] & sel_one_hot_i[1];
assign data_masked[56] = data_i[56] & sel_one_hot_i[1];
assign data_masked[55] = data_i[55] & sel_one_hot_i[1];
assign data_masked[54] = data_i[54] & sel_one_hot_i[1];
assign data_masked[53] = data_i[53] & sel_one_hot_i[1];
assign data_masked[52] = data_i[52] & sel_one_hot_i[1];
assign data_masked[51] = data_i[51] & sel_one_hot_i[1];
assign data_masked[50] = data_i[50] & sel_one_hot_i[1];
assign data_masked[49] = data_i[49] & sel_one_hot_i[1];
assign data_masked[48] = data_i[48] & sel_one_hot_i[1];
assign data_masked[47] = data_i[47] & sel_one_hot_i[1];
assign data_masked[46] = data_i[46] & sel_one_hot_i[1];
assign data_masked[45] = data_i[45] & sel_one_hot_i[1];
assign data_masked[44] = data_i[44] & sel_one_hot_i[1];
assign data_masked[43] = data_i[43] & sel_one_hot_i[1];
assign data_masked[42] = data_i[42] & sel_one_hot_i[1];
assign data_masked[41] = data_i[41] & sel_one_hot_i[1];
assign data_masked[40] = data_i[40] & sel_one_hot_i[1];
assign data_masked[39] = data_i[39] & sel_one_hot_i[1];
assign data_masked[38] = data_i[38] & sel_one_hot_i[1];
assign data_masked[37] = data_i[37] & sel_one_hot_i[1];
assign data_masked[36] = data_i[36] & sel_one_hot_i[1];
assign data_masked[35] = data_i[35] & sel_one_hot_i[1];
assign data_masked[34] = data_i[34] & sel_one_hot_i[1];
assign data_masked[33] = data_i[33] & sel_one_hot_i[1];
assign data_masked[98] = data_i[98] & sel_one_hot_i[2];
assign data_masked[97] = data_i[97] & sel_one_hot_i[2];
assign data_masked[96] = data_i[96] & sel_one_hot_i[2];
assign data_masked[95] = data_i[95] & sel_one_hot_i[2];
assign data_masked[94] = data_i[94] & sel_one_hot_i[2];
assign data_masked[93] = data_i[93] & sel_one_hot_i[2];
assign data_masked[92] = data_i[92] & sel_one_hot_i[2];
assign data_masked[91] = data_i[91] & sel_one_hot_i[2];
assign data_masked[90] = data_i[90] & sel_one_hot_i[2];
assign data_masked[89] = data_i[89] & sel_one_hot_i[2];
assign data_masked[88] = data_i[88] & sel_one_hot_i[2];
assign data_masked[87] = data_i[87] & sel_one_hot_i[2];
assign data_masked[86] = data_i[86] & sel_one_hot_i[2];
assign data_masked[85] = data_i[85] & sel_one_hot_i[2];
assign data_masked[84] = data_i[84] & sel_one_hot_i[2];
assign data_masked[83] = data_i[83] & sel_one_hot_i[2];
assign data_masked[82] = data_i[82] & sel_one_hot_i[2];
assign data_masked[81] = data_i[81] & sel_one_hot_i[2];
assign data_masked[80] = data_i[80] & sel_one_hot_i[2];
assign data_masked[79] = data_i[79] & sel_one_hot_i[2];
assign data_masked[78] = data_i[78] & sel_one_hot_i[2];
assign data_masked[77] = data_i[77] & sel_one_hot_i[2];
assign data_masked[76] = data_i[76] & sel_one_hot_i[2];
assign data_masked[75] = data_i[75] & sel_one_hot_i[2];
assign data_masked[74] = data_i[74] & sel_one_hot_i[2];
assign data_masked[73] = data_i[73] & sel_one_hot_i[2];
assign data_masked[72] = data_i[72] & sel_one_hot_i[2];
assign data_masked[71] = data_i[71] & sel_one_hot_i[2];
assign data_masked[70] = data_i[70] & sel_one_hot_i[2];
assign data_masked[69] = data_i[69] & sel_one_hot_i[2];
assign data_masked[68] = data_i[68] & sel_one_hot_i[2];
assign data_masked[67] = data_i[67] & sel_one_hot_i[2];
assign data_masked[66] = data_i[66] & sel_one_hot_i[2];
assign data_o[0] = N0 | data_masked[0];
assign N0 = data_masked[66] | data_masked[33];
assign data_o[1] = N1 | data_masked[1];
assign N1 = data_masked[67] | data_masked[34];
assign data_o[2] = N2 | data_masked[2];
assign N2 = data_masked[68] | data_masked[35];
assign data_o[3] = N3 | data_masked[3];
assign N3 = data_masked[69] | data_masked[36];
assign data_o[4] = N4 | data_masked[4];
assign N4 = data_masked[70] | data_masked[37];
assign data_o[5] = N5 | data_masked[5];
assign N5 = data_masked[71] | data_masked[38];
assign data_o[6] = N6 | data_masked[6];
assign N6 = data_masked[72] | data_masked[39];
assign data_o[7] = N7 | data_masked[7];
assign N7 = data_masked[73] | data_masked[40];
assign data_o[8] = N8 | data_masked[8];
assign N8 = data_masked[74] | data_masked[41];
assign data_o[9] = N9 | data_masked[9];
assign N9 = data_masked[75] | data_masked[42];
assign data_o[10] = N10 | data_masked[10];
assign N10 = data_masked[76] | data_masked[43];
assign data_o[11] = N11 | data_masked[11];
assign N11 = data_masked[77] | data_masked[44];
assign data_o[12] = N12 | data_masked[12];
assign N12 = data_masked[78] | data_masked[45];
assign data_o[13] = N13 | data_masked[13];
assign N13 = data_masked[79] | data_masked[46];
assign data_o[14] = N14 | data_masked[14];
assign N14 = data_masked[80] | data_masked[47];
assign data_o[15] = N15 | data_masked[15];
assign N15 = data_masked[81] | data_masked[48];
assign data_o[16] = N16 | data_masked[16];
assign N16 = data_masked[82] | data_masked[49];
assign data_o[17] = N17 | data_masked[17];
assign N17 = data_masked[83] | data_masked[50];
assign data_o[18] = N18 | data_masked[18];
assign N18 = data_masked[84] | data_masked[51];
assign data_o[19] = N19 | data_masked[19];
assign N19 = data_masked[85] | data_masked[52];
assign data_o[20] = N20 | data_masked[20];
assign N20 = data_masked[86] | data_masked[53];
assign data_o[21] = N21 | data_masked[21];
assign N21 = data_masked[87] | data_masked[54];
assign data_o[22] = N22 | data_masked[22];
assign N22 = data_masked[88] | data_masked[55];
assign data_o[23] = N23 | data_masked[23];
assign N23 = data_masked[89] | data_masked[56];
assign data_o[24] = N24 | data_masked[24];
assign N24 = data_masked[90] | data_masked[57];
assign data_o[25] = N25 | data_masked[25];
assign N25 = data_masked[91] | data_masked[58];
assign data_o[26] = N26 | data_masked[26];
assign N26 = data_masked[92] | data_masked[59];
assign data_o[27] = N27 | data_masked[27];
assign N27 = data_masked[93] | data_masked[60];
assign data_o[28] = N28 | data_masked[28];
assign N28 = data_masked[94] | data_masked[61];
assign data_o[29] = N29 | data_masked[29];
assign N29 = data_masked[95] | data_masked[62];
assign data_o[30] = N30 | data_masked[30];
assign N30 = data_masked[96] | data_masked[63];
assign data_o[31] = N31 | data_masked[31];
assign N31 = data_masked[97] | data_masked[64];
assign data_o[32] = N32 | data_masked[32];
assign N32 = data_masked[98] | data_masked[65];
endmodule |
module bsg_scan_2_1_0
(
i,
o
);
input [1:0] i;
output [1:0] o;
wire [1:0] o;
assign o[1] = i[1] | 1'b0;
assign o[0] = i[0] | i[1];
endmodule |
module bsg_mux_width_p33_els_p2
(
data_i,
sel_i,
data_o
);
input [65:0] data_i;
input [0:0] sel_i;
output [32:0] data_o;
wire [32:0] data_o;
wire N0,N1;
assign data_o[32] = (N1)? data_i[32] :
(N0)? data_i[65] : 1'b0;
assign N0 = sel_i[0];
assign data_o[31] = (N1)? data_i[31] :
(N0)? data_i[64] : 1'b0;
assign data_o[30] = (N1)? data_i[30] :
(N0)? data_i[63] : 1'b0;
assign data_o[29] = (N1)? data_i[29] :
(N0)? data_i[62] : 1'b0;
assign data_o[28] = (N1)? data_i[28] :
(N0)? data_i[61] : 1'b0;
assign data_o[27] = (N1)? data_i[27] :
(N0)? data_i[60] : 1'b0;
assign data_o[26] = (N1)? data_i[26] :
(N0)? data_i[59] : 1'b0;
assign data_o[25] = (N1)? data_i[25] :
(N0)? data_i[58] : 1'b0;
assign data_o[24] = (N1)? data_i[24] :
(N0)? data_i[57] : 1'b0;
assign data_o[23] = (N1)? data_i[23] :
(N0)? data_i[56] : 1'b0;
assign data_o[22] = (N1)? data_i[22] :
(N0)? data_i[55] : 1'b0;
assign data_o[21] = (N1)? data_i[21] :
(N0)? data_i[54] : 1'b0;
assign data_o[20] = (N1)? data_i[20] :
(N0)? data_i[53] : 1'b0;
assign data_o[19] = (N1)? data_i[19] :
(N0)? data_i[52] : 1'b0;
assign data_o[18] = (N1)? data_i[18] :
(N0)? data_i[51] : 1'b0;
assign data_o[17] = (N1)? data_i[17] :
(N0)? data_i[50] : 1'b0;
assign data_o[16] = (N1)? data_i[16] :
(N0)? data_i[49] : 1'b0;
assign data_o[15] = (N1)? data_i[15] :
(N0)? data_i[48] : 1'b0;
assign data_o[14] = (N1)? data_i[14] :
(N0)? data_i[47] : 1'b0;
assign data_o[13] = (N1)? data_i[13] :
(N0)? data_i[46] : 1'b0;
assign data_o[12] = (N1)? data_i[12] :
(N0)? data_i[45] : 1'b0;
assign data_o[11] = (N1)? data_i[11] :
(N0)? data_i[44] : 1'b0;
assign data_o[10] = (N1)? data_i[10] :
(N0)? data_i[43] : 1'b0;
assign data_o[9] = (N1)? data_i[9] :
(N0)? data_i[42] : 1'b0;
assign data_o[8] = (N1)? data_i[8] :
(N0)? data_i[41] : 1'b0;
assign data_o[7] = (N1)? data_i[7] :
(N0)? data_i[40] : 1'b0;
assign data_o[6] = (N1)? data_i[6] :
(N0)? data_i[39] : 1'b0;
assign data_o[5] = (N1)? data_i[5] :
(N0)? data_i[38] : 1'b0;
assign data_o[4] = (N1)? data_i[4] :
(N0)? data_i[37] : 1'b0;
assign data_o[3] = (N1)? data_i[3] :
(N0)? data_i[36] : 1'b0;
assign data_o[2] = (N1)? data_i[2] :
(N0)? data_i[35] : 1'b0;
assign data_o[1] = (N1)? data_i[1] :
(N0)? data_i[34] : 1'b0;
assign data_o[0] = (N1)? data_i[0] :
(N0)? data_i[33] : 1'b0;
assign N1 = ~sel_i[0];
endmodule |
module bsg_dff_reset_width_p65_harden_p0
(
clock_i,
data_i,
reset_i,
data_o
);
input [64:0] data_i;
output [64:0] data_o;
input clock_i;
input reset_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,
N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,
N62,N63,N64,N65,N66,N67;
reg [64:0] data_o;
always @(posedge clock_i) begin
if(1'b1) begin
data_o[64] <= N67;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[63] <= N66;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[62] <= N65;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[61] <= N64;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[60] <= N63;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[59] <= N62;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[58] <= N61;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[57] <= N60;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[56] <= N59;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[55] <= N58;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[54] <= N57;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[53] <= N56;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[52] <= N55;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[51] <= N54;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[50] <= N53;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[49] <= N52;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[48] <= N51;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[47] <= N50;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[46] <= N49;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[45] <= N48;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[44] <= N47;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[43] <= N46;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[42] <= N45;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[41] <= N44;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[40] <= N43;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[39] <= N42;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[38] <= N41;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[37] <= N40;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[36] <= N39;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[35] <= N38;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[34] <= N37;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[33] <= N36;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[32] <= N35;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[31] <= N34;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[30] <= N33;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[29] <= N32;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[28] <= N31;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[27] <= N30;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[26] <= N29;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[25] <= N28;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[24] <= N27;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[23] <= N26;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[22] <= N25;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[21] <= N24;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[20] <= N23;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[19] <= N22;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[18] <= N21;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[17] <= N20;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[16] <= N19;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[15] <= N18;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[14] <= N17;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[13] <= N16;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[12] <= N15;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[11] <= N14;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[10] <= N13;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[9] <= N12;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[8] <= N11;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[7] <= N10;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[6] <= N9;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[5] <= N8;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[4] <= N7;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[3] <= N6;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[2] <= N5;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[1] <= N4;
end
end
always @(posedge clock_i) begin
if(1'b1) begin
data_o[0] <= N3;
end
end
assign { N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7, N6, N5, N4, N3 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N1)? data_i : 1'b0;
assign N0 = reset_i;
assign N1 = N2;
assign N2 = ~reset_i;
endmodule |
module bsg_manycore_pkt_decode_x_cord_width_p4_y_cord_width_p5_data_width_p32_addr_width_p20
(
v_i,
data_i,
pkt_freeze_o,
pkt_unfreeze_o,
pkt_arb_cfg_o,
pkt_unknown_o,
pkt_remote_store_o,
data_o,
addr_o,
mask_o
);
input [75:0] data_i;
output [31:0] data_o;
output [19:0] addr_o;
output [3:0] mask_o;
input v_i;
output pkt_freeze_o;
output pkt_unfreeze_o;
output pkt_arb_cfg_o;
output pkt_unknown_o;
output pkt_remote_store_o;
wire [31:0] data_o;
wire [19:0] addr_o;
wire [3:0] mask_o;
wire pkt_freeze_o,pkt_unfreeze_o,pkt_arb_cfg_o,pkt_unknown_o,pkt_remote_store_o,N0,
N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,N22,
N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,
N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61,N62,
N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75;
assign addr_o[19] = data_i[75];
assign addr_o[18] = data_i[74];
assign addr_o[17] = data_i[73];
assign addr_o[16] = data_i[72];
assign addr_o[15] = data_i[71];
assign addr_o[14] = data_i[70];
assign addr_o[13] = data_i[69];
assign addr_o[12] = data_i[68];
assign addr_o[11] = data_i[67];
assign addr_o[10] = data_i[66];
assign addr_o[9] = data_i[65];
assign addr_o[8] = data_i[64];
assign addr_o[7] = data_i[63];
assign addr_o[6] = data_i[62];
assign addr_o[5] = data_i[61];
assign addr_o[4] = data_i[60];
assign addr_o[3] = data_i[59];
assign addr_o[2] = data_i[58];
assign addr_o[1] = data_i[57];
assign addr_o[0] = data_i[56];
assign data_o[31] = data_i[49];
assign data_o[30] = data_i[48];
assign data_o[29] = data_i[47];
assign data_o[28] = data_i[46];
assign data_o[27] = data_i[45];
assign data_o[26] = data_i[44];
assign data_o[25] = data_i[43];
assign data_o[24] = data_i[42];
assign data_o[23] = data_i[41];
assign data_o[22] = data_i[40];
assign data_o[21] = data_i[39];
assign data_o[20] = data_i[38];
assign data_o[19] = data_i[37];
assign data_o[18] = data_i[36];
assign data_o[17] = data_i[35];
assign data_o[16] = data_i[34];
assign data_o[15] = data_i[33];
assign data_o[14] = data_i[32];
assign data_o[13] = data_i[31];
assign data_o[12] = data_i[30];
assign data_o[11] = data_i[29];
assign data_o[10] = data_i[28];
assign data_o[9] = data_i[27];
assign data_o[8] = data_i[26];
assign data_o[7] = data_i[25];
assign data_o[6] = data_i[24];
assign data_o[5] = data_i[23];
assign data_o[4] = data_i[22];
assign data_o[3] = data_i[21];
assign data_o[2] = data_i[20];
assign data_o[1] = data_i[19];
assign data_o[0] = data_i[18];
assign N11 = data_i[55] | N10;
assign N14 = N13 | data_i[54];
assign N16 = data_i[55] & data_i[54];
assign N17 = N13 & N10;
assign N36 = ~data_i[56];
assign N37 = data_i[74] | data_i[75];
assign N38 = data_i[73] | N37;
assign N39 = data_i[72] | N38;
assign N40 = data_i[71] | N39;
assign N41 = data_i[70] | N40;
assign N42 = data_i[69] | N41;
assign N43 = data_i[68] | N42;
assign N44 = data_i[67] | N43;
assign N45 = data_i[66] | N44;
assign N46 = data_i[65] | N45;
assign N47 = data_i[64] | N46;
assign N48 = data_i[63] | N47;
assign N49 = data_i[62] | N48;
assign N50 = data_i[61] | N49;
assign N51 = data_i[60] | N50;
assign N52 = data_i[59] | N51;
assign N53 = data_i[58] | N52;
assign N54 = data_i[57] | N53;
assign N55 = N36 | N54;
assign N56 = ~N55;
assign N23 = (N0)? data_i[18] :
(N1)? 1'b0 :
(N2)? 1'b0 : 1'b0;
assign N0 = N19;
assign N1 = N75;
assign N2 = 1'b0;
assign N24 = (N0)? N22 :
(N1)? 1'b0 :
(N2)? 1'b0 : 1'b0;
assign N25 = (N0)? 1'b0 :
(N3)? 1'b1 :
(N21)? 1'b0 : 1'b0;
assign N3 = N56;
assign N26 = (N0)? 1'b0 :
(N3)? 1'b0 :
(N21)? 1'b1 : 1'b0;
assign N27 = (N4)? 1'b1 :
(N5)? 1'b0 :
(N6)? 1'b0 : 1'b0;
assign N4 = N12;
assign N5 = N15;
assign N6 = N18;
assign { N31, N30, N29, N28 } = (N4)? data_i[53:50] :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign N32 = (N4)? 1'b0 :
(N5)? N26 :
(N6)? 1'b1 : 1'b0;
assign N33 = (N4)? 1'b0 :
(N5)? N23 :
(N6)? 1'b0 : 1'b0;
assign N34 = (N4)? 1'b0 :
(N5)? N24 :
(N6)? 1'b0 : 1'b0;
assign N35 = (N4)? 1'b0 :
(N5)? N25 :
(N6)? 1'b0 : 1'b0;
assign pkt_freeze_o = (N7)? N33 :
(N8)? 1'b0 : 1'b0;
assign N7 = v_i;
assign N8 = N9;
assign pkt_unfreeze_o = (N7)? N34 :
(N8)? 1'b0 : 1'b0;
assign pkt_arb_cfg_o = (N7)? N35 :
(N8)? 1'b0 : 1'b0;
assign pkt_remote_store_o = (N7)? N27 :
(N8)? 1'b0 : 1'b0;
assign mask_o = (N7)? { N31, N30, N29, N28 } :
(N8)? { 1'b0, 1'b0, 1'b0, 1'b0 } : 1'b0;
assign pkt_unknown_o = (N7)? N32 :
(N8)? 1'b0 : 1'b0;
assign N9 = ~v_i;
assign N10 = ~data_i[54];
assign N12 = ~N11;
assign N13 = ~data_i[55];
assign N15 = ~N14;
assign N18 = N16 | N17;
assign N19 = ~N75;
assign N75 = N74 | data_i[56];
assign N74 = N73 | data_i[57];
assign N73 = N72 | data_i[58];
assign N72 = N71 | data_i[59];
assign N71 = N70 | data_i[60];
assign N70 = N69 | data_i[61];
assign N69 = N68 | data_i[62];
assign N68 = N67 | data_i[63];
assign N67 = N66 | data_i[64];
assign N66 = N65 | data_i[65];
assign N65 = N64 | data_i[66];
assign N64 = N63 | data_i[67];
assign N63 = N62 | data_i[68];
assign N62 = N61 | data_i[69];
assign N61 = N60 | data_i[70];
assign N60 = N59 | data_i[71];
assign N59 = N58 | data_i[72];
assign N58 = N57 | data_i[73];
assign N57 = data_i[75] | data_i[74];
assign N20 = N56 | N19;
assign N21 = ~N20;
assign N22 = ~data_i[18];
endmodule |
module bsg_dff_reset_en_width_p10_harden_p1
(
clock_i,
reset_i,
en_i,
data_i,
data_o
);
input [9:0] data_i;
output [9:0] data_o;
input clock_i;
input reset_i;
input en_i;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15;
reg [9:0] data_o;
always @(posedge clock_i) begin
if(N3) begin
data_o[9] <= N13;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[8] <= N12;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[7] <= N11;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[6] <= N10;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[5] <= N9;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[4] <= N8;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[3] <= N7;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[2] <= N6;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[1] <= N5;
end
end
always @(posedge clock_i) begin
if(N3) begin
data_o[0] <= N4;
end
end
assign N3 = (N0)? 1'b1 :
(N15)? 1'b1 :
(N2)? 1'b0 : 1'b0;
assign N0 = reset_i;
assign { N13, N12, N11, N10, N9, N8, N7, N6, N5, N4 } = (N0)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N15)? data_i : 1'b0;
assign N1 = en_i | reset_i;
assign N2 = ~N1;
assign N14 = ~reset_i;
assign N15 = en_i & N14;
endmodule |
module bsg_mux_one_hot_width_p9_els_p4
(
data_i,
sel_one_hot_i,
data_o
);
input [35:0] data_i;
input [3:0] sel_one_hot_i;
output [8:0] data_o;
wire [8:0] data_o;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17;
wire [35:0] data_masked;
assign data_masked[8] = data_i[8] & sel_one_hot_i[0];
assign data_masked[7] = data_i[7] & sel_one_hot_i[0];
assign data_masked[6] = data_i[6] & sel_one_hot_i[0];
assign data_masked[5] = data_i[5] & sel_one_hot_i[0];
assign data_masked[4] = data_i[4] & sel_one_hot_i[0];
assign data_masked[3] = data_i[3] & sel_one_hot_i[0];
assign data_masked[2] = data_i[2] & sel_one_hot_i[0];
assign data_masked[1] = data_i[1] & sel_one_hot_i[0];
assign data_masked[0] = data_i[0] & sel_one_hot_i[0];
assign data_masked[17] = data_i[17] & sel_one_hot_i[1];
assign data_masked[16] = data_i[16] & sel_one_hot_i[1];
assign data_masked[15] = data_i[15] & sel_one_hot_i[1];
assign data_masked[14] = data_i[14] & sel_one_hot_i[1];
assign data_masked[13] = data_i[13] & sel_one_hot_i[1];
assign data_masked[12] = data_i[12] & sel_one_hot_i[1];
assign data_masked[11] = data_i[11] & sel_one_hot_i[1];
assign data_masked[10] = data_i[10] & sel_one_hot_i[1];
assign data_masked[9] = data_i[9] & sel_one_hot_i[1];
assign data_masked[26] = data_i[26] & sel_one_hot_i[2];
assign data_masked[25] = data_i[25] & sel_one_hot_i[2];
assign data_masked[24] = data_i[24] & sel_one_hot_i[2];
assign data_masked[23] = data_i[23] & sel_one_hot_i[2];
assign data_masked[22] = data_i[22] & sel_one_hot_i[2];
assign data_masked[21] = data_i[21] & sel_one_hot_i[2];
assign data_masked[20] = data_i[20] & sel_one_hot_i[2];
assign data_masked[19] = data_i[19] & sel_one_hot_i[2];
assign data_masked[18] = data_i[18] & sel_one_hot_i[2];
assign data_masked[35] = data_i[35] & sel_one_hot_i[3];
assign data_masked[34] = data_i[34] & sel_one_hot_i[3];
assign data_masked[33] = data_i[33] & sel_one_hot_i[3];
assign data_masked[32] = data_i[32] & sel_one_hot_i[3];
assign data_masked[31] = data_i[31] & sel_one_hot_i[3];
assign data_masked[30] = data_i[30] & sel_one_hot_i[3];
assign data_masked[29] = data_i[29] & sel_one_hot_i[3];
assign data_masked[28] = data_i[28] & sel_one_hot_i[3];
assign data_masked[27] = data_i[27] & sel_one_hot_i[3];
assign data_o[0] = N1 | data_masked[0];
assign N1 = N0 | data_masked[9];
assign N0 = data_masked[27] | data_masked[18];
assign data_o[1] = N3 | data_masked[1];
assign N3 = N2 | data_masked[10];
assign N2 = data_masked[28] | data_masked[19];
assign data_o[2] = N5 | data_masked[2];
assign N5 = N4 | data_masked[11];
assign N4 = data_masked[29] | data_masked[20];
assign data_o[3] = N7 | data_masked[3];
assign N7 = N6 | data_masked[12];
assign N6 = data_masked[30] | data_masked[21];
assign data_o[4] = N9 | data_masked[4];
assign N9 = N8 | data_masked[13];
assign N8 = data_masked[31] | data_masked[22];
assign data_o[5] = N11 | data_masked[5];
assign N11 = N10 | data_masked[14];
assign N10 = data_masked[32] | data_masked[23];
assign data_o[6] = N13 | data_masked[6];
assign N13 = N12 | data_masked[15];
assign N12 = data_masked[33] | data_masked[24];
assign data_o[7] = N15 | data_masked[7];
assign N15 = N14 | data_masked[16];
assign N14 = data_masked[34] | data_masked[25];
assign data_o[8] = N17 | data_masked[8];
assign N17 = N16 | data_masked[17];
assign N16 = data_masked[35] | data_masked[26];
endmodule |
module bsg_dff_en_width_p33
(
clock_i,
data_i,
en_i,
data_o
);
input [32:0] data_i;
output [32:0] data_o;
input clock_i;
input en_i;
reg [32:0] data_o;
always @(posedge clock_i) begin
if(en_i) begin
data_o[32] <= data_i[32];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[31] <= data_i[31];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[30] <= data_i[30];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[29] <= data_i[29];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[28] <= data_i[28];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[27] <= data_i[27];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[26] <= data_i[26];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[25] <= data_i[25];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[24] <= data_i[24];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[23] <= data_i[23];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[22] <= data_i[22];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[21] <= data_i[21];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[20] <= data_i[20];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[19] <= data_i[19];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[18] <= data_i[18];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[17] <= data_i[17];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[16] <= data_i[16];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[15] <= data_i[15];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[14] <= data_i[14];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[13] <= data_i[13];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[12] <= data_i[12];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[11] <= data_i[11];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[10] <= data_i[10];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[9] <= data_i[9];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[8] <= data_i[8];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[7] <= data_i[7];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[6] <= data_i[6];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[5] <= data_i[5];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[4] <= data_i[4];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[3] <= data_i[3];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[2] <= data_i[2];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[1] <= data_i[1];
end
end
always @(posedge clock_i) begin
if(en_i) begin
data_o[0] <= data_i[0];
end
end
endmodule |
module data_arrays_0_ext(
input RW0_clk,
input [5:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [31:0] RW0_wdata,
output [31:0] RW0_rdata
);
fakeram45_64x32 mem (
.clk (RW0_clk ),
.rd_out (RW0_rdata ),
.ce_in (RW0_en ),
.we_in (RW0_wmode ),
.w_mask_in({ {8{RW0_wmask[3]}}
,{8{RW0_wmask[2]}}
,{8{RW0_wmask[1]}}
,{8{RW0_wmask[0]}}}
),
.addr_in (RW0_addr ),
.wd_in (RW0_wdata )
);
endmodule |
module tag_array_ext(
input RW0_clk,
input [1:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [0:0] RW0_wmask,
input [24:0] RW0_wdata,
output [24:0] RW0_rdata
);
reg reg_RW0_ren;
reg [1:0] reg_RW0_addr;
reg [24:0] ram [3:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 4; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for(i=0;i<1;i=i+1) begin
if(RW0_wmask[i]) begin
ram[RW0_addr][i*25 +: 25] <= RW0_wdata[i*25 +: 25];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[24:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule |
module mem_ext(
input W0_clk,
input [9:0] W0_addr,
input W0_en,
input [31:0] W0_data,
input [3:0] W0_mask,
input R0_clk,
input [9:0] R0_addr,
input R0_en,
output [31:0] R0_data
);
// WARNING: This should be a true dual port RAM (1read and 1write), however
// bsg_fakeram doesn't support this yet. Using a simple 1 rw as a
// place holder.
// WARNING: Ignoring R0_clk (assuming it is the same as W0_clk)
wire [9:0] addr;
wire en;
assign addr_int = W0_en ? W0_addr : R0_addr;
assign en = W0_en | R0_en;
fakeram45_1024x32 mem (
.clk (W0_clk ),
.rd_out (R0_data ),
.ce_in (en ),
.we_in (W0_en ),
.w_mask_in({ {8{W0_mask[3]}}
,{8{W0_mask[2]}}
,{8{W0_mask[1]}}
,{8{W0_mask[0]}}}
),
.addr_in (addr_int ),
.wd_in (W0_data )
);
endmodule |
module hard_mem_1rw_bit_mask_d64_w96_wrapper(clk_i, reset_i, data_i,
addr_i, v_i, w_mask_i, w_i, data_o);
input clk_i, reset_i, v_i, w_i;
input [95:0] data_i, w_mask_i;
input [5:0] addr_i;
output [95:0] data_o;
wire clk_i, reset_i, v_i, w_i;
wire [95:0] data_i, w_mask_i;
wire [5:0] addr_i;
wire [95:0] data_o;
fakeram45_64x96 mem (
.clk (clk_i ),
.rd_out (data_o ),
.ce_in (1'b1 ),
.we_in (w_i ),
.w_mask_in(w_mask_i),
.addr_in (addr_i ),
.wd_in (data_i )
);
endmodule |
module hard_mem_1rw_byte_mask_d512_w64_wrapper(clk_i, reset_i, data_i,
addr_i, v_i, write_mask_i, w_i, data_o);
input clk_i, reset_i, v_i, w_i;
input [63:0] data_i;
input [8:0] addr_i;
input [7:0] write_mask_i;
output [63:0] data_o;
wire clk_i, reset_i, v_i, w_i;
wire [63:0] data_i;
wire [8:0] addr_i;
wire [7:0] write_mask_i;
wire [63:0] data_o;
wire [63:0] wen;
fakeram45_512x64 mem (
.clk (clk_i ),
.rd_out (data_o ),
.ce_in (1'b1 ),
.we_in (w_i ),
.w_mask_in({{8{write_mask_i[7]}},
{8{write_mask_i[6]}},
{8{write_mask_i[5]}},
{8{write_mask_i[4]}},
{8{write_mask_i[3]}},
{8{write_mask_i[2]}},
{8{write_mask_i[1]}},
{8{write_mask_i[0]}}}
),
.addr_in (addr_i ),
.wd_in (data_i )
);
endmodule |
module hard_mem_1rw_bit_mask_d64_w15_wrapper(clk_i, reset_i, data_i,
addr_i, v_i, w_mask_i, w_i, data_o);
input clk_i, reset_i, v_i, w_i;
input [14:0] data_i, w_mask_i;
input [5:0] addr_i;
output [14:0] data_o;
wire clk_i, reset_i, v_i, w_i;
wire [14:0] data_i, w_mask_i;
wire [5:0] addr_i;
wire [14:0] data_o;
fakeram45_64x15 mem (
.clk (clk_i ),
.rd_out (data_o ),
.ce_in (1'b1 ),
.we_in (w_i ),
.w_mask_in(w_mask_i),
.addr_in (addr_i ),
.wd_in (data_i )
);
endmodule |
module aes_inv_cipher_top(clk, rst, kld, ld, done, key, text_in, text_out );
input clk, rst;
input kld, ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] wk0, wk1, wk2, wk3;
reg [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_ark, sa01_ark, sa02_ark, sa03_ark;
wire [7:0] sa10_ark, sa11_ark, sa12_ark, sa13_ark;
wire [7:0] sa20_ark, sa21_ark, sa22_ark, sa23_ark;
wire [7:0] sa30_ark, sa31_ark, sa32_ark, sa33_ark;
reg ld_r, go, done;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(done) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'h1;
else
if(go) dcnt <= #1 dcnt + 4'h1;
always @(posedge clk) done <= #1 (dcnt==4'hb) & !ld;
always @(posedge clk)
if(!rst) go <= #1 1'b0;
else
if(ld) go <= #1 1'b1;
else
if(done) go <= #1 1'b0;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00;
assign sa01_sr = sa01;
assign sa02_sr = sa02;
assign sa03_sr = sa03;
assign sa10_sr = sa13;
assign sa11_sr = sa10;
assign sa12_sr = sa11;
assign sa13_sr = sa12;
assign sa20_sr = sa22;
assign sa21_sr = sa23;
assign sa22_sr = sa20;
assign sa23_sr = sa21;
assign sa30_sr = sa31;
assign sa31_sr = sa32;
assign sa32_sr = sa33;
assign sa33_sr = sa30;
assign sa00_ark = sa00_sub ^ w0[31:24];
assign sa01_ark = sa01_sub ^ w1[31:24];
assign sa02_ark = sa02_sub ^ w2[31:24];
assign sa03_ark = sa03_sub ^ w3[31:24];
assign sa10_ark = sa10_sub ^ w0[23:16];
assign sa11_ark = sa11_sub ^ w1[23:16];
assign sa12_ark = sa12_sub ^ w2[23:16];
assign sa13_ark = sa13_sub ^ w3[23:16];
assign sa20_ark = sa20_sub ^ w0[15:08];
assign sa21_ark = sa21_sub ^ w1[15:08];
assign sa22_ark = sa22_sub ^ w2[15:08];
assign sa23_ark = sa23_sub ^ w3[15:08];
assign sa30_ark = sa30_sub ^ w0[07:00];
assign sa31_ark = sa31_sub ^ w1[07:00];
assign sa32_ark = sa32_sub ^ w2[07:00];
assign sa33_ark = sa33_sub ^ w3[07:00];
assign {sa00_next, sa10_next, sa20_next, sa30_next} = inv_mix_col(sa00_ark,sa10_ark,sa20_ark,sa30_ark);
assign {sa01_next, sa11_next, sa21_next, sa31_next} = inv_mix_col(sa01_ark,sa11_ark,sa21_ark,sa31_ark);
assign {sa02_next, sa12_next, sa22_next, sa32_next} = inv_mix_col(sa02_ark,sa12_ark,sa22_ark,sa32_ark);
assign {sa03_next, sa13_next, sa23_next, sa33_next} = inv_mix_col(sa03_ark,sa13_ark,sa23_ark,sa33_ark);
////////////////////////////////////////////////////////////////////
//
// Final Text Output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_ark;
always @(posedge clk) text_out[095:088] <= #1 sa01_ark;
always @(posedge clk) text_out[063:056] <= #1 sa02_ark;
always @(posedge clk) text_out[031:024] <= #1 sa03_ark;
always @(posedge clk) text_out[119:112] <= #1 sa10_ark;
always @(posedge clk) text_out[087:080] <= #1 sa11_ark;
always @(posedge clk) text_out[055:048] <= #1 sa12_ark;
always @(posedge clk) text_out[023:016] <= #1 sa13_ark;
always @(posedge clk) text_out[111:104] <= #1 sa20_ark;
always @(posedge clk) text_out[079:072] <= #1 sa21_ark;
always @(posedge clk) text_out[047:040] <= #1 sa22_ark;
always @(posedge clk) text_out[015:008] <= #1 sa23_ark;
always @(posedge clk) text_out[103:096] <= #1 sa30_ark;
always @(posedge clk) text_out[071:064] <= #1 sa31_ark;
always @(posedge clk) text_out[039:032] <= #1 sa32_ark;
always @(posedge clk) text_out[007:000] <= #1 sa33_ark;
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] inv_mix_col;
input [7:0] s0,s1,s2,s3;
begin
inv_mix_col[31:24]=pmul_e(s0)^pmul_b(s1)^pmul_d(s2)^pmul_9(s3);
inv_mix_col[23:16]=pmul_9(s0)^pmul_e(s1)^pmul_b(s2)^pmul_d(s3);
inv_mix_col[15:08]=pmul_d(s0)^pmul_9(s1)^pmul_e(s2)^pmul_b(s3);
inv_mix_col[07:00]=pmul_b(s0)^pmul_d(s1)^pmul_9(s2)^pmul_e(s3);
end
endfunction
// Some synthesis tools don't like xtime being called recursevly ...
function [7:0] pmul_e;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_e=eight^four^two;
end
endfunction
function [7:0] pmul_9;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_9=eight^b;
end
endfunction
function [7:0] pmul_d;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_d=eight^four^b;
end
endfunction
function [7:0] pmul_b;
input [7:0] b;
reg [7:0] two,four,eight;
begin
two=xtime(b);four=xtime(two);eight=xtime(four);pmul_b=eight^two^b;
end
endfunction
function [7:0] xtime;
input [7:0] b;xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Key Buffer
//
reg [127:0] kb[10:0];
reg [3:0] kcnt;
reg kdone;
reg kb_ld;
always @(posedge clk)
if(!rst) kcnt <= #1 4'ha;
else
if(kld) kcnt <= #1 4'ha;
else
if(kb_ld) kcnt <= #1 kcnt - 4'h1;
always @(posedge clk)
if(!rst) kb_ld <= #1 1'b0;
else
if(kld) kb_ld <= #1 1'b1;
else
if(kcnt==4'h0) kb_ld <= #1 1'b0;
always @(posedge clk) kdone <= #1 (kcnt==4'h0) & !kld;
always @(posedge clk) if(kb_ld) kb[kcnt] <= #1 {wk3, wk2, wk1, wk0};
always @(posedge clk) {w3, w2, w1, w0} <= #1 kb[dcnt];
////////////////////////////////////////////////////////////////////
//
// Modules
//
aes_key_expand_128 u0(
.clk( clk ),
.kld( kld ),
.key( key ),
.wo_0( wk0 ),
.wo_1( wk1 ),
.wo_2( wk2 ),
.wo_3( wk3 ));
aes_inv_sbox us00( .a( sa00_sr ), .d( sa00_sub ));
aes_inv_sbox us01( .a( sa01_sr ), .d( sa01_sub ));
aes_inv_sbox us02( .a( sa02_sr ), .d( sa02_sub ));
aes_inv_sbox us03( .a( sa03_sr ), .d( sa03_sub ));
aes_inv_sbox us10( .a( sa10_sr ), .d( sa10_sub ));
aes_inv_sbox us11( .a( sa11_sr ), .d( sa11_sub ));
aes_inv_sbox us12( .a( sa12_sr ), .d( sa12_sub ));
aes_inv_sbox us13( .a( sa13_sr ), .d( sa13_sub ));
aes_inv_sbox us20( .a( sa20_sr ), .d( sa20_sub ));
aes_inv_sbox us21( .a( sa21_sr ), .d( sa21_sub ));
aes_inv_sbox us22( .a( sa22_sr ), .d( sa22_sub ));
aes_inv_sbox us23( .a( sa23_sr ), .d( sa23_sub ));
aes_inv_sbox us30( .a( sa30_sr ), .d( sa30_sub ));
aes_inv_sbox us31( .a( sa31_sr ), .d( sa31_sub ));
aes_inv_sbox us32( .a( sa32_sr ), .d( sa32_sub ));
aes_inv_sbox us33( .a( sa33_sr ), .d( sa33_sub ));
endmodule |
module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3);
input clk;
input kld;
input [127:0] key;
output [31:0] wo_0, wo_1, wo_2, wo_3;
reg [31:0] w[3:0];
wire [31:0] tmp_w;
wire [31:0] subword;
wire [31:0] rcon;
assign wo_0 = w[0];
assign wo_1 = w[1];
assign wo_2 = w[2];
assign wo_3 = w[3];
always @(posedge clk) w[0] <= #1 kld ? key[127:096] : w[0]^subword^rcon;
always @(posedge clk) w[1] <= #1 kld ? key[095:064] : w[0]^w[1]^subword^rcon;
always @(posedge clk) w[2] <= #1 kld ? key[063:032] : w[0]^w[2]^w[1]^subword^rcon;
always @(posedge clk) w[3] <= #1 kld ? key[031:000] : w[0]^w[3]^w[2]^w[1]^subword^rcon;
assign tmp_w = w[3];
aes_sbox u0( .a(tmp_w[23:16]), .d(subword[31:24]));
aes_sbox u1( .a(tmp_w[15:08]), .d(subword[23:16]));
aes_sbox u2( .a(tmp_w[07:00]), .d(subword[15:08]));
aes_sbox u3( .a(tmp_w[31:24]), .d(subword[07:00]));
aes_rcon r0( .clk(clk), .kld(kld), .out(rcon));
endmodule |
module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
input clk, rst;
input ld;
output done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
reg done, ld_r;
reg [3:0] dcnt;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!rst) dcnt <= #1 4'h0;
else
if(ld) dcnt <= #1 4'hb;
else
if(|dcnt) dcnt <= #1 dcnt - 4'h1;
always @(posedge clk) done <= #1 !(|dcnt[3:1]) & dcnt[0] & !ld;
always @(posedge clk) if(ld) text_in_r <= #1 text_in;
always @(posedge clk) ld_r <= #1 ld;
////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//
always @(posedge clk) sa33 <= #1 ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 <= #1 ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 <= #1 ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 <= #1 ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 <= #1 ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 <= #1 ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 <= #1 ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 <= #1 ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 <= #1 ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 <= #1 ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 <= #1 ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 <= #1 ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 <= #1 ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 <= #1 ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 <= #1 ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 <= #1 ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;
////////////////////////////////////////////////////////////////////
//
// Round Permutations
//
assign sa00_sr = sa00_sub;
assign sa01_sr = sa01_sub;
assign sa02_sr = sa02_sub;
assign sa03_sr = sa03_sub;
assign sa10_sr = sa11_sub;
assign sa11_sr = sa12_sub;
assign sa12_sr = sa13_sub;
assign sa13_sr = sa10_sub;
assign sa20_sr = sa22_sub;
assign sa21_sr = sa23_sub;
assign sa22_sr = sa20_sub;
assign sa23_sr = sa21_sub;
assign sa30_sr = sa33_sub;
assign sa31_sr = sa30_sub;
assign sa32_sr = sa31_sub;
assign sa33_sr = sa32_sub;
assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc} = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc} = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc} = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc} = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
assign sa00_next = sa00_mc ^ w0[31:24];
assign sa01_next = sa01_mc ^ w1[31:24];
assign sa02_next = sa02_mc ^ w2[31:24];
assign sa03_next = sa03_mc ^ w3[31:24];
assign sa10_next = sa10_mc ^ w0[23:16];
assign sa11_next = sa11_mc ^ w1[23:16];
assign sa12_next = sa12_mc ^ w2[23:16];
assign sa13_next = sa13_mc ^ w3[23:16];
assign sa20_next = sa20_mc ^ w0[15:08];
assign sa21_next = sa21_mc ^ w1[15:08];
assign sa22_next = sa22_mc ^ w2[15:08];
assign sa23_next = sa23_mc ^ w3[15:08];
assign sa30_next = sa30_mc ^ w0[07:00];
assign sa31_next = sa31_mc ^ w1[07:00];
assign sa32_next = sa32_mc ^ w2[07:00];
assign sa33_next = sa33_mc ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Final text output
//
always @(posedge clk) text_out[127:120] <= #1 sa00_sr ^ w0[31:24];
always @(posedge clk) text_out[095:088] <= #1 sa01_sr ^ w1[31:24];
always @(posedge clk) text_out[063:056] <= #1 sa02_sr ^ w2[31:24];
always @(posedge clk) text_out[031:024] <= #1 sa03_sr ^ w3[31:24];
always @(posedge clk) text_out[119:112] <= #1 sa10_sr ^ w0[23:16];
always @(posedge clk) text_out[087:080] <= #1 sa11_sr ^ w1[23:16];
always @(posedge clk) text_out[055:048] <= #1 sa12_sr ^ w2[23:16];
always @(posedge clk) text_out[023:016] <= #1 sa13_sr ^ w3[23:16];
always @(posedge clk) text_out[111:104] <= #1 sa20_sr ^ w0[15:08];
always @(posedge clk) text_out[079:072] <= #1 sa21_sr ^ w1[15:08];
always @(posedge clk) text_out[047:040] <= #1 sa22_sr ^ w2[15:08];
always @(posedge clk) text_out[015:008] <= #1 sa23_sr ^ w3[15:08];
always @(posedge clk) text_out[103:096] <= #1 sa30_sr ^ w0[07:00];
always @(posedge clk) text_out[071:064] <= #1 sa31_sr ^ w1[07:00];
always @(posedge clk) text_out[039:032] <= #1 sa32_sr ^ w2[07:00];
always @(posedge clk) text_out[007:000] <= #1 sa33_sr ^ w3[07:00];
////////////////////////////////////////////////////////////////////
//
// Generic Functions
//
function [31:0] mix_col;
input [7:0] s0,s1,s2,s3;
reg [7:0] s0_o,s1_o,s2_o,s3_o;
begin
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
end
endfunction
function [7:0] xtime;
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&{8{b[7]}});
endfunction
////////////////////////////////////////////////////////////////////
//
// Modules
//
aes_key_expand_128 u0(
.clk( clk ),
.kld( ld ),
.key( key ),
.wo_0( w0 ),
.wo_1( w1 ),
.wo_2( w2 ),
.wo_3( w3 ));
aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
aes_sbox us33( .a( sa33 ), .d( sa33_sub ));
endmodule |
module aes_inv_sbox(a,d);
input [7:0] a;
output [7:0] d;
reg [7:0] d;
always @(a)
(* full_case, parallel_case *) case(a)
8'h00: d=8'h52;
8'h01: d=8'h09;
8'h02: d=8'h6a;
8'h03: d=8'hd5;
8'h04: d=8'h30;
8'h05: d=8'h36;
8'h06: d=8'ha5;
8'h07: d=8'h38;
8'h08: d=8'hbf;
8'h09: d=8'h40;
8'h0a: d=8'ha3;
8'h0b: d=8'h9e;
8'h0c: d=8'h81;
8'h0d: d=8'hf3;
8'h0e: d=8'hd7;
8'h0f: d=8'hfb;
8'h10: d=8'h7c;
8'h11: d=8'he3;
8'h12: d=8'h39;
8'h13: d=8'h82;
8'h14: d=8'h9b;
8'h15: d=8'h2f;
8'h16: d=8'hff;
8'h17: d=8'h87;
8'h18: d=8'h34;
8'h19: d=8'h8e;
8'h1a: d=8'h43;
8'h1b: d=8'h44;
8'h1c: d=8'hc4;
8'h1d: d=8'hde;
8'h1e: d=8'he9;
8'h1f: d=8'hcb;
8'h20: d=8'h54;
8'h21: d=8'h7b;
8'h22: d=8'h94;
8'h23: d=8'h32;
8'h24: d=8'ha6;
8'h25: d=8'hc2;
8'h26: d=8'h23;
8'h27: d=8'h3d;
8'h28: d=8'hee;
8'h29: d=8'h4c;
8'h2a: d=8'h95;
8'h2b: d=8'h0b;
8'h2c: d=8'h42;
8'h2d: d=8'hfa;
8'h2e: d=8'hc3;
8'h2f: d=8'h4e;
8'h30: d=8'h08;
8'h31: d=8'h2e;
8'h32: d=8'ha1;
8'h33: d=8'h66;
8'h34: d=8'h28;
8'h35: d=8'hd9;
8'h36: d=8'h24;
8'h37: d=8'hb2;
8'h38: d=8'h76;
8'h39: d=8'h5b;
8'h3a: d=8'ha2;
8'h3b: d=8'h49;
8'h3c: d=8'h6d;
8'h3d: d=8'h8b;
8'h3e: d=8'hd1;
8'h3f: d=8'h25;
8'h40: d=8'h72;
8'h41: d=8'hf8;
8'h42: d=8'hf6;
8'h43: d=8'h64;
8'h44: d=8'h86;
8'h45: d=8'h68;
8'h46: d=8'h98;
8'h47: d=8'h16;
8'h48: d=8'hd4;
8'h49: d=8'ha4;
8'h4a: d=8'h5c;
8'h4b: d=8'hcc;
8'h4c: d=8'h5d;
8'h4d: d=8'h65;
8'h4e: d=8'hb6;
8'h4f: d=8'h92;
8'h50: d=8'h6c;
8'h51: d=8'h70;
8'h52: d=8'h48;
8'h53: d=8'h50;
8'h54: d=8'hfd;
8'h55: d=8'hed;
8'h56: d=8'hb9;
8'h57: d=8'hda;
8'h58: d=8'h5e;
8'h59: d=8'h15;
8'h5a: d=8'h46;
8'h5b: d=8'h57;
8'h5c: d=8'ha7;
8'h5d: d=8'h8d;
8'h5e: d=8'h9d;
8'h5f: d=8'h84;
8'h60: d=8'h90;
8'h61: d=8'hd8;
8'h62: d=8'hab;
8'h63: d=8'h00;
8'h64: d=8'h8c;
8'h65: d=8'hbc;
8'h66: d=8'hd3;
8'h67: d=8'h0a;
8'h68: d=8'hf7;
8'h69: d=8'he4;
8'h6a: d=8'h58;
8'h6b: d=8'h05;
8'h6c: d=8'hb8;
8'h6d: d=8'hb3;
8'h6e: d=8'h45;
8'h6f: d=8'h06;
8'h70: d=8'hd0;
8'h71: d=8'h2c;
8'h72: d=8'h1e;
8'h73: d=8'h8f;
8'h74: d=8'hca;
8'h75: d=8'h3f;
8'h76: d=8'h0f;
8'h77: d=8'h02;
8'h78: d=8'hc1;
8'h79: d=8'haf;
8'h7a: d=8'hbd;
8'h7b: d=8'h03;
8'h7c: d=8'h01;
8'h7d: d=8'h13;
8'h7e: d=8'h8a;
8'h7f: d=8'h6b;
8'h80: d=8'h3a;
8'h81: d=8'h91;
8'h82: d=8'h11;
8'h83: d=8'h41;
8'h84: d=8'h4f;
8'h85: d=8'h67;
8'h86: d=8'hdc;
8'h87: d=8'hea;
8'h88: d=8'h97;
8'h89: d=8'hf2;
8'h8a: d=8'hcf;
8'h8b: d=8'hce;
8'h8c: d=8'hf0;
8'h8d: d=8'hb4;
8'h8e: d=8'he6;
8'h8f: d=8'h73;
8'h90: d=8'h96;
8'h91: d=8'hac;
8'h92: d=8'h74;
8'h93: d=8'h22;
8'h94: d=8'he7;
8'h95: d=8'had;
8'h96: d=8'h35;
8'h97: d=8'h85;
8'h98: d=8'he2;
8'h99: d=8'hf9;
8'h9a: d=8'h37;
8'h9b: d=8'he8;
8'h9c: d=8'h1c;
8'h9d: d=8'h75;
8'h9e: d=8'hdf;
8'h9f: d=8'h6e;
8'ha0: d=8'h47;
8'ha1: d=8'hf1;
8'ha2: d=8'h1a;
8'ha3: d=8'h71;
8'ha4: d=8'h1d;
8'ha5: d=8'h29;
8'ha6: d=8'hc5;
8'ha7: d=8'h89;
8'ha8: d=8'h6f;
8'ha9: d=8'hb7;
8'haa: d=8'h62;
8'hab: d=8'h0e;
8'hac: d=8'haa;
8'had: d=8'h18;
8'hae: d=8'hbe;
8'haf: d=8'h1b;
8'hb0: d=8'hfc;
8'hb1: d=8'h56;
8'hb2: d=8'h3e;
8'hb3: d=8'h4b;
8'hb4: d=8'hc6;
8'hb5: d=8'hd2;
8'hb6: d=8'h79;
8'hb7: d=8'h20;
8'hb8: d=8'h9a;
8'hb9: d=8'hdb;
8'hba: d=8'hc0;
8'hbb: d=8'hfe;
8'hbc: d=8'h78;
8'hbd: d=8'hcd;
8'hbe: d=8'h5a;
8'hbf: d=8'hf4;
8'hc0: d=8'h1f;
8'hc1: d=8'hdd;
8'hc2: d=8'ha8;
8'hc3: d=8'h33;
8'hc4: d=8'h88;
8'hc5: d=8'h07;
8'hc6: d=8'hc7;
8'hc7: d=8'h31;
8'hc8: d=8'hb1;
8'hc9: d=8'h12;
8'hca: d=8'h10;
8'hcb: d=8'h59;
8'hcc: d=8'h27;
8'hcd: d=8'h80;
8'hce: d=8'hec;
8'hcf: d=8'h5f;
8'hd0: d=8'h60;
8'hd1: d=8'h51;
8'hd2: d=8'h7f;
8'hd3: d=8'ha9;
8'hd4: d=8'h19;
8'hd5: d=8'hb5;
8'hd6: d=8'h4a;
8'hd7: d=8'h0d;
8'hd8: d=8'h2d;
8'hd9: d=8'he5;
8'hda: d=8'h7a;
8'hdb: d=8'h9f;
8'hdc: d=8'h93;
8'hdd: d=8'hc9;
8'hde: d=8'h9c;
8'hdf: d=8'hef;
8'he0: d=8'ha0;
8'he1: d=8'he0;
8'he2: d=8'h3b;
8'he3: d=8'h4d;
8'he4: d=8'hae;
8'he5: d=8'h2a;
8'he6: d=8'hf5;
8'he7: d=8'hb0;
8'he8: d=8'hc8;
8'he9: d=8'heb;
8'hea: d=8'hbb;
8'heb: d=8'h3c;
8'hec: d=8'h83;
8'hed: d=8'h53;
8'hee: d=8'h99;
8'hef: d=8'h61;
8'hf0: d=8'h17;
8'hf1: d=8'h2b;
8'hf2: d=8'h04;
8'hf3: d=8'h7e;
8'hf4: d=8'hba;
8'hf5: d=8'h77;
8'hf6: d=8'hd6;
8'hf7: d=8'h26;
8'hf8: d=8'he1;
8'hf9: d=8'h69;
8'hfa: d=8'h14;
8'hfb: d=8'h63;
8'hfc: d=8'h55;
8'hfd: d=8'h21;
8'hfe: d=8'h0c;
8'hff: d=8'h7d;
endcase
endmodule |
module plusarg_reader #(parameter FORMAT="borked=%d", DEFAULT=0, WIDTH=1) (
output [WIDTH-1:0] out
);
`ifdef SYNTHESIS
assign out = DEFAULT;
`else
reg [WIDTH-1:0] myplus;
assign out = myplus;
initial begin
if (!$value$plusargs(FORMAT, myplus)) myplus = DEFAULT;
end
`endif
endmodule |
module AsyncResetReg (d, q, en, clk, rst);
parameter RESET_VALUE = 0;
input wire d;
output reg q;
input wire en;
input wire clk;
input wire rst;
// There is a lot of initialization
// here you don't normally find in Verilog
// async registers because of scenarios in which reset
// is not actually asserted cleanly at time 0,
// and we want to make sure to properly model
// that, yet Chisel codebase is absolutely intolerant
// of Xs.
`ifndef SYNTHESIS
initial begin:B0
`ifdef RANDOMIZE
integer initvar;
reg [31:0] _RAND;
_RAND = {1{$random}};
q = _RAND[0];
`endif // RANDOMIZE
if (rst) begin
q = RESET_VALUE[0];
end
end
`endif
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= RESET_VALUE[0];
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg |
module ClockDivider3 (output reg clk_out, input clk_in);
reg delay;
initial begin
clk_out = 1'b0;
delay = 1'b0;
end
always @(posedge clk_in) begin
if (clk_out == 1'b0) begin
clk_out = 1'b1;
delay <= 1'b0;
end else if (delay == 1'b1) begin
clk_out = 1'b0;
delay <= 1'b0;
end else begin
delay <= 1'b1;
end
end
endmodule // ClockDivider3 |
module ClockDivider2 (output reg clk_out, input clk_in);
initial clk_out = 1'b0;
always @(posedge clk_in) begin
clk_out = ~clk_out; // Must use =, NOT <=
end
endmodule // ClockDivider2 |
module mc_obct_top(clk, rst, cs, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same, rfr_ack);
input clk, rst;
input [7:0] cs;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
input rfr_ack;
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
reg bank_open;
reg row_same;
reg any_bank_open;
wire bank_set_0;
wire bank_clr_0;
wire bank_clr_all_0;
wire bank_open_0;
wire row_same_0;
wire any_bank_open_0;
wire bank_set_1;
wire bank_clr_1;
wire bank_clr_all_1;
wire bank_open_1;
wire row_same_1;
wire any_bank_open_1;
wire bank_set_2;
wire bank_clr_2;
wire bank_clr_all_2;
wire bank_open_2;
wire row_same_2;
wire any_bank_open_2;
wire bank_set_3;
wire bank_clr_3;
wire bank_clr_all_3;
wire bank_open_3;
wire row_same_3;
wire any_bank_open_3;
wire bank_set_4;
wire bank_clr_4;
wire bank_clr_all_4;
wire bank_open_4;
wire row_same_4;
wire any_bank_open_4;
wire bank_set_5;
wire bank_clr_5;
wire bank_clr_all_5;
wire bank_open_5;
wire row_same_5;
wire any_bank_open_5;
wire bank_set_6;
wire bank_clr_6;
wire bank_clr_all_6;
wire bank_open_6;
wire row_same_6;
wire any_bank_open_6;
wire bank_set_7;
wire bank_clr_7;
wire bank_clr_all_7;
wire bank_open_7;
wire row_same_7;
wire any_bank_open_7;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign bank_set_0 = cs[0] & bank_set;
assign bank_set_1 = cs[1] & bank_set;
assign bank_set_2 = cs[2] & bank_set;
assign bank_set_3 = cs[3] & bank_set;
assign bank_set_4 = cs[4] & bank_set;
assign bank_set_5 = cs[5] & bank_set;
assign bank_set_6 = cs[6] & bank_set;
assign bank_set_7 = cs[7] & bank_set;
assign bank_clr_0 = cs[0] & bank_clr;
assign bank_clr_1 = cs[1] & bank_clr;
assign bank_clr_2 = cs[2] & bank_clr;
assign bank_clr_3 = cs[3] & bank_clr;
assign bank_clr_4 = cs[4] & bank_clr;
assign bank_clr_5 = cs[5] & bank_clr;
assign bank_clr_6 = cs[6] & bank_clr;
assign bank_clr_7 = cs[7] & bank_clr;
assign bank_clr_all_0 = (cs[0] & bank_clr_all) | rfr_ack;
assign bank_clr_all_1 = (cs[1] & bank_clr_all) | rfr_ack;
assign bank_clr_all_2 = (cs[2] & bank_clr_all) | rfr_ack;
assign bank_clr_all_3 = (cs[3] & bank_clr_all) | rfr_ack;
assign bank_clr_all_4 = (cs[4] & bank_clr_all) | rfr_ack;
assign bank_clr_all_5 = (cs[5] & bank_clr_all) | rfr_ack;
assign bank_clr_all_6 = (cs[6] & bank_clr_all) | rfr_ack;
assign bank_clr_all_7 = (cs[7] & bank_clr_all) | rfr_ack;
always @(posedge clk)
bank_open <= #1 (cs[0] & bank_open_0) | (cs[1] & bank_open_1) |
(cs[2] & bank_open_2) | (cs[3] & bank_open_3) |
(cs[4] & bank_open_4) | (cs[5] & bank_open_5) |
(cs[6] & bank_open_6) | (cs[7] & bank_open_7);
always @(posedge clk)
row_same <= #1 (cs[0] & row_same_0) | (cs[1] & row_same_1) |
(cs[2] & row_same_2) | (cs[3] & row_same_3) |
(cs[4] & row_same_4) | (cs[5] & row_same_5) |
(cs[6] & row_same_6) | (cs[7] & row_same_7);
always @(posedge clk)
any_bank_open <= #1 (cs[0] & any_bank_open_0) | (cs[1] & any_bank_open_1) |
(cs[2] & any_bank_open_2) | (cs[3] & any_bank_open_3) |
(cs[4] & any_bank_open_4) | (cs[5] & any_bank_open_5) |
(cs[6] & any_bank_open_6) | (cs[7] & any_bank_open_7);
////////////////////////////////////////////////////////////////////
//
// OBCT Modules for each Chip Select
//
mc_obct u0(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_0 ),
.bank_clr( bank_clr_0 ),
.bank_clr_all( bank_clr_all_0 ),
.bank_open( bank_open_0 ),
.any_bank_open( any_bank_open_0 ),
.row_same( row_same_0 )
);
`ifdef MC_HAVE_CS1
mc_obct u1(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_1 ),
.bank_clr( bank_clr_1 ),
.bank_clr_all( bank_clr_all_1 ),
.bank_open( bank_open_1 ),
.any_bank_open( any_bank_open_1 ),
.row_same( row_same_1 )
);
`else
mc_obct_dummy u1(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_1 ),
.bank_clr( bank_clr_1 ),
.bank_clr_all( bank_clr_all_1 ),
.bank_open( bank_open_1 ),
.any_bank_open( any_bank_open_1 ),
.row_same( row_same_1 )
);
`endif
`ifdef MC_HAVE_CS2
mc_obct u2(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_2 ),
.bank_clr( bank_clr_2 ),
.bank_clr_all( bank_clr_all_2 ),
.bank_open( bank_open_2 ),
.any_bank_open( any_bank_open_2 ),
.row_same( row_same_2 )
);
`else
mc_obct_dummy u2(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_2 ),
.bank_clr( bank_clr_2 ),
.bank_clr_all( bank_clr_all_2 ),
.bank_open( bank_open_2 ),
.any_bank_open( any_bank_open_2 ),
.row_same( row_same_2 )
);
`endif
`ifdef MC_HAVE_CS3
mc_obct u3(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_3 ),
.bank_clr( bank_clr_3 ),
.bank_clr_all( bank_clr_all_3 ),
.bank_open( bank_open_3 ),
.any_bank_open( any_bank_open_3 ),
.row_same( row_same_3 )
);
`else
mc_obct_dummy u3(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_3 ),
.bank_clr( bank_clr_3 ),
.bank_clr_all( bank_clr_all_3 ),
.bank_open( bank_open_3 ),
.any_bank_open( any_bank_open_3 ),
.row_same( row_same_3 )
);
`endif
`ifdef MC_HAVE_CS4
mc_obct u4(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_4 ),
.bank_clr( bank_clr_4 ),
.bank_clr_all( bank_clr_all_4 ),
.bank_open( bank_open_4 ),
.any_bank_open( any_bank_open_4 ),
.row_same( row_same_4 )
);
`else
mc_obct_dummy u4(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_4 ),
.bank_clr( bank_clr_4 ),
.bank_clr_all( bank_clr_all_4 ),
.bank_open( bank_open_4 ),
.any_bank_open( any_bank_open_4 ),
.row_same( row_same_4 )
);
`endif
`ifdef MC_HAVE_CS5
mc_obct u5(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_5 ),
.bank_clr( bank_clr_5 ),
.bank_clr_all( bank_clr_all_5 ),
.bank_open( bank_open_5 ),
.any_bank_open( any_bank_open_5 ),
.row_same( row_same_5 )
);
`else
mc_obct_dummy u5(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_5 ),
.bank_clr( bank_clr_5 ),
.bank_clr_all( bank_clr_all_5 ),
.bank_open( bank_open_5 ),
.any_bank_open( any_bank_open_5 ),
.row_same( row_same_5 )
);
`endif
`ifdef MC_HAVE_CS6
mc_obct u6(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_6 ),
.bank_clr( bank_clr_6 ),
.bank_clr_all( bank_clr_all_6 ),
.bank_open( bank_open_6 ),
.any_bank_open( any_bank_open_6 ),
.row_same( row_same_6 )
);
`else
mc_obct_dummy u6(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_6 ),
.bank_clr( bank_clr_6 ),
.bank_clr_all( bank_clr_all_6 ),
.bank_open( bank_open_6 ),
.any_bank_open( any_bank_open_6 ),
.row_same( row_same_6 )
);
`endif
`ifdef MC_HAVE_CS7
mc_obct u7(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_7 ),
.bank_clr( bank_clr_7 ),
.bank_clr_all( bank_clr_all_7 ),
.bank_open( bank_open_7 ),
.any_bank_open( any_bank_open_7 ),
.row_same( row_same_7 )
);
`else
mc_obct_dummy u7(
.clk( clk ),
.rst( rst ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set_7 ),
.bank_clr( bank_clr_7 ),
.bank_clr_all( bank_clr_all_7 ),
.bank_open( bank_open_7 ),
.any_bank_open( any_bank_open_7 ),
.row_same( row_same_7 )
);
`endif
endmodule |
module mc_adr_sel(clk, csc, tms, wb_ack_o, wb_stb_i, wb_addr_i, wb_we_i,
wb_write_go, wr_hold, cas_,
mc_addr, row_adr, bank_adr, rfr_ack,
cs_le, cmd_a10, row_sel, lmr_sel, next_adr, wr_cycle,
page_size);
input clk;
input [31:0] csc;
input [31:0] tms;
input wb_ack_o, wb_stb_i;
input [31:0] wb_addr_i;
input wb_we_i;
input wb_write_go;
input wr_hold;
input cas_;
output [23:0] mc_addr;
output [12:0] row_adr;
output [1:0] bank_adr;
input rfr_ack;
input cs_le;
input cmd_a10;
input row_sel;
input lmr_sel;
input next_adr;
input wr_cycle;
output [10:0] page_size;
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
reg [23:0] mc_addr_d;
reg [23:0] acs_addr;
wire [23:0] acs_addr_pl1;
reg [23:0] sram_addr;
wire [14:0] sdram_adr;
reg [12:0] row_adr;
reg [9:0] col_adr;
reg [1:0] bank_adr;
reg [10:0] page_size;
wire [2:0] mem_type;
wire [1:0] bus_width;
wire [1:0] mem_size;
wire bas;
// Aliases
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign mem_size = csc[7:6];
assign bas = csc[9];
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(mem_type or wr_hold or sdram_adr or acs_addr or sram_addr or wb_addr_i)
if(mem_type == `MC_MEM_TYPE_SDRAM) mc_addr_d = {9'h0, sdram_adr};
else
if(mem_type == `MC_MEM_TYPE_ACS) mc_addr_d = acs_addr;
else
if((mem_type == `MC_MEM_TYPE_SRAM) & wr_hold) mc_addr_d = sram_addr;
else mc_addr_d = wb_addr_i[25:2];
assign mc_addr = rfr_ack ? {mc_addr_d[23:11], 1'b1, mc_addr_d[9:0]} : mc_addr_d;
////////////////////////////////////////////////////////////////////
//
// Async Devices Address Latch & Counter
//
mc_incn_r #(24) u0( .clk( clk ),
.inc_in( acs_addr ),
.inc_out( acs_addr_pl1 ) );
always @(posedge clk)
if(wb_stb_i) sram_addr <= #1 wb_addr_i[25:2];
always @(posedge clk)
if(cs_le | wb_we_i)
case(bus_width) // synopsys full_case parallel_case
`MC_BW_8: acs_addr <= #1 wb_addr_i[23:0];
`MC_BW_16: acs_addr <= #1 wb_addr_i[24:1];
`MC_BW_32: acs_addr <= #1 wb_addr_i[25:2];
endcase
else
if(next_adr) acs_addr <= #1 acs_addr_pl1;
////////////////////////////////////////////////////////////////////
//
// SDRAM Address Mux
//
assign sdram_adr[12:0] = (lmr_sel & !cas_) ? tms[12:0] :
row_sel ? row_adr :
{2'h0, cmd_a10, col_adr};
assign sdram_adr[14:13] = bank_adr;
always @(posedge clk)
if(wr_cycle ? wb_ack_o : wb_stb_i)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
{`MC_BW_8, `MC_MEM_SIZE_128}: col_adr <= #1 wb_addr_i[11:2];
{`MC_BW_8, `MC_MEM_SIZE_256}: col_adr <= #1 wb_addr_i[11:2];
{`MC_BW_16, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_16, `MC_MEM_SIZE_128}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
{`MC_BW_16, `MC_MEM_SIZE_256}: col_adr <= #1 {1'h0, wb_addr_i[10:2]};
{`MC_BW_32, `MC_MEM_SIZE_64}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_32, `MC_MEM_SIZE_128}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
{`MC_BW_32, `MC_MEM_SIZE_256}: col_adr <= #1 {2'h0, wb_addr_i[09:2]};
endcase
always @(posedge clk)
if(cs_le)
begin
if(!bas)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[25:14]};
{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[26:14];
{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[24:13]};
{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[25:13];
{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[22:12]};
{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
endcase
else
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
{`MC_BW_8, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[23:12]};
{`MC_BW_8, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[24:12];
{`MC_BW_16, `MC_MEM_SIZE_64}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
{`MC_BW_16, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[22:11]};
{`MC_BW_16, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[23:11];
{`MC_BW_32, `MC_MEM_SIZE_64}: row_adr <= #1 {2'h0, wb_addr_i[20:10]};
{`MC_BW_32, `MC_MEM_SIZE_128}: row_adr <= #1 {1'h0, wb_addr_i[21:10]};
{`MC_BW_32, `MC_MEM_SIZE_256}: row_adr <= #1 wb_addr_i[22:10];
endcase
end
always @(posedge clk)
if(cs_le)
begin
if(!bas)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[13:12];
{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[13:12];
{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[12:11];
{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[11:10];
{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[11:10];
endcase
else
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[24:23];
{`MC_BW_8, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[25:24];
{`MC_BW_8, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[26:25];
{`MC_BW_16, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[23:22];
{`MC_BW_16, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[24:23];
{`MC_BW_16, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[25:24];
{`MC_BW_32, `MC_MEM_SIZE_64}: bank_adr <= #1 wb_addr_i[22:21];
{`MC_BW_32, `MC_MEM_SIZE_128}: bank_adr <= #1 wb_addr_i[23:22];
{`MC_BW_32, `MC_MEM_SIZE_256}: bank_adr <= #1 wb_addr_i[24:23];
endcase
end
always @(bus_width or mem_size)
casex({bus_width, mem_size}) // synopsys full_case parallel_case
{`MC_BW_8, `MC_MEM_SIZE_64}: page_size = 11'd512;
{`MC_BW_8, `MC_MEM_SIZE_128}: page_size = 11'd1024;
{`MC_BW_8, `MC_MEM_SIZE_256}: page_size = 11'd1024;
{`MC_BW_16, `MC_MEM_SIZE_64}: page_size = 11'd256;
{`MC_BW_16, `MC_MEM_SIZE_128}: page_size = 11'd512;
{`MC_BW_16, `MC_MEM_SIZE_256}: page_size = 11'd512;
{`MC_BW_32, `MC_MEM_SIZE_64}: page_size = 11'd256;
{`MC_BW_32, `MC_MEM_SIZE_128}: page_size = 11'd256;
{`MC_BW_32, `MC_MEM_SIZE_256}: page_size = 11'd256;
endcase
endmodule |
module mc_dp( clk, rst, csc,
wb_cyc_i, wb_stb_i, wb_ack_o, mem_ack, wb_data_i, wb_data_o,
wb_read_go, wb_we_i,
mc_clk, mc_data_del, mc_dp_i, mc_data_o, mc_dp_o,
dv, pack_le0, pack_le1, pack_le2,
byte_en, par_err
);
input clk, rst;
input [31:0] csc;
input wb_cyc_i;
input wb_stb_i;
input mem_ack;
input wb_ack_o;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input wb_read_go;
input wb_we_i;
input mc_clk;
input [35:0] mc_data_del;
input [3:0] mc_dp_i;
output [31:0] mc_data_o;
output [3:0] mc_dp_o;
input dv;
input pack_le0, pack_le1, pack_le2; // Pack Latch Enable
input [3:0] byte_en; // High Active byte enables
output par_err;
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
reg [31:0] wb_data_o;
reg [31:0] mc_data_o;
wire [35:0] rd_fifo_out;
wire rd_fifo_clr;
reg [3:0] mc_dp_o;
reg par_err_r;
reg [7:0] byte0, byte1, byte2;
reg [31:0] mc_data_d;
wire [2:0] mem_type;
wire [1:0] bus_width;
wire pen;
wire re;
// Aliases
assign mem_type = csc[3:1];
assign bus_width = csc[5:4];
assign pen = csc[11];
////////////////////////////////////////////////////////////////////
//
// WB READ Data Path
//
always @(mem_type or rd_fifo_out or mc_data_d)
if( (mem_type == `MC_MEM_TYPE_SDRAM) |
(mem_type == `MC_MEM_TYPE_SRAM) ) wb_data_o = rd_fifo_out[31:0];
else wb_data_o = mc_data_d;
//assign rd_fifo_clr = !(rst | !wb_cyc_i | (wb_we_i & wb_stb_i) );
assign rd_fifo_clr = !wb_cyc_i | (wb_we_i & wb_stb_i);
assign re = wb_ack_o & wb_read_go;
mc_rd_fifo u0(
.clk( clk ),
.rst( rst ),
.clr( rd_fifo_clr ),
.din( mc_data_del ),
.we( dv ),
.dout( rd_fifo_out ),
.re( re )
);
////////////////////////////////////////////////////////////////////
//
// WB WRITE Data Path
//
always @(posedge clk)
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_data_o <= #1 wb_data_i;
////////////////////////////////////////////////////////////////////
//
// Read Data Packing
//
always @(posedge clk)
if(pack_le0) byte0 <= #1 mc_data_del[7:0];
always @(posedge clk)
if(pack_le1 & (bus_width == `MC_BW_8)) byte1 <= #1 mc_data_del[7:0];
else
if(pack_le0 & (bus_width == `MC_BW_16)) byte1 <= #1 mc_data_del[15:8];
always @(posedge clk)
if(pack_le2) byte2 <= #1 mc_data_del[7:0];
always @(bus_width or mc_data_del or byte0 or byte1 or byte2)
if(bus_width == `MC_BW_8) mc_data_d = {mc_data_del[7:0], byte2, byte1, byte0};
else
if(bus_width == `MC_BW_16) mc_data_d = {mc_data_del[15:0], byte1, byte0};
else mc_data_d = mc_data_del[31:0];
////////////////////////////////////////////////////////////////////
//
// Parity Generation
//
always @(posedge clk)
if(wb_ack_o | (mem_type != `MC_MEM_TYPE_SDRAM) )
mc_dp_o <= #1 { ^wb_data_i[31:24], ^wb_data_i[23:16],
^wb_data_i[15:08], ^wb_data_i[07:00] };
////////////////////////////////////////////////////////////////////
//
// Parity Checking
//
assign par_err = !wb_we_i & mem_ack & pen & (
(( ^rd_fifo_out[31:24] ^ rd_fifo_out[35] ) & byte_en[3] ) |
(( ^rd_fifo_out[23:16] ^ rd_fifo_out[34] ) & byte_en[2] ) |
(( ^rd_fifo_out[15:08] ^ rd_fifo_out[33] ) & byte_en[1] ) |
(( ^rd_fifo_out[07:00] ^ rd_fifo_out[32] ) & byte_en[0] )
);
endmodule |
Subsets and Splits