module
stringlengths 21
82.9k
|
|---|
module pci_delayed_write_reg
(
reset_in,
req_clk_in,
comp_wdata_out,
req_we_in,
req_wdata_in
);
// system inputs
input reset_in,
req_clk_in ; // request clock input
output [31:0] comp_wdata_out ; // data output
input req_we_in ; // write enable input
input [31:0] req_wdata_in ; // data input - latched with posedge of req_clk_in when req_we_in is high
reg [31:0] comp_wdata_out ;
// write request operation
always@(posedge req_clk_in or posedge reset_in)
begin
if (reset_in)
comp_wdata_out <= #`FF_DELAY 32'h0000_0000 ;
else
if (req_we_in)
comp_wdata_out <= #`FF_DELAY req_wdata_in ;
end
endmodule // DELAYED_WRITE_REG |
module pci_wb_slave_unit
(
reset_in,
wb_clock_in,
pci_clock_in,
ADDR_I,
SDATA_I,
SDATA_O,
CYC_I,
STB_I,
WE_I,
SEL_I,
ACK_O,
RTY_O,
ERR_O,
CAB_I,
wbu_map_in,
wbu_pref_en_in,
wbu_mrl_en_in,
wbu_pci_drcomp_pending_in,
wbu_conf_data_in,
wbu_pciw_empty_in,
wbu_bar0_in,
wbu_bar1_in,
wbu_bar2_in,
wbu_bar3_in,
wbu_bar4_in,
wbu_bar5_in,
wbu_am0_in,
wbu_am1_in,
wbu_am2_in,
wbu_am3_in,
wbu_am4_in,
wbu_am5_in,
wbu_ta0_in,
wbu_ta1_in,
wbu_ta2_in,
wbu_ta3_in,
wbu_ta4_in,
wbu_ta5_in,
wbu_at_en_in,
wbu_ccyc_addr_in ,
wbu_master_enable_in,
wb_init_complete_in,
wbu_cache_line_size_not_zero,
wbu_cache_line_size_in,
wbu_pciif_gnt_in,
wbu_pciif_frame_in,
wbu_pciif_irdy_in,
wbu_pciif_trdy_in,
wbu_pciif_trdy_reg_in,
wbu_pciif_stop_in,
wbu_pciif_stop_reg_in,
wbu_pciif_devsel_in,
wbu_pciif_devsel_reg_in,
wbu_pciif_ad_reg_in,
wbu_pciif_req_out,
wbu_pciif_frame_out,
wbu_pciif_frame_en_out,
wbu_pciif_frame_en_in,
wbu_pciif_frame_out_in,
wbu_pciif_frame_load_out,
wbu_pciif_irdy_out,
wbu_pciif_irdy_en_out,
wbu_pciif_ad_out,
wbu_pciif_ad_en_out,
wbu_pciif_cbe_out,
wbu_pciif_cbe_en_out,
wbu_err_addr_out,
wbu_err_bc_out,
wbu_err_signal_out,
wbu_err_source_out,
wbu_err_rty_exp_out,
wbu_tabort_rec_out,
wbu_mabort_rec_out,
wbu_conf_offset_out,
wbu_conf_renable_out,
wbu_conf_wenable_out,
wbu_conf_be_out,
wbu_conf_data_out,
wbu_del_read_comp_pending_out,
wbu_wbw_fifo_empty_out,
wbu_latency_tim_val_in,
wbu_ad_load_out,
wbu_ad_load_on_transfer_out
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
input reset_in,
wb_clock_in,
pci_clock_in ;
input [31:0] ADDR_I ;
input [31:0] SDATA_I ;
output [31:0] SDATA_O ;
input CYC_I ;
input STB_I ;
input WE_I ;
input [3:0] SEL_I ;
output ACK_O ;
output RTY_O ;
output ERR_O ;
input CAB_I ;
input [5:0] wbu_map_in ;
input [5:0] wbu_pref_en_in ;
input [5:0] wbu_mrl_en_in ;
input wbu_pci_drcomp_pending_in ;
input [31:0] wbu_conf_data_in ;
input wbu_pciw_empty_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in ;
input [5:0] wbu_at_en_in ;
input [23:0] wbu_ccyc_addr_in ;
input wbu_master_enable_in ;
input wb_init_complete_in ;
input wbu_cache_line_size_not_zero ;
input [7:0] wbu_cache_line_size_in ;
input wbu_pciif_gnt_in ;
input wbu_pciif_frame_in ;
input wbu_pciif_frame_en_in ;
input wbu_pciif_irdy_in ;
input wbu_pciif_trdy_in;
input wbu_pciif_trdy_reg_in;
input wbu_pciif_stop_in ;
input wbu_pciif_stop_reg_in ;
input wbu_pciif_devsel_in ;
input wbu_pciif_devsel_reg_in ;
input [31:0] wbu_pciif_ad_reg_in ;
output wbu_pciif_req_out ;
output wbu_pciif_frame_out ;
output wbu_pciif_frame_en_out ;
input wbu_pciif_frame_out_in ;
output wbu_pciif_frame_load_out ;
output wbu_pciif_irdy_out ;
output wbu_pciif_irdy_en_out ;
output [31:0] wbu_pciif_ad_out ;
output wbu_pciif_ad_en_out ;
output [3:0] wbu_pciif_cbe_out ;
output wbu_pciif_cbe_en_out ;
output [31:0] wbu_err_addr_out ;
output [3:0] wbu_err_bc_out ;
output wbu_err_signal_out ;
output wbu_err_source_out ;
output wbu_err_rty_exp_out ;
output wbu_tabort_rec_out ;
output wbu_mabort_rec_out ;
output [11:0] wbu_conf_offset_out ;
output wbu_conf_renable_out ;
output wbu_conf_wenable_out ;
output [3:0] wbu_conf_be_out ;
output [31:0] wbu_conf_data_out ;
output wbu_del_read_comp_pending_out ;
output wbu_wbw_fifo_empty_out ;
input [7:0] wbu_latency_tim_val_in ;
output wbu_ad_load_out ;
output wbu_ad_load_on_transfer_out ;
`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
// pci master interface outputs
wire [31:0] pcim_if_address_out ;
wire [3:0] pcim_if_bc_out ;
wire [31:0] pcim_if_data_out ;
wire [3:0] pcim_if_be_out ;
wire pcim_if_req_out ;
wire pcim_if_rdy_out ;
wire pcim_if_last_out ;
wire pcim_if_wbw_renable_out ;
wire pcim_if_wbr_wenable_out ;
wire [31:0] pcim_if_wbr_data_out ;
wire [3:0] pcim_if_wbr_be_out ;
wire [3:0] pcim_if_wbr_control_out ;
wire pcim_if_del_complete_out ;
wire pcim_if_del_error_out ;
wire pcim_if_del_rty_exp_out ;
wire [31:0] pcim_if_err_addr_out ;
wire [3:0] pcim_if_err_bc_out ;
wire pcim_if_err_signal_out ;
wire pcim_if_err_source_out ;
wire pcim_if_err_rty_exp_out ;
wire pcim_if_tabort_out ;
wire pcim_if_mabort_out ;
wire [31:0] pcim_if_next_data_out ;
wire [3:0] pcim_if_next_be_out ;
wire pcim_if_next_last_out ;
wire pcim_if_posted_write_not_present_out ;
wire pcim_sm_req_out ;
wire pcim_sm_frame_out ;
wire pcim_sm_frame_en_out ;
wire pcim_sm_irdy_out ;
wire pcim_sm_irdy_en_out ;
wire [31:0] pcim_sm_ad_out ;
wire pcim_sm_ad_en_out ;
wire [3:0] pcim_sm_cbe_out ;
wire pcim_sm_cbe_en_out ;
wire pcim_sm_ad_load_out ;
wire pcim_sm_ad_load_on_transfer_out ;
wire pcim_sm_wait_out ;
wire pcim_sm_wtransfer_out ;
wire pcim_sm_rtransfer_out ;
wire pcim_sm_retry_out ;
wire pcim_sm_rerror_out ;
wire pcim_sm_first_out ;
wire pcim_sm_mabort_out ;
wire pcim_sm_frame_load_out ;
assign wbu_pciif_frame_load_out = pcim_sm_frame_load_out ;
assign wbu_err_addr_out = pcim_if_err_addr_out ;
assign wbu_err_bc_out = pcim_if_err_bc_out ;
assign wbu_err_signal_out = pcim_if_err_signal_out ;
assign wbu_err_source_out = pcim_if_err_source_out ;
assign wbu_err_rty_exp_out = pcim_if_err_rty_exp_out ;
assign wbu_tabort_rec_out = pcim_if_tabort_out ;
assign wbu_mabort_rec_out = pcim_if_mabort_out ;
assign wbu_wbw_fifo_empty_out = pcim_if_posted_write_not_present_out ;
// pci master state machine outputs
// pci interface signals
assign wbu_pciif_req_out = pcim_sm_req_out ;
assign wbu_pciif_frame_out = pcim_sm_frame_out ;
assign wbu_pciif_frame_en_out = pcim_sm_frame_en_out ;
assign wbu_pciif_irdy_out = pcim_sm_irdy_out ;
assign wbu_pciif_irdy_en_out = pcim_sm_irdy_en_out ;
assign wbu_pciif_ad_out = pcim_sm_ad_out ;
assign wbu_pciif_ad_en_out = pcim_sm_ad_en_out ;
assign wbu_pciif_cbe_out = pcim_sm_cbe_out ;
assign wbu_pciif_cbe_en_out = pcim_sm_cbe_en_out ;
assign wbu_ad_load_out = pcim_sm_ad_load_out ;
assign wbu_ad_load_on_transfer_out = pcim_sm_ad_load_on_transfer_out ;
// signals to internal of the core
wire [31:0] pcim_sm_data_out ;
// wishbone slave state machine outputs
wire [3:0] wbs_sm_del_bc_out ;
wire wbs_sm_del_req_out ;
wire wbs_sm_del_done_out ;
wire wbs_sm_del_burst_out ;
wire wbs_sm_del_write_out ;
wire [11:0] wbs_sm_conf_offset_out ;
wire wbs_sm_conf_renable_out ;
wire wbs_sm_conf_wenable_out ;
wire [3:0] wbs_sm_conf_be_out ;
wire [31:0] wbs_sm_conf_data_out ;
wire [31:0] wbs_sm_data_out ;
wire [3:0] wbs_sm_cbe_out ;
wire wbs_sm_wbw_wenable_out ;
wire [3:0] wbs_sm_wbw_control_out ;
wire wbs_sm_wbr_renable_out ;
wire wbs_sm_wbr_flush_out ;
wire wbs_sm_del_in_progress_out ;
wire [31:0] wbs_sm_sdata_out ;
wire wbs_sm_ack_out ;
wire wbs_sm_rty_out ;
wire wbs_sm_err_out ;
wire wbs_sm_sample_address_out ;
assign wbu_conf_offset_out = wbs_sm_conf_offset_out ;
assign wbu_conf_renable_out = wbs_sm_conf_renable_out ;
assign wbu_conf_wenable_out = wbs_sm_conf_wenable_out ;
assign wbu_conf_be_out = ~wbs_sm_conf_be_out ;
assign wbu_conf_data_out = wbs_sm_conf_data_out ;
assign SDATA_O = wbs_sm_sdata_out ;
assign ACK_O = wbs_sm_ack_out ;
assign RTY_O = wbs_sm_rty_out ;
assign ERR_O = wbs_sm_err_out ;
// wbw_wbr fifo outputs
// wbw_fifo_outputs:
wire [31:0] fifos_wbw_addr_data_out ;
wire [3:0] fifos_wbw_cbe_out ;
wire [3:0] fifos_wbw_control_out ;
wire fifos_wbw_almost_full_out ;
wire fifos_wbw_full_out ;
wire fifos_wbw_empty_out ;
wire fifos_wbw_transaction_ready_out ;
// wbr_fifo_outputs
wire [31:0] fifos_wbr_data_out ;
wire [3:0] fifos_wbr_be_out ;
wire [3:0] fifos_wbr_control_out ;
wire fifos_wbr_empty_out ;
// address multiplexer outputs
wire [5:0] amux_hit_out ;
wire [31:0] amux_address_out ;
// delayed transaction logic outputs
wire [31:0] del_sync_addr_out ;
wire [3:0] del_sync_be_out ;
wire del_sync_we_out ;
wire del_sync_comp_req_pending_out ;
wire del_sync_comp_comp_pending_out ;
wire del_sync_req_req_pending_out ;
wire del_sync_req_comp_pending_out ;
wire [3:0] del_sync_bc_out ;
wire del_sync_status_out ;
wire del_sync_comp_flush_out ;
wire del_sync_burst_out ;
assign wbu_del_read_comp_pending_out = del_sync_comp_comp_pending_out ;
// delayed write storage output
wire [31:0] del_write_data_out ;
// config. cycle address decoder output
wire [31:0] ccyc_addr_out ;
// WISHBONE slave interface inputs
wire [4:0] wbs_sm_hit_in = amux_hit_out[5:1] ;
wire wbs_sm_conf_hit_in = amux_hit_out[0] ;
wire [4:0] wbs_sm_map_in = wbu_map_in[5:1] ;
wire [4:0] wbs_sm_pref_en_in = wbu_pref_en_in[5:1] ;
wire [4:0] wbs_sm_mrl_en_in = wbu_mrl_en_in[5:1] ;
wire [31:0] wbs_sm_addr_in = amux_address_out ;
wire [3:0] wbs_sm_del_bc_in = del_sync_bc_out ;
wire wbs_sm_del_req_pending_in = del_sync_req_req_pending_out ;
wire wbs_sm_wb_del_comp_pending_in = del_sync_req_comp_pending_out ;
wire wbs_sm_pci_drcomp_pending_in = wbu_pci_drcomp_pending_in ;
wire wbs_sm_del_write_in = del_sync_we_out ;
wire wbs_sm_del_error_in = del_sync_status_out ;
wire [31:0] wbs_sm_del_addr_in = del_sync_addr_out ;
wire [3:0] wbs_sm_del_be_in = del_sync_be_out ;
wire [31:0] wbs_sm_conf_data_in = wbu_conf_data_in ;
wire wbs_sm_wbw_almost_full_in = fifos_wbw_almost_full_out ;
wire wbs_sm_wbw_full_in = fifos_wbw_full_out ;
wire [3:0] wbs_sm_wbr_be_in = fifos_wbr_be_out ;
wire [31:0] wbs_sm_wbr_data_in = fifos_wbr_data_out ;
wire [3:0] wbs_sm_wbr_control_in = fifos_wbr_control_out ;
wire wbs_sm_wbr_empty_in = fifos_wbr_empty_out ;
wire wbs_sm_pciw_empty_in = wbu_pciw_empty_in ;
wire wbs_sm_lock_in = ~wbu_master_enable_in ;
wire wbs_sm_cache_line_size_not_zero = wbu_cache_line_size_not_zero ;
wire wbs_sm_cyc_in = CYC_I ;
wire wbs_sm_stb_in = STB_I ;
wire wbs_sm_we_in = WE_I ;
wire [3:0] wbs_sm_sel_in = SEL_I ;
wire [31:0] wbs_sm_sdata_in = SDATA_I ;
wire wbs_sm_cab_in = CAB_I ;
wire [31:0] wbs_sm_ccyc_addr_in = ccyc_addr_out ;
wire wbs_sm_init_complete_in = wb_init_complete_in ;
// WISHBONE slave interface instantiation
pci_wb_slave wishbone_slave(
.wb_clock_in (wb_clock_in) ,
.reset_in (reset_in) ,
.wb_hit_in (wbs_sm_hit_in) ,
.wb_conf_hit_in (wbs_sm_conf_hit_in) ,
.wb_map_in (wbs_sm_map_in) ,
.wb_pref_en_in (wbs_sm_pref_en_in) ,
.wb_mrl_en_in (wbs_sm_mrl_en_in) ,
.wb_addr_in (wbs_sm_addr_in),
.del_bc_in (wbs_sm_del_bc_in),
.wb_del_req_pending_in (wbs_sm_del_req_pending_in),
.wb_del_comp_pending_in (wbs_sm_wb_del_comp_pending_in),
.pci_drcomp_pending_in (wbs_sm_pci_drcomp_pending_in),
.del_bc_out (wbs_sm_del_bc_out),
.del_req_out (wbs_sm_del_req_out),
.del_done_out (wbs_sm_del_done_out),
.del_burst_out (wbs_sm_del_burst_out),
.del_write_out (wbs_sm_del_write_out),
.del_write_in (wbs_sm_del_write_in),
.del_error_in (wbs_sm_del_error_in),
.wb_del_addr_in (wbs_sm_del_addr_in),
.wb_del_be_in (wbs_sm_del_be_in),
.wb_conf_offset_out (wbs_sm_conf_offset_out),
.wb_conf_renable_out (wbs_sm_conf_renable_out),
.wb_conf_wenable_out (wbs_sm_conf_wenable_out),
.wb_conf_be_out (wbs_sm_conf_be_out),
.wb_conf_data_in (wbs_sm_conf_data_in),
.wb_conf_data_out (wbs_sm_conf_data_out),
.wb_data_out (wbs_sm_data_out),
.wb_cbe_out (wbs_sm_cbe_out),
.wbw_fifo_wenable_out (wbs_sm_wbw_wenable_out),
.wbw_fifo_control_out (wbs_sm_wbw_control_out),
.wbw_fifo_almost_full_in (wbs_sm_wbw_almost_full_in),
.wbw_fifo_full_in (wbs_sm_wbw_full_in),
.wbr_fifo_renable_out (wbs_sm_wbr_renable_out),
.wbr_fifo_be_in (wbs_sm_wbr_be_in),
.wbr_fifo_data_in (wbs_sm_wbr_data_in),
.wbr_fifo_control_in (wbs_sm_wbr_control_in),
.wbr_fifo_flush_out (wbs_sm_wbr_flush_out),
.wbr_fifo_empty_in (wbs_sm_wbr_empty_in),
.pciw_fifo_empty_in (wbs_sm_pciw_empty_in),
.wbs_lock_in (wbs_sm_lock_in),
.init_complete_in (wbs_sm_init_complete_in),
.cache_line_size_not_zero (wbs_sm_cache_line_size_not_zero),
.del_in_progress_out (wbs_sm_del_in_progress_out),
.ccyc_addr_in (wbs_sm_ccyc_addr_in),
.sample_address_out (wbs_sm_sample_address_out),
.CYC_I (wbs_sm_cyc_in),
.STB_I (wbs_sm_stb_in),
.WE_I (wbs_sm_we_in),
.SEL_I (wbs_sm_sel_in),
.SDATA_I (wbs_sm_sdata_in),
.SDATA_O (wbs_sm_sdata_out),
.ACK_O (wbs_sm_ack_out),
.RTY_O (wbs_sm_rty_out),
.ERR_O (wbs_sm_err_out),
.CAB_I (wbs_sm_cab_in)
);
// wbw_wbr_fifos inputs
// WBW_FIFO inputs
wire fifos_wbw_wenable_in = wbs_sm_wbw_wenable_out;
wire [31:0] fifos_wbw_addr_data_in = wbs_sm_data_out ;
wire [3:0] fifos_wbw_cbe_in = wbs_sm_cbe_out ;
wire [3:0] fifos_wbw_control_in = wbs_sm_wbw_control_out ;
wire fifos_wbw_renable_in = pcim_if_wbw_renable_out ;
//wire fifos_wbw_flush_in = 1'b0 ; flush for write fifo not used
// WBR_FIFO inputs
wire fifos_wbr_wenable_in = pcim_if_wbr_wenable_out ;
wire [31:0] fifos_wbr_data_in = pcim_if_wbr_data_out ;
wire [3:0] fifos_wbr_be_in = pcim_if_wbr_be_out ;
wire [3:0] fifos_wbr_control_in = pcim_if_wbr_control_out ;
wire fifos_wbr_renable_in = wbs_sm_wbr_renable_out ;
wire fifos_wbr_flush_in = wbs_sm_wbr_flush_out || del_sync_comp_flush_out ;
// WBW_FIFO and WBR_FIFO instantiation
pci_wbw_wbr_fifos fifos
(
.wb_clock_in (wb_clock_in),
.pci_clock_in (pci_clock_in),
.reset_in (reset_in),
.wbw_wenable_in (fifos_wbw_wenable_in),
.wbw_addr_data_in (fifos_wbw_addr_data_in),
.wbw_cbe_in (fifos_wbw_cbe_in),
.wbw_control_in (fifos_wbw_control_in),
.wbw_renable_in (fifos_wbw_renable_in),
.wbw_addr_data_out (fifos_wbw_addr_data_out),
.wbw_cbe_out (fifos_wbw_cbe_out),
.wbw_control_out (fifos_wbw_control_out),
// .wbw_flush_in (fifos_wbw_flush_in), // flush for write fifo not used
.wbw_almost_full_out (fifos_wbw_almost_full_out),
.wbw_full_out (fifos_wbw_full_out),
.wbw_empty_out (fifos_wbw_empty_out),
.wbw_transaction_ready_out (fifos_wbw_transaction_ready_out),
.wbr_wenable_in (fifos_wbr_wenable_in),
.wbr_data_in (fifos_wbr_data_in),
.wbr_be_in (fifos_wbr_be_in),
.wbr_control_in (fifos_wbr_control_in),
.wbr_renable_in (fifos_wbr_renable_in),
.wbr_data_out (fifos_wbr_data_out),
.wbr_be_out (fifos_wbr_be_out),
.wbr_control_out (fifos_wbr_control_out),
.wbr_flush_in (fifos_wbr_flush_in),
.wbr_empty_out (fifos_wbr_empty_out)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
) ;
wire [31:0] amux_addr_in = ADDR_I ;
wire amux_sample_address_in = wbs_sm_sample_address_out ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar0_in = wbu_bar0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar1_in = wbu_bar1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar2_in = wbu_bar2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar3_in = wbu_bar3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar4_in = wbu_bar4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_bar5_in = wbu_bar5_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am0_in = wbu_am0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am1_in = wbu_am1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am2_in = wbu_am2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am3_in = wbu_am3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am4_in = wbu_am4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_am5_in = wbu_am5_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta0_in = wbu_ta0_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta1_in = wbu_ta1_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta2_in = wbu_ta2_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta3_in = wbu_ta3_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta4_in = wbu_ta4_in ;
wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] amux_ta5_in = wbu_ta5_in ;
wire [5:0] amux_at_en_in = wbu_at_en_in ;
pci_wb_addr_mux wb_addr_dec
(
`ifdef REGISTER_WBS_OUTPUTS
.clk_in (wb_clock_in),
.reset_in (reset_in),
.sample_address_in (amux_sample_address_in),
`endif
.address_in (amux_addr_in),
.bar0_in (amux_bar0_in),
.bar1_in (amux_bar1_in),
.bar2_in (amux_bar2_in),
.bar3_in (amux_bar3_in),
.bar4_in (amux_bar4_in),
.bar5_in (amux_bar5_in),
.am0_in (amux_am0_in),
.am1_in (amux_am1_in),
.am2_in (amux_am2_in),
.am3_in (amux_am3_in),
.am4_in (amux_am4_in),
.am5_in (amux_am5_in),
.ta0_in (amux_ta0_in),
.ta1_in (amux_ta1_in),
.ta2_in (amux_ta2_in),
.ta3_in (amux_ta3_in),
.ta4_in (amux_ta4_in),
.ta5_in (amux_ta5_in),
.at_en_in (amux_at_en_in),
.hit_out (amux_hit_out),
.address_out (amux_address_out)
);
// delayed transaction logic inputs
wire del_sync_req_in = wbs_sm_del_req_out ;
wire del_sync_comp_in = pcim_if_del_complete_out ;
wire del_sync_done_in = wbs_sm_del_done_out ;
wire del_sync_in_progress_in = wbs_sm_del_in_progress_out ;
wire [31:0] del_sync_addr_in = wbs_sm_data_out ;
wire [3:0] del_sync_be_in = wbs_sm_conf_be_out ;
wire del_sync_we_in = wbs_sm_del_write_out ;
wire [3:0] del_sync_bc_in = wbs_sm_del_bc_out ;
wire del_sync_status_in = pcim_if_del_error_out ;
wire del_sync_burst_in = wbs_sm_del_burst_out ;
wire del_sync_retry_expired_in = pcim_if_del_rty_exp_out ;
// delayed transaction logic instantiation
pci_delayed_sync del_sync (
.reset_in (reset_in),
.req_clk_in (wb_clock_in),
.comp_clk_in (pci_clock_in),
.req_in (del_sync_req_in),
.comp_in (del_sync_comp_in),
.done_in (del_sync_done_in),
.in_progress_in (del_sync_in_progress_in),
.comp_req_pending_out (del_sync_comp_req_pending_out),
.comp_comp_pending_out(del_sync_comp_comp_pending_out),
.req_req_pending_out (del_sync_req_req_pending_out),
.req_comp_pending_out (del_sync_req_comp_pending_out),
.addr_in (del_sync_addr_in),
.be_in (del_sync_be_in),
.addr_out (del_sync_addr_out),
.be_out (del_sync_be_out),
.we_in (del_sync_we_in),
.we_out (del_sync_we_out),
.bc_in (del_sync_bc_in),
.bc_out (del_sync_bc_out),
.status_in (del_sync_status_in),
.status_out (del_sync_status_out),
.comp_flush_out (del_sync_comp_flush_out),
.burst_in (del_sync_burst_in),
.burst_out (del_sync_burst_out),
.retry_expired_in (del_sync_retry_expired_in)
);
// delayed write storage inputs
wire del_write_we_in = wbs_sm_del_req_out && wbs_sm_del_write_out ;
wire [31:0] del_write_data_in = wbs_sm_conf_data_out ;
pci_delayed_write_reg delayed_write_data
(
.reset_in (reset_in),
.req_clk_in (wb_clock_in),
.comp_wdata_out (del_write_data_out),
.req_we_in (del_write_we_in),
.req_wdata_in (del_write_data_in)
);
`ifdef HOST
// configuration cycle address decoder input
wire [31:0] ccyc_addr_in = {8'h00, wbu_ccyc_addr_in} ;
pci_conf_cyc_addr_dec ccyc_addr_dec
(
.ccyc_addr_in (ccyc_addr_in),
.ccyc_addr_out (ccyc_addr_out)
) ;
`else
`ifdef GUEST
assign ccyc_addr_out = 32'h0000_0000 ;
`endif
`endif
// pci master interface inputs
wire [31:0] pcim_if_wbw_addr_data_in = fifos_wbw_addr_data_out ;
wire [3:0] pcim_if_wbw_cbe_in = fifos_wbw_cbe_out ;
wire [3:0] pcim_if_wbw_control_in = fifos_wbw_control_out ;
wire pcim_if_wbw_empty_in = fifos_wbw_empty_out ;
wire pcim_if_wbw_transaction_ready_in = fifos_wbw_transaction_ready_out ;
wire [31:0] pcim_if_data_in = pcim_sm_data_out ;
wire [31:0] pcim_if_del_wdata_in = del_write_data_out ;
wire pcim_if_del_req_in = del_sync_comp_req_pending_out ;
wire [31:0] pcim_if_del_addr_in = del_sync_addr_out ;
wire [3:0] pcim_if_del_bc_in = del_sync_bc_out ;
wire [3:0] pcim_if_del_be_in = del_sync_be_out ;
wire pcim_if_del_burst_in = del_sync_burst_out ;
wire pcim_if_del_we_in = del_sync_we_out ;
wire [7:0] pcim_if_cache_line_size_in = wbu_cache_line_size_in ;
wire pcim_if_wait_in = pcim_sm_wait_out ;
wire pcim_if_wtransfer_in = pcim_sm_wtransfer_out ;
wire pcim_if_rtransfer_in = pcim_sm_rtransfer_out ;
wire pcim_if_retry_in = pcim_sm_retry_out ;
wire pcim_if_rerror_in = pcim_sm_rerror_out ;
wire pcim_if_first_in = pcim_sm_first_out ;
wire pcim_if_mabort_in = pcim_sm_mabort_out ;
pci_master32_sm_if pci_initiator_if
(
.clk_in (pci_clock_in),
.reset_in (reset_in),
.address_out (pcim_if_address_out),
.bc_out (pcim_if_bc_out),
.data_out (pcim_if_data_out),
.data_in (pcim_if_data_in),
.be_out (pcim_if_be_out),
.req_out (pcim_if_req_out),
.rdy_out (pcim_if_rdy_out),
.last_out (pcim_if_last_out),
.wbw_renable_out (pcim_if_wbw_renable_out),
.wbw_fifo_addr_data_in (pcim_if_wbw_addr_data_in),
.wbw_fifo_cbe_in (pcim_if_wbw_cbe_in),
.wbw_fifo_control_in (pcim_if_wbw_control_in),
.wbw_fifo_empty_in (pcim_if_wbw_empty_in),
.wbw_fifo_transaction_ready_in (pcim_if_wbw_transaction_ready_in),
.wbr_fifo_wenable_out (pcim_if_wbr_wenable_out),
.wbr_fifo_data_out (pcim_if_wbr_data_out),
.wbr_fifo_be_out (pcim_if_wbr_be_out),
.wbr_fifo_control_out (pcim_if_wbr_control_out),
.del_wdata_in (pcim_if_del_wdata_in),
.del_complete_out (pcim_if_del_complete_out),
.del_req_in (pcim_if_del_req_in),
.del_addr_in (pcim_if_del_addr_in),
.del_bc_in (pcim_if_del_bc_in),
.del_be_in (pcim_if_del_be_in),
.del_burst_in (pcim_if_del_burst_in),
.del_error_out (pcim_if_del_error_out),
.del_rty_exp_out (pcim_if_del_rty_exp_out),
.del_we_in (pcim_if_del_we_in),
.err_addr_out (pcim_if_err_addr_out),
.err_bc_out (pcim_if_err_bc_out),
.err_signal_out (pcim_if_err_signal_out),
.err_source_out (pcim_if_err_source_out),
.err_rty_exp_out (pcim_if_err_rty_exp_out),
.cache_line_size_in (pcim_if_cache_line_size_in),
.mabort_received_out (pcim_if_mabort_out),
.tabort_received_out (pcim_if_tabort_out),
.next_data_out (pcim_if_next_data_out),
.next_be_out (pcim_if_next_be_out),
.next_last_out (pcim_if_next_last_out),
.wait_in (pcim_if_wait_in),
.wtransfer_in (pcim_if_wtransfer_in),
.rtransfer_in (pcim_if_rtransfer_in),
.retry_in (pcim_if_retry_in),
.rerror_in (pcim_if_rerror_in),
.first_in (pcim_if_first_in),
.mabort_in (pcim_if_mabort_in),
.posted_write_not_present_out (pcim_if_posted_write_not_present_out)
);
// pci master state machine inputs
wire pcim_sm_gnt_in = wbu_pciif_gnt_in ;
wire pcim_sm_frame_in = wbu_pciif_frame_in ;
wire pcim_sm_irdy_in = wbu_pciif_irdy_in ;
wire pcim_sm_trdy_in = wbu_pciif_trdy_in;
wire pcim_sm_stop_in = wbu_pciif_stop_in ;
wire pcim_sm_devsel_in = wbu_pciif_devsel_in ;
wire [31:0] pcim_sm_ad_reg_in = wbu_pciif_ad_reg_in ;
wire [31:0] pcim_sm_address_in = pcim_if_address_out ;
wire [3:0] pcim_sm_bc_in = pcim_if_bc_out ;
wire [31:0] pcim_sm_data_in = pcim_if_data_out ;
wire [3:0] pcim_sm_be_in = pcim_if_be_out ;
wire pcim_sm_req_in = pcim_if_req_out ;
wire pcim_sm_rdy_in = pcim_if_rdy_out ;
wire pcim_sm_last_in = pcim_if_last_out ;
wire [7:0] pcim_sm_latency_tim_val_in = wbu_latency_tim_val_in ;
wire [31:0] pcim_sm_next_data_in = pcim_if_next_data_out ;
wire [3:0] pcim_sm_next_be_in = pcim_if_next_be_out ;
wire pcim_sm_next_last_in = pcim_if_next_last_out ;
wire pcim_sm_trdy_reg_in = wbu_pciif_trdy_reg_in ;
wire pcim_sm_stop_reg_in = wbu_pciif_stop_reg_in ;
wire pcim_sm_devsel_reg_in = wbu_pciif_devsel_reg_in ;
wire pcim_sm_frame_en_in = wbu_pciif_frame_en_in ;
wire pcim_sm_frame_out_in = wbu_pciif_frame_out_in ;
pci_master32_sm pci_initiator_sm
(
.clk_in (pci_clock_in),
.reset_in (reset_in),
.pci_req_out (pcim_sm_req_out),
.pci_gnt_in (pcim_sm_gnt_in),
.pci_frame_in (pcim_sm_frame_in),
.pci_frame_out (pcim_sm_frame_out),
.pci_frame_en_out (pcim_sm_frame_en_out),
.pci_frame_out_in (pcim_sm_frame_out_in),
.pci_frame_load_out (pcim_sm_frame_load_out),
.pci_frame_en_in (pcim_sm_frame_en_in),
.pci_irdy_in (pcim_sm_irdy_in),
.pci_irdy_out (pcim_sm_irdy_out),
.pci_irdy_en_out (pcim_sm_irdy_en_out),
.pci_trdy_in (pcim_sm_trdy_in),
.pci_trdy_reg_in (pcim_sm_trdy_reg_in),
.pci_stop_in (pcim_sm_stop_in),
.pci_stop_reg_in (pcim_sm_stop_reg_in),
.pci_devsel_in (pcim_sm_devsel_in),
.pci_devsel_reg_in (pcim_sm_devsel_reg_in),
.pci_ad_reg_in (pcim_sm_ad_reg_in),
.pci_ad_out (pcim_sm_ad_out),
.pci_ad_en_out (pcim_sm_ad_en_out),
.pci_cbe_out (pcim_sm_cbe_out),
.pci_cbe_en_out (pcim_sm_cbe_en_out),
.address_in (pcim_sm_address_in),
.bc_in (pcim_sm_bc_in),
.data_in (pcim_sm_data_in),
.data_out (pcim_sm_data_out),
.be_in (pcim_sm_be_in),
.req_in (pcim_sm_req_in),
.rdy_in (pcim_sm_rdy_in),
.last_in (pcim_sm_last_in),
.latency_tim_val_in (pcim_sm_latency_tim_val_in),
.next_data_in (pcim_sm_next_data_in),
.next_be_in (pcim_sm_next_be_in),
.next_last_in (pcim_sm_next_last_in),
.ad_load_out (pcim_sm_ad_load_out),
.ad_load_on_transfer_out (pcim_sm_ad_load_on_transfer_out),
.wait_out (pcim_sm_wait_out),
.wtransfer_out (pcim_sm_wtransfer_out),
.rtransfer_out (pcim_sm_rtransfer_out),
.retry_out (pcim_sm_retry_out),
.rerror_out (pcim_sm_rerror_out),
.first_out (pcim_sm_first_out),
.mabort_out (pcim_sm_mabort_out)
) ;
endmodule |
module pci_serr_en_crit
(
serr_en_out,
non_critical_par_in,
pci_par_in,
serr_generate_in
);
output serr_en_out ;
input non_critical_par_in,
pci_par_in,
serr_generate_in ;
assign serr_en_out = serr_generate_in && ( non_critical_par_in ^ pci_par_in ) ;
endmodule |
module pci_mas_ad_en_crit
(
pci_ad_en_out,
ad_en_slow_in,
ad_en_on_grant_in,
pci_gnt_in
) ;
output pci_ad_en_out ;
input ad_en_slow_in,
ad_en_on_grant_in,
pci_gnt_in ;
assign pci_ad_en_out = ad_en_slow_in || (ad_en_on_grant_in && !pci_gnt_in) ;
endmodule |
module pci_serr_crit
(
serr_out,
non_critical_par_in,
pci_par_in,
serr_check_in
);
output serr_out ;
input non_critical_par_in,
pci_par_in,
serr_check_in ;
assign serr_out = ~(serr_check_in && ( non_critical_par_in ^ pci_par_in )) ;
endmodule |
module pci_synchronizer_flop (
data_in, clk_out, sync_data_out, async_reset
);
parameter width = 1 ;
parameter reset_val = 0 ;
input [width-1:0] data_in;
input clk_out;
output [width-1:0] sync_data_out;
input async_reset;
reg [width-1:0] sync_data_out;
always @(posedge clk_out or posedge async_reset)
begin
if (async_reset == 1'b1)
begin
sync_data_out <= reset_val;
end
else
begin
// In gate-level simulation, must only go to 1'bX if the input is 1'bX or 1'bZ.
// This should NEVER go to 1'bX due to setup or hold violations.
sync_data_out <= data_in;
end
end
endmodule |
module pci_wbr_fifo_control
(
rclock_in,
wclock_in,
renable_in,
wenable_in,
reset_in,
flush_in,
empty_out,
waddr_out,
raddr_out,
rallow_out,
wallow_out
) ;
parameter ADDR_LENGTH = 7 ;
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input rclock_in, wclock_in;
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
// write address changes on rising edge of wclock_in when writes are allowed
input renable_in, wenable_in;
// reset input
input reset_in;
// flush input
input flush_in ;
// empty status output
output empty_out;
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
// read and write allow outputs
output rallow_out, wallow_out ;
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
assign waddr_out = waddr ;
// grey code register
reg [(ADDR_LENGTH - 1):0] wgrey_addr ;
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
// grey code register
reg [(ADDR_LENGTH - 1):0] rgrey_addr ;
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
// FF for registered empty flag
wire empty ;
// write allow wire
wire wallow = wenable_in ;
// write allow output assignment
assign wallow_out = wallow ;
// read allow wire
wire rallow ;
// clear generation for FFs and registers
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
assign empty_out = empty ;
//rallow generation
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
// rallow output assignment
assign rallow_out = renable_in ;
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
// done for zero wait state burst
assign raddr_out = rallow ? raddr_plus_one : raddr ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
raddr_plus_one <= #`FF_DELAY 2 ;
raddr <= #`FF_DELAY 1 ;
end
else if (flush_in)
begin
raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ;
raddr <= #`FF_DELAY waddr ;
end
else if (rallow)
begin
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
raddr <= #`FF_DELAY raddr_plus_one ;
end
end
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address register
--------------------------------------------------------------------------------------------------*/
// grey coded address
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
rgrey_addr <= #`FF_DELAY 0 ;
end
else if (flush_in)
begin
rgrey_addr <= #`FF_DELAY wgrey_addr ; // when flushed, copy value from write side
end
else if (rallow)
begin
rgrey_addr <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
end
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and Grey Code Register
----------------------------------------------------------------------------------------------*/
// grey coded address for status generation in write clock domain
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wgrey_addr <= #1 0 ;
end
else
if (wallow)
begin
wgrey_addr <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
end
end
// write address counter - nothing special except initial value
always@(posedge wclock_in or posedge clear)
begin
if (clear)
// initial value is 1
waddr <= #`FF_DELAY 1 ;
else
if (wallow)
waddr <= #`FF_DELAY waddr + 1'b1 ;
end
/*------------------------------------------------------------------------------------------------------------------------------
Empty control:
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
If they are equal, fifo is empty.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
(
.data_in (wgrey_addr),
.clk_out (rclock_in),
.sync_data_out (rclk_sync_wgrey_addr),
.async_reset (clear)
) ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
rclk_wgrey_addr <= #`FF_DELAY 0 ;
else
rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
end
assign empty = (rgrey_addr == rclk_wgrey_addr) ;
endmodule |
module pci_wbw_fifo_control
(
rclock_in,
wclock_in,
renable_in,
wenable_in,
reset_in,
almost_full_out,
full_out,
empty_out,
waddr_out,
raddr_out,
rallow_out,
wallow_out
);
parameter ADDR_LENGTH = 7 ;
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input rclock_in, wclock_in;
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
// write address changes on rising edge of wclock_in when writes are allowed
input renable_in, wenable_in ;
// reset input
input reset_in;
// flush input
// input flush_in ; // not used
// almost full and empy status outputs
output almost_full_out ;
// full and empty status outputs
output full_out, empty_out;
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
// read and write allow outputs
output rallow_out, wallow_out ;
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
assign waddr_out = waddr ;
// grey code registers
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
// grey code register for next write address
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
// write allow wire - writes are allowed when fifo is not full
assign wallow_out = wenable_in & ~full_out ;
// clear generation for FFs and registers
wire clear = reset_in ;
//rallow generation
assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
// done for zero wait state burst
assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
raddr_plus_one <= #`FF_DELAY 4 ;
raddr <= #`FF_DELAY 3 ;
end
else if (rallow_out)
begin
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
raddr <= #`FF_DELAY raddr_plus_one ;
end
end
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 3 Grey addresses:
- rgrey_minus1 is Grey Code of address one before current address
- rgrey_addr is Grey Code of current read address
- rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in read clock domain
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
// initial value is 0
rgrey_minus1 <= #1 0 ;
rgrey_addr <= #1 1 ;
rgrey_next <= #`FF_DELAY 3 ;
end
else
if (rallow_out)
begin
rgrey_minus1 <= #1 rgrey_addr ;
rgrey_addr <= #1 rgrey_next ;
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
end
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and Grey Code Register
----------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in write clock domain
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wgrey_addr <= #`FF_DELAY 1 ;
wgrey_next <= #1 3 ;
end
else
if (wallow_out)
begin
wgrey_addr <= #`FF_DELAY wgrey_next ;
wgrey_next <= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
end
end
// write address counter - nothing special - initial value is important though
always@(posedge wclock_in or posedge clear)
begin
if (clear)
// initial value 4
waddr <= #`FF_DELAY 3 ;
else
if (wallow_out)
waddr <= #`FF_DELAY waddr + 1'b1 ;
end
/*------------------------------------------------------------------------------------------------------------------------------
Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to:
- Gray coded write address. If they are equal, fifo is full.
- Gray coded next write address. If they are equal, fifo is almost full.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ;
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ;
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1
(
.data_in (rgrey_minus1),
.clk_out (wclock_in),
.sync_data_out (wclk_sync_rgrey_minus1),
.async_reset (clear)
) ;
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wclk_rgrey_minus1 <= #`FF_DELAY 0 ;
end
else
begin
wclk_rgrey_minus1 <= #`FF_DELAY wclk_sync_rgrey_minus1 ;
end
end
assign full_out = (wgrey_addr == wclk_rgrey_minus1) ;
assign almost_full_out = (wgrey_next == wclk_rgrey_minus1) ;
/*------------------------------------------------------------------------------------------------------------------------------
Empty control:
Gray coded address of next write address is synchronized to read clock domain and compared to Gray coded next read address.
If they are equal, fifo is empty.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_next ;
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_next ;
pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_next
(
.data_in (wgrey_next),
.clk_out (rclock_in),
.sync_data_out (rclk_sync_wgrey_next),
.async_reset (clear)
) ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
rclk_wgrey_next <= #`FF_DELAY 3 ;
else
rclk_wgrey_next <= #`FF_DELAY rclk_sync_wgrey_next ;
end
assign empty_out = (rgrey_next == rclk_wgrey_next) ;
endmodule |
module pci_wb_decoder (hit, addr_out, addr_in, base_addr, mask_addr, tran_addr, at_en) ;
// Decoding address size parameter - for FPGAs 1MegByte is recommended
// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!
parameter decode_len = 12 ;
//###########################################################################################################
// ALL COMMENTS are written as there were decode_len 20. This number and 12 (32 - 20) are assigning the
// numbers of decoded and compared bits, etc.
//###########################################################################################################
/*-----------------------------------------------------------------------------------------------------------
DECODER interface decodes input address (ADDR_IN); what means that it validates (HIT), if input address
falls within the defined image space boundaries. Image space boundarie is defined with image base address
register (BASE_ADDR) and address mask register (MASK_ADDR).
Beside that, it also translates (maps) the input address to the output address (ADDR_OUT), regarding the
translation address register (TRAN_ADDR) and the address mask register.
-----------------------------------------------------------------------------------------------------------*/
// output control
output hit ;
// output address
output [31:0] addr_out ;
// input address
input [31:0] addr_in ;
// input registers - 12 LSbits are not valid since the smallest possible size is 4KB !
input [31:(32-decode_len)] base_addr ;
input [31:(32-decode_len)] mask_addr ;
input [31:(32-decode_len)] tran_addr ;
// input bit[2] of the Image Control register used to enable the address translation !
input at_en ;
/*-----------------------------------------------------------------------------------------------------------
Internal signals !
-----------------------------------------------------------------------------------------------------------*/
// bit[31] if address mask register is IMAGE ENABLE bit (img_en)
wire img_en ;
// addr_in_compare are masked input address bits that are compared with masked base_addr
wire [31:(32-decode_len)] addr_in_compare ;
// base_addr_compare are masked base address bits that are compared with masked addr_in
wire [31:(32-decode_len)] base_addr_compare ;
/*-----------------------------------------------------------------------------------------------------------
Decoding the input address!
This logic produces the loghest path in this module!
20 MSbits of input addres are as well as base address (20 bits) masked with corrected address mask. Only
masked bits of each vector are actually logically compared.
Bit[31] of address mask register is used to enable the image space !
-----------------------------------------------------------------------------------------------------------*/
assign addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ;
assign base_addr_compare = (base_addr & mask_addr) ;
assign img_en = mask_addr[31] ;
assign hit = { 1'b1, addr_in_compare } == { img_en, base_addr_compare } ;
/*-----------------------------------------------------------------------------------------------------------
Translating the input address!
Translation of input address is not implemented if ADDR_TRAN_IMPL is not defined
20 MSbits of input address are masked with negated value of the corrected address mask in order to get
address bits of the input address which won't be replaced with translation address bits.
Translation address bits (20 bits) are masked with corrected address mask. Only masked bits of vector are
actually valid, all others are zero.
Boath vectors are bit-wise ORed in order to get the valid translation address with an offset of an input
address.
12 LSbits of an input address are assigned to 12 LSbits of an output addres.
-----------------------------------------------------------------------------------------------------------*/
`ifdef ADDR_TRAN_IMPL
// if Address Translation Enable bit is set, then translation address is used othervise input address is used!
// addr_in_combine input address bits are not replaced with translation address!
wire [31:(32-decode_len)] addr_in_combine ;
// tran_addr_combine are masked and combined with addr_in_combine!
reg [31:(32-decode_len)] tran_addr_combine ;
assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ;
always@(at_en or tran_addr or mask_addr or addr_in)
begin
if (at_en)
begin
tran_addr_combine <= (tran_addr & mask_addr) ;
end
else
begin
tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ;
end
end
assign addr_out[31:(32-decode_len)] = addr_in_combine | tran_addr_combine ;
assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ;
`else
assign addr_out = addr_in ;
`endif
endmodule |
module usb_tx_phy(
clk, rst, fs_ce, phy_mode,
// Transciever Interface
txdp, txdn, txoe,
// UTMI Interface
DataOut_i, TxValid_i, TxReady_o
);
input clk;
input rst;
input fs_ce;
input phy_mode;
output txdp, txdn, txoe;
input [7:0] DataOut_i;
input TxValid_i;
output TxReady_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter IDLE = 3'd0,
SOP = 3'h1,
DATA = 3'h2,
EOP1 = 3'h3,
EOP2 = 3'h4,
WAIT = 3'h5;
reg TxReady_o;
reg [2:0] state, next_state;
reg tx_ready_d;
reg ld_sop_d;
reg ld_data_d;
reg ld_eop_d;
reg tx_ip;
reg tx_ip_sync;
reg [2:0] bit_cnt;
reg [7:0] hold_reg;
reg [7:0] hold_reg_d;
reg sd_raw_o;
wire hold;
reg data_done;
reg sft_done;
reg sft_done_r;
wire sft_done_e;
reg ld_data;
wire eop_done;
reg [2:0] one_cnt;
wire stuff;
reg sd_bs_o;
reg sd_nrzi_o;
reg append_eop;
reg append_eop_sync1;
reg append_eop_sync2;
reg append_eop_sync3;
reg append_eop_sync4;
reg txdp, txdn;
reg txoe_r1, txoe_r2;
reg txoe;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) TxReady_o <= 1'b0;
else TxReady_o <= tx_ready_d & TxValid_i;
always @(posedge clk) ld_data <= ld_data_d;
///////////////////////////////////////////////////////////////////
//
// Transmit in progress indicator
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) tx_ip <= 1'b0;
else
if(ld_sop_d) tx_ip <= 1'b1;
else
if(eop_done) tx_ip <= 1'b0;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) tx_ip_sync <= 1'b0;
else
if(fs_ce) tx_ip_sync <= tx_ip;
// data_done helps us to catch cases where TxValid drops due to
// packet end and then gets re-asserted as a new packet starts.
// We might not see this because we are still transmitting.
// data_done should solve those cases ...
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) data_done <= 1'b0;
else
if(TxValid_i && ! tx_ip) data_done <= 1'b1;
else
if(!TxValid_i) data_done <= 1'b0;
///////////////////////////////////////////////////////////////////
//
// Shift Register
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) bit_cnt <= 3'h0;
else
if(!tx_ip_sync) bit_cnt <= 3'h0;
else
if(fs_ce && !hold) bit_cnt <= bit_cnt + 3'h1;
assign hold = stuff;
always @(posedge clk)
if(!tx_ip_sync) sd_raw_o <= 1'b0;
else
case(bit_cnt) // synopsys full_case parallel_case
3'h0: sd_raw_o <= hold_reg_d[0];
3'h1: sd_raw_o <= hold_reg_d[1];
3'h2: sd_raw_o <= hold_reg_d[2];
3'h3: sd_raw_o <= hold_reg_d[3];
3'h4: sd_raw_o <= hold_reg_d[4];
3'h5: sd_raw_o <= hold_reg_d[5];
3'h6: sd_raw_o <= hold_reg_d[6];
3'h7: sd_raw_o <= hold_reg_d[7];
endcase
always @(posedge clk)
sft_done <= !hold & (bit_cnt == 3'h7);
always @(posedge clk)
sft_done_r <= sft_done;
assign sft_done_e = sft_done & !sft_done_r;
// Out Data Hold Register
always @(posedge clk)
if(ld_sop_d) hold_reg <= 8'h80;
else
if(ld_data) hold_reg <= DataOut_i;
always @(posedge clk) hold_reg_d <= hold_reg;
///////////////////////////////////////////////////////////////////
//
// Bit Stuffer
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) one_cnt <= 3'h0;
else
if(!tx_ip_sync) one_cnt <= 3'h0;
else
if(fs_ce)
begin
if(!sd_raw_o || stuff) one_cnt <= 3'h0;
else one_cnt <= one_cnt + 3'h1;
end
assign stuff = (one_cnt==3'h6);
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) sd_bs_o <= 1'h0;
else
if(fs_ce) sd_bs_o <= !tx_ip_sync ? 1'b0 : (stuff ? 1'b0 : sd_raw_o);
///////////////////////////////////////////////////////////////////
//
// NRZI Encoder
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) sd_nrzi_o <= 1'b1;
else
if(!tx_ip_sync || !txoe_r1) sd_nrzi_o <= 1'b1;
else
if(fs_ce) sd_nrzi_o <= sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o;
///////////////////////////////////////////////////////////////////
//
// EOP append logic
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop <= 1'b0;
else
if(ld_eop_d) append_eop <= 1'b1;
else
if(append_eop_sync2) append_eop <= 1'b0;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync1 <= 1'b0;
else
if(fs_ce) append_eop_sync1 <= append_eop;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync2 <= 1'b0;
else
if(fs_ce) append_eop_sync2 <= append_eop_sync1;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync3 <= 1'b0;
else
if(fs_ce) append_eop_sync3 <= append_eop_sync2 |
(append_eop_sync3 & !append_eop_sync4); // Make sure always 2 bit wide
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync4 <= 1'b0;
else
if(fs_ce) append_eop_sync4 <= append_eop_sync3;
assign eop_done = append_eop_sync3;
///////////////////////////////////////////////////////////////////
//
// Output Enable Logic
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) txoe_r1 <= 1'b0;
else
if(fs_ce) txoe_r1 <= tx_ip_sync;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) txoe_r2 <= 1'b0;
else
if(fs_ce) txoe_r2 <= txoe_r1;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) txoe <= 1'b1;
else
if(fs_ce) txoe <= !(txoe_r1 | txoe_r2);
///////////////////////////////////////////////////////////////////
//
// Output Registers
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) txdp <= 1'b1;
else
if(fs_ce) txdp <= phy_mode ?
(!append_eop_sync3 & sd_nrzi_o) :
sd_nrzi_o;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) txdn <= 1'b0;
else
if(fs_ce) txdn <= phy_mode ?
(!append_eop_sync3 & ~sd_nrzi_o) :
append_eop_sync3;
///////////////////////////////////////////////////////////////////
//
// Tx Statemashine
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) state <= IDLE;
else state <= next_state;
always @(state or TxValid_i or data_done or sft_done_e or eop_done or fs_ce)
begin
next_state = state;
tx_ready_d = 1'b0;
ld_sop_d = 1'b0;
ld_data_d = 1'b0;
ld_eop_d = 1'b0;
case(state) // synopsys full_case parallel_case
IDLE:
if(TxValid_i)
begin
ld_sop_d = 1'b1;
next_state = SOP;
end
SOP:
if(sft_done_e)
begin
tx_ready_d = 1'b1;
ld_data_d = 1'b1;
next_state = DATA;
end
DATA:
begin
if(!data_done && sft_done_e)
begin
ld_eop_d = 1'b1;
next_state = EOP1;
end
if(data_done && sft_done_e)
begin
tx_ready_d = 1'b1;
ld_data_d = 1'b1;
end
end
EOP1:
if(eop_done) next_state = EOP2;
EOP2:
if(!eop_done && fs_ce) next_state = WAIT;
WAIT:
if(fs_ce) next_state = IDLE;
endcase
end
endmodule |
module usb_phy(clk, rst, phy_tx_mode, usb_rst,
// Transciever Interface
txdp, txdn, txoe,
rxd, rxdp, rxdn,
// UTMI Interface
DataOut_i, TxValid_i, TxReady_o, RxValid_o,
RxActive_o, RxError_o, DataIn_o, LineState_o
);
input clk;
input rst;
input phy_tx_mode;
output usb_rst;
output txdp, txdn, txoe;
input rxd, rxdp, rxdn;
input [7:0] DataOut_i;
input TxValid_i;
output TxReady_o;
output [7:0] DataIn_o;
output RxValid_o;
output RxActive_o;
output RxError_o;
output [1:0] LineState_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [4:0] rst_cnt;
reg usb_rst;
wire fs_ce;
wire rst;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
///////////////////////////////////////////////////////////////////
//
// TX Phy
//
usb_tx_phy i_tx_phy(
.clk( clk ),
.rst( rst ),
.fs_ce( fs_ce ),
.phy_mode( phy_tx_mode ),
// Transciever Interface
.txdp( txdp ),
.txdn( txdn ),
.txoe( txoe ),
// UTMI Interface
.DataOut_i( DataOut_i ),
.TxValid_i( TxValid_i ),
.TxReady_o( TxReady_o )
);
///////////////////////////////////////////////////////////////////
//
// RX Phy and DPLL
//
usb_rx_phy i_rx_phy(
.clk( clk ),
.rst( rst ),
.fs_ce( fs_ce ),
// Transciever Interface
.rxd( rxd ),
.rxdp( rxdp ),
.rxdn( rxdn ),
// UTMI Interface
.DataIn_o( DataIn_o ),
.RxValid_o( RxValid_o ),
.RxActive_o( RxActive_o ),
.RxError_o( RxError_o ),
.RxEn_i( txoe ),
.LineState( LineState_o )
);
///////////////////////////////////////////////////////////////////
//
// Generate an USB Reset is we see SE0 for at least 2.5uS
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) rst_cnt <= 5'h0;
else
if(LineState_o != 2'h0) rst_cnt <= 5'h0;
else
if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;
always @(posedge clk)
usb_rst <= (rst_cnt == 5'h1f);
endmodule |
module usb_rx_phy( clk, rst, fs_ce,
// Transciever Interface
rxd, rxdp, rxdn,
// UTMI Interface
RxValid_o, RxActive_o, RxError_o, DataIn_o,
RxEn_i, LineState);
input clk;
input rst;
output fs_ce;
input rxd, rxdp, rxdn;
output [7:0] DataIn_o;
output RxValid_o;
output RxActive_o;
output RxError_o;
input RxEn_i;
output [1:0] LineState;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg rxd_s0, rxd_s1, rxd_s;
reg rxdp_s0, rxdp_s1, rxdp_s, rxdp_s_r;
reg rxdn_s0, rxdn_s1, rxdn_s, rxdn_s_r;
reg synced_d;
wire k, j, se0;
reg rxd_r;
reg rx_en;
reg rx_active;
reg [2:0] bit_cnt;
reg rx_valid1, rx_valid;
reg shift_en;
reg sd_r;
reg sd_nrzi;
reg [7:0] hold_reg;
wire drop_bit; // Indicates a stuffed bit
reg [2:0] one_cnt;
reg [1:0] dpll_state, dpll_next_state;
reg fs_ce_d;
reg fs_ce;
wire change;
wire lock_en;
reg [2:0] fs_state, fs_next_state;
reg rx_valid_r;
reg sync_err_d, sync_err;
reg bit_stuff_err;
reg se0_r, byte_err;
reg se0_s;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign RxActive_o = rx_active;
assign RxValid_o = rx_valid;
assign RxError_o = sync_err | bit_stuff_err | byte_err;
assign DataIn_o = hold_reg;
assign LineState = {rxdn_s1, rxdp_s1};
always @(posedge clk) rx_en <= RxEn_i;
always @(posedge clk) sync_err <= !rx_active & sync_err_d;
///////////////////////////////////////////////////////////////////
//
// Synchronize Inputs
//
// First synchronize to the local system clock to
// avoid metastability outside the sync block (*_s0).
// Then make sure we see the signal for at least two
// clock cycles stable to avoid glitches and noise
always @(posedge clk) rxd_s0 <= rxd;
always @(posedge clk) rxd_s1 <= rxd_s0;
always @(posedge clk) // Avoid detecting Line Glitches and noise
if(rxd_s0 && rxd_s1) rxd_s <= 1'b1;
else
if(!rxd_s0 && !rxd_s1) rxd_s <= 1'b0;
always @(posedge clk) rxdp_s0 <= rxdp;
always @(posedge clk) rxdp_s1 <= rxdp_s0;
always @(posedge clk) rxdp_s_r <= rxdp_s0 & rxdp_s1;
always @(posedge clk) rxdp_s <= (rxdp_s0 & rxdp_s1) | rxdp_s_r; // Avoid detecting Line Glitches and noise
always @(posedge clk) rxdn_s0 <= rxdn;
always @(posedge clk) rxdn_s1 <= rxdn_s0;
always @(posedge clk) rxdn_s_r <= rxdn_s0 & rxdn_s1;
always @(posedge clk) rxdn_s <= (rxdn_s0 & rxdn_s1) | rxdn_s_r; // Avoid detecting Line Glitches and noise
assign k = !rxdp_s & rxdn_s;
assign j = rxdp_s & !rxdn_s;
assign se0 = !rxdp_s & !rxdn_s;
always @(posedge clk) if(fs_ce) se0_s <= se0;
///////////////////////////////////////////////////////////////////
//
// DPLL
//
// This design uses a clock enable to do 12Mhz timing and not a
// real 12Mhz clock. Everything always runs at 48Mhz. We want to
// make sure however, that the clock enable is always exactly in
// the middle between two virtual 12Mhz rising edges.
// We monitor rxdp and rxdn for any changes and do the appropiate
// adjustments.
// In addition to the locking done in the dpll FSM, we adjust the
// final latch enable to compensate for various sync registers ...
// Allow lockinf only when we are receiving
assign lock_en = rx_en;
always @(posedge clk) rxd_r <= rxd_s;
// Edge detector
assign change = rxd_r != rxd_s;
// DPLL FSM
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) dpll_state <= 2'h1;
else dpll_state <= dpll_next_state;
always @(dpll_state or lock_en or change)
begin
fs_ce_d = 1'b0;
case(dpll_state) // synopsys full_case parallel_case
2'h0:
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h1;
2'h1:begin
fs_ce_d = 1'b1;
if(lock_en && change) dpll_next_state = 2'h3;
else dpll_next_state = 2'h2;
end
2'h2:
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h3;
2'h3:
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h0;
endcase
end
// Compensate for sync registers at the input - allign full speed
// clock enable to be in the middle between two bit changes ...
reg fs_ce_r1, fs_ce_r2;
always @(posedge clk) fs_ce_r1 <= fs_ce_d;
always @(posedge clk) fs_ce_r2 <= fs_ce_r1;
always @(posedge clk) fs_ce <= fs_ce_r2;
///////////////////////////////////////////////////////////////////
//
// Find Sync Pattern FSM
//
parameter FS_IDLE = 3'h0,
K1 = 3'h1,
J1 = 3'h2,
K2 = 3'h3,
J2 = 3'h4,
K3 = 3'h5,
J3 = 3'h6,
K4 = 3'h7;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) fs_state <= FS_IDLE;
else fs_state <= fs_next_state;
always @(fs_state or fs_ce or k or j or rx_en or rx_active or se0 or se0_s)
begin
synced_d = 1'b0;
sync_err_d = 1'b0;
fs_next_state = fs_state;
if(fs_ce && !rx_active && !se0 && !se0_s)
case(fs_state) // synopsys full_case parallel_case
FS_IDLE:
begin
if(k && rx_en) fs_next_state = K1;
end
K1:
begin
if(j && rx_en) fs_next_state = J1;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J1:
begin
if(k && rx_en) fs_next_state = K2;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K2:
begin
if(j && rx_en) fs_next_state = J2;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J2:
begin
if(k && rx_en) fs_next_state = K3;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K3:
begin
if(j && rx_en) fs_next_state = J3;
else
if(k && rx_en)
begin
fs_next_state = FS_IDLE; // Allow missing first K-J
synced_d = 1'b1;
end
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J3:
begin
if(k && rx_en) fs_next_state = K4;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K4:
begin
if(k) synced_d = 1'b1;
fs_next_state = FS_IDLE;
end
endcase
end
///////////////////////////////////////////////////////////////////
//
// Generate RxActive
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) rx_active <= 1'b0;
else
if(synced_d && rx_en) rx_active <= 1'b1;
else
if(se0 && rx_valid_r) rx_active <= 1'b0;
always @(posedge clk)
if(rx_valid) rx_valid_r <= 1'b1;
else
if(fs_ce) rx_valid_r <= 1'b0;
///////////////////////////////////////////////////////////////////
//
// NRZI Decoder
//
always @(posedge clk)
if(fs_ce) sd_r <= rxd_s;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) sd_nrzi <= 1'b0;
else
if(!rx_active) sd_nrzi <= 1'b1;
else
if(rx_active && fs_ce) sd_nrzi <= !(rxd_s ^ sd_r);
///////////////////////////////////////////////////////////////////
//
// Bit Stuff Detect
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) one_cnt <= 3'h0;
else
if(!shift_en) one_cnt <= 3'h0;
else
if(fs_ce)
begin
if(!sd_nrzi || drop_bit) one_cnt <= 3'h0;
else one_cnt <= one_cnt + 3'h1;
end
assign drop_bit = (one_cnt==3'h6);
always @(posedge clk) bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active; // Bit Stuff Error
///////////////////////////////////////////////////////////////////
//
// Serial => Parallel converter
//
always @(posedge clk)
if(fs_ce) shift_en <= synced_d | rx_active;
always @(posedge clk)
if(fs_ce && shift_en && !drop_bit)
hold_reg <= {sd_nrzi, hold_reg[7:1]};
///////////////////////////////////////////////////////////////////
//
// Generate RxValid
//
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) bit_cnt <= 3'b0;
else
if(!shift_en) bit_cnt <= 3'h0;
else
if(fs_ce && !drop_bit) bit_cnt <= bit_cnt + 3'h1;
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) rx_valid1 <= 1'b0;
else
if(fs_ce && !drop_bit && (bit_cnt==3'h7)) rx_valid1 <= 1'b1;
else
if(rx_valid1 && fs_ce && !drop_bit) rx_valid1 <= 1'b0;
always @(posedge clk) rx_valid <= !drop_bit & rx_valid1 & fs_ce;
always @(posedge clk) se0_r <= se0;
always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt[2:1]) & rx_active;
endmodule |
module tv80_reg (/*AUTOARG*/
// Outputs
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
// Inputs
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
);
input [2:0] AddrC;
output [7:0] DOBH;
input [2:0] AddrA;
input [2:0] AddrB;
input [7:0] DIH;
output [7:0] DOAL;
output [7:0] DOCL;
input [7:0] DIL;
output [7:0] DOBL;
output [7:0] DOCH;
output [7:0] DOAH;
input clk, CEN, WEH, WEL;
reg [7:0] RegsH [0:7];
reg [7:0] RegsL [0:7];
always @(posedge clk)
begin
if (CEN)
begin
if (WEH) RegsH[AddrA] <= DIH;
if (WEL) RegsL[AddrA] <= DIL;
end
end
assign DOAH = RegsH[AddrA];
assign DOAL = RegsL[AddrA];
assign DOBH = RegsH[AddrB];
assign DOBL = RegsL[AddrB];
assign DOCH = RegsH[AddrC];
assign DOCL = RegsL[AddrC];
// break out ram bits for waveform debug
wire [7:0] H = RegsH[2];
wire [7:0] L = RegsL[2];
// synopsys dc_script_begin
// set_attribute current_design "revision" "$Id: tv80_reg.v,v 1.1 2004/05/16 17:39:57 ghutchis Exp $" -type string -quiet
// synopsys dc_script_end
endmodule |
module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 0;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input Arith16;
input Z16;
input [3:0] ALU_Op ;
input [5:0] IR;
input [1:0] ISet;
input [7:0] BusA;
input [7:0] BusB;
input [7:0] F_In;
output [7:0] Q;
output [7:0] F_Out;
reg [7:0] Q;
reg [7:0] F_Out;
function [4:0] AddSub4;
input [3:0] A;
input [3:0] B;
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [3:0] AddSub3;
input [2:0] A;
input [2:0] B;
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [1:0] AddSub1;
input A;
input B;
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
// AddSub variables (temporary signals)
reg UseCarry;
reg Carry7_v;
reg OverFlow_v;
reg HalfCarry_v;
reg Carry_v;
reg [7:0] Q_v;
reg [7:0] BitMask;
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
begin
case (IR[5:3])
3'b000 : BitMask = 8'b00000001;
3'b001 : BitMask = 8'b00000010;
3'b010 : BitMask = 8'b00000100;
3'b011 : BitMask = 8'b00001000;
3'b100 : BitMask = 8'b00010000;
3'b101 : BitMask = 8'b00100000;
3'b110 : BitMask = 8'b01000000;
default: BitMask = 8'b10000000;
endcase // case(IR[5:3])
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
OverFlow_v = Carry_v ^ Carry7_v;
end // always @ *
reg [7:0] Q_t;
reg [8:0] DAA_Q;
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
or Carry_v or F_In or HalfCarry_v or IR or ISet
or OverFlow_v or Q_v or Z16)
begin
Q_t = 8'hxx;
DAA_Q = {9{1'bx}};
F_Out = F_In;
case (ALU_Op)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
F_Out[Flag_N] = 1'b0;
F_Out[Flag_C] = 1'b0;
case (ALU_Op[2:0])
3'b000, 3'b001 : // ADD, ADC
begin
Q_t = Q_v;
F_Out[Flag_C] = Carry_v;
F_Out[Flag_H] = HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
begin
Q_t = Q_v;
F_Out[Flag_N] = 1'b1;
F_Out[Flag_C] = ~ Carry_v;
F_Out[Flag_H] = ~ HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b100 : // AND
begin
Q_t[7:0] = BusA & BusB;
F_Out[Flag_H] = 1'b1;
end
3'b101 : // XOR
begin
Q_t[7:0] = BusA ^ BusB;
F_Out[Flag_H] = 1'b0;
end
default : // OR 3'b110
begin
Q_t[7:0] = BusA | BusB;
F_Out[Flag_H] = 1'b0;
end
endcase // case(ALU_OP[2:0])
if (ALU_Op[2:0] == 3'b111 )
begin // CP
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
else
begin
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
end
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
if (Z16 == 1'b1 )
begin
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
end
end
else
begin
F_Out[Flag_Z] = 1'b0;
end // else: !if(Q_t[7:0] == 8'b00000000 )
F_Out[Flag_S] = Q_t[7];
case (ALU_Op[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
;
default :
F_Out[Flag_P] = ~(^Q_t);
endcase // case(ALU_Op[2:0])
if (Arith16 == 1'b1 )
begin
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
F_Out[Flag_P] = F_In[Flag_P];
end
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
4'b1100 :
begin
// DAA
F_Out[Flag_H] = F_In[Flag_H];
F_Out[Flag_C] = F_In[Flag_C];
DAA_Q[7:0] = BusA;
DAA_Q[8] = 1'b0;
if (F_In[Flag_N] == 1'b0 )
begin
// After addition
// Alow > 9 || H == 1
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if ((DAA_Q[3:0] > 9) )
begin
F_Out[Flag_H] = 1'b1;
end
else
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q = DAA_Q + 6;
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
// new Ahigh > 9 || C == 1
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q + 96; // 0x60
end
end
else
begin
// After subtraction
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if (DAA_Q[3:0] > 5 )
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q[7:0] = DAA_Q[7:0] - 6;
end
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q - 352; // 0x160
end
end // else: !if(F_In[Flag_N] == 1'b0 )
F_Out[Flag_X] = DAA_Q[3];
F_Out[Flag_Y] = DAA_Q[5];
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
Q_t = DAA_Q[7:0];
if (DAA_Q[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = DAA_Q[7];
F_Out[Flag_P] = ~ (^DAA_Q);
end // case: 4'b1100
4'b1101, 4'b1110 :
begin
// RLD, RRD
Q_t[7:4] = BusA[7:4];
if (ALU_Op[0] == 1'b1 )
begin
Q_t[3:0] = BusB[7:4];
end
else
begin
Q_t[3:0] = BusB[3:0];
end
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = Q_t[7];
F_Out[Flag_P] = ~(^Q_t);
end // case: when 4'b1101, 4'b1110
4'b1001 :
begin
// BIT
Q_t[7:0] = BusB & BitMask;
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
F_Out[Flag_P] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
F_Out[Flag_P] = 1'b0;
end
F_Out[Flag_H] = 1'b1;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = 1'b0;
F_Out[Flag_Y] = 1'b0;
if (IR[2:0] != 3'b110 )
begin
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
end // case: when 4'b1001
4'b1010 :
// SET
Q_t[7:0] = BusB | BitMask;
4'b1011 :
// RES
Q_t[7:0] = BusB & ~ BitMask;
4'b1000 :
begin
// ROT
case (IR[5:3])
3'b000 : // RLC
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = BusA[7];
F_Out[Flag_C] = BusA[7];
end
3'b010 : // RL
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = F_In[Flag_C];
F_Out[Flag_C] = BusA[7];
end
3'b001 : // RRC
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[0];
F_Out[Flag_C] = BusA[0];
end
3'b011 : // RR
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = F_In[Flag_C];
F_Out[Flag_C] = BusA[0];
end
3'b100 : // SLA
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b0;
F_Out[Flag_C] = BusA[7];
end
3'b110 : // SLL (Undocumented) / SWAP
begin
if (Mode == 3 )
begin
Q_t[7:4] = BusA[3:0];
Q_t[3:0] = BusA[7:4];
F_Out[Flag_C] = 1'b0;
end
else
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b1;
F_Out[Flag_C] = BusA[7];
end // else: !if(Mode == 3 )
end // case: 3'b110
3'b101 : // SRA
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[7];
F_Out[Flag_C] = BusA[0];
end
default : // SRL
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = 1'b0;
F_Out[Flag_C] = BusA[0];
end
endcase // case(IR[5:3])
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_P] = ~(^Q_t);
if (ISet == 2'b00 )
begin
F_Out[Flag_P] = F_In[Flag_P];
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
end
end // case: 4'b1000
default :
;
endcase // case(ALU_Op)
Q = Q_t;
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
endmodule // T80_ALU |
module simple_spi_top(
// 8bit WISHBONE bus slave interface
input wire clk_i, // clock
input wire rst_i, // reset (asynchronous active low)
input wire cyc_i, // cycle
input wire stb_i, // strobe
input wire [1:0] adr_i, // address
input wire we_i, // write enable
input wire [7:0] dat_i, // data input
output reg [7:0] dat_o, // data output
output reg ack_o, // normal bus termination
output reg inta_o, // interrupt output
// SPI port
output reg sck_o, // serial clock output
output wire mosi_o, // MasterOut SlaveIN
input wire miso_i // MasterIn SlaveOut
);
//
// Module body
//
reg [7:0] spcr; // Serial Peripheral Control Register ('HC11 naming)
wire [7:0] spsr; // Serial Peripheral Status register ('HC11 naming)
reg [7:0] sper; // Serial Peripheral Extension register
reg [7:0] treg, rreg; // Transmit/Receive register
// fifo signals
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdout;
wire wfwe, wffull, wfempty;
// misc signals
wire tirq; // transfer interrupt (selected number of transfers done)
wire wfov; // write fifo overrun (writing while fifo full)
reg [1:0] state; // statemachine state
reg [2:0] bcnt;
//
// Wishbone interface
wire wb_acc = cyc_i & stb_i; // WISHBONE access
wire wb_wr = wb_acc & we_i; // WISHBONE write access
// dat_i
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
begin
spcr <= #1 8'h10; // set master bit
sper <= #1 8'h00;
end
else if (wb_wr)
begin
if (adr_i == 2'b00)
spcr <= #1 dat_i | 8'h10; // always set master bit
if (adr_i == 2'b11)
sper <= #1 dat_i;
end
// write fifo
assign wfwe = wb_acc & (adr_i == 2'b10) & ack_o & we_i;
assign wfov = wfwe & wffull;
// dat_o
always @(posedge clk_i)
case(adr_i) // synopsys full_case parallel_case
2'b00: dat_o <= #1 spcr;
2'b01: dat_o <= #1 spsr;
2'b10: dat_o <= #1 rfdout;
2'b11: dat_o <= #1 sper;
endcase
// read fifo
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
// ack_o
always @(posedge clk_i or negedge rst_i)
if (~rst_i)
ack_o <= #1 1'b0;
else
ack_o <= #1 wb_acc & !ack_o;
// decode Serial Peripheral Control Register
wire spie = spcr[7]; // Interrupt enable bit
wire spe = spcr[6]; // System Enable bit
wire dwom = spcr[5]; // Port D Wired-OR Mode Bit
wire mstr = spcr[4]; // Master Mode Select Bit
wire cpol = spcr[3]; // Clock Polarity Bit
wire cpha = spcr[2]; // Clock Phase Bit
wire [1:0] spr = spcr[1:0]; // Clock Rate Select Bits
// decode Serial Peripheral Extension Register
wire [1:0] icnt = sper[7:6]; // interrupt on transfer count
wire [1:0] spre = sper[1:0]; // extended clock rate select
wire [3:0] espr = {spre, spr};
// generate status register
wire wr_spsr = wb_wr & (adr_i == 2'b01);
reg spif;
always @(posedge clk_i)
if (~spe)
spif <= #1 1'b0;
else
spif <= #1 (tirq | spif) & ~(wr_spsr & dat_i[7]);
reg wcol;
always @(posedge clk_i)
if (~spe)
wcol <= #1 1'b0;
else
wcol <= #1 (wfov | wcol) & ~(wr_spsr & dat_i[6]);
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
// generate IRQ output (inta_o)
always @(posedge clk_i)
inta_o <= #1 spif & spie;
//
// hookup read/write buffer fifo
fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( dat_i ),
.we ( wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
//
// generate clk divider
reg [11:0] clkcnt;
always @(posedge clk_i)
if(spe & (|clkcnt & |state))
clkcnt <= #1 clkcnt - 11'h1;
else
case (espr) // synopsys full_case parallel_case
4'b0000: clkcnt <= #1 12'h0; // 2 -- original M68HC11 coding
4'b0001: clkcnt <= #1 12'h1; // 4 -- original M68HC11 coding
4'b0010: clkcnt <= #1 12'h3; // 16 -- original M68HC11 coding
4'b0011: clkcnt <= #1 12'hf; // 32 -- original M68HC11 coding
4'b0100: clkcnt <= #1 12'h1f; // 8
4'b0101: clkcnt <= #1 12'h7; // 64
4'b0110: clkcnt <= #1 12'h3f; // 128
4'b0111: clkcnt <= #1 12'h7f; // 256
4'b1000: clkcnt <= #1 12'hff; // 512
4'b1001: clkcnt <= #1 12'h1ff; // 1024
4'b1010: clkcnt <= #1 12'h3ff; // 2048
4'b1011: clkcnt <= #1 12'h7ff; // 4096
endcase
// generate clock enable signal
wire ena = ~|clkcnt;
// transfer statemachine
always @(posedge clk_i)
if (~spe)
begin
state <= #1 2'b00; // idle
bcnt <= #1 3'h0;
treg <= #1 8'h00;
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
sck_o <= #1 1'b0;
end
else
begin
wfre <= #1 1'b0;
rfwe <= #1 1'b0;
case (state) //synopsys full_case parallel_case
2'b00: // idle state
begin
bcnt <= #1 3'h7; // set transfer counter
treg <= #1 wfdout; // load transfer register
sck_o <= #1 cpol; // set sck
if (~wfempty) begin
wfre <= #1 1'b1;
state <= #1 2'b01;
if (cpha) sck_o <= #1 ~sck_o;
end
end
2'b01: // clock-phase2, next data
if (ena) begin
sck_o <= #1 ~sck_o;
state <= #1 2'b11;
end
2'b11: // clock phase1
if (ena) begin
treg <= #1 {treg[6:0], miso_i};
bcnt <= #1 bcnt -3'h1;
if (~|bcnt) begin
state <= #1 2'b00;
sck_o <= #1 cpol;
rfwe <= #1 1'b1;
end else begin
state <= #1 2'b01;
sck_o <= #1 ~sck_o;
end
end
2'b10: state <= #1 2'b00;
endcase
end
assign mosi_o = treg[7];
// count number of transfers (for interrupt generation)
reg [1:0] tcnt; // transfer count
always @(posedge clk_i)
if (~spe)
tcnt <= #1 icnt;
else if (rfwe) // rfwe gets asserted when all bits have been transfered
if (|tcnt)
tcnt <= #1 tcnt - 2'h1;
else
tcnt <= #1 icnt;
assign tirq = ~|tcnt & rfwe;
endmodule |
module eth_miim
(
Clk,
Reset,
Divider,
NoPre,
CtrlData,
Rgad,
Fiad,
WCtrlData,
RStat,
ScanStat,
Mdi,
Mdo,
MdoEn,
Mdc,
Busy,
Prsd,
LinkFail,
Nvalid,
WCtrlDataStart,
RStatStart,
UpdateMIIRX_DATAReg
);
input Clk; // Host Clock
input Reset; // General Reset
input [7:0] Divider; // Divider for the host clock
input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
input [4:0] Rgad; // Register Address (within the PHY)
input [4:0] Fiad; // PHY Address
input NoPre; // No Preamble (no 32-bit preamble)
input WCtrlData; // Write Control Data operation
input RStat; // Read Status operation
input ScanStat; // Scan Status operation
input Mdi; // MII Management Data In
output Mdc; // MII Management Data Clock
output Mdo; // MII Management Data Output
output MdoEn; // MII Management Data Output Enable
output Busy; // Busy Signal
output LinkFail; // Link Integrity Signal
output Nvalid; // Invalid Status (qualifier for the valid scan result)
output [15:0] Prsd; // Read Status Data (data read from the PHY)
output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
parameter Tp = 1;
reg Nvalid;
reg EndBusy_d; // Pre-end Busy signal
reg EndBusy; // End Busy signal (stops the operation in progress)
reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
reg WCtrlDataStart_q;
reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
reg RStat_q1; // Read Status operation delayed 1 Clk cycle
reg RStat_q2; // Read Status operation delayed 2 Clk cycles
reg RStat_q3; // Read Status operation delayed 3 Clk cycles
reg RStatStart; // Start Read Status Command (positive edge detected)
reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
reg ScanStat_q1; // Scan Status operation delayed 1 cycle
reg ScanStat_q2; // Scan Status operation delayed 2 cycles
reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
wire WriteDataOp; // Write Data Operation (positive edge detected)
wire ReadStatusOp; // Read Status Operation (positive edge detected)
wire ScanStatusOp; // Scan Status Operation (positive edge detected)
wire StartOp; // Start Operation (start of any of the preceding operations)
wire EndOp; // End of Operation
reg InProgress; // Operation in progress
reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
reg [6:0] BitCounter; // Bit Counter
wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
wire MdcEn_n;
wire LatchByte1_d2;
wire LatchByte0_d2;
reg LatchByte1_d;
reg LatchByte0_d;
reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
// Generation of the EndBusy signal. It is used for ending the MII Management operation.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
EndBusy_d <= #Tp 1'b0;
EndBusy <= #Tp 1'b0;
end
else
begin
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
EndBusy <= #Tp EndBusy_d;
end
end
// Update MII RX_DATA register
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
UpdateMIIRX_DATAReg <= #Tp 0;
else
if(EndBusy & ~WCtrlDataStart_q)
UpdateMIIRX_DATAReg <= #Tp 1;
else
UpdateMIIRX_DATAReg <= #Tp 0;
end
// Generation of the delayed signals used for positive edge triggering.
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlData_q1 <= #Tp 1'b0;
WCtrlData_q2 <= #Tp 1'b0;
WCtrlData_q3 <= #Tp 1'b0;
RStat_q1 <= #Tp 1'b0;
RStat_q2 <= #Tp 1'b0;
RStat_q3 <= #Tp 1'b0;
ScanStat_q1 <= #Tp 1'b0;
ScanStat_q2 <= #Tp 1'b0;
SyncStatMdcEn <= #Tp 1'b0;
end
else
begin
WCtrlData_q1 <= #Tp WCtrlData;
WCtrlData_q2 <= #Tp WCtrlData_q1;
WCtrlData_q3 <= #Tp WCtrlData_q2;
RStat_q1 <= #Tp RStat;
RStat_q2 <= #Tp RStat_q1;
RStat_q3 <= #Tp RStat_q2;
ScanStat_q1 <= #Tp ScanStat;
ScanStat_q2 <= #Tp ScanStat_q1;
if(MdcEn)
SyncStatMdcEn <= #Tp ScanStat_q2;
end
end
// Generation of the Start Commands (Write Control Data or Read Status)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart <= #Tp 1'b0;
WCtrlDataStart_q <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(EndBusy)
begin
WCtrlDataStart <= #Tp 1'b0;
RStatStart <= #Tp 1'b0;
end
else
begin
if(WCtrlData_q2 & ~WCtrlData_q3)
WCtrlDataStart <= #Tp 1'b1;
if(RStat_q2 & ~RStat_q3)
RStatStart <= #Tp 1'b1;
WCtrlDataStart_q <= #Tp WCtrlDataStart;
end
end
end
// Generation of the Nvalid signal (indicates when the status is invalid)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
Nvalid <= #Tp 1'b0;
else
begin
if(~InProgress_q2 & InProgress_q3)
begin
Nvalid <= #Tp 1'b0;
end
else
begin
if(ScanStat_q2 & ~SyncStatMdcEn)
Nvalid <= #Tp 1'b1;
end
end
end
// Signals used for the generation of the Operation signals (positive edge)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
WCtrlDataStart_q1 <= #Tp 1'b0;
WCtrlDataStart_q2 <= #Tp 1'b0;
RStatStart_q1 <= #Tp 1'b0;
RStatStart_q2 <= #Tp 1'b0;
InProgress_q1 <= #Tp 1'b0;
InProgress_q2 <= #Tp 1'b0;
InProgress_q3 <= #Tp 1'b0;
LatchByte0_d <= #Tp 1'b0;
LatchByte1_d <= #Tp 1'b0;
LatchByte <= #Tp 2'b00;
end
else
begin
if(MdcEn)
begin
WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
RStatStart_q1 <= #Tp RStatStart;
RStatStart_q2 <= #Tp RStatStart_q1;
LatchByte[0] <= #Tp LatchByte0_d;
LatchByte[1] <= #Tp LatchByte1_d;
LatchByte0_d <= #Tp LatchByte0_d2;
LatchByte1_d <= #Tp LatchByte1_d2;
InProgress_q1 <= #Tp InProgress;
InProgress_q2 <= #Tp InProgress_q1;
InProgress_q3 <= #Tp InProgress_q2;
end
end
end
// Generation of the Operation signals
assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
// Busy
assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
// Generation of the InProgress signal (indicates when an operation is in progress)
// Generation of the WriteOp signal (indicates when a write is in progress)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
else
begin
if(MdcEn)
begin
if(StartOp)
begin
if(~InProgress)
WriteOp <= #Tp WriteDataOp;
InProgress <= #Tp 1'b1;
end
else
begin
if(EndOp)
begin
InProgress <= #Tp 1'b0;
WriteOp <= #Tp 1'b0;
end
end
end
end
end
// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
BitCounter[6:0] <= #Tp 7'h0;
else
begin
if(MdcEn)
begin
if(InProgress)
begin
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= #Tp 7'h21;
else
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
end
else
BitCounter[6:0] <= #Tp 7'h0;
end
end
end
// Operation ends when the Bit Counter reaches 63
assign EndOp = BitCounter==63;
assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
// Latch Byte selects which part of Read Status Data is updated from the shift register
assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
// Connecting the Clock Generator Module
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
);
// Connecting the Shift Register Module
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
);
// Connecting the Output Control Module
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
.Mdo(Mdo), .MdoEn(MdoEn)
);
endmodule |
module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input MRxClk; // Receive clock (from PHY)
input TxReset; // Transmit reset
input RxReset; // Receive reset
input TPauseRq; // Transmit control frame (from host)
input [7:0] TxDataIn; // Transmit packet data byte (from host)
input TxStartFrmIn; // Transmit packet start frame input (from host)
input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
input TxEndFrmIn; // Transmit packet end frame input (from host)
input TxDoneIn; // Transmit packet done (from TxEthMAC)
input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
input PadIn; // Padding (input from registers)
input CrcEnIn; // Crc append (input from registers)
input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
input RxValid; // Received a valid packet
input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
input ReceivedPacketGood; // Received packet is good
input ReceivedLengthOK; // Length of the received packet is OK
input TxFlow; // Tx flow control (from registers)
input RxFlow; // Rx flow control (from registers)
input DlyCrcEn; // Delayed CRC enabled (from registers)
input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
input [47:0] MAC; // MAC address (from registers)
input RxStatusWriteLatched_sync2;
input r_PassAll;
output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
output TxDoneOut; // Transmit packet done (to host)
output TxAbortOut; // Transmit packet aborted (to host)
output TxUsedDataOut; // Transmit packet used data (to host)
output PadOut; // Padding (output to TxEthMAC)
output CrcEnOut; // Crc append (output to TxEthMAC)
output WillSendControlFrame;
output TxCtrlEndFrm;
output ReceivedPauseFrm;
output ControlFrmAddressOK;
output SetPauseTimer;
reg TxUsedDataOutDetected;
reg TxAbortInLatched;
reg TxDoneInLatched;
reg MuxedDone;
reg MuxedAbort;
wire Pause;
wire TxCtrlStartFrm;
wire [7:0] ControlData;
wire CtrlMux;
wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
wire BlockTxDone;
// Signal TxUsedDataOut was detected (a transfer is already in progress)
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxDoneIn | TxAbortIn)
TxUsedDataOutDetected <= #Tp 1'b0;
else
if(TxUsedDataOut)
TxUsedDataOutDetected <= #Tp 1'b1;
end
// Latching variables
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
begin
TxAbortInLatched <= #Tp 1'b0;
TxDoneInLatched <= #Tp 1'b0;
end
else
begin
TxAbortInLatched <= #Tp TxAbortIn;
TxDoneInLatched <= #Tp TxDoneIn;
end
end
// Generating muxed abort signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedAbort <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedAbort <= #Tp 1'b0;
else
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
MuxedAbort <= #Tp 1'b1;
end
// Generating muxed done signal
always @ (posedge MTxClk or posedge TxReset)
begin
if(TxReset)
MuxedDone <= #Tp 1'b0;
else
if(TxStartFrmIn)
MuxedDone <= #Tp 1'b0;
else
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
MuxedDone <= #Tp 1'b1;
end
// TxDoneOut
assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
// TxAbortOut
assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
// TxUsedDataOut
assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
// TxStartFrmOut
assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
// TxEndFrmOut
assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
// TxDataOut[7:0]
assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
// PadOut
assign PadOut = PadIn | SendingCtrlFrm;
// CrcEnOut
assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
// Connecting receivecontrol module
eth_receivecontrol receivecontrol1
(
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
.ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
.ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
.Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
.r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
);
eth_transmitcontrol transmitcontrol1
(
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
.TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
.MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
.CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
);
endmodule |
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
parameter WIDTH = 8; // default parameter of the register width
parameter RESET_VALUE = 0;
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input SyncReset;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
DataOut<=#1 RESET_VALUE;
else
if(SyncReset)
DataOut<=#1 RESET_VALUE;
else
if(Write) // write
DataOut<=#1 DataIn;
end
endmodule // Register |
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateJam_q;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule |
module eth_cop
(
// WISHBONE common
wb_clk_i, wb_rst_i,
// WISHBONE MASTER 1
m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o,
m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o,
m1_wb_err_o,
// WISHBONE MASTER 2
m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o,
m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o,
m2_wb_err_o,
// WISHBONE slave 1
s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o,
s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i,
s1_wb_dat_o,
// WISHBONE slave 2
s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o,
s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i,
s2_wb_dat_o
);
parameter Tp=1;
// WISHBONE common
input wb_clk_i, wb_rst_i;
// WISHBONE MASTER 1
input [31:0] m1_wb_adr_i, m1_wb_dat_i;
input [3:0] m1_wb_sel_i;
input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i;
output [31:0] m1_wb_dat_o;
output m1_wb_ack_o, m1_wb_err_o;
// WISHBONE MASTER 2
input [31:0] m2_wb_adr_i, m2_wb_dat_i;
input [3:0] m2_wb_sel_i;
input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i;
output [31:0] m2_wb_dat_o;
output m2_wb_ack_o, m2_wb_err_o;
// WISHBONE slave 1
input [31:0] s1_wb_dat_i;
input s1_wb_ack_i, s1_wb_err_i;
output [31:0] s1_wb_adr_o, s1_wb_dat_o;
output [3:0] s1_wb_sel_o;
output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o;
// WISHBONE slave 2
input [31:0] s2_wb_dat_i;
input s2_wb_ack_i, s2_wb_err_i;
output [31:0] s2_wb_adr_o, s2_wb_dat_o;
output [3:0] s2_wb_sel_o;
output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o;
reg m1_in_progress;
reg m2_in_progress;
reg [31:0] s1_wb_adr_o;
reg [3:0] s1_wb_sel_o;
reg s1_wb_we_o;
reg [31:0] s1_wb_dat_o;
reg s1_wb_cyc_o;
reg s1_wb_stb_o;
reg [31:0] s2_wb_adr_o;
reg [3:0] s2_wb_sel_o;
reg s2_wb_we_o;
reg [31:0] s2_wb_dat_o;
reg s2_wb_cyc_o;
reg s2_wb_stb_o;
reg m1_wb_ack_o;
reg [31:0] m1_wb_dat_o;
reg m2_wb_ack_o;
reg [31:0] m2_wb_dat_o;
reg m1_wb_err_o;
reg m2_wb_err_o;
wire m_wb_access_finished;
wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (`M1_ADDRESSED_S1 | `M1_ADDRESSED_S2);
wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (`M2_ADDRESSED_S1 | `M2_ADDRESSED_S2);
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
m1_in_progress <=#Tp 0;
m2_in_progress <=#Tp 0;
s1_wb_adr_o <=#Tp 0;
s1_wb_sel_o <=#Tp 0;
s1_wb_we_o <=#Tp 0;
s1_wb_dat_o <=#Tp 0;
s1_wb_cyc_o <=#Tp 0;
s1_wb_stb_o <=#Tp 0;
s2_wb_adr_o <=#Tp 0;
s2_wb_sel_o <=#Tp 0;
s2_wb_we_o <=#Tp 0;
s2_wb_dat_o <=#Tp 0;
s2_wb_cyc_o <=#Tp 0;
s2_wb_stb_o <=#Tp 0;
end
else
begin
case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case
5'b00_10_0, 5'b00_11_0 :
begin
m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m
if(`M1_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m1_wb_adr_i;
s1_wb_sel_o <=#Tp m1_wb_sel_i;
s1_wb_we_o <=#Tp m1_wb_we_i;
s1_wb_dat_o <=#Tp m1_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m1_wb_adr_i;
s2_wb_sel_o <=#Tp m1_wb_sel_i;
s2_wb_we_o <=#Tp m1_wb_we_i;
s2_wb_dat_o <=#Tp m1_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b00_01_0 :
begin
m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m
if(`M2_ADDRESSED_S1)
begin
s1_wb_adr_o <=#Tp m2_wb_adr_i;
s1_wb_sel_o <=#Tp m2_wb_sel_i;
s1_wb_we_o <=#Tp m2_wb_we_i;
s1_wb_dat_o <=#Tp m2_wb_dat_i;
s1_wb_cyc_o <=#Tp 1'b1;
s1_wb_stb_o <=#Tp 1'b1;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_adr_o <=#Tp m2_wb_adr_i;
s2_wb_sel_o <=#Tp m2_wb_sel_i;
s2_wb_we_o <=#Tp m2_wb_we_i;
s2_wb_dat_o <=#Tp m2_wb_dat_i;
s2_wb_cyc_o <=#Tp 1'b1;
s2_wb_stb_o <=#Tp 1'b1;
end
else
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time);
end
5'b10_10_1, 5'b10_11_1 :
begin
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1.
if(`M1_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M1_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
5'b01_01_1, 5'b01_11_1 :
begin
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2.
if(`M2_ADDRESSED_S1)
begin
s1_wb_cyc_o <=#Tp 1'b0;
s1_wb_stb_o <=#Tp 1'b0;
end
else if(`M2_ADDRESSED_S2)
begin
s2_wb_cyc_o <=#Tp 1'b0;
s2_wb_stb_o <=#Tp 1'b0;
end
end
endcase
end
end
// Generating Ack for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M1_ADDRESSED_S1 or `M1_ADDRESSED_S2)
begin
if(m1_in_progress)
begin
if(`M1_ADDRESSED_S1) begin
m1_wb_ack_o <= s1_wb_ack_i;
m1_wb_dat_o <= s1_wb_dat_i;
end
else if(`M1_ADDRESSED_S2) begin
m1_wb_ack_o <= s2_wb_ack_i;
m1_wb_dat_o <= s2_wb_dat_i;
end
end
else
m1_wb_ack_o <= 0;
end
// Generating Ack for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2)
begin
if(m2_in_progress)
begin
if(`M2_ADDRESSED_S1) begin
m2_wb_ack_o <= s1_wb_ack_i;
m2_wb_dat_o <= s1_wb_dat_i;
end
else if(`M2_ADDRESSED_S2) begin
m2_wb_ack_o <= s2_wb_ack_i;
m2_wb_dat_o <= s2_wb_dat_i;
end
end
else
m2_wb_ack_o <= 0;
end
// Generating Err for master 1
always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m1_wb_cyc_i or m1_wb_stb_i)
begin
if(m1_in_progress) begin
if(`M1_ADDRESSED_S1)
m1_wb_err_o <= s1_wb_err_i;
else if(`M1_ADDRESSED_S2)
m1_wb_err_o <= s2_wb_err_i;
end
else if(m1_wb_cyc_i & m1_wb_stb_i & ~`M1_ADDRESSED_S1 & ~`M1_ADDRESSED_S2)
m1_wb_err_o <= 1'b1;
else
m1_wb_err_o <= 1'b0;
end
// Generating Err for master 2
always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or `M2_ADDRESSED_S1 or `M2_ADDRESSED_S2 or
m2_wb_cyc_i or m2_wb_stb_i)
begin
if(m2_in_progress) begin
if(`M2_ADDRESSED_S1)
m2_wb_err_o <= s1_wb_err_i;
else if(`M2_ADDRESSED_S2)
m2_wb_err_o <= s2_wb_err_i;
end
else if(m2_wb_cyc_i & m2_wb_stb_i & ~`M2_ADDRESSED_S1 & ~`M2_ADDRESSED_S2)
m2_wb_err_o <= 1'b1;
else
m2_wb_err_o <= 1'b0;
end
assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o;
// Activity monitor
integer cnt;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
cnt <=#Tp 0;
else
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i)
cnt <=#Tp 0;
else
if(s1_wb_cyc_o | s2_wb_cyc_o)
cnt <=#Tp cnt+1;
end
always @ (posedge wb_clk_i)
begin
if(cnt==1000) begin
$display("(%0t)(%m) ERROR: WB activity ??? ", $time);
if(s1_wb_cyc_o) begin
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
end
else if(s2_wb_cyc_o) begin
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
end
$stop;
end
end
always @ (posedge wb_clk_i)
begin
if(s1_wb_err_i & s1_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o);
$display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o);
$display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o);
$display("s1_wb_we_o = 0x%0x", s1_wb_we_o);
$stop;
end
if(s2_wb_err_i & s2_wb_cyc_o) begin
$display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time);
$display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o);
$display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o);
$display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o);
$display("s2_wb_we_o = 0x%0x", s2_wb_we_o);
$stop;
end
end
endmodule |
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
parameter Tp = 1;
input MRxClk;
input Reset;
input MRxDV;
input StateSFD;
input [1:0] StateData;
input MRxDEqD;
input StateIdle;
input StateDrop;
input DlyCrcEn;
input StatePreamble;
input Transmitting;
input HugEn;
input [15:0] MaxFL;
input r_IFG;
output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
output [3:0] DlyCrcCnt; // Delayed CRC counter
output ByteCntEq0; // Byte counter = 0
output ByteCntEq1; // Byte counter = 1
output ByteCntEq2; // Byte counter = 2
output ByteCntEq3; // Byte counter = 3
output ByteCntEq4; // Byte counter = 4
output ByteCntEq5; // Byte counter = 5
output ByteCntEq6; // Byte counter = 6
output ByteCntEq7; // Byte counter = 7
output ByteCntGreat2; // Byte counter > 2
output ByteCntSmall7; // Byte counter < 7
output ByteCntMaxFrame; // Byte counter = MaxFL
output [15:0] ByteCntOut; // Byte counter
wire ResetByteCounter;
wire IncrementByteCounter;
wire ResetIFGCounter;
wire IncrementIFGCounter;
wire ByteCntMax;
reg [15:0] ByteCnt;
reg [3:0] DlyCrcCnt;
reg [4:0] IFGCounter;
wire [15:0] ByteCntDelayed;
assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
(StatePreamble | StateSFD | StateIdle & ~Transmitting |
StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
IFGCounter[4:0] <= #Tp 5'h0;
else
begin
if(ResetIFGCounter)
IFGCounter[4:0] <= #Tp 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
end
end
assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
begin
if(DlyCrcCnt[3:0] == 4'h9)
DlyCrcCnt[3:0] <= #Tp 4'h0;
else
if(DlyCrcEn & StateSFD)
DlyCrcCnt[3:0] <= #Tp 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
end
end
endmodule |
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
parameter Tp = 1;
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= #Tp 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= #Tp 16'h0;
else
if(IncrementNibCnt)
NibCnt <= #Tp NibCnt + 1'b1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= #Tp 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= #Tp 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= #Tp 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= #Tp 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
end
end
endmodule |
module eth_top
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
int_o
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
wire [29:0] m_wb_adr_tmp;
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
output int_o; // Interrupt output
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
`ifdef ETH_AVALON_BUS
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
`else // WISHBONE
assign temp_wb_ack_o = (|RegCs) | BDAck;
`endif
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <=#Tp 1'b0;
temp_wb_dat_o_reg <=#Tp 32'h0;
temp_wb_err_o_reg <=#Tp 1'b0;
end
else
begin
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.SetPauseTimer(SetPauseTimer)
);
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= #Tp 1'b0;
CarrierSense_Tx2 <= #Tp 1'b0;
end
else
begin
CarrierSense_Tx1 <= #Tp mcrs_pad_i;
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
end
end
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= #Tp 1'b0;
Collision_Tx2 <= #Tp 1'b0;
end
else
begin
Collision_Tx1 <= #Tp mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= #Tp 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= #Tp 1'b1;
end
end
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= #Tp WillTransmit;
WillTransmit_q2 <= #Tp WillTransmit_q;
end
assign Transmitting = ~r_FullD & WillTransmit_q2;
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= #Tp 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= #Tp r_RxEn;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= #Tp 1'b0;
TxPauseRq_sync2 <= #Tp 1'b0;
TxPauseRq_sync3 <= #Tp 1'b0;
end
else
begin
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
end
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= #Tp 1'b0;
else
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= #Tp 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= #Tp 1'b1;
else if(RxAbortRst)
RxAbort_latch <= #Tp 1'b0;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
RxAbort_wb <= #Tp 1'b0;
end
else
begin
RxAbort_sync1 <= #Tp RxAbort_latch;
RxAbort_wb <= #Tp RxAbort_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= #Tp 1'b0;
RxAbortRst <= #Tp 1'b0;
end
else
begin
RxAbortRst_sync1 <= #Tp RxAbort_wb;
RxAbortRst <= #Tp RxAbortRst_sync1;
end
end
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
.Reset(wb_rst_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
`endif
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
endmodule |
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifdef ETH_FIFO_XILINX
`else
`ifdef ETH_ALTERA_ALTSYNCRAM
`else
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
`endif
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <=#Tp 0;
else
if(clear)
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <=#Tp cnt - 1'b1;
else
cnt <=#Tp cnt + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <=#Tp 0;
else
if(clear)
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <=#Tp read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <=#Tp 0;
else
if(clear)
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <=#Tp write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst
(
.data (data_in),
.wren (write & ~full),
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
.clock (clk),
.q (data_out)
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
`else // !ETH_ALTERA_ALTSYNCRAM
always @ (posedge clk)
begin
if(write & clear)
fifo[0] <=#Tp data_in;
else
if(write & ~full)
fifo[write_pointer] <=#Tp data_in;
end
always @ (posedge clk)
begin
if(clear)
data_out <=#Tp fifo[0];
else
data_out <=#Tp fifo[read_pointer];
end
`endif // !ETH_ALTERA_ALTSYNCRAM
`endif // !ETH_FIFO_XILINX
endmodule |
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
// Rx Address Check
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
always @ (posedge MRxClk)
begin
CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
end
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= #Tp 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= #Tp Crc[31:26];
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= #Tp 8'h0;
DelayData <= #Tp 1'b0;
LatchedByte[7:0] <= #Tp 8'h0;
RxData[7:0] <= #Tp 8'h0;
end
else
begin
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
DelayData <= #Tp StateData[0];
if(GenerateRxValid)
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= #Tp 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= #Tp 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= #Tp 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= #Tp 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= #Tp 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= #Tp 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= #Tp 1'b0;
end
end
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= #Tp 1'b0;
RxValid <= #Tp 1'b0;
end
else
begin
RxValid_d <= #Tp GenerateRxValid;
RxValid <= #Tp RxValid_d;
end
end
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= #Tp 1'b0;
RxStartFrm <= #Tp 1'b0;
end
else
begin
RxStartFrm_d <= #Tp GenerateRxStartFrm;
RxStartFrm <= #Tp RxStartFrm_d;
end
end
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= #Tp 1'b0;
RxEndFrm <= #Tp 1'b0;
end
else
begin
RxEndFrm_d <= #Tp GenerateRxEndFrm;
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm;
end
end
endmodule |
module wb_conmax_pri_dec(valid, pri_in, pri_out);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input valid;
input [1:0] pri_in;
output [3:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [3:0] pri_out;
reg [3:0] pri_out_d0;
reg [3:0] pri_out_d1;
////////////////////////////////////////////////////////////////////
//
// Priority Decoder
//
// 4 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d1 = 4'b0001;
else
if(pri_in==2'h0) pri_out_d1 = 4'b0001;
else
if(pri_in==2'h1) pri_out_d1 = 4'b0010;
else
if(pri_in==2'h2) pri_out_d1 = 4'b0100;
else pri_out_d1 = 4'b1000;
// 2 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d0 = 4'b0001;
else
if(pri_in==2'h0) pri_out_d0 = 4'b0001;
else pri_out_d0 = 4'b0010;
// Select Configured Priority
assign pri_out = (pri_sel==2'd0) ? 4'h0 : ( (pri_sel==1'd1) ? pri_out_d0 : pri_out_d1 );
endmodule |
module wb_conmax_rf(
clk_i, rst_i,
// Internal Wishbone Interface
i_wb_data_i, i_wb_data_o, i_wb_addr_i, i_wb_sel_i, i_wb_we_i, i_wb_cyc_i,
i_wb_stb_i, i_wb_ack_o, i_wb_err_o, i_wb_rty_o,
// External Wishbone Interface
e_wb_data_i, e_wb_data_o, e_wb_addr_o, e_wb_sel_o, e_wb_we_o, e_wb_cyc_o,
e_wb_stb_o, e_wb_ack_i, e_wb_err_i, e_wb_rty_i,
// Configuration Registers
conf0, conf1, conf2, conf3, conf4, conf5, conf6, conf7,
conf8, conf9, conf10, conf11, conf12, conf13, conf14, conf15
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [3:0] rf_addr = 4'hf;
parameter dw = 32; // Data bus Width
parameter aw = 32; // Address bus Width
parameter sw = dw / 8; // Number of Select Lines
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
// Internal Wishbone Interface
input [dw-1:0] i_wb_data_i;
output [dw-1:0] i_wb_data_o;
input [aw-1:0] i_wb_addr_i;
input [sw-1:0] i_wb_sel_i;
input i_wb_we_i;
input i_wb_cyc_i;
input i_wb_stb_i;
output i_wb_ack_o;
output i_wb_err_o;
output i_wb_rty_o;
// External Wishbone Interface
input [dw-1:0] e_wb_data_i;
output [dw-1:0] e_wb_data_o;
output [aw-1:0] e_wb_addr_o;
output [sw-1:0] e_wb_sel_o;
output e_wb_we_o;
output e_wb_cyc_o;
output e_wb_stb_o;
input e_wb_ack_i;
input e_wb_err_i;
input e_wb_rty_i;
// Configuration Registers
output [15:0] conf0;
output [15:0] conf1;
output [15:0] conf2;
output [15:0] conf3;
output [15:0] conf4;
output [15:0] conf5;
output [15:0] conf6;
output [15:0] conf7;
output [15:0] conf8;
output [15:0] conf9;
output [15:0] conf10;
output [15:0] conf11;
output [15:0] conf12;
output [15:0] conf13;
output [15:0] conf14;
output [15:0] conf15;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [15:0] conf0, conf1, conf2, conf3, conf4, conf5;
reg [15:0] conf6, conf7, conf8, conf9, conf10, conf11;
reg [15:0] conf12, conf13, conf14, conf15;
//synopsys infer_multibit "conf0"
//synopsys infer_multibit "conf1"
//synopsys infer_multibit "conf2"
//synopsys infer_multibit "conf3"
//synopsys infer_multibit "conf4"
//synopsys infer_multibit "conf5"
//synopsys infer_multibit "conf6"
//synopsys infer_multibit "conf7"
//synopsys infer_multibit "conf8"
//synopsys infer_multibit "conf9"
//synopsys infer_multibit "conf10"
//synopsys infer_multibit "conf11"
//synopsys infer_multibit "conf12"
//synopsys infer_multibit "conf13"
//synopsys infer_multibit "conf14"
//synopsys infer_multibit "conf15"
wire rf_sel;
reg [15:0] rf_dout;
reg rf_ack;
reg rf_we;
////////////////////////////////////////////////////////////////////
//
// Register File Select Logic
//
assign rf_sel = i_wb_cyc_i & i_wb_stb_i & (i_wb_addr_i[aw-5:aw-8] == rf_addr);
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
always @(posedge clk_i)
rf_we <= #1 rf_sel & i_wb_we_i & !rf_we;
always @(posedge clk_i)
rf_ack <= #1 rf_sel & !rf_ack;
// Writre Logic
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf0 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd0) ) conf0 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf1 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd1) ) conf1 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf2 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd2) ) conf2 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf3 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd3) ) conf3 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf4 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd4) ) conf4 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf5 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd5) ) conf5 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf6 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd6) ) conf6 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf7 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd7) ) conf7 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf8 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd8) ) conf8 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf9 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd9) ) conf9 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf10 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd10) ) conf10 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf11 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd11) ) conf11 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf12 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd12) ) conf12 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf13 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd13) ) conf13 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf14 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd14) ) conf14 <= #1 i_wb_data_i[15:0];
always @(posedge clk_i or posedge rst_i)
if(rst_i) conf15 <= #1 16'h0;
else
if(rf_we & (i_wb_addr_i[5:2] == 4'd15) ) conf15 <= #1 i_wb_data_i[15:0];
// Read Logic
always @(posedge clk_i)
if(!rf_sel) rf_dout <= #1 16'h0;
else
case(i_wb_addr_i[5:2])
4'd0: rf_dout <= #1 conf0;
4'd1: rf_dout <= #1 conf1;
4'd2: rf_dout <= #1 conf2;
4'd3: rf_dout <= #1 conf3;
4'd4: rf_dout <= #1 conf4;
4'd5: rf_dout <= #1 conf5;
4'd6: rf_dout <= #1 conf6;
4'd7: rf_dout <= #1 conf7;
4'd8: rf_dout <= #1 conf8;
4'd9: rf_dout <= #1 conf9;
4'd10: rf_dout <= #1 conf10;
4'd11: rf_dout <= #1 conf11;
4'd12: rf_dout <= #1 conf12;
4'd13: rf_dout <= #1 conf13;
4'd14: rf_dout <= #1 conf14;
4'd15: rf_dout <= #1 conf15;
endcase
////////////////////////////////////////////////////////////////////
//
// Register File By-Pass Logic
//
assign e_wb_addr_o = i_wb_addr_i;
assign e_wb_sel_o = i_wb_sel_i;
assign e_wb_data_o = i_wb_data_i;
assign e_wb_cyc_o = rf_sel ? 1'b0 : i_wb_cyc_i;
assign e_wb_stb_o = i_wb_stb_i;
assign e_wb_we_o = i_wb_we_i;
assign i_wb_data_o = rf_sel ? { {aw-16{1'b0}}, rf_dout} : e_wb_data_i;
assign i_wb_ack_o = rf_sel ? rf_ack : e_wb_ack_i;
assign i_wb_err_o = rf_sel ? 1'b0 : e_wb_err_i;
assign i_wb_rty_o = rf_sel ? 1'b0 : e_wb_rty_i;
endmodule |
module wb_conmax_msel(
clk_i, rst_i,
conf, req, sel, next
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
input [15:0] conf;
input [7:0] req;
output [2:0] sel;
input next;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [1:0] pri0, pri1, pri2, pri3;
wire [1:0] pri4, pri5, pri6, pri7;
wire [1:0] pri_out_d;
reg [1:0] pri_out;
wire [7:0] req_p0, req_p1, req_p2, req_p3;
wire [2:0] gnt_p0, gnt_p1, gnt_p2, gnt_p3;
reg [2:0] sel1, sel2;
wire [2:0] sel;
////////////////////////////////////////////////////////////////////
//
// Priority Select logic
//
assign pri0[0] = (pri_sel == 2'd0) ? 1'b0 : conf[0];
assign pri0[1] = (pri_sel == 2'd2) ? conf[1] : 1'b0;
assign pri1[0] = (pri_sel == 2'd0) ? 1'b0 : conf[2];
assign pri1[1] = (pri_sel == 2'd2) ? conf[3] : 1'b0;
assign pri2[0] = (pri_sel == 2'd0) ? 1'b0 : conf[4];
assign pri2[1] = (pri_sel == 2'd2) ? conf[5] : 1'b0;
assign pri3[0] = (pri_sel == 2'd0) ? 1'b0 : conf[6];
assign pri3[1] = (pri_sel == 2'd2) ? conf[7] : 1'b0;
assign pri4[0] = (pri_sel == 2'd0) ? 1'b0 : conf[8];
assign pri4[1] = (pri_sel == 2'd2) ? conf[9] : 1'b0;
assign pri5[0] = (pri_sel == 2'd0) ? 1'b0 : conf[10];
assign pri5[1] = (pri_sel == 2'd2) ? conf[11] : 1'b0;
assign pri6[0] = (pri_sel == 2'd0) ? 1'b0 : conf[12];
assign pri6[1] = (pri_sel == 2'd2) ? conf[13] : 1'b0;
assign pri7[0] = (pri_sel == 2'd0) ? 1'b0 : conf[14];
assign pri7[1] = (pri_sel == 2'd2) ? conf[15] : 1'b0;
// Priority Encoder
wb_conmax_pri_enc #(pri_sel) pri_enc(
.valid( req ),
.pri0( pri0 ),
.pri1( pri1 ),
.pri2( pri2 ),
.pri3( pri3 ),
.pri4( pri4 ),
.pri5( pri5 ),
.pri6( pri6 ),
.pri7( pri7 ),
.pri_out( pri_out_d )
);
always @(posedge clk_i)
if(rst_i) pri_out <= #1 2'h0;
else
if(next) pri_out <= #1 pri_out_d;
////////////////////////////////////////////////////////////////////
//
// Arbiters
//
assign req_p0[0] = req[0] & (pri0 == 2'd0);
assign req_p0[1] = req[1] & (pri1 == 2'd0);
assign req_p0[2] = req[2] & (pri2 == 2'd0);
assign req_p0[3] = req[3] & (pri3 == 2'd0);
assign req_p0[4] = req[4] & (pri4 == 2'd0);
assign req_p0[5] = req[5] & (pri5 == 2'd0);
assign req_p0[6] = req[6] & (pri6 == 2'd0);
assign req_p0[7] = req[7] & (pri7 == 2'd0);
assign req_p1[0] = req[0] & (pri0 == 2'd1);
assign req_p1[1] = req[1] & (pri1 == 2'd1);
assign req_p1[2] = req[2] & (pri2 == 2'd1);
assign req_p1[3] = req[3] & (pri3 == 2'd1);
assign req_p1[4] = req[4] & (pri4 == 2'd1);
assign req_p1[5] = req[5] & (pri5 == 2'd1);
assign req_p1[6] = req[6] & (pri6 == 2'd1);
assign req_p1[7] = req[7] & (pri7 == 2'd1);
assign req_p2[0] = req[0] & (pri0 == 2'd2);
assign req_p2[1] = req[1] & (pri1 == 2'd2);
assign req_p2[2] = req[2] & (pri2 == 2'd2);
assign req_p2[3] = req[3] & (pri3 == 2'd2);
assign req_p2[4] = req[4] & (pri4 == 2'd2);
assign req_p2[5] = req[5] & (pri5 == 2'd2);
assign req_p2[6] = req[6] & (pri6 == 2'd2);
assign req_p2[7] = req[7] & (pri7 == 2'd2);
assign req_p3[0] = req[0] & (pri0 == 2'd3);
assign req_p3[1] = req[1] & (pri1 == 2'd3);
assign req_p3[2] = req[2] & (pri2 == 2'd3);
assign req_p3[3] = req[3] & (pri3 == 2'd3);
assign req_p3[4] = req[4] & (pri4 == 2'd3);
assign req_p3[5] = req[5] & (pri5 == 2'd3);
assign req_p3[6] = req[6] & (pri6 == 2'd3);
assign req_p3[7] = req[7] & (pri7 == 2'd3);
wb_conmax_arb arb0(
.clk( clk_i ),
.rst( rst_i ),
.req( req_p0 ),
.gnt( gnt_p0 ),
.next( 1'b0 )
);
wb_conmax_arb arb1(
.clk( clk_i ),
.rst( rst_i ),
.req( req_p1 ),
.gnt( gnt_p1 ),
.next( 1'b0 )
);
wb_conmax_arb arb2(
.clk( clk_i ),
.rst( rst_i ),
.req( req_p2 ),
.gnt( gnt_p2 ),
.next( 1'b0 )
);
wb_conmax_arb arb3(
.clk( clk_i ),
.rst( rst_i ),
.req( req_p3 ),
.gnt( gnt_p3 ),
.next( 1'b0 )
);
////////////////////////////////////////////////////////////////////
//
// Final Master Select
//
always @(pri_out or gnt_p0 or gnt_p1)
if(pri_out[0]) sel1 = gnt_p1;
else sel1 = gnt_p0;
always @(pri_out or gnt_p0 or gnt_p1 or gnt_p2 or gnt_p3)
case(pri_out)
2'd0: sel2 = gnt_p0;
2'd1: sel2 = gnt_p1;
2'd2: sel2 = gnt_p2;
2'd3: sel2 = gnt_p3;
endcase
assign sel = (pri_sel==2'd0) ? gnt_p0 : ( (pri_sel==2'd1) ? sel1 : sel2 );
endmodule |
module wb_conmax_slave_if(
clk_i, rst_i, conf,
// Slave interface
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
// Master 0 Interface
m0_data_i, m0_data_o, m0_addr_i, m0_sel_i, m0_we_i, m0_cyc_i,
m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o,
// Master 1 Interface
m1_data_i, m1_data_o, m1_addr_i, m1_sel_i, m1_we_i, m1_cyc_i,
m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o,
// Master 2 Interface
m2_data_i, m2_data_o, m2_addr_i, m2_sel_i, m2_we_i, m2_cyc_i,
m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o,
// Master 3 Interface
m3_data_i, m3_data_o, m3_addr_i, m3_sel_i, m3_we_i, m3_cyc_i,
m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o,
// Master 4 Interface
m4_data_i, m4_data_o, m4_addr_i, m4_sel_i, m4_we_i, m4_cyc_i,
m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o,
// Master 5 Interface
m5_data_i, m5_data_o, m5_addr_i, m5_sel_i, m5_we_i, m5_cyc_i,
m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o,
// Master 6 Interface
m6_data_i, m6_data_o, m6_addr_i, m6_sel_i, m6_we_i, m6_cyc_i,
m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o,
// Master 7 Interface
m7_data_i, m7_data_o, m7_addr_i, m7_sel_i, m7_we_i, m7_cyc_i,
m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd2;
parameter aw = 32; // Address bus Width
parameter dw = 32; // Data bus Width
parameter sw = dw / 8; // Number of Select Lines
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
input [15:0] conf;
// Slave Interface
input [dw-1:0] wb_data_i;
output [dw-1:0] wb_data_o;
output [aw-1:0] wb_addr_o;
output [sw-1:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// Master 0 Interface
input [dw-1:0] m0_data_i;
output [dw-1:0] m0_data_o;
input [aw-1:0] m0_addr_i;
input [sw-1:0] m0_sel_i;
input m0_we_i;
input m0_cyc_i;
input m0_stb_i;
output m0_ack_o;
output m0_err_o;
output m0_rty_o;
// Master 1 Interface
input [dw-1:0] m1_data_i;
output [dw-1:0] m1_data_o;
input [aw-1:0] m1_addr_i;
input [sw-1:0] m1_sel_i;
input m1_we_i;
input m1_cyc_i;
input m1_stb_i;
output m1_ack_o;
output m1_err_o;
output m1_rty_o;
// Master 2 Interface
input [dw-1:0] m2_data_i;
output [dw-1:0] m2_data_o;
input [aw-1:0] m2_addr_i;
input [sw-1:0] m2_sel_i;
input m2_we_i;
input m2_cyc_i;
input m2_stb_i;
output m2_ack_o;
output m2_err_o;
output m2_rty_o;
// Master 3 Interface
input [dw-1:0] m3_data_i;
output [dw-1:0] m3_data_o;
input [aw-1:0] m3_addr_i;
input [sw-1:0] m3_sel_i;
input m3_we_i;
input m3_cyc_i;
input m3_stb_i;
output m3_ack_o;
output m3_err_o;
output m3_rty_o;
// Master 4 Interface
input [dw-1:0] m4_data_i;
output [dw-1:0] m4_data_o;
input [aw-1:0] m4_addr_i;
input [sw-1:0] m4_sel_i;
input m4_we_i;
input m4_cyc_i;
input m4_stb_i;
output m4_ack_o;
output m4_err_o;
output m4_rty_o;
// Master 5 Interface
input [dw-1:0] m5_data_i;
output [dw-1:0] m5_data_o;
input [aw-1:0] m5_addr_i;
input [sw-1:0] m5_sel_i;
input m5_we_i;
input m5_cyc_i;
input m5_stb_i;
output m5_ack_o;
output m5_err_o;
output m5_rty_o;
// Master 6 Interface
input [dw-1:0] m6_data_i;
output [dw-1:0] m6_data_o;
input [aw-1:0] m6_addr_i;
input [sw-1:0] m6_sel_i;
input m6_we_i;
input m6_cyc_i;
input m6_stb_i;
output m6_ack_o;
output m6_err_o;
output m6_rty_o;
// Master 7 Interface
input [dw-1:0] m7_data_i;
output [dw-1:0] m7_data_o;
input [aw-1:0] m7_addr_i;
input [sw-1:0] m7_sel_i;
input m7_we_i;
input m7_cyc_i;
input m7_stb_i;
output m7_ack_o;
output m7_err_o;
output m7_rty_o;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [aw-1:0] wb_addr_o;
reg [dw-1:0] wb_data_o;
reg [sw-1:0] wb_sel_o;
reg wb_we_o;
reg wb_cyc_o;
reg wb_stb_o;
wire [2:0] mast_sel_simple;
wire [2:0] mast_sel_pe;
wire [2:0] mast_sel;
reg next;
reg m0_cyc_r, m1_cyc_r, m2_cyc_r, m3_cyc_r;
reg m4_cyc_r, m5_cyc_r, m6_cyc_r, m7_cyc_r;
////////////////////////////////////////////////////////////////////
//
// Select logic
//
always @(posedge clk_i)
next <= #1 ~wb_cyc_o;
wb_conmax_arb arb(
.clk( clk_i ),
.rst( rst_i ),
.req( { m7_cyc_i,
m6_cyc_i,
m5_cyc_i,
m4_cyc_i,
m3_cyc_i,
m2_cyc_i,
m1_cyc_i,
m0_cyc_i } ),
.gnt( mast_sel_simple ),
.next( 1'b0 )
);
wb_conmax_msel #(pri_sel) msel(
.clk_i( clk_i ),
.rst_i( rst_i ),
.conf( conf ),
.req( { m7_cyc_i,
m6_cyc_i,
m5_cyc_i,
m4_cyc_i,
m3_cyc_i,
m2_cyc_i,
m1_cyc_i,
m0_cyc_i} ),
.sel( mast_sel_pe ),
.next( next )
);
assign mast_sel = (pri_sel == 2'd0) ? mast_sel_simple : mast_sel_pe;
////////////////////////////////////////////////////////////////////
//
// Address & Data Pass
//
always @(mast_sel or m0_addr_i or m1_addr_i or m2_addr_i or m3_addr_i
or m4_addr_i or m5_addr_i or m6_addr_i or m7_addr_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_addr_o = m0_addr_i;
3'd1: wb_addr_o = m1_addr_i;
3'd2: wb_addr_o = m2_addr_i;
3'd3: wb_addr_o = m3_addr_i;
3'd4: wb_addr_o = m4_addr_i;
3'd5: wb_addr_o = m5_addr_i;
3'd6: wb_addr_o = m6_addr_i;
3'd7: wb_addr_o = m7_addr_i;
default: wb_addr_o = {aw{1'bx}};
endcase
always @(mast_sel or m0_sel_i or m1_sel_i or m2_sel_i or m3_sel_i
or m4_sel_i or m5_sel_i or m6_sel_i or m7_sel_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_sel_o = m0_sel_i;
3'd1: wb_sel_o = m1_sel_i;
3'd2: wb_sel_o = m2_sel_i;
3'd3: wb_sel_o = m3_sel_i;
3'd4: wb_sel_o = m4_sel_i;
3'd5: wb_sel_o = m5_sel_i;
3'd6: wb_sel_o = m6_sel_i;
3'd7: wb_sel_o = m7_sel_i;
default: wb_sel_o = {sw{1'bx}};
endcase
always @(mast_sel or m0_data_i or m1_data_i or m2_data_i or m3_data_i
or m4_data_i or m5_data_i or m6_data_i or m7_data_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_data_o = m0_data_i;
3'd1: wb_data_o = m1_data_i;
3'd2: wb_data_o = m2_data_i;
3'd3: wb_data_o = m3_data_i;
3'd4: wb_data_o = m4_data_i;
3'd5: wb_data_o = m5_data_i;
3'd6: wb_data_o = m6_data_i;
3'd7: wb_data_o = m7_data_i;
default: wb_data_o = {dw{1'bx}};
endcase
assign m0_data_o = wb_data_i;
assign m1_data_o = wb_data_i;
assign m2_data_o = wb_data_i;
assign m3_data_o = wb_data_i;
assign m4_data_o = wb_data_i;
assign m5_data_o = wb_data_i;
assign m6_data_o = wb_data_i;
assign m7_data_o = wb_data_i;
////////////////////////////////////////////////////////////////////
//
// Control Signal Pass
//
always @(mast_sel or m0_we_i or m1_we_i or m2_we_i or m3_we_i
or m4_we_i or m5_we_i or m6_we_i or m7_we_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_we_o = m0_we_i;
3'd1: wb_we_o = m1_we_i;
3'd2: wb_we_o = m2_we_i;
3'd3: wb_we_o = m3_we_i;
3'd4: wb_we_o = m4_we_i;
3'd5: wb_we_o = m5_we_i;
3'd6: wb_we_o = m6_we_i;
3'd7: wb_we_o = m7_we_i;
default: wb_we_o = 1'bx;
endcase
always @(posedge clk_i)
m0_cyc_r <= #1 m0_cyc_i;
always @(posedge clk_i)
m1_cyc_r <= #1 m1_cyc_i;
always @(posedge clk_i)
m2_cyc_r <= #1 m2_cyc_i;
always @(posedge clk_i)
m3_cyc_r <= #1 m3_cyc_i;
always @(posedge clk_i)
m4_cyc_r <= #1 m4_cyc_i;
always @(posedge clk_i)
m5_cyc_r <= #1 m5_cyc_i;
always @(posedge clk_i)
m6_cyc_r <= #1 m6_cyc_i;
always @(posedge clk_i)
m7_cyc_r <= #1 m7_cyc_i;
always @(mast_sel or m0_cyc_i or m1_cyc_i or m2_cyc_i or m3_cyc_i
or m4_cyc_i or m5_cyc_i or m6_cyc_i or m7_cyc_i
or m0_cyc_r or m1_cyc_r or m2_cyc_r or m3_cyc_r
or m4_cyc_r or m5_cyc_r or m6_cyc_r or m7_cyc_r)
case(mast_sel) // synopsys parallel_case
3'd0: wb_cyc_o = m0_cyc_i & m0_cyc_r;
3'd1: wb_cyc_o = m1_cyc_i & m1_cyc_r;
3'd2: wb_cyc_o = m2_cyc_i & m2_cyc_r;
3'd3: wb_cyc_o = m3_cyc_i & m3_cyc_r;
3'd4: wb_cyc_o = m4_cyc_i & m4_cyc_r;
3'd5: wb_cyc_o = m5_cyc_i & m5_cyc_r;
3'd6: wb_cyc_o = m6_cyc_i & m6_cyc_r;
3'd7: wb_cyc_o = m7_cyc_i & m7_cyc_r;
default: wb_cyc_o = 1'b0;
endcase
always @(mast_sel or m0_stb_i or m1_stb_i or m2_stb_i or m3_stb_i
or m4_stb_i or m5_stb_i or m6_stb_i or m7_stb_i)
case(mast_sel) // synopsys parallel_case
3'd0: wb_stb_o = m0_stb_i;
3'd1: wb_stb_o = m1_stb_i;
3'd2: wb_stb_o = m2_stb_i;
3'd3: wb_stb_o = m3_stb_i;
3'd4: wb_stb_o = m4_stb_i;
3'd5: wb_stb_o = m5_stb_i;
3'd6: wb_stb_o = m6_stb_i;
3'd7: wb_stb_o = m7_stb_i;
default: wb_stb_o = 1'b0;
endcase
assign m0_ack_o = (mast_sel==3'd0) & wb_ack_i;
assign m1_ack_o = (mast_sel==3'd1) & wb_ack_i;
assign m2_ack_o = (mast_sel==3'd2) & wb_ack_i;
assign m3_ack_o = (mast_sel==3'd3) & wb_ack_i;
assign m4_ack_o = (mast_sel==3'd4) & wb_ack_i;
assign m5_ack_o = (mast_sel==3'd5) & wb_ack_i;
assign m6_ack_o = (mast_sel==3'd6) & wb_ack_i;
assign m7_ack_o = (mast_sel==3'd7) & wb_ack_i;
assign m0_err_o = (mast_sel==3'd0) & wb_err_i;
assign m1_err_o = (mast_sel==3'd1) & wb_err_i;
assign m2_err_o = (mast_sel==3'd2) & wb_err_i;
assign m3_err_o = (mast_sel==3'd3) & wb_err_i;
assign m4_err_o = (mast_sel==3'd4) & wb_err_i;
assign m5_err_o = (mast_sel==3'd5) & wb_err_i;
assign m6_err_o = (mast_sel==3'd6) & wb_err_i;
assign m7_err_o = (mast_sel==3'd7) & wb_err_i;
assign m0_rty_o = (mast_sel==3'd0) & wb_rty_i;
assign m1_rty_o = (mast_sel==3'd1) & wb_rty_i;
assign m2_rty_o = (mast_sel==3'd2) & wb_rty_i;
assign m3_rty_o = (mast_sel==3'd3) & wb_rty_i;
assign m4_rty_o = (mast_sel==3'd4) & wb_rty_i;
assign m5_rty_o = (mast_sel==3'd5) & wb_rty_i;
assign m6_rty_o = (mast_sel==3'd6) & wb_rty_i;
assign m7_rty_o = (mast_sel==3'd7) & wb_rty_i;
endmodule |
module wb_conmax_arb(clk, rst, req, gnt, next);
input clk;
input rst;
input [7:0] req; // Req input
output [2:0] gnt; // Grant output
input next; // Next Target
///////////////////////////////////////////////////////////////////////
//
// Parameters
//
parameter [2:0]
grant0 = 3'h0,
grant1 = 3'h1,
grant2 = 3'h2,
grant3 = 3'h3,
grant4 = 3'h4,
grant5 = 3'h5,
grant6 = 3'h6,
grant7 = 3'h7;
///////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
reg [2:0] state, next_state;
///////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign gnt = state;
always@(posedge clk or posedge rst)
if(rst) state <= #1 grant0;
else state <= #1 next_state;
///////////////////////////////////////////////////////////////////////
//
// Next State Logic
// - implements round robin arbitration algorithm
// - switches grant if current req is dropped or next is asserted
// - parks at last grant
//
always@(state or req or next)
begin
next_state = state; // Default Keep State
case(state) // synopsys parallel_case full_case
grant0:
// if this req is dropped or next is asserted, check for other req's
if(!req[0] | next)
begin
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
end
grant1:
// if this req is dropped or next is asserted, check for other req's
if(!req[1] | next)
begin
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
end
grant2:
// if this req is dropped or next is asserted, check for other req's
if(!req[2] | next)
begin
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
end
grant3:
// if this req is dropped or next is asserted, check for other req's
if(!req[3] | next)
begin
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
end
grant4:
// if this req is dropped or next is asserted, check for other req's
if(!req[4] | next)
begin
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
end
grant5:
// if this req is dropped or next is asserted, check for other req's
if(!req[5] | next)
begin
if(req[6]) next_state = grant6;
else
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
end
grant6:
// if this req is dropped or next is asserted, check for other req's
if(!req[6] | next)
begin
if(req[7]) next_state = grant7;
else
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
end
grant7:
// if this req is dropped or next is asserted, check for other req's
if(!req[7] | next)
begin
if(req[0]) next_state = grant0;
else
if(req[1]) next_state = grant1;
else
if(req[2]) next_state = grant2;
else
if(req[3]) next_state = grant3;
else
if(req[4]) next_state = grant4;
else
if(req[5]) next_state = grant5;
else
if(req[6]) next_state = grant6;
end
endcase
end
endmodule |
module wb_conmax_pri_enc(
valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri_out
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter [1:0] pri_sel = 2'd0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input [7:0] valid;
input [1:0] pri0, pri1, pri2, pri3;
input [1:0] pri4, pri5, pri6, pri7;
output [1:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire [3:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [3:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [3:0] pri_out_tmp;
reg [1:0] pri_out0, pri_out1;
wire [1:0] pri_out;
////////////////////////////////////////////////////////////////////
//
// Priority Decoders
//
wb_conmax_pri_dec #(pri_sel) pd0(
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_conmax_pri_dec #(pri_sel) pd1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_conmax_pri_dec #(pri_sel) pd2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_conmax_pri_dec #(pri_sel) pd3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_conmax_pri_dec #(pri_sel) pd4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_conmax_pri_dec #(pri_sel) pd5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_conmax_pri_dec #(pri_sel) pd6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_conmax_pri_dec #(pri_sel) pd7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
////////////////////////////////////////////////////////////////////
//
// Priority Encoding
//
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out;
// 4 Priority Levels
always @(pri_out_tmp)
if(pri_out_tmp[3]) pri_out1 = 2'h3;
else
if(pri_out_tmp[2]) pri_out1 = 2'h2;
else
if(pri_out_tmp[1]) pri_out1 = 2'h1;
else pri_out1 = 2'h0;
// 2 Priority Levels
always @(pri_out_tmp)
if(pri_out_tmp[1]) pri_out0 = 2'h1;
else pri_out0 = 2'h0;
////////////////////////////////////////////////////////////////////
//
// Final Priority Output
//
// Select configured priority
assign pri_out = (pri_sel==2'd0) ? 2'h0 : ( (pri_sel==2'd1) ? pri_out0 : pri_out1 );
endmodule |
module wb_conmax_master_if(
clk_i, rst_i,
// Master interface
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
// Slave 0 Interface
s0_data_i, s0_data_o, s0_addr_o, s0_sel_o, s0_we_o, s0_cyc_o,
s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i,
// Slave 1 Interface
s1_data_i, s1_data_o, s1_addr_o, s1_sel_o, s1_we_o, s1_cyc_o,
s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i,
// Slave 2 Interface
s2_data_i, s2_data_o, s2_addr_o, s2_sel_o, s2_we_o, s2_cyc_o,
s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i,
// Slave 3 Interface
s3_data_i, s3_data_o, s3_addr_o, s3_sel_o, s3_we_o, s3_cyc_o,
s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i,
// Slave 4 Interface
s4_data_i, s4_data_o, s4_addr_o, s4_sel_o, s4_we_o, s4_cyc_o,
s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i,
// Slave 5 Interface
s5_data_i, s5_data_o, s5_addr_o, s5_sel_o, s5_we_o, s5_cyc_o,
s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i,
// Slave 6 Interface
s6_data_i, s6_data_o, s6_addr_o, s6_sel_o, s6_we_o, s6_cyc_o,
s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i,
// Slave 7 Interface
s7_data_i, s7_data_o, s7_addr_o, s7_sel_o, s7_we_o, s7_cyc_o,
s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i,
// Slave 8 Interface
s8_data_i, s8_data_o, s8_addr_o, s8_sel_o, s8_we_o, s8_cyc_o,
s8_stb_o, s8_ack_i, s8_err_i, s8_rty_i,
// Slave 9 Interface
s9_data_i, s9_data_o, s9_addr_o, s9_sel_o, s9_we_o, s9_cyc_o,
s9_stb_o, s9_ack_i, s9_err_i, s9_rty_i,
// Slave 10 Interface
s10_data_i, s10_data_o, s10_addr_o, s10_sel_o, s10_we_o, s10_cyc_o,
s10_stb_o, s10_ack_i, s10_err_i, s10_rty_i,
// Slave 11 Interface
s11_data_i, s11_data_o, s11_addr_o, s11_sel_o, s11_we_o, s11_cyc_o,
s11_stb_o, s11_ack_i, s11_err_i, s11_rty_i,
// Slave 12 Interface
s12_data_i, s12_data_o, s12_addr_o, s12_sel_o, s12_we_o, s12_cyc_o,
s12_stb_o, s12_ack_i, s12_err_i, s12_rty_i,
// Slave 13 Interface
s13_data_i, s13_data_o, s13_addr_o, s13_sel_o, s13_we_o, s13_cyc_o,
s13_stb_o, s13_ack_i, s13_err_i, s13_rty_i,
// Slave 14 Interface
s14_data_i, s14_data_o, s14_addr_o, s14_sel_o, s14_we_o, s14_cyc_o,
s14_stb_o, s14_ack_i, s14_err_i, s14_rty_i,
// Slave 15 Interface
s15_data_i, s15_data_o, s15_addr_o, s15_sel_o, s15_we_o, s15_cyc_o,
s15_stb_o, s15_ack_i, s15_err_i, s15_rty_i
);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
parameter dw = 32; // Data bus Width
parameter aw = 32; // Address bus Width
parameter sw = dw / 8; // Number of Select Lines
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk_i, rst_i;
// Master Interface
input [dw-1:0] wb_data_i;
output [dw-1:0] wb_data_o;
input [aw-1:0] wb_addr_i;
input [sw-1:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Slave 0 Interface
input [dw-1:0] s0_data_i;
output [dw-1:0] s0_data_o;
output [aw-1:0] s0_addr_o;
output [sw-1:0] s0_sel_o;
output s0_we_o;
output s0_cyc_o;
output s0_stb_o;
input s0_ack_i;
input s0_err_i;
input s0_rty_i;
// Slave 1 Interface
input [dw-1:0] s1_data_i;
output [dw-1:0] s1_data_o;
output [aw-1:0] s1_addr_o;
output [sw-1:0] s1_sel_o;
output s1_we_o;
output s1_cyc_o;
output s1_stb_o;
input s1_ack_i;
input s1_err_i;
input s1_rty_i;
// Slave 2 Interface
input [dw-1:0] s2_data_i;
output [dw-1:0] s2_data_o;
output [aw-1:0] s2_addr_o;
output [sw-1:0] s2_sel_o;
output s2_we_o;
output s2_cyc_o;
output s2_stb_o;
input s2_ack_i;
input s2_err_i;
input s2_rty_i;
// Slave 3 Interface
input [dw-1:0] s3_data_i;
output [dw-1:0] s3_data_o;
output [aw-1:0] s3_addr_o;
output [sw-1:0] s3_sel_o;
output s3_we_o;
output s3_cyc_o;
output s3_stb_o;
input s3_ack_i;
input s3_err_i;
input s3_rty_i;
// Slave 4 Interface
input [dw-1:0] s4_data_i;
output [dw-1:0] s4_data_o;
output [aw-1:0] s4_addr_o;
output [sw-1:0] s4_sel_o;
output s4_we_o;
output s4_cyc_o;
output s4_stb_o;
input s4_ack_i;
input s4_err_i;
input s4_rty_i;
// Slave 5 Interface
input [dw-1:0] s5_data_i;
output [dw-1:0] s5_data_o;
output [aw-1:0] s5_addr_o;
output [sw-1:0] s5_sel_o;
output s5_we_o;
output s5_cyc_o;
output s5_stb_o;
input s5_ack_i;
input s5_err_i;
input s5_rty_i;
// Slave 6 Interface
input [dw-1:0] s6_data_i;
output [dw-1:0] s6_data_o;
output [aw-1:0] s6_addr_o;
output [sw-1:0] s6_sel_o;
output s6_we_o;
output s6_cyc_o;
output s6_stb_o;
input s6_ack_i;
input s6_err_i;
input s6_rty_i;
// Slave 7 Interface
input [dw-1:0] s7_data_i;
output [dw-1:0] s7_data_o;
output [aw-1:0] s7_addr_o;
output [sw-1:0] s7_sel_o;
output s7_we_o;
output s7_cyc_o;
output s7_stb_o;
input s7_ack_i;
input s7_err_i;
input s7_rty_i;
// Slave 8 Interface
input [dw-1:0] s8_data_i;
output [dw-1:0] s8_data_o;
output [aw-1:0] s8_addr_o;
output [sw-1:0] s8_sel_o;
output s8_we_o;
output s8_cyc_o;
output s8_stb_o;
input s8_ack_i;
input s8_err_i;
input s8_rty_i;
// Slave 9 Interface
input [dw-1:0] s9_data_i;
output [dw-1:0] s9_data_o;
output [aw-1:0] s9_addr_o;
output [sw-1:0] s9_sel_o;
output s9_we_o;
output s9_cyc_o;
output s9_stb_o;
input s9_ack_i;
input s9_err_i;
input s9_rty_i;
// Slave 10 Interface
input [dw-1:0] s10_data_i;
output [dw-1:0] s10_data_o;
output [aw-1:0] s10_addr_o;
output [sw-1:0] s10_sel_o;
output s10_we_o;
output s10_cyc_o;
output s10_stb_o;
input s10_ack_i;
input s10_err_i;
input s10_rty_i;
// Slave 11 Interface
input [dw-1:0] s11_data_i;
output [dw-1:0] s11_data_o;
output [aw-1:0] s11_addr_o;
output [sw-1:0] s11_sel_o;
output s11_we_o;
output s11_cyc_o;
output s11_stb_o;
input s11_ack_i;
input s11_err_i;
input s11_rty_i;
// Slave 12 Interface
input [dw-1:0] s12_data_i;
output [dw-1:0] s12_data_o;
output [aw-1:0] s12_addr_o;
output [sw-1:0] s12_sel_o;
output s12_we_o;
output s12_cyc_o;
output s12_stb_o;
input s12_ack_i;
input s12_err_i;
input s12_rty_i;
// Slave 13 Interface
input [dw-1:0] s13_data_i;
output [dw-1:0] s13_data_o;
output [aw-1:0] s13_addr_o;
output [sw-1:0] s13_sel_o;
output s13_we_o;
output s13_cyc_o;
output s13_stb_o;
input s13_ack_i;
input s13_err_i;
input s13_rty_i;
// Slave 14 Interface
input [dw-1:0] s14_data_i;
output [dw-1:0] s14_data_o;
output [aw-1:0] s14_addr_o;
output [sw-1:0] s14_sel_o;
output s14_we_o;
output s14_cyc_o;
output s14_stb_o;
input s14_ack_i;
input s14_err_i;
input s14_rty_i;
// Slave 15 Interface
input [dw-1:0] s15_data_i;
output [dw-1:0] s15_data_o;
output [aw-1:0] s15_addr_o;
output [sw-1:0] s15_sel_o;
output s15_we_o;
output s15_cyc_o;
output s15_stb_o;
input s15_ack_i;
input s15_err_i;
input s15_rty_i;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [dw-1:0] wb_data_o;
reg wb_ack_o;
reg wb_err_o;
reg wb_rty_o;
wire [3:0] slv_sel;
wire s0_cyc_o_next, s1_cyc_o_next, s2_cyc_o_next, s3_cyc_o_next;
wire s4_cyc_o_next, s5_cyc_o_next, s6_cyc_o_next, s7_cyc_o_next;
wire s8_cyc_o_next, s9_cyc_o_next, s10_cyc_o_next, s11_cyc_o_next;
wire s12_cyc_o_next, s13_cyc_o_next, s14_cyc_o_next, s15_cyc_o_next;
reg s0_cyc_o, s1_cyc_o, s2_cyc_o, s3_cyc_o;
reg s4_cyc_o, s5_cyc_o, s6_cyc_o, s7_cyc_o;
reg s8_cyc_o, s9_cyc_o, s10_cyc_o, s11_cyc_o;
reg s12_cyc_o, s13_cyc_o, s14_cyc_o, s15_cyc_o;
////////////////////////////////////////////////////////////////////
//
// Select logic
//
assign slv_sel = wb_addr_i[aw-1:aw-4];
////////////////////////////////////////////////////////////////////
//
// Address & Data Pass
//
assign s0_addr_o = wb_addr_i;
assign s1_addr_o = wb_addr_i;
assign s2_addr_o = wb_addr_i;
assign s3_addr_o = wb_addr_i;
assign s4_addr_o = wb_addr_i;
assign s5_addr_o = wb_addr_i;
assign s6_addr_o = wb_addr_i;
assign s7_addr_o = wb_addr_i;
assign s8_addr_o = wb_addr_i;
assign s9_addr_o = wb_addr_i;
assign s10_addr_o = wb_addr_i;
assign s11_addr_o = wb_addr_i;
assign s12_addr_o = wb_addr_i;
assign s13_addr_o = wb_addr_i;
assign s14_addr_o = wb_addr_i;
assign s15_addr_o = wb_addr_i;
assign s0_sel_o = wb_sel_i;
assign s1_sel_o = wb_sel_i;
assign s2_sel_o = wb_sel_i;
assign s3_sel_o = wb_sel_i;
assign s4_sel_o = wb_sel_i;
assign s5_sel_o = wb_sel_i;
assign s6_sel_o = wb_sel_i;
assign s7_sel_o = wb_sel_i;
assign s8_sel_o = wb_sel_i;
assign s9_sel_o = wb_sel_i;
assign s10_sel_o = wb_sel_i;
assign s11_sel_o = wb_sel_i;
assign s12_sel_o = wb_sel_i;
assign s13_sel_o = wb_sel_i;
assign s14_sel_o = wb_sel_i;
assign s15_sel_o = wb_sel_i;
assign s0_data_o = wb_data_i;
assign s1_data_o = wb_data_i;
assign s2_data_o = wb_data_i;
assign s3_data_o = wb_data_i;
assign s4_data_o = wb_data_i;
assign s5_data_o = wb_data_i;
assign s6_data_o = wb_data_i;
assign s7_data_o = wb_data_i;
assign s8_data_o = wb_data_i;
assign s9_data_o = wb_data_i;
assign s10_data_o = wb_data_i;
assign s11_data_o = wb_data_i;
assign s12_data_o = wb_data_i;
assign s13_data_o = wb_data_i;
assign s14_data_o = wb_data_i;
assign s15_data_o = wb_data_i;
always @(slv_sel or s0_data_i or s1_data_i or s2_data_i or s3_data_i or
s4_data_i or s5_data_i or s6_data_i or s7_data_i or s8_data_i or
s9_data_i or s10_data_i or s11_data_i or s12_data_i or
s13_data_i or s14_data_i or s15_data_i)
case(slv_sel) // synopsys parallel_case
4'd0: wb_data_o = s0_data_i;
4'd1: wb_data_o = s1_data_i;
4'd2: wb_data_o = s2_data_i;
4'd3: wb_data_o = s3_data_i;
4'd4: wb_data_o = s4_data_i;
4'd5: wb_data_o = s5_data_i;
4'd6: wb_data_o = s6_data_i;
4'd7: wb_data_o = s7_data_i;
4'd8: wb_data_o = s8_data_i;
4'd9: wb_data_o = s9_data_i;
4'd10: wb_data_o = s10_data_i;
4'd11: wb_data_o = s11_data_i;
4'd12: wb_data_o = s12_data_i;
4'd13: wb_data_o = s13_data_i;
4'd14: wb_data_o = s14_data_i;
4'd15: wb_data_o = s15_data_i;
default: wb_data_o = {dw{1'bx}};
endcase
////////////////////////////////////////////////////////////////////
//
// Control Signal Pass
//
assign s0_we_o = wb_we_i;
assign s1_we_o = wb_we_i;
assign s2_we_o = wb_we_i;
assign s3_we_o = wb_we_i;
assign s4_we_o = wb_we_i;
assign s5_we_o = wb_we_i;
assign s6_we_o = wb_we_i;
assign s7_we_o = wb_we_i;
assign s8_we_o = wb_we_i;
assign s9_we_o = wb_we_i;
assign s10_we_o = wb_we_i;
assign s11_we_o = wb_we_i;
assign s12_we_o = wb_we_i;
assign s13_we_o = wb_we_i;
assign s14_we_o = wb_we_i;
assign s15_we_o = wb_we_i;
assign s0_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s0_cyc_o : ((slv_sel==4'd0) ? wb_cyc_i : 1'b0);
assign s1_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s1_cyc_o : ((slv_sel==4'd1) ? wb_cyc_i : 1'b0);
assign s2_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s2_cyc_o : ((slv_sel==4'd2) ? wb_cyc_i : 1'b0);
assign s3_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s3_cyc_o : ((slv_sel==4'd3) ? wb_cyc_i : 1'b0);
assign s4_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s4_cyc_o : ((slv_sel==4'd4) ? wb_cyc_i : 1'b0);
assign s5_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s5_cyc_o : ((slv_sel==4'd5) ? wb_cyc_i : 1'b0);
assign s6_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s6_cyc_o : ((slv_sel==4'd6) ? wb_cyc_i : 1'b0);
assign s7_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s7_cyc_o : ((slv_sel==4'd7) ? wb_cyc_i : 1'b0);
assign s8_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s8_cyc_o : ((slv_sel==4'd8) ? wb_cyc_i : 1'b0);
assign s9_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s9_cyc_o : ((slv_sel==4'd9) ? wb_cyc_i : 1'b0);
assign s10_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s10_cyc_o : ((slv_sel==4'd10) ? wb_cyc_i : 1'b0);
assign s11_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s11_cyc_o : ((slv_sel==4'd11) ? wb_cyc_i : 1'b0);
assign s12_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s12_cyc_o : ((slv_sel==4'd12) ? wb_cyc_i : 1'b0);
assign s13_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s13_cyc_o : ((slv_sel==4'd13) ? wb_cyc_i : 1'b0);
assign s14_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s14_cyc_o : ((slv_sel==4'd14) ? wb_cyc_i : 1'b0);
assign s15_cyc_o_next = (wb_cyc_i & !wb_stb_i) ? s15_cyc_o : ((slv_sel==4'd15) ? wb_cyc_i : 1'b0);
always @(posedge clk_i or posedge rst_i)
if(rst_i) s0_cyc_o <= #1 1'b0;
else s0_cyc_o <= #1 s0_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s1_cyc_o <= #1 1'b0;
else s1_cyc_o <= #1 s1_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s2_cyc_o <= #1 1'b0;
else s2_cyc_o <= #1 s2_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s3_cyc_o <= #1 1'b0;
else s3_cyc_o <= #1 s3_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s4_cyc_o <= #1 1'b0;
else s4_cyc_o <= #1 s4_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s5_cyc_o <= #1 1'b0;
else s5_cyc_o <= #1 s5_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s6_cyc_o <= #1 1'b0;
else s6_cyc_o <= #1 s6_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s7_cyc_o <= #1 1'b0;
else s7_cyc_o <= #1 s7_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s8_cyc_o <= #1 1'b0;
else s8_cyc_o <= #1 s8_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s9_cyc_o <= #1 1'b0;
else s9_cyc_o <= #1 s9_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s10_cyc_o <= #1 1'b0;
else s10_cyc_o <= #1 s10_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s11_cyc_o <= #1 1'b0;
else s11_cyc_o <= #1 s11_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s12_cyc_o <= #1 1'b0;
else s12_cyc_o <= #1 s12_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s13_cyc_o <= #1 1'b0;
else s13_cyc_o <= #1 s13_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s14_cyc_o <= #1 1'b0;
else s14_cyc_o <= #1 s14_cyc_o_next;
always @(posedge clk_i or posedge rst_i)
if(rst_i) s15_cyc_o <= #1 1'b0;
else s15_cyc_o <= #1 s15_cyc_o_next;
assign s0_stb_o = (slv_sel==4'd0) ? wb_stb_i : 1'b0;
assign s1_stb_o = (slv_sel==4'd1) ? wb_stb_i : 1'b0;
assign s2_stb_o = (slv_sel==4'd2) ? wb_stb_i : 1'b0;
assign s3_stb_o = (slv_sel==4'd3) ? wb_stb_i : 1'b0;
assign s4_stb_o = (slv_sel==4'd4) ? wb_stb_i : 1'b0;
assign s5_stb_o = (slv_sel==4'd5) ? wb_stb_i : 1'b0;
assign s6_stb_o = (slv_sel==4'd6) ? wb_stb_i : 1'b0;
assign s7_stb_o = (slv_sel==4'd7) ? wb_stb_i : 1'b0;
assign s8_stb_o = (slv_sel==4'd8) ? wb_stb_i : 1'b0;
assign s9_stb_o = (slv_sel==4'd9) ? wb_stb_i : 1'b0;
assign s10_stb_o = (slv_sel==4'd10) ? wb_stb_i : 1'b0;
assign s11_stb_o = (slv_sel==4'd11) ? wb_stb_i : 1'b0;
assign s12_stb_o = (slv_sel==4'd12) ? wb_stb_i : 1'b0;
assign s13_stb_o = (slv_sel==4'd13) ? wb_stb_i : 1'b0;
assign s14_stb_o = (slv_sel==4'd14) ? wb_stb_i : 1'b0;
assign s15_stb_o = (slv_sel==4'd15) ? wb_stb_i : 1'b0;
always @(slv_sel or s0_ack_i or s1_ack_i or s2_ack_i or s3_ack_i or
s4_ack_i or s5_ack_i or s6_ack_i or s7_ack_i or s8_ack_i or
s9_ack_i or s10_ack_i or s11_ack_i or s12_ack_i or
s13_ack_i or s14_ack_i or s15_ack_i)
case(slv_sel) // synopsys parallel_case
4'd0: wb_ack_o = s0_ack_i;
4'd1: wb_ack_o = s1_ack_i;
4'd2: wb_ack_o = s2_ack_i;
4'd3: wb_ack_o = s3_ack_i;
4'd4: wb_ack_o = s4_ack_i;
4'd5: wb_ack_o = s5_ack_i;
4'd6: wb_ack_o = s6_ack_i;
4'd7: wb_ack_o = s7_ack_i;
4'd8: wb_ack_o = s8_ack_i;
4'd9: wb_ack_o = s9_ack_i;
4'd10: wb_ack_o = s10_ack_i;
4'd11: wb_ack_o = s11_ack_i;
4'd12: wb_ack_o = s12_ack_i;
4'd13: wb_ack_o = s13_ack_i;
4'd14: wb_ack_o = s14_ack_i;
4'd15: wb_ack_o = s15_ack_i;
default: wb_ack_o = 1'b0;
endcase
always @(slv_sel or s0_err_i or s1_err_i or s2_err_i or s3_err_i or
s4_err_i or s5_err_i or s6_err_i or s7_err_i or s8_err_i or
s9_err_i or s10_err_i or s11_err_i or s12_err_i or
s13_err_i or s14_err_i or s15_err_i)
case(slv_sel) // synopsys parallel_case
4'd0: wb_err_o = s0_err_i;
4'd1: wb_err_o = s1_err_i;
4'd2: wb_err_o = s2_err_i;
4'd3: wb_err_o = s3_err_i;
4'd4: wb_err_o = s4_err_i;
4'd5: wb_err_o = s5_err_i;
4'd6: wb_err_o = s6_err_i;
4'd7: wb_err_o = s7_err_i;
4'd8: wb_err_o = s8_err_i;
4'd9: wb_err_o = s9_err_i;
4'd10: wb_err_o = s10_err_i;
4'd11: wb_err_o = s11_err_i;
4'd12: wb_err_o = s12_err_i;
4'd13: wb_err_o = s13_err_i;
4'd14: wb_err_o = s14_err_i;
4'd15: wb_err_o = s15_err_i;
default: wb_err_o = 1'b0;
endcase
always @(slv_sel or s0_rty_i or s1_rty_i or s2_rty_i or s3_rty_i or
s4_rty_i or s5_rty_i or s6_rty_i or s7_rty_i or s8_rty_i or
s9_rty_i or s10_rty_i or s11_rty_i or s12_rty_i or
s13_rty_i or s14_rty_i or s15_rty_i)
case(slv_sel) // synopsys parallel_case
4'd0: wb_rty_o = s0_rty_i;
4'd1: wb_rty_o = s1_rty_i;
4'd2: wb_rty_o = s2_rty_i;
4'd3: wb_rty_o = s3_rty_i;
4'd4: wb_rty_o = s4_rty_i;
4'd5: wb_rty_o = s5_rty_i;
4'd6: wb_rty_o = s6_rty_i;
4'd7: wb_rty_o = s7_rty_i;
4'd8: wb_rty_o = s8_rty_i;
4'd9: wb_rty_o = s9_rty_i;
4'd10: wb_rty_o = s10_rty_i;
4'd11: wb_rty_o = s11_rty_i;
4'd12: wb_rty_o = s12_rty_i;
4'd13: wb_rty_o = s13_rty_i;
4'd14: wb_rty_o = s14_rty_i;
4'd15: wb_rty_o = s15_rty_i;
default: wb_rty_o = 1'b0;
endcase
endmodule |
module spi_shift (clk, rst, latch, byte_sel, len, lsb, go,
pos_edge, neg_edge, rx_negedge, tx_negedge,
tip, last,
p_in, p_out, s_clk, s_in, s_out);
parameter Tp = 1;
input clk; // system clock
input rst; // reset
input [3:0] latch; // latch signal for storing the data in shift register
input [3:0] byte_sel; // byte select signals for storing the data in shift register
input [`SPI_CHAR_LEN_BITS-1:0] len; // data len in bits (minus one)
input lsb; // lbs first on the line
input go; // start stansfer
input pos_edge; // recognize posedge of sclk
input neg_edge; // recognize negedge of sclk
input rx_negedge; // s_in is sampled on negative edge
input tx_negedge; // s_out is driven on negative edge
output tip; // transfer in progress
output last; // last bit
input [31:0] p_in; // parallel in
output [`SPI_MAX_CHAR-1:0] p_out; // parallel out
input s_clk; // serial clock
input s_in; // serial in
output s_out; // serial out
reg s_out;
reg tip;
reg [`SPI_CHAR_LEN_BITS:0] cnt; // data bit count
reg [`SPI_MAX_CHAR-1:0] data; // shift register
wire [`SPI_CHAR_LEN_BITS:0] tx_bit_pos; // next bit position
wire [`SPI_CHAR_LEN_BITS:0] rx_bit_pos; // next bit position
wire rx_clk; // rx clock enable
wire tx_clk; // tx clock enable
assign p_out = data;
assign tx_bit_pos = lsb ? {!(|len), len} - cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1};
assign rx_bit_pos = lsb ? {!(|len), len} - (rx_negedge ? cnt + {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1} : cnt) :
(rx_negedge ? cnt : cnt - {{`SPI_CHAR_LEN_BITS{1'b0}},1'b1});
assign last = !(|cnt);
assign rx_clk = (rx_negedge ? neg_edge : pos_edge) && (!last || s_clk);
assign tx_clk = (tx_negedge ? neg_edge : pos_edge) && !last;
// Character bit counter
always @(posedge clk or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_CHAR_LEN_BITS+1{1'b0}};
else
begin
if(tip)
cnt <= #Tp pos_edge ? (cnt - {{`SPI_CHAR_LEN_BITS{1'b0}}, 1'b1}) : cnt;
else
cnt <= #Tp !(|len) ? {1'b1, {`SPI_CHAR_LEN_BITS{1'b0}}} : {1'b0, len};
end
end
// Transfer in progress
always @(posedge clk or posedge rst)
begin
if(rst)
tip <= #Tp 1'b0;
else if(go && ~tip)
tip <= #Tp 1'b1;
else if(tip && last && pos_edge)
tip <= #Tp 1'b0;
end
// Sending bits to the line
always @(posedge clk or posedge rst)
begin
if (rst)
s_out <= #Tp 1'b0;
else
s_out <= #Tp (tx_clk || !tip) ? data[tx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] : s_out;
end
// Receiving bits from the line
always @(posedge clk or posedge rst)
begin
if (rst)
data <= #Tp {`SPI_MAX_CHAR{1'b0}};
`ifdef SPI_MAX_CHAR_128
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
else if (latch[2] && !tip)
begin
if (byte_sel[3])
data[95:88] <= #Tp p_in[31:24];
if (byte_sel[2])
data[87:80] <= #Tp p_in[23:16];
if (byte_sel[1])
data[79:72] <= #Tp p_in[15:8];
if (byte_sel[0])
data[71:64] <= #Tp p_in[7:0];
end
else if (latch[3] && !tip)
begin
if (byte_sel[3])
data[127:120] <= #Tp p_in[31:24];
if (byte_sel[2])
data[119:112] <= #Tp p_in[23:16];
if (byte_sel[1])
data[111:104] <= #Tp p_in[15:8];
if (byte_sel[0])
data[103:96] <= #Tp p_in[7:0];
end
`else
`ifdef SPI_MAX_CHAR_64
else if (latch[0] && !tip)
begin
if (byte_sel[3])
data[31:24] <= #Tp p_in[31:24];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
end
else if (latch[1] && !tip)
begin
if (byte_sel[3])
data[63:56] <= #Tp p_in[31:24];
if (byte_sel[2])
data[55:48] <= #Tp p_in[23:16];
if (byte_sel[1])
data[47:40] <= #Tp p_in[15:8];
if (byte_sel[0])
data[39:32] <= #Tp p_in[7:0];
end
`else
else if (latch[0] && !tip)
begin
`ifdef SPI_MAX_CHAR_8
if (byte_sel[0])
data[`SPI_MAX_CHAR-1:0] <= #Tp p_in[`SPI_MAX_CHAR-1:0];
`endif
`ifdef SPI_MAX_CHAR_16
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[`SPI_MAX_CHAR-1:8] <= #Tp p_in[`SPI_MAX_CHAR-1:8];
`endif
`ifdef SPI_MAX_CHAR_24
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[`SPI_MAX_CHAR-1:16] <= #Tp p_in[`SPI_MAX_CHAR-1:16];
`endif
`ifdef SPI_MAX_CHAR_32
if (byte_sel[0])
data[7:0] <= #Tp p_in[7:0];
if (byte_sel[1])
data[15:8] <= #Tp p_in[15:8];
if (byte_sel[2])
data[23:16] <= #Tp p_in[23:16];
if (byte_sel[3])
data[`SPI_MAX_CHAR-1:24] <= #Tp p_in[`SPI_MAX_CHAR-1:24];
`endif
end
`endif
`endif
else
data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]] <= #Tp rx_clk ? s_in : data[rx_bit_pos[`SPI_CHAR_LEN_BITS-1:0]];
end
endmodule |
module spi_top
(
// Wishbone signals
wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_sel_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o,
// SPI signals
ss_pad_o, sclk_pad_o, mosi_pad_o, miso_pad_i
);
parameter Tp = 1;
// Wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input [4:0] wb_adr_i; // lower address bits
input [32-1:0] wb_dat_i; // databus input
output [32-1:0] wb_dat_o; // databus output
input [3:0] wb_sel_i; // byte select inputs
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_err_o; // termination w/ error
output wb_int_o; // interrupt request signal output
// SPI signals
output [`SPI_SS_NB-1:0] ss_pad_o; // slave select
output sclk_pad_o; // serial clock
output mosi_pad_o; // master out slave in
input miso_pad_i; // master in slave out
reg [32-1:0] wb_dat_o;
reg wb_ack_o;
reg wb_int_o;
// Internal signals
reg [`SPI_DIVIDER_LEN-1:0] divider; // Divider register
reg [`SPI_CTRL_BIT_NB-1:0] ctrl; // Control and status register
reg [`SPI_SS_NB-1:0] ss; // Slave select register
reg [32-1:0] wb_dat; // wb data out
wire [`SPI_MAX_CHAR-1:0] rx; // Rx register
wire rx_negedge; // miso is sampled on negative edge
wire tx_negedge; // mosi is driven on negative edge
wire [`SPI_CHAR_LEN_BITS-1:0] char_len; // char len
wire go; // go
wire lsb; // lsb first on line
wire ie; // interrupt enable
wire ass; // automatic slave select
wire spi_divider_sel; // divider register select
wire spi_ctrl_sel; // ctrl register select
wire [3:0] spi_tx_sel; // tx_l register select
wire spi_ss_sel; // ss register select
wire tip; // transfer in progress
wire pos_edge; // recognize posedge of sclk
wire neg_edge; // recognize negedge of sclk
wire last_bit; // marks last character bit
// Address decoder
assign spi_divider_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_DEVIDE);
assign spi_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_CTRL);
assign spi_tx_sel[0] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_0);
assign spi_tx_sel[1] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_1);
assign spi_tx_sel[2] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_2);
assign spi_tx_sel[3] = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_TX_3);
assign spi_ss_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`SPI_OFS_BITS] == `SPI_SS);
// Read from registers
always @(wb_adr_i or rx or ctrl or divider or ss)
begin
case (wb_adr_i[`SPI_OFS_BITS])
`ifdef SPI_MAX_CHAR_128
`SPI_RX_0: wb_dat = rx[31:0];
`SPI_RX_1: wb_dat = rx[63:32];
`SPI_RX_2: wb_dat = rx[95:64];
`SPI_RX_3: wb_dat = {{128-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:96]};
`else
`ifdef SPI_MAX_CHAR_64
`SPI_RX_0: wb_dat = rx[31:0];
`SPI_RX_1: wb_dat = {{64-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:32]};
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`else
`SPI_RX_0: wb_dat = {{32-`SPI_MAX_CHAR{1'b0}}, rx[`SPI_MAX_CHAR-1:0]};
`SPI_RX_1: wb_dat = 32'b0;
`SPI_RX_2: wb_dat = 32'b0;
`SPI_RX_3: wb_dat = 32'b0;
`endif
`endif
`SPI_CTRL: wb_dat = {{32-`SPI_CTRL_BIT_NB{1'b0}}, ctrl};
`SPI_DEVIDE: wb_dat = {{32-`SPI_DIVIDER_LEN{1'b0}}, divider};
`SPI_SS: wb_dat = {{32-`SPI_SS_NB{1'b0}}, ss};
default: wb_dat = 32'bx;
endcase
end
// Wb data out
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_dat_o <= #Tp 32'b0;
else
wb_dat_o <= #Tp wb_dat;
end
// Wb acknowledge
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_ack_o <= #Tp 1'b0;
else
wb_ack_o <= #Tp wb_cyc_i & wb_stb_i & ~wb_ack_o;
end
// Wb error
assign wb_err_o = 1'b0;
// Interrupt
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
wb_int_o <= #Tp 1'b0;
else if (ie && tip && last_bit && pos_edge)
wb_int_o <= #Tp 1'b1;
else if (wb_ack_o)
wb_int_o <= #Tp 1'b0;
end
// Divider register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
divider <= #Tp {`SPI_DIVIDER_LEN{1'b0}};
else if (spi_divider_sel && wb_we_i && !tip)
begin
`ifdef SPI_DIVIDER_LEN_8
if (wb_sel_i[0])
divider <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:0];
`endif
`ifdef SPI_DIVIDER_LEN_16
if (wb_sel_i[0])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
divider[`SPI_DIVIDER_LEN-1:8] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:8];
`endif
`ifdef SPI_DIVIDER_LEN_24
if (wb_sel_i[0])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
divider[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[2])
divider[`SPI_DIVIDER_LEN-1:16] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:16];
`endif
`ifdef SPI_DIVIDER_LEN_32
if (wb_sel_i[0])
divider[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
divider[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[2])
divider[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[3])
divider[`SPI_DIVIDER_LEN-1:24] <= #Tp wb_dat_i[`SPI_DIVIDER_LEN-1:24];
`endif
end
end
// Ctrl register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ctrl <= #Tp {`SPI_CTRL_BIT_NB{1'b0}};
else if(spi_ctrl_sel && wb_we_i && !tip)
begin
if (wb_sel_i[0])
ctrl[7:0] <= #Tp wb_dat_i[7:0] | {7'b0, ctrl[0]};
if (wb_sel_i[1])
ctrl[`SPI_CTRL_BIT_NB-1:8] <= #Tp wb_dat_i[`SPI_CTRL_BIT_NB-1:8];
end
else if(tip && last_bit && pos_edge)
ctrl[`SPI_CTRL_GO] <= #Tp 1'b0;
end
assign rx_negedge = ctrl[`SPI_CTRL_RX_NEGEDGE];
assign tx_negedge = ctrl[`SPI_CTRL_TX_NEGEDGE];
assign go = ctrl[`SPI_CTRL_GO];
assign char_len = ctrl[`SPI_CTRL_CHAR_LEN];
assign lsb = ctrl[`SPI_CTRL_LSB];
assign ie = ctrl[`SPI_CTRL_IE];
assign ass = ctrl[`SPI_CTRL_ASS];
// Slave select register
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ss <= #Tp {`SPI_SS_NB{1'b0}};
else if(spi_ss_sel && wb_we_i && !tip)
begin
`ifdef SPI_SS_NB_8
if (wb_sel_i[0])
ss <= #Tp wb_dat_i[`SPI_SS_NB-1:0];
`endif
`ifdef SPI_SS_NB_16
if (wb_sel_i[0])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
ss[`SPI_SS_NB-1:8] <= #Tp wb_dat_i[`SPI_SS_NB-1:8];
`endif
`ifdef SPI_SS_NB_24
if (wb_sel_i[0])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
ss[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[2])
ss[`SPI_SS_NB-1:16] <= #Tp wb_dat_i[`SPI_SS_NB-1:16];
`endif
`ifdef SPI_SS_NB_32
if (wb_sel_i[0])
ss[7:0] <= #Tp wb_dat_i[7:0];
if (wb_sel_i[1])
ss[15:8] <= #Tp wb_dat_i[15:8];
if (wb_sel_i[2])
ss[23:16] <= #Tp wb_dat_i[23:16];
if (wb_sel_i[3])
ss[`SPI_SS_NB-1:24] <= #Tp wb_dat_i[`SPI_SS_NB-1:24];
`endif
end
end
assign ss_pad_o = ~((ss & {`SPI_SS_NB{tip & ass}}) | (ss & {`SPI_SS_NB{!ass}}));
spi_clgen clgen (.clk_in(wb_clk_i), .rst(wb_rst_i), .go(go), .enable(tip), .last_clk(last_bit),
.divider(divider), .clk_out(sclk_pad_o), .pos_edge(pos_edge),
.neg_edge(neg_edge));
spi_shift shift (.clk(wb_clk_i), .rst(wb_rst_i), .len(char_len[`SPI_CHAR_LEN_BITS-1:0]),
.latch(spi_tx_sel[3:0] & {4{wb_we_i}}), .byte_sel(wb_sel_i), .lsb(lsb),
.go(go), .pos_edge(pos_edge), .neg_edge(neg_edge),
.rx_negedge(rx_negedge), .tx_negedge(tx_negedge),
.tip(tip), .last(last_bit),
.p_in(wb_dat_i), .p_out(rx),
.s_clk(sclk_pad_o), .s_in(miso_pad_i), .s_out(mosi_pad_o));
endmodule |
module spi_clgen (clk_in, rst, go, enable, last_clk, divider, clk_out, pos_edge, neg_edge);
parameter Tp = 1;
input clk_in; // input clock (system clock)
input rst; // reset
input enable; // clock enable
input go; // start transfer
input last_clk; // last clock
input [`SPI_DIVIDER_LEN-1:0] divider; // clock divider (output clock is divided by this value)
output clk_out; // output clock
output pos_edge; // pulse marking positive edge of clk_out
output neg_edge; // pulse marking negative edge of clk_out
reg clk_out;
reg pos_edge;
reg neg_edge;
reg [`SPI_DIVIDER_LEN-1:0] cnt; // clock counter
wire cnt_zero; // conter is equal to zero
wire cnt_one; // conter is equal to one
assign cnt_zero = cnt == {`SPI_DIVIDER_LEN{1'b0}};
assign cnt_one = cnt == {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
// Counter counts half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
cnt <= #Tp {`SPI_DIVIDER_LEN{1'b1}};
else
begin
if(!enable || cnt_zero)
cnt <= #Tp divider;
else
cnt <= #Tp cnt - {{`SPI_DIVIDER_LEN-1{1'b0}}, 1'b1};
end
end
// clk_out is asserted every other half period
always @(posedge clk_in or posedge rst)
begin
if(rst)
clk_out <= #Tp 1'b0;
else
clk_out <= #Tp (enable && cnt_zero && (!last_clk || clk_out)) ? ~clk_out : clk_out;
end
// Pos and neg edge signals
always @(posedge clk_in or posedge rst)
begin
if(rst)
begin
pos_edge <= #Tp 1'b0;
neg_edge <= #Tp 1'b0;
end
else
begin
pos_edge <= #Tp (enable && !clk_out && cnt_one) || (!(|divider) && clk_out) || (!(|divider) && go && !enable);
neg_edge <= #Tp (enable && clk_out && cnt_one) || (!(|divider) && !clk_out && enable);
end
end
endmodule |
module vga_cur_cregs (
clk_i, rst_i, arst_i,
hsel_i, hadr_i, hwe_i, hdat_i, hdat_o, hack_o,
cadr_i, cdat_o
);
//
// inputs & outputs
//
// wishbone signals
input clk_i; // master clock input
input rst_i; // synchronous active high reset
input arst_i; // asynchronous active low reset
// host interface
input hsel_i; // host select input
input [ 2:0] hadr_i; // host address input
input hwe_i; // host write enable input
input [31:0] hdat_i; // host data in
output [31:0] hdat_o; // host data out
output hack_o; // host acknowledge out
reg [31:0] hdat_o;
reg hack_o;
// cursor processor interface
input [ 3:0] cadr_i; // cursor address in
output [15:0] cdat_o; // cursor data out
reg [15:0] cdat_o;
//
// variable declarations
//
reg [31:0] cregs [7:0]; // color registers
wire [31:0] temp_cdat;
//
// module body
//
////////////////////////////
// generate host interface
// write section
always@(posedge clk_i)
if (hsel_i & hwe_i)
cregs[hadr_i] <= #1 hdat_i;
// read section
always@(posedge clk_i)
hdat_o <= #1 cregs[hadr_i];
// acknowledge section
always@(posedge clk_i)
hack_o <= #1 hsel_i & !hack_o;
//////////////////////////////
// generate cursor interface
// read section
assign temp_cdat = cregs[cadr_i[3:1]];
always@(posedge clk_i)
cdat_o <= #1 cadr_i[0] ? temp_cdat[31:16] : temp_cdat[15:0];
endmodule |
module vga_enh_top (
wb_clk_i, wb_rst_i, rst_i, wb_inta_o,
wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_ack_o, wbs_rty_o, wbs_err_o,
wbm_adr_o, wbm_dat_i, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_ack_i, wbm_err_i,
clk_p_i,
`ifdef VGA_12BIT_DVI
dvi_pclk_p_o, dvi_pclk_m_o, dvi_hsync_o, dvi_vsync_o, dvi_de_o, dvi_d_o,
`endif
clk_p_o, hsync_pad_o, vsync_pad_o, csync_pad_o, blank_pad_o, r_pad_o, g_pad_o, b_pad_o
);
//
// parameters
//
parameter ARST_LVL = 1'b0;
parameter LINE_FIFO_AWIDTH = 7;
//
// inputs & outputs
//
// syscon interface
input wb_clk_i; // wishbone clock input
input wb_rst_i; // synchronous active high reset
input rst_i; // asynchronous reset
output wb_inta_o; // interrupt request output
// slave signals
input [11:0] wbs_adr_i; // addressbus input (only 32bit databus accesses supported)
input [31:0] wbs_dat_i; // Slave databus output
output [31:0] wbs_dat_o; // Slave databus input
input [ 3:0] wbs_sel_i; // byte select inputs
input wbs_we_i; // write enabel input
input wbs_stb_i; // strobe/select input
input wbs_cyc_i; // valid bus cycle input
output wbs_ack_o; // bus cycle acknowledge output
output wbs_rty_o; // busy cycle retry output
output wbs_err_o; // bus cycle error output
// master signals
output [31:0] wbm_adr_o; // addressbus output
input [31:0] wbm_dat_i; // Master databus input
output [ 3:0] wbm_sel_o; // byte select outputs
output wbm_we_o; // write enable output
output wbm_stb_o; // strobe output
output wbm_cyc_o; // valid bus cycle output
output [ 2:0] wbm_cti_o; // cycle type identifier
output [ 1:0] wbm_bte_o; // burst type extensions
input wbm_ack_i; // bus cycle acknowledge input
input wbm_err_i; // bus cycle error input
// VGA signals
input clk_p_i; // pixel clock
// in DVI mode this is 2x as high (!!)
`ifdef VGA_12BIT_DVI
output dvi_pclk_p_o; // dvi pclk+
output dvi_pclk_m_o; // dvi pclk-
output dvi_hsync_o; // dvi hsync
output dvi_vsync_o; // dvi vsync
output dvi_de_o; // dvi data enable
output [11:0] dvi_d_o; // dvi 12bit output
`endif
output clk_p_o; // VGA pixel clock output
output hsync_pad_o; // horizontal sync
output vsync_pad_o; // vertical sync
output csync_pad_o; // composite sync
output blank_pad_o; // blanking signal
output [ 7:0] r_pad_o, g_pad_o, b_pad_o; // RGB color signals
//
// variable declarations
//
// programable asynchronous reset
wire arst = rst_i ^ ARST_LVL;
// from wb_slave
wire ctrl_bl, ctrl_csl, ctrl_vsl, ctrl_hsl, ctrl_pc, ctrl_cbsw, ctrl_vbsw, ctrl_ven;
wire [ 1: 0] ctrl_cd, ctrl_vbl, ctrl_dvi_odf;
wire [ 7: 0] Thsync, Thgdel, Tvsync, Tvgdel;
wire [15: 0] Thgate, Thlen, Tvgate, Tvlen;
wire [31: 2] VBARa, VBARb;
wire [ 8: 0] cursor_adr;
wire [31: 0] cursor0_xy, cursor1_xy;
wire cursor0_en, cursor1_en;
wire [31:11] cursor0_ba, cursor1_ba;
wire cursor0_ld, cursor1_ld;
wire cursor0_res, cursor1_res;
wire [15: 0] cc0_dat_o, cc1_dat_o;
// to wb_slave
wire stat_avmp, stat_acmp, vmem_swint, clut_swint, hint, vint, sint;
wire wmb_busy;
reg luint;
wire [ 3: 0] cc0_adr_i, cc1_adr_i;
// pixel generator
wire fb_data_fifo_rreq, fb_data_fifo_empty;
wire [31:0] fb_data_fifo_q;
wire ImDoneFifoQ;
// line fifo connections
wire line_fifo_wreq, line_fifo_rreq, line_fifo_empty_rd;
wire [23:0] line_fifo_d, line_fifo_q;
// clut connections
wire ext_clut_req, ext_clut_ack;
wire [23:0] ext_clut_q;
wire cp_clut_req, cp_clut_ack;
wire [ 8:0] cp_clut_adr;
wire [23:0] cp_clut_q;
//
// Module body
//
// hookup wishbone slave
vga_wb_slave wbs (
// wishbone interface
.clk_i ( wb_clk_i ),
.rst_i ( wb_rst_i ),
.arst_i ( arst ),
.adr_i ( wbs_adr_i[11:2] ),
.dat_i ( wbs_dat_i ),
.dat_o ( wbs_dat_o ),
.sel_i ( wbs_sel_i ),
.we_i ( wbs_we_i ),
.stb_i ( wbs_stb_i ),
.cyc_i ( wbs_cyc_i ),
.ack_o ( wbs_ack_o ),
.rty_o ( wbs_rty_o ),
.err_o ( wbs_err_o ),
.inta_o ( wb_inta_o ),
// internal connections
.wbm_busy ( wbm_busy ), // Data transfer in progress
.dvi_odf ( ctrl_dvi_odf ), // DVI output data format
.bl ( ctrl_bl ), // blank polarization level
.csl ( ctrl_csl ), // csync polarization level
.vsl ( ctrl_vsl ), // vsync polarization level
.hsl ( ctrl_hsl ), // hsync polarization level
.pc ( ctrl_pc ), // pseudo-color mode (only for 8bpp)
.cd ( ctrl_cd ), // color depth
.vbl ( ctrl_vbl ), // video memory burst length
.cbsw ( ctrl_cbsw ), // color lookup table bank switch enable
.vbsw ( ctrl_vbsw ), // video bank switch enable
.ven ( ctrl_ven ), // video enable
.acmp ( stat_acmp ), // active color lookup table page
.avmp ( stat_avmp ), // active video memory page
.cursor0_res ( cursor0_res ), // cursor0 resolution
.cursor0_en ( cursor0_en ), // cursor0 enable
.cursor0_xy ( cursor0_xy ), // cursor0 (x,y)
.cursor0_ba ( cursor0_ba ), // curso0 video memory base address
.cursor0_ld ( cursor0_ld ), // reload curso0 from video memory
.cc0_adr_i ( cc0_adr_i ), // cursor0 color registers address
.cc0_dat_o ( cc0_dat_o ), // cursor0 color registers data
.cursor1_res ( cursor1_res ), // cursor1 resolution
.cursor1_en ( cursor1_en ), // cursor1 enable
.cursor1_xy ( cursor1_xy ), // cursor1 (x,y)
.cursor1_ba ( cursor1_ba ), // cursor1 video memory base address
.cursor1_ld ( cursor1_ld ), // reload cursor1 from video memory
.cc1_adr_i ( cc1_adr_i ), // cursor1 color registers address
.cc1_dat_o ( cc1_dat_o ), // cursor1 color registers data
.vbsint_in ( vmem_swint ), // video memory bank switch interrupt
.cbsint_in ( clut_swint ), // clut memory bank switch interrupt
.hint_in ( hint ), // horizontal interrupt
.vint_in ( vint ), // vertical interrupt
.luint_in ( luint ), // line fifo underrun interrupt
.sint_in ( sint ), // system-error interrupt
.Thsync ( Thsync ),
.Thgdel ( Thgdel ),
.Thgate ( Thgate ),
.Thlen ( Thlen ),
.Tvsync ( Tvsync ),
.Tvgdel ( Tvgdel ),
.Tvgate ( Tvgate ),
.Tvlen ( Tvlen ),
.VBARa ( VBARa ),
.VBARb ( VBARb ),
.clut_acc ( ext_clut_req ),
.clut_ack ( ext_clut_ack ),
.clut_q ( ext_clut_q )
);
// hookup wishbone master
vga_wb_master wbm (
// wishbone interface
.clk_i ( wb_clk_i ),
.rst_i ( wb_rst_i ),
.nrst_i ( arst ),
.cyc_o ( wbm_cyc_o ),
.stb_o ( wbm_stb_o ),
.cti_o ( wbm_cti_o ),
.bte_o ( wbm_bte_o ),
.we_o ( wbm_we_o ),
.adr_o ( wbm_adr_o ),
.sel_o ( wbm_sel_o ),
.ack_i ( wbm_ack_i ),
.err_i ( wbm_err_i ),
.dat_i ( wbm_dat_i ),
// internal connections
.sint (sint ),
.ctrl_ven (ctrl_ven ),
.ctrl_cd (ctrl_cd ),
.ctrl_vbl (ctrl_vbl ),
.ctrl_vbsw (ctrl_vbsw ),
.busy (wbm_busy ),
.VBAa (VBARa ),
.VBAb (VBARb ),
.Thgate (Thgate ),
.Tvgate (Tvgate ),
.stat_avmp (stat_avmp ),
.vmem_switch (vmem_swint ),
.ImDoneFifoQ ( ImDoneFifoQ ),
.cursor_adr ( cursor_adr ),
.cursor0_ba ( cursor0_ba ), // curso0 video memory base address
.cursor0_ld ( cursor0_ld ), // reload curso0 from video memory
.cursor1_ba ( cursor1_ba ), // cursor1 video memory base address
.cursor1_ld ( cursor1_ld ), // reload cursor1 from video memory
.fb_data_fifo_rreq ( fb_data_fifo_rreq ),
.fb_data_fifo_q ( fb_data_fifo_q ),
.fb_data_fifo_empty ( fb_data_fifo_empty )
);
// hookup CLUT <cycle shared memory>
vga_csm_pb #(24, 9) clut_mem(
.clk_i(wb_clk_i),
// color processor access
.req0_i(cp_clut_req),
.ack0_o(cp_clut_ack),
.adr0_i(cp_clut_adr),
.dat0_i(24'h0),
.dat0_o(cp_clut_q),
.we0_i(1'b0), // no writes
// external access
.req1_i(ext_clut_req),
.ack1_o(ext_clut_ack),
.adr1_i(wbs_adr_i[10:2]),
.dat1_i(wbs_dat_i[23:0]),
.dat1_o(ext_clut_q),
.we1_i(wbs_we_i)
);
// hookup pixel and video timing generator
vga_pgen pixel_generator (
.clk_i ( wb_clk_i ),
.ctrl_ven ( ctrl_ven ),
.ctrl_HSyncL ( ctrl_hsl ),
.Thsync ( Thsync ),
.Thgdel ( Thgdel ),
.Thgate ( Thgate ),
.Thlen ( Thlen ),
.ctrl_VSyncL ( ctrl_vsl ),
.Tvsync ( Tvsync ),
.Tvgdel ( Tvgdel ),
.Tvgate ( Tvgate ),
.Tvlen ( Tvlen ),
.ctrl_CSyncL ( ctrl_csl ),
.ctrl_BlankL ( ctrl_bl ),
.eoh ( hint ),
.eov ( vint ),
// frame buffer data (from wbm)
.fb_data_fifo_rreq ( fb_data_fifo_rreq ),
.fb_data_fifo_q ( fb_data_fifo_q ),
.fb_data_fifo_empty ( fb_data_fifo_empty ),
.ImDoneFifoQ ( ImDoneFifoQ ),
// clut memory signals
.stat_acmp ( stat_acmp ),
.clut_req ( cp_clut_req ),
.clut_ack ( cp_clut_ack ),
.clut_adr ( cp_clut_adr ),
.clut_q ( cp_clut_q ),
.ctrl_cbsw ( ctrl_cbsw ),
.clut_switch ( clut_swint ),
.cursor_adr ( cursor_adr ), // cursor data address (from wbm)
.cursor0_en ( cursor0_en ), // cursor0 enable
.cursor0_res ( cursor0_res ), // cursor0 resolution
.cursor0_xy ( cursor0_xy ), // cursor0 (x,y)
.cc0_adr_o ( cc0_adr_i ), // cursor0 color registers address
.cc0_dat_i ( cc0_dat_o ), // cursor0 color registers data
.cursor1_en ( cursor1_en ), // cursor1 enable
.cursor1_res ( cursor1_res ), // cursor1 resolution
.cursor1_xy ( cursor1_xy ), // cursor1 (x,y)
.cc1_adr_o ( cc1_adr_i ), // cursor1 color registers address
.cc1_dat_i ( cc1_dat_o ), // cursor1 color registers data
.ctrl_dvi_odf ( ctrl_dvi_odf ),
.ctrl_cd ( ctrl_cd ),
.ctrl_pc ( ctrl_pc ),
// line fifo memory signals
.line_fifo_wreq ( line_fifo_wreq ),
.line_fifo_d ( line_fifo_d ),
.line_fifo_full ( line_fifo_full_wr ),
.line_fifo_rreq ( line_fifo_rreq ),
.line_fifo_q ( line_fifo_q ),
.pclk_i ( clk_p_i ),
`ifdef VGA_12BIT_DVI
.dvi_pclk_p_o ( dvi_pclk_p_o ),
.dvi_pclk_m_o ( dvi_pclk_m_o ),
.dvi_hsync_o ( dvi_hsync_o ),
.dvi_vsync_o ( dvi_vsync_o ),
.dvi_de_o ( dvi_de_o ),
.dvi_d_o ( dvi_d_o ),
`endif
.pclk_o ( clk_p_o ),
.hsync_o ( hsync_pad_o ),
.vsync_o ( vsync_pad_o ),
.csync_o ( csync_pad_o ),
.blank_o ( blank_pad_o ),
.r_o ( r_pad_o ),
.g_o ( g_pad_o ),
.b_o ( b_pad_o )
);
// hookup line-fifo
wire ctrl_ven_not = ~ctrl_ven;
vga_fifo_dc #(LINE_FIFO_AWIDTH, 24) line_fifo (
.rclk ( clk_p_i ),
.wclk ( wb_clk_i ),
.rclr ( 1'b0 ),
.wclr ( ctrl_ven_not ),
.wreq ( line_fifo_wreq ),
.d ( line_fifo_d ),
.rreq ( line_fifo_rreq ),
.q ( line_fifo_q ),
.empty ( line_fifo_empty_rd ),
.full ( line_fifo_full_wr )
);
// generate interrupt signal when reading line-fifo while it is empty (line-fifo under-run interrupt)
reg luint_pclk, sluint;
always @(posedge clk_p_i)
luint_pclk <= #1 line_fifo_rreq & line_fifo_empty_rd;
always @(posedge wb_clk_i)
if (!ctrl_ven)
begin
sluint <= #1 1'b0;
luint <= #1 1'b0;
end
else
begin
sluint <= #1 luint_pclk; // resample at wb_clk_i clock
luint <= #1 sluint; // sample again, reduce metastability risk
end
endmodule |
module vga_wb_master (clk_i, rst_i, nrst_i,
cyc_o, stb_o, cti_o, bte_o, we_o, adr_o, sel_o, ack_i, err_i, dat_i, sint,
ctrl_ven, ctrl_cd, ctrl_vbl, ctrl_vbsw, busy,
VBAa, VBAb, Thgate, Tvgate,
stat_avmp, vmem_switch, ImDoneFifoQ,
cursor_adr, cursor0_ba, cursor1_ba, cursor0_ld, cursor1_ld,
fb_data_fifo_rreq, fb_data_fifo_q, fb_data_fifo_empty);
// inputs & outputs
// wishbone signals
input clk_i; // master clock input
input rst_i; // synchronous active high reset
input nrst_i; // asynchronous low reset
output cyc_o; // cycle output
reg cyc_o;
output stb_o; // strobe ouput
reg stb_o;
output [ 2:0] cti_o; // cycle type id
reg [2:0] cti_o;
output [ 1:0] bte_o; // burst type extension
reg [1:0] bte_o;
output we_o; // write enable output
reg we_o;
output [31:0] adr_o; // address output
output [ 3:0] sel_o; // byte select outputs (only 32bits accesses are supported)
reg [3:0] sel_o;
input ack_i; // wishbone cycle acknowledge
input err_i; // wishbone cycle error
input [31:0] dat_i; // wishbone data in
output sint; // non recoverable error, interrupt host
// control register settings
input ctrl_ven; // video enable bit
input [1:0] ctrl_cd; // color depth
input [1:0] ctrl_vbl; // burst length
input ctrl_vbsw; // enable video bank switching
output busy; // data transfer in progress
// video memory addresses
input [31: 2] VBAa; // video memory base address A
input [31: 2] VBAb; // video memory base address B
input [15:0] Thgate; // horizontal visible area (in pixels)
input [15:0] Tvgate; // vertical visible area (in horizontal lines)
output stat_avmp; // active video memory page
output vmem_switch; // video memory bank-switch request: memory page switched (when enabled)
output ImDoneFifoQ;
output [ 8: 0] cursor_adr; // cursor address
input [31:11] cursor0_ba;
input [31:11] cursor1_ba;
input cursor0_ld; // load cursor0 (from wbs)
input cursor1_ld; // load cursor1 (from wbs)
input fb_data_fifo_rreq;
output [31: 0] fb_data_fifo_q;
output fb_data_fifo_empty;
//
// variable declarations
//
reg vmem_acc; // video memory access
wire vmem_req, vmem_ack; // video memory access request // video memory access acknowledge
wire ImDone; // Done reading image from video mem
reg dImDone; // delayed ImDone
wire ImDoneStrb; // image done (strobe signal)
reg dImDoneStrb; // delayed ImDoneStrb
reg sclr; // (video/cursor) synchronous clear
// hardware cursors
reg [31:11] cursor_ba; // cursor pattern base address
reg [ 8: 0] cursor_adr; // cursor pattern offset
wire cursor0_we, cursor1_we; // cursor buffers write_request
reg ld_cursor0, ld_cursor1; // reload cursor0, cursor1
reg cur_acc; // cursor processors request memory access
reg cur_acc_sel; // which cursor to reload
wire cur_ack; // cursor processor memory access acknowledge
wire cur_done; // done reading cursor pattern
//
// module body
//
// generate synchronous clear
always @(posedge clk_i)
sclr <= #1 ~ctrl_ven;
//
// WISHBONE block
//
reg [ 2:0] burst_cnt; // video memory burst access counter
wire burst_done; // completed burst access to video mem
reg sel_VBA; // select video memory base address
reg [31:2] vmemA; // video memory address
// wishbone access controller, video memory access request has highest priority (try to keep fifo full)
always @(posedge clk_i)
if (sclr)
vmem_acc <= #1 1'b0; // video memory access request
else
vmem_acc <= #1 (vmem_req | (vmem_acc & !(burst_done & vmem_ack)) ) & !ImDone & !cur_acc;
always @(posedge clk_i)
if (sclr)
cur_acc <= #1 1'b0; // cursor processor memory access request
else
cur_acc <= #1 (cur_acc | ImDone & (ld_cursor0 | ld_cursor1)) & !cur_done;
assign busy = vmem_acc | cur_acc;
assign vmem_ack = ack_i & stb_o & vmem_acc;
assign cur_ack = ack_i & stb_o & cur_acc;
assign sint = err_i; // Non recoverable error, interrupt host system
// select active memory page
assign vmem_switch = ImDoneStrb;
always @(posedge clk_i)
if (sclr)
sel_VBA <= #1 1'b0;
else if (ctrl_vbsw)
sel_VBA <= #1 sel_VBA ^ vmem_switch; // select next video memory bank when finished reading current bank (and bank switch enabled)
assign stat_avmp = sel_VBA; // assign output
// selecting active clut page / cursor data
// delay image done same amount as video-memory data
vga_fifo #(4, 1) clut_sw_fifo (
.clk ( clk_i ),
.aclr ( 1'b1 ),
.sclr ( sclr ),
.d ( ImDone ),
.wreq ( vmem_ack ),
.q ( ImDoneFifoQ ),
.rreq ( fb_data_fifo_rreq ),
.nword ( ),
.empty ( ),
.full ( ),
.aempty ( ),
.afull ( )
);
//
// generate burst counter
wire [3:0] burst_cnt_val;
assign burst_cnt_val = {1'b0, burst_cnt} -4'h1;
assign burst_done = burst_cnt_val[3];
always @(posedge clk_i)
if ( (burst_done & vmem_ack) | !vmem_acc)
case (ctrl_vbl) // synopsis full_case parallel_case
2'b00: burst_cnt <= #1 3'b000; // burst length 1
2'b01: burst_cnt <= #1 3'b001; // burst length 2
2'b10: burst_cnt <= #1 3'b011; // burst length 4
2'b11: burst_cnt <= #1 3'b111; // burst length 8
endcase
else if(vmem_ack)
burst_cnt <= #1 burst_cnt_val[2:0];
//
// generate image counters
//
// hgate counter
reg [15:0] hgate_cnt;
reg [16:0] hgate_cnt_val;
reg [1:0] hgate_div_cnt;
reg [2:0] hgate_div_val;
wire hdone = hgate_cnt_val[16] & vmem_ack; // ????
always @(hgate_cnt or hgate_div_cnt or ctrl_cd)
begin
hgate_div_val = {1'b0, hgate_div_cnt} - 3'h1;
if (ctrl_cd != 2'b10)
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
else if ( hgate_div_val[2] )
hgate_cnt_val = {1'b0, hgate_cnt} - 17'h1;
else
hgate_cnt_val = {1'b0, hgate_cnt};
end
always @(posedge clk_i)
if (sclr)
begin
case(ctrl_cd) // synopsys full_case parallel_case
2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle
2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle
endcase
hgate_div_cnt <= 2'b10;
end
else if (vmem_ack)
if (hdone)
begin
case(ctrl_cd) // synopsys full_case parallel_case
2'b00: hgate_cnt <= #1 Thgate >> 2; // 8bpp, 4 pixels per cycle
2'b01: hgate_cnt <= #1 Thgate >> 1; // 16bpp, 2 pixels per cycle
2'b10: hgate_cnt <= #1 Thgate >> 2; // 24bpp, 4/3 pixels per cycle
2'b11: hgate_cnt <= #1 Thgate; // 32bpp, 1 pixel per cycle
endcase
hgate_div_cnt <= 2'b10;
end
else //if (vmem_ack)
begin
hgate_cnt <= #1 hgate_cnt_val[15:0];
if ( hgate_div_val[2] )
hgate_div_cnt <= #1 2'b10;
else
hgate_div_cnt <= #1 hgate_div_val[1:0];
end
// vgate counter
reg [15:0] vgate_cnt;
wire [16:0] vgate_cnt_val;
wire vdone;
assign vgate_cnt_val = {1'b0, vgate_cnt} - 17'h1;
assign vdone = vgate_cnt_val[16];
always @(posedge clk_i)
if (sclr | ImDoneStrb)
vgate_cnt <= #1 Tvgate;
else if (hdone)
vgate_cnt <= #1 vgate_cnt_val[15:0];
assign ImDone = hdone & vdone;
assign ImDoneStrb = ImDone & !dImDone;
always @(posedge clk_i)
begin
dImDone <= #1 ImDone;
dImDoneStrb <= #1 ImDoneStrb;
end
//
// generate addresses
//
// select video memory base address
always @(posedge clk_i)
if (sclr | dImDoneStrb)
if (!sel_VBA)
vmemA <= #1 VBAa;
else
vmemA <= #1 VBAb;
else if (vmem_ack)
vmemA <= #1 vmemA +30'h1;
////////////////////////////////////
// hardware cursor signals section
//
always @(posedge clk_i)
if (ImDone)
cur_acc_sel <= #1 ld_cursor0; // cursor0 has highest priority
always @(posedge clk_i)
if (sclr)
begin
ld_cursor0 <= #1 1'b0;
ld_cursor1 <= #1 1'b0;
end
else
begin
ld_cursor0 <= #1 cursor0_ld | (ld_cursor0 & !(cur_done & cur_acc_sel));
ld_cursor1 <= #1 cursor1_ld | (ld_cursor1 & !(cur_done & !cur_acc_sel));
end
// select cursor base address
always @(posedge clk_i)
if (!cur_acc)
cursor_ba <= #1 ld_cursor0 ? cursor0_ba : cursor1_ba;
// generate pattern offset
wire [9:0] next_cursor_adr = {1'b0, cursor_adr} + 10'h1;
assign cur_done = next_cursor_adr[9] & cur_ack;
always @(posedge clk_i)
if (!cur_acc)
cursor_adr <= #1 9'h0;
else if (cur_ack)
cursor_adr <= #1 next_cursor_adr;
// generate cursor buffers write enable signals
assign cursor1_we = cur_ack & !cur_acc_sel;
assign cursor0_we = cur_ack & cur_acc_sel;
//////////////////////////////
// generate wishbone signals
//
assign adr_o = cur_acc ? {cursor_ba, cursor_adr, 2'b00} : {vmemA, 2'b00};
wire wb_cycle = vmem_acc & !(burst_done & vmem_ack & !vmem_req) & !ImDone ||
cur_acc & !cur_done;
always @(posedge clk_i or negedge nrst_i)
if (!nrst_i)
begin
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
sel_o <= #1 4'b1111;
cti_o <= #1 3'b000;
bte_o <= #1 2'b00;
we_o <= #1 1'b0;
end
else
if (rst_i)
begin
cyc_o <= #1 1'b0;
stb_o <= #1 1'b0;
sel_o <= #1 4'b1111;
cti_o <= #1 3'b000;
bte_o <= #1 2'b00;
we_o <= #1 1'b0;
end
else
begin
cyc_o <= #1 wb_cycle;
stb_o <= #1 wb_cycle;
sel_o <= #1 4'b1111; // only 32bit accesses are supported
if (wb_cycle) begin
if (cur_acc)
cti_o <= #1 &next_cursor_adr[8:0] ? 3'b111 : 3'b010;
else if (ctrl_vbl == 2'b00)
cti_o <= #1 3'b000;
else if (vmem_ack)
cti_o <= #1 (burst_cnt == 3'h1) ? 3'b111 : 3'b010;
end else
cti_o <= #1 (ctrl_vbl == 2'b00) ? 3'b000 : 3'b010;
bte_o <= #1 2'b00; // linear burst
we_o <= #1 1'b0; // read only
end
//
// video-data buffer (temporary store data read from video memory)
wire [4:0] fb_data_fifo_nword;
// wire fb_data_fifo_full;
vga_fifo #(4, 32) data_fifo (
.clk ( clk_i ),
.aclr ( 1'b1 ),
.sclr ( sclr ),
.d ( dat_i ),
.wreq ( vmem_ack ),
.q ( fb_data_fifo_q ),
.rreq ( fb_data_fifo_rreq ),
.nword ( fb_data_fifo_nword ),
.empty ( fb_data_fifo_empty ),
.full ( ),//fb_data_fifo_full ),
.aempty ( ),
.afull ( )
);
assign vmem_req = ~fb_data_fifo_nword[4] & ~fb_data_fifo_nword[3];
endmodule |
module vga_fifo (
clk,
aclr,
sclr,
wreq,
rreq,
d,
q,
nword,
empty,
full,
aempty,
afull
);
//
// parameters
//
parameter aw = 3; // no.of entries (in bits; 2^7=128 entries)
parameter dw = 8; // datawidth (in bits)
//
// inputs & outputs
//
input clk; // master clock
input aclr; // asynchronous active low reset
input sclr; // synchronous active high reset
input wreq; // write request
input rreq; // read request
input [dw:1] d; // data-input
output [dw:1] q; // data-output
output [aw:0] nword; // number of words in FIFO
output empty; // fifo empty
output full; // fifo full
output aempty; // fifo asynchronous/almost empty (1 entry left)
output afull; // fifo asynchronous/almost full (1 entry left)
reg [aw:0] nword;
reg empty, full;
//
// Module body
//
reg [aw:1] rp, wp;
wire [dw:1] ramq;
wire fwreq, frreq;
`ifdef VGA_FIFO_ALL_ENTRIES
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = &q[aw-1:1] ^ ~(q[3] ^ q[2]);
4: lsb = &q[aw-1:1] ^ ~(q[4] ^ q[3]);
5: lsb = &q[aw-1:1] ^ ~(q[5] ^ q[3]);
6: lsb = &q[aw-1:1] ^ ~(q[6] ^ q[5]);
7: lsb = &q[aw-1:1] ^ ~(q[7] ^ q[6]);
8: lsb = &q[aw-1:1] ^ ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = &q[aw-1:1] ^ ~(q[9] ^ q[5]);
10: lsb = &q[aw-1:1] ^ ~(q[10] ^ q[7]);
11: lsb = &q[aw-1:1] ^ ~(q[11] ^ q[9]);
12: lsb = &q[aw-1:1] ^ ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = &q[aw-1:1] ^ ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = &q[aw-1:1] ^ ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = &q[aw-1:1] ^ ~(q[15] ^ q[14]);
16: lsb = &q[aw-1:1] ^ ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`else
function lsb;
input [aw:1] q;
case (aw)
2: lsb = ~q[2];
3: lsb = ~(q[3] ^ q[2]);
4: lsb = ~(q[4] ^ q[3]);
5: lsb = ~(q[5] ^ q[3]);
6: lsb = ~(q[6] ^ q[5]);
7: lsb = ~(q[7] ^ q[6]);
8: lsb = ~(q[8] ^ q[6] ^ q[5] ^ q[4]);
9: lsb = ~(q[9] ^ q[5]);
10: lsb = ~(q[10] ^ q[7]);
11: lsb = ~(q[11] ^ q[9]);
12: lsb = ~(q[12] ^ q[6] ^ q[4] ^ q[1]);
13: lsb = ~(q[13] ^ q[4] ^ q[3] ^ q[1]);
14: lsb = ~(q[14] ^ q[5] ^ q[3] ^ q[1]);
15: lsb = ~(q[15] ^ q[14]);
16: lsb = ~(q[16] ^ q[15] ^ q[13] ^ q[4]);
endcase
endfunction
`endif
`ifdef RW_CHECK
assign fwreq = wreq & ~full;
assign frreq = rreq & ~empty;
`else
assign fwreq = wreq;
assign frreq = rreq;
`endif
//
// hookup read-pointer
//
always @(posedge clk or negedge aclr)
if (~aclr) rp <= #1 0;
else if (sclr) rp <= #1 0;
else if (frreq) rp <= #1 {rp[aw-1:1], lsb(rp)};
//
// hookup write-pointer
//
always @(posedge clk or negedge aclr)
if (~aclr) wp <= #1 0;
else if (sclr) wp <= #1 0;
else if (fwreq) wp <= #1 {wp[aw-1:1], lsb(wp)};
//
// hookup memory-block
//
reg [dw:1] mem [(1<<aw) -1:0];
// memory array operations
always @(posedge clk)
if (fwreq)
mem[wp] <= #1 d;
assign q = mem[rp];
// generate full/empty signals
assign aempty = (rp[aw-1:1] == wp[aw:2]) & (lsb(rp) == wp[1]) & frreq & ~fwreq;
always @(posedge clk or negedge aclr)
if (~aclr)
empty <= #1 1'b1;
else if (sclr)
empty <= #1 1'b1;
else
empty <= #1 aempty | (empty & (~fwreq + frreq));
assign afull = (wp[aw-1:1] == rp[aw:2]) & (lsb(wp) == rp[1]) & fwreq & ~frreq;
always @(posedge clk or negedge aclr)
if (~aclr)
full <= #1 1'b0;
else if (sclr)
full <= #1 1'b0;
else
full <= #1 afull | ( full & (~frreq + fwreq) );
// number of words in fifo
always @(posedge clk or negedge aclr)
if (~aclr)
nword <= #1 0;
else if (sclr)
nword <= #1 0;
else
begin
if (wreq & !rreq)
nword <= #1 nword +1;
else if (rreq & !wreq)
nword <= #1 nword -1;
end
//
// Simulation checks
//
// synopsys translate_off
always @(posedge clk)
if (full & fwreq)
$display("Writing while FIFO full (%m)\n");
always @(posedge clk)
if (empty & frreq)
$display("Reading while FIFO empty (%m)\n");
// synopsys translate_on
endmodule |
module vga_pgen (
clk_i, ctrl_ven, ctrl_HSyncL, Thsync, Thgdel, Thgate, Thlen,
ctrl_VSyncL, Tvsync, Tvgdel, Tvgate, Tvlen, ctrl_CSyncL, ctrl_BlankL,
eoh, eov,
ctrl_dvi_odf, ctrl_cd, ctrl_pc,
fb_data_fifo_rreq, fb_data_fifo_empty, fb_data_fifo_q, ImDoneFifoQ,
stat_acmp, clut_req, clut_adr, clut_q, clut_ack, ctrl_cbsw, clut_switch,
cursor_adr,
cursor0_en, cursor0_res, cursor0_xy, cc0_adr_o, cc0_dat_i,
cursor1_en, cursor1_res, cursor1_xy, cc1_adr_o, cc1_dat_i,
line_fifo_wreq, line_fifo_full, line_fifo_d, line_fifo_rreq, line_fifo_q,
pclk_i,
`ifdef VGA_12BIT_DVI
dvi_pclk_p_o, dvi_pclk_m_o, dvi_hsync_o, dvi_vsync_o, dvi_de_o, dvi_d_o,
`endif
pclk_o, hsync_o, vsync_o, csync_o, blank_o, r_o, g_o, b_o
);
// inputs & outputs
input clk_i; // master clock
input ctrl_ven; // Video enable signal
// horiontal timing settings
input ctrl_HSyncL; // horizontal sync pulse polarization level (pos/neg)
input [ 7:0] Thsync; // horizontal sync pulse width (in pixels)
input [ 7:0] Thgdel; // horizontal gate delay (in pixels)
input [15:0] Thgate; // horizontal gate length (number of visible pixels per line)
input [15:0] Thlen; // horizontal length (number of pixels per line)
// vertical timing settings
input ctrl_VSyncL; // vertical sync pulse polarization level (pos/neg)
input [ 7:0] Tvsync; // vertical sync pulse width (in lines)
input [ 7:0] Tvgdel; // vertical gate delay (in lines)
input [15:0] Tvgate; // vertical gate length (number of visible lines in frame)
input [15:0] Tvlen; // vertical length (number of lines in frame)
// composite signals
input ctrl_CSyncL; // composite sync pulse polarization level
input ctrl_BlankL; // blank signal polarization level
// status outputs
output eoh; // end of horizontal
reg eoh;
output eov; // end of vertical;
reg eov;
// Pixel signals
input [ 1: 0] ctrl_dvi_odf;
input [ 1: 0] ctrl_cd;
input ctrl_pc;
input [31: 0] fb_data_fifo_q;
input fb_data_fifo_empty;
output fb_data_fifo_rreq;
input ImDoneFifoQ;
output stat_acmp; // active CLUT memory page
reg stat_acmp;
output clut_req;
output [ 8: 0] clut_adr;
input [23: 0] clut_q;
input clut_ack;
input ctrl_cbsw; // enable clut bank switching
output clut_switch; // clut memory bank-switch request: clut page switched (when enabled)
input [ 8: 0] cursor_adr; // cursor data address (from wbm)
input cursor0_en; // enable hardware cursor0
input cursor0_res; // cursor0 resolution
input [31: 0] cursor0_xy; // (x,y) address hardware cursor0
output [ 3: 0] cc0_adr_o; // cursor0 color registers address output
input [15: 0] cc0_dat_i; // cursor0 color registers data input
input cursor1_en; // enable hardware cursor1
input cursor1_res; // cursor1 resolution
input [31: 0] cursor1_xy; // (x,y) address hardware cursor1
output [ 3: 0] cc1_adr_o; // cursor1 color registers address output
input [15: 0] cc1_dat_i; // cursor1 color registers data input
input line_fifo_full;
output line_fifo_wreq;
output [23: 0] line_fifo_d;
output line_fifo_rreq;
input [23: 0] line_fifo_q;
// pixel clock related outputs
input pclk_i; // pixel clock in
output pclk_o; // pixel clock out
output hsync_o; // horizontal sync pulse
output vsync_o; // vertical sync pulse
output csync_o; // composite sync: Hsync OR Vsync (logical OR function)
output blank_o; // blanking signal
output [ 7:0] r_o, g_o, b_o;
reg hsync_o, vsync_o, csync_o, blank_o;
reg [7:0] r_o, g_o, b_o;
`ifdef VGA_12BIT_DVI
output dvi_pclk_p_o; // dvi pclk+
output dvi_pclk_m_o; // dvi pclk-
output dvi_hsync_o; // dvi hsync
output dvi_vsync_o; // dvi vsync
output dvi_de_o; // dvi data enable
output [11:0] dvi_d_o; // dvi 12bit output
`endif
//
// variable declarations
//
reg nVen; // video enable signal (active low)
wire eol, eof;
wire ihsync, ivsync, icsync, iblank;
wire pclk_ena;
//////////////////////////////////
//
// module body
//
// synchronize timing/control settings (from master-clock-domain to pixel-clock-domain)
always @(posedge pclk_i)
nVen <= #1 ~ctrl_ven;
//////////////////////////////////
//
// Pixel Clock generator
//
vga_clkgen clk_gen(
.pclk_i ( pclk_i ),
.rst_i ( nVen ),
.pclk_o ( pclk_o ),
.dvi_pclk_p_o ( dvi_pclk_p_o ),
.dvi_pclk_m_o ( dvi_pclk_m_o ),
.pclk_ena_o ( pclk_ena )
);
//////////////////////////////////
//
// Timing generator
//
// hookup video timing generator
vga_tgen vtgen(
.clk(pclk_i),
.clk_ena ( pclk_ena ),
.rst ( nVen ),
.Thsync ( Thsync ),
.Thgdel ( Thgdel ),
.Thgate ( Thgate ),
.Thlen ( Thlen ),
.Tvsync ( Tvsync ),
.Tvgdel ( Tvgdel ),
.Tvgate ( Tvgate ),
.Tvlen ( Tvlen ),
.eol ( eol ),
.eof ( eof ),
.gate ( gate ),
.hsync ( ihsync ),
.vsync ( ivsync ),
.csync ( icsync ),
.blank ( iblank )
);
//
// from pixel-clock-domain to master-clock-domain
//
reg seol, seof; // synchronized end-of-line, end-of-frame
reg dseol, dseof; // delayed seol, seof
always @(posedge clk_i)
if (~ctrl_ven)
begin
seol <= #1 1'b0;
dseol <= #1 1'b0;
seof <= #1 1'b0;
dseof <= #1 1'b0;
eoh <= #1 1'b0;
eov <= #1 1'b0;
end
else
begin
seol <= #1 eol;
dseol <= #1 seol;
seof <= #1 eof;
dseof <= #1 seof;
eoh <= #1 seol & !dseol;
eov <= #1 seof & !dseof;
end
`ifdef VGA_12BIT_DVI
always @(posedge pclk_i)
if (pclk_ena)
begin
hsync_o <= #1 ihsync ^ ctrl_HSyncL;
vsync_o <= #1 ivsync ^ ctrl_VSyncL;
csync_o <= #1 icsync ^ ctrl_CSyncL;
blank_o <= #1 iblank ^ ctrl_BlankL;
end
`else
reg hsync, vsync, csync, blank;
always @(posedge pclk_i)
begin
hsync <= #1 ihsync ^ ctrl_HSyncL;
vsync <= #1 ivsync ^ ctrl_VSyncL;
csync <= #1 icsync ^ ctrl_CSyncL;
blank <= #1 iblank ^ ctrl_BlankL;
hsync_o <= #1 hsync;
vsync_o <= #1 vsync;
csync_o <= #1 csync;
blank_o <= #1 blank;
end
`endif
//////////////////////////////////
//
// Pixel generator section
//
wire [23:0] color_proc_q; // data from color processor
wire color_proc_wreq;
wire [ 7:0] clut_offs; // color lookup table offset
wire ImDoneFifoQ;
reg dImDoneFifoQ, ddImDoneFifoQ;
wire [23:0] cur1_q;
wire cur1_wreq;
wire [23:0] rgb_fifo_d;
wire rgb_fifo_empty, rgb_fifo_full, rgb_fifo_rreq, rgb_fifo_wreq;
wire sclr = ~ctrl_ven;
//
// hookup color processor
vga_colproc color_proc (
.clk ( clk_i ),
.srst ( sclr ),
.vdat_buffer_di ( fb_data_fifo_q ), //data_fifo_q),
.ColorDepth ( ctrl_cd ),
.PseudoColor ( ctrl_pc ),
.vdat_buffer_empty ( fb_data_fifo_empty ), //data_fifo_empty),
.vdat_buffer_rreq ( fb_data_fifo_rreq ), //data_fifo_rreq),
.rgb_fifo_full ( rgb_fifo_full ),
.rgb_fifo_wreq ( color_proc_wreq ),
.r ( color_proc_q[23:16] ),
.g ( color_proc_q[15: 8] ),
.b ( color_proc_q[ 7: 0] ),
.clut_req ( clut_req ),
.clut_ack ( clut_ack ),
.clut_offs ( clut_offs ),
.clut_q ( clut_q )
);
//
// clut bank switch / cursor data delay2: Account for ColorProcessor DataBuffer delay
always @(posedge clk_i)
if (sclr)
dImDoneFifoQ <= #1 1'b0;
else if (fb_data_fifo_rreq)
dImDoneFifoQ <= #1 ImDoneFifoQ;
always @(posedge clk_i)
if (sclr)
ddImDoneFifoQ <= #1 1'b0;
else
ddImDoneFifoQ <= #1 dImDoneFifoQ;
assign clut_switch = ddImDoneFifoQ & !dImDoneFifoQ;
always @(posedge clk_i)
if (sclr)
stat_acmp <= #1 1'b0;
else if (ctrl_cbsw)
stat_acmp <= #1 stat_acmp ^ clut_switch; // select next clut when finished reading clut for current video bank (and bank switch enabled)
// generate clut-address
assign clut_adr = {stat_acmp, clut_offs};
//
// hookup data-source-selector && hardware cursor module
`ifdef VGA_HWC1 // generate Hardware Cursor1 (if enabled)
wire cursor1_ld_strb;
reg scursor1_en;
reg scursor1_res;
reg [31:0] scursor1_xy;
assign cursor1_ld_strb = ddImDoneFifoQ & !dImDoneFifoQ;
always @(posedge clk_i)
if (sclr)
scursor1_en <= #1 1'b0;
else if (cursor1_ld_strb)
scursor1_en <= #1 cursor1_en;
always @(posedge clk_i)
if (cursor1_ld_strb)
scursor1_xy <= #1 cursor1_xy;
always @(posedge clk_i)
if (cursor1_ld_strb)
scursor1_res <= #1 cursor1_res;
vga_curproc hw_cursor1 (
.clk ( clk_i ),
.rst_i ( sclr ),
.Thgate ( Thgate ),
.Tvgate ( Tvgate ),
.idat ( color_proc_q ),
.idat_wreq ( color_proc_wreq ),
.cursor_xy ( scursor1_xy ),
.cursor_res ( scursor1_res ),
.cursor_en ( scursor1_en ),
.cursor_wadr ( cursor_adr ),
.cursor_we ( cursor1_we ),
.cursor_wdat ( dat_i ),
.cc_adr_o ( cc1_adr_o ),
.cc_dat_i ( cc1_dat_i ),
.rgb_fifo_wreq ( cur1_wreq ),
.rgb ( cur1_q )
);
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
reg sddImDoneFifoQ, sdImDoneFifoQ;
always @(posedge clk_i)
if (cur1_wreq)
begin
sdImDoneFifoQ <= #1 dImDoneFifoQ;
sddImDoneFifoQ <= #1 sdImDoneFifoQ;
end
`endif
`else // Hardware Cursor1 disabled, generate pass-through signals
assign cur1_wreq = color_proc_wreq;
assign cur1_q = color_proc_q;
assign cc1_adr_o = 4'h0;
`ifdef VGA_HWC0 // generate additional signals for Hardware Cursor0 (if enabled)
wire sddImDoneFifoQ, sdImDoneFifoQ;
assign sdImDoneFifoQ = dImDoneFifoQ;
assign sddImDoneFifoQ = ddImDoneFifoQ;
`endif
`endif
`ifdef VGA_HWC0 // generate Hardware Cursor0 (if enabled)
wire cursor0_ld_strb;
reg scursor0_en;
reg scursor0_res;
reg [31:0] scursor0_xy;
assign cursor0_ld_strb = sddImDoneFifoQ & !sdImDoneFifoQ;
always @(posedge clk_i)
if (sclr)
scursor0_en <= #1 1'b0;
else if (cursor0_ld_strb)
scursor0_en <= #1 cursor0_en;
always @(posedge clk_i)
if (cursor0_ld_strb)
scursor0_xy <= #1 cursor0_xy;
always @(posedge clk_i)
if (cursor0_ld_strb)
scursor0_res <= #1 cursor0_res;
vga_curproc hw_cursor0 (
.clk ( clk_i ),
.rst_i ( sclr ),
.Thgate ( Thgate ),
.Tvgate ( Tvgate ),
.idat ( ssel1_q ),
.idat_wreq ( ssel1_wreq ),
.cursor_xy ( scursor0_xy ),
.cursor_en ( scursor0_en ),
.cursor_res ( scursor0_res ),
.cursor_wadr ( cursor_adr ),
.cursor_we ( cursor0_we ),
.cursor_wdat ( dat_i ),
.cc_adr_o ( cc0_adr_o ),
.cc_dat_i ( cc0_dat_i ),
.rgb_fifo_wreq ( rgb_fifo_wreq ),
.rgb ( rgb_fifo_d )
);
`else // Hardware Cursor0 disabled, generate pass-through signals
assign rgb_fifo_wreq = cur1_wreq;
assign rgb_fifo_d = cur1_q;
assign cc0_adr_o = 4'h0;
`endif
//
// hookup RGB buffer (temporary station between WISHBONE-clock-domain
// and pixel-clock-domain)
// The cursor_processor pipelines introduce a delay between the color
// processor's rgb_fifo_wreq and the rgb_fifo_full signals. To compensate
// for this we double the rgb_fifo.
wire [4:0] rgb_fifo_nword;
vga_fifo #(4, 24) rgb_fifo (
.clk ( clk_i ),
.aclr ( 1'b1 ),
.sclr ( sclr ),
.d ( rgb_fifo_d ),
.wreq ( rgb_fifo_wreq ),
.q ( line_fifo_d ),
.rreq ( rgb_fifo_rreq ),
.empty ( rgb_fifo_empty ),
.nword ( rgb_fifo_nword ),
.full ( ),
.aempty ( ),
.afull ( )
);
assign rgb_fifo_full = rgb_fifo_nword[3]; // actually half full
assign line_fifo_rreq = gate & pclk_ena;
assign rgb_fifo_rreq = ~line_fifo_full & ~rgb_fifo_empty;
assign line_fifo_wreq = rgb_fifo_rreq;
wire [7:0] r = line_fifo_q[23:16];
wire [7:0] g = line_fifo_q[15: 8];
wire [7:0] b = line_fifo_q[ 7: 0];
always @(posedge pclk_i)
if (pclk_ena) begin
r_o <= #1 r;
g_o <= #1 g;
b_o <= #1 b;
end
//
// DVI section
//
`ifdef VGA_12BIT_DVI
reg [11:0] dvi_d_o;
reg dvi_de_o;
reg dvi_hsync_o;
reg dvi_vsync_o;
reg [11:0] pA, pB;
reg dgate, ddgate;
reg dhsync, ddhsync;
reg dvsync, ddvsync;
always @(posedge pclk_i)
if (pclk_ena)
case (ctrl_dvi_odf) // synopsys full_case parallel_case
2'b00: pA <= #1 {g[3:0], b[7:0]};
2'b01: pA <= #1 {g[4:2], b[7:3], g[0], b[2:0]};
2'b10: pA <= #1 {g[4:2], b[7:3], 4'h0};
2'b11: pA <= #1 {g[5:3], b[7:3], 4'h0};
endcase
always @(posedge pclk_i)
if (pclk_ena)
case (ctrl_dvi_odf) // synopsys full_case parallel_case
2'b00: pB <= #1 {r[7:0], g[7:4]};
2'b01: pB <= #1 {r[7:3], g[7:5], r[2:0], g[1]};
2'b10: pB <= #1 {r[7:3], g[7:5], 4'h0};
2'b11: pB <= #1 {1'b0, r[7:3], g[7:6], 4'h0};
endcase
always @(posedge pclk_i)
if (pclk_ena)
dvi_d_o <= #1 pB;
else
dvi_d_o <= #1 pA;
always @(posedge pclk_i)
if (pclk_ena) begin
dgate <= #1 gate; // delay once: delayed line fifo output
dhsync <= #1 ~ihsync;
ddhsync <= #1 dhsync;
dvsync <= #1 ~ivsync;
ddvsync <= #1 dvsync;
end
always @(posedge pclk_i)
begin
dvi_de_o <= #1 dgate;
dvi_hsync_o <= #1 dhsync;
dvi_vsync_o <= #1 dvsync;
end
`endif
endmodule |
module vga_vtim(clk, ena, rst, Tsync, Tgdel, Tgate, Tlen, Sync, Gate, Done);
// inputs & outputs
input clk; // master clock
input ena; // count enable
input rst; // synchronous active high reset
input [ 7:0] Tsync; // sync duration
input [ 7:0] Tgdel; // gate delay
input [15:0] Tgate; // gate length
input [15:0] Tlen; // line time / frame time
output Sync; // synchronization pulse
output Gate; // gate
output Done; // done with line/frame
reg Sync;
reg Gate;
reg Done;
//
// module body
//
// generate timing statemachine
reg [15:0] cnt, cnt_len;
wire [16:0] cnt_nxt, cnt_len_nxt;
wire cnt_done, cnt_len_done;
assign cnt_nxt = {1'b0, cnt} -17'h1;
assign cnt_done = cnt_nxt[16];
assign cnt_len_nxt = {1'b0, cnt_len} -17'h1;
assign cnt_len_done = cnt_len_nxt[16];
reg [4:0] state;
parameter [4:0] idle_state = 5'b00001;
parameter [4:0] sync_state = 5'b00010;
parameter [4:0] gdel_state = 5'b00100;
parameter [4:0] gate_state = 5'b01000;
parameter [4:0] len_state = 5'b10000;
always @(posedge clk)
if (rst)
begin
state <= #1 idle_state;
cnt <= #1 16'h0;
cnt_len <= #1 16'b0;
Sync <= #1 1'b0;
Gate <= #1 1'b0;
Done <= #1 1'b0;
end
else if (ena)
begin
cnt <= #1 cnt_nxt[15:0];
cnt_len <= #1 cnt_len_nxt[15:0];
Done <= #1 1'b0;
case (state) // synopsys full_case parallel_case
idle_state:
begin
state <= #1 sync_state;
cnt <= #1 Tsync;
cnt_len <= #1 Tlen;
Sync <= #1 1'b1;
end
sync_state:
if (cnt_done)
begin
state <= #1 gdel_state;
cnt <= #1 Tgdel;
Sync <= #1 1'b0;
end
gdel_state:
if (cnt_done)
begin
state <= #1 gate_state;
cnt <= #1 Tgate;
Gate <= #1 1'b1;
end
gate_state:
if (cnt_done)
begin
state <= #1 len_state;
Gate <= #1 1'b0;
end
len_state:
if (cnt_len_done)
begin
state <= #1 sync_state;
cnt <= #1 Tsync;
cnt_len <= #1 Tlen;
Sync <= #1 1'b1;
Done <= #1 1'b1;
end
endcase
end
endmodule |
module vga_tgen(
clk, clk_ena, rst,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen,
eol, eof, gate, hsync, vsync, csync, blank
);
// inputs & outputs
input clk;
input clk_ena;
input rst;
// horizontal timing settings inputs
input [ 7:0] Thsync; // horizontal sync pule width (in pixels)
input [ 7:0] Thgdel; // horizontal gate delay
input [15:0] Thgate; // horizontal gate (number of visible pixels per line)
input [15:0] Thlen; // horizontal length (number of pixels per line)
// vertical timing settings inputs
input [ 7:0] Tvsync; // vertical sync pule width (in pixels)
input [ 7:0] Tvgdel; // vertical gate delay
input [15:0] Tvgate; // vertical gate (number of visible pixels per line)
input [15:0] Tvlen; // vertical length (number of pixels per line)
// outputs
output eol; // end of line
output eof; // end of frame
output gate; // vertical AND horizontal gate (logical AND function)
output hsync; // horizontal sync pulse
output vsync; // vertical sync pulse
output csync; // composite sync
output blank; // blank signal
//
// variable declarations
//
wire Hgate, Vgate;
wire Hdone;
//
// module body
//
// hookup horizontal timing generator
vga_vtim hor_gen(
.clk(clk),
.ena(clk_ena),
.rst(rst),
.Tsync(Thsync),
.Tgdel(Thgdel),
.Tgate(Thgate),
.Tlen(Thlen),
.Sync(hsync),
.Gate(Hgate),
.Done(Hdone)
);
// hookup vertical timing generator
wire vclk_ena = Hdone & clk_ena;
vga_vtim ver_gen(
.clk(clk),
.ena(vclk_ena),
.rst(rst),
.Tsync(Tvsync),
.Tgdel(Tvgdel),
.Tgate(Tvgate),
.Tlen(Tvlen),
.Sync(vsync),
.Gate(Vgate),
.Done(eof)
);
// assign outputs
assign eol = Hdone;
assign gate = Hgate & Vgate;
assign csync = hsync | vsync;
assign blank = ~gate;
endmodule |
module vga_curproc (clk, rst_i, Thgate, Tvgate, idat, idat_wreq,
cursor_xy, cursor_en, cursor_res,
cursor_wadr, cursor_wdat, cursor_we,
cc_adr_o, cc_dat_i,
rgb_fifo_wreq, rgb);
//
// inputs & outputs
//
// wishbone signals
input clk; // master clock input
input rst_i; // synchronous active high reset
// image size
input [15:0] Thgate, Tvgate; // horizontal/vertical gate
// image data
input [23:0] idat; // image data input
input idat_wreq; // image data write request
// cursor data
input [31:0] cursor_xy; // cursor (x,y)
input cursor_en; // cursor enable (on/off)
input cursor_res; // cursor resolution (32x32 or 64x64 pixels)
input [ 8:0] cursor_wadr; // cursor buffer write address
input [31:0] cursor_wdat; // cursor buffer write data
input cursor_we; // cursor buffer write enable
// color registers interface
output [ 3:0] cc_adr_o; // cursor color registers address
reg [ 3:0] cc_adr_o;
input [15:0] cc_dat_i; // cursor color registers data
// rgb-fifo connections
output rgb_fifo_wreq; // rgb-out write request
reg rgb_fifo_wreq;
output [23:0] rgb; // rgb data output
reg [23:0] rgb;
//
// variable declarations
//
reg dcursor_en, ddcursor_en, dddcursor_en;
reg [15:0] xcnt, ycnt;
wire xdone, ydone;
wire [15:0] cursor_x, cursor_y;
wire cursor_isalpha;
reg [15:0] cdat, dcdat;
wire [ 7:0] cursor_r, cursor_g, cursor_b, cursor_alpha;
reg inbox_x, inbox_y;
wire inbox;
reg dinbox, ddinbox, dddinbox;
reg [23:0] didat, ddidat, dddidat;
reg didat_wreq, ddidat_wreq;
wire [31:0] cbuf_q;
reg [11:0] cbuf_ra;
reg [ 2:0] dcbuf_ra;
wire [ 8:0] cbuf_a;
reg store1, store2;
//
// module body
//
//
// generate x-y counters
always@(posedge clk)
if(rst_i || xdone)
xcnt <= #1 16'h0;
else if (idat_wreq)
xcnt <= #1 xcnt + 16'h1;
assign xdone = (xcnt == Thgate) && idat_wreq;
always@(posedge clk)
if(rst_i || ydone)
ycnt <= #1 16'h0;
else if (xdone)
ycnt <= #1 ycnt + 16'h1;
assign ydone = (ycnt == Tvgate) && xdone;
// decode cursor (x,y)
assign cursor_x = cursor_xy[15: 0];
assign cursor_y = cursor_xy[31:16];
//
// generate inbox signals
always@(posedge clk)
begin
inbox_x <= #1 (xcnt >= cursor_x) && (xcnt < (cursor_x + (cursor_res ? 16'h7f : 16'h1f) ));
inbox_y <= #1 (ycnt >= cursor_y) && (ycnt < (cursor_y + (cursor_res ? 16'h7f : 16'h1f) ));
end
assign inbox = inbox_x && inbox_y;
always@(posedge clk)
dinbox <= #1 inbox;
always@(posedge clk)
if (didat_wreq)
ddinbox <= #1 dinbox;
always@(posedge clk)
dddinbox <= #1 ddinbox;
//
// generate cursor buffer address counter
always@(posedge clk)
if (!cursor_en || ydone)
cbuf_ra <= #1 12'h0;
else if (inbox && idat_wreq)
cbuf_ra <= #1 cbuf_ra +12'h1;
always@(posedge clk)
dcbuf_ra <= #1 cbuf_ra[2:0];
assign cbuf_a = cursor_we ? cursor_wadr : cursor_res ? cbuf_ra[11:3] : cbuf_ra[9:1];
// hookup local cursor memory (generic synchronous single port memory)
// cursor memory should never be written to/read from at the same time
generic_spram #(9, 32) cbuf(
.clk(clk),
.rst(1'b0), // no reset
.ce(1'b1), // always enable memory
.we(cursor_we),
.oe(1'b1), // always output data
.addr(cbuf_a),
.di(cursor_wdat),
.do(cbuf_q)
);
//
// decode cursor data for 32x32x16bpp mode
always@(posedge clk)
if (didat_wreq)
cdat <= #1 dcbuf_ra[0] ? cbuf_q[31:16] : cbuf_q[15:0];
always@(posedge clk)
dcdat <= #1 cdat;
//
// decode cursor data for 64x64x4bpp mode
// generate cursor-color address
always@(posedge clk)
if (didat_wreq)
case (dcbuf_ra)
3'b000: cc_adr_o <= cbuf_q[ 3: 0];
3'b001: cc_adr_o <= cbuf_q[ 7: 4];
3'b010: cc_adr_o <= cbuf_q[11: 8];
3'b011: cc_adr_o <= cbuf_q[15:12];
3'b100: cc_adr_o <= cbuf_q[19:16];
3'b101: cc_adr_o <= cbuf_q[23:20];
3'b110: cc_adr_o <= cbuf_q[27:24];
3'b111: cc_adr_o <= cbuf_q[31:28];
endcase
//
// generate cursor colors
assign cursor_isalpha = cursor_res ? cc_dat_i[15] : dcdat[15];
assign cursor_alpha = cursor_res ? cc_dat_i[7:0] : dcdat[7:0];
assign cursor_r = {cursor_res ? cc_dat_i[14:10] : dcdat[14:10], 3'h0};
assign cursor_g = {cursor_res ? cc_dat_i[ 9: 5] : dcdat[ 9: 5], 3'h0};
assign cursor_b = {cursor_res ? cc_dat_i[ 4: 0] : dcdat[ 4: 0], 3'h0};
//
// delay image data
always@(posedge clk)
didat <= #1 idat;
always@(posedge clk)
if (didat_wreq)
ddidat <= #1 didat;
always@(posedge clk)
dddidat <= #1 ddidat;
always@(posedge clk)
begin
didat_wreq <= #1 idat_wreq;
ddidat_wreq <= #1 didat_wreq;
end
//
// generate selection unit
always@(posedge clk)
dcursor_en <= #1 cursor_en;
always@(posedge clk)
if (didat_wreq)
ddcursor_en <= #1 dcursor_en;
always@(posedge clk)
dddcursor_en <= #1 ddcursor_en;
// Alpha blending:
// rgb = (rgb1 * alhpa1) + (rgb2 * alpha2)
// We generate an alpha mixer (alpha1 + alpha2 = 1)
// rgb = (alpha1)(rgb1) + (1-alpha1)(rgb2)
// We always mix to black (rgb2 = 0)
// rgb = (alpha1)(rgb1)
always@(posedge clk)
if (ddidat_wreq)
if (!dddcursor_en || !dddinbox)
rgb <= #1 dddidat;
else if (cursor_isalpha)
`ifdef VGA_HWC_3D
rgb <= #1 dddidat * cursor_alpha;
`else
rgb <= #1 dddidat;
`endif
else
rgb <= #1 {cursor_r, cursor_g, cursor_b};
//
// generate write request signal
always@(posedge clk)
if (rst_i)
begin
store1 <= #1 1'b0;
store2 <= #1 1'b0;
end
else
begin
store1 <= #1 didat_wreq | store1;
store2 <= #1 (didat_wreq & store1) | store2;
end
// skip 2 idat_wreq signal, to keep in pace with rgb_fifo_full signal
always@(posedge clk)
rgb_fifo_wreq <= #1 ddidat_wreq & store2;
endmodule |
module vga_fifo_dc (rclk, wclk, rclr, wclr, wreq, d, rreq, q, empty, full);
// parameters
parameter AWIDTH = 7; //128 entries
parameter DWIDTH = 16; //16bit databus
// inputs & outputs
input rclk; // read clock
input wclk; // write clock
input rclr; // active high synchronous clear, synchronous to read clock
input wclr; // active high synchronous clear, synchronous to write clock
input wreq; // write request
input [DWIDTH -1:0] d; // data input
input rreq; // read request
output [DWIDTH -1:0] q; // data output
output empty; // FIFO is empty, synchronous to read clock
reg empty;
output full; // FIFO is full, synchronous to write clock
reg full;
// variable declarations
reg rrst, wrst, srclr, ssrclr, swclr, sswclr;
reg [AWIDTH -1:0] rptr, wptr, rptr_gray, wptr_gray;
//
// module body
//
function [AWIDTH:1] bin2gray;
input [AWIDTH:1] bin;
integer n;
begin
for (n=1; n<AWIDTH; n=n+1)
bin2gray[n] = bin[n+1] ^ bin[n];
bin2gray[AWIDTH] = bin[AWIDTH];
end
endfunction
function [AWIDTH:1] gray2bin;
input [AWIDTH:1] gray;
begin
// same logic as bin2gray
gray2bin = bin2gray(gray);
end
endfunction
//
// Pointers
//
// generate synchronized resets
always @(posedge rclk)
begin
swclr <= #1 wclr;
sswclr <= #1 swclr;
rrst <= #1 rclr | sswclr;
end
always @(posedge wclk)
begin
srclr <= #1 rclr;
ssrclr <= #1 srclr;
wrst <= #1 wclr | ssrclr;
end
// read pointer
always @(posedge rclk)
if (rrst) begin
rptr <= #1 0;
rptr_gray <= #1 0;
end else if (rreq) begin
rptr <= #1 rptr +1'h1;
rptr_gray <= #1 bin2gray(rptr +1'h1);
end
// write pointer
always @(posedge wclk)
if (wrst) begin
wptr <= #1 0;
wptr_gray <= #1 0;
end else if (wreq) begin
wptr <= #1 wptr +1'h1;
wptr_gray <= #1 bin2gray(wptr +1'h1);
end
//
// status flags
//
reg [AWIDTH-1:0] srptr_gray, ssrptr_gray;
reg [AWIDTH-1:0] swptr_gray, sswptr_gray;
// from one clock domain, to the other
always @(posedge rclk)
begin
swptr_gray <= #1 wptr_gray;
sswptr_gray <= #1 swptr_gray;
end
always @(posedge wclk)
begin
srptr_gray <= #1 rptr_gray;
ssrptr_gray <= #1 srptr_gray;
end
// EMPTY
// WC: wptr did not increase
always @(posedge rclk)
if (rrst)
empty <= #1 1'b1;
else if (rreq)
empty <= #1 bin2gray(rptr +1'h1) == sswptr_gray;
else
empty <= #1 empty & (rptr_gray == sswptr_gray);
// FULL
// WC: rptr did not increase
always @(posedge wclk)
if (wrst)
full <= #1 1'b0;
else if (wreq)
full <= #1 bin2gray(wptr +2'h2) == ssrptr_gray;
else
full <= #1 full & (bin2gray(wptr + 2'h1) == ssrptr_gray);
// hookup generic dual ported memory
generic_dpram #(AWIDTH, DWIDTH) fifo_dc_mem(
.rclk(rclk),
.rrst(1'b0),
.rce(1'b1),
.oe(1'b1),
.raddr(rptr),
.do(q),
.wclk(wclk),
.wrst(1'b0),
.wce(1'b1),
.we(wreq),
.waddr(wptr),
.di(d)
);
endmodule |
module vga_clkgen (
pclk_i, rst_i, pclk_o, dvi_pclk_p_o, dvi_pclk_m_o, pclk_ena_o
);
// inputs & outputs
input pclk_i; // pixel clock in
input rst_i; // reset input
output pclk_o; // pixel clock out
output dvi_pclk_p_o; // dvi cpclk+ output
output dvi_pclk_m_o; // dvi cpclk- output
output pclk_ena_o; // pixel clock enable output
//
// variable declarations
//
reg dvi_pclk_p_o;
reg dvi_pclk_m_o;
//////////////////////////////////
//
// module body
//
// These should be registers in or near IO buffers
always @(posedge pclk_i)
if (rst_i) begin
dvi_pclk_p_o <= #1 1'b0;
dvi_pclk_m_o <= #1 1'b0;
end else begin
dvi_pclk_p_o <= #1 ~dvi_pclk_p_o;
dvi_pclk_m_o <= #1 dvi_pclk_p_o;
end
`ifdef VGA_12BIT_DVI
// DVI circuit
// pixel clock is half of the input pixel clock
reg pclk_o, pclk_ena_o;
always @(posedge pclk_i)
if (rst_i)
pclk_o <= #1 1'b0;
else
pclk_o <= #1 ~pclk_o;
always @(posedge pclk_i)
if (rst_i)
pclk_ena_o <= #1 1'b1;
else
pclk_ena_o <= #1 ~pclk_ena_o;
`else
// No DVI circuit
// Simply reroute the pixel clock input
assign pclk_o = pclk_i;
assign pclk_ena_o = 1'b1;
`endif
endmodule |
module vga_csm_pb (clk_i, req0_i, ack0_o, adr0_i, dat0_i, dat0_o, we0_i, req1_i, ack1_o, adr1_i, dat1_i, dat1_o, we1_i);
//
// parameters
//
parameter DWIDTH = 32; // databus width
parameter AWIDTH = 8; // address bus width
//
// inputs & outputs
//
input clk_i; // clock input
// wishbone slave0 connections
input [ AWIDTH -1:0] adr0_i; // address input
input [ DWIDTH -1:0] dat0_i; // data input
output [ DWIDTH -1:0] dat0_o; // data output
input we0_i; // write enable input
input req0_i; // access request input
output ack0_o; // access acknowledge output
// wishbone slave1 connections
input [ AWIDTH -1:0] adr1_i; // address input
input [ DWIDTH -1:0] dat1_i; // data input
output [ DWIDTH -1:0] dat1_o; // data output
input we1_i; // write enable input
input req1_i; // access request input
output ack1_o; // access acknowledge output
//
// variable declarations
//
// multiplexor select signal
wire acc0, acc1;
reg dacc0, dacc1;
wire sel0, sel1;
reg ack0, ack1;
// memory data output
wire [DWIDTH -1:0] mem_q;
//
// module body
//
// generate multiplexor select signal
assign acc0 = req0_i;
assign acc1 = req1_i && !sel0;
always@(posedge clk_i)
begin
dacc0 <= #1 acc0 & !ack0_o;
dacc1 <= #1 acc1 & !ack1_o;
end
assign sel0 = acc0 && !dacc0;
assign sel1 = acc1 && !dacc1;
always@(posedge clk_i)
begin
ack0 <= #1 sel0 && !ack0_o;
ack1 <= #1 sel1 && !ack1_o;
end
wire [AWIDTH -1:0] mem_adr = sel0 ? adr0_i : adr1_i;
wire [DWIDTH -1:0] mem_d = sel0 ? dat0_i : dat1_i;
wire mem_we = sel0 ? req0_i && we0_i : req1_i && we1_i;
// hookup generic synchronous single port memory
generic_spram #(AWIDTH, DWIDTH) clut_mem(
.clk(clk_i),
.rst(1'b0), // no reset
.ce(1'b1), // always enable memory
.we(mem_we),
.oe(1'b1), // always output data
.addr(mem_adr),
.di(mem_d),
.do(mem_q)
);
// assign DAT_O outputs
assign dat0_o = mem_q;
assign dat1_o = mem_q;
// generate ack outputs
assign ack0_o = ( (sel0 && we0_i) || ack0 );
assign ack1_o = ( (sel1 && we1_i) || ack1 );
endmodule |
module vga_colproc(clk, srst, vdat_buffer_di, ColorDepth, PseudoColor,
vdat_buffer_empty, vdat_buffer_rreq, rgb_fifo_full,
rgb_fifo_wreq, r, g, b,
clut_req, clut_ack, clut_offs, clut_q
);
//
// inputs & outputs
//
input clk; // master clock
input srst; // synchronous reset
input [31:0] vdat_buffer_di; // video memory data input
input [1:0] ColorDepth; // color depth (8bpp, 16bpp, 24bpp)
input PseudoColor; // pseudo color enabled (only for 8bpp color depth)
input vdat_buffer_empty;
output vdat_buffer_rreq; // pixel buffer read request
reg vdat_buffer_rreq;
input rgb_fifo_full;
output rgb_fifo_wreq;
reg rgb_fifo_wreq;
output [7:0] r, g, b; // pixel color information
reg [7:0] r, g, b;
output clut_req; // clut request
reg clut_req;
input clut_ack; // clut acknowledge
output [ 7:0] clut_offs; // clut offset
reg [7:0] clut_offs;
input [23:0] clut_q; // clut data in
//
// variable declarations
//
reg [31:0] DataBuffer;
reg [7:0] Ra, Ga, Ba;
reg [1:0] colcnt;
reg RGBbuf_wreq;
//
// Module body
//
// store word from pixelbuffer / wishbone input
always @(posedge clk)
if (vdat_buffer_rreq)
DataBuffer <= #1 vdat_buffer_di;
//
// generate statemachine
//
// extract color information from data buffer
parameter idle = 7'b000_0000,
fill_buf = 7'b000_0001,
bw_8bpp = 7'b000_0010,
col_8bpp = 7'b000_0100,
col_16bpp_a = 7'b000_1000,
col_16bpp_b = 7'b001_0000,
col_24bpp = 7'b010_0000,
col_32bpp = 7'b100_0000;
reg [6:0] c_state; // xsynopsys enum_state
reg [6:0] nxt_state; // xsynopsys enum_state
// next state decoder
always @(c_state or vdat_buffer_empty or ColorDepth or PseudoColor or rgb_fifo_full or colcnt or clut_ack)
begin : nxt_state_decoder
// initial value
nxt_state = c_state;
case (c_state) // synopsis full_case parallel_case
// idle state
idle:
if (!vdat_buffer_empty && !rgb_fifo_full)
nxt_state = fill_buf;
// fill data buffer
fill_buf:
case (ColorDepth) // synopsis full_case parallel_case
2'b00:
if (PseudoColor)
nxt_state = col_8bpp;
else
nxt_state = bw_8bpp;
2'b01:
nxt_state = col_16bpp_a;
2'b10:
nxt_state = col_24bpp;
2'b11:
nxt_state = col_32bpp;
endcase
//
// 8 bits per pixel
//
bw_8bpp:
if (!rgb_fifo_full && !(|colcnt) )
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
col_8bpp:
// Do NOT check for rgb_fifo_full here.
// In 8bpp pseudo-color mode the color-processor must always finish
// the current 4pixel-block(i.e. it runs until colcnt = '11').
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
// Because of this we can not do an early video_memory_data fetch,
// i.e. we can not jump to the fill_buf state. Instead we always
// jump to idle and check for rgb_fifo_full there.
//
// The addition of the cursor-processors forces us to increase the
// rgb-fifo size. The increased rgb-fifo also handles the above
// described problem. Thus erradicating the above comment.
// We add the early video_memory_data fetch again.
if (!(|colcnt))
if (!vdat_buffer_empty && !rgb_fifo_full)
nxt_state = fill_buf;
else
nxt_state = idle;
//
// 16 bits per pixel
//
col_16bpp_a:
if (!rgb_fifo_full)
nxt_state = col_16bpp_b;
col_16bpp_b:
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
//
// 24 bits per pixel
//
col_24bpp:
if (!rgb_fifo_full)
if (colcnt == 2'h1) // (colcnt == 1)
nxt_state = col_24bpp; // stay in current state
else if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
//
// 32 bits per pixel
//
col_32bpp:
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
nxt_state = fill_buf;
else
nxt_state = idle;
endcase
end // next state decoder
// generate state registers
always @(posedge clk)
if (srst)
c_state <= #1 idle;
else
c_state <= #1 nxt_state;
reg iclut_req;
reg ivdat_buf_rreq;
reg [7:0] iR, iG, iB, iRa, iGa, iBa;
// output decoder
always @(c_state or vdat_buffer_empty or colcnt or DataBuffer or rgb_fifo_full or clut_ack or clut_q or Ba or Ga or Ra)
begin : output_decoder
// initial values
ivdat_buf_rreq = 1'b0;
RGBbuf_wreq = 1'b0;
iclut_req = 1'b0;
iR = 'h0;
iG = 'h0;
iB = 'h0;
iRa = 'h0;
iGa = 'h0;
iBa = 'h0;
case (c_state) // synopsis full_case parallel_case
idle:
begin
if (!rgb_fifo_full)
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
// when entering from 8bpp_pseudo_color_mode
RGBbuf_wreq = clut_ack;
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
end
fill_buf:
begin
// when entering from 8bpp_pseudo_color_mode
RGBbuf_wreq = clut_ack;
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
end
//
// 8 bits per pixel
//
bw_8bpp:
begin
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
if ( (!vdat_buffer_empty) && !(|colcnt) )
ivdat_buf_rreq = 1'b1;
end
case (colcnt) // synopsis full_case parallel_case
2'b11:
begin
iR = DataBuffer[31:24];
iG = DataBuffer[31:24];
iB = DataBuffer[31:24];
end
2'b10:
begin
iR = DataBuffer[23:16];
iG = DataBuffer[23:16];
iB = DataBuffer[23:16];
end
2'b01:
begin
iR = DataBuffer[15:8];
iG = DataBuffer[15:8];
iB = DataBuffer[15:8];
end
default:
begin
iR = DataBuffer[7:0];
iG = DataBuffer[7:0];
iB = DataBuffer[7:0];
end
endcase
end
col_8bpp:
begin
// Do NOT check for rgb_fifo_full here.
// In 8bpp pseudo-color mode the color-processor must always finish
// the current 4pixel-block(i.e. it runs until colcnt = '11').
// This is because of the late clut-response which shuffles all
// signals the state-machine depends on.
// Because of this we can not do an early video_memory_data fetch,
// i.e. we can not jump to the fill_buf state. Instead we always
// jump to idle and check for rgb_fifo_full there.
//
// The addition of the cursor-processors forces us to increase the
// rgb-fifo size. The increased rgb-fifo also handles the above
// described problem. Thus erradicating the above comment.
// We add the early video_memory_data fetch again.
if (!(|colcnt))
if (!vdat_buffer_empty && !rgb_fifo_full)
ivdat_buf_rreq = 1'b1;
RGBbuf_wreq = clut_ack;
iR = clut_q[23:16];
iG = clut_q[15: 8];
iB = clut_q[ 7: 0];
iclut_req = !rgb_fifo_full || (colcnt[1] ^ colcnt[0]);
end
//
// 16 bits per pixel
//
col_16bpp_a:
begin
if (!rgb_fifo_full)
RGBbuf_wreq = 1'b1;
iR[7:3] = DataBuffer[31:27];
iG[7:2] = DataBuffer[26:21];
iB[7:3] = DataBuffer[20:16];
end
col_16bpp_b:
begin
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
iR[7:3] = DataBuffer[15:11];
iG[7:2] = DataBuffer[10: 5];
iB[7:3] = DataBuffer[ 4: 0];
end
//
// 24 bits per pixel
//
col_24bpp:
begin
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
if ( (colcnt != 2'h1) && !vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
case (colcnt) // synopsis full_case parallel_case
2'b11:
begin
iR = DataBuffer[31:24];
iG = DataBuffer[23:16];
iB = DataBuffer[15: 8];
iRa = DataBuffer[ 7: 0];
end
2'b10:
begin
iR = Ra;
iG = DataBuffer[31:24];
iB = DataBuffer[23:16];
iRa = DataBuffer[15: 8];
iGa = DataBuffer[ 7: 0];
end
2'b01:
begin
iR = Ra;
iG = Ga;
iB = DataBuffer[31:24];
iRa = DataBuffer[23:16];
iGa = DataBuffer[15: 8];
iBa = DataBuffer[ 7: 0];
end
default:
begin
iR = Ra;
iG = Ga;
iB = Ba;
end
endcase
end
//
// 32 bits per pixel
//
col_32bpp:
begin
if (!rgb_fifo_full)
begin
RGBbuf_wreq = 1'b1;
if (!vdat_buffer_empty)
ivdat_buf_rreq = 1'b1;
end
iR[7:0] = DataBuffer[23:16];
iG[7:0] = DataBuffer[15:8];
iB[7:0] = DataBuffer[7:0];
end
endcase
end // output decoder
// generate output registers
always @(posedge clk)
begin
r <= #1 iR;
g <= #1 iG;
b <= #1 iB;
if (RGBbuf_wreq)
begin
Ra <= #1 iRa;
Ba <= #1 iBa;
Ga <= #1 iGa;
end
if (srst)
begin
vdat_buffer_rreq <= #1 1'b0;
rgb_fifo_wreq <= #1 1'b0;
clut_req <= #1 1'b0;
end
else
begin
vdat_buffer_rreq <= #1 ivdat_buf_rreq;
rgb_fifo_wreq <= #1 RGBbuf_wreq;
clut_req <= #1 iclut_req;
end
end
// assign clut offset
always @(colcnt or DataBuffer)
case (colcnt) // synopsis full_case parallel_case
2'b11: clut_offs = DataBuffer[31:24];
2'b10: clut_offs = DataBuffer[23:16];
2'b01: clut_offs = DataBuffer[15: 8];
2'b00: clut_offs = DataBuffer[ 7: 0];
endcase
//
// color counter
//
always @(posedge clk)
if (srst)
colcnt <= #1 2'b11;
else if (RGBbuf_wreq)
colcnt <= #1 colcnt -2'h1;
endmodule |
module vga_wb_slave(
clk_i, rst_i, arst_i, adr_i, dat_i, dat_o, sel_i, we_i, stb_i, cyc_i, ack_o, rty_o, err_o, inta_o,
wbm_busy, dvi_odf, bl, csl, vsl, hsl, pc, cd, vbl, cbsw, vbsw, ven, avmp, acmp,
cursor0_res, cursor0_en, cursor0_xy, cursor0_ba, cursor0_ld, cc0_adr_i, cc0_dat_o,
cursor1_res, cursor1_en, cursor1_xy, cursor1_ba, cursor1_ld, cc1_adr_i, cc1_dat_o,
vbsint_in, cbsint_in, hint_in, vint_in, luint_in, sint_in,
Thsync, Thgdel, Thgate, Thlen, Tvsync, Tvgdel, Tvgate, Tvlen, VBARa, VBARb,
clut_acc, clut_ack, clut_q
);
//
// inputs & outputs
//
// wishbone slave interface
input clk_i;
input rst_i;
input arst_i;
input [11:2] adr_i;
input [31:0] dat_i;
output [31:0] dat_o;
reg [31:0] dat_o;
input [ 3:0] sel_i;
input we_i;
input stb_i;
input cyc_i;
output ack_o;
reg ack_o;
output rty_o;
reg rty_o;
output err_o;
reg err_o;
output inta_o;
reg inta_o;
// wishbone master controller feedback
input wbm_busy; // data transfer in progress
// control register settings
output [1:0] dvi_odf; // DVI output data format
output bl; // blanking level
output csl; // composite sync level
output vsl; // vsync level
output hsl; // hsync level
output pc; // pseudo color
output [1:0] cd; // color depth
output [1:0] vbl; // video memory burst length
output cbsw; // clut bank switch enable
output vbsw; // video memory bank switch enable
output ven; // video system enable
// hardware cursor settings
output cursor0_res; // cursor0 resolution
output cursor0_en; // cursor0 enable
output [31: 0] cursor0_xy; // cursor0 location
output [31:11] cursor0_ba; // cursor0 base address
output cursor0_ld; // reload cursor0 from video memory
input [ 3: 0] cc0_adr_i; // cursor0 color register address
output [15: 0] cc0_dat_o; // cursor0 color register data
output cursor1_res; // cursor1 resolution
output cursor1_en; // cursor1 enable
output [31: 0] cursor1_xy; // cursor1 location
output [31:11] cursor1_ba; // cursor1 base address
output cursor1_ld; // reload cursor1 from video memory
input [ 3: 0] cc1_adr_i; // cursor1 color register address
output [15: 0] cc1_dat_o; // cursor1 color register data
reg [31: 0] cursor0_xy;
reg [31:11] cursor0_ba;
reg cursor0_ld;
reg [31: 0] cursor1_xy;
reg [31:11] cursor1_ba;
reg cursor1_ld;
// status register inputs
input avmp; // active video memory page
input acmp; // active clut memory page
input vbsint_in; // bank switch interrupt request
input cbsint_in; // clut switch interrupt request
input hint_in; // hsync interrupt request
input vint_in; // vsync interrupt request
input luint_in; // line fifo underrun interrupt request
input sint_in; // system error interrupt request
// Horizontal Timing Register
output [ 7:0] Thsync;
output [ 7:0] Thgdel;
output [15:0] Thgate;
output [15:0] Thlen;
// Vertical Timing Register
output [ 7:0] Tvsync;
output [ 7:0] Tvgdel;
output [15:0] Tvgate;
output [15:0] Tvlen;
// video base addresses
output [31:2] VBARa;
reg [31:2] VBARa;
output [31:2] VBARb;
reg [31:2] VBARb;
// color lookup table signals
output clut_acc;
input clut_ack;
input [23:0] clut_q;
//
// variable declarations
//
parameter REG_ADR_HIBIT = 7;
wire [REG_ADR_HIBIT:0] REG_ADR = adr_i[REG_ADR_HIBIT : 2];
wire CLUT_ADR = adr_i[11];
parameter [REG_ADR_HIBIT : 0] CTRL_ADR = 6'b00_0000;
parameter [REG_ADR_HIBIT : 0] STAT_ADR = 6'b00_0001;
parameter [REG_ADR_HIBIT : 0] HTIM_ADR = 6'b00_0010;
parameter [REG_ADR_HIBIT : 0] VTIM_ADR = 6'b00_0011;
parameter [REG_ADR_HIBIT : 0] HVLEN_ADR = 6'b00_0100;
parameter [REG_ADR_HIBIT : 0] VBARA_ADR = 6'b00_0101;
parameter [REG_ADR_HIBIT : 0] VBARB_ADR = 6'b00_0110;
parameter [REG_ADR_HIBIT : 0] C0XY_ADR = 6'b00_1100;
parameter [REG_ADR_HIBIT : 0] C0BAR_ADR = 6'b00_1101;
parameter [REG_ADR_HIBIT : 0] CCR0_ADR = 6'b01_0???;
parameter [REG_ADR_HIBIT : 0] C1XY_ADR = 6'b01_1100;
parameter [REG_ADR_HIBIT : 0] C1BAR_ADR = 6'b01_1101;
parameter [REG_ADR_HIBIT : 0] CCR1_ADR = 6'b10_0???;
reg [31:0] ctrl, stat, htim, vtim, hvlen;
wire hint, vint, vbsint, cbsint, luint, sint;
wire hie, vie, vbsie, cbsie;
wire acc, acc32, reg_acc, reg_wacc;
wire cc0_acc, cc1_acc;
wire [31:0] ccr0_dat_o, ccr1_dat_o;
reg [31:0] reg_dato; // data output from registers
//
// Module body
//
assign acc = cyc_i & stb_i;
assign acc32 = (sel_i == 4'b1111);
assign clut_acc = CLUT_ADR & acc & acc32;
assign reg_acc = ~CLUT_ADR & acc & acc32;
assign reg_wacc = reg_acc & we_i;
assign cc0_acc = (REG_ADR == CCR0_ADR) & acc & acc32;
assign cc1_acc = (REG_ADR == CCR1_ADR) & acc & acc32;
always @(posedge clk_i)
ack_o <= #1 ((reg_acc & acc32) | clut_ack) & ~(wbm_busy & REG_ADR == CTRL_ADR) & ~ack_o ;
always @(posedge clk_i)
rty_o <= #1 ((reg_acc & acc32) | clut_ack) & (wbm_busy & REG_ADR == CTRL_ADR) & ~rty_o ;
always @(posedge clk_i)
err_o <= #1 acc & ~acc32 & ~err_o;
// generate registers
always @(posedge clk_i or negedge arst_i)
begin : gen_regs
if (!arst_i)
begin
htim <= #1 0;
vtim <= #1 0;
hvlen <= #1 0;
VBARa <= #1 0;
VBARb <= #1 0;
cursor0_xy <= #1 0;
cursor0_ba <= #1 0;
cursor1_xy <= #1 0;
cursor1_ba <= #1 0;
end
else if (rst_i)
begin
htim <= #1 0;
vtim <= #1 0;
hvlen <= #1 0;
VBARa <= #1 0;
VBARb <= #1 0;
cursor0_xy <= #1 0;
cursor0_ba <= #1 0;
cursor1_xy <= #1 0;
cursor1_ba <= #1 0;
end
else if (reg_wacc)
case (adr_i) // synopsis full_case parallel_case
HTIM_ADR : htim <= #1 dat_i;
VTIM_ADR : vtim <= #1 dat_i;
HVLEN_ADR : hvlen <= #1 dat_i;
VBARA_ADR : VBARa <= #1 dat_i[31: 2];
VBARB_ADR : VBARb <= #1 dat_i[31: 2];
C0XY_ADR : cursor0_xy <= #1 dat_i[31: 0];
C0BAR_ADR : cursor0_ba <= #1 dat_i[31:11];
C1XY_ADR : cursor1_xy <= #1 dat_i[31: 0];
C1BAR_ADR : cursor1_ba <= #1 dat_i[31:11];
endcase
end
always @(posedge clk_i)
begin
cursor0_ld <= #1 reg_wacc && (adr_i == C0BAR_ADR);
cursor1_ld <= #1 reg_wacc && (adr_i == C1BAR_ADR);
end
// generate control register
always @(posedge clk_i or negedge arst_i)
if (!arst_i)
ctrl <= #1 0;
else if (rst_i)
ctrl <= #1 0;
else if (reg_wacc & (REG_ADR == CTRL_ADR) & ~wbm_busy )
ctrl <= #1 dat_i;
else begin
ctrl[6] <= #1 ctrl[6] & !cbsint_in;
ctrl[5] <= #1 ctrl[5] & !vbsint_in;
end
// generate status register
always @(posedge clk_i or negedge arst_i)
if (!arst_i)
stat <= #1 0;
else if (rst_i)
stat <= #1 0;
else begin
`ifdef VGA_HWC1
stat[21] <= #1 1'b1;
`else
stat[21] <= #1 1'b0;
`endif
`ifdef VGA_HWC0
stat[20] <= #1 1'b1;
`else
stat[20] <= #1 1'b0;
`endif
stat[17] <= #1 acmp;
stat[16] <= #1 avmp;
if (reg_wacc & (REG_ADR == STAT_ADR) )
begin
stat[7] <= #1 cbsint_in | (stat[7] & !dat_i[7]);
stat[6] <= #1 vbsint_in | (stat[6] & !dat_i[6]);
stat[5] <= #1 hint_in | (stat[5] & !dat_i[5]);
stat[4] <= #1 vint_in | (stat[4] & !dat_i[4]);
stat[1] <= #1 luint_in | (stat[3] & !dat_i[1]);
stat[0] <= #1 sint_in | (stat[0] & !dat_i[0]);
end
else
begin
stat[7] <= #1 stat[7] | cbsint_in;
stat[6] <= #1 stat[6] | vbsint_in;
stat[5] <= #1 stat[5] | hint_in;
stat[4] <= #1 stat[4] | vint_in;
stat[1] <= #1 stat[1] | luint_in;
stat[0] <= #1 stat[0] | sint_in;
end
end
// decode control register
assign dvi_odf = ctrl[29:28];
assign cursor1_res = ctrl[25];
assign cursor1_en = ctrl[24];
assign cursor0_res = ctrl[23];
assign cursor0_en = ctrl[20];
assign bl = ctrl[15];
assign csl = ctrl[14];
assign vsl = ctrl[13];
assign hsl = ctrl[12];
assign pc = ctrl[11];
assign cd = ctrl[10:9];
assign vbl = ctrl[8:7];
assign cbsw = ctrl[6];
assign vbsw = ctrl[5];
assign cbsie = ctrl[4];
assign vbsie = ctrl[3];
assign hie = ctrl[2];
assign vie = ctrl[1];
assign ven = ctrl[0];
// decode status register
assign cbsint = stat[7];
assign vbsint = stat[6];
assign hint = stat[5];
assign vint = stat[4];
assign luint = stat[1];
assign sint = stat[0];
// decode Horizontal Timing Register
assign Thsync = htim[31:24];
assign Thgdel = htim[23:16];
assign Thgate = htim[15:0];
assign Thlen = hvlen[31:16];
// decode Vertical Timing Register
assign Tvsync = vtim[31:24];
assign Tvgdel = vtim[23:16];
assign Tvgate = vtim[15:0];
assign Tvlen = hvlen[15:0];
`ifdef VGA_HWC0
// hookup cursor0 color registers
vga_cur_cregs cregs0(
.clk_i(clk_i),
.rst_i(rst_i),
.arst_i(arst_i),
.hsel_i(cc0_acc),
.hadr_i(adr_i[4:2]),
.hwe_i(we_i),
.hdat_i(dat_i),
.hdat_o(ccr0_dat_o), // host access
.hack_o(),
.cadr_i(cc0_adr_i),
.cdat_o(cc0_dat_o) // cursor processor access
);
`else
assign ccr0_dat_o = 32'h0;
assign cc0_dat_o = 32'h0;
`endif
`ifdef VGA_HWC1
// hookup cursor1 color registers
vga_cur_cregs cregs1(
.clk_i(clk_i),
.rst_i(rst_i),
.arst_i(arst_i),
.hsel_i(cc1_acc),
.hadr_i(adr_i[4:2]),
.hwe_i(we_i),
.hdat_i(dat_i),
.hdat_o(ccr1_dat_o), // host access
.hack_o(),
.cadr_i(cc1_adr_i),
.cdat_o(cc1_dat_o) // cursor processor access
);
`else
assign ccr1_dat_o = 32'h0;
assign cc1_dat_o = 32'h0;
`endif
// assign output
always @(REG_ADR or ctrl or stat or htim or vtim or hvlen or VBARa or VBARb or acmp or
cursor0_xy or cursor0_ba or cursor1_xy or cursor1_ba or ccr0_dat_o or ccr1_dat_o)
casez (REG_ADR) // synopsis full_case parallel_case
CTRL_ADR : reg_dato = ctrl;
STAT_ADR : reg_dato = stat;
HTIM_ADR : reg_dato = htim;
VTIM_ADR : reg_dato = vtim;
HVLEN_ADR : reg_dato = hvlen;
VBARA_ADR : reg_dato = {VBARa, 2'b0};
VBARB_ADR : reg_dato = {VBARb, 2'b0};
C0XY_ADR : reg_dato = cursor0_xy;
C0BAR_ADR : reg_dato = {cursor0_ba, 11'h0};
CCR0_ADR : reg_dato = ccr0_dat_o;
C1XY_ADR : reg_dato = cursor1_xy;
C1BAR_ADR : reg_dato = {cursor1_ba, 11'h0};
CCR1_ADR : reg_dato = ccr1_dat_o;
default : reg_dato = 32'h0000_0000;
endcase
always @(posedge clk_i)
dat_o <= #1 reg_acc ? reg_dato : {8'h0, clut_q};
// generate interrupt request signal
always @(posedge clk_i)
inta_o <= #1 (hint & hie) | (vint & vie) | (vbsint & vbsie) | (cbsint & cbsie) | luint | sint;
endmodule |
module picosoc (
input clk,
input resetn,
output iomem_valid,
input iomem_ready,
output [ 3:0] iomem_wstrb,
output [31:0] iomem_addr,
output [31:0] iomem_wdata,
input [31:0] iomem_rdata,
input irq_5,
input irq_6,
input irq_7,
output ser_tx,
input ser_rx,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
parameter [0:0] BARREL_SHIFTER = 1;
parameter [0:0] ENABLE_MULDIV = 1;
parameter [0:0] ENABLE_COMPRESSED = 1;
parameter [0:0] ENABLE_COUNTERS = 1;
parameter [0:0] ENABLE_IRQ_QREGS = 0;
parameter integer MEM_WORDS = 256;
parameter [31:0] STACKADDR = (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0010_0000; // 1 MB into flash
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
reg [31:0] irq;
wire irq_stall = 0;
wire irq_uart = 0;
always @* begin
irq = 0;
irq[3] = irq_stall;
irq[4] = irq_uart;
irq[5] = irq_5;
irq[6] = irq_6;
irq[7] = irq_7;
end
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
wire spimem_ready;
wire [31:0] spimem_rdata;
reg ram_ready;
wire [31:0] ram_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire spimemio_cfgreg_sel = mem_valid && (mem_addr == 32'h 0200_0000);
wire [31:0] spimemio_cfgreg_do;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
assign mem_ready = (iomem_valid && iomem_ready) || spimem_ready || ram_ready || spimemio_cfgreg_sel ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait);
assign mem_rdata = (iomem_valid && iomem_ready) ? iomem_rdata : spimem_ready ? spimem_rdata : ram_ready ? ram_rdata :
spimemio_cfgreg_sel ? spimemio_cfgreg_do : simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do : 32'h 0000_0000;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(PROGADDR_IRQ),
.BARREL_SHIFTER(BARREL_SHIFTER),
.COMPRESSED_ISA(ENABLE_COMPRESSED),
.ENABLE_COUNTERS(ENABLE_COUNTERS),
.ENABLE_MUL(ENABLE_MULDIV),
.ENABLE_DIV(ENABLE_MULDIV),
.ENABLE_IRQ(1),
.ENABLE_IRQ_QREGS(ENABLE_IRQ_QREGS)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq (irq )
);
spimemio spimemio (
.clk (clk),
.resetn (resetn),
.valid (mem_valid && mem_addr >= 4*MEM_WORDS && mem_addr < 32'h 0200_0000),
.ready (spimem_ready),
.addr (mem_addr[23:0]),
.rdata (spimem_rdata),
.flash_csb (flash_csb ),
.flash_clk (flash_clk ),
.flash_io0_oe (flash_io0_oe),
.flash_io1_oe (flash_io1_oe),
.flash_io2_oe (flash_io2_oe),
.flash_io3_oe (flash_io3_oe),
.flash_io0_do (flash_io0_do),
.flash_io1_do (flash_io1_do),
.flash_io2_do (flash_io2_do),
.flash_io3_do (flash_io3_do),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di),
.cfgreg_we(spimemio_cfgreg_sel ? mem_wstrb : 4'b 0000),
.cfgreg_di(mem_wdata),
.cfgreg_do(spimemio_cfgreg_do)
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (ser_tx ),
.ser_rx (ser_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
always @(posedge clk)
ram_ready <= mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS;
`PICOSOC_MEM #(
.WORDS(MEM_WORDS)
) memory (
.clk(clk),
.wen((mem_valid && !mem_ready && mem_addr < 4*MEM_WORDS) ? mem_wstrb : 4'b0),
.addr(mem_addr[23:2]),
.wdata(mem_wdata),
.rdata(ram_rdata)
);
endmodule |
module picosoc_mem #(
parameter integer WORDS = 256
) (
input clk,
input [3:0] wen,
input [21:0] addr,
input [31:0] wdata,
output reg [31:0] rdata
);
reg [31:0] mem [0:WORDS-1];
always @(posedge clk) begin
rdata <= mem[addr];
if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
if (wen[2]) mem[addr][23:16] <= wdata[23:16];
if (wen[3]) mem[addr][31:24] <= wdata[31:24];
end
endmodule |
module spimemio (
input clk, resetn,
input valid,
output ready,
input [23:0] addr,
output reg [31:0] rdata,
output flash_csb,
output flash_clk,
output flash_io0_oe,
output flash_io1_oe,
output flash_io2_oe,
output flash_io3_oe,
output flash_io0_do,
output flash_io1_do,
output flash_io2_do,
output flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di,
input [3:0] cfgreg_we,
input [31:0] cfgreg_di,
output [31:0] cfgreg_do
);
reg xfer_resetn;
reg din_valid;
wire din_ready;
reg [7:0] din_data;
reg [3:0] din_tag;
reg din_cont;
reg din_qspi;
reg din_ddr;
reg din_rd;
wire dout_valid;
wire [7:0] dout_data;
wire [3:0] dout_tag;
reg [23:0] buffer;
reg [23:0] rd_addr;
reg rd_valid;
reg rd_wait;
reg rd_inc;
assign ready = valid && (addr == rd_addr) && rd_valid;
wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid;
reg softreset;
reg config_en; // cfgreg[31]
reg config_ddr; // cfgreg[22]
reg config_qspi; // cfgreg[21]
reg config_cont; // cfgreg[20]
reg [3:0] config_dummy; // cfgreg[19:16]
reg [3:0] config_oe; // cfgreg[11:8]
reg config_csb; // cfgreg[5]
reg config_clk; // cfgref[4]
reg [3:0] config_do; // cfgreg[3:0]
assign cfgreg_do[31] = config_en;
assign cfgreg_do[30:23] = 0;
assign cfgreg_do[22] = config_ddr;
assign cfgreg_do[21] = config_qspi;
assign cfgreg_do[20] = config_cont;
assign cfgreg_do[19:16] = config_dummy;
assign cfgreg_do[15:12] = 0;
assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe};
assign cfgreg_do[7:6] = 0;
assign cfgreg_do[5] = flash_csb;
assign cfgreg_do[4] = flash_clk;
assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
always @(posedge clk) begin
softreset <= !config_en || cfgreg_we;
if (!resetn) begin
softreset <= 1;
config_en <= 1;
config_csb <= 0;
config_clk <= 0;
config_oe <= 0;
config_do <= 0;
config_ddr <= 0;
config_qspi <= 0;
config_cont <= 0;
config_dummy <= 8;
end else begin
if (cfgreg_we[0]) begin
config_csb <= cfgreg_di[5];
config_clk <= cfgreg_di[4];
config_do <= cfgreg_di[3:0];
end
if (cfgreg_we[1]) begin
config_oe <= cfgreg_di[11:8];
end
if (cfgreg_we[2]) begin
config_ddr <= cfgreg_di[22];
config_qspi <= cfgreg_di[21];
config_cont <= cfgreg_di[20];
config_dummy <= cfgreg_di[19:16];
end
if (cfgreg_we[3]) begin
config_en <= cfgreg_di[31];
end
end
end
wire xfer_csb;
wire xfer_clk;
wire xfer_io0_oe;
wire xfer_io1_oe;
wire xfer_io2_oe;
wire xfer_io3_oe;
wire xfer_io0_do;
wire xfer_io1_do;
wire xfer_io2_do;
wire xfer_io3_do;
reg xfer_io0_90;
reg xfer_io1_90;
reg xfer_io2_90;
reg xfer_io3_90;
always @(negedge clk) begin
xfer_io0_90 <= xfer_io0_do;
xfer_io1_90 <= xfer_io1_do;
xfer_io2_90 <= xfer_io2_do;
xfer_io3_90 <= xfer_io3_do;
end
assign flash_csb = config_en ? xfer_csb : config_csb;
assign flash_clk = config_en ? xfer_clk : config_clk;
assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0];
assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1];
assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2];
assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3];
assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0];
assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1];
assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2];
assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3];
wire xfer_dspi = din_ddr && !din_qspi;
wire xfer_ddr = din_ddr && din_qspi;
spimemio_xfer xfer (
.clk (clk ),
.resetn (xfer_resetn ),
.din_valid (din_valid ),
.din_ready (din_ready ),
.din_data (din_data ),
.din_tag (din_tag ),
.din_cont (din_cont ),
.din_dspi (xfer_dspi ),
.din_qspi (din_qspi ),
.din_ddr (xfer_ddr ),
.din_rd (din_rd ),
.dout_valid (dout_valid ),
.dout_data (dout_data ),
.dout_tag (dout_tag ),
.flash_csb (xfer_csb ),
.flash_clk (xfer_clk ),
.flash_io0_oe (xfer_io0_oe ),
.flash_io1_oe (xfer_io1_oe ),
.flash_io2_oe (xfer_io2_oe ),
.flash_io3_oe (xfer_io3_oe ),
.flash_io0_do (xfer_io0_do ),
.flash_io1_do (xfer_io1_do ),
.flash_io2_do (xfer_io2_do ),
.flash_io3_do (xfer_io3_do ),
.flash_io0_di (flash_io0_di),
.flash_io1_di (flash_io1_di),
.flash_io2_di (flash_io2_di),
.flash_io3_di (flash_io3_di)
);
reg [3:0] state;
always @(posedge clk) begin
xfer_resetn <= 1;
din_valid <= 0;
if (!resetn || softreset) begin
state <= 0;
xfer_resetn <= 0;
rd_valid <= 0;
din_tag <= 0;
din_cont <= 0;
din_qspi <= 0;
din_ddr <= 0;
din_rd <= 0;
end else begin
if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data;
if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data;
if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data;
if (dout_valid && dout_tag == 4) begin
rdata <= {dout_data, buffer};
rd_addr <= rd_inc ? rd_addr + 4 : addr;
rd_valid <= 1;
rd_wait <= rd_inc;
rd_inc <= 1;
end
if (valid)
rd_wait <= 0;
case (state)
0: begin
din_valid <= 1;
din_data <= 8'h ff;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 1;
end
end
1: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 2;
end
end
2: begin
din_valid <= 1;
din_data <= 8'h ab;
din_tag <= 0;
if (din_ready) begin
din_valid <= 0;
state <= 3;
end
end
3: begin
if (dout_valid) begin
xfer_resetn <= 0;
state <= 4;
end
end
4: begin
rd_inc <= 0;
din_valid <= 1;
din_tag <= 0;
case ({config_ddr, config_qspi})
2'b11: din_data <= 8'h ED;
2'b01: din_data <= 8'h EB;
2'b10: din_data <= 8'h BB;
2'b00: din_data <= 8'h 03;
endcase
if (din_ready) begin
din_valid <= 0;
state <= 5;
end
end
5: begin
if (valid && !ready) begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[23:16];
din_qspi <= config_qspi;
din_ddr <= config_ddr;
if (din_ready) begin
din_valid <= 0;
state <= 6;
end
end
end
6: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[15:8];
if (din_ready) begin
din_valid <= 0;
state <= 7;
end
end
7: begin
din_valid <= 1;
din_tag <= 0;
din_data <= addr[7:0];
if (din_ready) begin
din_valid <= 0;
din_data <= 0;
state <= config_qspi || config_ddr ? 8 : 9;
end
end
8: begin
din_valid <= 1;
din_tag <= 0;
din_data <= config_cont ? 8'h A5 : 8'h FF;
if (din_ready) begin
din_rd <= 1;
din_data <= config_dummy;
din_valid <= 0;
state <= 9;
end
end
9: begin
din_valid <= 1;
din_tag <= 1;
if (din_ready) begin
din_valid <= 0;
state <= 10;
end
end
10: begin
din_valid <= 1;
din_data <= 8'h 00;
din_tag <= 2;
if (din_ready) begin
din_valid <= 0;
state <= 11;
end
end
11: begin
din_valid <= 1;
din_tag <= 3;
if (din_ready) begin
din_valid <= 0;
state <= 12;
end
end
12: begin
if (!rd_wait || valid) begin
din_valid <= 1;
din_tag <= 4;
if (din_ready) begin
din_valid <= 0;
state <= 9;
end
end
end
endcase
if (jump) begin
rd_inc <= 0;
rd_valid <= 0;
xfer_resetn <= 0;
if (config_cont) begin
state <= 5;
end else begin
state <= 4;
din_qspi <= 0;
din_ddr <= 0;
end
din_rd <= 0;
end
end
end
endmodule |
module spimemio_xfer (
input clk, resetn,
input din_valid,
output din_ready,
input [7:0] din_data,
input [3:0] din_tag,
input din_cont,
input din_dspi,
input din_qspi,
input din_ddr,
input din_rd,
output dout_valid,
output [7:0] dout_data,
output [3:0] dout_tag,
output reg flash_csb,
output reg flash_clk,
output reg flash_io0_oe,
output reg flash_io1_oe,
output reg flash_io2_oe,
output reg flash_io3_oe,
output reg flash_io0_do,
output reg flash_io1_do,
output reg flash_io2_do,
output reg flash_io3_do,
input flash_io0_di,
input flash_io1_di,
input flash_io2_di,
input flash_io3_di
);
reg [7:0] obuffer;
reg [7:0] ibuffer;
reg [3:0] count;
reg [3:0] dummy_count;
reg xfer_cont;
reg xfer_dspi;
reg xfer_qspi;
reg xfer_ddr;
reg xfer_ddr_q;
reg xfer_rd;
reg [3:0] xfer_tag;
reg [3:0] xfer_tag_q;
reg [7:0] next_obuffer;
reg [7:0] next_ibuffer;
reg [3:0] next_count;
reg fetch;
reg next_fetch;
reg last_fetch;
always @(posedge clk) begin
xfer_ddr_q <= xfer_ddr;
xfer_tag_q <= xfer_tag;
end
assign din_ready = din_valid && resetn && next_fetch;
assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn;
assign dout_data = ibuffer;
assign dout_tag = xfer_tag_q;
always @* begin
flash_io0_oe = 0;
flash_io1_oe = 0;
flash_io2_oe = 0;
flash_io3_oe = 0;
flash_io0_do = 0;
flash_io1_do = 0;
flash_io2_do = 0;
flash_io3_do = 0;
next_obuffer = obuffer;
next_ibuffer = ibuffer;
next_count = count;
next_fetch = 0;
if (dummy_count == 0) begin
casez ({xfer_ddr, xfer_qspi, xfer_dspi})
3'b 000: begin
flash_io0_oe = 1;
flash_io0_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[6:0], 1'b 0};
next_count = count - |count;
end else begin
next_ibuffer = {ibuffer[6:0], flash_io1_di};
end
next_fetch = (next_count == 0);
end
3'b 01?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[3:0], 4'b 0000};
next_count = count - {|count, 2'b00};
end else begin
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
3'b 11?: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io2_oe = !xfer_rd;
flash_io3_oe = !xfer_rd;
flash_io0_do = obuffer[4];
flash_io1_do = obuffer[5];
flash_io2_do = obuffer[6];
flash_io3_do = obuffer[7];
next_obuffer = {obuffer[3:0], 4'b 0000};
next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di};
next_count = count - {|count, 2'b00};
next_fetch = (next_count == 0);
end
3'b ??1: begin
flash_io0_oe = !xfer_rd;
flash_io1_oe = !xfer_rd;
flash_io0_do = obuffer[6];
flash_io1_do = obuffer[7];
if (flash_clk) begin
next_obuffer = {obuffer[5:0], 2'b 00};
next_count = count - {|count, 1'b0};
end else begin
next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di};
end
next_fetch = (next_count == 0);
end
endcase
end
end
always @(posedge clk) begin
if (!resetn) begin
fetch <= 1;
last_fetch <= 1;
flash_csb <= 1;
flash_clk <= 0;
count <= 0;
dummy_count <= 0;
xfer_tag <= 0;
xfer_cont <= 0;
xfer_dspi <= 0;
xfer_qspi <= 0;
xfer_ddr <= 0;
xfer_rd <= 0;
end else begin
fetch <= next_fetch;
last_fetch <= xfer_ddr ? fetch : 1;
if (dummy_count) begin
flash_clk <= !flash_clk && !flash_csb;
dummy_count <= dummy_count - flash_clk;
end else
if (count) begin
flash_clk <= !flash_clk && !flash_csb;
obuffer <= next_obuffer;
ibuffer <= next_ibuffer;
count <= next_count;
end
if (din_valid && din_ready) begin
flash_csb <= 0;
flash_clk <= 0;
count <= 8;
dummy_count <= din_rd ? din_data : 0;
obuffer <= din_data;
xfer_tag <= din_tag;
xfer_cont <= din_cont;
xfer_dspi <= din_dspi;
xfer_qspi <= din_qspi;
xfer_ddr <= din_ddr;
xfer_rd <= din_rd;
end
end
end
endmodule |
module top(
input SYSCLK,
output LED_RED,
output LED_BLUE,
output LED_GREEN
);
reg [2:0] led_reg;
reg [32:0] counter;
assign LED_RED = led_reg[0];
assign LED_BLUE = led_reg[1];
assign LED_GREEN = led_reg[2];
always @(posedge SYSCLK) begin
if (counter < 25000000)
counter <= counter + 1;
else begin
counter <= 0;
led_reg <= led_reg + 1;
end
end
endmodule |
module core (
ir_next,
ir_be,
// ir0, ir1,
// ir11, ir10, ir01, ir00,
// ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000,
// ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000,
of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001,
// offset,
// pc_next,
// pc_en,
// pc,
// len,
// imm,
// imm_en
// , cur_len
clk, reset_n
);
input clk, reset_n;
input [63:0] ir_next;
input [1:0] ir_be;
// input [3:0] pc_next;
// input pc_en;
// input imm_en;
// output [31:0] ir1, ir0;
// output [15:0] ir11, ir10, ir01, ir00;
// output [7:0] ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000;
// output [3:0] ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000;
output [3:0] of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001;
// output [3:0] offset;
// output [3:0] len;
// output [2:0] cur_len;
// output [3:0] pc;
// output [31:0] imm;
reg [63:0] ir;
reg [31:0] ir0, ir1;
// reg [15:0] ir11, ir10, ir01, ir00;
// reg [7:0] ir111, ir110, ir101, ir100, ir011, ir010, ir001, ir000;
// reg [3:0] ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000, ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000;
reg [3:0] of_r1101, of_r1100, of_r1011, of_r1010, of_r1001, of_r1000, of_r0111, of_r0110, of_r0101, of_r0100, of_r0011, of_r0010, of_r0001;
wire [3:0]
// of1111, of1110,
of1101, of1100, of1011, of1010, of1001, of1000,
of0111, of0110, of0101, of0100, of0011, of0010, of0001;
//, of0000;
// wire [3:0] offset;
// wire [2:0] cur_len;
// wire [31:0] imm_next;
// reg [3:0] len;
// reg [3:0] pc;
// reg [31:0] imm;
always @(posedge clk or negedge reset_n) if (~reset_n) ir0 <= 32'b0; else if (ir_be[0]) ir0 <= ir_next[31:0];
always @(posedge clk or negedge reset_n) if (~reset_n) ir1 <= 32'b0; else if (ir_be[1]) ir1 <= ir_next[63:32];
// always @(posedge clk or negedge reset_n) if (~reset_n) pc <= 4'b0; else if (pc_en) pc <= pc_next;
always @ (ir0, ir1) begin
// {ir11, ir10} = ir1;
// {ir01, ir00} = ir0;
//
// {ir111, ir110, ir101, ir100} = ir1;
// {ir011, ir010, ir001, ir000} = ir0;
//
// {ir1111, ir1110, ir1101, ir1100, ir1011, ir1010, ir1001, ir1000} = ir1;
// {ir0111, ir0110, ir0101, ir0100, ir0011, ir0010, ir0001, ir0000} = ir0;
// len = ir0000;
ir = {ir1, ir0};
end
tail_offset u_tail_offset (
.ir(ir), /* .pc(pc), .offset(offset), */
.of1101(of1101),
.of1100(of1100),
.of1011(of1011),
.of1010(of1010),
.of1001(of1001),
.of1000(of1000),
.of0111(of0111),
.of0110(of0110),
.of0101(of0101),
.of0100(of0100),
.of0011(of0011),
.of0010(of0010),
.of0001(of0001)
// , .len(cur_len)
// , .imm(imm_next)
);
// always @(posedge clk) if (imm_en) imm <= imm_next;
always @(posedge clk) of_r1101 <= of1101;
always @(posedge clk) of_r1100 <= of1100;
always @(posedge clk) of_r1011 <= of1011;
always @(posedge clk) of_r1010 <= of1010;
always @(posedge clk) of_r1001 <= of1001;
always @(posedge clk) of_r1000 <= of1000;
always @(posedge clk) of_r0111 <= of0111;
always @(posedge clk) of_r0110 <= of0110;
always @(posedge clk) of_r0101 <= of0101;
always @(posedge clk) of_r0100 <= of0100;
always @(posedge clk) of_r0011 <= of0011;
always @(posedge clk) of_r0010 <= of0010;
always @(posedge clk) of_r0001 <= of0001;
endmodule |
module mux16 #( parameter W = 1 ) (
sel,
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000,
o
);
input [3:0] sel;
input [W-1:0]
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000;
output [W-1:0] o;
reg [W-1:0] o;
always @ (
sel,
i1111,
i1110,
i1101,
i1100,
i1011,
i1010,
i1001,
i1000,
i0111,
i0110,
i0101,
i0100,
i0011,
i0010,
i0001,
i0000
) begin
case (sel)
0: o = i0000;
1: o = i0001;
2: o = i0010;
3: o = i0011;
4: o = i0100;
5: o = i0101;
6: o = i0110;
7: o = i0111;
8: o = i1000;
9: o = i1001;
10: o = i1010;
11: o = i1011;
12: o = i1100;
13: o = i1101;
14: o = i1110;
default o = i1111;
endcase
end
endmodule |
module tail_length (ir, len);
input [3:0] ir;
output [3:0] len;
reg [3:0] len;
reg ir32;
/*
..00 ..01 ..10 ..11
00.. 1 0 0 0
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
len[0] = (ir[3] & !ir[1]) | (!ir[1] & !ir[0]);
..00 ..01 ..10 ..11
00.. 0 1 0 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[1] = !ir[3] & !ir[2] & !ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 0 0 1 0
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[2] = !ir[3] & !ir[2] & ir[1] & !ir[0];
..00 ..01 ..10 ..11
00.. 0 0 0 1
01.. 0 ? ? 0
10.. 0 0 0 0
11.. 0 0 0 0
len[3] = !ir[3] & !ir[2] & ir[1] & ir[0];
..00 ..01 ..10 ..11
00.. 1 2 4 8
01.. 1 ? ? 0
10.. 1 1 0 0
11.. 1 1 0 0
*/
always @ (ir)
begin
len = {
(ir == 4'b0011),
(ir == 4'b0010),
(ir == 4'b0001),
((ir | 4'b0101) == 4'b1101) | ((ir | 4'b1100) == 4'b1100)
};
end
// 107.89 / 121.08
// always @ (ir)
// begin
// ir32 = |ir[3:2];
// len = {
// (!ir32 & ir[1] & ir[0]),
// (!ir32 & ir[1] & !ir[0]),
// (!ir32 & !ir[1] & ir[0]),
// ((ir[3] & !ir[1]) | (!ir[1] & !ir[0]))
// };
// end
// always @ (ir)
// casez (ir)
// 4'b??00: len = 1;
// 4'b1?0?: len = 1;
// 4'b0001: len = 2;
// 4'b0010: len = 4;
// 4'b0011: len = 8;
// default len = 0;
// endcase
endmodule |
module tail_offset (ir, toff_0_0, toff_1_0, toff_2_0, toff_3_0, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_8_0, toff_9_0, toff_10_0, toff_11_0, toff_12_0, toff_13_0, toff_14_0, toff_15_0);
input [63:0] ir;
output [3:0] toff_0_0, toff_1_0, toff_2_0, toff_3_0, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_8_0, toff_9_0, toff_10_0, toff_11_0, toff_12_0, toff_13_0, toff_14_0, toff_15_0;
reg [3:0] toff_0_0, toff_1_1, toff_2_2, toff_3_3, toff_4_4, toff_5_5, toff_6_6, toff_7_7, toff_8_8, toff_9_9, toff_10_10, toff_11_11, toff_12_12, toff_13_13, toff_14_14, toff_15_15;
reg [3:0] ir0, ir1, ir2, ir3, ir4, ir5, ir6, ir7, ir8, ir9, ir10, ir11, ir12, ir13, ir14, ir15;
reg [3:0] toff_1_0, toff_3_2, toff_2_0, toff_3_0, toff_5_4, toff_7_6, toff_6_4, toff_7_4, toff_4_0, toff_5_0, toff_6_0, toff_7_0, toff_9_8, toff_11_10, toff_10_8, toff_11_8, toff_8_0, toff_9_0, toff_10_0, toff_11_0;
wire [3:0] tlen_1, tlen_2, tlen_3, tlen_4, tlen_5, tlen_6, tlen_7, tlen_8, tlen_9, tlen_10, tlen_11, tlen_12, tlen_13, tlen_14;
tail_length u_len1 (.ir(ir1), .len(tlen_1));
tail_length u_len2 (.ir(ir2), .len(tlen_2));
tail_length u_len3 (.ir(ir3), .len(tlen_3));
tail_length u_len4 (.ir(ir4), .len(tlen_4));
tail_length u_len5 (.ir(ir5), .len(tlen_5));
tail_length u_len6 (.ir(ir6), .len(tlen_6));
tail_length u_len7 (.ir(ir7), .len(tlen_7));
tail_length u_len8 (.ir(ir8), .len(tlen_8));
tail_length u_len9 (.ir(ir9), .len(tlen_9));
tail_length u_len10 (.ir(ir10), .len(tlen_10));
tail_length u_len11 (.ir(ir11), .len(tlen_11));
tail_length u_len12 (.ir(ir12), .len(tlen_12));
tail_length u_len13 (.ir(ir13), .len(tlen_13));
always @ (ir) { ir15, ir14, ir13, ir12, ir11, ir10, ir9, ir8, ir7, ir6, ir5, ir4, ir3, ir2, ir1, ir0 } = ir;
always @ ( toff_0_0, toff_1_1, toff_2_2, toff_3_3, toff_4_4, toff_5_5, toff_6_6, toff_7_7, toff_8_8, toff_9_9, toff_10_10, toff_11_11 )
begin
toff_1_0 = toff_1_1 + toff_0_0;
toff_3_2 = toff_3_3 + toff_2_2;
toff_2_0 = toff_2_2 + toff_1_0;
toff_3_0 = toff_3_2 + toff_1_0;
toff_5_4 = toff_5_5 + toff_4_4;
toff_7_6 = toff_7_7 + toff_6_6;
toff_6_4 = toff_6_6 + toff_5_4;
toff_7_4 = toff_7_6 + toff_5_4;
toff_4_0 = toff_4_4 + toff_3_0;
toff_5_0 = toff_5_4 + toff_3_0;
toff_6_0 = toff_6_4 + toff_3_0;
toff_7_0 = toff_7_4 + toff_3_0;
toff_9_8 = toff_9_9 + toff_8_8;
toff_11_10 = toff_11_11 + toff_10_10;
toff_10_8 = toff_10_10 + toff_9_8;
toff_11_8 = toff_11_10 + toff_9_8;
toff_8_0 = toff_8_8 + toff_7_0;
toff_9_0 = toff_9_8 + toff_7_0;
toff_10_0 = toff_10_8 + toff_7_0;
toff_11_0 = toff_11_8 + toff_7_0;;
end
/*
mux16 #(.W(4)) u_offset_mux (
.sel(pc),
.i0000(of0001),
.i0001(of0010),
.i0010(of0011),
.i0011(of0100),
.i0100(of0101),
.i0101(of0110),
.i0110(of0111),
.i0111(of1000),
.i1000(of1001),
.i1001(of1010),
.i1010(of1011),
.i1011(of1100),
.i1100(of1101),
.i1101(4'b????),
.i1110(4'b????),
.i1111(4'b????),
.o(offset)
);
*/
/*
mux16 #(.W(3)) u_len_mux (
.sel(pc),
.i0000(len0001),
.i0001(len0010),
.i0010(len0011),
.i0011(len0100),
.i0100(len0101),
.i0101(len0110),
.i0110(len0111),
.i0111(len1000),
.i1000(len1001),
.i1001(len1010),
.i1010(len1011),
.i1011(len1100),
.i1100(len1101),
.i1101(len1110),
.i1110(len1111),
.i1111(len1111),
.o(len)
);
*/
/*
mux16 #(.W(4)) imm3_0_mux (
.sel(offset),
.i0000(ir1111),
.i0001(ir1110),
.i0010(ir1101),
.i0011(ir1100),
.i0100(ir1011),
.i0101(ir1010),
.i0110(ir1001),
.i0111(ir1000),
.i1000(ir0111),
.i1001(ir0110),
.i1010(ir0101),
.i1011(ir0100),
.i1100(4'b????),
.i1101(4'b????),
.i1110(4'b????),
.i1111(4'b????),
.o(imm3_0)
);
*/
/*
always @ (imm31_16, imm15_8, imm7_4, imm3_0) imm = {imm31_16, imm15_8, imm7_4, imm3_0};
*/
endmodule |
module usb_loopback (
input clk,
input [7:0] btn,
`ifdef BADGE_V3
output [10:0] ledc,
output [2:0] leda,
inout [29:0] genio,
`else
output [8:0] led,
inout [27:0] genio,
`endif
output uart_tx,
input uart_rx,
`ifdef BADGE_V3
output irda_tx,
input irda_rx,
output irda_sd,
`endif
output pwmout,
output [17:0] lcd_db,
output lcd_rd,
output lcd_wr,
output lcd_rs,
output lcd_cs,
input lcd_id,
output lcd_rst,
input lcd_fmark,
output lcd_blen,
output psrama_nce,
output psrama_sclk,
inout [3:0] psrama_sio,
output psramb_nce,
output psramb_sclk,
inout [3:0] psramb_sio,
output flash_cs,
inout flash_miso,
inout flash_mosi,
inout flash_wp,
inout flash_hold,
output fsel_d,
output fsel_c,
output programn,
output [3:0] gpdi_dp, gpdi_dn,
inout usb_dp,
inout usb_dm,
output usb_pu,
input usb_vdet,
inout [5:0] sao1,
inout [5:0] sao2,
inout [7:0] pmod,
output adcrefout,
input adcref4
);
//
// Clocks
//
// This is so Diamond can run something. It is insufficently accurate to run USB
/*
wire clkint;
OSCG #(
.DIV( 2 ) //155MHz approx
) oscint (
.OSC(clkint)
);
*/
wire clock_48mhz;
clock_pll c_pll (.CLKI( clk ), .CLKOP( clock_48mhz ));
//
// RESET
//
reg [5:0] reset_counter = 0;
wire reset = ~reset_counter[5];
always @(posedge clock_48mhz)
reset_counter <= reset_counter + reset;
//
// Config
//
reg fpga_reload=0;
assign programn = ~fpga_reload;
always @( posedge clock_48mhz )
if ( ~btn[4] )
fpga_reload <= 1;
//
// LED
//
reg [28:0] led_counter = 0;
always @( posedge clock_48mhz ) begin
if ( reset ) begin
end else begin
led_counter <= led_counter + 1'H1;
end
end
`ifdef BADGE_V3
assign ledc[ 8 ] = led_counter[ 25:19 ] == 0;
assign leda = 1;
`else
assign led[ 8 ] = led_counter[ 25:19 ] == 0;
`endif
//
// USB CDC ACM
//
// uart pipeline in and out
localparam PipeSpec = `PS_d8s;
wire [`P_m( PipeSpec ):0 ] pipe;
// usb uart - this instanciates the entire USB device.
usb_uart #( .PipeSpec( PipeSpec ) ) uart (
.clk_48mhz (clock_48mhz),
.reset (reset),
// pins
.pin_usb_p( usb_dp ),
.pin_usb_n( usb_dm ),
// uart pipeline, in and out
.pipe_in( pipe ),
.pipe_out( pipe )
//.debug( debug )
);
// USB Host Detect Pull Up
assign usb_pu = 1'b1;
endmodule |
module clock_pll
(
input CLKI, // 8 MHz, 0 deg
output CLKOP, // 48 MHz, 0 deg
output locked
);
(* FREQUENCY_PIN_CLKI="8" *)
(* FREQUENCY_PIN_CLKOP="48" *)
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
EHXPLLL #(
.PLLRST_ENA("DISABLED"),
.INTFB_WAKE("DISABLED"),
.STDBY_ENABLE("DISABLED"),
.DPHASE_SOURCE("DISABLED"),
.OUTDIVIDER_MUXA("DIVA"),
.OUTDIVIDER_MUXB("DIVB"),
.OUTDIVIDER_MUXC("DIVC"),
.OUTDIVIDER_MUXD("DIVD"),
.CLKI_DIV(1),
.CLKOP_ENABLE("ENABLED"),
.CLKOP_DIV(12),
.CLKOP_CPHASE(5),
.CLKOP_FPHASE(0),
.FEEDBK_PATH("CLKOP"),
.CLKFB_DIV(6)
) pll_i (
.RST(1'b0),
.STDBY(1'b0),
.CLKI(CLKI),
.CLKOP(CLKOP),
.CLKFB(CLKOP),
.CLKINTFB(),
.PHASESEL0(1'b0),
.PHASESEL1(1'b0),
.PHASEDIR(1'b1),
.PHASESTEP(1'b1),
.PHASELOADREG(1'b1),
.PLLWAKESYNC(1'b0),
.ENCLKOP(1'b0),
.LOCK(locked)
);
endmodule |
module led_uart_soc (
input clk,
output reg [7:0] led,
output uart_tx,
input uart_rx
);
reg [5:0] reset_cnt = 0;
wire resetn = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !resetn;
end
parameter integer MEM_WORDS = 10000; // = 8192;
parameter [31:0] STACKADDR = 32'h 0000_0000 + (4*MEM_WORDS); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 0000_0000; // start of memory
reg [31:0] ram [0:MEM_WORDS-1];
initial $readmemh("firmware.hex", ram);
reg [31:0] ram_rdata;
reg ram_ready;
wire mem_valid;
wire mem_instr;
wire mem_ready;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
wire [31:0] mem_rdata;
always @(posedge clk)
begin
ram_ready <= 1'b0;
if (mem_addr[31:24] == 8'h00 && mem_valid) begin
if (mem_wstrb[0]) ram[mem_addr[23:2]][7:0] <= mem_wdata[7:0];
if (mem_wstrb[1]) ram[mem_addr[23:2]][15:8] <= mem_wdata[15:8];
if (mem_wstrb[2]) ram[mem_addr[23:2]][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) ram[mem_addr[23:2]][31:24] <= mem_wdata[31:24];
ram_rdata <= ram[mem_addr[23:2]];
ram_ready <= 1'b1;
end
end
wire iomem_valid;
reg iomem_ready;
wire [31:0] iomem_addr;
wire [31:0] iomem_wdata;
wire [3:0] iomem_wstrb;
wire [31:0] iomem_rdata;
assign iomem_valid = mem_valid && (mem_addr[31:24] > 8'h 01);
assign iomem_wstrb = mem_wstrb;
assign iomem_addr = mem_addr;
assign iomem_wdata = mem_wdata;
wire simpleuart_reg_div_sel = mem_valid && (mem_addr == 32'h 0200_0004);
wire [31:0] simpleuart_reg_div_do;
wire simpleuart_reg_dat_sel = mem_valid && (mem_addr == 32'h 0200_0008);
wire [31:0] simpleuart_reg_dat_do;
wire simpleuart_reg_dat_wait;
always @(posedge clk) begin
iomem_ready <= 1'b0;
if (iomem_valid && iomem_wstrb[0] && mem_addr == 32'h 02000000) begin
led <= iomem_wdata[7:0];
iomem_ready <= 1'b1;
end
end
assign mem_ready = (iomem_valid && iomem_ready) ||
simpleuart_reg_div_sel || (simpleuart_reg_dat_sel && !simpleuart_reg_dat_wait) ||
ram_ready;
assign mem_rdata = simpleuart_reg_div_sel ? simpleuart_reg_div_do :
simpleuart_reg_dat_sel ? simpleuart_reg_dat_do :
ram_rdata;
picorv32 #(
.STACKADDR(STACKADDR),
.PROGADDR_RESET(PROGADDR_RESET),
.PROGADDR_IRQ(32'h 0000_0000),
.BARREL_SHIFTER(0),
.COMPRESSED_ISA(0),
.ENABLE_MUL(0),
.ENABLE_DIV(0),
.ENABLE_IRQ(0),
.ENABLE_IRQ_QREGS(0)
) cpu (
.clk (clk ),
.resetn (resetn ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata )
);
simpleuart simpleuart (
.clk (clk ),
.resetn (resetn ),
.ser_tx (uart_tx ),
.ser_rx (uart_rx ),
.reg_div_we (simpleuart_reg_div_sel ? mem_wstrb : 4'b 0000),
.reg_div_di (mem_wdata),
.reg_div_do (simpleuart_reg_div_do),
.reg_dat_we (simpleuart_reg_dat_sel ? mem_wstrb[0] : 1'b 0),
.reg_dat_re (simpleuart_reg_dat_sel && !mem_wstrb),
.reg_dat_di (mem_wdata),
.reg_dat_do (simpleuart_reg_dat_do),
.reg_dat_wait(simpleuart_reg_dat_wait)
);
endmodule |
module top(
input clk,
output [7:0] led,
inout [7:0] pmod
);
wire clk;
wire [7:0] int_led;
wire clock_48mhz;
clock_pll c_pll (.CLKI( clk ), .CLKOP( clock_48mhz ));
led_uart_soc soc(
.clk(clock_48mhz),
.led(int_led),
.uart_tx(pmod[0]),
.uart_rx(pmod[1])
);
assign led = ~int_led;
endmodule |
module pipe_frontend #(
parameter PipeSpec = `PS_d8,
parameter Greedy = 1
) (
input clock,
input reset,
inout [`P_w(PipeSpec)-1:0] pipe_in,
output in_start,
output in_stop,
output [`P_Data_w(PipeSpec)-1:0] in_data,
output in_valid,
input in_ready
);
localparam Pipe_Data_w = `P_Data_w(PipeSpec);
wire pipe_in_start;
wire pipe_in_stop;
wire [Pipe_Data_w-1:0] pipe_in_data;
wire pipe_in_valid;
reg pipe_in_ready;
p_unpack_start_stop #( .PipeSpec( PipeSpec ) ) p_up_ss( .pipe(pipe_in), .start(pipe_in_start), .stop(pipe_in_stop) );
p_unpack_data #( .PipeSpec( PipeSpec ) ) p_up_d( .pipe(pipe_in), .data(pipe_in_data) );
p_unpack_valid_ready #( .PipeSpec( PipeSpec ) ) p_up_vr( .pipe(pipe_in), .valid(pipe_in_valid), .ready(pipe_in_ready) );
localparam ESC_FRONTEND_STATE_STREAM = 0,
ESC_FRONTEND_STATE_STALL = 1;
reg pf_state;
reg pf_state_next;
reg pf_start_store;
reg pf_stop_store;
reg [Pipe_Data_w-1:0] pf_data_store;
reg pf_valid_store;
reg pf_start_next;
reg pf_stop_next;
reg [Pipe_Data_w-1:0] pf_data_next;
reg pf_valid_next;
reg pf_in_start;
reg pf_in_stop;
reg [Pipe_Data_w-1:0] pf_in_data;
reg pf_in_valid;
// Front End
//
// State:
// Passing - signals passed directly to next stage, if not ready, save, next step stall
// Stall - stored signals passing to next state, if ready next state Passing
// This always @(*) statement does all the work. Mostly it passes state directly to the backend.
// However, if there is a holdup in the backend, it will hold the current data, and
// store any overun
always @(*) begin
// All the default behavior
// next state is just the current state
pf_state_next = pf_state;
// backend gets the input directly
pf_in_start = pipe_in_start;
pf_in_stop = pipe_in_stop;
pf_in_data = pipe_in_data;
pf_in_valid = pipe_in_valid;
// next frontend
pf_start_next = pf_start_store;
pf_stop_next = pf_stop_store;
pf_data_next = pf_data_store;
pf_valid_next = pf_valid_store;
case ( pf_state )
ESC_FRONTEND_STATE_STREAM: begin
// Flowing - in this state either the data gets passed through, or it gets remembered
if ( !in_ready && in_valid ) begin
// input is saved
pf_start_next = pipe_in_start;
pf_stop_next = pipe_in_stop;
pf_data_next = pipe_in_data;
pf_valid_next = pipe_in_valid;
pf_state_next = ESC_FRONTEND_STATE_STALL;
end
end
ESC_FRONTEND_STATE_STALL: begin
// current frontend output comes from storage
pf_in_start = pf_start_store;
pf_in_stop = pf_stop_store;
pf_in_data = pf_data_store;
pf_in_valid = pf_valid_store;
// If the backend can take the data
if ( in_ready ) begin
// wipe memory
pf_start_next = 0;
pf_stop_next = 0;
pf_data_next = 0;
pf_valid_next = 0;
pf_state_next = ESC_FRONTEND_STATE_STREAM;
end
end
default: begin
pf_state_next = ESC_FRONTEND_STATE_STREAM;
end
endcase
end
always @(posedge clock) begin
if ( reset ) begin
pf_state <= ESC_FRONTEND_STATE_STREAM;
// clear the memory
pf_start_store <= 0;
pf_stop_store <= 0;
pf_data_store <= 0;
pf_valid_store <= 0;
pipe_in_ready <= 0;
end else begin
pf_state <= pf_state_next;
// update memory
pf_start_store <= pf_start_next;
pf_stop_store <= pf_stop_next;
pf_data_store <= pf_data_next;
pf_valid_store <= pf_valid_next;
pipe_in_ready <= ( ( pf_state_next == ESC_FRONTEND_STATE_STREAM ) && in_ready );
end
end
assign in_start = pf_in_start;
assign in_stop = pf_in_stop;
assign in_data = pf_in_data;
assign in_valid = pf_in_valid;
endmodule |
module pipe_fifo #( parameter PipeSpec = `PS_d8s, parameter MemoryWidth = 3 ) (
input clock,
input reset,
inout [`P_m(PipeSpec):0] pipe_in,
inout [`P_m(PipeSpec):0] pipe_out
);
wire [`P_Payload_m(PipeSpec):0] in_payload;
wire in_valid;
wire in_ready;
wire [`P_Payload_m(PipeSpec):0] out_payload;
wire out_valid;
wire out_ready;
p_unpack_payload #( .PipeSpec(PipeSpec) ) p_up_p( .pipe(pipe_in), .payload(in_payload) );
p_unpack_valid_ready #( .PipeSpec(PipeSpec) ) p_up_vr( .pipe(pipe_in), .valid(in_valid), .ready(in_ready) );
p_pack_payload #( .PipeSpec(PipeSpec) ) p_p_p( .payload(out_payload), .pipe(pipe_out) );
p_pack_valid_ready #( .PipeSpec(PipeSpec) ) p_p_vr( .valid(out_valid), .ready(out_ready), .pipe(pipe_out) );
// Store the whole payload
reg [`P_Payload_m(PipeSpec):0] memory [0:1<<MemoryWidth];
// MemoryWidth + 1 (extra rX, wX, so read != write when full)
reg [MemoryWidth:0] read_address;
reg [MemoryWidth:0] write_address;
// Are we ready? There's room if r != w or rX == wX
assign in_ready = ( read_address[MemoryWidth] == write_address[MemoryWidth] ) ||
( read_address[MemoryWidth-1:0] != write_address[MemoryWidth-1:0] );
// Write logic
always @(posedge clock) begin
if ( reset ) begin
write_address <= 0;
end else begin
if ( in_ready ) begin
if ( in_valid ) begin
memory[ write_address[MemoryWidth-1:0] ] <= in_payload;
write_address <= write_address + 1;
end
end
end
end
// Are we valid? (any time the whole read and write addresses are not exactly equal)
assign out_valid = ( read_address != write_address );
// Read logic
always @(posedge clock) begin
if ( reset ) begin
read_address <= 0;
end else begin
if ( out_valid ) begin
if ( out_ready ) begin
read_address <= read_address + 1;
end
end
end
end
assign out_payload = ( out_valid ) ? memory[ read_address[MemoryWidth-1:0] ] : 0;
endmodule |
module p_pack_payload #( parameter PipeSpec = `PS_def ) (
input [`P_Payload_w(PipeSpec)-1:0] payload,
inout [`P_m(PipeSpec):0] pipe
);
assign pipe[`P_Payload_m(PipeSpec):0] = payload;
endmodule |
module p_unpack_payload #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output [`P_Payload_w(PipeSpec)-1:0] payload
);
assign payload = pipe[`P_Payload_m(PipeSpec):0];
endmodule |
module p_pack_valid_ready #( parameter PipeSpec = `PS_def ) (
input valid,
output ready,
inout [`P_m(PipeSpec):0] pipe
);
assign pipe[ `P_Valid_b(PipeSpec) ] = valid;
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_pack_valid #( parameter PipeSpec = `PS_def ) (
input valid,
inout [`P_m(PipeSpec):0] pipe
);
assign pipe[ `P_Valid_b(PipeSpec) ] = valid;
endmodule |
module p_monitor_valid_ready #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output valid,
output ready
);
assign valid = pipe[ `P_Valid_b(PipeSpec) ];
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_pack_start_stop #( parameter PipeSpec = `PS_def ) (
input start,
input stop,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_Start_w( PipeSpec ) )
assign pipe[ `P_Start_b(PipeSpec) ] = start;
if ( `P_Stop_w( PipeSpec ) )
assign pipe[ `P_Stop_b(PipeSpec) ] = stop;
endgenerate
endmodule |
module p_unpack_start_stop #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output start,
output stop
);
generate
if ( `P_Start_w( PipeSpec ) )
assign start = pipe[ `P_Start_b(PipeSpec) ];
else
assign start = 1'B0;
if ( `P_Stop_w( PipeSpec ) )
assign stop = pipe[ `P_Stop_b(PipeSpec) ];
else
assign stop = 1'B0;
endgenerate
endmodule |
module p_pack_data #( parameter PipeSpec = `PS_def ) (
input [`P_Data_w(PipeSpec)-1:0] data,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_Data_w( PipeSpec ) )
assign pipe[ `P_Data_m(PipeSpec):`P_Data_l(PipeSpec) ] = data;
endgenerate
endmodule |
module p_unpack_data #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output [`P_Data_w(PipeSpec)-1:0] data
);
generate
if ( `P_Data_w( PipeSpec ) )
assign data = pipe[ `P_Data_m(PipeSpec):`P_Data_l(PipeSpec) ];
endgenerate
endmodule |
module p_pack_data_size #( parameter PipeSpec = `PS_def ) (
input [`P_DataSize_w(PipeSpec)-1:0] data_size,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_DataSize_w( PipeSpec ) )
assign pipe[`P_DataSize_m(PipeSpec):`P_DataSize_l(PipeSpec)] = data_size;
endgenerate
endmodule |
module p_unpack_data_size #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output [`P_DataSize_w(PipeSpec)-1:0] data_size
);
generate
if ( `P_DataSize_w( PipeSpec ) )
assign data_size = pipe[`P_DataSize_m(PipeSpec):`P_DataSize_l(PipeSpec)];
else
assign data_size = 0;
endgenerate
endmodule |
module p_pack_rev_valid_ready #( parameter PipeSpec = `PS_def ) (
output rev_valid,
input rev_ready,
inout [`P_m(PipeSpec):0] pipe
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
assign rev_valid = pipe[ `P_RevValid_l(PipeSpec) ];
assign pipe[ `P_RevReady_l(PipeSpec) ] = rev_ready;
end
endmodule |
module p_pack_rev_ready #( parameter PipeSpec = `PS_def ) (
input rev_ready,
inout [`P_m(PipeSpec):0] pipe
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
assign pipe[ `P_RevReady_l(PipeSpec) ] = rev_ready;
end
endmodule |
module p_pack_rev_start_stop #( parameter PipeSpec = `PS_def ) (
output rev_start,
output rev_stop,
inout [`P_m(PipeSpec):0] pipe
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevStart_w( PipeSpec ) )
assign rev_start = pipe[ `P_RevStart_l(PipeSpec) ];
if ( `P_Stop_w( PipeSpec ) )
assign rev_stop = pipe[ `P_RevStop_l(PipeSpec) ];
end
endmodule |
module p_unpack_rev_start_stop #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
input rev_start,
input rev_stop
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevStart_w( PipeSpec ) )
assign pipe[ `P_RevStart_l(PipeSpec) ] = rev_start;
if ( `P_RevStop_w( PipeSpec ) )
assign pipe[ `P_RevStop_l(PipeSpec) ] = rev_stop;
end
endmodule |
module p_pack_rev_data #( parameter PipeSpec = `PS_def ) (
output [`P_RevData_w(PipeSpec)-1:0] rev_data,
inout [`P_m(PipeSpec):0] pipe
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevData_w( PipeSpec ) )
assign rev_data = pipe[ `P_RevData_m(PipeSpec):`P_RevData_l(PipeSpec) ];
end
endmodule |
module p_unpack_rev_data #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
input [`P_RevData_w(PipeSpec)-1:0] rev_data
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevData_w( PipeSpec ) )
assign pipe[ `P_RevData_m(PipeSpec):`P_RevData_l(PipeSpec) ] = rev_data;
end
endmodule |
module p_pack_rev_data_size #( parameter PipeSpec = `PS_def ) (
output [`P_RevDataSize_w(PipeSpec)-1:0] rev_data_size,
inout [`P_m(PipeSpec):0] pipe
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevDataSize_w( PipeSpec ) )
assign rev_data_size = pipe[`P_RevDataSize_m(PipeSpec):`P_RevDataSize_l(PipeSpec)];
else
assign rev_data_size = 0;
end
endmodule |
module p_unpack_rev_data_size #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
input [`P_RevDataSize_w(PipeSpec)-1:0] rev_data_size
);
if ( `PS_Reverse_v( PipeSpec ) ) begin
if ( `P_RevDataSize_w( PipeSpec ) )
assign pipe[`P_RevDataSize_m(PipeSpec):`P_RevDataSize_l(PipeSpec)] = rev_data_size;
end
endmodule |
module p_pack_command #( parameter PipeSpec = `PS_def ) (
input [`P_Command_w(PipeSpec)-1:0] command,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_Command_w( PipeSpec ) )
assign pipe[ `P_Command_m(PipeSpec):`P_Command_l(PipeSpec) ] = command;
endgenerate
endmodule |
module p_unpack_command #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output [`P_Command_w(PipeSpec)-1:0] command
);
generate
if ( `P_Command_w( PipeSpec ) )
assign command = pipe[ `P_Command_m(PipeSpec):`P_Command_l(PipeSpec) ];
endgenerate
endmodule |
module p_pack_result #( parameter PipeSpec = `PS_def ) (
output [`P_Result_w(PipeSpec)-1:0] result,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_Result_w( PipeSpec ) )
assign result = pipe[ `P_Result_m(PipeSpec):`P_Result_l(PipeSpec) ];
endgenerate
endmodule |
module p_unpack_result #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
input [`P_Result_w(PipeSpec)-1:0] result
);
generate
if ( `P_Result_w( PipeSpec ) )
assign pipe[ `P_Result_m(PipeSpec):`P_Result_l(PipeSpec) ] = result;
endgenerate
endmodule |
module p_pack_request #( parameter PipeSpec = `PS_def ) (
output [`P_Request_w(PipeSpec)-1:0] request,
inout [`P_m(PipeSpec):0] pipe
);
generate
if ( `P_Request_w( PipeSpec ) )
assign request = pipe[ `P_Request_m(PipeSpec):`P_Request_l(PipeSpec) ];
endgenerate
endmodule |
module p_unpack_request #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
input [`P_Request_w(PipeSpec)-1:0] request
);
generate
if ( `P_Request_w( PipeSpec ) )
assign pipe[ `P_Request_m(PipeSpec):`P_Request_l(PipeSpec) ] = request;
endgenerate
endmodule |
module p_info #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe,
output start,
output stop,
output [`P_Data_m(PipeSpec):0] data,
output valid,
output ready
);
generate
if ( `P_Start_w( PipeSpec ) )
assign start = pipe[ `P_Start_b(PipeSpec) ];
else
assign start = 0;
if ( `P_Stop_w( PipeSpec ) )
assign stop = pipe[ `P_Stop_b(PipeSpec) ];
else
assign stop = 0;
endgenerate
assign data = pipe[ `P_Data_m(PipeSpec):`P_Data_l(PipeSpec) ];
assign valid = pipe[ `P_Valid_b(PipeSpec) ];
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_specs #( parameter PipeDataWidth = 8 );
endmodule |
module p_pack_ssdvrp #( parameter PipeSpec = `PS_def ) (
input start,
input stop,
input [`P_Data_w(PipeSpec)-1:0] data,
input valid,
output ready,
inout [`P_w(PipeSpec)-1:0] pipe
);
generate
if ( `P_Start_w( PipeSpec ) )
assign pipe[ `P_Start_b(PipeSpec) ] = start;
if ( `P_Stop_w( PipeSpec ) )
assign pipe[ `P_Stop_b(PipeSpec) ] = stop;
endgenerate
assign pipe[ `P_Data_w(PipeSpec)-1:`P_Data_l(PipeSpec) ] = data;
assign pipe[ `P_Valid_b(PipeSpec) ] = valid;
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_pack_dvr #( parameter PipeSpec = `PS_def ) (
input [`P_Data_w(PipeSpec)-1:0] data,
input valid,
output ready,
inout [`P_w(PipeSpec)-1:0] pipe
);
assign pipe[ `P_Data_w(PipeSpec)-1:`P_Data_l(PipeSpec) ] = data;
assign pipe[ `P_Valid_b(PipeSpec) ] = valid;
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_pack #( parameter PipeSpec = `PS_def ) (
input start,
input stop,
input [`P_Data_w(PipeSpec)-1:0] data,
input [`P_DataSize_w(PipeSpec)-1:0] datasize,
input valid,
output ready,
inout [`P_w(PipeSpec)-1:0] pipe
);
generate
if ( `P_Start_w( PipeSpec ) )
assign pipe[ `P_Start_b(PipeSpec) ] = start;
if ( `P_Stop_w( PipeSpec ) )
assign pipe[ `P_Stop_b(PipeSpec) ] = stop;
endgenerate
generate
if ( `P_DataSize_w( PipeSpec ) )
assign pipe[ `P_DataSize_m(PipeSpec):`P_DataSize_l(PipeSpec) ] = datasize;
endgenerate
assign pipe[ `P_Data_m(PipeSpec):`P_Data_l(PipeSpec) ] = data;
assign pipe[ `P_Valid_b(PipeSpec) ] = valid;
assign ready = pipe[ `P_Ready_b(PipeSpec) ];
endmodule |
module p_null_source #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe_out
);
// doing nothing
assign pipe_out[`P_Payload_m(PipeSpec):0] = 0;
assign pipe_out[`P_Valid_b(PipeSpec)] = 0;
endmodule |
module p_null_sink #( parameter PipeSpec = `PS_def ) (
inout [`P_m(PipeSpec):0] pipe_in
);
// receiving everything
assign pipe_in[ `P_Ready_b(PipeSpec) ] = 1;
endmodule |
module p_pipe2data #( parameter PipeSpec = `PS_def ) (
input clock,
input reset,
inout [`P_m(PipeSpec):0] pipe,
output [`P_Data_m(PipeSpec):0] data,
output data_valid
);
wire [`P_Data_m(PipeSpec):0] in_data;
wire in_valid;
reg in_ready;
p_unpack_valid_ready #( .PipeSpec(PipeSpec) ) p_u_v( pipe, in_valid, in_ready );
p_unpack_data #( .PipeSpec(PipeSpec) ) p_u_d( pipe, in_data );
reg [`P_Data_m(PipeSpec):0] p2d_data;
reg p2d_data_valid;
always @(posedge clock) begin
if ( reset ) begin
p2d_data <= 0;
p2d_data_valid <= 0;
in_ready <= 1;
end else begin
if ( in_valid ) begin
p2d_data <= in_data;
p2d_data_valid <= 1;
end
end
end
assign data = p2d_data;
assign data_valid = p2d_data_valid;
endmodule |
module p_data2pipe #( parameter PipeSpec = `PS_def ) (
input clock,
input reset,
input send,
input [`P_Data_m(PipeSpec):0] data,
input data_valid,
inout [`P_m(PipeSpec):0] pipe
);
reg [`P_Data_m(PipeSpec):0] out_data;
reg out_valid;
wire out_ready;
reg out_start;
reg out_stop;
reg send_previous;
p_pack_valid_ready #( .PipeSpec(PipeSpec) ) p_p_v( out_valid, out_ready, pipe );
p_pack_data #( .PipeSpec(PipeSpec) ) p_p_d( out_data, pipe );
p_pack_start_stop #( .PipeSpec(PipeSpec) ) p_p_ss( out_start, out_stop, pipe );
reg [`P_Data_m(PipeSpec):0] transferred_data;
reg transferred_any;
always @(posedge clock) begin
if ( reset ) begin
out_data <= 0;
out_valid <= 0;
out_start <= 0;
out_stop <= 0;
transferred_data <= 0;
transferred_any <= 0;
send_previous <= 0;
end else begin
send_previous <= send;
if ( out_valid && out_ready ) begin
transferred_data <= out_data;
if ( data_valid && (( data != out_data ) || ( send && ~send_previous ) ) ) begin
out_data <= data;
end else begin
out_data <= 0;
out_valid <= 0;
out_start <= 0;
out_stop <= 0;
end
end else begin
if ( data_valid ) begin
if ( ( data != transferred_data ) || !transferred_any || ( send && ~send_previous ) ) begin
transferred_any <= 1;
out_start <= 1;
out_stop <= 1;
out_data <= data;
out_valid <= 1;
end else begin
out_start <= 0;
out_stop <= 0;
out_data <= 0;
out_valid <= 0;
end
end
end
end
end
endmodule |
module add_accum( clock, reset, x, valid, accumsum );
input clock;
input reset;
input [3:0] x;
input valid;
output reg [7:0] accumsum;
always @(posedge clock) begin
if ( reset )
accumsum <= 0;
else
if ( valid )
accumsum <= accumsum + x;
end
endmodule |
module add_sat( x, y, satsum );
parameter limit = 8'H0A;
input [3:0] x;
input [3:0] y;
output reg [4:0] satsum;
always @(*) begin
if ( x + y > limit)
satsum = limit;
else
satsum = x + y;
end
endmodule |
module image_background #(
parameter [`IS_w-1:0] IS = `IS_DEFAULT,
parameter Step = 0,
parameter Bayer_GreenFirst = 0,
parameter Bayer_BlueFirst = 1
) (
input clock,
input reset,
input [1:0] operation,
input [23:0 ] color,
input out_request_external,
inout [`I_w( IS )-1:0 ] image_out,
output out_sending
);
//
// Spec Info
//
localparam Width = `IS_WIDTH( IS );
localparam Height = `IS_HEIGHT( IS );
localparam WidthWidth = `IS_WIDTH_WIDTH( IS );
localparam HeightWidth = `IS_HEIGHT_WIDTH( IS );
localparam DataWidth = `IS_DATA_WIDTH( IS );
localparam [7:0] C0Width = `I_C0_w( IS );
localparam [7:0] C1Width = `I_C1_w( IS );
localparam [7:0] C2Width = `I_C2_w( IS );
localparam [7:0] AlphaWidth = `I_Alpha_w( IS );
localparam [7:0] ZWidth = `I_Z_w( IS );
localparam InternalWidth = 10;
localparam AccumulatorWidth = 12;
localparam Format = `IS_FORMAT( IS );
localparam [`IS_w-1:0] IS_RGB8 = `IS( 0, 0, 32, 32, 0, 1, `IS_FORMAT_RGB, 8, 8, 8, 0, 0 );
localparam SolidColorWidth = `I_C0_w( IS_RGB8 );
//
// Image Out
//
// Grab all the signals from the image pipe
reg out_start;
reg out_stop;
reg [DataWidth-1:0] out_data;
reg out_valid;
reg out_error;
wire out_ready;
wire out_request;
wire out_cancel;
// Assign the outgoing signals
assign `I_Start( IS, image_out ) = out_start;
assign `I_Stop( IS, image_out ) = out_stop;
assign `I_Data( IS, image_out ) = out_data;
assign `I_Valid( IS, image_out ) = out_valid;
assign `I_Error( IS, image_out ) = out_error;
// Assign the incoming signals
assign out_request = `I_Request( IS, image_out );
assign out_cancel = `I_Cancel( IS, image_out );
assign out_ready = `I_Ready( IS, image_out );
// States
localparam BOUT_STATE_IDLE = 0,
BOUT_STATE_SENDING = 1,
BOUT_STATE_COMPLETE = 2;
reg [1:0] bout_state;
reg [WidthWidth-1:0] bout_x;
reg [HeightWidth-1:0] bout_y;
wire [WidthWidth-1:0] bout_x_next = bout_x + 1;
wire [HeightWidth-1:0] bout_y_next = bout_y + 1;
reg bayer_green;
reg bayer_green_line;
reg bayer_blue;
wire bout_xy_start = ( bout_x == 0 ) && ( bout_y == 0 );
wire bout_xy_end = ( bout_x == Width - 1 ) && ( bout_y == Height - 1 );
reg [C0Width-1:0] c0;
reg [C1Width-1:0] c1;
reg [C2Width-1:0] c2;
if ( AlphaWidth > 0 )
reg [AlphaWidth-1:0] alpha;
else
reg alpha;
if ( ZWidth > 0 )
reg [ZWidth-1:0] z;
else
reg z;
reg [AccumulatorWidth-1:0] acc;
localparam C0Max = ( 1 << C0Width ) - 1;
localparam C1Max = ( 1 << C1Width ) - 1;
localparam C2Max = ( 1 << C2Width ) - 1;
if ( AlphaWidth > 0 )
localparam AlphaMax = ( 1 << AlphaWidth ) - 1;
if ( ZWidth > 0 )
localparam ZMax = ( 1 << ZWidth ) - 1;
localparam InternalMax = ( 1 << InternalWidth ) - 1;
reg [5:0] step;
//
// Grid Functions
//
function [InternalWidth-1:0] r_grid( input [WidthWidth-1:0] x, input [HeightWidth-1:0] y );
if ( ( x < 2 ) || ( y < 2 ) || ( x > (Width - 3)) || ( y > (Height - 3)) || ( y[3:1] == 2 ) || ( x[3:1] == 2 ) )
r_grid = InternalMax;
else
r_grid = 0;
endfunction
function [InternalWidth-1:0] g_grid( input [WidthWidth-1:0] x, input [HeightWidth-1:0] y );
if ( ( x < 2 ) || ( y < 2 ) || ( x > (Width - 3)) || ( y > (Height - 3)) || ( y[3:1] == 4 ) || ( x[3:1] == 4 ) )
g_grid = InternalMax;
else
g_grid = 0;
endfunction
function [InternalWidth-1:0] b_grid( input [WidthWidth-1:0] x, input [HeightWidth-1:0] y );
if ( ( x < 2 ) || ( y < 2 ) || ( x > (Width - 3)) || ( y > (Height - 3)) || ( y[3:1] == 6 ) || ( x[3:1] == 6 ) )
b_grid = InternalMax;
else
b_grid = 0;
endfunction
if ( AlphaWidth > 0 ) begin
function [InternalWidth-1:0] alpha_grid( input [WidthWidth-1:0] x, input [HeightWidth-1:0] y );
alpha_grid = InternalMax;
endfunction
end
if ( ZWidth > 0 ) begin
function [InternalWidth-1:0] z_grid( input [WidthWidth-1:0] x, input [HeightWidth-1:0] y );
z_grid = 0;
endfunction
end
always @( * ) begin
c0 = 0;
c1 = 0;
c2 = 0;
if ( AlphaWidth > 0 ) begin
alpha = 0;
end
if ( ZWidth > 0 ) begin
z = 0;
end
acc = 0;
if ( Format == `IS_FORMAT_GRAYSCALE ) begin
case ( operation )
0: begin
c0 = `I_ColorComponent( 10, C0Width, `I_C0( IS_RGB8, color ) + `I_C1( IS_RGB8, color ) + `I_C2( IS_RGB8, color ) );
end
1: begin
acc = r_grid( bout_x, bout_y ) + g_grid( bout_x, bout_y ) + b_grid( bout_x, bout_y );
c0 = acc[AccumulatorWidth-1 -: C0Width ];
end
endcase
end else begin
if ( Format == `IS_FORMAT_RGB ) begin
case ( operation )
0: begin
c0 = `I_C0( IS_RGB8, color );
c1 = `I_C1( IS_RGB8, color );
c2 = `I_C2( IS_RGB8, color );
end
1: begin
c0 = ( InternalWidth > C0Width ) ? r_grid( bout_x, bout_y ) >> ( InternalWidth - C0Width ) : r_grid( bout_x, bout_y ) << ( C0Width - InternalWidth );
c1 = ( InternalWidth > C1Width ) ? g_grid( bout_x, bout_y ) >> ( InternalWidth - C1Width ) : g_grid( bout_x, bout_y ) << ( C1Width - InternalWidth );
c2 = ( InternalWidth > C2Width ) ? b_grid( bout_x, bout_y ) >> ( InternalWidth - C2Width ) : b_grid( bout_x, bout_y ) << ( C2Width - InternalWidth );
end
endcase
end else begin
if ( Format == `IS_FORMAT_BAYER ) begin
case ( operation )
0: begin
if ( bayer_green )
c0 = `I_ColorComponent( SolidColorWidth, C0Width, `I_C1( IS_RGB8, color ) );
else begin
if ( bayer_blue )
c0 = `I_ColorComponent( SolidColorWidth, C0Width, `I_C2( IS_RGB8, color ) );
else
c0 = `I_ColorComponent( SolidColorWidth, C0Width, `I_C0( IS_RGB8, color ) );
end
end
1: begin
if ( bayer_green )
c0 = ( InternalWidth > C0Width ) ? g_grid( bout_x, bout_y ) >> ( InternalWidth - C0Width ) : g_grid( bout_x, bout_y ) << ( C0Width - InternalWidth );
else begin
if ( bayer_blue )
c0 = ( InternalWidth > C0Width ) ? b_grid( bout_x, bout_y ) >> ( InternalWidth - C0Width ) : b_grid( bout_x, bout_y ) << ( C0Width - InternalWidth );
else
c0 = ( InternalWidth > C0Width ) ? r_grid( bout_x, bout_y ) >> ( InternalWidth - C0Width ) : r_grid( bout_x, bout_y ) << ( C0Width - InternalWidth );
end
end
endcase
end
end
end
end
always @( posedge clock ) begin
if ( reset || out_cancel ) begin
bout_state <= BOUT_STATE_IDLE;
bout_x <= 0;
bout_y <= 0;
out_start <= 0;
out_stop <= 0;
out_data <= 0;
out_error <= 0;
out_valid <= 0;
bayer_green_line <= Bayer_GreenFirst;
bayer_green <= Bayer_GreenFirst;
bayer_blue <= Bayer_BlueFirst;
end else begin
case ( bout_state )
BOUT_STATE_IDLE: begin
if ( out_request || out_request_external ) begin
bout_state <= BOUT_STATE_SENDING;
end
end
BOUT_STATE_SENDING: begin
if ( out_ready || !out_valid ) begin
if ( ( Format == `IS_FORMAT_GRAYSCALE ) || ( Format == `IS_FORMAT_BAYER ) )
out_data <= c0;
else
out_data <= { c2, c1, c0 };
out_start <= ( bout_xy_start );
out_valid <= 1;
if ( bout_x == Width-1 ) begin
if ( bout_y == Height-1 ) begin
out_stop <= 1;
bout_state <= BOUT_STATE_COMPLETE;
end else begin
bout_x <= 0;
bayer_blue <= !bayer_blue;
bayer_green <= !bayer_green_line;
bayer_green_line <= !bayer_green_line;
bout_y <= bout_y_next;
end
end else begin
bout_x <= bout_x_next;
bayer_green <= !bayer_green;
end
end
end
BOUT_STATE_COMPLETE: begin
if ( out_ready ) begin
out_data <= 0;
out_start <= 0;
out_stop <= 0;
out_valid <= 0;
bout_x <= 0;
bout_y <= 0;
bayer_green_line <= Bayer_GreenFirst;
bayer_green <= Bayer_GreenFirst;
bayer_blue <= Bayer_BlueFirst;
bout_state <= BOUT_STATE_IDLE;
end
end
endcase
end
end
assign out_sending = ( bout_state != BOUT_STATE_IDLE );
endmodule |
Subsets and Splits