module
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module moving_avg
#(
parameter DATA_WIDTH = 32,
parameter WINDOW_SHIFT = 4,
parameter SIGNED = 0
)
(
input clock,
input enable,
input reset,
input signed [DATA_WIDTH-1:0] data_in,
input input_strobe,
output reg signed [DATA_WIDTH-1:0] data_out,
output reg output_strobe
);
localparam WINDOW_SIZE = 1<<WINDOW_SHIFT;
localparam SUM_WIDTH = DATA_WIDTH + WINDOW_SHIFT;
reg signed [(SUM_WIDTH-1):0] running_sum;
wire signed [DATA_WIDTH-1:0] old_data;
wire signed [DATA_WIDTH-1:0] new_data = data_in;
wire signed [SUM_WIDTH-1:0] ext_old_data = {{WINDOW_SHIFT{old_data[DATA_WIDTH-1]}}, old_data};
wire signed [SUM_WIDTH-1:0] ext_new_data = {{WINDOW_SHIFT{new_data[DATA_WIDTH-1]}}, new_data};
reg [WINDOW_SHIFT-1:0] addr;
reg full;
ram_2port #(.DWIDTH(DATA_WIDTH), .AWIDTH(WINDOW_SHIFT)) delay_line (
.clka(clock),
.ena(1),
.wea(input_strobe),
.addra(addr),
.dia(data_in),
.doa(),
.clkb(clock),
.enb(input_strobe),
.web(0),
.addrb(addr),
.dib(32'hFFFF),
.dob(old_data)
);
integer i;
always @(posedge clock) begin
if (reset) begin
addr <= 0;
running_sum <= 0;
full <= 0;
data_out <= 0;
end else if (enable) begin
if (input_strobe) begin
addr <= addr + 1;
data_out <= running_sum[SUM_WIDTH-1:WINDOW_SHIFT];
if (addr == WINDOW_SIZE-1) begin
full <= 1;
end
if (full) begin
running_sum <= running_sum + ext_new_data- ext_old_data;
end else begin
running_sum <= running_sum + ext_new_data;
end
output_strobe <= full;
end else begin
output_strobe <= 0;
end
end else begin
output_strobe <= 0;
end
end
endmodule |
module demodulate (
input clock,
input enable,
input reset,
input [7:0] rate,
input [15:0] cons_i,
input [15:0] cons_q,
input input_strobe,
output reg [5:0] bits,
output reg [5:0] soft_bits,
output reg [3:0] soft_bits_pos,
output output_strobe
);
localparam MAX = 1<<`CONS_SCALE_SHIFT;
localparam QAM_16_DIV = MAX*2/3;
localparam QAM_64_DIV_0 = MAX*2/7;
localparam QAM_64_DIV_1 = MAX*4/7;
localparam QAM_64_DIV_2 = MAX*6/7;
localparam BPSK_SOFT_4 = MAX;
localparam BPSK_SOFT_3 = MAX*3/4;
localparam BPSK_SOFT_2 = MAX*2/4;
localparam BPSK_SOFT_1 = MAX*1/4;
localparam BPSK_SOFT_0 = 0;
localparam QPSK_SOFT_4 = MAX;
localparam QPSK_SOFT_3 = MAX*3/4;
localparam QPSK_SOFT_2 = MAX*2/4;
localparam QPSK_SOFT_1 = MAX*1/4;
localparam QPSK_SOFT_0 = 0;
localparam QAM_16_SOFT_12 = MAX;
localparam QAM_16_SOFT_11 = MAX*11/12;
localparam QAM_16_SOFT_10 = MAX*10/12;
localparam QAM_16_SOFT_9 = MAX*9/12;
localparam QAM_16_SOFT_8 = MAX*8/12;
localparam QAM_16_SOFT_7 = MAX*7/12;
localparam QAM_16_SOFT_6 = MAX*6/12;
localparam QAM_16_SOFT_5 = MAX*5/12;
localparam QAM_16_SOFT_4 = MAX*4/12;
localparam QAM_16_SOFT_3 = MAX*3/12;
localparam QAM_16_SOFT_2 = MAX*2/12;
localparam QAM_16_SOFT_1 = MAX*1/12;
localparam QAM_16_SOFT_0 = 0;
localparam QAM_64_SOFT_28 = MAX;
localparam QAM_64_SOFT_27 = MAX*27/28;
localparam QAM_64_SOFT_26 = MAX*26/28;
localparam QAM_64_SOFT_25 = MAX*25/28;
localparam QAM_64_SOFT_24 = MAX*24/28;
localparam QAM_64_SOFT_23 = MAX*23/28;
localparam QAM_64_SOFT_22 = MAX*22/28;
localparam QAM_64_SOFT_21 = MAX*21/28;
localparam QAM_64_SOFT_20 = MAX*20/28;
localparam QAM_64_SOFT_19 = MAX*19/28;
localparam QAM_64_SOFT_18 = MAX*18/28;
localparam QAM_64_SOFT_17 = MAX*17/28;
localparam QAM_64_SOFT_16 = MAX*16/28;
localparam QAM_64_SOFT_15 = MAX*15/28;
localparam QAM_64_SOFT_14 = MAX*14/28;
localparam QAM_64_SOFT_13 = MAX*13/28;
localparam QAM_64_SOFT_12 = MAX*12/28;
localparam QAM_64_SOFT_11 = MAX*11/28;
localparam QAM_64_SOFT_10 = MAX*10/28;
localparam QAM_64_SOFT_9 = MAX*9/28;
localparam QAM_64_SOFT_8 = MAX*8/28;
localparam QAM_64_SOFT_7 = MAX*7/28;
localparam QAM_64_SOFT_6 = MAX*6/28;
localparam QAM_64_SOFT_5 = MAX*5/28;
localparam QAM_64_SOFT_4 = MAX*4/28;
localparam QAM_64_SOFT_3 = MAX*3/28;
localparam QAM_64_SOFT_2 = MAX*2/28;
localparam QAM_64_SOFT_1 = MAX*1/28;
localparam QAM_64_SOFT_0 = 0;
localparam BPSK = 1;
localparam QPSK = 2;
localparam QAM_16 = 3;
localparam QAM_64 = 4;
reg [15:0] cons_i_delayed;
reg [15:0] cons_q_delayed;
reg [15:0] abs_cons_i;
reg [15:0] abs_cons_q;
reg [2:0] mod;
delayT #(.DATA_WIDTH(1), .DELAY(2)) stb_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(output_strobe)
);
always @(posedge clock) begin
if (reset) begin
bits <= 0;
soft_bits <= 0;
soft_bits_pos <= 4'b1111;
abs_cons_i <= 0;
abs_cons_q <= 0;
cons_i_delayed <= 0;
cons_q_delayed <= 0;
mod <= 0;
end else if (enable) begin
abs_cons_i <= cons_i[15]? ~cons_i+1: cons_i;
abs_cons_q <= cons_q[15]? ~cons_q+1: cons_q;
cons_i_delayed <= cons_i;
cons_q_delayed <= cons_q;
case({rate[7], rate[3:0]})
// 802.11a rates
5'b01011: begin mod <= BPSK; end
5'b01111: begin mod <= BPSK; end
5'b01010: begin mod <= QPSK; end
5'b01110: begin mod <= QPSK; end
5'b01001: begin mod <= QAM_16; end
5'b01101: begin mod <= QAM_16; end
5'b01000: begin mod <= QAM_64; end
5'b01100: begin mod <= QAM_64; end
// 802.11n rates
5'b10000: begin mod <= BPSK; end
5'b10001: begin mod <= QPSK; end
5'b10010: begin mod <= QPSK; end
5'b10011: begin mod <= QAM_16; end
5'b10100: begin mod <= QAM_16; end
5'b10101: begin mod <= QAM_64; end
5'b10110: begin mod <= QAM_64; end
5'b10111: begin mod <= QAM_64; end
default: begin mod <= BPSK; end
endcase
case(mod)
BPSK: begin
// Hard decoded bits
bits[0] <= ~cons_i_delayed[15];
bits[5:1] <= 0;
// Inphase soft decoded bits
if(cons_i_delayed[15] == 0 && abs_cons_i >= BPSK_SOFT_3)
soft_bits[2:0] <= 3'b111;
else if(cons_i_delayed[15] == 0 && abs_cons_i < BPSK_SOFT_3 && abs_cons_i >= BPSK_SOFT_2)
soft_bits[2:0] <= 3'b110;
else if(cons_i_delayed[15] == 0 && abs_cons_i < BPSK_SOFT_2 && abs_cons_i >= BPSK_SOFT_1)
soft_bits[2:0] <= 3'b101;
else if(cons_i_delayed[15] == 0 && abs_cons_i < BPSK_SOFT_1 && abs_cons_i >= BPSK_SOFT_0)
soft_bits[2:0] <= 3'b100;
else if(cons_i_delayed[15] == 1 && abs_cons_i < BPSK_SOFT_1 && abs_cons_i >= BPSK_SOFT_0)
soft_bits[2:0] <= 3'b000;
else if(cons_i_delayed[15] == 1 && abs_cons_i < BPSK_SOFT_2 && abs_cons_i >= BPSK_SOFT_1)
soft_bits[2:0] <= 3'b001;
else if(cons_i_delayed[15] == 1 && abs_cons_i < BPSK_SOFT_3 && abs_cons_i >= BPSK_SOFT_2)
soft_bits[2:0] <= 3'b010;
else if(cons_i_delayed[15] == 1 && abs_cons_i < BPSK_SOFT_4 && abs_cons_i >= BPSK_SOFT_3)
soft_bits[2:0] <= 3'b011;
//
else
soft_bits[2:0] <= 3'b011;
// Quadrature soft decoded bits
soft_bits[5:3] <= 3'b000;
// Inphase soft decoded bit positions
if(abs_cons_i < BPSK_SOFT_4)
soft_bits_pos[1:0] <= 2'b00;
else
soft_bits_pos[1:0] <= 2'b11;
// Quadrature soft decoded bit positions
soft_bits_pos[3:2] <= 2'b11;
end
QPSK: begin
// Hard decoded bits
bits[0] <= ~cons_i_delayed[15];
bits[1] <= ~cons_q_delayed[15];
bits[5:2] <= 0;
// Inphase soft decoded bits
if(cons_i_delayed[15] == 0 && abs_cons_i >= QPSK_SOFT_3)
soft_bits[2:0] <= 3'b111;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QPSK_SOFT_3 && abs_cons_i >= QPSK_SOFT_2)
soft_bits[2:0] <= 3'b110;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QPSK_SOFT_2 && abs_cons_i >= QPSK_SOFT_1)
soft_bits[2:0] <= 3'b101;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QPSK_SOFT_1 && abs_cons_i >= QPSK_SOFT_0)
soft_bits[2:0] <= 3'b100;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QPSK_SOFT_1 && abs_cons_i >= QPSK_SOFT_0)
soft_bits[2:0] <= 3'b000;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QPSK_SOFT_2 && abs_cons_i >= QPSK_SOFT_1)
soft_bits[2:0] <= 3'b001;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QPSK_SOFT_3 && abs_cons_i >= QPSK_SOFT_2)
soft_bits[2:0] <= 3'b010;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QPSK_SOFT_4 && abs_cons_i >= QPSK_SOFT_3)
soft_bits[2:0] <= 3'b011;
//
else
soft_bits[2:0] <= 3'b011;
// Quadrature soft decoded bits
if(cons_q_delayed[15] == 0 && abs_cons_q >= QPSK_SOFT_3)
soft_bits[5:3] <= 3'b111;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QPSK_SOFT_3 && abs_cons_q >= QPSK_SOFT_2)
soft_bits[5:3] <= 3'b110;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QPSK_SOFT_2 && abs_cons_q >= QPSK_SOFT_1)
soft_bits[5:3] <= 3'b101;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QPSK_SOFT_1 && abs_cons_q >= QPSK_SOFT_0)
soft_bits[5:3] <= 3'b100;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QPSK_SOFT_1 && abs_cons_q >= QPSK_SOFT_0)
soft_bits[5:3] <= 3'b000;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QPSK_SOFT_2 && abs_cons_q >= QPSK_SOFT_1)
soft_bits[5:3] <= 3'b001;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QPSK_SOFT_3 && abs_cons_q >= QPSK_SOFT_2)
soft_bits[5:3] <= 3'b010;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QPSK_SOFT_4 && abs_cons_q >= QPSK_SOFT_3)
soft_bits[5:3] <= 3'b011;
//
else
soft_bits[5:3] <= 3'b011;
// Inphase soft decoded bit positions
if(abs_cons_i < QPSK_SOFT_4)
soft_bits_pos[1:0] <= 2'b00;
else
soft_bits_pos[1:0] <= 2'b11;
// Quadrature soft decoded bit positions
if(abs_cons_q < QPSK_SOFT_4)
soft_bits_pos[3:2] <= 2'b00;
else
soft_bits_pos[3:2] <= 2'b11;
end
QAM_16: begin
// Hard decoded bits
bits[0] <= ~cons_i_delayed[15];
bits[1] <= abs_cons_i < QAM_16_DIV? 1: 0;
bits[2] <= ~cons_q_delayed[15];
bits[3] <= abs_cons_q < QAM_16_DIV? 1: 0;
bits[5:4] <= 0;
// Inphase soft decoded bits
if(abs_cons_i < QAM_16_SOFT_12 && abs_cons_i >= QAM_16_SOFT_11)
soft_bits[2:0] <= 3'b011;
else if(abs_cons_i < QAM_16_SOFT_11 && abs_cons_i >= QAM_16_SOFT_10)
soft_bits[2:0] <= 3'b010;
else if(abs_cons_i < QAM_16_SOFT_10 && abs_cons_i >= QAM_16_SOFT_9)
soft_bits[2:0] <= 3'b001;
else if(abs_cons_i < QAM_16_SOFT_9 && abs_cons_i >= QAM_16_SOFT_8)
soft_bits[2:0] <= 3'b000;
else if(abs_cons_i < QAM_16_SOFT_8 && abs_cons_i >= QAM_16_SOFT_7)
soft_bits[2:0] <= 3'b100;
else if(abs_cons_i < QAM_16_SOFT_7 && abs_cons_i >= QAM_16_SOFT_6)
soft_bits[2:0] <= 3'b101;
else if(abs_cons_i < QAM_16_SOFT_6 && abs_cons_i >= QAM_16_SOFT_5)
soft_bits[2:0] <= 3'b110;
else if(abs_cons_i < QAM_16_SOFT_5 && abs_cons_i >= QAM_16_SOFT_4)
soft_bits[2:0] <= 3'b111;
//
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_16_SOFT_4 && abs_cons_i >= QAM_16_SOFT_3)
soft_bits[2:0] <= 3'b111;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_16_SOFT_3 && abs_cons_i >= QAM_16_SOFT_2)
soft_bits[2:0] <= 3'b110;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_16_SOFT_2 && abs_cons_i >= QAM_16_SOFT_1)
soft_bits[2:0] <= 3'b101;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_16_SOFT_1 && abs_cons_i >= QAM_16_SOFT_0)
soft_bits[2:0] <= 3'b100;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_16_SOFT_1 && abs_cons_i >= QAM_16_SOFT_0)
soft_bits[2:0] <= 3'b000;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_16_SOFT_2 && abs_cons_i >= QAM_16_SOFT_1)
soft_bits[2:0] <= 3'b001;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_16_SOFT_3 && abs_cons_i >= QAM_16_SOFT_2)
soft_bits[2:0] <= 3'b010;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_16_SOFT_4 && abs_cons_i >= QAM_16_SOFT_3)
soft_bits[2:0] <= 3'b011;
//
else
soft_bits[2:0] <= 3'b011;
// Quadrature soft decoded bits
if(abs_cons_q < QAM_16_SOFT_12 && abs_cons_q >= QAM_16_SOFT_11)
soft_bits[5:3] <= 3'b011;
else if(abs_cons_q < QAM_16_SOFT_11 && abs_cons_q >= QAM_16_SOFT_10)
soft_bits[5:3] <= 3'b010;
else if(abs_cons_q < QAM_16_SOFT_10 && abs_cons_q >= QAM_16_SOFT_9)
soft_bits[5:3] <= 3'b001;
else if(abs_cons_q < QAM_16_SOFT_9 && abs_cons_q >= QAM_16_SOFT_8)
soft_bits[5:3] <= 3'b000;
else if(abs_cons_q < QAM_16_SOFT_8 && abs_cons_q >= QAM_16_SOFT_7)
soft_bits[5:3] <= 3'b100;
else if(abs_cons_q < QAM_16_SOFT_7 && abs_cons_q >= QAM_16_SOFT_6)
soft_bits[5:3] <= 3'b101;
else if(abs_cons_q < QAM_16_SOFT_6 && abs_cons_q >= QAM_16_SOFT_5)
soft_bits[5:3] <= 3'b110;
else if(abs_cons_q < QAM_16_SOFT_5 && abs_cons_q >= QAM_16_SOFT_4)
soft_bits[5:3] <= 3'b111;
//
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_16_SOFT_4 && abs_cons_q >= QAM_16_SOFT_3)
soft_bits[5:3] <= 3'b111;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_16_SOFT_3 && abs_cons_q >= QAM_16_SOFT_2)
soft_bits[5:3] <= 3'b110;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_16_SOFT_2 && abs_cons_q >= QAM_16_SOFT_1)
soft_bits[5:3] <= 3'b101;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_16_SOFT_1 && abs_cons_q >= QAM_16_SOFT_0)
soft_bits[5:3] <= 3'b100;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_16_SOFT_1 && abs_cons_q >= QAM_16_SOFT_0)
soft_bits[5:3] <= 3'b000;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_16_SOFT_2 && abs_cons_q >= QAM_16_SOFT_1)
soft_bits[5:3] <= 3'b001;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_16_SOFT_3 && abs_cons_q >= QAM_16_SOFT_2)
soft_bits[5:3] <= 3'b010;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_16_SOFT_4 && abs_cons_q >= QAM_16_SOFT_3)
soft_bits[5:3] <= 3'b011;
//
else
soft_bits[5:3] <= 3'b011;
// Inphase soft decoded bit positions
if(abs_cons_i < QAM_16_SOFT_12 && abs_cons_i >= QAM_16_SOFT_4)
soft_bits_pos[1:0] <= 2'b01;
else if(abs_cons_i < QAM_16_SOFT_4)
soft_bits_pos[1:0] <= 2'b00;
else
soft_bits_pos[1:0] <= 2'b11;
// Quadrature soft decoded bit positions
if(abs_cons_q < QAM_16_SOFT_12 && abs_cons_q >= QAM_16_SOFT_4)
soft_bits_pos[3:2] <= 2'b01;
else if(abs_cons_q < QAM_16_SOFT_4)
soft_bits_pos[3:2] <= 2'b00;
else
soft_bits_pos[3:2] <= 2'b11;
end
QAM_64: begin
// Hard decoded bits
bits[0] <= ~cons_i_delayed[15];
bits[1] <= abs_cons_i < QAM_64_DIV_1? 1: 0;
bits[2] <= abs_cons_i > QAM_64_DIV_0 &&
abs_cons_i < QAM_64_DIV_2? 1: 0;
bits[3] <= ~cons_q_delayed[15];
bits[4] <= abs_cons_q < QAM_64_DIV_1? 1: 0;
bits[5] <= abs_cons_q > QAM_64_DIV_0 &&
abs_cons_q < QAM_64_DIV_2? 1: 0;
// Inphase soft decoded bits
if(abs_cons_i < QAM_64_SOFT_28 && abs_cons_i >= QAM_64_SOFT_27)
soft_bits[2:0] <= 3'b011;
else if(abs_cons_i < QAM_64_SOFT_27 && abs_cons_i >= QAM_64_SOFT_26)
soft_bits[2:0] <= 3'b010;
else if(abs_cons_i < QAM_64_SOFT_26 && abs_cons_i >= QAM_64_SOFT_25)
soft_bits[2:0] <= 3'b001;
else if(abs_cons_i < QAM_64_SOFT_25 && abs_cons_i >= QAM_64_SOFT_24)
soft_bits[2:0] <= 3'b000;
else if(abs_cons_i < QAM_64_SOFT_24 && abs_cons_i >= QAM_64_SOFT_23)
soft_bits[2:0] <= 3'b100;
else if(abs_cons_i < QAM_64_SOFT_23 && abs_cons_i >= QAM_64_SOFT_22)
soft_bits[2:0] <= 3'b101;
else if(abs_cons_i < QAM_64_SOFT_22 && abs_cons_i >= QAM_64_SOFT_21)
soft_bits[2:0] <= 3'b110;
else if(abs_cons_i < QAM_64_SOFT_21 && abs_cons_i >= QAM_64_SOFT_20)
soft_bits[2:0] <= 3'b111;
//
else if(abs_cons_i < QAM_64_SOFT_20 && abs_cons_i >= QAM_64_SOFT_19)
soft_bits[2:0] <= 3'b010;
else if(abs_cons_i < QAM_64_SOFT_19 && abs_cons_i >= QAM_64_SOFT_18)
soft_bits[2:0] <= 3'b010;
else if(abs_cons_i < QAM_64_SOFT_18 && abs_cons_i >= QAM_64_SOFT_17)
soft_bits[2:0] <= 3'b001;
else if(abs_cons_i < QAM_64_SOFT_17 && abs_cons_i >= QAM_64_SOFT_16)
soft_bits[2:0] <= 3'b000;
else if(abs_cons_i < QAM_64_SOFT_16 && abs_cons_i >= QAM_64_SOFT_15)
soft_bits[2:0] <= 3'b100;
else if(abs_cons_i < QAM_64_SOFT_15 && abs_cons_i >= QAM_64_SOFT_14)
soft_bits[2:0] <= 3'b101;
else if(abs_cons_i < QAM_64_SOFT_14 && abs_cons_i >= QAM_64_SOFT_13)
soft_bits[2:0] <= 3'b110;
else if(abs_cons_i < QAM_64_SOFT_13 && abs_cons_i >= QAM_64_SOFT_12)
soft_bits[2:0] <= 3'b111;
//
else if(abs_cons_i < QAM_64_SOFT_12 && abs_cons_i >= QAM_64_SOFT_11)
soft_bits[2:0] <= 3'b111;
else if(abs_cons_i < QAM_64_SOFT_11 && abs_cons_i >= QAM_64_SOFT_10)
soft_bits[2:0] <= 3'b110;
else if(abs_cons_i < QAM_64_SOFT_10 && abs_cons_i >= QAM_64_SOFT_9)
soft_bits[2:0] <= 3'b101;
else if(abs_cons_i < QAM_64_SOFT_9 && abs_cons_i >= QAM_64_SOFT_8)
soft_bits[2:0] <= 3'b100;
else if(abs_cons_i < QAM_64_SOFT_8 && abs_cons_i >= QAM_64_SOFT_7)
soft_bits[2:0] <= 3'b000;
else if(abs_cons_i < QAM_64_SOFT_7 && abs_cons_i >= QAM_64_SOFT_6)
soft_bits[2:0] <= 3'b001;
else if(abs_cons_i < QAM_64_SOFT_6 && abs_cons_i >= QAM_64_SOFT_5)
soft_bits[2:0] <= 3'b010;
else if(abs_cons_i < QAM_64_SOFT_5 && abs_cons_i >= QAM_64_SOFT_4)
soft_bits[2:0] <= 3'b011;
//
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_64_SOFT_4 && abs_cons_i >= QAM_64_SOFT_3)
soft_bits[2:0] <= 3'b111;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_64_SOFT_3 && abs_cons_i >= QAM_64_SOFT_2)
soft_bits[2:0] <= 3'b110;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_64_SOFT_2 && abs_cons_i >= QAM_64_SOFT_1)
soft_bits[2:0] <= 3'b101;
else if(cons_i_delayed[15] == 0 && abs_cons_i < QAM_64_SOFT_1 && abs_cons_i >= QAM_64_SOFT_0)
soft_bits[2:0] <= 3'b100;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_64_SOFT_1 && abs_cons_i >= QAM_64_SOFT_0)
soft_bits[2:0] <= 3'b000;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_64_SOFT_2 && abs_cons_i >= QAM_64_SOFT_1)
soft_bits[2:0] <= 3'b001;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_64_SOFT_3 && abs_cons_i >= QAM_64_SOFT_2)
soft_bits[2:0] <= 3'b010;
else if(cons_i_delayed[15] == 1 && abs_cons_i < QAM_64_SOFT_4 && abs_cons_i >= QAM_64_SOFT_3)
soft_bits[2:0] <= 3'b011;
//
else
soft_bits[2:0] <= 3'b011;
// Quadrature soft decoded bits
if(abs_cons_q < QAM_64_SOFT_28 && abs_cons_q >= QAM_64_SOFT_27)
soft_bits[5:3] <= 3'b011;
else if(abs_cons_q < QAM_64_SOFT_27 && abs_cons_q >= QAM_64_SOFT_26)
soft_bits[5:3] <= 3'b010;
else if(abs_cons_q < QAM_64_SOFT_26 && abs_cons_q >= QAM_64_SOFT_25)
soft_bits[5:3] <= 3'b001;
else if(abs_cons_q < QAM_64_SOFT_25 && abs_cons_q >= QAM_64_SOFT_24)
soft_bits[5:3] <= 3'b000;
else if(abs_cons_q < QAM_64_SOFT_24 && abs_cons_q >= QAM_64_SOFT_23)
soft_bits[5:3] <= 3'b100;
else if(abs_cons_q < QAM_64_SOFT_23 && abs_cons_q >= QAM_64_SOFT_22)
soft_bits[5:3] <= 3'b101;
else if(abs_cons_q < QAM_64_SOFT_22 && abs_cons_q >= QAM_64_SOFT_21)
soft_bits[5:3] <= 3'b110;
else if(abs_cons_q < QAM_64_SOFT_21 && abs_cons_q >= QAM_64_SOFT_20)
soft_bits[5:3] <= 3'b111;
//
else if(abs_cons_q < QAM_64_SOFT_20 && abs_cons_q >= QAM_64_SOFT_19)
soft_bits[5:3] <= 3'b010;
else if(abs_cons_q < QAM_64_SOFT_19 && abs_cons_q >= QAM_64_SOFT_18)
soft_bits[5:3] <= 3'b010;
else if(abs_cons_q < QAM_64_SOFT_18 && abs_cons_q >= QAM_64_SOFT_17)
soft_bits[5:3] <= 3'b001;
else if(abs_cons_q < QAM_64_SOFT_17 && abs_cons_q >= QAM_64_SOFT_16)
soft_bits[5:3] <= 3'b000;
else if(abs_cons_q < QAM_64_SOFT_16 && abs_cons_q >= QAM_64_SOFT_15)
soft_bits[5:3] <= 3'b100;
else if(abs_cons_q < QAM_64_SOFT_15 && abs_cons_q >= QAM_64_SOFT_14)
soft_bits[5:3] <= 3'b101;
else if(abs_cons_q < QAM_64_SOFT_14 && abs_cons_q >= QAM_64_SOFT_13)
soft_bits[5:3] <= 3'b110;
else if(abs_cons_q < QAM_64_SOFT_13 && abs_cons_q >= QAM_64_SOFT_12)
soft_bits[5:3] <= 3'b111;
//
else if(abs_cons_q < QAM_64_SOFT_12 && abs_cons_q >= QAM_64_SOFT_11)
soft_bits[5:3] <= 3'b111;
else if(abs_cons_q < QAM_64_SOFT_11 && abs_cons_q >= QAM_64_SOFT_10)
soft_bits[5:3] <= 3'b110;
else if(abs_cons_q < QAM_64_SOFT_10 && abs_cons_q >= QAM_64_SOFT_9)
soft_bits[5:3] <= 3'b101;
else if(abs_cons_q < QAM_64_SOFT_9 && abs_cons_q >= QAM_64_SOFT_8)
soft_bits[5:3] <= 3'b100;
else if(abs_cons_q < QAM_64_SOFT_8 && abs_cons_q >= QAM_64_SOFT_7)
soft_bits[5:3] <= 3'b000;
else if(abs_cons_q < QAM_64_SOFT_7 && abs_cons_q >= QAM_64_SOFT_6)
soft_bits[5:3] <= 3'b001;
else if(abs_cons_q < QAM_64_SOFT_6 && abs_cons_q >= QAM_64_SOFT_5)
soft_bits[5:3] <= 3'b010;
else if(abs_cons_q < QAM_64_SOFT_5 && abs_cons_q >= QAM_64_SOFT_4)
soft_bits[5:3] <= 3'b011;
//
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_64_SOFT_4 && abs_cons_q >= QAM_64_SOFT_3)
soft_bits[5:3] <= 3'b111;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_64_SOFT_3 && abs_cons_q >= QAM_64_SOFT_2)
soft_bits[5:3] <= 3'b110;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_64_SOFT_2 && abs_cons_q >= QAM_64_SOFT_1)
soft_bits[5:3] <= 3'b101;
else if(cons_q_delayed[15] == 0 && abs_cons_q < QAM_64_SOFT_1 && abs_cons_q >= QAM_64_SOFT_0)
soft_bits[5:3] <= 3'b100;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_64_SOFT_1 && abs_cons_q >= QAM_64_SOFT_0)
soft_bits[5:3] <= 3'b000;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_64_SOFT_2 && abs_cons_q >= QAM_64_SOFT_1)
soft_bits[5:3] <= 3'b001;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_64_SOFT_3 && abs_cons_q >= QAM_64_SOFT_2)
soft_bits[5:3] <= 3'b010;
else if(cons_q_delayed[15] == 1 && abs_cons_q < QAM_64_SOFT_4 && abs_cons_q >= QAM_64_SOFT_3)
soft_bits[5:3] <= 3'b011;
//
else
soft_bits[5:3] <= 3'b011;
// Inphase soft decoded bit positions
if(abs_cons_i < QAM_64_SOFT_28 && abs_cons_i >= QAM_64_SOFT_20)
soft_bits_pos[1:0] <= 2'b10;
else if(abs_cons_i < QAM_64_SOFT_20 && abs_cons_i >= QAM_64_SOFT_12)
soft_bits_pos[1:0] <= 2'b01;
else if(abs_cons_i < QAM_64_SOFT_12 && abs_cons_i >= QAM_64_SOFT_4)
soft_bits_pos[1:0] <= 2'b10;
else if(abs_cons_i < QAM_64_SOFT_4)
soft_bits_pos[1:0] <= 2'b00;
else
soft_bits_pos[1:0] <= 2'b11;
// Quadrature soft decoded bit positions
if(abs_cons_q < QAM_64_SOFT_28 && abs_cons_q >= QAM_64_SOFT_20)
soft_bits_pos[3:2] <= 2'b10;
else if(abs_cons_q < QAM_64_SOFT_20 && abs_cons_q >= QAM_64_SOFT_12)
soft_bits_pos[3:2] <= 2'b01;
else if(abs_cons_q < QAM_64_SOFT_12 && abs_cons_q >= QAM_64_SOFT_4)
soft_bits_pos[3:2] <= 2'b10;
else if(abs_cons_q < QAM_64_SOFT_4)
soft_bits_pos[3:2] <= 2'b00;
else
soft_bits_pos[3:2] <= 2'b11;
end
endcase
end
end
endmodule |
module equalizer
(
input clock,
input enable,
input reset,
input [31:0] sample_in,
input sample_in_strobe,
input ht_next,
input pkt_ht,
input ht_smoothing,
input wire disable_all_smoothing,
output [31:0] phase_in_i,
output [31:0] phase_in_q,
output reg phase_in_stb,
input [15:0] phase_out,
input phase_out_stb,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
output reg [31:0] sample_out,
output reg sample_out_strobe,
output reg [3:0] state,
// for side channel
output wire [31:0] csi,
output wire csi_valid
);
// mask[0] is DC, mask[1:26] -> 1,..., 26
// mask[38:63] -> -26,..., -1
localparam SUBCARRIER_MASK =
64'b1111111111111111111111111100000000000111111111111111111111111110;
localparam HT_SUBCARRIER_MASK =
64'b1111111111111111111111111111000000011111111111111111111111111110;
// -7, -21, 21, 7
localparam PILOT_MASK =
64'b0000001000000000000010000000000000000000001000000000000010000000;
localparam DATA_SUBCARRIER_MASK =
SUBCARRIER_MASK ^ PILOT_MASK;
localparam HT_DATA_SUBCARRIER_MASK =
HT_SUBCARRIER_MASK ^ PILOT_MASK;
// -1,..,-26, 26,..,1
localparam LTS_REF =
64'b0000101001100000010100110000000000000000010101100111110101001100;
localparam HT_LTS_REF =
64'b0000101001100000010100110000000000011000010101100111110101001100;
localparam POLARITY =
127'b1111111000111011000101001011111010101000010110111100111001010110011000001101101011101000110010001000000100100110100111101110000;
// 21, 7, -7, -21
localparam HT_POLARITY = 4'b1000;
localparam IN_BUF_LEN_SHIFT = 6;
reg enable_delay;
wire reset_internal = (enable==0 && enable_delay==1);//reset internal after the module is disabled in case the disable lock the state/stb to a non-end state.
reg ht;
reg [5:0] num_data_carrier;
reg [7:0] num_ofdm_sym;
// bit masks
reg [63:0] lts_ref;
reg [63:0] ht_lts_ref;
reg [63:0] subcarrier_mask;
reg [63:0] data_subcarrier_mask;
reg [63:0] pilot_mask;
reg [5:0] pilot_loc[3:0];
reg signed [5:0] pilot_idx[3:0];
localparam pilot_loc1 = 7;
localparam pilot_loc2 = 21;
localparam pilot_loc3 = 43;
localparam pilot_loc4 = 57;
localparam signed pilot_idx1 = 8;
localparam signed pilot_idx2 = 22;
localparam signed pilot_idx3 = -20;
localparam signed pilot_idx4 = -6;
initial begin
pilot_loc[0] = pilot_loc1;
pilot_idx[0] = pilot_idx1;
pilot_loc[1] = pilot_loc2;
pilot_idx[1] = pilot_idx2;
pilot_loc[2] = pilot_loc3;
pilot_idx[2] = pilot_idx3;
pilot_loc[3] = pilot_loc4;
pilot_idx[3] = pilot_idx4;
end
reg [126:0] polarity;
reg [3:0] ht_polarity;
reg [3:0] current_polarity;
reg [3:0] pilot_count1, pilot_count2, pilot_count3;
reg signed [15:0] input_i;
reg signed [15:0] input_q;
reg current_sign;
wire signed [15:0] new_lts_i;
wire signed [15:0] new_lts_q;
wire new_lts_stb;
reg calc_mean_strobe;
reg [5:0] lts_waddr;
reg [6:0] lts_raddr; // one bit wider to detect overflow
reg [15:0] lts_i_in;
reg [15:0] lts_q_in;
reg lts_in_stb;
wire signed [15:0] lts_i_out;
wire signed [15:0] lts_q_out;
wire signed [15:0] lts_q_out_neg = ~lts_q_out + 1;
reg [5:0] in_waddr;
reg [6:0] in_raddr;
wire [15:0] buf_i_out;
wire [15:0] buf_q_out;
reg pilot_in_stb;
wire signed [31:0] pilot_i;
wire signed [31:0] pilot_q;
reg signed [31:0] pilot_i_reg, pilot_q_reg;
reg signed [15:0] pilot_iq_phase[0:3];
reg signed [31:0] pilot_sum_i;
reg signed [31:0] pilot_sum_q;
assign phase_in_i = pilot_i_reg;
assign phase_in_q = pilot_q_reg;
//reg signed [15:0] pilot_phase_err;
reg signed [16:0] pilot_phase_err; // 15 --> 16 = 15 + 1, extended from cpe
reg signed [15:0] cpe; // common phase error due to RFO
//reg signed [15:0] Sxy;
reg signed [23:0] Sxy; // 15-->23. to avoid overflow: pilot_phase_err 16 + 5 + 2. 5 for 21* (rounding to 32); 2 for 4 pilots
localparam Sx2 = 980;
// linear varying phase error (LVPE) parameters
reg signed [7:0] sym_idx, sym_idx2;
reg lvpe_in_stb;
wire lvpe_out_stb;
wire signed [31:0] lvpe_dividend, lvpe, peg_sym_scale;
wire signed [23:0] lvpe_divisor;
assign lvpe_dividend = (sym_idx <= 33 ? sym_idx*Sxy : (sym_idx-64)*Sxy);
assign lvpe_divisor = Sx2;
reg signed [31:0] prev_peg, prev_peg_reg, peg_pilot_scale;
assign peg_sym_scale = (sym_idx2 <= 33 ? sym_idx2*prev_peg : (sym_idx2-64)*prev_peg);
//reg signed [15:0] phase_err;
reg signed [17:0] phase_err; // 15-->16: phase_err <= cpe + lvpe[17:0]; 16 + 1 = 17 for sym_phase
//wire signed [15:0] sym_phase;
wire signed [17:0] sym_phase;// phase_err 16 + 1
assign sym_phase = (phase_err > 1608) ? (phase_err - 3217) : ((phase_err < -1608) ? (phase_err + 3217) : phase_err);//only taking [15:0] to rotate could have overflow!
reg rot_in_stb;
wire signed [15:0] rot_i;
wire signed [15:0] rot_q;
wire [31:0] mag_sq;
wire [31:0] prod_i;
wire [31:0] prod_q;
wire [31:0] prod_i_scaled = prod_i<<(`CONS_SCALE_SHIFT+1);
wire [31:0] prod_q_scaled = prod_q<<(`CONS_SCALE_SHIFT+1); // +1 to fix the bug threshold for demodulate.v
wire prod_stb;
reg signed [15:0] lts_reg1_i, lts_reg2_i, lts_reg3_i, lts_reg4_i, lts_reg5_i;
reg signed [15:0] lts_reg1_q, lts_reg2_q, lts_reg3_q, lts_reg4_q, lts_reg5_q;
wire signed [18:0] lts_sum_1_3_i = lts_reg1_i + lts_reg2_i + lts_reg3_i;
wire signed [18:0] lts_sum_1_3_q = lts_reg1_q + lts_reg2_q + lts_reg3_q;
wire signed [18:0] lts_sum_1_4_i = lts_reg1_i + lts_reg2_i + lts_reg3_i + lts_reg4_i;
wire signed [18:0] lts_sum_1_4_q = lts_reg1_q + lts_reg2_q + lts_reg3_q + lts_reg4_q;
wire signed [18:0] lts_sum_1_5_i = lts_reg1_i + lts_reg2_i + lts_reg3_i + lts_reg4_i + lts_reg5_i;
wire signed [18:0] lts_sum_1_5_q = lts_reg1_q + lts_reg2_q + lts_reg3_q + lts_reg4_q + lts_reg5_q;
wire signed [18:0] lts_sum_2_5_i = lts_reg2_i + lts_reg3_i + lts_reg4_i + lts_reg5_i;
wire signed [18:0] lts_sum_2_5_q = lts_reg2_q + lts_reg3_q + lts_reg4_q + lts_reg5_q;
wire signed [18:0] lts_sum_3_5_i = lts_reg3_i + lts_reg4_i + lts_reg5_i;
wire signed [18:0] lts_sum_3_5_q = lts_reg3_q + lts_reg4_q + lts_reg5_q;
wire signed [18:0] lts_sum_wo3_i = lts_reg1_i + lts_reg2_i + lts_reg4_i + lts_reg5_i;
wire signed [18:0] lts_sum_wo3_q = lts_reg1_q + lts_reg2_q + lts_reg4_q + lts_reg5_q;
reg signed [18:0] lts_sum_i;
reg signed [18:0] lts_sum_q;
reg [2:0] lts_mv_avg_len;
reg lts_div_in_stb;
wire [31:0] dividend_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_i[18] == 0 ? {13'h0,lts_sum_i} : {13'h1FFF,lts_sum_i}) : (state == S_ALL_SC_PE_CORRECTION ? prod_i_scaled : 0);
wire [31:0] dividend_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? (lts_sum_q[18] == 0 ? {13'h0,lts_sum_q} : {13'h1FFF,lts_sum_q}) : (state == S_ALL_SC_PE_CORRECTION ? prod_q_scaled : 0);
wire [23:0] divisor_i = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
wire [23:0] divisor_q = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? {21'b0,lts_mv_avg_len} : (state == S_ALL_SC_PE_CORRECTION ? mag_sq[23:0] : 1);
wire div_in_stb = (state == S_SMOOTH_CH_DC || state == S_SMOOTH_CH_LTS) ? lts_div_in_stb : (state == S_ALL_SC_PE_CORRECTION ? prod_out_strobe : 0);
reg [15:0] num_output;
wire [31:0] quotient_i;
wire [31:0] quotient_q;
wire [31:0] norm_i = quotient_i;
wire [31:0] norm_q = quotient_q;
wire [31:0] lts_div_i = quotient_i;
wire [31:0] lts_div_q = quotient_q;
wire div_out_stb;
wire norm_out_stb = div_out_stb;
wire lts_div_out_stb = div_out_stb;
reg prod_in_strobe;
wire prod_out_strobe;
// for side channel
reg sample_in_strobe_dly;
assign csi = {lts_i_out, lts_q_out};
assign csi_valid = ( (num_ofdm_sym == 1 || (pkt_ht==1 && num_ofdm_sym==5)) && state == S_CPE_ESTIMATE && sample_in_strobe_dly == 1 && enable && (~reset) );
always @(posedge clock) begin
if (reset) begin
enable_delay <= 0;
end else begin
enable_delay <= enable;
end
end
ram_2port #(.DWIDTH(32), .AWIDTH(6)) lts_inst (
.clka(clock),
.ena(1),
.wea(lts_in_stb),
.addra(lts_waddr),
.dia({lts_i_in, lts_q_in}),
.doa(),
.clkb(clock),
.enb(1),
.web(1'b0),
.addrb(lts_raddr[5:0]),
.dib(32'hFFFF),
.dob({lts_i_out, lts_q_out})
);
calc_mean lts_i_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.a(lts_i_out),
.b(input_i),
.sign(current_sign),
.input_strobe(calc_mean_strobe),
.c(new_lts_i),
.output_strobe(new_lts_stb)
);
calc_mean lts_q_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.a(lts_q_out),
.b(input_q),
.sign(current_sign),
.input_strobe(calc_mean_strobe),
.c(new_lts_q)
);
ram_2port #(.DWIDTH(32), .AWIDTH(6)) in_buf_inst (
.clka(clock),
.ena(1),
.wea(sample_in_strobe),
.addra(in_waddr),
.dia(sample_in),
.doa(),
.clkb(clock),
.enb(1),
.web(1'b0),
.addrb(in_raddr[5:0]),
.dib(32'hFFFF),
.dob({buf_i_out, buf_q_out})
);
complex_mult pilot_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.a_i(input_i),
.a_q(input_q),
.b_i(lts_i_out),
.b_q(lts_q_out),
.input_strobe(pilot_in_stb),
.p_i(pilot_i),
.p_q(pilot_q),
.output_strobe(pilot_out_stb)
);
rotate rotate_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.in_i(buf_i_out),
.in_q(buf_q_out),
// .phase(sym_phase),
.phase(sym_phase[15:0]),//only taking [15:0] to rotate could have overflow!
.input_strobe(rot_in_stb),
.rot_addr(rot_addr),
.rot_data(rot_data),
.out_i(rot_i),
.out_q(rot_q),
.output_strobe(rot_out_stb)
);
complex_mult input_lts_prod_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.a_i(rot_i),
.a_q(rot_q),
.b_i(lts_i_out),
.b_q(lts_q_out_neg),
.input_strobe(rot_out_stb),
.p_i(prod_i),
.p_q(prod_q),
.output_strobe(prod_out_strobe)
);
complex_mult lts_lts_prod_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.a_i(lts_i_out),
.a_q(lts_q_out),
.b_i(lts_i_out),
.b_q(lts_q_out_neg),
.input_strobe(rot_out_stb),
.p_i(mag_sq)
);
divider norm_i_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.dividend(dividend_i),
.divisor(divisor_i),
.input_strobe(div_in_stb),
.quotient(quotient_i),
.output_strobe(div_out_stb)
);
divider norm_q_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.dividend(dividend_q),
.divisor(divisor_q),
.input_strobe(div_in_stb),
.quotient(quotient_q)
);
// LVPE calculation to estimate SFO
divider lvpe_inst (
.clock(clock),
.enable(enable),
.reset(reset|reset_internal),
.dividend(lvpe_dividend),
.divisor(lvpe_divisor),
.input_strobe(lvpe_in_stb),
.quotient(lvpe),
.output_strobe(lvpe_out_stb)
);
localparam S_FIRST_LTS = 0;
localparam S_SECOND_LTS = 1;
localparam S_SMOOTH_CH_DC = 2;
localparam S_SMOOTH_CH_LTS = 3;
localparam S_GET_POLARITY = 4;
localparam S_CPE_ESTIMATE = 5;
localparam S_PILOT_PE_CORRECTION = 6;
localparam S_LVPE_ESTIMATE = 7;
localparam S_ALL_SC_PE_CORRECTION = 8;
localparam S_HT_LTS = 9;
always @(posedge clock) begin
if (reset|reset_internal) begin
sample_out_strobe <= 0;
lts_raddr <= 0;
lts_waddr <= 0;
sample_out <= 0;
lts_in_stb <= 0;
lts_i_in <= 0;
lts_q_in <= 0;
ht <= 0;
num_data_carrier <= 48;
num_ofdm_sym <= 0;
subcarrier_mask <= SUBCARRIER_MASK;
data_subcarrier_mask <= DATA_SUBCARRIER_MASK;
pilot_mask <= PILOT_MASK;
lts_ref <= LTS_REF;
ht_lts_ref <= HT_LTS_REF;
polarity <= POLARITY;
ht_polarity <= HT_POLARITY;
current_polarity <= 0;
pilot_count1 <= 0;
pilot_count2 <= 0;
pilot_count3 <= 0;
in_waddr <= 0;
in_raddr <= 0;
sym_idx <= 0;
sym_idx2 <= 0;
lts_reg1_i <= 0; lts_reg2_i <= 0; lts_reg3_i <= 0; lts_reg4_i <= 0; lts_reg5_i <= 0;
lts_reg1_q <= 0; lts_reg2_q <= 0; lts_reg3_q <= 0; lts_reg4_q <= 0; lts_reg5_q <= 0;
lts_sum_i <= 0;
lts_sum_q <= 0;
lts_mv_avg_len <= 0;
lts_div_in_stb <= 0;
phase_in_stb <= 0;
pilot_sum_i <= 0;
pilot_sum_q <= 0;
pilot_phase_err <= 0;
cpe <= 0;
Sxy <= 0;
lvpe_in_stb <= 0;
phase_err <= 0;
pilot_in_stb <= 0;
pilot_i_reg <= 0;
pilot_q_reg <= 0;
pilot_iq_phase[0] <= 0; pilot_iq_phase[1] <= 0; pilot_iq_phase[2] <= 0; pilot_iq_phase[3] <= 0;
prev_peg <= 0;
prev_peg_reg <= 0;
peg_pilot_scale <= 0;
prod_in_strobe <= 0;
rot_in_stb <= 0;
current_sign <= 0;
input_i <= 0;
input_q <= 0;
calc_mean_strobe <= 0;
num_output <= 0;
state <= S_FIRST_LTS;
end else if (enable) begin
sample_in_strobe_dly <= sample_in_strobe;
case(state)
S_FIRST_LTS: begin
// store first LTS as is
lts_in_stb <= sample_in_strobe;
{lts_i_in, lts_q_in} <= sample_in;
if (lts_in_stb) begin
if (lts_waddr == 63) begin
lts_waddr <= 0;
lts_raddr <= 0;
state <= S_SECOND_LTS;
end else begin
lts_waddr <= lts_waddr + 1;
end
end
end
S_SECOND_LTS: begin
// calculate and store the mean of the two LTS
if (sample_in_strobe) begin
calc_mean_strobe <= sample_in_strobe;
{input_i, input_q} <= sample_in;
current_sign <= lts_ref[0];
lts_ref <= {lts_ref[0], lts_ref[63:1]};
lts_raddr <= lts_raddr + 1;
end else begin
calc_mean_strobe <= 0;
end
lts_in_stb <= new_lts_stb;
{lts_i_in, lts_q_in} <= {new_lts_i, new_lts_q};
if (lts_in_stb) begin
if (lts_waddr == 63) begin
lts_waddr <= 0;
lts_raddr <= 62;
lts_in_stb <= 0;
lts_div_in_stb <= 0;
state <= (disable_all_smoothing?S_GET_POLARITY:S_SMOOTH_CH_DC);
end else begin
lts_waddr <= lts_waddr + 1;
end
end
end
// 802.11-2012.pdf: 20.3.9.4.3 Table 20-11
// channel estimate smoothing (averaging length = 5)
S_SMOOTH_CH_DC: begin
if(lts_div_in_stb == 1) begin
lts_div_in_stb <= 0;
end else if(lts_raddr == 4) begin
lts_sum_i <= lts_sum_wo3_i;
lts_sum_q <= lts_sum_wo3_q;
lts_mv_avg_len <= 4;
lts_div_in_stb <= 1;
lts_raddr <= 5;
end else if(lts_raddr != 5) begin
// LTS Shift register
lts_reg1_i <= lts_i_out; lts_reg2_i <= lts_reg1_i; lts_reg3_i <= lts_reg2_i; lts_reg4_i <= lts_reg3_i; lts_reg5_i <= lts_reg4_i;
lts_reg1_q <= lts_q_out; lts_reg2_q <= lts_reg1_q; lts_reg3_q <= lts_reg2_q; lts_reg4_q <= lts_reg3_q; lts_reg5_q <= lts_reg4_q;
lts_raddr[5:0] <= lts_raddr[5:0] + 1;
end else begin
if(lts_in_stb == 1) begin
lts_waddr <= 37;
lts_raddr <= 38;
lts_in_stb <= 0;
state <= S_SMOOTH_CH_LTS;
end else if(lts_div_out_stb == 1) begin
lts_i_in <= lts_div_i[15:0];
lts_q_in <= lts_div_q[15:0];
lts_in_stb <= 1;
end
end
end
// 802.11-2012.pdf: 20.3.9.4.3 Table 20-11
// channel estimate smoothing (averaging length = 5)
S_SMOOTH_CH_LTS: begin
if(lts_raddr == 42) begin
lts_sum_i <= lts_sum_1_3_i;
lts_sum_q <= lts_sum_1_3_q;
lts_mv_avg_len <= 3;
lts_div_in_stb <= 1;
end else if(lts_raddr == 43) begin
lts_sum_i <= lts_sum_1_4_i;
lts_sum_q <= lts_sum_1_4_q;
lts_mv_avg_len <= 4;
lts_div_in_stb <= 1;
end else if(lts_raddr > 43 || lts_raddr < 29) begin
lts_sum_i <= lts_sum_1_5_i;
lts_sum_q <= lts_sum_1_5_q;
lts_mv_avg_len <= 5;
lts_div_in_stb <= 1;
end else if(lts_raddr == 29) begin
lts_sum_i <= lts_sum_2_5_i;
lts_sum_q <= lts_sum_2_5_q;
lts_mv_avg_len <= 4;
lts_div_in_stb <= 1;
end else if(lts_raddr == 30) begin
lts_sum_i <= lts_sum_3_5_i;
lts_sum_q <= lts_sum_3_5_q;
lts_mv_avg_len <= 3;
lts_div_in_stb <= 1;
end else if(lts_raddr == 31) begin
lts_div_in_stb <= 0;
end
if(lts_raddr >= 38 || lts_raddr <= 30) begin
// LTS Shift register
lts_reg1_i <= lts_i_out; lts_reg2_i <= lts_reg1_i; lts_reg3_i <= lts_reg2_i; lts_reg4_i <= lts_reg3_i; lts_reg5_i <= lts_reg4_i;
lts_reg1_q <= lts_q_out; lts_reg2_q <= lts_reg1_q; lts_reg3_q <= lts_reg2_q; lts_reg4_q <= lts_reg3_q; lts_reg5_q <= lts_reg4_q;
lts_raddr[5:0] <= lts_raddr[5:0] + 1;
end
if(lts_div_out_stb == 1) begin
lts_i_in <= lts_div_i[15:0];
lts_q_in <= lts_div_q[15:0];
lts_waddr[5:0] <= lts_waddr[5:0] + 1;
end
lts_in_stb <= lts_div_out_stb;
if(lts_waddr == 26) begin
state <= S_GET_POLARITY;
end
end
S_GET_POLARITY: begin
// obtain the polarity of pilot sub-carriers for next OFDM symbol
if (ht) begin
current_polarity <= {
ht_polarity[1]^polarity[0], // -7
ht_polarity[0]^polarity[0], // -21
ht_polarity[3]^polarity[0], // 21
ht_polarity[2]^polarity[0] // 7
};
ht_polarity <= {ht_polarity[0], ht_polarity[3:1]};
end else begin
current_polarity <= {
polarity[0], // -7
polarity[0], // -21
~polarity[0], // 21
polarity[0] // 7
};
end
polarity <= {polarity[0], polarity[126:1]};
pilot_sum_i <= 0;
pilot_sum_q <= 0;
pilot_count1 <= 0;
pilot_count2 <= 0;
cpe <= 0;
in_waddr <= 0;
in_raddr <= 0;
input_i <= 0;
input_q <= 0;
lts_raddr <= 0;
num_ofdm_sym <= num_ofdm_sym + 1;
state <= S_CPE_ESTIMATE;
end
S_CPE_ESTIMATE: begin
if (~ht & ht_next) begin
ht <= 1;
num_data_carrier <= 52;
lts_waddr <= 0;
lts_ref <= HT_LTS_REF;
subcarrier_mask <= HT_SUBCARRIER_MASK;
data_subcarrier_mask <= HT_DATA_SUBCARRIER_MASK;
pilot_mask <= PILOT_MASK;
// reverse this extra shift
polarity <= {polarity[125:0], polarity[126]};
state <= S_HT_LTS;
end
// calculate residue freq offset using pilot sub carriers
if (sample_in_strobe) begin
in_waddr <= in_waddr + 1;
lts_raddr <= lts_raddr + 1;
pilot_mask <= {pilot_mask[0], pilot_mask[63:1]};
if (pilot_mask[0]) begin
pilot_count1 <= pilot_count1 + 1;
// obtain the conjugate of current pilot sub carrier
if (current_polarity[pilot_count1] == 0) begin
input_i <= sample_in[31:16];
input_q <= ~sample_in[15:0] + 1;
end else begin
input_i <= ~sample_in[31:16] + 1;
input_q <= sample_in[15:0];
end
pilot_in_stb <= 1;
end else begin
pilot_in_stb <= 0;
end
end else begin
pilot_in_stb <= 0;
end
if (pilot_out_stb) begin
pilot_sum_i <= pilot_sum_i + pilot_i;
pilot_sum_q <= pilot_sum_q + pilot_q;
pilot_count2 <= pilot_count2 + 1;
end else if (pilot_count2 == 4) begin
pilot_i_reg <= pilot_sum_i;
pilot_q_reg <= pilot_sum_q;
phase_in_stb <= 1;
pilot_count2 <= 0;
end else begin
phase_in_stb <= 0;
end
if (phase_out_stb) begin
cpe <= phase_out;
pilot_count1 <= 0;
pilot_count2 <= 0;
pilot_count3 <= 0;
Sxy <= 0;
in_raddr <= pilot_loc[0][5:0]; // sample in location, compensate for RAM read delay
lts_raddr <= pilot_loc[0][5:0]; // LTS location, compensate for RAM read delay
peg_pilot_scale <= pilot_idx[0]*prev_peg;
state <= S_PILOT_PE_CORRECTION;
end
end
S_PILOT_PE_CORRECTION: begin
// rotate pilots with accumulated PEG up to previous symbol
if (pilot_count1 < 4) begin
if (pilot_count1 < 3) begin
in_raddr <= pilot_loc[pilot_count1+1][5:0];
peg_pilot_scale <= (pilot_idx[pilot_count1+1])*prev_peg;
rot_in_stb <= 1;
end
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + peg_pilot_scale[17:0];
pilot_count1 <= pilot_count1 + 1;
end else begin
rot_in_stb <= 0;
end
if (rot_out_stb && pilot_count2 < 4) begin
if (pilot_count2 < 3) begin
lts_raddr <= pilot_loc[pilot_count2+1][5:0];
end
// obtain the conjugate of current pilot sub carrier
if (current_polarity[pilot_count2] == 0) begin
input_i <= rot_i;
input_q <= -rot_q;
end else begin
input_i <= -rot_i;
input_q <= rot_q;
end
pilot_in_stb <= 1; // start complex mult. with LTS pilot
pilot_count2 <= pilot_count2 + 1;
end else begin
pilot_in_stb <= 0;
end
if (pilot_out_stb) begin
pilot_i_reg <= pilot_i;
pilot_q_reg <= pilot_q;
phase_in_stb <= 1;
end else begin
phase_in_stb <= 0;
end
if (phase_out_stb && pilot_count3 < 4) begin
pilot_count3 <= pilot_count3 + 1;
pilot_iq_phase[pilot_count3] <= phase_out;
end
if (pilot_count3 == 4) begin
phase_in_stb <= 0;
pilot_count1 <= 0;
pilot_count2 <= 0;
pilot_count3 <= 0;
state <= S_LVPE_ESTIMATE;
end
end
S_LVPE_ESTIMATE: begin
if (pilot_count1 < 4) begin
// sampling rate offset (SFO) is calculated as pilot phase error
if(pilot_iq_phase[pilot_count1] < -1608) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] + 3217;
end else if(pilot_iq_phase[pilot_count1] > 1608) begin
pilot_phase_err <= pilot_iq_phase[pilot_count1] - 3217;
end else begin
pilot_phase_err <= pilot_iq_phase[pilot_count1];
end
pilot_count1 <= pilot_count1 + 1;
end
if(pilot_count1 == 1) begin
Sxy <= Sxy + 7*pilot_phase_err;
end else if(pilot_count1 == 2) begin
Sxy <= Sxy + 21*pilot_phase_err;
end else if(pilot_count1 == 3) begin
Sxy <= Sxy + -21*pilot_phase_err;
end else if(pilot_count1 == 4) begin
Sxy <= Sxy + -7*pilot_phase_err;
in_raddr <= 0;
sym_idx <= 0;
sym_idx2 <= 1;
lvpe_in_stb <= 0;
// compensate for RAM read delay
lts_raddr <= 1;
rot_in_stb <= 0;
num_output <= 0;
state <= S_ALL_SC_PE_CORRECTION;
end
// Sx² = ∑(x-x̄)*(x-x̄) = ∑x² = (7² + 21² + (-21)² + (-7)²) = 980
// phase error gradient (PEG) = Sxy/Sx²
end
S_ALL_SC_PE_CORRECTION: begin
if (sym_idx < 64) begin
sym_idx <= sym_idx + 1;
lvpe_in_stb <= 1;
end else begin
lvpe_in_stb <= 0;
end
// first rotate, then normalize by avg LTS
if (lvpe_out_stb) begin
sym_idx2 <= sym_idx2 + 1;
phase_err <= {cpe[15], cpe[15], cpe[15:0]} + lvpe[17:0] + peg_sym_scale[17:0];
rot_in_stb <= 1;
in_raddr <= in_raddr + 1;
if (sym_idx2 == 32) begin
// lvpe output is 32*PEG due to sym_idx
prev_peg_reg <= prev_peg_reg + (lvpe >>> 5);
end
end else begin
rot_in_stb <= 0;
end
if (rot_out_stb) begin
lts_raddr <= lts_raddr + 1;
end
if (norm_out_stb) begin
data_subcarrier_mask <= {data_subcarrier_mask[0],
data_subcarrier_mask[63:1]};
if (data_subcarrier_mask[0]) begin
sample_out_strobe <= 1;
sample_out <= {norm_i[31], norm_i[14:0],
norm_q[31], norm_q[14:0]};
num_output <= num_output + 1;
end else begin
sample_out_strobe <= 0;
end
end else begin
sample_out_strobe <= 0;
end
if (num_output == num_data_carrier) begin
prev_peg <= prev_peg_reg;
state <= S_GET_POLARITY;
end
end
S_HT_LTS: begin
if (sample_in_strobe) begin
lts_in_stb <= 1;
ht_lts_ref <= {ht_lts_ref[0], ht_lts_ref[63:1]};
if (ht_lts_ref[0] == 0) begin
{lts_i_in, lts_q_in} <= sample_in;
end else begin
lts_i_in <= ~sample_in[31:16]+1;
lts_q_in <= ~sample_in[15:0]+1;
end
end else begin
lts_in_stb <= 0;
end
if (lts_in_stb) begin
if (lts_waddr == 63) begin
lts_waddr <= 0;
lts_raddr <= 62;
lts_in_stb <= 0;
lts_div_in_stb <= 0;
// Depending on smoothing bit in HT-SIG, smooth the channel
if(ht_smoothing==1 && disable_all_smoothing==0) begin
state <= S_SMOOTH_CH_DC;
end else begin
state <= S_GET_POLARITY;
end
end else begin
lts_waddr <= lts_waddr + 1;
end
end
end
default: begin
state <= S_FIRST_LTS;
end
endcase
end else begin
sample_out_strobe <= 0;
end
end
endmodule |
module ofdm_decoder
(
input clock,
input enable,
input reset,
input [31:0] sample_in,
input sample_in_strobe,
input soft_decoding,
// decode instructions
input [7:0] rate,
input do_descramble,
input [19:0] num_bits_to_decode, //4bits + ht_len: num_bits_to_decode <= (22+(ht_len<<3));
output [5:0] demod_out,
output [5:0] demod_soft_bits,
output [3:0] demod_soft_bits_pos,
output demod_out_strobe,
output [7:0] deinterleave_erase_out,
output deinterleave_erase_out_strobe,
output conv_decoder_out,
output conv_decoder_out_stb,
output descramble_out,
output descramble_out_strobe,
output [7:0] byte_out,
output byte_out_strobe
);
reg conv_in_stb, conv_in_stb_dly, do_descramble_dly;
reg [2:0] conv_in0, conv_in0_dly;
reg [2:0] conv_in1, conv_in1_dly;
reg [1:0] conv_erase, conv_erase_dly;
wire [15:0] input_i = sample_in[31:16];
wire [15:0] input_q = sample_in[15:0];
// wire vit_ce = reset | (enable & conv_in_stb) | conv_in_stb_dly; //Seems new viter decoder IP core does not need this complicated CE signal
wire vit_ce = 1'b1 ; //Need to be 1 to avoid the viterbi decoder freezing issue on adrv9364z7020 (demod_is_ongoing always high. dot11 stuck at state 3)
wire vit_clr = reset;
reg vit_clr_dly;
wire vit_rdy;
wire [5:0] deinterleave_out;
wire deinterleave_out_strobe;
wire [1:0] erase;
// assign conv_decoder_out_stb = vit_ce & vit_rdy;
assign conv_decoder_out_stb = m_axis_data_tvalid; // vit_rdy was used as data valid in the old version of the core, which is no longer the case
reg [3:0] skip_bit;
reg bit_in;
reg bit_in_stb;
reg [19:0] deinter_out_count; // bitwidth same as num_bits_to_decode
//reg flush;
assign deinterleave_erase_out = {erase,deinterleave_out};
assign deinterleave_erase_out_strobe = deinterleave_out_strobe;
demodulate demod_inst (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(rate),
.cons_i(input_i),
.cons_q(input_q),
.input_strobe(sample_in_strobe),
.bits(demod_out),
.soft_bits(demod_soft_bits),
.soft_bits_pos(demod_soft_bits_pos),
.output_strobe(demod_out_strobe)
);
deinterleave deinterleave_inst (
.clock(clock),
.reset(reset),
.enable(enable),
.rate(rate),
.in_bits(demod_out),
.soft_in_bits(demod_soft_bits),
.soft_in_bits_pos(demod_soft_bits_pos),
.input_strobe(demod_out_strobe),
.soft_decoding(soft_decoding),
.out_bits(deinterleave_out),
.output_strobe(deinterleave_out_strobe),
.erase(erase)
);
/*
viterbi_v7_0 viterbi_inst (
.clk(clock),
.ce(vit_ce),
.sclr(vit_clr),
.data_in0(conv_in0),
.data_in1(conv_in1),
.erase(conv_erase),
.rdy(vit_rdy),
.data_out(conv_decoder_out)
);
*/
wire m_axis_data_tvalid ;
//reg [4:0] idle_wire_5bit ;
//wire [6:0] idle_wire_7bit ;
viterbi_v7_0 viterbi_inst (
.aclk(clock), // input wire aclk
.aresetn(~vit_clr), // input wire aresetn
.aclken(vit_ce), // input wire aclken
.s_axis_data_tdata({5'b0,conv_in1_dly,5'b0,conv_in0_dly}), // input wire [15 : 0] s_axis_data_tdata
.s_axis_data_tuser({6'b0,conv_erase_dly}), // input wire [7 : 0] s_axis_data_tuser
.s_axis_data_tvalid(conv_in_stb_dly), // input wire s_axis_data_tvalid
.s_axis_data_tready(vit_rdy), // output wire s_axis_data_tready
.m_axis_data_tdata({idle_wire_7bit, conv_decoder_out}), // output wire [7 : 0] m_axis_data_tdata
.m_axis_data_tvalid(m_axis_data_tvalid) // output wire m_axis_data_tvalid
);
descramble decramble_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.in_bit(conv_decoder_out),
.input_strobe(conv_decoder_out_stb),
.out_bit(descramble_out),
.output_strobe(descramble_out_strobe)
);
bits_to_bytes byte_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.bit_in(bit_in),
.input_strobe(bit_in_stb),
.byte_out(byte_out),
.output_strobe(byte_out_strobe)
);
always @(posedge clock) begin
if (reset) begin
conv_in_stb <= 0;
conv_in0 <= 0;
conv_in1 <= 0;
conv_erase <= 0;
bit_in <= 0;
// skip the first 9 bits of descramble out (service bits)
skip_bit <= 9;
bit_in_stb <= 0;
//flush <= 0;
deinter_out_count <= 0;
end else if (enable) begin
if (deinterleave_out_strobe) begin
deinter_out_count <= deinter_out_count + 1;
end //else begin
// wait for finishing deinterleaving current symbol
// only do flush for non-DATA bits, such as SIG and HT-SIG, which
// are not scrambled
//if (~do_descramble && deinter_out_count >= num_bits_to_decode) begin
//if (deinter_out_count >= num_bits_to_decode) begin // careful! deinter_out_count is only correct from 6M ~ 48M! under 54M, it should be 2*216, but actual value is 288!
//flush <= 1;
//end
//end
//if (!flush) begin
if (!(deinter_out_count >= num_bits_to_decode)) begin
conv_in_stb <= deinterleave_out_strobe;
conv_in0 <= deinterleave_out[2:0];
conv_in1 <= deinterleave_out[5:3];
conv_erase <= erase;
end else begin
conv_in_stb <= 1;
conv_in0 <= 3'b011;
conv_in1 <= 3'b011;
conv_erase <= 0;
end
if (deinter_out_count > 0) begin
if (~do_descramble_dly) begin
bit_in <= conv_decoder_out;
bit_in_stb <= conv_decoder_out_stb;
end else begin
bit_in <= descramble_out;
if (descramble_out_strobe) begin
if (skip_bit > 0 ) begin
skip_bit <= skip_bit - 1;
bit_in_stb <= 0;
end else begin
bit_in_stb <= 1;
end
end else begin
bit_in_stb <= 0;
end
end
end
end
end
// process used to delay things
// TODO: this is only a temp solution, as tready only rise one clock after ce goes high, delay statically by one clock, in future should take into account tready
always @(posedge clock) begin
conv_in1_dly <= conv_in1;
conv_in0_dly <= conv_in0;
conv_erase_dly <= conv_erase;
conv_in_stb_dly <= conv_in_stb ;
do_descramble_dly <= do_descramble;
end
endmodule |
module delayT
#(
parameter DATA_WIDTH = 32,
parameter DELAY = 1
)
(
input clock,
input reset,
input [DATA_WIDTH-1:0] data_in,
output [DATA_WIDTH-1:0] data_out
);
reg [DATA_WIDTH-1:0] ram[DELAY-1:0];
integer i;
assign data_out = ram[DELAY-1];
always @(posedge clock) begin
if (reset) begin
for (i = 0; i < DELAY; i = i+1) begin
ram[i] <= 0;
end
end else begin
ram[0] <= data_in;
for (i = 1; i < DELAY; i= i+1) begin
ram[i] <= ram[i-1];
end
end
end
endmodule |
module phase
#(
parameter DATA_WIDTH = 32
)
(
input clock,
input reset,
input enable,
input signed [DATA_WIDTH-1:0] in_i,
input signed [DATA_WIDTH-1:0] in_q,
input input_strobe,
// [-pi, pi) scaled up by 512
output reg signed [15:0] phase,
output output_strobe
);
`include "common_params.v"
reg [DATA_WIDTH-1:0] in_i_delay;
reg [DATA_WIDTH-1:0] in_q_delay;
reg [DATA_WIDTH-1:0] abs_i;
reg [DATA_WIDTH-1:0] abs_q;
reg [DATA_WIDTH-1:0] max;
reg [DATA_WIDTH-1:0] min;
wire [DATA_WIDTH-1:0] dividend;
wire [DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0] divisor;
assign dividend = (max > 4194304) ? min : {min[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0], {`ATAN_LUT_LEN_SHIFT{1'b0}}};
assign divisor = (max > 4194304) ? max[DATA_WIDTH-1:`ATAN_LUT_LEN_SHIFT] : max[DATA_WIDTH-`ATAN_LUT_LEN_SHIFT-1:0];
wire div_in_stb;
wire [31:0] quotient;
wire div_out_stb;
wire [`ATAN_LUT_LEN_SHIFT-1:0] atan_addr;
wire [`ATAN_LUT_SCALE_SHIFT-1:0] atan_data;
assign atan_addr = (quotient>511?511:quotient[`ATAN_LUT_LEN_SHIFT-1:0]);
wire signed [`ATAN_LUT_SCALE_SHIFT:0] _phase = {1'b0, atan_data};
reg [2:0] quadrant;
wire [2:0] quadrant_delayed;
// 1 cycle for abs
// 1 cycle for quadrant
delayT #(.DATA_WIDTH(1), .DELAY(2)) div_in_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(div_in_stb)
);
// 1 cycle for atan_lut
// 1 cycle for quadrant_delayed
delayT #(.DATA_WIDTH(1), .DELAY(2)) output_inst (
.clock(clock),
.reset(reset),
.data_in(div_out_stb),
.data_out(output_strobe)
);
divider div_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.dividend(dividend),
.divisor({{(`ATAN_LUT_LEN_SHIFT-8){1'b0}}, divisor}),
.input_strobe(div_in_stb),
.quotient(quotient),
.output_strobe(div_out_stb)
);
delayT #(.DATA_WIDTH(3), .DELAY(37)) quadrant_inst (
.clock(clock),
.reset(reset),
.data_in(quadrant),
.data_out(quadrant_delayed)
);
atan_lut lut_inst (
.clka(clock),
.addra(atan_addr),
.douta(atan_data)
);
always @(posedge clock) begin
if (reset) begin
max <= 0;
min <= 0;
abs_i <= 0;
abs_q <= 0;
in_i_delay <= 0;
in_q_delay <= 0;
end else if (enable) begin
// 1st cycle
abs_i <= in_i[DATA_WIDTH-1]? ~in_i+1: in_i;
abs_q <= in_q[DATA_WIDTH-1]? ~in_q+1: in_q;
in_i_delay <= in_i;
in_q_delay <= in_q;
// 2nd cycle
if (abs_i >= abs_q) begin
quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b0};
max <= abs_i;
min <= abs_q;
end else begin
quadrant <= {in_i_delay[DATA_WIDTH-1], in_q_delay[DATA_WIDTH-1], 1'b1};
max <= abs_q;
min <= abs_i;
end
case(quadrant_delayed)
3'b000: phase <= _phase; // [0, PI/4]
3'b001: phase <= PI_2 - _phase; // [PI/4, PI/2]
3'b010: phase <= -_phase; // [-PI/4, 0]
3'b011: phase <= _phase - PI_2; // [-PI/2, -Pi/4]
3'b100: phase <= PI - _phase; // [3/4PI, PI]
3'b101: phase <= PI_2 + _phase; // [PI/2, 3/4PI]
3'b110: phase <= _phase - PI; // [-3/4PI, -PI]
3'b111: phase <= -PI_2 - _phase; // [-PI/2, -3/4PI]
endcase
end
end
endmodule |
module running_sum_dual_ch
#(
parameter DATA_WIDTH0 = 16,
parameter DATA_WIDTH1 = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH0-1:0] data_in0,
input signed [DATA_WIDTH1-1:0] data_in1,
input data_in_valid,
output reg signed [(DATA_WIDTH0 + LOG2_SUM_LEN-1):0] running_sum_result0,
output reg signed [(DATA_WIDTH1 + LOG2_SUM_LEN-1):0] running_sum_result1,
output reg data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH0 = DATA_WIDTH0 + LOG2_SUM_LEN;
localparam TOTAL_WIDTH1 = DATA_WIDTH1 + LOG2_SUM_LEN;
wire signed [DATA_WIDTH0-1:0] data_in_old0;
wire signed [DATA_WIDTH1-1:0] data_in_old1;
wire signed [TOTAL_WIDTH0-1:0] ext_data_in_old0 = {{LOG2_SUM_LEN{data_in_old0[DATA_WIDTH0-1]}}, data_in_old0};
wire signed [TOTAL_WIDTH0-1:0] ext_data_in0 = {{LOG2_SUM_LEN{data_in0[DATA_WIDTH0-1]}}, data_in0 };
wire signed [TOTAL_WIDTH1-1:0] ext_data_in_old1 = {{LOG2_SUM_LEN{data_in_old1[DATA_WIDTH1-1]}}, data_in_old1};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in1 = {{LOG2_SUM_LEN{data_in1[DATA_WIDTH1-1]}}, data_in1 };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
) fifo_1clk_for_running_sum_dual_ch_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout({data_in_old1, data_in_old0}),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din({data_in1, data_in0}),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result0 <= 0;
running_sum_result1 <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result0 <= running_sum_result0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0);
running_sum_result1 <= running_sum_result1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0);
end
end
end
endmodule |
module divider (
input clock,
input reset,
input enable,
input signed [31:0] dividend,
input signed [23:0] divisor,
input input_strobe,
output signed [31:0] quotient,
output output_strobe
);
div_gen div_inst (
.clk(clock),
.dividend(dividend),
.divisor(divisor),
.input_strobe(input_strobe),
.output_strobe(output_strobe),
.quotient(quotient)
);
// // --------old one---------------
// div_gen_v3_0 div_inst (
// .clk(clock),
// .dividend(dividend),
// .divisor(divisor),
// .quotient(quotient)
// );
// delayT #(.DATA_WIDTH(1), .DELAY(36)) out_inst (
// .clock(clock),
// .reset(reset),
// .data_in(input_strobe),
// .data_out(output_strobe)
// );
endmodule |
module rand_gen_tb;
reg clock;
reg reset;
reg enable;
wire [7:0] rnd;
integer fd;
rand_gen inst (
.clock(clock),
.enable(enable),
.reset(reset),
.rnd(rnd)
);
initial begin
clock = 0;
reset = 1;
enable = 0;
fd = $fopen("./sim_out/rand_gen.txt", "w");
# 10 reset = 0;
enable = 1;
# 10000000 $finish;
end
always begin
#1 clock <= ~clock;
end
always @(posedge clock) begin
if (enable) begin
$fwrite(fd, "%d\n", rnd);
end
end
endmodule |
module openofdm_rx_s_axi #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 7
)
(
// Users to add ports here
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG0,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG1,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG2,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG3,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG4,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG5,/*
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG6,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG7,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG8,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG9,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG10,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG11,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG12,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG13,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG14,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG15,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG16,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG17,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG18,
output wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG19,*/
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG20,/*
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG21,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG22,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG23,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG24,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG25,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG26,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG27,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG28,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG29,
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG30,*/
input wire [C_S_AXI_DATA_WIDTH-1:0] SLV_REG31,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 4;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 32
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg4;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg5;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg6;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg7;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg8;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg9;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg10;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg11;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg12;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg13;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg14;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg15;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg16;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg17;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg18;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg19;*/
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg20;/*
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg21;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg22;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg23;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg24;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg25;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg26;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg27;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg28;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg29;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg30;*/
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg31;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
assign SLV_REG0 = slv_reg0;
assign SLV_REG1 = slv_reg1;
assign SLV_REG2 = slv_reg2;
assign SLV_REG3 = slv_reg3;
assign SLV_REG4 = slv_reg4;
assign SLV_REG5 = slv_reg5; /*
assign SLV_REG6 = slv_reg6;
assign SLV_REG7 = slv_reg7;
assign SLV_REG8 = slv_reg8;
assign SLV_REG9 = slv_reg9;
assign SLV_REG10 = slv_reg10;
assign SLV_REG11 = slv_reg11;
assign SLV_REG12 = slv_reg12;
assign SLV_REG13 = slv_reg13;
assign SLV_REG14 = slv_reg14;
assign SLV_REG15 = slv_reg15;
assign SLV_REG16 = slv_reg16;
assign SLV_REG17 = slv_reg17;
assign SLV_REG18 = slv_reg18;
assign SLV_REG19 = slv_reg19;*/
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 32'h0;
slv_reg1 <= 32'h0;
slv_reg2 <= 32'h0;
slv_reg3 <= 32'h0;
slv_reg4 <= 32'h0;
slv_reg5 <= 32'h0; /*
slv_reg6 <= 32'h0;
slv_reg7 <= 32'h0;
slv_reg8 <= 32'h0;
slv_reg9 <= 32'h0;
slv_reg10 <= 32'h0;
slv_reg11 <= 32'h0;
slv_reg12 <= 32'h0;
slv_reg13 <= 32'h0;
slv_reg14 <= 32'h0;
slv_reg15 <= 32'h0;
slv_reg16 <= 32'h0;
slv_reg17 <= 32'h0;
slv_reg18 <= 32'h0;
slv_reg19 <= 32'h0;*/
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h01:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h02:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h03:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h04:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 4
slv_reg4[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h05:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 5
slv_reg5[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end /*
5'h06:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 6
slv_reg6[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h07:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 7
slv_reg7[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h08:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 8
slv_reg8[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h09:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 9
slv_reg9[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 10
slv_reg10[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 11
slv_reg11[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 12
slv_reg12[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 13
slv_reg13[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 14
slv_reg14[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h0F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 15
slv_reg15[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h10:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 16
slv_reg16[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h11:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 17
slv_reg17[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h12:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 18
slv_reg18[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h13:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 19
slv_reg19[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h14:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 20
//slv_reg20[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h15:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 21
//slv_reg21[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h16:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 22
//slv_reg22[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h17:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 23
//slv_reg23[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h18:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 24
//slv_reg24[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h19:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 25
//slv_reg25[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1A:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 26
//slv_reg26[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1B:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 27
//slv_reg27[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1C:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 28
//slv_reg28[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1D:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 29
//slv_reg29[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1E:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 30
//slv_reg30[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
5'h1F:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 31
//slv_reg31[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end */
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
slv_reg4 <= slv_reg4;
slv_reg5 <= slv_reg5; /*
slv_reg6 <= slv_reg6;
slv_reg7 <= slv_reg7;
slv_reg8 <= slv_reg8;
slv_reg9 <= slv_reg9;
slv_reg10 <= slv_reg10;
slv_reg11 <= slv_reg11;
slv_reg12 <= slv_reg12;
slv_reg13 <= slv_reg13;
slv_reg14 <= slv_reg14;
slv_reg15 <= slv_reg15;
slv_reg16 <= slv_reg16;
slv_reg17 <= slv_reg17;
slv_reg18 <= slv_reg18;
slv_reg19 <= slv_reg19;*/
//slv_reg20 <= slv_reg20;
//slv_reg21 <= slv_reg21;
//slv_reg22 <= slv_reg22;
//slv_reg23 <= slv_reg23;
//slv_reg24 <= slv_reg24;
//slv_reg25 <= slv_reg25;
//slv_reg26 <= slv_reg26;
//slv_reg27 <= slv_reg27;
//slv_reg28 <= slv_reg28;
//slv_reg29 <= slv_reg29;
//slv_reg30 <= slv_reg30;
//slv_reg31 <= slv_reg31;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
5'h00 : reg_data_out <= slv_reg0;
5'h01 : reg_data_out <= slv_reg1;
5'h02 : reg_data_out <= slv_reg2;
5'h03 : reg_data_out <= slv_reg3;
5'h04 : reg_data_out <= slv_reg4;
5'h05 : reg_data_out <= slv_reg5; /*
5'h06 : reg_data_out <= slv_reg6;
5'h07 : reg_data_out <= slv_reg7;
5'h08 : reg_data_out <= slv_reg8;
5'h09 : reg_data_out <= slv_reg9;
5'h0A : reg_data_out <= slv_reg10;
5'h0B : reg_data_out <= slv_reg11;
5'h0C : reg_data_out <= slv_reg12;
5'h0D : reg_data_out <= slv_reg13;
5'h0E : reg_data_out <= slv_reg14;
5'h0F : reg_data_out <= slv_reg15;
5'h10 : reg_data_out <= slv_reg16;
5'h11 : reg_data_out <= slv_reg17;
5'h12 : reg_data_out <= slv_reg18;
5'h13 : reg_data_out <= slv_reg19;*/
5'h14 : reg_data_out <= slv_reg20;/*
5'h15 : reg_data_out <= slv_reg21;
5'h16 : reg_data_out <= slv_reg22;
5'h17 : reg_data_out <= slv_reg23;
5'h18 : reg_data_out <= slv_reg24;
5'h19 : reg_data_out <= slv_reg25;
5'h1A : reg_data_out <= slv_reg26;
5'h1B : reg_data_out <= slv_reg27;
5'h1C : reg_data_out <= slv_reg28;
5'h1D : reg_data_out <= slv_reg29;
5'h1E : reg_data_out <= slv_reg30;*/
5'h1F : reg_data_out <= slv_reg31;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg20 <= 32'h0;/*
slv_reg21 <= 32'h0;
slv_reg22 <= 32'h0;
slv_reg23 <= 32'h0;
slv_reg24 <= 32'h0;
slv_reg25 <= 32'h0;
slv_reg26 <= 32'h0;
slv_reg27 <= 32'h0;
slv_reg28 <= 32'h0;
slv_reg29 <= 32'h0;
slv_reg30 <= 32'h0;*/
slv_reg31 <= 32'h0;
end
else
begin
slv_reg20 <= SLV_REG20;/*
slv_reg21 <= SLV_REG21;
slv_reg22 <= SLV_REG22;
slv_reg23 <= SLV_REG23;
slv_reg24 <= SLV_REG24;
slv_reg25 <= SLV_REG25;
slv_reg26 <= SLV_REG26;
slv_reg27 <= SLV_REG27;
slv_reg28 <= SLV_REG28;
slv_reg29 <= SLV_REG29;
slv_reg30 <= SLV_REG30;*/
slv_reg31 <= SLV_REG31;
end
end
// User logic ends
endmodule |
module power_trigger
(
input clock,
input enable,
input reset,
input set_stb,
input [7:0] set_addr,
input [31:0] set_data,
input [31:0] sample_in,
input sample_in_strobe,
output reg trigger
);
`include "common_params.v"
localparam S_SKIP = 0;
localparam S_IDLE = 1;
localparam S_PACKET = 2;
reg [1:0] state;
wire [15:0] power_thres;
wire [15:0] window_size;
wire [31:0] num_sample_to_skip;
wire num_sample_changed;
reg [31:0] sample_count;
wire [15:0] input_i = sample_in[31:16];
reg [15:0] abs_i;
// threshold to claim a power trigger.
setting_reg #(.my_addr(SR_POWER_THRES), .width(16), .at_reset(100)) sr_0 (
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(power_thres), .changed());
// power trigger window
setting_reg #(.my_addr(SR_POWER_WINDOW), .width(16), .at_reset(80)) sr_1 (
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(window_size), .changed());
// num samples to skip initially
setting_reg #(.my_addr(SR_SKIP_SAMPLE), .width(32), .at_reset(5000000)) sr_2 (
.clk(clock), .rst(reset), .strobe(set_stb), .addr(set_addr), .in(set_data),
.out(num_sample_to_skip), .changed(num_sample_changed));
always @(posedge clock) begin
if (reset) begin
sample_count <= 0;
trigger <= 0;
abs_i <= 0;
state <= S_SKIP;
end else if (enable & sample_in_strobe) begin
abs_i <= input_i[15]? ~input_i+1: input_i;
case(state)
S_SKIP: begin
if(sample_count > num_sample_to_skip) begin
state <= S_IDLE;
end else begin
sample_count <= sample_count + 1;
end
end
S_IDLE: begin
if (num_sample_changed) begin
sample_count <= 0;
state <= S_SKIP;
end else if (abs_i > power_thres) begin
// trigger on any significant signal
trigger <= 1;
sample_count <= 0;
state <= S_PACKET;
end
end
S_PACKET: begin
if (num_sample_changed) begin
sample_count <= 0;
state <= S_SKIP;
end else if (abs_i < power_thres) begin
// go back to idle for N consecutive low signals
if (sample_count > window_size) begin
trigger <= 0;
state <= S_IDLE;
end else begin
sample_count <= sample_count + 1;
end
end else begin
sample_count <= 0;
end
end
endcase
end
end
endmodule |
module stage_mult
(
input clock,
input enable,
input reset,
input signed [31:0] X0,
input signed [31:0] X1,
input signed [31:0] X2,
input signed [31:0] X3,
input signed [31:0] X4,
input signed [31:0] X5,
input signed [31:0] X6,
input signed [31:0] X7,
input signed [31:0] Y0,
input signed [31:0] Y1,
input signed [31:0] Y2,
input signed [31:0] Y3,
input signed [31:0] Y4,
input signed [31:0] Y5,
input signed [31:0] Y6,
input signed [31:0] Y7,
input input_strobe,
output reg [63:0] sum,
output output_strobe
);
wire signed [15:0] X0_q = X0[31:16];
wire signed [15:0] X0_i = X0[15:0];
wire signed [15:0] X1_q = X1[31:16];
wire signed [15:0] X1_i = X1[15:0];
wire signed [15:0] X2_q = X2[31:16];
wire signed [15:0] X2_i = X2[15:0];
wire signed [15:0] X3_q = X3[31:16];
wire signed [15:0] X3_i = X3[15:0];
wire signed [15:0] X4_q = X4[31:16];
wire signed [15:0] X4_i = X4[15:0];
wire signed [15:0] X5_q = X5[31:16];
wire signed [15:0] X5_i = X5[15:0];
wire signed [15:0] X6_q = X6[31:16];
wire signed [15:0] X6_i = X6[15:0];
wire signed [15:0] X7_q = X7[31:16];
wire signed [15:0] X7_i = X7[15:0];
wire signed [15:0] Y0_q = Y0[31:16];
wire signed [15:0] Y0_i = Y0[15:0];
wire signed [15:0] Y1_q = Y1[31:16];
wire signed [15:0] Y1_i = Y1[15:0];
wire signed [15:0] Y2_q = Y2[31:16];
wire signed [15:0] Y2_i = Y2[15:0];
wire signed [15:0] Y3_q = Y3[31:16];
wire signed [15:0] Y3_i = Y3[15:0];
wire signed [15:0] Y4_q = Y4[31:16];
wire signed [15:0] Y4_i = Y4[15:0];
wire signed [15:0] Y5_q = Y5[31:16];
wire signed [15:0] Y5_i = Y5[15:0];
wire signed [15:0] Y6_q = Y6[31:16];
wire signed [15:0] Y6_i = Y6[15:0];
wire signed [15:0] Y7_q = Y7[31:16];
wire signed [15:0] Y7_i = Y7[15:0];
wire signed [31:0] prod_0_i;
wire signed [31:0] prod_0_q;
wire signed [31:0] prod_1_i;
wire signed [31:0] prod_1_q;
wire signed [31:0] prod_2_i;
wire signed [31:0] prod_2_q;
wire signed [31:0] prod_3_i;
wire signed [31:0] prod_3_q;
wire signed [31:0] prod_4_i;
wire signed [31:0] prod_4_q;
wire signed [31:0] prod_5_i;
wire signed [31:0] prod_5_q;
wire signed [31:0] prod_6_i;
wire signed [31:0] prod_6_q;
wire signed [31:0] prod_7_i;
wire signed [31:0] prod_7_q;
complex_multiplier mult_inst1 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X0_i,X0_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y0_i,Y0_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_0_q,prod_0_i})
);
complex_multiplier mult_inst2 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X1_i,X1_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y1_i,Y1_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_1_q,prod_1_i})
);
complex_multiplier mult_inst3 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X2_i,X2_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y2_i,Y2_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_2_q,prod_2_i})
);
complex_multiplier mult_inst4 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X3_i,X3_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y3_i,Y3_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_3_q,prod_3_i})
);
complex_multiplier mult_inst5 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X4_i,X4_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y4_i,Y4_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_4_q,prod_4_i})
);
complex_multiplier mult_inst6 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X5_i,X5_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y5_i,Y5_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_5_q,prod_5_i})
);
complex_multiplier mult_inst7 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X6_i,X6_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y6_i,Y6_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_6_q,prod_6_i})
);
complex_multiplier mult_inst8 (
.aclk(clock),
.s_axis_a_tvalid(input_strobe),
.s_axis_a_tdata({X7_i,X7_q}),
.s_axis_b_tvalid(input_strobe),
.s_axis_b_tdata({Y7_i,Y7_q}),
.m_axis_dout_tvalid(),
.m_axis_dout_tdata({prod_7_q,prod_7_i})
);
reg signed [31:0] sum_i1;
reg signed [31:0] sum_i2;
reg signed [31:0] sum_i3;
reg signed [31:0] sum_i4;
reg signed [31:0] sum_q1;
reg signed [31:0] sum_q2;
reg signed [31:0] sum_q3;
reg signed [31:0] sum_q4;
delayT #(.DATA_WIDTH(1), .DELAY(5)) sum_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(output_strobe)
);
always @(posedge clock) begin
if (reset) begin
sum <= 0;
sum_i1 <= 0;
sum_i2 <= 0;
sum_i3 <= 0;
sum_i4 <= 0;
sum_q1 <= 0;
sum_q2 <= 0;
sum_q3 <= 0;
sum_q4 <= 0;
end else if (enable) begin
sum_i1 <= prod_0_i + prod_1_i;
sum_i2 <= prod_2_i + prod_3_i;
sum_i3 <= prod_4_i + prod_5_i;
sum_i4 <= prod_6_i + prod_7_i;
sum_q1 <= prod_0_q + prod_1_q;
sum_q2 <= prod_2_q + prod_3_q;
sum_q3 <= prod_4_q + prod_5_q;
sum_q4 <= prod_6_q + prod_7_q;
sum[63:32] <= sum_i1 + sum_i2 + sum_i3 + sum_i4;
sum[31:0] <= sum_q1 + sum_q2 + sum_q3 + sum_q4;
end
end
endmodule |
module viterbi
(
input clock,
input enable,
input reset,
input [2:0] sym0,
input [2:0] sym1,
input [1:0] erase,
input input_strobe,
output out_bit,
output output_strobe
);
viterbi_v7_0 viterbi_inst (
.clk(clock),
.ce(reset | (enable & input_strobe)),
.sclr(reset),
.data_in0(sym0),
.data_in1(sym1),
.erase(erase),
.rdy(output_strobe),
.data_out(out_bit)
);
endmodule |
module bits_to_bytes
(
input clock,
input enable,
input reset,
input bit_in,
input input_strobe,
output reg [7:0] byte_out,
output reg output_strobe
);
reg [7:0] bit_buf;
reg [2:0] addr;
always @(posedge clock) begin
if (reset) begin
addr <= 0;
bit_buf <= 0;
byte_out <= 0;
output_strobe <= 0;
end else if (enable & input_strobe) begin
bit_buf[7] <= bit_in;
bit_buf[6:0] <= bit_buf[7:1];
addr <= addr + 1;
if (addr == 7) begin
byte_out <= {bit_in, bit_buf[7:1]};
output_strobe <= 1;
end else begin
output_strobe <= 0;
end
end else begin
output_strobe <= 0;
end
end
endmodule |
module complex_mult
(
input clock,
input enable,
input reset,
input [15:0] a_i,
input [15:0] a_q,
input [15:0] b_i,
input [15:0] b_q,
input input_strobe,
output [31:0] p_i,
output [31:0] p_q,
output output_strobe
);
wire [63:0] m_axis_dout_tdata;
assign p_q = m_axis_dout_tdata[63:32];
assign p_i = m_axis_dout_tdata[31:0];
complex_multiplier mult_inst (
.aclk(clock), // input wire aclk
.s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
.s_axis_a_tdata({a_q, a_i}), // input wire [31 : 0] s_axis_a_tdata
.s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
.s_axis_b_tdata({b_q, b_i}), // input wire [31 : 0] s_axis_b_tdata
.m_axis_dout_tvalid(output_strobe), // output wire m_axis_dout_tvalid
.m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
);
// reg [15:0] ar;
// reg [15:0] ai;
// reg [15:0] br;
// reg [15:0] bi;
// wire [31:0] prod_i;
// wire [31:0] prod_q;
// // instantiation of complex multiplier
// wire [31:0] s_axis_a_tdata;
// assign s_axis_a_tdata = {ai,ar} ;
// wire [31:0] s_axis_b_tdata;
// assign s_axis_b_tdata = {bi, br} ;
// wire [63:0] m_axis_dout_tdata;
// assign prod_q = m_axis_dout_tdata[63:32];
// assign prod_i = m_axis_dout_tdata[31:0];
// wire m_axis_dout_tvalid ;
// assign output_strobe = m_axis_dout_tvalid; //output strobe valid at the beginning of new data -- simulation confirmed
// complex_multiplier mult_inst (
// .aclk(clock), // input wire aclk
// .s_axis_a_tvalid(input_strobe), // input wire s_axis_a_tvalid
// .s_axis_a_tdata(s_axis_a_tdata), // input wire [31 : 0] s_axis_a_tdata
// .s_axis_b_tvalid(input_strobe), // input wire s_axis_b_tvalid
// .s_axis_b_tdata(s_axis_b_tdata), // input wire [31 : 0] s_axis_b_tdata
// .m_axis_dout_tvalid(m_axis_dout_tvalid), // output wire m_axis_dout_tvalid
// .m_axis_dout_tdata(m_axis_dout_tdata) // output wire [63 : 0] m_axis_dout_tdata
// );
// always @(posedge clock) begin
// if (reset) begin
// ar <= 0;
// ai <= 0;
// br <= 0;
// bi <= 0;
// p_i <= 0;
// p_q <= 0;
// end else if (enable) begin
// ar <= a_i;
// ai <= a_q;
// br <= b_i;
// bi <= b_q;
// p_i <= prod_i;
// p_q <= prod_q;
// end
// end
endmodule |
module rotate
(
input clock,
input enable,
input reset,
input [15:0] in_i,
input [15:0] in_q,
// [-PI, PI]
// scaled up by ATAN_LUT_SCALE_SHIFT
input signed [15:0] phase,
input input_strobe,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
output signed [15:0] out_i,
output signed [15:0] out_q,
output output_strobe
);
`include "common_params.v"
reg [15:0] phase_delayed;
reg [15:0] phase_abs;
reg [2:0] quadrant;
reg [2:0] quadrant_delayed;
wire [15:0] in_i_delayed;
wire [15:0] in_q_delayed;
reg [15:0] actual_phase;
wire [15:0] raw_rot_i;
wire [15:0] raw_rot_q;
reg [15:0] rot_i;
reg [15:0] rot_q;
wire mult_in_stb;
wire [31:0] p_i;
wire [31:0] p_q;
assign out_i = p_i[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign out_q = p_q[`ROTATE_LUT_SCALE_SHIFT+15:`ROTATE_LUT_SCALE_SHIFT];
assign rot_addr = actual_phase[`ROTATE_LUT_LEN_SHIFT-1:0];
assign raw_rot_i = rot_data[31:16];
assign raw_rot_q = rot_data[15:0];
delayT #(.DATA_WIDTH(32), .DELAY(4)) in_delay_inst (
.clock(clock),
.reset(reset),
.data_in({in_i, in_q}),
.data_out({in_i_delayed, in_q_delayed})
);
delayT #(.DATA_WIDTH(1), .DELAY(4)) mult_delay_inst (
.clock(clock),
.reset(reset),
.data_in(input_strobe),
.data_out(mult_in_stb)
);
complex_mult mult_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.a_i(in_i_delayed),
.a_q(in_q_delayed),
.b_i(rot_i),
.b_q(rot_q),
.input_strobe(mult_in_stb),
.p_i(p_i),
.p_q(p_q),
.output_strobe(output_strobe)
);
integer i;
always @(posedge clock) begin
if (reset) begin
actual_phase <= 0;
rot_i <= 0;
rot_q <= 0;
phase_abs <= 0;
phase_delayed <= 0;
end else if (enable) begin
`ifdef DEBUG_PRINT
if (phase > PI || phase < -PI) begin
$display("[WARN] phase overflow: %d\n", phase);
end
`endif
// cycle 1
phase_abs <= phase[15]? ~phase+1: phase;
phase_delayed <= phase;
// cycle 2
if (phase_abs <= PI_4) begin
quadrant <= {phase_delayed[15], 2'b00};
actual_phase <= phase_abs;
end else if (phase_abs <= PI_2) begin
quadrant <= {phase_delayed[15], 2'b01};
actual_phase <= PI_2 - phase_abs;
end else if (phase_abs <= PI_3_4) begin
quadrant <= {phase_delayed[15], 2'b10};
actual_phase <= phase_abs - PI_2;
end else begin
quadrant <= {phase_delayed[15], 2'b11};
actual_phase <= PI - phase_abs;
end
// cycle 3
// wait for raw_rot_i
quadrant_delayed <= quadrant;
// cycle 4
case(quadrant_delayed)
3'b000: begin
rot_i <= raw_rot_i;
rot_q <= raw_rot_q;
end
3'b001: begin
rot_i <= raw_rot_q;
rot_q <= raw_rot_i;
end
3'b010: begin
rot_i <= ~raw_rot_q+1;
rot_q <= raw_rot_i;
end
3'b011: begin
rot_i <= ~raw_rot_i+1;
rot_q <= raw_rot_q;
end
3'b100: begin
rot_i <= raw_rot_i;
rot_q <= ~raw_rot_q+1;
end
3'b101: begin
rot_i <= raw_rot_q;
rot_q <= ~raw_rot_i+1;
end
3'b110: begin
rot_i <= ~raw_rot_q+1;
rot_q <= ~raw_rot_i+1;
end
3'b111: begin
rot_i <= ~raw_rot_i+1;
rot_q <= ~raw_rot_q+1;
end
endcase
end
end
endmodule |
module sync_long (
input clock,
input reset,
input enable,
input [31:0] sample_in,
input sample_in_strobe,
input signed [15:0] phase_offset,
input short_gi,
input [3:0] fft_win_shift,
output [`ROTATE_LUT_LEN_SHIFT-1:0] rot_addr,
input [31:0] rot_data,
output [31:0] metric,
output metric_stb,
output reg long_preamble_detected,
output reg [31:0] sample_out,
output reg sample_out_strobe,
output reg [15:0] num_ofdm_symbol,
output reg signed [31:0] phase_offset_taken,
output reg [1:0] state
);
`include "common_params.v"
localparam IN_BUF_LEN_SHIFT = 8;
localparam NUM_STS_TAIL = 32;
reg [15:0] in_offset;
reg [IN_BUF_LEN_SHIFT-1:0] in_waddr;
reg [IN_BUF_LEN_SHIFT-1:0] in_raddr;
wire [IN_BUF_LEN_SHIFT-1:0] gi_skip = short_gi? 9: 17;
reg signed [31:0] num_input_produced;
reg signed [31:0] num_input_consumed;
reg signed [31:0] num_input_avail;
reg [2:0] mult_stage;
reg [1:0] sum_stage;
reg mult_strobe;
wire signed [31:0] stage_sum_i;
wire signed [31:0] stage_sum_q;
wire stage_sum_stb;
reg signed [31:0] sum_i;
reg signed [31:0] sum_q;
reg sum_stb;
reg signed [31:0] phase_correction;
reg signed [31:0] next_phase_correction;
reg reset_delay ; // add reset signal for fft, somehow all kinds of event flag raises when feeding real rf signal, maybe reset will help
wire fft_resetn ;
always @(posedge clock) begin
reset_delay = reset ;
end
assign fft_resetn = (~reset) & (~reset_delay); // make sure resetn is at least 2 clock cycles low
complex_to_mag #(.DATA_WIDTH(32)) sum_mag_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.i(sum_i),
.q(sum_q),
.input_strobe(sum_stb),
.mag(metric),
.mag_stb(metric_stb)
);
reg [31:0] metric_max1;
reg [(IN_BUF_LEN_SHIFT-1):0] addr1;
reg [31:0] cross_corr_buf[0:31];
reg [31:0] stage_X0;
reg [31:0] stage_X1;
reg [31:0] stage_X2;
reg [31:0] stage_X3;
reg [31:0] stage_X4;
reg [31:0] stage_X5;
reg [31:0] stage_X6;
reg [31:0] stage_X7;
reg [31:0] stage_Y0;
reg [31:0] stage_Y1;
reg [31:0] stage_Y2;
reg [31:0] stage_Y3;
reg [31:0] stage_Y4;
reg [31:0] stage_Y5;
reg [31:0] stage_Y6;
reg [31:0] stage_Y7;
stage_mult stage_mult_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.X0(stage_X0),
.X1(stage_X1),
.X2(stage_X2),
.X3(stage_X3),
.X4(stage_X4),
.X5(stage_X5),
.X6(stage_X6),
.X7(stage_X7),
.Y0(stage_Y0),
.Y1(stage_Y1),
.Y2(stage_Y2),
.Y3(stage_Y3),
.Y4(stage_Y4),
.Y5(stage_Y5),
.Y6(stage_Y6),
.Y7(stage_Y7),
.input_strobe(mult_strobe),
.sum({stage_sum_i, stage_sum_q}),
.output_strobe(stage_sum_stb)
);
localparam S_SKIPPING = 0;
localparam S_WAIT_FOR_FIRST_PEAK = 1;
localparam S_IDLE = 2;
localparam S_FFT = 3;
reg fft_start;
//wire fft_start_delayed;
wire fft_in_stb;
reg fft_loading;
wire signed [15:0] fft_in_re;
wire signed [15:0] fft_in_im;
wire [22:0] fft_out_re;
wire [22:0] fft_out_im;
wire fft_ready;
wire fft_done;
wire fft_busy;
wire fft_valid;
wire [31:0] fft_out = {fft_out_re[22:7], fft_out_im[22:7]};
wire signed [15:0] raw_i;
wire signed [15:0] raw_q;
reg raw_stb;
wire idle_line1, idle_line2 ;
reg fft_din_data_tlast ;
wire fft_din_data_tlast_delayed ;
wire event_frame_started;
wire event_tlast_unexpected;
wire event_tlast_missing;
wire event_status_channel_halt;
wire event_data_in_channel_halt;
wire event_data_out_channel_halt;
wire s_axis_config_tready;
wire m_axis_data_tlast;
ram_2port #(.DWIDTH(32), .AWIDTH(IN_BUF_LEN_SHIFT)) in_buf (
.clka(clock),
.ena(1),
.wea(sample_in_strobe),
.addra(in_waddr),
.dia(sample_in),
.doa(),
.clkb(clock),
.enb(fft_start | fft_loading),
.web(1'b0),
.addrb(in_raddr),
.dib(32'hFFFF),
.dob({raw_i, raw_q})
);
rotate rotate_inst (
.clock(clock),
.enable(enable),
.reset(reset),
.in_i(raw_i),
.in_q(raw_q),
.phase(phase_correction),
.input_strobe(raw_stb),
.rot_addr(rot_addr),
.rot_data(rot_data),
.out_i(fft_in_re),
.out_q(fft_in_im),
.output_strobe(fft_in_stb)
);
delayT #(.DATA_WIDTH(1), .DELAY(10)) fft_delay_inst (
.clock(clock),
.reset(reset),
.data_in(fft_din_data_tlast),
.data_out(fft_din_data_tlast_delayed)
);
///the fft7_1 isntance is commented out, as it is upgraded to fft9 version
/*xfft_v7_1 dft_inst (
.clk(clock),
.fwd_inv(1),
.start(fft_start_delayed),
.fwd_inv_we(1),
.xn_re(fft_in_re),
.xn_im(fft_in_im),
.xk_re(fft_out_re),
.xk_im(fft_out_im),
.rfd(fft_ready),
.done(fft_done),
.busy(fft_busy),
.dv(fft_valid)
);*/
xfft_v9 dft_inst (
.aclk(clock), // input wire aclk
.aresetn(fft_resetn),
.s_axis_config_tdata({7'b0, 1'b1}), // input wire [7 : 0] s_axis_config_tdata, use LSB to indicate it is forward transform, the rest should be ignored
.s_axis_config_tvalid(1'b1), // input wire s_axis_config_tvalid
.s_axis_config_tready(s_axis_config_tready), // output wire s_axis_config_tready
.s_axis_data_tdata({fft_in_im, fft_in_re}), // input wire [31 : 0] s_axis_data_tdata
.s_axis_data_tvalid(fft_in_stb), // input wire s_axis_data_tvalid
.s_axis_data_tready(fft_ready), // output wire s_axis_data_tready
.s_axis_data_tlast(fft_din_data_tlast_delayed), // input wire s_axis_data_tlast
.m_axis_data_tdata({idle_line1,fft_out_im, idle_line2, fft_out_re}), // output wire [47 : 0] m_axis_data_tdata
.m_axis_data_tvalid(fft_valid), // output wire m_axis_data_tvalid
.m_axis_data_tready(1'b1), // input wire m_axis_data_tready
.m_axis_data_tlast(m_axis_data_tlast), // output wire m_axis_data_tlast
.event_frame_started(event_frame_started), // output wire event_frame_started
.event_tlast_unexpected(event_tlast_unexpected), // output wire event_tlast_unexpected
.event_tlast_missing(event_tlast_missing), // output wire event_tlast_missing
.event_status_channel_halt(event_status_channel_halt), // output wire event_status_channel_halt
.event_data_in_channel_halt(event_data_in_channel_halt), // output wire event_data_in_channel_halt
.event_data_out_channel_halt(event_data_out_channel_halt) // output wire event_data_out_channel_halt
);
reg [15:0] num_sample;
integer i;
integer j;
always @(posedge clock) begin
if (reset) begin
for (j = 0; j < 32; j= j+1) begin
cross_corr_buf[j] <= 0;
end
do_clear();
state <= S_SKIPPING;
fft_din_data_tlast <= 1'b0;
end else if (enable) begin
if (sample_in_strobe && state != S_SKIPPING) begin
in_waddr <= in_waddr + 1;
num_input_produced <= num_input_produced + 1;
end
num_input_avail <= num_input_produced - num_input_consumed;
case(state)
S_SKIPPING: begin
// skip the tail of short preamble
if (num_sample >= NUM_STS_TAIL) begin
num_sample <= 0;
state <= S_WAIT_FOR_FIRST_PEAK;
end else if (sample_in_strobe) begin
num_sample <= num_sample + 1;
end
end
S_WAIT_FOR_FIRST_PEAK: begin
do_mult();
if (metric_stb && (metric > metric_max1)) begin
metric_max1 <= metric;
addr1 <= in_raddr - 1 -fft_win_shift;
end
if (num_sample >= 88) begin
long_preamble_detected <= 1;
num_sample <= 0;
mult_strobe <= 0;
sum_stb <= 0;
// offset it by the length of cross correlation buffer
// size
in_raddr <= addr1 - 32;
num_input_consumed <= addr1 - 32;
in_offset <= 0;
num_ofdm_symbol <= 0;
phase_correction <= 0;
next_phase_correction <= phase_offset;
phase_offset_taken <= phase_offset;
state <= S_FFT;
end else if (metric_stb) begin
num_sample <= num_sample + 1;
end
end
S_FFT: begin
if (long_preamble_detected) begin
`ifdef DEBUG_PRINT
$display("Long preamble detected");
`endif
long_preamble_detected <= 0;
end
if (~fft_loading && num_input_avail > 88) begin
fft_start <= 1;
in_offset <= 0;
end
if (fft_start) begin
fft_start <= 0;
fft_loading <= 1;
end
raw_stb <= fft_start | fft_loading;
if (raw_stb) begin
if (phase_offset > 0) begin
if (next_phase_correction > PI) begin
phase_correction <= next_phase_correction - DOUBLE_PI;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction - DOUBLE_PI + phase_offset;
end else begin
phase_correction <= next_phase_correction;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + phase_offset;
end
end else begin
if (next_phase_correction < -PI) begin
phase_correction <= next_phase_correction + DOUBLE_PI;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + DOUBLE_PI + phase_offset;
end else begin
phase_correction <= next_phase_correction;
if(in_offset == 63 && num_ofdm_symbol > 0)
next_phase_correction <= next_phase_correction + phase_offset + (short_gi ? phase_offset<<<3 : phase_offset<<<4);
else
next_phase_correction <= next_phase_correction + phase_offset;
end
end
end
if (fft_start | fft_loading) begin
in_offset <= in_offset + 1;
if( in_offset == 62) begin
fft_din_data_tlast <= 1'b1;
end
if (in_offset == 63) begin
fft_din_data_tlast <= 1'b0;
fft_loading <= 0;
num_ofdm_symbol <= num_ofdm_symbol + 1;
if (num_ofdm_symbol > 0) begin
// skip the Guard Interval for data symbols
in_raddr <= in_raddr + gi_skip;
num_input_consumed <= num_input_consumed + gi_skip;
end else begin
in_raddr <= in_raddr + 1;
num_input_consumed <= num_input_consumed + 1;
end
end else begin
in_raddr <= in_raddr + 1;
num_input_consumed <= num_input_consumed + 1;
end
end
sample_out_strobe <= fft_valid;
sample_out <= fft_out;
end
S_IDLE: begin
end
default: begin
state <= S_WAIT_FOR_FIRST_PEAK;
end
endcase
end else begin
sample_out_strobe <= 0;
end
end
integer do_mult_i;
task do_mult; begin
// cross correlation of the first 16 samples of LTS
if (sample_in_strobe) begin
cross_corr_buf[31] <= sample_in;
for (do_mult_i = 0; do_mult_i < 31; do_mult_i = do_mult_i+1) begin
cross_corr_buf[do_mult_i] <= cross_corr_buf[do_mult_i+1];
end
sum_stage <= 0;
sum_i <= 0;
sum_q <= 0;
sum_stb <= 0;
stage_X0 <= cross_corr_buf[1];
stage_X1 <= cross_corr_buf[2];
stage_X2 <= cross_corr_buf[3];
stage_X3 <= cross_corr_buf[4];
stage_X4 <= cross_corr_buf[5];
stage_X5 <= cross_corr_buf[6];
stage_X6 <= cross_corr_buf[7];
stage_X7 <= cross_corr_buf[8];
stage_Y0 <= { 16'd156, 16'd0};
stage_Y1 <= {-16'd5, 16'd120};
stage_Y2 <= { 16'd40, 16'd111};
stage_Y3 <= { 16'd97, -16'd83};
stage_Y4 <= { 16'd21, -16'd28};
stage_Y5 <= { 16'd60, 16'd88};
stage_Y6 <= {-16'd115, 16'd55};
stage_Y7 <= {-16'd38, 16'd106};
mult_strobe <= 1;
mult_stage <= 1;
end
if (mult_stage == 1) begin
stage_X0 <= cross_corr_buf[8];
stage_X1 <= cross_corr_buf[9];
stage_X2 <= cross_corr_buf[10];
stage_X3 <= cross_corr_buf[11];
stage_X4 <= cross_corr_buf[12];
stage_X5 <= cross_corr_buf[13];
stage_X6 <= cross_corr_buf[14];
stage_X7 <= cross_corr_buf[15];
stage_Y0 <= { 16'd98, 16'd26};
stage_Y1 <= { 16'd53, -16'd4};
stage_Y2 <= { 16'd1, 16'd115};
stage_Y3 <= {-16'd137, 16'd47};
stage_Y4 <= { 16'd24, 16'd59};
stage_Y5 <= { 16'd59, 16'd15};
stage_Y6 <= {-16'd22, -16'd161};
stage_Y7 <= { 16'd119, 16'd4};
mult_stage <= 2;
end else if (mult_stage == 2) begin
stage_X0 <= cross_corr_buf[16];
stage_X1 <= cross_corr_buf[17];
stage_X2 <= cross_corr_buf[18];
stage_X3 <= cross_corr_buf[19];
stage_X4 <= cross_corr_buf[20];
stage_X5 <= cross_corr_buf[21];
stage_X6 <= cross_corr_buf[22];
stage_X7 <= cross_corr_buf[23];
stage_Y0 <= { 16'd62, 16'd62};
stage_Y1 <= { 16'd37, -16'd98};
stage_Y2 <= {-16'd57, -16'd39};
stage_Y3 <= {-16'd131, -16'd65};
stage_Y4 <= { 16'd82, -16'd92};
stage_Y5 <= { 16'd70, -16'd14};
stage_Y6 <= {-16'd60, -16'd81};
stage_Y7 <= {-16'd56, 16'd22};
mult_stage <= 3;
end else if (mult_stage == 3) begin
stage_X0 <= cross_corr_buf[24];
stage_X1 <= cross_corr_buf[25];
stage_X2 <= cross_corr_buf[26];
stage_X3 <= cross_corr_buf[27];
stage_X4 <= cross_corr_buf[28];
stage_X5 <= cross_corr_buf[29];
stage_X6 <= cross_corr_buf[30];
stage_X7 <= cross_corr_buf[31];
stage_Y0 <= {-16'd35, 16'd151};
stage_Y1 <= {-16'd122, 16'd17};
stage_Y2 <= {-16'd127, 16'd21};
stage_Y3 <= { 16'd75, 16'd74};
stage_Y4 <= {-16'd3, -16'd54};
stage_Y5 <= {-16'd92, -16'd115};
stage_Y6 <= { 16'd92, -16'd106};
stage_Y7 <= { 16'd12, -16'd98};
mult_stage <= 4;
end else if (mult_stage == 4) begin
mult_stage <= 0;
mult_strobe <= 0;
in_raddr <= in_raddr + 1;
num_input_consumed <= num_input_consumed + 1;
end
if (stage_sum_stb) begin
sum_stage <= sum_stage + 1;
sum_i <= sum_i + stage_sum_i;
sum_q <= sum_q + stage_sum_q;
if (sum_stage == 3) begin
sum_stb <= 1;
end
end else begin
sum_stb <= 0;
sum_i <= 0;
sum_q <= 0;
end
end
endtask
task do_clear; begin
in_waddr <= 0;
in_raddr <= 0;
in_offset <= 0;
num_input_produced <= 0;
num_input_consumed <= 0;
num_input_avail <= 0;
phase_correction <= 0;
next_phase_correction <= 0;
raw_stb <= 0;
sum_i <= 0;
sum_q <= 0;
sum_stb <= 0;
sum_stage <= 0;
mult_strobe <= 0;
metric_max1 <= 0;
addr1 <= 0;
mult_stage <= 0;
long_preamble_detected <= 0;
num_sample <= 0;
num_ofdm_symbol <= 0;
fft_start <= 0;
fft_loading <= 0;
sample_out_strobe <= 0;
sample_out <= 0;
stage_X0 <= 0;
stage_X1 <= 0;
stage_X2 <= 0;
stage_X3 <= 0;
stage_X4 <= 0;
stage_X5 <= 0;
stage_X6 <= 0;
stage_X7 <= 0;
stage_Y0 <= 0;
stage_Y1 <= 0;
stage_Y2 <= 0;
stage_Y3 <= 0;
stage_Y4 <= 0;
stage_Y5 <= 0;
stage_Y6 <= 0;
stage_Y7 <= 0;
end
endtask
endmodule |
module mv_avg
#(
parameter DATA_WIDTH = 16,
parameter LOG2_AVG_LEN = 5
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output wire signed [DATA_WIDTH-1:0] data_out,
output wire data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_AVG_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_AVG_LEN;
reg signed [(TOTAL_WIDTH-1):0] running_total;
reg signed [DATA_WIDTH-1:0] data_in_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_AVG_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_AVG_LEN{data_in_reg[DATA_WIDTH-1]}}, data_in_reg};
reg rd_en, rd_en_start;
wire [LOG2_AVG_LEN:0] wr_data_count;
reg [LOG2_AVG_LEN:0] wr_data_count_reg;
wire wr_complete_pulse;
reg wr_complete_pulse_reg;
assign wr_complete_pulse = (wr_data_count > wr_data_count_reg);
assign data_out_valid = wr_complete_pulse_reg;
assign data_out = running_total[TOTAL_WIDTH-1:LOG2_AVG_LEN];
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16!
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_reg <= 0;
wr_data_count_reg <= 0;
running_total <= 0;
rd_en <= 0;
rd_en_start <= 0;
wr_complete_pulse_reg <= 0;
end else begin
wr_complete_pulse_reg <= wr_complete_pulse;
data_in_reg <= (data_in_valid?data_in:data_in_reg);
wr_data_count_reg <= wr_data_count;
rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start);
rd_en <= (rd_en_start?wr_complete_pulse:rd_en);
if (wr_complete_pulse) begin
running_total <= running_total + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule |
module dot11_side_ch_tb;
`include "common_params.v"
localparam integer TSF_TIMER_WIDTH = 64; // according to 802.11 standard
localparam integer GPIO_STATUS_WIDTH = 8;
localparam integer RSSI_HALF_DB_WIDTH = 11;
localparam integer ADC_PACK_DATA_WIDTH = 64;
localparam integer IQ_DATA_WIDTH = 16;
localparam integer RSSI_DATA_WIDTH = 10;
localparam integer C_S00_AXI_DATA_WIDTH = 32;
localparam integer C_S00_AXI_ADDR_WIDTH = 7;
localparam integer C_S00_AXIS_TDATA_WIDTH = 64;
localparam integer C_M00_AXIS_TDATA_WIDTH = 64;
localparam integer WAIT_COUNT_BITS = 5;
localparam integer MAX_NUM_DMA_SYMBOL = 8192; // the fifo depth inside m_axis
function integer clogb2 (input integer bit_depth);
begin
for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
bit_depth = bit_depth >> 1;
end
endfunction
localparam integer MAX_BIT_NUM_DMA_SYMBOL = clogb2(MAX_NUM_DMA_SYMBOL);
reg clock;
reg reset;
reg enable;
reg [10:0] rssi_half_db;
reg[31:0] sample_in;
reg sample_in_strobe;
reg [15:0] clk_count;
wire [31:0] sync_short_metric;
wire short_preamble_detected;
wire power_trigger;
wire [31:0] sync_long_out;
wire sync_long_out_strobe;
wire [31:0] sync_long_metric;
wire sync_long_metric_stb;
wire long_preamble_detected;
wire [31:0] phase_offset_taken;
wire [31:0] equalizer_out;
wire equalizer_out_strobe;
wire [5:0] demod_out;
wire demod_out_strobe;
wire [7:0] deinterleave_erase_out;
wire deinterleave_erase_out_strobe;
wire conv_decoder_out;
wire conv_decoder_out_stb;
wire descramble_out;
wire descramble_out_strobe;
wire [3:0] legacy_rate;
wire legacy_sig_rsvd;
wire [11:0] legacy_len;
wire legacy_sig_parity;
wire [5:0] legacy_sig_tail;
wire legacy_sig_stb;
reg signal_done;
wire [3:0] dot11_state;
wire pkt_header_valid;
wire pkt_header_valid_strobe;
wire [7:0] byte_out;
wire byte_out_strobe;
wire [15:0] byte_count_total;
wire [15:0] byte_count;
wire [15:0] pkt_len_total;
wire [15:0] pkt_len;
// wire [63:0] word_out;
// wire word_out_strobe;
wire demod_is_ongoing;
wire ofdm_symbol_eq_out_pulse;
wire ht_unsupport;
wire [7:0] pkt_rate;
wire [(32-1):0] csi;
wire csi_valid;
wire [31:0] FC_DI;
wire FC_DI_valid;
wire [47:0] addr1;
wire addr1_valid;
wire [47:0] addr2;
wire addr2_valid;
wire [47:0] addr3;
wire addr3_valid;
wire m_axis_start_1trans;
wire [63:0] data_to_ps;
wire data_to_ps_valid;
wire [(MAX_BIT_NUM_DMA_SYMBOL-1):0] m_axis_data_count;
wire fulln_to_pl;
wire M_AXIS_TVALID;
wire M_AXIS_TLAST;
reg slv_reg_wren_signal;
reg [4:0] axi_awaddr_core;
reg [3:0] num_eq;
// iq capture configuration
reg iq_capture;
reg [3:0] iq_trigger_select;
reg signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_th;
reg [(GPIO_STATUS_WIDTH-2):0] gain_th;
reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] pre_trigger_len;
reg [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] iq_len_target;
reg set_stb;
reg [7:0] set_addr;
reg [31:0] set_data;
wire fcs_out_strobe, fcs_ok;
integer addr;
integer bb_sample_fd;
integer power_trigger_fd;
integer short_preamble_detected_fd;
integer long_preamble_detected_fd;
integer sync_long_metric_fd;
integer sync_long_out_fd;
integer equalizer_out_fd;
integer demod_out_fd;
integer deinterleave_erase_out_fd;
integer conv_out_fd;
integer descramble_out_fd;
integer signal_fd;
integer byte_out_fd;
integer file_i, file_q, file_rssi_half_db, iq_sample_file;
`define SPEED_100M // remove this to use 200M
localparam integer IQ_CAPTURE = 1; //0 -- CSI; 1 -- IQ
localparam integer IQ_TRIGGER_SELECT = 6;
localparam integer PRE_TRIGGER_LEN = 3;
localparam integer IQ_LEN_TARGET = 7;
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_ht_unsupport_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_ht_sig_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_wrong_sig_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_11n_mcs7_gi0_100B_openwifi.txt"
// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_52mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
// `define SAMPLE_FILE "../../../../../testing_inputs/radiated/dot11n_19.5mbps_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_58.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11n_65mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42_openwifi.txt"
// `define SAMPLE_FILE "../../../../../testing_inputs/conducted/dot11a_48mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42_openwifi.txt"
//`define SAMPLE_FILE "../../../../../testing_inputs/radiated/ack-ok-openwifi.txt"
`define SAMPLE_FILE "../../../../../testing_inputs/simulated/iq_mixed_for_side_ch_openwifi.txt"
`define NUM_SAMPLE 18560
//`define SAMPLE_FILE "../../../../../testing_inputs/simulated/openofdm_tx/PL_100Bytes/54Mbps.txt"
//`define NUM_SAMPLE 2048
initial begin
$dumpfile("dot11.vcd");
$dumpvars;
slv_reg_wren_signal = 0;
axi_awaddr_core = 0;
iq_capture = IQ_CAPTURE;
iq_trigger_select = IQ_TRIGGER_SELECT;
rssi_th = 0;
gain_th = 0;
pre_trigger_len = PRE_TRIGGER_LEN;
iq_len_target = IQ_LEN_TARGET;
clock = 0;
reset = 1;
enable = 0;
signal_done <= 0;
# 20 reset = 0;
enable = 1;
set_stb = 1;
# 20
// do not skip sample
set_addr = SR_SKIP_SAMPLE;
set_data = 0;
# 20 set_stb = 0;
end
integer file_open_trigger = 0;
always @(posedge clock) begin
file_open_trigger = file_open_trigger + 1;
if (file_open_trigger==1) begin
iq_sample_file = $fopen(`SAMPLE_FILE, "r");
bb_sample_fd = $fopen("./sample_in.txt", "w");
power_trigger_fd = $fopen("./power_trigger.txt", "w");
short_preamble_detected_fd = $fopen("./short_preamble_detected.txt", "w");
sync_long_metric_fd = $fopen("./sync_long_metric.txt", "w");
long_preamble_detected_fd = $fopen("./sync_long_frame_detected.txt", "w");
sync_long_out_fd = $fopen("./sync_long_out.txt", "w");
equalizer_out_fd = $fopen("./equalizer_out.txt", "w");
demod_out_fd = $fopen("./demod_out.txt", "w");
deinterleave_erase_out_fd = $fopen("./deinterleave_erase_out.txt", "w");
conv_out_fd = $fopen("./conv_out.txt", "w");
descramble_out_fd = $fopen("./descramble_out.txt", "w");
signal_fd = $fopen("./signal_out.txt", "w");
byte_out_fd = $fopen("./byte_out.txt", "w");
end
end
`ifdef SPEED_100M
always begin //100MHz
#5 clock = !clock;
end
`else
always begin //200MHz
#2.5 clock = !clock;
end
`endif
always @(posedge clock) begin
if (reset) begin
sample_in <= 0;
clk_count <= 0;
sample_in_strobe <= 0;
addr <= 0;
num_eq <= 5;
end else if (enable) begin
`ifdef SPEED_100M
if (clk_count == 4) begin // for 100M; 100/20 = 5
`else
if (clk_count == 9) begin // for 200M; 200/20 = 10
`endif
sample_in_strobe <= 1;
//$fscanf(iq_sample_file, "%d %d %d", file_i, file_q, file_rssi_half_db);
$fscanf(iq_sample_file, "%d %d", file_i, file_q);
sample_in[15:0] <= file_q;
sample_in[31:16]<= file_i;
//rssi_half_db <= file_rssi_half_db;
rssi_half_db <= 0;
addr <= addr + 1;
clk_count <= 0;
end else begin
sample_in_strobe <= 0;
clk_count <= clk_count + 1;
end
if (short_preamble_detected) begin
num_eq <= num_eq + 3;
end
if (legacy_sig_stb) begin
end
//if (sample_in_strobe && power_trigger) begin
if (sample_in_strobe) begin
$fwrite(bb_sample_fd, "%d %d %d\n", $time/2, $signed(sample_in[31:16]), $signed(sample_in[15:0]));
$fwrite(power_trigger_fd, "%d %d\n", $time/2, power_trigger);
$fwrite(short_preamble_detected_fd, "%d %d\n", $time/2, short_preamble_detected);
$fwrite(long_preamble_detected_fd, "%d %d\n", $time/2, long_preamble_detected);
$fflush(bb_sample_fd);
$fflush(power_trigger_fd);
$fflush(short_preamble_detected_fd);
$fflush(long_preamble_detected_fd);
if ((addr % 100) == 0) begin
$display("%d", addr);
end
if (addr == `NUM_SAMPLE) begin
$fclose(iq_sample_file);
$fclose(bb_sample_fd);
$fclose(power_trigger_fd);
$fclose(short_preamble_detected_fd);
$fclose(sync_long_metric_fd);
$fclose(long_preamble_detected_fd);
$fclose(sync_long_out_fd);
$fclose(equalizer_out_fd);
$fclose(demod_out_fd);
$fclose(deinterleave_erase_out_fd);
$fclose(conv_out_fd);
$fclose(descramble_out_fd);
$fclose(signal_fd);
$fclose(byte_out_fd);
$finish;
end
end
if (sync_long_metric_stb) begin
$fwrite(sync_long_metric_fd, "%d %d\n", $time/2, sync_long_metric);
$fflush(sync_long_metric_fd);
end
if (sync_long_out_strobe) begin
$fwrite(sync_long_out_fd, "%d %d\n", $signed(sync_long_out[31:16]), $signed(sync_long_out[15:0]));
$fflush(sync_long_out_fd);
end
if (equalizer_out_strobe) begin
$fwrite(equalizer_out_fd, "%d %d\n", $signed(equalizer_out[31:16]), $signed(equalizer_out[15:0]));
$fflush(equalizer_out_fd);
end
if (legacy_sig_stb) begin
signal_done <= 1;
$fwrite(signal_fd, "%04b %b %012b %b %06b", legacy_rate, legacy_sig_rsvd, legacy_len, legacy_sig_parity, legacy_sig_tail);
$fflush(signal_fd);
end
if (dot11_state == S_DECODE_DATA && demod_out_strobe) begin
$fwrite(demod_out_fd, "%b %b %b %b %b %b\n",demod_out[0],demod_out[1],demod_out[2],demod_out[3],demod_out[4],demod_out[5]);
$fflush(demod_out_fd);
end
if (dot11_state == S_DECODE_DATA && deinterleave_erase_out_strobe) begin
$fwrite(deinterleave_erase_out_fd, "%b %b %b %b %b %b %b %b\n", deinterleave_erase_out[0], deinterleave_erase_out[1], deinterleave_erase_out[2], deinterleave_erase_out[3], deinterleave_erase_out[4], deinterleave_erase_out[5], deinterleave_erase_out[6], deinterleave_erase_out[7]);
$fflush(deinterleave_erase_out_fd);
end
if (dot11_state == S_DECODE_DATA && conv_decoder_out_stb) begin
$fwrite(conv_out_fd, "%b\n", conv_decoder_out);
$fflush(conv_out_fd);
end
if (dot11_state == S_DECODE_DATA && descramble_out_strobe) begin
$fwrite(descramble_out_fd, "%b\n", descramble_out);
$fflush(descramble_out_fd);
end
if (dot11_state == S_DECODE_DATA && byte_out_strobe) begin
$fwrite(byte_out_fd, "%02x\n", byte_out);
$fflush(byte_out_fd);
end
end
end
side_ch_control # (
.TSF_TIMER_WIDTH(TSF_TIMER_WIDTH), // according to 802.11 standard
.GPIO_STATUS_WIDTH(GPIO_STATUS_WIDTH),
.RSSI_HALF_DB_WIDTH(RSSI_HALF_DB_WIDTH),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.IQ_DATA_WIDTH(IQ_DATA_WIDTH),
.C_S_AXIS_TDATA_WIDTH(C_S00_AXIS_TDATA_WIDTH),
.MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
.MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL)
) side_ch_control_i (
.clk(clock),
.rstn(~reset),
// from pl
.gpio_status(34),
.rssi_half_db(54),
.tsf_runtime_val(64'd123456),
.iq(sample_in),
.iq_strobe(sample_in_strobe),
.demod_is_ongoing(demod_is_ongoing),
.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
.long_preamble_detected(long_preamble_detected),
.short_preamble_detected(short_preamble_detected),
.ht_unsupport(ht_unsupport),
.pkt_rate(pkt_rate),
.pkt_len(pkt_len),
.csi(csi),
.csi_valid(csi_valid),
.phase_offset_taken(phase_offset_taken),
.equalizer(equalizer_out),
.equalizer_valid(equalizer_out_strobe),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.FC_DI(FC_DI),
.FC_DI_valid(FC_DI_valid),
.addr1(addr1),
.addr1_valid(addr1_valid),
.addr2(addr2),
.addr2_valid(addr2_valid),
.addr3(addr3),
.addr3_valid(addr3_valid),
.fcs_in_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.block_rx_dma_to_ps(),
.block_rx_dma_to_ps_valid(),
// from arm
.slv_reg_wren_signal(slv_reg_wren_signal), // to capture m axis num dma symbol write, so that auto trigger start
.axi_awaddr_core(axi_awaddr_core),
.iq_capture(iq_capture),
.iq_trigger_select(iq_trigger_select),
.rssi_th(rssi_th),
.gain_th(gain_th),
.pre_trigger_len(pre_trigger_len),
.iq_len_target(iq_len_target),
.FC_target(16'd3243),
.addr1_target(32'd23343),
.addr2_target(32'd98765),
.match_cfg(0),
.num_eq({1'd0, num_eq[2:0]}),
.m_axis_start_mode(1),
.m_axis_start_ext_trigger(),
// s_axis
.data_to_pl(),
.pl_ask_data(),
.s_axis_data_count(),
.emptyn_to_pl(),
.S_AXIS_TVALID(),
.S_AXIS_TLAST(),
// m_axis
.m_axis_start_1trans(m_axis_start_1trans),
.data_to_ps(data_to_ps),
.data_to_ps_valid(data_to_ps_valid),
.m_axis_data_count(m_axis_data_count),
.fulln_to_pl(fulln_to_pl),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TLAST(M_AXIS_TLAST)
);
side_ch_m_axis # (
// .WAIT_COUNT_BITS(WAIT_COUNT_BITS),
.MAX_NUM_DMA_SYMBOL(MAX_NUM_DMA_SYMBOL),
.MAX_BIT_NUM_DMA_SYMBOL(MAX_BIT_NUM_DMA_SYMBOL),
.C_M_AXIS_TDATA_WIDTH(C_M00_AXIS_TDATA_WIDTH)
) side_ch_m_axis_i (
.m_axis_endless_mode(0),
.M_AXIS_NUM_DMA_SYMBOL(3222-1),
.m_axis_start_1trans(m_axis_start_1trans),
.data_to_ps(data_to_ps),
.data_to_ps_valid(data_to_ps_valid),
.m_axis_data_count(m_axis_data_count),
.fulln_to_pl(fulln_to_pl),
.M_AXIS_ACLK(clock),
.M_AXIS_ARESETN( ~reset ),
.M_AXIS_TVALID(M_AXIS_TVALID),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TLAST(M_AXIS_TLAST),
.M_AXIS_TREADY(1)
);
phy_rx_parse phy_rx_parse_inst (
.clk(clock),
.rstn( ~reset ),
.ofdm_byte_index(byte_count),
.ofdm_byte(byte_out),
.ofdm_byte_valid(byte_out_strobe),
.FC_DI(FC_DI),
.FC_DI_valid(FC_DI_valid),
.rx_addr(addr1),
.rx_addr_valid(addr1_valid),
.dst_addr(addr2),
.dst_addr_valid(addr2_valid),
.tx_addr(addr3),
.tx_addr_valid(addr3_valid),
.SC(),
.SC_valid(),
.src_addr(),
.src_addr_valid()
);
dot11 dot11_inst (
.clock(clock),
.enable(enable),
.reset(reset),
//.set_stb(set_stb),
//.set_addr(set_addr),
//.set_data(set_data),
.power_thres(11'd0),
.min_plateau(32'd100),
.rssi_half_db(rssi_half_db),
.sample_in(sample_in),
.sample_in_strobe(sample_in_strobe),
.soft_decoding(1'b1),
.demod_is_ongoing(demod_is_ongoing),
.pkt_begin(pkt_begin),
.pkt_ht(pkt_ht),
.pkt_header_valid(pkt_header_valid),
.pkt_header_valid_strobe(pkt_header_valid_strobe),
.ht_unsupport(ht_unsupport),
.pkt_rate(pkt_rate),
.pkt_len(pkt_len),
.pkt_len_total(pkt_len_total),
.byte_out_strobe(byte_out_strobe),
.byte_out(byte_out),
.byte_count_total(byte_count_total),
.byte_count(byte_count),
.fcs_out_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.state(dot11_state),
.status_code(status_code),
.state_changed(state_changed),
.state_history(state_history),
.power_trigger(power_trigger),
.short_preamble_detected(short_preamble_detected),
.phase_offset(phase_offset),
.sync_long_metric(sync_long_metric),
.sync_long_metric_stb(sync_long_metric_stb),
.long_preamble_detected(long_preamble_detected),
.sync_long_out(sync_long_out),
.sync_long_out_strobe(sync_long_out_strobe),
.phase_offset_taken(phase_offset_taken),
.sync_long_state(sync_long_state),
.equalizer_out(equalizer_out),
.equalizer_out_strobe(equalizer_out_strobe),
.equalizer_state(equalizer_state),
.ofdm_symbol_eq_out_pulse(ofdm_symbol_eq_out_pulse),
.legacy_sig_stb(legacy_sig_stb),
.legacy_rate(legacy_rate),
.legacy_sig_rsvd(legacy_sig_rsvd),
.legacy_len(legacy_len),
.legacy_sig_parity(legacy_sig_parity),
.legacy_sig_parity_ok(legacy_sig_parity_ok),
.legacy_sig_tail(legacy_sig_tail),
.ht_sig_stb(ht_sig_stb),
.ht_mcs(ht_mcs),
.ht_cbw(ht_cbw),
.ht_len(ht_len),
.ht_smoothing(ht_smoothing),
.ht_not_sounding(ht_not_sounding),
.ht_aggregation(ht_aggregation),
.ht_stbc(ht_stbc),
.ht_fec_coding(ht_fec_coding),
.ht_sgi(ht_sgi),
.ht_num_ext(ht_num_ext),
.ht_sig_crc_ok(ht_sig_crc_ok),
.demod_out(demod_out),
.demod_out_strobe(demod_out_strobe),
.deinterleave_erase_out(deinterleave_erase_out),
.deinterleave_erase_out_strobe(deinterleave_erase_out_strobe),
.conv_decoder_out(conv_decoder_out),
.conv_decoder_out_stb(conv_decoder_out_stb),
.csi(csi),
.csi_valid(csi_valid),
.descramble_out(descramble_out),
.descramble_out_strobe(descramble_out_strobe)
);
/*
byte_to_word_fcs_sn_insert byte_to_word_fcs_sn_insert_inst (
.clk(clock),
.rstn((~reset)&(~pkt_header_valid_strobe)),
.byte_in(byte_out),
.byte_in_strobe(byte_out_strobe),
.byte_count(byte_count),
.num_byte(pkt_len),
.fcs_in_strobe(fcs_out_strobe),
.fcs_ok(fcs_ok),
.rx_pkt_sn_plus_one(0),
.word_out(word_out),
.word_out_strobe(word_out_strobe)
);
*/
endmodule |
module signal_watchdog
#(
parameter integer IQ_DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input enable,
input signed [(IQ_DATA_WIDTH-1):0] i_data,
input signed [(IQ_DATA_WIDTH-1):0] q_data,
input iq_valid,
input power_trigger,
input [15:0] signal_len,
input sig_valid,
input [15:0] min_signal_len_th,
input [15:0] max_signal_len_th,
input signed [(LOG2_SUM_LEN+2-1):0] dc_running_sum_th,
output receiver_rst
);
wire signed [1:0] i_sign;
wire signed [1:0] q_sign;
reg signed [1:0] fake_non_dc_in_case_all_zero;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_i_abs;
wire signed [(LOG2_SUM_LEN+2-1):0] running_sum_result_q_abs;
wire receiver_rst_internal;
reg receiver_rst_reg;
wire receiver_rst_pulse;
assign i_sign = (i_data == 0? fake_non_dc_in_case_all_zero : (i_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign q_sign = (q_data == 0? fake_non_dc_in_case_all_zero : (q_data[(IQ_DATA_WIDTH-1)] ? -1 : 1) );
assign running_sum_result_i_abs = (running_sum_result_i[LOG2_SUM_LEN+2-1]?(-running_sum_result_i):running_sum_result_i);
assign running_sum_result_q_abs = (running_sum_result_q[LOG2_SUM_LEN+2-1]?(-running_sum_result_q):running_sum_result_q);
assign receiver_rst_internal = (enable&(running_sum_result_i_abs>=dc_running_sum_th || running_sum_result_q_abs>=dc_running_sum_th));
assign receiver_rst_pulse = (receiver_rst_internal&&(~receiver_rst_reg));
assign receiver_rst = ( power_trigger & ( receiver_rst_reg | (sig_valid && (signal_len<min_signal_len_th || signal_len>max_signal_len_th)) ) );
always @(posedge clk) begin
if (~rstn) begin
receiver_rst_reg <= 0;
fake_non_dc_in_case_all_zero <= 1;
end else begin
receiver_rst_reg <= receiver_rst_internal;
if (iq_valid) begin
if (fake_non_dc_in_case_all_zero == 1) begin
fake_non_dc_in_case_all_zero <= -1;
end else begin
fake_non_dc_in_case_all_zero <= 1;
end
end
end
end
running_sum_dual_ch #(.DATA_WIDTH0(2), .DATA_WIDTH1(2), .LOG2_SUM_LEN(LOG2_SUM_LEN)) signal_watchdog_running_sum_inst (
.clk(clk),
.rstn(rstn),
.data_in0(i_sign),
.data_in1(q_sign),
.data_in_valid(iq_valid),
.running_sum_result0(running_sum_result_i),
.running_sum_result1(running_sum_result_q),
.data_out_valid()
);
endmodule |
module running_sum
#(
parameter DATA_WIDTH = 16,
parameter LOG2_SUM_LEN = 6
)
(
input clk,
input rstn,
input signed [DATA_WIDTH-1:0] data_in,
input data_in_valid,
output reg signed [(DATA_WIDTH + LOG2_SUM_LEN-1):0] running_sum_result,
output reg data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_SUM_LEN;
localparam TOTAL_WIDTH = DATA_WIDTH + LOG2_SUM_LEN;
wire signed [DATA_WIDTH-1:0] data_in_old;
wire signed [TOTAL_WIDTH-1:0] ext_data_in_old = {{LOG2_SUM_LEN{data_in_old[DATA_WIDTH-1]}}, data_in_old};
wire signed [TOTAL_WIDTH-1:0] ext_data_in = {{LOG2_SUM_LEN{data_in[DATA_WIDTH-1]}}, data_in };
reg data_in_valid_reg;
reg rd_en, rd_en_start;
wire [LOG2_SUM_LEN:0] wr_data_count;
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_SUM_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout(data_in_old),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din(data_in),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in_valid_reg <= 0;
running_sum_result <= 0;
data_out_valid <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in_valid_reg <= data_in_valid;
data_out_valid <= data_in_valid_reg;
rd_en_start <= ((wr_data_count == FIFO_SIZE)?1:rd_en_start);
rd_en <= (rd_en_start?data_in_valid:rd_en);
if (data_in_valid) begin
running_sum_result <= running_sum_result + ext_data_in - (rd_en_start?ext_data_in_old:0);
end
end
end
endmodule |
module complex_to_mag
#(
parameter DATA_WIDTH = 16
)
(
input clock,
input enable,
input reset,
input signed [DATA_WIDTH-1:0] i,
input signed [DATA_WIDTH-1:0] q,
input input_strobe,
output reg [DATA_WIDTH-1:0] mag,
output reg mag_stb
);
reg [DATA_WIDTH-1:0] abs_i;
reg [DATA_WIDTH-1:0] abs_q;
reg [DATA_WIDTH-1:0] max;
reg[ DATA_WIDTH-1:0] min;
reg input_strobe_reg0;
reg input_strobe_reg1;
// delayT #(.DATA_WIDTH(1), .DELAY(3)) stb_delay_inst (
// .clock(clock),
// .reset(reset),
// .data_in(input_strobe),
// .data_out(mag_stb)
// );
// http://dspguru.com/dsp/tricks/magnitude-estimator
// alpha = 1, beta = 1/4
// avg err 0.006
always @(posedge clock) begin
if (reset) begin
mag <= 0;
abs_i <= 0;
abs_q <= 0;
max <= 0;
min <= 0;
input_strobe_reg0 <= 0;
input_strobe_reg1 <= 0;
end else if (enable) begin
abs_i <= i[DATA_WIDTH-1]? (~i+1): i;
abs_q <= q[DATA_WIDTH-1]? (~q+1): q;
max <= abs_i > abs_q? abs_i: abs_q;
min <= abs_i > abs_q? abs_q: abs_i;
mag <= max + (min>>2);
input_strobe_reg0 <= input_strobe;
input_strobe_reg1 <= input_strobe_reg0;
mag_stb <= input_strobe_reg1;
end
end
endmodule |
module intf_64bit (
input clock,
input reset,
input enable,
input wire [15:0] pkt_len,
input wire [31:0] byte_index,
input wire [7:0] byte_in,
input wire byte_strobe,
output reg [63:0] data_out,
output reg output_strobe
);
reg byte_strobe_delay ;
reg [63:0] dout ;
always @ (posedge clock)
begin
byte_strobe_delay <= byte_strobe ;
//data_out <= dout ;
end
always @ (posedge clock)
begin
if(reset) begin
dout <= 64'h0 ;
data_out <= 64'h0;
output_strobe <= 1'b0 ;
end
else if(enable) begin
output_strobe <= 1'b0 ;
data_out <= dout ;
if(byte_strobe) begin
dout <= {byte_in, dout[63:8]} ;
end
if(byte_strobe_delay) begin
if(byte_index[2:0] == 3'b0 && byte_index[31:3] > 0 )
output_strobe <= 1'b1 ;
else if (pkt_len == byte_index) begin
output_strobe <= 1'b1 ;
case (pkt_len[2:0])
3'b000: data_out <= dout;
3'b001: begin data_out <= {56'b0,dout[63:56]}; dout <= {56'b0,dout[63:56]}; end
3'b010: begin data_out <= {48'b0,dout[63:48]}; dout <= {48'b0,dout[63:48]}; end
3'b011: begin data_out <= {40'b0,dout[63:40]}; dout <= {40'b0,dout[63:40]}; end
3'b100: begin data_out <= {32'b0,dout[63:32]}; dout <= {32'b0,dout[63:32]}; end
3'b101: begin data_out <= {24'b0,dout[63:24]}; dout <= {24'b0,dout[63:24]}; end
3'b110: begin data_out <= {16'b0,dout[63:16]}; dout <= {16'b0,dout[63:16]}; end
3'b111: begin data_out <= {8'b0,dout[63:8]}; dout <= {8'b0,dout[63:8]}; end
default: data_out <= dout;
endcase
end
end
end
end
endmodule |
module mv_avg_dual_ch
#(
parameter DATA_WIDTH0 = 16,
parameter DATA_WIDTH1 = 16,
parameter LOG2_AVG_LEN = 5
)
(
input clk,
input rstn,
input signed [DATA_WIDTH0-1:0] data_in0,
input signed [DATA_WIDTH1-1:0] data_in1,
input data_in_valid,
output signed [DATA_WIDTH0-1:0] data_out0,
output signed [DATA_WIDTH1-1:0] data_out1,
output data_out_valid
);
localparam FIFO_SIZE = 1<<LOG2_AVG_LEN;
localparam TOTAL_WIDTH0 = DATA_WIDTH0 + LOG2_AVG_LEN;
localparam TOTAL_WIDTH1 = DATA_WIDTH1 + LOG2_AVG_LEN;
reg signed [(TOTAL_WIDTH0-1):0] running_total0;
reg signed [(TOTAL_WIDTH1-1):0] running_total1;
reg signed [DATA_WIDTH0-1:0] data_in0_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
reg signed [DATA_WIDTH0-1:0] data_in1_reg; // to lock data_in by data_in_valid in case it changes in between two valid strobes
wire signed [DATA_WIDTH0-1:0] data_in_old0;
wire signed [DATA_WIDTH1-1:0] data_in_old1;
wire signed [TOTAL_WIDTH0-1:0] ext_data_in_old0 = {{LOG2_AVG_LEN{data_in_old0[DATA_WIDTH0-1]}}, data_in_old0};
wire signed [TOTAL_WIDTH0-1:0] ext_data_in0 = {{LOG2_AVG_LEN{data_in0_reg[DATA_WIDTH0-1]}}, data_in0_reg};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in_old1 = {{LOG2_AVG_LEN{data_in_old1[DATA_WIDTH1-1]}}, data_in_old1};
wire signed [TOTAL_WIDTH1-1:0] ext_data_in1 = {{LOG2_AVG_LEN{data_in1_reg[DATA_WIDTH1-1]}}, data_in1_reg};
reg rd_en, rd_en_start;
wire [LOG2_AVG_LEN:0] wr_data_count;
reg [LOG2_AVG_LEN:0] wr_data_count_reg;
wire wr_complete_pulse;
reg wr_complete_pulse_reg;
assign wr_complete_pulse = (wr_data_count > wr_data_count_reg);
assign data_out_valid = wr_complete_pulse_reg;
assign data_out0 = running_total0[TOTAL_WIDTH0-1:LOG2_AVG_LEN];
assign data_out1 = running_total1[TOTAL_WIDTH1-1:LOG2_AVG_LEN];
xpm_fifo_sync #(
.DOUT_RESET_VALUE("0"), // String
.ECC_MODE("no_ecc"), // String
.FIFO_MEMORY_TYPE("auto"), // String
.FIFO_READ_LATENCY(0), // DECIMAL
.FIFO_WRITE_DEPTH(FIFO_SIZE), // DECIMAL minimum 16!
.FULL_RESET_VALUE(0), // DECIMAL
.PROG_EMPTY_THRESH(10), // DECIMAL
.PROG_FULL_THRESH(10), // DECIMAL
.RD_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1), // DECIMAL
.READ_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.READ_MODE("fwft"), // String
.USE_ADV_FEATURES("0404"), // only enable rd_data_count and wr_data_count
.WAKEUP_TIME(0), // DECIMAL
.WRITE_DATA_WIDTH(DATA_WIDTH0+DATA_WIDTH1), // DECIMAL
.WR_DATA_COUNT_WIDTH(LOG2_AVG_LEN+1) // DECIMAL
) fifo_1clk_for_mv_avg_dual_ch_i (
.almost_empty(),
.almost_full(),
.data_valid(),
.dbiterr(),
.dout({data_in_old1, data_in_old0}),
.empty(empty),
.full(full),
.overflow(),
.prog_empty(),
.prog_full(),
.rd_data_count(),
.rd_rst_busy(),
.sbiterr(),
.underflow(),
.wr_ack(),
.wr_data_count(wr_data_count),
.wr_rst_busy(),
.din({data_in1, data_in0}),
.injectdbiterr(),
.injectsbiterr(),
.rd_en(rd_en),
.rst(~rstn),
.sleep(),
.wr_clk(clk),
.wr_en(data_in_valid)
);
always @(posedge clk) begin
if (~rstn) begin
data_in0_reg <= 0;
data_in1_reg <= 0;
wr_complete_pulse_reg <= 0;
wr_data_count_reg <= 0;
running_total0 <= 0;
running_total1 <= 0;
rd_en <= 0;
rd_en_start <= 0;
end else begin
data_in0_reg <= (data_in_valid?data_in0:data_in0_reg);
data_in1_reg <= (data_in_valid?data_in1:data_in1_reg);
wr_complete_pulse_reg <= wr_complete_pulse;
wr_data_count_reg <= wr_data_count;
rd_en_start <= ((wr_data_count == (FIFO_SIZE))?1:rd_en_start);
rd_en <= (rd_en_start?wr_complete_pulse:rd_en);
if (wr_complete_pulse) begin
running_total0 <= running_total0 + ext_data_in0 - (rd_en_start?ext_data_in_old0:0);
running_total1 <= running_total1 + ext_data_in1 - (rd_en_start?ext_data_in_old1:0);
end
end
end
endmodule |
module descramble
(
input clock,
input enable,
input reset,
input in_bit,
input input_strobe,
output reg out_bit,
output reg output_strobe
);
reg [6:0] state;
reg [4:0] bit_count;
reg inited;
wire feedback = state[6] ^ state[3];
always @(posedge clock) begin
if (reset) begin
bit_count <= 0;
state <= 0;
inited <= 0;
out_bit <= 0;
output_strobe <= 0;
end else if (enable & input_strobe) begin
if (!inited) begin
state[6-bit_count] <= in_bit;
if (bit_count == 6) begin
bit_count <= 0;
inited <= 1;
end else begin
bit_count <= bit_count + 1;
end
end else begin
out_bit <= feedback ^ in_bit;
output_strobe <= 1;
state <= {state[5:0], feedback};
end
end else begin
output_strobe <= 0;
end
end
endmodule |
module deinterleave
(
input clock,
input reset,
input enable,
input [7:0] rate,
input [5:0] in_bits,
input [5:0] soft_in_bits,
input [3:0] soft_in_bits_pos,
input input_strobe,
input soft_decoding,
output reg [5:0] out_bits,
output [1:0] erase,
output output_strobe
);
wire ht = rate[7];
wire [5:0] num_data_carrier = ht? 52: 48;
wire [5:0] half_data_carrier = ht? 26: 24;
reg [5:0] addra;
reg [5:0] addrb;
reg [11:0] lut_key;
wire [21:0] lut_out;
wire [21:0] lut_out_delayed;
reg lut_valid;
wire lut_valid_delayed;
assign erase[0] = lut_out_delayed[21];
assign erase[1] = lut_out_delayed[20];
wire [2:0] lut_bita = lut_out_delayed[7:5];
wire [2:0] lut_bitb = lut_out_delayed[4:2];
wire [5:0] bit_outa;
wire [5:0] bit_outb;
wire [5:0] soft_bit_outa;
wire [5:0] soft_bit_outb;
wire [3:0] soft_bit_outa_pos;
wire [3:0] soft_bit_outb_pos;
// Soft and hard decoding
wire [4:0] MOD_TYPE = {rate[7], rate[3:0]};
wire BPSK = MOD_TYPE == 5'b01011 || MOD_TYPE == 5'b01111 || MOD_TYPE == 5'b10000;
wire QPSK = MOD_TYPE == 5'b01010 || MOD_TYPE == 5'b01110 || MOD_TYPE == 5'b10001 || MOD_TYPE == 5'b10010;
wire QAM_16 = MOD_TYPE == 5'b01001 || MOD_TYPE == 5'b01101 || MOD_TYPE == 5'b10011 || MOD_TYPE == 5'b10100;
wire QAM_64 = MOD_TYPE == 5'b01000 || MOD_TYPE == 5'b01100 || MOD_TYPE == 5'b10101 || MOD_TYPE == 5'b10110 || MOD_TYPE == 5'b10111;
wire [2:0] N_BPSC_DIV_2 = BPSK ? 3'b000 : (QPSK ? 3'b001 : (QAM_16 ? 3'b010: (QAM_64 ? 3'b011 : 3'b111)));
always @* begin
if(lut_valid_delayed == 1'b1) begin
// Soft decoding
if(soft_decoding && (BPSK || QPSK || QAM_16 || QAM_64)) begin
if(BPSK || lut_bita < N_BPSC_DIV_2) begin
if(lut_bita[1:0] == soft_bit_outa_pos[1:0]) begin
out_bits[2:0] = soft_bit_outa[2:0];
end else begin
if(bit_outa[lut_bita] == 1'b1)
out_bits[2:0] = 3'b111;
else
out_bits[2:0] = 3'b011;
end
end else begin
if(lut_bita == ({1'b0,soft_bit_outa_pos[3:2]} + N_BPSC_DIV_2)) begin
out_bits[2:0] = soft_bit_outa[5:3];
end else begin
if(bit_outa[lut_bita] == 1'b1)
out_bits[2:0] = 3'b111;
else
out_bits[2:0] = 3'b011;
end
end
if(BPSK || lut_bitb < N_BPSC_DIV_2) begin
if(lut_bitb[1:0] == soft_bit_outb_pos[1:0]) begin
out_bits[5:3] = soft_bit_outb[2:0];
end else begin
if(bit_outb[lut_bitb] == 1'b1)
out_bits[5:3] = 3'b111;
else
out_bits[5:3] = 3'b011;
end
end else begin
if(lut_bitb == ({1'b0,soft_bit_outb_pos[3:2]} + N_BPSC_DIV_2)) begin
out_bits[5:3] = soft_bit_outb[5:3];
end else begin
if(bit_outb[lut_bitb] == 1'b1)
out_bits[5:3] = 3'b111;
else
out_bits[5:3] = 3'b011;
end
end
// Hard decoding
end else begin
if(bit_outa[lut_bita] == 1'b1)
out_bits[2:0] = 3'b111;
else
out_bits[2:0] = 3'b011;
if(bit_outb[lut_bitb] == 1'b1)
out_bits[5:3] = 3'b111;
else
out_bits[5:3] = 3'b011;
end
end else begin
out_bits[2:0] = 0;
out_bits[5:3] = 0;
end
end
//assign out_bits[0] = lut_valid_delayed? bit_outa[lut_bita]: 0;
//assign out_bits[1] = lut_valid_delayed? bit_outb[lut_bitb]: 0;
assign output_strobe = enable & lut_valid_delayed & lut_out_delayed[1];
wire [5:0] lut_addra = lut_out[19:14];
wire [5:0] lut_addrb = lut_out[13:8];
wire lut_done = lut_out[0];
reg ram_delay;
reg ht_delayed;
ram_2port #(.DWIDTH(16), .AWIDTH(6)) ram_inst (
.clka(clock),
.ena(1),
.wea(input_strobe),
.addra(addra),
.dia({in_bits, soft_in_bits, soft_in_bits_pos}),
.doa({bit_outa,soft_bit_outa,soft_bit_outa_pos}),
.clkb(clock),
.enb(1),
.web(0),
.addrb(addrb),
.dib(32'hFFFF),
.dob({bit_outb,soft_bit_outb,soft_bit_outb_pos})
);
deinter_lut lut_inst (
.clka(clock),
.addra(lut_key),
.douta(lut_out)
);
delayT #(.DATA_WIDTH(23), .DELAY(2)) delay_inst (
.clock(clock),
.reset(reset),
.data_in({lut_valid, lut_out}),
.data_out({lut_valid_delayed, lut_out_delayed})
);
localparam S_INPUT = 0;
localparam S_GET_BASE = 1;
localparam S_OUTPUT = 2;
reg [1:0] state;
always @(posedge clock) begin
if (reset) begin
addra <= num_data_carrier>>1;
addrb <= 0;
lut_key <= 0;
lut_valid <= 0;
ht_delayed <= 0;
ram_delay <= 0;
state <= S_INPUT;
end else if (enable) begin
ht_delayed <= ht;
if (ht != ht_delayed) begin
addra <= num_data_carrier>>1;
end
case(state)
S_INPUT: begin
if (input_strobe) begin
if (addra == half_data_carrier-1) begin
lut_key <= {7'b0, ht, rate[3:0]};
ram_delay <= 0;
lut_valid <= 0;
state <= S_GET_BASE;
end else begin
if (addra == num_data_carrier-1) begin
addra <= 0;
end else begin
addra <= addra + 1;
end
end
end
end
S_GET_BASE: begin
if (ram_delay) begin
lut_key <= lut_out;
ram_delay <= 0;
state <= S_OUTPUT;
end else begin
ram_delay <= 1;
end
end
S_OUTPUT: begin
if (ram_delay) begin
addra <= lut_addra;
addrb <= lut_addrb;
if (lut_done) begin
lut_key <= 0;
lut_valid <= 0;
state <= S_INPUT;
end else begin
lut_valid <= 1;
lut_key <= lut_key + 1;
end
end else begin
ram_delay <= 1;
lut_valid <= 1;
lut_key <= lut_key + 1;
end
end
default: begin
end
endcase
end
end
endmodule |
module ram_2port
#(
parameter DWIDTH=32,
parameter AWIDTH=9
)
(
input clka,
input ena,
input wea,
input [AWIDTH-1:0] addra,
input [DWIDTH-1:0] dia,
output reg [DWIDTH-1:0] doa,
input clkb,
input enb,
input web,
input [AWIDTH-1:0] addrb,
input [DWIDTH-1:0] dib,
output reg [DWIDTH-1:0] dob
);
reg [DWIDTH-1:0] ram [(1<<AWIDTH)-1:0];
integer i;
initial begin
for(i=0;i<(1<<AWIDTH);i=i+1)
ram[i] <= {DWIDTH{1'b0}};
doa <= 0;
dob <= 0;
end
always @(posedge clka) begin
if (ena)
begin
if (wea)
ram[addra] <= dia;
doa <= ram[addra];
end
end
always @(posedge clkb) begin
if (enb)
begin
if (web)
ram[addrb] <= dib;
dob <= ram[addrb];
end
end
endmodule // ram_2port |
module setting_reg
#(parameter my_addr = 0,
parameter width = 32,
parameter at_reset=32'd0)
(input clk, input rst, input strobe, input wire [7:0] addr,
input wire [31:0] in, output reg [width-1:0] out, output reg changed);
always @(posedge clk)
if(rst)
begin
out <= at_reset;
changed <= 1'b0;
end
else
if(strobe & (my_addr==addr))
begin
out <= in;
changed <= 1'b1;
end
else
changed <= 1'b0;
endmodule // setting_reg |
module deinter_lut(
clka,
addra,
douta);
input clka;
input [10 : 0] addra;
output [21 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V4_2 #(
.C_ADDRA_WIDTH(11),
.C_ADDRB_WIDTH(11),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan3"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("deinter_lut.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(2048),
.C_READ_DEPTH_B(2048),
.C_READ_WIDTH_A(22),
.C_READ_WIDTH_B(22),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(2048),
.C_WRITE_DEPTH_B(2048),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(22),
.C_WRITE_WIDTH_B(22),
.C_XDEVICEFAMILY("spartan3adsp"))
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of deinter_lut is "black_box"
endmodule |
module MUXF7_L (LO, I0, I1, S);
output LO;
reg LO;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
LO = I1;
else
LO = I0;
endmodule |
module LUT3_D (LO, O, I0, I1, I2);
parameter INIT = 8'h00;
input I0, I1, I2;
output LO, O;
reg O;
reg tmp;
assign LO = O;
always @( I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2;
if ( tmp == 0 || tmp == 1)
O = INIT[{I2, I1, I0}];
else
O = lut3_mux4 ( {1'b0, 1'b0, lut3_mux4 (INIT[7:4], {I1, I0}),
lut3_mux4 (INIT[3:0], {I1, I0}) }, {1'b0, I2});
end
function lut3_mux4;
input [3:0] d;
input [1:0] s;
begin
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
lut3_mux4 = d[s];
else if ((d[0] === d[1]) && (d[2] === d[3]) && (d[0] === d[2]))
lut3_mux4 = d[0];
else if ((s[1] == 0) && (d[0] === d[1]))
lut3_mux4 = d[0];
else if ((s[1] == 1) && (d[2] === d[3]))
lut3_mux4 = d[2];
else if ((s[0] == 0) && (d[0] === d[2]))
lut3_mux4 = d[0];
else if ((s[0] == 1) && (d[1] === d[3]))
lut3_mux4 = d[1];
else
lut3_mux4 = 1'bx;
end
endfunction
endmodule |
module SRL16E_1 (Q, A0, A1, A2, A3, CE, CLK, D);
parameter INIT = 16'h0000;
output Q;
input A0, A1, A2, A3, CE, CLK, D;
reg [15:0] data;
wire clk_;
assign Q = data[{A3, A2, A1, A0}];
assign clk_ = ~CLK;
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_===1'bX)
#10;
deassign data;
end
always @(posedge clk_)
begin
if (CE == 1'b1) begin
{data[15:0]} <= #100 {data[14:0], D};
end
end
endmodule |
module ICAP_VIRTEX5 (
BUSY,
O,
CE,
CLK,
I,
WRITE
);
output BUSY;
output [31:0] O;
input CE;
input CLK;
input WRITE;
input [31:0] I;
parameter ICAP_WIDTH = "X8";
initial begin
case (ICAP_WIDTH)
"X8" , "X16", "X32" : ;
default : begin
$display("Attribute Syntax Error : The Attribute ICAP_WIDTH on ICAP_VIRTEX5 instance %m is set to %s. Legal values for this attribute are X8, X16 or X32.", ICAP_WIDTH);
$finish;
end
endcase
end
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module IBUFG_HSTL_IV_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR4B4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv);
endmodule |
module GT11_CUSTOM (
CHBONDO,
DO,
DRDY,
RXBUFERR,
RXCALFAIL,
RXCHARISCOMMA,
RXCHARISK,
RXCOMMADET,
RXCRCOUT,
RXCYCLELIMIT,
RXDATA,
RXDISPERR,
RXLOCK,
RXLOSSOFSYNC,
RXMCLK,
RXNOTINTABLE,
RXPCSHCLKOUT,
RXREALIGN,
RXRECCLK1,
RXRECCLK2,
RXRUNDISP,
RXSIGDET,
RXSTATUS,
TX1N,
TX1P,
TXBUFERR,
TXCALFAIL,
TXCRCOUT,
TXCYCLELIMIT,
TXKERR,
TXLOCK,
TXOUTCLK1,
TXOUTCLK2,
TXPCSHCLKOUT,
TXRUNDISP,
CHBONDI,
DADDR,
DCLK,
DEN,
DI,
DWE,
ENCHANSYNC,
ENMCOMMAALIGN,
ENPCOMMAALIGN,
GREFCLK,
LOOPBACK,
POWERDOWN,
REFCLK1,
REFCLK2,
RX1N,
RX1P,
RXBLOCKSYNC64B66BUSE,
RXCLKSTABLE,
RXCOMMADETUSE,
RXCRCCLK,
RXCRCDATAVALID,
RXCRCDATAWIDTH,
RXCRCIN,
RXCRCINIT,
RXCRCINTCLK,
RXCRCPD,
RXCRCRESET,
RXDATAWIDTH,
RXDEC64B66BUSE,
RXDEC8B10BUSE,
RXDESCRAM64B66BUSE,
RXIGNOREBTF,
RXINTDATAWIDTH,
RXPMARESET,
RXPOLARITY,
RXRESET,
RXSLIDE,
RXSYNC,
RXUSRCLK,
RXUSRCLK2,
TXBYPASS8B10B,
TXCHARDISPMODE,
TXCHARDISPVAL,
TXCHARISK,
TXCLKSTABLE,
TXCRCCLK,
TXCRCDATAVALID,
TXCRCDATAWIDTH,
TXCRCIN,
TXCRCINIT,
TXCRCINTCLK,
TXCRCPD,
TXCRCRESET,
TXDATA,
TXDATAWIDTH,
TXENC64B66BUSE,
TXENC8B10BUSE,
TXENOOB,
TXGEARBOX64B66BUSE,
TXINHIBIT,
TXINTDATAWIDTH,
TXPMARESET,
TXPOLARITY,
TXRESET,
TXSCRAM64B66BUSE,
TXSYNC,
TXUSRCLK,
TXUSRCLK2
);
parameter BANDGAPSEL = "FALSE";
parameter BIASRESSEL = "FALSE";
parameter CCCB_ARBITRATOR_DISABLE = "FALSE";
parameter CHAN_BOND_MODE = "NONE";
parameter CHAN_BOND_ONE_SHOT = "FALSE";
parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_1_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000;
parameter CHAN_BOND_SEQ_2_MASK = 4'b1110;
parameter CHAN_BOND_SEQ_2_USE = "FALSE";
parameter CLK_CORRECT_USE = "FALSE";
parameter CLK_COR_8B10B_DE = "FALSE";
parameter CLK_COR_SEQ_1_1 = 11'b00000000000;
parameter CLK_COR_SEQ_1_2 = 11'b00000000000;
parameter CLK_COR_SEQ_1_3 = 11'b00000000000;
parameter CLK_COR_SEQ_1_4 = 11'b00000000000;
parameter CLK_COR_SEQ_1_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_1 = 11'b00000000000;
parameter CLK_COR_SEQ_2_2 = 11'b00000000000;
parameter CLK_COR_SEQ_2_3 = 11'b00000000000;
parameter CLK_COR_SEQ_2_4 = 11'b00000000000;
parameter CLK_COR_SEQ_2_MASK = 4'b1110;
parameter CLK_COR_SEQ_2_USE = "FALSE";
parameter CLK_COR_SEQ_DROP = "FALSE";
parameter COMMA32 = "FALSE";
parameter COMMA_10B_MASK = 10'h3FF;
parameter CYCLE_LIMIT_SEL = 2'b00;
parameter DCDR_FILTER = 3'b010;
parameter DEC_MCOMMA_DETECT = "TRUE";
parameter DEC_PCOMMA_DETECT = "TRUE";
parameter DEC_VALID_COMMA_ONLY = "TRUE";
parameter DIGRX_FWDCLK = 2'b00;
parameter DIGRX_SYNC_MODE = "FALSE";
parameter ENABLE_DCDR = "FALSE";
parameter FDET_HYS_CAL = 3'b010;
parameter FDET_HYS_SEL = 3'b100;
parameter FDET_LCK_CAL = 3'b100;
parameter FDET_LCK_SEL = 3'b001;
parameter IREFBIASMODE = 2'b11;
parameter LOOPCAL_WAIT = 2'b00;
parameter MCOMMA_32B_VALUE = 32'h00000000;
parameter MCOMMA_DETECT = "TRUE";
parameter OPPOSITE_SELECT = "FALSE";
parameter PCOMMA_32B_VALUE = 32'h00000000;
parameter PCOMMA_DETECT = "TRUE";
parameter PCS_BIT_SLIP = "FALSE";
parameter PMACLKENABLE = "TRUE";
parameter PMACOREPWRENABLE = "TRUE";
parameter PMAIREFTRIM = 4'b0111;
parameter PMAVBGCTRL = 5'b00000;
parameter PMAVREFTRIM = 4'b0111;
parameter PMA_BIT_SLIP = "FALSE";
parameter POWER_ENABLE = "TRUE";
parameter REPEATER = "FALSE";
parameter RXACTST = "FALSE";
parameter RXAFEEQ = 9'b000000000;
parameter RXAFEPD = "FALSE";
parameter RXAFETST = "FALSE";
parameter RXAPD = "FALSE";
parameter RXAREGCTRL = 5'b00000;
parameter RXASYNCDIVIDE = 2'b11;
parameter RXBY_32 = "FALSE";
parameter RXCDRLOS = 6'b000000;
parameter RXCLK0_FORCE_PMACLK = "FALSE";
parameter RXCLKMODE = 6'b110001;
parameter RXCLMODE = 2'b00;
parameter RXCMADJ = 2'b01;
parameter RXCPSEL = "TRUE";
parameter RXCPTST = "FALSE";
parameter RXCRCCLOCKDOUBLE = "FALSE";
parameter RXCRCENABLE = "FALSE";
parameter RXCRCINITVAL = 32'h00000000;
parameter RXCRCINVERTGEN = "FALSE";
parameter RXCRCSAMECLOCK = "FALSE";
parameter RXCTRL1 = 10'h200;
parameter RXCYCLE_LIMIT_SEL = 2'b00;
parameter RXDATA_SEL = 2'b00;
parameter RXDCCOUPLE = "FALSE";
parameter RXDIGRESET = "FALSE";
parameter RXDIGRX = "FALSE";
parameter RXEQ = 64'h4000000000000000;
parameter RXFDCAL_CLOCK_DIVIDE = "NONE";
parameter RXFDET_HYS_CAL = 3'b010;
parameter RXFDET_HYS_SEL = 3'b100;
parameter RXFDET_LCK_CAL = 3'b100;
parameter RXFDET_LCK_SEL = 3'b001;
parameter RXFECONTROL1 = 2'b00;
parameter RXFECONTROL2 = 3'b000;
parameter RXFETUNE = 2'b01;
parameter RXLB = "FALSE";
parameter RXLKADJ = 5'b00000;
parameter RXLKAPD = "FALSE";
parameter RXLOOPCAL_WAIT = 2'b00;
parameter RXLOOPFILT = 4'b0111;
parameter RXMODE = 6'b000000;
parameter RXPD = "FALSE";
parameter RXPDDTST = "TRUE";
parameter RXPMACLKSEL = "REFCLK1";
parameter RXRCPADJ = 3'b011;
parameter RXRCPPD = "FALSE";
parameter RXRECCLK1_USE_SYNC = "FALSE";
parameter RXRIBADJ = 2'b11;
parameter RXRPDPD = "FALSE";
parameter RXRSDPD = "FALSE";
parameter RXSLOWDOWN_CAL = 2'b00;
parameter RXTUNE = 13'h0000;
parameter RXVCODAC_INIT = 10'b1010000000;
parameter RXVCO_CTRL_ENABLE = "FALSE";
parameter RX_BUFFER_USE = "TRUE";
parameter RX_CLOCK_DIVIDER = 2'b00;
parameter SAMPLE_8X = "FALSE";
parameter SLOWDOWN_CAL = 2'b00;
parameter TXABPMACLKSEL = "REFCLK1";
parameter TXAPD = "FALSE";
parameter TXAREFBIASSEL = "TRUE";
parameter TXASYNCDIVIDE = 2'b11;
parameter TXCLK0_FORCE_PMACLK = "FALSE";
parameter TXCLKMODE = 4'b1001;
parameter TXCLMODE = 2'b00;
parameter TXCPSEL = "TRUE";
parameter TXCRCCLOCKDOUBLE = "FALSE";
parameter TXCRCENABLE = "FALSE";
parameter TXCRCINITVAL = 32'h00000000;
parameter TXCRCINVERTGEN = "FALSE";
parameter TXCRCSAMECLOCK = "FALSE";
parameter TXCTRL1 = 10'h200;
parameter TXDATA_SEL = 2'b00;
parameter TXDAT_PRDRV_DAC = 3'b111;
parameter TXDAT_TAP_DAC = 5'b10110;
parameter TXDIGPD = "FALSE";
parameter TXFDCAL_CLOCK_DIVIDE = "NONE";
parameter TXHIGHSIGNALEN = "TRUE";
parameter TXLOOPFILT = 4'b0111;
parameter TXLVLSHFTPD = "FALSE";
parameter TXOUTCLK1_USE_SYNC = "FALSE";
parameter TXPD = "FALSE";
parameter TXPHASESEL = "FALSE";
parameter TXPOST_PRDRV_DAC = 3'b111;
parameter TXPOST_TAP_DAC = 5'b01110;
parameter TXPOST_TAP_PD = "TRUE";
parameter TXPRE_PRDRV_DAC = 3'b111;
parameter TXPRE_TAP_DAC = 5'b00000;
parameter TXPRE_TAP_PD = "TRUE";
parameter TXSLEWRATE = "FALSE";
parameter TXTERMTRIM = 4'b1100;
parameter TXTUNE = 13'h0000;
parameter TX_BUFFER_USE = "TRUE";
parameter TX_CLOCK_DIVIDER = 2'b00;
parameter VCODAC_INIT = 10'b1010000000;
parameter VCO_CTRL_ENABLE = "FALSE";
parameter VREFBIASMODE = 2'b11;
parameter integer ALIGN_COMMA_WORD = 4;
parameter integer CHAN_BOND_LIMIT = 16;
parameter integer CHAN_BOND_SEQ_LEN = 1;
parameter integer CLK_COR_MAX_LAT = 48;
parameter integer CLK_COR_MIN_LAT = 36;
parameter integer CLK_COR_SEQ_LEN = 1;
parameter integer RXOUTDIV2SEL = 1;
parameter integer RXPLLNDIVSEL = 8;
parameter integer RXUSRDIVISOR = 1;
parameter integer SH_CNT_MAX = 64;
parameter integer SH_INVALID_CNT_MAX = 16;
parameter integer TXOUTDIV2SEL = 1;
parameter integer TXPLLNDIVSEL = 8;
output DRDY;
output RXBUFERR;
output RXCALFAIL;
output RXCOMMADET;
output RXCYCLELIMIT;
output RXLOCK;
output RXMCLK;
output RXPCSHCLKOUT;
output RXREALIGN;
output RXRECCLK1;
output RXRECCLK2;
output RXSIGDET;
output TX1N;
output TX1P;
output TXBUFERR;
output TXCALFAIL;
output TXCYCLELIMIT;
output TXLOCK;
output TXOUTCLK1;
output TXOUTCLK2;
output TXPCSHCLKOUT;
output [15:0] DO;
output [1:0] RXLOSSOFSYNC;
output [31:0] RXCRCOUT;
output [31:0] TXCRCOUT;
output [4:0] CHBONDO;
output [5:0] RXSTATUS;
output [63:0] RXDATA;
output [7:0] RXCHARISCOMMA;
output [7:0] RXCHARISK;
output [7:0] RXDISPERR;
output [7:0] RXNOTINTABLE;
output [7:0] RXRUNDISP;
output [7:0] TXKERR;
output [7:0] TXRUNDISP;
input DCLK;
input DEN;
input DWE;
input ENCHANSYNC;
input ENMCOMMAALIGN;
input ENPCOMMAALIGN;
input GREFCLK;
input POWERDOWN;
input REFCLK1;
input REFCLK2;
input RX1N;
input RX1P;
input RXBLOCKSYNC64B66BUSE;
input RXCLKSTABLE;
input RXCOMMADETUSE;
input RXCRCCLK;
input RXCRCDATAVALID;
input RXCRCINIT;
input RXCRCINTCLK;
input RXCRCPD;
input RXCRCRESET;
input RXDEC64B66BUSE;
input RXDEC8B10BUSE;
input RXDESCRAM64B66BUSE;
input RXIGNOREBTF;
input RXPMARESET;
input RXPOLARITY;
input RXRESET;
input RXSLIDE;
input RXSYNC;
input RXUSRCLK2;
input RXUSRCLK;
input TXCLKSTABLE;
input TXCRCCLK;
input TXCRCDATAVALID;
input TXCRCINIT;
input TXCRCINTCLK;
input TXCRCPD;
input TXCRCRESET;
input TXENC64B66BUSE;
input TXENC8B10BUSE;
input TXENOOB;
input TXGEARBOX64B66BUSE;
input TXINHIBIT;
input TXPMARESET;
input TXPOLARITY;
input TXRESET;
input TXSCRAM64B66BUSE;
input TXSYNC;
input TXUSRCLK2;
input TXUSRCLK;
input [15:0] DI;
input [1:0] LOOPBACK;
input [1:0] RXDATAWIDTH;
input [1:0] RXINTDATAWIDTH;
input [1:0] TXDATAWIDTH;
input [1:0] TXINTDATAWIDTH;
input [2:0] RXCRCDATAWIDTH;
input [2:0] TXCRCDATAWIDTH;
input [4:0] CHBONDI;
input [63:0] RXCRCIN;
input [63:0] TXCRCIN;
input [63:0] TXDATA;
input [7:0] DADDR;
input [7:0] TXBYPASS8B10B;
input [7:0] TXCHARDISPMODE;
input [7:0] TXCHARDISPVAL;
input [7:0] TXCHARISK;
wire [15:0] OPEN_COMBUSOUT;
GT11 gt11_1 (
.CHBONDI (CHBONDI),
.CHBONDO (CHBONDO),
.COMBUSIN (16'b0),
.COMBUSOUT (OPEN_COMBUSOUT),
.DADDR (DADDR),
.DCLK (DCLK),
.DEN (DEN),
.DI (DI),
.DO (DO),
.DRDY (DRDY),
.DWE (DWE),
.ENCHANSYNC (ENCHANSYNC),
.ENMCOMMAALIGN (ENMCOMMAALIGN),
.ENPCOMMAALIGN (ENPCOMMAALIGN),
.GREFCLK (GREFCLK),
.LOOPBACK (LOOPBACK),
.POWERDOWN (POWERDOWN),
.REFCLK1 (REFCLK1),
.REFCLK2 (REFCLK2),
.RX1N (RX1N),
.RX1P (RX1P),
.RXBLOCKSYNC64B66BUSE (RXBLOCKSYNC64B66BUSE),
.RXBUFERR (RXBUFERR),
.RXCALFAIL (RXCALFAIL),
.RXCHARISCOMMA (RXCHARISCOMMA),
.RXCHARISK (RXCHARISK),
.RXCLKSTABLE (RXCLKSTABLE),
.RXCOMMADET (RXCOMMADET),
.RXCOMMADETUSE (RXCOMMADETUSE),
.RXCRCCLK (RXCRCCLK),
.RXCRCDATAVALID (RXCRCDATAVALID),
.RXCRCDATAWIDTH (RXCRCDATAWIDTH),
.RXCRCIN (RXCRCIN),
.RXCRCINIT (RXCRCINIT),
.RXCRCINTCLK (RXCRCINTCLK),
.RXCRCOUT (RXCRCOUT),
.RXCRCPD (RXCRCPD),
.RXCRCRESET (RXCRCRESET),
.RXCYCLELIMIT (RXCYCLELIMIT),
.RXDATA (RXDATA),
.RXDATAWIDTH (RXDATAWIDTH),
.RXDEC64B66BUSE (RXDEC64B66BUSE),
.RXDEC8B10BUSE (RXDEC8B10BUSE),
.RXDESCRAM64B66BUSE (RXDESCRAM64B66BUSE),
.RXDISPERR (RXDISPERR),
.RXIGNOREBTF (RXIGNOREBTF),
.RXINTDATAWIDTH (RXINTDATAWIDTH),
.RXLOCK (RXLOCK),
.RXLOSSOFSYNC (RXLOSSOFSYNC),
.RXMCLK (RXMCLK),
.RXNOTINTABLE (RXNOTINTABLE),
.RXPCSHCLKOUT (RXPCSHCLKOUT),
.RXPMARESET (RXPMARESET),
.RXPOLARITY (RXPOLARITY),
.RXREALIGN (RXREALIGN),
.RXRECCLK1 (RXRECCLK1),
.RXRECCLK2 (RXRECCLK2),
.RXRESET (RXRESET),
.RXRUNDISP (RXRUNDISP),
.RXSIGDET (RXSIGDET),
.RXSLIDE (RXSLIDE),
.RXSTATUS (RXSTATUS),
.RXSYNC (RXSYNC),
.RXUSRCLK (RXUSRCLK),
.RXUSRCLK2 (RXUSRCLK2),
.TX1N (TX1N),
.TX1P (TX1P),
.TXBUFERR (TXBUFERR),
.TXBYPASS8B10B (TXBYPASS8B10B),
.TXCALFAIL (TXCALFAIL),
.TXCHARDISPMODE (TXCHARDISPMODE),
.TXCHARDISPVAL (TXCHARDISPVAL),
.TXCHARISK (TXCHARISK),
.TXCLKSTABLE (TXCLKSTABLE),
.TXCRCCLK (TXCRCCLK),
.TXCRCDATAVALID (TXCRCDATAVALID),
.TXCRCDATAWIDTH (TXCRCDATAWIDTH),
.TXCRCIN (TXCRCIN),
.TXCRCINIT (TXCRCINIT),
.TXCRCINTCLK (TXCRCINTCLK),
.TXCRCOUT (TXCRCOUT),
.TXCRCPD (TXCRCPD),
.TXCRCRESET (TXCRCRESET),
.TXCYCLELIMIT (TXCYCLELIMIT),
.TXDATA (TXDATA),
.TXDATAWIDTH (TXDATAWIDTH),
.TXENC64B66BUSE (TXENC64B66BUSE),
.TXENC8B10BUSE (TXENC8B10BUSE),
.TXENOOB (TXENOOB),
.TXGEARBOX64B66BUSE (TXGEARBOX64B66BUSE),
.TXINHIBIT (TXINHIBIT),
.TXINTDATAWIDTH (TXINTDATAWIDTH),
.TXKERR (TXKERR),
.TXLOCK (TXLOCK),
.TXOUTCLK1 (TXOUTCLK1),
.TXOUTCLK2 (TXOUTCLK2),
.TXPCSHCLKOUT (TXPCSHCLKOUT),
.TXPMARESET (TXPMARESET),
.TXPOLARITY (TXPOLARITY),
.TXRESET (TXRESET),
.TXRUNDISP (TXRUNDISP),
.TXSCRAM64B66BUSE (TXSCRAM64B66BUSE),
.TXSYNC (TXSYNC),
.TXUSRCLK (TXUSRCLK),
.TXUSRCLK2 (TXUSRCLK2)
);
defparam gt11_1.ALIGN_COMMA_WORD = ALIGN_COMMA_WORD;
defparam gt11_1.BANDGAPSEL = BANDGAPSEL;
defparam gt11_1.BIASRESSEL = BIASRESSEL;
defparam gt11_1.CCCB_ARBITRATOR_DISABLE = CCCB_ARBITRATOR_DISABLE;
defparam gt11_1.CHAN_BOND_LIMIT = CHAN_BOND_LIMIT;
defparam gt11_1.CHAN_BOND_MODE = CHAN_BOND_MODE;
defparam gt11_1.CHAN_BOND_ONE_SHOT = CHAN_BOND_ONE_SHOT;
defparam gt11_1.CHAN_BOND_SEQ_1_1 = CHAN_BOND_SEQ_1_1;
defparam gt11_1.CHAN_BOND_SEQ_1_2 = CHAN_BOND_SEQ_1_2;
defparam gt11_1.CHAN_BOND_SEQ_1_3 = CHAN_BOND_SEQ_1_3;
defparam gt11_1.CHAN_BOND_SEQ_1_4 = CHAN_BOND_SEQ_1_4;
defparam gt11_1.CHAN_BOND_SEQ_1_MASK = CHAN_BOND_SEQ_1_MASK;
defparam gt11_1.CHAN_BOND_SEQ_2_1 = CHAN_BOND_SEQ_2_1;
defparam gt11_1.CHAN_BOND_SEQ_2_2 = CHAN_BOND_SEQ_2_2;
defparam gt11_1.CHAN_BOND_SEQ_2_3 = CHAN_BOND_SEQ_2_3;
defparam gt11_1.CHAN_BOND_SEQ_2_4 = CHAN_BOND_SEQ_2_4;
defparam gt11_1.CHAN_BOND_SEQ_2_MASK = CHAN_BOND_SEQ_2_MASK;
defparam gt11_1.CHAN_BOND_SEQ_2_USE = CHAN_BOND_SEQ_2_USE;
defparam gt11_1.CHAN_BOND_SEQ_LEN = CHAN_BOND_SEQ_LEN;
defparam gt11_1.CLK_CORRECT_USE = CLK_CORRECT_USE;
defparam gt11_1.CLK_COR_8B10B_DE = CLK_COR_8B10B_DE;
defparam gt11_1.CLK_COR_MAX_LAT = CLK_COR_MAX_LAT;
defparam gt11_1.CLK_COR_MIN_LAT = CLK_COR_MIN_LAT;
defparam gt11_1.CLK_COR_SEQ_1_1 = CLK_COR_SEQ_1_1;
defparam gt11_1.CLK_COR_SEQ_1_2 = CLK_COR_SEQ_1_2;
defparam gt11_1.CLK_COR_SEQ_1_3 = CLK_COR_SEQ_1_3;
defparam gt11_1.CLK_COR_SEQ_1_4 = CLK_COR_SEQ_1_4;
defparam gt11_1.CLK_COR_SEQ_1_MASK = CLK_COR_SEQ_1_MASK;
defparam gt11_1.CLK_COR_SEQ_2_1 = CLK_COR_SEQ_2_1;
defparam gt11_1.CLK_COR_SEQ_2_2 = CLK_COR_SEQ_2_2;
defparam gt11_1.CLK_COR_SEQ_2_3 = CLK_COR_SEQ_2_3;
defparam gt11_1.CLK_COR_SEQ_2_4 = CLK_COR_SEQ_2_4;
defparam gt11_1.CLK_COR_SEQ_2_MASK = CLK_COR_SEQ_2_MASK;
defparam gt11_1.CLK_COR_SEQ_2_USE = CLK_COR_SEQ_2_USE;
defparam gt11_1.CLK_COR_SEQ_DROP = CLK_COR_SEQ_DROP;
defparam gt11_1.CLK_COR_SEQ_LEN = CLK_COR_SEQ_LEN;
defparam gt11_1.COMMA32 = COMMA32;
defparam gt11_1.COMMA_10B_MASK = COMMA_10B_MASK;
defparam gt11_1.CYCLE_LIMIT_SEL = CYCLE_LIMIT_SEL;
defparam gt11_1.DCDR_FILTER = DCDR_FILTER;
defparam gt11_1.DEC_MCOMMA_DETECT = DEC_MCOMMA_DETECT;
defparam gt11_1.DEC_PCOMMA_DETECT = DEC_PCOMMA_DETECT;
defparam gt11_1.DEC_VALID_COMMA_ONLY = DEC_VALID_COMMA_ONLY;
defparam gt11_1.DIGRX_FWDCLK = DIGRX_FWDCLK;
defparam gt11_1.DIGRX_SYNC_MODE = DIGRX_SYNC_MODE;
defparam gt11_1.ENABLE_DCDR = ENABLE_DCDR;
defparam gt11_1.FDET_HYS_CAL = FDET_HYS_CAL;
defparam gt11_1.FDET_HYS_SEL = FDET_HYS_SEL;
defparam gt11_1.FDET_LCK_CAL = FDET_LCK_CAL;
defparam gt11_1.FDET_LCK_SEL = FDET_LCK_SEL;
defparam gt11_1.GT11_MODE = "SINGLE";
defparam gt11_1.IREFBIASMODE = IREFBIASMODE;
defparam gt11_1.LOOPCAL_WAIT = LOOPCAL_WAIT;
defparam gt11_1.MCOMMA_32B_VALUE = MCOMMA_32B_VALUE;
defparam gt11_1.MCOMMA_DETECT = MCOMMA_DETECT;
defparam gt11_1.OPPOSITE_SELECT = OPPOSITE_SELECT;
defparam gt11_1.PCOMMA_32B_VALUE = PCOMMA_32B_VALUE;
defparam gt11_1.PCOMMA_DETECT = PCOMMA_DETECT;
defparam gt11_1.PCS_BIT_SLIP = PCS_BIT_SLIP;
defparam gt11_1.PMACLKENABLE = PMACLKENABLE;
defparam gt11_1.PMACOREPWRENABLE = PMACOREPWRENABLE;
defparam gt11_1.PMAIREFTRIM = PMAIREFTRIM;
defparam gt11_1.PMAVBGCTRL = PMAVBGCTRL;
defparam gt11_1.PMAVREFTRIM = PMAVREFTRIM;
defparam gt11_1.PMA_BIT_SLIP = PMA_BIT_SLIP;
defparam gt11_1.POWER_ENABLE = POWER_ENABLE;
defparam gt11_1.REPEATER = REPEATER;
defparam gt11_1.RXACTST = RXACTST;
defparam gt11_1.RXAFEEQ = RXAFEEQ;
defparam gt11_1.RXAFEPD = RXAFEPD;
defparam gt11_1.RXAFETST = RXAFETST;
defparam gt11_1.RXAPD = RXAPD;
defparam gt11_1.RXAREGCTRL = RXAREGCTRL;
defparam gt11_1.RXASYNCDIVIDE = RXASYNCDIVIDE;
defparam gt11_1.RXBY_32 = RXBY_32;
defparam gt11_1.RXCDRLOS = RXCDRLOS;
defparam gt11_1.RXCLK0_FORCE_PMACLK = RXCLK0_FORCE_PMACLK;
defparam gt11_1.RXCLKMODE = RXCLKMODE;
defparam gt11_1.RXCLMODE = RXCLMODE;
defparam gt11_1.RXCMADJ = RXCMADJ;
defparam gt11_1.RXCPSEL = RXCPSEL;
defparam gt11_1.RXCPTST = RXCPTST;
defparam gt11_1.RXCRCCLOCKDOUBLE = RXCRCCLOCKDOUBLE;
defparam gt11_1.RXCRCENABLE = RXCRCENABLE;
defparam gt11_1.RXCRCINITVAL = RXCRCINITVAL;
defparam gt11_1.RXCRCINVERTGEN = RXCRCINVERTGEN;
defparam gt11_1.RXCRCSAMECLOCK = RXCRCSAMECLOCK;
defparam gt11_1.RXCTRL1 = RXCTRL1;
defparam gt11_1.RXCYCLE_LIMIT_SEL = RXCYCLE_LIMIT_SEL;
defparam gt11_1.RXDATA_SEL = RXDATA_SEL;
defparam gt11_1.RXDCCOUPLE = RXDCCOUPLE;
defparam gt11_1.RXDIGRESET = RXDIGRESET;
defparam gt11_1.RXDIGRX = RXDIGRX;
defparam gt11_1.RXEQ = RXEQ;
defparam gt11_1.RXFDCAL_CLOCK_DIVIDE = RXFDCAL_CLOCK_DIVIDE;
defparam gt11_1.RXFDET_HYS_CAL = RXFDET_HYS_CAL;
defparam gt11_1.RXFDET_HYS_SEL = RXFDET_HYS_SEL;
defparam gt11_1.RXFDET_LCK_CAL = RXFDET_LCK_CAL;
defparam gt11_1.RXFDET_LCK_SEL = RXFDET_LCK_SEL;
defparam gt11_1.RXFECONTROL1 = RXFECONTROL1;
defparam gt11_1.RXFECONTROL2 = RXFECONTROL2;
defparam gt11_1.RXFETUNE = RXFETUNE;
defparam gt11_1.RXLB = RXLB;
defparam gt11_1.RXLKADJ = RXLKADJ;
defparam gt11_1.RXLKAPD = RXLKAPD;
defparam gt11_1.RXLOOPCAL_WAIT = RXLOOPCAL_WAIT;
defparam gt11_1.RXLOOPFILT = RXLOOPFILT;
defparam gt11_1.RXMODE = RXMODE;
defparam gt11_1.RXOUTDIV2SEL = RXOUTDIV2SEL;
defparam gt11_1.RXPD = RXPD;
defparam gt11_1.RXPDDTST = RXPDDTST;
defparam gt11_1.RXPLLNDIVSEL = RXPLLNDIVSEL;
defparam gt11_1.RXPMACLKSEL = RXPMACLKSEL;
defparam gt11_1.RXRCPADJ = RXRCPADJ;
defparam gt11_1.RXRCPPD = RXRCPPD;
defparam gt11_1.RXRECCLK1_USE_SYNC = RXRECCLK1_USE_SYNC;
defparam gt11_1.RXRIBADJ = RXRIBADJ;
defparam gt11_1.RXRPDPD = RXRPDPD;
defparam gt11_1.RXRSDPD = RXRSDPD;
defparam gt11_1.RXSLOWDOWN_CAL = RXSLOWDOWN_CAL;
defparam gt11_1.RXTUNE = RXTUNE;
defparam gt11_1.RXUSRDIVISOR = RXUSRDIVISOR;
defparam gt11_1.RXVCODAC_INIT = RXVCODAC_INIT;
defparam gt11_1.RXVCO_CTRL_ENABLE = RXVCO_CTRL_ENABLE;
defparam gt11_1.RX_BUFFER_USE = RX_BUFFER_USE;
defparam gt11_1.RX_CLOCK_DIVIDER = RX_CLOCK_DIVIDER;
defparam gt11_1.SAMPLE_8X = SAMPLE_8X;
defparam gt11_1.SH_CNT_MAX = SH_CNT_MAX;
defparam gt11_1.SH_INVALID_CNT_MAX = SH_INVALID_CNT_MAX;
defparam gt11_1.SLOWDOWN_CAL = SLOWDOWN_CAL;
defparam gt11_1.TXABPMACLKSEL = TXABPMACLKSEL;
defparam gt11_1.TXAPD = TXAPD;
defparam gt11_1.TXAREFBIASSEL = TXAREFBIASSEL;
defparam gt11_1.TXASYNCDIVIDE = TXASYNCDIVIDE;
defparam gt11_1.TXCLK0_FORCE_PMACLK = TXCLK0_FORCE_PMACLK;
defparam gt11_1.TXCLKMODE = TXCLKMODE;
defparam gt11_1.TXCLMODE = TXCLMODE;
defparam gt11_1.TXCPSEL = TXCPSEL;
defparam gt11_1.TXCRCCLOCKDOUBLE = TXCRCCLOCKDOUBLE;
defparam gt11_1.TXCRCENABLE = TXCRCENABLE;
defparam gt11_1.TXCRCINITVAL = TXCRCINITVAL;
defparam gt11_1.TXCRCINVERTGEN = TXCRCINVERTGEN;
defparam gt11_1.TXCRCSAMECLOCK = TXCRCSAMECLOCK;
defparam gt11_1.TXCTRL1 = TXCTRL1;
defparam gt11_1.TXDATA_SEL = TXDATA_SEL;
defparam gt11_1.TXDAT_PRDRV_DAC = TXDAT_PRDRV_DAC;
defparam gt11_1.TXDAT_TAP_DAC = TXDAT_TAP_DAC;
defparam gt11_1.TXDIGPD = TXDIGPD;
defparam gt11_1.TXFDCAL_CLOCK_DIVIDE = TXFDCAL_CLOCK_DIVIDE;
defparam gt11_1.TXHIGHSIGNALEN = TXHIGHSIGNALEN;
defparam gt11_1.TXLOOPFILT = TXLOOPFILT;
defparam gt11_1.TXLVLSHFTPD = TXLVLSHFTPD;
defparam gt11_1.TXOUTCLK1_USE_SYNC = TXOUTCLK1_USE_SYNC;
defparam gt11_1.TXOUTDIV2SEL = TXOUTDIV2SEL;
defparam gt11_1.TXPD = TXPD;
defparam gt11_1.TXPHASESEL = TXPHASESEL;
defparam gt11_1.TXPLLNDIVSEL = TXPLLNDIVSEL;
defparam gt11_1.TXPOST_PRDRV_DAC = TXPOST_PRDRV_DAC;
defparam gt11_1.TXPOST_TAP_DAC = TXPOST_TAP_DAC;
defparam gt11_1.TXPOST_TAP_PD = TXPOST_TAP_PD;
defparam gt11_1.TXPRE_PRDRV_DAC = TXPRE_PRDRV_DAC;
defparam gt11_1.TXPRE_TAP_DAC = TXPRE_TAP_DAC;
defparam gt11_1.TXPRE_TAP_PD = TXPRE_TAP_PD;
defparam gt11_1.TXSLEWRATE = TXSLEWRATE;
defparam gt11_1.TXTERMTRIM = TXTERMTRIM;
defparam gt11_1.TXTUNE = TXTUNE;
defparam gt11_1.TX_BUFFER_USE = TX_BUFFER_USE;
defparam gt11_1.TX_CLOCK_DIVIDER = TX_CLOCK_DIVIDER;
defparam gt11_1.VCODAC_INIT = VCODAC_INIT;
defparam gt11_1.VCO_CTRL_ENABLE = VCO_CTRL_ENABLE;
defparam gt11_1.VREFBIASMODE = VREFBIASMODE;
endmodule |
module IBUF_GTLP_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_PCI33_3 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_GTLP (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR3B3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
wire i1_inv;
wire i2_inv;
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, i1_inv, i2_inv);
endmodule |
module IBUF_GTL_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module XNOR2 (O, I0, I1);
output O;
input I0, I1;
xnor X1 (O, I0, I1);
endmodule |
module PLL_BASE (
CLKFBOUT,
CLKOUT0,
CLKOUT1,
CLKOUT2,
CLKOUT3,
CLKOUT4,
CLKOUT5,
LOCKED,
CLKFBIN,
CLKIN,
RST
);
parameter BANDWIDTH = "OPTIMIZED";
parameter integer CLKFBOUT_MULT = 1;
parameter real CLKFBOUT_PHASE = 0.0;
parameter real CLKIN_PERIOD = 0.000;
parameter integer CLKOUT0_DIVIDE = 1;
parameter real CLKOUT0_DUTY_CYCLE = 0.5;
parameter real CLKOUT0_PHASE = 0.0;
parameter integer CLKOUT1_DIVIDE = 1;
parameter real CLKOUT1_DUTY_CYCLE = 0.5;
parameter real CLKOUT1_PHASE = 0.0;
parameter integer CLKOUT2_DIVIDE = 1;
parameter real CLKOUT2_DUTY_CYCLE = 0.5;
parameter real CLKOUT2_PHASE = 0.0;
parameter integer CLKOUT3_DIVIDE = 1;
parameter real CLKOUT3_DUTY_CYCLE = 0.5;
parameter real CLKOUT3_PHASE = 0.0;
parameter integer CLKOUT4_DIVIDE = 1;
parameter real CLKOUT4_DUTY_CYCLE = 0.5;
parameter real CLKOUT4_PHASE = 0.0;
parameter integer CLKOUT5_DIVIDE = 1;
parameter real CLKOUT5_DUTY_CYCLE = 0.5;
parameter real CLKOUT5_PHASE = 0.0;
parameter CLK_FEEDBACK = "CLKFBOUT";
parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
parameter integer DIVCLK_DIVIDE = 1;
parameter real REF_JITTER = 0.100;
parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
output CLKFBOUT;
output CLKOUT0;
output CLKOUT1;
output CLKOUT2;
output CLKOUT3;
output CLKOUT4;
output CLKOUT5;
output LOCKED;
input CLKFBIN;
input CLKIN;
input RST;
wire OPEN_CLKFBDCM;
wire OPEN_CLKOUTDCM0;
wire OPEN_CLKOUTDCM1;
wire OPEN_CLKOUTDCM2;
wire OPEN_CLKOUTDCM3;
wire OPEN_CLKOUTDCM4;
wire OPEN_CLKOUTDCM5;
wire OPEN_DRDY;
wire [15:0] OPEN_DO;
PLL_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT(CLKFBOUT_MULT),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN_PERIOD),
.CLKIN2_PERIOD(10.0),
.CLKOUT0_DIVIDE(CLKOUT0_DIVIDE),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLK_FEEDBACK(CLK_FEEDBACK),
.COMPENSATION(COMPENSATION),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER(REF_JITTER),
.RESET_ON_LOSS_OF_LOCK(RESET_ON_LOSS_OF_LOCK)
)
pll_adv_1 (
.CLKFBDCM (OPEN_CLKFBDCM),
.CLKFBIN (CLKFBIN),
.CLKFBOUT (CLKFBOUT),
.CLKIN1 (CLKIN),
.CLKIN2 (1'b0),
.CLKOUT0 (CLKOUT0),
.CLKOUT1 (CLKOUT1),
.CLKOUT2 (CLKOUT2),
.CLKOUT3 (CLKOUT3),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUTDCM0 (OPEN_CLKOUTDCM0),
.CLKOUTDCM1 (OPEN_CLKOUTDCM1),
.CLKOUTDCM2 (OPEN_CLKOUTDCM2),
.CLKOUTDCM3 (OPEN_CLKOUTDCM3),
.CLKOUTDCM4 (OPEN_CLKOUTDCM4),
.CLKOUTDCM5 (OPEN_CLKOUTDCM5),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DO (OPEN_DO),
.DRDY (OPEN_DRDY),
.DWE (1'b0),
.LOCKED (LOCKED),
.CLKINSEL(1'b1),
.REL (1'b0),
.RST (RST)
);
endmodule |
module XNOR5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
xnor X1 (O, I0, I1, I2, I3, I4);
endmodule |
module NAND5B5 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
wire i4_inv;
not N4 (i4_inv, I4);
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv, i4_inv);
endmodule |
module IBUF_LVCMOS33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_I (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND5B2 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv, I2, I3, I4);
endmodule |
module NAND2 (O, I0, I1);
output O;
input I0, I1;
nand A1 (O, I0, I1);
endmodule |
module RAM128X1S_1 (O, A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE);
parameter INIT = 128'h00000000000000000000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, A6, D, WCLK, WE;
reg [127:0] mem;
wire [6:0] adr;
assign adr = {A6, A5, A4, A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(negedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUF_HSTL_II_DCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module LUT2 (O, I0, I1);
parameter INIT = 4'h0;
input I0, I1;
output O;
reg O;
wire [1:0] s;
assign s = {I1, I0};
always @(s)
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
O = INIT[s];
else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2]))
O = INIT[0];
else if ((s[1] == 0) && (INIT[0] == INIT[1]))
O = INIT[0];
else if ((s[1] == 1) && (INIT[2] == INIT[3]))
O = INIT[2];
else if ((s[0] == 0) && (INIT[0] == INIT[2]))
O = INIT[0];
else if ((s[0] == 1) && (INIT[1] == INIT[3]))
O = INIT[1];
else
O = 1'bx;
endmodule |
module XNOR4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
xnor X1 (O, I0, I1, I2, I3);
endmodule |
module IBUFG_HSTL_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module MUXCY_L (LO, CI, DI, S);
output LO;
reg LO;
input CI, DI, S;
always @(CI or DI or S)
if (S)
LO = CI;
else
LO = DI;
endmodule |
module ICAP_VIRTEX4 (BUSY, O, CE, CLK, I, WRITE);
output BUSY;
output [31:0] O;
input CE, CLK, WRITE;
input [31:0] I;
parameter ICAP_WIDTH = "X8";
endmodule |
module AND2B2 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
wire i1_inv;
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
and A1 (O, i0_inv, i1_inv);
endmodule |
module LUT1_L (LO, I0);
parameter INIT = 2'h0;
input I0;
output LO;
wire LO;
assign LO = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0];
endmodule |
module IBUF_SSTL3_I_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module OR5B4 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
or O1 (O, i0_inv, i1_inv, i2_inv, i3_inv, I4);
endmodule |
module NAND4B4 (O, I0, I1, I2, I3);
output O;
input I0, I1, I2, I3;
wire i0_inv;
wire i1_inv;
wire i2_inv;
wire i3_inv;
not N3 (i3_inv, I3);
not N2 (i2_inv, I2);
not N1 (i1_inv, I1);
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, i1_inv, i2_inv, i3_inv);
endmodule |
module USR_ACCESS_VIRTEX4 (DATA, DATAVALID);
output [31:0] DATA;
output DATAVALID;
endmodule // USR_ACCESS_VIRTEX4 |
module OR3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
or O1 (O, I0, I1, I2);
endmodule |
module IBUF_LVCMOS12 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module LUT2_D (LO, O, I0, I1);
parameter INIT = 4'h0;
input I0, I1;
output LO, O;
reg O;
wire LO;
wire [1:0] s;
assign s = {I1, I0};
assign LO = O;
always @(s)
if ((s[1]^s[0] ==1) || (s[1]^s[0] ==0))
O = INIT[s];
else if ((INIT[0] == INIT[1]) && (INIT[2] == INIT[3]) && (INIT[0] == INIT[2]))
O = INIT[0];
else if ((s[1] == 0) && (INIT[0] == INIT[1]))
O = INIT[0];
else if ((s[1] == 1) && (INIT[2] == INIT[3]))
O = INIT[2];
else if ((s[0] == 0) && (INIT[0] == INIT[2]))
O = INIT[0];
else if ((s[0] == 1) && (INIT[1] == INIT[3]))
O = INIT[1];
else
O = 1'bx;
endmodule |
module SRLC16_1 (Q, Q15, A0, A1, A2, A3, CLK, D);
parameter INIT = 16'h0000;
output Q, Q15;
input A0, A1, A2, A3, CLK, D;
reg [15:0] data;
wire [3:0] addr;
wire clk_;
wire q_int;
wire q15_int;
buf b_a3 (addr[3], A3);
buf b_a2 (addr[2], A2);
buf b_a1 (addr[1], A1);
buf b_a0 (addr[0], A0);
buf b_q_int (q_int, data[addr]);
buf b_q (Q, q_int);
buf b_q15_int (q15_int, data[15]);
buf b_q15 (Q15, q15_int);
not i_c (clk_, CLK);
initial
begin
assign data = INIT;
while (clk_ === 1'b1 || clk_ ===1'bX)
#10;
deassign data;
end
always @(posedge clk_) begin
{data[15:0]} <= #100 {data[14:0], D};
end
endmodule |
module IFDDRCPE (Q0, Q1, C0, C1, CE, CLR, D, PRE);
output Q0, Q1;
input C0, C1, CE, CLR, D, PRE;
wire d_in;
IBUF I1 (.I(D),
.O(d_in));
FDCPE F0 (.C(C0),
.CE(CE),
.CLR(CLR),
.D(d_in),
.PRE(PRE),
.Q(Q0));
defparam F0.INIT = 1'b0;
FDCPE F1 (.C(C1),
.CE(CE),
.CLR(CLR),
.D(d_in),
.PRE(PRE),
.Q(Q1));
defparam F1.INIT = 1'b0;
endmodule |
module IBUFG_LVCMOS33 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module AND3 (O, I0, I1, I2);
output O;
input I0, I1, I2;
and A1 (O, I0, I1, I2);
endmodule |
module NAND5B1 (O, I0, I1, I2, I3, I4);
output O;
input I0, I1, I2, I3, I4;
wire i0_inv;
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, I1, I2, I3, I4);
endmodule |
module IBUF_LVDCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module LUT1 (O, I0);
parameter INIT = 2'h0;
input I0;
output O;
wire O;
assign O = (INIT[0] == INIT[1]) ? INIT[0] : INIT[I0];
endmodule |
module BUFGCE_1 (O, CE, I);
output O;
input CE, I;
wire NCE;
BUFGMUX_1 B1 (.I0(I),
.I1(1'b1),
.O(O),
.S(NCE));
INV I1 (.I(CE),
.O(NCE));
endmodule |
module IBUF_LVCMOS25 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_HSTL_III_DCI_18 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVDCI_DV2_25 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFDS_DIFF_OUT (O, OB, I, IB);
parameter DIFF_TERM = "FALSE";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "LVDS_25";
output O, OB;
input I, IB;
reg o_out;
buf B0 (O, o_out);
not B1 (OB, o_out);
initial begin
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUFDS_DIFF_OUT instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end
always @(I or IB) begin
if (I == 1'b1 && IB == 1'b0)
o_out <= I;
else if (I == 1'b0 && IB == 1'b1)
o_out <= I;
else if (I == 1'bx || IB == 1'bx)
o_out <= 1'bx;
end
endmodule |
module IBUFG_HSTL_IV (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module GT11CLK_MGT (
SYNCLK1OUT,
SYNCLK2OUT,
MGTCLKN,
MGTCLKP
);
parameter SYNCLK1OUTEN = "ENABLE";
parameter SYNCLK2OUTEN = "DISABLE";
output SYNCLK1OUT;
output SYNCLK2OUT;
input MGTCLKN;
input MGTCLKP;
reg [0:0] SYNCLK1OUTEN_BINARY;
reg [0:0] SYNCLK2OUTEN_BINARY;
reg mgtclk_out;
initial begin
case (SYNCLK1OUTEN)
"ENABLE" : SYNCLK1OUTEN_BINARY <= 1'b1;
"DISABLE" : SYNCLK1OUTEN_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCLK1OUTEN on GT11CLK_MGT instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK1OUTEN);
$finish;
end
endcase
case (SYNCLK2OUTEN)
"ENABLE" : SYNCLK2OUTEN_BINARY <= 1'b1;
"DISABLE" : SYNCLK2OUTEN_BINARY <= 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute SYNCLK2OUTEN on GT11CLK_MGT instance %m is set to %s. Legal values for this attribute are ENABLE or DISABLE.", SYNCLK2OUTEN);
$finish;
end
endcase
end
always @(MGTCLKN or MGTCLKP) begin
if (MGTCLKP == 1'b1 && MGTCLKN == 1'b0)
mgtclk_out <= MGTCLKP;
else if (MGTCLKP == 1'b0 && MGTCLKN == 1'b1)
mgtclk_out <= MGTCLKP;
end
bufif1 (SYNCLK1OUT, mgtclk_out, SYNCLK1OUTEN_BINARY);
bufif1 (SYNCLK2OUT, mgtclk_out, SYNCLK2OUTEN_BINARY);
endmodule |
module IBUFG_GTLP (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_LVDCI_DV2_15 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_HSTL_III_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM32X1D (DPO, SPO, A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE);
parameter INIT = 32'h00000000;
output DPO, SPO;
input A0, A1, A2, A3, A4, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, WCLK, WE;
reg [31:0] mem;
wire [4:0] adr;
assign adr = {A4, A3, A2, A1, A0};
assign SPO = mem[adr];
assign DPO = mem[{DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module DCIRESET (LOCKED, RST);
output LOCKED;
input RST;
time sample_rising, sample_falling;
always @(RST)
begin
if (RST)
sample_rising = $time;
else if (!RST)
sample_falling = $time;
if (sample_falling - sample_rising < 100000)
$display ("Timing Violation Error : The high pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
if (sample_rising - sample_falling < 100000)
$display ("Timing Violation Error : The low pulse of RST signal at time %.3f ns in DCIRESET has to be greater than 100 ns", $time/1000.0);
end // always @ (RST)
assign #(100000, 0) LOCKED = RST ? 1'b0 : 1'b1;
endmodule |
module ORCY (O, CI, I);
output O;
input CI, I;
or X1 (O, CI, I);
endmodule |
module NAND2B1 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
nand A1 (O, i0_inv, I1);
endmodule |
module IBUF_HSTL_II_DCI (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUF_LVCMOS2 (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR2B1 (O, I0, I1);
output O;
input I0, I1;
wire i0_inv;
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, I1);
endmodule |
module BUFIODQS (O, DQSMASK, I);
parameter DQSMASK_ENABLE = "FALSE"; // TRUE, FALSE
output O;
input DQSMASK;
input I;
reg delay_bypass_attr;
reg dqsmask_enable_attr;
wire o_out;
// Other signals
reg attr_err_flag = 0;
//----------------------------------------------------------------------
//------------------------ Output Ports ------------------------------
//----------------------------------------------------------------------
buf buf_o(O, o_out);
initial begin
//-------------------------------------------------
//----- DQSMASK_ENABLE Check
//-------------------------------------------------
case (DQSMASK_ENABLE)
"TRUE" : dqsmask_enable_attr <= 1'b1;
"FALSE" :dqsmask_enable_attr <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQSMASK_ENABLE on BUFIODQS instance %m is set to %s. Legal values for this attribute are TRUE or FALSE", DQSMASK_ENABLE);
attr_err_flag = 1;
end
endcase // (DQSMASK_ENABLE)
if (attr_err_flag)
begin
#1;
$finish;
end
end // initial begin
reg q1, q2;
wire clk, dglitch_en;
assign clk = (dglitch_en == 1'b1) ? I : 1'b0;
always @(DQSMASK or clk) begin
if (DQSMASK == 1'b1) q1 = 0;
else #(300) if (clk == 1) q1 = 1;
end
always @(DQSMASK or clk) begin
if (DQSMASK == 1'b1) q2 = 0;
else #(400) if (clk == 0) q2 = q1;
end
assign dglitch_en = (~q2 | DQSMASK);
assign o_out = (DQSMASK_ENABLE == "TRUE") ? clk : I;
endmodule // BUFIODQS |
module IBUFG (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
end // initial begin
endmodule |
module IBUFG_LVPECL (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module IBUFG_CTT (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module NOR3B1 (O, I0, I1, I2);
output O;
input I0, I1, I2;
wire i0_inv;
not N0 (i0_inv, I0);
nor O1 (O, i0_inv, I1, I2);
endmodule |
module EMAC (
DCRHOSTDONEIR,
EMAC0CLIENTANINTERRUPT,
EMAC0CLIENTRXBADFRAME,
EMAC0CLIENTRXCLIENTCLKOUT,
EMAC0CLIENTRXD,
EMAC0CLIENTRXDVLD,
EMAC0CLIENTRXDVLDMSW,
EMAC0CLIENTRXDVREG6,
EMAC0CLIENTRXFRAMEDROP,
EMAC0CLIENTRXGOODFRAME,
EMAC0CLIENTRXSTATS,
EMAC0CLIENTRXSTATSBYTEVLD,
EMAC0CLIENTRXSTATSVLD,
EMAC0CLIENTTXACK,
EMAC0CLIENTTXCLIENTCLKOUT,
EMAC0CLIENTTXCOLLISION,
EMAC0CLIENTTXGMIIMIICLKOUT,
EMAC0CLIENTTXRETRANSMIT,
EMAC0CLIENTTXSTATS,
EMAC0CLIENTTXSTATSBYTEVLD,
EMAC0CLIENTTXSTATSVLD,
EMAC0PHYENCOMMAALIGN,
EMAC0PHYLOOPBACKMSB,
EMAC0PHYMCLKOUT,
EMAC0PHYMDOUT,
EMAC0PHYMDTRI,
EMAC0PHYMGTRXRESET,
EMAC0PHYMGTTXRESET,
EMAC0PHYPOWERDOWN,
EMAC0PHYSYNCACQSTATUS,
EMAC0PHYTXCHARDISPMODE,
EMAC0PHYTXCHARDISPVAL,
EMAC0PHYTXCHARISK,
EMAC0PHYTXCLK,
EMAC0PHYTXD,
EMAC0PHYTXEN,
EMAC0PHYTXER,
EMAC1CLIENTANINTERRUPT,
EMAC1CLIENTRXBADFRAME,
EMAC1CLIENTRXCLIENTCLKOUT,
EMAC1CLIENTRXD,
EMAC1CLIENTRXDVLD,
EMAC1CLIENTRXDVLDMSW,
EMAC1CLIENTRXDVREG6,
EMAC1CLIENTRXFRAMEDROP,
EMAC1CLIENTRXGOODFRAME,
EMAC1CLIENTRXSTATS,
EMAC1CLIENTRXSTATSBYTEVLD,
EMAC1CLIENTRXSTATSVLD,
EMAC1CLIENTTXACK,
EMAC1CLIENTTXCLIENTCLKOUT,
EMAC1CLIENTTXCOLLISION,
EMAC1CLIENTTXGMIIMIICLKOUT,
EMAC1CLIENTTXRETRANSMIT,
EMAC1CLIENTTXSTATS,
EMAC1CLIENTTXSTATSBYTEVLD,
EMAC1CLIENTTXSTATSVLD,
EMAC1PHYENCOMMAALIGN,
EMAC1PHYLOOPBACKMSB,
EMAC1PHYMCLKOUT,
EMAC1PHYMDOUT,
EMAC1PHYMDTRI,
EMAC1PHYMGTRXRESET,
EMAC1PHYMGTTXRESET,
EMAC1PHYPOWERDOWN,
EMAC1PHYSYNCACQSTATUS,
EMAC1PHYTXCHARDISPMODE,
EMAC1PHYTXCHARDISPVAL,
EMAC1PHYTXCHARISK,
EMAC1PHYTXCLK,
EMAC1PHYTXD,
EMAC1PHYTXEN,
EMAC1PHYTXER,
EMACDCRACK,
EMACDCRDBUS,
HOSTMIIMRDY,
HOSTRDDATA,
CLIENTEMAC0DCMLOCKED,
CLIENTEMAC0PAUSEREQ,
CLIENTEMAC0PAUSEVAL,
CLIENTEMAC0RXCLIENTCLKIN,
CLIENTEMAC0TXCLIENTCLKIN,
CLIENTEMAC0TXD,
CLIENTEMAC0TXDVLD,
CLIENTEMAC0TXDVLDMSW,
CLIENTEMAC0TXFIRSTBYTE,
CLIENTEMAC0TXGMIIMIICLKIN,
CLIENTEMAC0TXIFGDELAY,
CLIENTEMAC0TXUNDERRUN,
CLIENTEMAC1DCMLOCKED,
CLIENTEMAC1PAUSEREQ,
CLIENTEMAC1PAUSEVAL,
CLIENTEMAC1RXCLIENTCLKIN,
CLIENTEMAC1TXCLIENTCLKIN,
CLIENTEMAC1TXD,
CLIENTEMAC1TXDVLD,
CLIENTEMAC1TXDVLDMSW,
CLIENTEMAC1TXFIRSTBYTE,
CLIENTEMAC1TXGMIIMIICLKIN,
CLIENTEMAC1TXIFGDELAY,
CLIENTEMAC1TXUNDERRUN,
DCREMACABUS,
DCREMACCLK,
DCREMACDBUS,
DCREMACENABLE,
DCREMACREAD,
DCREMACWRITE,
HOSTADDR,
HOSTCLK,
HOSTEMAC1SEL,
HOSTMIIMSEL,
HOSTOPCODE,
HOSTREQ,
HOSTWRDATA,
PHYEMAC0COL,
PHYEMAC0CRS,
PHYEMAC0GTXCLK,
PHYEMAC0MCLKIN,
PHYEMAC0MDIN,
PHYEMAC0MIITXCLK,
PHYEMAC0PHYAD,
PHYEMAC0RXBUFERR,
PHYEMAC0RXBUFSTATUS,
PHYEMAC0RXCHARISCOMMA,
PHYEMAC0RXCHARISK,
PHYEMAC0RXCHECKINGCRC,
PHYEMAC0RXCLK,
PHYEMAC0RXCLKCORCNT,
PHYEMAC0RXCOMMADET,
PHYEMAC0RXD,
PHYEMAC0RXDISPERR,
PHYEMAC0RXDV,
PHYEMAC0RXER,
PHYEMAC0RXLOSSOFSYNC,
PHYEMAC0RXNOTINTABLE,
PHYEMAC0RXRUNDISP,
PHYEMAC0SIGNALDET,
PHYEMAC0TXBUFERR,
PHYEMAC1COL,
PHYEMAC1CRS,
PHYEMAC1GTXCLK,
PHYEMAC1MCLKIN,
PHYEMAC1MDIN,
PHYEMAC1MIITXCLK,
PHYEMAC1PHYAD,
PHYEMAC1RXBUFERR,
PHYEMAC1RXBUFSTATUS,
PHYEMAC1RXCHARISCOMMA,
PHYEMAC1RXCHARISK,
PHYEMAC1RXCHECKINGCRC,
PHYEMAC1RXCLK,
PHYEMAC1RXCLKCORCNT,
PHYEMAC1RXCOMMADET,
PHYEMAC1RXD,
PHYEMAC1RXDISPERR,
PHYEMAC1RXDV,
PHYEMAC1RXER,
PHYEMAC1RXLOSSOFSYNC,
PHYEMAC1RXNOTINTABLE,
PHYEMAC1RXRUNDISP,
PHYEMAC1SIGNALDET,
PHYEMAC1TXBUFERR,
RESET,
TIEEMAC0CONFIGVEC,
TIEEMAC0UNICASTADDR,
TIEEMAC1CONFIGVEC,
TIEEMAC1UNICASTADDR
);
output DCRHOSTDONEIR;
output EMAC0CLIENTANINTERRUPT;
output EMAC0CLIENTRXBADFRAME;
output EMAC0CLIENTRXCLIENTCLKOUT;
output EMAC0CLIENTRXDVLD;
output EMAC0CLIENTRXDVLDMSW;
output EMAC0CLIENTRXDVREG6;
output EMAC0CLIENTRXFRAMEDROP;
output EMAC0CLIENTRXGOODFRAME;
output EMAC0CLIENTRXSTATSBYTEVLD;
output EMAC0CLIENTRXSTATSVLD;
output EMAC0CLIENTTXACK;
output EMAC0CLIENTTXCLIENTCLKOUT;
output EMAC0CLIENTTXCOLLISION;
output EMAC0CLIENTTXGMIIMIICLKOUT;
output EMAC0CLIENTTXRETRANSMIT;
output EMAC0CLIENTTXSTATS;
output EMAC0CLIENTTXSTATSBYTEVLD;
output EMAC0CLIENTTXSTATSVLD;
output EMAC0PHYENCOMMAALIGN;
output EMAC0PHYLOOPBACKMSB;
output EMAC0PHYMCLKOUT;
output EMAC0PHYMDOUT;
output EMAC0PHYMDTRI;
output EMAC0PHYMGTRXRESET;
output EMAC0PHYMGTTXRESET;
output EMAC0PHYPOWERDOWN;
output EMAC0PHYSYNCACQSTATUS;
output EMAC0PHYTXCHARDISPMODE;
output EMAC0PHYTXCHARDISPVAL;
output EMAC0PHYTXCHARISK;
output EMAC0PHYTXCLK;
output EMAC0PHYTXEN;
output EMAC0PHYTXER;
output EMAC1CLIENTANINTERRUPT;
output EMAC1CLIENTRXBADFRAME;
output EMAC1CLIENTRXCLIENTCLKOUT;
output EMAC1CLIENTRXDVLD;
output EMAC1CLIENTRXDVLDMSW;
output EMAC1CLIENTRXDVREG6;
output EMAC1CLIENTRXFRAMEDROP;
output EMAC1CLIENTRXGOODFRAME;
output EMAC1CLIENTRXSTATSBYTEVLD;
output EMAC1CLIENTRXSTATSVLD;
output EMAC1CLIENTTXACK;
output EMAC1CLIENTTXCLIENTCLKOUT;
output EMAC1CLIENTTXCOLLISION;
output EMAC1CLIENTTXGMIIMIICLKOUT;
output EMAC1CLIENTTXRETRANSMIT;
output EMAC1CLIENTTXSTATS;
output EMAC1CLIENTTXSTATSBYTEVLD;
output EMAC1CLIENTTXSTATSVLD;
output EMAC1PHYENCOMMAALIGN;
output EMAC1PHYLOOPBACKMSB;
output EMAC1PHYMCLKOUT;
output EMAC1PHYMDOUT;
output EMAC1PHYMDTRI;
output EMAC1PHYMGTRXRESET;
output EMAC1PHYMGTTXRESET;
output EMAC1PHYPOWERDOWN;
output EMAC1PHYSYNCACQSTATUS;
output EMAC1PHYTXCHARDISPMODE;
output EMAC1PHYTXCHARDISPVAL;
output EMAC1PHYTXCHARISK;
output EMAC1PHYTXCLK;
output EMAC1PHYTXEN;
output EMAC1PHYTXER;
output EMACDCRACK;
output HOSTMIIMRDY;
output [0:31] EMACDCRDBUS;
output [15:0] EMAC0CLIENTRXD;
output [15:0] EMAC1CLIENTRXD;
output [31:0] HOSTRDDATA;
output [6:0] EMAC0CLIENTRXSTATS;
output [6:0] EMAC1CLIENTRXSTATS;
output [7:0] EMAC0PHYTXD;
output [7:0] EMAC1PHYTXD;
input CLIENTEMAC0DCMLOCKED;
input CLIENTEMAC0PAUSEREQ;
input CLIENTEMAC0RXCLIENTCLKIN;
input CLIENTEMAC0TXCLIENTCLKIN;
input CLIENTEMAC0TXDVLD;
input CLIENTEMAC0TXDVLDMSW;
input CLIENTEMAC0TXFIRSTBYTE;
input CLIENTEMAC0TXGMIIMIICLKIN;
input CLIENTEMAC0TXUNDERRUN;
input CLIENTEMAC1DCMLOCKED;
input CLIENTEMAC1PAUSEREQ;
input CLIENTEMAC1RXCLIENTCLKIN;
input CLIENTEMAC1TXCLIENTCLKIN;
input CLIENTEMAC1TXDVLD;
input CLIENTEMAC1TXDVLDMSW;
input CLIENTEMAC1TXFIRSTBYTE;
input CLIENTEMAC1TXGMIIMIICLKIN;
input CLIENTEMAC1TXUNDERRUN;
input DCREMACCLK;
input DCREMACENABLE;
input DCREMACREAD;
input DCREMACWRITE;
input HOSTCLK;
input HOSTEMAC1SEL;
input HOSTMIIMSEL;
input HOSTREQ;
input PHYEMAC0COL;
input PHYEMAC0CRS;
input PHYEMAC0GTXCLK;
input PHYEMAC0MCLKIN;
input PHYEMAC0MDIN;
input PHYEMAC0MIITXCLK;
input PHYEMAC0RXBUFERR;
input PHYEMAC0RXCHARISCOMMA;
input PHYEMAC0RXCHARISK;
input PHYEMAC0RXCHECKINGCRC;
input PHYEMAC0RXCLK;
input PHYEMAC0RXCOMMADET;
input PHYEMAC0RXDISPERR;
input PHYEMAC0RXDV;
input PHYEMAC0RXER;
input PHYEMAC0RXNOTINTABLE;
input PHYEMAC0RXRUNDISP;
input PHYEMAC0SIGNALDET;
input PHYEMAC0TXBUFERR;
input PHYEMAC1COL;
input PHYEMAC1CRS;
input PHYEMAC1GTXCLK;
input PHYEMAC1MCLKIN;
input PHYEMAC1MDIN;
input PHYEMAC1MIITXCLK;
input PHYEMAC1RXBUFERR;
input PHYEMAC1RXCHARISCOMMA;
input PHYEMAC1RXCHARISK;
input PHYEMAC1RXCHECKINGCRC;
input PHYEMAC1RXCLK;
input PHYEMAC1RXCOMMADET;
input PHYEMAC1RXDISPERR;
input PHYEMAC1RXDV;
input PHYEMAC1RXER;
input PHYEMAC1RXNOTINTABLE;
input PHYEMAC1RXRUNDISP;
input PHYEMAC1SIGNALDET;
input PHYEMAC1TXBUFERR;
input RESET;
input [0:31] DCREMACDBUS;
input [15:0] CLIENTEMAC0PAUSEVAL;
input [15:0] CLIENTEMAC0TXD;
input [15:0] CLIENTEMAC1PAUSEVAL;
input [15:0] CLIENTEMAC1TXD;
input [1:0] HOSTOPCODE;
input [1:0] PHYEMAC0RXBUFSTATUS;
input [1:0] PHYEMAC0RXLOSSOFSYNC;
input [1:0] PHYEMAC1RXBUFSTATUS;
input [1:0] PHYEMAC1RXLOSSOFSYNC;
input [2:0] PHYEMAC0RXCLKCORCNT;
input [2:0] PHYEMAC1RXCLKCORCNT;
input [31:0] HOSTWRDATA;
input [47:0] TIEEMAC0UNICASTADDR;
input [47:0] TIEEMAC1UNICASTADDR;
input [4:0] PHYEMAC0PHYAD;
input [4:0] PHYEMAC1PHYAD;
input [79:0] TIEEMAC0CONFIGVEC;
input [79:0] TIEEMAC1CONFIGVEC;
input [7:0] CLIENTEMAC0TXIFGDELAY;
input [7:0] CLIENTEMAC1TXIFGDELAY;
input [7:0] PHYEMAC0RXD;
input [7:0] PHYEMAC1RXD;
input [8:9] DCREMACABUS;
input [9:0] HOSTADDR;
reg notifier;
// Delay wrapper for 16-bit client mode
wire PHYEMAC0MIITXCLK_delay;
wire [15:0] CLIENTEMAC0TXD_delay;
wire CLIENTEMAC0TXDVLD_delay;
wire CLIENTEMAC0TXDVLDMSW_delay;
wire PHYEMAC0MIITXCLK_skewed;
wire [15:0] CLIENTEMAC0TXD_client16_delay;
wire CLIENTEMAC0TXDVLD_client16_delay;
wire CLIENTEMAC0TXDVLDMSW_client16_delay;
wire PHYEMAC1MIITXCLK_delay;
wire [15:0] CLIENTEMAC1TXD_delay;
wire CLIENTEMAC1TXDVLD_delay;
wire CLIENTEMAC1TXDVLDMSW_delay;
wire PHYEMAC1MIITXCLK_skewed;
wire [15:0] CLIENTEMAC1TXD_client16_delay;
wire CLIENTEMAC1TXDVLD_client16_delay;
wire CLIENTEMAC1TXDVLDMSW_client16_delay;
localparam client_in_delay = 50;
localparam miitxclk_delay = 0;
/*Delay EMAC# client input signals in 16-bit client mode*/
// EMAC0
assign #(client_in_delay) CLIENTEMAC0TXD_delay = CLIENTEMAC0TXD;
assign #(client_in_delay) CLIENTEMAC0TXDVLD_delay = CLIENTEMAC0TXDVLD;
assign #(client_in_delay) CLIENTEMAC0TXDVLDMSW_delay = CLIENTEMAC0TXDVLDMSW;
assign CLIENTEMAC0TXD_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXD_delay : CLIENTEMAC0TXD; // CONFIGVEC[66] is 16-bit Tx client
assign CLIENTEMAC0TXDVLD_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXDVLD_delay : CLIENTEMAC0TXDVLD;
assign CLIENTEMAC0TXDVLDMSW_client16_delay = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? CLIENTEMAC0TXDVLDMSW_delay : CLIENTEMAC0TXDVLDMSW;
// EMAC1
assign #(client_in_delay) CLIENTEMAC1TXD_delay = CLIENTEMAC1TXD;
assign #(client_in_delay) CLIENTEMAC1TXDVLD_delay = CLIENTEMAC1TXDVLD;
assign #(client_in_delay) CLIENTEMAC1TXDVLDMSW_delay = CLIENTEMAC1TXDVLDMSW;
assign CLIENTEMAC1TXD_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXD_delay : CLIENTEMAC1TXD; // CONFIGVEC[66] is 16-bit Tx client
assign CLIENTEMAC1TXDVLD_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXDVLD_delay : CLIENTEMAC1TXDVLD;
assign CLIENTEMAC1TXDVLDMSW_client16_delay = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? CLIENTEMAC1TXDVLDMSW_delay : CLIENTEMAC1TXDVLDMSW;
/*Skew 125 MHz clock EMAC#MIITXCLK against 250 MHz clock in 16-bit client mode*/
assign #(miitxclk_delay) PHYEMAC0MIITXCLK_delay = PHYEMAC0MIITXCLK;
assign PHYEMAC0MIITXCLK_skewed = (TIEEMAC0CONFIGVEC[66] == 1'b1) ? PHYEMAC0MIITXCLK_delay : PHYEMAC0MIITXCLK; // In TXCLIENT16 mode
assign #(miitxclk_delay) PHYEMAC1MIITXCLK_delay = PHYEMAC1MIITXCLK;
assign PHYEMAC1MIITXCLK_skewed = (TIEEMAC1CONFIGVEC[66] == 1'b1) ? PHYEMAC1MIITXCLK_delay : PHYEMAC1MIITXCLK; // In TXCLIENT16 mode
wire dcremacclk_delay;
assign #10 dcremacclk_delay = DCREMACCLK;
EMAC_SWIFT emac_swift_1 (
.CLIENTEMAC0DCMLOCKED (CLIENTEMAC0DCMLOCKED),
.CLIENTEMAC0PAUSEREQ (CLIENTEMAC0PAUSEREQ),
.CLIENTEMAC0PAUSEVAL (CLIENTEMAC0PAUSEVAL),
.CLIENTEMAC0RXCLIENTCLKIN (CLIENTEMAC0RXCLIENTCLKIN),
.CLIENTEMAC0TXCLIENTCLKIN (CLIENTEMAC0TXCLIENTCLKIN),
.CLIENTEMAC0TXD (CLIENTEMAC0TXD_client16_delay),
.CLIENTEMAC0TXDVLD (CLIENTEMAC0TXDVLD_client16_delay),
.CLIENTEMAC0TXDVLDMSW (CLIENTEMAC0TXDVLDMSW_client16_delay),
.CLIENTEMAC0TXFIRSTBYTE (CLIENTEMAC0TXFIRSTBYTE),
.CLIENTEMAC0TXGMIIMIICLKIN (CLIENTEMAC0TXGMIIMIICLKIN),
.CLIENTEMAC0TXIFGDELAY (CLIENTEMAC0TXIFGDELAY),
.CLIENTEMAC0TXUNDERRUN (CLIENTEMAC0TXUNDERRUN),
.CLIENTEMAC1DCMLOCKED (CLIENTEMAC1DCMLOCKED),
.CLIENTEMAC1PAUSEREQ (CLIENTEMAC1PAUSEREQ),
.CLIENTEMAC1PAUSEVAL (CLIENTEMAC1PAUSEVAL),
.CLIENTEMAC1RXCLIENTCLKIN (CLIENTEMAC1RXCLIENTCLKIN),
.CLIENTEMAC1TXCLIENTCLKIN (CLIENTEMAC1TXCLIENTCLKIN),
.CLIENTEMAC1TXD (CLIENTEMAC1TXD_client16_delay),
.CLIENTEMAC1TXDVLD (CLIENTEMAC1TXDVLD_client16_delay),
.CLIENTEMAC1TXDVLDMSW (CLIENTEMAC1TXDVLDMSW_client16_delay),
.CLIENTEMAC1TXFIRSTBYTE (CLIENTEMAC1TXFIRSTBYTE),
.CLIENTEMAC1TXGMIIMIICLKIN (CLIENTEMAC1TXGMIIMIICLKIN),
.CLIENTEMAC1TXIFGDELAY (CLIENTEMAC1TXIFGDELAY),
.CLIENTEMAC1TXUNDERRUN (CLIENTEMAC1TXUNDERRUN),
.DCREMACABUS (DCREMACABUS),
.DCREMACCLK (dcremacclk_delay),
.DCREMACDBUS (DCREMACDBUS),
.DCREMACENABLE (DCREMACENABLE),
.DCREMACREAD (DCREMACREAD),
.DCREMACWRITE (DCREMACWRITE),
.DCRHOSTDONEIR (DCRHOSTDONEIR),
.EMAC0CLIENTANINTERRUPT (EMAC0CLIENTANINTERRUPT),
.EMAC0CLIENTRXBADFRAME (EMAC0CLIENTRXBADFRAME),
.EMAC0CLIENTRXCLIENTCLKOUT (EMAC0CLIENTRXCLIENTCLKOUT),
.EMAC0CLIENTRXD (EMAC0CLIENTRXD),
.EMAC0CLIENTRXDVLD (EMAC0CLIENTRXDVLD),
.EMAC0CLIENTRXDVLDMSW (EMAC0CLIENTRXDVLDMSW),
.EMAC0CLIENTRXDVREG6 (EMAC0CLIENTRXDVREG6),
.EMAC0CLIENTRXFRAMEDROP (EMAC0CLIENTRXFRAMEDROP),
.EMAC0CLIENTRXGOODFRAME (EMAC0CLIENTRXGOODFRAME),
.EMAC0CLIENTRXSTATS (EMAC0CLIENTRXSTATS),
.EMAC0CLIENTRXSTATSBYTEVLD (EMAC0CLIENTRXSTATSBYTEVLD),
.EMAC0CLIENTRXSTATSVLD (EMAC0CLIENTRXSTATSVLD),
.EMAC0CLIENTTXACK (EMAC0CLIENTTXACK),
.EMAC0CLIENTTXCLIENTCLKOUT (EMAC0CLIENTTXCLIENTCLKOUT),
.EMAC0CLIENTTXCOLLISION (EMAC0CLIENTTXCOLLISION),
.EMAC0CLIENTTXGMIIMIICLKOUT (EMAC0CLIENTTXGMIIMIICLKOUT),
.EMAC0CLIENTTXRETRANSMIT (EMAC0CLIENTTXRETRANSMIT),
.EMAC0CLIENTTXSTATS (EMAC0CLIENTTXSTATS),
.EMAC0CLIENTTXSTATSBYTEVLD (EMAC0CLIENTTXSTATSBYTEVLD),
.EMAC0CLIENTTXSTATSVLD (EMAC0CLIENTTXSTATSVLD),
.EMAC0PHYENCOMMAALIGN (EMAC0PHYENCOMMAALIGN),
.EMAC0PHYLOOPBACKMSB (EMAC0PHYLOOPBACKMSB),
.EMAC0PHYMCLKOUT (EMAC0PHYMCLKOUT),
.EMAC0PHYMDOUT (EMAC0PHYMDOUT),
.EMAC0PHYMDTRI (EMAC0PHYMDTRI),
.EMAC0PHYMGTRXRESET (EMAC0PHYMGTRXRESET),
.EMAC0PHYMGTTXRESET (EMAC0PHYMGTTXRESET),
.EMAC0PHYPOWERDOWN (EMAC0PHYPOWERDOWN),
.EMAC0PHYSYNCACQSTATUS (EMAC0PHYSYNCACQSTATUS),
.EMAC0PHYTXCHARDISPMODE (EMAC0PHYTXCHARDISPMODE),
.EMAC0PHYTXCHARDISPVAL (EMAC0PHYTXCHARDISPVAL),
.EMAC0PHYTXCHARISK (EMAC0PHYTXCHARISK),
.EMAC0PHYTXCLK (EMAC0PHYTXCLK),
.EMAC0PHYTXD (EMAC0PHYTXD),
.EMAC0PHYTXEN (EMAC0PHYTXEN),
.EMAC0PHYTXER (EMAC0PHYTXER),
.EMAC1CLIENTANINTERRUPT (EMAC1CLIENTANINTERRUPT),
.EMAC1CLIENTRXBADFRAME (EMAC1CLIENTRXBADFRAME),
.EMAC1CLIENTRXCLIENTCLKOUT (EMAC1CLIENTRXCLIENTCLKOUT),
.EMAC1CLIENTRXD (EMAC1CLIENTRXD),
.EMAC1CLIENTRXDVLD (EMAC1CLIENTRXDVLD),
.EMAC1CLIENTRXDVLDMSW (EMAC1CLIENTRXDVLDMSW),
.EMAC1CLIENTRXDVREG6 (EMAC1CLIENTRXDVREG6),
.EMAC1CLIENTRXFRAMEDROP (EMAC1CLIENTRXFRAMEDROP),
.EMAC1CLIENTRXGOODFRAME (EMAC1CLIENTRXGOODFRAME),
.EMAC1CLIENTRXSTATS (EMAC1CLIENTRXSTATS),
.EMAC1CLIENTRXSTATSBYTEVLD (EMAC1CLIENTRXSTATSBYTEVLD),
.EMAC1CLIENTRXSTATSVLD (EMAC1CLIENTRXSTATSVLD),
.EMAC1CLIENTTXACK (EMAC1CLIENTTXACK),
.EMAC1CLIENTTXCLIENTCLKOUT (EMAC1CLIENTTXCLIENTCLKOUT),
.EMAC1CLIENTTXCOLLISION (EMAC1CLIENTTXCOLLISION),
.EMAC1CLIENTTXGMIIMIICLKOUT (EMAC1CLIENTTXGMIIMIICLKOUT),
.EMAC1CLIENTTXRETRANSMIT (EMAC1CLIENTTXRETRANSMIT),
.EMAC1CLIENTTXSTATS (EMAC1CLIENTTXSTATS),
.EMAC1CLIENTTXSTATSBYTEVLD (EMAC1CLIENTTXSTATSBYTEVLD),
.EMAC1CLIENTTXSTATSVLD (EMAC1CLIENTTXSTATSVLD),
.EMAC1PHYENCOMMAALIGN (EMAC1PHYENCOMMAALIGN),
.EMAC1PHYLOOPBACKMSB (EMAC1PHYLOOPBACKMSB),
.EMAC1PHYMCLKOUT (EMAC1PHYMCLKOUT),
.EMAC1PHYMDOUT (EMAC1PHYMDOUT),
.EMAC1PHYMDTRI (EMAC1PHYMDTRI),
.EMAC1PHYMGTRXRESET (EMAC1PHYMGTRXRESET),
.EMAC1PHYMGTTXRESET (EMAC1PHYMGTTXRESET),
.EMAC1PHYPOWERDOWN (EMAC1PHYPOWERDOWN),
.EMAC1PHYSYNCACQSTATUS (EMAC1PHYSYNCACQSTATUS),
.EMAC1PHYTXCHARDISPMODE (EMAC1PHYTXCHARDISPMODE),
.EMAC1PHYTXCHARDISPVAL (EMAC1PHYTXCHARDISPVAL),
.EMAC1PHYTXCHARISK (EMAC1PHYTXCHARISK),
.EMAC1PHYTXCLK (EMAC1PHYTXCLK),
.EMAC1PHYTXD (EMAC1PHYTXD),
.EMAC1PHYTXEN (EMAC1PHYTXEN),
.EMAC1PHYTXER (EMAC1PHYTXER),
.EMACDCRACK (EMACDCRACK),
.EMACDCRDBUS (EMACDCRDBUS),
.HOSTADDR (HOSTADDR),
.HOSTCLK (HOSTCLK),
.HOSTEMAC1SEL (HOSTEMAC1SEL),
.HOSTMIIMRDY (HOSTMIIMRDY),
.HOSTMIIMSEL (HOSTMIIMSEL),
.HOSTOPCODE (HOSTOPCODE),
.HOSTRDDATA (HOSTRDDATA),
.HOSTREQ (HOSTREQ),
.HOSTWRDATA (HOSTWRDATA),
.PHYEMAC0COL (PHYEMAC0COL),
.PHYEMAC0CRS (PHYEMAC0CRS),
.PHYEMAC0GTXCLK (PHYEMAC0GTXCLK),
.PHYEMAC0MCLKIN (PHYEMAC0MCLKIN),
.PHYEMAC0MDIN (PHYEMAC0MDIN),
.PHYEMAC0MIITXCLK (PHYEMAC0MIITXCLK_skewed),
.PHYEMAC0PHYAD (PHYEMAC0PHYAD),
.PHYEMAC0RXBUFERR (PHYEMAC0RXBUFERR),
.PHYEMAC0RXBUFSTATUS (PHYEMAC0RXBUFSTATUS),
.PHYEMAC0RXCHARISCOMMA (PHYEMAC0RXCHARISCOMMA),
.PHYEMAC0RXCHARISK (PHYEMAC0RXCHARISK),
.PHYEMAC0RXCHECKINGCRC (PHYEMAC0RXCHECKINGCRC),
.PHYEMAC0RXCLK (PHYEMAC0RXCLK),
.PHYEMAC0RXCLKCORCNT (PHYEMAC0RXCLKCORCNT),
.PHYEMAC0RXCOMMADET (PHYEMAC0RXCOMMADET),
.PHYEMAC0RXD (PHYEMAC0RXD),
.PHYEMAC0RXDISPERR (PHYEMAC0RXDISPERR),
.PHYEMAC0RXDV (PHYEMAC0RXDV),
.PHYEMAC0RXER (PHYEMAC0RXER),
.PHYEMAC0RXLOSSOFSYNC (PHYEMAC0RXLOSSOFSYNC),
.PHYEMAC0RXNOTINTABLE (PHYEMAC0RXNOTINTABLE),
.PHYEMAC0RXRUNDISP (PHYEMAC0RXRUNDISP),
.PHYEMAC0SIGNALDET (PHYEMAC0SIGNALDET),
.PHYEMAC0TXBUFERR (PHYEMAC0TXBUFERR),
.PHYEMAC1COL (PHYEMAC1COL),
.PHYEMAC1CRS (PHYEMAC1CRS),
.PHYEMAC1GTXCLK (PHYEMAC1GTXCLK),
.PHYEMAC1MCLKIN (PHYEMAC1MCLKIN),
.PHYEMAC1MDIN (PHYEMAC1MDIN),
.PHYEMAC1MIITXCLK (PHYEMAC1MIITXCLK_skewed),
.PHYEMAC1PHYAD (PHYEMAC1PHYAD),
.PHYEMAC1RXBUFERR (PHYEMAC1RXBUFERR),
.PHYEMAC1RXBUFSTATUS (PHYEMAC1RXBUFSTATUS),
.PHYEMAC1RXCHARISCOMMA (PHYEMAC1RXCHARISCOMMA),
.PHYEMAC1RXCHARISK (PHYEMAC1RXCHARISK),
.PHYEMAC1RXCHECKINGCRC (PHYEMAC1RXCHECKINGCRC),
.PHYEMAC1RXCLK (PHYEMAC1RXCLK),
.PHYEMAC1RXCLKCORCNT (PHYEMAC1RXCLKCORCNT),
.PHYEMAC1RXCOMMADET (PHYEMAC1RXCOMMADET),
.PHYEMAC1RXD (PHYEMAC1RXD),
.PHYEMAC1RXDISPERR (PHYEMAC1RXDISPERR),
.PHYEMAC1RXDV (PHYEMAC1RXDV),
.PHYEMAC1RXER (PHYEMAC1RXER),
.PHYEMAC1RXLOSSOFSYNC (PHYEMAC1RXLOSSOFSYNC),
.PHYEMAC1RXNOTINTABLE (PHYEMAC1RXNOTINTABLE),
.PHYEMAC1RXRUNDISP (PHYEMAC1RXRUNDISP),
.PHYEMAC1SIGNALDET (PHYEMAC1SIGNALDET),
.PHYEMAC1TXBUFERR (PHYEMAC1TXBUFERR),
.RESET (RESET),
.TIEEMAC0CONFIGVEC (TIEEMAC0CONFIGVEC),
.TIEEMAC0UNICASTADDR (TIEEMAC0UNICASTADDR),
.TIEEMAC1CONFIGVEC (TIEEMAC1CONFIGVEC),
.TIEEMAC1UNICASTADDR (TIEEMAC1UNICASTADDR)
);
specify
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXBADFRAME) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXD) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLD) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVLDMSW) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXDVREG6) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXFRAMEDROP) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXGOODFRAME) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATS) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSBYTEVLD) = (100, 100);
(CLIENTEMAC0RXCLIENTCLKIN => EMAC0CLIENTRXSTATSVLD) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXACK) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXCOLLISION) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXRETRANSMIT) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATS) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSBYTEVLD) = (100, 100);
(CLIENTEMAC0TXCLIENTCLKIN => EMAC0CLIENTTXSTATSVLD) = (100, 100);
(CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXD) = (100, 100);
(CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXEN) = (100, 100);
(CLIENTEMAC0TXGMIIMIICLKIN => EMAC0PHYTXER) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXBADFRAME) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXD) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLD) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVLDMSW) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXDVREG6) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXFRAMEDROP) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXGOODFRAME) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATS) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSBYTEVLD) = (100, 100);
(CLIENTEMAC1RXCLIENTCLKIN => EMAC1CLIENTRXSTATSVLD) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXACK) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXCOLLISION) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXRETRANSMIT) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATS) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSBYTEVLD) = (100, 100);
(CLIENTEMAC1TXCLIENTCLKIN => EMAC1CLIENTTXSTATSVLD) = (100, 100);
(CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXD) = (100, 100);
(CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXEN) = (100, 100);
(CLIENTEMAC1TXGMIIMIICLKIN => EMAC1PHYTXER) = (100, 100);
(HOSTCLK => EMAC0PHYMCLKOUT) = (100, 100);
(HOSTCLK => EMAC0PHYMDOUT) = (100, 100);
(HOSTCLK => EMAC0PHYMDTRI) = (100, 100);
(HOSTCLK => EMAC1PHYMCLKOUT) = (100, 100);
(HOSTCLK => EMAC1PHYMDOUT) = (100, 100);
(HOSTCLK => EMAC1PHYMDTRI) = (100, 100);
(HOSTCLK => HOSTMIIMRDY) = (100, 100);
(HOSTCLK => HOSTRDDATA) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0CLIENTANINTERRUPT) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0CLIENTRXCLIENTCLKOUT) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0CLIENTTXCLIENTCLKOUT) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0CLIENTTXGMIIMIICLKOUT) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYENCOMMAALIGN) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYLOOPBACKMSB) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYMGTRXRESET) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYMGTTXRESET) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYPOWERDOWN) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYSYNCACQSTATUS) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPMODE) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYTXCHARDISPVAL) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYTXCHARISK) = (100, 100);
(PHYEMAC0GTXCLK => EMAC0PHYTXCLK) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1CLIENTANINTERRUPT) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1CLIENTRXCLIENTCLKOUT) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1CLIENTTXCLIENTCLKOUT) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1CLIENTTXGMIIMIICLKOUT) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYENCOMMAALIGN) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYLOOPBACKMSB) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYMGTRXRESET) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYMGTTXRESET) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYPOWERDOWN) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYSYNCACQSTATUS) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPMODE) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYTXCHARDISPVAL) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYTXCHARISK) = (100, 100);
(PHYEMAC1GTXCLK => EMAC1PHYTXCLK) = (100, 100);
specparam PATHPULSE$ = 0;
endspecify
endmodule |
module RAM64X1S_1 (O, A0, A1, A2, A3, A4, A5, D, WCLK, WE);
parameter INIT = 64'h0000000000000000;
output O;
input A0, A1, A2, A3, A4, A5, D, WCLK, WE;
reg [63:0] mem;
wire [5:0] adr;
assign adr = {A5, A4, A3, A2, A1, A0};
assign O = mem[adr];
initial
mem = INIT;
always @(negedge WCLK)
if (WE == 1'b1)
mem[adr] <= #100 D;
endmodule |
module IBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
output O;
input I;
buf B1 (O, I);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on IBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
$finish;
end
endcase
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on IBUF instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE);
$finish;
end
endcase
end
endmodule |
module BUFG (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
module RAM128X1D (DPO, SPO, A, D, DPRA, WCLK, WE);
parameter INIT = 128'h0;
output DPO, SPO;
input [6:0] A;
input [6:0] DPRA;
input D;
input WCLK;
input WE;
reg [127:0] mem;
assign SPO = mem[A];
assign DPO = mem[DPRA];
initial
mem = INIT;
always @(posedge WCLK)
if (WE == 1'b1)
mem[A] <= #100 D;
endmodule |
module BUFGP (O, I);
output O;
input I;
buf B1 (O, I);
endmodule |
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