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module mc_top(clk_i, rst_i,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
susp_req_i, resume_req_i, suspended_o, poc_o,
mc_clk_i, mc_br_pad_i, mc_bg_pad_o, mc_ack_pad_i,
mc_addr_pad_o, mc_data_pad_i, mc_data_pad_o, mc_dp_pad_i,
mc_dp_pad_o, mc_doe_pad_doe_o, mc_dqm_pad_o, mc_oe_pad_o_,
mc_we_pad_o_, mc_cas_pad_o_, mc_ras_pad_o_, mc_cke_pad_o_,
mc_cs_pad_o_, mc_sts_pad_i, mc_rp_pad_o_, mc_vpen_pad_o,
mc_adsc_pad_o_, mc_adv_pad_o_, mc_zz_pad_o, mc_coe_pad_coe_o
);
input clk_i, rst_i;
// --------------------------------------
// WISHBONE SLAVE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// --------------------------------------
// Suspend Resume Interface
input susp_req_i;
input resume_req_i;
output suspended_o;
// POC
output [31:0] poc_o;
// --------------------------------------
// Memory Bus Signals
input mc_clk_i;
input mc_br_pad_i;
output mc_bg_pad_o;
input mc_ack_pad_i;
output [23:0] mc_addr_pad_o;
input [31:0] mc_data_pad_i;
output [31:0] mc_data_pad_o;
input [3:0] mc_dp_pad_i;
output [3:0] mc_dp_pad_o;
output mc_doe_pad_doe_o;
output [3:0] mc_dqm_pad_o;
output mc_oe_pad_o_;
output mc_we_pad_o_;
output mc_cas_pad_o_;
output mc_ras_pad_o_;
output mc_cke_pad_o_;
output [7:0] mc_cs_pad_o_;
input mc_sts_pad_i;
output mc_rp_pad_o_;
output mc_vpen_pad_o;
output mc_adsc_pad_o_;
output mc_adv_pad_o_;
output mc_zz_pad_o;
output mc_coe_pad_coe_o;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
// WISHBONE Interface Interconnects
wire wb_read_go;
wire wb_write_go;
wire wb_first;
wire wb_wait;
wire mem_ack;
// Suspend Resume Interface
wire susp_sel;
// Register File Interconnects
wire [31:0] rf_dout;
wire [31:0] csc;
wire [31:0] tms;
wire [31:0] sp_csc;
wire [31:0] sp_tms;
wire [7:0] cs;
wire fs;
wire cs_le;
wire [7:0] cs_need_rfr;
wire [2:0] ref_int;
wire [31:0] mem_dout;
wire wp_err;
// Address Select Signals
wire [12:0] row_adr;
wire [1:0] bank_adr;
wire cmd_a10;
wire row_sel;
wire next_adr;
wire [10:0] page_size;
wire lmr_sel;
wire wr_hold;
// OBCT Signals
wire bank_set;
wire bank_clr;
wire bank_clr_all;
wire bank_open;
wire row_same;
wire [7:0] obct_cs;
wire any_bank_open;
// Data path Controller Signals
wire dv;
wire pack_le0, pack_le1, pack_le2; // Pack Latch Enable
wire par_err;
wire [31:0] mc_data_od;
wire [3:0] mc_dp_od;
wire [23:0] mc_addr_d;
wire [35:0] mc_data_ir;
// Refresh Counter Signals
wire rfr_req;
wire rfr_ack;
wire [7:0] rfr_ps_val;
// Memory Timing Block Signals
wire data_oe;
wire oe_;
wire we_;
wire cas_;
wire ras_;
wire cke_;
wire lmr_req;
wire lmr_ack;
wire init_req;
wire init_ack;
wire [7:0] spec_req_cs;
wire cs_en;
wire wb_cycle, wr_cycle;
wire [31:0] tms_s;
wire [31:0] csc_s;
wire mc_c_oe_d;
wire mc_br_r;
wire mc_bg_d;
wire mc_adsc_d;
wire mc_adv_d;
wire mc_ack_r;
wire err;
wire mc_sts_i;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign obct_cs = (rfr_ack | susp_sel) ? cs_need_rfr :
(lmr_ack | init_ack) ? spec_req_cs : cs;
assign lmr_sel = lmr_ack | init_ack;
assign tms_s = lmr_sel ? sp_tms : tms;
assign csc_s = lmr_sel ? sp_csc : csc;
wire not_mem_cyc;
assign not_mem_cyc = wb_cyc_i & wb_stb_i & !( `MC_MEM_SEL );
reg mem_ack_r;
always @(posedge clk_i)
mem_ack_r <= #1 mem_ack;
////////////////////////////////////////////////////////////////////
//
// Modules
//
mc_rf u0(
.clk( clk_i ),
.rst( rst_i ),
.wb_data_i( wb_data_i ),
.rf_dout( rf_dout ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( ),
.wp_err( wp_err ),
.csc( csc ),
.tms( tms ),
.poc( poc_o ),
.sp_csc( sp_csc ),
.sp_tms( sp_tms ),
.cs( cs ),
.mc_data_i( mc_data_ir[31:0]),
.mc_sts( mc_sts_ir ),
.mc_vpen( mc_vpen_pad_o ),
.fs( fs ),
.cs_le( cs_le ),
.cs_le_d( cs_le_d ),
.cs_need_rfr( cs_need_rfr ),
.ref_int( ref_int ),
.rfr_ps_val( rfr_ps_val ),
.spec_req_cs( spec_req_cs ),
.init_req( init_req ),
.init_ack( init_ack ),
.lmr_req( lmr_req ),
.lmr_ack( lmr_ack )
);
mc_adr_sel u1(
.clk( clk_i ),
.csc( csc_s ),
.tms( tms_s ),
.wb_stb_i( wb_stb_i ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_addr_i( wb_addr_i ),
.wb_we_i( wb_we_i ),
.wb_write_go( wb_write_go ),
.wr_hold( wr_hold ),
.cas_( cas_ ),
.mc_addr( mc_addr_d ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.rfr_ack( rfr_ack ),
.cs_le( cs_le ),
.cmd_a10( cmd_a10 ),
.row_sel( row_sel ),
.lmr_sel( lmr_sel ),
.next_adr( next_adr ),
.wr_cycle( wr_cycle ),
.page_size( page_size )
);
mc_obct_top u2(
.clk( clk_i ),
.rst( rst_i ),
.cs( obct_cs ),
.row_adr( row_adr ),
.bank_adr( bank_adr ),
.bank_set( bank_set ),
.bank_clr( bank_clr ),
.bank_clr_all( bank_clr_all ),
.bank_open( bank_open ),
.any_bank_open( any_bank_open ),
.row_same( row_same ),
.rfr_ack( rfr_ack )
);
mc_dp u3(
.clk( clk_i ),
.rst( rst_i ),
.csc( csc ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.mem_ack( mem_ack ),
//.wb_ack_o( wb_ack_o ),
.wb_ack_o( mem_ack_r ),
.wb_we_i( wb_we_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( mem_dout ),
.wb_read_go( wb_read_go ),
.mc_clk( mc_clk_i ),
.mc_data_del( mc_data_ir ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_o( mc_data_od ),
.mc_dp_o( mc_dp_od ),
.dv( dv ),
.pack_le0( pack_le0 ),
.pack_le1( pack_le1 ),
.pack_le2( pack_le2 ),
.byte_en( wb_sel_i ),
.par_err( par_err )
);
mc_refresh u4(
.clk( clk_i ),
.rst( rst_i ),
.cs_need_rfr( cs_need_rfr ),
.ref_int( ref_int ),
.rfr_req( rfr_req ),
.rfr_ack( rfr_ack ),
.rfr_ps_val( rfr_ps_val )
);
mc_timing u5(
.clk( clk_i ),
.mc_clk( mc_clk_i ),
.rst( rst_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_we_i( wb_we_i ),
.wb_read_go( wb_read_go ),
.wb_write_go( wb_write_go ),
.wb_first( wb_first ),
.wb_wait( wb_wait ),
.mem_ack( mem_ack ),
.err( err ),
.susp_req( susp_req_i ),
.resume_req( resume_req_i ),
.suspended( suspended_o ),
.susp_sel( susp_sel ),
.mc_br( mc_br_r ),
.mc_bg( mc_bg_d ),
.mc_ack( mc_ack_r ),
.not_mem_cyc( not_mem_cyc ),
.data_oe( data_oe ),
.oe_( oe_ ),
.we_( we_ ),
.cas_( cas_ ),
.ras_( ras_ ),
.cke_( cke_ ),
.cs_en( cs_en ),
.mc_adsc( mc_adsc_d ),
.mc_adv( mc_adv_d ),
.mc_c_oe( mc_c_oe_d ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle ),
.csc( csc_s ),
.tms( tms_s ),
.cs( obct_cs ),
.lmr_req( lmr_req ),
.lmr_ack( lmr_ack ),
.cs_le( cs_le ),
.cs_le_d( cs_le_d ),
.cmd_a10( cmd_a10 ),
.row_sel( row_sel ),
.next_adr( next_adr ),
.page_size( page_size ),
.bank_set( bank_set ),
.bank_clr( bank_clr ),
.bank_clr_all( bank_clr_all ),
.bank_open( bank_open ),
.any_bank_open( any_bank_open ),
.row_same( row_same ),
.dv( dv ),
.pack_le0( pack_le0 ),
.pack_le1( pack_le1 ),
.pack_le2( pack_le2 ),
.par_err( par_err ),
.rfr_req( rfr_req ),
.rfr_ack( rfr_ack ),
.init_req( init_req ),
.init_ack( init_ack )
);
mc_wb_if u6(
.clk( clk_i ),
.rst( rst_i ),
.wb_addr_i( wb_addr_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_we_i( wb_we_i ),
.wb_ack_o( wb_ack_o ),
.wb_err( wb_err_o ),
.wb_read_go( wb_read_go ),
.wb_write_go( wb_write_go ),
.wb_first( wb_first ),
.wb_wait( wb_wait ),
.mem_ack( mem_ack ),
.wr_hold( wr_hold ),
.err( err ),
.par_err( par_err ),
.wp_err( wp_err ),
.wb_data_o( wb_data_o ),
.mem_dout( mem_dout ),
.rf_dout( rf_dout )
);
mc_mem_if u7(
.clk( clk_i ),
.rst( rst_i ),
.mc_rp( mc_rp_pad_o_ ),
.mc_clk( mc_clk_i ),
.mc_br( mc_br_pad_i ),
.mc_bg( mc_bg_pad_o ),
.mc_addr( mc_addr_pad_o ),
.mc_data_o( mc_data_pad_o ),
.mc_dp_o( mc_dp_pad_o ),
.mc_data_oe( mc_doe_pad_doe_o),
.mc_dqm( mc_dqm_pad_o ),
.mc_oe_( mc_oe_pad_o_ ),
.mc_we_( mc_we_pad_o_ ),
.mc_cas_( mc_cas_pad_o_ ),
.mc_ras_( mc_ras_pad_o_ ),
.mc_cke_( mc_cke_pad_o_ ),
.mc_cs_( mc_cs_pad_o_ ),
.mc_adsc_( mc_adsc_pad_o_ ),
.mc_adv_( mc_adv_pad_o_ ),
.mc_br_r( mc_br_r ),
.mc_bg_d( mc_bg_d ),
.mc_data_od( mc_data_od ),
.mc_dp_od( mc_dp_od ),
.mc_addr_d( mc_addr_d ),
.mc_ack( mc_ack_pad_i ),
.mc_zz_o( mc_zz_pad_o ),
.we_( we_ ),
.ras_( ras_ ),
.cas_( cas_ ),
.cke_( cke_ ),
.mc_adsc_d( mc_adsc_d ),
.mc_adv_d( mc_adv_d ),
.cs_en( cs_en ),
.rfr_ack( rfr_ack ),
.cs_need_rfr( cs_need_rfr ),
.lmr_sel( lmr_sel ),
.spec_req_cs( spec_req_cs ),
.cs( cs ),
.fs( fs ),
.data_oe( data_oe ),
.susp_sel( susp_sel ),
.suspended_o( suspended_o ),
.mc_c_oe( mc_coe_pad_coe_o),
.mc_c_oe_d( mc_c_oe_d ),
.mc_ack_r( mc_ack_r ),
.oe_( oe_ ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_sel_i( wb_sel_i ),
.wb_cycle( wb_cycle ),
.wr_cycle( wr_cycle ),
.mc_data_i( mc_data_pad_i ),
.mc_dp_i( mc_dp_pad_i ),
.mc_data_ir( mc_data_ir ),
.mc_sts_i( mc_sts_pad_i ),
.mc_sts_ir( mc_sts_ir )
);
endmodule |
module mc_mem_if(clk, rst, mc_clk, mc_br, mc_bg,
mc_addr, mc_data_o, mc_dp_o, mc_data_oe,
mc_dqm, mc_oe_, mc_we_, mc_cas_, mc_ras_, mc_cke_, mc_cs_,
mc_adsc_, mc_adv_, mc_ack, mc_rp, mc_c_oe, mc_c_oe_d,
mc_br_r, mc_bg_d, mc_data_od, mc_dp_od, mc_addr_d, mc_ack_r,
we_, ras_, cas_, cke_, mc_adsc_d, mc_adv_d, cs_en, rfr_ack,
cs_need_rfr, lmr_sel, spec_req_cs, cs, fs, data_oe, susp_sel,
suspended_o, oe_, wb_cyc_i, wb_stb_i, wb_sel_i, wb_cycle,
wr_cycle, mc_data_ir, mc_data_i, mc_dp_i, mc_sts_ir, mc_sts_i,
mc_zz_o
);
// Memory Interface
input clk;
input rst;
input mc_clk;
input mc_br;
output mc_bg;
output [23:0] mc_addr;
output [31:0] mc_data_o;
output [3:0] mc_dp_o;
output mc_data_oe;
output [3:0] mc_dqm;
output mc_oe_;
output mc_we_;
output mc_cas_;
output mc_ras_;
output mc_cke_;
output [7:0] mc_cs_;
output mc_adsc_;
output mc_adv_;
input mc_ack;
output mc_rp;
output mc_c_oe;
output [35:0] mc_data_ir;
output mc_sts_ir;
output mc_zz_o;
// Internal Interface
output mc_br_r;
input mc_bg_d;
input data_oe;
input susp_sel;
input suspended_o;
input [31:0] mc_data_od;
input [3:0] mc_dp_od;
input [23:0] mc_addr_d;
output mc_ack_r;
input wb_cyc_i;
input wb_stb_i;
input [3:0] wb_sel_i;
input wb_cycle;
input wr_cycle;
input oe_ ;
input we_;
input ras_;
input cas_;
input cke_;
input cs_en;
input rfr_ack;
input [7:0] cs_need_rfr;
input lmr_sel;
input [7:0] spec_req_cs;
input [7:0] cs;
input fs;
input mc_adsc_d;
input mc_adv_d;
input mc_c_oe_d;
input [31:0] mc_data_i;
input [3:0] mc_dp_i;
input mc_sts_i;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg mc_data_oe;
reg [31:0] mc_data_o;
reg [3:0] mc_dp_o;
reg [3:0] mc_dqm;
reg [3:0] mc_dqm_r;
reg [23:0] mc_addr;
reg mc_oe_;
reg mc_we_;
reg mc_cas_;
reg mc_ras_;
wire mc_cke_;
reg [7:0] mc_cs_;
reg mc_bg;
reg mc_adsc_;
reg mc_adv_;
reg mc_br_r;
reg mc_ack_r;
reg mc_rp;
reg mc_c_oe;
reg mc_zz_o;
reg [35:0] mc_data_ir;
reg mc_sts_ir;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge mc_clk)
mc_zz_o <= #1 suspended_o;
always @(posedge mc_clk)
mc_sts_ir <= #1 mc_sts_i;
always @(posedge mc_clk)
mc_data_ir <= #1 {mc_dp_i, mc_data_i};
always @(posedge mc_clk)
mc_c_oe <= #1 mc_c_oe_d;
always @(posedge mc_clk)
mc_rp <= #1 !suspended_o & !fs;
always @(posedge mc_clk)
mc_br_r <= #1 mc_br;
always @(posedge mc_clk)
mc_ack_r <= #1 mc_ack;
always @(posedge mc_clk)
mc_bg <= #1 mc_bg_d;
always @(posedge mc_clk or posedge rst)
if(rst) mc_data_oe <= #1 1'b0;
else mc_data_oe <= #1 data_oe & !susp_sel & mc_c_oe_d;
always @(posedge mc_clk)
mc_data_o <= #1 mc_data_od;
always @(posedge mc_clk)
mc_dp_o <= #1 mc_dp_od;
always @(posedge mc_clk)
mc_addr <= #1 mc_addr_d;
always @(posedge clk)
if(wb_cyc_i & wb_stb_i)
mc_dqm_r <= #1 wb_sel_i;
reg [3:0] mc_dqm_r2;
always @(posedge clk)
mc_dqm_r2 <= #1 mc_dqm_r;
always @(posedge mc_clk)
mc_dqm <= #1 susp_sel ? 4'hf :
data_oe ? ~mc_dqm_r2 :
(wb_cycle & !wr_cycle) ? 4'h0 : 4'hf;
always @(posedge mc_clk or posedge rst)
if(rst) mc_oe_ <= #1 1'b1;
else mc_oe_ <= #1 oe_ | susp_sel;
always @(posedge mc_clk)
mc_we_ <= #1 we_;
always @(posedge mc_clk)
mc_cas_ <= #1 cas_;
always @(posedge mc_clk)
mc_ras_ <= #1 ras_;
assign mc_cke_ = cke_;
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[0] <= #1 1'b1;
else
mc_cs_[0] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[0] :
lmr_sel ? spec_req_cs[0] :
cs[0]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[1] <= #1 1'b1;
else
mc_cs_[1] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[1] :
lmr_sel ? spec_req_cs[1] :
cs[1]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[2] <= #1 1'b1;
else
mc_cs_[2] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[2] :
lmr_sel ? spec_req_cs[2] :
cs[2]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[3] <= #1 1'b1;
else
mc_cs_[3] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[3] :
lmr_sel ? spec_req_cs[3] :
cs[3]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[4] <= #1 1'b1;
else
mc_cs_[4] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[4] :
lmr_sel ? spec_req_cs[4] :
cs[4]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[5] <= #1 1'b1;
else
mc_cs_[5] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[5] :
lmr_sel ? spec_req_cs[5] :
cs[5]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[6] <= #1 1'b1;
else
mc_cs_[6] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[6] :
lmr_sel ? spec_req_cs[6] :
cs[6]
));
always @(posedge mc_clk or posedge rst)
if(rst) mc_cs_[7] <= #1 1'b1;
else
mc_cs_[7] <= #1 ~(cs_en & (
(rfr_ack | susp_sel) ? cs_need_rfr[7] :
lmr_sel ? spec_req_cs[7] :
cs[7]
));
always @(posedge mc_clk)
mc_adsc_ <= #1 ~mc_adsc_d;
always @(posedge mc_clk)
mc_adv_ <= #1 ~mc_adv_d;
endmodule |
module mc_refresh(clk, rst,
cs_need_rfr, ref_int, rfr_req, rfr_ack,
rfr_ps_val
);
input clk, rst;
input [7:0] cs_need_rfr;
input [2:0] ref_int;
output rfr_req;
input rfr_ack;
input [7:0] rfr_ps_val;
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
reg rfr_en;
reg [7:0] ps_cnt;
wire ps_cnt_clr;
reg rfr_ce;
reg [7:0] rfr_cnt;
reg rfr_clr;
reg rfr_req;
reg rfr_early;
/*
Refresh generation
The prescaler generates a 0.48828 uS clock enable
The refresh counter generates the following refresh rates:
(Actual values are about 0.63% below the desired values).
This is for a 200 Mhz WISHBONE Bus.
0.970 uS,
1.940
3.880
7.760
15.520
32.040
62.080
124.160 uS
(desired values)
0.976 uS
1.953
3.906
7.812
15.625
31.250
62.500
125.000 uS
*/
////////////////////////////////////////////////////////////////////
//
// Prescaler
//
always @(posedge clk or posedge rst)
if(rst) rfr_en <= #1 1'b0;
else rfr_en <= #1 |cs_need_rfr;
always @(posedge clk or posedge rst)
if(rst) ps_cnt <= #1 8'h0;
else
if(ps_cnt_clr) ps_cnt <= #1 8'h0;
else
if(rfr_en) ps_cnt <= #1 ps_cnt + 8'h1;
assign ps_cnt_clr = (ps_cnt == rfr_ps_val) & (rfr_ps_val != 8'h0);
always @(posedge clk or posedge rst)
if(rst) rfr_early <= #1 1'b0;
else rfr_early <= #1 (ps_cnt == rfr_ps_val);
////////////////////////////////////////////////////////////////////
//
// Refresh Counter
//
always @(posedge clk or posedge rst)
if(rst) rfr_ce <= #1 1'b0;
else rfr_ce <= #1 ps_cnt_clr;
always @(posedge clk or posedge rst)
if(rst) rfr_cnt <= #1 8'h0;
else
if(rfr_ack) rfr_cnt <= #1 8'h0;
else
if(rfr_ce) rfr_cnt <= #1 rfr_cnt + 8'h1;
always @(posedge clk)
case(ref_int) // synopsys full_case parallel_case
3'h0: rfr_clr <= #1 rfr_cnt[0] & rfr_early;
3'h1: rfr_clr <= #1 &rfr_cnt[1:0] & rfr_early;
3'h2: rfr_clr <= #1 &rfr_cnt[2:0] & rfr_early;
3'h3: rfr_clr <= #1 &rfr_cnt[3:0] & rfr_early;
3'h4: rfr_clr <= #1 &rfr_cnt[4:0] & rfr_early;
3'h5: rfr_clr <= #1 &rfr_cnt[5:0] & rfr_early;
3'h6: rfr_clr <= #1 &rfr_cnt[6:0] & rfr_early;
3'h7: rfr_clr <= #1 &rfr_cnt[7:0] & rfr_early;
endcase
always @(posedge clk or posedge rst)
if(rst) rfr_req <= #1 1'b0;
else
if(rfr_ack) rfr_req <= #1 1'b0;
else
if(rfr_clr) rfr_req <= #1 1'b1;
endmodule |
module mc_rd_fifo(clk, rst, clr, din, we, dout, re);
input clk, rst, clr;
input [35:0] din;
input we;
output [35:0] dout;
input re;
reg [3:0] rd_adr, wr_adr;
reg [35:0] r0, r1, r2, r3;
reg [35:0] dout;
always @(posedge clk or posedge rst)
if(rst) rd_adr <= #1 4'h1;
else
if(clr) rd_adr <= #1 4'h1;
else
if(re) rd_adr <= #1 {rd_adr[2:0], rd_adr[3]};
always @(posedge clk or posedge rst)
if(rst) wr_adr <= #1 4'h1;
else
if(clr) wr_adr <= #1 4'h1;
else
if(we) wr_adr <= #1 {wr_adr[2:0], wr_adr[3]};
always @(posedge clk)
if(we & wr_adr[0]) r0 <= #1 din;
always @(posedge clk)
if(we & wr_adr[1]) r1 <= #1 din;
always @(posedge clk)
if(we & wr_adr[2]) r2 <= #1 din;
always @(posedge clk)
if(we & wr_adr[3]) r3 <= #1 din;
always @(rd_adr or r0 or r1 or r2 or r3 or re or we or din)
case(rd_adr) // synopsys full_case parallel_case
4'h1: dout = r0;
4'h2: dout = r1;
4'h4: dout = r2;
4'h8: dout = r3;
endcase
endmodule |
module mc_rf(clk, rst,
wb_data_i, rf_dout, wb_addr_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wp_err,
csc, tms, poc,
sp_csc, sp_tms, cs,
mc_data_i, mc_sts, mc_vpen, fs,
cs_le_d, cs_le, cs_need_rfr, ref_int, rfr_ps_val, init_req,
init_ack, lmr_req, lmr_ack,
spec_req_cs
);
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
// Slave Interface
input [31:0] wb_data_i;
output [31:0] rf_dout;
input [31:0] wb_addr_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wp_err;
// --------------------------------------
// Misc Signals
output [31:0] csc;
output [31:0] tms;
output [31:0] poc;
output [31:0] sp_csc;
output [31:0] sp_tms;
output [7:0] cs;
input [31:0] mc_data_i;
input mc_sts;
output mc_vpen;
output fs;
input cs_le_d;
input cs_le;
output [7:0] cs_need_rfr; // Indicates which chip selects have SDRAM
// attached and need to be refreshed
output [2:0] ref_int; // Refresh Interval
output [7:0] rfr_ps_val;
output init_req;
input init_ack;
output lmr_req;
input lmr_ack;
output [7:0] spec_req_cs;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg wb_ack_o;
reg [31:0] csc;
reg [31:0] tms;
reg [31:0] sp_csc;
reg [31:0] sp_tms;
reg [31:0] rf_dout;
reg [7:0] cs;
reg rf_we;
wire [31:0] csr;
reg [10:0] csr_r;
reg [7:0] csr_r2;
reg [31:0] poc;
wire [31:0] csc_mask;
reg [10:0] csc_mask_r;
wire [31:0] csc0, tms0;
wire [31:0] csc1, tms1;
wire [31:0] csc2, tms2;
wire [31:0] csc3, tms3;
wire [31:0] csc4, tms4;
wire [31:0] csc5, tms5;
wire [31:0] csc6, tms6;
wire [31:0] csc7, tms7;
wire cs0, cs1, cs2, cs3;
wire cs4, cs5, cs6, cs7;
wire wp_err0, wp_err1, wp_err2, wp_err3;
wire wp_err4, wp_err5, wp_err6, wp_err7;
reg wp_err;
wire lmr_req7, lmr_req6, lmr_req5, lmr_req4;
wire lmr_req3, lmr_req2, lmr_req1, lmr_req0;
wire lmr_ack7, lmr_ack6, lmr_ack5, lmr_ack4;
wire lmr_ack3, lmr_ack2, lmr_ack1, lmr_ack0;
wire init_req7, init_req6, init_req5, init_req4;
wire init_req3, init_req2, init_req1, init_req0;
wire init_ack7, init_ack6, init_ack5, init_ack4;
wire init_ack3, init_ack2, init_ack1, init_ack0;
reg init_ack_r;
wire init_ack_fe;
reg lmr_ack_r;
wire lmr_ack_fe;
wire [7:0] spec_req_cs_t;
wire [7:0] spec_req_cs_d;
reg [7:0] spec_req_cs;
reg init_req, lmr_req;
reg sreq_cs_le;
// Aliases
assign csr = {csr_r2, 8'h0, 5'h0, csr_r};
assign csc_mask = {21'h0, csc_mask_r};
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Read logic
//
always @(wb_addr_i or csr or poc or csc_mask or csc0 or tms0 or csc1 or
tms1 or csc2 or tms2 or csc3 or tms3 or csc4 or tms4 or csc5 or
tms5 or csc6 or tms6 or csc7 or tms7)
case(wb_addr_i[6:2]) // synopsys full_case parallel_case
5'h00: rf_dout <= #1 csr;
5'h01: rf_dout <= #1 poc;
5'h02: rf_dout <= #1 csc_mask;
5'h04: rf_dout <= #1 csc0;
5'h05: rf_dout <= #1 tms0;
5'h06: rf_dout <= #1 csc1;
5'h07: rf_dout <= #1 tms1;
5'h08: rf_dout <= #1 csc2;
5'h09: rf_dout <= #1 tms2;
5'h0a: rf_dout <= #1 csc3;
5'h0b: rf_dout <= #1 tms3;
5'h0c: rf_dout <= #1 csc4;
5'h0d: rf_dout <= #1 tms4;
5'h0e: rf_dout <= #1 csc5;
5'h0f: rf_dout <= #1 tms5;
5'h10: rf_dout <= #1 csc6;
5'h11: rf_dout <= #1 tms6;
5'h12: rf_dout <= #1 csc7;
5'h13: rf_dout <= #1 tms7;
endcase
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Write logic
//
reg [6:0] wb_addr_r;
always @(posedge clk)
wb_addr_r <= #1 wb_addr_i[6:0];
always @(posedge clk or posedge rst)
if(rst) rf_we <= #1 1'b0;
else rf_we <= #1 `MC_REG_SEL & wb_we_i & wb_cyc_i & wb_stb_i & !rf_we;
always @(posedge clk or posedge rst)
if(rst) csr_r2 <= #1 8'h0;
else
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r2 <= #1 wb_data_i[31:24];
always @(posedge clk or posedge rst)
if(rst) csr_r[10:1] <= #1 10'h0;
else
if(rf_we & (wb_addr_r[6:2] == 5'h0) )
csr_r[10:1] <= #1 wb_data_i[10:1];
always @(posedge clk)
csr_r[0] <= #1 mc_sts;
assign mc_vpen = csr_r[1];
assign fs = csr_r[2];
assign rfr_ps_val = csr_r2[7:0];
always @(posedge clk or posedge rst)
if(rst) csc_mask_r <= #1 11'h7ff;
else
if(rf_we & (wb_addr_r[6:2] == 5'h2) )
csc_mask_r <= #1 wb_data_i[10:0];
////////////////////////////////////////////////////////////////////
//
// A kludge for cases where there is no clock during reset ...
//
reg rst_r1, rst_r2, rst_r3;
always @(posedge clk or posedge rst)
if(rst) rst_r1 <= #1 1'b1;
else rst_r1 <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) rst_r2 <= #1 1'b1;
else rst_r2 <= #1 rst_r1;
always @(posedge clk or posedge rst)
if(rst) rst_r3 <= #1 1'b1;
else rst_r3 <= #1 rst_r2;
always @(posedge clk)
if(rst_r3) poc <= #1 mc_data_i;
////////////////////////////////////////////////////////////////////
//
// WISHBONE Register Ack logic
//
always @(posedge clk)
wb_ack_o <= #1 `MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
////////////////////////////////////////////////////////////////////
//
// Select CSC and TMS Registers
//
always @(posedge clk or posedge rst)
if(rst) cs <= #1 8'h0;
else
if(cs_le) cs <= #1 {cs7, cs6, cs5, cs4, cs3, cs2, cs1, cs0};
always @(posedge clk or posedge rst)
if(rst) wp_err <= #1 1'b0;
else
if(cs_le & wb_cyc_i & wb_stb_i)
wp_err <= #1 wp_err7 | wp_err6 | wp_err5 | wp_err4 |
wp_err3 | wp_err2 | wp_err1 | wp_err0;
else
if(!wb_cyc_i) wp_err <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) csc <= #1 32'h0;
else
if(cs_le_d & wb_cyc_i & wb_stb_i)
begin
if(cs0) csc <= #1 csc0;
else
if(cs1) csc <= #1 csc1;
else
if(cs2) csc <= #1 csc2;
else
if(cs3) csc <= #1 csc3;
else
if(cs4) csc <= #1 csc4;
else
if(cs5) csc <= #1 csc5;
else
if(cs6) csc <= #1 csc6;
else csc <= #1 csc7;
end
always @(posedge clk or posedge rst)
if(rst) tms <= #1 32'hffff_ffff;
else
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
begin
if(cs0) tms <= #1 tms0;
else
if(cs1) tms <= #1 tms1;
else
if(cs2) tms <= #1 tms2;
else
if(cs3) tms <= #1 tms3;
else
if(cs4) tms <= #1 tms4;
else
if(cs5) tms <= #1 tms5;
else
if(cs6) tms <= #1 tms6;
else tms <= #1 tms7;
end
always @(posedge clk or posedge rst)
if(rst) sp_csc <= #1 32'h0;
else
if(cs_le_d & wb_cyc_i & wb_stb_i)
begin
if(spec_req_cs[0]) sp_csc <= #1 csc0;
else
if(spec_req_cs[1]) sp_csc <= #1 csc1;
else
if(spec_req_cs[2]) sp_csc <= #1 csc2;
else
if(spec_req_cs[3]) sp_csc <= #1 csc3;
else
if(spec_req_cs[4]) sp_csc <= #1 csc4;
else
if(spec_req_cs[5]) sp_csc <= #1 csc5;
else
if(spec_req_cs[6]) sp_csc <= #1 csc6;
else sp_csc <= #1 csc7;
end
always @(posedge clk or posedge rst)
if(rst) sp_tms <= #1 32'hffff_ffff;
else
if((cs_le_d | rf_we) & wb_cyc_i & wb_stb_i)
begin
if(spec_req_cs[0]) sp_tms <= #1 tms0;
else
if(spec_req_cs[1]) sp_tms <= #1 tms1;
else
if(spec_req_cs[2]) sp_tms <= #1 tms2;
else
if(spec_req_cs[3]) sp_tms <= #1 tms3;
else
if(spec_req_cs[4]) sp_tms <= #1 tms4;
else
if(spec_req_cs[5]) sp_tms <= #1 tms5;
else
if(spec_req_cs[6]) sp_tms <= #1 tms6;
else sp_tms <= #1 tms7;
end
assign cs_need_rfr[0] = csc0[0] & (csc0[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[1] = csc1[0] & (csc1[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[2] = csc2[0] & (csc2[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[3] = csc3[0] & (csc3[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[4] = csc4[0] & (csc4[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[5] = csc5[0] & (csc5[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[6] = csc6[0] & (csc6[3:1] == `MC_MEM_TYPE_SDRAM);
assign cs_need_rfr[7] = csc7[0] & (csc7[3:1] == `MC_MEM_TYPE_SDRAM);
assign ref_int = csr_r[10:8];
////////////////////////////////////////////////////////////////////
//
// Init & Lmr Logic
//
// Init Ack falling edge detector
always @(posedge clk)
init_ack_r <= #1 init_ack;
assign init_ack_fe = init_ack_r & !init_ack;
// LMR Ack falling edge detector
always @(posedge clk)
lmr_ack_r <= #1 lmr_ack;
assign lmr_ack_fe = lmr_ack_r & !lmr_ack;
// Chip Select Output
always @(posedge clk or posedge rst)
if(rst) spec_req_cs <= #1 8'h0;
else
if(sreq_cs_le) spec_req_cs <= #1 spec_req_cs_d;
always @(posedge clk or posedge rst)
if(rst) sreq_cs_le <= #1 1'b0;
else sreq_cs_le <= #1 (!init_req & !lmr_req) | lmr_ack_fe | init_ack_fe;
// Make sure only one is serviced at a time
assign spec_req_cs_d[0] = spec_req_cs_t[0];
assign spec_req_cs_d[1] = spec_req_cs_t[1] & !spec_req_cs_t[0];
assign spec_req_cs_d[2] = spec_req_cs_t[2] & !( |spec_req_cs_t[1:0] );
assign spec_req_cs_d[3] = spec_req_cs_t[3] & !( |spec_req_cs_t[2:0] );
assign spec_req_cs_d[4] = spec_req_cs_t[4] & !( |spec_req_cs_t[3:0] );
assign spec_req_cs_d[5] = spec_req_cs_t[5] & !( |spec_req_cs_t[4:0] );
assign spec_req_cs_d[6] = spec_req_cs_t[6] & !( |spec_req_cs_t[5:0] );
assign spec_req_cs_d[7] = spec_req_cs_t[7] & !( |spec_req_cs_t[6:0] );
// Request Tracking
always @(posedge clk or posedge rst)
if(rst) init_req <= #1 1'b0;
else init_req <= #1 init_req0 | init_req1 | init_req2 | init_req3 |
init_req4 | init_req5 | init_req6 | init_req7;
always @(posedge clk or posedge rst)
if(rst) lmr_req <= #1 1'b0;
else lmr_req <= #1 lmr_req0 | lmr_req1 | lmr_req2 | lmr_req3 |
lmr_req4 | lmr_req5 | lmr_req6 | lmr_req7;
assign spec_req_cs_t = !init_req ? // Load Mode Register Requests
{lmr_req7, lmr_req6, lmr_req5, lmr_req4,
lmr_req3, lmr_req2, lmr_req1, lmr_req0 } :
// Initialize SDRAM Requests
{init_req7, init_req6, init_req5, init_req4,
init_req3, init_req2, init_req1, init_req0 };
// Ack distribution
assign lmr_ack0 = spec_req_cs[0] & lmr_ack_fe;
assign lmr_ack1 = spec_req_cs[1] & lmr_ack_fe;
assign lmr_ack2 = spec_req_cs[2] & lmr_ack_fe;
assign lmr_ack3 = spec_req_cs[3] & lmr_ack_fe;
assign lmr_ack4 = spec_req_cs[4] & lmr_ack_fe;
assign lmr_ack5 = spec_req_cs[5] & lmr_ack_fe;
assign lmr_ack6 = spec_req_cs[6] & lmr_ack_fe;
assign lmr_ack7 = spec_req_cs[7] & lmr_ack_fe;
assign init_ack0 = spec_req_cs[0] & init_ack_fe;
assign init_ack1 = spec_req_cs[1] & init_ack_fe;
assign init_ack2 = spec_req_cs[2] & init_ack_fe;
assign init_ack3 = spec_req_cs[3] & init_ack_fe;
assign init_ack4 = spec_req_cs[4] & init_ack_fe;
assign init_ack5 = spec_req_cs[5] & init_ack_fe;
assign init_ack6 = spec_req_cs[6] & init_ack_fe;
assign init_ack7 = spec_req_cs[7] & init_ack_fe;
////////////////////////////////////////////////////////////////////
//
// Modules
//
mc_cs_rf #(3'h0) u0(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc0 ),
.tms( tms0 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs0 ),
.wp_err( wp_err0 ),
.lmr_req( lmr_req0 ),
.lmr_ack( lmr_ack0 ),
.init_req( init_req0 ),
.init_ack( init_ack0 )
);
`ifdef MC_HAVE_CS1
mc_cs_rf #(3'h1) u1(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc1 ),
.tms( tms1 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs1 ),
.wp_err( wp_err1 ),
.lmr_req( lmr_req1 ),
.lmr_ack( lmr_ack1 ),
.init_req( init_req1 ),
.init_ack( init_ack1 )
);
`else
mc_cs_rf_dummy #(3'h1) u1(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc1 ),
.tms( tms1 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs1 ),
.wp_err( wp_err1 ),
.lmr_req( lmr_req1 ),
.lmr_ack( lmr_ack1 ),
.init_req( init_req1 ),
.init_ack( init_ack1 )
);
`endif
`ifdef MC_HAVE_CS2
mc_cs_rf #(3'h2) u2(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc2 ),
.tms( tms2 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs2 ),
.wp_err( wp_err2 ),
.lmr_req( lmr_req2 ),
.lmr_ack( lmr_ack2 ),
.init_req( init_req2 ),
.init_ack( init_ack2 )
);
`else
mc_cs_rf_dummy #(3'h2) u2(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc2 ),
.tms( tms2 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs2 ),
.wp_err( wp_err2 ),
.lmr_req( lmr_req2 ),
.lmr_ack( lmr_ack2 ),
.init_req( init_req2 ),
.init_ack( init_ack2 )
);
`endif
`ifdef MC_HAVE_CS3
mc_cs_rf #(3'h3) u3(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc3 ),
.tms( tms3 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs3 ),
.wp_err( wp_err3 ),
.lmr_req( lmr_req3 ),
.lmr_ack( lmr_ack3 ),
.init_req( init_req3 ),
.init_ack( init_ack3 )
);
`else
mc_cs_rf_dummy #(3'h3) u3(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc3 ),
.tms( tms3 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs3 ),
.wp_err( wp_err3 ),
.lmr_req( lmr_req3 ),
.lmr_ack( lmr_ack3 ),
.init_req( init_req3 ),
.init_ack( init_ack3 )
);
`endif
`ifdef MC_HAVE_CS4
mc_cs_rf #(3'h4) u4(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc4 ),
.tms( tms4 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs4 ),
.wp_err( wp_err4 ),
.lmr_req( lmr_req4 ),
.lmr_ack( lmr_ack4 ),
.init_req( init_req4 ),
.init_ack( init_ack4 )
);
`else
mc_cs_rf_dummy #(3'h4) u4(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc4 ),
.tms( tms4 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs4 ),
.wp_err( wp_err4 ),
.lmr_req( lmr_req4 ),
.lmr_ack( lmr_ack4 ),
.init_req( init_req4 ),
.init_ack( init_ack4 )
);
`endif
`ifdef MC_HAVE_CS5
mc_cs_rf #(3'h5) u5(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc5 ),
.tms( tms5 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs5 ),
.wp_err( wp_err5 ),
.lmr_req( lmr_req5 ),
.lmr_ack( lmr_ack5 ),
.init_req( init_req5 ),
.init_ack( init_ack5 )
);
`else
mc_cs_rf_dummy #(3'h5) u5(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc5 ),
.tms( tms5 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs5 ),
.wp_err( wp_err5 ),
.lmr_req( lmr_req5 ),
.lmr_ack( lmr_ack5 ),
.init_req( init_req5 ),
.init_ack( init_ack5 )
);
`endif
`ifdef MC_HAVE_CS6
mc_cs_rf #(3'h6) u6(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc6 ),
.tms( tms6 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs6 ),
.wp_err( wp_err6 ),
.lmr_req( lmr_req6 ),
.lmr_ack( lmr_ack6 ),
.init_req( init_req6 ),
.init_ack( init_ack6 )
);
`else
mc_cs_rf_dummy #(3'h6) u6(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc6 ),
.tms( tms6 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs6 ),
.wp_err( wp_err6 ),
.lmr_req( lmr_req6 ),
.lmr_ack( lmr_ack6 ),
.init_req( init_req6 ),
.init_ack( init_ack6 )
);
`endif
`ifdef MC_HAVE_CS7
mc_cs_rf #(3'h7) u7(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc7 ),
.tms( tms7 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs7 ),
.wp_err( wp_err7 ),
.lmr_req( lmr_req7 ),
.lmr_ack( lmr_ack7 ),
.init_req( init_req7 ),
.init_ack( init_ack7 )
);
`else
mc_cs_rf_dummy #(3'h7) u7(
.clk( clk ),
.rst( rst ),
.wb_we_i( wb_we_i ),
.din( wb_data_i ),
.rf_we( rf_we ),
.addr( wb_addr_i ),
.csc( csc7 ),
.tms( tms7 ),
.poc( poc ),
.csc_mask( csc_mask ),
.cs( cs7 ),
.wp_err( wp_err7 ),
.lmr_req( lmr_req7 ),
.lmr_ack( lmr_ack7 ),
.init_req( init_req7 ),
.init_ack( init_ack7 )
);
`endif
endmodule |
module mc_incn_r(clk, inc_in, inc_out);
parameter incN_width = 32;
input clk;
input [incN_width-1:0] inc_in;
output [incN_width-1:0] inc_out;
parameter incN_center = incN_width / 2;
reg [incN_center:0] out_r;
wire [31:0] tmp_zeros = 32'h0;
wire [incN_center-1:0] inc_next;
always @(posedge clk)
out_r <= #1 inc_in[incN_center - 1:0] + {tmp_zeros[incN_center-2:0], 1'h1};
assign inc_out[incN_width-1:incN_center] = inc_in[incN_width-1:incN_center] + inc_next;
assign inc_next = out_r[incN_center] ?
{tmp_zeros[incN_center-2:0], 1'h1} : tmp_zeros[incN_center-2:0];
assign inc_out[incN_center-1:0] = out_r;
endmodule |
module mc_obct(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same);
input clk, rst;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
////////////////////////////////////////////////////////////////////
//
// Local Registers & Wires
//
reg bank0_open, bank1_open, bank2_open, bank3_open;
reg bank_open;
reg [12:0] b0_last_row;
reg [12:0] b1_last_row;
reg [12:0] b2_last_row;
reg [12:0] b3_last_row;
wire row0_same, row1_same, row2_same, row3_same;
reg row_same;
////////////////////////////////////////////////////////////////////
//
// Bank Open/Closed Tracking
//
always @(posedge clk or posedge rst)
if(rst) bank0_open <= #1 1'b0;
else
if((bank_adr == 2'h0) & bank_set) bank0_open <= #1 1'b1;
else
if((bank_adr == 2'h0) & bank_clr) bank0_open <= #1 1'b0;
else
if(bank_clr_all) bank0_open <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) bank1_open <= #1 1'b0;
else
if((bank_adr == 2'h1) & bank_set) bank1_open <= #1 1'b1;
else
if((bank_adr == 2'h1) & bank_clr) bank1_open <= #1 1'b0;
else
if(bank_clr_all) bank1_open <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) bank2_open <= #1 1'b0;
else
if((bank_adr == 2'h2) & bank_set) bank2_open <= #1 1'b1;
else
if((bank_adr == 2'h2) & bank_clr) bank2_open <= #1 1'b0;
else
if(bank_clr_all) bank2_open <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) bank3_open <= #1 1'b0;
else
if((bank_adr == 2'h3) & bank_set) bank3_open <= #1 1'b1;
else
if((bank_adr == 2'h3) & bank_clr) bank3_open <= #1 1'b0;
else
if(bank_clr_all) bank3_open <= #1 1'b0;
always @(bank_adr or bank0_open or bank1_open or bank2_open or bank3_open)
case(bank_adr) // synopsys full_case parallel_case
2'h0: bank_open = bank0_open;
2'h1: bank_open = bank1_open;
2'h2: bank_open = bank2_open;
2'h3: bank_open = bank3_open;
endcase
assign any_bank_open = bank0_open | bank1_open | bank2_open | bank3_open;
////////////////////////////////////////////////////////////////////
//
// Raw Address Tracking
//
always @(posedge clk)
if((bank_adr == 2'h0) & bank_set) b0_last_row <= #1 row_adr;
always @(posedge clk)
if((bank_adr == 2'h1) & bank_set) b1_last_row <= #1 row_adr;
always @(posedge clk)
if((bank_adr == 2'h2) & bank_set) b2_last_row <= #1 row_adr;
always @(posedge clk)
if((bank_adr == 2'h3) & bank_set) b3_last_row <= #1 row_adr;
////////////////////////////////////////////////////////////////////
//
// Raw address checking
//
assign row0_same = (b0_last_row == row_adr);
assign row1_same = (b1_last_row == row_adr);
assign row2_same = (b2_last_row == row_adr);
assign row3_same = (b3_last_row == row_adr);
always @(bank_adr or row0_same or row1_same or row2_same or row3_same)
case(bank_adr) // synopsys full_case parallel_case
2'h0: row_same = row0_same;
2'h1: row_same = row1_same;
2'h2: row_same = row2_same;
2'h3: row_same = row3_same;
endcase
endmodule |
module mc_obct_dummy(clk, rst, row_adr, bank_adr, bank_set, bank_clr, bank_clr_all,
bank_open, any_bank_open, row_same);
input clk, rst;
input [12:0] row_adr;
input [1:0] bank_adr;
input bank_set;
input bank_clr;
input bank_clr_all;
output bank_open;
output any_bank_open;
output row_same;
assign bank_open = 1'b0;
assign any_bank_open = 1'b0;
assign row_same = 1'b0;
endmodule |
module mc_wb_if(clk, rst,
wb_addr_i, wb_cyc_i, wb_stb_i, wb_we_i, wb_err, wb_ack_o,
wb_read_go, wb_write_go,
wb_first, wb_wait, mem_ack, wr_hold,
err, par_err, wp_err,
wb_data_o, mem_dout, rf_dout);
input clk, rst;
input [31:0] wb_addr_i;
input wb_cyc_i;
input wb_stb_i;
input wb_we_i;
output wb_err;
output wb_ack_o;
output wb_read_go;
output wb_write_go;
output wb_first;
output wb_wait;
input mem_ack;
output wr_hold;
input err, par_err, wp_err;
output [31:0] wb_data_o;
input [31:0] mem_dout, rf_dout;
////////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire mem_sel;
reg read_go_r;
reg read_go_r1;
reg write_go_r;
reg write_go_r1;
reg wb_first_r;
wire wb_first_set;
reg wr_hold;
wire rmw;
reg rmw_r;
reg rmw_en;
reg wb_ack_o;
reg wb_err;
reg [31:0] wb_data_o;
////////////////////////////////////////////////////////////////////
//
// Memory Go Logic
//
assign mem_sel = `MC_MEM_SEL;
always @(posedge clk or posedge rst)
if(rst) rmw_en <= #1 1'b0;
else
if(wb_ack_o) rmw_en <= #1 1'b1;
else
if(!wb_cyc_i) rmw_en <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) rmw_r <= #1 1'b0;
else rmw_r <= #1 !wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en;
assign rmw = rmw_r | (!wr_hold & wb_we_i & wb_cyc_i & wb_stb_i & rmw_en);
always @(posedge clk or posedge rst)
if(rst) read_go_r1 <= #1 1'b0;
else read_go_r1 <= #1 !rmw & wb_cyc_i &
((wb_stb_i & mem_sel & !wb_we_i) | read_go_r);
always @(posedge clk or posedge rst)
if(rst) read_go_r <= #1 1'b0;
else read_go_r <= #1 read_go_r1 & wb_cyc_i;
assign wb_read_go = !rmw & read_go_r1 & wb_cyc_i;
always @(posedge clk or posedge rst)
if(rst) write_go_r1 <= #1 1'b0;
else write_go_r1 <= #1 wb_cyc_i &
((wb_stb_i & mem_sel & wb_we_i) | write_go_r);
always @(posedge clk or posedge rst)
if(rst) write_go_r <= #1 1'b0;
else write_go_r <= #1 write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
assign wb_write_go = !rmw & write_go_r1 & wb_cyc_i &
((wb_we_i & wb_stb_i) | !wb_stb_i);
assign wb_first_set = mem_sel & wb_cyc_i & wb_stb_i & !(read_go_r | write_go_r);
assign wb_first = wb_first_set | (wb_first_r & !wb_ack_o & !wb_err);
always @(posedge clk or posedge rst)
if(rst) wb_first_r <= #1 1'b0;
else
if(wb_first_set) wb_first_r <= #1 1'b1;
else
if(wb_ack_o | wb_err) wb_first_r <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) wr_hold <= #1 1'b0;
else
if(wb_cyc_i & wb_stb_i) wr_hold <= #1 wb_we_i;
////////////////////////////////////////////////////////////////////
//
// WB Ack
//
wire wb_err_d;
// Ack no longer asserted when wb_err is asserted
always @(posedge clk or posedge rst)
if(rst) wb_ack_o <= #1 1'b0;
else wb_ack_o <= #1 `MC_MEM_SEL ? mem_ack & !wb_err_d :
`MC_REG_SEL & wb_cyc_i & wb_stb_i & !wb_ack_o;
assign wb_err_d = wb_cyc_i & wb_stb_i & (par_err | err | wp_err);
always @(posedge clk or posedge rst)
if(rst) wb_err <= #1 1'b0;
else wb_err <= #1 `MC_MEM_SEL & wb_err_d & !wb_err;
////////////////////////////////////////////////////////////////////
//
// Memory Wait Logic
//
assign wb_wait = wb_cyc_i & !wb_stb_i & (wb_write_go | wb_read_go);
////////////////////////////////////////////////////////////////////
//
// WISHBONE Data Output
//
always @(posedge clk)
wb_data_o <= #1 `MC_MEM_SEL ? mem_dout : rf_dout;
endmodule |
module mc_cs_rf(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
wp_err, lmr_req, lmr_ack, init_req, init_ack );
input clk, rst;
input wb_we_i;
input [31:0] din;
input rf_we;
input [31:0] addr;
output [31:0] csc;
output [31:0] tms;
input [31:0] poc;
input [31:0] csc_mask;
output cs;
output wp_err;
output lmr_req;
input lmr_ack;
output init_req;
input init_ack;
parameter [2:0] this_cs = 0;
parameter [3:0] reg_select = this_cs + 2;
////////////////////////////////////////////////////////////////////
//
// Local Registers and Wires
//
reg [31:0] csc;
reg [31:0] tms;
wire sel;
wire cs_d;
wire wp;
reg inited;
reg init_req;
reg init_req_we;
reg lmr_req;
reg lmr_req_we;
////////////////////////////////////////////////////////////////////
//
// A kludge for cases where there is no clock during reset ...
//
reg rst_r1, rst_r2;
always @(posedge clk or posedge rst)
if(rst) rst_r1 <= #1 1'b1;
else rst_r1 <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) rst_r2 <= #1 1'b1;
else rst_r2 <= #1 rst_r1;
////////////////////////////////////////////////////////////////////
//
// Write Logic
//
reg [6:0] addr_r;
always @(posedge clk)
addr_r <= #1 addr[6:0];
assign sel = addr_r[6:3] == reg_select[3:0];
always @(posedge clk)
if(rst_r2) csc <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
{26'h0, poc[1:0], 1'b0, poc[3:2], (poc[3:2] != 2'b00)} : 32'h0;
else
if(rf_we & sel & !addr_r[2]) csc <= #1 din;
always @(posedge clk)
if(rst_r2) tms <= #1 (this_cs[2:0] == `MC_DEF_SEL) ?
`MC_DEF_POR_TMS : 32'h0;
else
if(rf_we & sel & addr_r[2]) tms <= #1 din;
////////////////////////////////////////////////////////////////////
//
// Load Mode Register Request/Ack Logic
//
always @(posedge clk or posedge rst)
if(rst) lmr_req_we <= #1 1'b0;
else lmr_req_we <= #1 rf_we & sel & addr_r[2];
always @(posedge clk or posedge rst)
if(rst) lmr_req <= #1 1'b0;
else
if(lmr_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM))
lmr_req <= #1 inited;
else
if(lmr_ack) lmr_req <= #1 1'b0;
////////////////////////////////////////////////////////////////////
//
// Initialize SDRAM Request/Ack & tracking logic
//
always @(posedge clk or posedge rst)
if(rst) init_req_we <= #1 1'b0;
else init_req_we <= #1 rf_we & sel & !addr_r[2];
always @(posedge clk or posedge rst)
if(rst) init_req <= #1 1'b0;
else
if(init_req_we & (csc[3:1] == `MC_MEM_TYPE_SDRAM) & csc[0] & !inited)
init_req <= #1 1'b1;
else
if(init_ack) init_req <= #1 1'b0;
always @(posedge clk or posedge rst)
if(rst) inited <= #1 1'b0;
else
if(init_ack) inited <= #1 1'b1;
////////////////////////////////////////////////////////////////////
//
// Chip Select Generation Logic
//
assign cs_d = ((csc[23:16] & csc_mask[7:0]) == (addr[28:21] & csc_mask[7:0])) & csc[0];
assign wp = wb_we_i & csc[8];
assign wp_err = cs_d & wp;
assign cs = cs_d & !wp;
endmodule |
module mc_cs_rf_dummy(clk, rst, wb_we_i, din, rf_we, addr, csc, tms, poc, csc_mask, cs,
wp_err, lmr_req, lmr_ack, init_req, init_ack );
parameter [2:0] this_cs = 0;
input clk, rst;
input wb_we_i;
input [31:0] din;
input rf_we;
input [31:0] addr;
output [31:0] csc;
output [31:0] tms;
input [31:0] poc;
input [31:0] csc_mask;
output cs;
output wp_err;
output lmr_req;
input lmr_ack;
output init_req;
input init_ack;
assign csc = 32'h0;
assign tms = 32'h0;
assign cs = 1'b0;
assign wp_err = 1'b0;
assign lmr_req = 1'b0;
assign init_req = 1'b0;
endmodule |
module i2c_master_byte_ctrl (
clk, rst, nReset, ena, clk_cnt, start, stop, read, write, ack_in, din,
cmd_ack, ack_out, dout, i2c_busy, i2c_al, scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen );
//
// inputs & outputs
//
input clk; // master clock
input rst; // synchronous active high reset
input nReset; // asynchronous active low reset
input ena; // core enable signal
input [15:0] clk_cnt; // 4x SCL
// control inputs
input start;
input stop;
input read;
input write;
input ack_in;
input [7:0] din;
// status outputs
output cmd_ack;
reg cmd_ack;
output ack_out;
reg ack_out;
output i2c_busy;
output i2c_al;
output [7:0] dout;
// I2C signals
input scl_i;
output scl_o;
output scl_oen;
input sda_i;
output sda_o;
output sda_oen;
//
// Variable declarations
//
// statemachine
parameter [4:0] ST_IDLE = 5'b0_0000;
parameter [4:0] ST_START = 5'b0_0001;
parameter [4:0] ST_READ = 5'b0_0010;
parameter [4:0] ST_WRITE = 5'b0_0100;
parameter [4:0] ST_ACK = 5'b0_1000;
parameter [4:0] ST_STOP = 5'b1_0000;
// signals for bit_controller
reg [3:0] core_cmd;
reg core_txd;
wire core_ack, core_rxd;
// signals for shift register
reg [7:0] sr; //8bit shift register
reg shift, ld;
// signals for state machine
wire go;
reg [2:0] dcnt;
wire cnt_done;
//
// Module body
//
// hookup bit_controller
i2c_master_bit_ctrl bit_controller (
.clk ( clk ),
.rst ( rst ),
.nReset ( nReset ),
.ena ( ena ),
.clk_cnt ( clk_cnt ),
.cmd ( core_cmd ),
.cmd_ack ( core_ack ),
.busy ( i2c_busy ),
.al ( i2c_al ),
.din ( core_txd ),
.dout ( core_rxd ),
.scl_i ( scl_i ),
.scl_o ( scl_o ),
.scl_oen ( scl_oen ),
.sda_i ( sda_i ),
.sda_o ( sda_o ),
.sda_oen ( sda_oen )
);
// generate go-signal
assign go = (read | write | stop) & ~cmd_ack;
// assign dout output to shift-register
assign dout = sr;
// generate shift register
always @(posedge clk or negedge nReset)
if (!nReset)
sr <= #1 8'h0;
else if (rst)
sr <= #1 8'h0;
else if (ld)
sr <= #1 din;
else if (shift)
sr <= #1 {sr[6:0], core_rxd};
// generate counter
always @(posedge clk or negedge nReset)
if (!nReset)
dcnt <= #1 3'h0;
else if (rst)
dcnt <= #1 3'h0;
else if (ld)
dcnt <= #1 3'h7;
else if (shift)
dcnt <= #1 dcnt - 3'h1;
assign cnt_done = ~(|dcnt);
//
// state machine
//
reg [4:0] c_state; // synopsis enum_state
always @(posedge clk or negedge nReset)
if (!nReset)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else if (rst | i2c_al)
begin
core_cmd <= #1 `I2C_CMD_NOP;
core_txd <= #1 1'b0;
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
c_state <= #1 ST_IDLE;
ack_out <= #1 1'b0;
end
else
begin
// initially reset all signals
core_txd <= #1 sr[7];
shift <= #1 1'b0;
ld <= #1 1'b0;
cmd_ack <= #1 1'b0;
case (c_state) // synopsys full_case parallel_case
ST_IDLE:
if (go)
begin
if (start)
begin
c_state <= #1 ST_START;
core_cmd <= #1 `I2C_CMD_START;
end
else if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else if (write)
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else // stop
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
ld <= #1 1'b1;
end
ST_START:
if (core_ack)
begin
if (read)
begin
c_state <= #1 ST_READ;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE;
core_cmd <= #1 `I2C_CMD_WRITE;
end
ld <= #1 1'b1;
end
ST_WRITE:
if (core_ack)
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_READ;
end
else
begin
c_state <= #1 ST_WRITE; // stay in same state
core_cmd <= #1 `I2C_CMD_WRITE; // write next bit
shift <= #1 1'b1;
end
ST_READ:
if (core_ack)
begin
if (cnt_done)
begin
c_state <= #1 ST_ACK;
core_cmd <= #1 `I2C_CMD_WRITE;
end
else
begin
c_state <= #1 ST_READ; // stay in same state
core_cmd <= #1 `I2C_CMD_READ; // read next bit
end
shift <= #1 1'b1;
core_txd <= #1 ack_in;
end
ST_ACK:
if (core_ack)
begin
if (stop)
begin
c_state <= #1 ST_STOP;
core_cmd <= #1 `I2C_CMD_STOP;
end
else
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
// assign ack_out output to bit_controller_rxd (contains last received bit)
ack_out <= #1 core_rxd;
core_txd <= #1 1'b1;
end
else
core_txd <= #1 ack_in;
ST_STOP:
if (core_ack)
begin
c_state <= #1 ST_IDLE;
core_cmd <= #1 `I2C_CMD_NOP;
// generate command acknowledge signal
cmd_ack <= #1 1'b1;
end
endcase
end
endmodule |
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i)
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
default: ;
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule |
module add_sub27(add, opa, opb, sum, co);
input add;
input [26:0] opa, opb;
output [26:0] sum;
output co;
assign {co, sum} = add ? (opa + opb) : (opa - opb);
endmodule |
module mul_r2(clk, opa, opb, prod);
input clk;
input [23:0] opa, opb;
output [47:0] prod;
reg [47:0] prod1, prod;
always @(posedge clk)
prod1 <= #1 opa * opb;
always @(posedge clk)
prod <= #1 prod1;
endmodule |
module div_r2(clk, opa, opb, quo, rem);
input clk;
input [49:0] opa;
input [23:0] opb;
output [49:0] quo, rem;
reg [49:0] quo, rem, quo1, remainder;
always @(posedge clk)
quo1 <= #1 opa / opb;
always @(posedge clk)
quo <= #1 quo1;
always @(posedge clk)
remainder <= #1 opa % opb;
always @(posedge clk)
rem <= #1 remainder;
endmodule |
module pre_norm(clk, rmode, add, opa, opb, opa_nan, opb_nan, fracta_out,
fractb_out, exp_dn_out, sign, nan_sign, result_zero_sign,
fasu_op);
input clk;
input [1:0] rmode;
input add;
input [31:0] opa, opb;
input opa_nan, opb_nan;
output [26:0] fracta_out, fractb_out;
output [7:0] exp_dn_out;
output sign;
output nan_sign, result_zero_sign;
output fasu_op; // Operation Output
////////////////////////////////////////////////////////////////////////
//
// Local Wires and registers
//
wire signa, signb; // alias to opX sign
wire [7:0] expa, expb; // alias to opX exponent
wire [22:0] fracta, fractb; // alias to opX fraction
wire expa_lt_expb; // expa is larger than expb indicator
wire fractb_lt_fracta; // fractb is larger than fracta indicator
reg [7:0] exp_dn_out; // de normalized exponent output
wire [7:0] exp_small, exp_large;
wire [7:0] exp_diff; // Numeric difference of the two exponents
wire [22:0] adj_op; // Fraction adjustment: input
wire [26:0] adj_op_tmp;
wire [26:0] adj_op_out; // Fraction adjustment: output
wire [26:0] fracta_n, fractb_n; // Fraction selection after normalizing
wire [26:0] fracta_s, fractb_s; // Fraction Sorting out
reg [26:0] fracta_out, fractb_out; // Fraction Output
reg sign, sign_d; // Sign Output
reg add_d; // operation (add/sub)
reg fasu_op; // operation (add/sub) register
wire expa_dn, expb_dn;
reg sticky;
reg result_zero_sign;
reg add_r, signa_r, signb_r;
wire [4:0] exp_diff_sft;
wire exp_lt_27;
wire op_dn;
wire [26:0] adj_op_out_sft;
reg fracta_lt_fractb, fracta_eq_fractb;
wire nan_sign1;
reg nan_sign;
////////////////////////////////////////////////////////////////////////
//
// Aliases
//
assign signa = opa[31];
assign signb = opb[31];
assign expa = opa[30:23];
assign expb = opb[30:23];
assign fracta = opa[22:0];
assign fractb = opb[22:0];
////////////////////////////////////////////////////////////////////////
//
// Pre-Normalize exponents (and fractions)
//
assign expa_lt_expb = expa > expb; // expa is larger than expb
// ---------------------------------------------------------------------
// Normalize
assign expa_dn = !(|expa); // opa denormalized
assign expb_dn = !(|expb); // opb denormalized
// ---------------------------------------------------------------------
// Calculate the difference between the smaller and larger exponent
wire [7:0] exp_diff1, exp_diff1a, exp_diff2;
assign exp_small = expa_lt_expb ? expb : expa;
assign exp_large = expa_lt_expb ? expa : expb;
assign exp_diff1 = exp_large - exp_small;
assign exp_diff1a = exp_diff1-1;
assign exp_diff2 = (expa_dn | expb_dn) ? exp_diff1a : exp_diff1;
assign exp_diff = (expa_dn & expb_dn) ? 8'h0 : exp_diff2;
always @(posedge clk) // If numbers are equal we should return zero
exp_dn_out <= #1 (!add_d & expa==expb & fracta==fractb) ? 8'h0 : exp_large;
// ---------------------------------------------------------------------
// Adjust the smaller fraction
assign op_dn = expa_lt_expb ? expb_dn : expa_dn;
assign adj_op = expa_lt_expb ? fractb : fracta;
assign adj_op_tmp = { ~op_dn, adj_op, 3'b0 }; // recover hidden bit (op_dn)
// adj_op_out is 27 bits wide, so can only be shifted 27 bits to the right
assign exp_lt_27 = exp_diff > 8'd27;
assign exp_diff_sft = exp_lt_27 ? 5'd27 : exp_diff[4:0];
assign adj_op_out_sft = adj_op_tmp >> exp_diff_sft;
assign adj_op_out = {adj_op_out_sft[26:1], adj_op_out_sft[0] | sticky };
// ---------------------------------------------------------------------
// Get truncated portion (sticky bit)
always @(exp_diff_sft or adj_op_tmp)
case(exp_diff_sft) // synopsys full_case parallel_case
00: sticky = 1'h0;
01: sticky = adj_op_tmp[0];
02: sticky = |adj_op_tmp[01:0];
03: sticky = |adj_op_tmp[02:0];
04: sticky = |adj_op_tmp[03:0];
05: sticky = |adj_op_tmp[04:0];
06: sticky = |adj_op_tmp[05:0];
07: sticky = |adj_op_tmp[06:0];
08: sticky = |adj_op_tmp[07:0];
09: sticky = |adj_op_tmp[08:0];
10: sticky = |adj_op_tmp[09:0];
11: sticky = |adj_op_tmp[10:0];
12: sticky = |adj_op_tmp[11:0];
13: sticky = |adj_op_tmp[12:0];
14: sticky = |adj_op_tmp[13:0];
15: sticky = |adj_op_tmp[14:0];
16: sticky = |adj_op_tmp[15:0];
17: sticky = |adj_op_tmp[16:0];
18: sticky = |adj_op_tmp[17:0];
19: sticky = |adj_op_tmp[18:0];
20: sticky = |adj_op_tmp[19:0];
21: sticky = |adj_op_tmp[20:0];
22: sticky = |adj_op_tmp[21:0];
23: sticky = |adj_op_tmp[22:0];
24: sticky = |adj_op_tmp[23:0];
25: sticky = |adj_op_tmp[24:0];
26: sticky = |adj_op_tmp[25:0];
27: sticky = |adj_op_tmp[26:0];
endcase
// ---------------------------------------------------------------------
// Select operands for add/sub (recover hidden bit)
assign fracta_n = expa_lt_expb ? {~expa_dn, fracta, 3'b0} : adj_op_out;
assign fractb_n = expa_lt_expb ? adj_op_out : {~expb_dn, fractb, 3'b0};
// ---------------------------------------------------------------------
// Sort operands (for sub only)
assign fractb_lt_fracta = fractb_n > fracta_n; // fractb is larger than fracta
assign fracta_s = fractb_lt_fracta ? fractb_n : fracta_n;
assign fractb_s = fractb_lt_fracta ? fracta_n : fractb_n;
always @(posedge clk)
fracta_out <= #1 fracta_s;
always @(posedge clk)
fractb_out <= #1 fractb_s;
// ---------------------------------------------------------------------
// Determine sign for the output
// sign: 0=Positive Number; 1=Negative Number
always @(signa or signb or add or fractb_lt_fracta)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b0_0_1: sign_d = 0;
3'b0_1_1: sign_d = fractb_lt_fracta;
3'b1_0_1: sign_d = !fractb_lt_fracta;
3'b1_1_1: sign_d = 1;
// Sub
3'b0_0_0: sign_d = fractb_lt_fracta;
3'b0_1_0: sign_d = 0;
3'b1_0_0: sign_d = 1;
3'b1_1_0: sign_d = !fractb_lt_fracta;
endcase
always @(posedge clk)
sign <= #1 sign_d;
// Fix sign for ZERO result
always @(posedge clk)
signa_r <= #1 signa;
always @(posedge clk)
signb_r <= #1 signb;
always @(posedge clk)
add_r <= #1 add;
always @(posedge clk)
result_zero_sign <= #1 ( add_r & signa_r & signb_r) |
(!add_r & signa_r & !signb_r) |
( add_r & (signa_r | signb_r) & (rmode==3)) |
(!add_r & (signa_r == signb_r) & (rmode==3));
// Fix sign for NAN result
always @(posedge clk)
fracta_lt_fractb <= #1 fracta < fractb;
always @(posedge clk)
fracta_eq_fractb <= #1 fracta == fractb;
assign nan_sign1 = fracta_eq_fractb ? (signa_r & signb_r) : fracta_lt_fractb ? signb_r : signa_r;
always @(posedge clk)
nan_sign <= #1 (opa_nan & opb_nan) ? nan_sign1 : opb_nan ? signb_r : signa_r;
////////////////////////////////////////////////////////////////////////
//
// Decode Add/Sub operation
//
// add: 1=Add; 0=Subtract
always @(signa or signb or add)
case({signa, signb, add}) // synopsys full_case parallel_case
// Add
3'b0_0_1: add_d = 1;
3'b0_1_1: add_d = 0;
3'b1_0_1: add_d = 0;
3'b1_1_1: add_d = 1;
// Sub
3'b0_0_0: add_d = 0;
3'b0_1_0: add_d = 1;
3'b1_0_0: add_d = 1;
3'b1_1_0: add_d = 0;
endcase
always @(posedge clk)
fasu_op <= #1 add_d;
endmodule |
module aes128_keyex(
input i_clk,
input i_rst,
input [127:0] i_key, //key
input i_key_en, //key init flag
output [128*11-1:0] o_exkey, //round key
output o_key_ok, //key init ok
output o_sbox_use,
output [31:0] o_sbox_din,
input [31:0] i_sbox_dout
);
localparam DLY = 1;
wire [127:0] s_key;
reg [127:0] r_key;
reg [1279:0] r_exkey;
reg [3:0] r_count;
reg r_key_ok;
wire s_busy;
wire [127:0] s_exk;
reg [31:0] r_rcon;
//round left shift
function [31:0] ROL;
input [31:0] D;
begin
ROL = {D[23:0],D[31:24]};
end
endfunction
always@(*) begin
case(r_count)
4'd0: r_rcon = 32'h01000000;
4'd1: r_rcon = 32'h02000000;
4'd2: r_rcon = 32'h04000000;
4'd3: r_rcon = 32'h08000000;
4'd4: r_rcon = 32'h10000000;
4'd5: r_rcon = 32'h20000000;
4'd6: r_rcon = 32'h40000000;
4'd7: r_rcon = 32'h80000000;
4'd8: r_rcon = 32'h1B000000;
4'd9: r_rcon = 32'h36000000;
default: r_rcon = 32'b0;
endcase
end
assign s_key = i_key_en ? i_key : r_key;
//left shift 1|2 bits
assign o_sbox_use = s_busy;
assign o_sbox_din = ROL(s_key[31:0]);
//
assign s_exk[127:96] = s_key[127:96]^i_sbox_dout^r_rcon;
assign s_exk[95:64] = s_key[95:64]^s_exk[127:96];
assign s_exk[63:32] = s_key[63:32]^s_exk[95:64];
assign s_exk[31:0] = s_key[31:0]^s_exk[63:32];
always@(posedge i_clk or posedge i_rst) begin
if(i_rst)
r_key <= #DLY 128'b0;
else if(s_busy)
r_key <= #DLY s_exk;
end
always@(posedge i_clk or posedge i_rst) begin
if(i_rst) begin
r_exkey <= #DLY 1280'b0;
end else if(s_busy)begin
r_exkey <= #DLY {r_exkey[128*9-1:0],s_exk};
end
end
always@(posedge i_clk or posedge i_rst) begin
if(i_rst)
r_count <= #DLY 4'd0;
else if(i_key_en)
r_count <= #DLY 4'd1;
else if(r_count ==4'd9)
r_count <= #DLY 4'd0;
else if(r_count!=4'd0)
r_count <= #DLY r_count + 4'd1;
end
assign s_busy = ((r_count!=5'd0)||(i_key_en==1'b1)) ? 1'b1 : 1'b0;
always@(posedge i_clk or posedge i_rst) begin
if(i_rst)
r_key_ok <= #DLY 1'b0;
else if(r_count==4'd9)
r_key_ok <= #DLY 1'b1;
else if(i_key_en==1'b1)
r_key_ok <= #DLY 1'b0;
end
assign o_key_ok = r_key_ok&(~i_key_en);
assign o_exkey = {i_key,r_exkey};
endmodule |
module aes128_core(
input i_clk,
input i_rst,
input i_flag, //1-encrypt,0-decrypt
input [127:0] i_key,
input i_key_en, //1-key init start
output o_key_ok, //1-key init done
input [127:0] i_din,
input i_din_en,
output [127:0] o_dout,
output o_dout_en
);
wire [128*11-1:0] s_exkey;
//KeyExpand
wire s_sbox_use_ke;
wire [31:0] s_sbox_din_ke;
wire [31:0] s_sbox_dout_ke;
//DataProcess
wire [127:0] s_sbox_din_dp;
wire [127:0] s_sbox_dout_dp;
//SubByte S-Box
wire [127:0] s_sbox_din;
wire [127:0] s_sbox_dout;
wire [127:0] s_sbox_dout_p;
wire [127:0] s_sbox_dout_n;
//
genvar i;
//key expand
aes128_keyex u_keyex(
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_key (i_key ),
.i_key_en (i_key_en ),
.o_exkey (s_exkey ),
.o_key_ok (o_key_ok ),
.o_sbox_use (s_sbox_use_ke ),
.o_sbox_din (s_sbox_din_ke ),
.i_sbox_dout(s_sbox_dout_ke )
);
//data encrypt or decrypt
aes128_dpc u_dpc(
.i_clk (i_clk ),
.i_rst (i_rst ),
.i_flag (i_flag ),
.i_keyex (s_exkey ),
.i_din (i_din ),
.i_din_en (i_din_en ),
.o_dout (o_dout ),
.o_dout_en (o_dout_en ),
.o_sbox_din (s_sbox_din_dp ),
.i_sbox_dout(s_sbox_dout_dp )
);
assign s_sbox_din = s_sbox_use_ke ? {96'b0,s_sbox_din_ke} : s_sbox_din_dp;
assign s_sbox_dout_ke = s_sbox_dout_p[31:0];
assign s_sbox_dout_dp = i_flag ? s_sbox_dout_p:s_sbox_dout_n;
generate
for(i=0;i<16;i=i+1) begin: INST_SBOX_P
aes_sbox_p u_sbox_p(
.din (s_sbox_din[8*i+7:8*i] ),
.dout (s_sbox_dout_p[8*i+7:8*i])
);
end
for(i=0;i<16;i=i+1) begin: INST_SBOX_N
aes_sbox_n u_sbox_n(
.din (s_sbox_din[8*i+7:8*i] ),
.dout (s_sbox_dout_n[8*i+7:8*i])
);
end
endgenerate
endmodule |
module aes128_dpc(
input i_clk,
input i_rst,
input i_flag,
input [128*11-1:0] i_keyex,
input [127:0] i_din,
input i_din_en,
output [127:0] o_dout,
output o_dout_en,
output [127:0] o_sbox_din,
input [127:0] i_sbox_dout
);
localparam DLY = 1;
reg [3:0] r_count;
reg [127:0] r_ka;
reg [127:0] r_din;
wire [127:0] s_din;
wire [31:0] s_dina,s_dinb,s_dinc,s_dind;
wire [127:0] s_mixc_doutx;
wire [127:0] s_mixc_douty;
wire [127:0] s_mixc_din;
wire [127:0] s_ikey;
//byte select
function [7:0] BS;
input [31:0] D;
input [1:0] S;
begin
BS = (S==2'd3) ? D[31:24]:
((S==2'd2) ? D[23:16]:
((S==2'd1) ? D[15:8] :
((S==2'd0) ? D[7:0] :8'b0)));
end
endfunction
always@(posedge i_clk or posedge i_rst) begin
if(i_rst)
r_count <= #DLY 4'b0;
else if(i_din_en)
r_count <= #DLY 4'd1;
else if(r_count==4'd9)
r_count <= #DLY 4'b0;
else if(r_count!=4'd0)
r_count <= #DLY r_count + 4'd1;
end
always@(*) begin
if(i_flag) begin //encrypt
case(r_count)
4'd0: r_ka = i_keyex[128*10-1:128* 9];
4'd1: r_ka = i_keyex[128* 9-1:128* 8];
4'd2: r_ka = i_keyex[128* 8-1:128* 7];
4'd3: r_ka = i_keyex[128* 7-1:128* 6];
4'd4: r_ka = i_keyex[128* 6-1:128* 5];
4'd5: r_ka = i_keyex[128* 5-1:128* 4];
4'd6: r_ka = i_keyex[128* 4-1:128* 3];
4'd7: r_ka = i_keyex[128* 3-1:128* 2];
4'd8: r_ka = i_keyex[128* 2-1:128* 1];
4'd9: r_ka = i_keyex[128* 1-1:128* 0];
endcase
end else begin //decrypt
case(r_count)
4'd9: r_ka = i_keyex[128*11-1:128*10];
4'd8: r_ka = i_keyex[128*10-1:128* 9];
4'd7: r_ka = i_keyex[128* 9-1:128* 8];
4'd6: r_ka = i_keyex[128* 8-1:128* 7];
4'd5: r_ka = i_keyex[128* 7-1:128* 6];
4'd4: r_ka = i_keyex[128* 6-1:128* 5];
4'd3: r_ka = i_keyex[128* 5-1:128* 4];
4'd2: r_ka = i_keyex[128* 4-1:128* 3];
4'd1: r_ka = i_keyex[128* 3-1:128* 2];
4'd0: r_ka = i_keyex[128* 2-1:128* 1];
endcase
end
end
assign s_ikey = i_flag ? i_keyex[128*11-1:128*10] : i_keyex[128* 1-1:128* 0];
assign s_din = i_din_en ? i_din^s_ikey : r_din;
assign s_dina = s_din[127:96]; //col-1
assign s_dinb = s_din[95:64]; //col-2
assign s_dinc = s_din[63:32]; //col-3
assign s_dind = s_din[31:0]; //col-4
//ShiftRows & SubBytes
assign o_sbox_din[127:96] = i_flag ? {BS(s_dina,3),BS(s_dinb,2),BS(s_dinc,1),BS(s_dind,0)} : {BS(s_dina,3),BS(s_dind,2),BS(s_dinc,1),BS(s_dinb,0)};
assign o_sbox_din[95:64] = i_flag ? {BS(s_dinb,3),BS(s_dinc,2),BS(s_dind,1),BS(s_dina,0)} : {BS(s_dinb,3),BS(s_dina,2),BS(s_dind,1),BS(s_dinc,0)};
assign o_sbox_din[63:32] = i_flag ? {BS(s_dinc,3),BS(s_dind,2),BS(s_dina,1),BS(s_dinb,0)} : {BS(s_dinc,3),BS(s_dinb,2),BS(s_dina,1),BS(s_dind,0)};
assign o_sbox_din[31:0] = i_flag ? {BS(s_dind,3),BS(s_dina,2),BS(s_dinb,1),BS(s_dinc,0)} : {BS(s_dind,3),BS(s_dinc,2),BS(s_dinb,1),BS(s_dina,0)};
//
assign s_mixc_din = i_flag ? i_sbox_dout : i_sbox_dout^r_ka;
//MixColumns
aes_mixcol_w u_mixcol_1(
.i_din (s_mixc_din[127:96] ),
.o_dout_x (s_mixc_doutx[127:96] ),
.o_dout_y (s_mixc_douty[127:96] ));
aes_mixcol_w u_mixcol_2(
.i_din (s_mixc_din[95:64] ),
.o_dout_x (s_mixc_doutx[95:64] ),
.o_dout_y (s_mixc_douty[95:64] ));
aes_mixcol_w u_mixcol_3(
.i_din (s_mixc_din[63:32] ),
.o_dout_x (s_mixc_doutx[63:32] ),
.o_dout_y (s_mixc_douty[63:32] ));
aes_mixcol_w u_mixcol_4(
.i_din (s_mixc_din[31:0] ),
.o_dout_x (s_mixc_doutx[31:0] ),
.o_dout_y (s_mixc_douty[31:0] ));
always@(posedge i_clk or posedge i_rst) begin
if(i_rst)
r_din <= #DLY 128'b0;
else if(i_flag)
r_din <= #DLY s_mixc_doutx^r_ka;
else
r_din <= #DLY s_mixc_douty;
end
assign o_dout = i_sbox_dout^r_ka;
assign o_dout_en = (r_count==4'd9) ? 1'b1:1'b0;
endmodule |
module aes_mixcol_w(
input [31:0] i_din,
output [31:0] o_dout_x,
output [31:0] o_dout_y);
wire [7:0] s_a,s_b,s_c,s_d;
wire [7:0] s_x1,s_x2,s_x3,s_x4;
wire [7:0] s_y1,s_y2,s_y3,s_y4;
assign s_a = i_din[31:24];
assign s_b = i_din[23:16];
assign s_c = i_din[15:8];
assign s_d = i_din[7:0];
aes_mixcol_b u_bm1 (.i_a(s_a), .i_b(s_b), .i_c(s_c), .i_d(s_d), .o_x(s_x1), .o_y(s_y1));
aes_mixcol_b u_bm2 (.i_a(s_b), .i_b(s_c), .i_c(s_d), .i_d(s_a), .o_x(s_x2), .o_y(s_y2));
aes_mixcol_b u_bm3 (.i_a(s_c), .i_b(s_d), .i_c(s_a), .i_d(s_b), .o_x(s_x3), .o_y(s_y3));
aes_mixcol_b u_bm4 (.i_a(s_d), .i_b(s_a), .i_c(s_b), .i_d(s_c), .o_x(s_x4), .o_y(s_y4));
assign o_dout_x = {s_x1,s_x2,s_x3,s_x4};
assign o_dout_y = {s_y1,s_y2,s_y3,s_y4};
endmodule |
module aes_mixcol_b(
input [7:0] i_a,
input [7:0] i_b,
input [7:0] i_c,
input [7:0] i_d,
output [7:0] o_x,
output [7:0] o_y);
wire [7:0] s_w1,s_w2,s_w3,s_w4;
wire [7:0] s_w5,s_w6,s_w7,s_w8;
function [7:0] xtime;
input [7:0] in;
reg [3:0] xtime_t;
begin
xtime[7:5] = in[6:4];
xtime_t[3] = in[7];
xtime_t[2] = in[7];
xtime_t[1] = 0;
xtime_t[0] = in[7];
xtime[4:1] =xtime_t^in[3:0];
xtime[0] = in[7];
end
endfunction
assign s_w1 = i_a ^i_b;
assign s_w2 = i_a ^i_c;
assign s_w3 = i_c ^i_d;
assign s_w4 = xtime(s_w1);
assign s_w5 = xtime(s_w3);
assign s_w6 = s_w2 ^s_w4 ^s_w5;
assign s_w7 = xtime(s_w6);
assign s_w8 = xtime(s_w7);
assign o_x = i_b^s_w3^s_w4;
assign o_y = s_w8^o_x;
endmodule |
module wb_dma_inc30r(clk, in, out);
input clk;
input [29:0] in;
output [29:0] out;
// INC30_CENTER indicates the center bit of the 30 bit incrementor
// so it can be easily manually optimized for best performance
parameter INC30_CENTER = 16;
reg [INC30_CENTER:0] out_r;
always @(posedge clk)
out_r <= #1 in[(INC30_CENTER - 1):0] + 1;
assign out[29:INC30_CENTER] = in[29:INC30_CENTER] + out_r[INC30_CENTER];
assign out[(INC30_CENTER - 1):0] = out_r;
endmodule |
module wb_dma_wb_mast(clk, rst,
wb_data_i, wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait,
pt_sel, mast_pt_in, mast_pt_out
);
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// INTERNAL DMA INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg mast_cyc, mast_stb;
reg mast_we_r;
reg [3:0] mast_be;
reg [31:0] mast_dout;
////////////////////////////////////////////////////////////////////
//
// Pass-Through Interface
//
assign {wb_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o} =
pt_sel ? mast_pt_in :
{mast_din, mast_adr, mast_be, mast_we_r, mast_cyc, mast_stb};
assign mast_pt_out = {wb_data_i, wb_ack_i, wb_err_i, wb_rty_i};
////////////////////////////////////////////////////////////////////
//
// DMA Engine Interface
//
always @(posedge clk)
if(wb_ack_i) mast_dout <= #1 wb_data_i;
always @(posedge clk)
mast_be <= #1 4'hf;
always @(posedge clk)
mast_we_r <= #1 mast_we;
always @(posedge clk)
mast_cyc <= #1 mast_go;
always @(posedge clk)
mast_stb <= #1 mast_go & !mast_wait;
assign mast_drdy = wb_ack_i;
assign mast_err = wb_err_i;
endmodule |
module wb_dma_ch_pri_enc(clk, valid,
pri0, pri1, pri2, pri3,
pri4, pri5, pri6, pri7,
pri8, pri9, pri10, pri11,
pri12, pri13, pri14, pri15,
pri16, pri17, pri18, pri19,
pri20, pri21, pri22, pri23,
pri24, pri25, pri26, pri27,
pri28, pri29, pri30,
pri_out);
////////////////////////////////////////////////////////////////////
//
// Module Parameters
//
// chXX_conf = { CBUF, ED, ARS, EN }
parameter [1:0] pri_sel = 2'd0;
parameter [3:0] ch0_conf = 4'h1;
parameter [3:0] ch1_conf = 4'h0;
parameter [3:0] ch2_conf = 4'h0;
parameter [3:0] ch3_conf = 4'h0;
parameter [3:0] ch4_conf = 4'h0;
parameter [3:0] ch5_conf = 4'h0;
parameter [3:0] ch6_conf = 4'h0;
parameter [3:0] ch7_conf = 4'h0;
parameter [3:0] ch8_conf = 4'h0;
parameter [3:0] ch9_conf = 4'h0;
parameter [3:0] ch10_conf = 4'h0;
parameter [3:0] ch11_conf = 4'h0;
parameter [3:0] ch12_conf = 4'h0;
parameter [3:0] ch13_conf = 4'h0;
parameter [3:0] ch14_conf = 4'h0;
parameter [3:0] ch15_conf = 4'h0;
parameter [3:0] ch16_conf = 4'h0;
parameter [3:0] ch17_conf = 4'h0;
parameter [3:0] ch18_conf = 4'h0;
parameter [3:0] ch19_conf = 4'h0;
parameter [3:0] ch20_conf = 4'h0;
parameter [3:0] ch21_conf = 4'h0;
parameter [3:0] ch22_conf = 4'h0;
parameter [3:0] ch23_conf = 4'h0;
parameter [3:0] ch24_conf = 4'h0;
parameter [3:0] ch25_conf = 4'h0;
parameter [3:0] ch26_conf = 4'h0;
parameter [3:0] ch27_conf = 4'h0;
parameter [3:0] ch28_conf = 4'h0;
parameter [3:0] ch29_conf = 4'h0;
parameter [3:0] ch30_conf = 4'h0;
////////////////////////////////////////////////////////////////////
//
// Module IOs
//
input clk;
input [30:0] valid; // Channel Valid bits
input [2:0] pri0, pri1, pri2, pri3; // Channel Priorities
input [2:0] pri4, pri5, pri6, pri7;
input [2:0] pri8, pri9, pri10, pri11;
input [2:0] pri12, pri13, pri14, pri15;
input [2:0] pri16, pri17, pri18, pri19;
input [2:0] pri20, pri21, pri22, pri23;
input [2:0] pri24, pri25, pri26, pri27;
input [2:0] pri28, pri29, pri30;
output [2:0] pri_out; // Highest unserviced priority
wire [7:0] pri0_out, pri1_out, pri2_out, pri3_out;
wire [7:0] pri4_out, pri5_out, pri6_out, pri7_out;
wire [7:0] pri8_out, pri9_out, pri10_out, pri11_out;
wire [7:0] pri12_out, pri13_out, pri14_out, pri15_out;
wire [7:0] pri16_out, pri17_out, pri18_out, pri19_out;
wire [7:0] pri20_out, pri21_out, pri22_out, pri23_out;
wire [7:0] pri24_out, pri25_out, pri26_out, pri27_out;
wire [7:0] pri28_out, pri29_out, pri30_out;
wire [7:0] pri_out_tmp;
reg [2:0] pri_out;
reg [2:0] pri_out2;
reg [2:0] pri_out1;
reg [2:0] pri_out0;
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u0( // Use channel config 1 for channel 0 encoder
.valid( valid[0] ),
.pri_in( pri0 ),
.pri_out( pri0_out )
);
wb_dma_pri_enc_sub #(ch1_conf,pri_sel) u1(
.valid( valid[1] ),
.pri_in( pri1 ),
.pri_out( pri1_out )
);
wb_dma_pri_enc_sub #(ch2_conf,pri_sel) u2(
.valid( valid[2] ),
.pri_in( pri2 ),
.pri_out( pri2_out )
);
wb_dma_pri_enc_sub #(ch3_conf,pri_sel) u3(
.valid( valid[3] ),
.pri_in( pri3 ),
.pri_out( pri3_out )
);
wb_dma_pri_enc_sub #(ch4_conf,pri_sel) u4(
.valid( valid[4] ),
.pri_in( pri4 ),
.pri_out( pri4_out )
);
wb_dma_pri_enc_sub #(ch5_conf,pri_sel) u5(
.valid( valid[5] ),
.pri_in( pri5 ),
.pri_out( pri5_out )
);
wb_dma_pri_enc_sub #(ch6_conf,pri_sel) u6(
.valid( valid[6] ),
.pri_in( pri6 ),
.pri_out( pri6_out )
);
wb_dma_pri_enc_sub #(ch7_conf,pri_sel) u7(
.valid( valid[7] ),
.pri_in( pri7 ),
.pri_out( pri7_out )
);
wb_dma_pri_enc_sub #(ch8_conf,pri_sel) u8(
.valid( valid[8] ),
.pri_in( pri8 ),
.pri_out( pri8_out )
);
wb_dma_pri_enc_sub #(ch9_conf,pri_sel) u9(
.valid( valid[9] ),
.pri_in( pri9 ),
.pri_out( pri9_out )
);
wb_dma_pri_enc_sub #(ch10_conf,pri_sel) u10(
.valid( valid[10] ),
.pri_in( pri10 ),
.pri_out( pri10_out )
);
wb_dma_pri_enc_sub #(ch11_conf,pri_sel) u11(
.valid( valid[11] ),
.pri_in( pri11 ),
.pri_out( pri11_out )
);
wb_dma_pri_enc_sub #(ch12_conf,pri_sel) u12(
.valid( valid[12] ),
.pri_in( pri12 ),
.pri_out( pri12_out )
);
wb_dma_pri_enc_sub #(ch13_conf,pri_sel) u13(
.valid( valid[13] ),
.pri_in( pri13 ),
.pri_out( pri13_out )
);
wb_dma_pri_enc_sub #(ch14_conf,pri_sel) u14(
.valid( valid[14] ),
.pri_in( pri14 ),
.pri_out( pri14_out )
);
wb_dma_pri_enc_sub #(ch15_conf,pri_sel) u15(
.valid( valid[15] ),
.pri_in( pri15 ),
.pri_out( pri15_out )
);
wb_dma_pri_enc_sub #(ch16_conf,pri_sel) u16(
.valid( valid[16] ),
.pri_in( pri16 ),
.pri_out( pri16_out )
);
wb_dma_pri_enc_sub #(ch17_conf,pri_sel) u17(
.valid( valid[17] ),
.pri_in( pri17 ),
.pri_out( pri17_out )
);
wb_dma_pri_enc_sub #(ch18_conf,pri_sel) u18(
.valid( valid[18] ),
.pri_in( pri18 ),
.pri_out( pri18_out )
);
wb_dma_pri_enc_sub #(ch19_conf,pri_sel) u19(
.valid( valid[19] ),
.pri_in( pri19 ),
.pri_out( pri19_out )
);
wb_dma_pri_enc_sub #(ch20_conf,pri_sel) u20(
.valid( valid[20] ),
.pri_in( pri20 ),
.pri_out( pri20_out )
);
wb_dma_pri_enc_sub #(ch21_conf,pri_sel) u21(
.valid( valid[21] ),
.pri_in( pri21 ),
.pri_out( pri21_out )
);
wb_dma_pri_enc_sub #(ch22_conf,pri_sel) u22(
.valid( valid[22] ),
.pri_in( pri22 ),
.pri_out( pri22_out )
);
wb_dma_pri_enc_sub #(ch23_conf,pri_sel) u23(
.valid( valid[23] ),
.pri_in( pri23 ),
.pri_out( pri23_out )
);
wb_dma_pri_enc_sub #(ch24_conf,pri_sel) u24(
.valid( valid[24] ),
.pri_in( pri24 ),
.pri_out( pri24_out )
);
wb_dma_pri_enc_sub #(ch25_conf,pri_sel) u25(
.valid( valid[25] ),
.pri_in( pri25 ),
.pri_out( pri25_out )
);
wb_dma_pri_enc_sub #(ch26_conf,pri_sel) u26(
.valid( valid[26] ),
.pri_in( pri26 ),
.pri_out( pri26_out )
);
wb_dma_pri_enc_sub #(ch27_conf,pri_sel) u27(
.valid( valid[27] ),
.pri_in( pri27 ),
.pri_out( pri27_out )
);
wb_dma_pri_enc_sub #(ch28_conf,pri_sel) u28(
.valid( valid[28] ),
.pri_in( pri28 ),
.pri_out( pri28_out )
);
wb_dma_pri_enc_sub #(ch29_conf,pri_sel) u29(
.valid( valid[29] ),
.pri_in( pri29 ),
.pri_out( pri29_out )
);
wb_dma_pri_enc_sub #(ch30_conf,pri_sel) u30(
.valid( valid[30] ),
.pri_in( pri30 ),
.pri_out( pri30_out )
);
assign pri_out_tmp = pri0_out | pri1_out | pri2_out | pri3_out |
pri4_out | pri5_out | pri6_out | pri7_out |
pri8_out | pri9_out | pri10_out | pri11_out |
pri12_out | pri13_out | pri14_out | pri15_out |
pri16_out | pri17_out | pri18_out | pri19_out |
pri20_out | pri21_out | pri22_out | pri23_out |
pri24_out | pri25_out | pri26_out | pri27_out |
pri28_out | pri29_out | pri30_out;
// 8 Priority Levels
always @(posedge clk)
if(pri_out_tmp[7]) pri_out2 <= #1 3'h7;
else
if(pri_out_tmp[6]) pri_out2 <= #1 3'h6;
else
if(pri_out_tmp[5]) pri_out2 <= #1 3'h5;
else
if(pri_out_tmp[4]) pri_out2 <= #1 3'h4;
else
if(pri_out_tmp[3]) pri_out2 <= #1 3'h3;
else
if(pri_out_tmp[2]) pri_out2 <= #1 3'h2;
else
if(pri_out_tmp[1]) pri_out2 <= #1 3'h1;
else pri_out2 <= #1 3'h0;
// 4 Priority Levels
always @(posedge clk)
if(pri_out_tmp[3]) pri_out1 <= #1 3'h3;
else
if(pri_out_tmp[2]) pri_out1 <= #1 3'h2;
else
if(pri_out_tmp[1]) pri_out1 <= #1 3'h1;
else pri_out1 <= #1 3'h0;
// 2 Priority Levels
always @(posedge clk)
if(pri_out_tmp[1]) pri_out0 <= #1 3'h1;
else pri_out0 <= #1 3'h0;
// Select configured priority
always @(pri_sel or pri_out0 or pri_out1 or pri_out2)
case(pri_sel) // synopsys parallel_case full_case
2'd0: pri_out = pri_out0;
2'd1: pri_out = pri_out1;
2'd2: pri_out = pri_out2;
endcase
endmodule |
module wb_dma_wb_if(clk, rst,
// Wishbone
wbs_data_i, wbs_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
wbm_data_i, wbm_data_o, wb_addr_o, wb_sel_o, wb_we_o, wb_cyc_o,
wb_stb_o, wb_ack_i, wb_err_i, wb_rty_i,
// Master
mast_go, mast_we, mast_adr, mast_din, mast_dout, mast_err,
mast_drdy, mast_wait, pt_sel_i, mast_pt_in, mast_pt_out,
// Slave
slv_adr, slv_din, slv_dout, slv_re, slv_we,
pt_sel_o, slv_pt_out, slv_pt_in
);
parameter rf_addr = 0;
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
// Slave Interface
input [31:0] wbs_data_i;
output [31:0] wbs_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// Master Interface
input [31:0] wbm_data_i;
output [31:0] wbm_data_o;
output [31:0] wb_addr_o;
output [3:0] wb_sel_o;
output wb_we_o;
output wb_cyc_o;
output wb_stb_o;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
// --------------------------------------
// MASTER INTERFACE
input mast_go; // Perform a Master Cycle (as long as this
// line is asserted)
input mast_we; // Read/Write
input [31:0] mast_adr; // Address for the transfer
input [31:0] mast_din; // Internal Input Data
output [31:0] mast_dout; // Internal Output Data
output mast_err; // Indicates an error has occurred
output mast_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
input mast_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// Pass Through Interface
input pt_sel_i; // Pass Through Mode Selected
input [70:0] mast_pt_in; // Grouped WISHBONE inputs
output [34:0] mast_pt_out; // Grouped WISHBONE outputs
// --------------------------------------
// Slave INTERFACE
// This is the register File Interface
output [31:0] slv_adr; // Slave Address
input [31:0] slv_din; // Slave Input Data
output [31:0] slv_dout; // Slave Output Data
output slv_re; // Slave Read Enable
output slv_we; // Slave Write Enable
// Pass through Interface
output pt_sel_o; // Pass Through Mode Active
output [70:0] slv_pt_out; // Grouped WISHBONE out signals
input [34:0] slv_pt_in; // Grouped WISHBONE in signals
////////////////////////////////////////////////////////////////////
//
// Modules
//
wb_dma_wb_mast u0(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbs_data_i ),
.wb_data_o( wbs_data_o ),
.wb_addr_o( wb_addr_o ),
.wb_sel_o( wb_sel_o ),
.wb_we_o( wb_we_o ),
.wb_cyc_o( wb_cyc_o ),
.wb_stb_o( wb_stb_o ),
.wb_ack_i( wb_ack_i ),
.wb_err_i( wb_err_i ),
.wb_rty_i( wb_rty_i ),
.mast_go( mast_go ),
.mast_we( mast_we ),
.mast_adr( mast_adr ),
.mast_din( mast_din ),
.mast_dout( mast_dout ),
.mast_err( mast_err ),
.mast_drdy( mast_drdy ),
.mast_wait( mast_wait ),
.pt_sel( pt_sel_i ),
.mast_pt_in( mast_pt_in ),
.mast_pt_out( mast_pt_out )
);
wb_dma_wb_slv #(rf_addr) u1(
.clk( clk ),
.rst( rst ),
.wb_data_i( wbm_data_i ),
.wb_data_o( wbm_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.wb_rty_o( wb_rty_o ),
.slv_adr( slv_adr ),
.slv_din( slv_din ),
.slv_dout( slv_dout ),
.slv_re( slv_re ),
.slv_we( slv_we ),
.pt_sel( pt_sel_o ),
.slv_pt_out( slv_pt_out ),
.slv_pt_in( slv_pt_in )
);
endmodule |
module wb_dma_de(clk, rst,
// WISHBONE MASTER INTERFACE 0
mast0_go, mast0_we, mast0_adr, mast0_din,
mast0_dout, mast0_err, mast0_drdy, mast0_wait,
// WISHBONE MASTER INTERFACE 1
mast1_go, mast1_we, mast1_adr, mast1_din,
mast1_dout, mast1_err, mast1_drdy, mast1_wait,
// DMA Engine Init & Setup
de_start, nd, csr, pointer, pointer_s, txsz,
adr0, adr1, am0, am1,
// DMA Engine Register File Update Outputs
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set,
de_csr, de_txsz, de_adr0, de_adr1, de_fetch_descr,
// DMA Engine Control Outputs
next_ch, de_ack,
// DMA Engine Status
pause_req, paused,
dma_abort, dma_busy, dma_err, dma_done, dma_done_all
);
input clk, rst;
// --------------------------------------
// WISHBONE MASTER INTERFACE 0
output mast0_go; // Perform a Master Cycle
output mast0_we; // Read/Write
output [31:0] mast0_adr; // Address for the transfer
input [31:0] mast0_din; // Internal Input Data
output [31:0] mast0_dout; // Internal Output Data
input mast0_err; // Indicates an error has occurred
input mast0_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast0_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// WISHBONE MASTER INTERFACE 1
output mast1_go; // Perform a Master Cycle
output mast1_we; // Read/Write
output [31:0] mast1_adr; // Address for the transfer
input [31:0] mast1_din; // Internal Input Data
output [31:0] mast1_dout; // Internal Output Data
input mast1_err; // Indicates an error has occurred
input mast1_drdy; // Indicated that either data is available
// during a read, or that the master can accept
// the next data during a write
output mast1_wait; // Tells the master to insert wait cycles
// because data can not be accepted/provided
// --------------------------------------
// DMA Engine Signals
// DMA Engine Init & Setup
input de_start; // Start DMA Engine Indicator
input nd; // Next Descriptor Indicator
input [31:0] csr; // Selected Channel CSR
input [31:0] pointer; // Linked List Descriptor pointer
input [31:0] pointer_s; // Previous Pointer
input [31:0] txsz; // Selected Channel Transfer Size
input [31:0] adr0, adr1; // Selected Channel Addresses
input [31:0] am0, am1; // Selected Channel Address Masks
// DMA Engine Register File Update Outputs
output de_csr_we; // Write enable for csr register
output de_txsz_we; // Write enable for txsz register
output de_adr0_we; // Write enable for adr0 register
output de_adr1_we; // Write enable for adr1 register
output ptr_set; // Set Pointer as Valid
output [31:0] de_csr; // Write Data for CSR when loading External Desc.
output [11:0] de_txsz; // Write back data for txsz register
output [31:0] de_adr0; // Write back data for adr0 register
output [31:0] de_adr1; // Write back data for adr1 register
output de_fetch_descr; // Indicates that we are fetching a descriptor
// DMA Engine Control Outputs
output next_ch; // Indicates the DMA Engine is done
output de_ack;
// DMA Abort from RF (software forced abort)
input dma_abort;
// DMA Engine Status
input pause_req;
output paused;
output dma_busy, dma_err, dma_done, dma_done_all;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
parameter [10:0] // synopsys enum state
IDLE = 11'b000_0000_0001,
READ = 11'b000_0000_0010,
WRITE = 11'b000_0000_0100,
UPDATE = 11'b000_0000_1000,
LD_DESC1 = 11'b000_0001_0000,
LD_DESC2 = 11'b000_0010_0000,
LD_DESC3 = 11'b000_0100_0000,
LD_DESC4 = 11'b000_1000_0000,
LD_DESC5 = 11'b001_0000_0000,
WB = 11'b010_0000_0000,
PAUSE = 11'b100_0000_0000;
reg [10:0] /* synopsys enum state */ state, next_state;
// synopsys state_vector state
reg [31:0] mast0_adr, mast1_adr;
reg [29:0] adr0_cnt, adr1_cnt;
wire [29:0] adr0_cnt_next, adr1_cnt_next;
wire [29:0] adr0_cnt_next1, adr1_cnt_next1;
reg adr0_inc, adr1_inc;
reg [8:0] chunk_cnt;
reg chunk_dec;
reg [11:0] tsz_cnt;
reg tsz_dec;
reg de_txsz_we;
reg de_csr_we;
reg de_adr0_we;
reg de_adr1_we;
reg ld_desc_sel;
wire chunk_cnt_is_0_d;
reg chunk_cnt_is_0_r;
wire tsz_cnt_is_0_d;
reg tsz_cnt_is_0_r;
reg read, write;
reg read_r, write_r;
wire rd_ack, wr_ack;
reg rd_ack_r;
reg chunk_0;
wire done;
reg dma_done_d;
reg dma_done_r;
reg dma_abort_r;
reg next_ch;
wire read_hold, write_hold;
reg write_hold_r;
reg [1:0] ptr_adr_low;
reg m0_go;
reg m0_we;
reg ptr_set;
// Aliases
wire a0_inc_en = csr[4]; // Source Address (Adr 0) increment enable
wire a1_inc_en = csr[3]; // Dest. Address (Adr 1) increment enable
wire ptr_valid = pointer[0];
wire use_ed = csr[`WDMA_USE_ED];
reg mast0_drdy_r;
reg paused;
reg de_fetch_descr; // Indicates that we are fetching a descriptor
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
dma_done_r <= #1 dma_done;
// Address Counter 0 (Source Address)
always @(posedge clk)
if(de_start | ptr_set) adr0_cnt <= #1 adr0[31:2];
else
if(adr0_inc & a0_inc_en) adr0_cnt <= #1 adr0_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u0( .clk( clk ),
.in( adr0_cnt ),
.out( adr0_cnt_next1 ) );
assign adr0_cnt_next[1:0] = adr0_cnt_next1[1:0];
assign adr0_cnt_next[2] = am0[4] ? adr0_cnt_next1[2] : adr0_cnt[2];
assign adr0_cnt_next[3] = am0[5] ? adr0_cnt_next1[3] : adr0_cnt[3];
assign adr0_cnt_next[4] = am0[6] ? adr0_cnt_next1[4] : adr0_cnt[4];
assign adr0_cnt_next[5] = am0[7] ? adr0_cnt_next1[5] : adr0_cnt[5];
assign adr0_cnt_next[6] = am0[8] ? adr0_cnt_next1[6] : adr0_cnt[6];
assign adr0_cnt_next[7] = am0[9] ? adr0_cnt_next1[7] : adr0_cnt[7];
assign adr0_cnt_next[8] = am0[10] ? adr0_cnt_next1[8] : adr0_cnt[8];
assign adr0_cnt_next[9] = am0[11] ? adr0_cnt_next1[9] : adr0_cnt[9];
assign adr0_cnt_next[10] = am0[12] ? adr0_cnt_next1[10] : adr0_cnt[10];
assign adr0_cnt_next[11] = am0[13] ? adr0_cnt_next1[11] : adr0_cnt[11];
assign adr0_cnt_next[12] = am0[14] ? adr0_cnt_next1[12] : adr0_cnt[12];
assign adr0_cnt_next[13] = am0[15] ? adr0_cnt_next1[13] : adr0_cnt[13];
assign adr0_cnt_next[14] = am0[16] ? adr0_cnt_next1[14] : adr0_cnt[14];
assign adr0_cnt_next[15] = am0[17] ? adr0_cnt_next1[15] : adr0_cnt[15];
assign adr0_cnt_next[16] = am0[18] ? adr0_cnt_next1[16] : adr0_cnt[16];
assign adr0_cnt_next[17] = am0[19] ? adr0_cnt_next1[17] : adr0_cnt[17];
assign adr0_cnt_next[18] = am0[20] ? adr0_cnt_next1[18] : adr0_cnt[18];
assign adr0_cnt_next[19] = am0[21] ? adr0_cnt_next1[19] : adr0_cnt[19];
assign adr0_cnt_next[20] = am0[22] ? adr0_cnt_next1[20] : adr0_cnt[20];
assign adr0_cnt_next[21] = am0[23] ? adr0_cnt_next1[21] : adr0_cnt[21];
assign adr0_cnt_next[22] = am0[24] ? adr0_cnt_next1[22] : adr0_cnt[22];
assign adr0_cnt_next[23] = am0[25] ? adr0_cnt_next1[23] : adr0_cnt[23];
assign adr0_cnt_next[24] = am0[26] ? adr0_cnt_next1[24] : adr0_cnt[24];
assign adr0_cnt_next[25] = am0[27] ? adr0_cnt_next1[25] : adr0_cnt[25];
assign adr0_cnt_next[26] = am0[28] ? adr0_cnt_next1[26] : adr0_cnt[26];
assign adr0_cnt_next[27] = am0[29] ? adr0_cnt_next1[27] : adr0_cnt[27];
assign adr0_cnt_next[28] = am0[30] ? adr0_cnt_next1[28] : adr0_cnt[28];
assign adr0_cnt_next[29] = am0[31] ? adr0_cnt_next1[29] : adr0_cnt[29];
// Address Counter 1 (Destination Address)
always @(posedge clk)
if(de_start | ptr_set) adr1_cnt <= #1 adr1[31:2];
else
if(adr1_inc & a1_inc_en) adr1_cnt <= #1 adr1_cnt_next;
// 30 Bit Incrementor (registered)
wb_dma_inc30r u1( .clk( clk ),
.in( adr1_cnt ),
.out( adr1_cnt_next1 ) );
assign adr1_cnt_next[1:0] = adr1_cnt_next1[1:0];
assign adr1_cnt_next[2] = am1[4] ? adr1_cnt_next1[2] : adr1_cnt[2];
assign adr1_cnt_next[3] = am1[5] ? adr1_cnt_next1[3] : adr1_cnt[3];
assign adr1_cnt_next[4] = am1[6] ? adr1_cnt_next1[4] : adr1_cnt[4];
assign adr1_cnt_next[5] = am1[7] ? adr1_cnt_next1[5] : adr1_cnt[5];
assign adr1_cnt_next[6] = am1[8] ? adr1_cnt_next1[6] : adr1_cnt[6];
assign adr1_cnt_next[7] = am1[9] ? adr1_cnt_next1[7] : adr1_cnt[7];
assign adr1_cnt_next[8] = am1[10] ? adr1_cnt_next1[8] : adr1_cnt[8];
assign adr1_cnt_next[9] = am1[11] ? adr1_cnt_next1[9] : adr1_cnt[9];
assign adr1_cnt_next[10] = am1[12] ? adr1_cnt_next1[10] : adr1_cnt[10];
assign adr1_cnt_next[11] = am1[13] ? adr1_cnt_next1[11] : adr1_cnt[11];
assign adr1_cnt_next[12] = am1[14] ? adr1_cnt_next1[12] : adr1_cnt[12];
assign adr1_cnt_next[13] = am1[15] ? adr1_cnt_next1[13] : adr1_cnt[13];
assign adr1_cnt_next[14] = am1[16] ? adr1_cnt_next1[14] : adr1_cnt[14];
assign adr1_cnt_next[15] = am1[17] ? adr1_cnt_next1[15] : adr1_cnt[15];
assign adr1_cnt_next[16] = am1[18] ? adr1_cnt_next1[16] : adr1_cnt[16];
assign adr1_cnt_next[17] = am1[19] ? adr1_cnt_next1[17] : adr1_cnt[17];
assign adr1_cnt_next[18] = am1[20] ? adr1_cnt_next1[18] : adr1_cnt[18];
assign adr1_cnt_next[19] = am1[21] ? adr1_cnt_next1[19] : adr1_cnt[19];
assign adr1_cnt_next[20] = am1[22] ? adr1_cnt_next1[20] : adr1_cnt[20];
assign adr1_cnt_next[21] = am1[23] ? adr1_cnt_next1[21] : adr1_cnt[21];
assign adr1_cnt_next[22] = am1[24] ? adr1_cnt_next1[22] : adr1_cnt[22];
assign adr1_cnt_next[23] = am1[25] ? adr1_cnt_next1[23] : adr1_cnt[23];
assign adr1_cnt_next[24] = am1[26] ? adr1_cnt_next1[24] : adr1_cnt[24];
assign adr1_cnt_next[25] = am1[27] ? adr1_cnt_next1[25] : adr1_cnt[25];
assign adr1_cnt_next[26] = am1[28] ? adr1_cnt_next1[26] : adr1_cnt[26];
assign adr1_cnt_next[27] = am1[29] ? adr1_cnt_next1[27] : adr1_cnt[27];
assign adr1_cnt_next[28] = am1[30] ? adr1_cnt_next1[28] : adr1_cnt[28];
assign adr1_cnt_next[29] = am1[31] ? adr1_cnt_next1[29] : adr1_cnt[29];
// Chunk Counter
always @(posedge clk)
if(de_start) chunk_cnt <= #1 txsz[24:16];
else
if(chunk_dec & !chunk_cnt_is_0_r) chunk_cnt <= #1 chunk_cnt - 9'h1;
assign chunk_cnt_is_0_d = (chunk_cnt == 9'h0);
always @(posedge clk)
chunk_cnt_is_0_r <= #1 chunk_cnt_is_0_d;
// Total Size Counter
always @(posedge clk)
if(de_start | ptr_set) tsz_cnt <= #1 txsz[11:0];
else
if(tsz_dec & !tsz_cnt_is_0_r) tsz_cnt <= #1 tsz_cnt - 12'h1;
assign tsz_cnt_is_0_d = (tsz_cnt == 12'h0) & !txsz[15];
always @(posedge clk)
tsz_cnt_is_0_r <= #1 tsz_cnt_is_0_d;
// Counter Control Logic
always @(posedge clk)
chunk_dec <= #1 read & !read_r;
always @(posedge clk)
tsz_dec <= #1 read & !read_r;
//always @(posedge clk)
always @(rd_ack or read_r)
adr0_inc = rd_ack & read_r;
//always @(posedge clk)
always @(wr_ack or write_r)
adr1_inc = wr_ack & write_r;
// Done logic
always @(posedge clk)
chunk_0 <= #1 (txsz[24:16] == 9'h0);
assign done = chunk_0 ? tsz_cnt_is_0_d : (tsz_cnt_is_0_d | chunk_cnt_is_0_d);
assign dma_done = dma_done_d & done;
assign dma_done_all = dma_done_d & (tsz_cnt_is_0_r | (nd & chunk_cnt_is_0_d));
always @(posedge clk)
next_ch <= #1 dma_done;
// Register Update Outputs
assign de_txsz = ld_desc_sel ? mast0_din[11:0] : tsz_cnt;
assign de_adr0 = ld_desc_sel ? mast0_din : {adr0_cnt, 2'b00};
assign de_adr1 = ld_desc_sel ? mast0_din : {adr1_cnt, 2'b00};
assign de_csr = mast0_din;
// Abort logic
always @(posedge clk)
dma_abort_r <= #1 dma_abort | mast0_err | mast1_err;
assign dma_err = dma_abort_r;
assign dma_busy = (state != IDLE);
////////////////////////////////////////////////////////////////////
//
// WISHBONE Interface Logic
//
always @(posedge clk)
read_r <= #1 read;
always @(posedge clk)
write_r <= #1 write;
always @(posedge clk)
rd_ack_r <= #1 read_r;
// Data Path
assign mast0_dout = m0_we ? {20'h0, tsz_cnt} : csr[2] ? mast1_din : mast0_din;
assign mast1_dout = csr[2] ? mast1_din : mast0_din;
// Address Path
always @(posedge clk)
mast0_adr <= #1 m0_go ?
(m0_we ? pointer_s : {pointer[31:4], ptr_adr_low, 2'b00}) :
read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
always @(posedge clk)
mast1_adr <= #1 read ? {adr0_cnt, 2'b00} : {adr1_cnt, 2'b00};
// CTRL
assign write_hold = (read | write) & write_hold_r;
always @(posedge clk)
write_hold_r <= #1 read | write;
assign read_hold = done ? read : (read | write);
assign mast0_go = (!csr[2] & read_hold) | (!csr[1] & write_hold) | m0_go;
assign mast1_go = ( csr[2] & read_hold) | ( csr[1] & write_hold);
assign mast0_we = m0_go ? m0_we : (!csr[1] & write);
assign mast1_we = csr[1] & write;
assign rd_ack = (csr[2] ? mast1_drdy : mast0_drdy);
assign wr_ack = (csr[1] ? mast1_drdy : mast0_drdy);
assign mast0_wait = !((!csr[2] & read) | (!csr[1] & write)) & !m0_go;
assign mast1_wait = !(( csr[2] & read) | ( csr[1] & write));
always @(posedge clk)
mast0_drdy_r <= #1 mast0_drdy;
assign de_ack = dma_done;
////////////////////////////////////////////////////////////////////
//
// State Machine
//
always @(posedge clk or negedge rst)
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
always @(state or pause_req or dma_abort_r or de_start or rd_ack or wr_ack or
done or ptr_valid or use_ed or mast0_drdy or mast0_drdy_r or csr or nd)
begin
next_state = state; // Default keep state
read = 1'b0;
write = 1'b0;
dma_done_d = 1'b0;
de_csr_we = 1'b0;
de_txsz_we = 1'b0;
de_adr0_we = 1'b0;
de_adr1_we = 1'b0;
de_fetch_descr = 1'b0;
m0_go = 1'b0;
m0_we = 1'b0;
ptr_adr_low = 2'h0;
ptr_set = 1'b0;
ld_desc_sel = 1'b0;
paused = 1'b0;
case(state) // synopsys parallel_case full_case
IDLE:
begin
if(pause_req) next_state = PAUSE;
else
if(de_start & !csr[`WDMA_ERR])
begin
if(use_ed & !ptr_valid) next_state = LD_DESC1;
else next_state = READ;
end
end
PAUSE:
begin
paused = 1'b1;
if(!pause_req) next_state = IDLE;
end
READ: // Read From Source
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!rd_ack) read = 1'b1;
else
begin
write = 1'b1;
next_state = WRITE;
end
end
WRITE: // Write To Destination
begin
if(dma_abort_r) next_state = UPDATE;
else
if(!wr_ack) write = 1'b1;
else
begin
if(done) next_state = UPDATE;
else
begin
read = 1'b1;
next_state = READ;
end
end
end
UPDATE: // Update Registers
begin
dma_done_d = 1'b1;
de_txsz_we = 1'b1;
de_adr0_we = 1'b1;
de_adr1_we = 1'b1;
if(use_ed & csr[`WDMA_WRB] & nd)
begin
m0_we = 1'b1;
m0_go = 1'b1;
next_state = WB;
end
else next_state = IDLE;
end
WB:
begin
m0_we = 1'b1;
if(mast0_drdy)
begin
next_state = IDLE;
end
else m0_go = 1'b1;
end
LD_DESC1: // Load Descriptor from memory to registers
begin
ptr_adr_low = 2'h0;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
de_csr_we = 1'b1;
de_txsz_we = 1'b1;
de_fetch_descr = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h1;
next_state = LD_DESC2;
end
end
LD_DESC2:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_csr_we = 1'b1;
if(mast0_drdy_r) de_txsz_we = 1'b1;
ptr_adr_low = 2'h1;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h2;
next_state = LD_DESC3;
end
end
LD_DESC3:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr0_we = 1'b1;
ptr_adr_low = 2'h2;
ld_desc_sel = 1'b1;
m0_go = 1'b1;
if(mast0_drdy)
begin
ptr_adr_low = 2'h3;
next_state = LD_DESC4;
end
end
LD_DESC4:
begin
de_fetch_descr = 1'b1;
if(mast0_drdy_r) de_adr1_we = 1'b1;
ptr_adr_low = 2'h3;
ld_desc_sel = 1'b1;
if(mast0_drdy)
begin
next_state = LD_DESC5;
end
else m0_go = 1'b1;
end
LD_DESC5:
begin
de_fetch_descr = 1'b1;
ptr_set = 1'b1;
next_state = READ;
end
endcase
end
endmodule |
module wb_dma_wb_slv(clk, rst,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
// This is the register File Interface
slv_adr, slv_din, slv_dout, slv_re, slv_we,
// Pass through Interface
pt_sel, slv_pt_out, slv_pt_in
);
parameter rf_addr = 0;
input clk, rst;
// --------------------------------------
// WISHBONE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
output wb_rty_o;
// This is the register File Interface
output [31:0] slv_adr; // Slave Address
input [31:0] slv_din; // Slave Input Data
output [31:0] slv_dout; // Slave Output Data
output slv_re; // Slave Read Enable
output slv_we; // Slave Write Enable
// Pass through Interface
output pt_sel; // Pass Through Mode Active
output [70:0] slv_pt_out; // Grouped WISHBONE out signals
input [34:0] slv_pt_in; // Grouped WISHBONE in signals
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg slv_re, slv_we;
wire rf_sel;
reg rf_ack;
reg [31:0] slv_adr, slv_dout;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign rf_sel = `WDMA_REG_SEL ;
////////////////////////////////////////////////////////////////////
//
// Pass Through Logic
//
//assign pt_sel = !rf_sel;
assign pt_sel = !rf_sel & wb_cyc_i;
assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i};
assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in :
{slv_din, rf_ack, 1'b0, 1'b0};
////////////////////////////////////////////////////////////////////
//
// Register File Logic
//
always @(posedge clk)
slv_adr <= #1 wb_addr_i;
always @(posedge clk)
slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re;
always @(posedge clk)
slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack;
always @(posedge clk)
slv_dout <= #1 wb_data_i;
always @(posedge clk)
rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ;
endmodule |
module wb_dma_pri_enc_sub(valid, pri_in, pri_out);
parameter [3:0] ch_conf = 4'b0000;
parameter [1:0] pri_sel = 2'd0;
input valid;
input [2:0] pri_in;
output [7:0] pri_out;
wire [7:0] pri_out;
reg [7:0] pri_out_d;
reg [7:0] pri_out_d0;
reg [7:0] pri_out_d1;
reg [7:0] pri_out_d2;
assign pri_out = ch_conf[0] ? pri_out_d : 8'h0;
// Select Configured Priority
always @(pri_sel or pri_out_d0 or pri_out_d1 or pri_out_d2)
case(pri_sel) // synopsys parallel_case full_case
2'd0: pri_out_d = pri_out_d0;
2'd1: pri_out_d = pri_out_d1;
2'd2: pri_out_d = pri_out_d2;
endcase
// 8 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d2 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d2 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d2 = 8'b0000_0100;
else
if(pri_in==3'h3) pri_out_d2 = 8'b0000_1000;
else
if(pri_in==3'h4) pri_out_d2 = 8'b0001_0000;
else
if(pri_in==3'h5) pri_out_d2 = 8'b0010_0000;
else
if(pri_in==3'h6) pri_out_d2 = 8'b0100_0000;
else pri_out_d2 = 8'b1000_0000;
// 4 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d1 = 8'b0000_0001;
else
if(pri_in==3'h1) pri_out_d1 = 8'b0000_0010;
else
if(pri_in==3'h2) pri_out_d1 = 8'b0000_0100;
else pri_out_d1 = 8'b0000_1000;
// 2 Priority Levels
always @(valid or pri_in)
if(!valid) pri_out_d0 = 8'b0000_0001;
else
if(pri_in==3'h0) pri_out_d0 = 8'b0000_0001;
else pri_out_d0 = 8'b0000_0010;
endmodule |
module div_su(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width-1:0] z; // divident
input [d_width-1:0] d; // divisor
output [d_width :0] q; // quotient
output [d_width-1:0] s; // remainder
output div0;
output ovf;
reg [d_width :0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// variables
//
reg [z_width -1:0] iz;
reg [d_width -1:0] id;
reg [d_width +1:0] spipe;
wire [d_width -1:0] iq, is;
wire idiv0, iovf;
//
// module body
//
// delay d
always @(posedge clk)
if (ena)
id <= #1 d;
// check z, take abs value
always @(posedge clk)
if (ena)
if (z[z_width-1])
iz <= #1 ~z +1'h1;
else
iz <= #1 z;
// generate spipe (sign bit pipe)
integer n;
always @(posedge clk)
if(ena)
begin
spipe[0] <= #1 z[z_width-1];
for(n=1; n <= d_width+1; n=n+1)
spipe[n] <= #1 spipe[n-1];
end
// hookup non-restoring divider
div_uu #(z_width, d_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(is),
.div0(idiv0),
.ovf(iovf)
);
// correct divider results if 'd' was negative
always @(posedge clk)
if(ena)
if(spipe[d_width+1])
begin
q <= #1 (~iq) + 1'h1;
s <= #1 (~is) + 1'h1;
end
else
begin
q <= #1 {1'b0, iq};
s <= #1 {1'b0, is};
end
// delay flags same as results
always @(posedge clk)
if(ena)
begin
div0 <= #1 idiv0;
ovf <= #1 iovf;
end
endmodule |
module dctub(clk, ena, ddgo, x, y, ddin,
dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 3'h0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go strobe
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout0, dout1, dout2, dout3, dout4, dout5, dout6, dout7;
//
// module body
//
// Hookup DCT units
dctu #(coef_width, di_width, v, 3'h0)
dct_unit_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout0)
);
dctu #(coef_width, di_width, v, 3'h1)
dct_unit_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout1)
);
dctu #(coef_width, di_width, v, 3'h2)
dct_unit_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout2)
);
dctu #(coef_width, di_width, v, 3'h3)
dct_unit_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout3)
);
dctu #(coef_width, di_width, v, 3'h4)
dct_unit_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout4)
);
dctu #(coef_width, di_width, v, 3'h5)
dct_unit_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout5)
);
dctu #(coef_width, di_width, v, 3'h6)
dct_unit_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout6)
);
dctu #(coef_width, di_width, v, 3'h7)
dct_unit_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(x),
.y(y),
.ddin(ddin),
.dout(dout7)
);
endmodule |
module jpeg_encoder(
clk,
ena,
rst,
dstrb,
din,
qnt_val,
qnt_cnt,
size,
rlen,
amp,
douten
);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// Tests with real continuous and non-continous tone image data //
// have shown that when using the examples quantization tables //
// from ITU-T.81 annex K 10bit coefficients are sufficient to //
// comply to the ITU-T.83 specs. Compliance tests have been met //
// using as little as 9bit coefficients. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8; // no function yet
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
input [7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // quantization value address
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
//
// variables
//
wire fdct_doe, qnr_doe;
wire [11:0] fdct_dout;
reg [11:0] dfdct_dout;
wire [10:0] qnr_dout;
reg dqnr_doe;
//
// module body
//
// Hookup FDCT & ZigZag module
fdct #(coef_width, di_width, 12)
fdct_zigzag(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout(fdct_dout),
.douten(fdct_doe)
);
// delay 'fdct_dout' => wait for synchronous quantization RAM/ROM
always @(posedge clk)
if(ena)
dfdct_dout <= #1 fdct_dout;
// Hookup QNR (Quantization and Rounding) unit
jpeg_qnr
qnr(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(fdct_doe),
.din(dfdct_dout),
.qnt_val(qnt_val),
.qnt_cnt(qnt_cnt),
.dout(qnr_dout),
.douten(qnr_doe)
);
// delay douten 1 clk_cycle => account for delayed fdct_res & qnt_val
always @(posedge clk)
if(ena)
dqnr_doe <= #1 qnr_doe;
//
// TODO: Insert DC differential generator here.
//
wire [11:0] dc_diff_dout = {qnr_dout[10], qnr_dout};
wire dc_diff_doe = dqnr_doe;
// Hookup Run Length Encoder
jpeg_rle
rle(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dc_diff_doe),
.din(dc_diff_dout),
.size(size),
.rlen(rlen),
.amp(amp),
.douten(douten),
.bstart()
);
endmodule |
module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input dstrb;
input [11:0] din; // data input
output [ 3:0] size; // size
output [ 3:0] rlen; // run-length
output [11:0] amp; // amplitude
output douten; // data output enable
output bstart; // block start
//
// variables
//
wire [ 3:0] rle_rlen, rz1_rlen, rz2_rlen, rz3_rlen, rz4_rlen;
wire [ 3:0] rle_size, rz1_size, rz2_size, rz3_size, rz4_size;
wire [11:0] rle_amp, rz1_amp, rz2_amp, rz3_amp, rz4_amp;
wire rle_den, rz1_den, rz2_den, rz3_den, rz4_den;
wire rle_dc, rz1_dc, rz2_dc, rz3_dc, rz4_dc;
//
// module body
//
reg ddstrb;
always @(posedge clk)
ddstrb <= #1 dstrb;
// generate run-length encoded signals
jpeg_rle1 rle(
.clk(clk),
.rst(rst),
.ena(ena),
.go(ddstrb),
.din(din),
.rlen(rle_rlen),
.size(rle_size),
.amp(rle_amp),
.den(rle_den),
.dcterm(rle_dc)
);
// Find (15,0) (0,0) sequences and replace by (0,0)
// There can be max. 4 (15,0) sequences in a row
// step1
jpeg_rzs rz1(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rle_rlen),
.sizei(rle_size),
.ampi(rle_amp),
.deni(rle_den),
.dci(rle_dc),
.rleno(rz1_rlen),
.sizeo(rz1_size),
.ampo(rz1_amp),
.deno(rz1_den),
.dco(rz1_dc)
);
// step2
jpeg_rzs rz2(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz1_rlen),
.sizei(rz1_size),
.ampi(rz1_amp),
.deni(rz1_den),
.dci(rz1_dc),
.rleno(rz2_rlen),
.sizeo(rz2_size),
.ampo(rz2_amp),
.deno(rz2_den),
.dco(rz2_dc)
);
// step3
jpeg_rzs rz3(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz2_rlen),
.sizei(rz2_size),
.ampi(rz2_amp),
.deni(rz2_den),
.dci(rz2_dc),
.rleno(rz3_rlen),
.sizeo(rz3_size),
.ampo(rz3_amp),
.deno(rz3_den),
.dco(rz3_dc)
);
// step4
jpeg_rzs rz4(
.clk(clk),
.rst(rst),
.ena(ena),
.rleni(rz3_rlen),
.sizei(rz3_size),
.ampi(rz3_amp),
.deni(rz3_den),
.dci(rz3_dc),
.rleno(rz4_rlen),
.sizeo(rz4_size),
.ampo(rz4_amp),
.deno(rz4_den),
.dco(rz4_dc)
);
// assign outputs
assign rlen = rz4_rlen;
assign size = rz4_size;
assign amp = rz4_amp;
assign douten = rz4_den;
assign bstart = rz4_dc;
endmodule |
module fdct(clk, ena, rst, dstrb, din, dout, douten);
//
// parameters
//
////////////////////////////////////////////////////////////////////
// //
// ITU-T.81, ITU-T.83 & Coefficient resolution notes //
// //
////////////////////////////////////////////////////////////////////
// //
// Worst case error (all input values -128) is //
// zero (i.e. no errors) when using 15bit coefficients //
// //
// Using less bits for the coefficients produces a biterror //
// approx. equal to (15 - used_coefficient-bits). //
// i.e. 14bit coefficients, errors in dout-bit[0] only //
// 13bit coefficients, errors in dout-bits[1:0] //
// 12bit coefficients, errors in dout-bits[2:0] etc. //
// Tests with real non-continous tone image data have shown that //
// even when using 13bit coefficients errors remain in the lsb //
// only (i.e. dout-bit[0] //
// //
// The amount of coefficient-bits needed is dependent on the //
// desired quality. //
// The JPEG-standard compliance specs.(ITU-T.83) prescribe //
// that the output of the combined DCT AND Quantization unit //
// shall not exceed 1 for the desired quality. //
// //
// This means for high quantization levels, lesser bits //
// for the DCT unit can be used. //
// //
// Looking at the recommended "quantization tables for generic //
// compliance testing of DCT-based processes" (ITU-T.83 annex B) //
// it can be noticed that relatively large quantization values //
// are being used. Errors in the lower-order bits should //
// therefore not be visible. //
// For certain applications some of the lower-order bits could //
// actually be discarded. When looking at the luminance and //
// chrominance example quantization tables (ITU-T.81 annex K) //
// it can be seen that the smallest quantization value is ten //
// (qnt_val_min = 10). This means that the lowest 2bits can be //
// discarded (set to zero '0') without having any effect on the //
// final result. In this example 11 bit or 12 bit coefficients //
// would be sufficient. //
// //
////////////////////////////////////////////////////////////////////
parameter coef_width = 11;
parameter di_width = 8;
parameter do_width = 12;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width-1:0] din;
output [do_width-1:0] dout;
output douten; // data-out enable
//
// variables
//
wire doe;
wire [do_width -1:0] // results from DCT module
res00, res01, res02, res03, res04, res05, res06, res07,
res10, res11, res12, res13, res14, res15, res16, res17,
res20, res21, res22, res23, res24, res25, res26, res27,
res30, res31, res32, res33, res34, res35, res36, res37,
res40, res41, res42, res43, res44, res45, res46, res47,
res50, res51, res52, res53, res54, res55, res56, res57,
res60, res61, res62, res63, res64, res65, res66, res67,
res70, res71, res72, res73, res74, res75, res76, res77;
//
// module body
//
// Hookup DCT module
dct #(coef_width, di_width, do_width)
dct_mod(
.clk(clk),
.ena(ena),
.rst(rst),
.dstrb(dstrb),
.din(din),
.dout_00(res00),
.dout_01(res01),
.dout_02(res02),
.dout_03(res03),
.dout_04(res04),
.dout_05(res05),
.dout_06(res06),
.dout_07(res07),
.dout_10(res10),
.dout_11(res11),
.dout_12(res12),
.dout_13(res13),
.dout_14(res14),
.dout_15(res15),
.dout_16(res16),
.dout_17(res17),
.dout_20(res20),
.dout_21(res21),
.dout_22(res22),
.dout_23(res23),
.dout_24(res24),
.dout_25(res25),
.dout_26(res26),
.dout_27(res27),
.dout_30(res30),
.dout_31(res31),
.dout_32(res32),
.dout_33(res33),
.dout_34(res34),
.dout_35(res35),
.dout_36(res36),
.dout_37(res37),
.dout_40(res40),
.dout_41(res41),
.dout_42(res42),
.dout_43(res43),
.dout_44(res44),
.dout_45(res45),
.dout_46(res46),
.dout_47(res47),
.dout_50(res50),
.dout_51(res51),
.dout_52(res52),
.dout_53(res53),
.dout_54(res54),
.dout_55(res55),
.dout_56(res56),
.dout_57(res57),
.dout_60(res60),
.dout_61(res61),
.dout_62(res62),
.dout_63(res63),
.dout_64(res64),
.dout_65(res65),
.dout_66(res66),
.dout_67(res67),
.dout_70(res70),
.dout_71(res71),
.dout_72(res72),
.dout_73(res73),
.dout_74(res74),
.dout_75(res75),
.dout_76(res76),
.dout_77(res77),
.douten(doe)
);
// Hookup ZigZag unit
zigzag zigzag_mod(
.clk(clk),
.ena(ena),
.dstrb(doe),
.din_00(res00),
.din_01(res01),
.din_02(res02),
.din_03(res03),
.din_04(res04),
.din_05(res05),
.din_06(res06),
.din_07(res07),
.din_10(res10),
.din_11(res11),
.din_12(res12),
.din_13(res13),
.din_14(res14),
.din_15(res15),
.din_16(res16),
.din_17(res17),
.din_20(res20),
.din_21(res21),
.din_22(res22),
.din_23(res23),
.din_24(res24),
.din_25(res25),
.din_26(res26),
.din_27(res27),
.din_30(res30),
.din_31(res31),
.din_32(res32),
.din_33(res33),
.din_34(res34),
.din_35(res35),
.din_36(res36),
.din_37(res37),
.din_40(res40),
.din_41(res41),
.din_42(res42),
.din_43(res43),
.din_44(res44),
.din_45(res45),
.din_46(res46),
.din_47(res47),
.din_50(res50),
.din_51(res51),
.din_52(res52),
.din_53(res53),
.din_54(res54),
.din_55(res55),
.din_56(res56),
.din_57(res57),
.din_60(res60),
.din_61(res61),
.din_62(res62),
.din_63(res63),
.din_64(res64),
.din_65(res65),
.din_66(res66),
.din_67(res67),
.din_70(res70),
.din_71(res71),
.din_72(res72),
.din_73(res73),
.din_74(res74),
.din_75(res75),
.din_76(res76),
.din_77(res77),
.dout(dout),
.douten(douten)
);
endmodule |
module jpeg_qnr(clk, ena, rst, dstrb, din, qnt_val, qnt_cnt, dout, douten);
//
// parameters
//
parameter d_width = 12;
parameter z_width = 2 * d_width;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input rst; // asynchronous active low reset
input dstrb; // present dstrb 1clk cycle before din
input [d_width-1:0] din; // data input
input [ 7:0] qnt_val; // quantization value
output [ 5:0] qnt_cnt; // sample number (get quantization value qnt_cnt)
output [10:0] dout; // data output
output douten;
//
// variables
//
wire [z_width-1:0] iz; // intermediate divident value
wire [d_width-1:0] id; // intermediate dividor value
wire [d_width :0] iq; // intermediate result divider
reg [d_width :0] rq; // rounded q-value
reg [d_width+3:0] dep;// data enable pipeline
// generate sample counter
reg [5:0] qnt_cnt;
wire dcnt = &qnt_cnt;
always @(posedge clk or negedge rst)
if (~rst)
qnt_cnt <= #1 6'h0;
else if (dstrb)
qnt_cnt <= #1 6'h0;
else if (ena)
qnt_cnt <= #1 qnt_cnt + 6'h1;
// generate intermediate dividor/divident values
assign id = { {(d_width - 8){1'b0}}, qnt_val};
assign iz = { {(z_width - d_width){din[d_width-1]}}, din};
// hookup division unit
div_su #(z_width)
divider (
.clk(clk),
.ena(ena),
.z(iz),
.d(id),
.q(iq),
.s(),
.div0(),
.ovf()
);
// round result to the nearest integer
always @(posedge clk)
if (ena)
if (iq[0])
if (iq[d_width])
rq <= #1 iq - 1'h1;
else
rq <= #1 iq + 1'h1;
else
rq <= #1 iq;
// assign dout signal
assign dout = rq[d_width -1: d_width-11];
// generate data-out enable signal
// This is a pipeline, data is not dependant on sample-count
integer n;
always @(posedge clk or negedge rst)
if (!rst)
dep <= #1 0;
else if(ena)
begin
dep[0] <= #1 dstrb;
for (n=1; n <= d_width +3; n = n +1)
dep[n] <= #1 dep[n-1];
end
assign douten = dep[d_width +3];
endmodule |
module dctu(clk, ena, ddgo, x, y, ddin, dout);
parameter coef_width = 16;
parameter di_width = 8;
parameter [2:0] v = 0;
parameter [2:0] u = 0;
//
// inputs & outputs
//
input clk;
input ena;
input ddgo; // double delayed go signal
input [2:0] x, y;
input [di_width:1] ddin; // delayed data input
output [11:0] dout;
//
// variables
//
reg [ 31:0] coef;
wire [coef_width +10:0] result;
`include "dct_cos_table.v"
//
// module body
//
// hookup cosine-table
always @(posedge clk)
if(ena)
coef <= #1 dct_cos_table(x, y, u, v);
// hookup dct-mac unit
dct_mac #(8, coef_width)
macu (
.clk(clk),
.ena(ena),
.dclr(ddgo),
.din(ddin),
.coef( coef[31:31 -coef_width +1] ),
.result(result)
);
assign dout = result[coef_width +10: coef_width -1];
endmodule |
module dct(
clk,
ena,
rst,
dstrb,
din,
dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77,
douten
);
//
// parameters
//
// Worst case errors (Din = 64* -128) remain in decimal bit
// when using 13bit coefficients
//
// For ultra-high
parameter coef_width = 11;
parameter di_width = 8;
parameter do_width = 12;
//
// inputs & outputs
//
input clk;
input ena;
input rst; // active low asynchronous reset
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [di_width:1] din;
output [do_width:1]
dout_00, dout_01, dout_02, dout_03, dout_04, dout_05, dout_06, dout_07,
dout_10, dout_11, dout_12, dout_13, dout_14, dout_15, dout_16, dout_17,
dout_20, dout_21, dout_22, dout_23, dout_24, dout_25, dout_26, dout_27,
dout_30, dout_31, dout_32, dout_33, dout_34, dout_35, dout_36, dout_37,
dout_40, dout_41, dout_42, dout_43, dout_44, dout_45, dout_46, dout_47,
dout_50, dout_51, dout_52, dout_53, dout_54, dout_55, dout_56, dout_57,
dout_60, dout_61, dout_62, dout_63, dout_64, dout_65, dout_66, dout_67,
dout_70, dout_71, dout_72, dout_73, dout_74, dout_75, dout_76, dout_77;
output douten; // data-out enable
reg douten;
//
// variables
//
reg go, dgo, ddgo, ddcnt, dddcnt;
reg [di_width:1] ddin;
//
// module body
//
// generate sample counter
reg [5:0] sample_cnt;
wire dcnt = &sample_cnt;
always @(posedge clk or negedge rst)
if (~rst)
sample_cnt <= #1 6'h0;
else if (ena)
if(dstrb)
sample_cnt <= #1 6'h0;
else if(~dcnt)
sample_cnt <= #1 sample_cnt + 6'h1;
// internal signals
always @(posedge clk or negedge rst)
if (~rst)
begin
go <= #1 1'b0;
dgo <= #1 1'b0;
ddgo <= #1 1'b0;
ddin <= #1 0;
douten <= #1 1'b0;
ddcnt <= #1 1'b1;
dddcnt <= #1 1'b1;
end
else if (ena)
begin
go <= #1 dstrb;
dgo <= #1 go;
ddgo <= #1 dgo;
ddin <= #1 din;
ddcnt <= #1 dcnt;
dddcnt <= #1 ddcnt;
douten <= #1 ddcnt & ~dddcnt;
end
// Hookup DCT units
// V = 0
dctub #(coef_width, di_width, 3'h0)
dct_block_0 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_00), // (U,V) = (0,0)
.dout1(dout_01), // (U,V) = (0,1)
.dout2(dout_02), // (U,V) = (0,2)
.dout3(dout_03), // (U,V) = (0,3)
.dout4(dout_04), // (U,V) = (0,4)
.dout5(dout_05), // (U,V) = (0,5)
.dout6(dout_06), // (U,V) = (0,6)
.dout7(dout_07) // (U,V) = (0,7)
);
// V = 1
dctub #(coef_width, di_width, 3'h1)
dct_block_1 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_10), // (U,V) = (1,0)
.dout1(dout_11), // (U,V) = (1,1)
.dout2(dout_12), // (U,V) = (1,2)
.dout3(dout_13), // (U,V) = (1,3)
.dout4(dout_14), // (U,V) = (1,4)
.dout5(dout_15), // (U,V) = (1,5)
.dout6(dout_16), // (U,V) = (1,6)
.dout7(dout_17) // (U,V) = (1,7)
);
// V = 2
dctub #(coef_width, di_width, 3'h2)
dct_block_2 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_20), // (U,V) = (2,0)
.dout1(dout_21), // (U,V) = (2,1)
.dout2(dout_22), // (U,V) = (2,2)
.dout3(dout_23), // (U,V) = (2,3)
.dout4(dout_24), // (U,V) = (2,4)
.dout5(dout_25), // (U,V) = (2,5)
.dout6(dout_26), // (U,V) = (2,6)
.dout7(dout_27) // (U,V) = (2,7)
);
// V = 3
dctub #(coef_width, di_width, 3'h3)
dct_block_3 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_30), // (U,V) = (3,0)
.dout1(dout_31), // (U,V) = (3,1)
.dout2(dout_32), // (U,V) = (3,2)
.dout3(dout_33), // (U,V) = (3,3)
.dout4(dout_34), // (U,V) = (3,4)
.dout5(dout_35), // (U,V) = (3,5)
.dout6(dout_36), // (U,V) = (3,6)
.dout7(dout_37) // (U,V) = (3,7)
);
// V = 4
dctub #(coef_width, di_width, 3'h4)
dct_block_4 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_40), // (U,V) = (4,0)
.dout1(dout_41), // (U,V) = (4,1)
.dout2(dout_42), // (U,V) = (4,2)
.dout3(dout_43), // (U,V) = (4,3)
.dout4(dout_44), // (U,V) = (4,4)
.dout5(dout_45), // (U,V) = (4,5)
.dout6(dout_46), // (U,V) = (4,6)
.dout7(dout_47) // (U,V) = (4,7)
);
// V = 5
dctub #(coef_width, di_width, 3'h5)
dct_block_5 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_50), // (U,V) = (5,0)
.dout1(dout_51), // (U,V) = (5,1)
.dout2(dout_52), // (U,V) = (5,2)
.dout3(dout_53), // (U,V) = (5,3)
.dout4(dout_54), // (U,V) = (5,4)
.dout5(dout_55), // (U,V) = (5,5)
.dout6(dout_56), // (U,V) = (5,6)
.dout7(dout_57) // (U,V) = (5,7)
);
// V = 6
dctub #(coef_width, di_width, 3'h6)
dct_block_6 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_60), // (U,V) = (6,0)
.dout1(dout_61), // (U,V) = (6,1)
.dout2(dout_62), // (U,V) = (6,2)
.dout3(dout_63), // (U,V) = (6,3)
.dout4(dout_64), // (U,V) = (6,4)
.dout5(dout_65), // (U,V) = (6,5)
.dout6(dout_66), // (U,V) = (6,6)
.dout7(dout_67) // (U,V) = (6,7)
);
// V = 7
dctub #(coef_width, di_width, 3'h7)
dct_block_7 (
.clk(clk),
.ena(ena),
.ddgo(ddgo),
.x(sample_cnt[2:0]),
.y(sample_cnt[5:3]),
.ddin(ddin),
.dout0(dout_70), // (U,V) = (7,0)
.dout1(dout_71), // (U,V) = (7,1)
.dout2(dout_72), // (U,V) = (7,2)
.dout3(dout_73), // (U,V) = (7,3)
.dout4(dout_74), // (U,V) = (7,4)
.dout5(dout_75), // (U,V) = (7,5)
.dout6(dout_76), // (U,V) = (7,6)
.dout7(dout_77) // (U,V) = (7,7)
);
endmodule |
module ac97_cra(clk, rst,
crac_we, crac_din, crac_out,
crac_wr_done, crac_rd_done,
valid, out_slt1, out_slt2,
in_slt2,
crac_valid, crac_wr
);
input clk, rst;
input crac_we;
output [15:0] crac_din;
input [31:0] crac_out;
output crac_wr_done, crac_rd_done;
input valid;
output [19:0] out_slt1;
output [19:0] out_slt2;
input [19:0] in_slt2;
output crac_valid;
output crac_wr;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg crac_wr;
reg crac_rd;
reg crac_rd_done;
reg [15:0] crac_din;
reg crac_we_r;
reg valid_r;
wire valid_ne;
wire valid_pe;
reg rdd1, rdd2, rdd3;
////////////////////////////////////////////////////////////////////
//
// Codec Register Data Path
//
// Control
assign out_slt1[19] = crac_out[31];
assign out_slt1[18:12] = crac_out[22:16];
assign out_slt1[11:0] = 12'h0;
// Write Data
assign out_slt2[19:4] = crac_out[15:0];
assign out_slt2[3:0] = 4'h0;
// Read Data
always @(posedge clk or negedge rst)
begin
if(!rst) crac_din <= #1 16'h0;
else
if(crac_rd_done) crac_din <= #1 in_slt2[19:4];
end
////////////////////////////////////////////////////////////////////
//
// Codec Register Access Tracking
//
assign crac_valid = crac_wr | crac_rd;
always @(posedge clk)
crac_we_r <= #1 crac_we;
always @(posedge clk or negedge rst)
if(!rst) crac_wr <= #1 1'b0;
else
if(crac_we_r & !crac_out[31]) crac_wr <= #1 1'b1;
else
if(valid_ne) crac_wr <= #1 1'b0;
assign crac_wr_done = crac_wr & valid_ne;
always @(posedge clk or negedge rst)
if(!rst) crac_rd <= #1 1'b0;
else
if(crac_we_r & crac_out[31]) crac_rd <= #1 1'b1;
else
if(rdd1 & valid_pe) crac_rd <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd1 <= #1 1'b0;
else
if(crac_rd & valid_ne) rdd1 <= #1 1'b1;
else
if(!crac_rd) rdd1 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd2 <= #1 1'b0;
else
if( (crac_rd & valid_ne) | (!rdd3 & rdd2) ) rdd2 <= #1 1'b1;
else
if(crac_rd_done) rdd2 <= #1 1'b0;
always @(posedge clk or negedge rst)
if(!rst) rdd3 <= #1 1'b0;
else
if(rdd2 & valid_pe) rdd3 <= #1 1'b1;
else
if(crac_rd_done) rdd3 <= #1 1'b0;
always @(posedge clk)
crac_rd_done <= #1 rdd3 & valid_pe;
always @(posedge clk)
valid_r <= #1 valid;
assign valid_ne = !valid & valid_r;
assign valid_pe = valid & !valid_r;
endmodule |
module ac97_rst(clk, rst, rst_force, ps_ce, ac97_rst_);
input clk, rst;
input rst_force;
output ps_ce;
output ac97_rst_;
reg ac97_rst_;
reg [2:0] cnt;
wire ce;
wire to;
reg [5:0] ps_cnt;
wire ps_ce;
always @(posedge clk or negedge rst)
if(!rst) ac97_rst_ <= #1 0;
else
if(rst_force) ac97_rst_ <= #1 0;
else
if(to) ac97_rst_ <= #1 1;
assign to = (cnt == `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 0;
else
if(rst_force) cnt <= #1 0;
else
if(ce) cnt <= #1 cnt + 1;
assign ce = ps_ce & (cnt != `AC97_RST_DEL);
always @(posedge clk or negedge rst)
if(!rst) ps_cnt <= #1 0;
else
if(ps_ce | rst_force) ps_cnt <= #1 0;
else ps_cnt <= #1 ps_cnt + 1;
assign ps_ce = (ps_cnt == `AC97_250_PS);
endmodule |
module ac97_sout(clk, rst,
so_ld, slt0, slt1, slt2, slt3, slt4,
slt6, slt7, slt8, slt9,
sdata_out
);
input clk, rst;
// --------------------------------------
// Misc Signals
input so_ld;
input [15:0] slt0;
input [19:0] slt1;
input [19:0] slt2;
input [19:0] slt3;
input [19:0] slt4;
input [19:0] slt6;
input [19:0] slt7;
input [19:0] slt8;
input [19:0] slt9;
// --------------------------------------
// AC97 Codec Interface
output sdata_out;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire sdata_out;
reg [15:0] slt0_r;
reg [19:0] slt1_r;
reg [19:0] slt2_r;
reg [19:0] slt3_r;
reg [19:0] slt4_r;
reg [19:0] slt5_r;
reg [19:0] slt6_r;
reg [19:0] slt7_r;
reg [19:0] slt8_r;
reg [19:0] slt9_r;
reg [19:0] slt10_r;
reg [19:0] slt11_r;
reg [19:0] slt12_r;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
assign sdata_out = slt0_r[15];
always @(posedge clk)
if(so_ld) slt0_r <= #1 slt0;
else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
always @(posedge clk)
if(so_ld) slt1_r <= #1 slt1;
else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
always @(posedge clk)
if(so_ld) slt2_r <= #1 slt2;
else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
always @(posedge clk)
if(so_ld) slt3_r <= #1 slt3;
else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
always @(posedge clk)
if(so_ld) slt4_r <= #1 slt4;
else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
always @(posedge clk)
if(so_ld) slt5_r <= #1 20'h0;
else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
always @(posedge clk)
if(so_ld) slt6_r <= #1 slt6;
else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
always @(posedge clk)
if(so_ld) slt7_r <= #1 slt7;
else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
always @(posedge clk)
if(so_ld) slt8_r <= #1 slt8;
else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
always @(posedge clk)
if(so_ld) slt9_r <= #1 slt9;
else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
always @(posedge clk)
if(so_ld) slt10_r <= #1 20'h0;
else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
always @(posedge clk)
if(so_ld) slt11_r <= #1 20'h0;
else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
always @(posedge clk)
if(so_ld) slt12_r <= #1 20'h0;
else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
endmodule |
module ac97_sin(clk, rst,
out_le, slt0, slt1, slt2, slt3, slt4,
slt6,
sdata_in
);
input clk, rst;
// --------------------------------------
// Misc Signals
input [5:0] out_le;
output [15:0] slt0;
output [19:0] slt1;
output [19:0] slt2;
output [19:0] slt3;
output [19:0] slt4;
output [19:0] slt6;
// --------------------------------------
// AC97 Codec Interface
input sdata_in;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg sdata_in_r;
reg [19:0] sr;
reg [15:0] slt0;
reg [19:0] slt1;
reg [19:0] slt2;
reg [19:0] slt3;
reg [19:0] slt4;
reg [19:0] slt6;
////////////////////////////////////////////////////////////////////
//
// Output Registers
//
always @(posedge clk)
if(out_le[0]) slt0 <= #1 sr[15:0];
always @(posedge clk)
if(out_le[1]) slt1 <= #1 sr;
always @(posedge clk)
if(out_le[2]) slt2 <= #1 sr;
always @(posedge clk)
if(out_le[3]) slt3 <= #1 sr;
always @(posedge clk)
if(out_le[4]) slt4 <= #1 sr;
always @(posedge clk)
if(out_le[5]) slt6 <= #1 sr;
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
always @(negedge clk)
sdata_in_r <= #1 sdata_in;
always @(posedge clk)
sr <= #1 {sr[18:0], sdata_in_r };
endmodule |
module ac97_dma_if(clk, rst,
o3_status, o4_status, o6_status, o7_status, o8_status, o9_status,
o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty,
i3_status, i4_status, i6_status,
i3_full, i4_full, i6_full,
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
dma_req, dma_ack);
input clk, rst;
input [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
input o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
input [1:0] i3_status, i4_status, i6_status;
input i3_full, i4_full, i6_full;
input [7:0] oc0_cfg;
input [7:0] oc1_cfg;
input [7:0] oc2_cfg;
input [7:0] oc3_cfg;
input [7:0] oc4_cfg;
input [7:0] oc5_cfg;
input [7:0] ic0_cfg;
input [7:0] ic1_cfg;
input [7:0] ic2_cfg;
output [8:0] dma_req;
input [8:0] dma_ack;
////////////////////////////////////////////////////////////////////
//
// DMA Request Modules
//
ac97_dma_req u0(.clk( clk ),
.rst( rst ),
.cfg( oc0_cfg ),
.status( o3_status ),
.full_empty( o3_empty ),
.dma_req( dma_req[0] ),
.dma_ack( dma_ack[0] )
);
ac97_dma_req u1(.clk( clk ),
.rst( rst ),
.cfg( oc1_cfg ),
.status( o4_status ),
.full_empty( o4_empty ),
.dma_req( dma_req[1] ),
.dma_ack( dma_ack[1] )
);
`ifdef AC97_CENTER
ac97_dma_req u2(.clk( clk ),
.rst( rst ),
.cfg( oc2_cfg ),
.status( o6_status ),
.full_empty( o6_empty ),
.dma_req( dma_req[2] ),
.dma_ack( dma_ack[2] )
);
`else
assign dma_req[2] = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_dma_req u3(.clk( clk ),
.rst( rst ),
.cfg( oc3_cfg ),
.status( o7_status ),
.full_empty( o7_empty ),
.dma_req( dma_req[3] ),
.dma_ack( dma_ack[3] )
);
ac97_dma_req u4(.clk( clk ),
.rst( rst ),
.cfg( oc4_cfg ),
.status( o8_status ),
.full_empty( o8_empty ),
.dma_req( dma_req[4] ),
.dma_ack( dma_ack[4] )
);
`else
assign dma_req[3] = 1'b0;
assign dma_req[4] = 1'b0;
`endif
`ifdef AC97_LFE
ac97_dma_req u5(.clk( clk ),
.rst( rst ),
.cfg( oc5_cfg ),
.status( o9_status ),
.full_empty( o9_empty ),
.dma_req( dma_req[5] ),
.dma_ack( dma_ack[5] )
);
`else
assign dma_req[5] = 1'b0;
`endif
`ifdef AC97_SIN
ac97_dma_req u6(.clk( clk ),
.rst( rst ),
.cfg( ic0_cfg ),
.status( i3_status ),
.full_empty( i3_full ),
.dma_req( dma_req[6] ),
.dma_ack( dma_ack[6] )
);
ac97_dma_req u7(.clk( clk ),
.rst( rst ),
.cfg( ic1_cfg ),
.status( i4_status ),
.full_empty( i4_full ),
.dma_req( dma_req[7] ),
.dma_ack( dma_ack[7] )
);
`else
assign dma_req[6] = 1'b0;
assign dma_req[7] = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_dma_req u8(.clk( clk ),
.rst( rst ),
.cfg( ic2_cfg ),
.status( i6_status ),
.full_empty( i6_full ),
.dma_req( dma_req[8] ),
.dma_ack( dma_ack[8] )
);
`else
assign dma_req[8] = 1'b0;
`endif
endmodule |
module ac97_dma_req(clk, rst, cfg, status, full_empty, dma_req, dma_ack);
input clk, rst;
input [7:0] cfg;
input [1:0] status;
input full_empty;
output dma_req;
input dma_ack;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg dma_req_d;
reg dma_req_r1;
reg dma_req;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(cfg or status or full_empty)
case(cfg[5:4]) // synopsys parallel_case full_case
// REQ = Ch_EN & DMA_EN & Status
// 1/4 full/empty
2'h2: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status == 2'h0));
// 1/2 full/empty
2'h1: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2'h0: dma_req_d = cfg[0] & cfg[6] & (full_empty | (status < 2'h3));
2'h3: dma_req_d = cfg[0] & cfg[6] & full_empty;
endcase
always @(posedge clk)
dma_req_r1 <= #1 dma_req_d & !dma_ack;
always @(posedge clk or negedge rst)
if(!rst) dma_req <= #1 1'b0;
else
if(dma_req_r1 & dma_req_d & !dma_ack) dma_req <= #1 1'b1;
else
if(dma_ack) dma_req <= #1 1'b0;
endmodule |
module ac97_soc(clk, wclk, rst,
ps_ce, resume, suspended,
sync, out_le, in_valid, ld, valid
);
input clk, wclk, rst;
input ps_ce;
input resume;
output suspended;
output sync;
output [5:0] out_le;
output [2:0] in_valid;
output ld;
output valid;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] cnt;
reg sync_beat;
reg sync_resume;
reg [5:0] out_le;
reg ld;
reg valid;
reg [2:0] in_valid;
reg bit_clk_r;
reg bit_clk_r1;
reg bit_clk_e;
reg suspended;
wire to;
reg [5:0] to_cnt;
reg [3:0] res_cnt;
wire resume_done;
assign sync = sync_beat | sync_resume;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) cnt <= #1 8'hff;
else
if(suspended) cnt <= #1 8'hff;
else cnt <= #1 cnt + 8'h1;
always @(posedge clk)
ld <= #1 (cnt == 8'h00);
always @(posedge clk)
sync_beat <= #1 (cnt == 8'h00) | ((cnt > 8'h00) & (cnt < 8'h10));
always @(posedge clk)
valid <= #1 (cnt > 8'h39);
always @(posedge clk)
out_le[0] <= #1 (cnt == 8'h11); // Slot 0 Latch Enable
always @(posedge clk)
out_le[1] <= #1 (cnt == 8'h25); // Slot 1 Latch Enable
always @(posedge clk)
out_le[2] <= #1 (cnt == 8'h39); // Slot 2 Latch Enable
always @(posedge clk)
out_le[3] <= #1 (cnt == 8'h4d); // Slot 3 Latch Enable
always @(posedge clk)
out_le[4] <= #1 (cnt == 8'h61); // Slot 4 Latch Enable
always @(posedge clk)
out_le[5] <= #1 (cnt == 8'h89); // Slot 6 Latch Enable
always @(posedge clk)
in_valid[0] <= #1 (cnt > 8'h4d); // Input Slot 3 Valid
always @(posedge clk)
in_valid[1] <= #1 (cnt > 8'h61); // Input Slot 3 Valid
always @(posedge clk)
in_valid[2] <= #1 (cnt > 8'h89); // Input Slot 3 Valid
////////////////////////////////////////////////////////////////////
//
// Suspend Detect
//
always @(posedge wclk)
bit_clk_r <= #1 clk;
always @(posedge wclk)
bit_clk_r1 <= #1 bit_clk_r;
always @(posedge wclk)
bit_clk_e <= #1 (bit_clk_r & !bit_clk_r1) | (!bit_clk_r & bit_clk_r1);
always @(posedge wclk)
suspended <= #1 to;
assign to = (to_cnt == `AC97_SUSP_DET);
always @(posedge wclk or negedge rst)
if(!rst) to_cnt <= #1 6'h0;
else
if(bit_clk_e) to_cnt <= #1 6'h0;
else
if(!to) to_cnt <= #1 to_cnt + 6'h1;
////////////////////////////////////////////////////////////////////
//
// Resume Signaling
//
always @(posedge wclk or negedge rst)
if(!rst) sync_resume <= #1 1'b0;
else
if(resume_done) sync_resume <= #1 1'b0;
else
if(suspended & resume) sync_resume <= #1 1'b1;
assign resume_done = (res_cnt == `AC97_RES_SIG);
always @(posedge wclk)
if(!sync_resume) res_cnt <= #1 4'h0;
else
if(ps_ce) res_cnt <= #1 res_cnt + 4'h1;
endmodule |
module ac97_out_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [31:0] din;
input we;
output [19:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [2:0] wp;
reg [3:0] rp;
wire [2:0] wp_p1;
reg [1:0] status;
reg [19:0] dout;
wire [31:0] dout_tmp;
wire [15:0] dout_tmp1;
wire m16b;
reg empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 3'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 3'h1;
always @(posedge clk)
if(!en) rp <= #1 4'h0;
else
if(re & m16b) rp <= #1 rp + 4'h1;
else
if(re & !m16b) rp <= #1 rp + 4'h2;
always @(posedge clk)
status <= #1 (wp[1:0] - rp[2:1]) - 2'h1;
wire [3:0] rp_p1 = rp[3:0] + 4'h1;
always @(posedge clk)
empty <= #1 (rp_p1[3:1] == wp[2:0]) & (m16b ? rp_p1[0] : 1'b1);
assign full = (wp[1:0] == rp[2:1]) & (wp[2] != rp[3]);
// Fifo Output
assign dout_tmp = mem[ rp[2:1] ];
// Fifo Output Half Word Select
assign dout_tmp1 = rp[0] ? dout_tmp[31:16] : dout_tmp[15:0];
always @(posedge clk)
if(!en) dout <= #1 20'h0;
else
if(re)
case(mode) // synopsys parallel_case full_case
2'h0: dout <= #1 {dout_tmp1, 4'h0}; // 16 Bit Output
2'h1: dout <= #1 {dout_tmp[17:0], 2'h0}; // 18 bit Output
2'h2: dout <= #1 dout_tmp[19:0]; // 20 Bit Output
endcase
always @(posedge clk)
if(we) mem[wp[1:0]] <= #1 din;
endmodule |
module ac97_int(clk, rst,
// Register File Interface
int_set,
// FIFO Interface
cfg, status, full_empty, full, empty, re, we
);
input clk, rst;
output [2:0] int_set;
input [7:0] cfg;
input [1:0] status;
input full_empty, full, empty, re, we;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [2:0] int_set;
////////////////////////////////////////////////////////////////////
//
// Interrupt Logic
//
always @(posedge clk or negedge rst)
if(!rst) int_set[0] <= #1 1'b0;
else
case(cfg[5:4]) // synopsys parallel_case full_case
// 1/4 full/empty
2'h2: int_set[0] <= #1 cfg[0] & (full_empty | (status == 2'h0));
// 1/2 full/empty
2'h1: int_set[0] <= #1 cfg[0] & (full_empty | (status[1] == 1'h0));
// 3/4 full/empty
2'h0: int_set[0] <= #1 cfg[0] & (full_empty | (status < 2'h3));
2'h3: int_set[0] <= #1 cfg[0] & full_empty;
endcase
always @(posedge clk or negedge rst)
if(!rst) int_set[1] <= #1 1'b0;
else
if(empty & re) int_set[1] <= #1 1'b1;
always @(posedge clk or negedge rst)
if(!rst) int_set[2] <= #1 1'b0;
else
if(full & we) int_set[2] <= #1 1'b1;
endmodule |
module ac97_prc(clk, rst,
// SR Slot Interface
valid, in_valid, out_slt0,
in_slt0, in_slt1,
// Codec Register Access
crac_valid, crac_wr,
// Channel Configuration
oc0_cfg, oc1_cfg, oc2_cfg, oc3_cfg, oc4_cfg, oc5_cfg,
ic0_cfg, ic1_cfg, ic2_cfg,
// FIFO Status
o3_empty, o4_empty, o6_empty, o7_empty, o8_empty,
o9_empty, i3_full, i4_full, i6_full,
// FIFO Control
o3_re, o4_re, o6_re, o7_re, o8_re, o9_re,
i3_we, i4_we, i6_we
);
input clk, rst;
input valid;
input [2:0] in_valid;
output [15:0] out_slt0;
input [15:0] in_slt0;
input [19:0] in_slt1;
input crac_valid;
input crac_wr;
input [7:0] oc0_cfg;
input [7:0] oc1_cfg;
input [7:0] oc2_cfg;
input [7:0] oc3_cfg;
input [7:0] oc4_cfg;
input [7:0] oc5_cfg;
input [7:0] ic0_cfg;
input [7:0] ic1_cfg;
input [7:0] ic2_cfg;
input o3_empty;
input o4_empty;
input o6_empty;
input o7_empty;
input o8_empty;
input o9_empty;
input i3_full;
input i4_full;
input i6_full;
output o3_re;
output o4_re;
output o6_re;
output o7_re;
output o8_re;
output o9_re;
output i3_we;
output i4_we;
output i6_we;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
wire o3_re_l;
wire o4_re_l;
wire o6_re_l;
wire o7_re_l;
wire o8_re_l;
wire o9_re_l;
reg crac_valid_r;
reg crac_wr_r;
////////////////////////////////////////////////////////////////////
//
// Output Tag Assembly
//
assign out_slt0[15] = |out_slt0[14:6];
assign out_slt0[14] = crac_valid_r;
assign out_slt0[13] = crac_wr_r;
assign out_slt0[12] = o3_re_l;
assign out_slt0[11] = o4_re_l;
assign out_slt0[10] = 1'b0;
assign out_slt0[09] = o6_re_l;
assign out_slt0[08] = o7_re_l;
assign out_slt0[07] = o8_re_l;
assign out_slt0[06] = o9_re_l;
assign out_slt0[5:0] = 6'h0;
////////////////////////////////////////////////////////////////////
//
// FIFO Control
//
always @(posedge clk)
if(valid) crac_valid_r <= #1 crac_valid;
always @(posedge clk)
if(valid) crac_wr_r <= #1 crac_valid & crac_wr;
// Output Channel 0 (Out Slot 3)
ac97_fifo_ctrl u0(
.clk( clk ),
.valid( valid ),
.ch_en( oc0_cfg[0] ),
.srs( oc0_cfg[1] ),
.full_empty( o3_empty ),
.req( ~in_slt1[11] ),
.crdy( in_slt0[15] ),
.en_out( o3_re ),
.en_out_l( o3_re_l )
);
// Output Channel 1 (Out Slot 4)
ac97_fifo_ctrl u1(
.clk( clk ),
.valid( valid ),
.ch_en( oc1_cfg[0] ),
.srs( oc1_cfg[1] ),
.full_empty( o4_empty ),
.req( ~in_slt1[10] ),
.crdy( in_slt0[15] ),
.en_out( o4_re ),
.en_out_l( o4_re_l )
);
`ifdef AC97_CENTER
// Output Channel 2 (Out Slot 6)
ac97_fifo_ctrl u2(
.clk( clk ),
.valid( valid ),
.ch_en( oc2_cfg[0] ),
.srs( oc2_cfg[1] ),
.full_empty( o6_empty ),
.req( ~in_slt1[8] ),
.crdy( in_slt0[15] ),
.en_out( o6_re ),
.en_out_l( o6_re_l )
);
`else
assign o6_re = 1'b0;
assign o6_re_l = 1'b0;
`endif
`ifdef AC97_SURROUND
// Output Channel 3 (Out Slot 7)
ac97_fifo_ctrl u3(
.clk( clk ),
.valid( valid ),
.ch_en( oc3_cfg[0] ),
.srs( oc3_cfg[1] ),
.full_empty( o7_empty ),
.req( ~in_slt1[7] ),
.crdy( in_slt0[15] ),
.en_out( o7_re ),
.en_out_l( o7_re_l )
);
// Output Channel 4 (Out Slot 8)
ac97_fifo_ctrl u4(
.clk( clk ),
.valid( valid ),
.ch_en( oc4_cfg[0] ),
.srs( oc4_cfg[1] ),
.full_empty( o8_empty ),
.req( ~in_slt1[6] ),
.crdy( in_slt0[15] ),
.en_out( o8_re ),
.en_out_l( o8_re_l )
);
`else
assign o7_re = 1'b0;
assign o7_re_l = 1'b0;
assign o8_re = 1'b0;
assign o8_re_l = 1'b0;
`endif
`ifdef AC97_LFE
// Output Channel 5 (Out Slot 9)
ac97_fifo_ctrl u5(
.clk( clk ),
.valid( valid ),
.ch_en( oc5_cfg[0] ),
.srs( oc5_cfg[1] ),
.full_empty( o9_empty ),
.req( ~in_slt1[5] ),
.crdy( in_slt0[15] ),
.en_out( o9_re ),
.en_out_l( o9_re_l )
);
`else
assign o9_re = 1'b0;
assign o9_re_l = 1'b0;
`endif
`ifdef AC97_SIN
// Input Channel 0 (In Slot 3)
ac97_fifo_ctrl u6(
.clk( clk ),
.valid( in_valid[0] ),
.ch_en( ic0_cfg[0] ),
.srs( ic0_cfg[1] ),
.full_empty( i3_full ),
.req( in_slt0[12] ),
.crdy( in_slt0[15] ),
.en_out( i3_we ),
.en_out_l( )
);
// Input Channel 1 (In Slot 4)
ac97_fifo_ctrl u7(
.clk( clk ),
.valid( in_valid[1] ),
.ch_en( ic1_cfg[0] ),
.srs( ic1_cfg[1] ),
.full_empty( i4_full ),
.req( in_slt0[11] ),
.crdy( in_slt0[15] ),
.en_out( i4_we ),
.en_out_l( )
);
`else
assign i3_we = 1'b0;
assign i4_we = 1'b0;
`endif
`ifdef AC97_MICIN
// Input Channel 2 (In Slot 6)
ac97_fifo_ctrl u8(
.clk( clk ),
.valid( in_valid[2] ),
.ch_en( ic2_cfg[0] ),
.srs( ic2_cfg[1] ),
.full_empty( i6_full ),
.req( in_slt0[9] ),
.crdy( in_slt0[15] ),
.en_out( i6_we ),
.en_out_l( )
);
`else
assign i6_we = 1'b0;
`endif
endmodule |
module ac97_wb_if(clk, rst,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
adr, dout, rf_din, i3_din, i4_din, i6_din,
rf_we, rf_re, o3_we, o4_we, o6_we, o7_we, o8_we, o9_we,
i3_re, i4_re, i6_re
);
input clk,rst;
// WISHBONE Interface
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// Internal Interface
output [3:0] adr;
output [31:0] dout;
input [31:0] rf_din, i3_din, i4_din, i6_din;
output rf_we;
output rf_re;
output o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
output i3_re, i4_re, i6_re;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] wb_data_o;
reg [31:0] dout;
reg wb_ack_o;
reg rf_we;
reg o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
reg i3_re, i4_re, i6_re;
reg we1, we2;
wire we;
reg re2, re1;
wire re;
////////////////////////////////////////////////////////////////////
//
// Modules
//
assign adr = wb_addr_i[5:2];
assign wb_err_o = 1'b0;
always @(posedge clk)
dout <= #1 wb_data_i;
always @(posedge clk)
case(wb_addr_i[6:2]) // synopsys parallel_case full_case
5'he: wb_data_o <= #1 i3_din;
5'hf: wb_data_o <= #1 i4_din;
5'h10: wb_data_o <= #1 i6_din;
default: wb_data_o <= #1 rf_din;
endcase
always @(posedge clk)
re1 <= #1 !re2 & wb_cyc_i & wb_stb_i & !wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
re2 <= #1 re & wb_cyc_i & wb_stb_i & !wb_we_i ;
assign re = re1 & !re2 & wb_cyc_i & wb_stb_i & !wb_we_i;
assign rf_re = re & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
we1 <= #1 !we & wb_cyc_i & wb_stb_i & wb_we_i & `AC97_REG_SEL;
always @(posedge clk)
we2 <= #1 we1 & wb_cyc_i & wb_stb_i & wb_we_i;
assign we = we1 & !we2 & wb_cyc_i & wb_stb_i & wb_we_i;
always @(posedge clk)
wb_ack_o <= #1 (re | we) & wb_cyc_i & wb_stb_i & ~wb_ack_o;
always @(posedge clk)
rf_we <= #1 we & (wb_addr_i[6:2] < 5'h8);
always @(posedge clk)
o3_we <= #1 we & (wb_addr_i[6:2] == 5'h8);
always @(posedge clk)
o4_we <= #1 we & (wb_addr_i[6:2] == 5'h9);
always @(posedge clk)
o6_we <= #1 we & (wb_addr_i[6:2] == 5'ha);
always @(posedge clk)
o7_we <= #1 we & (wb_addr_i[6:2] == 5'hb);
always @(posedge clk)
o8_we <= #1 we & (wb_addr_i[6:2] == 5'hc);
always @(posedge clk)
o9_we <= #1 we & (wb_addr_i[6:2] == 5'hd);
always @(posedge clk)
i3_re <= #1 re & (wb_addr_i[6:2] == 5'he);
always @(posedge clk)
i4_re <= #1 re & (wb_addr_i[6:2] == 5'hf);
always @(posedge clk)
i6_re <= #1 re & (wb_addr_i[6:2] == 5'h10);
endmodule |
module ac97_in_fifo(clk, rst, en, mode, din, we, dout, re, status, full, empty);
input clk, rst;
input en;
input [1:0] mode;
input [19:0] din;
input we;
output [31:0] dout;
input re;
output [1:0] status;
output full;
output empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [31:0] mem[0:3];
reg [31:0] dout;
reg [3:0] wp;
reg [2:0] rp;
wire [3:0] wp_p1;
reg [1:0] status;
reg [15:0] din_tmp1;
reg [31:0] din_tmp;
wire m16b;
reg full, empty;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
assign m16b = (mode == 2'h0); // 16 Bit Mode
always @(posedge clk)
if(!en) wp <= #1 4'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = m16b ? (wp + 4'h1) : (wp + 4'h2);
always @(posedge clk)
if(!en) rp <= #1 3'h0;
else
if(re) rp <= #1 rp + 3'h1;
always @(posedge clk)
status <= #1 ((rp[1:0] - wp[2:1]) - 2'h1);
always @(posedge clk)
empty <= #1 (wp[3:1] == rp[2:0]) & (m16b ? !wp[0] : 1'b0);
always @(posedge clk)
full <= #1 (wp[2:1] == rp[1:0]) & (wp[3] != rp[2]);
// Fifo Output
always @(posedge clk)
dout <= #1 mem[ rp[1:0] ];
// Fifo Input Half Word Latch
always @(posedge clk)
if(we & !wp[0]) din_tmp1 <= #1 din[19:4];
always @(mode or din_tmp1 or din)
case(mode) // synopsys parallel_case full_case
2'h0: din_tmp = {din[19:4], din_tmp1}; // 16 Bit Output
2'h1: din_tmp = {14'h0, din[19:2]}; // 18 bit Output
2'h2: din_tmp = {11'h0, din[19:0]}; // 20 Bit Output
endcase
always @(posedge clk)
if(we & (!m16b | (m16b & wp[0]) ) ) mem[ wp[2:1] ] <= #1 din_tmp;
endmodule |
module ac97_top(clk_i, rst_i,
wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
int_o, dma_req_o, dma_ack_i,
suspended_o,
bit_clk_pad_i, sync_pad_o, sdata_pad_o, sdata_pad_i,
ac97_reset_pad_o_
);
input clk_i, rst_i;
// --------------------------------------
// WISHBONE SLAVE INTERFACE
input [31:0] wb_data_i;
output [31:0] wb_data_o;
input [31:0] wb_addr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
// --------------------------------------
// Misc Signals
output int_o;
output [8:0] dma_req_o;
input [8:0] dma_ack_i;
// --------------------------------------
// Suspend Resume Interface
output suspended_o;
// --------------------------------------
// AC97 Codec Interface
input bit_clk_pad_i;
output sync_pad_o;
output sdata_pad_o;
input sdata_pad_i;
output ac97_reset_pad_o_;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
// Serial Output register interface
wire [15:0] out_slt0;
wire [19:0] out_slt1;
wire [19:0] out_slt2;
wire [19:0] out_slt3;
wire [19:0] out_slt4;
wire [19:0] out_slt6;
wire [19:0] out_slt7;
wire [19:0] out_slt8;
wire [19:0] out_slt9;
// Serial Input register interface
wire [15:0] in_slt0;
wire [19:0] in_slt1;
wire [19:0] in_slt2;
wire [19:0] in_slt3;
wire [19:0] in_slt4;
wire [19:0] in_slt6;
// Serial IO Controller Interface
wire ld;
wire valid;
wire [5:0] out_le;
wire [2:0] in_valid;
wire ps_ce;
// Valid Sync
reg valid_s1, valid_s;
reg [2:0] in_valid_s1, in_valid_s;
// Out FIFO interface
wire [31:0] wb_din;
wire [1:0] o3_mode, o4_mode, o6_mode, o7_mode, o8_mode, o9_mode;
wire o3_re, o4_re, o6_re, o7_re, o8_re, o9_re;
wire o3_we, o4_we, o6_we, o7_we, o8_we, o9_we;
wire [1:0] o3_status, o4_status, o6_status, o7_status, o8_status, o9_status;
wire o3_full, o4_full, o6_full, o7_full, o8_full, o9_full;
wire o3_empty, o4_empty, o6_empty, o7_empty, o8_empty, o9_empty;
// In FIFO interface
wire [31:0] i3_dout, i4_dout, i6_dout;
wire [1:0] i3_mode, i4_mode, i6_mode;
wire i3_we, i4_we, i6_we;
wire i3_re, i4_re, i6_re;
wire [1:0] i3_status, i4_status, i6_status;
wire i3_full, i4_full, i6_full;
wire i3_empty, i4_empty, i6_empty;
// Register File Interface
wire [3:0] adr;
wire [31:0] rf_dout;
wire [31:0] rf_din;
wire rf_we;
wire rf_re;
wire ac97_rst_force;
wire resume_req;
wire crac_we;
wire [15:0] crac_din;
wire [31:0] crac_out;
wire [7:0] oc0_cfg;
wire [7:0] oc1_cfg;
wire [7:0] oc2_cfg;
wire [7:0] oc3_cfg;
wire [7:0] oc4_cfg;
wire [7:0] oc5_cfg;
wire [7:0] ic0_cfg;
wire [7:0] ic1_cfg;
wire [7:0] ic2_cfg;
wire [2:0] oc0_int_set;
wire [2:0] oc1_int_set;
wire [2:0] oc2_int_set;
wire [2:0] oc3_int_set;
wire [2:0] oc4_int_set;
wire [2:0] oc5_int_set;
wire [2:0] ic0_int_set;
wire [2:0] ic1_int_set;
wire [2:0] ic2_int_set;
// CRA Module interface
wire crac_valid;
wire crac_wr;
wire crac_wr_done, crac_rd_done;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
// Sync Valid to WISHBONE Clock
always @(posedge clk_i)
valid_s1 <= #1 valid;
always @(posedge clk_i)
valid_s <= #1 valid_s1;
always @(posedge clk_i)
in_valid_s1 <= #1 in_valid;
always @(posedge clk_i)
in_valid_s <= #1 in_valid_s1;
// "valid_s" Indicates when any of the outputs to the output S/R may
// change or when outputs from input S/R may be sampled
assign o3_mode = oc0_cfg[3:2];
assign o4_mode = oc1_cfg[3:2];
assign o6_mode = oc2_cfg[3:2];
assign o7_mode = oc3_cfg[3:2];
assign o8_mode = oc4_cfg[3:2];
assign o9_mode = oc5_cfg[3:2];
assign i3_mode = ic0_cfg[3:2];
assign i4_mode = ic1_cfg[3:2];
assign i6_mode = ic2_cfg[3:2];
////////////////////////////////////////////////////////////////////
//
// Modules
//
ac97_sout u0(
.clk( bit_clk_pad_i ),
.rst( rst_i ),
.so_ld( ld ),
.slt0( out_slt0 ),
.slt1( out_slt1 ),
.slt2( out_slt2 ),
.slt3( out_slt3 ),
.slt4( out_slt4 ),
.slt6( out_slt6 ),
.slt7( out_slt7 ),
.slt8( out_slt8 ),
.slt9( out_slt9 ),
.sdata_out( sdata_pad_o )
);
ac97_sin u1(
.clk( bit_clk_pad_i ),
.rst( rst_i ),
.out_le( out_le ),
.slt0( in_slt0 ),
.slt1( in_slt1 ),
.slt2( in_slt2 ),
.slt3( in_slt3 ),
.slt4( in_slt4 ),
.slt6( in_slt6 ),
.sdata_in( sdata_pad_i )
);
ac97_soc u2(
.clk( bit_clk_pad_i ),
.wclk( clk_i ),
.rst( rst_i ),
.ps_ce( ps_ce ),
.resume( resume_req ),
.suspended( suspended_o ),
.sync( sync_pad_o ),
.out_le( out_le ),
.in_valid( in_valid ),
.ld( ld ),
.valid( valid )
);
ac97_out_fifo u3(
.clk( clk_i ),
.rst( rst_i ),
.en( oc0_cfg[0] ),
.mode( o3_mode ),
.din( wb_din ),
.we( o3_we ),
.dout( out_slt3 ),
.re( o3_re ),
.status( o3_status ),
.full( o3_full ),
.empty( o3_empty )
);
ac97_out_fifo u4(
.clk( clk_i ),
.rst( rst_i ),
.en( oc1_cfg[0] ),
.mode( o4_mode ),
.din( wb_din ),
.we( o4_we ),
.dout( out_slt4 ),
.re( o4_re ),
.status( o4_status ),
.full( o4_full ),
.empty( o4_empty )
);
`ifdef AC97_CENTER
ac97_out_fifo u5(
.clk( clk_i ),
.rst( rst_i ),
.en( oc2_cfg[0] ),
.mode( o6_mode ),
.din( wb_din ),
.we( o6_we ),
.dout( out_slt6 ),
.re( o6_re ),
.status( o6_status ),
.full( o6_full ),
.empty( o6_empty )
);
`else
assign out_slt6 = 20'h0;
assign o6_status = 2'h0;
assign o6_full = 1'b0;
assign o6_empty = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_out_fifo u6(
.clk( clk_i ),
.rst( rst_i ),
.en( oc3_cfg[0] ),
.mode( o7_mode ),
.din( wb_din ),
.we( o7_we ),
.dout( out_slt7 ),
.re( o7_re ),
.status( o7_status ),
.full( o7_full ),
.empty( o7_empty )
);
ac97_out_fifo u7(
.clk( clk_i ),
.rst( rst_i ),
.en( oc4_cfg[0] ),
.mode( o8_mode ),
.din( wb_din ),
.we( o8_we ),
.dout( out_slt8 ),
.re( o8_re ),
.status( o8_status ),
.full( o8_full ),
.empty( o8_empty )
);
`else
assign out_slt7 = 20'h0;
assign o7_status = 2'h0;
assign o7_full = 1'b0;
assign o7_empty = 1'b0;
assign out_slt8 = 20'h0;
assign o8_status = 2'h0;
assign o8_full = 1'b0;
assign o8_empty = 1'b0;
`endif
`ifdef AC97_LFE
ac97_out_fifo u8(
.clk( clk_i ),
.rst( rst_i ),
.en( oc5_cfg[0] ),
.mode( o9_mode ),
.din( wb_din ),
.we( o9_we ),
.dout( out_slt9 ),
.re( o9_re ),
.status( o9_status ),
.full( o9_full ),
.empty( o9_empty )
);
`else
assign out_slt9 = 20'h0;
assign o9_status = 2'h0;
assign o9_full = 1'b0;
assign o9_empty = 1'b0;
`endif
`ifdef AC97_SIN
ac97_in_fifo u9(
.clk( clk_i ),
.rst( rst_i ),
.en( ic0_cfg[0] ),
.mode( i3_mode ),
.din( in_slt3 ),
.we( i3_we ),
.dout( i3_dout ),
.re( i3_re ),
.status( i3_status ),
.full( i3_full ),
.empty( i3_empty )
);
ac97_in_fifo u10(
.clk( clk_i ),
.rst( rst_i ),
.en( ic1_cfg[0] ),
.mode( i4_mode ),
.din( in_slt4 ),
.we( i4_we ),
.dout( i4_dout ),
.re( i4_re ),
.status( i4_status ),
.full( i4_full ),
.empty( i4_empty )
);
`else
assign i3_dout = 20'h0;
assign i3_status = 2'h0;
assign i3_full = 1'b0;
assign i3_empty = 1'b0;
assign i4_dout = 20'h0;
assign i4_status = 2'h0;
assign i4_full = 1'b0;
assign i4_empty = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_in_fifo u11(
.clk( clk_i ),
.rst( rst_i ),
.en( ic2_cfg[0] ),
.mode( i6_mode ),
.din( in_slt6 ),
.we( i6_we ),
.dout( i6_dout ),
.re( i6_re ),
.status( i6_status ),
.full( i6_full ),
.empty( i6_empty )
);
`else
assign i6_dout = 20'h0;
assign i6_status = 2'h0;
assign i6_full = 1'b0;
assign i6_empty = 1'b0;
`endif
ac97_wb_if u12(
.clk( clk_i ),
.rst( rst_i ),
.wb_data_i( wb_data_i ),
.wb_data_o( wb_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.adr( adr ),
.dout( wb_din ),
.rf_din( rf_dout ),
.i3_din( i3_dout ),
.i4_din( i4_dout ),
.i6_din( i6_dout ),
.rf_we( rf_we ),
.rf_re( rf_re ),
.o3_we( o3_we ),
.o4_we( o4_we ),
.o6_we( o6_we ),
.o7_we( o7_we ),
.o8_we( o8_we ),
.o9_we( o9_we ),
.i3_re( i3_re ),
.i4_re( i4_re ),
.i6_re( i6_re )
);
ac97_rf u13( .clk( clk_i ),
.rst( rst_i ),
.adr( adr ),
.rf_dout( rf_dout ),
.rf_din( wb_din ),
.rf_we( rf_we ),
.rf_re( rf_re ),
.int( int_o ),
.ac97_rst_force(ac97_rst_force ),
.resume_req( resume_req ),
.suspended( suspended_o ),
.crac_we( crac_we ),
.crac_din( crac_din ),
.crac_out( crac_out ),
.crac_wr_done( crac_wr_done ),
.crac_rd_done( crac_rd_done ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.oc0_int_set( oc0_int_set ),
.oc1_int_set( oc1_int_set ),
.oc2_int_set( oc2_int_set ),
.oc3_int_set( oc3_int_set ),
.oc4_int_set( oc4_int_set ),
.oc5_int_set( oc5_int_set ),
.ic0_int_set( ic0_int_set ),
.ic1_int_set( ic1_int_set ),
.ic2_int_set( ic2_int_set )
);
ac97_prc u14( .clk( clk_i ),
.rst( rst_i ),
.valid( valid_s ),
.in_valid( in_valid_s ),
.out_slt0( out_slt0 ),
.in_slt0( in_slt0 ),
.in_slt1( in_slt1 ),
.crac_valid( crac_valid ),
.crac_wr( crac_wr ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.o3_empty( o3_empty ),
.o4_empty( o4_empty ),
.o6_empty( o6_empty ),
.o7_empty( o7_empty ),
.o8_empty( o8_empty ),
.o9_empty( o9_empty ),
.i3_full( i3_full ),
.i4_full( i4_full ),
.i6_full( i6_full ),
.o3_re( o3_re ),
.o4_re( o4_re ),
.o6_re( o6_re ),
.o7_re( o7_re ),
.o8_re( o8_re ),
.o9_re( o9_re ),
.i3_we( i3_we ),
.i4_we( i4_we ),
.i6_we( i6_we )
);
ac97_cra u15( .clk( clk_i ),
.rst( rst_i ),
.crac_we( crac_we ),
.crac_din( crac_din ),
.crac_out( crac_out ),
.crac_wr_done( crac_wr_done ),
.crac_rd_done( crac_rd_done ),
.valid( valid_s ),
.out_slt1( out_slt1 ),
.out_slt2( out_slt2 ),
.in_slt2( in_slt2 ),
.crac_valid( crac_valid ),
.crac_wr( crac_wr )
);
ac97_dma_if u16(.clk( clk_i ),
.rst( rst_i ),
.o3_status( o3_status ),
.o4_status( o4_status ),
.o6_status( o6_status ),
.o7_status( o7_status ),
.o8_status( o8_status ),
.o9_status( o9_status ),
.o3_empty( o3_empty ),
.o4_empty( o4_empty ),
.o6_empty( o6_empty ),
.o7_empty( o7_empty ),
.o8_empty( o8_empty ),
.o9_empty( o9_empty ),
.i3_status( i3_status ),
.i4_status( i4_status ),
.i6_status( i6_status ),
.i3_full( i3_full ),
.i4_full( i4_full ),
.i6_full( i6_full ),
.oc0_cfg( oc0_cfg ),
.oc1_cfg( oc1_cfg ),
.oc2_cfg( oc2_cfg ),
.oc3_cfg( oc3_cfg ),
.oc4_cfg( oc4_cfg ),
.oc5_cfg( oc5_cfg ),
.ic0_cfg( ic0_cfg ),
.ic1_cfg( ic1_cfg ),
.ic2_cfg( ic2_cfg ),
.dma_req( dma_req_o ),
.dma_ack( dma_ack_i )
);
ac97_int u17(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc0_int_set ),
.cfg( oc0_cfg ),
.status( o3_status ),
.full_empty( o3_empty ),
.full( o3_full ),
.empty( o3_empty ),
.re( o3_re ),
.we( o3_we )
);
ac97_int u18(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc1_int_set ),
.cfg( oc1_cfg ),
.status( o4_status ),
.full_empty( o4_empty ),
.full( o4_full ),
.empty( o4_empty ),
.re( o4_re ),
.we( o4_we )
);
`ifdef AC97_CENTER
ac97_int u19(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc2_int_set ),
.cfg( oc2_cfg ),
.status( o6_status ),
.full_empty( o6_empty ),
.full( o6_full ),
.empty( o6_empty ),
.re( o6_re ),
.we( o6_we )
);
`else
assign oc2_int_set = 1'b0;
`endif
`ifdef AC97_SURROUND
ac97_int u20(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc3_int_set ),
.cfg( oc3_cfg ),
.status( o7_status ),
.full_empty( o7_empty ),
.full( o7_full ),
.empty( o7_empty ),
.re( o7_re ),
.we( o7_we )
);
ac97_int u21(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc4_int_set ),
.cfg( oc4_cfg ),
.status( o8_status ),
.full_empty( o8_empty ),
.full( o8_full ),
.empty( o8_empty ),
.re( o8_re ),
.we( o8_we )
);
`else
assign oc3_int_set = 1'b0;
assign oc4_int_set = 1'b0;
`endif
`ifdef AC97_LFE
ac97_int u22(
.clk( clk_i ),
.rst( rst_i ),
.int_set( oc5_int_set ),
.cfg( oc5_cfg ),
.status( o9_status ),
.full_empty( o9_empty ),
.full( o9_full ),
.empty( o9_empty ),
.re( o9_re ),
.we( o9_we )
);
`else
assign oc5_int_set = 1'b0;
`endif
`ifdef AC97_SIN
ac97_int u23(
.clk( clk_i ),
.rst( rst_i ),
.int_set( ic0_int_set ),
.cfg( ic0_cfg ),
.status( i3_status ),
.full_empty( i3_full ),
.full( i3_full ),
.empty( i3_empty ),
.re( i3_re ),
.we( i3_we )
);
ac97_int u24(
.clk( clk_i ),
.rst( rst_i ),
.int_set( ic1_int_set ),
.cfg( ic1_cfg ),
.status( i4_status ),
.full_empty( i4_full ),
.full( i4_full ),
.empty( i4_empty ),
.re( i4_re ),
.we( i4_we )
);
`else
assign ic0_int_set = 1'b0;
assign ic1_int_set = 1'b0;
`endif
`ifdef AC97_MICIN
ac97_int u25(
.clk( clk_i ),
.rst( rst_i ),
.int_set( ic2_int_set ),
.cfg( ic2_cfg ),
.status( i6_status ),
.full_empty( i6_full ),
.full( i6_full ),
.empty( i6_empty ),
.re( i6_re ),
.we( i6_we )
);
`else
assign ic2_int_set = 1'b0;
`endif
ac97_rst u26(
.clk( clk_i ),
.rst( rst_i ),
.rst_force( ac97_rst_force ),
.ps_ce( ps_ce ),
.ac97_rst_( ac97_reset_pad_o_ )
);
endmodule |
module ac97_fifo_ctrl( clk,
valid, ch_en, srs, full_empty, req, crdy,
en_out, en_out_l
);
input clk;
input valid;
input ch_en; // Channel Enable
input srs; // Sample Rate Select
input full_empty; // Fifo Status
input req; // Codec Request
input crdy; // Codec Ready
output en_out; // Output read/write pulse
output en_out_l; // Latched Output
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg en_out_l, en_out_l2;
reg full_empty_r;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
if(!valid) full_empty_r <= #1 full_empty;
always @(posedge clk)
if(valid & ch_en & !full_empty_r & crdy & (!srs | (srs & req) ) )
en_out_l <= #1 1'b1;
else
if(!valid & !(ch_en & !full_empty_r & crdy & (!srs | (srs & req) )) )
en_out_l <= #1 1'b0;
always @(posedge clk)
en_out_l2 <= #1 en_out_l & valid;
assign en_out = en_out_l & !en_out_l2 & valid;
endmodule |
module sasc_brg(clk, rst, div0, div1, sio_ce, sio_ce_x4);
input clk;
input rst;
input [7:0] div0, div1;
output sio_ce, sio_ce_x4;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg [7:0] ps;
reg ps_clr;
reg [7:0] br_cnt;
reg br_clr;
reg sio_ce_x4_r;
reg [1:0] cnt;
reg sio_ce, sio_ce_x4;
reg sio_ce_r ;
reg sio_ce_x4_t;
///////////////////////////////////////////////////////////////////
//
// Boud Rate Generator
//
// -----------------------------------------------------
// Prescaler
always @(posedge clk)
if(!rst) ps <= #1 8'h0;
else
if(ps_clr) ps <= #1 8'h0;
else ps <= #1 ps + 8'h1;
always @(posedge clk)
ps_clr <= #1 (ps == div0); // Desired number of cycles less 2
// -----------------------------------------------------
// Oversampled Boud Rate (x4)
always @(posedge clk)
if(!rst) br_cnt <= #1 8'h0;
else
if(br_clr) br_cnt <= #1 8'h0;
else
if(ps_clr) br_cnt <= #1 br_cnt + 8'h1;
always @(posedge clk)
br_clr <= #1 (br_cnt == div1); // Prciese number of PS cycles
always @(posedge clk)
sio_ce_x4_r <= #1 br_clr;
always @(posedge clk)
sio_ce_x4_t <= #1 !sio_ce_x4_r & br_clr;
always @(posedge clk)
sio_ce_x4 <= #1 sio_ce_x4_t;
// -----------------------------------------------------
// Actual Boud rate
always @(posedge clk)
if(!rst) cnt <= #1 2'h0;
else
if(!sio_ce_x4_r & br_clr) cnt <= #1 cnt + 2'h1;
always @(posedge clk)
sio_ce_r <= #1 (cnt == 2'h0);
always @(posedge clk)
sio_ce <= #1 !sio_ce_r & (cnt == 2'h0);
endmodule |
module sasc_fifo4(clk, rst, clr, din, we, dout, re, full, empty);
input clk, rst;
input clr;
input [7:0] din;
input we;
output [7:0] dout;
input re;
output full, empty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [7:0] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk or negedge rst)
if(!rst) wp <= #1 2'h0;
else
if(clr) wp <= #1 2'h0;
else
if(we) wp <= #1 wp_p1;
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
always @(posedge clk or negedge rst)
if(!rst) rp <= #1 2'h0;
else
if(clr) rp <= #1 2'h0;
else
if(re) rp <= #1 rp_p1;
assign rp_p1 = rp + 2'h1;
// Fifo Output
assign dout = mem[ rp ];
// Fifo Input
always @(posedge clk)
if(we) mem[ wp ] <= #1 din;
// Status
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
// Guard Bit ...
always @(posedge clk)
if(!rst) gb <= #1 1'b0;
else
if(clr) gb <= #1 1'b0;
else
if((wp_p1 == rp) & we) gb <= #1 1'b1;
else
if(re) gb <= #1 1'b0;
endmodule |
module sasc_top( clk, rst,
// SIO
rxd_i, txd_o, cts_i, rts_o,
// External Baud Rate Generator
sio_ce, sio_ce_x4,
// Internal Interface
din_i, dout_o, re_i, we_i, full_o, empty_o);
input clk;
input rst;
input rxd_i;
output txd_o;
input cts_i;
output rts_o;
input sio_ce;
input sio_ce_x4;
input [7:0] din_i;
output [7:0] dout_o;
input re_i, we_i;
output full_o, empty_o;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter START_BIT = 1'b0,
STOP_BIT = 1'b1,
IDLE_BIT = 1'b1;
wire [7:0] txd_p;
reg load;
reg load_r;
wire load_e;
reg [9:0] hold_reg;
wire txf_empty;
reg txd_o;
reg shift_en;
reg [3:0] tx_bit_cnt;
reg rxd_s, rxd_r;
wire start;
reg [3:0] rx_bit_cnt;
reg rx_go;
reg [9:0] rxr;
reg rx_valid, rx_valid_r;
wire rx_we;
wire rxf_full;
reg rts_o;
reg txf_empty_r;
reg shift_en_r;
reg rxd_r1, rxd_r2;
wire lock_en;
reg change;
reg rx_sio_ce_d, rx_sio_ce_r1, rx_sio_ce_r2, rx_sio_ce;
reg [1:0] dpll_state, dpll_next_state;
///////////////////////////////////////////////////////////////////
//
// IO Fifo's
//
sasc_fifo4 tx_fifo( .clk( clk ),
.rst( rst ),
.clr( 1'b0 ),
.din( din_i ),
.we( we_i ),
.dout( txd_p ),
.re( load_e ),
.full( full_o ),
.empty( txf_empty )
);
sasc_fifo4 rx_fifo( .clk( clk ),
.rst( rst ),
.clr( 1'b0 ),
.din( rxr[9:2] ),
.we( rx_we ),
.dout( dout_o ),
.re( re_i ),
.full( rxf_full ),
.empty( empty_o )
);
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
always @(posedge clk)
if(!rst) txf_empty_r <= #1 1'b1;
else
if(sio_ce) txf_empty_r <= #1 txf_empty;
always @(posedge clk)
load <= #1 !txf_empty_r & !shift_en & !cts_i;
always @(posedge clk)
load_r <= #1 load;
assign load_e = load & sio_ce;
always @(posedge clk)
if(load_e) hold_reg <= #1 {STOP_BIT, txd_p, START_BIT};
else
if(shift_en & sio_ce) hold_reg <= #1 {IDLE_BIT, hold_reg[9:1]};
always @(posedge clk)
if(!rst) txd_o <= #1 IDLE_BIT;
else
if(sio_ce)
if(shift_en | shift_en_r) txd_o <= #1 hold_reg[0];
else txd_o <= #1 IDLE_BIT;
always @(posedge clk)
if(!rst) tx_bit_cnt <= #1 4'h9;
else
if(load_e) tx_bit_cnt <= #1 4'h0;
else
if(shift_en & sio_ce) tx_bit_cnt <= #1 tx_bit_cnt + 4'h1;
always @(posedge clk)
shift_en <= #1 (tx_bit_cnt != 4'h9);
always @(posedge clk)
if(!rst) shift_en_r <= #1 1'b0;
else
if(sio_ce) shift_en_r <= #1 shift_en;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk)
rxd_s <= #1 rxd_i;
always @(posedge clk)
rxd_r <= #1 rxd_s;
assign start = (rxd_r == IDLE_BIT) & (rxd_s == START_BIT);
always @(posedge clk)
if(!rst) rx_bit_cnt <= #1 4'ha;
else
if(!rx_go & start) rx_bit_cnt <= #1 4'h0;
else
if(rx_go & rx_sio_ce) rx_bit_cnt <= #1 rx_bit_cnt + 4'h1;
always @(posedge clk)
rx_go <= #1 (rx_bit_cnt != 4'ha);
always @(posedge clk)
rx_valid <= #1 (rx_bit_cnt == 4'h9);
always @(posedge clk)
rx_valid_r <= #1 rx_valid;
assign rx_we = !rx_valid_r & rx_valid & !rxf_full;
always @(posedge clk)
if(rx_go & rx_sio_ce) rxr <= {rxd_s, rxr[9:1]};
always @(posedge clk)
rts_o <= #1 rxf_full;
///////////////////////////////////////////////////////////////////
//
// Reciever DPLL
//
// Uses 4x baud clock to lock to incoming stream
// Edge detector
always @(posedge clk)
if(sio_ce_x4) rxd_r1 <= #1 rxd_s;
always @(posedge clk)
if(sio_ce_x4) rxd_r2 <= #1 rxd_r1;
always @(posedge clk)
if(!rst) change <= #1 1'b0;
else
if(rxd_r != rxd_s) change <= #1 1'b1;
else
if(sio_ce_x4) change <= #1 1'b0;
// DPLL FSM
always @(posedge clk or negedge rst)
if(!rst) dpll_state <= #1 2'h1;
else
if(sio_ce_x4) dpll_state <= #1 dpll_next_state;
always @(dpll_state or change)
begin
rx_sio_ce_d = 1'b0;
case(dpll_state)
2'h0:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h1;
2'h1:begin
rx_sio_ce_d = 1'b1;
if(change) dpll_next_state = 3'h3;
else dpll_next_state = 3'h2;
end
2'h2:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h3;
2'h3:
if(change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h0;
endcase
end
// Compensate for sync registers at the input - allign sio
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
rx_sio_ce_r1 <= #1 rx_sio_ce_d;
always @(posedge clk)
rx_sio_ce_r2 <= #1 rx_sio_ce_r1;
always @(posedge clk)
rx_sio_ce <= #1 rx_sio_ce_r1 & !rx_sio_ce_r2;
endmodule |
module sha256_w_mem(
input wire clk,
input wire rst,
input wire [511 : 0] block,
input wire init,
input wire next,
output wire [31 : 0] w
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 0;
parameter CTRL_UPDATE = 1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] w_mem [0 : 15];
reg [31 : 0] w_mem00_new;
reg [31 : 0] w_mem01_new;
reg [31 : 0] w_mem02_new;
reg [31 : 0] w_mem03_new;
reg [31 : 0] w_mem04_new;
reg [31 : 0] w_mem05_new;
reg [31 : 0] w_mem06_new;
reg [31 : 0] w_mem07_new;
reg [31 : 0] w_mem08_new;
reg [31 : 0] w_mem09_new;
reg [31 : 0] w_mem10_new;
reg [31 : 0] w_mem11_new;
reg [31 : 0] w_mem12_new;
reg [31 : 0] w_mem13_new;
reg [31 : 0] w_mem14_new;
reg [31 : 0] w_mem15_new;
reg w_mem_we;
reg [5 : 0] w_ctr_reg;
reg [5 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
reg [1 : 0] sha256_w_mem_ctrl_reg;
reg [1 : 0] sha256_w_mem_ctrl_new;
reg sha256_w_mem_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] w_tmp;
reg [31 : 0] w_new;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
w_mem[00] <= 32'h0;
w_mem[01] <= 32'h0;
w_mem[02] <= 32'h0;
w_mem[03] <= 32'h0;
w_mem[04] <= 32'h0;
w_mem[05] <= 32'h0;
w_mem[06] <= 32'h0;
w_mem[07] <= 32'h0;
w_mem[08] <= 32'h0;
w_mem[09] <= 32'h0;
w_mem[10] <= 32'h0;
w_mem[11] <= 32'h0;
w_mem[12] <= 32'h0;
w_mem[13] <= 32'h0;
w_mem[14] <= 32'h0;
w_mem[15] <= 32'h0;
w_ctr_reg <= 6'h00;
sha256_w_mem_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (w_mem_we)
begin
w_mem[00] <= w_mem00_new;
w_mem[01] <= w_mem01_new;
w_mem[02] <= w_mem02_new;
w_mem[03] <= w_mem03_new;
w_mem[04] <= w_mem04_new;
w_mem[05] <= w_mem05_new;
w_mem[06] <= w_mem06_new;
w_mem[07] <= w_mem07_new;
w_mem[08] <= w_mem08_new;
w_mem[09] <= w_mem09_new;
w_mem[10] <= w_mem10_new;
w_mem[11] <= w_mem11_new;
w_mem[12] <= w_mem12_new;
w_mem[13] <= w_mem13_new;
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
if (w_ctr_we)
w_ctr_reg <= w_ctr_new;
if (sha256_w_mem_ctrl_we)
sha256_w_mem_ctrl_reg <= sha256_w_mem_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// select_w
//
// Mux for the external read operation. This is where we exract
// the W variable.
//----------------------------------------------------------------
always @*
begin : select_w
if (w_ctr_reg < 16)
begin
w_tmp = w_mem[w_ctr_reg[3 : 0]];
end
else
begin
w_tmp = w_new;
end
end // select_w
//----------------------------------------------------------------
// w_new_logic
//
// Logic that calculates the next value to be inserted into
// the sliding window of the memory.
//----------------------------------------------------------------
always @*
begin : w_mem_update_logic
reg [31 : 0] w_0;
reg [31 : 0] w_1;
reg [31 : 0] w_9;
reg [31 : 0] w_14;
reg [31 : 0] d0;
reg [31 : 0] d1;
w_mem00_new = 32'h0;
w_mem01_new = 32'h0;
w_mem02_new = 32'h0;
w_mem03_new = 32'h0;
w_mem04_new = 32'h0;
w_mem05_new = 32'h0;
w_mem06_new = 32'h0;
w_mem07_new = 32'h0;
w_mem08_new = 32'h0;
w_mem09_new = 32'h0;
w_mem10_new = 32'h0;
w_mem11_new = 32'h0;
w_mem12_new = 32'h0;
w_mem13_new = 32'h0;
w_mem14_new = 32'h0;
w_mem15_new = 32'h0;
w_mem_we = 0;
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
w_14 = w_mem[14];
d0 = {w_1[6 : 0], w_1[31 : 7]} ^
{w_1[17 : 0], w_1[31 : 18]} ^
{3'b000, w_1[31 : 3]};
d1 = {w_14[16 : 0], w_14[31 : 17]} ^
{w_14[18 : 0], w_14[31 : 19]} ^
{10'b0000000000, w_14[31 : 10]};
w_new = d1 + w_9 + d0 + w_0;
if (init)
begin
w_mem00_new = block[511 : 480];
w_mem01_new = block[479 : 448];
w_mem02_new = block[447 : 416];
w_mem03_new = block[415 : 384];
w_mem04_new = block[383 : 352];
w_mem05_new = block[351 : 320];
w_mem06_new = block[319 : 288];
w_mem07_new = block[287 : 256];
w_mem08_new = block[255 : 224];
w_mem09_new = block[223 : 192];
w_mem10_new = block[191 : 160];
w_mem11_new = block[159 : 128];
w_mem12_new = block[127 : 96];
w_mem13_new = block[95 : 64];
w_mem14_new = block[63 : 32];
w_mem15_new = block[31 : 0];
w_mem_we = 1;
end
else if (w_ctr_reg > 15)
begin
w_mem00_new = w_mem[01];
w_mem01_new = w_mem[02];
w_mem02_new = w_mem[03];
w_mem03_new = w_mem[04];
w_mem04_new = w_mem[05];
w_mem05_new = w_mem[06];
w_mem06_new = w_mem[07];
w_mem07_new = w_mem[08];
w_mem08_new = w_mem[09];
w_mem09_new = w_mem[10];
w_mem10_new = w_mem[11];
w_mem11_new = w_mem[12];
w_mem12_new = w_mem[13];
w_mem13_new = w_mem[14];
w_mem14_new = w_mem[15];
w_mem15_new = w_new;
w_mem_we = 1;
end
end // w_mem_update_logic
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
// is used to expand the block into words.
//----------------------------------------------------------------
always @*
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
if (w_ctr_rst)
begin
w_ctr_new = 6'h00;
w_ctr_we = 1;
end
if (w_ctr_inc)
begin
w_ctr_new = w_ctr_reg + 6'h01;
w_ctr_we = 1;
end
end // w_ctr
//----------------------------------------------------------------
// sha256_w_mem_fsm
// Logic for the w shedule FSM.
//----------------------------------------------------------------
always @*
begin : sha256_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 0;
case (sha256_w_mem_ctrl_reg)
CTRL_IDLE:
begin
if (init)
begin
w_ctr_rst = 1;
sha256_w_mem_ctrl_new = CTRL_UPDATE;
sha256_w_mem_ctrl_we = 1;
end
end
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
if (w_ctr_reg == 6'h3f)
begin
sha256_w_mem_ctrl_new = CTRL_IDLE;
sha256_w_mem_ctrl_we = 1;
end
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_w_mem |
module sha256(
input wire clk,
input wire rst,
input wire init,
input wire next,
input wire [511 : 0] block,
output wire ready,
output wire [255 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA256_H0_0 = 32'h6a09e667;
parameter SHA256_H0_1 = 32'hbb67ae85;
parameter SHA256_H0_2 = 32'h3c6ef372;
parameter SHA256_H0_3 = 32'ha54ff53a;
parameter SHA256_H0_4 = 32'h510e527f;
parameter SHA256_H0_5 = 32'h9b05688c;
parameter SHA256_H0_6 = 32'h1f83d9ab;
parameter SHA256_H0_7 = 32'h5be0cd19;
parameter SHA256_ROUNDS = 63;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [31 : 0] a_reg;
reg [31 : 0] a_new;
reg [31 : 0] b_reg;
reg [31 : 0] b_new;
reg [31 : 0] c_reg;
reg [31 : 0] c_new;
reg [31 : 0] d_reg;
reg [31 : 0] d_new;
reg [31 : 0] e_reg;
reg [31 : 0] e_new;
reg [31 : 0] f_reg;
reg [31 : 0] f_new;
reg [31 : 0] g_reg;
reg [31 : 0] g_new;
reg [31 : 0] h_reg;
reg [31 : 0] h_new;
reg a_h_we;
reg [31 : 0] H0_reg;
reg [31 : 0] H0_new;
reg [31 : 0] H1_reg;
reg [31 : 0] H1_new;
reg [31 : 0] H2_reg;
reg [31 : 0] H2_new;
reg [31 : 0] H3_reg;
reg [31 : 0] H3_new;
reg [31 : 0] H4_reg;
reg [31 : 0] H4_new;
reg [31 : 0] H5_reg;
reg [31 : 0] H5_new;
reg [31 : 0] H6_reg;
reg [31 : 0] H6_new;
reg [31 : 0] H7_reg;
reg [31 : 0] H7_new;
reg H_we;
reg [5 : 0] t_ctr_reg;
reg [5 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha256_ctrl_reg;
reg [1 : 0] sha256_ctrl_new;
reg sha256_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [31 : 0] t1;
reg [31 : 0] t2;
wire [31 : 0] k_data;
reg w_init;
reg w_next;
wire [31 : 0] w_data;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
sha256_k_constants k_constants_inst(
.addr(t_ctr_reg),
.K(k_data)
);
sha256_w_mem w_mem_inst(
.clk(clk),
.rst(rst),
.block(block),
.init(w_init),
.next(w_next),
.w(w_data)
);
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk)
begin : reg_update
if (rst)
begin
a_reg <= 32'h0;
b_reg <= 32'h0;
c_reg <= 32'h0;
d_reg <= 32'h0;
e_reg <= 32'h0;
f_reg <= 32'h0;
g_reg <= 32'h0;
h_reg <= 32'h0;
H0_reg <= 32'h0;
H1_reg <= 32'h0;
H2_reg <= 32'h0;
H3_reg <= 32'h0;
H4_reg <= 32'h0;
H5_reg <= 32'h0;
H6_reg <= 32'h0;
H7_reg <= 32'h0;
digest_valid_reg <= 0;
t_ctr_reg <= 6'h0;
sha256_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
t_ctr_reg <= t_ctr_new;
if (digest_valid_we)
digest_valid_reg <= digest_valid_new;
if (sha256_ctrl_we)
sha256_ctrl_reg <= sha256_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 32'h0;
H1_new = 32'h0;
H2_new = 32'h0;
H3_new = 32'h0;
H4_new = 32'h0;
H5_new = 32'h0;
H6_new = 32'h0;
H7_new = 32'h0;
H_we = 0;
if (digest_init)
begin
H_we = 1;
H0_new = SHA256_H0_0;
H1_new = SHA256_H0_1;
H2_new = SHA256_H0_2;
H3_new = SHA256_H0_3;
H4_new = SHA256_H0_4;
H5_new = SHA256_H0_5;
H6_new = SHA256_H0_6;
H7_new = SHA256_H0_7;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [31 : 0] sum1;
reg [31 : 0] ch;
sum1 = {e_reg[5 : 0], e_reg[31 : 6]} ^
{e_reg[10 : 0], e_reg[31 : 11]} ^
{e_reg[24 : 0], e_reg[31 : 25]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + w_data + k_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [31 : 0] sum0;
reg [31 : 0] maj;
sum0 = {a_reg[1 : 0], a_reg[31 : 2]} ^
{a_reg[12 : 0], a_reg[31 : 13]} ^
{a_reg[21 : 0], a_reg[31 : 22]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 32'h0;
b_new = 32'h0;
c_new = 32'h0;
d_new = 32'h0;
e_new = 32'h0;
f_new = 32'h0;
g_new = 32'h0;
h_new = 32'h0;
a_h_we = 0;
if (state_init)
begin
a_h_we = 1;
if (first_block)
begin
a_new = SHA256_H0_0;
b_new = SHA256_H0_1;
c_new = SHA256_H0_2;
d_new = SHA256_H0_3;
e_new = SHA256_H0_4;
f_new = SHA256_H0_5;
g_new = SHA256_H0_6;
h_new = SHA256_H0_7;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 0;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 0;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// sha256_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha256_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 0;
case (sha256_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
if (next)
begin
t_ctr_rst = 1;
w_init = 1;
state_init = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_ROUNDS;
sha256_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA256_ROUNDS)
begin
sha256_ctrl_new = CTRL_DONE;
sha256_ctrl_we = 1;
end
end
CTRL_DONE:
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha256_ctrl_new = CTRL_IDLE;
sha256_ctrl_we = 1;
end
endcase // case (sha256_ctrl_reg)
end // sha256_ctrl_fsm
endmodule // sha256_core |
module crp(P, R, K_sub);
output [1:32] P;
input [1:32] R;
input [1:48] K_sub;
wire [1:48] E;
wire [1:48] X;
wire [1:32] S;
assign E[1:48] = { R[32], R[1], R[2], R[3], R[4], R[5], R[4], R[5],
R[6], R[7], R[8], R[9], R[8], R[9], R[10], R[11],
R[12], R[13], R[12], R[13], R[14], R[15], R[16],
R[17], R[16], R[17], R[18], R[19], R[20], R[21],
R[20], R[21], R[22], R[23], R[24], R[25], R[24],
R[25], R[26], R[27], R[28], R[29], R[28], R[29],
R[30], R[31], R[32], R[1]};
assign X = E ^ K_sub;
sbox1 u0( .addr(X[01:06]), .dout(S[01:04]) );
sbox2 u1( .addr(X[07:12]), .dout(S[05:08]) );
sbox3 u2( .addr(X[13:18]), .dout(S[09:12]) );
sbox4 u3( .addr(X[19:24]), .dout(S[13:16]) );
sbox5 u4( .addr(X[25:30]), .dout(S[17:20]) );
sbox6 u5( .addr(X[31:36]), .dout(S[21:24]) );
sbox7 u6( .addr(X[37:42]), .dout(S[25:28]) );
sbox8 u7( .addr(X[43:48]), .dout(S[29:32]) );
assign P[1:32] = { S[16], S[7], S[20], S[21], S[29], S[12], S[28],
S[17], S[1], S[15], S[23], S[26], S[5], S[18],
S[31], S[10], S[2], S[8], S[24], S[14], S[32],
S[27], S[3], S[9], S[19], S[13], S[30], S[6],
S[22], S[11], S[4], S[25]};
endmodule |
module key_sel3(K_sub, key1, key2, key3, roundSel, decrypt);
output [1:48] K_sub;
input [55:0] key1, key2, key3;
input [5:0] roundSel;
input decrypt;
wire decrypt_int;
reg [55:0] K;
reg [1:48] K_sub;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8, K9;
wire [1:48] K10, K11, K12, K13, K14, K15, K16;
always @(roundSel or decrypt or key1 or key2 or key3)
case ({decrypt, roundSel[5:4]}) // synopsys full_case parallel_case
3'b0_00: K = key1;
3'b0_01: K = key2;
3'b0_10: K = key3;
3'b1_00: K = key3;
3'b1_01: K = key2;
3'b1_10: K = key1;
endcase
assign decrypt_int = (roundSel[5:4]==2'h1) ? !decrypt : decrypt;
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or K9 or K10
or K11 or K12 or K13 or K14 or K15 or K16 or roundSel)
case(roundSel[3:0]) // synopsys full_case parallel_case
0: K_sub = K1;
1: K_sub = K2;
2: K_sub = K3;
3: K_sub = K4;
4: K_sub = K5;
5: K_sub = K6;
6: K_sub = K7;
7: K_sub = K8;
8: K_sub = K9;
9: K_sub = K10;
10: K_sub = K11;
11: K_sub = K12;
12: K_sub = K13;
13: K_sub = K14;
14: K_sub = K15;
15: K_sub = K16;
endcase
assign K16[1] = decrypt_int ? K[47] : K[40];
assign K16[2] = decrypt_int ? K[11] : K[4];
assign K16[3] = decrypt_int ? K[26] : K[19];
assign K16[4] = decrypt_int ? K[3] : K[53];
assign K16[5] = decrypt_int ? K[13] : K[6];
assign K16[6] = decrypt_int ? K[41] : K[34];
assign K16[7] = decrypt_int ? K[27] : K[20];
assign K16[8] = decrypt_int ? K[6] : K[24];
assign K16[9] = decrypt_int ? K[54] : K[47];
assign K16[10] = decrypt_int ? K[48] : K[41];
assign K16[11] = decrypt_int ? K[39] : K[32];
assign K16[12] = decrypt_int ? K[19] : K[12];
assign K16[13] = decrypt_int ? K[53] : K[46];
assign K16[14] = decrypt_int ? K[25] : K[18];
assign K16[15] = decrypt_int ? K[33] : K[26];
assign K16[16] = decrypt_int ? K[34] : K[27];
assign K16[17] = decrypt_int ? K[17] : K[10];
assign K16[18] = decrypt_int ? K[5] : K[55];
assign K16[19] = decrypt_int ? K[4] : K[54];
assign K16[20] = decrypt_int ? K[55] : K[48];
assign K16[21] = decrypt_int ? K[24] : K[17];
assign K16[22] = decrypt_int ? K[32] : K[25];
assign K16[23] = decrypt_int ? K[40] : K[33];
assign K16[24] = decrypt_int ? K[20] : K[13];
assign K16[25] = decrypt_int ? K[36] : K[29];
assign K16[26] = decrypt_int ? K[31] : K[51];
assign K16[27] = decrypt_int ? K[21] : K[14];
assign K16[28] = decrypt_int ? K[8] : K[1];
assign K16[29] = decrypt_int ? K[23] : K[16];
assign K16[30] = decrypt_int ? K[52] : K[45];
assign K16[31] = decrypt_int ? K[14] : K[7];
assign K16[32] = decrypt_int ? K[29] : K[22];
assign K16[33] = decrypt_int ? K[51] : K[44];
assign K16[34] = decrypt_int ? K[9] : K[2];
assign K16[35] = decrypt_int ? K[35] : K[28];
assign K16[36] = decrypt_int ? K[30] : K[23];
assign K16[37] = decrypt_int ? K[2] : K[50];
assign K16[38] = decrypt_int ? K[37] : K[30];
assign K16[39] = decrypt_int ? K[22] : K[15];
assign K16[40] = decrypt_int ? K[0] : K[52];
assign K16[41] = decrypt_int ? K[42] : K[35];
assign K16[42] = decrypt_int ? K[38] : K[31];
assign K16[43] = decrypt_int ? K[16] : K[9];
assign K16[44] = decrypt_int ? K[43] : K[36];
assign K16[45] = decrypt_int ? K[44] : K[37];
assign K16[46] = decrypt_int ? K[1] : K[49];
assign K16[47] = decrypt_int ? K[7] : K[0];
assign K16[48] = decrypt_int ? K[28] : K[21];
assign K15[1] = decrypt_int ? K[54] : K[33];
assign K15[2] = decrypt_int ? K[18] : K[54];
assign K15[3] = decrypt_int ? K[33] : K[12];
assign K15[4] = decrypt_int ? K[10] : K[46];
assign K15[5] = decrypt_int ? K[20] : K[24];
assign K15[6] = decrypt_int ? K[48] : K[27];
assign K15[7] = decrypt_int ? K[34] : K[13];
assign K15[8] = decrypt_int ? K[13] : K[17];
assign K15[9] = decrypt_int ? K[4] : K[40];
assign K15[10] = decrypt_int ? K[55] : K[34];
assign K15[11] = decrypt_int ? K[46] : K[25];
assign K15[12] = decrypt_int ? K[26] : K[5];
assign K15[13] = decrypt_int ? K[3] : K[39];
assign K15[14] = decrypt_int ? K[32] : K[11];
assign K15[15] = decrypt_int ? K[40] : K[19];
assign K15[16] = decrypt_int ? K[41] : K[20];
assign K15[17] = decrypt_int ? K[24] : K[3];
assign K15[18] = decrypt_int ? K[12] : K[48];
assign K15[19] = decrypt_int ? K[11] : K[47];
assign K15[20] = decrypt_int ? K[5] : K[41];
assign K15[21] = decrypt_int ? K[6] : K[10];
assign K15[22] = decrypt_int ? K[39] : K[18];
assign K15[23] = decrypt_int ? K[47] : K[26];
assign K15[24] = decrypt_int ? K[27] : K[6];
assign K15[25] = decrypt_int ? K[43] : K[22];
assign K15[26] = decrypt_int ? K[38] : K[44];
assign K15[27] = decrypt_int ? K[28] : K[7];
assign K15[28] = decrypt_int ? K[15] : K[49];
assign K15[29] = decrypt_int ? K[30] : K[9];
assign K15[30] = decrypt_int ? K[0] : K[38];
assign K15[31] = decrypt_int ? K[21] : K[0];
assign K15[32] = decrypt_int ? K[36] : K[15];
assign K15[33] = decrypt_int ? K[31] : K[37];
assign K15[34] = decrypt_int ? K[16] : K[50];
assign K15[35] = decrypt_int ? K[42] : K[21];
assign K15[36] = decrypt_int ? K[37] : K[16];
assign K15[37] = decrypt_int ? K[9] : K[43];
assign K15[38] = decrypt_int ? K[44] : K[23];
assign K15[39] = decrypt_int ? K[29] : K[8];
assign K15[40] = decrypt_int ? K[7] : K[45];
assign K15[41] = decrypt_int ? K[49] : K[28];
assign K15[42] = decrypt_int ? K[45] : K[51];
assign K15[43] = decrypt_int ? K[23] : K[2];
assign K15[44] = decrypt_int ? K[50] : K[29];
assign K15[45] = decrypt_int ? K[51] : K[30];
assign K15[46] = decrypt_int ? K[8] : K[42];
assign K15[47] = decrypt_int ? K[14] : K[52];
assign K15[48] = decrypt_int ? K[35] : K[14];
assign K14[1] = decrypt_int ? K[11] : K[19];
assign K14[2] = decrypt_int ? K[32] : K[40];
assign K14[3] = decrypt_int ? K[47] : K[55];
assign K14[4] = decrypt_int ? K[24] : K[32];
assign K14[5] = decrypt_int ? K[34] : K[10];
assign K14[6] = decrypt_int ? K[5] : K[13];
assign K14[7] = decrypt_int ? K[48] : K[24];
assign K14[8] = decrypt_int ? K[27] : K[3];
assign K14[9] = decrypt_int ? K[18] : K[26];
assign K14[10] = decrypt_int ? K[12] : K[20];
assign K14[11] = decrypt_int ? K[3] : K[11];
assign K14[12] = decrypt_int ? K[40] : K[48];
assign K14[13] = decrypt_int ? K[17] : K[25];
assign K14[14] = decrypt_int ? K[46] : K[54];
assign K14[15] = decrypt_int ? K[54] : K[5];
assign K14[16] = decrypt_int ? K[55] : K[6];
assign K14[17] = decrypt_int ? K[13] : K[46];
assign K14[18] = decrypt_int ? K[26] : K[34];
assign K14[19] = decrypt_int ? K[25] : K[33];
assign K14[20] = decrypt_int ? K[19] : K[27];
assign K14[21] = decrypt_int ? K[20] : K[53];
assign K14[22] = decrypt_int ? K[53] : K[4];
assign K14[23] = decrypt_int ? K[4] : K[12];
assign K14[24] = decrypt_int ? K[41] : K[17];
assign K14[25] = decrypt_int ? K[2] : K[8];
assign K14[26] = decrypt_int ? K[52] : K[30];
assign K14[27] = decrypt_int ? K[42] : K[52];
assign K14[28] = decrypt_int ? K[29] : K[35];
assign K14[29] = decrypt_int ? K[44] : K[50];
assign K14[30] = decrypt_int ? K[14] : K[51];
assign K14[31] = decrypt_int ? K[35] : K[45];
assign K14[32] = decrypt_int ? K[50] : K[1];
assign K14[33] = decrypt_int ? K[45] : K[23];
assign K14[34] = decrypt_int ? K[30] : K[36];
assign K14[35] = decrypt_int ? K[1] : K[7];
assign K14[36] = decrypt_int ? K[51] : K[2];
assign K14[37] = decrypt_int ? K[23] : K[29];
assign K14[38] = decrypt_int ? K[31] : K[9];
assign K14[39] = decrypt_int ? K[43] : K[49];
assign K14[40] = decrypt_int ? K[21] : K[31];
assign K14[41] = decrypt_int ? K[8] : K[14];
assign K14[42] = decrypt_int ? K[0] : K[37];
assign K14[43] = decrypt_int ? K[37] : K[43];
assign K14[44] = decrypt_int ? K[9] : K[15];
assign K14[45] = decrypt_int ? K[38] : K[16];
assign K14[46] = decrypt_int ? K[22] : K[28];
assign K14[47] = decrypt_int ? K[28] : K[38];
assign K14[48] = decrypt_int ? K[49] : K[0];
assign K13[1] = decrypt_int ? K[25] : K[5];
assign K13[2] = decrypt_int ? K[46] : K[26];
assign K13[3] = decrypt_int ? K[4] : K[41];
assign K13[4] = decrypt_int ? K[13] : K[18];
assign K13[5] = decrypt_int ? K[48] : K[53];
assign K13[6] = decrypt_int ? K[19] : K[24];
assign K13[7] = decrypt_int ? K[5] : K[10];
assign K13[8] = decrypt_int ? K[41] : K[46];
assign K13[9] = decrypt_int ? K[32] : K[12];
assign K13[10] = decrypt_int ? K[26] : K[6];
assign K13[11] = decrypt_int ? K[17] : K[54];
assign K13[12] = decrypt_int ? K[54] : K[34];
assign K13[13] = decrypt_int ? K[6] : K[11];
assign K13[14] = decrypt_int ? K[3] : K[40];
assign K13[15] = decrypt_int ? K[11] : K[48];
assign K13[16] = decrypt_int ? K[12] : K[17];
assign K13[17] = decrypt_int ? K[27] : K[32];
assign K13[18] = decrypt_int ? K[40] : K[20];
assign K13[19] = decrypt_int ? K[39] : K[19];
assign K13[20] = decrypt_int ? K[33] : K[13];
assign K13[21] = decrypt_int ? K[34] : K[39];
assign K13[22] = decrypt_int ? K[10] : K[47];
assign K13[23] = decrypt_int ? K[18] : K[55];
assign K13[24] = decrypt_int ? K[55] : K[3];
assign K13[25] = decrypt_int ? K[16] : K[49];
assign K13[26] = decrypt_int ? K[7] : K[16];
assign K13[27] = decrypt_int ? K[1] : K[38];
assign K13[28] = decrypt_int ? K[43] : K[21];
assign K13[29] = decrypt_int ? K[31] : K[36];
assign K13[30] = decrypt_int ? K[28] : K[37];
assign K13[31] = decrypt_int ? K[49] : K[31];
assign K13[32] = decrypt_int ? K[9] : K[42];
assign K13[33] = decrypt_int ? K[0] : K[9];
assign K13[34] = decrypt_int ? K[44] : K[22];
assign K13[35] = decrypt_int ? K[15] : K[52];
assign K13[36] = decrypt_int ? K[38] : K[43];
assign K13[37] = decrypt_int ? K[37] : K[15];
assign K13[38] = decrypt_int ? K[45] : K[50];
assign K13[39] = decrypt_int ? K[2] : K[35];
assign K13[40] = decrypt_int ? K[35] : K[44];
assign K13[41] = decrypt_int ? K[22] : K[0];
assign K13[42] = decrypt_int ? K[14] : K[23];
assign K13[43] = decrypt_int ? K[51] : K[29];
assign K13[44] = decrypt_int ? K[23] : K[1];
assign K13[45] = decrypt_int ? K[52] : K[2];
assign K13[46] = decrypt_int ? K[36] : K[14];
assign K13[47] = decrypt_int ? K[42] : K[51];
assign K13[48] = decrypt_int ? K[8] : K[45];
assign K12[1] = decrypt_int ? K[39] : K[48];
assign K12[2] = decrypt_int ? K[3] : K[12];
assign K12[3] = decrypt_int ? K[18] : K[27];
assign K12[4] = decrypt_int ? K[27] : K[4];
assign K12[5] = decrypt_int ? K[5] : K[39];
assign K12[6] = decrypt_int ? K[33] : K[10];
assign K12[7] = decrypt_int ? K[19] : K[53];
assign K12[8] = decrypt_int ? K[55] : K[32];
assign K12[9] = decrypt_int ? K[46] : K[55];
assign K12[10] = decrypt_int ? K[40] : K[17];
assign K12[11] = decrypt_int ? K[6] : K[40];
assign K12[12] = decrypt_int ? K[11] : K[20];
assign K12[13] = decrypt_int ? K[20] : K[54];
assign K12[14] = decrypt_int ? K[17] : K[26];
assign K12[15] = decrypt_int ? K[25] : K[34];
assign K12[16] = decrypt_int ? K[26] : K[3];
assign K12[17] = decrypt_int ? K[41] : K[18];
assign K12[18] = decrypt_int ? K[54] : K[6];
assign K12[19] = decrypt_int ? K[53] : K[5];
assign K12[20] = decrypt_int ? K[47] : K[24];
assign K12[21] = decrypt_int ? K[48] : K[25];
assign K12[22] = decrypt_int ? K[24] : K[33];
assign K12[23] = decrypt_int ? K[32] : K[41];
assign K12[24] = decrypt_int ? K[12] : K[46];
assign K12[25] = decrypt_int ? K[30] : K[35];
assign K12[26] = decrypt_int ? K[21] : K[2];
assign K12[27] = decrypt_int ? K[15] : K[51];
assign K12[28] = decrypt_int ? K[2] : K[7];
assign K12[29] = decrypt_int ? K[45] : K[22];
assign K12[30] = decrypt_int ? K[42] : K[23];
assign K12[31] = decrypt_int ? K[8] : K[44];
assign K12[32] = decrypt_int ? K[23] : K[28];
assign K12[33] = decrypt_int ? K[14] : K[50];
assign K12[34] = decrypt_int ? K[31] : K[8];
assign K12[35] = decrypt_int ? K[29] : K[38];
assign K12[36] = decrypt_int ? K[52] : K[29];
assign K12[37] = decrypt_int ? K[51] : K[1];
assign K12[38] = decrypt_int ? K[0] : K[36];
assign K12[39] = decrypt_int ? K[16] : K[21];
assign K12[40] = decrypt_int ? K[49] : K[30];
assign K12[41] = decrypt_int ? K[36] : K[45];
assign K12[42] = decrypt_int ? K[28] : K[9];
assign K12[43] = decrypt_int ? K[38] : K[15];
assign K12[44] = decrypt_int ? K[37] : K[42];
assign K12[45] = decrypt_int ? K[7] : K[43];
assign K12[46] = decrypt_int ? K[50] : K[0];
assign K12[47] = decrypt_int ? K[1] : K[37];
assign K12[48] = decrypt_int ? K[22] : K[31];
assign K11[1] = decrypt_int ? K[53] : K[34];
assign K11[2] = decrypt_int ? K[17] : K[55];
assign K11[3] = decrypt_int ? K[32] : K[13];
assign K11[4] = decrypt_int ? K[41] : K[47];
assign K11[5] = decrypt_int ? K[19] : K[25];
assign K11[6] = decrypt_int ? K[47] : K[53];
assign K11[7] = decrypt_int ? K[33] : K[39];
assign K11[8] = decrypt_int ? K[12] : K[18];
assign K11[9] = decrypt_int ? K[3] : K[41];
assign K11[10] = decrypt_int ? K[54] : K[3];
assign K11[11] = decrypt_int ? K[20] : K[26];
assign K11[12] = decrypt_int ? K[25] : K[6];
assign K11[13] = decrypt_int ? K[34] : K[40];
assign K11[14] = decrypt_int ? K[6] : K[12];
assign K11[15] = decrypt_int ? K[39] : K[20];
assign K11[16] = decrypt_int ? K[40] : K[46];
assign K11[17] = decrypt_int ? K[55] : K[4];
assign K11[18] = decrypt_int ? K[11] : K[17];
assign K11[19] = decrypt_int ? K[10] : K[48];
assign K11[20] = decrypt_int ? K[4] : K[10];
assign K11[21] = decrypt_int ? K[5] : K[11];
assign K11[22] = decrypt_int ? K[13] : K[19];
assign K11[23] = decrypt_int ? K[46] : K[27];
assign K11[24] = decrypt_int ? K[26] : K[32];
assign K11[25] = decrypt_int ? K[44] : K[21];
assign K11[26] = decrypt_int ? K[35] : K[43];
assign K11[27] = decrypt_int ? K[29] : K[37];
assign K11[28] = decrypt_int ? K[16] : K[52];
assign K11[29] = decrypt_int ? K[0] : K[8];
assign K11[30] = decrypt_int ? K[1] : K[9];
assign K11[31] = decrypt_int ? K[22] : K[30];
assign K11[32] = decrypt_int ? K[37] : K[14];
assign K11[33] = decrypt_int ? K[28] : K[36];
assign K11[34] = decrypt_int ? K[45] : K[49];
assign K11[35] = decrypt_int ? K[43] : K[51];
assign K11[36] = decrypt_int ? K[7] : K[15];
assign K11[37] = decrypt_int ? K[38] : K[42];
assign K11[38] = decrypt_int ? K[14] : K[22];
assign K11[39] = decrypt_int ? K[30] : K[7];
assign K11[40] = decrypt_int ? K[8] : K[16];
assign K11[41] = decrypt_int ? K[50] : K[31];
assign K11[42] = decrypt_int ? K[42] : K[50];
assign K11[43] = decrypt_int ? K[52] : K[1];
assign K11[44] = decrypt_int ? K[51] : K[28];
assign K11[45] = decrypt_int ? K[21] : K[29];
assign K11[46] = decrypt_int ? K[9] : K[45];
assign K11[47] = decrypt_int ? K[15] : K[23];
assign K11[48] = decrypt_int ? K[36] : K[44];
assign K10[1] = decrypt_int ? K[10] : K[20];
assign K10[2] = decrypt_int ? K[6] : K[41];
assign K10[3] = decrypt_int ? K[46] : K[24];
assign K10[4] = decrypt_int ? K[55] : K[33];
assign K10[5] = decrypt_int ? K[33] : K[11];
assign K10[6] = decrypt_int ? K[4] : K[39];
assign K10[7] = decrypt_int ? K[47] : K[25];
assign K10[8] = decrypt_int ? K[26] : K[4];
assign K10[9] = decrypt_int ? K[17] : K[27];
assign K10[10] = decrypt_int ? K[11] : K[46];
assign K10[11] = decrypt_int ? K[34] : K[12];
assign K10[12] = decrypt_int ? K[39] : K[17];
assign K10[13] = decrypt_int ? K[48] : K[26];
assign K10[14] = decrypt_int ? K[20] : K[55];
assign K10[15] = decrypt_int ? K[53] : K[6];
assign K10[16] = decrypt_int ? K[54] : K[32];
assign K10[17] = decrypt_int ? K[12] : K[47];
assign K10[18] = decrypt_int ? K[25] : K[3];
assign K10[19] = decrypt_int ? K[24] : K[34];
assign K10[20] = decrypt_int ? K[18] : K[53];
assign K10[21] = decrypt_int ? K[19] : K[54];
assign K10[22] = decrypt_int ? K[27] : K[5];
assign K10[23] = decrypt_int ? K[3] : K[13];
assign K10[24] = decrypt_int ? K[40] : K[18];
assign K10[25] = decrypt_int ? K[31] : K[7];
assign K10[26] = decrypt_int ? K[49] : K[29];
assign K10[27] = decrypt_int ? K[43] : K[23];
assign K10[28] = decrypt_int ? K[30] : K[38];
assign K10[29] = decrypt_int ? K[14] : K[49];
assign K10[30] = decrypt_int ? K[15] : K[50];
assign K10[31] = decrypt_int ? K[36] : K[16];
assign K10[32] = decrypt_int ? K[51] : K[0];
assign K10[33] = decrypt_int ? K[42] : K[22];
assign K10[34] = decrypt_int ? K[0] : K[35];
assign K10[35] = decrypt_int ? K[2] : K[37];
assign K10[36] = decrypt_int ? K[21] : K[1];
assign K10[37] = decrypt_int ? K[52] : K[28];
assign K10[38] = decrypt_int ? K[28] : K[8];
assign K10[39] = decrypt_int ? K[44] : K[52];
assign K10[40] = decrypt_int ? K[22] : K[2];
assign K10[41] = decrypt_int ? K[9] : K[44];
assign K10[42] = decrypt_int ? K[1] : K[36];
assign K10[43] = decrypt_int ? K[7] : K[42];
assign K10[44] = decrypt_int ? K[38] : K[14];
assign K10[45] = decrypt_int ? K[35] : K[15];
assign K10[46] = decrypt_int ? K[23] : K[31];
assign K10[47] = decrypt_int ? K[29] : K[9];
assign K10[48] = decrypt_int ? K[50] : K[30];
assign K9[1] = decrypt_int ? K[24] : K[6];
assign K9[2] = decrypt_int ? K[20] : K[27];
assign K9[3] = decrypt_int ? K[3] : K[10];
assign K9[4] = decrypt_int ? K[12] : K[19];
assign K9[5] = decrypt_int ? K[47] : K[54];
assign K9[6] = decrypt_int ? K[18] : K[25];
assign K9[7] = decrypt_int ? K[4] : K[11];
assign K9[8] = decrypt_int ? K[40] : K[47];
assign K9[9] = decrypt_int ? K[6] : K[13];
assign K9[10] = decrypt_int ? K[25] : K[32];
assign K9[11] = decrypt_int ? K[48] : K[55];
assign K9[12] = decrypt_int ? K[53] : K[3];
assign K9[13] = decrypt_int ? K[5] : K[12];
assign K9[14] = decrypt_int ? K[34] : K[41];
assign K9[15] = decrypt_int ? K[10] : K[17];
assign K9[16] = decrypt_int ? K[11] : K[18];
assign K9[17] = decrypt_int ? K[26] : K[33];
assign K9[18] = decrypt_int ? K[39] : K[46];
assign K9[19] = decrypt_int ? K[13] : K[20];
assign K9[20] = decrypt_int ? K[32] : K[39];
assign K9[21] = decrypt_int ? K[33] : K[40];
assign K9[22] = decrypt_int ? K[41] : K[48];
assign K9[23] = decrypt_int ? K[17] : K[24];
assign K9[24] = decrypt_int ? K[54] : K[4];
assign K9[25] = decrypt_int ? K[45] : K[52];
assign K9[26] = decrypt_int ? K[8] : K[15];
assign K9[27] = decrypt_int ? K[2] : K[9];
assign K9[28] = decrypt_int ? K[44] : K[51];
assign K9[29] = decrypt_int ? K[28] : K[35];
assign K9[30] = decrypt_int ? K[29] : K[36];
assign K9[31] = decrypt_int ? K[50] : K[2];
assign K9[32] = decrypt_int ? K[38] : K[45];
assign K9[33] = decrypt_int ? K[1] : K[8];
assign K9[34] = decrypt_int ? K[14] : K[21];
assign K9[35] = decrypt_int ? K[16] : K[23];
assign K9[36] = decrypt_int ? K[35] : K[42];
assign K9[37] = decrypt_int ? K[7] : K[14];
assign K9[38] = decrypt_int ? K[42] : K[49];
assign K9[39] = decrypt_int ? K[31] : K[38];
assign K9[40] = decrypt_int ? K[36] : K[43];
assign K9[41] = decrypt_int ? K[23] : K[30];
assign K9[42] = decrypt_int ? K[15] : K[22];
assign K9[43] = decrypt_int ? K[21] : K[28];
assign K9[44] = decrypt_int ? K[52] : K[0];
assign K9[45] = decrypt_int ? K[49] : K[1];
assign K9[46] = decrypt_int ? K[37] : K[44];
assign K9[47] = decrypt_int ? K[43] : K[50];
assign K9[48] = decrypt_int ? K[9] : K[16];
assign K8[1] = decrypt_int ? K[6] : K[24];
assign K8[2] = decrypt_int ? K[27] : K[20];
assign K8[3] = decrypt_int ? K[10] : K[3];
assign K8[4] = decrypt_int ? K[19] : K[12];
assign K8[5] = decrypt_int ? K[54] : K[47];
assign K8[6] = decrypt_int ? K[25] : K[18];
assign K8[7] = decrypt_int ? K[11] : K[4];
assign K8[8] = decrypt_int ? K[47] : K[40];
assign K8[9] = decrypt_int ? K[13] : K[6];
assign K8[10] = decrypt_int ? K[32] : K[25];
assign K8[11] = decrypt_int ? K[55] : K[48];
assign K8[12] = decrypt_int ? K[3] : K[53];
assign K8[13] = decrypt_int ? K[12] : K[5];
assign K8[14] = decrypt_int ? K[41] : K[34];
assign K8[15] = decrypt_int ? K[17] : K[10];
assign K8[16] = decrypt_int ? K[18] : K[11];
assign K8[17] = decrypt_int ? K[33] : K[26];
assign K8[18] = decrypt_int ? K[46] : K[39];
assign K8[19] = decrypt_int ? K[20] : K[13];
assign K8[20] = decrypt_int ? K[39] : K[32];
assign K8[21] = decrypt_int ? K[40] : K[33];
assign K8[22] = decrypt_int ? K[48] : K[41];
assign K8[23] = decrypt_int ? K[24] : K[17];
assign K8[24] = decrypt_int ? K[4] : K[54];
assign K8[25] = decrypt_int ? K[52] : K[45];
assign K8[26] = decrypt_int ? K[15] : K[8];
assign K8[27] = decrypt_int ? K[9] : K[2];
assign K8[28] = decrypt_int ? K[51] : K[44];
assign K8[29] = decrypt_int ? K[35] : K[28];
assign K8[30] = decrypt_int ? K[36] : K[29];
assign K8[31] = decrypt_int ? K[2] : K[50];
assign K8[32] = decrypt_int ? K[45] : K[38];
assign K8[33] = decrypt_int ? K[8] : K[1];
assign K8[34] = decrypt_int ? K[21] : K[14];
assign K8[35] = decrypt_int ? K[23] : K[16];
assign K8[36] = decrypt_int ? K[42] : K[35];
assign K8[37] = decrypt_int ? K[14] : K[7];
assign K8[38] = decrypt_int ? K[49] : K[42];
assign K8[39] = decrypt_int ? K[38] : K[31];
assign K8[40] = decrypt_int ? K[43] : K[36];
assign K8[41] = decrypt_int ? K[30] : K[23];
assign K8[42] = decrypt_int ? K[22] : K[15];
assign K8[43] = decrypt_int ? K[28] : K[21];
assign K8[44] = decrypt_int ? K[0] : K[52];
assign K8[45] = decrypt_int ? K[1] : K[49];
assign K8[46] = decrypt_int ? K[44] : K[37];
assign K8[47] = decrypt_int ? K[50] : K[43];
assign K8[48] = decrypt_int ? K[16] : K[9];
assign K7[1] = decrypt_int ? K[20] : K[10];
assign K7[2] = decrypt_int ? K[41] : K[6];
assign K7[3] = decrypt_int ? K[24] : K[46];
assign K7[4] = decrypt_int ? K[33] : K[55];
assign K7[5] = decrypt_int ? K[11] : K[33];
assign K7[6] = decrypt_int ? K[39] : K[4];
assign K7[7] = decrypt_int ? K[25] : K[47];
assign K7[8] = decrypt_int ? K[4] : K[26];
assign K7[9] = decrypt_int ? K[27] : K[17];
assign K7[10] = decrypt_int ? K[46] : K[11];
assign K7[11] = decrypt_int ? K[12] : K[34];
assign K7[12] = decrypt_int ? K[17] : K[39];
assign K7[13] = decrypt_int ? K[26] : K[48];
assign K7[14] = decrypt_int ? K[55] : K[20];
assign K7[15] = decrypt_int ? K[6] : K[53];
assign K7[16] = decrypt_int ? K[32] : K[54];
assign K7[17] = decrypt_int ? K[47] : K[12];
assign K7[18] = decrypt_int ? K[3] : K[25];
assign K7[19] = decrypt_int ? K[34] : K[24];
assign K7[20] = decrypt_int ? K[53] : K[18];
assign K7[21] = decrypt_int ? K[54] : K[19];
assign K7[22] = decrypt_int ? K[5] : K[27];
assign K7[23] = decrypt_int ? K[13] : K[3];
assign K7[24] = decrypt_int ? K[18] : K[40];
assign K7[25] = decrypt_int ? K[7] : K[31];
assign K7[26] = decrypt_int ? K[29] : K[49];
assign K7[27] = decrypt_int ? K[23] : K[43];
assign K7[28] = decrypt_int ? K[38] : K[30];
assign K7[29] = decrypt_int ? K[49] : K[14];
assign K7[30] = decrypt_int ? K[50] : K[15];
assign K7[31] = decrypt_int ? K[16] : K[36];
assign K7[32] = decrypt_int ? K[0] : K[51];
assign K7[33] = decrypt_int ? K[22] : K[42];
assign K7[34] = decrypt_int ? K[35] : K[0];
assign K7[35] = decrypt_int ? K[37] : K[2];
assign K7[36] = decrypt_int ? K[1] : K[21];
assign K7[37] = decrypt_int ? K[28] : K[52];
assign K7[38] = decrypt_int ? K[8] : K[28];
assign K7[39] = decrypt_int ? K[52] : K[44];
assign K7[40] = decrypt_int ? K[2] : K[22];
assign K7[41] = decrypt_int ? K[44] : K[9];
assign K7[42] = decrypt_int ? K[36] : K[1];
assign K7[43] = decrypt_int ? K[42] : K[7];
assign K7[44] = decrypt_int ? K[14] : K[38];
assign K7[45] = decrypt_int ? K[15] : K[35];
assign K7[46] = decrypt_int ? K[31] : K[23];
assign K7[47] = decrypt_int ? K[9] : K[29];
assign K7[48] = decrypt_int ? K[30] : K[50];
assign K6[1] = decrypt_int ? K[34] : K[53];
assign K6[2] = decrypt_int ? K[55] : K[17];
assign K6[3] = decrypt_int ? K[13] : K[32];
assign K6[4] = decrypt_int ? K[47] : K[41];
assign K6[5] = decrypt_int ? K[25] : K[19];
assign K6[6] = decrypt_int ? K[53] : K[47];
assign K6[7] = decrypt_int ? K[39] : K[33];
assign K6[8] = decrypt_int ? K[18] : K[12];
assign K6[9] = decrypt_int ? K[41] : K[3];
assign K6[10] = decrypt_int ? K[3] : K[54];
assign K6[11] = decrypt_int ? K[26] : K[20];
assign K6[12] = decrypt_int ? K[6] : K[25];
assign K6[13] = decrypt_int ? K[40] : K[34];
assign K6[14] = decrypt_int ? K[12] : K[6];
assign K6[15] = decrypt_int ? K[20] : K[39];
assign K6[16] = decrypt_int ? K[46] : K[40];
assign K6[17] = decrypt_int ? K[4] : K[55];
assign K6[18] = decrypt_int ? K[17] : K[11];
assign K6[19] = decrypt_int ? K[48] : K[10];
assign K6[20] = decrypt_int ? K[10] : K[4];
assign K6[21] = decrypt_int ? K[11] : K[5];
assign K6[22] = decrypt_int ? K[19] : K[13];
assign K6[23] = decrypt_int ? K[27] : K[46];
assign K6[24] = decrypt_int ? K[32] : K[26];
assign K6[25] = decrypt_int ? K[21] : K[44];
assign K6[26] = decrypt_int ? K[43] : K[35];
assign K6[27] = decrypt_int ? K[37] : K[29];
assign K6[28] = decrypt_int ? K[52] : K[16];
assign K6[29] = decrypt_int ? K[8] : K[0];
assign K6[30] = decrypt_int ? K[9] : K[1];
assign K6[31] = decrypt_int ? K[30] : K[22];
assign K6[32] = decrypt_int ? K[14] : K[37];
assign K6[33] = decrypt_int ? K[36] : K[28];
assign K6[34] = decrypt_int ? K[49] : K[45];
assign K6[35] = decrypt_int ? K[51] : K[43];
assign K6[36] = decrypt_int ? K[15] : K[7];
assign K6[37] = decrypt_int ? K[42] : K[38];
assign K6[38] = decrypt_int ? K[22] : K[14];
assign K6[39] = decrypt_int ? K[7] : K[30];
assign K6[40] = decrypt_int ? K[16] : K[8];
assign K6[41] = decrypt_int ? K[31] : K[50];
assign K6[42] = decrypt_int ? K[50] : K[42];
assign K6[43] = decrypt_int ? K[1] : K[52];
assign K6[44] = decrypt_int ? K[28] : K[51];
assign K6[45] = decrypt_int ? K[29] : K[21];
assign K6[46] = decrypt_int ? K[45] : K[9];
assign K6[47] = decrypt_int ? K[23] : K[15];
assign K6[48] = decrypt_int ? K[44] : K[36];
assign K5[1] = decrypt_int ? K[48] : K[39];
assign K5[2] = decrypt_int ? K[12] : K[3];
assign K5[3] = decrypt_int ? K[27] : K[18];
assign K5[4] = decrypt_int ? K[4] : K[27];
assign K5[5] = decrypt_int ? K[39] : K[5];
assign K5[6] = decrypt_int ? K[10] : K[33];
assign K5[7] = decrypt_int ? K[53] : K[19];
assign K5[8] = decrypt_int ? K[32] : K[55];
assign K5[9] = decrypt_int ? K[55] : K[46];
assign K5[10] = decrypt_int ? K[17] : K[40];
assign K5[11] = decrypt_int ? K[40] : K[6];
assign K5[12] = decrypt_int ? K[20] : K[11];
assign K5[13] = decrypt_int ? K[54] : K[20];
assign K5[14] = decrypt_int ? K[26] : K[17];
assign K5[15] = decrypt_int ? K[34] : K[25];
assign K5[16] = decrypt_int ? K[3] : K[26];
assign K5[17] = decrypt_int ? K[18] : K[41];
assign K5[18] = decrypt_int ? K[6] : K[54];
assign K5[19] = decrypt_int ? K[5] : K[53];
assign K5[20] = decrypt_int ? K[24] : K[47];
assign K5[21] = decrypt_int ? K[25] : K[48];
assign K5[22] = decrypt_int ? K[33] : K[24];
assign K5[23] = decrypt_int ? K[41] : K[32];
assign K5[24] = decrypt_int ? K[46] : K[12];
assign K5[25] = decrypt_int ? K[35] : K[30];
assign K5[26] = decrypt_int ? K[2] : K[21];
assign K5[27] = decrypt_int ? K[51] : K[15];
assign K5[28] = decrypt_int ? K[7] : K[2];
assign K5[29] = decrypt_int ? K[22] : K[45];
assign K5[30] = decrypt_int ? K[23] : K[42];
assign K5[31] = decrypt_int ? K[44] : K[8];
assign K5[32] = decrypt_int ? K[28] : K[23];
assign K5[33] = decrypt_int ? K[50] : K[14];
assign K5[34] = decrypt_int ? K[8] : K[31];
assign K5[35] = decrypt_int ? K[38] : K[29];
assign K5[36] = decrypt_int ? K[29] : K[52];
assign K5[37] = decrypt_int ? K[1] : K[51];
assign K5[38] = decrypt_int ? K[36] : K[0];
assign K5[39] = decrypt_int ? K[21] : K[16];
assign K5[40] = decrypt_int ? K[30] : K[49];
assign K5[41] = decrypt_int ? K[45] : K[36];
assign K5[42] = decrypt_int ? K[9] : K[28];
assign K5[43] = decrypt_int ? K[15] : K[38];
assign K5[44] = decrypt_int ? K[42] : K[37];
assign K5[45] = decrypt_int ? K[43] : K[7];
assign K5[46] = decrypt_int ? K[0] : K[50];
assign K5[47] = decrypt_int ? K[37] : K[1];
assign K5[48] = decrypt_int ? K[31] : K[22];
assign K4[1] = decrypt_int ? K[5] : K[25];
assign K4[2] = decrypt_int ? K[26] : K[46];
assign K4[3] = decrypt_int ? K[41] : K[4];
assign K4[4] = decrypt_int ? K[18] : K[13];
assign K4[5] = decrypt_int ? K[53] : K[48];
assign K4[6] = decrypt_int ? K[24] : K[19];
assign K4[7] = decrypt_int ? K[10] : K[5];
assign K4[8] = decrypt_int ? K[46] : K[41];
assign K4[9] = decrypt_int ? K[12] : K[32];
assign K4[10] = decrypt_int ? K[6] : K[26];
assign K4[11] = decrypt_int ? K[54] : K[17];
assign K4[12] = decrypt_int ? K[34] : K[54];
assign K4[13] = decrypt_int ? K[11] : K[6];
assign K4[14] = decrypt_int ? K[40] : K[3];
assign K4[15] = decrypt_int ? K[48] : K[11];
assign K4[16] = decrypt_int ? K[17] : K[12];
assign K4[17] = decrypt_int ? K[32] : K[27];
assign K4[18] = decrypt_int ? K[20] : K[40];
assign K4[19] = decrypt_int ? K[19] : K[39];
assign K4[20] = decrypt_int ? K[13] : K[33];
assign K4[21] = decrypt_int ? K[39] : K[34];
assign K4[22] = decrypt_int ? K[47] : K[10];
assign K4[23] = decrypt_int ? K[55] : K[18];
assign K4[24] = decrypt_int ? K[3] : K[55];
assign K4[25] = decrypt_int ? K[49] : K[16];
assign K4[26] = decrypt_int ? K[16] : K[7];
assign K4[27] = decrypt_int ? K[38] : K[1];
assign K4[28] = decrypt_int ? K[21] : K[43];
assign K4[29] = decrypt_int ? K[36] : K[31];
assign K4[30] = decrypt_int ? K[37] : K[28];
assign K4[31] = decrypt_int ? K[31] : K[49];
assign K4[32] = decrypt_int ? K[42] : K[9];
assign K4[33] = decrypt_int ? K[9] : K[0];
assign K4[34] = decrypt_int ? K[22] : K[44];
assign K4[35] = decrypt_int ? K[52] : K[15];
assign K4[36] = decrypt_int ? K[43] : K[38];
assign K4[37] = decrypt_int ? K[15] : K[37];
assign K4[38] = decrypt_int ? K[50] : K[45];
assign K4[39] = decrypt_int ? K[35] : K[2];
assign K4[40] = decrypt_int ? K[44] : K[35];
assign K4[41] = decrypt_int ? K[0] : K[22];
assign K4[42] = decrypt_int ? K[23] : K[14];
assign K4[43] = decrypt_int ? K[29] : K[51];
assign K4[44] = decrypt_int ? K[1] : K[23];
assign K4[45] = decrypt_int ? K[2] : K[52];
assign K4[46] = decrypt_int ? K[14] : K[36];
assign K4[47] = decrypt_int ? K[51] : K[42];
assign K4[48] = decrypt_int ? K[45] : K[8];
assign K3[1] = decrypt_int ? K[19] : K[11];
assign K3[2] = decrypt_int ? K[40] : K[32];
assign K3[3] = decrypt_int ? K[55] : K[47];
assign K3[4] = decrypt_int ? K[32] : K[24];
assign K3[5] = decrypt_int ? K[10] : K[34];
assign K3[6] = decrypt_int ? K[13] : K[5];
assign K3[7] = decrypt_int ? K[24] : K[48];
assign K3[8] = decrypt_int ? K[3] : K[27];
assign K3[9] = decrypt_int ? K[26] : K[18];
assign K3[10] = decrypt_int ? K[20] : K[12];
assign K3[11] = decrypt_int ? K[11] : K[3];
assign K3[12] = decrypt_int ? K[48] : K[40];
assign K3[13] = decrypt_int ? K[25] : K[17];
assign K3[14] = decrypt_int ? K[54] : K[46];
assign K3[15] = decrypt_int ? K[5] : K[54];
assign K3[16] = decrypt_int ? K[6] : K[55];
assign K3[17] = decrypt_int ? K[46] : K[13];
assign K3[18] = decrypt_int ? K[34] : K[26];
assign K3[19] = decrypt_int ? K[33] : K[25];
assign K3[20] = decrypt_int ? K[27] : K[19];
assign K3[21] = decrypt_int ? K[53] : K[20];
assign K3[22] = decrypt_int ? K[4] : K[53];
assign K3[23] = decrypt_int ? K[12] : K[4];
assign K3[24] = decrypt_int ? K[17] : K[41];
assign K3[25] = decrypt_int ? K[8] : K[2];
assign K3[26] = decrypt_int ? K[30] : K[52];
assign K3[27] = decrypt_int ? K[52] : K[42];
assign K3[28] = decrypt_int ? K[35] : K[29];
assign K3[29] = decrypt_int ? K[50] : K[44];
assign K3[30] = decrypt_int ? K[51] : K[14];
assign K3[31] = decrypt_int ? K[45] : K[35];
assign K3[32] = decrypt_int ? K[1] : K[50];
assign K3[33] = decrypt_int ? K[23] : K[45];
assign K3[34] = decrypt_int ? K[36] : K[30];
assign K3[35] = decrypt_int ? K[7] : K[1];
assign K3[36] = decrypt_int ? K[2] : K[51];
assign K3[37] = decrypt_int ? K[29] : K[23];
assign K3[38] = decrypt_int ? K[9] : K[31];
assign K3[39] = decrypt_int ? K[49] : K[43];
assign K3[40] = decrypt_int ? K[31] : K[21];
assign K3[41] = decrypt_int ? K[14] : K[8];
assign K3[42] = decrypt_int ? K[37] : K[0];
assign K3[43] = decrypt_int ? K[43] : K[37];
assign K3[44] = decrypt_int ? K[15] : K[9];
assign K3[45] = decrypt_int ? K[16] : K[38];
assign K3[46] = decrypt_int ? K[28] : K[22];
assign K3[47] = decrypt_int ? K[38] : K[28];
assign K3[48] = decrypt_int ? K[0] : K[49];
assign K2[1] = decrypt_int ? K[33] : K[54];
assign K2[2] = decrypt_int ? K[54] : K[18];
assign K2[3] = decrypt_int ? K[12] : K[33];
assign K2[4] = decrypt_int ? K[46] : K[10];
assign K2[5] = decrypt_int ? K[24] : K[20];
assign K2[6] = decrypt_int ? K[27] : K[48];
assign K2[7] = decrypt_int ? K[13] : K[34];
assign K2[8] = decrypt_int ? K[17] : K[13];
assign K2[9] = decrypt_int ? K[40] : K[4];
assign K2[10] = decrypt_int ? K[34] : K[55];
assign K2[11] = decrypt_int ? K[25] : K[46];
assign K2[12] = decrypt_int ? K[5] : K[26];
assign K2[13] = decrypt_int ? K[39] : K[3];
assign K2[14] = decrypt_int ? K[11] : K[32];
assign K2[15] = decrypt_int ? K[19] : K[40];
assign K2[16] = decrypt_int ? K[20] : K[41];
assign K2[17] = decrypt_int ? K[3] : K[24];
assign K2[18] = decrypt_int ? K[48] : K[12];
assign K2[19] = decrypt_int ? K[47] : K[11];
assign K2[20] = decrypt_int ? K[41] : K[5];
assign K2[21] = decrypt_int ? K[10] : K[6];
assign K2[22] = decrypt_int ? K[18] : K[39];
assign K2[23] = decrypt_int ? K[26] : K[47];
assign K2[24] = decrypt_int ? K[6] : K[27];
assign K2[25] = decrypt_int ? K[22] : K[43];
assign K2[26] = decrypt_int ? K[44] : K[38];
assign K2[27] = decrypt_int ? K[7] : K[28];
assign K2[28] = decrypt_int ? K[49] : K[15];
assign K2[29] = decrypt_int ? K[9] : K[30];
assign K2[30] = decrypt_int ? K[38] : K[0];
assign K2[31] = decrypt_int ? K[0] : K[21];
assign K2[32] = decrypt_int ? K[15] : K[36];
assign K2[33] = decrypt_int ? K[37] : K[31];
assign K2[34] = decrypt_int ? K[50] : K[16];
assign K2[35] = decrypt_int ? K[21] : K[42];
assign K2[36] = decrypt_int ? K[16] : K[37];
assign K2[37] = decrypt_int ? K[43] : K[9];
assign K2[38] = decrypt_int ? K[23] : K[44];
assign K2[39] = decrypt_int ? K[8] : K[29];
assign K2[40] = decrypt_int ? K[45] : K[7];
assign K2[41] = decrypt_int ? K[28] : K[49];
assign K2[42] = decrypt_int ? K[51] : K[45];
assign K2[43] = decrypt_int ? K[2] : K[23];
assign K2[44] = decrypt_int ? K[29] : K[50];
assign K2[45] = decrypt_int ? K[30] : K[51];
assign K2[46] = decrypt_int ? K[42] : K[8];
assign K2[47] = decrypt_int ? K[52] : K[14];
assign K2[48] = decrypt_int ? K[14] : K[35];
assign K1[1] = decrypt_int ? K[40] : K[47];
assign K1[2] = decrypt_int ? K[4] : K[11];
assign K1[3] = decrypt_int ? K[19] : K[26];
assign K1[4] = decrypt_int ? K[53] : K[3];
assign K1[5] = decrypt_int ? K[6] : K[13];
assign K1[6] = decrypt_int ? K[34] : K[41];
assign K1[7] = decrypt_int ? K[20] : K[27];
assign K1[8] = decrypt_int ? K[24] : K[6];
assign K1[9] = decrypt_int ? K[47] : K[54];
assign K1[10] = decrypt_int ? K[41] : K[48];
assign K1[11] = decrypt_int ? K[32] : K[39];
assign K1[12] = decrypt_int ? K[12] : K[19];
assign K1[13] = decrypt_int ? K[46] : K[53];
assign K1[14] = decrypt_int ? K[18] : K[25];
assign K1[15] = decrypt_int ? K[26] : K[33];
assign K1[16] = decrypt_int ? K[27] : K[34];
assign K1[17] = decrypt_int ? K[10] : K[17];
assign K1[18] = decrypt_int ? K[55] : K[5];
assign K1[19] = decrypt_int ? K[54] : K[4];
assign K1[20] = decrypt_int ? K[48] : K[55];
assign K1[21] = decrypt_int ? K[17] : K[24];
assign K1[22] = decrypt_int ? K[25] : K[32];
assign K1[23] = decrypt_int ? K[33] : K[40];
assign K1[24] = decrypt_int ? K[13] : K[20];
assign K1[25] = decrypt_int ? K[29] : K[36];
assign K1[26] = decrypt_int ? K[51] : K[31];
assign K1[27] = decrypt_int ? K[14] : K[21];
assign K1[28] = decrypt_int ? K[1] : K[8];
assign K1[29] = decrypt_int ? K[16] : K[23];
assign K1[30] = decrypt_int ? K[45] : K[52];
assign K1[31] = decrypt_int ? K[7] : K[14];
assign K1[32] = decrypt_int ? K[22] : K[29];
assign K1[33] = decrypt_int ? K[44] : K[51];
assign K1[34] = decrypt_int ? K[2] : K[9];
assign K1[35] = decrypt_int ? K[28] : K[35];
assign K1[36] = decrypt_int ? K[23] : K[30];
assign K1[37] = decrypt_int ? K[50] : K[2];
assign K1[38] = decrypt_int ? K[30] : K[37];
assign K1[39] = decrypt_int ? K[15] : K[22];
assign K1[40] = decrypt_int ? K[52] : K[0];
assign K1[41] = decrypt_int ? K[35] : K[42];
assign K1[42] = decrypt_int ? K[31] : K[38];
assign K1[43] = decrypt_int ? K[9] : K[16];
assign K1[44] = decrypt_int ? K[36] : K[43];
assign K1[45] = decrypt_int ? K[37] : K[44];
assign K1[46] = decrypt_int ? K[49] : K[1];
assign K1[47] = decrypt_int ? K[0] : K[7];
assign K1[48] = decrypt_int ? K[21] : K[28];
endmodule |
module sbox5(addr, dout);
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
always @(addr) begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0: dout = 2;
1: dout = 12;
2: dout = 4;
3: dout = 1;
4: dout = 7;
5: dout = 10;
6: dout = 11;
7: dout = 6;
8: dout = 8;
9: dout = 5;
10: dout = 3;
11: dout = 15;
12: dout = 13;
13: dout = 0;
14: dout = 14;
15: dout = 9;
16: dout = 14;
17: dout = 11;
18: dout = 2;
19: dout = 12;
20: dout = 4;
21: dout = 7;
22: dout = 13;
23: dout = 1;
24: dout = 5;
25: dout = 0;
26: dout = 15;
27: dout = 10;
28: dout = 3;
29: dout = 9;
30: dout = 8;
31: dout = 6;
32: dout = 4;
33: dout = 2;
34: dout = 1;
35: dout = 11;
36: dout = 10;
37: dout = 13;
38: dout = 7;
39: dout = 8;
40: dout = 15;
41: dout = 9;
42: dout = 12;
43: dout = 5;
44: dout = 6;
45: dout = 3;
46: dout = 0;
47: dout = 14;
48: dout = 11;
49: dout = 8;
50: dout = 12;
51: dout = 7;
52: dout = 1;
53: dout = 14;
54: dout = 2;
55: dout = 13;
56: dout = 6;
57: dout = 15;
58: dout = 0;
59: dout = 9;
60: dout = 10;
61: dout = 4;
62: dout = 5;
63: dout = 3;
endcase
end
endmodule |
module sbox4(addr, dout);
input [1:6] addr;
output [1:4] dout;
reg [1:4] dout;
always @(addr) begin
case ({addr[1], addr[6], addr[2:5]}) //synopsys full_case parallel_case
0: dout = 7;
1: dout = 13;
2: dout = 14;
3: dout = 3;
4: dout = 0;
5: dout = 6;
6: dout = 9;
7: dout = 10;
8: dout = 1;
9: dout = 2;
10: dout = 8;
11: dout = 5;
12: dout = 11;
13: dout = 12;
14: dout = 4;
15: dout = 15;
16: dout = 13;
17: dout = 8;
18: dout = 11;
19: dout = 5;
20: dout = 6;
21: dout = 15;
22: dout = 0;
23: dout = 3;
24: dout = 4;
25: dout = 7;
26: dout = 2;
27: dout = 12;
28: dout = 1;
29: dout = 10;
30: dout = 14;
31: dout = 9;
32: dout = 10;
33: dout = 6;
34: dout = 9;
35: dout = 0;
36: dout = 12;
37: dout = 11;
38: dout = 7;
39: dout = 13;
40: dout = 15;
41: dout = 1;
42: dout = 3;
43: dout = 14;
44: dout = 5;
45: dout = 2;
46: dout = 8;
47: dout = 4;
48: dout = 3;
49: dout = 15;
50: dout = 0;
51: dout = 6;
52: dout = 10;
53: dout = 1;
54: dout = 13;
55: dout = 8;
56: dout = 9;
57: dout = 4;
58: dout = 5;
59: dout = 11;
60: dout = 12;
61: dout = 7;
62: dout = 2;
63: dout = 14;
endcase
end
endmodule |
module des(desOut, desIn, key, decrypt, roundSel, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key;
input decrypt;
input [3:0] roundSel;
input clk;
wire [1:48] K_sub;
wire [1:64] IP, FP;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout, Rout;
wire [1:32] out;
assign Lout = (roundSel == 0) ? IP[33:64] : R;
assign Xin = (roundSel == 0) ? IP[01:32] : L;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
crp u0( .P(out), .R(Lout), .K_sub(K_sub) );
always @(posedge clk)
L <= #1 Lout;
always @(posedge clk)
R <= #1 Rout;
// Select a subkey from key.
key_sel u1(
.K_sub( K_sub ),
.K( key ),
.roundSel( roundSel ),
.decrypt( decrypt )
);
// Perform initial permutation
assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule |
module key_sel(K_sub, K, roundSel, decrypt);
output [1:48] K_sub;
input [55:0] K;
input [3:0] roundSel;
input decrypt;
reg [1:48] K_sub;
wire [1:48] K1, K2, K3, K4, K5, K6, K7, K8;
//// Modified: for about Half slices decreased
wire [2:0] roundSelH; // ADD Sakamoto
wire decryptH; // ADD Sakamoto
assign roundSelH[2:0] = roundSel[3] ? (~roundSel[2:0]) : roundSel[2:0];
assign decryptH = decrypt ^ roundSel[3];
always @(K1 or K2 or K3 or K4 or K5 or K6 or K7 or K8 or roundSelH)
case (roundSelH) // synopsys full_case parallel_case
0: K_sub = K1;
1: K_sub = K2;
2: K_sub = K3;
3: K_sub = K4;
4: K_sub = K5;
5: K_sub = K6;
6: K_sub = K7;
7: K_sub = K8;
endcase
assign K8[1] = decryptH ? K[6] : K[24];
assign K8[2] = decryptH ? K[27] : K[20];
assign K8[3] = decryptH ? K[10] : K[3] ;
assign K8[4] = decryptH ? K[19] : K[12];
assign K8[5] = decryptH ? K[54] : K[47];
assign K8[6] = decryptH ? K[25] : K[18];
assign K8[7] = decryptH ? K[11] : K[4] ;
assign K8[8] = decryptH ? K[47] : K[40];
assign K8[9] = decryptH ? K[13] : K[6] ;
assign K8[10] = decryptH ? K[32] : K[25];
assign K8[11] = decryptH ? K[55] : K[48];
assign K8[12] = decryptH ? K[3] : K[53];
assign K8[13] = decryptH ? K[12] : K[5] ;
assign K8[14] = decryptH ? K[41] : K[34];
assign K8[15] = decryptH ? K[17] : K[10];
assign K8[16] = decryptH ? K[18] : K[11];
assign K8[17] = decryptH ? K[33] : K[26];
assign K8[18] = decryptH ? K[46] : K[39];
assign K8[19] = decryptH ? K[20] : K[13];
assign K8[20] = decryptH ? K[39] : K[32];
assign K8[21] = decryptH ? K[40] : K[33];
assign K8[22] = decryptH ? K[48] : K[41];
assign K8[23] = decryptH ? K[24] : K[17];
assign K8[24] = decryptH ? K[4] : K[54];
assign K8[25] = decryptH ? K[52] : K[45];
assign K8[26] = decryptH ? K[15] : K[8] ;
assign K8[27] = decryptH ? K[9] : K[2] ;
assign K8[28] = decryptH ? K[51] : K[44];
assign K8[29] = decryptH ? K[35] : K[28];
assign K8[30] = decryptH ? K[36] : K[29];
assign K8[31] = decryptH ? K[2] : K[50];
assign K8[32] = decryptH ? K[45] : K[38];
assign K8[33] = decryptH ? K[8] : K[1] ;
assign K8[34] = decryptH ? K[21] : K[14];
assign K8[35] = decryptH ? K[23] : K[16];
assign K8[36] = decryptH ? K[42] : K[35];
assign K8[37] = decryptH ? K[14] : K[7] ;
assign K8[38] = decryptH ? K[49] : K[42];
assign K8[39] = decryptH ? K[38] : K[31];
assign K8[40] = decryptH ? K[43] : K[36];
assign K8[41] = decryptH ? K[30] : K[23];
assign K8[42] = decryptH ? K[22] : K[15];
assign K8[43] = decryptH ? K[28] : K[21];
assign K8[44] = decryptH ? K[0] : K[52];
assign K8[45] = decryptH ? K[1] : K[49];
assign K8[46] = decryptH ? K[44] : K[37];
assign K8[47] = decryptH ? K[50] : K[43];
assign K8[48] = decryptH ? K[16] : K[9] ;
assign K7[1] = decryptH ? K[20] : K[10];
assign K7[2] = decryptH ? K[41] : K[6] ;
assign K7[3] = decryptH ? K[24] : K[46];
assign K7[4] = decryptH ? K[33] : K[55];
assign K7[5] = decryptH ? K[11] : K[33];
assign K7[6] = decryptH ? K[39] : K[4] ;
assign K7[7] = decryptH ? K[25] : K[47];
assign K7[8] = decryptH ? K[4] : K[26];
assign K7[9] = decryptH ? K[27] : K[17];
assign K7[10] = decryptH ? K[46] : K[11];
assign K7[11] = decryptH ? K[12] : K[34];
assign K7[12] = decryptH ? K[17] : K[39];
assign K7[13] = decryptH ? K[26] : K[48];
assign K7[14] = decryptH ? K[55] : K[20];
assign K7[15] = decryptH ? K[6] : K[53];
assign K7[16] = decryptH ? K[32] : K[54];
assign K7[17] = decryptH ? K[47] : K[12];
assign K7[18] = decryptH ? K[3] : K[25];
assign K7[19] = decryptH ? K[34] : K[24];
assign K7[20] = decryptH ? K[53] : K[18];
assign K7[21] = decryptH ? K[54] : K[19];
assign K7[22] = decryptH ? K[5] : K[27];
assign K7[23] = decryptH ? K[13] : K[3] ;
assign K7[24] = decryptH ? K[18] : K[40];
assign K7[25] = decryptH ? K[7] : K[31];
assign K7[26] = decryptH ? K[29] : K[49];
assign K7[27] = decryptH ? K[23] : K[43];
assign K7[28] = decryptH ? K[38] : K[30];
assign K7[29] = decryptH ? K[49] : K[14];
assign K7[30] = decryptH ? K[50] : K[15];
assign K7[31] = decryptH ? K[16] : K[36];
assign K7[32] = decryptH ? K[0] : K[51];
assign K7[33] = decryptH ? K[22] : K[42];
assign K7[34] = decryptH ? K[35] : K[0] ;
assign K7[35] = decryptH ? K[37] : K[2] ;
assign K7[36] = decryptH ? K[1] : K[21];
assign K7[37] = decryptH ? K[28] : K[52];
assign K7[38] = decryptH ? K[8] : K[28];
assign K7[39] = decryptH ? K[52] : K[44];
assign K7[40] = decryptH ? K[2] : K[22];
assign K7[41] = decryptH ? K[44] : K[9] ;
assign K7[42] = decryptH ? K[36] : K[1] ;
assign K7[43] = decryptH ? K[42] : K[7] ;
assign K7[44] = decryptH ? K[14] : K[38];
assign K7[45] = decryptH ? K[15] : K[35];
assign K7[46] = decryptH ? K[31] : K[23];
assign K7[47] = decryptH ? K[9] : K[29];
assign K7[48] = decryptH ? K[30] : K[50];
assign K6[1] = decryptH ? K[34] : K[53];
assign K6[2] = decryptH ? K[55] : K[17];
assign K6[3] = decryptH ? K[13] : K[32];
assign K6[4] = decryptH ? K[47] : K[41];
assign K6[5] = decryptH ? K[25] : K[19];
assign K6[6] = decryptH ? K[53] : K[47];
assign K6[7] = decryptH ? K[39] : K[33];
assign K6[8] = decryptH ? K[18] : K[12];
assign K6[9] = decryptH ? K[41] : K[3] ;
assign K6[10] = decryptH ? K[3] : K[54];
assign K6[11] = decryptH ? K[26] : K[20];
assign K6[12] = decryptH ? K[6] : K[25];
assign K6[13] = decryptH ? K[40] : K[34];
assign K6[14] = decryptH ? K[12] : K[6] ;
assign K6[15] = decryptH ? K[20] : K[39];
assign K6[16] = decryptH ? K[46] : K[40];
assign K6[17] = decryptH ? K[4] : K[55];
assign K6[18] = decryptH ? K[17] : K[11];
assign K6[19] = decryptH ? K[48] : K[10];
assign K6[20] = decryptH ? K[10] : K[4] ;
assign K6[21] = decryptH ? K[11] : K[5] ;
assign K6[22] = decryptH ? K[19] : K[13];
assign K6[23] = decryptH ? K[27] : K[46];
assign K6[24] = decryptH ? K[32] : K[26];
assign K6[25] = decryptH ? K[21] : K[44];
assign K6[26] = decryptH ? K[43] : K[35];
assign K6[27] = decryptH ? K[37] : K[29];
assign K6[28] = decryptH ? K[52] : K[16];
assign K6[29] = decryptH ? K[8] : K[0] ;
assign K6[30] = decryptH ? K[9] : K[1] ;
assign K6[31] = decryptH ? K[30] : K[22];
assign K6[32] = decryptH ? K[14] : K[37];
assign K6[33] = decryptH ? K[36] : K[28];
assign K6[34] = decryptH ? K[49] : K[45];
assign K6[35] = decryptH ? K[51] : K[43];
assign K6[36] = decryptH ? K[15] : K[7] ;
assign K6[37] = decryptH ? K[42] : K[38];
assign K6[38] = decryptH ? K[22] : K[14];
assign K6[39] = decryptH ? K[7] : K[30];
assign K6[40] = decryptH ? K[16] : K[8] ;
assign K6[41] = decryptH ? K[31] : K[50];
assign K6[42] = decryptH ? K[50] : K[42];
assign K6[43] = decryptH ? K[1] : K[52];
assign K6[44] = decryptH ? K[28] : K[51];
assign K6[45] = decryptH ? K[29] : K[21];
assign K6[46] = decryptH ? K[45] : K[9] ;
assign K6[47] = decryptH ? K[23] : K[15];
assign K6[48] = decryptH ? K[44] : K[36];
assign K5[1] = decryptH ? K[48] : K[39];
assign K5[2] = decryptH ? K[12] : K[3] ;
assign K5[3] = decryptH ? K[27] : K[18];
assign K5[4] = decryptH ? K[4] : K[27];
assign K5[5] = decryptH ? K[39] : K[5] ;
assign K5[6] = decryptH ? K[10] : K[33];
assign K5[7] = decryptH ? K[53] : K[19];
assign K5[8] = decryptH ? K[32] : K[55];
assign K5[9] = decryptH ? K[55] : K[46];
assign K5[10] = decryptH ? K[17] : K[40];
assign K5[11] = decryptH ? K[40] : K[6] ;
assign K5[12] = decryptH ? K[20] : K[11];
assign K5[13] = decryptH ? K[54] : K[20];
assign K5[14] = decryptH ? K[26] : K[17];
assign K5[15] = decryptH ? K[34] : K[25];
assign K5[16] = decryptH ? K[3] : K[26];
assign K5[17] = decryptH ? K[18] : K[41];
assign K5[18] = decryptH ? K[6] : K[54];
assign K5[19] = decryptH ? K[5] : K[53];
assign K5[20] = decryptH ? K[24] : K[47];
assign K5[21] = decryptH ? K[25] : K[48];
assign K5[22] = decryptH ? K[33] : K[24];
assign K5[23] = decryptH ? K[41] : K[32];
assign K5[24] = decryptH ? K[46] : K[12];
assign K5[25] = decryptH ? K[35] : K[30];
assign K5[26] = decryptH ? K[2] : K[21];
assign K5[27] = decryptH ? K[51] : K[15];
assign K5[28] = decryptH ? K[7] : K[2] ;
assign K5[29] = decryptH ? K[22] : K[45];
assign K5[30] = decryptH ? K[23] : K[42];
assign K5[31] = decryptH ? K[44] : K[8] ;
assign K5[32] = decryptH ? K[28] : K[23];
assign K5[33] = decryptH ? K[50] : K[14];
assign K5[34] = decryptH ? K[8] : K[31];
assign K5[35] = decryptH ? K[38] : K[29];
assign K5[36] = decryptH ? K[29] : K[52];
assign K5[37] = decryptH ? K[1] : K[51];
assign K5[38] = decryptH ? K[36] : K[0] ;
assign K5[39] = decryptH ? K[21] : K[16];
assign K5[40] = decryptH ? K[30] : K[49];
assign K5[41] = decryptH ? K[45] : K[36];
assign K5[42] = decryptH ? K[9] : K[28];
assign K5[43] = decryptH ? K[15] : K[38];
assign K5[44] = decryptH ? K[42] : K[37];
assign K5[45] = decryptH ? K[43] : K[7] ;
assign K5[46] = decryptH ? K[0] : K[50];
assign K5[47] = decryptH ? K[37] : K[1] ;
assign K5[48] = decryptH ? K[31] : K[22];
assign K4[1] = decryptH ? K[5] : K[25];
assign K4[2] = decryptH ? K[26] : K[46];
assign K4[3] = decryptH ? K[41] : K[4] ;
assign K4[4] = decryptH ? K[18] : K[13];
assign K4[5] = decryptH ? K[53] : K[48];
assign K4[6] = decryptH ? K[24] : K[19];
assign K4[7] = decryptH ? K[10] : K[5] ;
assign K4[8] = decryptH ? K[46] : K[41];
assign K4[9] = decryptH ? K[12] : K[32];
assign K4[10] = decryptH ? K[6] : K[26];
assign K4[11] = decryptH ? K[54] : K[17];
assign K4[12] = decryptH ? K[34] : K[54];
assign K4[13] = decryptH ? K[11] : K[6] ;
assign K4[14] = decryptH ? K[40] : K[3] ;
assign K4[15] = decryptH ? K[48] : K[11];
assign K4[16] = decryptH ? K[17] : K[12];
assign K4[17] = decryptH ? K[32] : K[27];
assign K4[18] = decryptH ? K[20] : K[40];
assign K4[19] = decryptH ? K[19] : K[39];
assign K4[20] = decryptH ? K[13] : K[33];
assign K4[21] = decryptH ? K[39] : K[34];
assign K4[22] = decryptH ? K[47] : K[10];
assign K4[23] = decryptH ? K[55] : K[18];
assign K4[24] = decryptH ? K[3] : K[55];
assign K4[25] = decryptH ? K[49] : K[16];
assign K4[26] = decryptH ? K[16] : K[7] ;
assign K4[27] = decryptH ? K[38] : K[1] ;
assign K4[28] = decryptH ? K[21] : K[43];
assign K4[29] = decryptH ? K[36] : K[31];
assign K4[30] = decryptH ? K[37] : K[28];
assign K4[31] = decryptH ? K[31] : K[49];
assign K4[32] = decryptH ? K[42] : K[9] ;
assign K4[33] = decryptH ? K[9] : K[0] ;
assign K4[34] = decryptH ? K[22] : K[44];
assign K4[35] = decryptH ? K[52] : K[15];
assign K4[36] = decryptH ? K[43] : K[38];
assign K4[37] = decryptH ? K[15] : K[37];
assign K4[38] = decryptH ? K[50] : K[45];
assign K4[39] = decryptH ? K[35] : K[2] ;
assign K4[40] = decryptH ? K[44] : K[35];
assign K4[41] = decryptH ? K[0] : K[22];
assign K4[42] = decryptH ? K[23] : K[14];
assign K4[43] = decryptH ? K[29] : K[51];
assign K4[44] = decryptH ? K[1] : K[23];
assign K4[45] = decryptH ? K[2] : K[52];
assign K4[46] = decryptH ? K[14] : K[36];
assign K4[47] = decryptH ? K[51] : K[42];
assign K4[48] = decryptH ? K[45] : K[8] ;
assign K3[1] = decryptH ? K[19] : K[11];
assign K3[2] = decryptH ? K[40] : K[32];
assign K3[3] = decryptH ? K[55] : K[47];
assign K3[4] = decryptH ? K[32] : K[24];
assign K3[5] = decryptH ? K[10] : K[34];
assign K3[6] = decryptH ? K[13] : K[5] ;
assign K3[7] = decryptH ? K[24] : K[48];
assign K3[8] = decryptH ? K[3] : K[27];
assign K3[9] = decryptH ? K[26] : K[18];
assign K3[10] = decryptH ? K[20] : K[12];
assign K3[11] = decryptH ? K[11] : K[3] ;
assign K3[12] = decryptH ? K[48] : K[40];
assign K3[13] = decryptH ? K[25] : K[17];
assign K3[14] = decryptH ? K[54] : K[46];
assign K3[15] = decryptH ? K[5] : K[54];
assign K3[16] = decryptH ? K[6] : K[55];
assign K3[17] = decryptH ? K[46] : K[13];
assign K3[18] = decryptH ? K[34] : K[26];
assign K3[19] = decryptH ? K[33] : K[25];
assign K3[20] = decryptH ? K[27] : K[19];
assign K3[21] = decryptH ? K[53] : K[20];
assign K3[22] = decryptH ? K[4] : K[53];
assign K3[23] = decryptH ? K[12] : K[4] ;
assign K3[24] = decryptH ? K[17] : K[41];
assign K3[25] = decryptH ? K[8] : K[2] ;
assign K3[26] = decryptH ? K[30] : K[52];
assign K3[27] = decryptH ? K[52] : K[42];
assign K3[28] = decryptH ? K[35] : K[29];
assign K3[29] = decryptH ? K[50] : K[44];
assign K3[30] = decryptH ? K[51] : K[14];
assign K3[31] = decryptH ? K[45] : K[35];
assign K3[32] = decryptH ? K[1] : K[50];
assign K3[33] = decryptH ? K[23] : K[45];
assign K3[34] = decryptH ? K[36] : K[30];
assign K3[35] = decryptH ? K[7] : K[1] ;
assign K3[36] = decryptH ? K[2] : K[51];
assign K3[37] = decryptH ? K[29] : K[23];
assign K3[38] = decryptH ? K[9] : K[31];
assign K3[39] = decryptH ? K[49] : K[43];
assign K3[40] = decryptH ? K[31] : K[21];
assign K3[41] = decryptH ? K[14] : K[8] ;
assign K3[42] = decryptH ? K[37] : K[0] ;
assign K3[43] = decryptH ? K[43] : K[37];
assign K3[44] = decryptH ? K[15] : K[9] ;
assign K3[45] = decryptH ? K[16] : K[38];
assign K3[46] = decryptH ? K[28] : K[22];
assign K3[47] = decryptH ? K[38] : K[28];
assign K3[48] = decryptH ? K[0] : K[49];
assign K2[1] = decryptH ? K[33] : K[54];
assign K2[2] = decryptH ? K[54] : K[18];
assign K2[3] = decryptH ? K[12] : K[33];
assign K2[4] = decryptH ? K[46] : K[10];
assign K2[5] = decryptH ? K[24] : K[20];
assign K2[6] = decryptH ? K[27] : K[48];
assign K2[7] = decryptH ? K[13] : K[34];
assign K2[8] = decryptH ? K[17] : K[13];
assign K2[9] = decryptH ? K[40] : K[4] ;
assign K2[10] = decryptH ? K[34] : K[55];
assign K2[11] = decryptH ? K[25] : K[46];
assign K2[12] = decryptH ? K[5] : K[26];
assign K2[13] = decryptH ? K[39] : K[3] ;
assign K2[14] = decryptH ? K[11] : K[32];
assign K2[15] = decryptH ? K[19] : K[40];
assign K2[16] = decryptH ? K[20] : K[41];
assign K2[17] = decryptH ? K[3] : K[24];
assign K2[18] = decryptH ? K[48] : K[12];
assign K2[19] = decryptH ? K[47] : K[11];
assign K2[20] = decryptH ? K[41] : K[5] ;
assign K2[21] = decryptH ? K[10] : K[6] ;
assign K2[22] = decryptH ? K[18] : K[39];
assign K2[23] = decryptH ? K[26] : K[47];
assign K2[24] = decryptH ? K[6] : K[27];
assign K2[25] = decryptH ? K[22] : K[43];
assign K2[26] = decryptH ? K[44] : K[38];
assign K2[27] = decryptH ? K[7] : K[28];
assign K2[28] = decryptH ? K[49] : K[15];
assign K2[29] = decryptH ? K[9] : K[30];
assign K2[30] = decryptH ? K[38] : K[0] ;
assign K2[31] = decryptH ? K[0] : K[21];
assign K2[32] = decryptH ? K[15] : K[36];
assign K2[33] = decryptH ? K[37] : K[31];
assign K2[34] = decryptH ? K[50] : K[16];
assign K2[35] = decryptH ? K[21] : K[42];
assign K2[36] = decryptH ? K[16] : K[37];
assign K2[37] = decryptH ? K[43] : K[9] ;
assign K2[38] = decryptH ? K[23] : K[44];
assign K2[39] = decryptH ? K[8] : K[29];
assign K2[40] = decryptH ? K[45] : K[7] ;
assign K2[41] = decryptH ? K[28] : K[49];
assign K2[42] = decryptH ? K[51] : K[45];
assign K2[43] = decryptH ? K[2] : K[23];
assign K2[44] = decryptH ? K[29] : K[50];
assign K2[45] = decryptH ? K[30] : K[51];
assign K2[46] = decryptH ? K[42] : K[8] ;
assign K2[47] = decryptH ? K[52] : K[14];
assign K2[48] = decryptH ? K[14] : K[35];
assign K1[1] = decryptH ? K[40] : K[47];
assign K1[2] = decryptH ? K[4] : K[11];
assign K1[3] = decryptH ? K[19] : K[26];
assign K1[4] = decryptH ? K[53] : K[3] ;
assign K1[5] = decryptH ? K[6] : K[13];
assign K1[6] = decryptH ? K[34] : K[41];
assign K1[7] = decryptH ? K[20] : K[27];
assign K1[8] = decryptH ? K[24] : K[6] ;
assign K1[9] = decryptH ? K[47] : K[54];
assign K1[10] = decryptH ? K[41] : K[48];
assign K1[11] = decryptH ? K[32] : K[39];
assign K1[12] = decryptH ? K[12] : K[19];
assign K1[13] = decryptH ? K[46] : K[53];
assign K1[14] = decryptH ? K[18] : K[25];
assign K1[15] = decryptH ? K[26] : K[33];
assign K1[16] = decryptH ? K[27] : K[34];
assign K1[17] = decryptH ? K[10] : K[17];
assign K1[18] = decryptH ? K[55] : K[5] ;
assign K1[19] = decryptH ? K[54] : K[4] ;
assign K1[20] = decryptH ? K[48] : K[55];
assign K1[21] = decryptH ? K[17] : K[24];
assign K1[22] = decryptH ? K[25] : K[32];
assign K1[23] = decryptH ? K[33] : K[40];
assign K1[24] = decryptH ? K[13] : K[20];
assign K1[25] = decryptH ? K[29] : K[36];
assign K1[26] = decryptH ? K[51] : K[31];
assign K1[27] = decryptH ? K[14] : K[21];
assign K1[28] = decryptH ? K[1] : K[8] ;
assign K1[29] = decryptH ? K[16] : K[23];
assign K1[30] = decryptH ? K[45] : K[52];
assign K1[31] = decryptH ? K[7] : K[14];
assign K1[32] = decryptH ? K[22] : K[29];
assign K1[33] = decryptH ? K[44] : K[51];
assign K1[34] = decryptH ? K[2] : K[9] ;
assign K1[35] = decryptH ? K[28] : K[35];
assign K1[36] = decryptH ? K[23] : K[30];
assign K1[37] = decryptH ? K[50] : K[2] ;
assign K1[38] = decryptH ? K[30] : K[37];
assign K1[39] = decryptH ? K[15] : K[22];
assign K1[40] = decryptH ? K[52] : K[0] ;
assign K1[41] = decryptH ? K[35] : K[42];
assign K1[42] = decryptH ? K[31] : K[38];
assign K1[43] = decryptH ? K[9] : K[16];
assign K1[44] = decryptH ? K[36] : K[43];
assign K1[45] = decryptH ? K[37] : K[44];
assign K1[46] = decryptH ? K[49] : K[1] ;
assign K1[47] = decryptH ? K[0] : K[7] ;
assign K1[48] = decryptH ? K[21] : K[28];
endmodule |
module des3(desOut, desIn, key1, key2, key3, decrypt, roundSel, clk);
output [63:0] desOut;
input [63:0] desIn;
input [55:0] key1;
input [55:0] key2;
input [55:0] key3;
input decrypt;
input [5:0] roundSel;
input clk;
wire [1:48] K_sub;
wire [1:64] IP, FP, tmp;
reg [1:64] FP_R;
reg [1:32] L, R;
wire [1:32] Xin;
wire [1:32] Lout;
wire [1:32] Rout;
wire [1:32] out;
//assign Lout = (roundSel == 0) ? IP[33:64] : R;
//assign Xin = (roundSel == 0) ? IP[01:32] : L;
assign Lout = (roundSel == 0) ? IP[33:64] :
( (roundSel == 16) ? FP_R[33:64] :
( (roundSel == 32) ? FP_R[33:64] :
R ));
assign Xin = (roundSel == 0) ? IP[01:32] :
( (roundSel == 16) ? FP_R[01:32] :
( (roundSel == 32) ? FP_R[01:32] :
L ));
/*
always @(roundSel or IP or tmp or R or FP)
case(roundSel)
6'h0: Lout = IP[33:64];
6'h10: Lout = FP[33:64];
6'h20: Lout = FP[33:64];
default: Lout = R;
endcase
always @(roundSel or IP or tmp or L or FP)
case(roundSel)
6'h0: Xin = IP[01:32];
6'h10: Xin = FP[01:32];
6'h20: Xin = FP[01:32];
default: Xin = L;
endcase
*/
always @(posedge clk)
FP_R <= #1 FP;
assign Rout = Xin ^ out;
assign FP = { Rout, Lout};
crp u0( .P(out), .R(Lout), .K_sub(K_sub) );
always @(posedge clk)
L <= #1 Lout;
always @(posedge clk)
R <= #1 Rout;
// Select a subkey from key.
key_sel3 u1(
.K_sub( K_sub ),
.key1( key1 ),
.key2( key2 ),
.key3( key3 ),
.roundSel( roundSel ),
.decrypt( decrypt )
);
assign tmp[1:64] = { desOut[06], desOut[14], desOut[22], desOut[30], desOut[38], desOut[46],
desOut[54], desOut[62], desOut[04], desOut[12], desOut[20], desOut[28],
desOut[36], desOut[44], desOut[52], desOut[60], desOut[02], desOut[10],
desOut[18], desOut[26], desOut[34], desOut[42], desOut[50], desOut[58],
desOut[00], desOut[08], desOut[16], desOut[24], desOut[32], desOut[40],
desOut[48], desOut[56], desOut[07], desOut[15], desOut[23], desOut[31],
desOut[39], desOut[47], desOut[55], desOut[63], desOut[05], desOut[13],
desOut[21], desOut[29], desOut[37], desOut[45], desOut[53], desOut[61],
desOut[03], desOut[11], desOut[19], desOut[27], desOut[35], desOut[43],
desOut[51], desOut[59], desOut[01], desOut[09], desOut[17], desOut[25],
desOut[33], desOut[41], desOut[49], desOut[57] };
// Perform initial permutation
assign IP[1:64] = { desIn[06], desIn[14], desIn[22], desIn[30], desIn[38], desIn[46],
desIn[54], desIn[62], desIn[04], desIn[12], desIn[20], desIn[28],
desIn[36], desIn[44], desIn[52], desIn[60], desIn[02], desIn[10],
desIn[18], desIn[26], desIn[34], desIn[42], desIn[50], desIn[58],
desIn[00], desIn[08], desIn[16], desIn[24], desIn[32], desIn[40],
desIn[48], desIn[56], desIn[07], desIn[15], desIn[23], desIn[31],
desIn[39], desIn[47], desIn[55], desIn[63], desIn[05], desIn[13],
desIn[21], desIn[29], desIn[37], desIn[45], desIn[53], desIn[61],
desIn[03], desIn[11], desIn[19], desIn[27], desIn[35], desIn[43],
desIn[51], desIn[59], desIn[01], desIn[09], desIn[17], desIn[25],
desIn[33], desIn[41], desIn[49], desIn[57] };
// Perform final permutation
assign desOut = { FP[40], FP[08], FP[48], FP[16], FP[56], FP[24], FP[64], FP[32],
FP[39], FP[07], FP[47], FP[15], FP[55], FP[23], FP[63], FP[31],
FP[38], FP[06], FP[46], FP[14], FP[54], FP[22], FP[62], FP[30],
FP[37], FP[05], FP[45], FP[13], FP[53], FP[21], FP[61], FP[29],
FP[36], FP[04], FP[44], FP[12], FP[52], FP[20], FP[60], FP[28],
FP[35], FP[03], FP[43], FP[11], FP[51], FP[19], FP[59], FP[27],
FP[34], FP[02], FP[42], FP[10], FP[50], FP[18], FP[58], FP[26],
FP[33], FP[01], FP[41], FP[09], FP[49], FP[17], FP[57], FP[25] };
endmodule |
module pcm_slv_top( clk, rst,
ssel,
// PCM
pcm_clk_i, pcm_sync_i, pcm_din_i, pcm_dout_o,
// Internal Interface
din_i, dout_o, re_i, we_i);
input clk, rst;
input [2:0] ssel; // Number of bits to delay (0-7)
input pcm_clk_i, pcm_sync_i, pcm_din_i;
output pcm_dout_o;
input [7:0] din_i;
output [7:0] dout_o;
input re_i;
input [1:0] we_i;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
reg pclk_t, pclk_s, pclk_r;
wire pclk_ris, pclk_fal;
reg psync;
reg pcm_sync_r1, pcm_sync_r2, pcm_sync_r3;
reg tx_go;
wire tx_data_le;
reg [15:0] tx_hold_reg;
reg [7:0] tx_hold_byte_h, tx_hold_byte_l;
reg [3:0] tx_cnt;
wire tx_done;
reg [15:0] rx_hold_reg, rx_reg;
wire rx_data_le;
reg rxd_t, rxd;
reg tx_go_r1, tx_go_r2;
reg [7:0] psa;
///////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk)
pclk_t <= #1 pcm_clk_i;
always @(posedge clk)
pclk_s <= #1 pclk_t;
always @(posedge clk)
pclk_r <= #1 pclk_s;
assign pclk_ris = !pclk_r & pclk_s;
assign pclk_fal = pclk_r & !pclk_s;
///////////////////////////////////////////////////////////////////
//
// Retrieve Sync Signal
//
always @(posedge clk) // Latch it at falling edge
if(pclk_fal) pcm_sync_r1 <= #1 pcm_sync_i;
always @(posedge clk) // resync to rising edge
if(pclk_ris) psa <= #1 {psa[6:0], pcm_sync_r1};
always @(posedge clk) //delay bit N
pcm_sync_r2 <= #1 psa[ssel];
always @(posedge clk) // edge detector
pcm_sync_r3 <= #1 pcm_sync_r2;
always @(posedge clk)
psync <= #1 !pcm_sync_r3 & pcm_sync_r2;
///////////////////////////////////////////////////////////////////
//
// Transmit Logic
//
assign tx_data_le = tx_go & pclk_ris;
always @(posedge clk)
if(we_i[1]) tx_hold_byte_h <= #1 din_i;
always @(posedge clk)
if(we_i[0]) tx_hold_byte_l <= #1 din_i;
always @(posedge clk)
if(!rst) tx_go <= #1 1'b0;
else
if(psync) tx_go <= #1 1'b1;
else
if(tx_done) tx_go <= #1 1'b0;
always @(posedge clk)
if(!rst) tx_hold_reg <= #1 16'h0;
else
if(psync) tx_hold_reg <= #1 {tx_hold_byte_h, tx_hold_byte_l};
else
if(tx_data_le) tx_hold_reg <= #1 {tx_hold_reg[14:0],1'b0};
assign pcm_dout_o = tx_hold_reg[15];
always @(posedge clk)
if(!rst) tx_cnt <= #1 4'h0;
else
if(tx_data_le) tx_cnt <= tx_cnt + 4'h1;
assign tx_done = (tx_cnt == 4'hf) & tx_data_le;
///////////////////////////////////////////////////////////////////
//
// Recieve Logic
//
always @(posedge clk)
if(pclk_ris) tx_go_r1 <= #1 tx_go;
always @(posedge clk)
if(pclk_ris) tx_go_r2 <= #1 tx_go_r1;
// Receive is in sync with transmit ...
always @(posedge clk)
if(pclk_fal) rxd_t <= #1 pcm_din_i;
always @(posedge clk)
rxd <= #1 rxd_t;
assign rx_data_le = (tx_go_r1 | tx_go) & pclk_fal;
always @(posedge clk)
if(!rst) rx_hold_reg <= #1 16'h0;
else
if(rx_data_le) rx_hold_reg <= #1 {rx_hold_reg[14:0], rxd};
always @(posedge clk)
if(!rst) rx_reg <= #1 16'h0;
else
if(tx_go_r1 & !tx_go & pclk_ris) rx_reg <= #1 rx_hold_reg;
assign dout_o = re_i ? rx_reg[15:8] : rx_reg[7:0];
endmodule |
module pci_pci_decoder (hit, addr_out,
addr_in, bc_in,
base_addr, mask_addr, tran_addr, at_en,
mem_io_space, mem_en, io_en) ;
// Decoding address size parameter - for FPGAs 1MegByte is recommended
// MAXIMUM is 20 (4KBytes), length 12 is 1 MByte !!!
parameter decode_len = 12 ;
//###########################################################################################################
// ALL COMMENTS are written as there were decode_len 20. This number and 12 (32 - 20) are assigning the
// numbers of decoded and compared bits, etc.
//###########################################################################################################
/*-----------------------------------------------------------------------------------------------------------
DECODER interface decodes input address (ADDR_IN); what means that it validates (HIT), if input address
falls within the defined image space boundaries. Image space boundarie is defined with image base address
register (BASE_ADDR) and address mask register (MASK_ADDR).
Beside that, it also translates (maps) the input address to the output address (ADDR_OUT), regarding the
translation address register (TRAN_ADDR) and the address mask register.
-----------------------------------------------------------------------------------------------------------*/
// output control
output hit ;
// output address
output [31:0] addr_out ;
// input address and bus command
input [31:0] addr_in ;
input [3:0] bc_in ;
// input registers - 12 LSbits are not valid since the smallest possible size is 4KB !
input [31:(32-decode_len)] base_addr ;
input [31:(32-decode_len)] mask_addr ;
input [31:(32-decode_len)] tran_addr ;
// input bit[2] of the Image Control register used to enable the address translation !
input at_en ;
// memory or io space selection and its enable signals !
input mem_io_space ;
input mem_en ;
input io_en ;
/*-----------------------------------------------------------------------------------------------------------
Internal signals !
-----------------------------------------------------------------------------------------------------------*/
// bit[31] if address mask register is IMAGE ENABLE bit (img_en)
wire img_en ;
// addr_in_compare are masked input address bits that are compared with masked base_addr
wire [31:(32-decode_len)] addr_in_compare ;
// base_addr_compare are masked base address bits that are compared with masked addr_in
wire [31:(32-decode_len)] base_addr_compare ;
/*-----------------------------------------------------------------------------------------------------------
Decoding the input address!
This logic produces the loghest path in this module!
20 MSbits of input addres are as well as base address (20 bits) masked with corrected address mask. Only
masked bits of each vector are actually logically compared.
Bit[31] of address mask register is used to enable the image space !
Because of PCI bus specifications, there is also the comparison of memory/io selection (mem_io_space) and
its appropriate enable bit (mem_en / io_en).
-----------------------------------------------------------------------------------------------------------*/
assign addr_in_compare = (addr_in[31:(32-decode_len)] & mask_addr) ;
assign base_addr_compare = (base_addr & mask_addr) ;
assign img_en = mask_addr[31] ;
wire addr_hit = (addr_in_compare == base_addr_compare) ;
wire space_hit = (!mem_io_space && mem_en && img_en) || (mem_io_space && io_en && img_en) ;
reg bc_hit ;
always@(bc_in or mem_io_space)
begin // Allowed bus commands for accesses through IMAGEs to WB bus - BC_CONF_WRITE/READ are not used with address claim!!!
case ( {bc_in[3:1], mem_io_space} )
4'b001_1, // BC_IO_READ or BC_IO_WRITE and IO space
4'b011_0, // BC_MEM_READ or BC_MEM_WRITE and MEM space
4'b110_0, // BC_MEM_READ_MUL and MEM space - BC_DUAL_ADDR_CYC must NOT be allowed!
4'b111_0: // BC_MEM_READ_LN or BC_MEM_WRITE_INVAL and MEM space
bc_hit <= 1'b1 ;
default:
bc_hit <= 1'b0 ;
endcase
end
wire bc_forbid = bc_in[3] && bc_in[2] && !bc_in[1] && bc_in[0] ; // BC_DUAL_ADDR_CYC must NOT be allowed!
assign hit = (addr_hit && space_hit && bc_hit && !bc_forbid) ;
/*-----------------------------------------------------------------------------------------------------------
Translating the input address!
Translation of input address is not implemented if ADDR_TRAN_IMPL is not defined
20 MSbits of input address are masked with negated value of the corrected address mask in order to get
address bits of the input address which won't be replaced with translation address bits.
Translation address bits (20 bits) are masked with corrected address mask. Only masked bits of vector are
actually valid, all others are zero.
Boath vectors are bit-wise ORed in order to get the valid translation address with an offset of an input
address.
12 LSbits of an input address are assigned to 12 LSbits of an output addres.
-----------------------------------------------------------------------------------------------------------*/
`ifdef ADDR_TRAN_IMPL
// if Address Translation Enable bit is set, then translation address is used othervise input address is used!
// addr_in_combine input address bits are not replaced with translation address!
wire [31:(32-decode_len)] addr_in_combine ;
// tran_addr_combine are masked and combined with addr_in_combine!
reg [31:(32-decode_len)] tran_addr_combine ;
assign addr_in_combine = (addr_in[31:(32-decode_len)] & ~mask_addr) ;
always@(at_en or tran_addr or mask_addr or addr_in)
begin
if (at_en)
begin
tran_addr_combine <= (tran_addr & mask_addr) ;
end
else
begin
tran_addr_combine <= (addr_in[31:(32-decode_len)] & mask_addr) ;
end
end
assign addr_out[31:(32-decode_len)] = (addr_in_combine | tran_addr_combine) ;
assign addr_out[(31-decode_len):0] = addr_in [(31-decode_len):0] ;
`else
assign addr_out = addr_in ;
`endif
endmodule |
module pci_io_mux_ad_load_crit
(
load_in,
load_on_transfer_in,
pci_irdy_in,
pci_trdy_in,
load_out
);
input load_in,
load_on_transfer_in,
pci_irdy_in,
pci_trdy_in ;
output load_out ;
assign load_out = load_in || (load_on_transfer_in && ~pci_irdy_in && ~pci_trdy_in) ;
endmodule |
module pci_perr_en_crit
(
reset_in,
clk_in,
perr_en_out,
perr_en_reg_out,
non_critical_par_in,
pci_par_in,
perr_generate_in,
par_err_response_in
) ;
output perr_en_out,
perr_en_reg_out ;
input reset_in,
clk_in,
non_critical_par_in,
pci_par_in,
perr_generate_in,
par_err_response_in ;
wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^ pci_par_in ) ;
// PERR# is enabled for two clocks after parity error is detected - one cycle active, another inactive
reg perr_en_reg_out ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
perr_en_reg_out <= #1 1'b0 ;
else
perr_en_reg_out <= #1 perr ;
end
assign perr_en_out = perr || perr_en_reg_out ;
endmodule |
module pci_conf_cyc_addr_dec
(
ccyc_addr_in,
ccyc_addr_out
) ;
input [31:0] ccyc_addr_in ;
output [31:0] ccyc_addr_out ;
reg [31:11] ccyc_addr_31_11 ;
// lower 11 address lines are alweys going through unchanged
assign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ;
// configuration cycle type indicator
wire ccyc_type = ccyc_addr_in[0] ;
always@(ccyc_addr_in or ccyc_type)
begin
if (ccyc_type)
// type 1 cycle - address goes through unchanged
ccyc_addr_31_11 = ccyc_addr_in[31:11] ;
else
begin
// type 0 conf. cycle - decode device number field to appropriate value
case (ccyc_addr_in[15:11])
5'h00:ccyc_addr_31_11 = 21'h00_0001 ;
5'h01:ccyc_addr_31_11 = 21'h00_0002 ;
5'h02:ccyc_addr_31_11 = 21'h00_0004 ;
5'h03:ccyc_addr_31_11 = 21'h00_0008 ;
5'h04:ccyc_addr_31_11 = 21'h00_0010 ;
5'h05:ccyc_addr_31_11 = 21'h00_0020 ;
5'h06:ccyc_addr_31_11 = 21'h00_0040 ;
5'h07:ccyc_addr_31_11 = 21'h00_0080 ;
5'h08:ccyc_addr_31_11 = 21'h00_0100 ;
5'h09:ccyc_addr_31_11 = 21'h00_0200 ;
5'h0A:ccyc_addr_31_11 = 21'h00_0400 ;
5'h0B:ccyc_addr_31_11 = 21'h00_0800 ;
5'h0C:ccyc_addr_31_11 = 21'h00_1000 ;
5'h0D:ccyc_addr_31_11 = 21'h00_2000 ;
5'h0E:ccyc_addr_31_11 = 21'h00_4000 ;
5'h0F:ccyc_addr_31_11 = 21'h00_8000 ;
5'h10:ccyc_addr_31_11 = 21'h01_0000 ;
5'h11:ccyc_addr_31_11 = 21'h02_0000 ;
5'h12:ccyc_addr_31_11 = 21'h04_0000 ;
5'h13:ccyc_addr_31_11 = 21'h08_0000 ;
5'h14:ccyc_addr_31_11 = 21'h10_0000 ;
default: ccyc_addr_31_11 = 21'h00_0000 ;
endcase
end
end
endmodule |
module pci_frame_crit
(
pci_frame_out,
force_frame_in,
slow_frame_in,
pci_stop_in
) ;
output pci_frame_out ;
input force_frame_in,
slow_frame_in,
pci_stop_in ;
assign pci_frame_out = force_frame_in && (slow_frame_in || ~pci_stop_in) ;
endmodule |
module pci_mas_ad_load_crit
(
ad_load_out,
ad_load_in,
ad_load_on_grant_in,
pci_gnt_in
);
output ad_load_out ;
input ad_load_in,
ad_load_on_grant_in,
pci_gnt_in ;
assign ad_load_out = ad_load_in || ( ad_load_on_grant_in && !pci_gnt_in ) ;
endmodule |
module pci_pciw_pcir_fifos
(
wb_clock_in,
pci_clock_in,
reset_in,
pciw_wenable_in,
pciw_addr_data_in,
pciw_cbe_in,
pciw_control_in,
pciw_renable_in,
pciw_addr_data_out,
pciw_cbe_out,
pciw_control_out,
// pciw_flush_in, // not used
pciw_three_left_out,
pciw_two_left_out,
pciw_almost_full_out,
pciw_full_out,
pciw_almost_empty_out,
pciw_empty_out,
pciw_transaction_ready_out,
pcir_wenable_in,
pcir_data_in,
pcir_be_in,
pcir_control_in,
pcir_renable_in,
pcir_data_out,
pcir_be_out,
pcir_control_out,
pcir_flush_in,
pcir_full_out,
pcir_almost_empty_out,
pcir_empty_out,
pcir_transaction_ready_out
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
) ;
/*-----------------------------------------------------------------------------------------------------------
System inputs:
wb_clock_in - WISHBONE bus clock
pci_clock_in - PCI bus clock
reset_in - reset from control logic
-------------------------------------------------------------------------------------------------------------*/
input wb_clock_in, pci_clock_in, reset_in ;
/*-----------------------------------------------------------------------------------------------------------
PCI WRITE FIFO interface signals prefixed with pciw_ - FIFO is used for posted writes initiated by external
PCI master through PCI target interface, traveling through FIFO and are completed on WISHBONE by
WISHBONE master interface
write enable signal:
pciw_wenable_in = write enable input for PCIW_FIFO - driven by PCI TARGET interface
data input signals:
pciw_addr_data_in = data input - data from PCI bus - first entry of transaction is address others are data entries
pciw_cbe_in = bus command/byte enable(~#BE[3:0]) input - first entry of transaction is bus command, other are byte enables
pciw_control_in = control input - encoded control bus input
read enable signal:
pciw_renable_in = read enable input driven by WISHBONE master interface
data output signals:
pciw_addr_data_out = data output - data from PCI bus - first entry of transaction is address, others are data entries
pciw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
pciw_control_out = control input - encoded control bus input
status signals - monitored by various resources in the core
pciw_flush_in = flush signal input for PCIW_FIFO - when asserted, fifo is flushed(emptied)
pciw_almost_full_out = almost full output from PCIW_FIFO
pciw_full_out = full output from PCIW_FIFO
pciw_almost_empty_out = almost empty output from PCIW_FIFO
pciw_empty_out = empty output from PCIW_FIFO
pciw_transaction_ready_out = output indicating that one complete transaction is waiting in PCIW_FIFO
-----------------------------------------------------------------------------------------------------------*/
// input control and data
input pciw_wenable_in ;
input [31:0] pciw_addr_data_in ;
input [3:0] pciw_cbe_in ;
input [3:0] pciw_control_in ;
// output control and data
input pciw_renable_in ;
output [31:0] pciw_addr_data_out ;
output [3:0] pciw_cbe_out ;
output [3:0] pciw_control_out ;
// flush input
//input pciw_flush_in ; // not used
// status outputs
output pciw_three_left_out ;
output pciw_two_left_out ;
output pciw_almost_full_out ;
output pciw_full_out ;
output pciw_almost_empty_out ;
output pciw_empty_out ;
output pciw_transaction_ready_out ;
/*-----------------------------------------------------------------------------------------------------------
PCI READ FIFO interface signals prefixed with pcir_ - FIFO is used for holding delayed read completions
initiated by master on PCI bus and completed on WISHBONE bus,
write enable signal:
pcir_wenable_in = write enable input for PCIR_FIFO - driven by WISHBONE master interface
data input signals:
pcir_data_in = data input - data from WISHBONE bus - there is no address entry here, since address is stored in separate register
pcir_be_in = byte enable(~SEL[3:0]) input - byte enables - same through one transaction
pcir_control_in = control input - encoded control bus input
read enable signal:
pcir_renable_in = read enable input driven by PCI target interface
data output signals:
pcir_data_out = data output - data from WISHBONE bus
pcir_be_out = byte enable output(~SEL)
pcir_control_out = control output - encoded control bus output
status signals - monitored by various resources in the core
pcir_flush_in = flush signal input for PCIR_FIFO - when asserted, fifo is flushed(emptied)
pcir full_out = full output from PCIR_FIFO
pcir_almost_empty_out = almost empty output from PCIR_FIFO
pcir_empty_out = empty output from PCIR_FIFO
pcir_transaction_ready_out = output indicating that one complete transaction is waiting in PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
// input control and data
input pcir_wenable_in ;
input [31:0] pcir_data_in ;
input [3:0] pcir_be_in ;
input [3:0] pcir_control_in ;
// output control and data
input pcir_renable_in ;
output [31:0] pcir_data_out ;
output [3:0] pcir_be_out ;
output [3:0] pcir_control_out ;
// flush input
input pcir_flush_in ;
// status outputs
output pcir_full_out ;
output pcir_almost_empty_out ;
output pcir_empty_out ;
output pcir_transaction_ready_out ;
`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
/*-----------------------------------------------------------------------------------------------------------
Address length parameters:
PCIW_DEPTH = defines PCIW_FIFO depth
PCIR_DEPTH = defines PCIR_FIFO depth
PCIW_ADDR_LENGTH = defines PCIW_FIFO's location address length - log2(PCIW_DEPTH)
PCIR_ADDR_LENGTH = defines PCIR_FIFO's location address length - log2(PCIR_DEPTH)
-----------------------------------------------------------------------------------------------------------*/
parameter PCIW_DEPTH = `PCIW_DEPTH ;
parameter PCIW_ADDR_LENGTH = `PCIW_ADDR_LENGTH ;
parameter PCIR_DEPTH = `PCIR_DEPTH ;
parameter PCIR_ADDR_LENGTH = `PCIR_ADDR_LENGTH ;
/*-----------------------------------------------------------------------------------------------------------
pciw_wallow = PCIW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
pciw_rallow = PCIW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire pciw_wallow ;
wire pciw_rallow ;
/*-----------------------------------------------------------------------------------------------------------
pcir_wallow = PCIR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
pcir_rallow = PCIR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire pcir_wallow ;
wire pcir_rallow ;
/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from PCIW_FIFO control logic to RAM blocks used for PCIW_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_raddr ;
wire [(PCIW_ADDR_LENGTH - 1):0] pciw_waddr ;
/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from PCIR_FIFO control logic to RAM blocks used for PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_raddr ;
wire [(PCIR_ADDR_LENGTH - 1):0] pcir_waddr ;
/*-----------------------------------------------------------------------------------------------------------
PCIW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
currently present in the FIFO.
-----------------------------------------------------------------------------------------------------------*/
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_inTransactionCount ;
reg [(PCIW_ADDR_LENGTH - 1):0] pciw_outTransactionCount ;
/*-----------------------------------------------------------------------------------------------------------
FlipFlops for indicating if complete delayed read completion is present in the FIFO
-----------------------------------------------------------------------------------------------------------*/
/*reg pcir_inTransactionCount ;
reg pcir_outTransactionCount ;*/
/*-----------------------------------------------------------------------------------------------------------
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
wire pciw_last_in = pciw_control_in[`LAST_CTRL_BIT] ;
wire pciw_last_out = pciw_control_out[`LAST_CTRL_BIT] ;
/*wire pcir_last_in = pcir_wallow && (pcir_control_in == `LAST) ;
wire pcir_last_out = pcir_rallow && (pcir_control_out == `LAST) ;*/
wire pciw_empty ;
wire pcir_empty ;
assign pciw_empty_out = pciw_empty ;
assign pcir_empty_out = pcir_empty ;
// clear wires for clearing FFs and registers
wire pciw_clear = reset_in /*|| pciw_flush_in*/ ; // PCIW_FIFO's clear signal - flush not used
wire pcir_clear = reset_in /*|| pcir_flush_in*/ ; // PCIR_FIFO's clear signal - flush changed to synchronous op.
/*-----------------------------------------------------------------------------------------------------------
Definitions of wires for connecting RAM instances
-----------------------------------------------------------------------------------------------------------*/
wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;
wire [39:0] dpram_portA_input = {pciw_control_in, pciw_cbe_in, pciw_addr_data_in} ;
wire [39:0] dpram_portB_input = {pcir_control_in, pcir_be_in, pcir_data_in} ;
/*-----------------------------------------------------------------------------------------------------------
Fifo output assignments - each ram port provides data for different fifo
-----------------------------------------------------------------------------------------------------------*/
assign pciw_control_out = dpram_portB_output[39:36] ;
assign pcir_control_out = dpram_portA_output[39:36] ;
assign pciw_cbe_out = dpram_portB_output[35:32] ;
assign pcir_be_out = dpram_portA_output[35:32] ;
assign pciw_addr_data_out = dpram_portB_output[31:0] ;
assign pcir_data_out = dpram_portA_output[31:0] ;
`ifdef PCI_RAM_DONT_SHARE
/*-----------------------------------------------------------------------------------------------------------
Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
write port is always port a and read port is port b.
-----------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------
Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
-----------------------------------------------------------------------------------------------------------*/
/*
wire [(`PCIW_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH - 1):0] pciw_addr_prefix = {( `PCIW_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH){1'b0}} ;
wire [(`PCIR_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH - 1):0] pcir_addr_prefix = {( `PCIR_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH){1'b0}} ;
*/
// compose complete port addresses
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pciw_whole_waddr = pciw_waddr ;
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pciw_whole_raddr = pciw_raddr ;
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pcir_whole_waddr = pcir_waddr ;
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] pcir_whole_raddr = pcir_raddr ;
wire pciw_read_enable = 1'b1 ;
wire pcir_read_enable = 1'b1 ;
`ifdef PCI_BIST
wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
wire mbist_si_i_internal = mbist_so_o_internal ;
`endif
// instantiate and connect two generic rams - one for pci write fifo and one for pci read fifo
pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciw_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(pci_clock_in),
.rst_a(reset_in),
.ce_a(1'b1),
.we_a(pciw_wallow),
.oe_a(1'b1),
.addr_a(pciw_whole_waddr),
.di_a(dpram_portA_input),
.do_a(),
.clk_b(wb_clock_in),
.rst_b(reset_in),
.ce_b(pciw_read_enable),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(pciw_whole_raddr),
.di_b(40'h00_0000_0000),
.do_b(dpram_portB_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pcir_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(wb_clock_in),
.rst_a(reset_in),
.ce_a(1'b1),
.we_a(pcir_wallow),
.oe_a(1'b1),
.addr_a(pcir_whole_waddr),
.di_a(dpram_portB_input),
.do_a(),
.clk_b(pci_clock_in),
.rst_b(reset_in),
.ce_b(pcir_read_enable),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(pcir_whole_raddr),
.di_b(40'h00_0000_0000),
.do_b(dpram_portA_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // RAM blocks sharing between two fifos
/*-----------------------------------------------------------------------------------------------------------
Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
case one RAM instance is used for both - pci read and pci write fifo.
-----------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------
Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
addresses. pci write fifo addresses are padded with zeros on the MSB side ( at least one address line
must be used for this ), pci read fifo addresses are padded with ones on the right ( at least one ).
-----------------------------------------------------------------------------------------------------------*/
wire [(`PCI_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH - 1):0] pciw_addr_prefix = {( `PCI_FIFO_RAM_ADDR_LENGTH - PCIW_ADDR_LENGTH){1'b0}} ;
wire [(`PCI_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH - 1):0] pcir_addr_prefix = {( `PCI_FIFO_RAM_ADDR_LENGTH - PCIR_ADDR_LENGTH){1'b1}} ;
/*-----------------------------------------------------------------------------------------------------------
Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
on both sides.
Port A is clocked by PCI clock, DIA is input for pciw_fifo, DOA is output for pcir_fifo.
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
-----------------------------------------------------------------------------------------------------------*/
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = pciw_wallow ? {pciw_addr_prefix, pciw_waddr} : {pcir_addr_prefix, pcir_raddr} ;
/*-----------------------------------------------------------------------------------------------------------
Port B is clocked by WISHBONE clock, DIB is input for pcir_fifo, DOB is output for pciw_fifo.
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
-----------------------------------------------------------------------------------------------------------*/
wire [(`PCI_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr = pcir_wallow ? {pcir_addr_prefix, pcir_waddr} : {pciw_addr_prefix, pciw_raddr} ;
wire portA_enable = 1'b1 ;
wire portB_enable = 1'b1 ;
// instantiate RAM for these two fifos
pci_pci_tpram #(`PCI_FIFO_RAM_ADDR_LENGTH, 40) pciu_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(pci_clock_in),
.rst_a(reset_in),
.ce_a(portA_enable),
.we_a(pciw_wallow),
.oe_a(1'b1),
.addr_a(portA_addr),
.di_a(dpram_portA_input),
.do_a(dpram_portA_output),
.clk_b(wb_clock_in),
.rst_b(reset_in),
.ce_b(portB_enable),
.we_b(pcir_wallow),
.oe_b(1'b1),
.addr_b(portB_addr),
.di_b(dpram_portB_input),
.do_b(dpram_portB_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`endif
/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for PCIW_FIFO and one for PCIR_FIFO
-----------------------------------------------------------------------------------------------------------*/
pci_pciw_fifo_control #(PCIW_ADDR_LENGTH) pciw_fifo_ctrl
(
.rclock_in(wb_clock_in),
.wclock_in(pci_clock_in),
.renable_in(pciw_renable_in),
.wenable_in(pciw_wenable_in),
.reset_in(reset_in),
// .flush_in(pciw_flush_in), // flush not used
.three_left_out(pciw_three_left_out),
.two_left_out(pciw_two_left_out),
.almost_full_out(pciw_almost_full_out),
.full_out(pciw_full_out),
.almost_empty_out(pciw_almost_empty_out),
.empty_out(pciw_empty),
.waddr_out(pciw_waddr),
.raddr_out(pciw_raddr),
.rallow_out(pciw_rallow),
.wallow_out(pciw_wallow)
);
pci_pcir_fifo_control #(PCIR_ADDR_LENGTH) pcir_fifo_ctrl
(
.rclock_in(pci_clock_in),
.wclock_in(wb_clock_in),
.renable_in(pcir_renable_in),
.wenable_in(pcir_wenable_in),
.reset_in(reset_in),
.flush_in(pcir_flush_in),
.full_out(pcir_full_out),
.almost_empty_out(pcir_almost_empty_out),
.empty_out(pcir_empty),
.waddr_out(pcir_waddr),
.raddr_out(pcir_raddr),
.rallow_out(pcir_rallow),
.wallow_out(pcir_wallow)
);
// in and out transaction counters and grey codes
reg [(PCIW_ADDR_LENGTH-2):0] inGreyCount ;
reg [(PCIW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(PCIW_ADDR_LENGTH-2):0] inNextGreyCount = {pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_inTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_inTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
wire [(PCIW_ADDR_LENGTH-2):0] outNextGreyCount = {pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2)], pciw_outTransactionCount[(PCIW_ADDR_LENGTH-2):1] ^ pciw_outTransactionCount[(PCIW_ADDR_LENGTH-3):0]} ;
// input transaction counter is incremented when whole transaction is written to fifo. This is indicated by last control bit written to last transaction location
wire in_count_en = pciw_wallow && pciw_last_in ;
// output transaction counter is incremented when whole transaction is pulled out of fifo. This is indicated when location with last control bit set is read
wire out_count_en = pciw_rallow && pciw_last_out ;
always@(posedge pci_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
begin
inGreyCount <= 0 ;
end
else
if (in_count_en)
inGreyCount <= #`FF_DELAY inNextGreyCount ;
end
wire [(PCIW_ADDR_LENGTH-2):0] wb_clk_sync_inGreyCount ;
reg [(PCIW_ADDR_LENGTH-2):0] wb_clk_inGreyCount ;
pci_synchronizer_flop #((PCIW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
.data_in (inGreyCount),
.clk_out (wb_clock_in),
.sync_data_out (wb_clk_sync_inGreyCount),
.async_reset (pciw_clear)
) ;
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
wb_clk_inGreyCount <= #`FF_DELAY 0 ;
else
wb_clk_inGreyCount <= # `FF_DELAY wb_clk_sync_inGreyCount ;
end
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
begin
outGreyCount <= #`FF_DELAY 0 ;
end
else
if (out_count_en)
outGreyCount <= #`FF_DELAY outNextGreyCount ;
end
always@(posedge pci_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
pciw_inTransactionCount <= #`FF_DELAY 1 ;
else
if (in_count_en)
pciw_inTransactionCount <= #`FF_DELAY pciw_inTransactionCount + 1'b1 ;
end
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
pciw_outTransactionCount <= #`FF_DELAY 1 ;
else
if (out_count_en)
pciw_outTransactionCount <= #`FF_DELAY pciw_outTransactionCount + 1'b1 ;
end
assign pciw_transaction_ready_out = wb_clk_inGreyCount != outGreyCount ;
assign pcir_transaction_ready_out = 1'b0 ;
endmodule |
module pci_cur_out_reg
(
reset_in,
clk_in,
frame_in,
frame_load_in,
irdy_in,
devsel_in,
trdy_in,
trdy_en_in,
stop_in,
ad_load_in,
cbe_in,
cbe_en_in,
mas_ad_in,
tar_ad_in,
frame_en_in,
irdy_en_in,
mas_ad_en_in,
tar_ad_en_in,
ad_en_unregistered_in,
par_in,
par_en_in,
perr_in,
perr_en_in,
serr_in,
serr_en_in,
frame_out,
irdy_out,
devsel_out,
trdy_out,
stop_out,
cbe_out,
cbe_en_out,
ad_out,
frame_en_out,
irdy_en_out,
ad_en_out,
mas_ad_en_out,
tar_ad_en_out,
trdy_en_out,
par_out,
par_en_out,
perr_out,
perr_en_out,
serr_out,
serr_en_out
) ;
input reset_in, clk_in ;
input frame_in ;
input frame_load_in ;
input irdy_in ;
input devsel_in ;
input trdy_in ;
input stop_in ;
input ad_load_in ;
input [3:0] cbe_in ;
input cbe_en_in ;
input [31:0] mas_ad_in ;
input [31:0] tar_ad_in ;
input mas_ad_en_in ;
input tar_ad_en_in ;
input ad_en_unregistered_in ;
input frame_en_in,
irdy_en_in ;
input trdy_en_in ;
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
output frame_out ;
reg frame_out ;
output irdy_out ;
reg irdy_out ;
output devsel_out ;
reg devsel_out ;
output trdy_out ;
reg trdy_out ;
output stop_out ;
reg stop_out ;
output [3:0] cbe_out ;
reg [3:0] cbe_out ;
output [31:0] ad_out ;
reg [31:0] ad_out ;
output frame_en_out,
irdy_en_out,
ad_en_out,
cbe_en_out,
mas_ad_en_out,
tar_ad_en_out,
trdy_en_out ;
reg frame_en_out,
irdy_en_out,
cbe_en_out,
mas_ad_en_out,
tar_ad_en_out,
trdy_en_out;
output par_out ;
output par_en_out ;
output perr_out ;
output perr_en_out ;
output serr_out ;
output serr_en_out ;
reg par_out ;
reg par_en_out ;
reg perr_out ;
reg perr_en_out ;
reg serr_out ;
reg serr_en_out ;
assign ad_en_out = mas_ad_en_out || tar_ad_en_out ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
begin
irdy_out <= #`FF_DELAY 1'b1 ;
devsel_out <= #`FF_DELAY 1'b1 ;
trdy_out <= #`FF_DELAY 1'b1 ;
stop_out <= #`FF_DELAY 1'b1 ;
frame_en_out <= #`FF_DELAY 1'b0 ;
irdy_en_out <= #`FF_DELAY 1'b0 ;
mas_ad_en_out<= #`FF_DELAY 1'b0 ;
tar_ad_en_out<= #`FF_DELAY 1'b0 ;
trdy_en_out <= #`FF_DELAY 1'b0 ;
par_out <= #`FF_DELAY 1'b0 ;
par_en_out <= #`FF_DELAY 1'b0 ;
perr_out <= #`FF_DELAY 1'b1 ;
perr_en_out <= #`FF_DELAY 1'b0 ;
serr_out <= #`FF_DELAY 1'b1 ;
serr_en_out <= #`FF_DELAY 1'b0 ;
cbe_en_out <= #`FF_DELAY 1'b0 ;
end
else
begin
irdy_out <= #`FF_DELAY irdy_in ;
devsel_out <= #`FF_DELAY devsel_in ;
trdy_out <= #`FF_DELAY trdy_in ;
stop_out <= #`FF_DELAY stop_in ;
frame_en_out <= #`FF_DELAY frame_en_in ;
irdy_en_out <= #`FF_DELAY irdy_en_in ;
mas_ad_en_out<= #`FF_DELAY mas_ad_en_in && ad_en_unregistered_in ;
tar_ad_en_out<= #`FF_DELAY tar_ad_en_in && ad_en_unregistered_in ;
trdy_en_out <= #`FF_DELAY trdy_en_in ;
par_out <= #`FF_DELAY par_in ;
par_en_out <= #`FF_DELAY par_en_in ;
perr_out <= #`FF_DELAY perr_in ;
perr_en_out <= #`FF_DELAY perr_en_in ;
serr_out <= #`FF_DELAY serr_in ;
serr_en_out <= #`FF_DELAY serr_en_in ;
cbe_en_out <= #`FF_DELAY cbe_en_in ;
end
end
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
cbe_out <= #`FF_DELAY 4'hF ;
else if ( ad_load_in )
cbe_out <= #`FF_DELAY cbe_in ;
end
wire [31:0] ad_source = tar_ad_en_out ? tar_ad_in : mas_ad_in ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
ad_out <= #`FF_DELAY 32'h0000_0000 ;
else if ( ad_load_in )
ad_out <= #`FF_DELAY ad_source ;
end
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
frame_out <= #`FF_DELAY 1'b1 ;
else if ( frame_load_in )
frame_out <= #`FF_DELAY frame_in ;
end
endmodule |
module pci_wbw_wbr_fifos
(
wb_clock_in,
pci_clock_in,
reset_in,
wbw_wenable_in,
wbw_addr_data_in,
wbw_cbe_in,
wbw_control_in,
wbw_renable_in,
wbw_addr_data_out,
wbw_cbe_out,
wbw_control_out,
// wbw_flush_in, write fifo flush not used
wbw_almost_full_out,
wbw_full_out,
wbw_empty_out,
wbw_transaction_ready_out,
wbr_wenable_in,
wbr_data_in,
wbr_be_in,
wbr_control_in,
wbr_renable_in,
wbr_data_out,
wbr_be_out,
wbr_control_out,
wbr_flush_in,
wbr_empty_out
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
) ;
/*-----------------------------------------------------------------------------------------------------------
System inputs:
wb_clock_in - WISHBONE bus clock
pci_clock_in - PCI bus clock
reset_in - reset from control logic
-------------------------------------------------------------------------------------------------------------*/
input wb_clock_in, pci_clock_in, reset_in ;
/*-----------------------------------------------------------------------------------------------------------
WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
write enable signal:
wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
data input signals:
wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
wbw_cbe_in = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
wbw_control_in = control input - encoded control bus input
read enable signal:
wbw_renable_in = read enable input driven by PCI master interface
data output signals:
wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
wbw_cbe_out = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
wbw_control_out = control input - encoded control bus input
status signals - monitored by various resources in the core
wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
wbw_almost_full_out = almost full output from WBW_FIFO
wbw_full_out = full output from WBW_FIFO
wbw_empty_out = empty output from WBW_FIFO
wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
-----------------------------------------------------------------------------------------------------------*/
// input control and data
input wbw_wenable_in ;
input [31:0] wbw_addr_data_in ;
input [3:0] wbw_cbe_in ;
input [3:0] wbw_control_in ;
// output control and data
input wbw_renable_in ;
output [31:0] wbw_addr_data_out ;
output [3:0] wbw_cbe_out ;
output [3:0] wbw_control_out ;
// flush input
// input wbw_flush_in ; // not used
// status outputs
output wbw_almost_full_out ;
output wbw_full_out ;
output wbw_empty_out ;
output wbw_transaction_ready_out ;
/*-----------------------------------------------------------------------------------------------------------
WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
initiated by master on WISHBONE bus and completed on PCI bus,
write enable signal:
wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
data input signals:
wbr_data_in = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
wbr_be_in = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
wbr_control_in = control input - encoded control bus input
read enable signal:
wbr_renable_in = read enable input driven by WISHBONE slave interface
data output signals:
wbr_data_out = data output - data from PCI bus
wbr_be_out = byte enable output(~#BE)
wbr_control_out = control output - encoded control bus output
status signals - monitored by various resources in the core
wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
wbr full_out = full output from WBR_FIFO
wbr_empty_out = empty output from WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
// input control and data
input wbr_wenable_in ;
input [31:0] wbr_data_in ;
input [3:0] wbr_be_in ;
input [3:0] wbr_control_in ;
// output control and data
input wbr_renable_in ;
output [31:0] wbr_data_out ;
output [3:0] wbr_be_out ;
output [3:0] wbr_control_out ;
// flush input
input wbr_flush_in ;
output wbr_empty_out ;
`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
/*-----------------------------------------------------------------------------------------------------------
FIFO depth parameters:
WBW_DEPTH = defines WBW_FIFO depth
WBR_DEPTH = defines WBR_FIFO depth
WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
-----------------------------------------------------------------------------------------------------------*/
parameter WBW_DEPTH = `WBW_DEPTH ;
parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
parameter WBR_DEPTH = `WBR_DEPTH ;
parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
/*-----------------------------------------------------------------------------------------------------------
wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire wbw_wallow ;
wire wbw_rallow ;
/*-----------------------------------------------------------------------------------------------------------
wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
-----------------------------------------------------------------------------------------------------------*/
wire wbr_wallow ;
wire wbr_rallow ;
/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
/*-----------------------------------------------------------------------------------------------------------
wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
/*-----------------------------------------------------------------------------------------------------------
WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
input transactions is equal to number of output transactions, it means that there isn't any complete transaction
currently present in the FIFO.
-----------------------------------------------------------------------------------------------------------*/
reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
/*-----------------------------------------------------------------------------------------------------------
wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
it means that there was one complete transaction taken out of FIFO.
-----------------------------------------------------------------------------------------------------------*/
wire wbw_last_in = wbw_control_in[`LAST_CTRL_BIT] ;
wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
wire wbw_empty ;
wire wbr_empty ;
assign wbw_empty_out = wbw_empty ;
assign wbr_empty_out = wbr_empty ;
// clear wires for fifos
wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
/*-----------------------------------------------------------------------------------------------------------
Definitions of wires for connecting RAM instances
-----------------------------------------------------------------------------------------------------------*/
wire [39:0] dpram_portA_output ;
wire [39:0] dpram_portB_output ;
wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
/*-----------------------------------------------------------------------------------------------------------
Fifo output assignments - each ram port provides data for different fifo
-----------------------------------------------------------------------------------------------------------*/
assign wbw_control_out = dpram_portB_output[39:36] ;
assign wbr_control_out = dpram_portA_output[39:36] ;
assign wbw_cbe_out = dpram_portB_output[35:32] ;
assign wbr_be_out = dpram_portA_output[35:32] ;
assign wbw_addr_data_out = dpram_portB_output[31:0] ;
assign wbr_data_out = dpram_portA_output[31:0] ;
`ifdef WB_RAM_DONT_SHARE
/*-----------------------------------------------------------------------------------------------------------
Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
write port is always port a and read port is port b.
-----------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------
Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
-----------------------------------------------------------------------------------------------------------*/
/*
wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
*/
// compose complete port addresses
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
wire wbw_read_enable = 1'b1 ;
wire wbr_read_enable = 1'b1 ;
`ifdef PCI_BIST
wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
wire mbist_si_i_internal = mbist_so_o_internal ;
`endif
// instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(wb_clock_in),
.rst_a(reset_in),
.ce_a(1'b1),
.we_a(wbw_wallow),
.oe_a(1'b1),
.addr_a(wbw_whole_waddr),
.di_a(dpram_portA_input),
.do_a(),
.clk_b(pci_clock_in),
.rst_b(reset_in),
.ce_b(wbw_read_enable),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(wbw_whole_raddr),
.di_b(40'h00_0000_0000),
.do_b(dpram_portB_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o_internal),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(pci_clock_in),
.rst_a(reset_in),
.ce_a(1'b1),
.we_a(wbr_wallow),
.oe_a(1'b1),
.addr_a(wbr_whole_waddr),
.di_a(dpram_portB_input),
.do_a(),
.clk_b(wb_clock_in),
.rst_b(reset_in),
.ce_b(wbr_read_enable),
.we_b(1'b0),
.oe_b(1'b1),
.addr_b(wbr_whole_raddr),
.di_b(40'h00_0000_0000),
.do_b(dpram_portA_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i_internal),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`else // RAM blocks sharing between two fifos
/*-----------------------------------------------------------------------------------------------------------
Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
-----------------------------------------------------------------------------------------------------------*/
/*-----------------------------------------------------------------------------------------------------------
Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
-----------------------------------------------------------------------------------------------------------*/
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
/*-----------------------------------------------------------------------------------------------------------
Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
on both sides.
Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
-----------------------------------------------------------------------------------------------------------*/
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
/*-----------------------------------------------------------------------------------------------------------
Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
Address is multiplexed so operation can be switched between fifos. Default is a read on port.
-----------------------------------------------------------------------------------------------------------*/
wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
wire portA_enable = 1'b1 ;
wire portB_enable = 1'b1 ;
// instantiate RAM for these two fifos
pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
(
// Generic synchronous two-port RAM interface
.clk_a(wb_clock_in),
.rst_a(reset_in),
.ce_a(portA_enable),
.we_a(wbw_wallow),
.oe_a(1'b1),
.addr_a(portA_addr),
.di_a(dpram_portA_input),
.do_a(dpram_portA_output),
.clk_b(pci_clock_in),
.rst_b(reset_in),
.ce_b(portB_enable),
.we_b(wbr_wallow),
.oe_b(1'b1),
.addr_b(portB_addr),
.di_b(dpram_portB_input),
.do_b(dpram_portB_output)
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
`endif
/*-----------------------------------------------------------------------------------------------------------
Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
-----------------------------------------------------------------------------------------------------------*/
pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
(
.rclock_in(pci_clock_in),
.wclock_in(wb_clock_in),
.renable_in(wbw_renable_in),
.wenable_in(wbw_wenable_in),
.reset_in(reset_in),
// .flush_in(wbw_flush_in),
.almost_full_out(wbw_almost_full_out),
.full_out(wbw_full_out),
.empty_out(wbw_empty),
.waddr_out(wbw_waddr),
.raddr_out(wbw_raddr),
.rallow_out(wbw_rallow),
.wallow_out(wbw_wallow)
);
pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
( .rclock_in(wb_clock_in),
.wclock_in(pci_clock_in),
.renable_in(wbr_renable_in),
.wenable_in(wbr_wenable_in),
.reset_in(reset_in),
.flush_in(wbr_flush_in),
.empty_out(wbr_empty),
.waddr_out(wbr_waddr),
.raddr_out(wbr_raddr),
.rallow_out(wbr_rallow),
.wallow_out(wbr_wallow)
);
// in and out transaction counters and grey codes
reg [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
reg [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
// input transaction counter increment - when last data of transaction is written to fifo
wire in_count_en = wbw_wallow && wbw_last_in ;
// output transaction counter increment - when last data is on top of fifo and read from it
wire out_count_en = wbw_renable_in && wbw_last_out ;
// register holding grey coded count of incoming transactions
always@(posedge wb_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
begin
inGreyCount <= #3 0 ;
end
else
if (in_count_en)
inGreyCount <= #3 inNextGreyCount ;
end
wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
reg [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
(
.data_in (inGreyCount),
.clk_out (pci_clock_in),
.sync_data_out (pci_clk_sync_inGreyCount),
.async_reset (wbw_clear)
) ;
always@(posedge pci_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
pci_clk_inGreyCount <= #`FF_DELAY 0 ;
else
pci_clk_inGreyCount <= # `FF_DELAY pci_clk_sync_inGreyCount ;
end
// register holding grey coded count of outgoing transactions
always@(posedge pci_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
begin
outGreyCount <= #`FF_DELAY 0 ;
end
else
if (out_count_en)
outGreyCount <= #`FF_DELAY outNextGreyCount ;
end
// incoming transactions counter
always@(posedge wb_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
wbw_inTransactionCount <= #`FF_DELAY 1 ;
else
if (in_count_en)
wbw_inTransactionCount <= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
end
// outgoing transactions counter
always@(posedge pci_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
wbw_outTransactionCount <= 1 ;
else
if (out_count_en)
wbw_outTransactionCount <= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
end
assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;
endmodule |
module pci_delayed_sync
(
reset_in,
req_clk_in,
comp_clk_in,
req_in,
comp_in,
done_in,
in_progress_in,
comp_req_pending_out,
req_req_pending_out,
req_comp_pending_out,
comp_comp_pending_out,
addr_in,
be_in,
addr_out,
be_out,
we_in,
we_out,
bc_in,
bc_out,
status_in,
status_out,
comp_flush_out,
burst_in,
burst_out,
retry_expired_in
);
// system inputs
input reset_in, // reset input
req_clk_in, // requesting clock input
comp_clk_in ; // completing clock input
// request, completion, done and in progress indication inputs
input req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs
comp_in, // completion qualifier - when 1, completing side indicates that request has completed
done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus
in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge
// pending indication outputs
output comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock
req_req_pending_out, // request pending output for requesting side
req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus
comp_comp_pending_out ; // completion pending output for completing side of the bridge
// additional signals and wires for clock domain passage of signals
reg comp_req_pending,
req_req_pending,
req_comp_pending,
req_comp_pending_sample,
comp_comp_pending,
req_done_reg,
comp_done_reg_main,
comp_done_reg_clr,
req_rty_exp_reg,
req_rty_exp_clr,
comp_rty_exp_reg,
comp_rty_exp_clr ;
wire sync_comp_req_pending,
sync_req_comp_pending,
sync_comp_done,
sync_req_rty_exp,
sync_comp_rty_exp_clr ;
// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides
// all signals that identify requests are stored in this module
input [31:0] addr_in ; // address bus input
input [3:0] be_in ; // byte enable input
input we_in ; // write enable input - read/write request indication 1 = write request / 0 = read request
input [3:0] bc_in ; // bus command input
input burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer
// common request outputs used both by completing and requesting sides
// this outputs are not resynchronized, since flags determine the request status
output [31:0] addr_out ;
output [3:0] be_out ;
output we_out ;
output [3:0] bc_out ;
output burst_out ;
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
input status_in ;
output status_out ;
// input signals that delayed transaction has been retried for max number of times
// on this signal request is ditched, otherwise it would cause a deadlock
// requestor can issue another request and procedure will be repeated
input retry_expired_in ;
// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion data
output comp_flush_out ;
// output registers for common signals
reg [31:0] addr_out ;
reg [3:0] be_out ;
reg we_out ;
reg [3:0] bc_out ;
reg burst_out ;
// delayed transaction information is stored only when request is issued and request nor completion are pending
wire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
if (reset_in)
begin
addr_out <= #`FF_DELAY 32'h0000_0000 ;
be_out <= #`FF_DELAY 4'h0 ;
we_out <= #`FF_DELAY 1'b0 ;
bc_out <= #`FF_DELAY `BC_RESERVED0 ;
burst_out <= #`FF_DELAY 1'b0 ;
end
else
if (new_request)
begin
addr_out <= #`FF_DELAY addr_in ;
be_out <= #`FF_DELAY be_in ;
we_out <= #`FF_DELAY we_in ;
bc_out <= #`FF_DELAY bc_in ;
burst_out <= #`FF_DELAY burst_in ;
end
end
// completion pending cycle counter
reg [16:0] comp_cycle_count ;
/*=================================================================================================================================
Passing of requests between clock domains:
request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain
=================================================================================================================================*/
// main request flip-flop triggered on requesting side's clock
// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge
wire req_req_clear = req_comp_pending || (req_rty_exp_reg && ~req_rty_exp_clr) ;
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_req_pending <= #`FF_DELAY 1'b0 ;
else
if ( req_req_clear )
req_req_pending <= #`FF_DELAY 1'b0 ;
else
if ( req_in )
req_req_pending <= #`FF_DELAY 1'b1 ;
end
// interemediate stage request synchronization flip - flop - this one is prone to metastability
// and should have setup and hold times disabled during simulation
pci_synchronizer_flop #(1, 0) req_sync
(
.data_in (req_req_pending),
.clk_out (comp_clk_in),
.sync_data_out (sync_comp_req_pending),
.async_reset (reset_in)
) ;
// wire for clearing completion side request flag - whenever completion or retry expired are signalled
wire comp_req_pending_clear = comp_req_pending && ( comp_in || retry_expired_in) ;
// wire for enabling request flip - flop - it is enabled when completion is not active and done is not active
wire comp_req_pending_ena = ~comp_comp_pending && ~comp_done_reg_main && ~comp_rty_exp_reg ;
// completion side request flip flop - gets a value from intermediate stage sync flip flop
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_req_pending <= #`FF_DELAY 1'b0 ;
else
if ( comp_req_pending_clear )
comp_req_pending <= #`FF_DELAY 1'b0 ;
else
if ( comp_req_pending_ena )
comp_req_pending <= #`FF_DELAY sync_comp_req_pending ;
end
// completion side request output assignment - when request ff is set and completion ff is not set
assign comp_req_pending_out = comp_req_pending ;
// requesting side request pending output
assign req_req_pending_out = req_req_pending ;
/*=================================================================================================================================
Passing of completions between clock domains:
completion originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main completion Flip - Flop - triggered by completing side's clock
// completion side completion pending flag is cleared when done flag propagates through clock domains
wire comp_comp_clear = comp_done_reg_main && ~comp_done_reg_clr ;
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_comp_pending <= #`FF_DELAY 1'b0 ;
else
if ( comp_comp_clear )
comp_comp_pending <= #`FF_DELAY 1'b0 ;
else
if ( comp_in && comp_req_pending )
comp_comp_pending <= #`FF_DELAY 1'b1 ;
end
assign comp_comp_pending_out = comp_comp_pending ;
// interemediate stage completion synchronization flip - flop - this one is prone to metastability
pci_synchronizer_flop #(1, 0) comp_sync
(
.data_in (comp_comp_pending),
.clk_out (req_clk_in),
.sync_data_out (sync_req_comp_pending),
.async_reset (reset_in)
) ;
// request side completion pending flip flop is cleared whenever done is signalled or completion counter expires - 2^^16 clock cycles
wire req_comp_pending_clear = done_in || comp_cycle_count[16];
// request side completion pending flip flop is disabled while done flag is set
wire req_comp_pending_ena = ~req_done_reg ;
// request side completion flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_comp_pending <= #`FF_DELAY 1'b0 ;
else
if ( req_comp_pending_clear )
req_comp_pending <= #`FF_DELAY 1'b0 ;
else
if ( req_comp_pending_ena )
req_comp_pending <= #`FF_DELAY sync_req_comp_pending ;
end
// sampling FF - used for sampling incoming completion flag from completing side
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_comp_pending_sample <= #`FF_DELAY 1'b0 ;
else
req_comp_pending_sample <= #`FF_DELAY sync_req_comp_pending ;
end
// requesting side completion pending output assignment
assign req_comp_pending_out = req_comp_pending && ~req_req_pending ;
/*==================================================================================================================================
Passing of delayed transaction done signal between clock domains.
Done is signalled by requesting side of the bridge and is passed to completing side of the bridge
==================================================================================================================================*/
// main done flip-flop triggered on requesting side's clock
// when completing side removes completion flag, done flag is also removed, so requests can proceede
wire req_done_clear = ~req_comp_pending_sample ;
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_done_reg <= #`FF_DELAY 1'b0 ;
else
if ( req_done_clear )
req_done_reg <= #`FF_DELAY 1'b0 ;
else
if ( done_in || comp_cycle_count[16] )
req_done_reg <= #`FF_DELAY 1'b1 ;
end
pci_synchronizer_flop #(1, 0) done_sync
(
.data_in (req_done_reg),
.clk_out (comp_clk_in),
.sync_data_out (sync_comp_done),
.async_reset (reset_in)
) ;
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_done_reg_main <= #`FF_DELAY 1'b0 ;
else
comp_done_reg_main <= #`FF_DELAY sync_comp_done ;
end
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_done_reg_clr <= #`FF_DELAY 1'b0 ;
else
comp_done_reg_clr <= #`FF_DELAY comp_done_reg_main ;
end
/*=================================================================================================================================
Passing of retry expired signal between clock domains
Retry expiration originates on completing side. It's then synchronized with two flip-flops to cross to requesting clock domain
=================================================================================================================================*/
// main retry expired Flip - Flop - triggered by completing side's clock
wire comp_rty_exp_clear = comp_rty_exp_clr && comp_rty_exp_reg ;
// retry expired is a special case of transaction removal - retry expired propagates from completing
// clock domain to requesting clock domain to remove all pending requests and than propagates back
// to completing side to qualify valid new requests
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
else
if ( comp_rty_exp_clear )
comp_rty_exp_reg <= #`FF_DELAY 1'b0 ;
else
if ( retry_expired_in && comp_req_pending)
comp_rty_exp_reg <= #`FF_DELAY 1'b1 ;
end
// interemediate stage retry expired synchronization flip - flop - this one is prone to metastability
pci_synchronizer_flop #(1, 0) rty_exp_sync
(
.data_in (comp_rty_exp_reg),
.clk_out (req_clk_in),
.sync_data_out (sync_req_rty_exp),
.async_reset (reset_in)
) ;
// request retry expired flip flop - gets a value from intermediate stage sync flip flop
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_rty_exp_reg <= #`FF_DELAY 1'b0 ;
else
req_rty_exp_reg <= #`FF_DELAY sync_req_rty_exp ;
end
always@(posedge req_clk_in or posedge reset_in)
begin
if ( reset_in )
req_rty_exp_clr <= #`FF_DELAY 1'b0 ;
else
req_rty_exp_clr <= #`FF_DELAY req_rty_exp_reg ;
end
pci_synchronizer_flop #(1, 0) rty_exp_back_prop_sync
(
.data_in (req_rty_exp_reg && req_rty_exp_clr),
.clk_out (comp_clk_in),
.sync_data_out (sync_comp_rty_exp_clr),
.async_reset (reset_in)
) ;
always@(posedge comp_clk_in or posedge reset_in)
begin
if ( reset_in )
comp_rty_exp_clr <= #`FF_DELAY 1'b0 ;
else
comp_rty_exp_clr <= #`FF_DELAY sync_comp_rty_exp_clr ;
end
// completion status flip flop - if 0 when completion is signalled it's finished OK otherwise it means error
reg status_out ;
always@(posedge comp_clk_in or posedge reset_in)
begin
if (reset_in)
status_out <= #`FF_DELAY 1'b0 ;
else
if (comp_in && comp_req_pending)
status_out <= #`FF_DELAY status_in ;
end
// clocks counter - it counts how many clock cycles completion is present without beeing repeated
// if it counts to 2^^16 cycles the completion must be ditched
// wire for clearing this counter
wire clear_count = in_progress_in || ~req_comp_pending_out || comp_cycle_count[16] ;
always@(posedge req_clk_in or posedge reset_in)
begin
if (reset_in)
comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
else
if (clear_count)
comp_cycle_count <= #`FF_DELAY 17'h0_0000 ;
else
comp_cycle_count <= #`FF_DELAY comp_cycle_count + 1'b1 ;
end
// completion flush output - used for flushing fifos when counter expires
// if counter doesn't expire, fifo flush is up to WISHBONE slave or PCI target state machines
reg comp_flush_out ;
always@(posedge req_clk_in or posedge reset_in)
begin
if (reset_in)
comp_flush_out <= #`FF_DELAY 1'b0 ;
else
comp_flush_out <= #`FF_DELAY comp_cycle_count[16] ;
end
endmodule //delayed_sync |
module pci_rst_int
(
clk_in,
// reset signals
rst_i,
pci_rstn_in,
conf_soft_res_in,
reset,
pci_rstn_out,
pci_rstn_en_out,
rst_o,
// interrupt signals
pci_intan_in,
conf_int_in,
int_i,
pci_intan_out,
pci_intan_en_out,
int_o,
conf_isr_int_prop_out,
init_complete_in
);
input clk_in;
// RESET inputs and outputs
input rst_i;
input pci_rstn_in;
input conf_soft_res_in;
output reset;
output pci_rstn_out;
output pci_rstn_en_out;
output rst_o;
// INTERRUPT inputs and outputs
input pci_intan_in;
input conf_int_in;
input int_i;
output pci_intan_out;
output pci_intan_en_out;
output int_o;
output conf_isr_int_prop_out;
input init_complete_in ;
/*--------------------------------------------------------------------------------------------------------
RESET logic
--------------------------------------------------------------------------------------------------------*/
assign pci_rstn_out = 1'b0 ;
// host implementation of the bridge gets its reset from WISHBONE bus - RST_I and propagates it to PCI bus
`ifdef HOST
assign reset = rst_i ;
`ifdef ACTIVE_LOW_OE
assign pci_rstn_en_out = ~(rst_i || conf_soft_res_in) ;
`else
assign pci_rstn_en_out = rst_i || conf_soft_res_in ;
`endif
assign rst_o = 1'b0 ;
`else
// guest implementation of the bridge gets its reset from PCI bus - RST# and propagates it to WISHBONE bus
`ifdef GUEST
assign reset = ~pci_rstn_in ;
assign rst_o = (~pci_rstn_in) || conf_soft_res_in ;
`ifdef ACTIVE_LOW_OE
assign pci_rstn_en_out = 1'b1 ; // disabled
`else
assign pci_rstn_en_out = 1'b0 ; // disabled
`endif
`endif
`endif
/*--------------------------------------------------------------------------------------------------------
INTERRUPT logic
--------------------------------------------------------------------------------------------------------*/
assign pci_intan_out = 1'b0 ;
// host implementation of the bridge gets its interrupt from PCI bus - INTA# and propagates it to WISHBONE bus
`ifdef HOST
assign conf_isr_int_prop_out = ~pci_intan_in ;
assign int_o = conf_int_in ;
`ifdef ACTIVE_LOW_OE
assign pci_intan_en_out = 1'b1 ; // disabled
`else
assign pci_intan_en_out = 1'b0 ; // disabled
`endif
`else
// guest implementation of the bridge gets its interrupt from WISHBONE bus - INT_I and propagates it to PCI bus
`ifdef GUEST
wire interrupt_a_en;
pci_out_reg inta
(
.reset_in ( reset ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( init_complete_in ),
.dat_in ( 1'b0 ) , // active low
.en_in ( conf_int_in ) ,
.en_out ( interrupt_a_en ),
.dat_out ( )
);
assign conf_isr_int_prop_out = int_i ;
assign int_o = 1'b0 ;
assign pci_intan_en_out = interrupt_a_en ;
`endif
`endif
endmodule |
module pci_io_mux_ad_en_crit
(
ad_en_in,
pci_frame_in,
pci_trdy_in,
pci_stop_in,
ad_en_out
);
input ad_en_in,
pci_frame_in,
pci_trdy_in,
pci_stop_in ;
output ad_en_out ;
assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ;
endmodule |
module pci_sync_module
(
set_clk_in,
delete_clk_in,
reset_in,
delete_set_out,
block_set_out,
delete_in
);
// system inputs from two clock domains
input set_clk_in;
input delete_clk_in;
input reset_in;
// control outputs
output delete_set_out;
output block_set_out;
// control input
input delete_in;
// internal signals
reg del_bit;
wire meta_del_bit;
reg sync_del_bit;
reg delayed_del_bit;
wire meta_bckp_bit;
reg sync_bckp_bit;
reg delayed_bckp_bit;
// DELETE_IN input FF - when set must be active, until it is sinchronously cleared
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
del_bit <= 1'b0;
else
begin
if (!delayed_bckp_bit && sync_bckp_bit)
del_bit <= 1'b0;
else if (delete_in)
del_bit <= 1'b1;
end
end
assign block_set_out = del_bit;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) delete_sync
(
.data_in (del_bit),
.clk_out (set_clk_in),
.sync_data_out (meta_del_bit),
.async_reset (reset_in)
) ;
// Final synchronization of del_bit signal to the set clock domain
always@(posedge set_clk_in or posedge reset_in)
begin
if (reset_in)
sync_del_bit <= 1'b0;
else
sync_del_bit <= meta_del_bit;
end
// Delayed sync_del_bit signal for one clock period pulse generation
always@(posedge set_clk_in or posedge reset_in)
begin
if (reset_in)
delayed_del_bit <= 1'b0;
else
delayed_del_bit <= sync_del_bit;
end
assign delete_set_out = !delayed_del_bit && sync_del_bit;
// interemediate stage to clk synchronization flip - flops - this ones are prone to metastability
pci_synchronizer_flop #(1, 0) clear_delete_sync
(
.data_in (sync_del_bit),
.clk_out (delete_clk_in),
.sync_data_out (meta_bckp_bit),
.async_reset (reset_in)
) ;
// Final synchronization of sync_del_bit signal to the delete clock domain
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
sync_bckp_bit <= 1'b0;
else
sync_bckp_bit <= meta_bckp_bit;
end
// Delayed sync_bckp_bit signal for one clock period pulse generation
always@(posedge delete_clk_in or posedge reset_in)
begin
if (reset_in)
delayed_bckp_bit <= 1'b0;
else
delayed_bckp_bit <= sync_bckp_bit;
end
endmodule |
module pci_io_mux
(
reset_in,
clk_in,
frame_in,
frame_en_in,
frame_load_in,
irdy_in,
irdy_en_in,
devsel_in,
devsel_en_in,
trdy_in,
trdy_en_in,
stop_in,
stop_en_in,
master_load_in,
master_load_on_transfer_in,
target_load_in,
target_load_on_transfer_in,
cbe_in,
cbe_en_in,
mas_ad_in,
tar_ad_in,
par_in,
par_en_in,
perr_in,
perr_en_in,
serr_in,
serr_en_in,
req_in,
mas_ad_en_in,
tar_ad_en_in,
tar_ad_en_reg_in,
ad_en_out,
frame_en_out,
irdy_en_out,
devsel_en_out,
trdy_en_out,
stop_en_out,
cbe_en_out,
frame_out,
irdy_out,
devsel_out,
trdy_out,
stop_out,
cbe_out,
ad_out,
ad_load_out,
ad_en_unregistered_out,
par_out,
par_en_out,
perr_out,
perr_en_out,
serr_out,
serr_en_out,
req_out,
req_en_out,
pci_trdy_in,
pci_irdy_in,
pci_frame_in,
pci_stop_in,
init_complete_in
);
input reset_in, clk_in ;
input frame_in ;
input frame_en_in ;
input frame_load_in ;
input irdy_in ;
input irdy_en_in ;
input devsel_in ;
input devsel_en_in ;
input trdy_in ;
input trdy_en_in ;
input stop_in ;
input stop_en_in ;
input master_load_in ;
input target_load_in ;
input [3:0] cbe_in ;
input cbe_en_in ;
input [31:0] mas_ad_in ;
input [31:0] tar_ad_in ;
input mas_ad_en_in ;
input tar_ad_en_in ;
input tar_ad_en_reg_in ;
input par_in ;
input par_en_in ;
input perr_in ;
input perr_en_in ;
input serr_in ;
input serr_en_in ;
output frame_en_out ;
output irdy_en_out ;
output devsel_en_out ;
output trdy_en_out ;
output stop_en_out ;
output [31:0] ad_en_out ;
output [3:0] cbe_en_out ;
output frame_out ;
output irdy_out ;
output devsel_out ;
output trdy_out ;
output stop_out ;
output [3:0] cbe_out ;
output [31:0] ad_out ;
output ad_load_out ;
output ad_en_unregistered_out ;
output par_out ;
output par_en_out ;
output perr_out ;
output perr_en_out ;
output serr_out ;
output serr_en_out ;
input req_in ;
output req_out ;
output req_en_out ;
input pci_trdy_in,
pci_irdy_in,
pci_frame_in,
pci_stop_in ;
input master_load_on_transfer_in ;
input target_load_on_transfer_in ;
input init_complete_in ;
wire [31:0] temp_ad = tar_ad_en_reg_in ? tar_ad_in : mas_ad_in ;
wire ad_en_ctrl_low ;
wire ad_en_ctrl_mlow ;
wire ad_en_ctrl_mhigh ;
wire ad_en_ctrl_high ;
wire ad_enable_internal = mas_ad_en_in || tar_ad_en_in ;
pci_io_mux_ad_en_crit ad_en_low_gen
(
.ad_en_in (ad_enable_internal),
.pci_frame_in (pci_frame_in),
.pci_trdy_in (pci_trdy_in),
.pci_stop_in (pci_stop_in),
.ad_en_out (ad_en_ctrl_low)
);
pci_io_mux_ad_en_crit ad_en_mlow_gen
(
.ad_en_in (ad_enable_internal),
.pci_frame_in (pci_frame_in),
.pci_trdy_in (pci_trdy_in),
.pci_stop_in (pci_stop_in),
.ad_en_out (ad_en_ctrl_mlow)
);
pci_io_mux_ad_en_crit ad_en_mhigh_gen
(
.ad_en_in (ad_enable_internal),
.pci_frame_in (pci_frame_in),
.pci_trdy_in (pci_trdy_in),
.pci_stop_in (pci_stop_in),
.ad_en_out (ad_en_ctrl_mhigh)
);
pci_io_mux_ad_en_crit ad_en_high_gen
(
.ad_en_in (ad_enable_internal),
.pci_frame_in (pci_frame_in),
.pci_trdy_in (pci_trdy_in),
.pci_stop_in (pci_stop_in),
.ad_en_out (ad_en_ctrl_high)
);
assign ad_en_unregistered_out = ad_en_ctrl_high ;
wire load = master_load_in || target_load_in ;
wire load_on_transfer = master_load_on_transfer_in || target_load_on_transfer_in ;
wire ad_load_ctrl_low ;
wire ad_load_ctrl_mlow ;
wire ad_load_ctrl_mhigh ;
wire ad_load_ctrl_high ;
assign ad_load_out = ad_load_ctrl_high ;
pci_io_mux_ad_load_crit ad_load_low_gen
(
.load_in(load),
.load_on_transfer_in(load_on_transfer),
.pci_irdy_in(pci_irdy_in),
.pci_trdy_in(pci_trdy_in),
.load_out(ad_load_ctrl_low)
);
pci_io_mux_ad_load_crit ad_load_mlow_gen
(
.load_in(load),
.load_on_transfer_in(load_on_transfer),
.pci_irdy_in(pci_irdy_in),
.pci_trdy_in(pci_trdy_in),
.load_out(ad_load_ctrl_mlow)
);
pci_io_mux_ad_load_crit ad_load_mhigh_gen
(
.load_in(load),
.load_on_transfer_in(load_on_transfer),
.pci_irdy_in(pci_irdy_in),
.pci_trdy_in(pci_trdy_in),
.load_out(ad_load_ctrl_mhigh)
);
pci_io_mux_ad_load_crit ad_load_high_gen
(
.load_in(load),
.load_on_transfer_in(load_on_transfer),
.pci_irdy_in(pci_irdy_in),
.pci_trdy_in(pci_trdy_in),
.load_out(ad_load_ctrl_high)
);
pci_out_reg ad_iob0
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[0] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[0] ),
.dat_out ( ad_out[0] )
);
pci_out_reg ad_iob1
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[1] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[1] ),
.dat_out ( ad_out[1] )
);
pci_out_reg ad_iob2
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[2] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[2] ),
.dat_out ( ad_out[2] )
);
pci_out_reg ad_iob3
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[3] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[3] ),
.dat_out ( ad_out[3] )
);
pci_out_reg ad_iob4
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[4] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[4] ),
.dat_out ( ad_out[4] )
);
pci_out_reg ad_iob5
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[5] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[5] ),
.dat_out ( ad_out[5] )
);
pci_out_reg ad_iob6
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[6] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[6] ),
.dat_out ( ad_out[6] )
);
pci_out_reg ad_iob7
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_low ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[7] ) ,
.en_in ( ad_en_ctrl_low ) ,
.en_out ( ad_en_out[7] ),
.dat_out ( ad_out[7] )
);
pci_out_reg ad_iob8
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[8] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[8] ),
.dat_out ( ad_out[8] )
);
pci_out_reg ad_iob9
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[9] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[9] ),
.dat_out ( ad_out[9] )
);
pci_out_reg ad_iob10
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[10] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[10] ),
.dat_out ( ad_out[10] )
);
pci_out_reg ad_iob11
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[11] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[11] ),
.dat_out ( ad_out[11] )
);
pci_out_reg ad_iob12
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[12] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[12] ),
.dat_out ( ad_out[12] )
);
pci_out_reg ad_iob13
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[13] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[13] ),
.dat_out ( ad_out[13] )
);
pci_out_reg ad_iob14
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[14] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[14] ),
.dat_out ( ad_out[14] )
);
pci_out_reg ad_iob15
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mlow ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[15] ) ,
.en_in ( ad_en_ctrl_mlow ) ,
.en_out ( ad_en_out[15] ),
.dat_out ( ad_out[15] )
);
pci_out_reg ad_iob16
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[16] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[16] ),
.dat_out ( ad_out[16] )
);
pci_out_reg ad_iob17
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[17] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[17] ),
.dat_out ( ad_out[17] )
);
pci_out_reg ad_iob18
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[18] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[18] ),
.dat_out ( ad_out[18] )
);
pci_out_reg ad_iob19
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[19] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[19] ),
.dat_out ( ad_out[19] )
);
pci_out_reg ad_iob20
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[20] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[20] ),
.dat_out ( ad_out[20] )
);
pci_out_reg ad_iob21
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[21] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[21] ),
.dat_out ( ad_out[21] )
);
pci_out_reg ad_iob22
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[22] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[22] ),
.dat_out ( ad_out[22] )
);
pci_out_reg ad_iob23
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_mhigh ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[23] ) ,
.en_in ( ad_en_ctrl_mhigh ) ,
.en_out ( ad_en_out[23] ),
.dat_out ( ad_out[23] )
);
pci_out_reg ad_iob24
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[24] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[24] ),
.dat_out ( ad_out[24] )
);
pci_out_reg ad_iob25
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[25] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[25] ),
.dat_out ( ad_out[25] )
);
pci_out_reg ad_iob26
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[26] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[26] ),
.dat_out ( ad_out[26] )
);
pci_out_reg ad_iob27
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[27] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[27] ),
.dat_out ( ad_out[27] )
);
pci_out_reg ad_iob28
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[28] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[28] ),
.dat_out ( ad_out[28] )
);
pci_out_reg ad_iob29
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[29] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[29] ),
.dat_out ( ad_out[29] )
);
pci_out_reg ad_iob30
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[30] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[30] ),
.dat_out ( ad_out[30] )
);
pci_out_reg ad_iob31
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( ad_load_ctrl_high ),
.en_en_in ( 1'b1 ),
.dat_in ( temp_ad[31] ) ,
.en_in ( ad_en_ctrl_high ) ,
.en_out ( ad_en_out[31] ),
.dat_out ( ad_out[31] )
);
wire [3:0] cbe_load_ctrl = {4{ master_load_in }} ;
wire [3:0] cbe_en_ctrl = {4{ cbe_en_in }} ;
pci_out_reg cbe_iob0
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( cbe_load_ctrl[0] ),
.en_en_in ( 1'b1 ),
.dat_in ( cbe_in[0] ) ,
.en_in ( cbe_en_ctrl[0] ) ,
.en_out ( cbe_en_out[0] ),
.dat_out ( cbe_out[0] )
);
pci_out_reg cbe_iob1
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( cbe_load_ctrl[1] ),
.en_en_in ( 1'b1 ),
.dat_in ( cbe_in[1] ) ,
.en_in ( cbe_en_ctrl[1] ) ,
.en_out ( cbe_en_out[1] ),
.dat_out ( cbe_out[1] )
);
pci_out_reg cbe_iob2
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( cbe_load_ctrl[2] ),
.en_en_in ( 1'b1 ),
.dat_in ( cbe_in[2] ) ,
.en_in ( cbe_en_ctrl[2] ) ,
.en_out ( cbe_en_out[2] ),
.dat_out ( cbe_out[2] )
);
pci_out_reg cbe_iob3
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( cbe_load_ctrl[3] ),
.en_en_in ( 1'b1 ),
.dat_in ( cbe_in[3] ) ,
.en_in ( cbe_en_ctrl[3] ) ,
.en_out ( cbe_en_out[3] ),
.dat_out ( cbe_out[3] )
);
pci_out_reg frame_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( frame_load_in ),
.en_en_in ( 1'b1 ),
.dat_in ( frame_in ) ,
.en_in ( frame_en_in ) ,
.en_out ( frame_en_out ),
.dat_out ( frame_out )
);
pci_out_reg irdy_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( irdy_in ) ,
.en_in ( irdy_en_in ) ,
.en_out ( irdy_en_out ),
.dat_out ( irdy_out )
);
pci_out_reg trdy_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( trdy_in ) ,
.en_in ( trdy_en_in ) ,
.en_out ( trdy_en_out ),
.dat_out ( trdy_out )
);
pci_out_reg stop_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( stop_in ) ,
.en_in ( stop_en_in ) ,
.en_out ( stop_en_out ),
.dat_out ( stop_out )
);
pci_out_reg devsel_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( devsel_in ) ,
.en_in ( devsel_en_in ) ,
.en_out ( devsel_en_out ),
.dat_out ( devsel_out )
);
pci_out_reg par_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( par_in ) ,
.en_in ( par_en_in ) ,
.en_out ( par_en_out ),
.dat_out ( par_out )
);
pci_out_reg perr_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( perr_in ) ,
.en_in ( perr_en_in ) ,
.en_out ( perr_en_out ),
.dat_out ( perr_out )
);
pci_out_reg serr_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( serr_in ) ,
.en_in ( serr_en_in ) ,
.en_out ( serr_en_out ),
.dat_out ( serr_out )
);
pci_out_reg req_iob
(
.reset_in ( reset_in ),
.clk_in ( clk_in) ,
.dat_en_in ( 1'b1 ),
.en_en_in ( 1'b1 ),
.dat_in ( req_in ) ,
.en_in ( init_complete_in ) ,
.en_out ( req_en_out ),
.dat_out ( req_out )
);
endmodule |
module pci_target32_devs_crit
(
devs_w,
devs_w_frm,
devs_w_frm_irdy,
pci_frame_in,
pci_irdy_in,
pci_devsel_out
);
input devs_w ; // devsel signal (composed without critical signals) that do not need critical inputs
input devs_w_frm ; // devsel signal (composed without critical signals) that needs AND with critical FRAME input
input devs_w_frm_irdy ; // devsel signal (composed without critical signals) that needs AND with critical FRAME and
// IRDY inputs
input pci_frame_in ; // critical constrained input signal
input pci_irdy_in ; // critical constrained input signal
output pci_devsel_out ; // PCI devsel output
// PCI devsel output with preserved hierarchy for minimum delay!
assign pci_devsel_out = ~(devs_w || (devs_w_frm && ~pci_frame_in) || (devs_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
endmodule |
module pci_target32_interface
(
// system inputs
clk_in,
reset_in,
// PCI Target side of INTERFACE
address_in,
addr_claim_out,
bc_in,
bc0_in,
data_in,
data_out,
be_in,
next_be_in,
req_in,
rdy_in,
addr_phase_in,
bckp_devsel_in,
bckp_trdy_in,
bckp_stop_in,
last_reg_in,
frame_reg_in,
fetch_pcir_fifo_in,
load_medium_reg_in,
sel_fifo_mreg_in,
sel_conf_fifo_in,
load_to_pciw_fifo_in,
load_to_conf_in,
same_read_out,
norm_access_to_config_out,
read_completed_out,
read_processing_out,
target_abort_out,
disconect_wo_data_out,
disconect_w_data_out,
pciw_fifo_full_out,
pcir_fifo_data_err_out,
wbw_fifo_empty_out,
wbu_del_read_comp_pending_out,
// Delayed synchronizacion module signals
req_out,
done_out,
in_progress_out,
req_req_pending_in,
req_comp_pending_in,
addr_out,
be_out,
we_out,
bc_out,
burst_ok_out,
strd_addr_in,
strd_bc_in,
status_in,
comp_flush_in,
// FIFO signals
pcir_fifo_renable_out,
pcir_fifo_data_in,
pcir_fifo_be_in,
pcir_fifo_control_in,
pcir_fifo_flush_out,
pcir_fifo_almost_empty_in,
pcir_fifo_empty_in,
pciw_fifo_wenable_out,
pciw_fifo_addr_data_out,
pciw_fifo_cbe_out,
pciw_fifo_control_out,
pciw_fifo_three_left_in,
pciw_fifo_two_left_in,
pciw_fifo_almost_full_in,
pciw_fifo_full_in,
wbw_fifo_empty_in,
wbu_del_read_comp_pending_in,
// Configuration space signals
conf_addr_out,
conf_data_out,
conf_data_in,
conf_be_out,
conf_we_out,
conf_re_out,
mem_enable_in,
io_enable_in,
mem_io_addr_space0_in,
mem_io_addr_space1_in,
mem_io_addr_space2_in,
mem_io_addr_space3_in,
mem_io_addr_space4_in,
mem_io_addr_space5_in,
pre_fetch_en0_in,
pre_fetch_en1_in,
pre_fetch_en2_in,
pre_fetch_en3_in,
pre_fetch_en4_in,
pre_fetch_en5_in,
pci_base_addr0_in,
pci_base_addr1_in,
pci_base_addr2_in,
pci_base_addr3_in,
pci_base_addr4_in,
pci_base_addr5_in,
pci_addr_mask0_in,
pci_addr_mask1_in,
pci_addr_mask2_in,
pci_addr_mask3_in,
pci_addr_mask4_in,
pci_addr_mask5_in,
pci_tran_addr0_in,
pci_tran_addr1_in,
pci_tran_addr2_in,
pci_tran_addr3_in,
pci_tran_addr4_in,
pci_tran_addr5_in,
addr_tran_en0_in,
addr_tran_en1_in,
addr_tran_en2_in,
addr_tran_en3_in,
addr_tran_en4_in,
addr_tran_en5_in
) ;
`ifdef HOST
`ifdef NO_CNF_IMAGE
parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
`else
parameter pci_ba0_width = 20 ;
`endif
`endif
`ifdef GUEST
parameter pci_ba0_width = 20 ;
`endif
parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
/*==================================================================================================================
System inputs.
==================================================================================================================*/
// PCI side clock and reset
input clk_in,
reset_in ;
/*==================================================================================================================
Side of the PCI Target state machine
==================================================================================================================*/
// Data, byte enables, bus commands and address ports
input [31:0] address_in ; // current request address input - registered
output addr_claim_out ; // current request address claim output
input [3:0] bc_in ; // current request bus command input - registered
input bc0_in ; // current cycle RW signal
output [31:0] data_out ; // for read operations - current dataphase data output
input [31:0] data_in ; // for write operations - current request data input - registered
input [3:0] be_in ; // current dataphase byte enable inputs - registered
input [3:0] next_be_in ; // next dataphase byte enable inputs - NOT registered
// Port connection control signals from PCI FSM
input req_in ; // Read is requested to WB master from PCI side
input rdy_in ; // DATA / ADDRESS selection from PCI side when read or write - registered
input addr_phase_in ; // Indicates address phase and also fast-back-to-back address phase - registered
input bckp_devsel_in ; // DEVSEL input (which is registered) equivalent
input bckp_trdy_in ; // TRDY input (which is registered) equivalent
input bckp_stop_in ; // STOP input (which is registered) equivalent
input last_reg_in ; // Indicates last data phase - registered
input frame_reg_in ; // FRAME input signal - registered
input fetch_pcir_fifo_in ;// Read enable for PCIR_FIFO when when read is finishen on WB side
input load_medium_reg_in ;// Load data from PCIR_FIFO to medium register (first data must be prepared on time)
input sel_fifo_mreg_in ; // Read data selection between PCIR_FIFO and medium register
input sel_conf_fifo_in ; // Read data selection between Configuration registers and "FIFO"
input load_to_pciw_fifo_in ;// Write enable to PCIW_FIFO
input load_to_conf_in ; // Write enable to Configuration space registers
/*==================================================================================================================
Status outputs to PCI side (FSM)
==================================================================================================================*/
output same_read_out ; // Indicates the same read request (important when read is finished on WB side)
output norm_access_to_config_out ; // Indicates the access to Configuration space with MEMORY commands
output read_completed_out ; // Indicates that read request is completed on WB side
output read_processing_out ; // Indicates that read request is processing on WB side
output target_abort_out ; // Indicates target abort termination
output disconect_wo_data_out ; // Indicates disconnect without data termination
output disconect_w_data_out ; // Indicates disconnect with data termination
output pciw_fifo_full_out ; // Indicates that write PCIW_FIFO is full
output pcir_fifo_data_err_out ; // Indicates data error on current data read from PCIR_FIFO
output wbw_fifo_empty_out ; // Indicates that WB SLAVE has no data to be written to PCI bus
output wbu_del_read_comp_pending_out ; // Indicates that WB Unit has a delayed read poending!
/*==================================================================================================================
Read request interface through Delayed sinchronization module to WB Master
==================================================================================================================*/
// request, completion, done and progress indicator outputs for delayed_sync module where they are synchronized
output req_out, // request qualifier - when 1 it indicates that valid data is provided on outputs
done_out, // done output - when 1 indicates that PCI Target has completed a cycle on its bus
in_progress_out ; // out progress indicator - indicates that current completion is in progress on
// PCI Target side
// pending indication inputs - PCI Target side must know about requests and completions
input req_req_pending_in ; // request pending input for PCI Target side
input req_comp_pending_in ; // completion pending input for PCI Target side - it indicates when completion
// is ready for completing on PCI Target bus
// various data outputs - PCI Target sets address, bus command, byte enables, write enable and burst
output [31:0] addr_out ; // address bus output
output [3:0] be_out ; // byte enable output
output we_out ; // write enable output - read/write request indication 1 = write request / 0 = read request
output [3:0] bc_out ; // bus command output
output burst_ok_out ; // pre-fetch enable & burst read - qualifies pre-fetch for access to current image space
// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completion
input [31:0] strd_addr_in ; // Stored requested read access address
input [3:0] strd_bc_in ; // Stored requested read access bus command
input status_in ; // Error status reported - NOT USED because FIFO control bits determin data error status
input comp_flush_in ; // If completition counter (2^16 clk periods) has expired, PCIR_FIFO must flush data
/*==================================================================================================================
PCIR_PCIW_FIFO signals from pci side
==================================================================================================================*/
// PCIR_FIFO control signals used for fetching data from PCIR_FIFO
output pcir_fifo_renable_out ; // read enable output to PCIR_FIFO
input [31:0] pcir_fifo_data_in ; // data input from PCIR_FIFO
input [3:0] pcir_fifo_be_in ; // byte enable input from PCIR_FIFO
input [3:0] pcir_fifo_control_in ; // control signals input from PCIR_FIFO
output pcir_fifo_flush_out ; // flush PCIR_FIFO
input pcir_fifo_almost_empty_in ; // almost empty indicator from PCIR_FIFO
input pcir_fifo_empty_in ; // empty indicator
// PCIW_FIFO control signals used for sinking data into PCIW_FIFO and status monitoring
output pciw_fifo_wenable_out ; // write enable output to PCIW_FIFO
wire pciw_fifo_wenable ; // not registered we
output [31:0] pciw_fifo_addr_data_out ; // address / data output signals to PCIW_FIFO
output [3:0] pciw_fifo_cbe_out ; // command / byte enable signals to PCIW_FIFO
output [3:0] pciw_fifo_control_out ; // control signals to PCIW_FIFO
input pciw_fifo_three_left_in ; // three data spaces left in PCIW_FIFO
input pciw_fifo_two_left_in ; // two data spaces left in PCIW_FIFO
input pciw_fifo_almost_full_in ; // almost full indicator from PCIW_FIFO
input pciw_fifo_full_in ; // full indicator from PCIW_FIFO
// WBW_FIFO empy control signal used when delayed read is complete in PCIR_FIFO
input wbw_fifo_empty_in ; // empty indicator from WBW_FIFO
input wbu_del_read_comp_pending_in ; // delayed read pending indicator from WB Unit
/*==================================================================================================================
Configuration space signals - from and to registers
==================================================================================================================*/
// BUS for reading and writing to configuration space registers
output [11:0] conf_addr_out ; // address to configuration space when there is access to it
output [31:0] conf_data_out ; // data to configuration space - for writing to registers
input [31:0] conf_data_in ; // data from configuration space - for reading from registers
output [3:0] conf_be_out ; // byte enables used for correct writing to configuration space
output conf_we_out ; // write enable control signal - 1 for writing / 0 for nothing
output conf_re_out ; // read enable control signal - 1 for reading / 0 for nothing
// Inputs for image control registers
input mem_enable_in ; // allowed access to memory mapped image
input io_enable_in ; // allowed access to io mapped image
// Inputs needed for determining if image is assigned to memory or io space with pre-fetch and address translation
input mem_io_addr_space0_in ; // bit-0 in pci_base_addr0 register
input mem_io_addr_space1_in ; // bit-0 in pci_base_addr1 register
input mem_io_addr_space2_in ; // bit-0 in pci_base_addr2 register
input mem_io_addr_space3_in ; // bit-0 in pci_base_addr3 register
input mem_io_addr_space4_in ; // bit-0 in pci_base_addr4 register
input mem_io_addr_space5_in ; // bit-0 in pci_base_addr5 register
input pre_fetch_en0_in ; // bit-1 in pci_image_ctr0 register
input pre_fetch_en1_in ; // bit-1 in pci_image_ctr1 register
input pre_fetch_en2_in ; // bit-1 in pci_image_ctr2 register
input pre_fetch_en3_in ; // bit-1 in pci_image_ctr3 register
input pre_fetch_en4_in ; // bit-1 in pci_image_ctr4 register
input pre_fetch_en5_in ; // bit-1 in pci_image_ctr5 register
// Input from image registers - register values needed for decoder to work properly
input [pci_ba0_width - 1:0] pci_base_addr0_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_base_addr1_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_base_addr2_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_base_addr3_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_base_addr4_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_base_addr5_in ; // base address from base address register
input [pci_ba1_5_width - 1:0] pci_addr_mask0_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_addr_mask1_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_addr_mask2_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_addr_mask3_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_addr_mask4_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_addr_mask5_in ; // masking of base address from address mask register
input [pci_ba1_5_width - 1:0] pci_tran_addr0_in ; // translation address from address translation register
input [pci_ba1_5_width - 1:0] pci_tran_addr1_in ; // translation address from address translation register
input [pci_ba1_5_width - 1:0] pci_tran_addr2_in ; // translation address from address translation register
input [pci_ba1_5_width - 1:0] pci_tran_addr3_in ; // translation address from address translation register
input [pci_ba1_5_width - 1:0] pci_tran_addr4_in ; // translation address from address translation register
input [pci_ba1_5_width - 1:0] pci_tran_addr5_in ; // translation address from address translation register
input addr_tran_en0_in ; // address translation enable bit
input addr_tran_en1_in ; // address translation enable bit
input addr_tran_en2_in ; // address translation enable bit
input addr_tran_en3_in ; // address translation enable bit
input addr_tran_en4_in ; // address translation enable bit
input addr_tran_en5_in ; // address translation enable bit
/*==================================================================================================================
END of input / output PORT DEFINITONS !!!
==================================================================================================================*/
// address output from address multiplexer
reg [31:0] address ;
// prefetch enable for access to selected image space
reg pre_fetch_en ;
// Input addresses and image hits from address decoders - addresses are multiplexed to address
`ifdef HOST
`ifdef NO_CNF_IMAGE
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
wire hit0_in ;
wire [31:0] address0_in ;
wire pre_fetch_en0 = pre_fetch_en0_in ;
`else
wire hit0_in = 1'b0 ;
wire [31:0] address0_in = 32'h0 ;
wire pre_fetch_en0 = 1'b0 ;
`endif
`else
wire hit0_in ;
wire [31:0] address0_in ;
wire pre_fetch_en0 = pre_fetch_en0_in ;
`endif
`else // GUEST
wire hit0_in ;
wire [31:0] address0_in ;
wire pre_fetch_en0 = pre_fetch_en0_in ;
`endif
wire hit1_in ;
wire [31:0] address1_in ;
wire pre_fetch_en1 = pre_fetch_en1_in ;
`ifdef PCI_IMAGE2
wire hit2_in ;
wire [31:0] address2_in ;
wire pre_fetch_en2 = pre_fetch_en2_in ;
`else
wire hit2_in = 1'b0 ;
wire [31:0] address2_in = 32'h0 ;
wire pre_fetch_en2 = 1'b0 ;
`endif
`ifdef PCI_IMAGE3
wire hit3_in ;
wire [31:0] address3_in ;
wire pre_fetch_en3 = pre_fetch_en3_in ;
`else
wire hit3_in = 1'b0 ;
wire [31:0] address3_in = 32'h0 ;
wire pre_fetch_en3 = 1'b0 ;
`endif
`ifdef PCI_IMAGE4
wire hit4_in ;
wire [31:0] address4_in ;
wire pre_fetch_en4 = pre_fetch_en4_in ;
`else
wire hit4_in = 1'b0 ;
wire [31:0] address4_in = 32'h0 ;
wire pre_fetch_en4 = 1'b0 ;
`endif
`ifdef PCI_IMAGE5
wire hit5_in ;
wire [31:0] address5_in ;
wire pre_fetch_en5 = pre_fetch_en5_in ;
`else
wire hit5_in = 1'b0 ;
wire [31:0] address5_in = 32'h0 ;
wire pre_fetch_en5 = 1'b0 ;
`endif
// Include address decoders
`ifdef HOST
`ifdef NO_CNF_IMAGE
`ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space
pci_pci_decoder #(pci_ba0_width) decoder0
(.hit (hit0_in),
.addr_out (address0_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr0_in),
.mask_addr (pci_addr_mask0_in),
.tran_addr (pci_tran_addr0_in),
.at_en (addr_tran_en0_in),
.mem_io_space (mem_io_addr_space0_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`endif
`else
pci_pci_decoder #(pci_ba0_width) decoder0
(.hit (hit0_in),
.addr_out (address0_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr0_in),
.mask_addr ({pci_ba0_width{1'b1}}),
.tran_addr ({pci_ba0_width{1'b0}}),
.at_en (1'b0),
.mem_io_space (1'b0),
.mem_en (mem_enable_in),
.io_en (1'b0)
) ;
`endif
`else // GUEST
pci_pci_decoder #(pci_ba0_width) decoder0
(.hit (hit0_in),
.addr_out (address0_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr0_in),
.mask_addr ({pci_ba0_width{1'b1}}),
.tran_addr ({pci_ba0_width{1'b0}}),
.at_en (1'b0),
.mem_io_space (1'b0),
.mem_en (mem_enable_in),
.io_en (1'b0)
) ;
`endif
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder1
(.hit (hit1_in),
.addr_out (address1_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr1_in),
.mask_addr (pci_addr_mask1_in),
.tran_addr (pci_tran_addr1_in),
.at_en (addr_tran_en1_in),
.mem_io_space (mem_io_addr_space1_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`ifdef PCI_IMAGE2
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder2
(.hit (hit2_in),
.addr_out (address2_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr2_in),
.mask_addr (pci_addr_mask2_in),
.tran_addr (pci_tran_addr2_in),
.at_en (addr_tran_en2_in),
.mem_io_space (mem_io_addr_space2_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`endif
`ifdef PCI_IMAGE3
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder3
(.hit (hit3_in),
.addr_out (address3_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr3_in),
.mask_addr (pci_addr_mask3_in),
.tran_addr (pci_tran_addr3_in),
.at_en (addr_tran_en3_in),
.mem_io_space (mem_io_addr_space3_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`endif
`ifdef PCI_IMAGE4
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder4
(.hit (hit4_in),
.addr_out (address4_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr4_in),
.mask_addr (pci_addr_mask4_in),
.tran_addr (pci_tran_addr4_in),
.at_en (addr_tran_en4_in),
.mem_io_space (mem_io_addr_space4_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`endif
`ifdef PCI_IMAGE5
pci_pci_decoder #(`PCI_NUM_OF_DEC_ADDR_LINES) decoder5
(.hit (hit5_in),
.addr_out (address5_in),
.addr_in (address_in),
.bc_in (bc_in),
.base_addr (pci_base_addr5_in),
.mask_addr (pci_addr_mask5_in),
.tran_addr (pci_tran_addr5_in),
.at_en (addr_tran_en5_in),
.mem_io_space (mem_io_addr_space5_in),
.mem_en (mem_enable_in),
.io_en (io_enable_in)
) ;
`endif
// Internal signals for image hit determination
reg addr_claim ;// address claim signal is asinchronous set for addr_claim_out signal to PCI Target SM
// Determining if image 0 is assigned to configuration space or as normal pci to wb access!
// if normal access is allowed to configuration space, then hit0 is hit0_conf
`ifdef HOST
`ifdef NO_CNF_IMAGE
parameter hit0_conf = 1'b0 ;
`else
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
`endif
`else // GUEST
parameter hit0_conf = 1'b1 ; // if normal access is allowed to configuration space, then hit0 is hit0_conf
`endif
// Logic with address mux, determining if address is still in the same image space and if it is prefetced or not
always@(hit5_in or hit4_in or hit3_in or hit2_in or hit1_in or hit0_in or
address5_in or address4_in or address3_in or address2_in or address1_in or address0_in or
pre_fetch_en5 or
pre_fetch_en4 or
pre_fetch_en3 or
pre_fetch_en2 or
pre_fetch_en1 or
pre_fetch_en0
)
begin
addr_claim <= (hit5_in || hit4_in) || (hit3_in || hit2_in || hit1_in || hit0_in) ;
case ({hit5_in, hit4_in, hit3_in, hit2_in, hit0_in})
5'b10000 :
begin
address <= address5_in ;
pre_fetch_en <= pre_fetch_en5 ;
end
5'b01000 :
begin
address <= address4_in ;
pre_fetch_en <= pre_fetch_en4 ;
end
5'b00100 :
begin
address <= address3_in ;
pre_fetch_en <= pre_fetch_en3 ;
end
5'b00010 :
begin
address <= address2_in ;
pre_fetch_en <= pre_fetch_en2 ;
end
5'b00001 :
begin
address <= address0_in ;
pre_fetch_en <= pre_fetch_en0 ;
end
default : // IMAGE 1 is always included into PCI bridge
begin
address <= address1_in ;
pre_fetch_en <= pre_fetch_en1 ;
end
endcase
end
// Address claim output to PCI Target SM
assign addr_claim_out = addr_claim ;
reg [31:0] norm_address ; // stored normal address (decoded and translated) for access to WB
reg norm_prf_en ; // stored pre-fetch enable
reg [3:0] norm_bc ; // stored bus-command
reg same_read_reg ; // stored SAME_READ information
reg target_rd ; // delayed registered TRDY output equivalent signal
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
norm_address <= #`FF_DELAY 32'h0000_0000 ;
norm_prf_en <= #`FF_DELAY 1'b0 ;
norm_bc <= #`FF_DELAY 4'h0 ;
same_read_reg <= #`FF_DELAY 1'b0 ;
end
else
begin
if (addr_phase_in)
begin
norm_address <= #`FF_DELAY address ;
norm_prf_en <= #`FF_DELAY pre_fetch_en ;
norm_bc <= #`FF_DELAY bc_in ;
same_read_reg <= #`FF_DELAY same_read_out ;
end
end
end
`ifdef HOST
`ifdef NO_CNF_IMAGE
reg [1:0] strd_address ; // stored INPUT address for accessing Configuration space registers
`else
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
`endif
`else
reg [11:0] strd_address ; // stored INPUT address for accessing Configuration space registers
`endif
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
strd_address <= #`FF_DELAY 0 ;
end
else
begin
if (addr_phase_in)
begin
`ifdef HOST
`ifdef NO_CNF_IMAGE
strd_address <= #`FF_DELAY address_in[1:0] ;
`else
strd_address <= #`FF_DELAY address_in[11:0] ;
`endif
`else
strd_address <= #`FF_DELAY address_in[11:0] ;
`endif
end
end
end
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
target_rd <= #`FF_DELAY 1'b0 ;
end
else
begin
if (same_read_reg && !bckp_trdy_in)
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
else if (same_read_reg && bckp_devsel_in && !bckp_stop_in)
target_rd <= #`FF_DELAY 1'b1 ;// Signal indicates when target ready is deaserted on PCI bus
else if ((!same_read_reg) || (last_reg_in && target_rd))
target_rd <= #`FF_DELAY 1'b0 ;// Signal indicates when target ready is deaserted on PCI bus
end
end
// '1' indicates asserted TRDY signal when same read operation is performed
wire target_rd_completed = target_rd ;
reg same_read_request ;
// When delayed read is completed on WB, addres and bc must be compered, if there is the same read request
always@(address or strd_addr_in or bc_in or strd_bc_in)
begin
if ((address == strd_addr_in) & (bc_in == strd_bc_in))
same_read_request <= 1'b1 ;
else
same_read_request <= 1'b0 ;
end
assign same_read_out = (same_read_request) ; // && ~pcir_fifo_empty_in) ;
// Signals for byte enable checking
reg addr_burst_ok ;
reg io_be_ok ;
// Byte enable checking for IO, MEMORY and CONFIGURATION spaces - be_in is active low!
always@(strd_address or be_in)
begin
case (strd_address[1:0])
2'b11 :
begin
addr_burst_ok <= 1'b0 ;
io_be_ok <= (be_in[2] && be_in[1] && be_in[0]) ; // only be3 can be active
end
2'b10 :
begin
addr_burst_ok <= 1'b0 ;
io_be_ok <= (~be_in[2] && be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
end
2'b01 :
begin
addr_burst_ok <= 1'b0 ;
io_be_ok <= (~be_in[1] && be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
end
default : // 2'b00
begin
addr_burst_ok <= 1'b1 ;
io_be_ok <= (~be_in[0]) || (be_in[3] && be_in[2] && be_in[1] && be_in[0]) ;
end
endcase
end
wire calc_target_abort = (norm_bc[3:1] == `BC_IO_RW) ? !io_be_ok : 1'b0 ;
wire [3:0] pcir_fifo_control_input = pcir_fifo_empty_in ? 4'h0 : pcir_fifo_control_in ;
// Medium registers for data and control busses from PCIR_FIFO
reg [31:0] pcir_fifo_data_reg ;
reg [3:0] pcir_fifo_ctrl_reg ;
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
pcir_fifo_data_reg <= #`FF_DELAY 32'h0000_0000 ;
pcir_fifo_ctrl_reg <= #`FF_DELAY 4'h0 ;
end
else
begin
if (load_medium_reg_in)
begin
pcir_fifo_data_reg <= #`FF_DELAY pcir_fifo_data_in ;
pcir_fifo_ctrl_reg <= #`FF_DELAY pcir_fifo_control_input ;
end
end
end
// when disconnect is signalled, the next data written to fifo will be the last
// also when this happens, disconnect must stay asserted until last data is written to the fifo
reg keep_desconnect_wo_data_set ;
// selecting "fifo data" from medium registers or from PCIR_FIFO
wire [31:0] pcir_fifo_data = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_data_in : pcir_fifo_data_reg ;
wire [3:0] pcir_fifo_ctrl = (sel_fifo_mreg_in && !pcir_fifo_empty_in) ? pcir_fifo_control_input : pcir_fifo_ctrl_reg ;
// signal assignments to PCI Target FSM
assign read_completed_out = req_comp_pending_in ; // completion pending input for requesting side of the bridge
assign read_processing_out = req_req_pending_in ; // request pending input for requesting side
// when '1', the bus command is IO command - not supported commands are checked in pci_decoder modules
wire io_memory_bus_command = !norm_bc[3] && !norm_bc[2] ;
assign disconect_wo_data_out = (
((/*pcir_fifo_ctrl[`LAST_CTRL_BIT] ||*/ pcir_fifo_empty_in || ~burst_ok_out/*addr_burst_ok*/ || io_memory_bus_command) &&
~bc0_in && ~frame_reg_in) ||
((pciw_fifo_full_in || pciw_fifo_almost_full_in || keep_desconnect_wo_data_set || pciw_fifo_two_left_in ||
(pciw_fifo_three_left_in && pciw_fifo_wenable) || ~addr_burst_ok || io_memory_bus_command) &&
bc0_in && ~frame_reg_in)
) ;
assign disconect_w_data_out = (
( burst_ok_out && !io_memory_bus_command && ~bc0_in ) ||
( addr_burst_ok && !io_memory_bus_command && bc0_in )
) ;
assign target_abort_out = ( ~addr_phase_in && calc_target_abort ) ;
`ifdef HOST
`ifdef NO_CNF_IMAGE
// signal assignments to PCI Target FSM
assign norm_access_to_config_out = 1'b0 ;
// control signal assignments to read request sinchronization module
assign done_out = (target_rd_completed && last_reg_in) ;
assign in_progress_out = (same_read_reg && ~bckp_trdy_in) ;
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
wire pcir_fifo_flush = (target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
`else
// signal assignments to PCI Target FSM
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
// control signal assignments to read request sinchronization module
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
`endif
`else
// signal assignments to PCI Target FSM
assign norm_access_to_config_out = (hit0_in && hit0_conf) ;
// control signal assignments to read request sinchronization module
assign done_out = (~sel_conf_fifo_in && target_rd_completed && last_reg_in) ;
assign in_progress_out = (~sel_conf_fifo_in && same_read_reg && ~bckp_trdy_in) ;
// signal used for PCIR_FIFO flush (with comp_flush_in signal)
wire pcir_fifo_flush = (~sel_conf_fifo_in && target_rd_completed && last_reg_in && ~pcir_fifo_empty_in) ;
`endif
// flush signal for PCIR_FIFO must be registered, since it asinchronously resets some status registers
wire pcir_fifo_flush_reg ;
pci_async_reset_flop async_reset_as_pcir_flush
(
.data_in (comp_flush_in || pcir_fifo_flush),
.clk_in (clk_in),
.async_reset_data_out (pcir_fifo_flush_reg),
.reset_in (reset_in)
) ;
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
keep_desconnect_wo_data_set <= #1 1'b0 ;
else if (keep_desconnect_wo_data_set && pciw_fifo_wenable)
keep_desconnect_wo_data_set <= #1 1'b0 ;
else if (pciw_fifo_wenable && disconect_wo_data_out)
keep_desconnect_wo_data_set <= #1 1'b1 ;
end
// signal assignments from fifo to PCI Target FSM
assign wbw_fifo_empty_out = wbw_fifo_empty_in ;
assign wbu_del_read_comp_pending_out = wbu_del_read_comp_pending_in ;
assign pciw_fifo_full_out = (pciw_fifo_full_in || pciw_fifo_almost_full_in || pciw_fifo_two_left_in || pciw_fifo_three_left_in) ;
assign pcir_fifo_data_err_out = pcir_fifo_ctrl[`DATA_ERROR_CTRL_BIT] && !sel_conf_fifo_in ;
// signal assignments to PCIR FIFO fifo
assign pcir_fifo_flush_out = pcir_fifo_flush_reg ;
assign pcir_fifo_renable_out = fetch_pcir_fifo_in && !pcir_fifo_empty_in ;
// signal assignments to PCIW FIFO
reg pciw_fifo_wenable_out;
assign pciw_fifo_wenable = load_to_pciw_fifo_in ;
reg [3:0] pciw_fifo_control_out;
reg [31:0] pciw_fifo_addr_data_out;
reg [3:0] pciw_fifo_cbe_out;
always@(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
pciw_fifo_wenable_out <= #1 1'b0;
pciw_fifo_control_out <= #1 4'h0;
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
pciw_fifo_addr_data_out <= #1 32'h0;
pciw_fifo_cbe_out <= #1 4'h0;
end
else
begin
pciw_fifo_wenable_out <= #1 load_to_pciw_fifo_in ;
pciw_fifo_control_out[`ADDR_CTRL_BIT] <= #1 ~rdy_in ;
pciw_fifo_control_out[`BURST_BIT] <= #1 rdy_in ? ~frame_reg_in : 1'b0 ;
// if '1' then next burst BE is not equat to current one => burst will be chopped into single transfers
pciw_fifo_control_out[`DATA_ERROR_CTRL_BIT] <= #1 rdy_in && (next_be_in != be_in) && ~bckp_trdy_in; // valid comp.
pciw_fifo_control_out[`LAST_CTRL_BIT] <= #1 rdy_in && (frame_reg_in || (bckp_trdy_in && ~bckp_stop_in));
// data and address outputs assignments to PCIW_FIFO - correction of 2 LSBits
pciw_fifo_addr_data_out <= #1 rdy_in ? data_in : {norm_address[31:2],
norm_address[1] && io_memory_bus_command,
norm_address[0] && io_memory_bus_command} ;
pciw_fifo_cbe_out <= #1 rdy_in ? be_in : norm_bc ;
end
end
`ifdef HOST
`ifdef NO_CNF_IMAGE
// data and address outputs assignments to PCI Target FSM
assign data_out = pcir_fifo_data ;
`else
// data and address outputs assignments to PCI Target FSM
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
`endif
`else
// data and address outputs assignments to PCI Target FSM
assign data_out = sel_conf_fifo_in ? conf_data_in : pcir_fifo_data ;
`endif
// data and address outputs assignments to read request sinchronization module
assign req_out = req_in ;
// this address is stored in delayed_sync module and is connected back as strd_addr_in
assign addr_out = norm_address[31:0] ; // correction of 2 LSBits is done in wb_master module, original address must be saved
assign be_out = be_in ;
assign we_out = 1'b0 ;
assign bc_out = norm_bc ;
// burst is OK for reads when there is ((MEM_READ_LN or MEM_READ_MUL) and AD[1:0]==2'b00) OR
// (MEM_READ and Prefetchable_IMAGE and AD[1:0]==2'b00)
assign burst_ok_out = (norm_bc[3] && addr_burst_ok) || (norm_bc[2] && norm_prf_en && addr_burst_ok) ;
// data and address outputs assignments to Configuration space
`ifdef HOST
`ifdef NO_CNF_IMAGE
assign conf_data_out = 32'h0 ;
assign conf_addr_out = 12'h0 ;
assign conf_be_out = 4'b0 ;
assign conf_we_out = 1'h0 ;
`else
assign conf_data_out = data_in ;
assign conf_addr_out = strd_address[11:0] ;
assign conf_be_out = be_in ;
assign conf_we_out = load_to_conf_in ;
`endif
`else
assign conf_data_out = data_in ;
assign conf_addr_out = strd_address[11:0] ;
assign conf_be_out = be_in ;
assign conf_we_out = load_to_conf_in ;
`endif
// NOT USED NOW, SONCE READ IS ASYNCHRONOUS
//assign conf_re_out = fetch_conf_in ;
assign conf_re_out = 1'b0 ;
endmodule |
module pci_wb_tpram
(
// Generic synchronous two-port RAM interface
clk_a,
rst_a,
ce_a,
we_a,
oe_a,
addr_a,
di_a,
do_a,
clk_b,
rst_b,
ce_b,
we_b,
oe_b,
addr_b,
di_b,
do_b
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 40;
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
`ifdef PCI_BIST
// debug chain signals
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
//
// Internal wires and registers
//
`ifdef WB_VS_STP
`define PCI_WB_RAM_SELECTED
`ifdef PCI_BIST
vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
`else
vs_hdtp_64x40 i_vs_hdtp_64x40
`endif
(
.RCK (clk_b),
.WCK (clk_a),
.RADR (addr_b),
.WADR (addr_a),
.DI (di_a),
.DOUT (do_b),
.REN (1'b0),
.WEN (!we_a)
`ifdef PCI_BIST
,
// debug chain signals
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign do_a = 0 ;
`endif
`ifdef WB_ARTISAN_SDP
`define PCI_WB_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef PCI_BIST
art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.QA(do_a),
.CLKA(clk_a),
.CENA(~ce_a),
.WENA(~we_a),
.AA(addr_a),
.DA(di_a),
.OENA(~oe_a),
.QB(do_b),
.CLKB(clk_b),
.CENB(~ce_b),
.WENB(~we_b),
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b),
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
);
`else
art_hsdp_64x40 /*#(dw, 1<<aw, aw) */ artisan_sdp
(
.QA(do_a),
.CLKA(clk_a),
.CENA(~ce_a),
.WENA(~we_a),
.AA(addr_a),
.DA(di_a),
.OENA(~oe_a),
.QB(do_b),
.CLKB(clk_b),
.CENB(~ce_b),
.WENB(~we_b),
.AB(addr_b),
.DB(di_b),
.OENB(~oe_b)
);
`endif
`endif
`ifdef AVANT_ATP
`define PCI_WB_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.do(do)
);
`endif
`ifdef VIRAGE_STP
`define PCI_WB_RAM_SELECTED
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
`endif
`ifdef WB_XILINX_DIST_RAM
`define PCI_WB_RAM_SELECTED
reg [(aw-1):0] out_address ;
always@(posedge clk_b or posedge rst_b)
begin
if ( rst_b )
out_address <= #1 0 ;
else if (ce_b)
out_address <= #1 addr_b ;
end
pci_ram_16x40d #(aw) wb_distributed_ram
(
.data_out (do_b),
.we (we_a),
.data_in (di_a),
.read_address (out_address),
.write_address (addr_a),
.wclk (clk_a)
);
assign do_a = 0 ;
`endif
`ifdef WB_XILINX_RAMB4
`define PCI_WB_RAM_SELECTED
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
//
// Block 2
//
// block ram2 wires - non generic width of block rams
wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
wire [15:0] blk2_do_a ;
wire [15:0] blk2_do_b ;
assign do_a[39:32] = blk2_do_a[7:0] ;
assign do_b[39:32] = blk2_do_b[7:0] ;
RAMB4_S16_S16 ramb4_s16_s16_2(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(blk2_di_a),
.ENA(ce_a),
.WEA(we_a),
.DOA(blk2_do_a),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(blk2_di_b),
.ENB(ce_b),
.WEB(we_b),
.DOB(blk2_do_b)
);
`endif
`ifdef PCI_WB_RAM_SELECTED
`else
//
// Generic two-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [dw-1:0] do_reg_b; // RAM data output register
//
// Data output drivers
//
assign do_a = {dw{1'b0}} ;
assign do_b = do_reg_b ;
//
// RAM read and write
//
always @(posedge clk_a)
if (ce_a && we_a)
mem[addr_a] <= #1 di_a;
//
// RAM read and write
//
always @(posedge clk_b)
if (ce_b)
do_reg_b <= #1 mem[addr_b];
`endif
// synopsys translate_off
initial
begin
if (dw !== 40)
begin
$display("RAM instantiation error! Expected RAM width %d, actual %h!", 40, dw) ;
$finish ;
end
`ifdef XILINX_RAMB4
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
// currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
`ifdef ARTISAN_SDP
if (aw !== 8)
begin
$display("RAM instantiation error! Expected RAM address width %d, actual %h!", 40, aw) ;
$finish ;
end
`endif
end
// synopsys translate_on
endmodule |
module pci_mas_ch_state_crit
(
change_state_out,
ch_state_med_in,
sm_data_phases_in,
pci_trdy_in,
pci_stop_in
) ;
output change_state_out ;
input ch_state_med_in,
sm_data_phases_in,
pci_trdy_in,
pci_stop_in ;
assign change_state_out = ch_state_med_in || sm_data_phases_in && (~(pci_trdy_in && pci_stop_in)) ;
endmodule |
module pci_in_reg
(
reset_in,
clk_in,
init_complete_in,
pci_gnt_in,
pci_frame_in,
pci_irdy_in,
pci_trdy_in,
pci_stop_in,
pci_devsel_in,
pci_idsel_in,
pci_ad_in,
pci_cbe_in,
pci_gnt_reg_out,
pci_frame_reg_out,
pci_irdy_reg_out,
pci_trdy_reg_out,
pci_stop_reg_out,
pci_devsel_reg_out,
pci_idsel_reg_out,
pci_ad_reg_out,
pci_cbe_reg_out
);
input reset_in, clk_in, init_complete_in ;
input pci_gnt_in ;
input pci_frame_in ;
input pci_irdy_in ;
input pci_trdy_in ;
input pci_stop_in ;
input pci_devsel_in ;
input pci_idsel_in ;
input [31:0] pci_ad_in ;
input [3:0] pci_cbe_in ;
output pci_gnt_reg_out ;
output pci_frame_reg_out ;
output pci_irdy_reg_out ;
output pci_trdy_reg_out ;
output pci_stop_reg_out ;
output pci_devsel_reg_out ;
output pci_idsel_reg_out ;
output [31:0] pci_ad_reg_out ;
output [3:0] pci_cbe_reg_out ;
reg pci_gnt_reg_out ;
reg pci_frame_reg_out ;
reg pci_irdy_reg_out ;
reg pci_trdy_reg_out ;
reg pci_stop_reg_out ;
reg pci_devsel_reg_out ;
reg pci_idsel_reg_out ;
reg [31:0] pci_ad_reg_out ;
reg [3:0] pci_cbe_reg_out ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
begin
pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
pci_frame_reg_out <= #`FF_DELAY 1'b0 ;
pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
end
else if (init_complete_in)
begin
pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;
pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;
pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;
pci_ad_reg_out <= #`FF_DELAY pci_ad_in ;
pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
end
end
endmodule |
module pci_target32_stop_crit
(
stop_w,
stop_w_frm,
stop_w_frm_irdy,
pci_frame_in,
pci_irdy_in,
pci_stop_out
);
input stop_w ; // stop signal (composed without critical signals) that do not need critical inputs
input stop_w_frm ; // stop signal (composed without critical signals) that needs AND with critical FRAME input
input stop_w_frm_irdy ; // stop signal (composed without critical signals) that needs AND with critical FRAME and
// IRDY inputs
input pci_frame_in ; // critical constrained input signal
input pci_irdy_in ; // critical constrained input signal
output pci_stop_out ; // PCI stop output
// PCI stop output with preserved hierarchy for minimum delay!
assign pci_stop_out = ~(stop_w || (stop_w_frm && ~pci_frame_in) || (stop_w_frm_irdy && ~pci_frame_in && ~pci_irdy_in)) ;
endmodule |
module pci_wbs_wbb3_2_wbb2
(
wb_clk_i,
wb_rst_i,
wbs_cyc_i,
wbs_cyc_o,
wbs_stb_i,
wbs_stb_o,
wbs_adr_i,
wbs_adr_o,
wbs_dat_i_i,
wbs_dat_i_o,
wbs_dat_o_i,
wbs_dat_o_o,
wbs_we_i,
wbs_we_o,
wbs_sel_i,
wbs_sel_o,
wbs_ack_i,
wbs_ack_o,
wbs_err_i,
wbs_err_o,
wbs_rty_i,
wbs_rty_o,
wbs_cti_i,
wbs_bte_i,
wbs_cab_o,
wb_init_complete_i
) ;
input wb_clk_i ;
input wb_rst_i ;
input wbs_cyc_i ;
output wbs_cyc_o ;
input wbs_stb_i ;
output wbs_stb_o ;
input [31:0] wbs_adr_i ;
output [31:0] wbs_adr_o ;
input [31:0] wbs_dat_i_i ;
output [31:0] wbs_dat_i_o ;
input [31:0] wbs_dat_o_i ;
output [31:0] wbs_dat_o_o ;
input wbs_we_i ;
output wbs_we_o ;
input [ 3:0] wbs_sel_i ;
output [ 3:0] wbs_sel_o ;
input wbs_ack_i ;
output wbs_ack_o ;
input wbs_err_i ;
output wbs_err_o ;
input wbs_rty_i ;
output wbs_rty_o ;
input [ 2:0] wbs_cti_i ;
input [ 1:0] wbs_bte_i ;
output wbs_cab_o ;
input wb_init_complete_i ;
reg wbs_cyc_o ;
reg [31:0] wbs_adr_o ;
reg [31:0] wbs_dat_i_o ;
reg wbs_dat_i_o_valid ;
reg [31:0] wbs_dat_o_o ;
reg wbs_we_o ;
reg [ 3:0] wbs_sel_o ;
reg wbs_ack_o ;
reg wbs_err_o ;
reg wbs_rty_o ;
reg wbs_cab_o ;
always@(posedge wb_rst_i or posedge wb_clk_i)
begin
if (wb_rst_i)
begin
wbs_cyc_o <= 1'b0 ;
wbs_adr_o <= 32'h0 ;
wbs_dat_i_o <= 32'h0 ;
wbs_dat_o_o <= 32'h0 ;
wbs_sel_o <= 4'h0 ;
wbs_we_o <= 1'b0 ;
wbs_dat_i_o_valid <= 1'b0 ;
wbs_cab_o <= 1'b0 ;
end
else
begin:transfer_and_transfer_adr_ctrl_blk
reg start_cycle ;
reg [3:0] end_cycle ;
reg generate_int_adr ;
start_cycle = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i ;
// there is a few conditions when cycle must be terminated
// I've put them into bit array for better readability of the code
// 1st condition - pci bridge is signaling an error
end_cycle[0] = wbs_err_i ;
// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
end_cycle[1] = wbs_rty_i
`ifdef PCI_WBS_B3_RTY_DISABLE
& 1'b0
`endif
;
// 3rd condition - end non burst cycles as soon as pci bridge response is received
end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
if (wbs_dat_i_o_valid)
begin
if (wbs_ack_i | wbs_err_i
`ifdef PCI_WBS_B3_RTY_DISABLE
`else
| wbs_rty_i
`endif
)
wbs_dat_i_o_valid <= 1'b0 ;
end
else
begin
if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i)
begin
wbs_dat_i_o <= wbs_dat_i_i ;
wbs_dat_i_o_valid <= 1'b1 ;
end
end
if (start_cycle)
begin
wbs_cyc_o <= 1'b1 ;
wbs_sel_o <= wbs_sel_i ;
wbs_we_o <= wbs_we_i ;
if (wbs_cti_i == 3'b010)
begin
case (wbs_bte_i)
2'b00: begin
wbs_cab_o <= 1'b1 ;
end
2'b01: begin
if (wbs_adr_i[3:2] == 2'b00)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
end
2'b10: begin
if (wbs_adr_i[4:2] == 3'b000)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
end
2'b11: begin
if (wbs_adr_i[5:2] == 4'b0000)
wbs_cab_o <= 1'b1 ;
else
wbs_cab_o <= 1'b0 ;
end
endcase
end
else
begin
wbs_cab_o <= 1'b0 ;
end
end
else if ( wbs_cyc_o & (|end_cycle) )
begin
wbs_cyc_o <= 1'b0 ;
end
if (start_cycle)
wbs_adr_o <= wbs_adr_i ;
else if (wbs_ack_i)
wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;
if (~wbs_we_o & wbs_ack_i)
wbs_dat_o_o <= wbs_dat_o_i ;
end
end
always@(posedge wb_rst_i or posedge wb_clk_i)
begin
if (wb_rst_i)
begin
wbs_ack_o <= 1'b0 ;
wbs_err_o <= 1'b0 ;
wbs_rty_o <= 1'b0 ;
end
else
begin
if (wbs_ack_o)
wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ;
else
wbs_ack_o <= wbs_ack_i ;
if (wbs_err_o)
wbs_err_o <= ~wbs_stb_i ;
else
wbs_err_o <= wbs_err_i ;
`ifdef PCI_WBS_B3_RTY_DISABLE
wbs_rty_o <= 1'b0 ;
`else
if (wbs_rty_o)
wbs_rty_o <= ~wbs_stb_i ;
else
wbs_rty_o <= wbs_rty_i ;
`endif
end
end
assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i != 3'b111) |
(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
endmodule |
module pci_cbe_en_crit
(
pci_cbe_en_out,
cbe_en_slow_in,
cbe_en_keep_in,
pci_stop_in,
pci_trdy_in
) ;
output pci_cbe_en_out ;
input cbe_en_slow_in,
cbe_en_keep_in,
pci_stop_in,
pci_trdy_in ;
assign pci_cbe_en_out = cbe_en_slow_in || cbe_en_keep_in && pci_stop_in && pci_trdy_in ;
endmodule |
module pci_spoci_ctrl
(
reset_i ,
clk_i ,
do_rnd_read_i ,
do_seq_read_i ,
do_write_i ,
write_done_o ,
dat_rdy_o ,
no_ack_o ,
adr_i ,
dat_i ,
dat_o ,
pci_spoci_sda_i ,
pci_spoci_sda_oe_o ,
pci_spoci_scl_oe_o
);
parameter tx_rx_state_width = 9 ;
parameter tx_rx_idle = 'h1 ;
parameter tx_rx_start = 'h2 ;
parameter tx_rx_restart = 'h4 ;
parameter tx_rx_send_bits = 'h8 ;
parameter tx_rx_rec_bits = 'h10 ;
parameter tx_rx_send_ack = 'h20 ;
parameter tx_rx_rec_ack = 'h40 ;
parameter tx_rx_send_nack = 'h80 ;
parameter tx_rx_stop = 'h100 ;
parameter rw_seq_state_width = 5 ;
parameter rw_seq_idle = 'h1 ;
parameter rw_seq_tx_ctrl = 'h2 ;
parameter rw_seq_tx_adr = 'h4 ;
parameter rw_seq_tx_byte = 'h8 ;
parameter rw_seq_rx_byte = 'h10 ;
`ifdef PCI33
parameter cnt_width = 9 ;
parameter period_cnt = 334 ;
`endif
`ifdef PCI66
parameter cnt_width = 10 ;
parameter period_cnt = 667 ;
`endif
input reset_i ,
clk_i ;
input do_rnd_read_i ,
do_seq_read_i ,
do_write_i ;
output write_done_o ,
dat_rdy_o ,
no_ack_o ;
input [10: 0] adr_i ;
input [ 7: 0] dat_i ;
output [ 7: 0] dat_o ;
input pci_spoci_sda_i ;
output pci_spoci_sda_oe_o ,
pci_spoci_scl_oe_o ;
reg write_done_o ,
dat_rdy_o ,
no_ack_o ;
reg [ 7: 0] dat_o ;
reg pci_spoci_sda_oe_o ,
pci_spoci_scl_oe_o ;
reg clk_gen_cnt_en ;
reg clk_gen_cnt_clr ;
reg [cnt_width - 1:0] clk_gen_cnt ;
reg [tx_rx_state_width - 1:0] tx_rx_state ;
reg [tx_rx_state_width - 1:0] tx_rx_next_state ;
reg tx_rx_sm_idle ;
reg scl_oe ;
reg scl_oe_en ;
reg sda_oe ;
reg sda_oe_en ;
reg sda_i_reg_en ;
reg sda_i_reg ;
always@(posedge clk_i or posedge reset_i)
begin
if (reset_i)
begin
clk_gen_cnt <= 'h0 ;
tx_rx_state <= tx_rx_idle ;
`ifdef ACTIVE_LOW_OE
pci_spoci_sda_oe_o <= 1'b1 ;
pci_spoci_scl_oe_o <= 1'b1 ;
`endif
`ifdef ACTIVE_HIGH_OE
pci_spoci_sda_oe_o <= 1'b0 ;
pci_spoci_scl_oe_o <= 1'b0 ;
`endif
sda_i_reg <= 1'b1 ;
end
else
begin
tx_rx_state <= tx_rx_next_state ;
if (clk_gen_cnt_clr)
clk_gen_cnt <= 'h0 ;
else if (clk_gen_cnt_en)
clk_gen_cnt <= clk_gen_cnt + 1'b1 ;
if (sda_oe_en)
begin
`ifdef ACTIVE_LOW_OE
pci_spoci_sda_oe_o <= ~sda_oe ;
`endif
`ifdef ACTIVE_HIGH_OE
pci_spoci_sda_oe_o <= sda_oe ;
`endif
end
if (scl_oe_en)
begin
`ifdef ACTIVE_LOW_OE
pci_spoci_scl_oe_o <= ~scl_oe ;
`endif
`ifdef ACTIVE_HIGH_OE
pci_spoci_scl_oe_o <= scl_oe ;
`endif
end
if (sda_i_reg_en)
sda_i_reg <= pci_spoci_sda_i ;
end
end
reg [ 7: 0] tx_shift_reg ;
reg send_start ;
reg start_sent ;
reg send_bit ;
reg bit_sent ;
reg rec_bit ;
reg bit_rec ;
reg rec_ack ;
reg ack_rec ;
reg nack_rec ;
reg send_ack ;
reg ack_sent ;
reg send_nack ;
reg nack_sent ;
reg send_stop ;
reg stop_sent ;
always@
(
tx_rx_state or
clk_gen_cnt or
send_start or
send_bit or
tx_shift_reg or
send_stop or
rec_ack or
sda_i_reg or
rec_bit or
send_ack or
send_nack
)
begin
clk_gen_cnt_clr = 1'b0 ;
clk_gen_cnt_en = 1'b0 ;
tx_rx_next_state = tx_rx_state ;
tx_rx_sm_idle = 1'b0 ;
scl_oe = 1'b0 ;
sda_oe = 1'b0 ;
scl_oe_en = 1'b0 ;
sda_oe_en = 1'b0 ;
start_sent = 1'b0 ;
bit_sent = 1'b0 ;
ack_rec = 1'b0 ;
nack_rec = 1'b0 ;
sda_i_reg_en = 1'b0 ;
stop_sent = 1'b0 ;
bit_rec = 1'b0 ;
ack_sent = 1'b0 ;
nack_sent = 1'b0 ;
case (tx_rx_state)
tx_rx_idle:
begin
tx_rx_sm_idle = 1'b1 ;
// from idle state, the only transition can be to the send start bit
if (send_start)
begin
tx_rx_next_state = tx_rx_start ;
clk_gen_cnt_clr = 1'b1 ;
end
end
tx_rx_start:
begin
clk_gen_cnt_en = 1'b1 ;
sda_oe = 1'b1 ;
// start bit is sent by transmiting 0 on the sda line
if (clk_gen_cnt == (period_cnt >> 1))
begin
start_sent = 1'b1 ;
sda_oe_en = 1'b1 ;
end
// after half clock period of driving the sda low, the only possible
// transition is to send state.
// if send bit is not active, stop the procedure - undrive sda
if (clk_gen_cnt == period_cnt)
begin
clk_gen_cnt_clr = 1'b1 ;
if (send_bit)
begin
tx_rx_next_state = tx_rx_send_bits ;
end
else
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
tx_rx_next_state = tx_rx_idle ;
end
end
end
tx_rx_send_bits:
begin
clk_gen_cnt_en = 1'b1 ;
// generate high to low transition on the scl line immediately
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, load new value for sda oe, depending on the
// msb bit in the shift register
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = ~tx_shift_reg[7] ;
sda_oe_en = 1'b1 ;
bit_sent = 1'b1 ;
end
// after clock low time, generate low to high transition on the scl line
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after clock high time, check what to do next
if (clk_gen_cnt == (period_cnt))
begin
clk_gen_cnt_clr = 1'b1 ;
if (~send_bit)
begin
// after transmiting all the bits, the only possible transition is to the state
// that checks the eprom acknowledge
if (rec_ack)
tx_rx_next_state = tx_rx_rec_ack ;
else
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
tx_rx_next_state = tx_rx_idle ;
end
end
end
end
tx_rx_rec_bits:
begin
clk_gen_cnt_en = 1'b1 ;
sda_i_reg_en = 1'b1 ;
// generate high to low transition on the scl line immediately
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, disable sda driver
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
end
// after clock low time, generate low to high transition on the scl line
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after half of clock high time, report received bit
if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
begin
bit_rec = 1'b1 ;
end
// after clock period is finished, check the next operation
if (clk_gen_cnt == (period_cnt))
begin
clk_gen_cnt_clr = 1'b1 ;
if (~rec_bit)
begin
// when all bits are received, only nack or ack next states are possible
if (send_ack)
tx_rx_next_state = tx_rx_send_ack ;
else if (send_nack)
tx_rx_next_state = tx_rx_send_nack ;
else
begin
tx_rx_next_state = tx_rx_idle ;
end
end
end
end
tx_rx_send_ack:
begin
clk_gen_cnt_en = 1'b1 ;
// generate high to low transition on the scl line
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, enable the sda driver
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b1 ;
sda_oe_en = 1'b1 ;
ack_sent = 1'b1 ;
end
// after clock low time, disable the scl driver - generate low to high transition on the scl line
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after clock period time expires, check what to do next
if (clk_gen_cnt == period_cnt)
begin
clk_gen_cnt_clr = 1'b1 ;
// after the byte is acknowledged, the only possible next state is receive bits
// state
if (rec_bit)
tx_rx_next_state = tx_rx_rec_bits ;
else
begin
// this should never happen
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
tx_rx_next_state = tx_rx_idle ;
end
end
end
tx_rx_rec_ack:
begin
clk_gen_cnt_en = 1'b1 ;
sda_i_reg_en = 1'b1 ;
// generate high to low transition on the scl line
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, disable the sda driver
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
end
// after clock low time, disable the scl driver - generate low to high transition on the scl line
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after 1/2 clock high time, report ack or nack condition, depending on the sda input state
if (clk_gen_cnt == ((period_cnt >> 1) + (period_cnt >> 2)) )
begin
ack_rec = ~sda_i_reg ;
nack_rec = sda_i_reg ;
end
// after clock period time expires, check what to do next
if (clk_gen_cnt == period_cnt)
begin
clk_gen_cnt_clr = 1'b1 ;
if (send_bit)
tx_rx_next_state = tx_rx_send_bits ;
else if (rec_bit)
tx_rx_next_state = tx_rx_rec_bits ;
else if (send_stop)
tx_rx_next_state = tx_rx_stop ;
else if (send_start)
tx_rx_next_state = tx_rx_restart ;
else
begin
// this should never happen
tx_rx_next_state = tx_rx_idle ;
end
end
end
tx_rx_send_nack:
begin
clk_gen_cnt_en = 1'b1 ;
// generate high to low transition on the scl line
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, disable the sda driver
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
nack_sent = 1'b1 ;
end
// after clock low time, disable the scl driver - generate low to high transition on the scl line
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after clock period time expires, check what to do next
if (clk_gen_cnt == period_cnt)
begin
clk_gen_cnt_clr = 1'b1 ;
// after the no acknowledge is sent, the only possible next state is stop
// state
if (send_stop)
tx_rx_next_state = tx_rx_stop ;
else
begin
// this should never happen
tx_rx_next_state = tx_rx_idle ;
end
end
end
tx_rx_restart:
begin
clk_gen_cnt_en = 1'b1 ;
// generate high to low transition
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, release sda line
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
end
// generate low to high transition
if (clk_gen_cnt == (period_cnt >> 1))
begin
clk_gen_cnt_clr = 1'b1 ;
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
if (send_start)
tx_rx_next_state = tx_rx_start ;
else
tx_rx_next_state = tx_rx_idle ;
end
end
tx_rx_stop:
begin
clk_gen_cnt_en = 1'b1 ;
// generate high to low transition
if (clk_gen_cnt == 'h0)
begin
scl_oe = 1'b1 ;
scl_oe_en = 1'b1 ;
end
// after half of clock low time, drive sda line low
if (clk_gen_cnt == (period_cnt >> 2))
begin
sda_oe = 1'b1 ;
sda_oe_en = 1'b1 ;
end
// generate low to high transition
if (clk_gen_cnt == (period_cnt >> 1))
begin
scl_oe = 1'b0 ;
scl_oe_en = 1'b1 ;
end
// after full clock period, release the sda line
if (clk_gen_cnt == period_cnt)
begin
sda_oe = 1'b0 ;
sda_oe_en = 1'b1 ;
stop_sent = 1'b1 ;
tx_rx_next_state = tx_rx_idle ;
end
end
endcase
end
reg [rw_seq_state_width - 1:0] rw_seq_state ;
reg doing_read ,
doing_write ,
doing_seq_read ,
adr_set ;
reg [ 3: 0] bits_transfered ;
always@(posedge clk_i or posedge reset_i)
begin
if (reset_i)
begin
rw_seq_state <= rw_seq_idle ;
adr_set <= 1'b0 ;
doing_read <= 1'b0 ;
doing_write <= 1'b0 ;
doing_seq_read <= 1'b0 ;
dat_o <= 'h0 ;
tx_shift_reg <= 'h0 ;
send_start <= 'h0 ;
send_stop <= 'h0 ;
send_bit <= 'h0 ;
send_nack <= 'h0 ;
rec_ack <= 'h0 ;
no_ack_o <= 'h0 ;
bits_transfered <= 'h0 ;
write_done_o <= 'h0 ;
dat_rdy_o <= 'h0 ;
send_ack <= 'h0 ;
rec_bit <= 'h0 ;
end
else
begin
case (rw_seq_state)
rw_seq_idle:
begin
tx_shift_reg <= {4'b1010, adr_i[10: 8], 1'b0} ;
adr_set <= 1'b0 ;
if ( tx_rx_sm_idle & ~(doing_write | doing_read | doing_seq_read) )
begin
if (do_write_i | do_rnd_read_i | do_seq_read_i)
begin
rw_seq_state <= rw_seq_tx_ctrl ;
send_start <= 1'b1 ;
end
if (do_write_i)
doing_write <= 1'b1 ;
else if (do_rnd_read_i)
doing_read <= 1'b1 ;
else if (do_seq_read_i)
doing_seq_read <= 1'b1 ;
end
else
begin
doing_write <= 1'b0 ;
doing_read <= 1'b0 ;
doing_seq_read <= 1'b0 ;
end
end
rw_seq_tx_ctrl:
begin
if (send_start)
begin
bits_transfered <= 'h0 ;
if (start_sent)
begin
send_start <= 1'b0 ;
send_bit <= 1'b1 ;
end
end
else if (send_bit)
begin
if (bit_sent)
begin
bits_transfered <= bits_transfered + 1'b1 ;
tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
end
if (bits_transfered == 'h8)
begin
send_bit <= 1'b0 ;
rec_ack <= 1'b1 ;
end
end
else if (rec_ack)
begin
bits_transfered <= 'h0 ;
if (ack_rec | nack_rec)
rec_ack <= 1'b0 ;
if (ack_rec)
begin
if (doing_write | ~adr_set)
begin
rw_seq_state <= rw_seq_tx_adr ;
tx_shift_reg <= adr_i[ 7: 0] ;
send_bit <= 1'b1 ;
end
else
begin
rw_seq_state <= rw_seq_rx_byte ;
rec_bit <= 1'b1 ;
end
end
else if (nack_rec)
begin
no_ack_o <= 1'b1 ;
send_stop <= 1'b1 ;
end
end
else if (send_stop)
begin
no_ack_o <= 1'b0 ;
if (stop_sent)
begin
send_stop <= 1'b0 ;
rw_seq_state <= rw_seq_idle ;
end
end
end
rw_seq_tx_adr:
begin
if (send_bit)
begin
if (bit_sent)
begin
bits_transfered <= bits_transfered + 1'b1 ;
tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
end
if (bits_transfered == 'h8)
begin
send_bit <= 1'b0 ;
rec_ack <= 1'b1 ;
end
end
else if (rec_ack)
begin
bits_transfered <= 'h0 ;
if (ack_rec | nack_rec)
rec_ack <= 1'b0 ;
if (ack_rec)
begin
adr_set <= 1'b1 ;
if (doing_write)
begin
send_bit <= 1'b1 ;
rw_seq_state <= rw_seq_tx_byte ;
tx_shift_reg <= dat_i ;
end
else if (doing_read | doing_seq_read)
begin
send_start <= 1'b1 ;
rw_seq_state <= rw_seq_tx_ctrl ;
tx_shift_reg <= 8'b10100001 ;
end
end
else if (nack_rec)
begin
no_ack_o <= 1'b1 ;
send_stop <= 1'b1 ;
end
end
else if (send_stop)
begin
no_ack_o <= 1'b0 ;
if (stop_sent)
begin
send_stop <= 1'b0 ;
rw_seq_state <= rw_seq_idle ;
end
end
end
rw_seq_tx_byte:
begin
if (send_bit)
begin
if (bit_sent)
begin
bits_transfered <= bits_transfered + 1'b1 ;
tx_shift_reg <= {tx_shift_reg[6:0], tx_shift_reg[0]} ;
end
if (bits_transfered == 'h8)
begin
send_bit <= 1'b0 ;
rec_ack <= 1'b1 ;
end
end
else if (rec_ack)
begin
bits_transfered <= 'h0 ;
if (ack_rec | nack_rec)
begin
rec_ack <= 1'b0 ;
send_stop <= 1'b1 ;
end
if (nack_rec)
no_ack_o <= 1'b1 ;
if (ack_rec)
write_done_o <= 1'b1 ;
end
else if (send_stop)
begin
no_ack_o <= 1'b0 ;
write_done_o <= 1'b0 ;
if (stop_sent)
begin
send_stop <= 1'b0 ;
rw_seq_state <= rw_seq_idle ;
end
end
end
rw_seq_rx_byte:
begin
if (rec_bit)
begin
if (bit_rec)
begin
bits_transfered <= bits_transfered + 1'b1 ;
dat_o <= {dat_o[6:0], sda_i_reg} ;
end
if (bits_transfered == 'h8)
begin
rec_bit <= 1'b0 ;
dat_rdy_o <= 1'b1 ;
if (doing_read)
send_nack <= 1'b1 ;
else
send_ack <= 1'b1 ;
end
end
else if (send_nack)
begin
dat_rdy_o <= 1'b0 ;
bits_transfered <= 'h0 ;
if (nack_sent)
begin
send_stop <= 1'b1 ;
send_nack <= 1'b0 ;
end
end
else if (send_ack)
begin
dat_rdy_o <= 1'b0 ;
bits_transfered <= 'h0 ;
if (~do_seq_read_i)
begin
send_ack <= 1'b0 ;
send_nack <= 1'b1 ;
end
else if (ack_sent)
begin
send_ack <= 1'b0 ;
rec_bit <= 1'b1 ;
end
end
else if (send_stop)
begin
if (stop_sent)
begin
send_stop <= 1'b0 ;
rw_seq_state <= rw_seq_idle ;
end
end
end
endcase
end
end
endmodule // pci_spoci_ctrl |
module pci_par_crit
(
par_out,
par_out_in,
pci_cbe_en_in,
data_par_in,
pci_cbe_in
) ;
output par_out ;
input par_out_in,
pci_cbe_en_in,
data_par_in ;
input [3:0] pci_cbe_in ;
assign par_out = pci_cbe_en_in ? par_out_in : ( pci_cbe_in[3] ^ pci_cbe_in[2] ^ pci_cbe_in[1] ^ pci_cbe_in[0] ^ data_par_in) ;
endmodule |
module pci_frame_en_crit
(
pci_frame_en_out,
frame_en_slow_in,
frame_en_keep_in,
pci_stop_in,
pci_trdy_in
) ;
output pci_frame_en_out ;
input frame_en_slow_in,
frame_en_keep_in,
pci_stop_in,
pci_trdy_in ;
assign pci_frame_en_out = frame_en_slow_in || frame_en_keep_in && pci_stop_in && pci_trdy_in ;
endmodule |
module pci_pciw_fifo_control
(
rclock_in,
wclock_in,
renable_in,
wenable_in,
reset_in,
almost_full_out,
full_out,
almost_empty_out,
empty_out,
waddr_out,
raddr_out,
rallow_out,
wallow_out,
three_left_out,
two_left_out
);
parameter ADDR_LENGTH = 7 ;
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input rclock_in, wclock_in;
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
// write address changes on rising edge of wclock_in when writes are allowed
input renable_in, wenable_in;
// reset input
input reset_in;
// almost full and empy status outputs
output almost_full_out, almost_empty_out;
// full and empty status outputs
output full_out, empty_out;
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
// read and write allow outputs
output rallow_out, wallow_out ;
// three and two locations left output indicator
output three_left_out ;
output two_left_out ;
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
reg [(ADDR_LENGTH - 1):0] waddr_plus1;
assign waddr_out = waddr ;
// grey code registers
// grey code pipeline for write address
reg [(ADDR_LENGTH - 1):0] wgrey_minus1 ; // previous
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
reg [(ADDR_LENGTH - 1):0] wgrey_next_plus1 ; // next plus 1
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next_plus1 = waddr_plus1[(ADDR_LENGTH - 1):1] ^ waddr_plus1[(ADDR_LENGTH - 2):0] ;
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
// write allow - writes are allowed when fifo is not full
assign wallow_out = wenable_in & ~full_out ;
// clear generation for FFs and registers
wire clear = reset_in ;
//rallow generation
assign rallow_out = renable_in & ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
// read address mux - when read is performed, next address is driven, so next data is available immediately after read
// this is convenient for zero wait stait bursts
assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
raddr_plus_one <= #`FF_DELAY 5 ;
raddr <= #`FF_DELAY 4 ;
// raddr_plus_one <= #`FF_DELAY 6 ;
// raddr <= #`FF_DELAY 5 ;
end
else if (rallow_out)
begin
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
raddr <= #`FF_DELAY raddr_plus_one ;
end
end
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 4 Grey addresses:
- rgrey_minus2 is Grey Code of address two before current address
- rgrey_minus1 is Grey Code of address one before current address
- rgrey_addr is Grey Code of current read address
- rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in read clock domain
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
rgrey_minus2 <= #1 0 ;
rgrey_minus1 <= #`FF_DELAY 1 ;
rgrey_addr <= #1 3 ;
rgrey_next <= #`FF_DELAY 2 ;
end
else
if (rallow_out)
begin
rgrey_minus2 <= #1 rgrey_minus1 ;
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
rgrey_addr <= #1 rgrey_next ;
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
end
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and 3 Grey Code Registers:
- wgrey_minus1 represents previous Grey coded write address
- wgrey_addr represents current Grey Coded write address
- wgrey_next represents next Grey Coded write address
- wgrey_next_plus1 represents second next Grey Coded write address
----------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in write clock domain
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wgrey_minus1 <= #`FF_DELAY 1 ;
wgrey_addr <= #`FF_DELAY 3 ;
wgrey_next <= #`FF_DELAY 2 ;
wgrey_next_plus1 <= #`FF_DELAY 6;
end
else
if (wallow_out)
begin
wgrey_minus1 <= #`FF_DELAY wgrey_addr ;
wgrey_addr <= #`FF_DELAY wgrey_next ;
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
// wgrey_next <= #`FF_DELAY wgrey_next_plus1 ;
wgrey_next_plus1 <= #`FF_DELAY {waddr_plus1[(ADDR_LENGTH - 1)], calc_wgrey_next_plus1} ;
end
end
// write address counter - nothing special except initial value
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
// initial value 5
waddr <= #`FF_DELAY 4 ;
waddr_plus1 <= #`FF_DELAY 5 ;
end
else
if (wallow_out)
begin
waddr <= #`FF_DELAY waddr + 1'b1 ;
waddr_plus1 <= #`FF_DELAY waddr_plus1 + 1'b1 ;
end
end
/*------------------------------------------------------------------------------------------------------------------------------
Gray coded address of read address decremented by two is synchronized to write clock domain and compared to:
- previous grey coded write address - if they are equal, the fifo is full
- gray coded write address. If they are equal, fifo is almost full.
- grey coded next write address. If they are equal, the fifo has two free locations left.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus2 ;
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_minus2 ;
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus2
(
.data_in (rgrey_minus2),
.clk_out (wclock_in),
.sync_data_out (wclk_sync_rgrey_minus2),
.async_reset (clear)
) ;
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wclk_rgrey_minus2 <= #`FF_DELAY 0 ;
end
else
begin
wclk_rgrey_minus2 <= #`FF_DELAY wclk_sync_rgrey_minus2 ;
end
end
assign full_out = (wgrey_minus1 == wclk_rgrey_minus2) ;
assign almost_full_out = (wgrey_addr == wclk_rgrey_minus2) ;
assign two_left_out = (wgrey_next == wclk_rgrey_minus2) ;
assign three_left_out = (wgrey_next_plus1 == wclk_rgrey_minus2) ;
/*------------------------------------------------------------------------------------------------------------------------------
Empty control:
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
If they are equal, fifo is empty.
Almost empty control:
Synchronized write pointer is also compared to Gray coded next read address. If these two are
equal, fifo is almost empty.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_addr
(
.data_in (wgrey_addr),
.clk_out (rclock_in),
.sync_data_out (rclk_sync_wgrey_addr),
.async_reset (clear)
) ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
rclk_wgrey_addr <= #`FF_DELAY 3 ;
else
rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
end
assign almost_empty_out = (rgrey_next == rclk_wgrey_addr) ;
assign empty_out = (rgrey_addr == rclk_wgrey_addr) ;
endmodule |
module pci_wb_addr_mux
(
`ifdef REGISTER_WBS_OUTPUTS
clk_in,
reset_in,
sample_address_in,
`endif
address_in,
bar0_in,
bar1_in,
bar2_in,
bar3_in,
bar4_in,
bar5_in,
am0_in,
am1_in,
am2_in,
am3_in,
am4_in,
am5_in,
ta0_in,
ta1_in,
ta2_in,
ta3_in,
ta4_in,
ta5_in,
at_en_in,
hit_out,
address_out
);
input [31:0] address_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] bar5_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] am5_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta0_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta1_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta2_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta3_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta4_in ;
input [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] ta5_in ;
input [5:0] at_en_in ;
output [5:0] hit_out ;
output [31:0] address_out ;
reg [31:0] address_out ;
wire [31:0] addr0 ;
wire [31:0] addr1 ;
wire [31:0] addr2 ;
wire [31:0] addr3 ;
wire [31:0] addr4 ;
wire [31:0] addr5 ;
wire [5:0] hit ;
assign hit_out = hit ;
`ifdef REGISTER_WBS_OUTPUTS
input clk_in, reset_in, sample_address_in ;
reg [31:0] address ;
always@(posedge clk_in or posedge reset_in)
begin
if ( reset_in )
address <= #`FF_DELAY 0 ;
else
if ( sample_address_in )
address <= #`FF_DELAY address_in ;
end
`else
wire [31:0] address = address_in ;
`endif
`ifdef GUEST
`ifdef NO_CNF_IMAGE
`else
`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
`endif
`else
`ifdef HOST
`define PCI_WB_ADDR_MUX_DEC0_INCLUDE
`endif
`endif
`ifdef PCI_WB_ADDR_MUX_DEC0_INCLUDE
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec0
(
.hit (hit[0]),
.addr_out (addr0),
.addr_in (address),
.base_addr (bar0_in),
.mask_addr (am0_in),
.tran_addr (ta0_in),
.at_en (1'b0)
) ;
`else
// configuration image not implemented
assign hit[0] = 1'b0 ;
assign addr0 = 32'h0000_0000 ;
`endif
// one image is always implemented
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec1
(
.hit (hit[1]),
.addr_out (addr1),
.addr_in (address),
.base_addr (bar1_in),
.mask_addr (am1_in),
.tran_addr (ta1_in),
.at_en (at_en_in[1])
) ;
`ifdef WB_IMAGE2
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec2
(
.hit (hit[2]),
.addr_out (addr2),
.addr_in (address),
.base_addr (bar2_in),
.mask_addr (am2_in),
.tran_addr (ta2_in),
.at_en (at_en_in[2])
) ;
`else
assign hit[2] = 1'b0 ;
assign addr2 = 0 ;
`endif
`ifdef WB_IMAGE3
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec3
(
.hit (hit[3]),
.addr_out (addr3),
.addr_in (address),
.base_addr (bar3_in),
.mask_addr (am3_in),
.tran_addr (ta3_in),
.at_en (at_en_in[3])
) ;
`else
assign hit[3] = 1'b0 ;
assign addr3 = 0 ;
`endif
`ifdef WB_IMAGE4
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec4
(
.hit (hit[4]),
.addr_out (addr4),
.addr_in (address),
.base_addr (bar4_in),
.mask_addr (am4_in),
.tran_addr (ta4_in),
.at_en (at_en_in[4])
) ;
`else
assign hit[4] = 1'b0 ;
assign addr4 = 0 ;
`endif
`ifdef WB_IMAGE5
pci_wb_decoder #(`WB_NUM_OF_DEC_ADDR_LINES) dec5
(
.hit (hit[5]),
.addr_out (addr5),
.addr_in (address),
.base_addr (bar5_in),
.mask_addr (am5_in),
.tran_addr (ta5_in),
.at_en (at_en_in[5])
) ;
`else
assign hit[5] = 1'b0 ;
assign addr5 = 0 ;
`endif
// address multiplexer
always@
(
hit or
addr0 or
addr1 or
addr2 or
addr3 or
addr4 or
addr5
)
begin
case ( {hit[5:2], hit[0]} )
5'b0_0_0_0_1: address_out = addr0 ;
5'b0_0_0_1_0: address_out = addr2 ;
5'b0_0_1_0_0: address_out = addr3 ;
5'b0_1_0_0_0: address_out = addr4 ;
5'b1_0_0_0_0: address_out = addr5 ;
// default address is address from decoder 1 - it is always implemented - in case of stripped down core to only one image
// this multiplexer can be completely removed during synthesys
default: address_out = addr1 ;
endcase
end
endmodule |
module pci_perr_crit
(
perr_out,
perr_n_out,
non_critical_par_in,
pci_par_in,
perr_generate_in
) ;
output perr_out,
perr_n_out;
input non_critical_par_in,
pci_par_in,
perr_generate_in ;
assign perr_out = (non_critical_par_in ^ pci_par_in) && perr_generate_in ;
assign perr_n_out = ~perr_out ;
endmodule |
module pci_master32_sm_if
(
clk_in,
reset_in,
// interconnect to pci master state machine
address_out,
bc_out,
data_out,
data_in,
be_out,
req_out,
rdy_out,
last_out,
next_data_out,
next_be_out,
next_last_out,
// status inputs from master SM
wait_in,
wtransfer_in,
rtransfer_in,
retry_in,
rerror_in,
first_in ,
mabort_in,
// WISHBONE WRITE fifo inputs and outputs
wbw_renable_out,
wbw_fifo_addr_data_in,
wbw_fifo_cbe_in,
wbw_fifo_control_in,
wbw_fifo_empty_in,
wbw_fifo_transaction_ready_in,
// WISHBONE READ fifo inputs and outputs
wbr_fifo_wenable_out,
wbr_fifo_data_out,
wbr_fifo_be_out,
wbr_fifo_control_out,
// delayed transaction control logic inputs and outputs
del_wdata_in,
del_complete_out,
del_req_in,
del_addr_in,
del_bc_in,
del_be_in,
del_burst_in,
del_error_out,
del_rty_exp_out,
del_we_in,
// configuration space interconnect
// error reporting
err_addr_out,
err_bc_out,
err_signal_out,
err_source_out,
err_rty_exp_out,
cache_line_size_in,
// two signals for pci control and status
mabort_received_out,
tabort_received_out,
posted_write_not_present_out
);
// system inputs
input clk_in ;
input reset_in ;
// PCI master state machine interconnect
output [31:0] address_out ; // address output
output [3:0] bc_out ; // bus command output
reg [3:0] bc_out ;
output [31:0] data_out ; // data output for writes
reg [31:0] data_out ;
input [31:0] data_in ; // data input for reads
output [3:0] be_out ; // byte enable output
reg [3:0] be_out ;
output req_out ; // request output
output rdy_out ; // ready output
reg rdy_out ;
output last_out ; // last data indicator output
output [31:0] next_data_out ; // next data output
output [3:0] next_be_out ; // next byte enable output
output next_last_out ; // next transfer last indicator
input wait_in,
wtransfer_in,
rtransfer_in,
retry_in,
rerror_in,
first_in ,
mabort_in ;
// WISHBONE write fifo interconnect
output wbw_renable_out ; // WBW_FIFO read enable signal
input [31:0] wbw_fifo_addr_data_in ; // WBW_FIFO address/data bus
input [3:0] wbw_fifo_cbe_in ; // WBW_FIFO command/byte enable bus
input [3:0] wbw_fifo_control_in ; // WBW_FIFO control bus
input wbw_fifo_empty_in ; // WBW_FIFO's empty status indicator
input wbw_fifo_transaction_ready_in ; // WBW_FIFO transaction ready indicator
// WISHBONE read FIFO interconnect
output wbr_fifo_wenable_out ; // write enable for WBR_FIFO
output [31:0] wbr_fifo_data_out ; // data output to WBR_FIFO
output [3:0] wbr_fifo_be_out ; // byte enable output for WBR_FIFO
output [3:0] wbr_fifo_control_out ; // WBR_FIFO control output
// delayed transaction control logic inputs and outputs
input [31:0] del_wdata_in ; // delayed write data input
output del_complete_out ; // delayed transaction completed output
input del_req_in ; // delayed transaction request
input [31:0] del_addr_in ; // delayed transaction address
input [3:0] del_bc_in ; // delayed transaction bus command input
input [3:0] del_be_in ; // delayed transaction byte enables input
input del_burst_in ; // delayed transaction burst req. indicator
output del_error_out ; // delayed transation error termination signal
output del_rty_exp_out ; // retry expired output for delayed transactions
input del_we_in ; // delayed write request indicator
output [31:0] err_addr_out ; // erroneous address output
output [3:0] err_bc_out ; // erroneous bus command output
output err_signal_out ; // error signalization
output err_source_out ; // error source indicator
input [7:0] cache_line_size_in ; // cache line size value input
output err_rty_exp_out ; // retry expired error output
output mabort_received_out ; // master abort signaled to status register
output tabort_received_out ; // target abort signaled to status register
output posted_write_not_present_out ; // used in target state machine - must deny read completions when this signal is 0
assign err_bc_out = bc_out ;
// assign read outputs
/*==================================================================================================================
WISHBONE read FIFO data outputs - just link them to SM data outputs and delayed BE input
==================================================================================================================*/
assign wbr_fifo_data_out = data_in ;
assign wbr_fifo_be_out = del_be_in ;
// decode if current bus command is configuration command
wire conf_cyc_bc = ( bc_out[3:1] == `BC_CONF_RW ) ;
// register for indicating that current data is also last in transfer
reg current_last ;
// register indicating that last data was transfered OK
reg last_transfered ;
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
last_transfered <= #`FF_DELAY 1'b0 ;
else
last_transfered <= #`FF_DELAY ~wait_in && last_out && wtransfer_in ;
end
// status signals output assignement
assign mabort_received_out = mabort_in ;
wire tabort_ff_in = ~wait_in && rerror_in ;
reg tabort_received_out ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
tabort_received_out <= #`FF_DELAY 1'b0 ;
else
tabort_received_out <= #`FF_DELAY tabort_ff_in ;
end
// error recovery indicator
reg err_recovery ;
// operation is locked until error recovery is in progress or error bit is not cleared in configuration space
wire err_lock = err_recovery ;
// three requests are possible - posted write, delayed write and delayed read
reg del_write_req ;
reg posted_write_req ;
reg del_read_req ;
// assign request output
assign req_out = del_write_req || posted_write_req || del_read_req ;
// posted write is not present, when WB Write Fifo is empty and posted write transaction is not beeing requested at present time
assign posted_write_not_present_out = !posted_write_req && wbw_fifo_empty_in ;
// write requests are staged, so data is read from source into current data register and next data register
reg write_req_int ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
write_req_int <= #`FF_DELAY 1'b0 ;
else
write_req_int <= #`FF_DELAY posted_write_req || del_write_req ;
end
// ready output is generated one clock after request for reads and two after for writes
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
rdy_out <= #`FF_DELAY 1'b0 ;
else
rdy_out <= #`FF_DELAY del_read_req || ( (posted_write_req || del_write_req) && write_req_int) ;
end
// wires with logic used as inputs to request FFs
wire do_posted_write = ( wbw_fifo_transaction_ready_in && ~wbw_fifo_empty_in && ~err_lock ) ;
wire do_del = ( del_req_in && ~err_lock && wbw_fifo_empty_in ) ;
wire do_del_write = do_del && del_we_in ;
wire do_del_read = do_del && ~del_we_in ;
// register for indicating current operation's data source
parameter DELAYED_WRITE = 1'b1 ;
parameter POSTED_WRITE = 1'b0 ;
// new data source - depending on which transaction will be processed next - delayed read is here because source of byte enables must
// be specified for delayed reads also - data source is not relevant for delayed reads, so value is don't care anyway
wire new_data_source = (do_del_write || do_del_read) ? DELAYED_WRITE : POSTED_WRITE ; // input to data source register
wire data_source_change = ~req_out ; // change (enable) for data source register - when no requests are in progress
reg data_source ; // data source value
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
// default value is posted write source - wbw_fifo
data_source <= #`FF_DELAY POSTED_WRITE ;
else
if (data_source_change)
// change data source on rising clock edge
data_source <= #`FF_DELAY new_data_source ;
end
// multiplexer for data output to PCI MASTER state machine
reg [31:0] source_data ;
reg [3:0] source_be ;
always@(data_source or wbw_fifo_addr_data_in or wbw_fifo_cbe_in or del_wdata_in or del_be_in or del_burst_in)
begin
case (data_source)
POSTED_WRITE: begin
source_data = wbw_fifo_addr_data_in ;
source_be = wbw_fifo_cbe_in ;
end
DELAYED_WRITE: begin
source_data = del_wdata_in ;
// read all bytes during delayed burst read!
source_be = ~( del_be_in | {4{del_burst_in}} ) ;
end
endcase
end
wire waddr = wbw_fifo_control_in[`ADDR_CTRL_BIT] ;
// address change indicator - address is allowed to be loaded only when no transaction is in progress!
wire address_change = ~req_out ; // address change - whenever there is no request in progress
// new address - input to register storing address of current request - if posted write request will be next,
// load address and bus command from wbw_fifo, else load data from delayed transaction logic
wire [31:0] new_address = ( ~req_out && do_posted_write ) ? wbw_fifo_addr_data_in[31:0] : del_addr_in[31:0] ;
wire [3:0] new_bc = ( ~req_out && do_posted_write ) ? wbw_fifo_cbe_in : del_bc_in ;
// address counter enable - only for posted writes when data is actually transfered
wire addr_count_en = !wait_in && posted_write_req && rtransfer_in ;
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
bc_out <= #`FF_DELAY `BC_RESERVED0 ;
else
if (address_change)
bc_out <= #`FF_DELAY new_bc ;
end
reg [29:0] current_dword_address ;
// DWORD address counter with load
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
current_dword_address <= #`FF_DELAY 30'h0000_0000 ;
else
if (address_change)
current_dword_address <= #`FF_DELAY new_address[31:2] ;
else
if (addr_count_en)
current_dword_address <= #`FF_DELAY current_dword_address + 1'b1 ;
end
reg [1:0] current_byte_address ;
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
current_byte_address <= #`FF_DELAY 2'b00 ;
else
if (address_change)
current_byte_address <= #`FF_DELAY new_address[1:0] ;
end
// byte address generation logic
reg [ 1: 0] generated_byte_adr ;
reg [ 1: 0] pci_byte_adr ;
always@(be_out)
begin
casex(be_out)
4'bxxx0:generated_byte_adr = 2'b00 ;
4'bxx01:generated_byte_adr = 2'b01 ;
4'bx011:generated_byte_adr = 2'b10 ;
4'b0111:generated_byte_adr = 2'b11 ;
4'b1111:generated_byte_adr = 2'b00 ;
endcase
end
always@(generated_byte_adr or bc_out or current_byte_address)
begin
// for memory access commands, set lower 2 address bits to 0
if ((bc_out == `BC_MEM_READ) | (bc_out == `BC_MEM_WRITE) |
(bc_out == `BC_MEM_READ_MUL) | (bc_out == `BC_MEM_READ_LN) |
(bc_out == `BC_MEM_WRITE_INVAL))
begin
pci_byte_adr = 2'b00 ;
end
else if ((bc_out == `BC_IO_WRITE) | (bc_out == `BC_IO_READ))
begin
pci_byte_adr = generated_byte_adr ;
end
else
begin
pci_byte_adr = current_byte_address ;
end
end
// address output to PCI master state machine assignment
assign address_out = { current_dword_address, pci_byte_adr } ;
// the same for erroneous address assignement
assign err_addr_out = { current_dword_address, pci_byte_adr } ;
// cacheline size counter - for read transaction length control
// cache line count is enabled during burst reads when data is actually transfered
wire read_count_enable = ~wait_in && del_read_req && del_burst_in && wtransfer_in ;
// cache line counter is loaded when del read request is not in progress
wire read_count_load = ~del_read_req ;
reg [(`WBR_ADDR_LENGTH - 1):0] max_read_count ;
always@(cache_line_size_in or del_bc_in)
begin
if ( (cache_line_size_in >= `WBR_DEPTH) || (~del_bc_in[1] && ~del_bc_in[0]) )
max_read_count = `WBR_DEPTH - 1'b1;
else
max_read_count = cache_line_size_in ;
end
reg [(`WBR_ADDR_LENGTH - 1):0] read_count ;
// cache line bound indicator - it signals when data for one complete cacheline was read
wire read_bound_comb = ~|(read_count[(`WBR_ADDR_LENGTH - 1):2]) ;
reg read_bound ;
always@(posedge clk_in or posedge reset_in)
begin
if ( reset_in )
read_bound <= #`FF_DELAY 1'b0 ;
else if (read_count_load)
read_bound <= #`FF_DELAY 1'b0 ;
else if ( read_count_enable )
read_bound <= #`FF_DELAY read_bound_comb ;
end
wire read_count_change_val = read_count_load | read_count_enable ;
wire [(`WBR_ADDR_LENGTH - 1):0] read_count_next = read_count_load ? max_read_count : (read_count - 1'b1) ;
// down counter with load
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
read_count <= #`FF_DELAY 0 ;
else
/* if (read_count_load)
read_count <= #`FF_DELAY max_read_count ;
else
if (read_count_enable)
read_count <= #`FF_DELAY read_count - 1'b1 ;
*/ if (read_count_change_val)
read_count <= #`FF_DELAY read_count_next ;
end
// flip flop indicating error recovery is in progress
reg err_recovery_in ;
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
err_recovery <= #`FF_DELAY 1'b0 ;
else
err_recovery <= #`FF_DELAY err_recovery_in ;
end
/*// retry counter implementation
reg [7:0] retry_count ;
wire retry_expired = ~|(retry_count[7:1]) ;
// loading of retry counter - whenever no request is present or other termination than retry or wait is signalled
wire retry_load = ~req_out || (~wait_in && rtransfer_in) ;
// retry DOWN counter with load
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
retry_count <= #`FF_DELAY 8'hFF ;
else
if ( retry_load )
retry_count <= #`FF_DELAY `PCI_RTY_CNT_MAX ;
else
if (retry_in)
retry_count <= #`FF_DELAY retry_count - 1'b1 ;
end*/
/*==================================================================================================================
Delayed write requests are always single transfers!
Delayed write request starts, when no request is currently beeing processed and it is signaled from other side
of the bridge.
==================================================================================================================*/
// delayed write request FF input control
reg del_write_req_input ;
always@(
do_del_write or
del_write_req or
posted_write_req or
del_read_req or
wait_in or
//retry_in or
//retry_expired or
rtransfer_in or
rerror_in or
mabort_in
)
begin
if (~del_write_req)
begin
// delayed write is not in progress and is requested
// delayed write can be requested when no other request is in progress
del_write_req_input = ~posted_write_req && ~del_read_req && do_del_write ;
end
else
begin
// delayed write request is in progress - assign input
del_write_req_input = wait_in ||
( /*~( retry_in && retry_expired) &&*/
~rtransfer_in && ~rerror_in && ~mabort_in
);
end
end
// delayed write request FLIP-FLOP
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
del_write_req <= #`FF_DELAY 1'b0 ;
else
del_write_req <= #`FF_DELAY del_write_req_input ;
end
/*================================================================================================
Posted write request indicator.
Posted write starts whenever no request is in progress and one whole posted write is
stored in WBW_FIFO. It ends on error terminations ( master, target abort, retry expired) or
data transfer terminations if last data is on top of FIFO.
Continues on wait, retry, and disconnect without data.
================================================================================================*/
// posted write request FF input control
reg posted_write_req_input ;
always@(
do_posted_write or
del_write_req or
posted_write_req or
del_read_req or
wait_in or
//retry_in or
rerror_in or
mabort_in or
//retry_expired or
rtransfer_in or
last_transfered
)
begin
if (~posted_write_req)
begin
// posted write is not in progress
posted_write_req_input = ~del_write_req && ~del_read_req && do_posted_write ;
end
else
begin
posted_write_req_input = wait_in ||
(/*~(retry_in && retry_expired && ~rtransfer_in) &&*/
~rerror_in && ~mabort_in &&
~(last_transfered)
) ;
end
end
// posted write request flip flop
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
posted_write_req <= #`FF_DELAY 1'b0 ;
else
posted_write_req <= #`FF_DELAY posted_write_req_input ;
end
/*================================================================================================
Delayed read request indicator.
Delayed read starts whenever no request is in progress and delayed read request is signaled from
other side of bridge. It ends on error terminations ( master, target abort, retry expired) or
data transfer terminations if it is not burst transfer or on cache line bounds on burst transfer.
It also ends on disconnects.
Continues on wait and retry.
================================================================================================*/
// delayed read FF input control
reg del_read_req_input ;
always@(
do_del_read or
del_write_req or
posted_write_req or
del_read_req or
last_transfered or
wait_in or
retry_in or
//retry_expired or
mabort_in or
rtransfer_in or
rerror_in or
first_in or
del_complete_out
)
begin
if (~del_read_req)
begin
del_read_req_input = ~del_write_req && ~posted_write_req && ~del_complete_out && do_del_read ;
end
else
begin
del_read_req_input = wait_in ||
( ~(retry_in && (~first_in /*|| retry_expired */)) &&
~mabort_in && ~rerror_in &&
~(last_transfered)
) ;
end
end
// delayed read request FF
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
del_read_req <= #`FF_DELAY 1'b0 ;
else
del_read_req <= #`FF_DELAY del_read_req_input ;
end
// wire indicating last entry of transaction on top of fifo
wire wlast = wbw_fifo_control_in[`LAST_CTRL_BIT] ;
wire last_int = posted_write_req && wlast || del_write_req ;
// intermidiate data, byte enable and last registers
reg [31:0] intermediate_data ;
reg [3:0] intermediate_be ;
reg intermediate_last ;
wire intermediate_enable = ( posted_write_req || del_write_req ) && ( ~write_req_int || (( ~rdy_out || ~wait_in && rtransfer_in ) && ~intermediate_last)) ;
always@(posedge reset_in or posedge clk_in)
begin
if ( reset_in )
begin
intermediate_data <= #`FF_DELAY 32'h0000_0000 ;
intermediate_be <= #`FF_DELAY 4'h0 ;
intermediate_last <= #`FF_DELAY 1'b0 ;
end
else
if ( intermediate_enable )
begin
intermediate_data <= #`FF_DELAY source_data ;
intermediate_be <= #`FF_DELAY source_be ;
intermediate_last <= #`FF_DELAY last_int ;
end
end
// multiplexer for next data
reg [31:0] next_data_out ;
reg [3:0] next_be_out ;
reg write_next_last ;
reg [3:0] write_next_be ;
always@
(
rtransfer_in or
intermediate_data or
intermediate_be or
intermediate_last or
wbw_fifo_addr_data_in or
wbw_fifo_cbe_in or
wlast or
wait_in
)
begin
if( rtransfer_in & ~wait_in )
begin
next_data_out = wbw_fifo_addr_data_in ;
write_next_last = wlast ;
write_next_be = wbw_fifo_cbe_in ;
end
else
begin
next_data_out = intermediate_data ;
write_next_last = intermediate_last ;
write_next_be = intermediate_be ;
end
end
always@(del_read_req or source_be or write_next_be)
begin
if (del_read_req)
next_be_out = source_be ;
else
next_be_out = write_next_be ;
end
/*================================================================================================
WBW_FIFO read enable - read from WBW_FIFO is performed on posted writes, when data transfer
termination is received - transfer or disconnect with data. Reads are enabled during error
recovery also, since erroneous transaction must be pulled out of FIFO!
================================================================================================*/
// wbw_fifo read enable input control
assign wbw_renable_out = ~req_out && (do_posted_write || err_recovery) ||
posted_write_req && ( ~write_req_int || (~rdy_out && ~intermediate_last) || (~wait_in && rtransfer_in && ~intermediate_last)) ;
/*================================================================================================
WBR_FIFO write enable control -
writes to FIFO are possible only when delayed read request is in progress and data transfer
or error termination is signalled. It is not enabled on retry or disconnect without data.
================================================================================================*/
// wbr_fifo write enable control - enabled when transfer is in progress and data is transfered or error is signalled
assign wbr_fifo_wenable_out = del_read_req && ~wait_in && ( rtransfer_in || mabort_in || rerror_in ) ;
/*================================================================================================
WBR_FIFO control output for identifying data entries.
This is necesary because of prefetched reads, which partially succeed. On error, error entry
gets in to signal it on WISHBONE bus if WISHBONE master reads up to this entry.
================================================================================================*/
assign wbr_fifo_control_out[`ADDR_CTRL_BIT] = 1'b0 ;
assign wbr_fifo_control_out[`LAST_CTRL_BIT] = last_transfered ;
assign wbr_fifo_control_out[`DATA_ERROR_CTRL_BIT] = rerror_in || (mabort_in && ~conf_cyc_bc) ;
assign wbr_fifo_control_out[`UNUSED_CTRL_BIT] = 1'b0 ;
// retry expired error for posted writes control
//assign err_rty_exp_out = posted_write_req && ~wait_in && retry_in && retry_expired && ~rtransfer_in;
assign err_rty_exp_out = 1'b0 ;
// error source and error signal output control logic - only for posted writes
assign err_source_out = mabort_in /*|| err_rty_exp_out*/ ;
assign err_signal_out = /*err_rty_exp_out || */ posted_write_req && ~wait_in && (mabort_in || rerror_in) ;
//assign del_rty_exp_out = (~wait_in && (del_read_req || del_write_req)) && (retry_in && retry_expired && ~rtransfer_in) ;
assign del_rty_exp_out = 1'b0 ;
assign del_error_out = ~wait_in && (del_write_req || del_read_req) && ( (mabort_in && ~conf_cyc_bc) || rerror_in ) ;
wire del_write_complete = del_write_req && ~wait_in && ( rtransfer_in || rerror_in || mabort_in ) ;
wire del_read_complete = del_read_req && ~wait_in && ( rerror_in || mabort_in || last_transfered || ( retry_in && ~first_in ) ) ;
assign del_complete_out = ~wait_in && ( del_write_complete || del_read_complete ) ;
// next last output generation
assign next_last_out = del_write_req || del_read_req && ( ~del_burst_in || read_bound ) || posted_write_req && ( write_next_last ) ;
/*==================================================================================================================
Error recovery FF gets a value of one, when during posted write error occurs. It is cleared when all the data provided
for erroneous transaction is pulled out of WBW_FIFO
==================================================================================================================*/
// error recovery flip flop input - used when posted write is terminated with an error
always@(
err_recovery or
last_out or
wlast or
err_signal_out or
intermediate_last
)
begin
// when error recovery is not set - drive its input so it gets set
if ( ~err_recovery )
err_recovery_in = ~last_out && ~intermediate_last && err_signal_out ;
else
// when error recovery is set, wbw_fifo is enabled - clear err_recovery when last data entry of erroneous transaction is pulled out of fifo
err_recovery_in = ~wlast ;
end
wire data_out_load = (posted_write_req || del_write_req) && ( !rdy_out || ( !wait_in && rtransfer_in ) ) ;
wire be_out_load = (req_out && !rdy_out) || ( posted_write_req && !wait_in && rtransfer_in ) ;
wire last_load = req_out && ( ~rdy_out || ~wait_in && wtransfer_in ) ;
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
data_out <= #`FF_DELAY 32'h0000_0000 ;
else
if ( data_out_load )
data_out <= #`FF_DELAY intermediate_data ;
end
always@(posedge clk_in or posedge reset_in)
begin
if ( reset_in )
be_out <= #`FF_DELAY 4'hF ;
else
if ( be_out_load )
be_out <= #`FF_DELAY posted_write_req ? intermediate_be : source_be ;
end
always@(posedge reset_in or posedge clk_in)
begin
if (reset_in)
current_last <= #`FF_DELAY 1'b0 ;
else
if ( last_load )
current_last <= #`FF_DELAY next_last_out ;
end
assign last_out = current_last ;
endmodule |
module pci_target32_clk_en
(
addr_phase,
config_access,
addr_claim_in,
pci_frame_in,
state_wait,
state_transfere,
state_default,
clk_enable
);
input addr_phase ; // indicates registered address phase on PCI bus
input config_access ; // indicates configuration access
input addr_claim_in ; // indicates claimed input PCI address
input pci_frame_in ; // critical constrained input signal
input state_wait ; // indicates WAIT state of FSM
input state_transfere ; // indicates TRANSFERE state of FSM
input state_default ; // indicates DEFAULT state of FSM
output clk_enable ; // FSM clock enable output
// clock enable signal when FSM is in IDLE state
wire s_idle_clk_en = ((addr_phase && config_access) ||
(addr_phase && ~config_access && addr_claim_in)) ;
// clock enable signal when FSM is in WAIT state or in DEFAULT state
wire s_wait_clk_en = (state_wait || state_default) ;
// clock enable signal when FSM is in TRANSFERE state
wire s_tran_clk_en = (state_transfere && pci_frame_in) ;
// Clock enable signal for FSM with preserved hierarchy for minimum delay!
assign clk_enable = (s_idle_clk_en || s_wait_clk_en || s_tran_clk_en) ;
endmodule |
module pci_pcir_fifo_control
(
rclock_in,
wclock_in,
renable_in,
wenable_in,
reset_in,
flush_in,
full_out,
almost_empty_out,
empty_out,
waddr_out,
raddr_out,
rallow_out,
wallow_out
);
// address length parameter - depends on fifo depth
parameter ADDR_LENGTH = 7 ;
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
input rclock_in, wclock_in;
// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
// write address changes on rising edge of wclock_in when writes are allowed
input renable_in, wenable_in;
// reset input
input reset_in;
// flush input
input flush_in ;
// almost empy status output
output almost_empty_out;
// full and empty status outputs
output full_out, empty_out;
// read and write addresses outputs
output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
// read and write allow outputs
output rallow_out, wallow_out ;
// read address register
reg [(ADDR_LENGTH - 1):0] raddr ;
// write address register
reg [(ADDR_LENGTH - 1):0] waddr;
assign waddr_out = waddr ;
// grey code registers
// grey code pipeline for write address
reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
// next write gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
// grey code pipeline for read address
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
// next read gray address calculation - bitwise xor between address and shifted address
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
// FFs for registered empty and full flags
wire empty ;
wire full ;
// almost_empty tag
wire almost_empty ;
// write allow wire - writes are allowed when fifo is not full
wire wallow = wenable_in && !full ;
// write allow output assignment
assign wallow_out = wallow ;
// read allow wire
wire rallow ;
// full output assignment
assign full_out = full ;
// clear generation for FFs and registers
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
assign empty_out = empty ;
//rallow generation
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
// rallow output assignment
assign rallow_out = rallow ;
// almost empty output assignment
assign almost_empty_out = almost_empty ;
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
// address output mux - when FIFO is not read, current actual address is driven out, when it is read, next address is driven out to provide
// next data immediately
// done for zero wait state burst operation
assign raddr_out = rallow ? raddr_plus_one : raddr ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
raddr_plus_one <= #`FF_DELAY 3 ;
raddr <= #`FF_DELAY 2 ;
end
else if (flush_in)
begin
raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ;
raddr <= #`FF_DELAY waddr ;
end
else if (rallow)
begin
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
raddr <= #`FF_DELAY raddr_plus_one ;
end
end
/*-----------------------------------------------------------------------------------------------
Read address control consists of Read address counter and Grey Address pipeline
There are 2 Grey addresses:
- rgrey_addr is Grey Code of current read address
- rgrey_next is Grey Code of next read address
--------------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in read clock domain
always@(posedge rclock_in or posedge clear)
begin
if (clear)
begin
rgrey_addr <= #1 0 ;
rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
end
else if (flush_in)
begin
// when fifo is flushed, load the register values from the write clock domain.
// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
rgrey_addr <= #1 wgrey_addr ;
rgrey_next <= #`FF_DELAY wgrey_next ;
end
else if (rallow)
begin
// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
rgrey_addr <= #1 rgrey_next ;
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
end
end
/*--------------------------------------------------------------------------------------------
Write address control consists of write address counter and 2 Grey Code Registers:
- wgrey_addr represents current Grey Coded write address
- wgrey_next represents Grey Coded next write address
----------------------------------------------------------------------------------------------*/
// grey coded address pipeline for status generation in write clock domain
always@(posedge wclock_in or posedge clear)
begin
if (clear)
begin
wgrey_addr <= #1 0 ;
wgrey_next <= #`FF_DELAY 1 ;
end
else
if (wallow)
begin
wgrey_addr <= #1 wgrey_next ;
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
end
end
// write address binary counter - nothing special except initial value
always@(posedge wclock_in or posedge clear)
begin
if (clear)
// initial value 2
waddr <= #`FF_DELAY 2 ;
else
if (wallow)
waddr <= #`FF_DELAY waddr + 1'b1 ;
end
/*------------------------------------------------------------------------------------------------------------------------------
Full control:
Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.
If they are equal, fifo is full.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr
(
.data_in (rgrey_addr),
.clk_out (wclock_in),
.sync_data_out (wclk_sync_rgrey_addr),
.async_reset (clear)
) ;
always@(posedge wclock_in or posedge clear)
begin
if (clear)
wclk_rgrey_addr <= #`FF_DELAY 0 ;
else
wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ;
end
assign full = (wgrey_next == wclk_rgrey_addr) ;
/*------------------------------------------------------------------------------------------------------------------------------
Empty control:
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
If they are equal, fifo is empty. Synchronized write pointer is also compared to Gray coded next read address. If these two are
equal, fifo is almost empty.
--------------------------------------------------------------------------------------------------------------------------------*/
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
(
.data_in (wgrey_addr),
.clk_out (rclock_in),
.sync_data_out (rclk_sync_wgrey_addr),
.async_reset (clear)
) ;
always@(posedge rclock_in or posedge clear)
begin
if (clear)
rclk_wgrey_addr <= #`FF_DELAY 0 ;
else
rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
end
assign almost_empty = (rgrey_next == rclk_wgrey_addr) ;
assign empty = (rgrey_addr == rclk_wgrey_addr) ;
endmodule |
module pci_async_reset_flop (
data_in, clk_in, async_reset_data_out, reset_in
);
input data_in;
input clk_in;
output async_reset_data_out;
input reset_in;
reg async_reset_data_out;
always @(posedge clk_in or posedge reset_in)
begin
if (reset_in)
begin
async_reset_data_out <= #`FF_DELAY 1'b0;
end
else
begin
async_reset_data_out <= #`FF_DELAY data_in;
end
end
endmodule |
module pci_target32_trdy_crit
(
trdy_w,
trdy_w_frm,
trdy_w_frm_irdy,
pci_frame_in,
pci_irdy_in,
pci_trdy_out
);
input trdy_w ; // trdy signal (composed without critical signals) that do not need critical inputs
input trdy_w_frm ; // trdy signal (composed without critical signals) that needs AND with critical FRAME input
input trdy_w_frm_irdy ; // trdy signal (composed without critical signals) that needs AND with critical FRAME and
// IRDY inputs
input pci_frame_in ; // critical constrained input signal
input pci_irdy_in ; // critical constrained input signal
output pci_trdy_out ; // PCI trdy output
// PCI trdy output with preserved hierarchy for minimum delay!
assign pci_trdy_out = ~(trdy_w || (trdy_w_frm && ~pci_frame_in) || (trdy_w_frm_irdy && ~pci_frame_in && pci_irdy_in)) ;
endmodule |
module pci_irdy_out_crit
(
pci_irdy_out,
irdy_slow_in,
pci_frame_out_in,
pci_trdy_in,
pci_stop_in
) ;
output pci_irdy_out ;
input irdy_slow_in,
pci_frame_out_in,
pci_trdy_in,
pci_stop_in ;
assign pci_irdy_out = irdy_slow_in || (pci_frame_out_in && ~(pci_trdy_in && pci_stop_in)) ;
endmodule |
module pci_target_unit
(
reset_in,
wb_clock_in,
pci_clock_in,
pciu_wbm_adr_o,
pciu_wbm_dat_o,
pciu_wbm_dat_i,
pciu_wbm_cyc_o,
pciu_wbm_stb_o,
pciu_wbm_we_o,
pciu_wbm_cti_o,
pciu_wbm_bte_o,
pciu_wbm_sel_o,
pciu_wbm_ack_i,
pciu_wbm_rty_i,
pciu_wbm_err_i,
pciu_mem_enable_in,
pciu_io_enable_in,
pciu_map_in,
pciu_pref_en_in,
pciu_conf_data_in,
pciu_wbw_fifo_empty_in,
pciu_wbu_del_read_comp_pending_in,
pciu_wbu_frame_en_in,
pciu_bar0_in,
pciu_bar1_in,
pciu_bar2_in,
pciu_bar3_in,
pciu_bar4_in,
pciu_bar5_in,
pciu_am0_in,
pciu_am1_in,
pciu_am2_in,
pciu_am3_in,
pciu_am4_in,
pciu_am5_in,
pciu_ta0_in,
pciu_ta1_in,
pciu_ta2_in,
pciu_ta3_in,
pciu_ta4_in,
pciu_ta5_in,
pciu_at_en_in,
pciu_cache_line_size_in,
pciu_cache_lsize_not_zero_in,
pciu_pciif_frame_in,
pciu_pciif_irdy_in,
pciu_pciif_idsel_in,
pciu_pciif_frame_reg_in,
pciu_pciif_irdy_reg_in,
pciu_pciif_idsel_reg_in,
pciu_pciif_ad_reg_in,
pciu_pciif_cbe_reg_in,
pciu_pciif_cbe_in,
pciu_pciif_bckp_trdy_en_in,
pciu_pciif_bckp_devsel_in,
pciu_pciif_bckp_trdy_in,
pciu_pciif_bckp_stop_in,
pciu_pciif_trdy_reg_in,
pciu_pciif_stop_reg_in,
pciu_pciif_trdy_out,
pciu_pciif_stop_out,
pciu_pciif_devsel_out,
pciu_pciif_trdy_en_out,
pciu_pciif_stop_en_out,
pciu_pciif_devsel_en_out,
pciu_ad_load_out,
pciu_ad_load_on_transfer_out,
pciu_pciif_ad_out,
pciu_pciif_ad_en_out,
pciu_pciif_tabort_set_out,
pciu_err_addr_out,
pciu_err_bc_out,
pciu_err_data_out,
pciu_err_be_out,
pciu_err_signal_out,
pciu_err_source_out,
pciu_err_rty_exp_out,
pciu_conf_offset_out,
pciu_conf_renable_out,
pciu_conf_wenable_out,
pciu_conf_be_out,
pciu_conf_data_out,
pciu_pci_drcomp_pending_out,
pciu_pciw_fifo_empty_out
`ifdef PCI_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
`ifdef HOST
`ifdef NO_CNF_IMAGE
parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
`else
parameter pci_ba0_width = 20 ;
`endif
`endif
`ifdef GUEST
parameter pci_ba0_width = 20 ;
`endif
parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
input reset_in,
wb_clock_in,
pci_clock_in ;
output [31:0] pciu_wbm_adr_o ;
output [31:0] pciu_wbm_dat_o ;
input [31:0] pciu_wbm_dat_i ;
output pciu_wbm_cyc_o ;
output pciu_wbm_stb_o ;
output pciu_wbm_we_o ;
output [2:0] pciu_wbm_cti_o ;
output [1:0] pciu_wbm_bte_o ;
output [3:0] pciu_wbm_sel_o ;
input pciu_wbm_ack_i ;
input pciu_wbm_rty_i ;
input pciu_wbm_err_i ;
input pciu_wbw_fifo_empty_in ;
input pciu_wbu_del_read_comp_pending_in ;
input pciu_wbu_frame_en_in ;
input pciu_mem_enable_in ;
input pciu_io_enable_in ;
input [5:0] pciu_map_in ;
input [5:0] pciu_pref_en_in ;
input [31:0] pciu_conf_data_in ;
input [pci_ba0_width - 1:0] pciu_bar0_in ;
input [pci_ba1_5_width - 1:0] pciu_bar1_in ;
input [pci_ba1_5_width - 1:0] pciu_bar2_in ;
input [pci_ba1_5_width - 1:0] pciu_bar3_in ;
input [pci_ba1_5_width - 1:0] pciu_bar4_in ;
input [pci_ba1_5_width - 1:0] pciu_bar5_in ;
input [pci_ba1_5_width - 1:0] pciu_am0_in ;
input [pci_ba1_5_width - 1:0] pciu_am1_in ;
input [pci_ba1_5_width - 1:0] pciu_am2_in ;
input [pci_ba1_5_width - 1:0] pciu_am3_in ;
input [pci_ba1_5_width - 1:0] pciu_am4_in ;
input [pci_ba1_5_width - 1:0] pciu_am5_in ;
input [pci_ba1_5_width - 1:0] pciu_ta0_in ;
input [pci_ba1_5_width - 1:0] pciu_ta1_in ;
input [pci_ba1_5_width - 1:0] pciu_ta2_in ;
input [pci_ba1_5_width - 1:0] pciu_ta3_in ;
input [pci_ba1_5_width - 1:0] pciu_ta4_in ;
input [pci_ba1_5_width - 1:0] pciu_ta5_in ;
input [5:0] pciu_at_en_in ;
input [7:0] pciu_cache_line_size_in ;
input pciu_cache_lsize_not_zero_in ;
input pciu_pciif_frame_in ;
input pciu_pciif_irdy_in ;
input pciu_pciif_idsel_in ;
input pciu_pciif_frame_reg_in ;
input pciu_pciif_irdy_reg_in ;
input pciu_pciif_idsel_reg_in ;
input [31:0] pciu_pciif_ad_reg_in ;
input [3:0] pciu_pciif_cbe_reg_in ;
input [3:0] pciu_pciif_cbe_in;
input pciu_pciif_bckp_trdy_en_in ;
input pciu_pciif_bckp_devsel_in ;
input pciu_pciif_bckp_trdy_in ;
input pciu_pciif_bckp_stop_in ;
input pciu_pciif_trdy_reg_in ;
input pciu_pciif_stop_reg_in ;
output pciu_pciif_trdy_out ;
output pciu_pciif_stop_out ;
output pciu_pciif_devsel_out ;
output pciu_pciif_trdy_en_out ;
output pciu_pciif_stop_en_out ;
output pciu_pciif_devsel_en_out ;
output pciu_ad_load_out ;
output pciu_ad_load_on_transfer_out ;
output [31:0] pciu_pciif_ad_out ;
output pciu_pciif_ad_en_out ;
output pciu_pciif_tabort_set_out ;
output [31:0] pciu_err_addr_out ;
output [3:0] pciu_err_bc_out ;
output [31:0] pciu_err_data_out ;
output [3:0] pciu_err_be_out ;
output pciu_err_signal_out ;
output pciu_err_source_out ;
output pciu_err_rty_exp_out ;
output [11:0] pciu_conf_offset_out ;
output pciu_conf_renable_out ;
output pciu_conf_wenable_out ;
output [3:0] pciu_conf_be_out ;
output [31:0] pciu_conf_data_out ;
output pciu_pci_drcomp_pending_out ;
output pciu_pciw_fifo_empty_out ;
`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
// pci target state machine and interface outputs
wire pcit_sm_trdy_out ;
wire pcit_sm_stop_out ;
wire pcit_sm_devsel_out ;
wire pcit_sm_trdy_en_out ;
wire pcit_sm_stop_en_out ;
wire pcit_sm_devsel_en_out ;
wire pcit_sm_ad_load_out ;
wire pcit_sm_ad_load_on_transfer_out ;
wire [31:0] pcit_sm_ad_out ;
wire pcit_sm_ad_en_out ;
wire [31:0] pcit_sm_address_out ;
wire [3:0] pcit_sm_bc_out ;
wire pcit_sm_bc0_out ;
wire [31:0] pcit_sm_data_out ;
wire [3:0] pcit_sm_be_out ;
wire [3:0] pcit_sm_next_be_out ;
wire pcit_sm_req_out ;
wire pcit_sm_rdy_out ;
wire pcit_sm_addr_phase_out ;
wire pcit_sm_bckp_devsel_out ;
wire pcit_sm_bckp_trdy_out ;
wire pcit_sm_bckp_stop_out ;
wire pcit_sm_last_reg_out ;
wire pcit_sm_frame_reg_out ;
wire pcit_sm_fetch_pcir_fifo_out ;
wire pcit_sm_load_medium_reg_out ;
wire pcit_sm_sel_fifo_mreg_out ;
wire pcit_sm_sel_conf_fifo_out ;
wire pcit_sm_load_to_pciw_fifo_out ;
wire pcit_sm_load_to_conf_out ;
wire pcit_sm_target_abort_set_out ; // to conf space
assign pciu_pciif_trdy_out = pcit_sm_trdy_out ;
assign pciu_pciif_stop_out = pcit_sm_stop_out ;
assign pciu_pciif_devsel_out = pcit_sm_devsel_out ;
assign pciu_pciif_trdy_en_out = pcit_sm_trdy_en_out ;
assign pciu_pciif_stop_en_out = pcit_sm_stop_en_out ;
assign pciu_pciif_devsel_en_out = pcit_sm_devsel_en_out ;
assign pciu_ad_load_out = pcit_sm_ad_load_out ;
assign pciu_ad_load_on_transfer_out = pcit_sm_ad_load_on_transfer_out ;
assign pciu_pciif_ad_out = pcit_sm_ad_out ;
assign pciu_pciif_ad_en_out = pcit_sm_ad_en_out ;
assign pciu_pciif_tabort_set_out = pcit_sm_target_abort_set_out ;
wire pcit_if_addr_claim_out ;
wire [31:0] pcit_if_data_out ;
wire pcit_if_same_read_out ;
wire pcit_if_norm_access_to_config_out ;
wire pcit_if_read_completed_out ;
wire pcit_if_read_processing_out ;
wire pcit_if_target_abort_out ;
wire pcit_if_disconect_wo_data_out ;
wire pcit_if_disconect_w_data_out ;
wire pcit_if_pciw_fifo_full_out ;
wire pcit_if_pcir_fifo_data_err_out ;
wire pcit_if_wbw_fifo_empty_out ;
wire pcit_if_wbu_del_read_comp_pending_out ;
wire pcit_if_req_out ;
wire pcit_if_done_out ;
wire pcit_if_in_progress_out ;
wire [31:0] pcit_if_addr_out ;
wire [3:0] pcit_if_be_out ;
wire pcit_if_we_out ;
wire [3:0] pcit_if_bc_out ;
wire pcit_if_burst_ok_out ;
wire pcit_if_pcir_fifo_renable_out ;
wire pcit_if_pcir_fifo_flush_out ;
wire pcit_if_pciw_fifo_wenable_out ;
wire [31:0] pcit_if_pciw_fifo_addr_data_out ;
wire [3:0] pcit_if_pciw_fifo_cbe_out ;
wire [3:0] pcit_if_pciw_fifo_control_out ;
wire [11:0] pcit_if_conf_addr_out ;
wire [31:0] pcit_if_conf_data_out ;
wire [3:0] pcit_if_conf_be_out ;
wire pcit_if_conf_we_out ;
wire pcit_if_conf_re_out ;
// pci target state machine outputs
// pci interface signals
assign pciu_conf_offset_out = pcit_if_conf_addr_out ;
assign pciu_conf_renable_out = pcit_if_conf_re_out ;
assign pciu_conf_wenable_out = pcit_if_conf_we_out ;
assign pciu_conf_be_out = pcit_if_conf_be_out ;
assign pciu_conf_data_out = pcit_if_conf_data_out ;
// wishbone master state machine outputs
wire wbm_sm_wb_read_done ;
wire wbm_sm_write_attempt ;
wire wbm_sm_pcir_fifo_wenable_out ;
wire [31:0] wbm_sm_pcir_fifo_data_out ;
wire [3:0] wbm_sm_pcir_fifo_be_out ;
wire [3:0] wbm_sm_pcir_fifo_control_out ;
wire wbm_sm_pciw_fifo_renable_out ;
wire wbm_sm_pci_error_sig_out ;
wire [3:0] wbm_sm_pci_error_bc ;
wire wbm_sm_write_rty_cnt_exp_out ;
wire wbm_sm_error_source_out ;
wire wbm_sm_read_rty_cnt_exp_out ;
wire wbm_sm_cyc_out ;
wire wbm_sm_stb_out ;
wire wbm_sm_we_out ;
wire [2:0] wbm_sm_cti_out ;
wire [1:0] wbm_sm_bte_out ;
wire [3:0] wbm_sm_sel_out ;
wire [31:0] wbm_sm_adr_out ;
wire [31:0] wbm_sm_mdata_out ;
assign pciu_err_addr_out = wbm_sm_adr_out ;
assign pciu_err_bc_out = wbm_sm_pci_error_bc ;
assign pciu_err_data_out = wbm_sm_mdata_out ;
assign pciu_err_be_out = ~wbm_sm_sel_out ;
assign pciu_err_signal_out = wbm_sm_pci_error_sig_out ;
assign pciu_err_source_out = wbm_sm_error_source_out ;
assign pciu_err_rty_exp_out = wbm_sm_write_rty_cnt_exp_out ;
assign pciu_wbm_adr_o = wbm_sm_adr_out ;
assign pciu_wbm_dat_o = wbm_sm_mdata_out ;
assign pciu_wbm_cyc_o = wbm_sm_cyc_out ;
assign pciu_wbm_stb_o = wbm_sm_stb_out ;
assign pciu_wbm_we_o = wbm_sm_we_out ;
assign pciu_wbm_cti_o = wbm_sm_cti_out ;
assign pciu_wbm_bte_o = wbm_sm_bte_out ;
assign pciu_wbm_sel_o = wbm_sm_sel_out ;
// pciw_pcir fifo outputs
// pciw_fifo_outputs:
wire [31:0] fifos_pciw_addr_data_out ;
wire [3:0] fifos_pciw_cbe_out ;
wire [3:0] fifos_pciw_control_out ;
wire fifos_pciw_three_left_out ;
wire fifos_pciw_two_left_out ;
wire fifos_pciw_almost_full_out ;
wire fifos_pciw_full_out ;
wire fifos_pciw_almost_empty_out ;
wire fifos_pciw_empty_out ;
wire fifos_pciw_transaction_ready_out ;
assign pciu_pciw_fifo_empty_out = !wbm_sm_write_attempt;
// pcir_fifo_outputs
wire [31:0] fifos_pcir_data_out ;
wire [3:0] fifos_pcir_be_out ;
wire [3:0] fifos_pcir_control_out ;
wire fifos_pcir_almost_empty_out ;
wire fifos_pcir_empty_out ;
// delayed transaction logic outputs
wire [31:0] del_sync_addr_out ;
wire [3:0] del_sync_be_out ;
wire del_sync_we_out ;
wire del_sync_comp_req_pending_out ;
wire del_sync_comp_comp_pending_out ;
wire del_sync_req_req_pending_out ;
wire del_sync_req_comp_pending_out ;
wire [3:0] del_sync_bc_out ;
wire del_sync_status_out ;
wire del_sync_comp_flush_out ;
wire del_sync_burst_out ;
assign pciu_pci_drcomp_pending_out = del_sync_comp_comp_pending_out ;
// WISHBONE master interface inputs
wire wbm_sm_pci_tar_read_request = del_sync_comp_req_pending_out ;
wire [31:0] wbm_sm_pci_tar_address = del_sync_addr_out ;
wire [3:0] wbm_sm_pci_tar_cmd = del_sync_bc_out ;
wire [3:0] wbm_sm_pci_tar_be = del_sync_be_out ;
wire wbm_sm_pci_tar_burst_ok = del_sync_burst_out ;
wire [7:0] wbm_sm_pci_cache_line_size = pciu_cache_line_size_in ;
wire wbm_sm_cache_lsize_not_zero_in = pciu_cache_lsize_not_zero_in ;
wire [31:0] wbm_sm_pciw_fifo_addr_data_in = fifos_pciw_addr_data_out ;
wire [3:0] wbm_sm_pciw_fifo_cbe_in = fifos_pciw_cbe_out ;
wire [3:0] wbm_sm_pciw_fifo_control_in = fifos_pciw_control_out ;
wire wbm_sm_pciw_fifo_almost_empty_in = fifos_pciw_almost_empty_out ;
wire wbm_sm_pciw_fifo_empty_in = fifos_pciw_empty_out ;
wire wbm_sm_pciw_fifo_transaction_ready_in = fifos_pciw_transaction_ready_out ;
wire [31:0] wbm_sm_mdata_in = pciu_wbm_dat_i ;
wire wbm_sm_ack_in = pciu_wbm_ack_i ;
wire wbm_sm_rty_in = pciu_wbm_rty_i ;
wire wbm_sm_err_in = pciu_wbm_err_i ;
// WISHBONE master interface instantiation
pci_wb_master wishbone_master
(
.wb_clock_in (wb_clock_in),
.reset_in (reset_in),
.pci_tar_read_request (wbm_sm_pci_tar_read_request), //in
.pci_tar_address (wbm_sm_pci_tar_address), //in
.pci_tar_cmd (wbm_sm_pci_tar_cmd), //in
.pci_tar_be (wbm_sm_pci_tar_be), //in
.pci_tar_burst_ok (wbm_sm_pci_tar_burst_ok), //in
.pci_cache_line_size (wbm_sm_pci_cache_line_size), //in
.cache_lsize_not_zero (wbm_sm_cache_lsize_not_zero_in),
.wb_read_done_out (wbm_sm_wb_read_done), //out
.w_attempt (wbm_sm_write_attempt), //out
.pcir_fifo_wenable_out (wbm_sm_pcir_fifo_wenable_out),
.pcir_fifo_data_out (wbm_sm_pcir_fifo_data_out),
.pcir_fifo_be_out (wbm_sm_pcir_fifo_be_out),
.pcir_fifo_control_out (wbm_sm_pcir_fifo_control_out),
.pciw_fifo_renable_out (wbm_sm_pciw_fifo_renable_out),
.pciw_fifo_addr_data_in (wbm_sm_pciw_fifo_addr_data_in),
.pciw_fifo_cbe_in (wbm_sm_pciw_fifo_cbe_in),
.pciw_fifo_control_in (wbm_sm_pciw_fifo_control_in),
.pciw_fifo_almost_empty_in (wbm_sm_pciw_fifo_almost_empty_in),
.pciw_fifo_empty_in (wbm_sm_pciw_fifo_empty_in),
.pciw_fifo_transaction_ready_in (wbm_sm_pciw_fifo_transaction_ready_in),
.pci_error_sig_out (wbm_sm_pci_error_sig_out),
.pci_error_bc (wbm_sm_pci_error_bc),
.write_rty_cnt_exp_out (wbm_sm_write_rty_cnt_exp_out),
.error_source_out (wbm_sm_error_source_out),
.read_rty_cnt_exp_out (wbm_sm_read_rty_cnt_exp_out),
.wb_cyc_o (wbm_sm_cyc_out),
.wb_stb_o (wbm_sm_stb_out),
.wb_we_o (wbm_sm_we_out),
.wb_cti_o (wbm_sm_cti_out),
.wb_bte_o (wbm_sm_bte_out),
.wb_sel_o (wbm_sm_sel_out),
.wb_adr_o (wbm_sm_adr_out),
.wb_dat_i (wbm_sm_mdata_in),
.wb_dat_o (wbm_sm_mdata_out),
.wb_ack_i (wbm_sm_ack_in),
.wb_rty_i (wbm_sm_rty_in),
.wb_err_i (wbm_sm_err_in)
);
// pciw_pcir_fifos inputs
// PCIW_FIFO inputs
wire fifos_pciw_wenable_in = pcit_if_pciw_fifo_wenable_out ;
wire [31:0] fifos_pciw_addr_data_in = pcit_if_pciw_fifo_addr_data_out ;
wire [3:0] fifos_pciw_cbe_in = pcit_if_pciw_fifo_cbe_out ;
wire [3:0] fifos_pciw_control_in = pcit_if_pciw_fifo_control_out ;
wire fifos_pciw_renable_in = wbm_sm_pciw_fifo_renable_out ;
//wire fifos_pciw_flush_in = 1'b0 ; // flush not used for write fifo
// PCIR_FIFO inputs
wire fifos_pcir_wenable_in = wbm_sm_pcir_fifo_wenable_out ;
wire [31:0] fifos_pcir_data_in = wbm_sm_pcir_fifo_data_out ;
wire [3:0] fifos_pcir_be_in = wbm_sm_pcir_fifo_be_out ;
wire [3:0] fifos_pcir_control_in = wbm_sm_pcir_fifo_control_out ;
wire fifos_pcir_renable_in = pcit_if_pcir_fifo_renable_out ;
wire fifos_pcir_flush_in = pcit_if_pcir_fifo_flush_out ;
// PCIW_FIFO and PCIR_FIFO instantiation
pci_pciw_pcir_fifos fifos
(
.wb_clock_in (wb_clock_in),
.pci_clock_in (pci_clock_in),
.reset_in (reset_in),
.pciw_wenable_in (fifos_pciw_wenable_in), //for PCI Target !!!
.pciw_addr_data_in (fifos_pciw_addr_data_in), //for PCI Target !!!
.pciw_cbe_in (fifos_pciw_cbe_in), //for PCI Target !!!
.pciw_control_in (fifos_pciw_control_in), //for PCI Target !!!
.pciw_renable_in (fifos_pciw_renable_in),
.pciw_addr_data_out (fifos_pciw_addr_data_out),
.pciw_cbe_out (fifos_pciw_cbe_out),
.pciw_control_out (fifos_pciw_control_out),
// .pciw_flush_in (fifos_pciw_flush_in), // flush not used for write fifo
.pciw_three_left_out (fifos_pciw_three_left_out), //for PCI Target !!!
.pciw_two_left_out (fifos_pciw_two_left_out), //for PCI Target !!!
.pciw_almost_full_out (fifos_pciw_almost_full_out), //for PCI Target !!!
.pciw_full_out (fifos_pciw_full_out), //for PCI Target !!!
.pciw_almost_empty_out (fifos_pciw_almost_empty_out),
.pciw_empty_out (fifos_pciw_empty_out),
.pciw_transaction_ready_out (fifos_pciw_transaction_ready_out),
.pcir_wenable_in (fifos_pcir_wenable_in),
.pcir_data_in (fifos_pcir_data_in),
.pcir_be_in (fifos_pcir_be_in),
.pcir_control_in (fifos_pcir_control_in),
.pcir_renable_in (fifos_pcir_renable_in), //for PCI Target !!!
.pcir_data_out (fifos_pcir_data_out), //for PCI Target !!!
.pcir_be_out (fifos_pcir_be_out), //for PCI Target !!!
.pcir_control_out (fifos_pcir_control_out), //for PCI Target !!!
.pcir_flush_in (fifos_pcir_flush_in), //for PCI Target !!!
.pcir_full_out (),
.pcir_almost_empty_out (fifos_pcir_almost_empty_out), //for PCI Target !!!
.pcir_empty_out (fifos_pcir_empty_out), //for PCI Target !!!
.pcir_transaction_ready_out ()
`ifdef PCI_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
) ;
// delayed transaction logic inputs
wire del_sync_req_in = pcit_if_req_out ;
wire del_sync_comp_in = wbm_sm_wb_read_done ;
wire del_sync_done_in = pcit_if_done_out ;
wire del_sync_in_progress_in = pcit_if_in_progress_out ;
wire [31:0] del_sync_addr_in = pcit_if_addr_out ;
wire [3:0] del_sync_be_in = pcit_if_be_out ;
wire del_sync_we_in = pcit_if_we_out ;
wire [3:0] del_sync_bc_in = pcit_if_bc_out ;
wire del_sync_status_in = 1'b0 ;
wire del_sync_burst_in = pcit_if_burst_ok_out ;
wire del_sync_retry_expired_in = wbm_sm_read_rty_cnt_exp_out ;
// delayed transaction logic instantiation
pci_delayed_sync del_sync
(
.reset_in (reset_in),
.req_clk_in (pci_clock_in),
.comp_clk_in (wb_clock_in),
.req_in (del_sync_req_in),
.comp_in (del_sync_comp_in),
.done_in (del_sync_done_in),
.in_progress_in (del_sync_in_progress_in),
.comp_req_pending_out (del_sync_comp_req_pending_out),
.comp_comp_pending_out (del_sync_comp_comp_pending_out),
.req_req_pending_out (del_sync_req_req_pending_out),
.req_comp_pending_out (del_sync_req_comp_pending_out),
.addr_in (del_sync_addr_in),
.be_in (del_sync_be_in),
.addr_out (del_sync_addr_out),
.be_out (del_sync_be_out),
.we_in (del_sync_we_in),
.we_out (del_sync_we_out),
.bc_in (del_sync_bc_in),
.bc_out (del_sync_bc_out),
.status_in (del_sync_status_in),
.status_out (del_sync_status_out),
.comp_flush_out (del_sync_comp_flush_out),
.burst_in (del_sync_burst_in),
.burst_out (del_sync_burst_out),
.retry_expired_in (del_sync_retry_expired_in)
);
// pci target interface inputs
wire [31:0] pcit_if_address_in = pcit_sm_address_out ;
wire [3:0] pcit_if_bc_in = pcit_sm_bc_out ;
wire pcit_if_bc0_in = pcit_sm_bc0_out ;
wire [31:0] pcit_if_data_in = pcit_sm_data_out ;
wire [3:0] pcit_if_be_in = pcit_sm_be_out ;
wire [3:0] pcit_if_next_be_in = pcit_sm_next_be_out ;
wire pcit_if_req_in = pcit_sm_req_out ;
wire pcit_if_rdy_in = pcit_sm_rdy_out ;
wire pcit_if_addr_phase_in = pcit_sm_addr_phase_out ;
wire pcit_if_bckp_devsel_in = pcit_sm_bckp_devsel_out ;
wire pcit_if_bckp_trdy_in = pcit_sm_bckp_trdy_out ;
wire pcit_if_bckp_stop_in = pcit_sm_bckp_stop_out ;
wire pcit_if_last_reg_in = pcit_sm_last_reg_out ;
wire pcit_if_frame_reg_in = pcit_sm_frame_reg_out ;
wire pcit_if_fetch_pcir_fifo_in = pcit_sm_fetch_pcir_fifo_out ;
wire pcit_if_load_medium_reg_in = pcit_sm_load_medium_reg_out ;
wire pcit_if_sel_fifo_mreg_in = pcit_sm_sel_fifo_mreg_out ;
wire pcit_if_sel_conf_fifo_in = pcit_sm_sel_conf_fifo_out ;
wire pcit_if_load_to_pciw_fifo_in = pcit_sm_load_to_pciw_fifo_out ;
wire pcit_if_load_to_conf_in = pcit_sm_load_to_conf_out ;
wire pcit_if_req_req_pending_in = del_sync_req_req_pending_out ;
wire pcit_if_req_comp_pending_in = del_sync_req_comp_pending_out ;
wire pcit_if_status_in = del_sync_status_out ;
wire [31:0] pcit_if_strd_addr_in = del_sync_addr_out ;
wire [3:0] pcit_if_strd_bc_in = del_sync_bc_out ;
wire pcit_if_comp_flush_in = del_sync_comp_flush_out ;
wire [31:0] pcit_if_pcir_fifo_data_in = fifos_pcir_data_out ;
wire [3:0] pcit_if_pcir_fifo_be_in = fifos_pcir_be_out ;
wire [3:0] pcit_if_pcir_fifo_control_in = fifos_pcir_control_out ;
wire pcit_if_pcir_fifo_almost_empty_in = fifos_pcir_almost_empty_out ;
wire pcit_if_pcir_fifo_empty_in = fifos_pcir_empty_out ;
wire pcit_if_pciw_fifo_three_left_in = fifos_pciw_three_left_out ;
wire pcit_if_pciw_fifo_two_left_in = fifos_pciw_two_left_out ;
wire pcit_if_pciw_fifo_almost_full_in = fifos_pciw_almost_full_out ;
wire pcit_if_pciw_fifo_full_in = fifos_pciw_full_out ;
wire pcit_if_wbw_fifo_empty_in = pciu_wbw_fifo_empty_in ;
wire pcit_if_wbu_del_read_comp_pending_in = pciu_wbu_del_read_comp_pending_in ;
wire [31:0] pcit_if_conf_data_in = pciu_conf_data_in ;
wire pcit_if_mem_enable_in = pciu_mem_enable_in ;
wire pcit_if_io_enable_in = pciu_io_enable_in ;
wire pcit_if_mem_io_addr_space0_in = pciu_map_in[0] ;
wire pcit_if_mem_io_addr_space1_in = pciu_map_in[1] ;
wire pcit_if_mem_io_addr_space2_in = pciu_map_in[2] ;
wire pcit_if_mem_io_addr_space3_in = pciu_map_in[3] ;
wire pcit_if_mem_io_addr_space4_in = pciu_map_in[4] ;
wire pcit_if_mem_io_addr_space5_in = pciu_map_in[5] ;
wire pcit_if_pre_fetch_en0_in = pciu_pref_en_in[0] ;
wire pcit_if_pre_fetch_en1_in = pciu_pref_en_in[1] ;
wire pcit_if_pre_fetch_en2_in = pciu_pref_en_in[2] ;
wire pcit_if_pre_fetch_en3_in = pciu_pref_en_in[3] ;
wire pcit_if_pre_fetch_en4_in = pciu_pref_en_in[4] ;
wire pcit_if_pre_fetch_en5_in = pciu_pref_en_in[5] ;
wire [(pci_ba0_width - 1):0] pcit_if_pci_base_addr0_in = pciu_bar0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr1_in = pciu_bar1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr2_in = pciu_bar2_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr3_in = pciu_bar3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr4_in = pciu_bar4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_base_addr5_in = pciu_bar5_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask0_in = pciu_am0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask1_in = pciu_am1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask2_in = pciu_am2_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask3_in = pciu_am3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask4_in = pciu_am4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_addr_mask5_in = pciu_am5_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr0_in = pciu_ta0_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr1_in = pciu_ta1_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr2_in = pciu_ta2_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr3_in = pciu_ta3_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr4_in = pciu_ta4_in ;
wire [(pci_ba1_5_width - 1):0] pcit_if_pci_tran_addr5_in = pciu_ta5_in ;
wire pcit_if_addr_tran_en0_in = pciu_at_en_in[0] ;
wire pcit_if_addr_tran_en1_in = pciu_at_en_in[1] ;
wire pcit_if_addr_tran_en2_in = pciu_at_en_in[2] ;
wire pcit_if_addr_tran_en3_in = pciu_at_en_in[3] ;
wire pcit_if_addr_tran_en4_in = pciu_at_en_in[4] ;
wire pcit_if_addr_tran_en5_in = pciu_at_en_in[5] ;
pci_target32_interface pci_target_if
(
.clk_in (pci_clock_in),
.reset_in (reset_in),
.address_in (pcit_if_address_in),
.addr_claim_out (pcit_if_addr_claim_out),
.bc_in (pcit_if_bc_in),
.bc0_in (pcit_if_bc0_in),
.data_in (pcit_if_data_in),
.data_out (pcit_if_data_out),
.be_in (pcit_if_be_in),
.next_be_in (pcit_if_next_be_in),
.req_in (pcit_if_req_in),
.rdy_in (pcit_if_rdy_in),
.addr_phase_in (pcit_if_addr_phase_in),
.bckp_devsel_in (pcit_if_bckp_devsel_in),
.bckp_trdy_in (pcit_if_bckp_trdy_in),
.bckp_stop_in (pcit_if_bckp_stop_in),
.last_reg_in (pcit_if_last_reg_in),
.frame_reg_in (pcit_if_frame_reg_in),
.fetch_pcir_fifo_in (pcit_if_fetch_pcir_fifo_in),
.load_medium_reg_in (pcit_if_load_medium_reg_in),
.sel_fifo_mreg_in (pcit_if_sel_fifo_mreg_in),
.sel_conf_fifo_in (pcit_if_sel_conf_fifo_in),
.load_to_pciw_fifo_in (pcit_if_load_to_pciw_fifo_in),
.load_to_conf_in (pcit_if_load_to_conf_in),
.same_read_out (pcit_if_same_read_out),
.norm_access_to_config_out (pcit_if_norm_access_to_config_out),
.read_completed_out (pcit_if_read_completed_out),
.read_processing_out (pcit_if_read_processing_out),
.target_abort_out (pcit_if_target_abort_out),
.disconect_wo_data_out (pcit_if_disconect_wo_data_out),
.disconect_w_data_out (pcit_if_disconect_w_data_out),
.pciw_fifo_full_out (pcit_if_pciw_fifo_full_out),
.pcir_fifo_data_err_out (pcit_if_pcir_fifo_data_err_out),
.wbw_fifo_empty_out (pcit_if_wbw_fifo_empty_out),
.wbu_del_read_comp_pending_out (pcit_if_wbu_del_read_comp_pending_out),
.req_out (pcit_if_req_out),
.done_out (pcit_if_done_out),
.in_progress_out (pcit_if_in_progress_out),
.req_req_pending_in (pcit_if_req_req_pending_in),
.req_comp_pending_in (pcit_if_req_comp_pending_in),
.addr_out (pcit_if_addr_out),
.be_out (pcit_if_be_out),
.we_out (pcit_if_we_out),
.bc_out (pcit_if_bc_out),
.burst_ok_out (pcit_if_burst_ok_out),
.strd_addr_in (pcit_if_strd_addr_in),
.strd_bc_in (pcit_if_strd_bc_in),
.status_in (pcit_if_status_in),
.comp_flush_in (pcit_if_comp_flush_in),
.pcir_fifo_renable_out (pcit_if_pcir_fifo_renable_out),
.pcir_fifo_data_in (pcit_if_pcir_fifo_data_in),
.pcir_fifo_be_in (pcit_if_pcir_fifo_be_in),
.pcir_fifo_control_in (pcit_if_pcir_fifo_control_in),
.pcir_fifo_flush_out (pcit_if_pcir_fifo_flush_out),
.pcir_fifo_almost_empty_in (pcit_if_pcir_fifo_almost_empty_in),
.pcir_fifo_empty_in (pcit_if_pcir_fifo_empty_in),
.pciw_fifo_wenable_out (pcit_if_pciw_fifo_wenable_out),
.pciw_fifo_addr_data_out (pcit_if_pciw_fifo_addr_data_out),
.pciw_fifo_cbe_out (pcit_if_pciw_fifo_cbe_out),
.pciw_fifo_control_out (pcit_if_pciw_fifo_control_out),
.pciw_fifo_three_left_in (pcit_if_pciw_fifo_three_left_in),
.pciw_fifo_two_left_in (pcit_if_pciw_fifo_two_left_in),
.pciw_fifo_almost_full_in (pcit_if_pciw_fifo_almost_full_in),
.pciw_fifo_full_in (pcit_if_pciw_fifo_full_in),
.wbw_fifo_empty_in (pcit_if_wbw_fifo_empty_in),
.wbu_del_read_comp_pending_in (pcit_if_wbu_del_read_comp_pending_in),
.conf_addr_out (pcit_if_conf_addr_out),
.conf_data_out (pcit_if_conf_data_out),
.conf_data_in (pcit_if_conf_data_in),
.conf_be_out (pcit_if_conf_be_out),
.conf_we_out (pcit_if_conf_we_out),
.conf_re_out (pcit_if_conf_re_out),
.mem_enable_in (pcit_if_mem_enable_in),
.io_enable_in (pcit_if_io_enable_in),
.mem_io_addr_space0_in (pcit_if_mem_io_addr_space0_in),
.mem_io_addr_space1_in (pcit_if_mem_io_addr_space1_in),
.mem_io_addr_space2_in (pcit_if_mem_io_addr_space2_in),
.mem_io_addr_space3_in (pcit_if_mem_io_addr_space3_in),
.mem_io_addr_space4_in (pcit_if_mem_io_addr_space4_in),
.mem_io_addr_space5_in (pcit_if_mem_io_addr_space5_in),
.pre_fetch_en0_in (pcit_if_pre_fetch_en0_in),
.pre_fetch_en1_in (pcit_if_pre_fetch_en1_in),
.pre_fetch_en2_in (pcit_if_pre_fetch_en2_in),
.pre_fetch_en3_in (pcit_if_pre_fetch_en3_in),
.pre_fetch_en4_in (pcit_if_pre_fetch_en4_in),
.pre_fetch_en5_in (pcit_if_pre_fetch_en5_in),
.pci_base_addr0_in (pcit_if_pci_base_addr0_in),
.pci_base_addr1_in (pcit_if_pci_base_addr1_in),
.pci_base_addr2_in (pcit_if_pci_base_addr2_in),
.pci_base_addr3_in (pcit_if_pci_base_addr3_in),
.pci_base_addr4_in (pcit_if_pci_base_addr4_in),
.pci_base_addr5_in (pcit_if_pci_base_addr5_in),
.pci_addr_mask0_in (pcit_if_pci_addr_mask0_in),
.pci_addr_mask1_in (pcit_if_pci_addr_mask1_in),
.pci_addr_mask2_in (pcit_if_pci_addr_mask2_in),
.pci_addr_mask3_in (pcit_if_pci_addr_mask3_in),
.pci_addr_mask4_in (pcit_if_pci_addr_mask4_in),
.pci_addr_mask5_in (pcit_if_pci_addr_mask5_in),
.pci_tran_addr0_in (pcit_if_pci_tran_addr0_in),
.pci_tran_addr1_in (pcit_if_pci_tran_addr1_in),
.pci_tran_addr2_in (pcit_if_pci_tran_addr2_in),
.pci_tran_addr3_in (pcit_if_pci_tran_addr3_in),
.pci_tran_addr4_in (pcit_if_pci_tran_addr4_in),
.pci_tran_addr5_in (pcit_if_pci_tran_addr5_in),
.addr_tran_en0_in (pcit_if_addr_tran_en0_in),
.addr_tran_en1_in (pcit_if_addr_tran_en1_in),
.addr_tran_en2_in (pcit_if_addr_tran_en2_in),
.addr_tran_en3_in (pcit_if_addr_tran_en3_in),
.addr_tran_en4_in (pcit_if_addr_tran_en4_in),
.addr_tran_en5_in (pcit_if_addr_tran_en5_in)
) ;
// pci target state machine inputs
wire pcit_sm_frame_in = pciu_pciif_frame_in ;
wire pcit_sm_irdy_in = pciu_pciif_irdy_in ;
wire pcit_sm_idsel_in = pciu_pciif_idsel_in ;
wire pcit_sm_frame_reg_in = pciu_pciif_frame_reg_in ;
wire pcit_sm_irdy_reg_in = pciu_pciif_irdy_reg_in ;
wire pcit_sm_idsel_reg_in = pciu_pciif_idsel_reg_in ;
wire [31:0] pcit_sm_ad_reg_in = pciu_pciif_ad_reg_in ;
wire [3:0] pcit_sm_cbe_reg_in = pciu_pciif_cbe_reg_in ;
wire [3:0] pcit_sm_cbe_in = pciu_pciif_cbe_in ;
wire pcit_sm_bckp_trdy_en_in = pciu_pciif_bckp_trdy_en_in ;
wire pcit_sm_bckp_devsel_in = pciu_pciif_bckp_devsel_in ;
wire pcit_sm_bckp_trdy_in = pciu_pciif_bckp_trdy_in ;
wire pcit_sm_bckp_stop_in = pciu_pciif_bckp_stop_in ;
wire pcit_sm_addr_claim_in = pcit_if_addr_claim_out ;
wire [31:0] pcit_sm_data_in = pcit_if_data_out ;
wire pcit_sm_same_read_in = pcit_if_same_read_out ;
wire pcit_sm_norm_access_to_config_in = pcit_if_norm_access_to_config_out ;
wire pcit_sm_read_completed_in = pcit_if_read_completed_out ;
wire pcit_sm_read_processing_in = pcit_if_read_processing_out ;
wire pcit_sm_target_abort_in = pcit_if_target_abort_out ;
wire pcit_sm_disconect_wo_data_in = pcit_if_disconect_wo_data_out ;
wire pcit_sm_disconect_w_data_in = pcit_if_disconect_w_data_out ;
wire pcit_sm_pciw_fifo_full_in = pcit_if_pciw_fifo_full_out ;
wire pcit_sm_pcir_fifo_data_err_in = pcit_if_pcir_fifo_data_err_out ;
wire pcit_sm_wbw_fifo_empty_in = pcit_if_wbw_fifo_empty_out ;
wire pcit_sm_wbu_del_read_comp_pending_in = pcit_if_wbu_del_read_comp_pending_out ;
wire pcit_sm_wbu_frame_en_in = pciu_wbu_frame_en_in ;
wire pcit_sm_trdy_reg_in = pciu_pciif_trdy_reg_in ;
wire pcit_sm_stop_reg_in = pciu_pciif_stop_reg_in ;
pci_target32_sm pci_target_sm
(
.clk_in (pci_clock_in),
.reset_in (reset_in),
.pci_frame_in (pcit_sm_frame_in),
.pci_irdy_in (pcit_sm_irdy_in),
.pci_idsel_in (pcit_sm_idsel_in),
.pci_frame_reg_in (pcit_sm_frame_reg_in),
.pci_irdy_reg_in (pcit_sm_irdy_reg_in),
.pci_idsel_reg_in (pcit_sm_idsel_reg_in),
.pci_trdy_out (pcit_sm_trdy_out),
.pci_stop_out (pcit_sm_stop_out),
.pci_devsel_out (pcit_sm_devsel_out),
.pci_trdy_en_out (pcit_sm_trdy_en_out),
.pci_stop_en_out (pcit_sm_stop_en_out),
.pci_devsel_en_out (pcit_sm_devsel_en_out),
.ad_load_out (pcit_sm_ad_load_out),
.ad_load_on_transfer_out (pcit_sm_ad_load_on_transfer_out),
.pci_ad_reg_in (pcit_sm_ad_reg_in),
.pci_ad_out (pcit_sm_ad_out),
.pci_ad_en_out (pcit_sm_ad_en_out),
.pci_cbe_reg_in (pcit_sm_cbe_reg_in),
.pci_cbe_in (pcit_sm_cbe_in),
.bckp_trdy_en_in (pcit_sm_bckp_trdy_en_in),
.bckp_devsel_in (pcit_sm_bckp_devsel_in),
.bckp_trdy_in (pcit_sm_bckp_trdy_in),
.bckp_stop_in (pcit_sm_bckp_stop_in),
.pci_trdy_reg_in (pcit_sm_trdy_reg_in),
.pci_stop_reg_in (pcit_sm_stop_reg_in),
.address_out (pcit_sm_address_out),
.addr_claim_in (pcit_sm_addr_claim_in),
.bc_out (pcit_sm_bc_out),
.bc0_out (pcit_sm_bc0_out),
.data_out (pcit_sm_data_out),
.data_in (pcit_sm_data_in),
.be_out (pcit_sm_be_out),
.next_be_out (pcit_sm_next_be_out),
.req_out (pcit_sm_req_out),
.rdy_out (pcit_sm_rdy_out),
.addr_phase_out (pcit_sm_addr_phase_out),
.bckp_devsel_out (pcit_sm_bckp_devsel_out),
.bckp_trdy_out (pcit_sm_bckp_trdy_out),
.bckp_stop_out (pcit_sm_bckp_stop_out),
.last_reg_out (pcit_sm_last_reg_out),
.frame_reg_out (pcit_sm_frame_reg_out),
.fetch_pcir_fifo_out (pcit_sm_fetch_pcir_fifo_out),
.load_medium_reg_out (pcit_sm_load_medium_reg_out),
.sel_fifo_mreg_out (pcit_sm_sel_fifo_mreg_out),
.sel_conf_fifo_out (pcit_sm_sel_conf_fifo_out),
.load_to_pciw_fifo_out (pcit_sm_load_to_pciw_fifo_out),
.load_to_conf_out (pcit_sm_load_to_conf_out),
.same_read_in (pcit_sm_same_read_in),
.norm_access_to_config_in (pcit_sm_norm_access_to_config_in),
.read_completed_in (pcit_sm_read_completed_in),
.read_processing_in (pcit_sm_read_processing_in),
.target_abort_in (pcit_sm_target_abort_in),
.disconect_wo_data_in (pcit_sm_disconect_wo_data_in),
.disconect_w_data_in (pcit_sm_disconect_w_data_in),
.target_abort_set_out (pcit_sm_target_abort_set_out),
.pciw_fifo_full_in (pcit_sm_pciw_fifo_full_in),
.pcir_fifo_data_err_in (pcit_sm_pcir_fifo_data_err_in),
.wbw_fifo_empty_in (pcit_sm_wbw_fifo_empty_in),
.wbu_del_read_comp_pending_in (pcit_sm_wbu_del_read_comp_pending_in),
.wbu_frame_en_in (pcit_sm_wbu_frame_en_in)
) ;
endmodule |
module pci_frame_load_crit
(
pci_frame_load_out,
sm_data_phases_in,
frame_load_slow_in,
pci_trdy_in,
pci_stop_in
) ;
output pci_frame_load_out ;
input sm_data_phases_in,
frame_load_slow_in,
pci_trdy_in,
pci_stop_in ;
assign pci_frame_load_out = frame_load_slow_in || sm_data_phases_in && (~(pci_trdy_in && pci_stop_in)) ;
endmodule |
Subsets and Splits