module
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module sine_wave_generator(o,t);
input [9:0]t;
output [15:0]o;
reg [15:0] i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,i17,i18,i19,i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30,i31,i32,i33,i34,i35,i36,i37,i38,i39,i40,i41,i42,i43,i44,i45,i46,i47,i48,i49,i50,i51,i52,i53,i54,i55,i56,i57,i58,i59,i60,i61,i62,i63,i64;
mux_16_64 mux_1(o,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,i17,i18,i19,i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30,i31,i32,i33,i34,i35,i36,i37,i38,i39,i40,i41,i42,i43,i44,i45,i46,i47,i48,i49,i50,i51,i52,i53,i54,i55,i56,i57,i58,i59,i60,i61,i62,i63,i64,t);
initial
begin
i1=1000; //1000*sin(t*360/64)+1000 values recorded in order
i2=1098;
i3=1195;
i4=1290;
i5=1383;
i6=1471;
i7=1556;
i8=1634;
i9=1707;
i10=1773;
i11=1831;
i12=1882;
i13=1924;
i14=1957;
i15=1981;
i16=1995;
i17=2000;
i18=1995;
i19=1981;
i20=1957;
i21=1924;
i22=1882;
i23=1831;
i24=1773;
i25=1707;
i26=1634;
i27=1556;
i28=1471;
i29=1383;
i30=1290;
i31=1195;
i32=1098;
i33=1000;
i34=902;
i35=805;
i36=710;
i37=617;
i38=529;
i39=444;
i40=366;
i41=293;
i42=227;
i43=169;
i44=118;
i45=76;
i46=43;
i47=19;
i48=5;
i49=0;
i50=5;
i51=19;
i52=43;
i53=76;
i54=118;
i55=169;
i56=227;
i57=293;
i58=366;
i59=444;
i60=529;
i61=617;
i62=710;
i63=805;
i64=902;
end
endmodule |
module mux_16_64(o,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,i17,i18,i19,i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30,i31,i32,i33,i34,i35,i36,i37,i38,i39,i40,i41,i42,i43,i44,i45,i46,i47,i48,i49,i50,i51,i52,i53,i54,i55,i56,i57,i58,i59,i60,i61,i62,i63,i64,s);
input [15:0]i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,i17,i18,i19,i20,i21,i22,i23,i24,i25,i26,i27,i28,i29,i30,i31,i32,i33,i34,i35,i36,i37,i38,i39,i40,i41,i42,i43,i44,i45,i46,i47,i48,i49,i50,i51,i52,i53,i54,i55,i56,i57,i58,i59,i60,i61,i62,i63,i64;
input [5:0]s;
output [15:0]o;
wire [15:0]x1,x2,x3,x4,x5,x6,x7,x8;
mux_16_8 mux_16_8_1(x1,i1,i2,i3,i4,i5,i6,i7,i8,s[2:0]);
mux_16_8 mux_16_8_2(x2,i9,i10,i11,i12,i13,i14,i15,i16,s[2:0]);
mux_16_8 mux_16_8_3(x3,i17,i18,i19,i20,i21,i22,i23,i24,s[2:0]);
mux_16_8 mux_16_8_4(x4,i25,i26,i27,i28,i29,i30,i31,i32,s[2:0]);
mux_16_8 mux_16_8_5(x5,i33,i34,i35,i36,i37,i38,i39,i40,s[2:0]);
mux_16_8 mux_16_8_6(x6,i41,i42,i43,i44,i45,i46,i47,i48,s[2:0]);
mux_16_8 mux_16_8_7(x7,i49,i50,i51,i52,i53,i54,i55,i56,s[2:0]);
mux_16_8 mux_16_8_8(x8,i57,i58,i59,i60,i61,i62,i63,i64,s[2:0]);
mux_16_8 mux_16_8_9(o,x1,x2,x3,x4,x5,x6,x7,x8,s[5:3]);
endmodule |
module mux_16(o,i1,i2,s); //2x1 MUX with 16-bit I/O
input [15:0]i1,i2;
input s;
output [15:0]o;
mux mux_1[15:0](o,i1,i2,s);
endmodule |
module TB_SWG;
reg [9:0]t;
wire [15:0]o;
sine_wave_generator SWG(o,t);
integer i;
initial
begin
$monitor("o=%d",o);
#5 t=0;
for(i=0;i<1024;i=i+1)
begin
#5 t=i;
end
end
endmodule |
module mux_16_8(o,i1,i2,i3,i4,i5,i6,i7,i8,s); //8x1 MUX with 16-bit I/O
input [15:0]i1,i2,i3,i4,i5,i6,i7,i8;
input [2:0]s;
output [15:0]o;
wire [15:0]x1,x2,x3,x4;
wire [15:0]y1,y2;
mux_16 mux_16_1(x1,i1,i2,s[0]);
mux_16 mux_16_2(x2,i3,i4,s[0]);
mux_16 mux_16_3(x3,i5,i6,s[0]);
mux_16 mux_16_4(x4,i7,i8,s[0]);
mux_16 mux_16_5(y1,x1,x2,s[1]);
mux_16 mux_16_6(y2,x3,x4,s[1]);
mux_16 mux_16_7(o,y1,y2,s[2]);
endmodule |
module test_bench_fs;
reg a, b, bin;
wire diff, bout;
reg clk;
fs_nand dut(a, b, bin, diff, bout);
always #5 clk = ~clk;
initial begin
clk = 0;
a = 0; b = 0; bin = 0;
#10;
a = 0; b = 0; bin = 1;
#10;
a = 0; b = 1; bin = 0;
#10;
a = 0; b = 1; bin = 1;
#10;
a = 1; b = 0; bin = 0;
#10;
a = 1; b = 0; bin = 1;
#10;
a = 1; b = 1; bin = 0;
#10;
a = 1; b = 1; bin = 1;
#10;
$finish;
end
always @(posedge clk) begin
$display("a: %b, b: %b, bin: %b, difference: %b, borrow: %b", a, b, bin, diff, bout);
end
endmodule |
module fa_nand(
input a, b, cin,
output sout, cout
);
wire [6:0]w;
nand n0(w[0], a, b);
nand n1(w[1], a, w[0]);
nand n2(w[2], b, w[0]);
nand n3(w[3], w[1], w[2]);
nand n4(w[4], w[3], cin);
nand n5(w[5], w[3], w[4]);
nand n6(w[6], w[4], cin);
nand n7(sout, w[5], w[6]);
nand n8(cout, w[0], w[4]);
endmodule |
module test_bench_hs;
reg a, b;
wire diff, bout;
reg clk;
hs_nand dut(a, b, diff, bout);
always #5 clk = ~clk;
initial begin
clk = 0;
a = 0; b = 0;
#10;
a = 0; b = 1;
#10;
a = 1; b = 0;
#10;
a = 1; b = 1;
#10
$finish;
end
always @(posedge clk) begin
$display("a: %b, b: %b, difference: %b, borrow: %b", a, b, diff, bout);
end
endmodule |
module hs_nand(
input a, b,
output sout, cout
);
wire [2:0]w;
nand n0(w[0], a, b);
nand n1(w[1], a, w[0]);
nand n2(w[2], b, w[0]);
nand n3(sout, w[1], w[2]);
nand n4(cout, w[2], w[2]);
endmodule |
module fs_nand(
input a, b, bin,
output sout, cout
);
wire [6:0]w;
nand n0(w[0], a, b);
nand n1(w[1], a, w[0]);
nand n2(w[2], b, w[0]);
nand n3(w[3], w[1], w[2]);
nand n4(w[4], w[3], bin);
nand n5(w[5], w[3], w[4]);
nand n6(w[6], w[4], bin);
nand n7(sout, w[5], w[6]);
nand n8(cout, w[2], w[6]);
endmodule |
module test_bench_fa;
reg a, b, cin;
wire sout, cout;
reg clk;
fa_nand dut(a, b, cin, sout, cout);
always #5 clk = ~clk;
initial begin
clk = 0;
a = 0; b = 0; cin = 0;
#10;
a = 0; b = 0; cin = 1;
#10;
a = 0; b = 1; cin = 0;
#10;
a = 0; b = 1; cin = 1;
#10;
a = 1; b = 0; cin = 0;
#10;
a = 1; b = 0; cin = 1;
#10;
a = 1; b = 1; cin = 0;
#10;
a = 1; b = 1; cin = 1;
#10;
$finish;
end
always @(posedge clk) begin
$display("a = %b, b = %b, cin = %b, sum = %b, carry = %b", a, b, cin, sout, cout);
end
endmodule |
module ha_nand(
input a, b,
output sout, cout
);
wire [2:0]w;
nand n0(w[0], a, b);
nand n1(w[1], a, w[0]);
nand n2(w[2], b, w[0]);
nand n3(sout, w[1], w[2]);
nand n4(cout, w[0], w[0]);
endmodule |
module nor_gate(
input Vin1, Vin2,
output Vout
);
supply0 gnd;
supply1 vdd;
wire temp;
pmos (temp, vdd, Vin1);
pmos (Vout, temp, Vin2);
nmos (Vout, gnd, Vin1);
nmos (Vout, gnd, Vin2);
endmodule |
module tb_nand;
reg Vin1, Vin2;
wire Vout;
nand_gate dut(Vin1, Vin2, Vout);
initial Vin1= 1'b0;
initial Vin2= 1'b0;
initial forever #50 Vin1 = ~Vin1;
initial forever #100 Vin2 = ~Vin2;
initial #600 $finish;
endmodule |
module nand_gate(
input Vin1, Vin2,
output Vout
);
supply0 gnd;
supply1 vdd;
wire temp;
pmos (Vout, vdd, Vin1);
pmos (Vout, vdd, Vin2);
nmos (temp, gnd, Vin2);
nmos (Vout, temp, Vin1);
endmodule |
module tb_nor;
reg Vin1, Vin2;
wire Vout;
nor_gate dut(Vin1, Vin2, Vout);
initial Vin1= 1'b0;
initial Vin2= 1'b0;
initial forever #50 Vin1 = ~Vin1;
initial forever #100 Vin2 = ~Vin2;
initial #600 $finish;
endmodule |
module test_bench;
reg clk,rst,t;
wire Q_sr, Q_jk, Q_d;
T_using_SR_JK_D dut(clk, rst, t, Q_sr, Q_jk, Q_d);
initial
begin
clk=0;
t=0;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever
begin
#10 t = 1'b1;
#20 t = 1'b0;
end
end
initial begin
$monitor("\t clock: %b T: %b Q_sr: %d Q_jk: %d Q_d: %b",clk,t,Q_sr, Q_jk, Q_d);
#100$finish;
end
endmodule |
module T_using_SR_JK_D(
input clk, reset, T,
output Q_sr, Q_jk, Q_d
);
wire w1, w2, w3;
assign w1= T & (~Q_sr);
assign w2= T & Q_sr;
SR_flipflop SR(clk, reset, w1, w2, Q_sr);
JK_flipflop JK(T, T, clk, reset, Q_jk);
assign w3= T ^ Q_d;
D_flipflop D(w3, clk, reset, Q_d);
endmodule |
module test_decoder;
reg [6:0] ham_data_encoder;
wire [2:0]error_position;
wire is_error;
wire [3:0]data;
hamming_decoder dut(ham_data_encoder,data,error_position,is_error);
initial begin
ham_data_encoder= 7'b0110011;//error input at 0th position
#20 ham_data_encoder= 7'b1110011;//error input at 7th position
#20 ham_data_encoder= 7'b0110111;//error input at 3rd position
end
initial begin
$monitor("\t\t Decoded Data: %b Is there an Error=%b Error is at Position: %d \n", data,is_error,error_position);
#60 $finish;
end
endmodule |
module test_encoder;
reg [3:0]data;
wire [6:0] ham_data_encoder;
hamming_encoder dut(data, ham_data_encoder);
initial begin
data=4'b0110;
#2 $display("\n \t Output of Hamming Encoder: %b \n",ham_data_encoder);
#10 $stop; //we will get output=1010101, please check in console after run the simulation
end
endmodule |
module hamming_encoder(
input [3:0]data,
output [6:0] ham_data_encoder
);
assign ham_data_encoder[0]=data[0]^data[1]^data[3]; // P1= 1 xor 3 xor 5 xor 7
assign ham_data_encoder[1]=data[0]^data[2]^data[3]; // P2= 2 xor 3 xor 6 xor 7
assign ham_data_encoder[2]=data[0];
assign ham_data_encoder[3]=data[1]^data[2]^data[3]; // P3= 4 xor 5 xor 6 xor 7
assign ham_data_encoder[4]=data[1];
assign ham_data_encoder[5]=data[2];
assign ham_data_encoder[6]=data[3];
endmodule |
module hamming_decoder(
input [6:0] ham_data_encoder,
output [3:0] data,
output [2:0] error_position,
output is_error
);
assign data[0]= ham_data_encoder[2];
assign data[1]= ham_data_encoder[4];
assign data[2]= ham_data_encoder[5];
assign data[3]= ham_data_encoder[6];
assign c1= ham_data_encoder[0]^ham_data_encoder[2]^ham_data_encoder[4]^ham_data_encoder[6]; // C1= 1 xor 3 xor 5 xor 7
assign c2= ham_data_encoder[1]^ham_data_encoder[2]^ham_data_encoder[5]^ham_data_encoder[6]; // C2= 2 xor 3 xor 6 xor 7
assign c3= ham_data_encoder[3]^ham_data_encoder[4]^ham_data_encoder[5]^ham_data_encoder[6]; // C3= 4 xor 5 xor 6 xor 7
assign error_position= {c3,c2,c1};//position of error,
assign is_error = c3 |c2 | c1;//or (any '1'=>is_error=1)
endmodule |
module spi_state(
input wire clk, // System clock
input wire reset, // Asynchronous system reset
input wire [15:0] datain, // Binary input vector
output wire spi_cs_l, //SPI Active-low chip select
output wire spi_sclk, // SPI bus clock
output wire spi_data, // SPI bus data
output [4:0]counter
);
reg [15:0] MOSI; // SPI shift register
reg [4:0] count; // Control counter
reg cs_l; // SPI chip select (active-low)
reg sclk;
reg [2:0]state;
always@(posedge clk or posedge reset)
if(reset) begin
MOSI <= 16'b0;
count<= 5'd16;
cs_l <= 1'b1;
sclk <= 1'b0;
end
else begin
case (state)
0: begin
sclk <= 1'b0;
cs_l <= 1'b1;
state<=1;
end
1: begin
sclk <= 1'b0;
cs_l <= 1'b0;
MOSI <=datain[count-1];
count <=count-1;
state <=2;
end
2: begin
sclk <= 1'b1;
if(count > 0)
state<=1;
else begin
count<=16;
state<=0;
end
end
default:state<=0;
endcase
end
assign spi_cs_l = cs_l;
assign spi_sclk = sclk;
assign spi_data = MOSI;
assign counter=count;
endmodule |
module test_bench;
reg clk;
reg reset;
reg [15:0]datain;
wire spi_cs_l;
wire spi_sclk;
wire spi_data;
wire [4:0]counter;
spi_state dut(clk, reset, datain, spi_cs_l, spi_sclk, spi_data, counter);
initial begin
clk = 0;
reset = 1;
datain = 0;
end
always #5 clk=~clk;
initial begin
#10 reset=1'b0;
#10 datain=16'h0412;
#335 datain=16'h4839;
#335 datain=16'habeb;
end
endmodule |
module half_subtractor(
input a, b,
output diff, bout
);
assign diff = a ^ b;
assign bout = ~a & b;
endmodule |
module full_subtractor(
input a, b, bin,
output diff, bout
);
assign diff = a ^ b ^ bin;
assign bout = (~a & (b^bin)) | (b & bin) ;
endmodule |
module demux_and_gate(
input a, b,
output and_g
);
wire w;
demux_1_2 andgate(b, a, w, and_g);
endmodule |
module tb_and;
reg a, b;
wire and_out;
demux_and_gate dut(a, b, and_out);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b and: %b ",a, b, and_out);
#40 $finish;
end
endmodule |
module demux_or_gate(
input a, b,
output or_g
);
wire w0, w1, w2;
demux_1_2 gate(b, ~a, w0, w1);
demux_1_2 not_t(w0, 1'b1, or_g, w2);
endmodule |
module demux_not_gate(
input a,
output not_g
);
wire w;
demux_1_2 notgate(a, 1'b1, not_g, w);
endmodule |
module demux_nor(
input a, b,
output nor_g
);
wire w;
demux_1_2 norgate(b, ~a, nor_g, w);
endmodule |
module demux_nand(
input a, b,
output nand_g
);
wire w0, w1, w2;
demux_1_2 nandgate(b, a, w0, w1);
demux_1_2 not_t(w1, 1'b1, nand_g, w2);
endmodule |
module star_pattern_2;
integer i,j;
initial begin
for(i=1;i<10;i=i+1)begin
for(j=1;j<10-i;j=j+1)begin
$write("*");
end
$display("");
end
end
endmodule |
module star_pattern_1;
integer i,j;
initial begin
for(i=1; i<10; i=i+1) begin
for(j=1; j<=i; j=j+1) begin
$write("*");
end
$display("");
end
end
endmodule |
module number_pattern_1;
integer i,j;
initial begin
for(i=0; i<10; i=i+1) begin
for(j=0; j<=i; j=j+1) begin
$write("%0d ",j+1);
end
$display("");
end
end
endmodule |
module number_pattern_4;
integer i,j;
integer n=1;
initial begin
for(i=0;i<=9;i=i+1)begin
for(j=0;j<9-i;j=j+1)begin
$write("%0d ",n+i);
end
$display("");
end
end
endmodule |
module number_pattern_3;
integer i,j;
integer n=1;
initial begin
for(i=0;i<=8;i=i+1)begin
for(j=0;j<=i;j=j+1)begin
$write("%0d ",n+i);
end
$display("");
end
end
endmodule |
module number_pattern_2;
integer i,j;
initial begin
for(i=0;i<=10;i=i+1)begin
for(j=1;j<=10-i;j=j+1)begin
$write("%0d ",j);
end
$display("");
end
end
endmodule |
module test_bitonic_sorting_top;
// Parameters
parameter LOG_INPUT_NUM = 4;
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 4;
parameter SIGNED = 1;
parameter ASCENDING = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [DATA_WIDTH-1 : 0] x_4 = 0;
reg [DATA_WIDTH-1 : 0] x_5 = 0;
reg [DATA_WIDTH-1 : 0] x_6 = 0;
reg [DATA_WIDTH-1 : 0] x_7 = 0;
reg [DATA_WIDTH-1 : 0] x_8 = 0;
reg [DATA_WIDTH-1 : 0] x_9 = 0;
reg [DATA_WIDTH-1 : 0] x_10 = 0;
reg [DATA_WIDTH-1 : 0] x_11 = 0;
reg [DATA_WIDTH-1 : 0] x_12 = 0;
reg [DATA_WIDTH-1 : 0] x_13 = 0;
reg [DATA_WIDTH-1 : 0] x_14 = 0;
reg [DATA_WIDTH-1 : 0] x_15 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_4 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_5 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_6 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_7 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_8 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_9 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_10 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_11 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_12 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_13 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_14 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_15 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [DATA_WIDTH-1 : 0] y_4;
wire [DATA_WIDTH-1 : 0] y_5;
wire [DATA_WIDTH-1 : 0] y_6;
wire [DATA_WIDTH-1 : 0] y_7;
wire [DATA_WIDTH-1 : 0] y_8;
wire [DATA_WIDTH-1 : 0] y_9;
wire [DATA_WIDTH-1 : 0] y_10;
wire [DATA_WIDTH-1 : 0] y_11;
wire [DATA_WIDTH-1 : 0] y_12;
wire [DATA_WIDTH-1 : 0] y_13;
wire [DATA_WIDTH-1 : 0] y_14;
wire [DATA_WIDTH-1 : 0] y_15;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire [LABEL_WIDTH-1 : 0] y_label_4;
wire [LABEL_WIDTH-1 : 0] y_label_5;
wire [LABEL_WIDTH-1 : 0] y_label_6;
wire [LABEL_WIDTH-1 : 0] y_label_7;
wire [LABEL_WIDTH-1 : 0] y_label_8;
wire [LABEL_WIDTH-1 : 0] y_label_9;
wire [LABEL_WIDTH-1 : 0] y_label_10;
wire [LABEL_WIDTH-1 : 0] y_label_11;
wire [LABEL_WIDTH-1 : 0] y_label_12;
wire [LABEL_WIDTH-1 : 0] y_label_13;
wire [LABEL_WIDTH-1 : 0] y_label_14;
wire [LABEL_WIDTH-1 : 0] y_label_15;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
x_0,
x_1,
x_2,
x_3,
x_4,
x_5,
x_6,
x_7,
x_8,
x_9,
x_10,
x_11,
x_12,
x_13,
x_14,
x_15,
x_label_0,
x_label_1,
x_label_2,
x_label_3,
x_label_4,
x_label_5,
x_label_6,
x_label_7,
x_label_8,
x_label_9,
x_label_10,
x_label_11,
x_label_12,
x_label_13,
x_label_14,
x_label_15,
x_valid
);
$to_myhdl(
y_0,
y_1,
y_2,
y_3,
y_4,
y_5,
y_6,
y_7,
y_8,
y_9,
y_10,
y_11,
y_12,
y_13,
y_14,
y_15,
y_label_0,
y_label_1,
y_label_2,
y_label_3,
y_label_4,
y_label_5,
y_label_6,
y_label_7,
y_label_8,
y_label_9,
y_label_10,
y_label_11,
y_label_12,
y_label_13,
y_label_14,
y_label_15,
y_valid
);
// dump file
$dumpfile("test_bitonic_sorting_top.lxt");
$dumpvars(0, test_bitonic_sorting_top);
end
bitonic_sorting_top #(
.LOG_INPUT_NUM(LOG_INPUT_NUM),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x({x_15, x_14, x_13, x_12, x_11, x_10, x_9, x_8, x_7, x_6, x_5, x_4, x_3, x_2, x_1, x_0}),
.x_label({x_label_15, x_label_14, x_label_13, x_label_12, x_label_11, x_label_10, x_label_9, x_label_8, x_label_7, x_label_6, x_label_5, x_label_4, x_label_3, x_label_2, x_label_1, x_label_0}),
.y({y_15, y_14, y_13, y_12, y_11, y_10, y_9, y_8, y_7, y_6, y_5, y_4, y_3, y_2, y_1, y_0}),
.y_label({y_label_15, y_label_14, y_label_13, y_label_12, y_label_11, y_label_10, y_label_9, y_label_8, y_label_7, y_label_6, y_label_5, y_label_4, y_label_3, y_label_2, y_label_1, y_label_0}),
.y_valid(y_valid)
);
endmodule |
module test_input_2;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 1;
parameter SIGNED = 1;
parameter ASCENDING = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
x_0,
x_1,
x_label_0,
x_label_1,
x_valid
);
$to_myhdl(
y_0,
y_1,
y_label_0,
y_label_1,
y_valid
);
// dump file
$dumpfile("test_input_2.lxt");
$dumpvars(0, test_input_2);
end
input_2 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_1),
.x_label_0(x_label_0),
.x_label_1(x_label_1),
.y_0(y_0),
.y_1(y_1),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_valid(y_valid)
);
endmodule |
module bitonic_sorting_top #
(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
output y_valid
);
bitonic_sorting_recursion #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
bitonic_sorting_inst
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x),
.x_label(x_label),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
endmodule |
module bitonic_sorting_recursion_submodule #
(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 4,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
output y_valid
);
if (LOG_INPUT_NUM > 1) begin
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1: 0] stage0_labl;
wire stage0_valid;
genvar i;
// Stage 1
// Stage0_0~2**(n-1)-1 has the same ascending feature with the entire network output.
for ( i = 0; i < (2**(LOG_INPUT_NUM-1)); i = i + 1) begin: stage0
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
.x_1(x[DATA_WIDTH*(i+1+(2**(LOG_INPUT_NUM-1)))-1:DATA_WIDTH*(i+(2**(LOG_INPUT_NUM-1)))]),
.x_label_0(x_label[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
.x_label_1(x_label[LABEL_WIDTH*(i+1+(2**(LOG_INPUT_NUM-1)))-1:LABEL_WIDTH*(i+(2**(LOG_INPUT_NUM-1)))]),
.y_0(stage0_rslt[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
.y_1(stage0_rslt[DATA_WIDTH*(i+1+(2**(LOG_INPUT_NUM-1)))-1:DATA_WIDTH*(i+(2**(LOG_INPUT_NUM-1)))]),
.y_label_0(stage0_labl[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
.y_label_1(stage0_labl[LABEL_WIDTH*(i+1+(2**(LOG_INPUT_NUM-1)))-1:LABEL_WIDTH*(i+(2**(LOG_INPUT_NUM-1)))]),
.y_valid(stage0_valid)
);
end
// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
bitonic_sorting_recursion_submodule #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM-1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
inst_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.x_label(stage0_labl[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y(y[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_label(y_label[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_valid(y_valid)
);
bitonic_sorting_recursion_submodule #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM-1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
inst_stage1_1
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.x_label(stage0_labl[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y(y[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_label(y_label[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_valid()
);
end else if (LOG_INPUT_NUM == 1) begin
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH-1:0]),
.x_1(x[DATA_WIDTH*2-1:DATA_WIDTH]),
.x_label_0(x_label[LABEL_WIDTH-1:0]),
.x_label_1(x_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_0(y[DATA_WIDTH-1:0]),
.y_1(y[DATA_WIDTH*2-1:DATA_WIDTH]),
.y_label_0(y_label[LABEL_WIDTH-1:0]),
.y_label_1(y_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_valid(y_valid)
);
end
endmodule |
module bitonic_sorting_recursion #
(
parameter LOG_INPUT_NUM = 4, // Eg: If LOG_INPUT_NUM=4, then input number is 2**4=16
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = LOG_INPUT_NUM,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x,
input [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] x_label,
output [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y,
output [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] y_label,
output y_valid
);
if (LOG_INPUT_NUM > 1) begin
// Declare the wires which come out of the 2 2**(n-1)-input comparators with opposite ascending feature.
wire [DATA_WIDTH*(2**LOG_INPUT_NUM)-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*(2**LOG_INPUT_NUM)-1: 0] stage0_labl;
wire stage0_valid;
// Stage 1, use two 2**(n-1)-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
bitonic_sorting_recursion #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM-1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
inst_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.x_label(x_label[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y(stage0_rslt[DATA_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_label(stage0_labl[LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))-1:0]),
.y_valid(stage0_valid)
);
bitonic_sorting_recursion #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM-1),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(1-ASCENDING)
)
inst_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.x_label(x_label[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y(stage0_rslt[DATA_WIDTH*(2**LOG_INPUT_NUM)-1:DATA_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_label(stage0_labl[LABEL_WIDTH*(2**LOG_INPUT_NUM)-1:LABEL_WIDTH*(2**(LOG_INPUT_NUM-1))]),
.y_valid()
);
// Stage 2, use a 2**n-input bitonic submodule to sort the outputs of the stage 1.
// bitonic_sorting_resursion_submodule should have the same ascending feature with the entire network output.
bitonic_sorting_recursion_submodule #
(
.LOG_INPUT_NUM(LOG_INPUT_NUM),
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
inst_stage1
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt),
.x_label(stage0_labl),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
end else if (LOG_INPUT_NUM == 1) begin
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH-1:0]),
.x_1(x[DATA_WIDTH*2-1:DATA_WIDTH]),
.x_label_0(x_label[LABEL_WIDTH-1:0]),
.x_label_1(x_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_0(y[DATA_WIDTH-1:0]),
.y_1(y[DATA_WIDTH*2-1:DATA_WIDTH]),
.y_label_0(y_label[LABEL_WIDTH-1:0]),
.y_label_1(y_label[LABEL_WIDTH*2-1:LABEL_WIDTH]),
.y_valid(y_valid)
);
end
endmodule |
module input_2 #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 1,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH-1 : 0] x_0, x_1,
input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1,
output reg [DATA_WIDTH-1 : 0] y_0, y_1,
output reg [LABEL_WIDTH-1 : 0] y_label_0, y_label_1,
output reg y_valid
);
always @ (posedge clk)
begin
if (rst == 1'b1) begin
y_0 <= 0;
y_1 <= 0;
y_valid <= 0;
end else begin
y_valid <= x_valid;
if (SIGNED == 0) begin
if (ASCENDING == 1) begin
if ($unsigned(x_0) < $unsigned(x_1)) begin
y_0 <= x_0;
y_label_0 <= x_label_0;
y_1 <= x_1;
y_label_1 <= x_label_1;
end else begin
y_0 <= x_1;
y_label_0 <= x_label_1;
y_1 <= x_0;
y_label_1 <= x_label_0;
end
end else if (ASCENDING == 0) begin
if ($unsigned(x_0) > $unsigned(x_1)) begin
y_0 <= x_0;
y_label_0 <= x_label_0;
y_1 <= x_1;
y_label_1 <= x_label_1;
end else begin
y_0 <= x_1;
y_label_0 <= x_label_1;
y_1 <= x_0;
y_label_1 <= x_label_0;
end
end
end else if (SIGNED == 1) begin
if (ASCENDING == 1) begin
if ($signed(x_0) < $signed(x_1)) begin
y_0 <= x_0;
y_label_0 <= x_label_0;
y_1 <= x_1;
y_label_1 <= x_label_1;
end else begin
y_0 <= x_1;
y_label_0 <= x_label_1;
y_1 <= x_0;
y_label_1 <= x_label_0;
end
end else if (ASCENDING == 0) begin
if ($signed(x_0) > $signed(x_1)) begin
y_0 <= x_0;
y_label_0 <= x_label_0;
y_1 <= x_1;
y_label_1 <= x_label_1;
end else begin
y_0 <= x_1;
y_label_0 <= x_label_1;
y_1 <= x_0;
y_label_1 <= x_label_0;
end
end
end
end
end
endmodule |
module test_input_4;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 2;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
x_0,
x_1,
x_2,
x_3,
x_label_0,
x_label_1,
x_label_2,
x_label_3,
x_valid
);
$to_myhdl(
y_0,
y_1,
y_2,
y_3,
y_label_0,
y_label_1,
y_label_2,
y_label_3,
y_valid
);
// dump file
$dumpfile("test_input_4.lxt");
$dumpvars(0, test_input_4);
end
input_4 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_1),
.x_2(x_2),
.x_3(x_3),
.x_label_0(x_label_0),
.x_label_1(x_label_1),
.x_label_2(x_label_2),
.x_label_3(x_label_3),
.y_0(y_0),
.y_1(y_1),
.y_2(y_2),
.y_3(y_3),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_label_2(y_label_2),
.y_label_3(y_label_3),
.y_valid(y_valid)
);
endmodule |
module test_input_8;
// Parameters
parameter DATA_WIDTH = 8;
parameter LABEL_WIDTH = 3;
parameter SIGNED = 1;
parameter ASCENDING = 0;
// Inputs
reg clk = 0;
reg rst = 0;
reg x_valid = 0;
reg [DATA_WIDTH-1 : 0] x_0 = 0;
reg [DATA_WIDTH-1 : 0] x_1 = 0;
reg [DATA_WIDTH-1 : 0] x_2 = 0;
reg [DATA_WIDTH-1 : 0] x_3 = 0;
reg [DATA_WIDTH-1 : 0] x_4 = 0;
reg [DATA_WIDTH-1 : 0] x_5 = 0;
reg [DATA_WIDTH-1 : 0] x_6 = 0;
reg [DATA_WIDTH-1 : 0] x_7 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_0 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_1 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_2 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_3 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_4 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_5 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_6 = 0;
reg [LABEL_WIDTH-1 : 0] x_label_7 = 0;
// Outputs
wire [DATA_WIDTH-1 : 0] y_0;
wire [DATA_WIDTH-1 : 0] y_1;
wire [DATA_WIDTH-1 : 0] y_2;
wire [DATA_WIDTH-1 : 0] y_3;
wire [DATA_WIDTH-1 : 0] y_4;
wire [DATA_WIDTH-1 : 0] y_5;
wire [DATA_WIDTH-1 : 0] y_6;
wire [DATA_WIDTH-1 : 0] y_7;
wire [LABEL_WIDTH-1 : 0] y_label_0;
wire [LABEL_WIDTH-1 : 0] y_label_1;
wire [LABEL_WIDTH-1 : 0] y_label_2;
wire [LABEL_WIDTH-1 : 0] y_label_3;
wire [LABEL_WIDTH-1 : 0] y_label_4;
wire [LABEL_WIDTH-1 : 0] y_label_5;
wire [LABEL_WIDTH-1 : 0] y_label_6;
wire [LABEL_WIDTH-1 : 0] y_label_7;
wire y_valid;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
x_0,
x_1,
x_2,
x_3,
x_4,
x_5,
x_6,
x_7,
x_label_0,
x_label_1,
x_label_2,
x_label_3,
x_label_4,
x_label_5,
x_label_6,
x_label_7,
x_valid
);
$to_myhdl(
y_0,
y_1,
y_2,
y_3,
y_4,
y_5,
y_6,
y_7,
y_label_0,
y_label_1,
y_label_2,
y_label_3,
y_label_4,
y_label_5,
y_label_6,
y_label_7,
y_valid
);
// dump file
$dumpfile("test_input_8.lxt");
$dumpvars(0, test_input_8);
end
input_8 #(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
UUT (
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x({x_7, x_6, x_5, x_4, x_3, x_2, x_1, x_0}),
.x_label({x_label_7, x_label_6, x_label_5, x_label_4, x_label_3, x_label_2, x_label_1, x_label_0}),
.y({y_7, y_6, y_5, y_4, y_3, y_2, y_1, y_0}),
.y_label({y_label_7, y_label_6, y_label_5, y_label_4, y_label_3, y_label_2, y_label_1, y_label_0}),
.y_valid(y_valid)
);
endmodule |
module input_4 #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 1,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH-1 : 0] x_0, x_1, x_2, x_3,
input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1, x_label_2, x_label_3,
output [DATA_WIDTH-1 : 0] y_0, y_1, y_2, y_3,
output [LABEL_WIDTH-1 : 0] y_label_0, y_label_1, y_label_2, y_label_3,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH-1 : 0] stage0_rslt_0, stage0_rslt_1, stage0_rslt_2, stage0_rslt_3;
wire [LABEL_WIDTH-1: 0] stage0_labl_0, stage0_labl_1, stage0_labl_2, stage0_labl_3;
wire stage0_valid;
// Stage 1, use two 2-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_1),
.x_label_0(x_label_0),
.x_label_1(x_label_1),
.y_0(stage0_rslt_0),
.y_1(stage0_rslt_1),
.y_label_0(stage0_labl_0),
.y_label_1(stage0_labl_1),
.y_valid(stage0_valid)
);
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(1-ASCENDING)
)
input_2_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_2),
.x_1(x_3),
.x_label_0(x_label_2),
.x_label_1(x_label_3),
.y_0(stage0_rslt_2),
.y_1(stage0_rslt_3),
.y_label_0(stage0_labl_2),
.y_label_1(stage0_labl_3),
.y_valid()
);
// Stage 2, use a 4-input bitonic required compare network to sort the outputs of the stage 1.
// input_4_bitonic_required module should have the same ascending feature with the entire network output.
input_4_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_4_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x_0(stage0_rslt_0),
.x_1(stage0_rslt_1),
.x_2(stage0_rslt_2),
.x_3(stage0_rslt_3),
.x_label_0(stage0_labl_0),
.x_label_1(stage0_labl_1),
.x_label_2(stage0_labl_2),
.x_label_3(stage0_labl_3),
.y_0(y_0),
.y_1(y_1),
.y_2(y_2),
.y_3(y_3),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_label_2(y_label_2),
.y_label_3(y_label_3),
.y_valid(y_valid)
);
endmodule |
module input_8_bitonic_required #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 3,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH*8-1 : 0] x,
input [LABEL_WIDTH*8-1 : 0] x_label,
output [DATA_WIDTH*8-1 : 0] y,
output [LABEL_WIDTH*8-1 : 0] y_label,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*8-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*8-1: 0] stage0_labl;
wire stage0_valid;
genvar i;
// Stage 1
// Stage0~3 has the same ascending feature with the entire network output.
for (i = 0; i < 4; i = i + 1) begin: stage0
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH*(i+1)-1:DATA_WIDTH*(i)]),
.x_1(x[DATA_WIDTH*(i+5)-1:DATA_WIDTH*(i+4)]),
.x_label_0(x_label[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*(i)]),
.x_label_1(x_label[LABEL_WIDTH*(i+5)-1:LABEL_WIDTH*(i+4)]),
.y_0(stage0_rslt[DATA_WIDTH*(i+1)-1:DATA_WIDTH*(i)]),
.y_1(stage0_rslt[DATA_WIDTH*(i+5)-1:DATA_WIDTH*(i+4)]),
.y_label_0(stage0_labl[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*(i)]),
.y_label_1(stage0_labl[LABEL_WIDTH*(i+5)-1:LABEL_WIDTH*(i+4)]),
.y_valid(stage0_valid)
);
end
// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
input_4_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_4_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x_0(stage0_rslt[DATA_WIDTH*1-1:0]),
.x_1(stage0_rslt[DATA_WIDTH*2-1:DATA_WIDTH*1]),
.x_2(stage0_rslt[DATA_WIDTH*3-1:DATA_WIDTH*2]),
.x_3(stage0_rslt[DATA_WIDTH*4-1:DATA_WIDTH*3]),
.x_label_0(stage0_labl[LABEL_WIDTH*1-1:0]),
.x_label_1(stage0_labl[LABEL_WIDTH*2-1:LABEL_WIDTH*1]),
.x_label_2(stage0_labl[LABEL_WIDTH*3-1:LABEL_WIDTH*2]),
.x_label_3(stage0_labl[LABEL_WIDTH*4-1:LABEL_WIDTH*3]),
.y_0(y[DATA_WIDTH*1-1:0]),
.y_1(y[DATA_WIDTH*2-1:DATA_WIDTH*1]),
.y_2(y[DATA_WIDTH*3-1:DATA_WIDTH*2]),
.y_3(y[DATA_WIDTH*4-1:DATA_WIDTH*3]),
.y_label_0(y_label[LABEL_WIDTH*1-1:0]),
.y_label_1(y_label[LABEL_WIDTH*2-1:LABEL_WIDTH*1]),
.y_label_2(y_label[LABEL_WIDTH*3-1:LABEL_WIDTH*2]),
.y_label_3(y_label[LABEL_WIDTH*4-1:LABEL_WIDTH*3]),
.y_valid(y_valid)
);
input_4_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_4_stage1_1
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x_0(stage0_rslt[DATA_WIDTH*5-1:DATA_WIDTH*4]),
.x_1(stage0_rslt[DATA_WIDTH*6-1:DATA_WIDTH*5]),
.x_2(stage0_rslt[DATA_WIDTH*7-1:DATA_WIDTH*6]),
.x_3(stage0_rslt[DATA_WIDTH*8-1:DATA_WIDTH*7]),
.x_label_0(stage0_labl[LABEL_WIDTH*5-1:LABEL_WIDTH*4]),
.x_label_1(stage0_labl[LABEL_WIDTH*6-1:LABEL_WIDTH*5]),
.x_label_2(stage0_labl[LABEL_WIDTH*7-1:LABEL_WIDTH*6]),
.x_label_3(stage0_labl[LABEL_WIDTH*8-1:LABEL_WIDTH*7]),
.y_0(y[DATA_WIDTH*5-1:DATA_WIDTH*4]),
.y_1(y[DATA_WIDTH*6-1:DATA_WIDTH*5]),
.y_2(y[DATA_WIDTH*7-1:DATA_WIDTH*6]),
.y_3(y[DATA_WIDTH*8-1:DATA_WIDTH*7]),
.y_label_0(y_label[LABEL_WIDTH*5-1:LABEL_WIDTH*4]),
.y_label_1(y_label[LABEL_WIDTH*6-1:LABEL_WIDTH*5]),
.y_label_2(y_label[LABEL_WIDTH*7-1:LABEL_WIDTH*6]),
.y_label_3(y_label[LABEL_WIDTH*8-1:LABEL_WIDTH*7]),
.y_valid()
);
endmodule |
module input_16 #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 1,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH*16-1 : 0] x,
input [LABEL_WIDTH*16-1 : 0] x_label,
output [DATA_WIDTH*16-1 : 0] y,
output [LABEL_WIDTH*16-1 : 0] y_label,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*16-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*16-1: 0] stage0_labl;
wire stage0_valid;
// Stage 1, use two 8-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
input_8 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_8_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*8-1:0]),
.x_label(x_label[LABEL_WIDTH*8-1:0]),
.y(stage0_rslt[DATA_WIDTH*8-1:0]),
.y_label(stage0_labl[LABEL_WIDTH*8-1:0]),
.y_valid(stage0_valid)
);
input_8 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(1-ASCENDING)
)
input_8_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x(x[DATA_WIDTH*16-1:DATA_WIDTH*8]),
.x_label(x_label[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
.y(stage0_rslt[DATA_WIDTH*16-1:DATA_WIDTH*8]),
.y_label(stage0_labl[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
.y_valid()
);
// Stage 2, use a 8-input bitonic required compare network to sort the outputs of the stage 1.
// input_8_bitonic_required module should have the same ascending feature with the entire network output.
input_16_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_16_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt),
.x_label(stage0_labl),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
endmodule |
module input_16_bitonic_required #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 4,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
// Put all the inputs into one vector.
// x[DATA_WIDTH-1 : 0] is the first input x_0,
// x[DATA_WIDTH*2-1 : DATA_WIDTH] is the second input x_1, etc.
input [DATA_WIDTH*16-1 : 0] x,
input [LABEL_WIDTH*16-1 : 0] x_label,
output [DATA_WIDTH*16-1 : 0] y,
output [LABEL_WIDTH*16-1 : 0] y_label,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*16-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*16-1: 0] stage0_labl;
wire stage0_valid;
genvar i;
// Stage 1
// Stage0_0~7 has the same ascending feature with the entire network output.
for ( i = 0; i < 8; i = i + 1) begin: stage0
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
.x_1(x[DATA_WIDTH*(i+9)-1:DATA_WIDTH*(i+8)]),
.x_label_0(x_label[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
.x_label_1(x_label[LABEL_WIDTH*(i+9)-1:LABEL_WIDTH*(i+8)]),
.y_0(stage0_rslt[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i]),
.y_1(stage0_rslt[DATA_WIDTH*(i+9)-1:DATA_WIDTH*(i+8)]),
.y_label_0(stage0_labl[LABEL_WIDTH*(i+1)-1:LABEL_WIDTH*i]),
.y_label_1(stage0_labl[LABEL_WIDTH*(i+9)-1:LABEL_WIDTH*(i+8)]),
.y_valid(stage0_valid)
);
end
// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
input_8_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_8_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt[DATA_WIDTH*8-1:0]),
.x_label(stage0_labl[LABEL_WIDTH*8-1:0]),
.y(y[DATA_WIDTH*8-1:0]),
.y_label(y_label[LABEL_WIDTH*8-1:0]),
.y_valid(y_valid)
);
input_8_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_8_stage1_1
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt[DATA_WIDTH*16-1:DATA_WIDTH*8]),
.x_label(stage0_labl[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
.y(y[DATA_WIDTH*16-1:DATA_WIDTH*8]),
.y_label(y_label[LABEL_WIDTH*16-1:LABEL_WIDTH*8]),
.y_valid()
);
endmodule |
module input_4_bitonic_required #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 1,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH-1 : 0] x_0, x_1, x_2, x_3,
input [LABEL_WIDTH-1 : 0] x_label_0, x_label_1, x_label_2, x_label_3,
output [DATA_WIDTH-1 : 0] y_0, y_1, y_2, y_3,
output [LABEL_WIDTH-1 : 0] y_label_0, y_label_1, y_label_2, y_label_3,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH-1 : 0] stage0_rslt_0, stage0_rslt_1, stage0_rslt_2, stage0_rslt_3;
wire [LABEL_WIDTH-1: 0] stage0_labl_0, stage0_labl_1, stage0_labl_2, stage0_labl_3;
wire stage0_valid;
// Stage 1
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the same ascending feature with the entire network output as well.
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_0),
.x_1(x_2),
.x_label_0(x_label_0),
.x_label_1(x_label_2),
.y_0(stage0_rslt_0),
.y_1(stage0_rslt_2),
.y_label_0(stage0_labl_0),
.y_label_1(stage0_labl_2),
.y_valid(stage0_valid)
);
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x_1),
.x_1(x_3),
.x_label_0(x_label_1),
.x_label_1(x_label_3),
.y_0(stage0_rslt_1),
.y_1(stage0_rslt_3),
.y_label_0(stage0_labl_1),
.y_label_1(stage0_labl_3),
.y_valid()
);
// Stage 2
// Stage1_0 has the same ascending feature with the entire network output.
// Stage1_1 has the same ascending feature with the entire network output as well.
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x_0(stage0_rslt_0),
.x_1(stage0_rslt_1),
.x_label_0(stage0_labl_0),
.x_label_1(stage0_labl_1),
.y_0(y_0),
.y_1(y_1),
.y_label_0(y_label_0),
.y_label_1(y_label_1),
.y_valid(y_valid)
);
input_2 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_2_stage1_1
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x_0(stage0_rslt_2),
.x_1(stage0_rslt_3),
.x_label_0(stage0_labl_2),
.x_label_1(stage0_labl_3),
.y_0(y_2),
.y_1(y_3),
.y_label_0(y_label_2),
.y_label_1(y_label_3),
.y_valid()
);
endmodule |
module input_8 #
(
parameter DATA_WIDTH = 8,
parameter LABEL_WIDTH = 1,
parameter SIGNED = 0,
parameter ASCENDING = 1
)
(
input clk, rst, x_valid,
input [DATA_WIDTH*8-1 : 0] x,
input [LABEL_WIDTH*8-1 : 0] x_label,
output [DATA_WIDTH*8-1 : 0] y,
output [LABEL_WIDTH*8-1 : 0] y_label,
output y_valid
);
// Declare the wires which come out of the input_2 compare network of every stage
wire [DATA_WIDTH*8-1 : 0] stage0_rslt;
wire [LABEL_WIDTH*8-1: 0] stage0_labl;
wire stage0_valid;
// Stage 1, use two 4-input comparators with opposite ascending features to sort.
// Stage0_0 has the same ascending feature with the entire network output.
// Stage0_1 has the opposite ascending feature with the entire network output.
input_4 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_4_stage0_0
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH*1-1:0]),
.x_1(x[DATA_WIDTH*2-1:DATA_WIDTH*1]),
.x_2(x[DATA_WIDTH*3-1:DATA_WIDTH*2]),
.x_3(x[DATA_WIDTH*4-1:DATA_WIDTH*3]),
.x_label_0(x_label[LABEL_WIDTH*1-1:0]),
.x_label_1(x_label[LABEL_WIDTH*2-1:LABEL_WIDTH*1]),
.x_label_2(x_label[LABEL_WIDTH*3-1:LABEL_WIDTH*2]),
.x_label_3(x_label[LABEL_WIDTH*4-1:LABEL_WIDTH*3]),
.y_0(stage0_rslt[DATA_WIDTH*1-1:0]),
.y_1(stage0_rslt[DATA_WIDTH*2-1:DATA_WIDTH*1]),
.y_2(stage0_rslt[DATA_WIDTH*3-1:DATA_WIDTH*2]),
.y_3(stage0_rslt[DATA_WIDTH*4-1:DATA_WIDTH*3]),
.y_label_0(stage0_labl[LABEL_WIDTH*1-1:0]),
.y_label_1(stage0_labl[LABEL_WIDTH*2-1:LABEL_WIDTH*1]),
.y_label_2(stage0_labl[LABEL_WIDTH*3-1:LABEL_WIDTH*2]),
.y_label_3(stage0_labl[LABEL_WIDTH*4-1:LABEL_WIDTH*3]),
.y_valid(stage0_valid)
);
input_4 #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(1-ASCENDING)
)
input_4_stage0_1
(
.clk(clk),
.rst(rst),
.x_valid(x_valid),
.x_0(x[DATA_WIDTH*5-1:DATA_WIDTH*4]),
.x_1(x[DATA_WIDTH*6-1:DATA_WIDTH*5]),
.x_2(x[DATA_WIDTH*7-1:DATA_WIDTH*6]),
.x_3(x[DATA_WIDTH*8-1:DATA_WIDTH*7]),
.x_label_0(x_label[LABEL_WIDTH*5-1:LABEL_WIDTH*4]),
.x_label_1(x_label[LABEL_WIDTH*6-1:LABEL_WIDTH*5]),
.x_label_2(x_label[LABEL_WIDTH*7-1:LABEL_WIDTH*6]),
.x_label_3(x_label[LABEL_WIDTH*8-1:LABEL_WIDTH*7]),
.y_0(stage0_rslt[DATA_WIDTH*5-1:DATA_WIDTH*4]),
.y_1(stage0_rslt[DATA_WIDTH*6-1:DATA_WIDTH*5]),
.y_2(stage0_rslt[DATA_WIDTH*7-1:DATA_WIDTH*6]),
.y_3(stage0_rslt[DATA_WIDTH*8-1:DATA_WIDTH*7]),
.y_label_0(stage0_labl[LABEL_WIDTH*5-1:LABEL_WIDTH*4]),
.y_label_1(stage0_labl[LABEL_WIDTH*6-1:LABEL_WIDTH*5]),
.y_label_2(stage0_labl[LABEL_WIDTH*7-1:LABEL_WIDTH*6]),
.y_label_3(stage0_labl[LABEL_WIDTH*8-1:LABEL_WIDTH*7]),
.y_valid()
);
// Stage 2, use a 8-input bitonic required compare network to sort the outputs of the stage 1.
// input_8_bitonic_required module should have the same ascending feature with the entire network output.
input_8_bitonic_required #
(
.DATA_WIDTH(DATA_WIDTH),
.LABEL_WIDTH(LABEL_WIDTH),
.SIGNED(SIGNED),
.ASCENDING(ASCENDING)
)
input_8_stage1_0
(
.clk(clk),
.rst(rst),
.x_valid(stage0_valid),
.x(stage0_rslt),
.x_label(stage0_labl),
.y(y),
.y_label(y_label),
.y_valid(y_valid)
);
endmodule |
module aes_rcon(clk, kld, out);
input clk;
input kld;
output [31:0] out;
reg [31:0] out;
reg [3:0] rcnt;
wire [3:0] rcnt_next;
always @(posedge clk)
if(kld) out <= #1 32'h01_00_00_00;
else out <= #1 frcon(rcnt_next);
assign rcnt_next = rcnt + 4'h1;
always @(posedge clk)
if(kld) rcnt <= #1 4'h0;
else rcnt <= #1 rcnt_next;
function [31:0] frcon;
input [3:0] i;
(* parallel_case *) case(i)
4'h0: frcon=32'h01_00_00_00;
4'h1: frcon=32'h02_00_00_00;
4'h2: frcon=32'h04_00_00_00;
4'h3: frcon=32'h08_00_00_00;
4'h4: frcon=32'h10_00_00_00;
4'h5: frcon=32'h20_00_00_00;
4'h6: frcon=32'h40_00_00_00;
4'h7: frcon=32'h80_00_00_00;
4'h8: frcon=32'h1b_00_00_00;
4'h9: frcon=32'h36_00_00_00;
default: frcon=32'h00_00_00_00;
endcase
endfunction
endmodule |
module sha3_core(
input wire clk,
input wire reset_n,
input wire init,
input wire next,
input wire [1 : 0] mode,
input wire work_factor,
input wire [31 : 0] work_factor_num,
input wire [1023 : 0] block,
output wire ready,
output wire [511 : 0] digest,
output wire digest_valid
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA512_ROUNDS = 79;
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [63 : 0] a_reg;
reg [63 : 0] a_new;
reg [63 : 0] b_reg;
reg [63 : 0] b_new;
reg [63 : 0] c_reg;
reg [63 : 0] c_new;
reg [63 : 0] d_reg;
reg [63 : 0] d_new;
reg [63 : 0] e_reg;
reg [63 : 0] e_new;
reg [63 : 0] f_reg;
reg [63 : 0] f_new;
reg [63 : 0] g_reg;
reg [63 : 0] g_new;
reg [63 : 0] h_reg;
reg [63 : 0] h_new;
reg a_h_we;
reg [63 : 0] H0_reg;
reg [63 : 0] H0_new;
reg [63 : 0] H1_reg;
reg [63 : 0] H1_new;
reg [63 : 0] H2_reg;
reg [63 : 0] H2_new;
reg [63 : 0] H3_reg;
reg [63 : 0] H3_new;
reg [63 : 0] H4_reg;
reg [63 : 0] H4_new;
reg [63 : 0] H5_reg;
reg [63 : 0] H5_new;
reg [63 : 0] H6_reg;
reg [63 : 0] H6_new;
reg [63 : 0] H7_reg;
reg [63 : 0] H7_new;
reg H_we;
reg [6 : 0] t_ctr_reg;
reg [6 : 0] t_ctr_new;
reg t_ctr_we;
reg t_ctr_inc;
reg t_ctr_rst;
reg [31 : 0] work_factor_ctr_reg;
reg [31 : 0] work_factor_ctr_new;
reg work_factor_ctr_rst;
reg work_factor_ctr_inc;
reg work_factor_ctr_done;
reg work_factor_ctr_we;
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
reg [1 : 0] sha512_ctrl_reg;
reg [1 : 0] sha512_ctrl_new;
reg sha512_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg digest_init;
reg digest_update;
reg state_init;
reg state_update;
reg first_block;
reg ready_flag;
reg [63 : 0] t1;
reg [63 : 0] t2;
wire [63 : 0] k_data;
reg w_init;
reg w_next;
wire [63 : 0] w_data;
wire [63 : 0] H0_0;
wire [63 : 0] H0_1;
wire [63 : 0] H0_2;
wire [63 : 0] H0_3;
wire [63 : 0] H0_4;
wire [63 : 0] H0_5;
wire [63 : 0] H0_6;
wire [63 : 0] H0_7;
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
assign digest_valid = digest_valid_reg;
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
// All registers are positive edge triggered with asynchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin : reg_update
if (!reset_n)
begin
a_reg <= 64'h0000000000000000;
b_reg <= 64'h0000000000000000;
c_reg <= 64'h0000000000000000;
d_reg <= 64'h0000000000000000;
e_reg <= 64'h0000000000000000;
f_reg <= 64'h0000000000000000;
g_reg <= 64'h0000000000000000;
h_reg <= 64'h0000000000000000;
H0_reg <= 64'h0000000000000000;
H1_reg <= 64'h0000000000000000;
H2_reg <= 64'h0000000000000000;
H3_reg <= 64'h0000000000000000;
H4_reg <= 64'h0000000000000000;
H5_reg <= 64'h0000000000000000;
H6_reg <= 64'h0000000000000000;
H7_reg <= 64'h0000000000000000;
work_factor_ctr_reg <= 32'h00000000;
digest_valid_reg <= 0;
t_ctr_reg <= 7'h00;
sha512_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (a_h_we)
begin
a_reg <= a_new;
b_reg <= b_new;
c_reg <= c_new;
d_reg <= d_new;
e_reg <= e_new;
f_reg <= f_new;
g_reg <= g_new;
h_reg <= h_new;
end
if (H_we)
begin
H0_reg <= H0_new;
H1_reg <= H1_new;
H2_reg <= H2_new;
H3_reg <= H3_new;
H4_reg <= H4_new;
H5_reg <= H5_new;
H6_reg <= H6_new;
H7_reg <= H7_new;
end
if (t_ctr_we)
begin
t_ctr_reg <= t_ctr_new;
end
if (work_factor_ctr_we)
begin
work_factor_ctr_reg <= work_factor_ctr_new;
end
if (digest_valid_we)
begin
digest_valid_reg <= digest_valid_new;
end
if (sha512_ctrl_we)
begin
sha512_ctrl_reg <= sha512_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// digest_logic
//
// The logic needed to init as well as update the digest.
//----------------------------------------------------------------
always @*
begin : digest_logic
H0_new = 64'h00000000;
H1_new = 64'h00000000;
H2_new = 64'h00000000;
H3_new = 64'h00000000;
H4_new = 64'h00000000;
H5_new = 64'h00000000;
H6_new = 64'h00000000;
H7_new = 64'h00000000;
H_we = 0;
if (digest_init)
begin
H0_new = H0_0;
H1_new = H0_1;
H2_new = H0_2;
H3_new = H0_3;
H4_new = H0_4;
H5_new = H0_5;
H6_new = H0_6;
H7_new = H0_7;
H_we = 1;
end
if (digest_update)
begin
H0_new = H0_reg + a_reg;
H1_new = H1_reg + b_reg;
H2_new = H2_reg + c_reg;
H3_new = H3_reg + d_reg;
H4_new = H4_reg + e_reg;
H5_new = H5_reg + f_reg;
H6_new = H6_reg + g_reg;
H7_new = H7_reg + h_reg;
H_we = 1;
end
end // digest_logic
//----------------------------------------------------------------
// t1_logic
//
// The logic for the T1 function.
//----------------------------------------------------------------
always @*
begin : t1_logic
reg [63 : 0] sum1;
reg [63 : 0] ch;
sum1 = {e_reg[13 : 0], e_reg[63 : 14]} ^
{e_reg[17 : 0], e_reg[63 : 18]} ^
{e_reg[40 : 0], e_reg[63 : 41]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
t1 = h_reg + sum1 + ch + k_data + w_data;
end // t1_logic
//----------------------------------------------------------------
// t2_logic
//
// The logic for the T2 function
//----------------------------------------------------------------
always @*
begin : t2_logic
reg [63 : 0] sum0;
reg [63 : 0] maj;
sum0 = {a_reg[27 : 0], a_reg[63 : 28]} ^
{a_reg[33 : 0], a_reg[63 : 34]} ^
{a_reg[38 : 0], a_reg[63 : 39]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
t2 = sum0 + maj;
end // t2_logic
//----------------------------------------------------------------
// state_logic
//
// The logic needed to init as well as update the state during
// round processing.
//----------------------------------------------------------------
always @*
begin : state_logic
a_new = 64'h00000000;
b_new = 64'h00000000;
c_new = 64'h00000000;
d_new = 64'h00000000;
e_new = 64'h00000000;
f_new = 64'h00000000;
g_new = 64'h00000000;
h_new = 64'h00000000;
a_h_we = 0;
if (state_init)
begin
if (first_block)
begin
a_new = H0_0;
b_new = H0_1;
c_new = H0_2;
d_new = H0_3;
e_new = H0_4;
f_new = H0_5;
g_new = H0_6;
h_new = H0_7;
a_h_we = 1;
end
else
begin
a_new = H0_reg;
b_new = H1_reg;
c_new = H2_reg;
d_new = H3_reg;
e_new = H4_reg;
f_new = H5_reg;
g_new = H6_reg;
h_new = H7_reg;
a_h_we = 1;
end
end
if (state_update)
begin
a_new = t1 + t2;
b_new = a_reg;
c_new = b_reg;
d_new = c_reg;
e_new = d_reg + t1;
f_new = e_reg;
g_new = f_reg;
h_new = g_reg;
a_h_we = 1;
end
end // state_logic
//----------------------------------------------------------------
// t_ctr
//
// Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 7'h00;
t_ctr_we = 0;
if (t_ctr_rst)
begin
t_ctr_new = 7'h00;
t_ctr_we = 1;
end
if (t_ctr_inc)
begin
t_ctr_new = t_ctr_reg + 1'b1;
t_ctr_we = 1;
end
end // t_ctr
//----------------------------------------------------------------
// work_factor_ctr
//
// Work factor counter logic.
//----------------------------------------------------------------
always @*
begin : work_factor_ctr
work_factor_ctr_new = 32'h00000000;
work_factor_ctr_we = 0;
work_factor_ctr_done = 0;
if (work_factor_ctr_reg == work_factor_num)
begin
work_factor_ctr_done = 1;
end
if (work_factor_ctr_rst)
begin
work_factor_ctr_new = 32'h00000000;
work_factor_ctr_we = 1;
end
if (work_factor_ctr_inc)
begin
work_factor_ctr_new = work_factor_ctr_reg + 1'b1;
work_factor_ctr_we = 1;
end
end // work_factor_ctr
//----------------------------------------------------------------
// sha512_ctrl_fsm
//
// Logic for the state machine controlling the core behaviour.
//----------------------------------------------------------------
always @*
begin : sha512_ctrl_fsm
digest_init = 0;
digest_update = 0;
state_init = 0;
state_update = 0;
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
t_ctr_inc = 0;
t_ctr_rst = 0;
digest_valid_new = 0;
digest_valid_we = 0;
work_factor_ctr_rst = 0;
work_factor_ctr_inc = 0;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 0;
case (sha512_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
if (init)
begin
work_factor_ctr_rst = 1;
digest_init = 1;
w_init = 1;
state_init = 1;
first_block = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
if (next)
begin
work_factor_ctr_rst = 1;
w_init = 1;
state_init = 1;
t_ctr_rst = 1;
digest_valid_new = 0;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
end
CTRL_ROUNDS:
begin
w_next = 1;
state_update = 1;
t_ctr_inc = 1;
if (t_ctr_reg == SHA512_ROUNDS)
begin
work_factor_ctr_inc = 1;
sha512_ctrl_new = CTRL_DONE;
sha512_ctrl_we = 1;
end
end
CTRL_DONE:
begin
if (work_factor)
begin
if (!work_factor_ctr_done)
begin
w_init = 1;
state_init = 1;
t_ctr_rst = 1;
sha512_ctrl_new = CTRL_ROUNDS;
sha512_ctrl_we = 1;
end
else
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1;
end
end
else
begin
digest_update = 1;
digest_valid_new = 1;
digest_valid_we = 1;
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 1;
end
end
endcase // case (sha512_ctrl_reg)
end // sha512_ctrl_fsm
endmodule |
module div_uu(clk, ena, z, d, q, s, div0, ovf);
//
// parameters
//
parameter z_width = 16;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
reg [d_width-1:0] q;
output [d_width -1:0] s; // remainder
reg [d_width-1:0] s;
output div0;
reg div0;
output ovf;
reg ovf;
//
// functions
//
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-4];
end
endfunction
//
// variables
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
//
// perform parameter checks
//
`ifdef SIMULATION
initial
begin
if(d_width !== z_width / 2)
$display("div.v parameter error (d_width != z_width/2).");
end
`endif
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= #1 d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= #1 gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= #1 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= #1 gen_q(q_pipe[n2-1], s_pipe[n2]);
// flags (divide_by_zero, overflow)
always @(z or d)
begin
ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= #1 ovf_pipe[n3-1];
div0_pipe[n3] <= #1 div0_pipe[n3-1];
end
// assign outputs
always @(posedge clk)
if(ena)
ovf <= #1 ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= #1 div0_pipe[d_width];
always @(posedge clk)
if(ena)
q <= #1 gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= #1 assign_s(s_pipe[d_width], d_pipe[d_width]);
endmodule |
module zigzag(
clk,
ena,
dstrb,
din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77,
dout,
douten
);
//
// inputs & outputs
//
input clk; // system clock
input ena; // clock enable
input dstrb; // data-strobe. Present dstrb 1clk-cycle before data block
input [11:0]
din_00, din_01, din_02, din_03, din_04, din_05, din_06, din_07,
din_10, din_11, din_12, din_13, din_14, din_15, din_16, din_17,
din_20, din_21, din_22, din_23, din_24, din_25, din_26, din_27,
din_30, din_31, din_32, din_33, din_34, din_35, din_36, din_37,
din_40, din_41, din_42, din_43, din_44, din_45, din_46, din_47,
din_50, din_51, din_52, din_53, din_54, din_55, din_56, din_57,
din_60, din_61, din_62, din_63, din_64, din_65, din_66, din_67,
din_70, din_71, din_72, din_73, din_74, din_75, din_76, din_77;
output [11:0] dout;
output douten; // data-out enable
//
// variables
//
reg ld_zigzag;
reg [11:0] sresult [63:0]; // store results for zig-zagging
//
// module body
//
always @(posedge clk)
if(ena)
ld_zigzag <= #1 dstrb;
assign douten = ld_zigzag;
//
// Generate zig-zag structure
//
// This implicates that the quantization step be performed after
// the zig-zagging.
//
// 0: 1: 2: 3: 4: 5: 6: 7: 0: 1: 2: 3: 4: 5: 6: 7:
// 0: 63 62 58 57 49 48 36 35 3f 3e 3a 39 31 30 24 23
// 1: 61 59 56 50 47 37 34 21 3d 3b 38 32 2f 25 22 15
// 2: 60 55 51 46 38 33 22 20 3c 37 33 2e 26 21 16 14
// 3: 54 52 45 39 32 23 19 10 36 34 2d 27 20 17 13 0a
// 4: 53 44 40 31 24 18 11 09 35 2c 28 1f 18 12 0b 09
// 5: 43 41 30 25 17 12 08 03 2b 29 1e 19 11 0c 08 03
// 6: 42 29 26 16 13 07 04 02 2a 1d 1a 10 0d 07 04 02
// 7: 28 27 15 14 06 05 01 00 1c 1b 0f 0e 06 05 01 00
//
// zig-zag the DCT results
integer n;
always @(posedge clk)
if(ena)
if(ld_zigzag) // reload results-register file
begin
sresult[63] <= #1 din_00;
sresult[62] <= #1 din_01;
sresult[61] <= #1 din_10;
sresult[60] <= #1 din_20;
sresult[59] <= #1 din_11;
sresult[58] <= #1 din_02;
sresult[57] <= #1 din_03;
sresult[56] <= #1 din_12;
sresult[55] <= #1 din_21;
sresult[54] <= #1 din_30;
sresult[53] <= #1 din_40;
sresult[52] <= #1 din_31;
sresult[51] <= #1 din_22;
sresult[50] <= #1 din_13;
sresult[49] <= #1 din_04;
sresult[48] <= #1 din_05;
sresult[47] <= #1 din_14;
sresult[46] <= #1 din_23;
sresult[45] <= #1 din_32;
sresult[44] <= #1 din_41;
sresult[43] <= #1 din_50;
sresult[42] <= #1 din_60;
sresult[41] <= #1 din_51;
sresult[40] <= #1 din_42;
sresult[39] <= #1 din_33;
sresult[38] <= #1 din_24;
sresult[37] <= #1 din_15;
sresult[36] <= #1 din_06;
sresult[35] <= #1 din_07;
sresult[34] <= #1 din_16;
sresult[33] <= #1 din_25;
sresult[32] <= #1 din_34;
sresult[31] <= #1 din_43;
sresult[30] <= #1 din_52;
sresult[29] <= #1 din_61;
sresult[28] <= #1 din_70;
sresult[27] <= #1 din_71;
sresult[26] <= #1 din_62;
sresult[25] <= #1 din_53;
sresult[24] <= #1 din_44;
sresult[23] <= #1 din_35;
sresult[22] <= #1 din_26;
sresult[21] <= #1 din_17;
sresult[20] <= #1 din_27;
sresult[19] <= #1 din_36;
sresult[18] <= #1 din_45;
sresult[17] <= #1 din_54;
sresult[16] <= #1 din_63;
sresult[15] <= #1 din_72;
sresult[14] <= #1 din_73;
sresult[13] <= #1 din_64;
sresult[12] <= #1 din_55;
sresult[11] <= #1 din_46;
sresult[10] <= #1 din_37;
sresult[09] <= #1 din_47;
sresult[08] <= #1 din_56;
sresult[07] <= #1 din_65;
sresult[06] <= #1 din_74;
sresult[05] <= #1 din_75;
sresult[04] <= #1 din_66;
sresult[03] <= #1 din_57;
sresult[02] <= #1 din_67;
sresult[01] <= #1 din_76;
sresult[00] <= #1 din_77;
end
else // shift results out
for (n=1; n<=63; n=n+1) // do not change sresult[0]
sresult[n] <= #1 sresult[n -1];
assign dout = sresult[63];
endmodule |
module jpeg_rzs(clk, ena, rst, deni, dci, rleni, sizei, ampi, deno, dco, rleno, sizeo, ampo);
//
// inputs & outputs
//
input clk;
input ena;
input rst;
input deni;
input dci;
input [ 3:0] sizei;
input [ 3:0] rleni;
input [11:0] ampi;
output deno;
output dco;
output [ 3:0] sizeo;
output [ 3:0] rleno;
output [11:0] ampo;
reg deno, dco;
reg [ 3:0] sizeo, rleno;
reg [11:0] ampo;
//
// variables
//
reg [ 3:0] size;
reg [ 3:0] rlen;
reg [11:0] amp;
reg den;
reg dc;
wire eob;
wire zerobl;
reg state;
//
// module body
//
always @(posedge clk)
if(ena & deni)
begin
size <= #1 sizei;
rlen <= #1 rleni;
amp <= #1 ampi;
end
always @(posedge clk)
if(ena)
begin
sizeo <= #1 size;
rleno <= #1 rlen;
ampo <= #1 amp;
dc <= #1 dci;
dco <= #1 dc;
end
assign zerobl = &rleni & ~|sizei & deni;
assign eob = ~|{rleni, sizei} & deni & ~dci;
always @(posedge clk or negedge rst)
if (!rst)
begin
state <= #1 1'b0;
den <= #1 1'b0;
deno <= #1 1'b0;
end
else
if(ena)
(* full_case, parallel_case *) case (state)
1'b0:
begin
if (zerobl)
begin
state <= #1 1'b1; // go to zero-detection state
den <= #1 1'b0; // do not yet set data output enable
deno <= #1 den; // output previous data
end
else
begin
state <= #1 1'b0; // stay in 'normal' state
den <= #1 deni; // set data output enable
deno <= #1 den; // output previous data
end
end
1'b1:
begin
deno <= #1 1'b0;
if (deni)
if (zerobl)
begin
state <= #1 1'b1; // stay in zero-detection state
den <= #1 1'b0; // hold current zer-block
deno <= #1 1'b1; // output previous zero-block
end
else if (eob)
begin
state <= #1 1'b0; // go to 'normal' state
den <= #1 1'b1; // set output enable for EOB
deno <= #1 1'b0; // (was already zero), maybe optimize ??
end
else
begin
state <= #1 1'b0; // go to normal state
den <= #1 1'b1; // set data output enable
deno <= #1 1'b1; // oops, zero-block should have been output
end
end
endcase
endmodule |
module jpeg_rle1(clk, rst, ena, go, din, rlen, size, amp, den, dcterm);
//
// parameters
//
//
// inputs & outputs
//
input clk; // system clock
input rst; // asynchronous reset
input ena; // clock enable
input go;
input [11:0] din; // data input
output [ 3:0] rlen; // run-length
output [ 3:0] size; // size (or category)
output [11:0] amp; // amplitude
output den; // data output enable
output dcterm; // DC-term (start of new block)
reg [ 3:0] rlen, size;
reg [11:0] amp;
reg den, dcterm;
//
// variables
//
reg [5:0] sample_cnt;
reg [3:0] zero_cnt;
wire is_zero;
reg state;
parameter dc = 1'b0;
parameter ac = 1'b1;
//
// module body
//
//
// function declarations
//
// Function abs; absolute value
function [10:0] abs;
input [11:0] a;
begin
if (a[11])
abs = (~a[10:0]) +11'h1;
else
abs = a[10:0];
end
endfunction
// Function cat, calculates category for Din
function [3:0] cat;
input [11:0] a;
reg [10:0] tmp;
begin
// get absolute value
tmp = abs(a);
// determine category
(* full_case, parallel_case *) casex(tmp)
11'b1??_????_???? : cat = 4'hb; // 1024..2047
11'b01?_????_???? : cat = 4'ha; // 512..1023
11'b001_????_???? : cat = 4'h9; // 256.. 511
11'b000_1???_???? : cat = 4'h8; // 128.. 255
11'b000_01??_???? : cat = 4'h7; // 64.. 127
11'b000_001?_???? : cat = 4'h6; // 32.. 63
11'b000_0001_???? : cat = 4'h5; // 16.. 31
11'b000_0000_1??? : cat = 4'h4; // 8.. 15
11'b000_0000_01?? : cat = 4'h3; // 4.. 7
11'b000_0000_001? : cat = 4'h2; // 2.. 3
11'b000_0000_0001 : cat = 4'h1; // 1
11'b000_0000_0000 : cat = 4'h0; // 0 (DC only)
endcase
end
endfunction
// Function modamp, calculate additional bits per category
function [10:0] rem;
input [11:0] a;
reg [10:0] tmp, tmp_rem;
begin
tmp_rem = a[11] ? (a[10:0] - 10'h1) : a[10:0];
if(0)
begin
// get absolute value
tmp = abs(a);
(* full_case, parallel_case *) casex(tmp)
11'b1??_????_???? : rem = tmp_rem & 11'b111_1111_1111;
11'b01?_????_???? : rem = tmp_rem & 11'b011_1111_1111;
11'b001_????_???? : rem = tmp_rem & 11'b001_1111_1111;
11'b000_1???_???? : rem = tmp_rem & 11'b000_1111_1111;
11'b000_01??_???? : rem = tmp_rem & 11'b000_0111_1111;
11'b000_001?_???? : rem = tmp_rem & 11'b000_0011_1111;
11'b000_0001_???? : rem = tmp_rem & 11'b000_0001_1111;
11'b000_0000_1??? : rem = tmp_rem & 11'b000_0000_1111;
11'b000_0000_01?? : rem = tmp_rem & 11'b000_0000_0111;
11'b000_0000_001? : rem = tmp_rem & 11'b000_0000_0011;
11'b000_0000_0001 : rem = tmp_rem & 11'b000_0000_0001;
11'b000_0000_0000 : rem = tmp_rem & 11'b000_0000_0000;
endcase
end
else
rem = tmp_rem;
end
endfunction
// detect zero
assign is_zero = ~|din;
// assign dout
always @(posedge clk)
if (ena)
amp <= #1 rem(din);
// generate sample counter
always @(posedge clk)
if (ena)
if (go)
sample_cnt <= #1 1; // count AC-terms, 'go=1' is sample-zero
else
sample_cnt <= #1 sample_cnt +1;
// generate zero counter
always @(posedge clk)
if (ena)
if (is_zero)
zero_cnt <= #1 zero_cnt +1;
else
zero_cnt <= #1 0;
// statemachine, create intermediate results
always @(posedge clk or negedge rst)
if(!rst)
begin
state <= #1 dc;
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
else if (ena)
(* full_case, parallel_case *) case (state)
dc:
begin
rlen <= #1 0;
size <= #1 cat(din);
if(go)
begin
state <= #1 ac;
den <= #1 1'b1;
dcterm <= #1 1'b1;
end
else
begin
state <= #1 dc;
den <= #1 1'b0;
dcterm <= #1 1'b0;
end
end
ac:
if(&sample_cnt) // finished current block
begin
state <= #1 dc;
if (is_zero) // last sample zero? send EOB
begin
rlen <= #1 0;
size <= #1 0;
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
else
begin
rlen <= #1 zero_cnt;
size <= #1 cat(din);
den <= #1 1'b1;
dcterm <= #1 1'b0;
end
end
else
begin
state <= #1 ac;
rlen <= #1 zero_cnt;
dcterm <= #1 1'b0;
if (is_zero)
begin
size <= #1 0;
den <= #1 &zero_cnt;
end
else
begin
size <= #1 cat(din);
den <= #1 1'b1;
end
end
endcase
endmodule |
module dct_mac(clk, ena, dclr, din, coef, result);
//
// parameters
//
parameter dwidth = 8;
parameter cwidth = 16;
parameter mwidth = dwidth + cwidth; // multiplier result
parameter rwidth = mwidth +3; // add 3 bits for growth
//
// inputs & outputs
//
input clk; // clock input
input ena; // clock enable
input dclr; // start new mac (delayed 1 cycle)
input [dwidth-1:0] din; // data input
input [cwidth-1:0] coef; // coefficient input
output [rwidth-1:0] result; // mac-result
reg [rwidth -1:0] result;
//
// variables
//
wire [mwidth-1:0] idin;
wire [mwidth-1:0] icoef;
reg [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
wire [rwidth -1:0] ext_mult_res;
//
// module body
//
assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
assign idin = { {(mwidth-dwidth){din[dwidth-1]}}, din};
// generate multiplier structure
always @(posedge clk)
if(ena)
mult_res <= #1 icoef * idin;
assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
// generate adder structure
always @(posedge clk)
if(ena)
if(dclr)
result <= #1 ext_mult_res;
else
result <= #1 ext_mult_res + result;
endmodule |
module adder (input [31:0] a, b,
output [31:0] y);
assign y = a + b;
endmodule |
module shifter (input wire signed [31:0] a,
input wire [ 4:0] shamt,
input wire [ 1:0] shtype,
output reg [31:0] y);
always@(*)
case (shtype)
2'b00:
begin
y = a << shamt;
end
2'b01:
begin
y = a >> shamt;
end
2'b10:
begin
y = a >>> shamt;
end
default:
begin
y = a;
end
endcase // case (shtype)
endmodule |
module magcompare2b (LT, GT, A, B);
input [1:0] A;
input [1:0] B;
output LT;
output GT;
// Determine if A < B using a minimized sum-of-products expression
assign LT = ~A[1]&B[1] | ~A[1]&~A[0]&B[0] | ~A[0]&B[1]&B[0];
// Determine if A > B using a minimized sum-of-products expression
assign GT = A[1]&~B[1] | A[1]&A[0]&~B[0] | A[0]&~B[1]&~B[0];
endmodule |
module aludec (input wire funct7b,
input wire [2:0] funct3,
input wire [2:0] aluop,
output reg [3:0] alucontrol,
output reg [1:0] shtype,
output reg alu2src,
output reg sltunsigned,
output reg lh, lb, lhu, lbu);
always@(*)
case(aluop)
3'b000:
begin
casex({funct7b, funct3})
// slli
4'b0001:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b1;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// srli
4'b0101:
begin
alucontrol <= 4'b0010;
shtype <= 2'b01;
alu2src <= 1'b1;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// andi
4'b?111:
begin
alucontrol <= 4'b0000;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// xori
4'b?100:
begin
alucontrol <= 4'b1000;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// ori
4'b?110:
begin
alucontrol <= 4'b0001;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
//slti
4'b?010:
begin
alucontrol <= 4'b0111;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// srai
4'b1101:
begin
alucontrol <= 4'b0010;
shtype <= 2'b10;
alu2src <= 1'b1;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// sltiu
4'b?011:
begin
alucontrol <= 4'b0111;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b1;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// Handle other immediates
default:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
endcase // casex ({funct7b, funct3})
end
// lw/sw
3'b100:
case(funct3)
// lb/sb
3'b000:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b1;
lhu <= 1'b0;
lbu <= 1'b0;
end // case: 3'b000
// lh/sh
3'b001:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b1;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// lw/sw
3'b010:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// lbu/sbu
3'b100:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b1;
lhu <= 1'b0;
lbu <= 1'b1;
end
// lhu/shu
3'b101:
begin
alucontrol <= 4'b0010;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b1;
lb <= 1'b0;
lhu <= 1'b1;
lbu <= 1'b0;
end
default:
begin
alucontrol <= 4'b0000;
shtype <= 2'b00;
alu2src <= 1'b0;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end // case: default
endcase
// R-type
3'b010:
case({funct7b, funct3})
// add
4'b0000:
begin
alucontrol <= 4'b0010;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// sll
4'b0001:
begin
alucontrol <= 4'b0010;
alu2src <= 1'b1;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// xor
4'b0100:
begin
alucontrol <= 4'b1000;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// srl
4'b0101:
begin
alucontrol <= 4'b0010;
alu2src <= 1'b1;
shtype <= 2'b01;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// sra
4'b1101:
begin
alucontrol <= 4'b0010;
alu2src <= 1'b1;
shtype <= 2'b10;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// sub
4'b1000:
begin
alucontrol <= 4'b0110;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// and
4'b0111:
begin
alucontrol <= 4'b0000;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// or
4'b0110:
begin
alucontrol <= 4'b0001;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// slt
4'b0010:
begin
alucontrol <= 4'b0111;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// sltu
4'b0011:
begin
alucontrol <= 4'b0111;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b1;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
// ???
default:
begin
alucontrol <= 4'b0000;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
endcase // case ({funct7b, funct3})
// ???
default:
begin
alucontrol <= 4'b0000;
alu2src <= 1'b0;
shtype <= 2'b00;
sltunsigned <= 1'b0;
lh <= 1'b0;
lb <= 1'b0;
lhu <= 1'b0;
lbu <= 1'b0;
end
endcase // case (aluop)
endmodule |
module maindec (input [6:0] op,
output memtoreg, memwrite,
output branch, alusrc,
output regwrite,
output storepc,
output pcadd,
output pcext,
output [2:0] imm,
output [2:0] aluop,
output auipc_cntrl,
output memread,
input gt, lt, eq,
output suspend);
reg [16:0] controls;
assign {memread, auipc_cntrl, pcadd, pcext, suspend, regwrite, alusrc,
branch, memwrite,
memtoreg, storepc, aluop, imm} = controls;
always @(*)
case(op)
7'b011_0011: controls <= 17'b00000100_000_010_000; // R
7'b000_0011: controls <= 17'b10000110_010_100_000; // LW
7'b010_0011: controls <= 17'b00000010_100_100_001; // SW
7'b110_0011: controls <= 17'b00110011_000_000_010; // BXX
7'b110_1111: controls <= 17'b00110110_001_000_011; // JAL/J
7'b001_0011: controls <= 17'b00000110_000_000_000; // ADDI/ORI
7'b011_0111: controls <= 17'b00000110_000_000_100; // LUI
7'b111_0011: controls <= 17'b00001000_000_000_000; // ecall/ebreak
7'b110_0111: controls <= 17'b00000110_001_000_000; // JALR/JR
7'b001_0111: controls <= 17'b01100110_000_000_100; // AUIPC
default: controls <= 17'b00000000_000_000_000; // default
endcase // case (op)
endmodule |
module regfile (input clk,
input we3,
input [4:0] ra1, ra2, wa3,
input [31:0] wd3,
output [31:0] rd1, rd2);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
always @(posedge clk)
if (we3 && wa3!=0) rf[wa3] <= wd3;
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule |
module magcompare2c (LT, GT, GT_in, LT_in);
input [1:0] LT_in;
input [1:0] GT_in;
output LT;
output GT;
// Determine if A < B using a minimized sum-of-products expression
assign GT = GT_in[1] | ~LT_in[1]>_in[0];
// Determine if A > B using a minimized sum-of-products expression
assign LT = LT_in[1] | !GT_in[1]<_in[0];
endmodule |
module alu (input wire [31:0] a, b,
input wire [3:0] alucont,
input wire sltunsigned,
output reg [31:0] result,
output wire zero);
wire [32:0] a2, b2, sum;
wire [31:0] slt;
wire [31:0] exor;
assign a2 = {sltunsigned ? 1'b0 : a[31], a};
assign b2 = alucont[2] ? ~{sltunsigned ? 1'b0 : b[31], b} :
{sltunsigned ? 1'b0 : b[31], b};
assign sum = a2 + b2 + alucont[2];
assign exor = a2 ^ b2;
assign slt = sum[32];
always@(*)
case({alucont[3], alucont[1:0]})
3'b000: result <= a2 & b2;
3'b001: result <= a2 | b2;
3'b010: result <= sum[31:0];
3'b011: result <= slt;
3'b100: result <= exor;
default: result <= 32'h0;
endcase // case ({alucont[3], alucont[1:0]})
assign zero = ~| exor;
endmodule |
module ibex_counter (
clk_i,
rst_ni,
counter_inc_i,
counterh_we_i,
counter_we_i,
counter_val_i,
counter_val_o
);
parameter signed [31:0] CounterWidth = 32;
input wire clk_i;
input wire rst_ni;
input wire counter_inc_i;
input wire counterh_we_i;
input wire counter_we_i;
input wire [31:0] counter_val_i;
output wire [63:0] counter_val_o;
wire [63:0] counter;
reg [CounterWidth - 1:0] counter_upd;
reg [63:0] counter_load;
reg we;
reg [CounterWidth - 1:0] counter_d;
always @(*) begin
we = counter_we_i | counterh_we_i;
counter_load[63:32] = counter[63:32];
counter_load[31:0] = counter_val_i;
if (counterh_we_i) begin
counter_load[63:32] = counter_val_i;
counter_load[31:0] = counter[31:0];
end
counter_upd = counter[CounterWidth - 1:0] + {{CounterWidth - 1 {1'b0}}, 1'b1};
if (we)
counter_d = counter_load[CounterWidth - 1:0];
else if (counter_inc_i)
counter_d = counter_upd[CounterWidth - 1:0];
else
counter_d = counter[CounterWidth - 1:0];
end
reg [CounterWidth - 1:0] counter_q;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
counter_q <= {CounterWidth {1'sb0}};
else
counter_q <= counter_d;
generate
if (CounterWidth < 64) begin : g_counter_narrow
wire [63:CounterWidth] unused_counter_load;
assign counter[CounterWidth - 1:0] = counter_q;
assign counter[63:CounterWidth] = {(63 >= CounterWidth ? 64 - CounterWidth : CounterWidth - 62) {1'sb0}};
assign unused_counter_load = counter_load[63:CounterWidth];
end
else begin : g_counter_full
assign counter = counter_q;
end
endgenerate
assign counter_val_o = counter;
endmodule |
module ibex_multdiv_fast (
clk_i,
rst_ni,
mult_en_i,
div_en_i,
mult_sel_i,
div_sel_i,
operator_i,
signed_mode_i,
op_a_i,
op_b_i,
alu_adder_ext_i,
alu_adder_i,
equal_to_zero_i,
data_ind_timing_i,
alu_operand_a_o,
alu_operand_b_o,
imd_val_q_i,
imd_val_d_o,
imd_val_we_o,
multdiv_ready_id_i,
multdiv_result_o,
valid_o
);
localparam integer ibex_pkg_RV32MFast = 2;
parameter integer RV32M = ibex_pkg_RV32MFast;
input wire clk_i;
input wire rst_ni;
input wire mult_en_i;
input wire div_en_i;
input wire mult_sel_i;
input wire div_sel_i;
input wire [1:0] operator_i;
input wire [1:0] signed_mode_i;
input wire [31:0] op_a_i;
input wire [31:0] op_b_i;
input wire [33:0] alu_adder_ext_i;
input wire [31:0] alu_adder_i;
input wire equal_to_zero_i;
input wire data_ind_timing_i;
output reg [32:0] alu_operand_a_o;
output reg [32:0] alu_operand_b_o;
input wire [67:0] imd_val_q_i;
output wire [67:0] imd_val_d_o;
output wire [1:0] imd_val_we_o;
input wire multdiv_ready_id_i;
output wire [31:0] multdiv_result_o;
output wire valid_o;
wire signed [34:0] mac_res_signed;
wire [34:0] mac_res_ext;
reg [33:0] accum;
reg sign_a;
reg sign_b;
reg mult_valid;
wire signed_mult;
reg [33:0] mac_res_d;
reg [33:0] op_remainder_d;
wire [33:0] mac_res;
wire div_sign_a;
wire div_sign_b;
reg is_greater_equal;
wire div_change_sign;
wire rem_change_sign;
wire [31:0] one_shift;
wire [31:0] op_denominator_q;
reg [31:0] op_numerator_q;
reg [31:0] op_quotient_q;
reg [31:0] op_denominator_d;
reg [31:0] op_numerator_d;
reg [31:0] op_quotient_d;
wire [31:0] next_remainder;
wire [32:0] next_quotient;
wire [31:0] res_adder_h;
reg div_valid;
reg [4:0] div_counter_q;
reg [4:0] div_counter_d;
wire multdiv_en;
reg mult_hold;
reg div_hold;
reg div_by_zero_d;
reg div_by_zero_q;
wire mult_en_internal;
wire div_en_internal;
reg [2:0] md_state_q;
reg [2:0] md_state_d;
wire unused_mult_sel_i;
assign unused_mult_sel_i = mult_sel_i;
assign mult_en_internal = mult_en_i & ~mult_hold;
assign div_en_internal = div_en_i & ~div_hold;
localparam [2:0] MD_IDLE = 0;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
div_counter_q <= {5 {1'sb0}};
md_state_q <= MD_IDLE;
op_numerator_q <= {32 {1'sb0}};
op_quotient_q <= {32 {1'sb0}};
div_by_zero_q <= 1'b0;
end
else if (div_en_internal) begin
div_counter_q <= div_counter_d;
op_numerator_q <= op_numerator_d;
op_quotient_q <= op_quotient_d;
md_state_q <= md_state_d;
div_by_zero_q <= div_by_zero_d;
end
assign multdiv_en = mult_en_internal | div_en_internal;
assign imd_val_d_o[34+:34] = (div_sel_i ? op_remainder_d : mac_res_d);
assign imd_val_we_o[0] = multdiv_en;
assign imd_val_d_o[0+:34] = {2'b00, op_denominator_d};
assign imd_val_we_o[1] = div_en_internal;
assign op_denominator_q = imd_val_q_i[31-:32];
wire [1:0] unused_imd_val;
assign unused_imd_val = imd_val_q_i[33-:2];
wire unused_mac_res_ext;
assign unused_mac_res_ext = mac_res_ext[34];
assign signed_mult = signed_mode_i != 2'b00;
assign multdiv_result_o = (div_sel_i ? imd_val_q_i[65-:32] : mac_res_d[31:0]);
localparam [1:0] AHBH = 3;
localparam [1:0] AHBL = 2;
localparam [1:0] ALBH = 1;
localparam [1:0] ALBL = 0;
localparam [0:0] MULH = 1;
localparam [0:0] MULL = 0;
localparam [1:0] ibex_pkg_MD_OP_MULL = 0;
localparam integer ibex_pkg_RV32MSingleCycle = 3;
generate
if (RV32M == ibex_pkg_RV32MSingleCycle) begin : gen_mult_single_cycle
reg mult_state_q;
reg mult_state_d;
wire signed [33:0] mult1_res;
wire signed [33:0] mult2_res;
wire signed [33:0] mult3_res;
wire [33:0] mult1_res_uns;
wire [33:32] unused_mult1_res_uns;
wire [15:0] mult1_op_a;
wire [15:0] mult1_op_b;
wire [15:0] mult2_op_a;
wire [15:0] mult2_op_b;
reg [15:0] mult3_op_a;
reg [15:0] mult3_op_b;
wire mult1_sign_a;
wire mult1_sign_b;
wire mult2_sign_a;
wire mult2_sign_b;
reg mult3_sign_a;
reg mult3_sign_b;
reg [33:0] summand1;
reg [33:0] summand2;
reg [33:0] summand3;
assign mult1_res = $signed({mult1_sign_a, mult1_op_a}) * $signed({mult1_sign_b, mult1_op_b});
assign mult2_res = $signed({mult2_sign_a, mult2_op_a}) * $signed({mult2_sign_b, mult2_op_b});
assign mult3_res = $signed({mult3_sign_a, mult3_op_a}) * $signed({mult3_sign_b, mult3_op_b});
assign mac_res_signed = ($signed(summand1) + $signed(summand2)) + $signed(summand3);
assign mult1_res_uns = $unsigned(mult1_res);
assign mac_res_ext = $unsigned(mac_res_signed);
assign mac_res = mac_res_ext[33:0];
wire [1:1] sv2v_tmp_1E8D3;
assign sv2v_tmp_1E8D3 = signed_mode_i[0] & op_a_i[31];
always @(*) sign_a = sv2v_tmp_1E8D3;
wire [1:1] sv2v_tmp_3B65C;
assign sv2v_tmp_3B65C = signed_mode_i[1] & op_b_i[31];
always @(*) sign_b = sv2v_tmp_3B65C;
assign mult1_sign_a = 1'b0;
assign mult1_sign_b = 1'b0;
assign mult1_op_a = op_a_i[15:0];
assign mult1_op_b = op_b_i[15:0];
assign mult2_sign_a = 1'b0;
assign mult2_sign_b = sign_b;
assign mult2_op_a = op_a_i[15:0];
assign mult2_op_b = op_b_i[31:16];
wire [18:1] sv2v_tmp_4D45D;
assign sv2v_tmp_4D45D = imd_val_q_i[67-:18];
always @(*) accum[17:0] = sv2v_tmp_4D45D;
wire [16:1] sv2v_tmp_D5F47;
assign sv2v_tmp_D5F47 = {16 {signed_mult & imd_val_q_i[67]}};
always @(*) accum[33:18] = sv2v_tmp_D5F47;
always @(*) begin
mult3_sign_a = sign_a;
mult3_sign_b = 1'b0;
mult3_op_a = op_a_i[31:16];
mult3_op_b = op_b_i[15:0];
summand1 = {18'h00000, mult1_res_uns[31:16]};
summand2 = $unsigned(mult2_res);
summand3 = $unsigned(mult3_res);
mac_res_d = {2'b00, mac_res[15:0], mult1_res_uns[15:0]};
mult_valid = mult_en_i;
mult_state_d = MULL;
mult_hold = 1'b0;
case (mult_state_q)
MULL:
if (operator_i != ibex_pkg_MD_OP_MULL) begin
mac_res_d = mac_res;
mult_valid = 1'b0;
mult_state_d = MULH;
end
else
mult_hold = ~multdiv_ready_id_i;
MULH: begin
mult3_sign_a = sign_a;
mult3_sign_b = sign_b;
mult3_op_a = op_a_i[31:16];
mult3_op_b = op_b_i[31:16];
mac_res_d = mac_res;
summand1 = {34 {1'sb0}};
summand2 = accum;
summand3 = mult3_res;
mult_state_d = MULL;
mult_valid = 1'b1;
mult_hold = ~multdiv_ready_id_i;
end
default: mult_state_d = MULL;
endcase
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
mult_state_q <= MULL;
else if (mult_en_internal)
mult_state_q <= mult_state_d;
assign unused_mult1_res_uns = mult1_res_uns[33:32];
end
else begin : gen_mult_fast
reg [15:0] mult_op_a;
reg [15:0] mult_op_b;
reg [1:0] mult_state_q;
reg [1:0] mult_state_d;
assign mac_res_signed = ($signed({sign_a, mult_op_a}) * $signed({sign_b, mult_op_b})) + $signed(accum);
assign mac_res_ext = $unsigned(mac_res_signed);
assign mac_res = mac_res_ext[33:0];
always @(*) begin
mult_op_a = op_a_i[15:0];
mult_op_b = op_b_i[15:0];
sign_a = 1'b0;
sign_b = 1'b0;
accum = imd_val_q_i[34+:34];
mac_res_d = mac_res;
mult_state_d = mult_state_q;
mult_valid = 1'b0;
mult_hold = 1'b0;
case (mult_state_q)
ALBL: begin
mult_op_a = op_a_i[15:0];
mult_op_b = op_b_i[15:0];
sign_a = 1'b0;
sign_b = 1'b0;
accum = {34 {1'sb0}};
mac_res_d = mac_res;
mult_state_d = ALBH;
end
ALBH: begin
mult_op_a = op_a_i[15:0];
mult_op_b = op_b_i[31:16];
sign_a = 1'b0;
sign_b = signed_mode_i[1] & op_b_i[31];
accum = {18'b000000000000000000, imd_val_q_i[65-:16]};
if (operator_i == ibex_pkg_MD_OP_MULL)
mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]};
else
mac_res_d = mac_res;
mult_state_d = AHBL;
end
AHBL: begin
mult_op_a = op_a_i[31:16];
mult_op_b = op_b_i[15:0];
sign_a = signed_mode_i[0] & op_a_i[31];
sign_b = 1'b0;
if (operator_i == ibex_pkg_MD_OP_MULL) begin
accum = {18'b000000000000000000, imd_val_q_i[65-:16]};
mac_res_d = {2'b00, mac_res[15:0], imd_val_q_i[49-:16]};
mult_valid = 1'b1;
mult_state_d = ALBL;
mult_hold = ~multdiv_ready_id_i;
end
else begin
accum = imd_val_q_i[34+:34];
mac_res_d = mac_res;
mult_state_d = AHBH;
end
end
AHBH: begin
mult_op_a = op_a_i[31:16];
mult_op_b = op_b_i[31:16];
sign_a = signed_mode_i[0] & op_a_i[31];
sign_b = signed_mode_i[1] & op_b_i[31];
accum[17:0] = imd_val_q_i[67-:18];
accum[33:18] = {16 {signed_mult & imd_val_q_i[67]}};
mac_res_d = mac_res;
mult_valid = 1'b1;
mult_state_d = ALBL;
mult_hold = ~multdiv_ready_id_i;
end
default: mult_state_d = ALBL;
endcase
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
mult_state_q <= ALBL;
else if (mult_en_internal)
mult_state_q <= mult_state_d;
end
endgenerate
assign res_adder_h = alu_adder_ext_i[32:1];
wire [1:0] unused_alu_adder_ext;
assign unused_alu_adder_ext = {alu_adder_ext_i[33], alu_adder_ext_i[0]};
assign next_remainder = (is_greater_equal ? res_adder_h[31:0] : imd_val_q_i[65-:32]);
assign next_quotient = (is_greater_equal ? {1'b0, op_quotient_q} | {1'b0, one_shift} : {1'b0, op_quotient_q});
assign one_shift = {31'b0000000000000000000000000000000, 1'b1} << div_counter_q;
always @(*)
if ((imd_val_q_i[65] ^ op_denominator_q[31]) == 1'b0)
is_greater_equal = res_adder_h[31] == 1'b0;
else
is_greater_equal = imd_val_q_i[65];
assign div_sign_a = op_a_i[31] & signed_mode_i[0];
assign div_sign_b = op_b_i[31] & signed_mode_i[1];
assign div_change_sign = (div_sign_a ^ div_sign_b) & ~div_by_zero_q;
assign rem_change_sign = div_sign_a;
localparam [2:0] MD_ABS_A = 1;
localparam [2:0] MD_ABS_B = 2;
localparam [2:0] MD_CHANGE_SIGN = 5;
localparam [2:0] MD_COMP = 3;
localparam [2:0] MD_FINISH = 6;
localparam [2:0] MD_LAST = 4;
localparam [1:0] ibex_pkg_MD_OP_DIV = 2;
always @(*) begin
div_counter_d = div_counter_q - 5'h01;
op_remainder_d = imd_val_q_i[34+:34];
op_quotient_d = op_quotient_q;
md_state_d = md_state_q;
op_numerator_d = op_numerator_q;
op_denominator_d = op_denominator_q;
alu_operand_a_o = {32'h00000000, 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
div_valid = 1'b0;
div_hold = 1'b0;
div_by_zero_d = div_by_zero_q;
case (md_state_q)
MD_IDLE: begin
if (operator_i == ibex_pkg_MD_OP_DIV) begin
op_remainder_d = {34 {1'sb1}};
md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A);
div_by_zero_d = equal_to_zero_i;
end
else begin
op_remainder_d = {2'b00, op_a_i};
md_state_d = (!data_ind_timing_i && equal_to_zero_i ? MD_FINISH : MD_ABS_A);
end
alu_operand_a_o = {32'h00000000, 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
div_counter_d = 5'd31;
end
MD_ABS_A: begin
op_quotient_d = {32 {1'sb0}};
op_numerator_d = (div_sign_a ? alu_adder_i : op_a_i);
md_state_d = MD_ABS_B;
div_counter_d = 5'd31;
alu_operand_a_o = {32'h00000000, 1'b1};
alu_operand_b_o = {~op_a_i, 1'b1};
end
MD_ABS_B: begin
op_remainder_d = {33'h000000000, op_numerator_q[31]};
op_denominator_d = (div_sign_b ? alu_adder_i : op_b_i);
md_state_d = MD_COMP;
div_counter_d = 5'd31;
alu_operand_a_o = {32'h00000000, 1'b1};
alu_operand_b_o = {~op_b_i, 1'b1};
end
MD_COMP: begin
op_remainder_d = {1'b0, next_remainder[31:0], op_numerator_q[div_counter_d]};
op_quotient_d = next_quotient[31:0];
md_state_d = (div_counter_q == 5'd1 ? MD_LAST : MD_COMP);
alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1};
alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
end
MD_LAST: begin
if (operator_i == ibex_pkg_MD_OP_DIV)
op_remainder_d = {1'b0, next_quotient};
else
op_remainder_d = {2'b00, next_remainder[31:0]};
alu_operand_a_o = {imd_val_q_i[65-:32], 1'b1};
alu_operand_b_o = {~op_denominator_q[31:0], 1'b1};
md_state_d = MD_CHANGE_SIGN;
end
MD_CHANGE_SIGN: begin
md_state_d = MD_FINISH;
if (operator_i == ibex_pkg_MD_OP_DIV)
op_remainder_d = (div_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]);
else
op_remainder_d = (rem_change_sign ? {2'h0, alu_adder_i} : imd_val_q_i[34+:34]);
alu_operand_a_o = {32'h00000000, 1'b1};
alu_operand_b_o = {~imd_val_q_i[65-:32], 1'b1};
end
MD_FINISH: begin
md_state_d = MD_IDLE;
div_hold = ~multdiv_ready_id_i;
div_valid = 1'b1;
end
default: md_state_d = MD_IDLE;
endcase
end
assign valid_o = mult_valid | div_valid;
endmodule |
module prim_secded_72_64_enc (
in,
out
);
input [63:0] in;
output wire [71:0] out;
assign out[0] = in[0];
assign out[1] = in[1];
assign out[2] = in[2];
assign out[3] = in[3];
assign out[4] = in[4];
assign out[5] = in[5];
assign out[6] = in[6];
assign out[7] = in[7];
assign out[8] = in[8];
assign out[9] = in[9];
assign out[10] = in[10];
assign out[11] = in[11];
assign out[12] = in[12];
assign out[13] = in[13];
assign out[14] = in[14];
assign out[15] = in[15];
assign out[16] = in[16];
assign out[17] = in[17];
assign out[18] = in[18];
assign out[19] = in[19];
assign out[20] = in[20];
assign out[21] = in[21];
assign out[22] = in[22];
assign out[23] = in[23];
assign out[24] = in[24];
assign out[25] = in[25];
assign out[26] = in[26];
assign out[27] = in[27];
assign out[28] = in[28];
assign out[29] = in[29];
assign out[30] = in[30];
assign out[31] = in[31];
assign out[32] = in[32];
assign out[33] = in[33];
assign out[34] = in[34];
assign out[35] = in[35];
assign out[36] = in[36];
assign out[37] = in[37];
assign out[38] = in[38];
assign out[39] = in[39];
assign out[40] = in[40];
assign out[41] = in[41];
assign out[42] = in[42];
assign out[43] = in[43];
assign out[44] = in[44];
assign out[45] = in[45];
assign out[46] = in[46];
assign out[47] = in[47];
assign out[48] = in[48];
assign out[49] = in[49];
assign out[50] = in[50];
assign out[51] = in[51];
assign out[52] = in[52];
assign out[53] = in[53];
assign out[54] = in[54];
assign out[55] = in[55];
assign out[56] = in[56];
assign out[57] = in[57];
assign out[58] = in[58];
assign out[59] = in[59];
assign out[60] = in[60];
assign out[61] = in[61];
assign out[62] = in[62];
assign out[63] = in[63];
assign out[64] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63];
assign out[65] = ((((((((((((((((((((((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63];
assign out[66] = ((((((((((((((((((((((((in[0] ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63];
assign out[67] = ((((((((((((((((((((((((in[1] ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63];
assign out[68] = ((((((((((((((((((((((((in[2] ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62];
assign out[69] = ((((((((((((((((((((((((in[3] ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61];
assign out[70] = ((((((((((((((((((((((((in[4] ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62];
assign out[71] = ((((((((((((((((((((((((in[5] ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63];
endmodule |
module ibex_controller (
clk_i,
rst_ni,
ctrl_busy_o,
illegal_insn_i,
ecall_insn_i,
mret_insn_i,
dret_insn_i,
wfi_insn_i,
ebrk_insn_i,
csr_pipe_flush_i,
instr_valid_i,
instr_i,
instr_compressed_i,
instr_is_compressed_i,
instr_bp_taken_i,
instr_fetch_err_i,
instr_fetch_err_plus2_i,
pc_id_i,
instr_valid_clear_o,
id_in_ready_o,
controller_run_o,
instr_req_o,
pc_set_o,
pc_set_spec_o,
pc_mux_o,
nt_branch_mispredict_o,
exc_pc_mux_o,
exc_cause_o,
lsu_addr_last_i,
load_err_i,
store_err_i,
wb_exception_o,
branch_set_i,
branch_set_spec_i,
branch_not_set_i,
jump_set_i,
csr_mstatus_mie_i,
irq_pending_i,
irqs_i,
irq_nm_i,
nmi_mode_o,
debug_req_i,
debug_cause_o,
debug_csr_save_o,
debug_mode_o,
debug_single_step_i,
debug_ebreakm_i,
debug_ebreaku_i,
trigger_match_i,
csr_save_if_o,
csr_save_id_o,
csr_save_wb_o,
csr_restore_mret_id_o,
csr_restore_dret_id_o,
csr_save_cause_o,
csr_mtval_o,
priv_mode_i,
csr_mstatus_tw_i,
stall_id_i,
stall_wb_i,
flush_id_o,
ready_wb_i,
perf_jump_o,
perf_tbranch_o
);
parameter [0:0] WritebackStage = 0;
parameter [0:0] BranchPredictor = 0;
input wire clk_i;
input wire rst_ni;
output reg ctrl_busy_o;
input wire illegal_insn_i;
input wire ecall_insn_i;
input wire mret_insn_i;
input wire dret_insn_i;
input wire wfi_insn_i;
input wire ebrk_insn_i;
input wire csr_pipe_flush_i;
input wire instr_valid_i;
input wire [31:0] instr_i;
input wire [15:0] instr_compressed_i;
input wire instr_is_compressed_i;
input wire instr_bp_taken_i;
input wire instr_fetch_err_i;
input wire instr_fetch_err_plus2_i;
input wire [31:0] pc_id_i;
output wire instr_valid_clear_o;
output wire id_in_ready_o;
output reg controller_run_o;
output reg instr_req_o;
output reg pc_set_o;
output reg pc_set_spec_o;
output reg [2:0] pc_mux_o;
output reg nt_branch_mispredict_o;
output reg [1:0] exc_pc_mux_o;
output reg [5:0] exc_cause_o;
input wire [31:0] lsu_addr_last_i;
input wire load_err_i;
input wire store_err_i;
output wire wb_exception_o;
input wire branch_set_i;
input wire branch_set_spec_i;
input wire branch_not_set_i;
input wire jump_set_i;
input wire csr_mstatus_mie_i;
input wire irq_pending_i;
input wire [17:0] irqs_i;
input wire irq_nm_i;
output wire nmi_mode_o;
input wire debug_req_i;
output reg [2:0] debug_cause_o;
output reg debug_csr_save_o;
output wire debug_mode_o;
input wire debug_single_step_i;
input wire debug_ebreakm_i;
input wire debug_ebreaku_i;
input wire trigger_match_i;
output reg csr_save_if_o;
output reg csr_save_id_o;
output reg csr_save_wb_o;
output reg csr_restore_mret_id_o;
output reg csr_restore_dret_id_o;
output reg csr_save_cause_o;
output reg [31:0] csr_mtval_o;
input wire [1:0] priv_mode_i;
input wire csr_mstatus_tw_i;
input wire stall_id_i;
input wire stall_wb_i;
output wire flush_id_o;
input wire ready_wb_i;
output reg perf_jump_o;
output reg perf_tbranch_o;
reg [3:0] ctrl_fsm_cs;
reg [3:0] ctrl_fsm_ns;
reg nmi_mode_q;
reg nmi_mode_d;
reg debug_mode_q;
reg debug_mode_d;
reg load_err_q;
wire load_err_d;
reg store_err_q;
wire store_err_d;
reg exc_req_q;
wire exc_req_d;
reg illegal_insn_q;
wire illegal_insn_d;
reg instr_fetch_err_prio;
reg illegal_insn_prio;
reg ecall_insn_prio;
reg ebrk_insn_prio;
reg store_err_prio;
reg load_err_prio;
wire stall;
reg halt_if;
reg retain_id;
reg flush_id;
wire illegal_dret;
wire illegal_umode;
wire exc_req_lsu;
wire special_req_all;
wire special_req_branch;
wire enter_debug_mode;
wire ebreak_into_debug;
wire handle_irq;
reg [3:0] mfip_id;
wire unused_irq_timer;
wire ecall_insn;
wire mret_insn;
wire dret_insn;
wire wfi_insn;
wire ebrk_insn;
wire csr_pipe_flush;
wire instr_fetch_err;
assign load_err_d = load_err_i;
assign store_err_d = store_err_i;
assign ecall_insn = ecall_insn_i & instr_valid_i;
assign mret_insn = mret_insn_i & instr_valid_i;
assign dret_insn = dret_insn_i & instr_valid_i;
assign wfi_insn = wfi_insn_i & instr_valid_i;
assign ebrk_insn = ebrk_insn_i & instr_valid_i;
assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i;
assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;
assign illegal_dret = dret_insn & ~debug_mode_q;
localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11;
assign illegal_umode = (priv_mode_i != ibex_pkg_PRIV_LVL_M) & (mret_insn | (csr_mstatus_tw_i & wfi_insn));
localparam [3:0] FLUSH = 6;
assign illegal_insn_d = ((illegal_insn_i | illegal_dret) | illegal_umode) & (ctrl_fsm_cs != FLUSH);
assign exc_req_d = (((ecall_insn | ebrk_insn) | illegal_insn_d) | instr_fetch_err) & (ctrl_fsm_cs != FLUSH);
assign exc_req_lsu = store_err_i | load_err_i;
assign special_req_all = ((((mret_insn | dret_insn) | wfi_insn) | csr_pipe_flush) | exc_req_d) | exc_req_lsu;
assign special_req_branch = instr_fetch_err & (ctrl_fsm_cs != FLUSH);
generate
if (WritebackStage) begin : g_wb_exceptions
always @(*) begin
instr_fetch_err_prio = 0;
illegal_insn_prio = 0;
ecall_insn_prio = 0;
ebrk_insn_prio = 0;
store_err_prio = 0;
load_err_prio = 0;
if (store_err_q)
store_err_prio = 1'b1;
else if (load_err_q)
load_err_prio = 1'b1;
else if (instr_fetch_err)
instr_fetch_err_prio = 1'b1;
else if (illegal_insn_q)
illegal_insn_prio = 1'b1;
else if (ecall_insn)
ecall_insn_prio = 1'b1;
else if (ebrk_insn)
ebrk_insn_prio = 1'b1;
end
assign wb_exception_o = ((load_err_q | store_err_q) | load_err_i) | store_err_i;
end
else begin : g_no_wb_exceptions
always @(*) begin
instr_fetch_err_prio = 0;
illegal_insn_prio = 0;
ecall_insn_prio = 0;
ebrk_insn_prio = 0;
store_err_prio = 0;
load_err_prio = 0;
if (instr_fetch_err)
instr_fetch_err_prio = 1'b1;
else if (illegal_insn_q)
illegal_insn_prio = 1'b1;
else if (ecall_insn)
ecall_insn_prio = 1'b1;
else if (ebrk_insn)
ebrk_insn_prio = 1'b1;
else if (store_err_q)
store_err_prio = 1'b1;
else if (load_err_q)
load_err_prio = 1'b1;
end
assign wb_exception_o = 1'b0;
end
endgenerate
assign enter_debug_mode = ((debug_req_i | (debug_single_step_i & instr_valid_i)) | trigger_match_i) & ~debug_mode_q;
localparam [1:0] ibex_pkg_PRIV_LVL_U = 2'b00;
assign ebreak_into_debug = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? debug_ebreakm_i : (priv_mode_i == ibex_pkg_PRIV_LVL_U ? debug_ebreaku_i : 1'b0));
assign handle_irq = (~debug_mode_q & ~nmi_mode_q) & (irq_nm_i | (irq_pending_i & csr_mstatus_mie_i));
always @(*) begin : gen_mfip_id
if (irqs_i[14])
mfip_id = 4'd14;
else if (irqs_i[13])
mfip_id = 4'd13;
else if (irqs_i[12])
mfip_id = 4'd12;
else if (irqs_i[11])
mfip_id = 4'd11;
else if (irqs_i[10])
mfip_id = 4'd10;
else if (irqs_i[9])
mfip_id = 4'd9;
else if (irqs_i[8])
mfip_id = 4'd8;
else if (irqs_i[7])
mfip_id = 4'd7;
else if (irqs_i[6])
mfip_id = 4'd6;
else if (irqs_i[5])
mfip_id = 4'd5;
else if (irqs_i[4])
mfip_id = 4'd4;
else if (irqs_i[3])
mfip_id = 4'd3;
else if (irqs_i[2])
mfip_id = 4'd2;
else if (irqs_i[1])
mfip_id = 4'd1;
else
mfip_id = 4'd0;
end
assign unused_irq_timer = irqs_i[16];
localparam [3:0] BOOT_SET = 1;
localparam [3:0] DBG_TAKEN_ID = 9;
localparam [3:0] DBG_TAKEN_IF = 8;
localparam [3:0] DECODE = 5;
localparam [3:0] FIRST_FETCH = 4;
localparam [3:0] IRQ_TAKEN = 7;
localparam [3:0] RESET = 0;
localparam [3:0] SLEEP = 3;
localparam [3:0] WAIT_SLEEP = 2;
localparam [2:0] ibex_pkg_DBG_CAUSE_EBREAK = 3'h1;
localparam [2:0] ibex_pkg_DBG_CAUSE_HALTREQ = 3'h3;
localparam [2:0] ibex_pkg_DBG_CAUSE_STEP = 3'h4;
localparam [2:0] ibex_pkg_DBG_CAUSE_TRIGGER = 3'h2;
localparam [5:0] ibex_pkg_EXC_CAUSE_BREAKPOINT = {1'b0, 5'd3};
localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11};
localparam [5:0] ibex_pkg_EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd8};
localparam [5:0] ibex_pkg_EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd2};
localparam [5:0] ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd0};
localparam [5:0] ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd1};
localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11};
localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_NM = {1'b1, 5'd31};
localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd3};
localparam [5:0] ibex_pkg_EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd7};
localparam [5:0] ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd5};
localparam [5:0] ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd7};
localparam [1:0] ibex_pkg_EXC_PC_DBD = 2;
localparam [1:0] ibex_pkg_EXC_PC_DBG_EXC = 3;
localparam [1:0] ibex_pkg_EXC_PC_EXC = 0;
localparam [1:0] ibex_pkg_EXC_PC_IRQ = 1;
localparam [2:0] ibex_pkg_PC_BOOT = 0;
localparam [2:0] ibex_pkg_PC_DRET = 4;
localparam [2:0] ibex_pkg_PC_ERET = 3;
localparam [2:0] ibex_pkg_PC_EXC = 2;
localparam [2:0] ibex_pkg_PC_JUMP = 1;
function automatic [5:0] sv2v_cast_6;
input reg [5:0] inp;
sv2v_cast_6 = inp;
endfunction
always @(*) begin
instr_req_o = 1'b1;
csr_save_if_o = 1'b0;
csr_save_id_o = 1'b0;
csr_save_wb_o = 1'b0;
csr_restore_mret_id_o = 1'b0;
csr_restore_dret_id_o = 1'b0;
csr_save_cause_o = 1'b0;
csr_mtval_o = {32 {1'sb0}};
pc_mux_o = ibex_pkg_PC_BOOT;
pc_set_o = 1'b0;
pc_set_spec_o = 1'b0;
nt_branch_mispredict_o = 1'b0;
exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ;
exc_cause_o = ibex_pkg_EXC_CAUSE_INSN_ADDR_MISA;
ctrl_fsm_ns = ctrl_fsm_cs;
ctrl_busy_o = 1'b1;
halt_if = 1'b0;
retain_id = 1'b0;
flush_id = 1'b0;
debug_csr_save_o = 1'b0;
debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK;
debug_mode_d = debug_mode_q;
nmi_mode_d = nmi_mode_q;
perf_tbranch_o = 1'b0;
perf_jump_o = 1'b0;
controller_run_o = 1'b0;
case (ctrl_fsm_cs)
RESET: begin
instr_req_o = 1'b0;
pc_mux_o = ibex_pkg_PC_BOOT;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
ctrl_fsm_ns = BOOT_SET;
end
BOOT_SET: begin
instr_req_o = 1'b1;
pc_mux_o = ibex_pkg_PC_BOOT;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
ctrl_fsm_ns = FIRST_FETCH;
end
WAIT_SLEEP: begin
ctrl_busy_o = 1'b0;
instr_req_o = 1'b0;
halt_if = 1'b1;
flush_id = 1'b1;
ctrl_fsm_ns = SLEEP;
end
SLEEP: begin
instr_req_o = 1'b0;
halt_if = 1'b1;
flush_id = 1'b1;
if ((((irq_nm_i || irq_pending_i) || debug_req_i) || debug_mode_q) || debug_single_step_i)
ctrl_fsm_ns = FIRST_FETCH;
else
ctrl_busy_o = 1'b0;
end
FIRST_FETCH: begin
if (id_in_ready_o)
ctrl_fsm_ns = DECODE;
if (handle_irq) begin
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
end
if (enter_debug_mode) begin
ctrl_fsm_ns = DBG_TAKEN_IF;
halt_if = 1'b1;
end
end
DECODE: begin
controller_run_o = 1'b1;
pc_mux_o = ibex_pkg_PC_JUMP;
if (special_req_all) begin
retain_id = 1'b1;
if (ready_wb_i | wb_exception_o)
ctrl_fsm_ns = FLUSH;
end
if (!special_req_branch) begin
if (branch_set_i || jump_set_i) begin
pc_set_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1);
perf_tbranch_o = branch_set_i;
perf_jump_o = jump_set_i;
end
if (BranchPredictor)
if (instr_bp_taken_i & branch_not_set_i)
nt_branch_mispredict_o = 1'b1;
end
if ((branch_set_spec_i || jump_set_i) && !special_req_branch)
pc_set_spec_o = (BranchPredictor ? ~instr_bp_taken_i : 1'b1);
if ((enter_debug_mode || handle_irq) && stall)
halt_if = 1'b1;
if (!stall && !special_req_all)
if (enter_debug_mode) begin
ctrl_fsm_ns = DBG_TAKEN_IF;
halt_if = 1'b1;
end
else if (handle_irq) begin
ctrl_fsm_ns = IRQ_TAKEN;
halt_if = 1'b1;
end
end
IRQ_TAKEN: begin
pc_mux_o = ibex_pkg_PC_EXC;
exc_pc_mux_o = ibex_pkg_EXC_PC_IRQ;
if (handle_irq) begin
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_save_if_o = 1'b1;
csr_save_cause_o = 1'b1;
if (irq_nm_i && !nmi_mode_q) begin
exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_NM;
nmi_mode_d = 1'b1;
end
else if (irqs_i[14-:15] != 15'b000000000000000)
exc_cause_o = sv2v_cast_6({2'b11, mfip_id});
else if (irqs_i[15])
exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_EXTERNAL_M;
else if (irqs_i[17])
exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_SOFTWARE_M;
else
exc_cause_o = ibex_pkg_EXC_CAUSE_IRQ_TIMER_M;
end
ctrl_fsm_ns = DECODE;
end
DBG_TAKEN_IF: begin
pc_mux_o = ibex_pkg_PC_EXC;
exc_pc_mux_o = ibex_pkg_EXC_PC_DBD;
if ((debug_single_step_i || debug_req_i) || trigger_match_i) begin
flush_id = 1'b1;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_save_if_o = 1'b1;
debug_csr_save_o = 1'b1;
csr_save_cause_o = 1'b1;
if (trigger_match_i)
debug_cause_o = ibex_pkg_DBG_CAUSE_TRIGGER;
else if (debug_single_step_i)
debug_cause_o = ibex_pkg_DBG_CAUSE_STEP;
else
debug_cause_o = ibex_pkg_DBG_CAUSE_HALTREQ;
debug_mode_d = 1'b1;
end
ctrl_fsm_ns = DECODE;
end
DBG_TAKEN_ID: begin
flush_id = 1'b1;
pc_mux_o = ibex_pkg_PC_EXC;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
exc_pc_mux_o = ibex_pkg_EXC_PC_DBD;
if (ebreak_into_debug && !debug_mode_q) begin
csr_save_cause_o = 1'b1;
csr_save_id_o = 1'b1;
debug_csr_save_o = 1'b1;
debug_cause_o = ibex_pkg_DBG_CAUSE_EBREAK;
end
debug_mode_d = 1'b1;
ctrl_fsm_ns = DECODE;
end
FLUSH: begin
halt_if = 1'b1;
flush_id = 1'b1;
ctrl_fsm_ns = DECODE;
if ((exc_req_q || store_err_q) || load_err_q) begin
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
pc_mux_o = ibex_pkg_PC_EXC;
exc_pc_mux_o = (debug_mode_q ? ibex_pkg_EXC_PC_DBG_EXC : ibex_pkg_EXC_PC_EXC);
if (WritebackStage) begin : g_writeback_mepc_save
csr_save_id_o = ~(store_err_q | load_err_q);
csr_save_wb_o = store_err_q | load_err_q;
end
else begin : g_no_writeback_mepc_save
csr_save_id_o = 1'b0;
end
csr_save_cause_o = 1'b1;
case (1'b1)
instr_fetch_err_prio: begin
exc_cause_o = ibex_pkg_EXC_CAUSE_INSTR_ACCESS_FAULT;
csr_mtval_o = (instr_fetch_err_plus2_i ? pc_id_i + 32'd2 : pc_id_i);
end
illegal_insn_prio: begin
exc_cause_o = ibex_pkg_EXC_CAUSE_ILLEGAL_INSN;
csr_mtval_o = (instr_is_compressed_i ? {16'b0000000000000000, instr_compressed_i} : instr_i);
end
ecall_insn_prio: exc_cause_o = (priv_mode_i == ibex_pkg_PRIV_LVL_M ? ibex_pkg_EXC_CAUSE_ECALL_MMODE : ibex_pkg_EXC_CAUSE_ECALL_UMODE);
ebrk_insn_prio:
if (debug_mode_q | ebreak_into_debug) begin
pc_set_o = 1'b0;
pc_set_spec_o = 1'b0;
csr_save_id_o = 1'b0;
csr_save_cause_o = 1'b0;
ctrl_fsm_ns = DBG_TAKEN_ID;
flush_id = 1'b0;
end
else
exc_cause_o = ibex_pkg_EXC_CAUSE_BREAKPOINT;
store_err_prio: begin
exc_cause_o = ibex_pkg_EXC_CAUSE_STORE_ACCESS_FAULT;
csr_mtval_o = lsu_addr_last_i;
end
load_err_prio: begin
exc_cause_o = ibex_pkg_EXC_CAUSE_LOAD_ACCESS_FAULT;
csr_mtval_o = lsu_addr_last_i;
end
default:
;
endcase
end
else if (mret_insn) begin
pc_mux_o = ibex_pkg_PC_ERET;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
csr_restore_mret_id_o = 1'b1;
if (nmi_mode_q)
nmi_mode_d = 1'b0;
end
else if (dret_insn) begin
pc_mux_o = ibex_pkg_PC_DRET;
pc_set_o = 1'b1;
pc_set_spec_o = 1'b1;
debug_mode_d = 1'b0;
csr_restore_dret_id_o = 1'b1;
end
else if (wfi_insn)
ctrl_fsm_ns = WAIT_SLEEP;
else if (csr_pipe_flush && handle_irq)
ctrl_fsm_ns = IRQ_TAKEN;
if (enter_debug_mode && !(ebrk_insn_prio && ebreak_into_debug))
ctrl_fsm_ns = DBG_TAKEN_IF;
end
default: begin
instr_req_o = 1'b0;
ctrl_fsm_ns = RESET;
end
endcase
end
assign flush_id_o = flush_id;
assign debug_mode_o = debug_mode_q;
assign nmi_mode_o = nmi_mode_q;
assign stall = stall_id_i | stall_wb_i;
assign id_in_ready_o = (~stall & ~halt_if) & ~retain_id;
assign instr_valid_clear_o = ~(stall | retain_id) | flush_id;
always @(posedge clk_i or negedge rst_ni) begin : update_regs
if (!rst_ni) begin
ctrl_fsm_cs <= RESET;
nmi_mode_q <= 1'b0;
debug_mode_q <= 1'b0;
load_err_q <= 1'b0;
store_err_q <= 1'b0;
exc_req_q <= 1'b0;
illegal_insn_q <= 1'b0;
end
else begin
ctrl_fsm_cs <= ctrl_fsm_ns;
nmi_mode_q <= nmi_mode_d;
debug_mode_q <= debug_mode_d;
load_err_q <= load_err_d;
store_err_q <= store_err_d;
exc_req_q <= exc_req_d;
illegal_insn_q <= illegal_insn_d;
end
end
endmodule |
module ibex_compressed_decoder (
clk_i,
rst_ni,
valid_i,
instr_i,
instr_o,
is_compressed_o,
illegal_instr_o
);
input wire clk_i;
input wire rst_ni;
input wire valid_i;
input wire [31:0] instr_i;
output reg [31:0] instr_o;
output wire is_compressed_o;
output reg illegal_instr_o;
wire unused_valid;
assign unused_valid = valid_i;
localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63;
localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f;
localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67;
localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03;
localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37;
localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33;
localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13;
localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23;
always @(*) begin
instr_o = instr_i;
illegal_instr_o = 1'b0;
case (instr_i[1:0])
2'b00:
case (instr_i[15:13])
3'b000: begin
instr_o = {2'b00, instr_i[10:7], instr_i[12:11], instr_i[5], instr_i[6], 2'b00, 5'h02, 3'b000, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_OP_IMM}};
if (instr_i[12:5] == 8'b00000000)
illegal_instr_o = 1'b1;
end
3'b010: instr_o = {5'b00000, instr_i[5], instr_i[12:10], instr_i[6], 2'b00, 2'b01, instr_i[9:7], 3'b010, 2'b01, instr_i[4:2], {ibex_pkg_OPCODE_LOAD}};
3'b110: instr_o = {5'b00000, instr_i[5], instr_i[12], 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b010, instr_i[11:10], instr_i[6], 2'b00, {ibex_pkg_OPCODE_STORE}};
3'b001, 3'b011, 3'b100, 3'b101, 3'b111: illegal_instr_o = 1'b1;
default: illegal_instr_o = 1'b1;
endcase
2'b01:
case (instr_i[15:13])
3'b000: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}};
3'b001, 3'b101: instr_o = {instr_i[12], instr_i[8], instr_i[10:9], instr_i[6], instr_i[7], instr_i[2], instr_i[11], instr_i[5:3], {9 {instr_i[12]}}, 4'b0000, ~instr_i[15], {ibex_pkg_OPCODE_JAL}};
3'b010: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}};
3'b011: begin
instr_o = {{15 {instr_i[12]}}, instr_i[6:2], instr_i[11:7], {ibex_pkg_OPCODE_LUI}};
if (instr_i[11:7] == 5'h02)
instr_o = {{3 {instr_i[12]}}, instr_i[4:3], instr_i[5], instr_i[2], instr_i[6], 4'b0000, 5'h02, 3'b000, 5'h02, {ibex_pkg_OPCODE_OP_IMM}};
if ({instr_i[12], instr_i[6:2]} == 6'b000000)
illegal_instr_o = 1'b1;
end
3'b100:
case (instr_i[11:10])
2'b00, 2'b01: begin
instr_o = {1'b0, instr_i[10], 5'b00000, instr_i[6:2], 2'b01, instr_i[9:7], 3'b101, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}};
if (instr_i[12] == 1'b1)
illegal_instr_o = 1'b1;
end
2'b10: instr_o = {{6 {instr_i[12]}}, instr_i[12], instr_i[6:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP_IMM}};
2'b11:
case ({instr_i[12], instr_i[6:5]})
3'b000: instr_o = {2'b01, 5'b00000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b000, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}};
3'b001: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b100, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}};
3'b010: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b110, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}};
3'b011: instr_o = {7'b0000000, 2'b01, instr_i[4:2], 2'b01, instr_i[9:7], 3'b111, 2'b01, instr_i[9:7], {ibex_pkg_OPCODE_OP}};
3'b100, 3'b101, 3'b110, 3'b111: illegal_instr_o = 1'b1;
default: illegal_instr_o = 1'b1;
endcase
default: illegal_instr_o = 1'b1;
endcase
3'b110, 3'b111: instr_o = {{4 {instr_i[12]}}, instr_i[6:5], instr_i[2], 5'b00000, 2'b01, instr_i[9:7], 2'b00, instr_i[13], instr_i[11:10], instr_i[4:3], instr_i[12], {ibex_pkg_OPCODE_BRANCH}};
default: illegal_instr_o = 1'b1;
endcase
2'b10:
case (instr_i[15:13])
3'b000: begin
instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b001, instr_i[11:7], {ibex_pkg_OPCODE_OP_IMM}};
if (instr_i[12] == 1'b1)
illegal_instr_o = 1'b1;
end
3'b010: begin
instr_o = {4'b0000, instr_i[3:2], instr_i[12], instr_i[6:4], 2'b00, 5'h02, 3'b010, instr_i[11:7], ibex_pkg_OPCODE_LOAD};
if (instr_i[11:7] == 5'b00000)
illegal_instr_o = 1'b1;
end
3'b100:
if (instr_i[12] == 1'b0) begin
if (instr_i[6:2] != 5'b00000)
instr_o = {7'b0000000, instr_i[6:2], 5'b00000, 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}};
else begin
instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00000, {ibex_pkg_OPCODE_JALR}};
if (instr_i[11:7] == 5'b00000)
illegal_instr_o = 1'b1;
end
end
else if (instr_i[6:2] != 5'b00000)
instr_o = {7'b0000000, instr_i[6:2], instr_i[11:7], 3'b000, instr_i[11:7], {ibex_pkg_OPCODE_OP}};
else if (instr_i[11:7] == 5'b00000)
instr_o = 32'h00100073;
else
instr_o = {12'b000000000000, instr_i[11:7], 3'b000, 5'b00001, {ibex_pkg_OPCODE_JALR}};
3'b110: instr_o = {4'b0000, instr_i[8:7], instr_i[12], instr_i[6:2], 5'h02, 3'b010, instr_i[11:9], 2'b00, {ibex_pkg_OPCODE_STORE}};
3'b001, 3'b011, 3'b101, 3'b111: illegal_instr_o = 1'b1;
default: illegal_instr_o = 1'b1;
endcase
2'b11:
;
default: illegal_instr_o = 1'b1;
endcase
end
assign is_compressed_o = instr_i[1:0] != 2'b11;
endmodule |
module ibex_load_store_unit (
clk_i,
rst_ni,
data_req_o,
data_gnt_i,
data_rvalid_i,
data_err_i,
data_pmp_err_i,
data_addr_o,
data_we_o,
data_be_o,
data_wdata_o,
data_rdata_i,
lsu_we_i,
lsu_type_i,
lsu_wdata_i,
lsu_sign_ext_i,
lsu_rdata_o,
lsu_rdata_valid_o,
lsu_req_i,
adder_result_ex_i,
addr_incr_req_o,
addr_last_o,
lsu_req_done_o,
lsu_resp_valid_o,
load_err_o,
store_err_o,
busy_o,
perf_load_o,
perf_store_o
);
input wire clk_i;
input wire rst_ni;
output reg data_req_o;
input wire data_gnt_i;
input wire data_rvalid_i;
input wire data_err_i;
input wire data_pmp_err_i;
output wire [31:0] data_addr_o;
output wire data_we_o;
output wire [3:0] data_be_o;
output wire [31:0] data_wdata_o;
input wire [31:0] data_rdata_i;
input wire lsu_we_i;
input wire [1:0] lsu_type_i;
input wire [31:0] lsu_wdata_i;
input wire lsu_sign_ext_i;
output wire [31:0] lsu_rdata_o;
output wire lsu_rdata_valid_o;
input wire lsu_req_i;
input wire [31:0] adder_result_ex_i;
output reg addr_incr_req_o;
output wire [31:0] addr_last_o;
output wire lsu_req_done_o;
output wire lsu_resp_valid_o;
output wire load_err_o;
output wire store_err_o;
output wire busy_o;
output reg perf_load_o;
output reg perf_store_o;
wire [31:0] data_addr;
wire [31:0] data_addr_w_aligned;
reg [31:0] addr_last_q;
reg addr_update;
reg ctrl_update;
reg rdata_update;
reg [31:8] rdata_q;
reg [1:0] rdata_offset_q;
reg [1:0] data_type_q;
reg data_sign_ext_q;
reg data_we_q;
wire [1:0] data_offset;
reg [3:0] data_be;
reg [31:0] data_wdata;
reg [31:0] data_rdata_ext;
reg [31:0] rdata_w_ext;
reg [31:0] rdata_h_ext;
reg [31:0] rdata_b_ext;
wire split_misaligned_access;
reg handle_misaligned_q;
reg handle_misaligned_d;
reg pmp_err_q;
reg pmp_err_d;
reg lsu_err_q;
reg lsu_err_d;
wire data_or_pmp_err;
reg [2:0] ls_fsm_cs;
reg [2:0] ls_fsm_ns;
assign data_addr = adder_result_ex_i;
assign data_offset = data_addr[1:0];
always @(*)
case (lsu_type_i)
2'b00:
if (!handle_misaligned_q)
case (data_offset)
2'b00: data_be = 4'b1111;
2'b01: data_be = 4'b1110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
else
case (data_offset)
2'b00: data_be = 4'b0000;
2'b01: data_be = 4'b0001;
2'b10: data_be = 4'b0011;
2'b11: data_be = 4'b0111;
default: data_be = 4'b1111;
endcase
2'b01:
if (!handle_misaligned_q)
case (data_offset)
2'b00: data_be = 4'b0011;
2'b01: data_be = 4'b0110;
2'b10: data_be = 4'b1100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
else
data_be = 4'b0001;
2'b10, 2'b11:
case (data_offset)
2'b00: data_be = 4'b0001;
2'b01: data_be = 4'b0010;
2'b10: data_be = 4'b0100;
2'b11: data_be = 4'b1000;
default: data_be = 4'b1111;
endcase
default: data_be = 4'b1111;
endcase
always @(*)
case (data_offset)
2'b00: data_wdata = lsu_wdata_i[31:0];
2'b01: data_wdata = {lsu_wdata_i[23:0], lsu_wdata_i[31:24]};
2'b10: data_wdata = {lsu_wdata_i[15:0], lsu_wdata_i[31:16]};
2'b11: data_wdata = {lsu_wdata_i[7:0], lsu_wdata_i[31:8]};
default: data_wdata = lsu_wdata_i[31:0];
endcase
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rdata_q <= {24 {1'sb0}};
else if (rdata_update)
rdata_q <= data_rdata_i[31:8];
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
rdata_offset_q <= 2'h0;
data_type_q <= 2'h0;
data_sign_ext_q <= 1'b0;
data_we_q <= 1'b0;
end
else if (ctrl_update) begin
rdata_offset_q <= data_offset;
data_type_q <= lsu_type_i;
data_sign_ext_q <= lsu_sign_ext_i;
data_we_q <= lsu_we_i;
end
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
addr_last_q <= {32 {1'sb0}};
else if (addr_update)
addr_last_q <= data_addr;
always @(*)
case (rdata_offset_q)
2'b00: rdata_w_ext = data_rdata_i[31:0];
2'b01: rdata_w_ext = {data_rdata_i[7:0], rdata_q[31:8]};
2'b10: rdata_w_ext = {data_rdata_i[15:0], rdata_q[31:16]};
2'b11: rdata_w_ext = {data_rdata_i[23:0], rdata_q[31:24]};
default: rdata_w_ext = data_rdata_i[31:0];
endcase
always @(*)
case (rdata_offset_q)
2'b00:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
else
rdata_h_ext = {{16 {data_rdata_i[15]}}, data_rdata_i[15:0]};
2'b01:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[23:8]};
else
rdata_h_ext = {{16 {data_rdata_i[23]}}, data_rdata_i[23:8]};
2'b10:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[31:16]};
else
rdata_h_ext = {{16 {data_rdata_i[31]}}, data_rdata_i[31:16]};
2'b11:
if (!data_sign_ext_q)
rdata_h_ext = {16'h0000, data_rdata_i[7:0], rdata_q[31:24]};
else
rdata_h_ext = {{16 {data_rdata_i[7]}}, data_rdata_i[7:0], rdata_q[31:24]};
default: rdata_h_ext = {16'h0000, data_rdata_i[15:0]};
endcase
always @(*)
case (rdata_offset_q)
2'b00:
if (!data_sign_ext_q)
rdata_b_ext = {24'h000000, data_rdata_i[7:0]};
else
rdata_b_ext = {{24 {data_rdata_i[7]}}, data_rdata_i[7:0]};
2'b01:
if (!data_sign_ext_q)
rdata_b_ext = {24'h000000, data_rdata_i[15:8]};
else
rdata_b_ext = {{24 {data_rdata_i[15]}}, data_rdata_i[15:8]};
2'b10:
if (!data_sign_ext_q)
rdata_b_ext = {24'h000000, data_rdata_i[23:16]};
else
rdata_b_ext = {{24 {data_rdata_i[23]}}, data_rdata_i[23:16]};
2'b11:
if (!data_sign_ext_q)
rdata_b_ext = {24'h000000, data_rdata_i[31:24]};
else
rdata_b_ext = {{24 {data_rdata_i[31]}}, data_rdata_i[31:24]};
default: rdata_b_ext = {24'h000000, data_rdata_i[7:0]};
endcase
always @(*)
case (data_type_q)
2'b00: data_rdata_ext = rdata_w_ext;
2'b01: data_rdata_ext = rdata_h_ext;
2'b10, 2'b11: data_rdata_ext = rdata_b_ext;
default: data_rdata_ext = rdata_w_ext;
endcase
assign split_misaligned_access = ((lsu_type_i == 2'b00) && (data_offset != 2'b00)) || ((lsu_type_i == 2'b01) && (data_offset == 2'b11));
localparam [2:0] IDLE = 0;
localparam [2:0] WAIT_GNT = 3;
localparam [2:0] WAIT_GNT_MIS = 1;
localparam [2:0] WAIT_RVALID_MIS = 2;
localparam [2:0] WAIT_RVALID_MIS_GNTS_DONE = 4;
always @(*) begin
ls_fsm_ns = ls_fsm_cs;
data_req_o = 1'b0;
addr_incr_req_o = 1'b0;
handle_misaligned_d = handle_misaligned_q;
pmp_err_d = pmp_err_q;
lsu_err_d = lsu_err_q;
addr_update = 1'b0;
ctrl_update = 1'b0;
rdata_update = 1'b0;
perf_load_o = 1'b0;
perf_store_o = 1'b0;
case (ls_fsm_cs)
IDLE: begin
pmp_err_d = 1'b0;
if (lsu_req_i) begin
data_req_o = 1'b1;
pmp_err_d = data_pmp_err_i;
lsu_err_d = 1'b0;
perf_load_o = ~lsu_we_i;
perf_store_o = lsu_we_i;
if (data_gnt_i) begin
ctrl_update = 1'b1;
addr_update = 1'b1;
handle_misaligned_d = split_misaligned_access;
ls_fsm_ns = (split_misaligned_access ? WAIT_RVALID_MIS : IDLE);
end
else
ls_fsm_ns = (split_misaligned_access ? WAIT_GNT_MIS : WAIT_GNT);
end
end
WAIT_GNT_MIS: begin
data_req_o = 1'b1;
if (data_gnt_i || pmp_err_q) begin
addr_update = 1'b1;
ctrl_update = 1'b1;
handle_misaligned_d = 1'b1;
ls_fsm_ns = WAIT_RVALID_MIS;
end
end
WAIT_RVALID_MIS: begin
data_req_o = 1'b1;
addr_incr_req_o = 1'b1;
if (data_rvalid_i || pmp_err_q) begin
pmp_err_d = data_pmp_err_i;
lsu_err_d = data_err_i | pmp_err_q;
rdata_update = ~data_we_q;
ls_fsm_ns = (data_gnt_i ? IDLE : WAIT_GNT);
addr_update = data_gnt_i & ~(data_err_i | pmp_err_q);
handle_misaligned_d = ~data_gnt_i;
end
else if (data_gnt_i) begin
ls_fsm_ns = WAIT_RVALID_MIS_GNTS_DONE;
handle_misaligned_d = 1'b0;
end
end
WAIT_GNT: begin
addr_incr_req_o = handle_misaligned_q;
data_req_o = 1'b1;
if (data_gnt_i || pmp_err_q) begin
ctrl_update = 1'b1;
addr_update = ~lsu_err_q;
ls_fsm_ns = IDLE;
handle_misaligned_d = 1'b0;
end
end
WAIT_RVALID_MIS_GNTS_DONE: begin
addr_incr_req_o = 1'b1;
if (data_rvalid_i) begin
pmp_err_d = data_pmp_err_i;
lsu_err_d = data_err_i;
addr_update = ~data_err_i;
rdata_update = ~data_we_q;
ls_fsm_ns = IDLE;
end
end
default: ls_fsm_ns = IDLE;
endcase
end
assign lsu_req_done_o = (lsu_req_i | (ls_fsm_cs != IDLE)) & (ls_fsm_ns == IDLE);
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni) begin
ls_fsm_cs <= IDLE;
handle_misaligned_q <= 1'b0;
pmp_err_q <= 1'b0;
lsu_err_q <= 1'b0;
end
else begin
ls_fsm_cs <= ls_fsm_ns;
handle_misaligned_q <= handle_misaligned_d;
pmp_err_q <= pmp_err_d;
lsu_err_q <= lsu_err_d;
end
assign data_or_pmp_err = (lsu_err_q | data_err_i) | pmp_err_q;
assign lsu_resp_valid_o = (data_rvalid_i | pmp_err_q) & (ls_fsm_cs == IDLE);
assign lsu_rdata_valid_o = (((ls_fsm_cs == IDLE) & data_rvalid_i) & ~data_or_pmp_err) & ~data_we_q;
assign lsu_rdata_o = data_rdata_ext;
assign data_addr_w_aligned = {data_addr[31:2], 2'b00};
assign data_addr_o = data_addr_w_aligned;
assign data_wdata_o = data_wdata;
assign data_we_o = lsu_we_i;
assign data_be_o = data_be;
assign addr_last_o = addr_last_q;
assign load_err_o = (data_or_pmp_err & ~data_we_q) & lsu_resp_valid_o;
assign store_err_o = (data_or_pmp_err & data_we_q) & lsu_resp_valid_o;
assign busy_o = ls_fsm_cs != IDLE;
endmodule |
module ibex_register_file_fpga (
clk_i,
rst_ni,
test_en_i,
dummy_instr_id_i,
raddr_a_i,
rdata_a_o,
raddr_b_i,
rdata_b_o,
waddr_a_i,
wdata_a_i,
we_a_i
);
parameter [0:0] RV32E = 0;
parameter [31:0] DataWidth = 32;
parameter [0:0] DummyInstructions = 0;
input wire clk_i;
input wire rst_ni;
input wire test_en_i;
input wire dummy_instr_id_i;
input wire [4:0] raddr_a_i;
output wire [DataWidth - 1:0] rdata_a_o;
input wire [4:0] raddr_b_i;
output wire [DataWidth - 1:0] rdata_b_o;
input wire [4:0] waddr_a_i;
input wire [DataWidth - 1:0] wdata_a_i;
input wire we_a_i;
localparam signed [31:0] ADDR_WIDTH = (RV32E ? 4 : 5);
localparam signed [31:0] NUM_WORDS = 2 ** ADDR_WIDTH;
reg [DataWidth - 1:0] mem [0:NUM_WORDS - 1];
wire we;
assign rdata_a_o = (raddr_a_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_a_i]);
assign rdata_b_o = (raddr_b_i == {5 {1'sb0}} ? {DataWidth {1'sb0}} : mem[raddr_b_i]);
assign we = (waddr_a_i == {5 {1'sb0}} ? 1'b0 : we_a_i);
always @(posedge clk_i) begin : sync_write
if (we == 1'b1)
mem[waddr_a_i] <= wdata_a_i;
end
wire unused_rst_ni;
assign unused_rst_ni = rst_ni;
wire unused_dummy_instr;
assign unused_dummy_instr = dummy_instr_id_i;
wire unused_test_en;
assign unused_test_en = test_en_i;
endmodule |
module ibex_fetch_fifo (
clk_i,
rst_ni,
clear_i,
busy_o,
in_valid_i,
in_addr_i,
in_rdata_i,
in_err_i,
out_valid_o,
out_ready_i,
out_addr_o,
out_addr_next_o,
out_rdata_o,
out_err_o,
out_err_plus2_o
);
parameter [31:0] NUM_REQS = 2;
input wire clk_i;
input wire rst_ni;
input wire clear_i;
output wire [NUM_REQS - 1:0] busy_o;
input wire in_valid_i;
input wire [31:0] in_addr_i;
input wire [31:0] in_rdata_i;
input wire in_err_i;
output reg out_valid_o;
input wire out_ready_i;
output wire [31:0] out_addr_o;
output wire [31:0] out_addr_next_o;
output reg [31:0] out_rdata_o;
output reg out_err_o;
output reg out_err_plus2_o;
localparam [31:0] DEPTH = NUM_REQS + 1;
wire [(DEPTH * 32) - 1:0] rdata_d;
reg [(DEPTH * 32) - 1:0] rdata_q;
wire [DEPTH - 1:0] err_d;
reg [DEPTH - 1:0] err_q;
wire [DEPTH - 1:0] valid_d;
reg [DEPTH - 1:0] valid_q;
wire [DEPTH - 1:0] lowest_free_entry;
wire [DEPTH - 1:0] valid_pushed;
wire [DEPTH - 1:0] valid_popped;
wire [DEPTH - 1:0] entry_en;
wire pop_fifo;
wire [31:0] rdata;
wire [31:0] rdata_unaligned;
wire err;
wire err_unaligned;
wire err_plus2;
wire valid;
wire valid_unaligned;
wire aligned_is_compressed;
wire unaligned_is_compressed;
wire addr_incr_two;
wire [31:1] instr_addr_next;
wire [31:1] instr_addr_d;
reg [31:1] instr_addr_q;
wire instr_addr_en;
wire unused_addr_in;
assign rdata = (valid_q[0] ? rdata_q[0+:32] : in_rdata_i);
assign err = (valid_q[0] ? err_q[0] : in_err_i);
assign valid = valid_q[0] | in_valid_i;
assign rdata_unaligned = (valid_q[1] ? {rdata_q[47-:16], rdata[31:16]} : {in_rdata_i[15:0], rdata[31:16]});
assign err_unaligned = (valid_q[1] ? (err_q[1] & ~unaligned_is_compressed) | err_q[0] : (valid_q[0] & err_q[0]) | (in_err_i & (~valid_q[0] | ~unaligned_is_compressed)));
assign err_plus2 = (valid_q[1] ? err_q[1] & ~err_q[0] : (in_err_i & valid_q[0]) & ~err_q[0]);
assign valid_unaligned = (valid_q[1] ? 1'b1 : valid_q[0] & in_valid_i);
assign unaligned_is_compressed = (rdata[17:16] != 2'b11) & ~err;
assign aligned_is_compressed = (rdata[1:0] != 2'b11) & ~err;
always @(*)
if (out_addr_o[1]) begin
out_rdata_o = rdata_unaligned;
out_err_o = err_unaligned;
out_err_plus2_o = err_plus2;
if (unaligned_is_compressed)
out_valid_o = valid;
else
out_valid_o = valid_unaligned;
end
else begin
out_rdata_o = rdata;
out_err_o = err;
out_err_plus2_o = 1'b0;
out_valid_o = valid;
end
assign instr_addr_en = clear_i | (out_ready_i & out_valid_o);
assign addr_incr_two = (instr_addr_q[1] ? unaligned_is_compressed : aligned_is_compressed);
assign instr_addr_next = instr_addr_q[31:1] + {29'd0, ~addr_incr_two, addr_incr_two};
assign instr_addr_d = (clear_i ? in_addr_i[31:1] : instr_addr_next);
always @(posedge clk_i)
if (instr_addr_en)
instr_addr_q <= instr_addr_d;
assign out_addr_next_o = {instr_addr_next, 1'b0};
assign out_addr_o = {instr_addr_q, 1'b0};
assign unused_addr_in = in_addr_i[0];
assign busy_o = valid_q[DEPTH - 1:DEPTH - NUM_REQS];
assign pop_fifo = (out_ready_i & out_valid_o) & (~aligned_is_compressed | out_addr_o[1]);
generate
genvar i;
for (i = 0; i < (DEPTH - 1); i = i + 1) begin : g_fifo_next
if (i == 0) begin : g_ent0
assign lowest_free_entry[i] = ~valid_q[i];
end
else begin : g_ent_others
assign lowest_free_entry[i] = ~valid_q[i] & valid_q[i - 1];
end
assign valid_pushed[i] = (in_valid_i & lowest_free_entry[i]) | valid_q[i];
assign valid_popped[i] = (pop_fifo ? valid_pushed[i + 1] : valid_pushed[i]);
assign valid_d[i] = valid_popped[i] & ~clear_i;
assign entry_en[i] = (valid_pushed[i + 1] & pop_fifo) | ((in_valid_i & lowest_free_entry[i]) & ~pop_fifo);
assign rdata_d[i * 32+:32] = (valid_q[i + 1] ? rdata_q[(i + 1) * 32+:32] : in_rdata_i);
assign err_d[i] = (valid_q[i + 1] ? err_q[i + 1] : in_err_i);
end
endgenerate
assign lowest_free_entry[DEPTH - 1] = ~valid_q[DEPTH - 1] & valid_q[DEPTH - 2];
assign valid_pushed[DEPTH - 1] = valid_q[DEPTH - 1] | (in_valid_i & lowest_free_entry[DEPTH - 1]);
assign valid_popped[DEPTH - 1] = (pop_fifo ? 1'b0 : valid_pushed[DEPTH - 1]);
assign valid_d[DEPTH - 1] = valid_popped[DEPTH - 1] & ~clear_i;
assign entry_en[DEPTH - 1] = in_valid_i & lowest_free_entry[DEPTH - 1];
assign rdata_d[(DEPTH - 1) * 32+:32] = in_rdata_i;
assign err_d[DEPTH - 1] = in_err_i;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
valid_q <= {DEPTH {1'sb0}};
else
valid_q <= valid_d;
generate
for (i = 0; i < DEPTH; i = i + 1) begin : g_fifo_regs
always @(posedge clk_i)
if (entry_en[i]) begin
rdata_q[i * 32+:32] <= rdata_d[i * 32+:32];
err_q[i] <= err_d[i];
end
end
endgenerate
endmodule |
module prim_secded_72_64_dec (
in,
d_o,
syndrome_o,
err_o
);
input [71:0] in;
output wire [63:0] d_o;
output wire [7:0] syndrome_o;
output wire [1:0] err_o;
wire single_error;
assign syndrome_o[0] = (((((((((((((((((((((((((in[64] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[62]) ^ in[63];
assign syndrome_o[1] = (((((((((((((((((((((((((in[65] ^ in[0]) ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[33]) ^ in[34]) ^ in[35]) ^ in[58]) ^ in[59]) ^ in[60]) ^ in[62]) ^ in[63];
assign syndrome_o[2] = (((((((((((((((((((((((((in[66] ^ in[0]) ^ in[6]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[21]) ^ in[22]) ^ in[23]) ^ in[24]) ^ in[25]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[43]) ^ in[44]) ^ in[45]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[63];
assign syndrome_o[3] = (((((((((((((((((((((((((in[67] ^ in[1]) ^ in[6]) ^ in[11]) ^ in[12]) ^ in[13]) ^ in[14]) ^ in[21]) ^ in[26]) ^ in[27]) ^ in[28]) ^ in[29]) ^ in[36]) ^ in[37]) ^ in[38]) ^ in[39]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[49]) ^ in[50]) ^ in[51]) ^ in[56]) ^ in[57]) ^ in[58]) ^ in[61]) ^ in[63];
assign syndrome_o[4] = (((((((((((((((((((((((((in[68] ^ in[2]) ^ in[7]) ^ in[11]) ^ in[15]) ^ in[16]) ^ in[17]) ^ in[22]) ^ in[26]) ^ in[30]) ^ in[31]) ^ in[32]) ^ in[36]) ^ in[40]) ^ in[41]) ^ in[42]) ^ in[46]) ^ in[47]) ^ in[48]) ^ in[52]) ^ in[53]) ^ in[54]) ^ in[56]) ^ in[58]) ^ in[59]) ^ in[61]) ^ in[62];
assign syndrome_o[5] = (((((((((((((((((((((((((in[69] ^ in[3]) ^ in[8]) ^ in[12]) ^ in[15]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[27]) ^ in[30]) ^ in[33]) ^ in[34]) ^ in[37]) ^ in[40]) ^ in[43]) ^ in[44]) ^ in[46]) ^ in[49]) ^ in[50]) ^ in[52]) ^ in[53]) ^ in[55]) ^ in[56]) ^ in[57]) ^ in[59]) ^ in[60]) ^ in[61];
assign syndrome_o[6] = (((((((((((((((((((((((((in[70] ^ in[4]) ^ in[9]) ^ in[13]) ^ in[16]) ^ in[18]) ^ in[20]) ^ in[24]) ^ in[28]) ^ in[31]) ^ in[33]) ^ in[35]) ^ in[38]) ^ in[41]) ^ in[43]) ^ in[45]) ^ in[47]) ^ in[49]) ^ in[51]) ^ in[52]) ^ in[54]) ^ in[55]) ^ in[56]) ^ in[59]) ^ in[60]) ^ in[61]) ^ in[62];
assign syndrome_o[7] = (((((((((((((((((((((((((in[71] ^ in[5]) ^ in[10]) ^ in[14]) ^ in[17]) ^ in[19]) ^ in[20]) ^ in[25]) ^ in[29]) ^ in[32]) ^ in[34]) ^ in[35]) ^ in[39]) ^ in[42]) ^ in[44]) ^ in[45]) ^ in[48]) ^ in[50]) ^ in[51]) ^ in[53]) ^ in[54]) ^ in[55]) ^ in[57]) ^ in[58]) ^ in[60]) ^ in[62]) ^ in[63];
assign d_o[0] = (syndrome_o == 8'h07) ^ in[0];
assign d_o[1] = (syndrome_o == 8'h0b) ^ in[1];
assign d_o[2] = (syndrome_o == 8'h13) ^ in[2];
assign d_o[3] = (syndrome_o == 8'h23) ^ in[3];
assign d_o[4] = (syndrome_o == 8'h43) ^ in[4];
assign d_o[5] = (syndrome_o == 8'h83) ^ in[5];
assign d_o[6] = (syndrome_o == 8'h0d) ^ in[6];
assign d_o[7] = (syndrome_o == 8'h15) ^ in[7];
assign d_o[8] = (syndrome_o == 8'h25) ^ in[8];
assign d_o[9] = (syndrome_o == 8'h45) ^ in[9];
assign d_o[10] = (syndrome_o == 8'h85) ^ in[10];
assign d_o[11] = (syndrome_o == 8'h19) ^ in[11];
assign d_o[12] = (syndrome_o == 8'h29) ^ in[12];
assign d_o[13] = (syndrome_o == 8'h49) ^ in[13];
assign d_o[14] = (syndrome_o == 8'h89) ^ in[14];
assign d_o[15] = (syndrome_o == 8'h31) ^ in[15];
assign d_o[16] = (syndrome_o == 8'h51) ^ in[16];
assign d_o[17] = (syndrome_o == 8'h91) ^ in[17];
assign d_o[18] = (syndrome_o == 8'h61) ^ in[18];
assign d_o[19] = (syndrome_o == 8'ha1) ^ in[19];
assign d_o[20] = (syndrome_o == 8'hc1) ^ in[20];
assign d_o[21] = (syndrome_o == 8'h0e) ^ in[21];
assign d_o[22] = (syndrome_o == 8'h16) ^ in[22];
assign d_o[23] = (syndrome_o == 8'h26) ^ in[23];
assign d_o[24] = (syndrome_o == 8'h46) ^ in[24];
assign d_o[25] = (syndrome_o == 8'h86) ^ in[25];
assign d_o[26] = (syndrome_o == 8'h1a) ^ in[26];
assign d_o[27] = (syndrome_o == 8'h2a) ^ in[27];
assign d_o[28] = (syndrome_o == 8'h4a) ^ in[28];
assign d_o[29] = (syndrome_o == 8'h8a) ^ in[29];
assign d_o[30] = (syndrome_o == 8'h32) ^ in[30];
assign d_o[31] = (syndrome_o == 8'h52) ^ in[31];
assign d_o[32] = (syndrome_o == 8'h92) ^ in[32];
assign d_o[33] = (syndrome_o == 8'h62) ^ in[33];
assign d_o[34] = (syndrome_o == 8'ha2) ^ in[34];
assign d_o[35] = (syndrome_o == 8'hc2) ^ in[35];
assign d_o[36] = (syndrome_o == 8'h1c) ^ in[36];
assign d_o[37] = (syndrome_o == 8'h2c) ^ in[37];
assign d_o[38] = (syndrome_o == 8'h4c) ^ in[38];
assign d_o[39] = (syndrome_o == 8'h8c) ^ in[39];
assign d_o[40] = (syndrome_o == 8'h34) ^ in[40];
assign d_o[41] = (syndrome_o == 8'h54) ^ in[41];
assign d_o[42] = (syndrome_o == 8'h94) ^ in[42];
assign d_o[43] = (syndrome_o == 8'h64) ^ in[43];
assign d_o[44] = (syndrome_o == 8'ha4) ^ in[44];
assign d_o[45] = (syndrome_o == 8'hc4) ^ in[45];
assign d_o[46] = (syndrome_o == 8'h38) ^ in[46];
assign d_o[47] = (syndrome_o == 8'h58) ^ in[47];
assign d_o[48] = (syndrome_o == 8'h98) ^ in[48];
assign d_o[49] = (syndrome_o == 8'h68) ^ in[49];
assign d_o[50] = (syndrome_o == 8'ha8) ^ in[50];
assign d_o[51] = (syndrome_o == 8'hc8) ^ in[51];
assign d_o[52] = (syndrome_o == 8'h70) ^ in[52];
assign d_o[53] = (syndrome_o == 8'hb0) ^ in[53];
assign d_o[54] = (syndrome_o == 8'hd0) ^ in[54];
assign d_o[55] = (syndrome_o == 8'he0) ^ in[55];
assign d_o[56] = (syndrome_o == 8'h7c) ^ in[56];
assign d_o[57] = (syndrome_o == 8'had) ^ in[57];
assign d_o[58] = (syndrome_o == 8'h9b) ^ in[58];
assign d_o[59] = (syndrome_o == 8'h76) ^ in[59];
assign d_o[60] = (syndrome_o == 8'he6) ^ in[60];
assign d_o[61] = (syndrome_o == 8'h79) ^ in[61];
assign d_o[62] = (syndrome_o == 8'hd3) ^ in[62];
assign d_o[63] = (syndrome_o == 8'h8f) ^ in[63];
assign single_error = ^syndrome_o;
assign err_o[0] = single_error;
assign err_o[1] = ~single_error & |syndrome_o;
endmodule |
module prim_clock_gating (
input clk_i,
input en_i,
input test_en_i,
output clk_o
);
reg en_latch;
always @* begin
if (!clk_i) begin
en_latch = en_i | test_en_i;
end
end
assign clk_o = en_latch & clk_i;
endmodule |
module prim_secded_39_32_dec (
in,
d_o,
syndrome_o,
err_o
);
input [38:0] in;
output wire [31:0] d_o;
output wire [6:0] syndrome_o;
output wire [1:0] err_o;
wire single_error;
assign syndrome_o[0] = ((((((((((((in[32] ^ in[2]) ^ in[3]) ^ in[7]) ^ in[8]) ^ in[14]) ^ in[15]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[23]) ^ in[24]) ^ in[28]) ^ in[29];
assign syndrome_o[1] = (((((((((((((in[33] ^ in[3]) ^ in[6]) ^ in[8]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[17]) ^ in[19]) ^ in[21]) ^ in[25]) ^ in[27]) ^ in[29]) ^ in[30]) ^ in[31];
assign syndrome_o[2] = (((((((((((((in[34] ^ in[0]) ^ in[5]) ^ in[7]) ^ in[9]) ^ in[10]) ^ in[12]) ^ in[13]) ^ in[15]) ^ in[16]) ^ in[22]) ^ in[23]) ^ in[26]) ^ in[27]) ^ in[31];
assign syndrome_o[3] = (((((((((((((in[35] ^ in[0]) ^ in[1]) ^ in[4]) ^ in[6]) ^ in[9]) ^ in[11]) ^ in[12]) ^ in[14]) ^ in[22]) ^ in[23]) ^ in[25]) ^ in[28]) ^ in[29]) ^ in[30];
assign syndrome_o[4] = (((((((((((in[36] ^ in[0]) ^ in[2]) ^ in[3]) ^ in[4]) ^ in[5]) ^ in[11]) ^ in[17]) ^ in[20]) ^ in[24]) ^ in[26]) ^ in[27]) ^ in[30];
assign syndrome_o[5] = (((((((((((((in[37] ^ in[1]) ^ in[2]) ^ in[4]) ^ in[6]) ^ in[10]) ^ in[13]) ^ in[14]) ^ in[16]) ^ in[18]) ^ in[19]) ^ in[20]) ^ in[21]) ^ in[22]) ^ in[26];
assign syndrome_o[6] = ((((((((((((((in[38] ^ in[1]) ^ in[5]) ^ in[7]) ^ in[8]) ^ in[9]) ^ in[10]) ^ in[11]) ^ in[17]) ^ in[18]) ^ in[20]) ^ in[21]) ^ in[24]) ^ in[25]) ^ in[28]) ^ in[31];
assign d_o[0] = (syndrome_o == 7'h1c) ^ in[0];
assign d_o[1] = (syndrome_o == 7'h68) ^ in[1];
assign d_o[2] = (syndrome_o == 7'h31) ^ in[2];
assign d_o[3] = (syndrome_o == 7'h13) ^ in[3];
assign d_o[4] = (syndrome_o == 7'h38) ^ in[4];
assign d_o[5] = (syndrome_o == 7'h54) ^ in[5];
assign d_o[6] = (syndrome_o == 7'h2a) ^ in[6];
assign d_o[7] = (syndrome_o == 7'h45) ^ in[7];
assign d_o[8] = (syndrome_o == 7'h43) ^ in[8];
assign d_o[9] = (syndrome_o == 7'h4c) ^ in[9];
assign d_o[10] = (syndrome_o == 7'h64) ^ in[10];
assign d_o[11] = (syndrome_o == 7'h58) ^ in[11];
assign d_o[12] = (syndrome_o == 7'h0e) ^ in[12];
assign d_o[13] = (syndrome_o == 7'h26) ^ in[13];
assign d_o[14] = (syndrome_o == 7'h29) ^ in[14];
assign d_o[15] = (syndrome_o == 7'h07) ^ in[15];
assign d_o[16] = (syndrome_o == 7'h25) ^ in[16];
assign d_o[17] = (syndrome_o == 7'h52) ^ in[17];
assign d_o[18] = (syndrome_o == 7'h61) ^ in[18];
assign d_o[19] = (syndrome_o == 7'h23) ^ in[19];
assign d_o[20] = (syndrome_o == 7'h70) ^ in[20];
assign d_o[21] = (syndrome_o == 7'h62) ^ in[21];
assign d_o[22] = (syndrome_o == 7'h2c) ^ in[22];
assign d_o[23] = (syndrome_o == 7'h0d) ^ in[23];
assign d_o[24] = (syndrome_o == 7'h51) ^ in[24];
assign d_o[25] = (syndrome_o == 7'h4a) ^ in[25];
assign d_o[26] = (syndrome_o == 7'h34) ^ in[26];
assign d_o[27] = (syndrome_o == 7'h16) ^ in[27];
assign d_o[28] = (syndrome_o == 7'h49) ^ in[28];
assign d_o[29] = (syndrome_o == 7'h0b) ^ in[29];
assign d_o[30] = (syndrome_o == 7'h1a) ^ in[30];
assign d_o[31] = (syndrome_o == 7'h46) ^ in[31];
assign single_error = ^syndrome_o;
assign err_o[0] = single_error;
assign err_o[1] = ~single_error & |syndrome_o;
endmodule |
module ibex_pmp (
clk_i,
rst_ni,
csr_pmp_cfg_i,
csr_pmp_addr_i,
priv_mode_i,
pmp_req_addr_i,
pmp_req_type_i,
pmp_req_err_o
);
parameter [31:0] PMPGranularity = 0;
parameter [31:0] PMPNumChan = 2;
parameter [31:0] PMPNumRegions = 4;
input wire clk_i;
input wire rst_ni;
input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 6) + (((PMPNumRegions - 1) * 6) - 1) : (PMPNumRegions * 6) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 6 : 0)] csr_pmp_cfg_i;
input wire [(0 >= (PMPNumRegions - 1) ? ((2 - PMPNumRegions) * 34) + (((PMPNumRegions - 1) * 34) - 1) : (PMPNumRegions * 34) - 1):(0 >= (PMPNumRegions - 1) ? (PMPNumRegions - 1) * 34 : 0)] csr_pmp_addr_i;
input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] priv_mode_i;
input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 34) + (((PMPNumChan - 1) * 34) - 1) : (PMPNumChan * 34) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 34 : 0)] pmp_req_addr_i;
input wire [(0 >= (PMPNumChan - 1) ? ((2 - PMPNumChan) * 2) + (((PMPNumChan - 1) * 2) - 1) : (PMPNumChan * 2) - 1):(0 >= (PMPNumChan - 1) ? (PMPNumChan - 1) * 2 : 0)] pmp_req_type_i;
output wire [0:PMPNumChan - 1] pmp_req_err_o;
wire [33:0] region_start_addr [0:PMPNumRegions - 1];
wire [33:PMPGranularity + 2] region_addr_mask [0:PMPNumRegions - 1];
wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_gt;
wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_lt;
wire [(PMPNumChan * PMPNumRegions) - 1:0] region_match_eq;
reg [(PMPNumChan * PMPNumRegions) - 1:0] region_match_all;
wire [(PMPNumChan * PMPNumRegions) - 1:0] region_perm_check;
reg [PMPNumChan - 1:0] access_fault;
localparam [1:0] ibex_pkg_PMP_MODE_NAPOT = 2'b11;
localparam [1:0] ibex_pkg_PMP_MODE_TOR = 2'b01;
generate
genvar r;
for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_addr_exp
if (r == 0) begin : g_entry0
assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? 34'h000000000 : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]);
end
else begin : g_oth
assign region_start_addr[r] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] == ibex_pkg_PMP_MODE_TOR ? csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r - 1 : (PMPNumRegions - 1) - (r - 1)) * 34+:34] : csr_pmp_addr_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34+:34]);
end
genvar b;
for (b = PMPGranularity + 2; b < 34; b = b + 1) begin : g_bitmask
if (b == 2) begin : g_bit0
assign region_addr_mask[r][b] = csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT;
end
else begin : g_others
assign region_addr_mask[r][b] = (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2] != ibex_pkg_PMP_MODE_NAPOT) | ~&csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + ((b - 1) >= (PMPGranularity + 1) ? b - 1 : ((b - 1) + ((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)) - 1)-:((b - 1) >= (PMPGranularity + 1) ? ((b - 1) - (PMPGranularity + 1)) + 1 : ((PMPGranularity + 1) - (b - 1)) + 1)];
end
end
end
endgenerate
localparam [1:0] ibex_pkg_PMP_ACC_EXEC = 2'b00;
localparam [1:0] ibex_pkg_PMP_ACC_READ = 2'b10;
localparam [1:0] ibex_pkg_PMP_ACC_WRITE = 2'b01;
localparam [1:0] ibex_pkg_PMP_MODE_NA4 = 2'b10;
localparam [1:0] ibex_pkg_PMP_MODE_OFF = 2'b00;
localparam [1:0] ibex_pkg_PRIV_LVL_M = 2'b11;
generate
genvar c;
for (c = 0; c < PMPNumChan; c = c + 1) begin : g_access_check
for (r = 0; r < PMPNumRegions; r = r + 1) begin : g_regions
assign region_match_eq[(c * PMPNumRegions) + r] = (pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] & region_addr_mask[r]) == (region_start_addr[r][33:PMPGranularity + 2] & region_addr_mask[r]);
assign region_match_gt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] > region_start_addr[r][33:PMPGranularity + 2];
assign region_match_lt[(c * PMPNumRegions) + r] = pmp_req_addr_i[((0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)] < csr_pmp_addr_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 34) + (33 >= (PMPGranularity + 2) ? 33 : (33 + (33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)) - 1)-:(33 >= (PMPGranularity + 2) ? 34 - (PMPGranularity + 2) : PMPGranularity - 30)];
always @(*) begin
region_match_all[(c * PMPNumRegions) + r] = 1'b0;
case (csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 4-:2])
ibex_pkg_PMP_MODE_OFF: region_match_all[(c * PMPNumRegions) + r] = 1'b0;
ibex_pkg_PMP_MODE_NA4: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r];
ibex_pkg_PMP_MODE_NAPOT: region_match_all[(c * PMPNumRegions) + r] = region_match_eq[(c * PMPNumRegions) + r];
ibex_pkg_PMP_MODE_TOR: region_match_all[(c * PMPNumRegions) + r] = (region_match_eq[(c * PMPNumRegions) + r] | region_match_gt[(c * PMPNumRegions) + r]) & region_match_lt[(c * PMPNumRegions) + r];
default: region_match_all[(c * PMPNumRegions) + r] = 1'b0;
endcase
end
assign region_perm_check[(c * PMPNumRegions) + r] = (((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_EXEC) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 2]) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_WRITE) & csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 1])) | ((pmp_req_type_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PMP_ACC_READ) & csr_pmp_cfg_i[(0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6]);
end
always @(*) begin
access_fault[c] = priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] != ibex_pkg_PRIV_LVL_M;
begin : sv2v_autoblock_1
reg signed [31:0] r;
for (r = PMPNumRegions - 1; r >= 0; r = r - 1)
if (region_match_all[(c * PMPNumRegions) + r])
access_fault[c] = (priv_mode_i[(0 >= (PMPNumChan - 1) ? c : (PMPNumChan - 1) - c) * 2+:2] == ibex_pkg_PRIV_LVL_M ? csr_pmp_cfg_i[((0 >= (PMPNumRegions - 1) ? r : (PMPNumRegions - 1) - r) * 6) + 5] & ~region_perm_check[(c * PMPNumRegions) + r] : ~region_perm_check[(c * PMPNumRegions) + r]);
end
end
assign pmp_req_err_o[c] = access_fault[c];
end
endgenerate
endmodule |
module prim_generic_ram_1p (
clk_i,
req_i,
write_i,
addr_i,
wdata_i,
wmask_i,
rdata_o
);
parameter signed [31:0] Width = 32;
parameter signed [31:0] Depth = 128;
parameter signed [31:0] DataBitsPerMask = 1;
parameter _sv2v_width_MemInitFile = 1;
parameter [_sv2v_width_MemInitFile - 1:0] MemInitFile = "";
localparam signed [31:0] Aw = $clog2(Depth);
input wire clk_i;
input wire req_i;
input wire write_i;
input wire [Aw - 1:0] addr_i;
input wire [Width - 1:0] wdata_i;
input wire [Width - 1:0] wmask_i;
output reg [Width - 1:0] rdata_o;
localparam signed [31:0] MaskWidth = Width / DataBitsPerMask;
reg [Width - 1:0] mem [0:Depth - 1];
wire [MaskWidth - 1:0] wmask;
generate
genvar k;
for (k = 0; k < MaskWidth; k = k + 1) begin : gen_wmask
assign wmask[k] = &wmask_i[k * DataBitsPerMask+:DataBitsPerMask];
end
endgenerate
always @(posedge clk_i)
if (req_i)
if (write_i) begin : sv2v_autoblock_2
reg signed [31:0] i;
for (i = 0; i < MaskWidth; i = i + 1)
if (wmask[i])
mem[addr_i][i * DataBitsPerMask+:DataBitsPerMask] <= wdata_i[i * DataBitsPerMask+:DataBitsPerMask];
end
else
rdata_o <= mem[addr_i];
initial if (MemInitFile != "") begin : gen_meminit
$display("Initializing memory %m from file '%s'.", MemInitFile);
$readmemh(MemInitFile, mem);
end
endmodule |
module ibex_decoder (
clk_i,
rst_ni,
illegal_insn_o,
ebrk_insn_o,
mret_insn_o,
dret_insn_o,
ecall_insn_o,
wfi_insn_o,
jump_set_o,
branch_taken_i,
icache_inval_o,
instr_first_cycle_i,
instr_rdata_i,
instr_rdata_alu_i,
illegal_c_insn_i,
imm_a_mux_sel_o,
imm_b_mux_sel_o,
bt_a_mux_sel_o,
bt_b_mux_sel_o,
imm_i_type_o,
imm_s_type_o,
imm_b_type_o,
imm_u_type_o,
imm_j_type_o,
zimm_rs1_type_o,
rf_wdata_sel_o,
rf_we_o,
rf_raddr_a_o,
rf_raddr_b_o,
rf_waddr_o,
rf_ren_a_o,
rf_ren_b_o,
alu_operator_o,
alu_op_a_mux_sel_o,
alu_op_b_mux_sel_o,
alu_multicycle_o,
mult_en_o,
div_en_o,
mult_sel_o,
div_sel_o,
multdiv_operator_o,
multdiv_signed_mode_o,
csr_access_o,
csr_op_o,
data_req_o,
data_we_o,
data_type_o,
data_sign_extension_o,
jump_in_dec_o,
branch_in_dec_o
);
parameter [0:0] RV32E = 0;
localparam integer ibex_pkg_RV32MFast = 2;
parameter integer RV32M = ibex_pkg_RV32MFast;
localparam integer ibex_pkg_RV32BNone = 0;
parameter integer RV32B = ibex_pkg_RV32BNone;
parameter [0:0] BranchTargetALU = 0;
input wire clk_i;
input wire rst_ni;
output wire illegal_insn_o;
output reg ebrk_insn_o;
output reg mret_insn_o;
output reg dret_insn_o;
output reg ecall_insn_o;
output reg wfi_insn_o;
output reg jump_set_o;
input wire branch_taken_i;
output reg icache_inval_o;
input wire instr_first_cycle_i;
input wire [31:0] instr_rdata_i;
input wire [31:0] instr_rdata_alu_i;
input wire illegal_c_insn_i;
output reg imm_a_mux_sel_o;
output reg [2:0] imm_b_mux_sel_o;
output reg [1:0] bt_a_mux_sel_o;
output reg [2:0] bt_b_mux_sel_o;
output wire [31:0] imm_i_type_o;
output wire [31:0] imm_s_type_o;
output wire [31:0] imm_b_type_o;
output wire [31:0] imm_u_type_o;
output wire [31:0] imm_j_type_o;
output wire [31:0] zimm_rs1_type_o;
output reg rf_wdata_sel_o;
output wire rf_we_o;
output wire [4:0] rf_raddr_a_o;
output wire [4:0] rf_raddr_b_o;
output wire [4:0] rf_waddr_o;
output reg rf_ren_a_o;
output reg rf_ren_b_o;
output reg [5:0] alu_operator_o;
output reg [1:0] alu_op_a_mux_sel_o;
output reg alu_op_b_mux_sel_o;
output reg alu_multicycle_o;
output wire mult_en_o;
output wire div_en_o;
output reg mult_sel_o;
output reg div_sel_o;
output reg [1:0] multdiv_operator_o;
output reg [1:0] multdiv_signed_mode_o;
output reg csr_access_o;
output reg [1:0] csr_op_o;
output reg data_req_o;
output reg data_we_o;
output reg [1:0] data_type_o;
output reg data_sign_extension_o;
output reg jump_in_dec_o;
output reg branch_in_dec_o;
reg illegal_insn;
wire illegal_reg_rv32e;
reg csr_illegal;
reg rf_we;
wire [31:0] instr;
wire [31:0] instr_alu;
wire [9:0] unused_instr_alu;
wire [4:0] instr_rs1;
wire [4:0] instr_rs2;
wire [4:0] instr_rs3;
wire [4:0] instr_rd;
reg use_rs3_d;
reg use_rs3_q;
reg [1:0] csr_op;
reg [6:0] opcode;
reg [6:0] opcode_alu;
assign instr = instr_rdata_i;
assign instr_alu = instr_rdata_alu_i;
assign imm_i_type_o = {{20 {instr[31]}}, instr[31:20]};
assign imm_s_type_o = {{20 {instr[31]}}, instr[31:25], instr[11:7]};
assign imm_b_type_o = {{19 {instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
assign imm_u_type_o = {instr[31:12], 12'b000000000000};
assign imm_j_type_o = {{12 {instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};
assign zimm_rs1_type_o = {27'b000000000000000000000000000, instr_rs1};
generate
if (RV32B != ibex_pkg_RV32BNone) begin : gen_rs3_flop
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
use_rs3_q <= 1'b0;
else
use_rs3_q <= use_rs3_d;
end
else begin : gen_no_rs3_flop
wire [1:1] sv2v_tmp_66FD5;
assign sv2v_tmp_66FD5 = use_rs3_d;
always @(*) use_rs3_q = sv2v_tmp_66FD5;
end
endgenerate
assign instr_rs1 = instr[19:15];
assign instr_rs2 = instr[24:20];
assign instr_rs3 = instr[31:27];
assign rf_raddr_a_o = (use_rs3_q & ~instr_first_cycle_i ? instr_rs3 : instr_rs1);
assign rf_raddr_b_o = instr_rs2;
assign instr_rd = instr[11:7];
assign rf_waddr_o = instr_rd;
localparam [1:0] ibex_pkg_OP_A_REG_A = 0;
localparam [0:0] ibex_pkg_OP_B_REG_B = 0;
generate
if (RV32E) begin : gen_rv32e_reg_check_active
assign illegal_reg_rv32e = ((rf_raddr_a_o[4] & (alu_op_a_mux_sel_o == ibex_pkg_OP_A_REG_A)) | (rf_raddr_b_o[4] & (alu_op_b_mux_sel_o == ibex_pkg_OP_B_REG_B))) | (rf_waddr_o[4] & rf_we);
end
else begin : gen_rv32e_reg_check_inactive
assign illegal_reg_rv32e = 1'b0;
end
endgenerate
localparam [1:0] ibex_pkg_CSR_OP_CLEAR = 3;
localparam [1:0] ibex_pkg_CSR_OP_READ = 0;
localparam [1:0] ibex_pkg_CSR_OP_SET = 2;
always @(*) begin : csr_operand_check
csr_op_o = csr_op;
if (((csr_op == ibex_pkg_CSR_OP_SET) || (csr_op == ibex_pkg_CSR_OP_CLEAR)) && (instr_rs1 == {5 {1'sb0}}))
csr_op_o = ibex_pkg_CSR_OP_READ;
end
localparam [1:0] ibex_pkg_CSR_OP_WRITE = 1;
localparam [1:0] ibex_pkg_MD_OP_DIV = 2;
localparam [1:0] ibex_pkg_MD_OP_MULH = 1;
localparam [1:0] ibex_pkg_MD_OP_MULL = 0;
localparam [1:0] ibex_pkg_MD_OP_REM = 3;
localparam [6:0] ibex_pkg_OPCODE_AUIPC = 7'h17;
localparam [6:0] ibex_pkg_OPCODE_BRANCH = 7'h63;
localparam [6:0] ibex_pkg_OPCODE_JAL = 7'h6f;
localparam [6:0] ibex_pkg_OPCODE_JALR = 7'h67;
localparam [6:0] ibex_pkg_OPCODE_LOAD = 7'h03;
localparam [6:0] ibex_pkg_OPCODE_LUI = 7'h37;
localparam [6:0] ibex_pkg_OPCODE_MISC_MEM = 7'h0f;
localparam [6:0] ibex_pkg_OPCODE_OP = 7'h33;
localparam [6:0] ibex_pkg_OPCODE_OP_IMM = 7'h13;
localparam [6:0] ibex_pkg_OPCODE_STORE = 7'h23;
localparam [6:0] ibex_pkg_OPCODE_SYSTEM = 7'h73;
localparam [0:0] ibex_pkg_RF_WD_CSR = 1;
localparam [0:0] ibex_pkg_RF_WD_EX = 0;
localparam integer ibex_pkg_RV32BBalanced = 1;
localparam integer ibex_pkg_RV32BFull = 2;
localparam integer ibex_pkg_RV32MNone = 0;
always @(*) begin
jump_in_dec_o = 1'b0;
jump_set_o = 1'b0;
branch_in_dec_o = 1'b0;
icache_inval_o = 1'b0;
multdiv_operator_o = ibex_pkg_MD_OP_MULL;
multdiv_signed_mode_o = 2'b00;
rf_wdata_sel_o = ibex_pkg_RF_WD_EX;
rf_we = 1'b0;
rf_ren_a_o = 1'b0;
rf_ren_b_o = 1'b0;
csr_access_o = 1'b0;
csr_illegal = 1'b0;
csr_op = ibex_pkg_CSR_OP_READ;
data_we_o = 1'b0;
data_type_o = 2'b00;
data_sign_extension_o = 1'b0;
data_req_o = 1'b0;
illegal_insn = 1'b0;
ebrk_insn_o = 1'b0;
mret_insn_o = 1'b0;
dret_insn_o = 1'b0;
ecall_insn_o = 1'b0;
wfi_insn_o = 1'b0;
opcode = instr[6:0];
case (opcode)
ibex_pkg_OPCODE_JAL: begin
jump_in_dec_o = 1'b1;
if (instr_first_cycle_i) begin
rf_we = BranchTargetALU;
jump_set_o = 1'b1;
end
else
rf_we = 1'b1;
end
ibex_pkg_OPCODE_JALR: begin
jump_in_dec_o = 1'b1;
if (instr_first_cycle_i) begin
rf_we = BranchTargetALU;
jump_set_o = 1'b1;
end
else
rf_we = 1'b1;
if (instr[14:12] != 3'b000)
illegal_insn = 1'b1;
rf_ren_a_o = 1'b1;
end
ibex_pkg_OPCODE_BRANCH: begin
branch_in_dec_o = 1'b1;
case (instr[14:12])
3'b000, 3'b001, 3'b100, 3'b101, 3'b110, 3'b111: illegal_insn = 1'b0;
default: illegal_insn = 1'b1;
endcase
rf_ren_a_o = 1'b1;
rf_ren_b_o = 1'b1;
end
ibex_pkg_OPCODE_STORE: begin
rf_ren_a_o = 1'b1;
rf_ren_b_o = 1'b1;
data_req_o = 1'b1;
data_we_o = 1'b1;
if (instr[14])
illegal_insn = 1'b1;
case (instr[13:12])
2'b00: data_type_o = 2'b10;
2'b01: data_type_o = 2'b01;
2'b10: data_type_o = 2'b00;
default: illegal_insn = 1'b1;
endcase
end
ibex_pkg_OPCODE_LOAD: begin
rf_ren_a_o = 1'b1;
data_req_o = 1'b1;
data_type_o = 2'b00;
data_sign_extension_o = ~instr[14];
case (instr[13:12])
2'b00: data_type_o = 2'b10;
2'b01: data_type_o = 2'b01;
2'b10: begin
data_type_o = 2'b00;
if (instr[14])
illegal_insn = 1'b1;
end
default: illegal_insn = 1'b1;
endcase
end
ibex_pkg_OPCODE_LUI: rf_we = 1'b1;
ibex_pkg_OPCODE_AUIPC: rf_we = 1'b1;
ibex_pkg_OPCODE_OP_IMM: begin
rf_ren_a_o = 1'b1;
rf_we = 1'b1;
case (instr[14:12])
3'b000, 3'b010, 3'b011, 3'b100, 3'b110, 3'b111: illegal_insn = 1'b0;
3'b001:
case (instr[31:27])
5'b00000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1);
5'b00100, 5'b01001, 5'b00101, 5'b01101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
5'b00001:
if (instr[26] == 1'b0)
illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1);
else
illegal_insn = 1'b1;
5'b01100:
case (instr[26:20])
7'b0000000, 7'b0000001, 7'b0000010, 7'b0000100, 7'b0000101: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
7'b0010000, 7'b0010001, 7'b0010010, 7'b0011000, 7'b0011001, 7'b0011010: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1);
default: illegal_insn = 1'b1;
endcase
default: illegal_insn = 1'b1;
endcase
3'b101:
if (instr[26])
illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
else
case (instr[31:27])
5'b00000, 5'b01000: illegal_insn = (instr[26:25] == 2'b00 ? 1'b0 : 1'b1);
5'b00100, 5'b01100, 5'b01001: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
5'b01101:
if (RV32B == ibex_pkg_RV32BFull)
illegal_insn = 1'b0;
else
case (instr[24:20])
5'b11111, 5'b11000: illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1);
default: illegal_insn = 1'b1;
endcase
5'b00101:
if (RV32B == ibex_pkg_RV32BFull)
illegal_insn = 1'b0;
else if (instr[24:20] == 5'b00111)
illegal_insn = (RV32B == ibex_pkg_RV32BBalanced ? 1'b0 : 1'b1);
else
illegal_insn = 1'b1;
5'b00001:
if (instr[26] == 1'b0)
illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1);
else
illegal_insn = 1'b1;
default: illegal_insn = 1'b1;
endcase
default: illegal_insn = 1'b1;
endcase
end
ibex_pkg_OPCODE_OP: begin
rf_ren_a_o = 1'b1;
rf_ren_b_o = 1'b1;
rf_we = 1'b1;
if ({instr[26], instr[13:12]} == {1'b1, 2'b01})
illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
else
case ({instr[31:25], instr[14:12]})
{7'b0000000, 3'b000}, {7'b0100000, 3'b000}, {7'b0000000, 3'b010}, {7'b0000000, 3'b011}, {7'b0000000, 3'b100}, {7'b0000000, 3'b110}, {7'b0000000, 3'b111}, {7'b0000000, 3'b001}, {7'b0000000, 3'b101}, {7'b0100000, 3'b101}: illegal_insn = 1'b0;
{7'b0100000, 3'b111}, {7'b0100000, 3'b110}, {7'b0100000, 3'b100}, {7'b0010000, 3'b001}, {7'b0010000, 3'b101}, {7'b0110000, 3'b001}, {7'b0110000, 3'b101}, {7'b0000101, 3'b100}, {7'b0000101, 3'b101}, {7'b0000101, 3'b110}, {7'b0000101, 3'b111}, {7'b0000100, 3'b100}, {7'b0100100, 3'b100}, {7'b0000100, 3'b111}, {7'b0100100, 3'b001}, {7'b0010100, 3'b001}, {7'b0110100, 3'b001}, {7'b0100100, 3'b101}, {7'b0100100, 3'b111}: illegal_insn = (RV32B != ibex_pkg_RV32BNone ? 1'b0 : 1'b1);
{7'b0100100, 3'b110}, {7'b0000100, 3'b110}, {7'b0110100, 3'b101}, {7'b0010100, 3'b101}, {7'b0000100, 3'b001}, {7'b0000100, 3'b101}, {7'b0000101, 3'b001}, {7'b0000101, 3'b010}, {7'b0000101, 3'b011}: illegal_insn = (RV32B == ibex_pkg_RV32BFull ? 1'b0 : 1'b1);
{7'b0000001, 3'b000}: begin
multdiv_operator_o = ibex_pkg_MD_OP_MULL;
multdiv_signed_mode_o = 2'b00;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b001}: begin
multdiv_operator_o = ibex_pkg_MD_OP_MULH;
multdiv_signed_mode_o = 2'b11;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b010}: begin
multdiv_operator_o = ibex_pkg_MD_OP_MULH;
multdiv_signed_mode_o = 2'b01;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b011}: begin
multdiv_operator_o = ibex_pkg_MD_OP_MULH;
multdiv_signed_mode_o = 2'b00;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b100}: begin
multdiv_operator_o = ibex_pkg_MD_OP_DIV;
multdiv_signed_mode_o = 2'b11;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b101}: begin
multdiv_operator_o = ibex_pkg_MD_OP_DIV;
multdiv_signed_mode_o = 2'b00;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b110}: begin
multdiv_operator_o = ibex_pkg_MD_OP_REM;
multdiv_signed_mode_o = 2'b11;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
{7'b0000001, 3'b111}: begin
multdiv_operator_o = ibex_pkg_MD_OP_REM;
multdiv_signed_mode_o = 2'b00;
illegal_insn = (RV32M == ibex_pkg_RV32MNone ? 1'b1 : 1'b0);
end
default: illegal_insn = 1'b1;
endcase
end
ibex_pkg_OPCODE_MISC_MEM:
case (instr[14:12])
3'b000: rf_we = 1'b0;
3'b001: begin
jump_in_dec_o = 1'b1;
rf_we = 1'b0;
if (instr_first_cycle_i) begin
jump_set_o = 1'b1;
icache_inval_o = 1'b1;
end
end
default: illegal_insn = 1'b1;
endcase
ibex_pkg_OPCODE_SYSTEM:
if (instr[14:12] == 3'b000) begin
case (instr[31:20])
12'h000: ecall_insn_o = 1'b1;
12'h001: ebrk_insn_o = 1'b1;
12'h302: mret_insn_o = 1'b1;
12'h7b2: dret_insn_o = 1'b1;
12'h105: wfi_insn_o = 1'b1;
default: illegal_insn = 1'b1;
endcase
if ((instr_rs1 != 5'b00000) || (instr_rd != 5'b00000))
illegal_insn = 1'b1;
end
else begin
csr_access_o = 1'b1;
rf_wdata_sel_o = ibex_pkg_RF_WD_CSR;
rf_we = 1'b1;
if (~instr[14])
rf_ren_a_o = 1'b1;
case (instr[13:12])
2'b01: csr_op = ibex_pkg_CSR_OP_WRITE;
2'b10: csr_op = ibex_pkg_CSR_OP_SET;
2'b11: csr_op = ibex_pkg_CSR_OP_CLEAR;
default: csr_illegal = 1'b1;
endcase
illegal_insn = csr_illegal;
end
default: illegal_insn = 1'b1;
endcase
if (illegal_c_insn_i)
illegal_insn = 1'b1;
if (illegal_insn) begin
rf_we = 1'b0;
data_req_o = 1'b0;
data_we_o = 1'b0;
jump_in_dec_o = 1'b0;
jump_set_o = 1'b0;
branch_in_dec_o = 1'b0;
csr_access_o = 1'b0;
end
end
localparam [5:0] ibex_pkg_ALU_ADD = 0;
localparam [5:0] ibex_pkg_ALU_AND = 4;
localparam [5:0] ibex_pkg_ALU_ANDN = 7;
localparam [5:0] ibex_pkg_ALU_BDEP = 48;
localparam [5:0] ibex_pkg_ALU_BEXT = 47;
localparam [5:0] ibex_pkg_ALU_BFP = 49;
localparam [5:0] ibex_pkg_ALU_CLMUL = 50;
localparam [5:0] ibex_pkg_ALU_CLMULH = 52;
localparam [5:0] ibex_pkg_ALU_CLMULR = 51;
localparam [5:0] ibex_pkg_ALU_CLZ = 34;
localparam [5:0] ibex_pkg_ALU_CMIX = 40;
localparam [5:0] ibex_pkg_ALU_CMOV = 39;
localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54;
localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56;
localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58;
localparam [5:0] ibex_pkg_ALU_CRC32_B = 53;
localparam [5:0] ibex_pkg_ALU_CRC32_H = 55;
localparam [5:0] ibex_pkg_ALU_CRC32_W = 57;
localparam [5:0] ibex_pkg_ALU_CTZ = 35;
localparam [5:0] ibex_pkg_ALU_EQ = 23;
localparam [5:0] ibex_pkg_ALU_FSL = 41;
localparam [5:0] ibex_pkg_ALU_FSR = 42;
localparam [5:0] ibex_pkg_ALU_GE = 21;
localparam [5:0] ibex_pkg_ALU_GEU = 22;
localparam [5:0] ibex_pkg_ALU_GORC = 16;
localparam [5:0] ibex_pkg_ALU_GREV = 15;
localparam [5:0] ibex_pkg_ALU_LT = 19;
localparam [5:0] ibex_pkg_ALU_LTU = 20;
localparam [5:0] ibex_pkg_ALU_MAX = 27;
localparam [5:0] ibex_pkg_ALU_MAXU = 28;
localparam [5:0] ibex_pkg_ALU_MIN = 25;
localparam [5:0] ibex_pkg_ALU_MINU = 26;
localparam [5:0] ibex_pkg_ALU_NE = 24;
localparam [5:0] ibex_pkg_ALU_OR = 3;
localparam [5:0] ibex_pkg_ALU_ORN = 6;
localparam [5:0] ibex_pkg_ALU_PACK = 29;
localparam [5:0] ibex_pkg_ALU_PACKH = 31;
localparam [5:0] ibex_pkg_ALU_PACKU = 30;
localparam [5:0] ibex_pkg_ALU_PCNT = 36;
localparam [5:0] ibex_pkg_ALU_ROL = 14;
localparam [5:0] ibex_pkg_ALU_ROR = 13;
localparam [5:0] ibex_pkg_ALU_SBCLR = 44;
localparam [5:0] ibex_pkg_ALU_SBEXT = 46;
localparam [5:0] ibex_pkg_ALU_SBINV = 45;
localparam [5:0] ibex_pkg_ALU_SBSET = 43;
localparam [5:0] ibex_pkg_ALU_SEXTB = 32;
localparam [5:0] ibex_pkg_ALU_SEXTH = 33;
localparam [5:0] ibex_pkg_ALU_SHFL = 17;
localparam [5:0] ibex_pkg_ALU_SLL = 10;
localparam [5:0] ibex_pkg_ALU_SLO = 12;
localparam [5:0] ibex_pkg_ALU_SLT = 37;
localparam [5:0] ibex_pkg_ALU_SLTU = 38;
localparam [5:0] ibex_pkg_ALU_SRA = 8;
localparam [5:0] ibex_pkg_ALU_SRL = 9;
localparam [5:0] ibex_pkg_ALU_SRO = 11;
localparam [5:0] ibex_pkg_ALU_SUB = 1;
localparam [5:0] ibex_pkg_ALU_UNSHFL = 18;
localparam [5:0] ibex_pkg_ALU_XNOR = 5;
localparam [5:0] ibex_pkg_ALU_XOR = 2;
localparam [0:0] ibex_pkg_IMM_A_Z = 0;
localparam [0:0] ibex_pkg_IMM_A_ZERO = 1;
localparam [2:0] ibex_pkg_IMM_B_B = 2;
localparam [2:0] ibex_pkg_IMM_B_I = 0;
localparam [2:0] ibex_pkg_IMM_B_INCR_PC = 5;
localparam [2:0] ibex_pkg_IMM_B_J = 4;
localparam [2:0] ibex_pkg_IMM_B_S = 1;
localparam [2:0] ibex_pkg_IMM_B_U = 3;
localparam [1:0] ibex_pkg_OP_A_CURRPC = 2;
localparam [1:0] ibex_pkg_OP_A_IMM = 3;
localparam [0:0] ibex_pkg_OP_B_IMM = 1;
always @(*) begin
alu_operator_o = ibex_pkg_ALU_SLTU;
alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO;
imm_b_mux_sel_o = ibex_pkg_IMM_B_I;
bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
bt_b_mux_sel_o = ibex_pkg_IMM_B_I;
opcode_alu = instr_alu[6:0];
use_rs3_d = 1'b0;
alu_multicycle_o = 1'b0;
mult_sel_o = 1'b0;
div_sel_o = 1'b0;
case (opcode_alu)
ibex_pkg_OPCODE_JAL: begin
if (BranchTargetALU) begin
bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
bt_b_mux_sel_o = ibex_pkg_IMM_B_J;
end
if (instr_first_cycle_i && !BranchTargetALU) begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_J;
alu_operator_o = ibex_pkg_ALU_ADD;
end
else begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC;
alu_operator_o = ibex_pkg_ALU_ADD;
end
end
ibex_pkg_OPCODE_JALR: begin
if (BranchTargetALU) begin
bt_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
bt_b_mux_sel_o = ibex_pkg_IMM_B_I;
end
if (instr_first_cycle_i && !BranchTargetALU) begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_I;
alu_operator_o = ibex_pkg_ALU_ADD;
end
else begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC;
alu_operator_o = ibex_pkg_ALU_ADD;
end
end
ibex_pkg_OPCODE_BRANCH: begin
case (instr_alu[14:12])
3'b000: alu_operator_o = ibex_pkg_ALU_EQ;
3'b001: alu_operator_o = ibex_pkg_ALU_NE;
3'b100: alu_operator_o = ibex_pkg_ALU_LT;
3'b101: alu_operator_o = ibex_pkg_ALU_GE;
3'b110: alu_operator_o = ibex_pkg_ALU_LTU;
3'b111: alu_operator_o = ibex_pkg_ALU_GEU;
default:
;
endcase
if (BranchTargetALU) begin
bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
bt_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC);
end
if (instr_first_cycle_i) begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B;
end
else begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = (branch_taken_i ? ibex_pkg_IMM_B_B : ibex_pkg_IMM_B_INCR_PC);
alu_operator_o = ibex_pkg_ALU_ADD;
end
end
ibex_pkg_OPCODE_STORE: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B;
alu_operator_o = ibex_pkg_ALU_ADD;
if (!instr_alu[14]) begin
imm_b_mux_sel_o = ibex_pkg_IMM_B_S;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
end
end
ibex_pkg_OPCODE_LOAD: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_operator_o = ibex_pkg_ALU_ADD;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_I;
end
ibex_pkg_OPCODE_LUI: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_a_mux_sel_o = ibex_pkg_IMM_A_ZERO;
imm_b_mux_sel_o = ibex_pkg_IMM_B_U;
alu_operator_o = ibex_pkg_ALU_ADD;
end
ibex_pkg_OPCODE_AUIPC: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_U;
alu_operator_o = ibex_pkg_ALU_ADD;
end
ibex_pkg_OPCODE_OP_IMM: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_I;
case (instr_alu[14:12])
3'b000: alu_operator_o = ibex_pkg_ALU_ADD;
3'b010: alu_operator_o = ibex_pkg_ALU_SLT;
3'b011: alu_operator_o = ibex_pkg_ALU_SLTU;
3'b100: alu_operator_o = ibex_pkg_ALU_XOR;
3'b110: alu_operator_o = ibex_pkg_ALU_OR;
3'b111: alu_operator_o = ibex_pkg_ALU_AND;
3'b001:
if (RV32B != ibex_pkg_RV32BNone)
case (instr_alu[31:27])
5'b00000: alu_operator_o = ibex_pkg_ALU_SLL;
5'b00100: alu_operator_o = ibex_pkg_ALU_SLO;
5'b01001: alu_operator_o = ibex_pkg_ALU_SBCLR;
5'b00101: alu_operator_o = ibex_pkg_ALU_SBSET;
5'b01101: alu_operator_o = ibex_pkg_ALU_SBINV;
5'b00001:
if (instr_alu[26] == 0)
alu_operator_o = ibex_pkg_ALU_SHFL;
5'b01100:
case (instr_alu[26:20])
7'b0000000: alu_operator_o = ibex_pkg_ALU_CLZ;
7'b0000001: alu_operator_o = ibex_pkg_ALU_CTZ;
7'b0000010: alu_operator_o = ibex_pkg_ALU_PCNT;
7'b0000100: alu_operator_o = ibex_pkg_ALU_SEXTB;
7'b0000101: alu_operator_o = ibex_pkg_ALU_SEXTH;
7'b0010000:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32_B;
alu_multicycle_o = 1'b1;
end
7'b0010001:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32_H;
alu_multicycle_o = 1'b1;
end
7'b0010010:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32_W;
alu_multicycle_o = 1'b1;
end
7'b0011000:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32C_B;
alu_multicycle_o = 1'b1;
end
7'b0011001:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32C_H;
alu_multicycle_o = 1'b1;
end
7'b0011010:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_CRC32C_W;
alu_multicycle_o = 1'b1;
end
default:
;
endcase
default:
;
endcase
else
alu_operator_o = ibex_pkg_ALU_SLL;
3'b101:
if (RV32B != ibex_pkg_RV32BNone) begin
if (instr_alu[26] == 1'b1) begin
alu_operator_o = ibex_pkg_ALU_FSR;
alu_multicycle_o = 1'b1;
if (instr_first_cycle_i)
use_rs3_d = 1'b1;
else
use_rs3_d = 1'b0;
end
else
case (instr_alu[31:27])
5'b00000: alu_operator_o = ibex_pkg_ALU_SRL;
5'b01000: alu_operator_o = ibex_pkg_ALU_SRA;
5'b00100: alu_operator_o = ibex_pkg_ALU_SRO;
5'b01001: alu_operator_o = ibex_pkg_ALU_SBEXT;
5'b01100: begin
alu_operator_o = ibex_pkg_ALU_ROR;
alu_multicycle_o = 1'b1;
end
5'b01101: alu_operator_o = ibex_pkg_ALU_GREV;
5'b00101: alu_operator_o = ibex_pkg_ALU_GORC;
5'b00001:
if (RV32B == ibex_pkg_RV32BFull)
if (instr_alu[26] == 1'b0)
alu_operator_o = ibex_pkg_ALU_UNSHFL;
default:
;
endcase
end
else if (instr_alu[31:27] == 5'b00000)
alu_operator_o = ibex_pkg_ALU_SRL;
else if (instr_alu[31:27] == 5'b01000)
alu_operator_o = ibex_pkg_ALU_SRA;
default:
;
endcase
end
ibex_pkg_OPCODE_OP: begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_REG_B;
if (instr_alu[26]) begin
if (RV32B != ibex_pkg_RV32BNone)
case ({instr_alu[26:25], instr_alu[14:12]})
{2'b11, 3'b001}: begin
alu_operator_o = ibex_pkg_ALU_CMIX;
alu_multicycle_o = 1'b1;
if (instr_first_cycle_i)
use_rs3_d = 1'b1;
else
use_rs3_d = 1'b0;
end
{2'b11, 3'b101}: begin
alu_operator_o = ibex_pkg_ALU_CMOV;
alu_multicycle_o = 1'b1;
if (instr_first_cycle_i)
use_rs3_d = 1'b1;
else
use_rs3_d = 1'b0;
end
{2'b10, 3'b001}: begin
alu_operator_o = ibex_pkg_ALU_FSL;
alu_multicycle_o = 1'b1;
if (instr_first_cycle_i)
use_rs3_d = 1'b1;
else
use_rs3_d = 1'b0;
end
{2'b10, 3'b101}: begin
alu_operator_o = ibex_pkg_ALU_FSR;
alu_multicycle_o = 1'b1;
if (instr_first_cycle_i)
use_rs3_d = 1'b1;
else
use_rs3_d = 1'b0;
end
default:
;
endcase
end
else
case ({instr_alu[31:25], instr_alu[14:12]})
{7'b0000000, 3'b000}: alu_operator_o = ibex_pkg_ALU_ADD;
{7'b0100000, 3'b000}: alu_operator_o = ibex_pkg_ALU_SUB;
{7'b0000000, 3'b010}: alu_operator_o = ibex_pkg_ALU_SLT;
{7'b0000000, 3'b011}: alu_operator_o = ibex_pkg_ALU_SLTU;
{7'b0000000, 3'b100}: alu_operator_o = ibex_pkg_ALU_XOR;
{7'b0000000, 3'b110}: alu_operator_o = ibex_pkg_ALU_OR;
{7'b0000000, 3'b111}: alu_operator_o = ibex_pkg_ALU_AND;
{7'b0000000, 3'b001}: alu_operator_o = ibex_pkg_ALU_SLL;
{7'b0000000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRL;
{7'b0100000, 3'b101}: alu_operator_o = ibex_pkg_ALU_SRA;
{7'b0010000, 3'b001}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SLO;
{7'b0010000, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SRO;
{7'b0110000, 3'b001}:
if (RV32B != ibex_pkg_RV32BNone) begin
alu_operator_o = ibex_pkg_ALU_ROL;
alu_multicycle_o = 1'b1;
end
{7'b0110000, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone) begin
alu_operator_o = ibex_pkg_ALU_ROR;
alu_multicycle_o = 1'b1;
end
{7'b0000101, 3'b100}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_MIN;
{7'b0000101, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_MAX;
{7'b0000101, 3'b110}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_MINU;
{7'b0000101, 3'b111}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_MAXU;
{7'b0000100, 3'b100}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_PACK;
{7'b0100100, 3'b100}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_PACKU;
{7'b0000100, 3'b111}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_PACKH;
{7'b0100000, 3'b100}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_XNOR;
{7'b0100000, 3'b110}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_ORN;
{7'b0100000, 3'b111}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_ANDN;
{7'b0100100, 3'b001}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SBCLR;
{7'b0010100, 3'b001}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SBSET;
{7'b0110100, 3'b001}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SBINV;
{7'b0100100, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_SBEXT;
{7'b0100100, 3'b111}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_BFP;
{7'b0110100, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_GREV;
{7'b0010100, 3'b101}:
if (RV32B != ibex_pkg_RV32BNone)
alu_operator_o = ibex_pkg_ALU_GORC;
{7'b0000100, 3'b001}:
if (RV32B == ibex_pkg_RV32BFull)
alu_operator_o = ibex_pkg_ALU_SHFL;
{7'b0000100, 3'b101}:
if (RV32B == ibex_pkg_RV32BFull)
alu_operator_o = ibex_pkg_ALU_UNSHFL;
{7'b0000101, 3'b001}:
if (RV32B == ibex_pkg_RV32BFull)
alu_operator_o = ibex_pkg_ALU_CLMUL;
{7'b0000101, 3'b010}:
if (RV32B == ibex_pkg_RV32BFull)
alu_operator_o = ibex_pkg_ALU_CLMULR;
{7'b0000101, 3'b011}:
if (RV32B == ibex_pkg_RV32BFull)
alu_operator_o = ibex_pkg_ALU_CLMULH;
{7'b0100100, 3'b110}:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_BDEP;
alu_multicycle_o = 1'b1;
end
{7'b0000100, 3'b110}:
if (RV32B == ibex_pkg_RV32BFull) begin
alu_operator_o = ibex_pkg_ALU_BEXT;
alu_multicycle_o = 1'b1;
end
{7'b0000001, 3'b000}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b001}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b010}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b011}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
mult_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b100}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b101}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b110}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
{7'b0000001, 3'b111}: begin
alu_operator_o = ibex_pkg_ALU_ADD;
div_sel_o = (RV32M == ibex_pkg_RV32MNone ? 1'b0 : 1'b1);
end
default:
;
endcase
end
ibex_pkg_OPCODE_MISC_MEM:
case (instr_alu[14:12])
3'b000: begin
alu_operator_o = ibex_pkg_ALU_ADD;
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
end
3'b001:
if (BranchTargetALU) begin
bt_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
bt_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC;
end
else begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_CURRPC;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_b_mux_sel_o = ibex_pkg_IMM_B_INCR_PC;
alu_operator_o = ibex_pkg_ALU_ADD;
end
default:
;
endcase
ibex_pkg_OPCODE_SYSTEM:
if (instr_alu[14:12] == 3'b000) begin
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
end
else begin
alu_op_b_mux_sel_o = ibex_pkg_OP_B_IMM;
imm_a_mux_sel_o = ibex_pkg_IMM_A_Z;
imm_b_mux_sel_o = ibex_pkg_IMM_B_I;
if (instr_alu[14])
alu_op_a_mux_sel_o = ibex_pkg_OP_A_IMM;
else
alu_op_a_mux_sel_o = ibex_pkg_OP_A_REG_A;
end
default:
;
endcase
end
assign mult_en_o = (illegal_insn ? 1'b0 : mult_sel_o);
assign div_en_o = (illegal_insn ? 1'b0 : div_sel_o);
assign illegal_insn_o = illegal_insn | illegal_reg_rv32e;
assign rf_we_o = rf_we & ~illegal_reg_rv32e;
assign unused_instr_alu = {instr_alu[19:15], instr_alu[11:7]};
endmodule |
module ibex_csr (
clk_i,
rst_ni,
wr_data_i,
wr_en_i,
rd_data_o,
rd_error_o
);
parameter [31:0] Width = 32;
parameter [0:0] ShadowCopy = 1'b0;
parameter [Width - 1:0] ResetValue = 1'sb0;
input wire clk_i;
input wire rst_ni;
input wire [Width - 1:0] wr_data_i;
input wire wr_en_i;
output wire [Width - 1:0] rd_data_o;
output wire rd_error_o;
reg [Width - 1:0] rdata_q;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
rdata_q <= ResetValue;
else if (wr_en_i)
rdata_q <= wr_data_i;
assign rd_data_o = rdata_q;
generate
if (ShadowCopy) begin : gen_shadow
reg [Width - 1:0] shadow_q;
always @(posedge clk_i or negedge rst_ni)
if (!rst_ni)
shadow_q <= ~ResetValue;
else if (wr_en_i)
shadow_q <= ~wr_data_i;
assign rd_error_o = rdata_q != ~shadow_q;
end
else begin : gen_no_shadow
assign rd_error_o = 1'b0;
end
endgenerate
endmodule |
module ibex_alu (
operator_i,
operand_a_i,
operand_b_i,
instr_first_cycle_i,
multdiv_operand_a_i,
multdiv_operand_b_i,
multdiv_sel_i,
imd_val_q_i,
imd_val_d_o,
imd_val_we_o,
adder_result_o,
adder_result_ext_o,
result_o,
comparison_result_o,
is_equal_result_o
);
localparam integer ibex_pkg_RV32BNone = 0;
parameter integer RV32B = ibex_pkg_RV32BNone;
input wire [5:0] operator_i;
input wire [31:0] operand_a_i;
input wire [31:0] operand_b_i;
input wire instr_first_cycle_i;
input wire [32:0] multdiv_operand_a_i;
input wire [32:0] multdiv_operand_b_i;
input wire multdiv_sel_i;
input wire [63:0] imd_val_q_i;
output reg [63:0] imd_val_d_o;
output reg [1:0] imd_val_we_o;
output wire [31:0] adder_result_o;
output wire [33:0] adder_result_ext_o;
output reg [31:0] result_o;
output wire comparison_result_o;
output wire is_equal_result_o;
wire [31:0] operand_a_rev;
wire [32:0] operand_b_neg;
generate
genvar k;
for (k = 0; k < 32; k = k + 1) begin : gen_rev_operand_a
assign operand_a_rev[k] = operand_a_i[31 - k];
end
endgenerate
reg adder_op_b_negate;
wire [32:0] adder_in_a;
reg [32:0] adder_in_b;
wire [31:0] adder_result;
localparam [5:0] ibex_pkg_ALU_EQ = 23;
localparam [5:0] ibex_pkg_ALU_GE = 21;
localparam [5:0] ibex_pkg_ALU_GEU = 22;
localparam [5:0] ibex_pkg_ALU_LT = 19;
localparam [5:0] ibex_pkg_ALU_LTU = 20;
localparam [5:0] ibex_pkg_ALU_MAX = 27;
localparam [5:0] ibex_pkg_ALU_MAXU = 28;
localparam [5:0] ibex_pkg_ALU_MIN = 25;
localparam [5:0] ibex_pkg_ALU_MINU = 26;
localparam [5:0] ibex_pkg_ALU_NE = 24;
localparam [5:0] ibex_pkg_ALU_SLT = 37;
localparam [5:0] ibex_pkg_ALU_SLTU = 38;
localparam [5:0] ibex_pkg_ALU_SUB = 1;
always @(*) begin
adder_op_b_negate = 1'b0;
case (operator_i)
ibex_pkg_ALU_SUB, ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: adder_op_b_negate = 1'b1;
default:
;
endcase
end
assign adder_in_a = (multdiv_sel_i ? multdiv_operand_a_i : {operand_a_i, 1'b1});
assign operand_b_neg = {operand_b_i, 1'b0} ^ {33 {1'b1}};
always @(*)
case (1'b1)
multdiv_sel_i: adder_in_b = multdiv_operand_b_i;
adder_op_b_negate: adder_in_b = operand_b_neg;
default: adder_in_b = {operand_b_i, 1'b0};
endcase
assign adder_result_ext_o = $unsigned(adder_in_a) + $unsigned(adder_in_b);
assign adder_result = adder_result_ext_o[32:1];
assign adder_result_o = adder_result;
wire is_equal;
reg is_greater_equal;
reg cmp_signed;
always @(*)
case (operator_i)
ibex_pkg_ALU_GE, ibex_pkg_ALU_LT, ibex_pkg_ALU_SLT, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX: cmp_signed = 1'b1;
default: cmp_signed = 1'b0;
endcase
assign is_equal = adder_result == 32'b00000000000000000000000000000000;
assign is_equal_result_o = is_equal;
always @(*)
if ((operand_a_i[31] ^ operand_b_i[31]) == 1'b0)
is_greater_equal = adder_result[31] == 1'b0;
else
is_greater_equal = operand_a_i[31] ^ cmp_signed;
reg cmp_result;
always @(*)
case (operator_i)
ibex_pkg_ALU_EQ: cmp_result = is_equal;
ibex_pkg_ALU_NE: cmp_result = ~is_equal;
ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MAXU: cmp_result = is_greater_equal;
ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_MIN, ibex_pkg_ALU_MINU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: cmp_result = ~is_greater_equal;
default: cmp_result = is_equal;
endcase
assign comparison_result_o = cmp_result;
reg shift_left;
wire shift_ones;
wire shift_arith;
wire shift_funnel;
wire shift_sbmode;
reg [5:0] shift_amt;
wire [5:0] shift_amt_compl;
reg [31:0] shift_operand;
reg [32:0] shift_result_ext;
reg unused_shift_result_ext;
reg [31:0] shift_result;
reg [31:0] shift_result_rev;
wire bfp_op;
wire [4:0] bfp_len;
wire [4:0] bfp_off;
wire [31:0] bfp_mask;
wire [31:0] bfp_mask_rev;
wire [31:0] bfp_result;
localparam [5:0] ibex_pkg_ALU_BFP = 49;
assign bfp_op = (RV32B != ibex_pkg_RV32BNone ? operator_i == ibex_pkg_ALU_BFP : 1'b0);
assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]};
assign bfp_off = operand_b_i[20:16];
assign bfp_mask = (RV32B != ibex_pkg_RV32BNone ? ~(32'hffffffff << bfp_len) : {32 {1'sb0}});
generate
genvar i;
for (i = 0; i < 32; i = i + 1) begin : gen_rev_bfp_mask
assign bfp_mask_rev[i] = bfp_mask[31 - i];
end
endgenerate
assign bfp_result = (RV32B != ibex_pkg_RV32BNone ? (~shift_result & operand_a_i) | ((operand_b_i & bfp_mask) << bfp_off) : {32 {1'sb0}});
wire [1:1] sv2v_tmp_86907;
assign sv2v_tmp_86907 = operand_b_i[5] & shift_funnel;
always @(*) shift_amt[5] = sv2v_tmp_86907;
assign shift_amt_compl = 32 - operand_b_i[4:0];
always @(*)
if (bfp_op)
shift_amt[4:0] = bfp_off;
else
shift_amt[4:0] = (instr_first_cycle_i ? (operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) : (operand_b_i[5] && shift_funnel ? operand_b_i[4:0] : shift_amt_compl[4:0]));
localparam [5:0] ibex_pkg_ALU_SBCLR = 44;
localparam [5:0] ibex_pkg_ALU_SBINV = 45;
localparam [5:0] ibex_pkg_ALU_SBSET = 43;
assign shift_sbmode = (RV32B != ibex_pkg_RV32BNone ? ((operator_i == ibex_pkg_ALU_SBSET) | (operator_i == ibex_pkg_ALU_SBCLR)) | (operator_i == ibex_pkg_ALU_SBINV) : 1'b0);
localparam [5:0] ibex_pkg_ALU_FSL = 41;
localparam [5:0] ibex_pkg_ALU_FSR = 42;
localparam [5:0] ibex_pkg_ALU_ROL = 14;
localparam [5:0] ibex_pkg_ALU_ROR = 13;
localparam [5:0] ibex_pkg_ALU_SLL = 10;
localparam [5:0] ibex_pkg_ALU_SLO = 12;
always @(*) begin
case (operator_i)
ibex_pkg_ALU_SLL: shift_left = 1'b1;
ibex_pkg_ALU_SLO, ibex_pkg_ALU_BFP: shift_left = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0);
ibex_pkg_ALU_ROL: shift_left = (RV32B != ibex_pkg_RV32BNone ? instr_first_cycle_i : 0);
ibex_pkg_ALU_ROR: shift_left = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 0);
ibex_pkg_ALU_FSL: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? ~instr_first_cycle_i : instr_first_cycle_i) : 1'b0);
ibex_pkg_ALU_FSR: shift_left = (RV32B != ibex_pkg_RV32BNone ? (shift_amt[5] ? instr_first_cycle_i : ~instr_first_cycle_i) : 1'b0);
default: shift_left = 1'b0;
endcase
if (shift_sbmode)
shift_left = 1'b1;
end
localparam [5:0] ibex_pkg_ALU_SRA = 8;
assign shift_arith = operator_i == ibex_pkg_ALU_SRA;
localparam [5:0] ibex_pkg_ALU_SRO = 11;
assign shift_ones = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_SLO) | (operator_i == ibex_pkg_ALU_SRO) : 1'b0);
assign shift_funnel = (RV32B != ibex_pkg_RV32BNone ? (operator_i == ibex_pkg_ALU_FSL) | (operator_i == ibex_pkg_ALU_FSR) : 1'b0);
always @(*) begin
if (RV32B == ibex_pkg_RV32BNone)
shift_operand = (shift_left ? operand_a_rev : operand_a_i);
else
case (1'b1)
bfp_op: shift_operand = bfp_mask_rev;
shift_sbmode: shift_operand = 32'h80000000;
default: shift_operand = (shift_left ? operand_a_rev : operand_a_i);
endcase
shift_result_ext = $unsigned($signed({shift_ones | (shift_arith & shift_operand[31]), shift_operand}) >>> shift_amt[4:0]);
shift_result = shift_result_ext[31:0];
unused_shift_result_ext = shift_result_ext[32];
begin : sv2v_autoblock_6
reg [31:0] i;
for (i = 0; i < 32; i = i + 1)
shift_result_rev[i] = shift_result[31 - i];
end
shift_result = (shift_left ? shift_result_rev : shift_result);
end
wire bwlogic_or;
wire bwlogic_and;
wire [31:0] bwlogic_operand_b;
wire [31:0] bwlogic_or_result;
wire [31:0] bwlogic_and_result;
wire [31:0] bwlogic_xor_result;
reg [31:0] bwlogic_result;
reg bwlogic_op_b_negate;
localparam [5:0] ibex_pkg_ALU_ANDN = 7;
localparam [5:0] ibex_pkg_ALU_CMIX = 40;
localparam [5:0] ibex_pkg_ALU_ORN = 6;
localparam [5:0] ibex_pkg_ALU_XNOR = 5;
always @(*)
case (operator_i)
ibex_pkg_ALU_XNOR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_ANDN: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? 1'b1 : 1'b0);
ibex_pkg_ALU_CMIX: bwlogic_op_b_negate = (RV32B != ibex_pkg_RV32BNone ? ~instr_first_cycle_i : 1'b0);
default: bwlogic_op_b_negate = 1'b0;
endcase
assign bwlogic_operand_b = (bwlogic_op_b_negate ? operand_b_neg[32:1] : operand_b_i);
assign bwlogic_or_result = operand_a_i | bwlogic_operand_b;
assign bwlogic_and_result = operand_a_i & bwlogic_operand_b;
assign bwlogic_xor_result = operand_a_i ^ bwlogic_operand_b;
localparam [5:0] ibex_pkg_ALU_OR = 3;
assign bwlogic_or = (operator_i == ibex_pkg_ALU_OR) | (operator_i == ibex_pkg_ALU_ORN);
localparam [5:0] ibex_pkg_ALU_AND = 4;
assign bwlogic_and = (operator_i == ibex_pkg_ALU_AND) | (operator_i == ibex_pkg_ALU_ANDN);
always @(*)
case (1'b1)
bwlogic_or: bwlogic_result = bwlogic_or_result;
bwlogic_and: bwlogic_result = bwlogic_and_result;
default: bwlogic_result = bwlogic_xor_result;
endcase
wire [5:0] bitcnt_result;
wire [31:0] minmax_result;
reg [31:0] pack_result;
wire [31:0] sext_result;
reg [31:0] singlebit_result;
reg [31:0] rev_result;
reg [31:0] shuffle_result;
reg [31:0] butterfly_result;
reg [31:0] invbutterfly_result;
reg [31:0] clmul_result;
reg [31:0] multicycle_result;
localparam [5:0] ibex_pkg_ALU_BDEP = 48;
localparam [5:0] ibex_pkg_ALU_BEXT = 47;
localparam [5:0] ibex_pkg_ALU_CLMULH = 52;
localparam [5:0] ibex_pkg_ALU_CLMULR = 51;
localparam [5:0] ibex_pkg_ALU_CLZ = 34;
localparam [5:0] ibex_pkg_ALU_CMOV = 39;
localparam [5:0] ibex_pkg_ALU_CRC32C_B = 54;
localparam [5:0] ibex_pkg_ALU_CRC32C_H = 56;
localparam [5:0] ibex_pkg_ALU_CRC32C_W = 58;
localparam [5:0] ibex_pkg_ALU_CRC32_B = 53;
localparam [5:0] ibex_pkg_ALU_CRC32_H = 55;
localparam [5:0] ibex_pkg_ALU_CRC32_W = 57;
localparam [5:0] ibex_pkg_ALU_CTZ = 35;
localparam [5:0] ibex_pkg_ALU_GORC = 16;
localparam [5:0] ibex_pkg_ALU_PACKH = 31;
localparam [5:0] ibex_pkg_ALU_PACKU = 30;
localparam [5:0] ibex_pkg_ALU_SEXTB = 32;
localparam [5:0] ibex_pkg_ALU_UNSHFL = 18;
localparam integer ibex_pkg_RV32BFull = 2;
generate
if (RV32B != ibex_pkg_RV32BNone) begin : g_alu_rvb
wire zbe_op;
wire bitcnt_ctz;
wire bitcnt_clz;
wire bitcnt_cz;
reg [31:0] bitcnt_bits;
wire [31:0] bitcnt_mask_op;
reg [31:0] bitcnt_bit_mask;
reg [191:0] bitcnt_partial;
wire [31:0] bitcnt_partial_lsb_d;
wire [31:0] bitcnt_partial_msb_d;
assign bitcnt_ctz = operator_i == ibex_pkg_ALU_CTZ;
assign bitcnt_clz = operator_i == ibex_pkg_ALU_CLZ;
assign bitcnt_cz = bitcnt_ctz | bitcnt_clz;
assign bitcnt_result = bitcnt_partial[0+:6];
assign bitcnt_mask_op = (bitcnt_clz ? operand_a_rev : operand_a_i);
always @(*) begin
bitcnt_bit_mask = bitcnt_mask_op;
bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 1);
bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 2);
bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 4);
bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 8);
bitcnt_bit_mask = bitcnt_bit_mask | (bitcnt_bit_mask << 16);
bitcnt_bit_mask = ~bitcnt_bit_mask;
end
assign zbe_op = (operator_i == ibex_pkg_ALU_BEXT) | (operator_i == ibex_pkg_ALU_BDEP);
always @(*)
case (1'b1)
zbe_op: bitcnt_bits = operand_b_i;
bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op;
default: bitcnt_bits = operand_a_i;
endcase
always @(*) begin
bitcnt_partial = {32 {6'b000000}};
begin : sv2v_autoblock_7
reg [31:0] i;
for (i = 1; i < 32; i = i + 2)
bitcnt_partial[(31 - i) * 6+:6] = {5'h00, bitcnt_bits[i]} + {5'h00, bitcnt_bits[i - 1]};
end
begin : sv2v_autoblock_8
reg [31:0] i;
for (i = 3; i < 32; i = i + 4)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
end
begin : sv2v_autoblock_9
reg [31:0] i;
for (i = 7; i < 32; i = i + 8)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
end
begin : sv2v_autoblock_10
reg [31:0] i;
for (i = 15; i < 32; i = i + 16)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(39 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
end
bitcnt_partial[0+:6] = bitcnt_partial[96+:6] + bitcnt_partial[0+:6];
bitcnt_partial[48+:6] = bitcnt_partial[96+:6] + bitcnt_partial[48+:6];
begin : sv2v_autoblock_11
reg [31:0] i;
for (i = 11; i < 32; i = i + 8)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(35 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
end
begin : sv2v_autoblock_12
reg [31:0] i;
for (i = 5; i < 32; i = i + 4)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(33 - i) * 6+:6] + bitcnt_partial[(31 - i) * 6+:6];
end
bitcnt_partial[186+:6] = {5'h00, bitcnt_bits[0]};
begin : sv2v_autoblock_13
reg [31:0] i;
for (i = 2; i < 32; i = i + 2)
bitcnt_partial[(31 - i) * 6+:6] = bitcnt_partial[(32 - i) * 6+:6] + {5'h00, bitcnt_bits[i]};
end
end
assign minmax_result = (cmp_result ? operand_a_i : operand_b_i);
wire packu;
wire packh;
assign packu = operator_i == ibex_pkg_ALU_PACKU;
assign packh = operator_i == ibex_pkg_ALU_PACKH;
always @(*)
case (1'b1)
packu: pack_result = {operand_b_i[31:16], operand_a_i[31:16]};
packh: pack_result = {16'h0000, operand_b_i[7:0], operand_a_i[7:0]};
default: pack_result = {operand_b_i[15:0], operand_a_i[15:0]};
endcase
assign sext_result = (operator_i == ibex_pkg_ALU_SEXTB ? {{24 {operand_a_i[7]}}, operand_a_i[7:0]} : {{16 {operand_a_i[15]}}, operand_a_i[15:0]});
always @(*)
case (operator_i)
ibex_pkg_ALU_SBSET: singlebit_result = operand_a_i | shift_result;
ibex_pkg_ALU_SBCLR: singlebit_result = operand_a_i & ~shift_result;
ibex_pkg_ALU_SBINV: singlebit_result = operand_a_i ^ shift_result;
default: singlebit_result = {31'h00000000, shift_result[0]};
endcase
wire [4:0] zbp_shift_amt;
wire gorc_op;
assign gorc_op = operator_i == ibex_pkg_ALU_GORC;
assign zbp_shift_amt[2:0] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[2:0] : {3 {&shift_amt[2:0]}});
assign zbp_shift_amt[4:3] = (RV32B == ibex_pkg_RV32BFull ? shift_amt[4:3] : {2 {&shift_amt[4:3]}});
always @(*) begin
rev_result = operand_a_i;
if (zbp_shift_amt[0])
rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h55555555) << 1)) | ((rev_result & 32'haaaaaaaa) >> 1);
if (zbp_shift_amt[1])
rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h33333333) << 2)) | ((rev_result & 32'hcccccccc) >> 2);
if (zbp_shift_amt[2])
rev_result = ((gorc_op ? rev_result : 32'h00000000) | ((rev_result & 32'h0f0f0f0f) << 4)) | ((rev_result & 32'hf0f0f0f0) >> 4);
if (zbp_shift_amt[3])
rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h00ff00ff) << 8)) | ((rev_result & 32'hff00ff00) >> 8);
if (zbp_shift_amt[4])
rev_result = ((gorc_op & (RV32B == ibex_pkg_RV32BFull) ? rev_result : 32'h00000000) | ((rev_result & 32'h0000ffff) << 16)) | ((rev_result & 32'hffff0000) >> 16);
end
wire crc_hmode;
wire crc_bmode;
wire [31:0] clmul_result_rev;
if (RV32B == ibex_pkg_RV32BFull) begin : gen_alu_rvb_full
localparam [127:0] SHUFFLE_MASK_L = {32'h00ff0000, 32'h0f000f00, 32'h30303030, 32'h44444444};
localparam [127:0] SHUFFLE_MASK_R = {32'h0000ff00, 32'h00f000f0, 32'h0c0c0c0c, 32'h22222222};
localparam [127:0] FLIP_MASK_L = {32'h22001100, 32'h00440000, 32'h44110000, 32'h11000000};
localparam [127:0] FLIP_MASK_R = {32'h00880044, 32'h00002200, 32'h00008822, 32'h00000088};
wire [31:0] SHUFFLE_MASK_NOT [0:3];
for (i = 0; i < 4; i = i + 1) begin : gen_shuffle_mask_not
assign SHUFFLE_MASK_NOT[i] = ~(SHUFFLE_MASK_L[(3 - i) * 32+:32] | SHUFFLE_MASK_R[(3 - i) * 32+:32]);
end
wire shuffle_flip;
assign shuffle_flip = operator_i == ibex_pkg_ALU_UNSHFL;
reg [3:0] shuffle_mode;
always @(*) begin
shuffle_result = operand_a_i;
if (shuffle_flip) begin
shuffle_mode[3] = shift_amt[0];
shuffle_mode[2] = shift_amt[1];
shuffle_mode[1] = shift_amt[2];
shuffle_mode[0] = shift_amt[3];
end
else
shuffle_mode = shift_amt[3:0];
if (shuffle_flip)
shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]);
if (shuffle_mode[3])
shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[0]) | (((shuffle_result << 8) & SHUFFLE_MASK_L[96+:32]) | ((shuffle_result >> 8) & SHUFFLE_MASK_R[96+:32]));
if (shuffle_mode[2])
shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[1]) | (((shuffle_result << 4) & SHUFFLE_MASK_L[64+:32]) | ((shuffle_result >> 4) & SHUFFLE_MASK_R[64+:32]));
if (shuffle_mode[1])
shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[2]) | (((shuffle_result << 2) & SHUFFLE_MASK_L[32+:32]) | ((shuffle_result >> 2) & SHUFFLE_MASK_R[32+:32]));
if (shuffle_mode[0])
shuffle_result = (shuffle_result & SHUFFLE_MASK_NOT[3]) | (((shuffle_result << 1) & SHUFFLE_MASK_L[0+:32]) | ((shuffle_result >> 1) & SHUFFLE_MASK_R[0+:32]));
if (shuffle_flip)
shuffle_result = ((((((((shuffle_result & 32'h88224411) | ((shuffle_result << 6) & FLIP_MASK_L[96+:32])) | ((shuffle_result >> 6) & FLIP_MASK_R[96+:32])) | ((shuffle_result << 9) & FLIP_MASK_L[64+:32])) | ((shuffle_result >> 9) & FLIP_MASK_R[64+:32])) | ((shuffle_result << 15) & FLIP_MASK_L[32+:32])) | ((shuffle_result >> 15) & FLIP_MASK_R[32+:32])) | ((shuffle_result << 21) & FLIP_MASK_L[0+:32])) | ((shuffle_result >> 21) & FLIP_MASK_R[0+:32]);
end
reg [191:0] bitcnt_partial_q;
for (i = 0; i < 32; i = i + 1) begin : gen_bitcnt_reg_in_lsb
assign bitcnt_partial_lsb_d[i] = bitcnt_partial[(31 - i) * 6];
end
for (i = 0; i < 16; i = i + 1) begin : gen_bitcnt_reg_in_b1
assign bitcnt_partial_msb_d[i] = bitcnt_partial[((31 - ((2 * i) + 1)) * 6) + 1];
end
for (i = 0; i < 8; i = i + 1) begin : gen_bitcnt_reg_in_b2
assign bitcnt_partial_msb_d[16 + i] = bitcnt_partial[((31 - ((4 * i) + 3)) * 6) + 2];
end
for (i = 0; i < 4; i = i + 1) begin : gen_bitcnt_reg_in_b3
assign bitcnt_partial_msb_d[24 + i] = bitcnt_partial[((31 - ((8 * i) + 7)) * 6) + 3];
end
for (i = 0; i < 2; i = i + 1) begin : gen_bitcnt_reg_in_b4
assign bitcnt_partial_msb_d[28 + i] = bitcnt_partial[((31 - ((16 * i) + 15)) * 6) + 4];
end
assign bitcnt_partial_msb_d[30] = bitcnt_partial[5];
assign bitcnt_partial_msb_d[31] = 1'b0;
always @(*) begin
bitcnt_partial_q = {32 {6'b000000}};
begin : sv2v_autoblock_14
reg [31:0] i;
for (i = 0; i < 32; i = i + 1)
begin : gen_bitcnt_reg_out_lsb
bitcnt_partial_q[(31 - i) * 6] = imd_val_q_i[32 + i];
end
end
begin : sv2v_autoblock_15
reg [31:0] i;
for (i = 0; i < 16; i = i + 1)
begin : gen_bitcnt_reg_out_b1
bitcnt_partial_q[((31 - ((2 * i) + 1)) * 6) + 1] = imd_val_q_i[i];
end
end
begin : sv2v_autoblock_16
reg [31:0] i;
for (i = 0; i < 8; i = i + 1)
begin : gen_bitcnt_reg_out_b2
bitcnt_partial_q[((31 - ((4 * i) + 3)) * 6) + 2] = imd_val_q_i[16 + i];
end
end
begin : sv2v_autoblock_17
reg [31:0] i;
for (i = 0; i < 4; i = i + 1)
begin : gen_bitcnt_reg_out_b3
bitcnt_partial_q[((31 - ((8 * i) + 7)) * 6) + 3] = imd_val_q_i[24 + i];
end
end
begin : sv2v_autoblock_18
reg [31:0] i;
for (i = 0; i < 2; i = i + 1)
begin : gen_bitcnt_reg_out_b4
bitcnt_partial_q[((31 - ((16 * i) + 15)) * 6) + 4] = imd_val_q_i[28 + i];
end
end
bitcnt_partial_q[5] = imd_val_q_i[30];
end
wire [31:0] butterfly_mask_l [0:4];
wire [31:0] butterfly_mask_r [0:4];
wire [31:0] butterfly_mask_not [0:4];
wire [31:0] lrotc_stage [0:4];
genvar stg;
for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_ctrl_stage
genvar seg;
for (seg = 0; seg < (2 ** stg); seg = seg + 1) begin : gen_butterfly_ctrl
assign lrotc_stage[stg][((2 * (16 >> stg)) * (seg + 1)) - 1:(2 * (16 >> stg)) * seg] = {{16 >> stg {1'b0}}, {16 >> stg {1'b1}}} << bitcnt_partial_q[((32 - ((16 >> stg) * ((2 * seg) + 1))) * 6) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) : ($clog2(16 >> stg) + ($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))) - 1)-:($clog2(16 >> stg) >= 0 ? $clog2(16 >> stg) + 1 : 1 - $clog2(16 >> stg))];
assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)];
assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = ~lrotc_stage[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)];
assign butterfly_mask_l[stg][((16 >> stg) * ((2 * seg) + 1)) - 1:(16 >> stg) * (2 * seg)] = {((((16 >> stg) * ((2 * seg) + 1)) - 1) >= ((16 >> stg) * (2 * seg)) ? ((((16 >> stg) * ((2 * seg) + 1)) - 1) - ((16 >> stg) * (2 * seg))) + 1 : (((16 >> stg) * (2 * seg)) - (((16 >> stg) * ((2 * seg) + 1)) - 1)) + 1) {1'sb0}};
assign butterfly_mask_r[stg][((16 >> stg) * ((2 * seg) + 2)) - 1:(16 >> stg) * ((2 * seg) + 1)] = {((((16 >> stg) * ((2 * seg) + 2)) - 1) >= ((16 >> stg) * ((2 * seg) + 1)) ? ((((16 >> stg) * ((2 * seg) + 2)) - 1) - ((16 >> stg) * ((2 * seg) + 1))) + 1 : (((16 >> stg) * ((2 * seg) + 1)) - (((16 >> stg) * ((2 * seg) + 2)) - 1)) + 1) {1'sb0}};
end
end
for (stg = 0; stg < 5; stg = stg + 1) begin : gen_butterfly_not
assign butterfly_mask_not[stg] = ~(butterfly_mask_l[stg] | butterfly_mask_r[stg]);
end
always @(*) begin
butterfly_result = operand_a_i;
butterfly_result = ((butterfly_result & butterfly_mask_not[0]) | ((butterfly_result & butterfly_mask_l[0]) >> 16)) | ((butterfly_result & butterfly_mask_r[0]) << 16);
butterfly_result = ((butterfly_result & butterfly_mask_not[1]) | ((butterfly_result & butterfly_mask_l[1]) >> 8)) | ((butterfly_result & butterfly_mask_r[1]) << 8);
butterfly_result = ((butterfly_result & butterfly_mask_not[2]) | ((butterfly_result & butterfly_mask_l[2]) >> 4)) | ((butterfly_result & butterfly_mask_r[2]) << 4);
butterfly_result = ((butterfly_result & butterfly_mask_not[3]) | ((butterfly_result & butterfly_mask_l[3]) >> 2)) | ((butterfly_result & butterfly_mask_r[3]) << 2);
butterfly_result = ((butterfly_result & butterfly_mask_not[4]) | ((butterfly_result & butterfly_mask_l[4]) >> 1)) | ((butterfly_result & butterfly_mask_r[4]) << 1);
butterfly_result = butterfly_result & operand_b_i;
end
always @(*) begin
invbutterfly_result = operand_a_i & operand_b_i;
invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[4]) | ((invbutterfly_result & butterfly_mask_l[4]) >> 1)) | ((invbutterfly_result & butterfly_mask_r[4]) << 1);
invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[3]) | ((invbutterfly_result & butterfly_mask_l[3]) >> 2)) | ((invbutterfly_result & butterfly_mask_r[3]) << 2);
invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[2]) | ((invbutterfly_result & butterfly_mask_l[2]) >> 4)) | ((invbutterfly_result & butterfly_mask_r[2]) << 4);
invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[1]) | ((invbutterfly_result & butterfly_mask_l[1]) >> 8)) | ((invbutterfly_result & butterfly_mask_r[1]) << 8);
invbutterfly_result = ((invbutterfly_result & butterfly_mask_not[0]) | ((invbutterfly_result & butterfly_mask_l[0]) >> 16)) | ((invbutterfly_result & butterfly_mask_r[0]) << 16);
end
wire clmul_rmode;
wire clmul_hmode;
reg [31:0] clmul_op_a;
reg [31:0] clmul_op_b;
wire [31:0] operand_b_rev;
wire [31:0] clmul_and_stage [0:31];
wire [31:0] clmul_xor_stage1 [0:15];
wire [31:0] clmul_xor_stage2 [0:7];
wire [31:0] clmul_xor_stage3 [0:3];
wire [31:0] clmul_xor_stage4 [0:1];
wire [31:0] clmul_result_raw;
for (i = 0; i < 32; i = i + 1) begin : gen_rev_operand_b
assign operand_b_rev[i] = operand_b_i[31 - i];
end
assign clmul_rmode = operator_i == ibex_pkg_ALU_CLMULR;
assign clmul_hmode = operator_i == ibex_pkg_ALU_CLMULH;
localparam [31:0] CRC32_POLYNOMIAL = 32'h04c11db7;
localparam [31:0] CRC32_MU_REV = 32'hf7011641;
localparam [31:0] CRC32C_POLYNOMIAL = 32'h1edc6f41;
localparam [31:0] CRC32C_MU_REV = 32'hdea713f1;
wire crc_op;
wire crc_cpoly;
reg [31:0] crc_operand;
wire [31:0] crc_poly;
wire [31:0] crc_mu_rev;
assign crc_op = (((((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32_W)) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B)) | (operator_i == ibex_pkg_ALU_CRC32_B);
assign crc_cpoly = ((operator_i == ibex_pkg_ALU_CRC32C_W) | (operator_i == ibex_pkg_ALU_CRC32C_H)) | (operator_i == ibex_pkg_ALU_CRC32C_B);
assign crc_hmode = (operator_i == ibex_pkg_ALU_CRC32_H) | (operator_i == ibex_pkg_ALU_CRC32C_H);
assign crc_bmode = (operator_i == ibex_pkg_ALU_CRC32_B) | (operator_i == ibex_pkg_ALU_CRC32C_B);
assign crc_poly = (crc_cpoly ? CRC32C_POLYNOMIAL : CRC32_POLYNOMIAL);
assign crc_mu_rev = (crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV);
always @(*)
case (1'b1)
crc_bmode: crc_operand = {operand_a_i[7:0], 24'h000000};
crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0000};
default: crc_operand = operand_a_i;
endcase
always @(*)
if (crc_op) begin
clmul_op_a = (instr_first_cycle_i ? crc_operand : imd_val_q_i[32+:32]);
clmul_op_b = (instr_first_cycle_i ? crc_mu_rev : crc_poly);
end
else begin
clmul_op_a = (clmul_rmode | clmul_hmode ? operand_a_rev : operand_a_i);
clmul_op_b = (clmul_rmode | clmul_hmode ? operand_b_rev : operand_b_i);
end
for (i = 0; i < 32; i = i + 1) begin : gen_clmul_and_op
assign clmul_and_stage[i] = (clmul_op_b[i] ? clmul_op_a << i : {32 {1'sb0}});
end
for (i = 0; i < 16; i = i + 1) begin : gen_clmul_xor_op_l1
assign clmul_xor_stage1[i] = clmul_and_stage[2 * i] ^ clmul_and_stage[(2 * i) + 1];
end
for (i = 0; i < 8; i = i + 1) begin : gen_clmul_xor_op_l2
assign clmul_xor_stage2[i] = clmul_xor_stage1[2 * i] ^ clmul_xor_stage1[(2 * i) + 1];
end
for (i = 0; i < 4; i = i + 1) begin : gen_clmul_xor_op_l3
assign clmul_xor_stage3[i] = clmul_xor_stage2[2 * i] ^ clmul_xor_stage2[(2 * i) + 1];
end
for (i = 0; i < 2; i = i + 1) begin : gen_clmul_xor_op_l4
assign clmul_xor_stage4[i] = clmul_xor_stage3[2 * i] ^ clmul_xor_stage3[(2 * i) + 1];
end
assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1];
for (i = 0; i < 32; i = i + 1) begin : gen_rev_clmul_result
assign clmul_result_rev[i] = clmul_result_raw[31 - i];
end
always @(*)
case (1'b1)
clmul_rmode: clmul_result = clmul_result_rev;
clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]};
default: clmul_result = clmul_result_raw;
endcase
end
else begin : gen_alu_rvb_notfull
wire [31:0] unused_imd_val_q_1;
assign unused_imd_val_q_1 = imd_val_q_i[0+:32];
wire [32:1] sv2v_tmp_8C42B;
assign sv2v_tmp_8C42B = {32 {1'sb0}};
always @(*) shuffle_result = sv2v_tmp_8C42B;
wire [32:1] sv2v_tmp_B0AD4;
assign sv2v_tmp_B0AD4 = {32 {1'sb0}};
always @(*) butterfly_result = sv2v_tmp_B0AD4;
wire [32:1] sv2v_tmp_AFC2C;
assign sv2v_tmp_AFC2C = {32 {1'sb0}};
always @(*) invbutterfly_result = sv2v_tmp_AFC2C;
wire [32:1] sv2v_tmp_3A741;
assign sv2v_tmp_3A741 = {32 {1'sb0}};
always @(*) clmul_result = sv2v_tmp_3A741;
assign bitcnt_partial_lsb_d = {32 {1'sb0}};
assign bitcnt_partial_msb_d = {32 {1'sb0}};
assign clmul_result_rev = {32 {1'sb0}};
assign crc_bmode = 1'b0;
assign crc_hmode = 1'b0;
end
always @(*)
case (operator_i)
ibex_pkg_ALU_CMOV: begin
multicycle_result = (operand_b_i == 32'h00000000 ? operand_a_i : imd_val_q_i[32+:32]);
imd_val_d_o = {operand_a_i, 32'h00000000};
if (instr_first_cycle_i)
imd_val_we_o = 2'b01;
else
imd_val_we_o = 2'b00;
end
ibex_pkg_ALU_CMIX: begin
multicycle_result = imd_val_q_i[32+:32] | bwlogic_and_result;
imd_val_d_o = {bwlogic_and_result, 32'h00000000};
if (instr_first_cycle_i)
imd_val_we_o = 2'b01;
else
imd_val_we_o = 2'b00;
end
ibex_pkg_ALU_FSR, ibex_pkg_ALU_FSL, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR: begin
if (shift_amt[4:0] == 5'h00)
multicycle_result = (shift_amt[5] ? operand_a_i : imd_val_q_i[32+:32]);
else
multicycle_result = imd_val_q_i[32+:32] | shift_result;
imd_val_d_o = {shift_result, 32'h00000000};
if (instr_first_cycle_i)
imd_val_we_o = 2'b01;
else
imd_val_we_o = 2'b00;
end
ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B:
if (RV32B == ibex_pkg_RV32BFull) begin
case (1'b1)
crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8);
crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16);
default: multicycle_result = clmul_result_rev;
endcase
imd_val_d_o = {clmul_result_rev, 32'h00000000};
if (instr_first_cycle_i)
imd_val_we_o = 2'b01;
else
imd_val_we_o = 2'b00;
end
else begin
imd_val_d_o = {operand_a_i, 32'h00000000};
imd_val_we_o = 2'b00;
multicycle_result = {32 {1'sb0}};
end
ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP:
if (RV32B == ibex_pkg_RV32BFull) begin
multicycle_result = (operator_i == ibex_pkg_ALU_BDEP ? butterfly_result : invbutterfly_result);
imd_val_d_o = {bitcnt_partial_lsb_d, bitcnt_partial_msb_d};
if (instr_first_cycle_i)
imd_val_we_o = 2'b11;
else
imd_val_we_o = 2'b00;
end
else begin
imd_val_d_o = {operand_a_i, 32'h00000000};
imd_val_we_o = 2'b00;
multicycle_result = {32 {1'sb0}};
end
default: begin
imd_val_d_o = {operand_a_i, 32'h00000000};
imd_val_we_o = 2'b00;
multicycle_result = {32 {1'sb0}};
end
endcase
end
else begin : g_no_alu_rvb
wire [63:0] unused_imd_val_q;
assign unused_imd_val_q = imd_val_q_i;
wire [31:0] unused_butterfly_result;
assign unused_butterfly_result = butterfly_result;
wire [31:0] unused_invbutterfly_result;
assign unused_invbutterfly_result = invbutterfly_result;
assign bitcnt_result = {6 {1'sb0}};
assign minmax_result = {32 {1'sb0}};
wire [32:1] sv2v_tmp_68181;
assign sv2v_tmp_68181 = {32 {1'sb0}};
always @(*) pack_result = sv2v_tmp_68181;
assign sext_result = {32 {1'sb0}};
wire [32:1] sv2v_tmp_D756E;
assign sv2v_tmp_D756E = {32 {1'sb0}};
always @(*) singlebit_result = sv2v_tmp_D756E;
wire [32:1] sv2v_tmp_BAAB3;
assign sv2v_tmp_BAAB3 = {32 {1'sb0}};
always @(*) rev_result = sv2v_tmp_BAAB3;
wire [32:1] sv2v_tmp_8C42B;
assign sv2v_tmp_8C42B = {32 {1'sb0}};
always @(*) shuffle_result = sv2v_tmp_8C42B;
wire [32:1] sv2v_tmp_B0AD4;
assign sv2v_tmp_B0AD4 = {32 {1'sb0}};
always @(*) butterfly_result = sv2v_tmp_B0AD4;
wire [32:1] sv2v_tmp_AFC2C;
assign sv2v_tmp_AFC2C = {32 {1'sb0}};
always @(*) invbutterfly_result = sv2v_tmp_AFC2C;
wire [32:1] sv2v_tmp_3A741;
assign sv2v_tmp_3A741 = {32 {1'sb0}};
always @(*) clmul_result = sv2v_tmp_3A741;
wire [32:1] sv2v_tmp_172E8;
assign sv2v_tmp_172E8 = {32 {1'sb0}};
always @(*) multicycle_result = sv2v_tmp_172E8;
wire [64:1] sv2v_tmp_CAB3F;
assign sv2v_tmp_CAB3F = {2 {32'b00000000000000000000000000000000}};
always @(*) imd_val_d_o = sv2v_tmp_CAB3F;
wire [2:1] sv2v_tmp_B65CC;
assign sv2v_tmp_B65CC = {2 {1'b0}};
always @(*) imd_val_we_o = sv2v_tmp_B65CC;
end
endgenerate
localparam [5:0] ibex_pkg_ALU_ADD = 0;
localparam [5:0] ibex_pkg_ALU_CLMUL = 50;
localparam [5:0] ibex_pkg_ALU_GREV = 15;
localparam [5:0] ibex_pkg_ALU_PACK = 29;
localparam [5:0] ibex_pkg_ALU_PCNT = 36;
localparam [5:0] ibex_pkg_ALU_SBEXT = 46;
localparam [5:0] ibex_pkg_ALU_SEXTH = 33;
localparam [5:0] ibex_pkg_ALU_SHFL = 17;
localparam [5:0] ibex_pkg_ALU_SRL = 9;
localparam [5:0] ibex_pkg_ALU_XOR = 2;
always @(*) begin
result_o = {32 {1'sb0}};
case (operator_i)
ibex_pkg_ALU_XOR, ibex_pkg_ALU_XNOR, ibex_pkg_ALU_OR, ibex_pkg_ALU_ORN, ibex_pkg_ALU_AND, ibex_pkg_ALU_ANDN: result_o = bwlogic_result;
ibex_pkg_ALU_ADD, ibex_pkg_ALU_SUB: result_o = adder_result;
ibex_pkg_ALU_SLL, ibex_pkg_ALU_SRL, ibex_pkg_ALU_SRA, ibex_pkg_ALU_SLO, ibex_pkg_ALU_SRO: result_o = shift_result;
ibex_pkg_ALU_SHFL, ibex_pkg_ALU_UNSHFL: result_o = shuffle_result;
ibex_pkg_ALU_EQ, ibex_pkg_ALU_NE, ibex_pkg_ALU_GE, ibex_pkg_ALU_GEU, ibex_pkg_ALU_LT, ibex_pkg_ALU_LTU, ibex_pkg_ALU_SLT, ibex_pkg_ALU_SLTU: result_o = {31'h00000000, cmp_result};
ibex_pkg_ALU_MIN, ibex_pkg_ALU_MAX, ibex_pkg_ALU_MINU, ibex_pkg_ALU_MAXU: result_o = minmax_result;
ibex_pkg_ALU_CLZ, ibex_pkg_ALU_CTZ, ibex_pkg_ALU_PCNT: result_o = {26'h0000000, bitcnt_result};
ibex_pkg_ALU_PACK, ibex_pkg_ALU_PACKH, ibex_pkg_ALU_PACKU: result_o = pack_result;
ibex_pkg_ALU_SEXTB, ibex_pkg_ALU_SEXTH: result_o = sext_result;
ibex_pkg_ALU_CMIX, ibex_pkg_ALU_CMOV, ibex_pkg_ALU_FSL, ibex_pkg_ALU_FSR, ibex_pkg_ALU_ROL, ibex_pkg_ALU_ROR, ibex_pkg_ALU_CRC32_W, ibex_pkg_ALU_CRC32C_W, ibex_pkg_ALU_CRC32_H, ibex_pkg_ALU_CRC32C_H, ibex_pkg_ALU_CRC32_B, ibex_pkg_ALU_CRC32C_B, ibex_pkg_ALU_BEXT, ibex_pkg_ALU_BDEP: result_o = multicycle_result;
ibex_pkg_ALU_SBSET, ibex_pkg_ALU_SBCLR, ibex_pkg_ALU_SBINV, ibex_pkg_ALU_SBEXT: result_o = singlebit_result;
ibex_pkg_ALU_GREV, ibex_pkg_ALU_GORC: result_o = rev_result;
ibex_pkg_ALU_BFP: result_o = bfp_result;
ibex_pkg_ALU_CLMUL, ibex_pkg_ALU_CLMULR, ibex_pkg_ALU_CLMULH: result_o = clmul_result;
default:
;
endcase
end
wire unused_shift_amt_compl;
assign unused_shift_amt_compl = shift_amt_compl[5];
endmodule |
module ibex_wb_stage (
clk_i,
rst_ni,
en_wb_i,
instr_type_wb_i,
pc_id_i,
instr_is_compressed_id_i,
instr_perf_count_id_i,
ready_wb_o,
rf_write_wb_o,
outstanding_load_wb_o,
outstanding_store_wb_o,
pc_wb_o,
perf_instr_ret_wb_o,
perf_instr_ret_compressed_wb_o,
rf_waddr_id_i,
rf_wdata_id_i,
rf_we_id_i,
rf_wdata_lsu_i,
rf_we_lsu_i,
rf_wdata_fwd_wb_o,
rf_waddr_wb_o,
rf_wdata_wb_o,
rf_we_wb_o,
lsu_resp_valid_i,
lsu_resp_err_i,
instr_done_wb_o
);
parameter [0:0] WritebackStage = 1'b0;
input wire clk_i;
input wire rst_ni;
input wire en_wb_i;
input wire [1:0] instr_type_wb_i;
input wire [31:0] pc_id_i;
input wire instr_is_compressed_id_i;
input wire instr_perf_count_id_i;
output wire ready_wb_o;
output wire rf_write_wb_o;
output wire outstanding_load_wb_o;
output wire outstanding_store_wb_o;
output wire [31:0] pc_wb_o;
output wire perf_instr_ret_wb_o;
output wire perf_instr_ret_compressed_wb_o;
input wire [4:0] rf_waddr_id_i;
input wire [31:0] rf_wdata_id_i;
input wire rf_we_id_i;
input wire [31:0] rf_wdata_lsu_i;
input wire rf_we_lsu_i;
output wire [31:0] rf_wdata_fwd_wb_o;
output wire [4:0] rf_waddr_wb_o;
output wire [31:0] rf_wdata_wb_o;
output wire rf_we_wb_o;
input wire lsu_resp_valid_i;
input wire lsu_resp_err_i;
output wire instr_done_wb_o;
wire [31:0] rf_wdata_wb_mux [0:1];
wire [1:0] rf_wdata_wb_mux_we;
localparam [1:0] ibex_pkg_WB_INSTR_LOAD = 0;
localparam [1:0] ibex_pkg_WB_INSTR_OTHER = 2;
localparam [1:0] ibex_pkg_WB_INSTR_STORE = 1;
generate
if (WritebackStage) begin : g_writeback_stage
reg [31:0] rf_wdata_wb_q;
reg rf_we_wb_q;
reg [4:0] rf_waddr_wb_q;
wire wb_done;
reg wb_valid_q;
reg [31:0] wb_pc_q;
reg wb_compressed_q;
reg wb_count_q;
reg [1:0] wb_instr_type_q;
wire wb_valid_d;
assign wb_valid_d = (en_wb_i & ready_wb_o) | (wb_valid_q & ~wb_done);
assign wb_done = (wb_instr_type_q == ibex_pkg_WB_INSTR_OTHER) | lsu_resp_valid_i;
always @(posedge clk_i or negedge rst_ni)
if (~rst_ni)
wb_valid_q <= 1'b0;
else
wb_valid_q <= wb_valid_d;
always @(posedge clk_i)
if (en_wb_i) begin
rf_we_wb_q <= rf_we_id_i;
rf_waddr_wb_q <= rf_waddr_id_i;
rf_wdata_wb_q <= rf_wdata_id_i;
wb_instr_type_q <= instr_type_wb_i;
wb_pc_q <= pc_id_i;
wb_compressed_q <= instr_is_compressed_id_i;
wb_count_q <= instr_perf_count_id_i;
end
assign rf_waddr_wb_o = rf_waddr_wb_q;
assign rf_wdata_wb_mux[0] = rf_wdata_wb_q;
assign rf_wdata_wb_mux_we[0] = rf_we_wb_q & wb_valid_q;
assign ready_wb_o = ~wb_valid_q | wb_done;
assign rf_write_wb_o = wb_valid_q & (rf_we_wb_q | (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD));
assign outstanding_load_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_LOAD);
assign outstanding_store_wb_o = wb_valid_q & (wb_instr_type_q == ibex_pkg_WB_INSTR_STORE);
assign pc_wb_o = wb_pc_q;
assign instr_done_wb_o = wb_valid_q & wb_done;
assign perf_instr_ret_wb_o = (instr_done_wb_o & wb_count_q) & ~(lsu_resp_valid_i & lsu_resp_err_i);
assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & wb_compressed_q;
assign rf_wdata_fwd_wb_o = rf_wdata_wb_q;
end
else begin : g_bypass_wb
assign rf_waddr_wb_o = rf_waddr_id_i;
assign rf_wdata_wb_mux[0] = rf_wdata_id_i;
assign rf_wdata_wb_mux_we[0] = rf_we_id_i;
assign perf_instr_ret_wb_o = (instr_perf_count_id_i & en_wb_i) & ~(lsu_resp_valid_i & lsu_resp_err_i);
assign perf_instr_ret_compressed_wb_o = perf_instr_ret_wb_o & instr_is_compressed_id_i;
assign ready_wb_o = 1'b1;
wire unused_clk;
wire unused_rst;
wire [1:0] unused_instr_type_wb;
wire [31:0] unused_pc_id;
assign unused_clk = clk_i;
assign unused_rst = rst_ni;
assign unused_instr_type_wb = instr_type_wb_i;
assign unused_pc_id = pc_id_i;
assign outstanding_load_wb_o = 1'b0;
assign outstanding_store_wb_o = 1'b0;
assign pc_wb_o = {32 {1'sb0}};
assign rf_write_wb_o = 1'b0;
assign rf_wdata_fwd_wb_o = 32'b00000000000000000000000000000000;
assign instr_done_wb_o = 1'b0;
end
endgenerate
assign rf_wdata_wb_mux[1] = rf_wdata_lsu_i;
assign rf_wdata_wb_mux_we[1] = rf_we_lsu_i;
assign rf_wdata_wb_o = (rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1]);
assign rf_we_wb_o = |rf_wdata_wb_mux_we;
endmodule |
module stream_demux_N_OUP3
(
inp_valid_i,
inp_ready_o,
oup_sel_i,
oup_valid_o,
oup_ready_i
);
input [1:0] oup_sel_i;
output [2:0] oup_valid_o;
input [2:0] oup_ready_i;
input inp_valid_i;
output inp_ready_o;
wire [2:0] oup_valid_o;
wire inp_ready_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign N10 = N0 & oup_sel_i[1];
assign N0 = ~oup_sel_i[0];
assign N9 = oup_sel_i[0] & N1;
assign N1 = ~oup_sel_i[1];
assign N14 = N2 & N3;
assign N2 = ~oup_sel_i[0];
assign N3 = ~oup_sel_i[1];
assign oup_valid_o[0] = (N4)? inp_valid_i :
(N11)? 1'b0 : 1'b0;
assign N4 = N14;
assign oup_valid_o[1] = (N5)? inp_valid_i :
(N12)? 1'b0 : 1'b0;
assign N5 = N9;
assign oup_valid_o[2] = (N6)? inp_valid_i :
(N13)? 1'b0 : 1'b0;
assign N6 = N10;
assign inp_ready_o = (N4)? oup_ready_i[0] :
(N7)? oup_ready_i[1] :
(N8)? oup_ready_i[2] : 1'b0;
assign N7 = oup_sel_i[0];
assign N8 = oup_sel_i[1];
assign N11 = ~N14;
assign N12 = ~N9;
assign N13 = ~N10;
endmodule |
module re_name
(
clk_i,
rst_ni,
flush_i,
flush_unissied_instr_i,
issue_instr_i,
issue_instr_valid_i,
issue_ack_o,
issue_instr_o,
issue_instr_valid_o,
issue_ack_i
);
input [361:0] issue_instr_i;
output [361:0] issue_instr_o;
input clk_i;
input rst_ni;
input flush_i;
input flush_unissied_instr_i;
input issue_instr_valid_i;
input issue_ack_i;
output issue_ack_o;
output issue_instr_valid_o;
wire [361:0] issue_instr_o;
wire issue_ack_o,issue_instr_valid_o,issue_ack_i,issue_instr_valid_i;
assign issue_instr_o[271] = 1'b0;
assign issue_instr_o[277] = 1'b0;
assign issue_instr_o[283] = 1'b0;
assign issue_ack_o = issue_ack_i;
assign issue_instr_o[361] = issue_instr_i[361];
assign issue_instr_o[360] = issue_instr_i[360];
assign issue_instr_o[359] = issue_instr_i[359];
assign issue_instr_o[358] = issue_instr_i[358];
assign issue_instr_o[357] = issue_instr_i[357];
assign issue_instr_o[356] = issue_instr_i[356];
assign issue_instr_o[355] = issue_instr_i[355];
assign issue_instr_o[354] = issue_instr_i[354];
assign issue_instr_o[353] = issue_instr_i[353];
assign issue_instr_o[352] = issue_instr_i[352];
assign issue_instr_o[351] = issue_instr_i[351];
assign issue_instr_o[350] = issue_instr_i[350];
assign issue_instr_o[349] = issue_instr_i[349];
assign issue_instr_o[348] = issue_instr_i[348];
assign issue_instr_o[347] = issue_instr_i[347];
assign issue_instr_o[346] = issue_instr_i[346];
assign issue_instr_o[345] = issue_instr_i[345];
assign issue_instr_o[344] = issue_instr_i[344];
assign issue_instr_o[343] = issue_instr_i[343];
assign issue_instr_o[342] = issue_instr_i[342];
assign issue_instr_o[341] = issue_instr_i[341];
assign issue_instr_o[340] = issue_instr_i[340];
assign issue_instr_o[339] = issue_instr_i[339];
assign issue_instr_o[338] = issue_instr_i[338];
assign issue_instr_o[337] = issue_instr_i[337];
assign issue_instr_o[336] = issue_instr_i[336];
assign issue_instr_o[335] = issue_instr_i[335];
assign issue_instr_o[334] = issue_instr_i[334];
assign issue_instr_o[333] = issue_instr_i[333];
assign issue_instr_o[332] = issue_instr_i[332];
assign issue_instr_o[331] = issue_instr_i[331];
assign issue_instr_o[330] = issue_instr_i[330];
assign issue_instr_o[329] = issue_instr_i[329];
assign issue_instr_o[328] = issue_instr_i[328];
assign issue_instr_o[327] = issue_instr_i[327];
assign issue_instr_o[326] = issue_instr_i[326];
assign issue_instr_o[325] = issue_instr_i[325];
assign issue_instr_o[324] = issue_instr_i[324];
assign issue_instr_o[323] = issue_instr_i[323];
assign issue_instr_o[322] = issue_instr_i[322];
assign issue_instr_o[321] = issue_instr_i[321];
assign issue_instr_o[320] = issue_instr_i[320];
assign issue_instr_o[319] = issue_instr_i[319];
assign issue_instr_o[318] = issue_instr_i[318];
assign issue_instr_o[317] = issue_instr_i[317];
assign issue_instr_o[316] = issue_instr_i[316];
assign issue_instr_o[315] = issue_instr_i[315];
assign issue_instr_o[314] = issue_instr_i[314];
assign issue_instr_o[313] = issue_instr_i[313];
assign issue_instr_o[312] = issue_instr_i[312];
assign issue_instr_o[311] = issue_instr_i[311];
assign issue_instr_o[310] = issue_instr_i[310];
assign issue_instr_o[309] = issue_instr_i[309];
assign issue_instr_o[308] = issue_instr_i[308];
assign issue_instr_o[307] = issue_instr_i[307];
assign issue_instr_o[306] = issue_instr_i[306];
assign issue_instr_o[305] = issue_instr_i[305];
assign issue_instr_o[304] = issue_instr_i[304];
assign issue_instr_o[303] = issue_instr_i[303];
assign issue_instr_o[302] = issue_instr_i[302];
assign issue_instr_o[301] = issue_instr_i[301];
assign issue_instr_o[300] = issue_instr_i[300];
assign issue_instr_o[299] = issue_instr_i[299];
assign issue_instr_o[298] = issue_instr_i[298];
assign issue_instr_o[297] = issue_instr_i[297];
assign issue_instr_o[296] = issue_instr_i[296];
assign issue_instr_o[295] = issue_instr_i[295];
assign issue_instr_o[294] = issue_instr_i[294];
assign issue_instr_o[293] = issue_instr_i[293];
assign issue_instr_o[292] = issue_instr_i[292];
assign issue_instr_o[291] = issue_instr_i[291];
assign issue_instr_o[290] = issue_instr_i[290];
assign issue_instr_o[289] = issue_instr_i[289];
assign issue_instr_o[288] = issue_instr_i[288];
assign issue_instr_o[287] = issue_instr_i[287];
assign issue_instr_o[286] = issue_instr_i[286];
assign issue_instr_o[285] = issue_instr_i[285];
assign issue_instr_o[284] = issue_instr_i[284];
assign issue_instr_o[282] = issue_instr_i[282];
assign issue_instr_o[281] = issue_instr_i[281];
assign issue_instr_o[280] = issue_instr_i[280];
assign issue_instr_o[279] = issue_instr_i[279];
assign issue_instr_o[278] = issue_instr_i[278];
assign issue_instr_o[276] = issue_instr_i[276];
assign issue_instr_o[275] = issue_instr_i[275];
assign issue_instr_o[274] = issue_instr_i[274];
assign issue_instr_o[273] = issue_instr_i[273];
assign issue_instr_o[272] = issue_instr_i[272];
assign issue_instr_o[270] = issue_instr_i[270];
assign issue_instr_o[269] = issue_instr_i[269];
assign issue_instr_o[268] = issue_instr_i[268];
assign issue_instr_o[267] = issue_instr_i[267];
assign issue_instr_o[266] = issue_instr_i[266];
assign issue_instr_o[265] = issue_instr_i[265];
assign issue_instr_o[264] = issue_instr_i[264];
assign issue_instr_o[263] = issue_instr_i[263];
assign issue_instr_o[262] = issue_instr_i[262];
assign issue_instr_o[261] = issue_instr_i[261];
assign issue_instr_o[260] = issue_instr_i[260];
assign issue_instr_o[259] = issue_instr_i[259];
assign issue_instr_o[258] = issue_instr_i[258];
assign issue_instr_o[257] = issue_instr_i[257];
assign issue_instr_o[256] = issue_instr_i[256];
assign issue_instr_o[255] = issue_instr_i[255];
assign issue_instr_o[254] = issue_instr_i[254];
assign issue_instr_o[253] = issue_instr_i[253];
assign issue_instr_o[252] = issue_instr_i[252];
assign issue_instr_o[251] = issue_instr_i[251];
assign issue_instr_o[250] = issue_instr_i[250];
assign issue_instr_o[249] = issue_instr_i[249];
assign issue_instr_o[248] = issue_instr_i[248];
assign issue_instr_o[247] = issue_instr_i[247];
assign issue_instr_o[246] = issue_instr_i[246];
assign issue_instr_o[245] = issue_instr_i[245];
assign issue_instr_o[244] = issue_instr_i[244];
assign issue_instr_o[243] = issue_instr_i[243];
assign issue_instr_o[242] = issue_instr_i[242];
assign issue_instr_o[241] = issue_instr_i[241];
assign issue_instr_o[240] = issue_instr_i[240];
assign issue_instr_o[239] = issue_instr_i[239];
assign issue_instr_o[238] = issue_instr_i[238];
assign issue_instr_o[237] = issue_instr_i[237];
assign issue_instr_o[236] = issue_instr_i[236];
assign issue_instr_o[235] = issue_instr_i[235];
assign issue_instr_o[234] = issue_instr_i[234];
assign issue_instr_o[233] = issue_instr_i[233];
assign issue_instr_o[232] = issue_instr_i[232];
assign issue_instr_o[231] = issue_instr_i[231];
assign issue_instr_o[230] = issue_instr_i[230];
assign issue_instr_o[229] = issue_instr_i[229];
assign issue_instr_o[228] = issue_instr_i[228];
assign issue_instr_o[227] = issue_instr_i[227];
assign issue_instr_o[226] = issue_instr_i[226];
assign issue_instr_o[225] = issue_instr_i[225];
assign issue_instr_o[224] = issue_instr_i[224];
assign issue_instr_o[223] = issue_instr_i[223];
assign issue_instr_o[222] = issue_instr_i[222];
assign issue_instr_o[221] = issue_instr_i[221];
assign issue_instr_o[220] = issue_instr_i[220];
assign issue_instr_o[219] = issue_instr_i[219];
assign issue_instr_o[218] = issue_instr_i[218];
assign issue_instr_o[217] = issue_instr_i[217];
assign issue_instr_o[216] = issue_instr_i[216];
assign issue_instr_o[215] = issue_instr_i[215];
assign issue_instr_o[214] = issue_instr_i[214];
assign issue_instr_o[213] = issue_instr_i[213];
assign issue_instr_o[212] = issue_instr_i[212];
assign issue_instr_o[211] = issue_instr_i[211];
assign issue_instr_o[210] = issue_instr_i[210];
assign issue_instr_o[209] = issue_instr_i[209];
assign issue_instr_o[208] = issue_instr_i[208];
assign issue_instr_o[207] = issue_instr_i[207];
assign issue_instr_o[206] = issue_instr_i[206];
assign issue_instr_o[205] = issue_instr_i[205];
assign issue_instr_o[204] = issue_instr_i[204];
assign issue_instr_o[203] = issue_instr_i[203];
assign issue_instr_o[202] = issue_instr_i[202];
assign issue_instr_o[201] = issue_instr_i[201];
assign issue_instr_o[200] = issue_instr_i[200];
assign issue_instr_o[199] = issue_instr_i[199];
assign issue_instr_o[198] = issue_instr_i[198];
assign issue_instr_o[197] = issue_instr_i[197];
assign issue_instr_o[196] = issue_instr_i[196];
assign issue_instr_o[195] = issue_instr_i[195];
assign issue_instr_o[194] = issue_instr_i[194];
assign issue_instr_o[193] = issue_instr_i[193];
assign issue_instr_o[192] = issue_instr_i[192];
assign issue_instr_o[191] = issue_instr_i[191];
assign issue_instr_o[190] = issue_instr_i[190];
assign issue_instr_o[189] = issue_instr_i[189];
assign issue_instr_o[188] = issue_instr_i[188];
assign issue_instr_o[187] = issue_instr_i[187];
assign issue_instr_o[186] = issue_instr_i[186];
assign issue_instr_o[185] = issue_instr_i[185];
assign issue_instr_o[184] = issue_instr_i[184];
assign issue_instr_o[183] = issue_instr_i[183];
assign issue_instr_o[182] = issue_instr_i[182];
assign issue_instr_o[181] = issue_instr_i[181];
assign issue_instr_o[180] = issue_instr_i[180];
assign issue_instr_o[179] = issue_instr_i[179];
assign issue_instr_o[178] = issue_instr_i[178];
assign issue_instr_o[177] = issue_instr_i[177];
assign issue_instr_o[176] = issue_instr_i[176];
assign issue_instr_o[175] = issue_instr_i[175];
assign issue_instr_o[174] = issue_instr_i[174];
assign issue_instr_o[173] = issue_instr_i[173];
assign issue_instr_o[172] = issue_instr_i[172];
assign issue_instr_o[171] = issue_instr_i[171];
assign issue_instr_o[170] = issue_instr_i[170];
assign issue_instr_o[169] = issue_instr_i[169];
assign issue_instr_o[168] = issue_instr_i[168];
assign issue_instr_o[167] = issue_instr_i[167];
assign issue_instr_o[166] = issue_instr_i[166];
assign issue_instr_o[165] = issue_instr_i[165];
assign issue_instr_o[164] = issue_instr_i[164];
assign issue_instr_o[163] = issue_instr_i[163];
assign issue_instr_o[162] = issue_instr_i[162];
assign issue_instr_o[161] = issue_instr_i[161];
assign issue_instr_o[160] = issue_instr_i[160];
assign issue_instr_o[159] = issue_instr_i[159];
assign issue_instr_o[158] = issue_instr_i[158];
assign issue_instr_o[157] = issue_instr_i[157];
assign issue_instr_o[156] = issue_instr_i[156];
assign issue_instr_o[155] = issue_instr_i[155];
assign issue_instr_o[154] = issue_instr_i[154];
assign issue_instr_o[153] = issue_instr_i[153];
assign issue_instr_o[152] = issue_instr_i[152];
assign issue_instr_o[151] = issue_instr_i[151];
assign issue_instr_o[150] = issue_instr_i[150];
assign issue_instr_o[149] = issue_instr_i[149];
assign issue_instr_o[148] = issue_instr_i[148];
assign issue_instr_o[147] = issue_instr_i[147];
assign issue_instr_o[146] = issue_instr_i[146];
assign issue_instr_o[145] = issue_instr_i[145];
assign issue_instr_o[144] = issue_instr_i[144];
assign issue_instr_o[143] = issue_instr_i[143];
assign issue_instr_o[142] = issue_instr_i[142];
assign issue_instr_o[141] = issue_instr_i[141];
assign issue_instr_o[140] = issue_instr_i[140];
assign issue_instr_o[139] = issue_instr_i[139];
assign issue_instr_o[138] = issue_instr_i[138];
assign issue_instr_o[137] = issue_instr_i[137];
assign issue_instr_o[136] = issue_instr_i[136];
assign issue_instr_o[135] = issue_instr_i[135];
assign issue_instr_o[134] = issue_instr_i[134];
assign issue_instr_o[133] = issue_instr_i[133];
assign issue_instr_o[132] = issue_instr_i[132];
assign issue_instr_o[131] = issue_instr_i[131];
assign issue_instr_o[130] = issue_instr_i[130];
assign issue_instr_o[129] = issue_instr_i[129];
assign issue_instr_o[128] = issue_instr_i[128];
assign issue_instr_o[127] = issue_instr_i[127];
assign issue_instr_o[126] = issue_instr_i[126];
assign issue_instr_o[125] = issue_instr_i[125];
assign issue_instr_o[124] = issue_instr_i[124];
assign issue_instr_o[123] = issue_instr_i[123];
assign issue_instr_o[122] = issue_instr_i[122];
assign issue_instr_o[121] = issue_instr_i[121];
assign issue_instr_o[120] = issue_instr_i[120];
assign issue_instr_o[119] = issue_instr_i[119];
assign issue_instr_o[118] = issue_instr_i[118];
assign issue_instr_o[117] = issue_instr_i[117];
assign issue_instr_o[116] = issue_instr_i[116];
assign issue_instr_o[115] = issue_instr_i[115];
assign issue_instr_o[114] = issue_instr_i[114];
assign issue_instr_o[113] = issue_instr_i[113];
assign issue_instr_o[112] = issue_instr_i[112];
assign issue_instr_o[111] = issue_instr_i[111];
assign issue_instr_o[110] = issue_instr_i[110];
assign issue_instr_o[109] = issue_instr_i[109];
assign issue_instr_o[108] = issue_instr_i[108];
assign issue_instr_o[107] = issue_instr_i[107];
assign issue_instr_o[106] = issue_instr_i[106];
assign issue_instr_o[105] = issue_instr_i[105];
assign issue_instr_o[104] = issue_instr_i[104];
assign issue_instr_o[103] = issue_instr_i[103];
assign issue_instr_o[102] = issue_instr_i[102];
assign issue_instr_o[101] = issue_instr_i[101];
assign issue_instr_o[100] = issue_instr_i[100];
assign issue_instr_o[99] = issue_instr_i[99];
assign issue_instr_o[98] = issue_instr_i[98];
assign issue_instr_o[97] = issue_instr_i[97];
assign issue_instr_o[96] = issue_instr_i[96];
assign issue_instr_o[95] = issue_instr_i[95];
assign issue_instr_o[94] = issue_instr_i[94];
assign issue_instr_o[93] = issue_instr_i[93];
assign issue_instr_o[92] = issue_instr_i[92];
assign issue_instr_o[91] = issue_instr_i[91];
assign issue_instr_o[90] = issue_instr_i[90];
assign issue_instr_o[89] = issue_instr_i[89];
assign issue_instr_o[88] = issue_instr_i[88];
assign issue_instr_o[87] = issue_instr_i[87];
assign issue_instr_o[86] = issue_instr_i[86];
assign issue_instr_o[85] = issue_instr_i[85];
assign issue_instr_o[84] = issue_instr_i[84];
assign issue_instr_o[83] = issue_instr_i[83];
assign issue_instr_o[82] = issue_instr_i[82];
assign issue_instr_o[81] = issue_instr_i[81];
assign issue_instr_o[80] = issue_instr_i[80];
assign issue_instr_o[79] = issue_instr_i[79];
assign issue_instr_o[78] = issue_instr_i[78];
assign issue_instr_o[77] = issue_instr_i[77];
assign issue_instr_o[76] = issue_instr_i[76];
assign issue_instr_o[75] = issue_instr_i[75];
assign issue_instr_o[74] = issue_instr_i[74];
assign issue_instr_o[73] = issue_instr_i[73];
assign issue_instr_o[72] = issue_instr_i[72];
assign issue_instr_o[71] = issue_instr_i[71];
assign issue_instr_o[70] = issue_instr_i[70];
assign issue_instr_o[69] = issue_instr_i[69];
assign issue_instr_o[68] = issue_instr_i[68];
assign issue_instr_o[67] = issue_instr_i[67];
assign issue_instr_o[66] = issue_instr_i[66];
assign issue_instr_o[65] = issue_instr_i[65];
assign issue_instr_o[64] = issue_instr_i[64];
assign issue_instr_o[63] = issue_instr_i[63];
assign issue_instr_o[62] = issue_instr_i[62];
assign issue_instr_o[61] = issue_instr_i[61];
assign issue_instr_o[60] = issue_instr_i[60];
assign issue_instr_o[59] = issue_instr_i[59];
assign issue_instr_o[58] = issue_instr_i[58];
assign issue_instr_o[57] = issue_instr_i[57];
assign issue_instr_o[56] = issue_instr_i[56];
assign issue_instr_o[55] = issue_instr_i[55];
assign issue_instr_o[54] = issue_instr_i[54];
assign issue_instr_o[53] = issue_instr_i[53];
assign issue_instr_o[52] = issue_instr_i[52];
assign issue_instr_o[51] = issue_instr_i[51];
assign issue_instr_o[50] = issue_instr_i[50];
assign issue_instr_o[49] = issue_instr_i[49];
assign issue_instr_o[48] = issue_instr_i[48];
assign issue_instr_o[47] = issue_instr_i[47];
assign issue_instr_o[46] = issue_instr_i[46];
assign issue_instr_o[45] = issue_instr_i[45];
assign issue_instr_o[44] = issue_instr_i[44];
assign issue_instr_o[43] = issue_instr_i[43];
assign issue_instr_o[42] = issue_instr_i[42];
assign issue_instr_o[41] = issue_instr_i[41];
assign issue_instr_o[40] = issue_instr_i[40];
assign issue_instr_o[39] = issue_instr_i[39];
assign issue_instr_o[38] = issue_instr_i[38];
assign issue_instr_o[37] = issue_instr_i[37];
assign issue_instr_o[36] = issue_instr_i[36];
assign issue_instr_o[35] = issue_instr_i[35];
assign issue_instr_o[34] = issue_instr_i[34];
assign issue_instr_o[33] = issue_instr_i[33];
assign issue_instr_o[32] = issue_instr_i[32];
assign issue_instr_o[31] = issue_instr_i[31];
assign issue_instr_o[30] = issue_instr_i[30];
assign issue_instr_o[29] = issue_instr_i[29];
assign issue_instr_o[28] = issue_instr_i[28];
assign issue_instr_o[27] = issue_instr_i[27];
assign issue_instr_o[26] = issue_instr_i[26];
assign issue_instr_o[25] = issue_instr_i[25];
assign issue_instr_o[24] = issue_instr_i[24];
assign issue_instr_o[23] = issue_instr_i[23];
assign issue_instr_o[22] = issue_instr_i[22];
assign issue_instr_o[21] = issue_instr_i[21];
assign issue_instr_o[20] = issue_instr_i[20];
assign issue_instr_o[19] = issue_instr_i[19];
assign issue_instr_o[18] = issue_instr_i[18];
assign issue_instr_o[17] = issue_instr_i[17];
assign issue_instr_o[16] = issue_instr_i[16];
assign issue_instr_o[15] = issue_instr_i[15];
assign issue_instr_o[14] = issue_instr_i[14];
assign issue_instr_o[13] = issue_instr_i[13];
assign issue_instr_o[12] = issue_instr_i[12];
assign issue_instr_o[11] = issue_instr_i[11];
assign issue_instr_o[10] = issue_instr_i[10];
assign issue_instr_o[9] = issue_instr_i[9];
assign issue_instr_o[8] = issue_instr_i[8];
assign issue_instr_o[7] = issue_instr_i[7];
assign issue_instr_o[6] = issue_instr_i[6];
assign issue_instr_o[5] = issue_instr_i[5];
assign issue_instr_o[4] = issue_instr_i[4];
assign issue_instr_o[3] = issue_instr_i[3];
assign issue_instr_o[2] = issue_instr_i[2];
assign issue_instr_o[1] = issue_instr_i[1];
assign issue_instr_o[0] = issue_instr_i[0];
assign issue_instr_valid_o = issue_instr_valid_i;
endmodule |
module lzc_WIDTH64_MODE1
(
in_i,
cnt_o,
empty_o
);
input [63:0] in_i;
output [5:0] cnt_o;
output empty_o;
wire [5:0] cnt_o;
wire empty_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,
N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,index_nodes_62__0_,index_nodes_61__0_,
index_nodes_60__0_,index_nodes_59__0_,index_nodes_58__0_,index_nodes_57__0_,
index_nodes_56__0_,index_nodes_55__0_,index_nodes_54__0_,index_nodes_53__0_,
index_nodes_52__0_,index_nodes_51__0_,index_nodes_50__0_,index_nodes_49__0_,
index_nodes_48__0_,index_nodes_47__0_,index_nodes_46__0_,index_nodes_45__0_,
index_nodes_44__0_,index_nodes_43__0_,index_nodes_42__0_,index_nodes_41__0_,index_nodes_40__0_,
index_nodes_39__0_,index_nodes_38__0_,index_nodes_37__0_,index_nodes_36__0_,
index_nodes_35__0_,index_nodes_34__0_,index_nodes_33__0_,index_nodes_32__0_,
index_nodes_31__0_,index_nodes_30__1_,index_nodes_30__0_,index_nodes_29__1_,
index_nodes_29__0_,index_nodes_28__1_,index_nodes_28__0_,index_nodes_27__1_,
index_nodes_27__0_,index_nodes_26__1_,index_nodes_26__0_,index_nodes_25__1_,index_nodes_25__0_,
index_nodes_24__1_,index_nodes_24__0_,index_nodes_23__1_,index_nodes_23__0_,
index_nodes_22__1_,index_nodes_22__0_,index_nodes_21__1_,index_nodes_21__0_,
index_nodes_20__1_,index_nodes_20__0_,index_nodes_19__1_,index_nodes_19__0_,
index_nodes_18__1_,index_nodes_18__0_,index_nodes_17__1_,index_nodes_17__0_,
index_nodes_16__1_,index_nodes_16__0_,index_nodes_15__1_,index_nodes_15__0_,index_nodes_14__2_,
index_nodes_14__1_,index_nodes_14__0_,index_nodes_13__2_,index_nodes_13__1_,
index_nodes_13__0_,index_nodes_12__2_,index_nodes_12__1_,index_nodes_12__0_,
index_nodes_11__2_,index_nodes_11__1_,index_nodes_11__0_,index_nodes_10__2_,
index_nodes_10__1_,index_nodes_10__0_,index_nodes_9__2_,index_nodes_9__1_,index_nodes_9__0_,
index_nodes_8__2_,index_nodes_8__1_,index_nodes_8__0_,index_nodes_7__2_,
index_nodes_7__1_,index_nodes_7__0_,index_nodes_6__3_,index_nodes_6__2_,index_nodes_6__1_,
index_nodes_6__0_,index_nodes_5__3_,index_nodes_5__2_,index_nodes_5__1_,
index_nodes_5__0_,index_nodes_4__3_,index_nodes_4__2_,index_nodes_4__1_,
index_nodes_4__0_,index_nodes_3__3_,index_nodes_3__2_,index_nodes_3__1_,index_nodes_3__0_,
index_nodes_2__4_,index_nodes_2__3_,index_nodes_2__2_,index_nodes_2__1_,
index_nodes_2__0_,index_nodes_1__4_,index_nodes_1__3_,index_nodes_1__2_,index_nodes_1__1_,
index_nodes_1__0_,N31,N32,N33,N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,
N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,N58,N59,N60,N61;
wire [62:0] sel_nodes;
assign cnt_o[5] = ~sel_nodes[1];
assign cnt_o[4:0] = (N0)? { index_nodes_1__4_, index_nodes_1__3_, index_nodes_1__2_, index_nodes_1__1_, index_nodes_1__0_ } :
(N31)? { index_nodes_2__4_, index_nodes_2__3_, index_nodes_2__2_, index_nodes_2__1_, index_nodes_2__0_ } : 1'b0;
assign N0 = sel_nodes[1];
assign index_nodes_1__4_ = ~sel_nodes[3];
assign { index_nodes_1__3_, index_nodes_1__2_, index_nodes_1__1_, index_nodes_1__0_ } = (N1)? { index_nodes_3__3_, index_nodes_3__2_, index_nodes_3__1_, index_nodes_3__0_ } :
(N32)? { index_nodes_4__3_, index_nodes_4__2_, index_nodes_4__1_, index_nodes_4__0_ } : 1'b0;
assign N1 = sel_nodes[3];
assign index_nodes_2__4_ = ~sel_nodes[5];
assign { index_nodes_2__3_, index_nodes_2__2_, index_nodes_2__1_, index_nodes_2__0_ } = (N2)? { index_nodes_5__3_, index_nodes_5__2_, index_nodes_5__1_, index_nodes_5__0_ } :
(N33)? { index_nodes_6__3_, index_nodes_6__2_, index_nodes_6__1_, index_nodes_6__0_ } : 1'b0;
assign N2 = sel_nodes[5];
assign index_nodes_3__3_ = ~sel_nodes[7];
assign { index_nodes_3__2_, index_nodes_3__1_, index_nodes_3__0_ } = (N3)? { index_nodes_7__2_, index_nodes_7__1_, index_nodes_7__0_ } :
(N34)? { index_nodes_8__2_, index_nodes_8__1_, index_nodes_8__0_ } : 1'b0;
assign N3 = sel_nodes[7];
assign index_nodes_4__3_ = ~sel_nodes[9];
assign { index_nodes_4__2_, index_nodes_4__1_, index_nodes_4__0_ } = (N4)? { index_nodes_9__2_, index_nodes_9__1_, index_nodes_9__0_ } :
(N35)? { index_nodes_10__2_, index_nodes_10__1_, index_nodes_10__0_ } : 1'b0;
assign N4 = sel_nodes[9];
assign index_nodes_5__3_ = ~sel_nodes[11];
assign { index_nodes_5__2_, index_nodes_5__1_, index_nodes_5__0_ } = (N5)? { index_nodes_11__2_, index_nodes_11__1_, index_nodes_11__0_ } :
(N36)? { index_nodes_12__2_, index_nodes_12__1_, index_nodes_12__0_ } : 1'b0;
assign N5 = sel_nodes[11];
assign index_nodes_6__3_ = ~sel_nodes[13];
assign { index_nodes_6__2_, index_nodes_6__1_, index_nodes_6__0_ } = (N6)? { index_nodes_13__2_, index_nodes_13__1_, index_nodes_13__0_ } :
(N37)? { index_nodes_14__2_, index_nodes_14__1_, index_nodes_14__0_ } : 1'b0;
assign N6 = sel_nodes[13];
assign index_nodes_7__2_ = ~sel_nodes[15];
assign { index_nodes_7__1_, index_nodes_7__0_ } = (N7)? { index_nodes_15__1_, index_nodes_15__0_ } :
(N38)? { index_nodes_16__1_, index_nodes_16__0_ } : 1'b0;
assign N7 = sel_nodes[15];
assign index_nodes_8__2_ = ~sel_nodes[17];
assign { index_nodes_8__1_, index_nodes_8__0_ } = (N8)? { index_nodes_17__1_, index_nodes_17__0_ } :
(N39)? { index_nodes_18__1_, index_nodes_18__0_ } : 1'b0;
assign N8 = sel_nodes[17];
assign index_nodes_9__2_ = ~sel_nodes[19];
assign { index_nodes_9__1_, index_nodes_9__0_ } = (N9)? { index_nodes_19__1_, index_nodes_19__0_ } :
(N40)? { index_nodes_20__1_, index_nodes_20__0_ } : 1'b0;
assign N9 = sel_nodes[19];
assign index_nodes_10__2_ = ~sel_nodes[21];
assign { index_nodes_10__1_, index_nodes_10__0_ } = (N10)? { index_nodes_21__1_, index_nodes_21__0_ } :
(N41)? { index_nodes_22__1_, index_nodes_22__0_ } : 1'b0;
assign N10 = sel_nodes[21];
assign index_nodes_11__2_ = ~sel_nodes[23];
assign { index_nodes_11__1_, index_nodes_11__0_ } = (N11)? { index_nodes_23__1_, index_nodes_23__0_ } :
(N42)? { index_nodes_24__1_, index_nodes_24__0_ } : 1'b0;
assign N11 = sel_nodes[23];
assign index_nodes_12__2_ = ~sel_nodes[25];
assign { index_nodes_12__1_, index_nodes_12__0_ } = (N12)? { index_nodes_25__1_, index_nodes_25__0_ } :
(N43)? { index_nodes_26__1_, index_nodes_26__0_ } : 1'b0;
assign N12 = sel_nodes[25];
assign index_nodes_13__2_ = ~sel_nodes[27];
assign { index_nodes_13__1_, index_nodes_13__0_ } = (N13)? { index_nodes_27__1_, index_nodes_27__0_ } :
(N44)? { index_nodes_28__1_, index_nodes_28__0_ } : 1'b0;
assign N13 = sel_nodes[27];
assign index_nodes_14__2_ = ~sel_nodes[29];
assign { index_nodes_14__1_, index_nodes_14__0_ } = (N14)? { index_nodes_29__1_, index_nodes_29__0_ } :
(N45)? { index_nodes_30__1_, index_nodes_30__0_ } : 1'b0;
assign N14 = sel_nodes[29];
assign index_nodes_15__1_ = ~sel_nodes[31];
assign index_nodes_15__0_ = (N15)? index_nodes_31__0_ :
(N46)? index_nodes_32__0_ : 1'b0;
assign N15 = sel_nodes[31];
assign index_nodes_16__1_ = ~sel_nodes[33];
assign index_nodes_16__0_ = (N16)? index_nodes_33__0_ :
(N47)? index_nodes_34__0_ : 1'b0;
assign N16 = sel_nodes[33];
assign index_nodes_17__1_ = ~sel_nodes[35];
assign index_nodes_17__0_ = (N17)? index_nodes_35__0_ :
(N48)? index_nodes_36__0_ : 1'b0;
assign N17 = sel_nodes[35];
assign index_nodes_18__1_ = ~sel_nodes[37];
assign index_nodes_18__0_ = (N18)? index_nodes_37__0_ :
(N49)? index_nodes_38__0_ : 1'b0;
assign N18 = sel_nodes[37];
assign index_nodes_19__1_ = ~sel_nodes[39];
assign index_nodes_19__0_ = (N19)? index_nodes_39__0_ :
(N50)? index_nodes_40__0_ : 1'b0;
assign N19 = sel_nodes[39];
assign index_nodes_20__1_ = ~sel_nodes[41];
assign index_nodes_20__0_ = (N20)? index_nodes_41__0_ :
(N51)? index_nodes_42__0_ : 1'b0;
assign N20 = sel_nodes[41];
assign index_nodes_21__1_ = ~sel_nodes[43];
assign index_nodes_21__0_ = (N21)? index_nodes_43__0_ :
(N52)? index_nodes_44__0_ : 1'b0;
assign N21 = sel_nodes[43];
assign index_nodes_22__1_ = ~sel_nodes[45];
assign index_nodes_22__0_ = (N22)? index_nodes_45__0_ :
(N53)? index_nodes_46__0_ : 1'b0;
assign N22 = sel_nodes[45];
assign index_nodes_23__1_ = ~sel_nodes[47];
assign index_nodes_23__0_ = (N23)? index_nodes_47__0_ :
(N54)? index_nodes_48__0_ : 1'b0;
assign N23 = sel_nodes[47];
assign index_nodes_24__1_ = ~sel_nodes[49];
assign index_nodes_24__0_ = (N24)? index_nodes_49__0_ :
(N55)? index_nodes_50__0_ : 1'b0;
assign N24 = sel_nodes[49];
assign index_nodes_25__1_ = ~sel_nodes[51];
assign index_nodes_25__0_ = (N25)? index_nodes_51__0_ :
(N56)? index_nodes_52__0_ : 1'b0;
assign N25 = sel_nodes[51];
assign index_nodes_26__1_ = ~sel_nodes[53];
assign index_nodes_26__0_ = (N26)? index_nodes_53__0_ :
(N57)? index_nodes_54__0_ : 1'b0;
assign N26 = sel_nodes[53];
assign index_nodes_27__1_ = ~sel_nodes[55];
assign index_nodes_27__0_ = (N27)? index_nodes_55__0_ :
(N58)? index_nodes_56__0_ : 1'b0;
assign N27 = sel_nodes[55];
assign index_nodes_28__1_ = ~sel_nodes[57];
assign index_nodes_28__0_ = (N28)? index_nodes_57__0_ :
(N59)? index_nodes_58__0_ : 1'b0;
assign N28 = sel_nodes[57];
assign index_nodes_29__1_ = ~sel_nodes[59];
assign index_nodes_29__0_ = (N29)? index_nodes_59__0_ :
(N60)? index_nodes_60__0_ : 1'b0;
assign N29 = sel_nodes[59];
assign index_nodes_30__1_ = ~sel_nodes[61];
assign index_nodes_30__0_ = (N30)? index_nodes_61__0_ :
(N61)? index_nodes_62__0_ : 1'b0;
assign N30 = sel_nodes[61];
assign index_nodes_31__0_ = ~in_i[63];
assign index_nodes_32__0_ = ~in_i[61];
assign index_nodes_33__0_ = ~in_i[59];
assign index_nodes_34__0_ = ~in_i[57];
assign index_nodes_35__0_ = ~in_i[55];
assign index_nodes_36__0_ = ~in_i[53];
assign index_nodes_37__0_ = ~in_i[51];
assign index_nodes_38__0_ = ~in_i[49];
assign index_nodes_39__0_ = ~in_i[47];
assign index_nodes_40__0_ = ~in_i[45];
assign index_nodes_41__0_ = ~in_i[43];
assign index_nodes_42__0_ = ~in_i[41];
assign index_nodes_43__0_ = ~in_i[39];
assign index_nodes_44__0_ = ~in_i[37];
assign index_nodes_45__0_ = ~in_i[35];
assign index_nodes_46__0_ = ~in_i[33];
assign index_nodes_47__0_ = ~in_i[31];
assign index_nodes_48__0_ = ~in_i[29];
assign index_nodes_49__0_ = ~in_i[27];
assign index_nodes_50__0_ = ~in_i[25];
assign index_nodes_51__0_ = ~in_i[23];
assign index_nodes_52__0_ = ~in_i[21];
assign index_nodes_53__0_ = ~in_i[19];
assign index_nodes_54__0_ = ~in_i[17];
assign index_nodes_55__0_ = ~in_i[15];
assign index_nodes_56__0_ = ~in_i[13];
assign index_nodes_57__0_ = ~in_i[11];
assign index_nodes_58__0_ = ~in_i[9];
assign index_nodes_59__0_ = ~in_i[7];
assign index_nodes_60__0_ = ~in_i[5];
assign index_nodes_61__0_ = ~in_i[3];
assign index_nodes_62__0_ = ~in_i[1];
assign sel_nodes[0] = sel_nodes[1] | sel_nodes[2];
assign N31 = ~sel_nodes[1];
assign sel_nodes[1] = sel_nodes[3] | sel_nodes[4];
assign N32 = ~sel_nodes[3];
assign sel_nodes[2] = sel_nodes[5] | sel_nodes[6];
assign N33 = ~sel_nodes[5];
assign sel_nodes[3] = sel_nodes[7] | sel_nodes[8];
assign N34 = ~sel_nodes[7];
assign sel_nodes[4] = sel_nodes[9] | sel_nodes[10];
assign N35 = ~sel_nodes[9];
assign sel_nodes[5] = sel_nodes[11] | sel_nodes[12];
assign N36 = ~sel_nodes[11];
assign sel_nodes[6] = sel_nodes[13] | sel_nodes[14];
assign N37 = ~sel_nodes[13];
assign sel_nodes[7] = sel_nodes[15] | sel_nodes[16];
assign N38 = ~sel_nodes[15];
assign sel_nodes[8] = sel_nodes[17] | sel_nodes[18];
assign N39 = ~sel_nodes[17];
assign sel_nodes[9] = sel_nodes[19] | sel_nodes[20];
assign N40 = ~sel_nodes[19];
assign sel_nodes[10] = sel_nodes[21] | sel_nodes[22];
assign N41 = ~sel_nodes[21];
assign sel_nodes[11] = sel_nodes[23] | sel_nodes[24];
assign N42 = ~sel_nodes[23];
assign sel_nodes[12] = sel_nodes[25] | sel_nodes[26];
assign N43 = ~sel_nodes[25];
assign sel_nodes[13] = sel_nodes[27] | sel_nodes[28];
assign N44 = ~sel_nodes[27];
assign sel_nodes[14] = sel_nodes[29] | sel_nodes[30];
assign N45 = ~sel_nodes[29];
assign sel_nodes[15] = sel_nodes[31] | sel_nodes[32];
assign N46 = ~sel_nodes[31];
assign sel_nodes[16] = sel_nodes[33] | sel_nodes[34];
assign N47 = ~sel_nodes[33];
assign sel_nodes[17] = sel_nodes[35] | sel_nodes[36];
assign N48 = ~sel_nodes[35];
assign sel_nodes[18] = sel_nodes[37] | sel_nodes[38];
assign N49 = ~sel_nodes[37];
assign sel_nodes[19] = sel_nodes[39] | sel_nodes[40];
assign N50 = ~sel_nodes[39];
assign sel_nodes[20] = sel_nodes[41] | sel_nodes[42];
assign N51 = ~sel_nodes[41];
assign sel_nodes[21] = sel_nodes[43] | sel_nodes[44];
assign N52 = ~sel_nodes[43];
assign sel_nodes[22] = sel_nodes[45] | sel_nodes[46];
assign N53 = ~sel_nodes[45];
assign sel_nodes[23] = sel_nodes[47] | sel_nodes[48];
assign N54 = ~sel_nodes[47];
assign sel_nodes[24] = sel_nodes[49] | sel_nodes[50];
assign N55 = ~sel_nodes[49];
assign sel_nodes[25] = sel_nodes[51] | sel_nodes[52];
assign N56 = ~sel_nodes[51];
assign sel_nodes[26] = sel_nodes[53] | sel_nodes[54];
assign N57 = ~sel_nodes[53];
assign sel_nodes[27] = sel_nodes[55] | sel_nodes[56];
assign N58 = ~sel_nodes[55];
assign sel_nodes[28] = sel_nodes[57] | sel_nodes[58];
assign N59 = ~sel_nodes[57];
assign sel_nodes[29] = sel_nodes[59] | sel_nodes[60];
assign N60 = ~sel_nodes[59];
assign sel_nodes[30] = sel_nodes[61] | sel_nodes[62];
assign N61 = ~sel_nodes[61];
assign sel_nodes[31] = in_i[63] | in_i[62];
assign sel_nodes[32] = in_i[61] | in_i[60];
assign sel_nodes[33] = in_i[59] | in_i[58];
assign sel_nodes[34] = in_i[57] | in_i[56];
assign sel_nodes[35] = in_i[55] | in_i[54];
assign sel_nodes[36] = in_i[53] | in_i[52];
assign sel_nodes[37] = in_i[51] | in_i[50];
assign sel_nodes[38] = in_i[49] | in_i[48];
assign sel_nodes[39] = in_i[47] | in_i[46];
assign sel_nodes[40] = in_i[45] | in_i[44];
assign sel_nodes[41] = in_i[43] | in_i[42];
assign sel_nodes[42] = in_i[41] | in_i[40];
assign sel_nodes[43] = in_i[39] | in_i[38];
assign sel_nodes[44] = in_i[37] | in_i[36];
assign sel_nodes[45] = in_i[35] | in_i[34];
assign sel_nodes[46] = in_i[33] | in_i[32];
assign sel_nodes[47] = in_i[31] | in_i[30];
assign sel_nodes[48] = in_i[29] | in_i[28];
assign sel_nodes[49] = in_i[27] | in_i[26];
assign sel_nodes[50] = in_i[25] | in_i[24];
assign sel_nodes[51] = in_i[23] | in_i[22];
assign sel_nodes[52] = in_i[21] | in_i[20];
assign sel_nodes[53] = in_i[19] | in_i[18];
assign sel_nodes[54] = in_i[17] | in_i[16];
assign sel_nodes[55] = in_i[15] | in_i[14];
assign sel_nodes[56] = in_i[13] | in_i[12];
assign sel_nodes[57] = in_i[11] | in_i[10];
assign sel_nodes[58] = in_i[9] | in_i[8];
assign sel_nodes[59] = in_i[7] | in_i[6];
assign sel_nodes[60] = in_i[5] | in_i[4];
assign sel_nodes[61] = in_i[3] | in_i[2];
assign sel_nodes[62] = in_i[1] | in_i[0];
assign empty_o = ~sel_nodes[0];
endmodule |
module lzc_00000003
(
in_i,
cnt_o,
empty_o
);
input [2:0] in_i;
output [1:0] cnt_o;
output empty_o;
wire [1:0] cnt_o,sel_nodes;
wire empty_o,N0,index_nodes_1__0_,N1;
assign cnt_o[1] = ~sel_nodes[1];
assign cnt_o[0] = (N0)? index_nodes_1__0_ :
(N1)? 1'b0 : 1'b0;
assign N0 = sel_nodes[1];
assign index_nodes_1__0_ = ~in_i[0];
assign sel_nodes[0] = sel_nodes[1] | in_i[2];
assign N1 = ~sel_nodes[1];
assign sel_nodes[1] = in_i[0] | in_i[1];
assign empty_o = ~sel_nodes[0];
endmodule |
module lzc_00000004
(
in_i,
cnt_o,
empty_o
);
input [3:0] in_i;
output [1:0] cnt_o;
output empty_o;
wire [1:0] cnt_o;
wire empty_o,N0,index_nodes_2__0_,index_nodes_1__0_,N1;
wire [2:0] sel_nodes;
assign cnt_o[1] = ~sel_nodes[1];
assign cnt_o[0] = (N0)? index_nodes_1__0_ :
(N1)? index_nodes_2__0_ : 1'b0;
assign N0 = sel_nodes[1];
assign index_nodes_1__0_ = ~in_i[0];
assign index_nodes_2__0_ = ~in_i[2];
assign sel_nodes[0] = sel_nodes[1] | sel_nodes[2];
assign N1 = ~sel_nodes[1];
assign sel_nodes[1] = in_i[0] | in_i[1];
assign sel_nodes[2] = in_i[2] | in_i[3];
assign empty_o = ~sel_nodes[0];
endmodule |
module pipe_reg_simple_Depth0
(
clk_i,
rst_ni,
d_i,
d_o
);
input [196:0] d_i;
output [196:0] d_o;
input clk_i;
input rst_ni;
wire [196:0] d_o;
assign d_o[196] = d_i[196];
assign d_o[195] = d_i[195];
assign d_o[194] = d_i[194];
assign d_o[193] = d_i[193];
assign d_o[192] = d_i[192];
assign d_o[191] = d_i[191];
assign d_o[190] = d_i[190];
assign d_o[189] = d_i[189];
assign d_o[188] = d_i[188];
assign d_o[187] = d_i[187];
assign d_o[186] = d_i[186];
assign d_o[185] = d_i[185];
assign d_o[184] = d_i[184];
assign d_o[183] = d_i[183];
assign d_o[182] = d_i[182];
assign d_o[181] = d_i[181];
assign d_o[180] = d_i[180];
assign d_o[179] = d_i[179];
assign d_o[178] = d_i[178];
assign d_o[177] = d_i[177];
assign d_o[176] = d_i[176];
assign d_o[175] = d_i[175];
assign d_o[174] = d_i[174];
assign d_o[173] = d_i[173];
assign d_o[172] = d_i[172];
assign d_o[171] = d_i[171];
assign d_o[170] = d_i[170];
assign d_o[169] = d_i[169];
assign d_o[168] = d_i[168];
assign d_o[167] = d_i[167];
assign d_o[166] = d_i[166];
assign d_o[165] = d_i[165];
assign d_o[164] = d_i[164];
assign d_o[163] = d_i[163];
assign d_o[162] = d_i[162];
assign d_o[161] = d_i[161];
assign d_o[160] = d_i[160];
assign d_o[159] = d_i[159];
assign d_o[158] = d_i[158];
assign d_o[157] = d_i[157];
assign d_o[156] = d_i[156];
assign d_o[155] = d_i[155];
assign d_o[154] = d_i[154];
assign d_o[153] = d_i[153];
assign d_o[152] = d_i[152];
assign d_o[151] = d_i[151];
assign d_o[150] = d_i[150];
assign d_o[149] = d_i[149];
assign d_o[148] = d_i[148];
assign d_o[147] = d_i[147];
assign d_o[146] = d_i[146];
assign d_o[145] = d_i[145];
assign d_o[144] = d_i[144];
assign d_o[143] = d_i[143];
assign d_o[142] = d_i[142];
assign d_o[141] = d_i[141];
assign d_o[140] = d_i[140];
assign d_o[139] = d_i[139];
assign d_o[138] = d_i[138];
assign d_o[137] = d_i[137];
assign d_o[136] = d_i[136];
assign d_o[135] = d_i[135];
assign d_o[134] = d_i[134];
assign d_o[133] = d_i[133];
assign d_o[132] = d_i[132];
assign d_o[131] = d_i[131];
assign d_o[130] = d_i[130];
assign d_o[129] = d_i[129];
assign d_o[128] = d_i[128];
assign d_o[127] = d_i[127];
assign d_o[126] = d_i[126];
assign d_o[125] = d_i[125];
assign d_o[124] = d_i[124];
assign d_o[123] = d_i[123];
assign d_o[122] = d_i[122];
assign d_o[121] = d_i[121];
assign d_o[120] = d_i[120];
assign d_o[119] = d_i[119];
assign d_o[118] = d_i[118];
assign d_o[117] = d_i[117];
assign d_o[116] = d_i[116];
assign d_o[115] = d_i[115];
assign d_o[114] = d_i[114];
assign d_o[113] = d_i[113];
assign d_o[112] = d_i[112];
assign d_o[111] = d_i[111];
assign d_o[110] = d_i[110];
assign d_o[109] = d_i[109];
assign d_o[108] = d_i[108];
assign d_o[107] = d_i[107];
assign d_o[106] = d_i[106];
assign d_o[105] = d_i[105];
assign d_o[104] = d_i[104];
assign d_o[103] = d_i[103];
assign d_o[102] = d_i[102];
assign d_o[101] = d_i[101];
assign d_o[100] = d_i[100];
assign d_o[99] = d_i[99];
assign d_o[98] = d_i[98];
assign d_o[97] = d_i[97];
assign d_o[96] = d_i[96];
assign d_o[95] = d_i[95];
assign d_o[94] = d_i[94];
assign d_o[93] = d_i[93];
assign d_o[92] = d_i[92];
assign d_o[91] = d_i[91];
assign d_o[90] = d_i[90];
assign d_o[89] = d_i[89];
assign d_o[88] = d_i[88];
assign d_o[87] = d_i[87];
assign d_o[86] = d_i[86];
assign d_o[85] = d_i[85];
assign d_o[84] = d_i[84];
assign d_o[83] = d_i[83];
assign d_o[82] = d_i[82];
assign d_o[81] = d_i[81];
assign d_o[80] = d_i[80];
assign d_o[79] = d_i[79];
assign d_o[78] = d_i[78];
assign d_o[77] = d_i[77];
assign d_o[76] = d_i[76];
assign d_o[75] = d_i[75];
assign d_o[74] = d_i[74];
assign d_o[73] = d_i[73];
assign d_o[72] = d_i[72];
assign d_o[71] = d_i[71];
assign d_o[70] = d_i[70];
assign d_o[69] = d_i[69];
assign d_o[68] = d_i[68];
assign d_o[67] = d_i[67];
assign d_o[66] = d_i[66];
assign d_o[65] = d_i[65];
assign d_o[64] = d_i[64];
assign d_o[63] = d_i[63];
assign d_o[62] = d_i[62];
assign d_o[61] = d_i[61];
assign d_o[60] = d_i[60];
assign d_o[59] = d_i[59];
assign d_o[58] = d_i[58];
assign d_o[57] = d_i[57];
assign d_o[56] = d_i[56];
assign d_o[55] = d_i[55];
assign d_o[54] = d_i[54];
assign d_o[53] = d_i[53];
assign d_o[52] = d_i[52];
assign d_o[51] = d_i[51];
assign d_o[50] = d_i[50];
assign d_o[49] = d_i[49];
assign d_o[48] = d_i[48];
assign d_o[47] = d_i[47];
assign d_o[46] = d_i[46];
assign d_o[45] = d_i[45];
assign d_o[44] = d_i[44];
assign d_o[43] = d_i[43];
assign d_o[42] = d_i[42];
assign d_o[41] = d_i[41];
assign d_o[40] = d_i[40];
assign d_o[39] = d_i[39];
assign d_o[38] = d_i[38];
assign d_o[37] = d_i[37];
assign d_o[36] = d_i[36];
assign d_o[35] = d_i[35];
assign d_o[34] = d_i[34];
assign d_o[33] = d_i[33];
assign d_o[32] = d_i[32];
assign d_o[31] = d_i[31];
assign d_o[30] = d_i[30];
assign d_o[29] = d_i[29];
assign d_o[28] = d_i[28];
assign d_o[27] = d_i[27];
assign d_o[26] = d_i[26];
assign d_o[25] = d_i[25];
assign d_o[24] = d_i[24];
assign d_o[23] = d_i[23];
assign d_o[22] = d_i[22];
assign d_o[21] = d_i[21];
assign d_o[20] = d_i[20];
assign d_o[19] = d_i[19];
assign d_o[18] = d_i[18];
assign d_o[17] = d_i[17];
assign d_o[16] = d_i[16];
assign d_o[15] = d_i[15];
assign d_o[14] = d_i[14];
assign d_o[13] = d_i[13];
assign d_o[12] = d_i[12];
assign d_o[11] = d_i[11];
assign d_o[10] = d_i[10];
assign d_o[9] = d_i[9];
assign d_o[8] = d_i[8];
assign d_o[7] = d_i[7];
assign d_o[6] = d_i[6];
assign d_o[5] = d_i[5];
assign d_o[4] = d_i[4];
assign d_o[3] = d_i[3];
assign d_o[2] = d_i[2];
assign d_o[1] = d_i[1];
assign d_o[0] = d_i[0];
endmodule |
module lfsr_8bit_00000008
(
clk_i,
rst_ni,
en_i,
refill_way_oh,
refill_way_bin
);
output [7:0] refill_way_oh;
output [2:0] refill_way_bin;
input clk_i;
input rst_ni;
input en_i;
wire [7:0] refill_way_oh;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,N18,N19,N20,N21,
N22,N23,N24;
reg [7:3] shift_q;
reg [2:0] refill_way_bin;
always @(posedge clk_i or posedge N13) begin
if(N13) begin
shift_q[7] <= 1'b0;
end else if(en_i) begin
shift_q[7] <= shift_q[6];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
shift_q[6] <= 1'b0;
end else if(en_i) begin
shift_q[6] <= shift_q[5];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
shift_q[5] <= 1'b0;
end else if(en_i) begin
shift_q[5] <= shift_q[4];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
shift_q[4] <= 1'b0;
end else if(en_i) begin
shift_q[4] <= shift_q[3];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
shift_q[3] <= 1'b0;
end else if(en_i) begin
shift_q[3] <= refill_way_bin[2];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
refill_way_bin[2] <= 1'b0;
end else if(en_i) begin
refill_way_bin[2] <= refill_way_bin[1];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
refill_way_bin[1] <= 1'b0;
end else if(en_i) begin
refill_way_bin[1] <= refill_way_bin[0];
end
end
always @(posedge clk_i or posedge N13) begin
if(N13) begin
refill_way_bin[0] <= 1'b0;
end else if(en_i) begin
refill_way_bin[0] <= N12;
end
end
assign N14 = refill_way_bin[0] & refill_way_bin[1];
assign refill_way_oh[7] = N14 & refill_way_bin[2];
assign N15 = N0 & refill_way_bin[1];
assign N0 = ~refill_way_bin[0];
assign refill_way_oh[6] = N15 & refill_way_bin[2];
assign N16 = refill_way_bin[0] & N1;
assign N1 = ~refill_way_bin[1];
assign refill_way_oh[5] = N16 & refill_way_bin[2];
assign N17 = N2 & N3;
assign N2 = ~refill_way_bin[0];
assign N3 = ~refill_way_bin[1];
assign refill_way_oh[4] = N17 & refill_way_bin[2];
assign N18 = refill_way_bin[0] & refill_way_bin[1];
assign refill_way_oh[3] = N18 & N4;
assign N4 = ~refill_way_bin[2];
assign N19 = N5 & refill_way_bin[1];
assign N5 = ~refill_way_bin[0];
assign refill_way_oh[2] = N19 & N6;
assign N6 = ~refill_way_bin[2];
assign N20 = refill_way_bin[0] & N7;
assign N7 = ~refill_way_bin[1];
assign refill_way_oh[1] = N20 & N8;
assign N8 = ~refill_way_bin[2];
assign N21 = N9 & N10;
assign N9 = ~refill_way_bin[0];
assign N10 = ~refill_way_bin[1];
assign refill_way_oh[0] = N21 & N11;
assign N11 = ~refill_way_bin[2];
assign N12 = ~N24;
assign N24 = N23 ^ refill_way_bin[1];
assign N23 = N22 ^ refill_way_bin[2];
assign N22 = shift_q[7] ^ shift_q[3];
assign N13 = ~rst_ni;
endmodule |
module compressed_decoder
(
instr_i,
instr_o,
illegal_instr_o,
is_compressed_o
);
input [31:0] instr_i;
output [31:0] instr_o;
output illegal_instr_o;
output is_compressed_o;
wire [31:0] instr_o;
wire illegal_instr_o,is_compressed_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,
N14,N15,N16,N17,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,
N34,N35,N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,
N54,N55,N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,
N74,N75,N76,N77,N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,
N94,N95,N96,N97,N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,
N111,N112,N113,N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,
N127,N128,N129,N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,
N143,N144,N145,N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,
N159,N160,N161,N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,
N175,N176,N177,N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,
N191,N192,N193,N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,
N207,N208,N209,N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,
N223,N224,N225,N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,
N239,N240,N241,N242,N243,N244,N245,N246,N247,N248,N249,N250,N251,N252,N253,N254,
N255,N256,N257,N258,N259,N260,N261,N262,N263,N264,N265,N266,N267,N268,N269,N270,
N271,N272,N273,N274,N275,N276,N277,N278,N279,N280,N281,N282,N283,N284,N285,N286,
N287,N288,N289,N290,N291,N292,N293,N294,N295,N296,N297,N298,N299,N300,N301,N302,
N303,N304,N305,N306,N307,N308,N309,N310,N311,N312,N313,N314,N315,N316,N317,N318,
N319,N320,N321,N322,N323,N324,N325,N326,N327,N328,N329,N330,N331,N332,N333,N334,
N335,N336,N337,N338,N339,N340,N341,N342,N343,N344,N345,N346,N347,N348,N349,N350,
N351,N352,N353,N354,N355,N356,N357,N358,N359,N360,N361,N362,N363,N364,N365,N366,
N367,N368,N369,N370,N371,N372,N373,N374,N375,N376,N377,N378,N379,N380,N381,N382,
N383,N384,N385,N386,N387,N388,N389,N390,N391,N392,N393,N394,N395,N396,N397,N398,
N399,N400,N401,N402,N403,N404,N405,N406,N407,N408,N409,N410,N411,N412,N413,N414,
N415;
assign N36 = N34 & N35;
assign N37 = instr_i[1] | N35;
assign N39 = N34 | instr_i[0];
assign N41 = instr_i[1] & instr_i[0];
assign N44 = N231 & N42;
assign N45 = N44 & N43;
assign N46 = instr_i[15] | instr_i[14];
assign N47 = N46 | N43;
assign N49 = instr_i[15] | N42;
assign N50 = N49 | instr_i[13];
assign N52 = N49 | N43;
assign N54 = N231 | instr_i[14];
assign N55 = N54 | N43;
assign N57 = N231 | N42;
assign N58 = N57 | instr_i[13];
assign N60 = instr_i[15] & instr_i[14];
assign N61 = N60 & instr_i[13];
assign N62 = N54 | instr_i[13];
assign N143 = N141 & N142;
assign N144 = instr_i[11] | N142;
assign N146 = N141 | instr_i[10];
assign N148 = instr_i[11] & instr_i[10];
assign N151 = N413 & N149;
assign N152 = N151 & N150;
assign N153 = instr_i[12] | instr_i[6];
assign N154 = N153 | N150;
assign N156 = instr_i[12] | N149;
assign N157 = N156 | instr_i[5];
assign N159 = N156 | N150;
assign N161 = N413 | instr_i[6];
assign N162 = N161 | instr_i[5];
assign N164 = N161 | N150;
assign N166 = N413 | N149;
assign N167 = N166 | instr_i[5];
assign N168 = instr_i[12] & instr_i[6];
assign N169 = N168 & instr_i[5];
assign N385 = ~instr_i[8];
assign N386 = instr_i[10] | instr_i[11];
assign N387 = instr_i[9] | N386;
assign N388 = N385 | N387;
assign N389 = instr_i[7] | N388;
assign N390 = ~N389;
assign N391 = instr_i[5] | instr_i[6];
assign N392 = instr_i[4] | N391;
assign N393 = instr_i[3] | N392;
assign N394 = instr_i[2] | N393;
assign N395 = ~N394;
assign N396 = instr_i[8] | N387;
assign N397 = instr_i[7] | N396;
assign N398 = ~N397;
assign N399 = instr_i[11] | instr_i[12];
assign N400 = instr_i[10] | N399;
assign N401 = instr_i[9] | N400;
assign N402 = instr_i[8] | N401;
assign N403 = instr_i[7] | N402;
assign N404 = instr_i[6] | N403;
assign N405 = instr_i[5] | N404;
assign N406 = ~N405;
assign N407 = instr_i[6] | instr_i[12];
assign N408 = instr_i[5] | N407;
assign N409 = instr_i[4] | N408;
assign N410 = instr_i[3] | N409;
assign N411 = instr_i[2] | N410;
assign N412 = ~N411;
assign N413 = ~instr_i[12];
assign { N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64 } = (N0)? { 1'b0, 1'b0, instr_i[10:7], instr_i[12:11], instr_i[5:5], instr_i[6:6], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N1)? { 1'b0, 1'b0, 1'b0, 1'b0, instr_i[6:5], instr_i[12:10], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b1, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 } :
(N2)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, instr_i[5:5], instr_i[12:10], instr_i[6:6], 1'b0, 1'b0, 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N3)? { 1'b0, 1'b0, 1'b0, 1'b0, instr_i[6:5], instr_i[12:10], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b1, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N4)? { 1'b0, 1'b0, 1'b0, 1'b0, instr_i[6:5], instr_i[12:12], 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b1, instr_i[11:10], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1 } :
(N5)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, instr_i[5:5], instr_i[12:12], 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b0, instr_i[11:10], instr_i[6:6], 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N6)? { 1'b0, 1'b0, 1'b0, 1'b0, instr_i[6:5], instr_i[12:12], 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b1, 1'b1, instr_i[11:10], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N7)? instr_i : 1'b0;
assign N0 = N45;
assign N1 = N48;
assign N2 = N51;
assign N3 = N53;
assign N4 = N56;
assign N5 = N59;
assign N6 = N61;
assign N7 = N63;
assign N96 = (N0)? N406 :
(N1)? 1'b0 :
(N2)? 1'b0 :
(N3)? 1'b0 :
(N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b0 :
(N7)? 1'b1 : 1'b0;
assign { N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98 } = (N8)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:2], instr_i[11:7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N9)? { instr_i[31:12], instr_i[6:0] } : 1'b0;
assign N8 = N397;
assign N9 = N398;
assign { N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125 } = (N10)? { instr_i[4:3], instr_i[5:5], instr_i[2:2], instr_i[6:6], 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0 } :
(N11)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:2], instr_i[11:7] } : 1'b0;
assign N10 = N390;
assign N11 = N389;
assign { N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171 } = (N12)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N13)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N14)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N15)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N16)? { 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N17)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[4:2], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1 } :
(N18)? { instr_i[31:10], instr_i[6:0] } : 1'b0;
assign N12 = N152;
assign N13 = N155;
assign N14 = N158;
assign N15 = N160;
assign N16 = N163;
assign N17 = N165;
assign N18 = N170;
assign N200 = (N12)? 1'b0 :
(N13)? 1'b0 :
(N14)? 1'b0 :
(N15)? 1'b0 :
(N16)? 1'b0 :
(N17)? 1'b0 :
(N18)? 1'b1 : 1'b0;
assign { N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201 } = (N19)? { 1'b0, instr_i[10:10], 1'b0, 1'b0, 1'b0, 1'b0, instr_i[12:12], instr_i[6:2], 1'b0, 1'b1, instr_i[9:7], 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N20)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:2], 1'b0, 1'b1, instr_i[9:7], 1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N21)? { N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171 } : 1'b0;
assign N19 = N145;
assign N20 = N147;
assign N21 = N148;
assign N230 = (N19)? 1'b0 :
(N20)? 1'b0 :
(N21)? N200 : 1'b0;
assign { N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232 } = (N0)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:2], instr_i[11:7], 1'b0, 1'b0, 1'b0, instr_i[11:7], 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N1)? { N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, instr_i[11:7], N104, N103, N102, N101, N100, N99, N98 } :
(N2)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, instr_i[11:7], 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1 } :
(N3)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], N140, N139, N138, N137, N136, N135, N135, N135, N135, N135, N135, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, 1'b0, N389, 1'b1, 1'b0, N389, 1'b1, 1'b1 } :
(N7)? { N229, N228, N227, N226, N225, N224, N223, N222, N221, N220, N219, N218, N217, N216, N215, N214, N213, N212, N211, N210, N209, N208, instr_i[9:7], N207, N206, N205, N204, N203, N202, N201 } :
(N4)? { instr_i[12:12], instr_i[8:8], instr_i[10:9], instr_i[6:6], instr_i[7:7], instr_i[2:2], instr_i[11:11], instr_i[5:3], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], 1'b0, 1'b0, 1'b0, 1'b0, N231, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1, 1'b1 } :
(N22)? { instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[12:12], instr_i[6:5], instr_i[2:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b0, instr_i[13:13], instr_i[11:10], instr_i[4:3], instr_i[12:12], 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1 } : 1'b0;
assign N22 = N97;
assign N264 = (N0)? 1'b0 :
(N1)? N398 :
(N2)? 1'b0 :
(N3)? N412 :
(N7)? N230 :
(N4)? 1'b0 :
(N22)? 1'b0 : 1'b0;
assign { N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265 } = (N23)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, instr_i[11:7], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N24)? { instr_i[6:2], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, instr_i[11:7] } : 1'b0;
assign N23 = N395;
assign N24 = N394;
assign N280 = (N23)? N398 :
(N24)? 1'b0 : 1'b0;
assign { N303, N302, N301, N300, N299, N292, N291, N290, N289, N288, N287, N286, N285 } = (N25)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0 } :
(N384)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b1 } :
(N284)? { instr_i[6:2], instr_i[11:7], 1'b0, 1'b1, 1'b0 } : 1'b0;
assign N25 = N281;
assign { N298, N297, N296, N295, N294 } = (N25)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 } :
(N293)? instr_i[11:7] :
(N26)? instr_i[11:7] : 1'b0;
assign N26 = 1'b0;
assign { N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, N311, N310, N309, N308, N307, N306, N305, N304 } = (N27)? { N279, N278, N277, N276, N275, N274, N273, N272, N271, N270, N269, N268, N267, N266, N265, N395, N394, N395 } :
(N28)? { N303, N302, N301, N300, N299, N298, N297, N296, N295, N294, N292, N291, N290, N289, N288, N287, N286, N285 } : 1'b0;
assign N27 = N413;
assign N28 = instr_i[12];
assign N322 = (N27)? N280 :
(N28)? 1'b0 : 1'b0;
assign { N348, N347, N346, N345, N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, N334, N333, N329, N328, N327, N326, N325, N324, N323 } = (N0)? { 1'b0, 1'b0, 1'b0, instr_i[12:12], instr_i[6:2], instr_i[11:7], 1'b0, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b1, 1'b0 } :
(N1)? { instr_i[4:2], instr_i[12:12], instr_i[6:5], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b1 } :
(N2)? { 1'b0, instr_i[3:2], instr_i[12:12], instr_i[6:4], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b0 } :
(N3)? { instr_i[4:2], instr_i[12:12], instr_i[6:5], 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, instr_i[9:7], 1'b0, 1'b0, 1'b0, 1'b0 } :
(N7)? { 1'b0, 1'b0, 1'b0, 1'b0, N321, N320, N319, N318, N317, N316, N315, N314, N313, N312, 1'b0, 1'b0, N309, N308, N307, N306, 1'b1, N305, N304 } :
(N4)? { instr_i[9:7], instr_i[12:12], instr_i[6:2], 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1 } :
(N5)? { 1'b0, instr_i[8:7], instr_i[12:12], instr_i[6:2], 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, instr_i[9:9], 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } :
(N6)? { instr_i[9:7], instr_i[12:12], instr_i[6:2], 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0 } : 1'b0;
assign { N332, N331 } = (N7)? { N311, N310 } :
(N330)? instr_i[11:10] : 1'b0;
assign N349 = (N0)? 1'b0 :
(N1)? N398 :
(N2)? N398 :
(N3)? N398 :
(N7)? N322 :
(N4)? 1'b0 :
(N5)? 1'b0 :
(N6)? 1'b0 : 1'b0;
assign { N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350 } = (N29)? { N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79, N78, N77, N76, N75, N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64 } :
(N30)? { N263, N262, N261, N260, N259, N258, N257, N256, N255, N254, N253, N252, N251, N250, N249, N248, N247, N246, N245, N244, N243, N242, N241, N240, N239, N238, N237, N236, N235, N234, N233, N232 } :
(N31)? { 1'b0, 1'b0, 1'b0, N348, N347, N346, N345, N344, N343, N342, N341, N340, N339, N338, N337, N336, N335, 1'b0, N334, N333, N332, N331, N329, N328, N327, N326, N325, N324, 1'b0, N323, 1'b1, 1'b1 } :
(N32)? instr_i : 1'b0;
assign N29 = N36;
assign N30 = N38;
assign N31 = N40;
assign N32 = N41;
assign illegal_instr_o = (N29)? N96 :
(N30)? N264 :
(N31)? N349 :
(N32)? 1'b0 : 1'b0;
assign is_compressed_o = (N29)? 1'b1 :
(N30)? 1'b1 :
(N31)? 1'b1 :
(N32)? 1'b0 : 1'b0;
assign instr_o = (N33)? instr_i :
(N383)? { N381, N380, N379, N378, N377, N376, N375, N374, N373, N372, N371, N370, N369, N368, N367, N366, N365, N364, N363, N362, N361, N360, N359, N358, N357, N356, N355, N354, N353, N352, N351, N350 } : 1'b0;
assign N33 = N382;
assign N34 = ~instr_i[1];
assign N35 = ~instr_i[0];
assign N38 = ~N37;
assign N40 = ~N39;
assign N42 = ~instr_i[14];
assign N43 = ~instr_i[13];
assign N48 = ~N47;
assign N51 = ~N50;
assign N53 = ~N52;
assign N56 = ~N55;
assign N59 = ~N58;
assign N63 = ~N62;
assign N97 = N59 | N61;
assign N141 = ~instr_i[11];
assign N142 = ~instr_i[10];
assign N145 = N143 | N414;
assign N414 = ~N144;
assign N147 = ~N146;
assign N149 = ~instr_i[6];
assign N150 = ~instr_i[5];
assign N155 = ~N154;
assign N158 = ~N157;
assign N160 = ~N159;
assign N163 = ~N162;
assign N165 = ~N164;
assign N170 = N415 | N169;
assign N415 = ~N167;
assign N231 = ~instr_i[15];
assign N281 = N398 & N395;
assign N282 = N397 & N395;
assign N283 = N282 | N281;
assign N284 = ~N283;
assign N293 = ~N281;
assign N330 = N62;
assign N382 = illegal_instr_o & is_compressed_o;
assign N383 = ~N382;
assign N384 = N282 & N293;
endmodule |
module fifo_v3_DATA_WIDTH2_DEPTH4
(
clk_i,
rst_ni,
flush_i,
testmode_i,
full_o,
empty_o,
usage_o,
data_i,
push_i,
data_o,
pop_i
);
output [1:0] usage_o;
input [1:0] data_i;
output [1:0] data_o;
input clk_i;
input rst_ni;
input flush_i;
input testmode_i;
input push_i;
input pop_i;
output full_o;
output empty_o;
wire [1:0] data_o;
wire full_o,empty_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
gate_clock,N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,
N36,N37,N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,
N56,N57,N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N76,
N77,N78,N80,N81;
wire [7:0] mem_n;
reg [2:2] status_cnt_q;
reg [1:0] usage_o,read_pointer_q,write_pointer_q;
reg [7:0] mem_q;
assign data_o[1] = (N14)? mem_q[1] :
(N16)? mem_q[3] :
(N15)? mem_q[5] :
(N17)? mem_q[7] : 1'b0;
assign data_o[0] = (N14)? mem_q[0] :
(N16)? mem_q[2] :
(N15)? mem_q[4] :
(N17)? mem_q[6] : 1'b0;
always @(posedge clk_i or posedge N53) begin
if(N53) begin
status_cnt_q[2] <= 1'b0;
end else if(N68) begin
status_cnt_q[2] <= N61;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
usage_o[1] <= 1'b0;
end else if(N68) begin
usage_o[1] <= N60;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
usage_o[0] <= 1'b0;
end else if(N68) begin
usage_o[0] <= N59;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
read_pointer_q[1] <= 1'b0;
end else if(N70) begin
read_pointer_q[1] <= N56;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
read_pointer_q[0] <= 1'b0;
end else if(N70) begin
read_pointer_q[0] <= N55;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
write_pointer_q[1] <= 1'b0;
end else if(N72) begin
write_pointer_q[1] <= N58;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
write_pointer_q[0] <= 1'b0;
end else if(N72) begin
write_pointer_q[0] <= N57;
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[7] <= 1'b0;
end else if(N62) begin
mem_q[7] <= mem_n[7];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[6] <= 1'b0;
end else if(N62) begin
mem_q[6] <= mem_n[6];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[5] <= 1'b0;
end else if(N62) begin
mem_q[5] <= mem_n[5];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[4] <= 1'b0;
end else if(N62) begin
mem_q[4] <= mem_n[4];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[3] <= 1'b0;
end else if(N62) begin
mem_q[3] <= mem_n[3];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[2] <= 1'b0;
end else if(N62) begin
mem_q[2] <= mem_n[2];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[1] <= 1'b0;
end else if(N62) begin
mem_q[1] <= mem_n[1];
end
end
always @(posedge clk_i or posedge N53) begin
if(N53) begin
mem_q[0] <= 1'b0;
end else if(N62) begin
mem_q[0] <= mem_n[0];
end
end
assign N73 = usage_o[1] | status_cnt_q[2];
assign N74 = usage_o[0] | N73;
assign empty_o = ~N74;
assign N76 = ~status_cnt_q[2];
assign N77 = usage_o[1] | N76;
assign N78 = usage_o[0] | N77;
assign full_o = ~N78;
assign { N44, N43 } = read_pointer_q + 1'b1;
assign { N47, N46, N45 } = { status_cnt_q[2:2], usage_o } - 1'b1;
assign { N37, N36 } = write_pointer_q + 1'b1;
assign { N40, N39, N38 } = { status_cnt_q[2:2], usage_o } + 1'b1;
assign N23 = write_pointer_q[0] & write_pointer_q[1];
assign N22 = N0 & write_pointer_q[1];
assign N0 = ~write_pointer_q[0];
assign N21 = write_pointer_q[0] & N1;
assign N1 = ~write_pointer_q[1];
assign N20 = N2 & N3;
assign N2 = ~write_pointer_q[0];
assign N3 = ~write_pointer_q[1];
assign { N26, N25 } = (N4)? { data_i[0:0], data_i[1:1] } :
(N24)? { mem_q[0:0], mem_q[1:1] } : 1'b0;
assign N4 = N20;
assign { N29, N28 } = (N5)? { data_i[0:0], data_i[1:1] } :
(N27)? { mem_q[2:2], mem_q[3:3] } : 1'b0;
assign N5 = N21;
assign { N32, N31 } = (N6)? { data_i[0:0], data_i[1:1] } :
(N30)? { mem_q[4:4], mem_q[5:5] } : 1'b0;
assign N6 = N22;
assign { N35, N34 } = (N7)? { data_i[0:0], data_i[1:1] } :
(N33)? { mem_q[6:6], mem_q[7:7] } : 1'b0;
assign N7 = N23;
assign mem_n = (N8)? { N34, N35, N31, N32, N28, N29, N25, N26 } :
(N19)? mem_q : 1'b0;
assign N8 = N18;
assign gate_clock = ~N18;
assign { N50, N49, N48 } = (N9)? { N47, N46, N45 } :
(N42)? { N40, N39, N38 } : 1'b0;
assign N9 = N41;
assign { N56, N55 } = (N10)? { 1'b0, 1'b0 } :
(N11)? { N44, N43 } : 1'b0;
assign N10 = flush_i;
assign N11 = N54;
assign { N58, N57 } = (N10)? { 1'b0, 1'b0 } :
(N11)? { N37, N36 } : 1'b0;
assign { N61, N60, N59 } = (N10)? { 1'b0, 1'b0, 1'b0 } :
(N11)? { N50, N49, N48 } : 1'b0;
assign N12 = ~read_pointer_q[0];
assign N13 = ~read_pointer_q[1];
assign N14 = N12 & N13;
assign N15 = N12 & read_pointer_q[1];
assign N16 = read_pointer_q[0] & N13;
assign N17 = read_pointer_q[0] & read_pointer_q[1];
assign N18 = push_i & N78;
assign N19 = ~N18;
assign N24 = ~N20;
assign N27 = ~N21;
assign N30 = ~N22;
assign N33 = ~N23;
assign N41 = pop_i & N74;
assign N42 = ~N41;
assign N51 = N81 & N74;
assign N81 = N80 & N78;
assign N80 = push_i & pop_i;
assign N52 = ~N51;
assign N53 = ~rst_ni;
assign N54 = ~flush_i;
assign N62 = ~gate_clock;
assign N63 = N51 & N54;
assign N64 = N52 & N54;
assign N65 = N42 & N64;
assign N66 = N19 & N65;
assign N67 = N63 | N66;
assign N68 = ~N67;
assign N69 = N42 & N54;
assign N70 = ~N69;
assign N71 = N19 & N54;
assign N72 = ~N71;
endmodule |
module stream_mux_N_INP3
(
inp_data_i,
inp_valid_i,
inp_ready_o,
inp_sel_i,
oup_data_o,
oup_valid_o,
oup_ready_i
);
input [218:0] inp_data_i;
input [2:0] inp_valid_i;
output [2:0] inp_ready_o;
input [1:0] inp_sel_i;
output [72:0] oup_data_o;
input oup_ready_i;
output oup_valid_o;
wire [2:0] inp_ready_o;
wire [72:0] oup_data_o;
wire oup_valid_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14;
assign N10 = N0 & inp_sel_i[1];
assign N0 = ~inp_sel_i[0];
assign N9 = inp_sel_i[0] & N1;
assign N1 = ~inp_sel_i[1];
assign N14 = N2 & N3;
assign N2 = ~inp_sel_i[0];
assign N3 = ~inp_sel_i[1];
assign inp_ready_o[0] = (N4)? oup_ready_i :
(N11)? 1'b0 : 1'b0;
assign N4 = N14;
assign inp_ready_o[1] = (N5)? oup_ready_i :
(N12)? 1'b0 : 1'b0;
assign N5 = N9;
assign inp_ready_o[2] = (N6)? oup_ready_i :
(N13)? 1'b0 : 1'b0;
assign N6 = N10;
assign oup_data_o[72] = (N4)? inp_data_i[72] :
(N7)? inp_data_i[145] :
(N8)? inp_data_i[218] : 1'b0;
assign N7 = inp_sel_i[0];
assign N8 = inp_sel_i[1];
assign oup_data_o[71] = (N4)? inp_data_i[71] :
(N7)? inp_data_i[144] :
(N8)? inp_data_i[217] : 1'b0;
assign oup_data_o[70] = (N4)? inp_data_i[70] :
(N7)? inp_data_i[143] :
(N8)? inp_data_i[216] : 1'b0;
assign oup_data_o[69] = (N4)? inp_data_i[69] :
(N7)? inp_data_i[142] :
(N8)? inp_data_i[215] : 1'b0;
assign oup_data_o[68] = (N4)? inp_data_i[68] :
(N7)? inp_data_i[141] :
(N8)? inp_data_i[214] : 1'b0;
assign oup_data_o[67] = (N4)? inp_data_i[67] :
(N7)? inp_data_i[140] :
(N8)? inp_data_i[213] : 1'b0;
assign oup_data_o[66] = (N4)? inp_data_i[66] :
(N7)? inp_data_i[139] :
(N8)? inp_data_i[212] : 1'b0;
assign oup_data_o[65] = (N4)? inp_data_i[65] :
(N7)? inp_data_i[138] :
(N8)? inp_data_i[211] : 1'b0;
assign oup_data_o[64] = (N4)? inp_data_i[64] :
(N7)? inp_data_i[137] :
(N8)? inp_data_i[210] : 1'b0;
assign oup_data_o[63] = (N4)? inp_data_i[63] :
(N7)? inp_data_i[136] :
(N8)? inp_data_i[209] : 1'b0;
assign oup_data_o[62] = (N4)? inp_data_i[62] :
(N7)? inp_data_i[135] :
(N8)? inp_data_i[208] : 1'b0;
assign oup_data_o[61] = (N4)? inp_data_i[61] :
(N7)? inp_data_i[134] :
(N8)? inp_data_i[207] : 1'b0;
assign oup_data_o[60] = (N4)? inp_data_i[60] :
(N7)? inp_data_i[133] :
(N8)? inp_data_i[206] : 1'b0;
assign oup_data_o[59] = (N4)? inp_data_i[59] :
(N7)? inp_data_i[132] :
(N8)? inp_data_i[205] : 1'b0;
assign oup_data_o[58] = (N4)? inp_data_i[58] :
(N7)? inp_data_i[131] :
(N8)? inp_data_i[204] : 1'b0;
assign oup_data_o[57] = (N4)? inp_data_i[57] :
(N7)? inp_data_i[130] :
(N8)? inp_data_i[203] : 1'b0;
assign oup_data_o[56] = (N4)? inp_data_i[56] :
(N7)? inp_data_i[129] :
(N8)? inp_data_i[202] : 1'b0;
assign oup_data_o[55] = (N4)? inp_data_i[55] :
(N7)? inp_data_i[128] :
(N8)? inp_data_i[201] : 1'b0;
assign oup_data_o[54] = (N4)? inp_data_i[54] :
(N7)? inp_data_i[127] :
(N8)? inp_data_i[200] : 1'b0;
assign oup_data_o[53] = (N4)? inp_data_i[53] :
(N7)? inp_data_i[126] :
(N8)? inp_data_i[199] : 1'b0;
assign oup_data_o[52] = (N4)? inp_data_i[52] :
(N7)? inp_data_i[125] :
(N8)? inp_data_i[198] : 1'b0;
assign oup_data_o[51] = (N4)? inp_data_i[51] :
(N7)? inp_data_i[124] :
(N8)? inp_data_i[197] : 1'b0;
assign oup_data_o[50] = (N4)? inp_data_i[50] :
(N7)? inp_data_i[123] :
(N8)? inp_data_i[196] : 1'b0;
assign oup_data_o[49] = (N4)? inp_data_i[49] :
(N7)? inp_data_i[122] :
(N8)? inp_data_i[195] : 1'b0;
assign oup_data_o[48] = (N4)? inp_data_i[48] :
(N7)? inp_data_i[121] :
(N8)? inp_data_i[194] : 1'b0;
assign oup_data_o[47] = (N4)? inp_data_i[47] :
(N7)? inp_data_i[120] :
(N8)? inp_data_i[193] : 1'b0;
assign oup_data_o[46] = (N4)? inp_data_i[46] :
(N7)? inp_data_i[119] :
(N8)? inp_data_i[192] : 1'b0;
assign oup_data_o[45] = (N4)? inp_data_i[45] :
(N7)? inp_data_i[118] :
(N8)? inp_data_i[191] : 1'b0;
assign oup_data_o[44] = (N4)? inp_data_i[44] :
(N7)? inp_data_i[117] :
(N8)? inp_data_i[190] : 1'b0;
assign oup_data_o[43] = (N4)? inp_data_i[43] :
(N7)? inp_data_i[116] :
(N8)? inp_data_i[189] : 1'b0;
assign oup_data_o[42] = (N4)? inp_data_i[42] :
(N7)? inp_data_i[115] :
(N8)? inp_data_i[188] : 1'b0;
assign oup_data_o[41] = (N4)? inp_data_i[41] :
(N7)? inp_data_i[114] :
(N8)? inp_data_i[187] : 1'b0;
assign oup_data_o[40] = (N4)? inp_data_i[40] :
(N7)? inp_data_i[113] :
(N8)? inp_data_i[186] : 1'b0;
assign oup_data_o[39] = (N4)? inp_data_i[39] :
(N7)? inp_data_i[112] :
(N8)? inp_data_i[185] : 1'b0;
assign oup_data_o[38] = (N4)? inp_data_i[38] :
(N7)? inp_data_i[111] :
(N8)? inp_data_i[184] : 1'b0;
assign oup_data_o[37] = (N4)? inp_data_i[37] :
(N7)? inp_data_i[110] :
(N8)? inp_data_i[183] : 1'b0;
assign oup_data_o[36] = (N4)? inp_data_i[36] :
(N7)? inp_data_i[109] :
(N8)? inp_data_i[182] : 1'b0;
assign oup_data_o[35] = (N4)? inp_data_i[35] :
(N7)? inp_data_i[108] :
(N8)? inp_data_i[181] : 1'b0;
assign oup_data_o[34] = (N4)? inp_data_i[34] :
(N7)? inp_data_i[107] :
(N8)? inp_data_i[180] : 1'b0;
assign oup_data_o[33] = (N4)? inp_data_i[33] :
(N7)? inp_data_i[106] :
(N8)? inp_data_i[179] : 1'b0;
assign oup_data_o[32] = (N4)? inp_data_i[32] :
(N7)? inp_data_i[105] :
(N8)? inp_data_i[178] : 1'b0;
assign oup_data_o[31] = (N4)? inp_data_i[31] :
(N7)? inp_data_i[104] :
(N8)? inp_data_i[177] : 1'b0;
assign oup_data_o[30] = (N4)? inp_data_i[30] :
(N7)? inp_data_i[103] :
(N8)? inp_data_i[176] : 1'b0;
assign oup_data_o[29] = (N4)? inp_data_i[29] :
(N7)? inp_data_i[102] :
(N8)? inp_data_i[175] : 1'b0;
assign oup_data_o[28] = (N4)? inp_data_i[28] :
(N7)? inp_data_i[101] :
(N8)? inp_data_i[174] : 1'b0;
assign oup_data_o[27] = (N4)? inp_data_i[27] :
(N7)? inp_data_i[100] :
(N8)? inp_data_i[173] : 1'b0;
assign oup_data_o[26] = (N4)? inp_data_i[26] :
(N7)? inp_data_i[99] :
(N8)? inp_data_i[172] : 1'b0;
assign oup_data_o[25] = (N4)? inp_data_i[25] :
(N7)? inp_data_i[98] :
(N8)? inp_data_i[171] : 1'b0;
assign oup_data_o[24] = (N4)? inp_data_i[24] :
(N7)? inp_data_i[97] :
(N8)? inp_data_i[170] : 1'b0;
assign oup_data_o[23] = (N4)? inp_data_i[23] :
(N7)? inp_data_i[96] :
(N8)? inp_data_i[169] : 1'b0;
assign oup_data_o[22] = (N4)? inp_data_i[22] :
(N7)? inp_data_i[95] :
(N8)? inp_data_i[168] : 1'b0;
assign oup_data_o[21] = (N4)? inp_data_i[21] :
(N7)? inp_data_i[94] :
(N8)? inp_data_i[167] : 1'b0;
assign oup_data_o[20] = (N4)? inp_data_i[20] :
(N7)? inp_data_i[93] :
(N8)? inp_data_i[166] : 1'b0;
assign oup_data_o[19] = (N4)? inp_data_i[19] :
(N7)? inp_data_i[92] :
(N8)? inp_data_i[165] : 1'b0;
assign oup_data_o[18] = (N4)? inp_data_i[18] :
(N7)? inp_data_i[91] :
(N8)? inp_data_i[164] : 1'b0;
assign oup_data_o[17] = (N4)? inp_data_i[17] :
(N7)? inp_data_i[90] :
(N8)? inp_data_i[163] : 1'b0;
assign oup_data_o[16] = (N4)? inp_data_i[16] :
(N7)? inp_data_i[89] :
(N8)? inp_data_i[162] : 1'b0;
assign oup_data_o[15] = (N4)? inp_data_i[15] :
(N7)? inp_data_i[88] :
(N8)? inp_data_i[161] : 1'b0;
assign oup_data_o[14] = (N4)? inp_data_i[14] :
(N7)? inp_data_i[87] :
(N8)? inp_data_i[160] : 1'b0;
assign oup_data_o[13] = (N4)? inp_data_i[13] :
(N7)? inp_data_i[86] :
(N8)? inp_data_i[159] : 1'b0;
assign oup_data_o[12] = (N4)? inp_data_i[12] :
(N7)? inp_data_i[85] :
(N8)? inp_data_i[158] : 1'b0;
assign oup_data_o[11] = (N4)? inp_data_i[11] :
(N7)? inp_data_i[84] :
(N8)? inp_data_i[157] : 1'b0;
assign oup_data_o[10] = (N4)? inp_data_i[10] :
(N7)? inp_data_i[83] :
(N8)? inp_data_i[156] : 1'b0;
assign oup_data_o[9] = (N4)? inp_data_i[9] :
(N7)? inp_data_i[82] :
(N8)? inp_data_i[155] : 1'b0;
assign oup_data_o[8] = (N4)? inp_data_i[8] :
(N7)? inp_data_i[81] :
(N8)? inp_data_i[154] : 1'b0;
assign oup_data_o[7] = (N4)? inp_data_i[7] :
(N7)? inp_data_i[80] :
(N8)? inp_data_i[153] : 1'b0;
assign oup_data_o[6] = (N4)? inp_data_i[6] :
(N7)? inp_data_i[79] :
(N8)? inp_data_i[152] : 1'b0;
assign oup_data_o[5] = (N4)? inp_data_i[5] :
(N7)? inp_data_i[78] :
(N8)? inp_data_i[151] : 1'b0;
assign oup_data_o[4] = (N4)? inp_data_i[4] :
(N7)? inp_data_i[77] :
(N8)? inp_data_i[150] : 1'b0;
assign oup_data_o[3] = (N4)? inp_data_i[3] :
(N7)? inp_data_i[76] :
(N8)? inp_data_i[149] : 1'b0;
assign oup_data_o[2] = (N4)? inp_data_i[2] :
(N7)? inp_data_i[75] :
(N8)? inp_data_i[148] : 1'b0;
assign oup_data_o[1] = (N4)? inp_data_i[1] :
(N7)? inp_data_i[74] :
(N8)? inp_data_i[147] : 1'b0;
assign oup_data_o[0] = (N4)? inp_data_i[0] :
(N7)? inp_data_i[73] :
(N8)? inp_data_i[146] : 1'b0;
assign oup_valid_o = (N4)? inp_valid_i[0] :
(N7)? inp_valid_i[1] :
(N8)? inp_valid_i[2] : 1'b0;
assign N11 = ~N14;
assign N12 = ~N9;
assign N13 = ~N10;
endmodule |
module csr_buffer
(
clk_i,
rst_ni,
flush_i,
fu_data_i,
csr_ready_o,
csr_valid_i,
csr_result_o,
csr_commit_i,
csr_addr_o
);
input [205:0] fu_data_i;
output [63:0] csr_result_o;
output [11:0] csr_addr_o;
input clk_i;
input rst_ni;
input flush_i;
input csr_valid_i;
input csr_commit_i;
output csr_ready_o;
wire [63:0] csr_result_o;
wire csr_ready_o,N0,N1,csr_reg_n_valid_,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13;
reg [11:0] csr_addr_o;
reg csr_reg_q_valid_;
assign csr_result_o[63] = fu_data_i[194];
assign csr_result_o[62] = fu_data_i[193];
assign csr_result_o[61] = fu_data_i[192];
assign csr_result_o[60] = fu_data_i[191];
assign csr_result_o[59] = fu_data_i[190];
assign csr_result_o[58] = fu_data_i[189];
assign csr_result_o[57] = fu_data_i[188];
assign csr_result_o[56] = fu_data_i[187];
assign csr_result_o[55] = fu_data_i[186];
assign csr_result_o[54] = fu_data_i[185];
assign csr_result_o[53] = fu_data_i[184];
assign csr_result_o[52] = fu_data_i[183];
assign csr_result_o[51] = fu_data_i[182];
assign csr_result_o[50] = fu_data_i[181];
assign csr_result_o[49] = fu_data_i[180];
assign csr_result_o[48] = fu_data_i[179];
assign csr_result_o[47] = fu_data_i[178];
assign csr_result_o[46] = fu_data_i[177];
assign csr_result_o[45] = fu_data_i[176];
assign csr_result_o[44] = fu_data_i[175];
assign csr_result_o[43] = fu_data_i[174];
assign csr_result_o[42] = fu_data_i[173];
assign csr_result_o[41] = fu_data_i[172];
assign csr_result_o[40] = fu_data_i[171];
assign csr_result_o[39] = fu_data_i[170];
assign csr_result_o[38] = fu_data_i[169];
assign csr_result_o[37] = fu_data_i[168];
assign csr_result_o[36] = fu_data_i[167];
assign csr_result_o[35] = fu_data_i[166];
assign csr_result_o[34] = fu_data_i[165];
assign csr_result_o[33] = fu_data_i[164];
assign csr_result_o[32] = fu_data_i[163];
assign csr_result_o[31] = fu_data_i[162];
assign csr_result_o[30] = fu_data_i[161];
assign csr_result_o[29] = fu_data_i[160];
assign csr_result_o[28] = fu_data_i[159];
assign csr_result_o[27] = fu_data_i[158];
assign csr_result_o[26] = fu_data_i[157];
assign csr_result_o[25] = fu_data_i[156];
assign csr_result_o[24] = fu_data_i[155];
assign csr_result_o[23] = fu_data_i[154];
assign csr_result_o[22] = fu_data_i[153];
assign csr_result_o[21] = fu_data_i[152];
assign csr_result_o[20] = fu_data_i[151];
assign csr_result_o[19] = fu_data_i[150];
assign csr_result_o[18] = fu_data_i[149];
assign csr_result_o[17] = fu_data_i[148];
assign csr_result_o[16] = fu_data_i[147];
assign csr_result_o[15] = fu_data_i[146];
assign csr_result_o[14] = fu_data_i[145];
assign csr_result_o[13] = fu_data_i[144];
assign csr_result_o[12] = fu_data_i[143];
assign csr_result_o[11] = fu_data_i[142];
assign csr_result_o[10] = fu_data_i[141];
assign csr_result_o[9] = fu_data_i[140];
assign csr_result_o[8] = fu_data_i[139];
assign csr_result_o[7] = fu_data_i[138];
assign csr_result_o[6] = fu_data_i[137];
assign csr_result_o[5] = fu_data_i[136];
assign csr_result_o[4] = fu_data_i[135];
assign csr_result_o[3] = fu_data_i[134];
assign csr_result_o[2] = fu_data_i[133];
assign csr_result_o[1] = fu_data_i[132];
assign csr_result_o[0] = fu_data_i[131];
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[11] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[11] <= fu_data_i[78];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[10] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[10] <= fu_data_i[77];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[9] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[9] <= fu_data_i[76];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[8] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[8] <= fu_data_i[75];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[7] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[7] <= fu_data_i[74];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[6] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[6] <= fu_data_i[73];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[5] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[5] <= fu_data_i[72];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[4] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[4] <= fu_data_i[71];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[3] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[3] <= fu_data_i[70];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[2] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[2] <= fu_data_i[69];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[1] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[1] <= fu_data_i[68];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_addr_o[0] <= 1'b0;
end else if(csr_valid_i) begin
csr_addr_o[0] <= fu_data_i[67];
end
end
always @(posedge clk_i or posedge N8) begin
if(N8) begin
csr_reg_q_valid_ <= 1'b0;
end else if(N11) begin
csr_reg_q_valid_ <= csr_reg_n_valid_;
end
end
assign csr_ready_o = ~N2;
assign N6 = ~N4;
assign csr_reg_n_valid_ = (N0)? 1'b0 :
(N1)? N6 : 1'b0;
assign N0 = flush_i;
assign N1 = N7;
assign N2 = N12 & N13;
assign N12 = csr_reg_q_valid_ | csr_valid_i;
assign N13 = ~csr_commit_i;
assign N3 = ~csr_valid_i;
assign N4 = csr_commit_i & N3;
assign N5 = ~N4;
assign N7 = ~flush_i;
assign N8 = ~rst_ni;
assign N9 = N5 & N7;
assign N10 = N3 & N9;
assign N11 = ~N10;
endmodule |
module branch_unit
(
fu_data_i,
pc_i,
is_compressed_instr_i,
fu_valid_i,
branch_valid_i,
branch_comp_res_i,
branch_result_o,
branch_predict_i,
resolved_branch_o,
resolve_branch_o,
branch_exception_o
);
input [205:0] fu_data_i;
input [63:0] pc_i;
output [63:0] branch_result_o;
input [67:0] branch_predict_i;
output [133:0] resolved_branch_o;
output [128:0] branch_exception_o;
input is_compressed_instr_i;
input fu_valid_i;
input branch_valid_i;
input branch_comp_res_i;
output resolve_branch_o;
wire [63:0] branch_result_o,target_address;
wire [133:0] resolved_branch_o;
wire [128:0] branch_exception_o;
wire resolve_branch_o,N0,N1,N2,N3,N4,N5,N6,N7,N8,N9,N10,N11,N12,N13,N14,N15,N16,N17,
N18,N19,N20,N21,N22,N23,N24,N25,N26,N27,N28,N29,N30,N31,N32,N33,N34,N35,N36,N37,
N38,N39,N40,N41,N42,N43,N44,N45,N46,N47,N48,N49,N50,N51,N52,N53,N54,N55,N56,N57,
N58,N59,N60,N61,N62,N63,N64,N65,N66,N67,N68,N69,N70,N71,N72,N73,N74,N75,N76,N77,
N78,N79,N80,N81,N82,N83,N84,N85,N86,N87,N88,N89,N90,N91,N92,N93,N94,N95,N96,N97,
N98,N99,N100,N101,N102,N103,N104,N105,N106,N107,N108,N109,N110,N111,N112,N113,
N114,N115,N116,N117,N118,N119,N120,N121,N122,N123,N124,N125,N126,N127,N128,N129,
N130,N131,N132,N133,N134,N135,N136,N137,N138,N139,N140,N141,N142,N143,N144,N145,
N146,N147,N148,N149,N150,N151,N152,N153,N154,N155,N156,N157,N158,N159,N160,N161,
N162,N163,N164,N165,N166,N167,N168,N169,N170,N171,N172,N173,N174,N175,N176,N177,
N178,N179,N180,N181,N182,N183,N184,N185,N186,N187,N188,N189,N190,N191,N192,N193,
N194,N195,N196,N197,N198,N199,N200,N201,N202,N203,N204,N205,N206,N207,N208,N209,
N210,N211,N212,N213,N214,N215,N216,N217,N218,N219,N220,N221,N222,N223,N224,N225,
N226,N227,N228,N229,N230,N231,N232,N233,N234,N235,N236,N237,N238,N239;
assign branch_exception_o[65] = 1'b0;
assign branch_exception_o[66] = 1'b0;
assign branch_exception_o[67] = 1'b0;
assign branch_exception_o[68] = 1'b0;
assign branch_exception_o[69] = 1'b0;
assign branch_exception_o[70] = 1'b0;
assign branch_exception_o[71] = 1'b0;
assign branch_exception_o[72] = 1'b0;
assign branch_exception_o[73] = 1'b0;
assign branch_exception_o[74] = 1'b0;
assign branch_exception_o[75] = 1'b0;
assign branch_exception_o[76] = 1'b0;
assign branch_exception_o[77] = 1'b0;
assign branch_exception_o[78] = 1'b0;
assign branch_exception_o[79] = 1'b0;
assign branch_exception_o[80] = 1'b0;
assign branch_exception_o[81] = 1'b0;
assign branch_exception_o[82] = 1'b0;
assign branch_exception_o[83] = 1'b0;
assign branch_exception_o[84] = 1'b0;
assign branch_exception_o[85] = 1'b0;
assign branch_exception_o[86] = 1'b0;
assign branch_exception_o[87] = 1'b0;
assign branch_exception_o[88] = 1'b0;
assign branch_exception_o[89] = 1'b0;
assign branch_exception_o[90] = 1'b0;
assign branch_exception_o[91] = 1'b0;
assign branch_exception_o[92] = 1'b0;
assign branch_exception_o[93] = 1'b0;
assign branch_exception_o[94] = 1'b0;
assign branch_exception_o[95] = 1'b0;
assign branch_exception_o[96] = 1'b0;
assign branch_exception_o[97] = 1'b0;
assign branch_exception_o[98] = 1'b0;
assign branch_exception_o[99] = 1'b0;
assign branch_exception_o[100] = 1'b0;
assign branch_exception_o[101] = 1'b0;
assign branch_exception_o[102] = 1'b0;
assign branch_exception_o[103] = 1'b0;
assign branch_exception_o[104] = 1'b0;
assign branch_exception_o[105] = 1'b0;
assign branch_exception_o[106] = 1'b0;
assign branch_exception_o[107] = 1'b0;
assign branch_exception_o[108] = 1'b0;
assign branch_exception_o[109] = 1'b0;
assign branch_exception_o[110] = 1'b0;
assign branch_exception_o[111] = 1'b0;
assign branch_exception_o[112] = 1'b0;
assign branch_exception_o[113] = 1'b0;
assign branch_exception_o[114] = 1'b0;
assign branch_exception_o[115] = 1'b0;
assign branch_exception_o[116] = 1'b0;
assign branch_exception_o[117] = 1'b0;
assign branch_exception_o[118] = 1'b0;
assign branch_exception_o[119] = 1'b0;
assign branch_exception_o[120] = 1'b0;
assign branch_exception_o[121] = 1'b0;
assign branch_exception_o[122] = 1'b0;
assign branch_exception_o[123] = 1'b0;
assign branch_exception_o[124] = 1'b0;
assign branch_exception_o[125] = 1'b0;
assign branch_exception_o[126] = 1'b0;
assign branch_exception_o[127] = 1'b0;
assign branch_exception_o[128] = 1'b0;
assign resolved_branch_o[1] = branch_predict_i[1];
assign resolved_branch_o[0] = branch_predict_i[0];
assign branch_exception_o[64] = pc_i[63];
assign branch_exception_o[63] = pc_i[62];
assign branch_exception_o[62] = pc_i[61];
assign branch_exception_o[61] = pc_i[60];
assign branch_exception_o[60] = pc_i[59];
assign branch_exception_o[59] = pc_i[58];
assign branch_exception_o[58] = pc_i[57];
assign branch_exception_o[57] = pc_i[56];
assign branch_exception_o[56] = pc_i[55];
assign branch_exception_o[55] = pc_i[54];
assign branch_exception_o[54] = pc_i[53];
assign branch_exception_o[53] = pc_i[52];
assign branch_exception_o[52] = pc_i[51];
assign branch_exception_o[51] = pc_i[50];
assign branch_exception_o[50] = pc_i[49];
assign branch_exception_o[49] = pc_i[48];
assign branch_exception_o[48] = pc_i[47];
assign branch_exception_o[47] = pc_i[46];
assign branch_exception_o[46] = pc_i[45];
assign branch_exception_o[45] = pc_i[44];
assign branch_exception_o[44] = pc_i[43];
assign branch_exception_o[43] = pc_i[42];
assign branch_exception_o[42] = pc_i[41];
assign branch_exception_o[41] = pc_i[40];
assign branch_exception_o[40] = pc_i[39];
assign branch_exception_o[39] = pc_i[38];
assign branch_exception_o[38] = pc_i[37];
assign branch_exception_o[37] = pc_i[36];
assign branch_exception_o[36] = pc_i[35];
assign branch_exception_o[35] = pc_i[34];
assign branch_exception_o[34] = pc_i[33];
assign branch_exception_o[33] = pc_i[32];
assign branch_exception_o[32] = pc_i[31];
assign branch_exception_o[31] = pc_i[30];
assign branch_exception_o[30] = pc_i[29];
assign branch_exception_o[29] = pc_i[28];
assign branch_exception_o[28] = pc_i[27];
assign branch_exception_o[27] = pc_i[26];
assign branch_exception_o[26] = pc_i[25];
assign branch_exception_o[25] = pc_i[24];
assign branch_exception_o[24] = pc_i[23];
assign branch_exception_o[23] = pc_i[22];
assign branch_exception_o[22] = pc_i[21];
assign branch_exception_o[21] = pc_i[20];
assign branch_exception_o[20] = pc_i[19];
assign branch_exception_o[19] = pc_i[18];
assign branch_exception_o[18] = pc_i[17];
assign branch_exception_o[17] = pc_i[16];
assign branch_exception_o[16] = pc_i[15];
assign branch_exception_o[15] = pc_i[14];
assign branch_exception_o[14] = pc_i[13];
assign branch_exception_o[13] = pc_i[12];
assign branch_exception_o[12] = pc_i[11];
assign branch_exception_o[11] = pc_i[10];
assign branch_exception_o[10] = pc_i[9];
assign branch_exception_o[9] = pc_i[8];
assign branch_exception_o[8] = pc_i[7];
assign branch_exception_o[7] = pc_i[6];
assign branch_exception_o[6] = pc_i[5];
assign branch_exception_o[5] = pc_i[4];
assign branch_exception_o[4] = pc_i[3];
assign branch_exception_o[3] = pc_i[2];
assign branch_exception_o[2] = pc_i[1];
assign branch_exception_o[1] = pc_i[0];
assign { target_address[63:1], N76 } = $signed({ N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11 }) + $signed(fu_data_i[66:3]);
assign N215 = branch_predict_i[2] ^ branch_comp_res_i;
assign N216 = target_address != branch_predict_i[66:3];
assign N227 = ~pc_i[1];
assign N228 = ~target_address[0];
assign N229 = ~fu_data_i[199];
assign N230 = ~fu_data_i[196];
assign N231 = ~fu_data_i[195];
assign N232 = fu_data_i[200] | fu_data_i[201];
assign N233 = N229 | N232;
assign N234 = fu_data_i[198] | N233;
assign N235 = fu_data_i[197] | N234;
assign N236 = N230 | N235;
assign N237 = N231 | N236;
assign N238 = ~N237;
assign { N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79 } = { pc_i[63:2], 1'b0, 1'b0 } + { 1'b1, 1'b0, 1'b0 };
assign branch_result_o = pc_i + { N75, is_compressed_instr_i, 1'b0 };
assign { N74, N73, N72, N71, N70, N69, N68, N67, N66, N65, N64, N63, N62, N61, N60, N59, N58, N57, N56, N55, N54, N53, N52, N51, N50, N49, N48, N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34, N33, N32, N31, N30, N29, N28, N27, N26, N25, N24, N23, N22, N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11 } = (N0)? fu_data_i[194:131] :
(N1)? pc_i : 1'b0;
assign N0 = N238;
assign N1 = N237;
assign target_address[0] = (N0)? 1'b0 :
(N1)? N76 : 1'b0;
assign resolved_branch_o[133:70] = (N2)? pc_i :
(N78)? { N142, N141, N140, N139, N138, N137, N136, N135, N134, N133, N132, N131, N130, N129, N128, N127, N126, N125, N124, N123, N122, N121, N120, N119, N118, N117, N116, N115, N114, N113, N112, N111, N110, N109, N108, N107, N106, N105, N104, N103, N102, N101, N100, N99, N98, N97, N96, N95, N94, N93, N92, N91, N90, N89, N88, N87, N86, N85, N84, N83, N82, N81, N80, N79 } : 1'b0;
assign N2 = N77;
assign { N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148 } = (N3)? target_address :
(N4)? branch_result_o : 1'b0;
assign N3 = branch_comp_res_i;
assign N4 = N147;
assign N219 = (N5)? 1'b1 :
(N218)? N215 : 1'b0;
assign N5 = N217;
assign N220 = (N6)? N219 :
(N225)? 1'b1 :
(N214)? 1'b0 : 1'b0;
assign N6 = branch_predict_i[67];
assign N221 = (N7)? N220 :
(N8)? 1'b0 : 1'b0;
assign N7 = N228;
assign N8 = target_address[0];
assign { resolved_branch_o[69:5], resolved_branch_o[3:2] } = (N9)? { N211, N210, N209, N208, N207, N206, N205, N204, N203, N202, N201, N200, N199, N198, N197, N196, N195, N194, N193, N192, N191, N190, N189, N188, N187, N186, N185, N184, N183, N182, N181, N180, N179, N178, N177, N176, N175, N174, N173, N172, N171, N170, N169, N168, N167, N166, N165, N164, N163, N162, N161, N160, N159, N158, N157, N156, N155, N154, N153, N152, N151, N150, N149, N148, N221, branch_valid_i, 1'b0 } :
(N223)? { branch_result_o, 1'b1, 1'b1, 1'b1 } :
(N145)? { 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, branch_valid_i, 1'b0 } : 1'b0;
assign N9 = branch_valid_i;
assign resolved_branch_o[4] = (N9)? branch_comp_res_i :
(N222)? 1'b0 :
(N10)? 1'b0 : 1'b0;
assign N10 = 1'b0;
assign resolve_branch_o = (N9)? 1'b1 :
(N223)? 1'b1 :
(N145)? 1'b0 : 1'b0;
assign N75 = ~is_compressed_instr_i;
assign N77 = is_compressed_instr_i | N227;
assign N78 = ~N77;
assign N143 = N239 & branch_predict_i[2];
assign N239 = fu_valid_i & branch_predict_i[67];
assign N144 = N143 | branch_valid_i;
assign N145 = ~N144;
assign N146 = branch_valid_i;
assign N147 = ~branch_comp_res_i;
assign N212 = N146 & N228;
assign N213 = branch_comp_res_i | branch_predict_i[67];
assign N214 = ~N213;
assign N217 = branch_predict_i[2] & N216;
assign N218 = ~N217;
assign N222 = ~branch_valid_i;
assign N223 = N143 & N222;
assign N224 = ~branch_predict_i[67];
assign N225 = branch_comp_res_i & N224;
assign N226 = branch_valid_i & target_address[0];
assign branch_exception_o[0] = N226;
endmodule |
module lfsr_8bit_00000004
(
clk_i,
rst_ni,
en_i,
refill_way_oh,
refill_way_bin
);
output [3:0] refill_way_oh;
output [1:0] refill_way_bin;
input clk_i;
input rst_ni;
input en_i;
wire [3:0] refill_way_oh;
wire N0,N1,N2,N3,N4,N5,N6,N7,N8;
reg [7:2] shift_q;
reg [1:0] refill_way_bin;
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[7] <= 1'b0;
end else if(en_i) begin
shift_q[7] <= shift_q[6];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[6] <= 1'b0;
end else if(en_i) begin
shift_q[6] <= shift_q[5];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[5] <= 1'b0;
end else if(en_i) begin
shift_q[5] <= shift_q[4];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[4] <= 1'b0;
end else if(en_i) begin
shift_q[4] <= shift_q[3];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[3] <= 1'b0;
end else if(en_i) begin
shift_q[3] <= shift_q[2];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
shift_q[2] <= 1'b0;
end else if(en_i) begin
shift_q[2] <= refill_way_bin[1];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
refill_way_bin[1] <= 1'b0;
end else if(en_i) begin
refill_way_bin[1] <= refill_way_bin[0];
end
end
always @(posedge clk_i or posedge N5) begin
if(N5) begin
refill_way_bin[0] <= 1'b0;
end else if(en_i) begin
refill_way_bin[0] <= N4;
end
end
assign refill_way_oh[3] = refill_way_bin[0] & refill_way_bin[1];
assign refill_way_oh[2] = N0 & refill_way_bin[1];
assign N0 = ~refill_way_bin[0];
assign refill_way_oh[1] = refill_way_bin[0] & N1;
assign N1 = ~refill_way_bin[1];
assign refill_way_oh[0] = N2 & N3;
assign N2 = ~refill_way_bin[0];
assign N3 = ~refill_way_bin[1];
assign N4 = ~N8;
assign N8 = N7 ^ refill_way_bin[1];
assign N7 = N6 ^ shift_q[2];
assign N6 = shift_q[7] ^ shift_q[3];
assign N5 = ~rst_ni;
endmodule |
module Subtractor_0x422b1f52edd46a85
(
input wire [ 0:0] clk,
input wire [ 15:0] in0,
input wire [ 15:0] in1,
output reg [ 15:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// s.out.value = s.in0 - s.in1
// logic for comb_logic()
always @ (*) begin
out = (in0-in1);
end
endmodule |
module Mux_0xdd6473406d1a99a
(
input wire [ 0:0] clk,
input wire [ 15:0] in_$000,
input wire [ 15:0] in_$001,
output reg [ 15:0] out,
input wire [ 0:0] reset,
input wire [ 0:0] sel
);
// localparam declarations
localparam nports = 2;
// array declarations
wire [ 15:0] in_[0:1];
assign in_[ 0] = in_$000;
assign in_[ 1] = in_$001;
// PYMTL SOURCE:
//
// @s.combinational
// def comb_logic():
// assert s.sel < nports
// s.out.v = s.in_[ s.sel ]
// logic for comb_logic()
always @ (*) begin
out = in_[sel];
end
endmodule |
module RegEn_0x68db79c4ec1d6e5b
(
input wire [ 0:0] clk,
input wire [ 0:0] en,
input wire [ 15:0] in_,
output reg [ 15:0] out,
input wire [ 0:0] reset
);
// PYMTL SOURCE:
//
// @s.posedge_clk
// def seq_logic():
// if s.en:
// s.out.next = s.in_
// logic for seq_logic()
always @ (posedge clk) begin
if (en) begin
out <= in_;
end
else begin
end
end
endmodule |
Subsets and Splits