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module gates_mux(
input a,b,
output xor_out, xnor_out
);
wire bbar;
mux_2_1 mbbar({1'b0, 1'b1}, b, bbar);
mux_2_1 mxor({bbar, b}, a, xor_out);
mux_2_1 mxnor({b, bbar}, a, xnor_out);
endmodule |
module test_bench;
parameter N = 6;
parameter LENGTH = 3;
reg clk,reset;
wire [LENGTH-1:0] counter;
mod_N_counter dut(clk, reset, counter);
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
initial
begin
reset = 1;
#10;
reset = 0;
end
initial begin
$monitor("\t\t\t counter: %d",counter);
#125 $finish;
end
endmodule |
module mod_N_counter
#(parameter N = 6,
parameter LENGTH = 3)
(input clk,reset, output reg [LENGTH-1:0] counter);
always@(posedge clk)
begin
if(reset)
counter <= 0;
else
if(counter == N-1)
counter <= 0;
else
counter <= counter + 1;
end
endmodule |
module up_down_counter
# (parameter N = 4)
( input clk, reset, upordown, output reg[N-1:0] count);
always @ (posedge clk )
begin
if (reset==1)
count <= 0;
else if(upordown==1) //Up Mode is selected
if (count == 2*N -1)
count <= 0;
else
count<=count+1; //increment counter
else //Down Mode is selected
if(count==0)
count<= 2*N -1;
else
count<=count-1; //Decrement the counter
end
endmodule |
module test_bench;
reg clk;
reg reset;
reg upordown;
wire [3:0] count;
up_down_counter uut (clk, reset, upordown, count);
initial begin
clk = 0;
reset = 1;
#50 reset =0;
upordown = 0;
#220;
upordown = 1;
#200;
upordown = 0;
#100;
reset = 0;
end
always #10 clk=~clk;
initial
begin
$monitor("\t\t UporDown=%b Count=%b",upordown,count);
#550 $finish;
end
endmodule |
module dual_edge_trig_ff(
input clk, reset, d,
output q
);
reg q1, q2;
assign q = clk ? q1 : q2;
always@ (posedge clk)
begin
if(reset) q1<= 1'b0;
q1 <= d;
end
always@ (negedge clk)
begin
if(reset) q2<= 1'b0;
q2 <= d;
end
endmodule |
module test_bench;
reg clk,rst,d;
wire Q;
dual_edge_trig_ff dut(clk,rst,d,Q);
initial begin
clk=0;
d=0;
forever #9 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever #6 d= ~d;
end
initial begin
$monitor("\t\t\t clk: %d D: %d Q: %d", clk, d, Q);
#80 $finish;
end
endmodule |
module test_bench;
reg [3:0] i;
reg [1:0] select;
wire y_out;
mux_4_1 dut(i, select, y_out);
always begin
i=$random;
select=$random;
#10;
end
initial
begin $monitor("Input Data : %b Select Line : %b Output : %b ",i, select, y_out);
#100 $finish;
end
endmodule |
module test_bench;
reg [31:0] number;
wire [31:0] sq_root, cube_root;
root dut(number, sq_root, cube_root);
initial begin
#10 number = 27;
#10 number = 121;
#10 number = 961;
#10 number = 512;
#10 number = 1764;
#10 number = 1000;
#10 number = 4761;
#10 number = 5832;
#10 $finish;
end
endmodule |
module root(
input [31:0] number,
output reg [31:0] sq_root, cube_root
);
real red;
always@(number) begin
find_sq_root(number, sq_root);
find_cube_root(number, cube_root);
$display("\n \t\t Square Root of %0d is %0d", number, sq_root);
$display(" \t\t Cube Root of %0d is %0d ", number, cube_root);
end
task find_sq_root;
input [31:0] num;
output [31:0] res;
begin
res = num**(0.5);
end
endtask
task find_cube_root;
input [31:0] num;
output [31:0] res;
begin
res= num**(0.33);
end
endtask
endmodule |
module test_bench;
reg clk, reset;
wire [3:0] state;
wire [1:0] out;
one_hot_fsm dut(clk, reset, state, out);
initial begin
clk = 0;
forever #10 clk = ~clk;
end
initial begin
reset = 1;
#20 reset = 0;
end
initial begin
$monitor("\t\t State: %b Output: %b", state, out);
#170 $finish;
end
endmodule |
module one_hot_fsm (
input clk, reset,
output reg [3:0] state,
output reg [1:0]out);
parameter [3:0] IDLE = 4'b0001,
STATE1 = 4'b0010,
STATE2 = 4'b0100,
STATE3 = 4'b1000;
always @(posedge clk, posedge reset) begin
if (reset)
begin
state <= IDLE;
out<= 2'b00;
end
else
begin
case(state)
IDLE: begin
out<= 2'b00;
state <= STATE1;
end
STATE1: begin
out<= 2'b01;
state <= STATE2;
end
STATE2: begin
out<= 2'b10;
state <= STATE3;
end
STATE3: begin
out<= 2'b11;
state <= IDLE;
end
default: state <= IDLE;
endcase
end
end
endmodule |
module test_bench;
reg clk, reset;
wire clk_by4;
freq_div_by4 dut(clk, reset, clk_by4);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
reset= 1'b1;
#20
reset= 1'b0;
#220 $finish;
end
endmodule |
module freq_div_by4(
input clk, reset,
output clk_by4
);
wire clk_by2;
D_flipflop D1(clk, reset, ~clk_by4, clk_by2);
D_flipflop D2(clk, reset, clk_by2, clk_by4);
endmodule |
module T_flipflop(
input t,clk,reset,
output reg Q
);
always@(posedge clk)
begin
if(reset)
Q <= 1'b0;
else
begin
if(t)
Q<= ~Q;
else
Q<= Q;
end
end
endmodule |
module test_bench;
reg clk,rst,t;
wire q;
T_flipflop dut(t,clk,rst,q);
initial
begin
clk=0;
t=0;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever
begin
#10 t = 1'b1;
#20 t = 1'b0;
end
end
initial begin
$monitor("\t clock: %b T: %b Q: %b",clk,t,q);
#100$finish;
end
endmodule |
module test_bench;
reg [3:0]dividend,divisor;
wire [3:0]quotient,remainder;
divide dut(dividend,divisor,quotient,remainder);
always begin
dividend =$random;
divisor =$random;
#10;
end
initial
begin $monitor("%0d / %0d = %0d with remainder %0d ",dividend,divisor,quotient,remainder);
#100 $finish;
end
endmodule |
module divide(
input [3:0]dividend,divisor,
output reg [3:0]quotient,remainder);
always@(dividend,divisor)
begin
quotient = 0;
remainder= dividend;
while(remainder>=divisor)
begin
remainder = remainder - divisor;
quotient = quotient + 1;
end
end
endmodule |
module ring_counter #(parameter N=4)
(input clk, reset,
output reg [N-1:0] counter );
always @(posedge clk)
begin
if (reset)
counter <= 1;
else
counter <= {counter[0], counter[N-1:1]};
end
endmodule |
module test_bench;
parameter N=4;
reg clk, reset;
wire [N-1:0] counter;
ring_counter dut(clk, reset, counter);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset = 1;
#10;
reset = 0;
end
initial begin
$monitor("\t\t counter: %d", counter);
#90 $finish;
end
endmodule |
module N_bit_comparator(a,b,Lesser,Greater,Equal);
parameter N=8;
input [N-1:0]a,b;
output Lesser,Greater,Equal;
reg Lesser=0,Greater=0,Equal=0;
always@(*) begin
if(a<b)
begin
Lesser=1'b1;
Equal=1'b0;
Greater=1'b0;
end
else if (a>b)
begin
Lesser=1'b0;
Equal=1'b0;
Greater=1'b1;
end
else
begin
Lesser=1'b0;
Equal=1'b1;
Greater=1'b0;
end
end
endmodule |
module test_bench;
reg [7:0]a;
reg [7:0]b;
wire Lesser,Greater,Equal;
N_bit_comparator dut(a,b,Lesser,Greater,Equal);
always begin
a=111;
b=250;
#10;
a=147;
b=103;
#10;
a=199;
b=220;
#10;
a=137;
b=171;
#10;
a=255;
b=255;
#10;
a=169;
b=169;
#10;
a=85;
b=25;
#10;
a=21;
b=50;
#10;
a=79;
b=74;
#10;
a=96;
b=96;
#10;
end
initial
begin $monitor("a= %0d b= %0d then Lesser= %0d Greater= %0d Equal= %0d ",a, b,Lesser,Greater,Equal );
#100 $finish;
end
endmodule |
module clk_phase(
input clk, rst,
output clk_0, clk_90, clk_180, clk_270
);
reg [1:0] count;
reg div_2;
always @(posedge clk or posedge rst)
begin
if(rst)
count <= 0;
else
count <= {~count[0], count[1]};
end
always @(posedge clk or posedge rst)
begin
if (rst)
div_2 <= 0;
else
div_2 = ~div_2;
end
assign clk_0 = count[1];
assign clk_90 = count[1] ^ div_2;
assign clk_180 = ~count[1];
assign clk_270 = ~clk_90;
endmodule |
module test_bench;
reg clk;
reg rst;
wire clk_0;
wire clk_90;
wire clk_180;
wire clk_270;
clk_phase dut(clk, rst, clk_0, clk_90, clk_180, clk_270);
initial begin
clk = 0;
forever #1 clk = ~clk;
end
initial begin
rst = 1;
#5 rst = 0;
#50 $finish;
end
endmodule |
module siso(
input clk, reset, serial_in,
output serial_out
);
wire q1, q0;
D_flipflop D2(serial_in, clk, reset, q1);
D_flipflop D1(q1, clk, reset, q0);
D_flipflop D0(q0, clk, reset, serial_out);
endmodule |
module test_bench;
reg clk, reset, serial_in;
wire serial_out;
siso dut(clk, reset, serial_in, serial_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1'b1;
serial_in= 1'b0;
#10 reset= 1'b0;
#0 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'bx;
end
initial begin
$monitor("\t\t clk: %d reset: %d serial_in: %d serial_out: %d", clk, reset, serial_in, serial_out);
#120 $finish;
end
endmodule |
module armstrong(
input [8:0] number,
output reg is_armstrong
);
parameter ARMSTRONG= 1'b1, Not_ARMSTRONG= 1'b0;
always@(number)
begin
is_armstrong= check_armstrong(number);
if(is_armstrong== 1'b1) $display("\t\t %d is a armstrong number", number);
else $display("\t\t %d is not a armstrong number", number);
end
function check_armstrong;
input [8:0]num;
reg [8:0] temp_num;
reg [8:0] remainder;
reg [8:0] result;
begin
result= 9'd0;
temp_num = num;
while (temp_num != 0) begin
remainder = temp_num % 10;
result = result + (remainder * remainder * remainder);
temp_num = temp_num/ 10;
end
if (result == num) check_armstrong= ARMSTRONG;
else check_armstrong= Not_ARMSTRONG;
end
endfunction
endmodule |
module test_bench;
reg [8:0]number;
wire is_armstrong;
armstrong dut(number, is_armstrong);
always
begin
number=9'd153;
#10;
number=9'd300;
#10;
number=9'd370;
#10;
number=9'd190;
#10;
number=9'd407;
#10;
number=9'd420;
#10;
end
initial #60 $finish;
endmodule |
module SR_latch(
input en, rst, S, R,
output reg Q
);
always@(*)
begin
if(rst) Q<= 1'b0;
else if(en) begin
case({S,R})
2'b00 : Q<= Q;
2'b01 : Q<= 1'b0;
2'b10 : Q<= 1'b1;
default : Q<=2'bxx;
endcase
end
end
endmodule |
module test_bench;
reg S, R, en, rst;
wire Q;
SR_latch dut(en,rst,S,R,Q);
initial begin
rst=1;
S = 0;
R = 0;
en = 0;
#10;
rst=0;
en=1;
end
always begin
S=0;
R=0;
#10;
S=0;
R=1;
#10;
S=1;
R=0;
#10;
S=1;
R=1;
#10;
end
initial begin
$monitor("\t en: %d S: %d R: %d Q: %d", en,S,R,Q);
#90 $finish;
end
endmodule |
module not_gate(
input in,
output out
);
supply0 gnd;
supply1 vdd;
pmos(out, vdd, in);
nmos(out, gnd, in);
endmodule |
module test_bench;
reg in;
wire out;
not_gate dut(in, out);
initial in= 1'b0;
initial forever #50 in = ~in;
initial #600 $finish;
endmodule |
module decoder_3_8(
input [2:0] in,
output reg[7:0] out
);
always@(*)
begin
out=0;
case(in)
3'b000 : out[0] = 1'b1;
3'b001 : out[1] = 1'b1;
3'b010 : out[2] = 1'b1;
3'b011 : out[3] = 1'b1;
3'b100 : out[4] = 1'b1;
3'b101 : out[5] = 1'b1;
3'b110 : out[6] = 1'b1;
3'b111 : out[7] = 1'b1;
default: out = 0;
endcase
end
endmodule |
module test_bench;
reg [2:0] in;
wire [7:0] out;
decoder_3_8 dut(in,out);
initial
begin
in=3'b000;
#10;
end
always begin
#10 in=3'b000;
#10 in=3'b001;
#10 in=3'b010;
#10 in=3'b011;
#10 in=3'b100;
#10 in=3'b101;
#10 in=3'b110;
#10 in=3'b111;
end
initial begin
$monitor("in: %b out: %b", in, out);
#90 $finish;
end
endmodule |
module HCF #(parameter N= 8)
( input [N-1:0] in1,in2,
output [N-1:0] HCF );
reg [N-1:0] i1,i2;
always@(*)
begin
i1=in1;
i2=in2;
while(i1 != i2)
begin
if(i1 > i2) i1= i1 - i2;
else i2= i2 - i1;
end
end
assign HCF = i1;
endmodule |
module test_bench #(parameter N= 8);
reg [N-1:0] in1;
reg [N-1:0] in2;
wire [N-1:0] HCF;
HCF dut(in1, in2, HCF);
initial begin
in1 = 27; in2 = 45; #10;
in1 = 56; in2 = 84; #10;
in1 = 49; in2 = 77; #10;
in1 = 108; in2 = 24; #10;
in1 = 17; in2 = 103; #10;
in1 = 100; in2 = 70; #10;
$finish;
end
initial
$monitor("\t 1st INPUT: %d 2nd INPUT: %d Highest Common Factor: %d",in1,in2,HCF);
endmodule |
module carry_look_ahead_gen(
input [3:0] a, b,
input cin,
output [3:0] sum,
output carry
);
wire p0, g0, p1, g1, p2, g2, p3, g3;
wire [3:0]c;
and (g0, a[0], b[0]),
(g1, a[1], b[1]),
(g2, a[2], b[2]),
(g3, a[3], b[3]);
xor (p0, a[0], b[0]),
(p1, a[1], b[1]),
(p2, a[2], b[2]),
(p3, a[3], b[3]);
xor (sum[0], p0, cin),
(sum[1], p1, c0),
(sum[2], p2, c1),
(sum[3], p3, c2);
assign c[0] = g0 | (p0 & cin),
c[1] = g1 | (p1 & g0) | (p1 & p0 & cin),
c[2] = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cin),
c[3] = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) |(p3 & p2 & p1 & p0 & cin);
assign carry = c[3];
endmodule |
module test_bench;
reg clk,rst,d;
wire Q;
D_flipflop dut(clk,rst,d,Q);
initial begin
clk=0;
d=0;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever #10 d= ~d;
end
initial begin
$monitor("\t clk: %d D: %d Q: %d", clk, d, Q);
#80 $finish;
end
endmodule |
module prime(
input [7:0]number,
output reg is_prime
);
parameter PRIME= 1'b1, Not_PRIME= 1'b0;
always@(number) begin
is_prime= check_prime(number);
if(is_prime== 1'b1) $display("\t\t %d is a prime number", number);
else $display("\t\t %d is not a prime number", number);
end
function automatic integer check_prime;
input [7:0]num;
integer i;
integer count;
begin
count= 0;
for (i = 2; i < num/2; i = i + 1) begin
if (num % i == 0) begin
count = count+1;
end
end
if(count== 0) check_prime= PRIME;
else check_prime= Not_PRIME;
end
endfunction
endmodule |
module test_bench;
reg [7:0] number;
wire is_prime;
prime dut(number, is_prime);
always begin
number=8'd36;
#10;
number=8'd71;
#10;
number=8'd49;
#10;
number=8'd11;
#10;
number=8'd3;
#10;
number=8'd91;
#10;
#10;
end
initial #60 $finish;
endmodule |
module PWM(
input clk, rst,
output reg dout
);
parameter period = 10;
integer count;
integer ton;
reg ncyc;
always@(posedge clk)
begin
if(rst == 1'b1)
begin
count <= 0;
ton <= 0;
ncyc <= 1'b0;
end
else
begin
if(count <= ton)
begin
count <= count + 1;
dout <= 1'b1;
ncyc <= 1'b0;
end
else if (count < period)
begin
count <= count + 1;
dout <= 1'b0;
ncyc <= 1'b0;
end
else
begin
ncyc <= 1'b1;
count <= 0;
end
end
end
always@(posedge clk)
begin
if(rst == 1'b0)
begin
if(ncyc == 1'b1)
begin
if(ton < period)
ton <= ton + 1;
else
ton <= 0;
end
end
end
endmodule |
module demux_2_1(
input sel,
input i,
output y0, y1
);
assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule |
module dmux_1_8(
input [2:0]sel,
input i,
output y0, y1, y2, y3, y4, y5, y6, y7
);
wire [5:0]z;
demux_2_1 d1(sel[2], i, z[0], z[1]);
demux_2_1 d2(sel[1], z[0], z[2], z[3]);
demux_2_1 d3(sel[1], z[1], z[4], z[5]);
demux_2_1 d4(sel[0], z[2], y0, y1);
demux_2_1 d5(sel[0], z[3], y2, y3);
demux_2_1 d6(sel[0], z[4], y4, y5);
demux_2_1 d7(sel[0], z[5], y6, y7);
endmodule |
module test_bench;
reg [2:0]sel;
reg i;
wire y0, y1, y2, y3, y4, y5, y6, y7;
dmux_1_8 demux(sel, i, y0, y1, y2, y3, y4, y5, y6, y7);
always begin
sel= $random;
i= 1'b1;
#10;
end
initial
begin $monitor("sel: %b i: %b y0 = %0b y1 = %0b y2 = %0b y3 = %0b y4 = %0b y5 = %0b y6 = %0b y7 = %0b", sel, i, y0, y1, y2, y3, y4, y5, y6, y7);
#80 $finish;
end
endmodule |
module test_bench;
reg [3:0] n;
wire [31:0] result;
integer x;
factorial dut(n, result);
always for(x=0; x<11; x=x+1) #10 n=x;
initial begin
$monitor("\t\t factorial of %d is %0d", n, result);
#120 $finish;
end
endmodule |
module factorial( input [3:0]n, output reg [31:0] result);
function automatic integer fact(input integer i);
begin
if (i > 1) fact = i * fact(i - 1);
else fact = 1;
end
endfunction
always@(n) result = fact(n);
endmodule |
module fifo #( parameter WIDTH = 8, DEPTH = 16 )
( input clk, rst, wr_en, rd_en,
input [WIDTH-1:0] wr_data,
output reg [WIDTH-1:0] rd_data,
output reg empty, full
);
reg [WIDTH-1:0] mem [0:DEPTH-1];
reg [WIDTH-1:0] rd_ptr = 0;
reg [WIDTH-1:0] wr_ptr = 0;
reg [WIDTH-1:0] next_wr_ptr;
reg [WIDTH-1:0] next_rd_ptr;
reg [DEPTH-1:0] num_items = 0;
always @(posedge clk)
begin
if (rst)
begin
rd_ptr <= 0;
wr_ptr <= 0;
next_rd_ptr <= 0;
next_wr_ptr <= 0;
num_items <= 0;
empty <= 1;
full <= 0;
end
else
begin
rd_ptr <= next_rd_ptr;
wr_ptr <= next_wr_ptr;
empty <= (num_items == 0);
full <= (num_items == DEPTH);
if (wr_en && !full)
begin
mem[wr_ptr] <= wr_data;
next_wr_ptr <= (wr_ptr + 1) % DEPTH;
num_items <= num_items + 1;
end
if (rd_en && !empty)
begin
rd_data <= mem[rd_ptr];
next_rd_ptr <= (rd_ptr + 1) % DEPTH;
num_items <= num_items - 1;
end
end
end
endmodule |
module test_bench;
localparam WIDTH = 8, DEPTH = 16;
reg clk, rst, wr_en, rd_en;
reg [WIDTH-1:0] wr_data;
wire [WIDTH-1:0] rd_data;
wire empty, full;
fifo #(WIDTH,DEPTH) dut(clk,rst,wr_en,rd_en,wr_data,rd_data,empty,full);
initial begin
clk= 0;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
wr_en = 0;
rd_en = 0;
wr_data = 0;
#10 rst = 0;
#10 wr_en = 1; wr_data = 1;
#10 wr_en = 1; wr_data = 2;
#10 wr_en = 1; wr_data = 3;
#10 rd_en = 1;
#10 rd_en = 1;
#10 wr_en = 1; wr_data = 4;
#10 wr_en = 1; wr_data = 5;
#80 $finish;
end
always @(posedge clk) begin
$display("RD Data: %d, Empty: %d, Full: %d", rd_data, empty, full);
end
endmodule |
module jhonson_counter #(parameter N=4)
(input clk, reset,
output reg [3:0] counter);
always@(posedge clk)
begin
if(reset)
counter <= 0;
else
counter <= {~counter[0], counter[N-1:1]};
end
endmodule |
module test_bench;
parameter N=4;
reg clk, reset;
wire [N-1:0] counter;
jhonson_counter dut(clk, reset, counter);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10;
reset= 1'b0;
end
initial begin
$monitor("\t\t counter: %d", counter);
#95 $finish;
end
endmodule |
module test_bench;
reg [3:0] a;
reg [3:0] b;
reg cin;
wire [3:0] sum;
wire carry;
parallel_adder dut (a,b,cin,sum,carry);
always begin
a= $random;
b= $random;
cin= $random;
#10;
end
initial
begin $monitor("a= %b b= %b cin= %b sum= %b carry= %b",a, b, cin, sum, carry);
#60 $finish;
end
endmodule |
module test_bench;
reg clk, reset;
wire clk_by5;
freq_div_by5 dut(clk, reset, clk_by5);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
reset= 1'b1;
#20
reset= 1'b0;
#380 $finish;
end
endmodule |
module mod_5_counter
(input clk,reset, output reg [2:0] counter);
always@(posedge clk)
begin
if(reset)
counter <= 0;
else
if(counter == 4)
counter <= 0;
else
counter <= counter + 1;
end
endmodule |
module freq_div_by5(
input clk, reset,
output clk_by5
);
wire[2:0] q;
wire temp;
mod_5_counter M5C(clk, reset, q);
D_flipflop D(~clk, reset, q[1], temp);
or(clk_by5, q[1], temp);
endmodule |
module Palindrome(
input [15:0] number,
output reg is_palindrome
);
parameter PALINDROME= 1'b1, Not_PALINDROME= 1'b0;
always@(number)
begin
is_palindrome= check_palindrome(number);
if(is_palindrome== 1'b1) $display("\t\t %d is a palindrome number", number);
else $display("\t\t %d is not a palindrome odd number", number);
end
function check_palindrome;
input [15:0]num;
reg [15:0]lastDigit;
reg [15:0]reverseNum;
reg [15:0]temp_num;
begin
temp_num= num;
reverseNum= 1'b0;
while (temp_num > 0) begin
lastDigit = temp_num % 10;
reverseNum = (reverseNum * 10) + lastDigit;
temp_num = temp_num / 10;
end
if (num == reverseNum) check_palindrome= PALINDROME;
else check_palindrome= Not_PALINDROME;
end
endfunction
endmodule |
module test_bench;
reg [15:0]number;
wire is_palindrome;
Palindrome dut(number, is_palindrome);
always
begin
number=16'd18681;
#10;
number=16'd3453;
#10;
number=16'd14441;
#10;
number=16'd51125;
#10;
number=16'd12021;
#10;
number=16'd35153;
#10;
number=16'd8998;
#10;
number=16'd6196;
#10;
end
initial #80 $finish;
endmodule |
module universal_shift_register (
input clk, reset, shift_left, shift_right,
input [7:0] parallel_in,
output [7:0] parallel_out
);
reg [7:0] reg_data;
always @(posedge clk)
begin
if (reset)
reg_data <= 8'b0;
else if (shift_left)
reg_data <= {reg_data[6:0], 1'b0};
else if (shift_right)
reg_data <= {1'b0, reg_data[7:1]};
else
reg_data <= parallel_in;
end
assign parallel_out = reg_data;
endmodule |
module test_bench;
reg clk, reset, shift_left, shift_right;
reg [7:0] parallel_in;
wire [7:0] parallel_out;
universal_shift_register dut (clk, reset, shift_left, shift_right, parallel_in, parallel_out);
initial begin
clk = 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset = 1'b1;
shift_left = 1'b0;
shift_right = 1'b0;
parallel_in = 8'he5;
#10;
reset = 1'b0;
#10;
shift_left = 1'b1;
shift_right = 1'b0;
#10;
shift_left = 1'b0;
shift_right = 1'b1;
#10;
shift_left = 1'b1;
shift_right = 1'b0;
#10;
shift_left = 1'b1;
shift_right = 1'b0;
#10;
shift_left = 1'b0;
shift_right = 1'b1;
end
initial begin
$monitor("\t input: %b right shift: %b left shift: %b output: %b", parallel_in, shift_right, shift_left, parallel_out);
#75 $finish;
end
endmodule |
module adder_4bit(
input [3:0] x,y,
output [3:0] z
);
assign z=x+y;
endmodule |
module adder_6bit(
input [5:0] x,y,
output [5:0] z
);
assign z=x+y;
endmodule |
module vedic_mul_4_4(
input [3:0] a,b,
output [7:0] out
);
wire [3:0] w3,w2,w1,w0,w;
wire [5:0] w4;
vedic_mul_2_2 m1(b[3:2],a[3:2],w3[3:0]);
vedic_mul_2_2 m2(b[3:2],a[1:0],w2[3:0]);
vedic_mul_2_2 m3(b[1:0],a[3:2],w1[3:0]);
vedic_mul_2_2 m4(b[1:0],a[1:0],w0[3:0]);
adder_6bit m5({w3[3:0],2'b00},{2'b00,w2[3:0]},w4);
adder_4bit m6(w1[3:0],{2'b00,w0[3:2]},w);
adder_6bit m7(w4,{2'b00,w[3:0]},out[7:2]);
assign out[1:0]=w0[1:0];
endmodule |
module test_bench;
reg [3:0] a,b;
wire [7:0] out;
vedic_mul_4_4 dut(a,b,out);
always begin
a=$random;
b=$random;
#10;
end
initial begin
$monitor("%d * %d = %d", a,b,out);
#60 $finish;
end
endmodule |
module dual_port_ram
#(parameter data_width=8,
parameter addr_width=4,
parameter depth=16)
( input clk,
input wr_en,
input [data_width-1:0] data_in,
input [addr_width-1:0] addr_in_0, //address for port 0
input [addr_width-1:0] addr_in_1, //address for port 1
input port_en_0, //enable port 0.
input port_en_1, //enable port 1.
output [data_width-1:0] data_out_0, //output data from port 0.
output [data_width-1:0] data_out_1 //output data from port 1.
);
reg [data_width-1:0] ram [0:depth-1];
always@(posedge clk)
begin
if(port_en_0 == 1 && wr_en == 1)
ram[addr_in_0] <= data_in;
end
assign data_out_0 = port_en_0 ? ram[addr_in_0] : 'dZ;
assign data_out_1 = port_en_1 ? ram[addr_in_1] : 'dZ;
endmodule |
module test_bench;
parameter data_width = 8;
parameter addr_width = 4;
parameter depth = 16;
integer i;
reg clk;
reg wr_en;
reg [data_width-1:0] data_in;
reg [addr_width-1:0] addr_in_0;
reg [addr_width-1:0] addr_in_1;
reg port_en_0;
reg port_en_1;
wire [data_width-1:0] data_out_0;
wire [data_width-1:0] data_out_1;
dual_port_ram dut(clk, wr_en, data_in, addr_in_0, addr_in_1, port_en_0, port_en_1, data_out_0, data_out_1);
initial begin
clk= 1'b1;
forever #5 clk = ~clk;
end
initial begin
addr_in_1 = 0;
port_en_0 = 0;
port_en_1 = 0;
wr_en = 0;
data_in = 0;
addr_in_0 = 0;
#20;
port_en_0 = 1;
wr_en = 1;
for(i=1; i <= 16; i = i + 1) begin
data_in = i;
addr_in_0 = i-1;
#10;
end
wr_en = 0;
port_en_0 = 0;
port_en_1 = 1;
for(i=1; i <= 16; i = i + 1) begin
addr_in_1 = i-1;
#10;
end
port_en_1 = 0;
end
initial begin
$monitor("write enable: %d input data: %d address 0: %d address 1: %d output 0: %d output 1: %d", wr_en, data_in, addr_in_0, addr_in_1, data_out_0, data_out_1);
#340 $finish;
end
endmodule |
module complement_2s(
input [3:0] data,
output signed [3:0] out
);
wire [3:0]temp;
assign temp= 4'b1111 - data;
assign out= temp + 4'b0001;
endmodule |
module test_bench;
reg [3:0] data;
wire signed [3:0]out;
complement_2s dut(data, out);
initial begin
data= 4'd0;
#10;
data= 4'd1;
#10;
data= 4'd2;
#10;
data= 4'd3;
#10;
data= 4'd4;
#10;
data= 4'd5;
#10;
data= 4'd6;
#10;
data= 4'd7;
#10;
data= 4'd8;
#10;
data= 4'd9;
#10;
data= 4'd10;
#10;
data= 4'd11;
#10;
data= 4'd12;
#10;
data= 4'd13;
#10;
data= 4'd14;
#10;
data= 4'd15;
end
initial
begin $monitor("input number: %d 2's Complement: %d", data, out);
#160 $finish;
end
endmodule |
module test_bench;
reg sel, i;
wire [1:0]y;
demux_1_2 dut(sel, i, y);
initial begin
sel=0; i=0;
#10;
sel=0; i=1;
#10;
sel=1; i=0;
#10;
sel=1; i=1;
end
initial
begin $monitor("sel: %b i: %b y[0]: %b y[1]: %b", sel, i, y[0], y[1]);
#40 $finish;
end
endmodule |
module n_bit_square(num, result);
parameter n=4;
input [n-1:0] num;
output reg [2*n-1:0] result;
reg [2*n-1:0] tmp;
always @(*) begin
tmp = num * num;
result = tmp;
end
endmodule |
module test_bench;
parameter n=4;
reg [n-1:0]num;
wire [2*n-1:0]result;
n_bit_square dut(num, result);
always begin
num=$random;
#10;
end
initial
begin $monitor("%d^2 = %0d ",num, result);
#80 $finish;
end
endmodule |
module pipo(
input clk, reset,
input [2:0] parallel_in,
output [2:0] parallel_out
);
D_flipflop D2(parallel_in[2], clk, reset, parallel_out[2]);
D_flipflop D1(parallel_in[1], clk, reset, parallel_out[1]);
D_flipflop D0(parallel_in[0], clk, reset, parallel_out[0]);
endmodule |
module test_bench;
reg clk, reset;
reg [2:0] parallel_in;
wire [2:0] parallel_out;
pipo dut(clk, reset, parallel_in, parallel_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1'b1;
parallel_in= 3'b000;
#10 reset= 1'b0;
end
always #10 parallel_in= $random;
initial begin
$monitor("\t\t clk: %d reset: %d parallel_in: %b parallel_out: %b", clk, reset, parallel_in, parallel_out);
#100 $finish;
end
endmodule |
module logic_gates(
input a, b,
output reg and_g,
output reg or_g,
output reg not_g,
output reg nand_g,
output reg nor_g,
output reg xor_g,
output reg xnor_g
);
always@(*)
begin
and_g = a&b;
or_g = a|b;
not_g = ~a;
nand_g = ~(a&b);
nor_g = ~(a|b);
xor_g = a^b;
xnor_g = ~(a^b);
end
endmodule |
module tb_nor;
reg a, b;
wire nor_out;
decoder_nor dut(a, b, nor_out);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b nor: %b ",a, b, nor_out);
#40 $finish;
end
endmodule |
module decoder_nor(
input a,b,
output nor_g
);
wire [3:0]w;
decoder_2_4 norgate({a,b}, w);
assign nor_g= w[0];
endmodule |
module tb_nand;
reg a, b;
wire nand_out;
decoder_nand dut(a, b, nand_out);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b nand: %b ",a, b, nand_out);
#40 $finish;
end
endmodule |
module decoder_nand(
input a,b,
output nand_g
);
wire [3:0]w;
decoder_2_4 nandgate({a,b}, w);
assign nand_g= ~w[3];
endmodule |
module decoder_and(
input a,b,
output and_g
);
wire [3:0]w;
decoder_2_4 andgate({a,b}, w);
assign and_g= w[3];
endmodule |
module tb_and;
reg a, b;
wire and_out;
decoder_and dut(a, b, and_out);
initial begin
#0 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b and: %b ",a, b, and_out);
#40 $finish;
end
endmodule |
module tb_or;
reg a, b;
wire or_out;
decoder_or dut(a, b, or_out);
initial begin
#0 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b or: %b ",a, b, or_out);
#40 $finish;
end
endmodule |
module decoder_or(
input a,b,
output or_g
);
wire [3:0]w;
decoder_2_4 orgate({a,b}, w);
assign or_g= ~w[0];
endmodule |
module decoder_not(
input a,
output not_g
);
wire [3:0]w;
decoder_2_4 notgate({a,1'b0}, w);
assign not_g= w[0];
endmodule |
module tb_not;
reg a;
wire not_out;
decoder_not dut(a, not_out);
initial begin
#0 a= 1'b0;
#10 a= 1'b1;
end
initial
begin $monitor("a: %b not: %b ",a, not_out);
#20 $finish;
end
endmodule |
module half_adder(
input a, b,
output sout, cout
);
assign sout = a^b;
assign cout = a&b;
endmodule |
module test_bench_ha;
reg a, b;
wire sout, cout;
reg clk;
half_adder dut(a, b, sout, cout);
always #5 clk = ~clk;
initial begin
clk = 0;
a = 0; b = 0;
#10;
a = 0; b = 1;
#10;
a = 1; b = 0;
#10;
a = 1; b = 1;
#10;
$finish;
end
always @(posedge clk) begin
$display("a = %b, b = %b, sum = %b, carry = %b", a, b, sout, cout);
end
endmodule |
module test_bench;
reg a, b, cin;
wire sout, cout;
reg clk;
full_adder dut(a, b, cin, sout, cout);
always #5 clk = ~clk;
initial begin
clk = 0;
a = 0; b = 0; cin = 0;
#10;
a = 0; b = 0; cin = 1;
#10;
a = 0; b = 1; cin = 0;
#10;
a = 0; b = 1; cin = 1;
#10;
a = 1; b = 0; cin = 0;
#10;
a = 1; b = 0; cin = 1;
#10;
a = 1; b = 1; cin = 0;
#10;
a = 1; b = 1; cin = 1;
#10;
$finish;
end
always @(posedge clk) begin
$display("a = %b, b = %b, cin = %b, sum = %b, carry = %b", a, b, cin, sout, cout);
end
endmodule |
module SR_flipflop(
input clk,reset,S,R,
output reg Q);
always@(posedge clk)
begin
if(reset)
Q <= 1'b0;
else
begin
case({S,R})
2'b00:Q<=Q;
2'b01:Q<=1'b0;
2'b10:Q<=1'b1;
default: Q<= 2'bxx;
endcase
end
end
endmodule |
module test_bench;
reg clk,rst,d;
wire Q_sr, Q_jk, Q_t;
D_using_SR_JK_T dut(clk,rst,d,Q_sr, Q_jk, Q_t);
initial begin
clk=0;
d=0;
forever #4 clk=~clk;
end
initial
begin
rst=1;
#10;
rst=0;
forever #10 d= ~d;
end
initial begin
$monitor("\t clk: %d D: %d Q_sr: %d Q_jk: %d Q_t: %d", clk, d, Q_sr, Q_jk, Q_t);
#80 $finish;
end
endmodule |
module D_using_SR_JK_T(
input clk, reset, D,
output Q_sr, Q_jk, Q_t
);
wire w;
SR_flipflop SR(clk, reset, D, ~D, Q_sr);
JK_flipflop JK(D, ~D, clk, reset, Q_jk);
assign w= D ^ Q_t;
T_flipflop T(w, clk, reset, Q_t);
endmodule |
module even_parity_generator (
input wire [7:0] data_in,
output wire parity
);
assign parity = ^data_in;
endmodule |
module even_parity_checker(
input wire [7:0] data_in,
input wire parity_in,
output wire error
);
assign error = ^({parity_in, data_in});
endmodule |
module test_bench_pg;
reg [7:0] data_in;
wire parity;
reg clk;
even_parity_generator dut(data_in, parity);
always #5 clk = ~clk;
initial begin
clk = 0;
data_in = 8'b00000000;
#10;
data_in = 8'b00000001;
#10;
data_in = 8'b00000011;
#10;
data_in = 8'b10000000;
#10;
data_in = 8'b11011111;
#10;
data_in = 8'b01010101;
#10;
data_in = 8'b10101010;
#10;
$finish;
end
always @(posedge clk) begin
$display("Data: %b, Parity: %b", data_in, parity);
end
endmodule |
module test_bench_pc;
reg [7:0] data_in;
reg parity_in;
reg clk;
wire error;
even_parity_checker dut(data_in, parity_in, error);
always #5 clk = ~clk;
initial begin
clk = 0;
data_in = 8'b00000000;
parity_in = 1;
#10;
data_in = 8'b00000001;
parity_in = 0;
#10;
data_in = 8'b00000011;
parity_in = 1;
#10;
data_in = 8'b10000000;
parity_in = 0;
#10;
data_in = 8'b11011111;
parity_in = 1;
#10;
data_in = 8'b01010101;
parity_in = 0;
#10;
data_in = 8'b10101010;
parity_in = 1;
#10;
$finish;
end
always @(posedge clk) begin
$display("Data: %b, Parity: %b, Error: %b", data_in, parity_in, error);
end
endmodule |
module freq_div_by3(
input clk, reset,
output clk_by3
);
wire[1:0] q;
wire temp;
mod_3_counter M3C(clk, reset, q);
D_flipflop D(~clk, reset, q[1], temp);
or(clk_by3, q[1], temp);
endmodule |
module freq_div(
input clk, reset,
output new_clk
);
wire t1, t2;
freq_div_by3 FD3(clk, reset, t1);
dual_edge_trig_ff DETF(clk, reset, t1, t2);
xor(new_clk, t1, t2);
endmodule |
module test_bench;
reg clk, reset;
wire new_clk;
freq_div dut(clk, reset, new_clk);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
reset= 1'b1;
#20
reset= 1'b0;
#200 $finish;
end
endmodule |
module JK_using_SR_D_T(
input J, K, clk, reset,
output Q_sr, Q_d, Q_t
);
wire w1, w2, w3, w4, w5, w6, w7, w8;
assign w1= J & (~Q_sr);
assign w2= K & Q_sr;
SR_flipflop SR(clk, reset, w1, w2, Q_sr);
assign w3= J & (~Q_d);
assign w4= (~K) & Q_d;
assign w5= w3 | w4;
D_flipflop D(w5, clk, reset, Q_d);
assign w6= J & (~Q_t);
assign w7= K & Q_t;
assign w8= w6 | w7;
T_flipflop T(w8, clk, reset, Q_t);
endmodule |
module test_bench;
reg clk,rst,J,K;
wire Q_sr, Q_d, Q_t;
JK_using_SR_D_T dut(J, K, clk, rst, Q_sr, Q_d, Q_t);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst=1;
J = 0;
K = 0;
#10;
rst=0;
end
always begin
J=0;
K=0;
#10;
J=0;
K=1;
#10;
J=1;
K=0;
#10;
J=1;
K=1;
#10;
end
initial begin
$monitor("\t clk: %d J: %d K: %d Q_sr: %d Q_d: %d Q_t:%d", clk,J,K,Q_sr, Q_d, Q_t);
#90 $finish;
end
endmodule |
module SR_using_JK_D_T(
input S, R, clk, rst,
output Q_jk, Q_d, Q_t
);
wire w1, w2, w3, w4, w5;
JK_flipflop JK(S, R, clk, rst, Q_jk);
assign w1= ~R & Q_d;
assign w2= S | w1;
D_flipflop D(w2, clk, rst, Q_d);
assign w3= S & ~Q_t;
assign w4= R & Q_t;
assign w5= w3 | w4;
T_flipflop T(w5, clk, rst, Q_t);
endmodule |
module test_bench;
reg S, R, clk, rst;
wire Q_jk, Q_d, Q_t;
SR_using_JK_D_T dut(S, R, clk, rst, Q_jk, Q_d, Q_t);
initial begin
clk = 0;
forever #5 clk = ~clk;
end
initial begin
rst=1;
S = 0;
R = 0;
#10;
rst=0;
end
always begin
S=0;
R=0;
#10;
S=0;
R=1;
#10;
S=1;
R=0;
#10;
S=1;
R=1;
#10;
end
initial begin
$monitor("\t clk: %d S: %d R: %d Q_jk: %d Q_d: %d Q_t:%d", clk,S,R,Q_jk, Q_d, Q_t);
#90 $finish;
end
endmodule |
module mux(o,i1,i2,s); //2x1 MUX
input i1,i2,s;
output o;
wire x1,x2,sc;
not(sc,s);
and(x1,i1,sc);
and(x2,i2,s);
or(o,x1,x2);
endmodule |
Subsets and Splits