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module e203_exu_oitf (
output dis_ready,
input dis_ena,
input ret_ena,
output [`E203_ITAG_WIDTH-1:0] dis_ptr,
output [`E203_ITAG_WIDTH-1:0] ret_ptr,
output [`E203_RFIDX_WIDTH-1:0] ret_rdidx,
output ret_rdwen,
output ret_rdfpu,
output [`E203_PC_SIZE-1:0] ret_pc,
input disp_i_rs1en,
input disp_i_rs2en,
input disp_i_rs3en,
input disp_i_rdwen,
input disp_i_rs1fpu,
input disp_i_rs2fpu,
input disp_i_rs3fpu,
input disp_i_rdfpu,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs3idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
input [`E203_PC_SIZE -1:0] disp_i_pc,
output oitfrd_match_disprs1,
output oitfrd_match_disprs2,
output oitfrd_match_disprs3,
output oitfrd_match_disprd,
output oitf_empty,
input clk,
input rst_n
);
wire [`E203_OITF_DEPTH-1:0] vld_set;
wire [`E203_OITF_DEPTH-1:0] vld_clr;
wire [`E203_OITF_DEPTH-1:0] vld_ena;
wire [`E203_OITF_DEPTH-1:0] vld_nxt;
wire [`E203_OITF_DEPTH-1:0] vld_r;
wire [`E203_OITF_DEPTH-1:0] rdwen_r;
wire [`E203_OITF_DEPTH-1:0] rdfpu_r;
wire [`E203_RFIDX_WIDTH-1:0] rdidx_r[`E203_OITF_DEPTH-1:0];
// The PC here is to be used at wback stage to track out the
// PC of exception of long-pipe instruction
wire [`E203_PC_SIZE-1:0] pc_r[`E203_OITF_DEPTH-1:0];
wire alc_ptr_ena = dis_ena;
wire ret_ptr_ena = ret_ena;
wire oitf_full ;
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_r;
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_r;
generate
if(`E203_OITF_DEPTH > 1) begin: depth_gt1//{
wire alc_ptr_flg_r;
wire alc_ptr_flg_nxt = ~alc_ptr_flg_r;
wire alc_ptr_flg_ena = (alc_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & alc_ptr_ena;
sirv_gnrl_dfflr #(1) alc_ptr_flg_dfflrs(alc_ptr_flg_ena, alc_ptr_flg_nxt, alc_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] alc_ptr_nxt;
assign alc_ptr_nxt = alc_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (alc_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) alc_ptr_dfflrs(alc_ptr_ena, alc_ptr_nxt, alc_ptr_r, clk, rst_n);
wire ret_ptr_flg_r;
wire ret_ptr_flg_nxt = ~ret_ptr_flg_r;
wire ret_ptr_flg_ena = (ret_ptr_r == ($unsigned(`E203_OITF_DEPTH-1))) & ret_ptr_ena;
sirv_gnrl_dfflr #(1) ret_ptr_flg_dfflrs(ret_ptr_flg_ena, ret_ptr_flg_nxt, ret_ptr_flg_r, clk, rst_n);
wire [`E203_ITAG_WIDTH-1:0] ret_ptr_nxt;
assign ret_ptr_nxt = ret_ptr_flg_ena ? `E203_ITAG_WIDTH'b0 : (ret_ptr_r + 1'b1);
sirv_gnrl_dfflr #(`E203_ITAG_WIDTH) ret_ptr_dfflrs(ret_ptr_ena, ret_ptr_nxt, ret_ptr_r, clk, rst_n);
assign oitf_empty = (ret_ptr_r == alc_ptr_r) & (ret_ptr_flg_r == alc_ptr_flg_r);
assign oitf_full = (ret_ptr_r == alc_ptr_r) & (~(ret_ptr_flg_r == alc_ptr_flg_r));
end//}
else begin: depth_eq1//}{
assign alc_ptr_r =1'b0;
assign ret_ptr_r =1'b0;
assign oitf_empty = ~vld_r[0];
assign oitf_full = vld_r[0];
end//}
endgenerate//}
assign ret_ptr = ret_ptr_r;
assign dis_ptr = alc_ptr_r;
////
//// // If the OITF is not full, or it is under retiring, then it is ready to accept new dispatch
//// assign dis_ready = (~oitf_full) | ret_ena;
// To cut down the loop between ALU write-back valid --> oitf_ret_ena --> oitf_ready ---> dispatch_ready --- > alu_i_valid
// we exclude the ret_ena from the ready signal
assign dis_ready = (~oitf_full);
wire [`E203_OITF_DEPTH-1:0] rd_match_rs1idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs2idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rs3idx;
wire [`E203_OITF_DEPTH-1:0] rd_match_rdidx;
genvar i;
generate //{
for (i=0; i<`E203_OITF_DEPTH; i=i+1) begin:oitf_entries//{
assign vld_set[i] = alc_ptr_ena & (alc_ptr_r == i);
assign vld_clr[i] = ret_ptr_ena & (ret_ptr_r == i);
assign vld_ena[i] = vld_set[i] | vld_clr[i];
assign vld_nxt[i] = vld_set[i] | (~vld_clr[i]);
sirv_gnrl_dfflr #(1) vld_dfflrs(vld_ena[i], vld_nxt[i], vld_r[i], clk, rst_n);
//Payload only set, no need to clear
sirv_gnrl_dffl #(`E203_RFIDX_WIDTH) rdidx_dfflrs(vld_set[i], disp_i_rdidx, rdidx_r[i], clk);
sirv_gnrl_dffl #(`E203_PC_SIZE ) pc_dfflrs (vld_set[i], disp_i_pc , pc_r[i] , clk);
sirv_gnrl_dffl #(1) rdwen_dfflrs(vld_set[i], disp_i_rdwen, rdwen_r[i], clk);
sirv_gnrl_dffl #(1) rdfpu_dfflrs(vld_set[i], disp_i_rdfpu, rdfpu_r[i], clk);
assign rd_match_rs1idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs1en & (rdfpu_r[i] == disp_i_rs1fpu) & (rdidx_r[i] == disp_i_rs1idx);
assign rd_match_rs2idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs2en & (rdfpu_r[i] == disp_i_rs2fpu) & (rdidx_r[i] == disp_i_rs2idx);
assign rd_match_rs3idx[i] = vld_r[i] & rdwen_r[i] & disp_i_rs3en & (rdfpu_r[i] == disp_i_rs3fpu) & (rdidx_r[i] == disp_i_rs3idx);
assign rd_match_rdidx [i] = vld_r[i] & rdwen_r[i] & disp_i_rdwen & (rdfpu_r[i] == disp_i_rdfpu ) & (rdidx_r[i] == disp_i_rdidx );
end//}
endgenerate//}
assign oitfrd_match_disprs1 = |rd_match_rs1idx;
assign oitfrd_match_disprs2 = |rd_match_rs2idx;
assign oitfrd_match_disprs3 = |rd_match_rs3idx;
assign oitfrd_match_disprd = |rd_match_rdidx ;
assign ret_rdidx = rdidx_r[ret_ptr];
assign ret_pc = pc_r [ret_ptr];
assign ret_rdwen = rdwen_r[ret_ptr];
assign ret_rdfpu = rdfpu_r[ret_ptr];
endmodule |
module sirv_clint_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_tiles_0_mtip,
output io_tiles_0_msip,
input io_rtcToggle
);
wire io_rtcToggle_r;
sirv_gnrl_dffr #(1) io_rtcToggle_dffr (io_rtcToggle, io_rtcToggle_r, clk, rst_n);
wire io_rtcToggle_edge = io_rtcToggle ^ io_rtcToggle_r;
wire io_rtcTick = io_rtcToggle_edge;
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [25:0] io_in_0_a_bits_address = i_icb_cmd_addr[25:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [25:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [25:0] io_in_0_c_bits_address = 26'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_clint u_sirv_clint(
.clock (clk ),
.reset (~rst_n ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_tiles_0_mtip (io_tiles_0_mtip),
.io_tiles_0_msip (io_tiles_0_msip),
.io_rtcTick (io_rtcTick )
);
endmodule |
module sirv_qspi_arbiter(
input clock,
input reset,
output io_inner_0_tx_ready,
input io_inner_0_tx_valid,
input [7:0] io_inner_0_tx_bits,
output io_inner_0_rx_valid,
output [7:0] io_inner_0_rx_bits,
input [7:0] io_inner_0_cnt,
input [1:0] io_inner_0_fmt_proto,
input io_inner_0_fmt_endian,
input io_inner_0_fmt_iodir,
input io_inner_0_cs_set,
input io_inner_0_cs_clear,
input io_inner_0_cs_hold,
output io_inner_0_active,
input io_inner_0_lock,
output io_inner_1_tx_ready,
input io_inner_1_tx_valid,
input [7:0] io_inner_1_tx_bits,
output io_inner_1_rx_valid,
output [7:0] io_inner_1_rx_bits,
input [7:0] io_inner_1_cnt,
input [1:0] io_inner_1_fmt_proto,
input io_inner_1_fmt_endian,
input io_inner_1_fmt_iodir,
input io_inner_1_cs_set,
input io_inner_1_cs_clear,
input io_inner_1_cs_hold,
output io_inner_1_active,
input io_inner_1_lock,
input io_outer_tx_ready,
output io_outer_tx_valid,
output [7:0] io_outer_tx_bits,
input io_outer_rx_valid,
input [7:0] io_outer_rx_bits,
output [7:0] io_outer_cnt,
output [1:0] io_outer_fmt_proto,
output io_outer_fmt_endian,
output io_outer_fmt_iodir,
output io_outer_cs_set,
output io_outer_cs_clear,
output io_outer_cs_hold,
input io_outer_active,
input io_sel
);
wire T_335_0;
wire T_335_1;
reg sel_0;
reg [31:0] GEN_4;
reg sel_1;
reg [31:0] GEN_5;
wire T_346;
wire T_349;
wire T_351;
wire T_352;
wire [7:0] T_354;
wire [7:0] T_356;
wire [7:0] T_358;
wire [7:0] T_359;
wire [7:0] T_361;
wire [7:0] T_363;
wire [7:0] T_365;
wire [7:0] T_366;
wire [2:0] T_367;
wire [3:0] T_368;
wire [3:0] T_370;
wire [2:0] T_371;
wire [3:0] T_372;
wire [3:0] T_374;
wire [3:0] T_379;
wire [1:0] T_384_proto;
wire T_384_endian;
wire T_384_iodir;
wire T_388;
wire T_389;
wire [1:0] T_390;
wire [1:0] T_391;
wire [2:0] T_392;
wire [2:0] T_394;
wire [1:0] T_395;
wire [2:0] T_396;
wire [2:0] T_398;
wire [2:0] T_406;
wire T_414_set;
wire T_414_clear;
wire T_414_hold;
wire T_421;
wire T_422;
wire T_423;
wire T_424;
wire T_425;
wire T_426;
wire T_427;
wire T_428;
wire T_429;
wire T_431;
wire nsel_0;
wire nsel_1;
wire T_445;
wire T_448;
wire T_450;
wire lock;
wire T_452;
wire [1:0] T_453;
wire [1:0] T_454;
wire T_455;
wire GEN_0;
wire GEN_1;
wire GEN_2;
wire GEN_3;
assign io_inner_0_tx_ready = T_424;
assign io_inner_0_rx_valid = T_425;
assign io_inner_0_rx_bits = io_outer_rx_bits;
assign io_inner_0_active = T_426;
assign io_inner_1_tx_ready = T_427;
assign io_inner_1_rx_valid = T_428;
assign io_inner_1_rx_bits = io_outer_rx_bits;
assign io_inner_1_active = T_429;
assign io_outer_tx_valid = T_352;
assign io_outer_tx_bits = T_359;
assign io_outer_cnt = T_366;
assign io_outer_fmt_proto = T_384_proto;
assign io_outer_fmt_endian = T_384_endian;
assign io_outer_fmt_iodir = T_384_iodir;
assign io_outer_cs_set = T_414_set;
assign io_outer_cs_clear = GEN_3;
assign io_outer_cs_hold = T_414_hold;
assign T_335_0 = 1'h1;
assign T_335_1 = 1'h0;
assign T_346 = sel_0 ? io_inner_0_tx_valid : 1'h0;
assign T_349 = sel_1 ? io_inner_1_tx_valid : 1'h0;
assign T_351 = T_346 | T_349;
assign T_352 = T_351;
assign T_354 = sel_0 ? io_inner_0_tx_bits : 8'h0;
assign T_356 = sel_1 ? io_inner_1_tx_bits : 8'h0;
assign T_358 = T_354 | T_356;
assign T_359 = T_358;
assign T_361 = sel_0 ? io_inner_0_cnt : 8'h0;
assign T_363 = sel_1 ? io_inner_1_cnt : 8'h0;
assign T_365 = T_361 | T_363;
assign T_366 = T_365;
assign T_367 = {io_inner_0_fmt_proto,io_inner_0_fmt_endian};
assign T_368 = {T_367,io_inner_0_fmt_iodir};
assign T_370 = sel_0 ? T_368 : 4'h0;
assign T_371 = {io_inner_1_fmt_proto,io_inner_1_fmt_endian};
assign T_372 = {T_371,io_inner_1_fmt_iodir};
assign T_374 = sel_1 ? T_372 : 4'h0;
assign T_379 = T_370 | T_374;
assign T_384_proto = T_390;
assign T_384_endian = T_389;
assign T_384_iodir = T_388;
assign T_388 = T_379[0];
assign T_389 = T_379[1];
assign T_390 = T_379[3:2];
assign T_391 = {io_inner_0_cs_set,io_inner_0_cs_clear};
assign T_392 = {T_391,io_inner_0_cs_hold};
assign T_394 = sel_0 ? T_392 : 3'h0;
assign T_395 = {io_inner_1_cs_set,io_inner_1_cs_clear};
assign T_396 = {T_395,io_inner_1_cs_hold};
assign T_398 = sel_1 ? T_396 : 3'h0;
assign T_406 = T_394 | T_398;
assign T_414_set = T_423;
assign T_414_clear = T_422;
assign T_414_hold = T_421;
assign T_421 = T_406[0];
assign T_422 = T_406[1];
assign T_423 = T_406[2];
assign T_424 = io_outer_tx_ready & sel_0;
assign T_425 = io_outer_rx_valid & sel_0;
assign T_426 = io_outer_active & sel_0;
assign T_427 = io_outer_tx_ready & sel_1;
assign T_428 = io_outer_rx_valid & sel_1;
assign T_429 = io_outer_active & sel_1;
assign T_431 = io_sel == 1'h0;
assign nsel_0 = T_431;
assign nsel_1 = io_sel;
assign T_445 = sel_0 ? io_inner_0_lock : 1'h0;
assign T_448 = sel_1 ? io_inner_1_lock : 1'h0;
assign T_450 = T_445 | T_448;
assign lock = T_450;
assign T_452 = lock == 1'h0;
assign T_453 = {sel_1,sel_0};
assign T_454 = {nsel_1,nsel_0};
assign T_455 = T_453 != T_454;
assign GEN_0 = T_455 ? 1'h1 : T_414_clear;
assign GEN_1 = T_452 ? nsel_0 : sel_0;
assign GEN_2 = T_452 ? nsel_1 : sel_1;
assign GEN_3 = T_452 ? GEN_0 : T_414_clear;
always @(posedge clock or posedge reset)
if (reset) begin
sel_0 <= T_335_0;
end else begin
if (T_452) begin
sel_0 <= nsel_0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sel_1 <= T_335_1;
end else begin
if (T_452) begin
sel_1 <= nsel_1;
end
end
endmodule |
module e203_exu_alu_muldiv(
input mdv_nob2b,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Issue Handshake Interface to MULDIV
//
input muldiv_i_valid, // Handshake valid
output muldiv_i_ready, // Handshake ready
input [`E203_XLEN-1:0] muldiv_i_rs1,
input [`E203_XLEN-1:0] muldiv_i_rs2,
input [`E203_XLEN-1:0] muldiv_i_imm,
input [`E203_DECINFO_MULDIV_WIDTH-1:0] muldiv_i_info,
input [`E203_ITAG_WIDTH-1:0] muldiv_i_itag,
output muldiv_i_longpipe,
input flush_pulse,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The MULDIV Write-Back/Commit Interface
output muldiv_o_valid, // Handshake valid
input muldiv_o_ready, // Handshake ready
output [`E203_XLEN-1:0] muldiv_o_wbck_wdat,
output muldiv_o_wbck_err,
// There is no exception cases for MULDIV, so no addtional cmt signals
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath, generate interface to ALU
//
// The operands and info to ALU
output [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_op1,
output [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_op2,
output muldiv_req_alu_add ,
output muldiv_req_alu_sub ,
input [`E203_MULDIV_ADDER_WIDTH-1:0] muldiv_req_alu_res,
// The Shared-Buffer interface to ALU-Shared-Buffer
output muldiv_sbf_0_ena,
output [33-1:0] muldiv_sbf_0_nxt,
input [33-1:0] muldiv_sbf_0_r,
output muldiv_sbf_1_ena,
output [33-1:0] muldiv_sbf_1_nxt,
input [33-1:0] muldiv_sbf_1_r,
input clk,
input rst_n
);
wire muldiv_i_hsked = muldiv_i_valid & muldiv_i_ready;
wire muldiv_o_hsked = muldiv_o_valid & muldiv_o_ready;
wire flushed_r;
wire flushed_set = flush_pulse;
wire flushed_clr = muldiv_o_hsked & (~flush_pulse);
wire flushed_ena = flushed_set | flushed_clr;
wire flushed_nxt = flushed_set | (~flushed_clr);
sirv_gnrl_dfflr #(1) flushed_dfflr (flushed_ena, flushed_nxt, flushed_r, clk, rst_n);
wire i_mul = muldiv_i_info[`E203_DECINFO_MULDIV_MUL ];// We treat this as signed X signed
wire i_mulh = muldiv_i_info[`E203_DECINFO_MULDIV_MULH ];
wire i_mulhsu = muldiv_i_info[`E203_DECINFO_MULDIV_MULHSU];
wire i_mulhu = muldiv_i_info[`E203_DECINFO_MULDIV_MULHU ];
wire i_div = muldiv_i_info[`E203_DECINFO_MULDIV_DIV ];
wire i_divu = muldiv_i_info[`E203_DECINFO_MULDIV_DIVU ];
wire i_rem = muldiv_i_info[`E203_DECINFO_MULDIV_REM ];
wire i_remu = muldiv_i_info[`E203_DECINFO_MULDIV_REMU ];
// If it is flushed then it is not back2back real case
wire i_b2b = muldiv_i_info[`E203_DECINFO_MULDIV_B2B ] & (~flushed_r) & (~mdv_nob2b);
wire back2back_seq = i_b2b;
wire mul_rs1_sign = (i_mulhu) ? 1'b0 : muldiv_i_rs1[`E203_XLEN-1];
wire mul_rs2_sign = (i_mulhsu | i_mulhu) ? 1'b0 : muldiv_i_rs2[`E203_XLEN-1];
wire [32:0] mul_op1 = {mul_rs1_sign, muldiv_i_rs1};
wire [32:0] mul_op2 = {mul_rs2_sign, muldiv_i_rs2};
wire i_op_mul = i_mul | i_mulh | i_mulhsu | i_mulhu;
wire i_op_div = i_div | i_divu | i_rem | i_remu;
/////////////////////////////////////////////////////////////////////////////////
// Implement the state machine for
// (1) The MUL instructions
// (2) The DIV instructions
localparam MULDIV_STATE_WIDTH = 3;
wire [MULDIV_STATE_WIDTH-1:0] muldiv_state_nxt;
wire [MULDIV_STATE_WIDTH-1:0] muldiv_state_r;
wire muldiv_state_ena;
// State 0: The 0th state, means this is the 1 cycle see the operand inputs
localparam MULDIV_STATE_0TH = 3'd0;
// State 1: Executing the instructions
localparam MULDIV_STATE_EXEC = 3'd1;
// State 2: Div check if need correction
localparam MULDIV_STATE_REMD_CHCK = 3'd2;
// State 3: Quotient correction
localparam MULDIV_STATE_QUOT_CORR = 3'd3;
// State 4: Reminder correction
localparam MULDIV_STATE_REMD_CORR = 3'd4;
wire [MULDIV_STATE_WIDTH-1:0] state_0th_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_exec_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_remd_chck_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_quot_corr_nxt;
wire [MULDIV_STATE_WIDTH-1:0] state_remd_corr_nxt;
wire state_0th_exit_ena;
wire state_exec_exit_ena;
wire state_remd_chck_exit_ena;
wire state_quot_corr_exit_ena;
wire state_remd_corr_exit_ena;
wire special_cases;
wire muldiv_i_valid_nb2b = muldiv_i_valid & (~back2back_seq) & (~special_cases);
// Define some common signals and reused later to save gatecounts
wire muldiv_sta_is_0th = (muldiv_state_r == MULDIV_STATE_0TH );
wire muldiv_sta_is_exec = (muldiv_state_r == MULDIV_STATE_EXEC );
wire muldiv_sta_is_remd_chck = (muldiv_state_r == MULDIV_STATE_REMD_CHCK );
wire muldiv_sta_is_quot_corr = (muldiv_state_r == MULDIV_STATE_QUOT_CORR );
wire muldiv_sta_is_remd_corr = (muldiv_state_r == MULDIV_STATE_REMD_CORR );
// **** If the current state is 0th,
// If a new instruction come (non back2back), next state is MULDIV_STATE_EXEC
assign state_0th_exit_ena = muldiv_sta_is_0th & muldiv_i_valid_nb2b & (~flush_pulse);
assign state_0th_nxt = MULDIV_STATE_EXEC;
// **** If the current state is exec,
wire div_need_corrct;
wire mul_exec_last_cycle;
wire div_exec_last_cycle;
wire exec_last_cycle;
assign state_exec_exit_ena = muldiv_sta_is_exec & ((
// If it is the last cycle (16th or 32rd cycles),
exec_last_cycle
// If it is div op, then jump to DIV_CHECK state
& (i_op_div ? 1'b1
// If it is not div-need-correction, then jump to 0th
: muldiv_o_hsked))
| flush_pulse);
assign state_exec_nxt =
(
flush_pulse ? MULDIV_STATE_0TH :
// If it is div op, then jump to DIV_CHECK state
i_op_div ? MULDIV_STATE_REMD_CHCK
// If it is not div-need-correction, then jump to 0th
: MULDIV_STATE_0TH
);
// **** If the current state is REMD_CHCK,
// If it is div-need-correction, then jump to QUOT_CORR state
// otherwise jump to the 0th
assign state_remd_chck_exit_ena = (muldiv_sta_is_remd_chck & (
// If it is div op, then jump to DIV_CHECK state
(div_need_corrct ? 1'b1
// If it is not div-need-correction, then jump to 0th
: muldiv_o_hsked)
| flush_pulse )) ;
assign state_remd_chck_nxt = flush_pulse ? MULDIV_STATE_0TH :
// If it is div-need-correction, then jump to QUOT_CORR state
div_need_corrct ? MULDIV_STATE_QUOT_CORR
// If it is not div-need-correction, then jump to 0th
: MULDIV_STATE_0TH;
// **** If the current state is QUOT_CORR,
// Always jump to REMD_CORR state
assign state_quot_corr_exit_ena = (muldiv_sta_is_quot_corr & (flush_pulse | 1'b1));
assign state_quot_corr_nxt = flush_pulse ? MULDIV_STATE_0TH : MULDIV_STATE_REMD_CORR;
// **** If the current state is REMD_CORR,
// Then jump to 0th
assign state_remd_corr_exit_ena = (muldiv_sta_is_remd_corr & (flush_pulse | muldiv_o_hsked));
assign state_remd_corr_nxt = flush_pulse ? MULDIV_STATE_0TH : MULDIV_STATE_0TH;
// The state will only toggle when each state is meeting the condition to exit
assign muldiv_state_ena = state_0th_exit_ena
| state_exec_exit_ena
| state_remd_chck_exit_ena
| state_quot_corr_exit_ena
| state_remd_corr_exit_ena;
// The next-state is onehot mux to select different entries
assign muldiv_state_nxt =
({MULDIV_STATE_WIDTH{state_0th_exit_ena }} & state_0th_nxt )
| ({MULDIV_STATE_WIDTH{state_exec_exit_ena }} & state_exec_nxt )
| ({MULDIV_STATE_WIDTH{state_remd_chck_exit_ena}} & state_remd_chck_nxt)
| ({MULDIV_STATE_WIDTH{state_quot_corr_exit_ena}} & state_quot_corr_nxt)
| ({MULDIV_STATE_WIDTH{state_remd_corr_exit_ena}} & state_remd_corr_nxt)
;
sirv_gnrl_dfflr #(MULDIV_STATE_WIDTH) muldiv_state_dfflr (muldiv_state_ena, muldiv_state_nxt, muldiv_state_r, clk, rst_n);
wire state_exec_enter_ena = muldiv_state_ena & (muldiv_state_nxt == MULDIV_STATE_EXEC);
localparam EXEC_CNT_W = 6;
localparam EXEC_CNT_1 = 6'd1 ;
localparam EXEC_CNT_16 = 6'd16;
localparam EXEC_CNT_32 = 6'd32;
wire[EXEC_CNT_W-1:0] exec_cnt_r;
wire exec_cnt_set = state_exec_enter_ena;
wire exec_cnt_inc = muldiv_sta_is_exec & (~exec_last_cycle);
wire exec_cnt_ena = exec_cnt_inc | exec_cnt_set;
// When set, the counter is set to 1, because the 0th state also counted as 0th cycle
wire[EXEC_CNT_W-1:0] exec_cnt_nxt = exec_cnt_set ? EXEC_CNT_1 : (exec_cnt_r + 1'b1);
sirv_gnrl_dfflr #(EXEC_CNT_W) exec_cnt_dfflr (exec_cnt_ena, exec_cnt_nxt, exec_cnt_r, clk, rst_n);
// The exec state is the last cycle when the exec_cnt_r is reaching the last cycle (16 or 32cycles)
wire cycle_0th = muldiv_sta_is_0th;
wire cycle_16th = (exec_cnt_r == EXEC_CNT_16);
wire cycle_32nd = (exec_cnt_r == EXEC_CNT_32);
assign mul_exec_last_cycle = cycle_16th;
assign div_exec_last_cycle = cycle_32nd;
assign exec_last_cycle = i_op_mul ? mul_exec_last_cycle : div_exec_last_cycle;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// Use booth-4 algorithm to conduct the multiplication
wire [32:0] part_prdt_hi_r;
wire [32:0] part_prdt_lo_r;
wire [32:0] part_prdt_hi_nxt;
wire [32:0] part_prdt_lo_nxt;
wire part_prdt_sft1_r;
wire [2:0] booth_code = cycle_0th ? {muldiv_i_rs1[1:0],1'b0}
: cycle_16th ? {mul_rs1_sign,part_prdt_lo_r[0],part_prdt_sft1_r}
: {part_prdt_lo_r[1:0],part_prdt_sft1_r};
//booth_code == 3'b000 = 0
//booth_code == 3'b001 = 1
//booth_code == 3'b010 = 1
//booth_code == 3'b011 = 2
//booth_code == 3'b100 = -2
//booth_code == 3'b101 = -1
//booth_code == 3'b110 = -1
//booth_code == 3'b111 = -0
wire booth_sel_zero = (booth_code == 3'b000) | (booth_code == 3'b111);
wire booth_sel_two = (booth_code == 3'b011) | (booth_code == 3'b100);
wire booth_sel_one = (~booth_sel_zero) & (~booth_sel_two);
wire booth_sel_sub = booth_code[2];
// 35 bits adder needed
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_res = muldiv_req_alu_res;
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_op2 =
({`E203_MULDIV_ADDER_WIDTH{booth_sel_zero}} & `E203_MULDIV_ADDER_WIDTH'b0)
| ({`E203_MULDIV_ADDER_WIDTH{booth_sel_one }} & {mul_rs2_sign,mul_rs2_sign,mul_rs2_sign,muldiv_i_rs2})
| ({`E203_MULDIV_ADDER_WIDTH{booth_sel_two }} & {mul_rs2_sign,mul_rs2_sign,muldiv_i_rs2,1'b0})
;
wire [`E203_MULDIV_ADDER_WIDTH-1:0] mul_exe_alu_op1 =
cycle_0th ? `E203_MULDIV_ADDER_WIDTH'b0 : {part_prdt_hi_r[32],part_prdt_hi_r[32],part_prdt_hi_r};
wire mul_exe_alu_add = (~booth_sel_sub);
wire mul_exe_alu_sub = booth_sel_sub;
assign part_prdt_hi_nxt = mul_exe_alu_res[34:2];
assign part_prdt_lo_nxt = {mul_exe_alu_res[1:0],
(cycle_0th ? {mul_rs1_sign,muldiv_i_rs1[31:2]} : part_prdt_lo_r[32:2])
};
wire part_prdt_sft1_nxt = cycle_0th ? muldiv_i_rs1[1] : part_prdt_lo_r[1];
wire mul_exe_cnt_set = exec_cnt_set & i_op_mul;
wire mul_exe_cnt_inc = exec_cnt_inc & i_op_mul;
wire part_prdt_hi_ena = mul_exe_cnt_set | mul_exe_cnt_inc | state_exec_exit_ena;
wire part_prdt_lo_ena = part_prdt_hi_ena;
sirv_gnrl_dfflr #(1) part_prdt_sft1_dfflr (part_prdt_lo_ena, part_prdt_sft1_nxt, part_prdt_sft1_r, clk, rst_n);
// This mul_res is not back2back case, so directly from the adder result
wire[`E203_XLEN-1:0] mul_res = i_mul ? part_prdt_lo_r[32:1] : mul_exe_alu_res[31:0];
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// The Divider Implementation, using the non-restoring signed division
wire [32:0] part_remd_r;
wire [32:0] part_quot_r;
wire div_rs1_sign = (i_divu | i_remu) ? 1'b0 : muldiv_i_rs1[`E203_XLEN-1];
wire div_rs2_sign = (i_divu | i_remu) ? 1'b0 : muldiv_i_rs2[`E203_XLEN-1];
wire [65:0] dividend = {{33{div_rs1_sign}}, div_rs1_sign, muldiv_i_rs1};
wire [33:0] divisor = {div_rs2_sign, div_rs2_sign, muldiv_i_rs2};
wire quot_0cycl = (dividend[65] ^ divisor[33]) ? 1'b0 : 1'b1;// If the sign(s0)!=sign(d), then set q_1st = -1
wire [66:0] dividend_lsft1 = {dividend[65:0],quot_0cycl};
wire prev_quot = cycle_0th ? quot_0cycl : part_quot_r[0];
wire part_remd_sft1_r;
// 34 bits adder needed
wire [33:0] div_exe_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_exe_alu_op1 = cycle_0th ? dividend_lsft1[66:33] : {part_remd_sft1_r, part_remd_r[32:0]};
wire [33:0] div_exe_alu_op2 = divisor;
wire div_exe_alu_add = (~prev_quot);
wire div_exe_alu_sub = prev_quot ;
wire current_quot = (div_exe_alu_res[33] ^ divisor[33]) ? 1'b0 : 1'b1;
wire [66:0] div_exe_part_remd;
assign div_exe_part_remd[66:33] = div_exe_alu_res;
assign div_exe_part_remd[32: 0] = cycle_0th ? dividend_lsft1[32:0] : part_quot_r[32:0];
wire [67:0] div_exe_part_remd_lsft1 = {div_exe_part_remd[66:0],current_quot};
wire part_remd_ena;
// Since the part_remd_r is only save 33bits (after left shifted), so the adder result MSB bit we need to save
// it here, which will be used at next round
sirv_gnrl_dfflr #(1) part_remd_sft1_dfflr (part_remd_ena, div_exe_alu_res[32], part_remd_sft1_r, clk, rst_n);
wire div_exe_cnt_set = exec_cnt_set & i_op_div;
wire div_exe_cnt_inc = exec_cnt_inc & i_op_div;
wire corrct_phase = muldiv_sta_is_remd_corr | muldiv_sta_is_quot_corr;
wire check_phase = muldiv_sta_is_remd_chck;
wire [33:0] div_quot_corr_alu_res;
wire [33:0] div_remd_corr_alu_res;
// Note: in last cycle, the reminder value is the non-shifted value
// but the quotient value is the shifted value, and last bit of quotient value is shifted always by 1
// If need corrective, the correct quot first, and then reminder, so reminder output as comb logic directly to
// save a cycle
wire [32:0] div_remd = check_phase ? part_remd_r [32:0]:
corrct_phase ? div_remd_corr_alu_res[32:0] :
div_exe_part_remd[65:33];
wire [32:0] div_quot = check_phase ? part_quot_r [32:0]:
corrct_phase ? part_quot_r [32:0]:
{div_exe_part_remd[31:0],1'b1};
// The partial reminder and quotient
wire [32:0] part_remd_nxt = corrct_phase ? div_remd_corr_alu_res[32:0] :
(muldiv_sta_is_exec & div_exec_last_cycle) ? div_remd :
div_exe_part_remd_lsft1[65:33];
wire [32:0] part_quot_nxt = corrct_phase ? div_quot_corr_alu_res[32:0] :
(muldiv_sta_is_exec & div_exec_last_cycle) ? div_quot :
div_exe_part_remd_lsft1[32: 0];
wire [33:0] div_remd_chck_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_remd_chck_alu_op1 = {part_remd_r[32], part_remd_r};
wire [33:0] div_remd_chck_alu_op2 = divisor;
wire div_remd_chck_alu_add = 1'b1;
wire div_remd_chck_alu_sub = 1'b0;
wire remd_is_0 = ~(|part_remd_r);
wire remd_is_neg_divs = ~(|div_remd_chck_alu_res);
wire remd_is_divs = (part_remd_r == divisor[32:0]);
assign div_need_corrct = i_op_div & (
((part_remd_r[32] ^ dividend[65]) & (~remd_is_0))
| remd_is_neg_divs
| remd_is_divs
);
wire remd_inc_quot_dec = (part_remd_r[32] ^ divisor[33]);
assign div_quot_corr_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_quot_corr_alu_op1 = {part_quot_r[32], part_quot_r};
wire [33:0] div_quot_corr_alu_op2 = 34'b1;
wire div_quot_corr_alu_add = (~remd_inc_quot_dec);
wire div_quot_corr_alu_sub = remd_inc_quot_dec;
assign div_remd_corr_alu_res = muldiv_req_alu_res[33:0];
wire [33:0] div_remd_corr_alu_op1 = {part_remd_r[32], part_remd_r};
wire [33:0] div_remd_corr_alu_op2 = divisor;
wire div_remd_corr_alu_add = remd_inc_quot_dec;
wire div_remd_corr_alu_sub = ~remd_inc_quot_dec;
// The partial reminder register will be loaded in the exe state, and in reminder correction cycle
assign part_remd_ena = div_exe_cnt_set | div_exe_cnt_inc | state_exec_exit_ena | state_remd_corr_exit_ena;
// The partial quotient register will be loaded in the exe state, and in quotient correction cycle
wire part_quot_ena = div_exe_cnt_set | div_exe_cnt_inc | state_exec_exit_ena | state_quot_corr_exit_ena;
wire[`E203_XLEN-1:0] div_res = (i_div | i_divu) ? div_quot[`E203_XLEN-1:0] : div_remd[`E203_XLEN-1:0];
wire div_by_0 = ~(|muldiv_i_rs2);// Divisor is all zeros
wire div_ovf = (i_div | i_rem) & (&muldiv_i_rs2) // Divisor is all ones, means -1
//Dividend is 10000...000, means -(2^xlen -1)
& muldiv_i_rs1[`E203_XLEN-1] & (~(|muldiv_i_rs1[`E203_XLEN-2:0]));
wire[`E203_XLEN-1:0] div_by_0_res_quot = ~`E203_XLEN'b0;
wire[`E203_XLEN-1:0] div_by_0_res_remd = dividend[`E203_XLEN-1:0];
wire[`E203_XLEN-1:0] div_by_0_res = (i_div | i_divu) ? div_by_0_res_quot : div_by_0_res_remd;
wire[`E203_XLEN-1:0] div_ovf_res_quot = {1'b1,{`E203_XLEN-1{1'b0}}};
wire[`E203_XLEN-1:0] div_ovf_res_remd = `E203_XLEN'b0;
wire[`E203_XLEN-1:0] div_ovf_res = (i_div | i_divu) ? div_ovf_res_quot : div_ovf_res_remd;
wire div_special_cases = i_op_div & (div_by_0 | div_ovf);
wire[`E203_XLEN-1:0] div_special_res = div_by_0 ? div_by_0_res : div_ovf_res;
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// Output generateion
assign special_cases = div_special_cases;// Only divider have special cases
wire[`E203_XLEN-1:0] special_res = div_special_res;// Only divider have special cases
// To detect the sequence of MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2
// To detect the sequence of DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2
wire [`E203_XLEN-1:0] back2back_mul_res = {part_prdt_lo_r[`E203_XLEN-2:0],part_prdt_sft1_r};// Only the MUL will be treated as back2back
wire [`E203_XLEN-1:0] back2back_mul_rem = part_remd_r[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] back2back_mul_div = part_quot_r[`E203_XLEN-1:0];
wire [`E203_XLEN-1:0] back2back_res = (
({`E203_XLEN{i_mul }} & back2back_mul_res)
| ({`E203_XLEN{i_rem | i_remu}} & back2back_mul_rem)
| ({`E203_XLEN{i_div | i_divu}} & back2back_mul_div)
);
// The output will be valid:
// * If it is back2back and sepcial cases, just directly pass out from input
// * If it is not back2back sequence when it is the last cycle of exec state
// (not div need correction) or last correct state;
wire wbck_condi = (back2back_seq | special_cases) ? 1'b1 :
(
(muldiv_sta_is_exec & exec_last_cycle & (~i_op_div))
| (muldiv_sta_is_remd_chck & (~div_need_corrct))
| muldiv_sta_is_remd_corr
);
assign muldiv_o_valid = wbck_condi & muldiv_i_valid;
assign muldiv_i_ready = wbck_condi & muldiv_o_ready;
wire res_sel_spl = special_cases;
wire res_sel_b2b = back2back_seq & (~special_cases);
wire res_sel_div = (~back2back_seq) & (~special_cases) & i_op_div;
wire res_sel_mul = (~back2back_seq) & (~special_cases) & i_op_mul;
assign muldiv_o_wbck_wdat =
({`E203_XLEN{res_sel_b2b}} & back2back_res)
| ({`E203_XLEN{res_sel_spl}} & special_res)
| ({`E203_XLEN{res_sel_div}} & div_res)
| ({`E203_XLEN{res_sel_mul}} & mul_res);
// There is no exception cases for MULDIV, so no addtional cmt signals
assign muldiv_o_wbck_err = 1'b0;
// The operands and info to ALU
wire req_alu_sel1 = i_op_mul;
wire req_alu_sel2 = i_op_div & (muldiv_sta_is_0th | muldiv_sta_is_exec);
wire req_alu_sel3 = i_op_div & muldiv_sta_is_quot_corr;
wire req_alu_sel4 = i_op_div & muldiv_sta_is_remd_corr;
wire req_alu_sel5 = i_op_div & muldiv_sta_is_remd_chck;
assign muldiv_req_alu_op1 =
({`E203_MULDIV_ADDER_WIDTH{req_alu_sel1}} & mul_exe_alu_op1 )
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel2}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_exe_alu_op1 })
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel3}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_quot_corr_alu_op1})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel4}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_corr_alu_op1})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel5}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_chck_alu_op1});
assign muldiv_req_alu_op2 =
({`E203_MULDIV_ADDER_WIDTH{req_alu_sel1}} & mul_exe_alu_op2 )
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel2}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_exe_alu_op2 })
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel3}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_quot_corr_alu_op2})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel4}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_corr_alu_op2})
| ({`E203_MULDIV_ADDER_WIDTH{req_alu_sel5}} & {{`E203_MULDIV_ADDER_WIDTH-34{1'b0}},div_remd_chck_alu_op2});
assign muldiv_req_alu_add =
(req_alu_sel1 & mul_exe_alu_add )
| (req_alu_sel2 & div_exe_alu_add )
| (req_alu_sel3 & div_quot_corr_alu_add)
| (req_alu_sel4 & div_remd_corr_alu_add)
| (req_alu_sel5 & div_remd_chck_alu_add);
assign muldiv_req_alu_sub =
(req_alu_sel1 & mul_exe_alu_sub )
| (req_alu_sel2 & div_exe_alu_sub )
| (req_alu_sel3 & div_quot_corr_alu_sub)
| (req_alu_sel4 & div_remd_corr_alu_sub)
| (req_alu_sel5 & div_remd_chck_alu_sub);
assign muldiv_sbf_0_ena = part_remd_ena | part_prdt_hi_ena;
assign muldiv_sbf_0_nxt = i_op_mul ? part_prdt_hi_nxt : part_remd_nxt;
assign muldiv_sbf_1_ena = part_quot_ena | part_prdt_lo_ena;
assign muldiv_sbf_1_nxt = i_op_mul ? part_prdt_lo_nxt : part_quot_nxt;
assign part_remd_r = muldiv_sbf_0_r;
assign part_quot_r = muldiv_sbf_1_r;
assign part_prdt_hi_r = muldiv_sbf_0_r;
assign part_prdt_lo_r = muldiv_sbf_1_r;
assign muldiv_i_longpipe = 1'b0;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////
// These below code are used for reference check with assertion
wire [31:0] golden0_mul_op1 = mul_op1[32] ? (~mul_op1[31:0]+1) : mul_op1[31:0];
wire [31:0] golden0_mul_op2 = mul_op2[32] ? (~mul_op2[31:0]+1) : mul_op2[31:0];
wire [63:0] golden0_mul_res_pre = golden0_mul_op1 * golden0_mul_op2;
wire [63:0] golden0_mul_res = (mul_op1[32]^mul_op2[32]) ? (~golden0_mul_res_pre + 1) : golden0_mul_res_pre;
wire [63:0] golden1_mul_res = $signed(mul_op1) * $signed(mul_op2);
// To check the signed * operation is really get what we wanted
CHECK_SIGNED_OP_CORRECT:
assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid)) ((golden0_mul_res == golden1_mul_res)))
else $fatal ("\n Error: Oops, This should never happen. \n");
wire [31:0] golden1_res_mul = golden1_mul_res[31:0];
wire [31:0] golden1_res_mulh = golden1_mul_res[63:32];
wire [31:0] golden1_res_mulhsu = golden1_mul_res[63:32];
wire [31:0] golden1_res_mulhu = golden1_mul_res[63:32];
wire [63:0] golden2_res_mul_SxS = $signed(muldiv_i_rs1) * $signed(muldiv_i_rs2);
wire [63:0] golden2_res_mul_SxU = $signed(muldiv_i_rs1) * $unsigned(muldiv_i_rs2);
wire [63:0] golden2_res_mul_UxS = $unsigned(muldiv_i_rs1) * $signed(muldiv_i_rs2);
wire [63:0] golden2_res_mul_UxU = $unsigned(muldiv_i_rs1) * $unsigned(muldiv_i_rs2);
wire [31:0] golden2_res_mul = golden2_res_mul_SxS[31:0];
wire [31:0] golden2_res_mulh = golden2_res_mul_SxS[63:32];
wire [31:0] golden2_res_mulhsu = golden2_res_mul_SxU[63:32];
wire [31:0] golden2_res_mulhu = golden2_res_mul_UxU[63:32];
// To check four different combination will all generate same lower 32bits result
CHECK_FOUR_COMB_SAME_RES:
assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid))
(golden2_res_mul_SxS[31:0] == golden2_res_mul_SxU[31:0])
& (golden2_res_mul_UxS[31:0] == golden2_res_mul_UxU[31:0])
& (golden2_res_mul_SxU[31:0] == golden2_res_mul_UxS[31:0])
)
else $fatal ("\n Error: Oops, This should never happen. \n");
// Seems the golden2 result is not correct in case of mulhsu, so have to comment it out
// // To check golden1 and golden2 result are same
// CHECK_GOLD1_AND_GOLD2_SAME:
// assert property (@(posedge clk) disable iff ((~rst_n) | (~muldiv_o_valid))
// (i_mul ? (golden1_res_mul == golden2_res_mul ) : 1'b1)
// &(i_mulh ? (golden1_res_mulh == golden2_res_mulh ) : 1'b1)
// &(i_mulhsu ? (golden1_res_mulhsu == golden2_res_mulhsu) : 1'b1)
// &(i_mulhu ? (golden1_res_mulhu == golden2_res_mulhu ) : 1'b1)
// )
// else $fatal ("\n Error: Oops, This should never happen. \n");
// The special case will need to be handled specially
wire [32:0] golden_res_div = div_special_cases ? div_special_res :
( $signed({div_rs1_sign,muldiv_i_rs1}) / ((div_by_0 | div_ovf) ? 1 : $signed({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_divu = div_special_cases ? div_special_res :
($unsigned({div_rs1_sign,muldiv_i_rs1}) / ((div_by_0 | div_ovf) ? 1 : $unsigned({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_rem = div_special_cases ? div_special_res :
( $signed({div_rs1_sign,muldiv_i_rs1}) % ((div_by_0 | div_ovf) ? 1 : $signed({div_rs2_sign,muldiv_i_rs2})));
wire [32:0] golden_res_remu = div_special_cases ? div_special_res :
($unsigned({div_rs1_sign,muldiv_i_rs1}) % ((div_by_0 | div_ovf) ? 1 : $unsigned({div_rs2_sign,muldiv_i_rs2})));
// To check golden and actual result are same
wire [`E203_XLEN-1:0] golden_res =
i_mul ? golden1_res_mul :
i_mulh ? golden1_res_mulh :
i_mulhsu ? golden1_res_mulhsu :
i_mulhu ? golden1_res_mulhu :
i_div ? golden_res_div [31:0] :
i_divu ? golden_res_divu[31:0] :
i_rem ? golden_res_rem [31:0] :
i_remu ? golden_res_remu[31:0] :
`E203_XLEN'b0;
CHECK_GOLD_AND_ACTUAL_SAME:
// Since the printed value is not aligned with posedge clock, so change it to negetive
assert property (@(negedge clk) disable iff ((~rst_n) | flush_pulse)
(muldiv_o_valid ? (golden_res == muldiv_o_wbck_wdat ) : 1'b1)
)
else begin
$display("??????????????????????????????????????????");
$display("??????????????????????????????????????????");
$display("{i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu}=%d%d%d%d%d%d%d%d",i_mul,i_mulh,i_mulhsu,i_mulhu,i_div,i_divu,i_rem,i_remu);
$display("muldiv_i_rs1=%h\nmuldiv_i_rs2=%h\n",muldiv_i_rs1,muldiv_i_rs2);
$display("golden_res=%h\nmuldiv_o_wbck_wdat=%h",golden_res,muldiv_o_wbck_wdat);
$display("??????????????????????????????????????????");
$fatal ("\n Error: Oops, This should never happen. \n");
end
//synopsys translate_on
`endif//}
`endif//}
endmodule |
module e203_subsys_plic(
input plic_icb_cmd_valid,
output plic_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
input plic_icb_cmd_read,
input [`E203_XLEN-1:0] plic_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
output plic_icb_rsp_valid,
input plic_icb_rsp_ready,
output plic_icb_rsp_err,
output [`E203_XLEN-1:0] plic_icb_rsp_rdata,
output plic_ext_irq,
input wdg_irq_a,
input rtc_irq_a,
input qspi0_irq,
input qspi1_irq,
input qspi2_irq,
input uart0_irq,
input uart1_irq,
input pwm0_irq_0,
input pwm0_irq_1,
input pwm0_irq_2,
input pwm0_irq_3,
input pwm1_irq_0,
input pwm1_irq_1,
input pwm1_irq_2,
input pwm1_irq_3,
input pwm2_irq_0,
input pwm2_irq_1,
input pwm2_irq_2,
input pwm2_irq_3,
input i2c_mst_irq,
input gpio_irq_0,
input gpio_irq_1,
input gpio_irq_2,
input gpio_irq_3,
input gpio_irq_4,
input gpio_irq_5,
input gpio_irq_6,
input gpio_irq_7,
input gpio_irq_8,
input gpio_irq_9,
input gpio_irq_10,
input gpio_irq_11,
input gpio_irq_12,
input gpio_irq_13,
input gpio_irq_14,
input gpio_irq_15,
input gpio_irq_16,
input gpio_irq_17,
input gpio_irq_18,
input gpio_irq_19,
input gpio_irq_20,
input gpio_irq_21,
input gpio_irq_22,
input gpio_irq_23,
input gpio_irq_24,
input gpio_irq_25,
input gpio_irq_26,
input gpio_irq_27,
input gpio_irq_28,
input gpio_irq_29,
input gpio_irq_30,
input gpio_irq_31,
input clk,
input rst_n
);
assign plic_icb_rsp_err = 1'b0;
wire wdg_irq_r;
wire rtc_irq_r;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_rtc_irq_sync(
.din_a (rtc_irq_a),
.dout (rtc_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_wdg_irq_sync(
.din_a (wdg_irq_a),
.dout (wdg_irq_r),
.clk (clk ),
.rst_n (rst_n)
);
wire plic_irq_i_0 = wdg_irq_r;
wire plic_irq_i_1 = rtc_irq_r;
wire plic_irq_i_2 = uart0_irq;
wire plic_irq_i_3 = uart1_irq;
wire plic_irq_i_4 = qspi0_irq;
wire plic_irq_i_5 = qspi1_irq;
wire plic_irq_i_6 = qspi2_irq;
wire plic_irq_i_7 = gpio_irq_0 ;
wire plic_irq_i_8 = gpio_irq_1 ;
wire plic_irq_i_9 = gpio_irq_2 ;
wire plic_irq_i_10 = gpio_irq_3 ;
wire plic_irq_i_11 = gpio_irq_4 ;
wire plic_irq_i_12 = gpio_irq_5 ;
wire plic_irq_i_13 = gpio_irq_6 ;
wire plic_irq_i_14 = gpio_irq_7 ;
wire plic_irq_i_15 = gpio_irq_8 ;
wire plic_irq_i_16 = gpio_irq_9 ;
wire plic_irq_i_17 = gpio_irq_10;
wire plic_irq_i_18 = gpio_irq_11;
wire plic_irq_i_19 = gpio_irq_12;
wire plic_irq_i_20 = gpio_irq_13;
wire plic_irq_i_21 = gpio_irq_14;
wire plic_irq_i_22 = gpio_irq_15;
wire plic_irq_i_23 = gpio_irq_16;
wire plic_irq_i_24 = gpio_irq_17;
wire plic_irq_i_25 = gpio_irq_18;
wire plic_irq_i_26 = gpio_irq_19;
wire plic_irq_i_27 = gpio_irq_20;
wire plic_irq_i_28 = gpio_irq_21;
wire plic_irq_i_29 = gpio_irq_22;
wire plic_irq_i_30 = gpio_irq_23;
wire plic_irq_i_31 = gpio_irq_24;
wire plic_irq_i_32 = gpio_irq_25;
wire plic_irq_i_33 = gpio_irq_26;
wire plic_irq_i_34 = gpio_irq_27;
wire plic_irq_i_35 = gpio_irq_28;
wire plic_irq_i_36 = gpio_irq_29;
wire plic_irq_i_37 = gpio_irq_30;
wire plic_irq_i_38 = gpio_irq_31;
wire plic_irq_i_39 = pwm0_irq_0;
wire plic_irq_i_40 = pwm0_irq_1;
wire plic_irq_i_41 = pwm0_irq_2;
wire plic_irq_i_42 = pwm0_irq_3;
wire plic_irq_i_43 = pwm1_irq_0;
wire plic_irq_i_44 = pwm1_irq_1;
wire plic_irq_i_45 = pwm1_irq_2;
wire plic_irq_i_46 = pwm1_irq_3;
wire plic_irq_i_47 = pwm2_irq_0;
wire plic_irq_i_48 = pwm2_irq_1;
wire plic_irq_i_49 = pwm2_irq_2;
wire plic_irq_i_50 = pwm2_irq_3;
wire plic_irq_i_51 = i2c_mst_irq;
sirv_plic_top u_sirv_plic_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (plic_icb_cmd_valid),
.i_icb_cmd_ready (plic_icb_cmd_ready),
.i_icb_cmd_addr (plic_icb_cmd_addr ),
.i_icb_cmd_read (plic_icb_cmd_read ),
.i_icb_cmd_wdata (plic_icb_cmd_wdata),
.i_icb_rsp_valid (plic_icb_rsp_valid),
.i_icb_rsp_ready (plic_icb_rsp_ready),
.i_icb_rsp_rdata (plic_icb_rsp_rdata),
.io_devices_0_0 (plic_irq_i_0 ),
.io_devices_0_1 (plic_irq_i_1 ),
.io_devices_0_2 (plic_irq_i_2 ),
.io_devices_0_3 (plic_irq_i_3 ),
.io_devices_0_4 (plic_irq_i_4 ),
.io_devices_0_5 (plic_irq_i_5 ),
.io_devices_0_6 (plic_irq_i_6 ),
.io_devices_0_7 (plic_irq_i_7 ),
.io_devices_0_8 (plic_irq_i_8 ),
.io_devices_0_9 (plic_irq_i_9 ),
.io_devices_0_10 (plic_irq_i_10),
.io_devices_0_11 (plic_irq_i_11),
.io_devices_0_12 (plic_irq_i_12),
.io_devices_0_13 (plic_irq_i_13),
.io_devices_0_14 (plic_irq_i_14),
.io_devices_0_15 (plic_irq_i_15),
.io_devices_0_16 (plic_irq_i_16),
.io_devices_0_17 (plic_irq_i_17),
.io_devices_0_18 (plic_irq_i_18),
.io_devices_0_19 (plic_irq_i_19),
.io_devices_0_20 (plic_irq_i_20),
.io_devices_0_21 (plic_irq_i_21),
.io_devices_0_22 (plic_irq_i_22),
.io_devices_0_23 (plic_irq_i_23),
.io_devices_0_24 (plic_irq_i_24),
.io_devices_0_25 (plic_irq_i_25),
.io_devices_0_26 (plic_irq_i_26),
.io_devices_0_27 (plic_irq_i_27),
.io_devices_0_28 (plic_irq_i_28),
.io_devices_0_29 (plic_irq_i_29),
.io_devices_0_30 (plic_irq_i_30),
.io_devices_0_31 (plic_irq_i_31),
.io_devices_0_32 (plic_irq_i_32),
.io_devices_0_33 (plic_irq_i_33),
.io_devices_0_34 (plic_irq_i_34),
.io_devices_0_35 (plic_irq_i_35),
.io_devices_0_36 (plic_irq_i_36),
.io_devices_0_37 (plic_irq_i_37),
.io_devices_0_38 (plic_irq_i_38),
.io_devices_0_39 (plic_irq_i_39),
.io_devices_0_40 (plic_irq_i_40),
.io_devices_0_41 (plic_irq_i_41),
.io_devices_0_42 (plic_irq_i_42),
.io_devices_0_43 (plic_irq_i_43),
.io_devices_0_44 (plic_irq_i_44),
.io_devices_0_45 (plic_irq_i_45),
.io_devices_0_46 (plic_irq_i_46),
.io_devices_0_47 (plic_irq_i_47),
.io_devices_0_48 (plic_irq_i_48),
.io_devices_0_49 (plic_irq_i_49),
.io_devices_0_50 (plic_irq_i_50),
.io_devices_0_51 (plic_irq_i_51),
.io_harts_0_0 (plic_ext_irq )
);
endmodule |
module e203_dtcm_ctrl(
output dtcm_active,
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 1
// // This register is our self-defined CSR register to disable the
// DTCM SRAM clock gating for debugging purpose
input tcm_cgstop,
// Note: the DTCM ICB interface only support the single-transaction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// LSU ICB to DTCM
// * Bus cmd channel
input lsu2dtcm_icb_cmd_valid, // Handshake valid
output lsu2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr, // Bus transaction start addr
input lsu2dtcm_icb_cmd_read, // Read or write
input [32-1:0] lsu2dtcm_icb_cmd_wdata,
input [4-1:0] lsu2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output lsu2dtcm_icb_rsp_valid, // Response valid
input lsu2dtcm_icb_rsp_ready, // Response ready
output lsu2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] lsu2dtcm_icb_rsp_rdata,
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid, // Handshake valid
output ext2dtcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr, // Bus transaction start addr
input ext2dtcm_icb_cmd_read, // Read or write
input [32-1:0] ext2dtcm_icb_cmd_wdata,
input [ 4-1:0] ext2dtcm_icb_cmd_wmask,
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid, // Response valid
input ext2dtcm_icb_rsp_ready, // Response ready
output ext2dtcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
output [32-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
input test_mode,
input clk,
input rst_n
);
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] arbt_icb_cmd_wmask;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire [`E203_DTCM_DATA_WIDTH-1:0] arbt_icb_rsp_rdata;
`ifdef E203_HAS_DTCM_EXTITF //{
localparam DTCM_ARBT_I_NUM = 2;
localparam DTCM_ARBT_I_PTR_W = 1;
`else//}{
localparam DTCM_ARBT_I_NUM = 1;
localparam DTCM_ARBT_I_PTR_W = 1;
`endif//}
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_ADDR_WIDTH-1:0] arbt_bus_icb_cmd_addr;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_cmd_wdata;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_WMSK_WIDTH-1:0] arbt_bus_icb_cmd_wmask;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [DTCM_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [DTCM_ARBT_I_NUM*`E203_DTCM_DATA_WIDTH-1:0] arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_cmd_valid =
//LSU take higher priority
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_valid,
`endif//}
lsu2dtcm_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_addr,
`endif//}
lsu2dtcm_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_read,
`endif//}
lsu2dtcm_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wdata,
`endif//}
lsu2dtcm_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_wmask,
`endif//}
lsu2dtcm_icb_cmd_wmask
} ;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_cmd_ready,
`endif//}
lsu2dtcm_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_valid,
`endif//}
lsu2dtcm_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_err,
`endif//}
lsu2dtcm_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_rdata,
`endif//}
lsu2dtcm_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_DTCM_EXTITF //{
ext2dtcm_icb_rsp_ready,
`endif//}
lsu2dtcm_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because for ITCM and DTCM,
// Dcache, .etc, definitely they cannot reponse as 0 cycle
.FIFO_OUTS_NUM (`E203_DTCM_OUTS_NUM),
.FIFO_CUT_READY(0),
.USR_W (1),
.ARBT_NUM (DTCM_ARBT_I_NUM ),
.ARBT_PTR_W (DTCM_ARBT_I_PTR_W),
.AW (`E203_DTCM_ADDR_WIDTH),
.DW (`E203_DTCM_DATA_WIDTH)
) u_dtcm_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst () ,
.o_icb_cmd_beat () ,
.o_icb_cmd_lock () ,
.o_icb_cmd_excl () ,
.o_icb_cmd_size () ,
.o_icb_cmd_usr () ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0),
.o_icb_rsp_excl_ok (1'b0),
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_beat ({2*DTCM_ARBT_I_NUM{1'b0}}) ,
.i_bus_icb_cmd_lock ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_excl ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_size ({2*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_cmd_usr ({1*DTCM_ARBT_I_NUM{1'b0}}),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr (),
.i_bus_icb_rsp_excl_ok (),
.clk (clk ) ,
.rst_n (rst_n)
);
wire sram_icb_cmd_ready;
wire sram_icb_cmd_valid;
wire [`E203_DTCM_ADDR_WIDTH-1:0] sram_icb_cmd_addr;
wire sram_icb_cmd_read;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_cmd_wdata;
wire [`E203_DTCM_WMSK_WIDTH-1:0] sram_icb_cmd_wmask;
assign arbt_icb_cmd_ready = sram_icb_cmd_ready;
assign sram_icb_cmd_valid = arbt_icb_cmd_valid;
assign sram_icb_cmd_addr = arbt_icb_cmd_addr;
assign sram_icb_cmd_read = arbt_icb_cmd_read;
assign sram_icb_cmd_wdata = arbt_icb_cmd_wdata;
assign sram_icb_cmd_wmask = arbt_icb_cmd_wmask;
wire sram_icb_rsp_valid;
wire sram_icb_rsp_ready;
wire [`E203_DTCM_DATA_WIDTH-1:0] sram_icb_rsp_rdata;
wire sram_icb_rsp_err;
wire dtcm_sram_ctrl_active;
wire sram_icb_rsp_read;
`ifndef E203_HAS_ECC //{
sirv_sram_icb_ctrl #(
.DW (`E203_DTCM_DATA_WIDTH),
.AW (`E203_DTCM_ADDR_WIDTH),
.MW (`E203_DTCM_WMSK_WIDTH),
.AW_LSB (2),// DTCM is 32bits wide, so the LSB is 2
.USR_W (1)
) u_sram_icb_ctrl (
.sram_ctrl_active (dtcm_sram_ctrl_active),
.tcm_cgstop (tcm_cgstop),
.i_icb_cmd_valid (sram_icb_cmd_valid),
.i_icb_cmd_ready (sram_icb_cmd_ready),
.i_icb_cmd_read (sram_icb_cmd_read ),
.i_icb_cmd_addr (sram_icb_cmd_addr ),
.i_icb_cmd_wdata (sram_icb_cmd_wdata),
.i_icb_cmd_wmask (sram_icb_cmd_wmask),
.i_icb_cmd_usr (sram_icb_cmd_read ),
.i_icb_rsp_valid (sram_icb_rsp_valid),
.i_icb_rsp_ready (sram_icb_rsp_ready),
.i_icb_rsp_rdata (sram_icb_rsp_rdata),
.i_icb_rsp_usr (sram_icb_rsp_read),
.ram_cs (dtcm_ram_cs ),
.ram_we (dtcm_ram_we ),
.ram_addr (dtcm_ram_addr),
.ram_wem (dtcm_ram_wem ),
.ram_din (dtcm_ram_din ),
.ram_dout (dtcm_ram_dout),
.clk_ram (clk_dtcm_ram ),
.test_mode(test_mode ),
.clk (clk ),
.rst_n(rst_n)
);
assign sram_icb_rsp_err = 1'b0;
`endif//}
assign sram_icb_rsp_ready = arbt_icb_rsp_ready;
assign arbt_icb_rsp_valid = sram_icb_rsp_valid;
assign arbt_icb_rsp_err = sram_icb_rsp_err;
assign arbt_icb_rsp_rdata = sram_icb_rsp_rdata;
assign dtcm_active = lsu2dtcm_icb_cmd_valid | dtcm_sram_ctrl_active
`ifdef E203_HAS_DTCM_EXTITF //{
| ext2dtcm_icb_cmd_valid
`endif//}
;
endmodule |
module reset_sys (
input slowest_sync_clk,
input ext_reset_in,
input aux_reset_in,//Not used
input mb_debug_sys_rst,//Not used
input dcm_locked,
output mb_reset,// Not used
output bus_struct_reset,// Not used
output peripheral_reset,
output interconnect_aresetn,// Not used
output peripheral_aresetn// Not used
);
wire clk = slowest_sync_clk;
wire rst_n = ext_reset_in;
reg record_rst_r;
// When the peripheral_reset is really asserted, then we can clear the record rst
wire record_rst_clr = peripheral_reset;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
record_rst_r <= 1'b1;
end
else if (record_rst_clr) begin
record_rst_r <= 1'b0;
end
end
reg gen_rst_r;
// When the locked and the record_rst is there, then we assert the gen_rst
wire gen_rst_set = dcm_locked & record_rst_r;
// When the gen_rst asserted with max cycles, then we de-assert it
wire gen_rst_cnt_is_max;
wire gen_rst_clr = gen_rst_r & gen_rst_cnt_is_max;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
gen_rst_r <= 1'b0;
end
else if (gen_rst_set) begin
gen_rst_r <= 1'b1;
end
else if (gen_rst_clr) begin
gen_rst_r <= 1'b0;
end
end
assign peripheral_reset = gen_rst_r;
reg[9:0] gen_rst_cnt_r;
// When the gen_rst is asserted, it need to be clear
wire gen_rst_cnt_clr = gen_rst_set;
// When the gen_rst is asserted, and the counter is not reach the max value
wire gen_rst_cnt_inc = gen_rst_r & (~gen_rst_cnt_is_max);
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
gen_rst_cnt_r <= 10'b0;
end
else if (gen_rst_cnt_clr) begin
gen_rst_cnt_r <= 10'b0;
end
else if (gen_rst_cnt_inc) begin
gen_rst_cnt_r <= gen_rst_cnt_r + 1'b1;
end
end
assign gen_rst_cnt_is_max = (gen_rst_cnt_r == 10'd256);
endmodule |
module riscv_pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
riscv_pll_0002 riscv_pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule |
module riscv_ram32 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [7:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input rden;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule |
module riscv_ram64 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [12:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input rden;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module riscv_ram32 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [7:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input rden;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule |
module riscv_ram64 (
address,
byteena,
clock,
data,
rden,
wren,
q);
input [12:0] address;
input [7:0] byteena;
input clock;
input [63:0] data;
input rden;
input wren;
output [63:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [7:0] byteena;
tri1 clock;
tri1 rden;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.rden_a (rden),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "./software/led_blink_itcm.rif"
`else
altsyncram_component.init_file = "./software/led_blink_itcm.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 8192,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 13,
altsyncram_component.width_a = 64,
altsyncram_component.width_byteena_a = 8;
endmodule |
module riscv_pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("16.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("8.387096 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule |
module priority_encoder(
input [7:0]in,
output reg [2:0]out);
always @(*)
begin
if(in[7]==1) out=3'b111;
else if(in[6]==1) out=3'b110;
else if(in[5]==1) out=3'b101;
else if(in[4]==1) out=3'b100;
else if(in[3]==1) out=3'b011;
else if(in[2]==1) out=3'b010;
else if(in[1]==1) out=3'b001;
else out=3'b000;
end
endmodule |
module test_bench;
reg [7:0]in;
wire [2:0]out;
priority_encoder dut(in, out);
always
begin
in= $random;
#10;
end
initial
begin $monitor("in: %b out: %b",in, out);
#100 $finish;
end
endmodule |
module lfsr (
input clk, reset,
output [7:0] lfsr_out
);
reg [7:0] data;
always @(posedge clk) begin
if (reset)
data <= 8'hff;
else
data <= {data[6:0], data[7] ^ data[5] ^ data[3] ^ data[1]};
end
assign lfsr_out = data;
endmodule |
module test_bench;
reg clk, reset;
wire [7:0] lfsr_out;
lfsr dut(clk, reset, lfsr_out);
initial begin
clk = 0;
reset = 1;
#10 reset = 0;
end
always #5 clk = ~clk;
initial begin
$monitor("\t\t clk: %b lfsr_out: %b", clk, lfsr_out);
#115 $finish;
end
endmodule |
module test_bench;
reg [3:0] bcd_in;
wire [3:0] excess3_out;
BCD2excess3 dut(bcd_in, excess3_out);
always begin
bcd_in= 4'd0;
#10;
bcd_in= 4'd1;
#10;
bcd_in= 4'd2;
#10;
bcd_in= 4'd3;
#10;
bcd_in= 4'd4;
#10;
bcd_in= 4'd5;
#10;
bcd_in= 4'd6;
#10;
bcd_in= 4'd7;
#10;
bcd_in= 4'd8;
#10;
bcd_in= 4'd9;
#10;
bcd_in= 4'd10;
#10;
bcd_in= 4'd11;
#10;
bcd_in= 4'd12;
#10;
bcd_in= 4'd13;
#10;
bcd_in= 4'd14;
#10;
bcd_in= 4'd15;
#10;
end
initial begin
$monitor("Input: %b Excess-3 Code: %b", bcd_in, excess3_out);
#160 $finish;
end
endmodule |
module BCD2excess3(
input [3:0] bcd_in,
output reg [3:0] excess3_out
);
always@(bcd_in)
begin
case(bcd_in)
4'b0000 : excess3_out = 4'b0011;
4'b0001 : excess3_out = 4'b0100;
4'b0010 : excess3_out = 4'b0101;
4'b0011 : excess3_out = 4'b0110;
4'b0100 : excess3_out = 4'b0111;
4'b0101 : excess3_out = 4'b1000;
4'b0110 : excess3_out = 4'b1001;
4'b0111 : excess3_out = 4'b1010;
4'b1000 : excess3_out = 4'b1011;
4'b1001 : excess3_out = 4'b1100;
default : excess3_out = 4'bxxxx;
endcase
end
endmodule |
module test_bench;
reg [3:0] a;
reg [3:0] b;
reg en;
wire [3:0] sdout;
wire cbout;
add_sub dut(a, b, en, sdout, cbout);
initial begin
a = 4'b1010;
b = 4'b0101;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b0100;
b = 4'b0111;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b1001;
b = 4'b1111;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
a = 4'b0101;
b = 4'b1101;
en = 1'b0;
#10;
$display("a= %b b= %b sum = %b, carry = %b", a, b,sdout, cbout);
en = 1'b1;
#10;
$display("a= %b b= %b difference = %b, borrow = %b", a, b, sdout, cbout);
$finish;
end
endmodule |
module add_sub(
input [3:0] A, B,
input en,
output [3:0] sdout,
output cbout
);
wire [2:0]c;
full_adder fa1(A[0], (B[0]^en), en, sdout[0], c[0]);
full_adder fa2(A[1], (B[1]^en), c[0], sdout[1], c[1]);
full_adder fa3(A[2], (B[2]^en), c[1], sdout[2], c[2]);
full_adder fa4(A[3], (B[3]^en), c[2], sdout[3], cbout);
endmodule |
module test_bench;
reg [7:0] in;
wire [2:0] out;
encoder_8_3 dut(in, out);
initial
begin
#0 in=8'b10000000;
#10 in=8'b01000000;
#10 in=8'b00100000;
#10 in=8'b00010000;
#10 in=8'b00001000;
#10 in=8'b00000100;
#10 in=8'b00000010;
#10 in=8'b00000001;
#10 in=8'b00000000;
end
initial
begin $monitor("in: %b out: %b ",in, out);
#90 $finish;
end
endmodule |
module synchronous_asynchronous_reset(
input clk,rst,in,
output reg out_async,out_sync
);
////////// SYNCHRONOUS RESET //////////
always@(posedge clk)
begin
if(rst) out_sync<= 1'b0;
else out_sync <= in;
end
////////// ASYNCHRONOUS RESET /////////
always@(posedge clk, posedge rst)
begin
if(rst) out_async<= 1'b0;
else out_async <= in;
end
endmodule |
module test_bench;
reg clk, rst, in;
wire out_async,out_sync;
synchronous_asynchronous_reset dut(clk, rst, in, out_async, out_sync);
initial begin
clk= 0; rst= 0; in= 1;
end
initial forever #130 clk<= ~clk;
initial forever #450 rst<= ~rst;
initial forever #400 in<= ~in;
initial #6000 $stop;
endmodule |
module BCD_to_7segment(
input [3:0]BCD,
output [6:0]segment7
);
wire a,b,c,d,e,f,g;
assign a = BCD[3] | BCD[1] | (BCD[2]~^BCD[0]);
assign b = (~BCD[2])| (BCD[1]~^BCD[0]);
assign c = BCD[2] | (~BCD[1]) | (BCD[0]);
assign d = BCD[3] | ((~BCD[2])&(~BCD[0])) | ((~BCD[2])&BCD[1]) | (BCD[1]&(~BCD[0])) | (BCD[2]&(~BCD[1])&BCD[0]);
assign e = ~BCD[0]&(~BCD[2]|BCD[1]);
assign f = BCD[3] | (BCD[2]&(~BCD[1]|~BCD[0])) | ((~BCD[1])&(~BCD[0]));
assign g = BCD[3] | (BCD[2]&(~BCD[1])) | (BCD[1]&(~BCD[2]|~BCD[0]));
assign segment7= {a,b,c,d,e,f,g};
endmodule |
module test_bench;
reg [3:0]BCD;
wire [6:0]segment7;
BCD_to_7segment dut(BCD, segment7);
always begin
BCD= 4'd0;
#10;
BCD= 4'd1;
#10;
BCD= 4'd2;
#10;
BCD= 4'd3;
#10;
BCD= 4'd4;
#10;
BCD= 4'd5;
#10;
BCD= 4'd6;
#10;
BCD= 4'd7;
#10;
BCD= 4'd8;
#10;
BCD= 4'd9;
#10;
end
initial begin
$monitor("\t BCD: %d : 7 segment display: %h", BCD, segment7);
#100 $finish;
end
endmodule |
module even_or_odd(
input [3:0] number,
output reg even_odd);
parameter EVEN= 1'b1, ODD= 1'b0;
always@(number)
begin
even_odd= check_even_odd(number);
if(even_odd== 1'b1) $display("\t\t %d is an even number", number);
else $display("\t\t %d is an odd number", number);
end
function check_even_odd;
input [3:0]num;
begin
if(num%2== 0) check_even_odd= EVEN;
else check_even_odd= ODD;
end
endfunction
endmodule |
module test_bench;
reg [3:0]number;
wire even_odd;
even_or_odd dut(number, even_odd);
always
begin
number=4'd6;
#10;
number=4'd3;
#10;
number=4'd14;
#10;
number=4'd10;
#10;
number=4'd11;
#10;
number=4'd7;
#10;
end
initial #60 $finish;
endmodule |
module clk_edge_detector(
input clk, temp_clk,
output posedge_detect, negedge_detect, dualedge_detect
);
assign posedge_detect= clk & (~temp_clk);
assign negedge_detect= (~clk) & temp_clk;
assign dualedge_detect= clk ^ temp_clk;
endmodule |
module test_bench;
reg clk, temp_clk;
wire posedge_detect, negedge_detect, dualedge_detect;
clk_edge_detector dut(clk, temp_clk, posedge_detect, negedge_detect, dualedge_detect);
initial begin
clk= 1'b0;
temp_clk= 1'b0;
end
initial forever #5 clk<= ~clk;
initial forever #5.5 temp_clk<= ~temp_clk;
initial begin
$monitor("clock: %b posedge: %b negedge: %b dualedge: %b", clk, posedge_detect, negedge_detect, dualedge_detect);
#30 $finish;
end
endmodule |
module single_port_ram
#(parameter addr_width = 6,
parameter data_width = 8,
parameter depth = 128)
(input [data_width-1:0] data,
input [addr_width-1:0] address,
input we,clk,
output [data_width-1:0] q);
reg [data_width-1:0] ram [depth-1:0];
reg [addr_width-1:0] addr_reg;
always @(posedge clk)
begin
if(we)
ram[address] <=data;
else
addr_reg <=address;
end
assign q= ram[addr_reg];
endmodule |
module test_bench;
parameter addr_width = 6;
parameter data_width = 8;
parameter depth = 128;
reg [data_width-1:0] data;
reg [addr_width-1:0] address;
reg we, clk;
wire [data_width-1:0] q;
single_port_ram dut(data, address, we, clk, q);
initial begin
clk=1'b1;
forever #5 clk=~clk;
end
initial begin
data= 8'hf0;
address= 6'd0;
we= 1'b1; //write data
#10;
data= 8'he1;
address= 6'd1;
#10;
data= 8'hd2;
address= 6'd2;
#10;
data= 8'hz;
//read operation
address= 5'd0;
we= 1'b0;
#10;
address= 5'd2;
#10;
address= 5'd1;
#10;
end
initial begin
$monitor("write enable: %b address: %b data: %b output: %b", we, address, data, q);
#60 $finish;
end
endmodule |
module full_adder(
input a, b, cin,
output sout, cout
);
assign sout = a ^ b ^ cin;
assign cout = (a&b) | cin&(a^b);
endmodule |
module parallel_adder(
input [3:0] A, B,
input carry_in,
output [3:0] sum,
output carry
);
wire [2:0] c;
full_adder fa1(A[0], B[0], carry_in, sum[0], c[0]);
full_adder fa2(A[1], B[1], c[0], sum[1], c[1]);
full_adder fa3(A[2], B[2], c[1], sum[2], c[2]);
full_adder fa4(A[3], B[3], c[2], sum[3], carry);
endmodule |
module carry_skip_adder(
output [3:0]sum,
output cout,
input [3:0]a, b,
input cin
);
wire c, sel;
wire [3:0]p;
parallel_adder pa(a, b, cin, sum, c);
xor (p[0], a[0], b[0]),
(p[1], a[1], b[1]),
(p[2], a[2], b[2]),
(p[3], a[3], b[3]);
and (sel, p[0],p[1], p[2], p[3]);
assign cout = sel ? cin : c;
endmodule |
module test_bench;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire carry;
carry_skip_adder dut(sum, carry, a, b, cin);
initial
begin
a = 4'b1000; b = 4'b0011; cin = 1'b0;
#10 a = 4'b0001; b = 4'b1010; cin = 1'b1;
#10 a = 4'b0110; b = 4'b0110; cin = 1'b0;
#10 a = 4'b0111; b = 4'b1110; cin = 1'b0;
#10 a = 4'b1001; b = 4'b0110; cin = 1'b1;
#10 a = 4'b1001; b = 4'b0100; cin = 1'b0;
#10 a = 4'b1111; b = 4'b1110; cin = 1'b1;
end
initial
begin $monitor("a=%b b=%b cin=%b Sum=%b Carry=%b",a,b,cin,sum,carry);
#70 $finish;
end
endmodule |
module decoder_2_4(
input [1:0] i,
output reg[3:0] y);
always@(i)
begin
y=0;
case(i)
2'b00 : y[0] = 1'b1;
2'b01 : y[1] = 1'b1;
2'b10 : y[2] = 1'b1;
2'b11 : y[3] = 1'b1;
endcase
end
endmodule |
module decoder_xor_xnor(
input a,b,
output xor_g, xnor_g
);
wire [3:0] w;
decoder_2_4 gate({a,b}, w);
assign xor_g= w[1] | w[2];
assign xnor_g= w[0] | w[3];
endmodule |
module test_bench;
reg a, b;
wire xor_g, xnor_g;
decoder_xor_xnor dut(a, b, xor_g, xnor_g);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b xor: %b xnor: %b",a, b, xor_g, xnor_g);
#40 $finish;
end
endmodule |
module fsm_101_0110(
input din,clk,reset,
output reg y);
reg[2:0] cst, nst;
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100,
S5=3'b101;
always@ (posedge clk)
begin
if(reset)
cst<=S0;
else
cst<=nst;
end
always @(cst or din)
begin
case(cst)
S0: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S2;
y<=1'b0;
end
S1: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S2: if(din==1'b1)
begin
nst<=S4;
y<=1'b0;
end
else
begin
nst<=S2;
y<=1'b0;
end
S3: if(din==1'b1)
begin
nst<=S4;
y<=1'b1;
end
else
begin
nst<=S2;
y<=1'b0;
end
S4: if(din==1'b1)
begin
nst<=S5;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b0;
end
S5: if(din==1'b1)
begin
nst<=S1;
y<=1'b0;
end
else
begin
nst<=S3;
y<=1'b1;
end
default: nst<=S0;
endcase
end
endmodule |
module test_bench;
reg din,clk,reset;
wire y;
fsm_101_0110 dut(din,clk,reset,y);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10 reset= 1'b0;
#5 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b0;
#10 din= 1'b1;
#10 din= 1'b1;
#10 din= 1'b0;
end
initial begin
$monitor("\t\t clock: %d input: %d detect: %d",clk, din, y);
#180 $finish;
end
endmodule |
module full_adder(
input A, B, Cin,
output reg Sout, Cout
);
always@(*) begin
Sout = A ^ B ^ Cin;
Cout = (A&B) | (B&Cin) | (Cin&A);
end
endmodule |
module mux(
input a,b,sel,
output reg y
);
always@(*) y = (~sel&a) | (sel&b);
endmodule |
module carry_select (
input [3:0]a,b,
input carry,
output [3:0]sum,
output cout
);
wire [16:1]w;
full_adder fa1 (a[0], b[0], 1'b0, w[1], w[2]);
full_adder fa2 (a[1], b[1], w[2], w[3], w[4]);
full_adder fa3 (a[2], b[2], w[4], w[5], w[6]);
full_adder fa4 (a[3], b[3], w[6], w[7], w[8]);
full_adder fa5 (a[0], b[0], 1'b1, w[9], w[10]);
full_adder fa6 (a[1], b[1], w[10], w[11], w[12]);
full_adder fa7 (a[2], b[2], w[12], w[13], w[14]);
full_adder fa8 (a[3], b[3], w[14], w[15], w[16]);
mux m1(w[1], w[9], carry, sum[0]);
mux m2(w[3], w[11], carry, sum[1]);
mux m3(w[5], w[13], carry, sum[2]);
mux m4(w[7], w[15], carry, sum[3]);
mux m5(w[8], w[16], carry, cout);
endmodule |
module test_bench;
reg [3:0]a,b;
reg carry;
wire[3:0]sum;
wire cout ;
carry_select dut(a,b,carry,sum,cout);
initial begin
carry=1'b0;a=4'b1011;b=4'b1010;
#10 carry=1'b1;a=4'b1001;b=4'b1110;
#10 carry=1'b0;a=4'b0001;b=4'b1010;
#10 carry=1'b1;a=4'b1100;b=4'b0011;
end
initial begin
$monitor("a=%b b=%b carry=%b sum=%b cout=%b",a,b,carry,sum,cout);
#40 $finish;
end
endmodule |
module piso (
input clk, reset, load,
input [2:0]parallel_in,
output serial_out
);
reg [2:0]q= 3'd0;
always @ (posedge clk)
begin
if(reset) q<= 0;
else begin
if (load)
q <= parallel_in;
else
begin
q[0]=q[1];
q[1]=q[2];
q[2]= 1'bx;
end
end
end
assign serial_out= q[0];
endmodule |
module test_bench;
reg clk, reset, load;
reg [2:0] parallel_in;
wire serial_out;
piso dut(clk, reset, load, parallel_in, serial_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1;
#10 reset= 0;
load= 1'b1;
parallel_in= 3'b001;
#10 load= 1'b0;
#30 load= 1'b1;
parallel_in= 3'b100;
#10 load= 1'b0;
#30 load= 1'b1;
parallel_in= 3'b101;
#10 load= 1'b0;
end
initial begin
$monitor("\t\t clk: %d load: %d paralel_in: %b serial_out: %d", clk, load, parallel_in, serial_out);
#120 $finish;
end
endmodule |
module D_flipflop(
input d, clk, reset,
output reg Q
);
always@(posedge clk)
begin
if(reset)
Q<= 1'b0;
else
Q <= d;
end
endmodule |
module sipo(
input clk, reset, serial_in,
output [2:0] parallel_out
);
D_flipflop D2(serial_in, clk, reset, parallel_out[2]);
D_flipflop D1(parallel_out[2], clk, reset, parallel_out[1]);
D_flipflop D0(parallel_out[1], clk, reset, parallel_out[0]);
endmodule |
module test_bench;
reg clk, reset, serial_in;
wire [2:0] parallel_out;
sipo dut(clk, reset, serial_in, parallel_out);
initial begin
clk=1'b0;
forever #5 clk=~clk;
end
initial begin
reset= 1'b1;
serial_in= 1'b0;
#10 reset= 1'b0;
#0 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'b0;
#10 serial_in= 1'b1;
#10 serial_in= 1'b0;
#10 serial_in= 1'bx;
end
initial begin
$monitor("\t\t clk: %d reset: %d serial_in: %d parallel_out: %b", clk, reset, serial_in, parallel_out);
#120 $finish;
end
endmodule |
module logic_gates(
input a, b,
output and_g,
output or_g,
output not_g,
output nand_g,
output nor_g,
output xor_g,
output xnor_g
);
assign and_g = a&b;
assign or_g = a|b;
assign not_g = ~a;
assign nand_g = ~(a&b);
assign nor_g = ~(a|b);
assign xor_g = a^b;
assign xnor_g = ~(a^b);
endmodule |
module test_bench;
reg a, b;
wire and_g,
or_g,
not_g,
nand_g,
nor_g,
xor_g,
xnor_g;
logic_gates dut(a, b, and_g,or_g,not_g,nand_g,nor_g,xor_g,xnor_g);
initial begin
#10 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
endmodule |
module multiplier(
input [3:0]a,b,
output reg [7:0] out
);
reg [7:0] t1,t2,t3,t4;
always@(a,b)
begin
t1=0; t2=0; t3=0; t4=0;
if(b[0])
t1 = a<<0;
if(b[1])
t2 = a<<1;
if(b[2])
t3 = a<<2;
if(b[3])
t4 = a<<3;
out = t1+t2+t3+t4;
end
endmodule |
module test_bench;
reg [3:0]a,b;
wire [7:0]mul_out;
multiplier dut(a, b, mul_out);
always begin
a=$random;
b=$random;
#10;
end
initial
begin $monitor("%0d * %0d = %0d ",a, b, mul_out);
#100 $finish;
end
endmodule |
module lifo(
input [3:0] dataIn,
input rd_en, wr_en, rst, clk,
output reg empty, full,
output reg [3:0] dataOut
);
reg [3:0] stack_mem[0:3];
reg [2:0] stack_ptr;
integer i;
always @ (posedge clk)
begin
if (wr_en==0);
else begin
if (rst==1) begin
stack_ptr = 3'd4;
empty = stack_ptr[2];
dataOut = 4'h0;
for (i=0;i<4;i=i+1) begin
stack_mem[i]= 0;
end
end
else if (rst==0) begin
full = stack_ptr? 0:1;
empty = stack_ptr[2];
dataOut = 4'hx;
if (full == 1'b0 && rd_en == 1'b0) begin
stack_ptr = stack_ptr-1'b1;
full = stack_ptr? 0:1;
empty = stack_ptr[2];
stack_mem[stack_ptr] = dataIn;
end
else if (empty == 1'b0 && rd_en == 1'b1) begin
dataOut = stack_mem[stack_ptr];
stack_mem[stack_ptr] = 0;
stack_ptr = stack_ptr+1;
full = stack_ptr? 0:1;
empty = stack_ptr[2];
end
end
end
end
endmodule |
module test_bench;
reg [3:0] dataIn;
reg rd_en, wr_en, rst, clk;
wire [3:0] dataOut;
wire empty, full;
lifo uut (dataIn, rd_en, wr_en, rst, clk, empty, full, dataOut);
initial begin
dataIn = 4'h0;
rd_en = 1'b0;
wr_en = 1'b0;
rst = 1'b1;
clk = 1'b0;
#10;
wr_en = 1'b1;
rst = 1'b1;
#40;
rst = 1'b0;
rd_en = 1'b0;
dataIn = 4'h0;
#20;
dataIn = 4'h3;
#20;
dataIn = 4'h7;
#20;
dataIn = 4'ha;
#20;
rd_en = 1'b1;
#100 $finish;
end
always #10 clk = ~clk;
always @(posedge clk) begin
$display("Data in: %d Data out: %d Empty: %d Full: %d", dataIn, dataOut, empty, full);
end
endmodule |
module gray_counter(
input clk,rst,
output reg [3:0] gray_count
);
reg [3:0] bin_count;
always@(posedge clk)
begin
if(rst)
begin
gray_count=4'b0000;
bin_count=4'b0000;
end
else
begin
bin_count = bin_count + 1;
gray_count = {bin_count[3],bin_count[3]^bin_count[2],bin_count[2]^bin_count[1],bin_count[1]^bin_count[0]};
end
end
endmodule |
module test_bench;
reg clk,reset;
wire [3:0] gray_count;
gray_counter dut(clk, reset, gray_count);
initial begin
clk= 1'b0;
forever #5 clk= ~clk;
end
initial begin
reset= 1'b1;
#10;
reset= 1'b0;
end
initial begin
$monitor("\t\t counter: %d", gray_count);
#175 $finish;
end
endmodule |
module logic_gates(
input a, b,
output and_g,
output or_g,
output not_g,
output nand_g,
output nor_g,
output xor_g,
output xnor_g
);
and andgate(and_g, a, b);
or orgate(or_g, a, b);
not notgate(not_g, a);
nand nandgate(nand_g, a, b);
nor norgate(nor_g, a, b);
xor xorgate(xor_g, a, b);
xnor xnorgate(xnor_g, a, b);
endmodule |
module gray2binary(
input [3:0] gray_in,
output [3:0] binary_out
);
buf buf1(binary_out[3],gray_in[3]);
xor xor1(binary_out[2],gray_in[2],binary_out[3]),
xor2(binary_out[1],gray_in[1],binary_out[2]),
xor3(binary_out[0],gray_in[0],binary_out[1]);
endmodule |
module test_bench;
reg [3:0] gray_in;
wire [3:0]binary_out;
gray2binary dut(gray_in, binary_out);
initial begin
gray_in= 4'd0;
#10;
gray_in= 4'd1;
#10;
gray_in= 4'd2;
#10;
gray_in= 4'd3;
#10;
gray_in= 4'd4;
#10;
gray_in= 4'd5;
#10;
gray_in= 4'd6;
#10;
gray_in= 4'd7;
#10;
gray_in= 4'd8;
#10;
gray_in= 4'd9;
#10;
gray_in= 4'd10;
#10;
gray_in= 4'd11;
#10;
gray_in= 4'd12;
#10;
gray_in= 4'd13;
#10;
gray_in= 4'd14;
#10;
gray_in= 4'd15;
end
initial
begin $monitor("gray: %b -> binary: %b", gray_in, binary_out);
#160 $finish;
end
endmodule |
module test_bench;
reg signed [3:0] Q,M;
wire signed [7:0] result;
booth_algorithm dut(Q,M,result);
initial begin
Q= 3; M= 7; #10;
Q= 3; M= -7; #10;
Q= -3; M= -7; #10;
Q= 5; M= 6; #10;
Q= 5; M= -6; #10;
Q= -5; M= -6; #10;
end
initial begin
$monitor("%d * %d = %d", Q,M,result);
#60 $finish;
end
endmodule |
module booth_algorithm(
input signed [3:0] Q, M,
output reg signed [7:0] result
);
reg [1:0] operation;
integer i;
reg q0;
reg [3:0] M_comp;
always @(Q,M)
begin
result = 8'd0;
q0 = 1'b0;
M_comp = -M;
for (i=0; i<4; i=i+1)
begin
operation = { Q[i], q0 };
case(operation)
2'b10 : result[7:4] = result[7:4] + M_comp;
2'b01 : result[7:4] = result[7:4] + M;
endcase
result = result >> 1;
result[7] = result[6];
q0= Q[i];
end
end
endmodule |
module half_adder(
input a,b,
output sum,carry
);
assign sum=a^b;
assign carry=a&b;
endmodule |
module vedic_mul_2_2(
input [1:0] a,b,
output [3:0] out
);
wire [3:0] w;
and m1(out[0],a[0],b[0]);
and m2(w[0],a[0],b[1]);
and m3(w[1],a[1],b[0]);
and m4(w[2],a[1],b[1]);
half_adder ha1(w[0],w[1],out[1],w[3]);
half_adder ha2(w[3],w[2],out[2],out[3]);
endmodule |
module test_bench;
reg [1:0]a,b;
wire [3:0]out;
vedic_mul_2_2 dut(a,b,out);
always begin
a=2'd2;
b=2'd1;
#10;
a=2'd3;
b=2'd2;
#10;
a=2'd0;
b=2'd1;
#10;
a=2'd3;
b=2'd1;
#10;
a=2'd2;
b=2'd2;
#10;
a=2'd3;
b=2'd3;
#10;
end
initial begin
$monitor("%d * %d = %d", a,b,out);
#60 $finish;
end
endmodule |
module test_bench;
reg a, b, cin;
wire sum, carry;
full_adder dut(a, b, cin, sum, carry);
initial begin
a = 0; b = 0; cin = 0;
#10;
a = 0; b = 0; cin = 1;
#10;
a = 0; b = 1; cin = 0;
#10;
a = 0; b = 1; cin = 1;
#10;
a = 1; b = 0; cin = 0;
#10;
a = 1; b = 0; cin = 1;
#10;
a = 1; b = 1; cin = 0;
#10;
a = 1; b = 1; cin = 1;
#10;
end
initial begin
$monitor("a = %b, b = %b, cin = %b, sum = %b, carry = %b", a, b, cin, sum, carry);
#80 $finish;
end
endmodule |
module mux2_1(
input m,n,
input sel,
output y_out
);
assign y_out= sel ? n : m;
endmodule |
module full_adder(
input a,b,cin,
output sum, carry
);
wire [4:0]w;
mux2_1 m0(1'b1, 1'b0, a, w[0]);
mux2_1 m1(a, w[0], b, w[1]);
mux2_1 m2(1'b1, 1'b0, w[1], w[2]);
mux2_1 m3(w[1], w[2], cin, sum);
mux2_1 m4(1'b0, w[1], cin, w[3]);
mux2_1 m5(1'b0, a, b, w[4]);
mux2_1 m6(w[3], w[4], w[4], carry);
endmodule |
module traffic_light_control(highway, small_road, sensor, clk, clr);
input sensor, clk, clr;
output reg [1:0] highway, small_road;
parameter RED=2'd0, YELLOW=2'd1, GREEN=2'd2;
parameter S0=3'd0,
S1=3'd1,
S2=3'd2,
S3=3'd3,
S4=3'd4;
reg[2:0] state, next_state;
always@(posedge clk)
if(clr)
state<=S0;
else
state<=next_state;
always@(state) begin
highway= GREEN;
small_road= RED;
case(state)
S0:;
S1: highway= YELLOW;
S2: highway= RED;
S3: begin
highway= RED;
small_road= GREEN;
end
S4: begin
highway= RED;
small_road= YELLOW;
end
endcase
end
always@(state or sensor) begin
case(state)
S0: if(sensor)
next_state= S1;
else
next_state= S0;
S1: begin
repeat (`G2YDELAY) next_state= S1;
next_state= S2;
end
S2: begin
repeat (`Y2RDELAY) next_state= S2;
next_state= S3;
end
S3: begin
if(sensor)
next_state= S3;
else
next_state= S4;
end
S4: begin
repeat (`G2YDELAY) next_state= S4;
next_state= S0;
end
default: next_state= S0;
endcase
end
endmodule |
module test_bench;
reg sensor, clk, clr;
wire [1:0] highway, small_road;
traffic_light_control dut(highway, small_road, sensor, clk, clr);
initial begin
clk= 1'b0;
forever #10 clk= ~clk;
end
initial begin
clr= 1'b1;
sensor= 1'b0;
#20 clr= 1'b0;
#10 sensor= 1'b1;
#50 sensor= 1'b0;
#70 sensor= 1'b1;
#60 $stop;
end
endmodule |
module JK_flipflop(
input j,k,clk,reset,
output reg Q
);
always@(posedge clk)
begin
if({reset})
Q <= 1'b0;
else
begin
case({j,k})
2'b00:Q<=Q;
2'b01:Q<=1'b0;
2'b10:Q<=1'b1;
2'b11:Q<=~Q;
endcase
end
end
endmodule |
module test_bench;
reg clk,rst,j,k;
wire Q;
JK_flipflop dut(j,k,clk,rst,Q);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
rst=1;
#10;
j = 1'b0;
k = 1'b0;
#10;
rst=0;
#10;
j = 1'b0;
k = 1'b1;
#10;
j = 1'b1;
k = 1'b0;
#10;
j = 1'b1;
k = 1'b1;
#10;
end
initial begin
$monitor("\t clk: %d J: %d K: %d Q: %d", clk, j, k, Q);
#80 $finish;
end
endmodule |
module test_bench;
reg [7:0] data;
reg [2:0] amt;
wire [7:0] out;
barrel_shifter dut(data, amt, out);
initial begin
data= 8'hf0;
amt=0;
forever #10 amt= amt+1;
end
initial begin
$monitor("\t\t data: %b shifting amount: %d output: %b", data, amt, out);
#80 $finish;
end
endmodule |
module mux_2_1(
input [1:0] i,
input sel,
output y_out
);
assign y_out= sel ? i[1] : i[0];
endmodule |
module mux_4_1(
input [3:0] i,
input [1:0]select,
output y_out
);
wire [1:0]w;
mux_2_1 m1(i[1:0], select[0], w[0]);
mux_2_1 m2(i[3:2], select[0], w[1]);
mux_2_1 m3(w, select[1], y_out);
endmodule |
module barrel_shifter(
input [7:0] data,
input [2:0] amt,
output [7:0] out
);
mux_8_1 m0(data, amt, out[0]);
mux_8_1 m1({data[0], data[7:1]}, amt, out[1]);
mux_8_1 m2({data[1:0], data[7:2]}, amt, out[2]);
mux_8_1 m3({data[2:0], data[7:3]}, amt, out[3]);
mux_8_1 m4({data[3:0], data[7:4]}, amt, out[4]);
mux_8_1 m5({data[4:0], data[7:5]}, amt, out[5]);
mux_8_1 m6({data[5:0], data[7:6]}, amt, out[6]);
mux_8_1 m7({data[6:0], data[7]}, amt, out[7]);
endmodule |
module demux_1_2(
input sel,
input i,
output y0, y1
);
assign {y0,y1} = sel?{1'b0,i}: {i,1'b0};
endmodule |
module demux_xor_xnor(
input a,b,
output xor_g, xnor_g
);
wire [3:0] w;
demux_1_2 demux1(b, ~a, w[0], w[1]);
demux_1_2 demux2(b, a, w[2], w[3]);
assign xor_g= w[1] | w[2];
assign xnor_g= w[0] | w[3];
endmodule |
module fsm_1011(
input clk,rst,din,
output reg y);
parameter S0=3'b000,
S1=3'b001,
S2=3'b010,
S3=3'b011,
S4=3'b100;
reg[2:0] cs, nst;
always @(posedge clk)
begin
if(rst)
cs<=S0;
else
cs<=nst;
end
always @(cs,din)
begin
case(cs)
S0: begin
if(din==1)
nst<=S1;
else
nst<=S0;
end
S1: begin
if(din==1)
nst<=S1;
else
nst<=S2;
end
S2: begin
if(din==1)
nst<=S3;
else
nst<=S0;
end
S3: begin
if(din==1)
nst<=S4;
else
nst<=S0;
end
S4: begin
if(din==1)
nst<=S1;
else
nst<=S0;
end
default: nst<=S0;
endcase
end
always @(cs)
begin
case(cs)
S0: y<=0;
S1: y<=0;
S2: y<=0;
S3: y<=0;
S4: y<=1;
default: y<=0;
endcase
end
endmodule |
module car_parking_management(
input clk, rst, sense_entry, sense_exit,
input [1:0] password_1, password_2,
output reg green_light, red_light,
output reg [6:0] hex_1, hex_2,
output reg [3:0] space_available, space_utilized, count_cars
);
reg [3:0] overall_space=4'b1000;
reg [2:0] current_state, next_state;
reg [1:0] wait_time;
//declaring parameters list
parameter idle = 3'b000,
wait_time_state=3'b001,
password_correct=3'b010,
password_incorrect=3'b011,
stop=3'b100;
//declarimg current state
always@(posedge clk) begin
if(rst==1) current_state<= idle;
else current_state<= next_state;
end
//parking space management
always@(posedge clk) begin
if(rst==1) begin //reseting whole design
space_available<= overall_space;
space_utilized<= 0;
count_cars<=4'b0;
end
else begin
if ((sense_entry==1) && (space_available>0))begin //entry of 1 vehicle
space_available<= space_available - 3'b001;
space_utilized<= space_utilized + 3'b001;
count_cars<=count_cars + 4'b0001;
end
else if ((sense_exit==1) && (space_utilized>0)) begin //exit of 1 vehicle
space_available<= space_available + 3'b001;
space_utilized<= space_utilized - 3'b001;
count_cars<= count_cars - 4'b0001;
end
else begin //no vehicle entered and exited
space_available<= overall_space;
space_utilized<= 0;
count_cars<=4'b0;
end
end
end
//declarationn of wait_timeing period in the wait_time_state
always@(posedge clk) begin
if(rst==1) wait_time<= 2'b0;
else begin
if(current_state==wait_time_state) wait_time<= wait_time + 2'b01;
else wait_time<= 2'b0;
end
end
//declaration of next state
always@(*) begin
case(current_state)
idle: begin
if((sense_entry==1) && (space_available>0)) next_state<= wait_time_state;
else next_state<= idle;
end
wait_time_state: begin
if(wait_time<= 3'b011) next_state<= wait_time_state;
else begin
if ((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= password_incorrect;
end
end
password_correct: begin
if((sense_entry==1) && (sense_exit==1)) next_state<= stop;
else if((sense_exit==1)) next_state<= idle;
else next_state<= password_correct;
end
password_incorrect: begin
if((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= password_incorrect;
end
stop: begin
if((password_1==2'b01) && (password_2==2'b01)) next_state<= password_correct;
else next_state<= stop;
end
default: next_state<= idle;
endcase
end
always@(posedge clk) begin
case(current_state)
idle: begin //starting state with no entry and exit of vehicles
green_light<= 1'b0;
red_light<= 1'b0;
hex_1<= 7'b0000000; //0
hex_2<= 7'b0000000; //0
end
wait_time_state: begin //vechile wait_timeing in the lobby
green_light<= ~green_light;
red_light<= 1'b0;
hex_1<= 7'b1111001; //alphabet-E
hex_2<= 7'b0110111; //N -> ENTER
end
password_correct: begin //vehicle entering and providing password_correct
green_light<= 1'b1;
red_light<= 1'b0;
hex_1<= 7'b1111001; //6
hex_2<= 7'b0000000; //0 -> GO
end
password_incorrect: begin //vehicle entering and providing password_incorrect
green_light<= 1'b0;
red_light<= 1'b1;
hex_1<= 7'b1111001; //E
hex_2<= 7'b1111001; //E -> ERROR
end
stop: begin //stay of the vehicle for some period
green_light<= 1'b0;
red_light<= ~red_light;
hex_1<= 7'b1101101; //5
hex_2<= 7'b1110011; //P -> STOP
end
endcase
end
endmodule |
module test_bench;
reg clk, rst, sense_entry, sense_exit;
reg [1:0] password_1, password_2;
wire green_light, red_light;
wire [6:0] hex_1, hex_2;
wire [3:0] space_available, space_utilized, count_cars;
car_parking_management dut(clk, rst, sense_entry, sense_exit, password_1, password_2, green_light, red_light, hex_1, hex_2, space_available, space_utilized, count_cars);
initial begin
clk = 1;
forever #5 clk = ~clk;
end
initial begin
rst = 1;
sense_entry = 0;
sense_exit = 0;
password_1 = 0;
password_2 = 0;
#10;
rst = 1'b0;
sense_entry = 1'b1;
sense_exit = 1'b0;
password_1 = 2'b01;
password_2 = 2'b01;
#80; sense_exit = 1'b1; sense_entry = 1'b0;
end
initial begin
$monitor("time=%g, clk=%b, rst=%b, sense_entry=%b, sense_exit=%b, password_1=%b, password_2=%b,\ngreen_light=%b, red_light=%b, hex_1=%b, hex_2=%b, space_available=%d, space_utilized=%d, count_cars=%d", $time, clk, rst, sense_entry, sense_exit, password_1, password_2, green_light, red_light, hex_1, hex_2, space_available, space_utilized, count_cars);
#150 $finish;
end
endmodule |
module vend(coin, clock, reset, newspaper);
//Input output port declarations
input [1:0] coin;
input clock;
input reset;
output newspaper;
//internal FSM state declarations
wire [1:0] NEXT_STATE;
reg [1:0] PRES_STATE;
//state encodings
parameter s0 = 2'b00,
s5 = 2'b01,
s10 = 2'b10,
s15 = 2'b11;
//Combinational logic
function [2:0] fsm;
input [1:0] fsm_coin;
input [1:0] fsm_PRES_STATE;
reg fsm_newspaper;
reg [1:0] fsm_NEXT_STATE;
begin
case (fsm_PRES_STATE)
s0: //state = s0
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s5;
end
else
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s0;
end
end
s5: //state = s5
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s15 ;
end
else if (fsm_coin == 2'b01)
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s10;
end
else
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s5;
end
end
s10: //state = s10
begin
if (fsm_coin == 2'b10)
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE =s15 ;
end
else if (fsm_coin == 2'b01 )
begin
fsm_newspaper = 1'b0;
fsm_NEXT_STATE = s15 ;
end
else
begin
fsm_newspaper = 1'b0 ;
fsm_NEXT_STATE = s10;
end
end
s15: //state = s 15
begin
fsm_newspaper = 1'b1 ;
fsm_NEXT_STATE = s0 ;
end
endcase
fsm= {fsm_newspaper, fsm_NEXT_STATE};
end
endfunction
//Reevaluate combinational logic each time a coin is put or the present state changes
assign {newspaper, NEXT_STATE}= fsm(coin, PRES_STATE);
//clock the state flip-flops.
//use synchronous reset
always @(posedge clock)
begin
if (reset == 1'b1)
PRES_STATE = s0 ;
else
PRES_STATE = NEXT_STATE;
end
endmodule |
module test_bench;
reg clock;
reg [1:0] coin;
reg reset;
wire newspaper;
//instantiate the vending state machine
vend dut(coin, clock, reset, newspaper);
//Display the output
initial begin
$display("\t\tTime Reset Newspaper");
$monitor("\t\t %0d \t %0d \t %0d", $time, reset, newspaper);
end
//Apply stimulus to the vending machine
initial begin
clock = 0;
coin = 0 ;
reset = 1 ;
#50 reset = 0 ;
@(negedge clock); //wait until negative edge of clock
//Put 3 nickels to get newspaper
#80 coin = 1; #40 coin = 0;
#80 coin = 1; #40 coin = 0;
#80 coin = 1; #40 coin = 0 ;
//Put one nickel and then one dime to get newspaper
#180 coin = 1; #40 coin = 0;
#80 coin = 2; #40 coin = 0;
//Put two dimes; machine does not return a nickel to get newspaper
#180 coin = 2 ; #40 coin = 0 ;
#80 coin = 2; #40 coin = 0;
//Put one dime and then one nickel to get newspaper
#180 coin = 2; #40 coin = 0;
#80 coin = 1; #40 coin = 0;
end
initial #1500 $finish;
//setup clock; cycle time = 40 units
always #20 clock = ~clock;
endmodule |
module sequence_counter(
input clk,
input reset,
output reg [3:0] counter
);
reg [3:0] count;
always @(posedge clk, posedge reset) begin
if (reset) begin
count <= 4'b0000;
counter <= 4'b0000;
end
else begin
case (count)
4'b0000: begin // 0
counter <= 4'b0000;
count <= 3'b010;
end
4'b0010: begin // 2
counter <= 4'b0010;
count <= 4'b0101;
end
4'b0101: begin // 5
counter <= 4'b0101;
count <= 4'b1000;
end
4'b1000: begin // 8
counter <= 4'b1000;
count <= 4'b1011;
end
4'b1011: begin // 11
counter <= 4'b1011;
count <= 4'b1110;
end
4'b1110: begin // 14
counter <= 4'b1110;
count <= 4'b0000;
end
default: count <= 4'b0000;
endcase
end
end
endmodule |
module test_bench;
reg clk, reset;
wire [3:0] counter;
sequence_counter dut(clk, reset,counter);
initial
begin
clk = 0;
reset = 1;
# 10 reset = 0 ;
end
always #5 clk = ~clk;
initial begin
$monitor("\t\t clk: %b counter:%b", clk, counter);
#140 $finish;
end
endmodule |
module test_bench;
reg a, b;
wire nand_out, nor_out;
gates_mux dut(a, b, nand_out, nor_out);
initial begin
#0 a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b nand: %b nor: %b ",a, b, nand_out, nor_out );
#40 $finish;
end
endmodule |
module mux_2_1(
input [1:0] i,
input select,
output y_out
);
assign y_out= select ? i[1] : i[0];
endmodule |
module gates_mux(
input a, b,
output nand_out, nor_out
);
wire bbar;
mux_2_1 mbbar({1'b0, 1'b1}, b, bbar);
mux_2_1 mnand({bbar, 1'b1}, a, nand_out);
mux_2_1 mnor({1'b0, bbar}, a, nor_out);
endmodule |
module majority_input(
input [6:0] in,
output out
);
wire [2:0] test;
assign test[0] = (in[0] & in[1]) | (in[0] & in[2]) | (in[1] & in[2]);
assign test[1] = (in[3] & in[4]) | (in[3] & in[5]) | (in[4] & in[5]);
assign test[2] = in[6];
assign out = (test[0]) & (test[1]) | (test[0] & test[2]) | (test[1] & test[2]);
endmodule |
module test_bench;
reg [6:0]in;
wire out;
majority_input dut(in, out);
initial begin
in=7'd99;
#10;
in=7'd28;
#10;
in=7'd119;
#10;
in=7'd101;
#10;
in=7'd32;
#10;
in=7'd48;
#10;
in=7'd75;
#10;
end
initial
begin $monitor("%b is a majority input of number %b ",out, in);
#70 $finish;
end
endmodule |
module gates_mux(
input a,b,
output and_out,
output or_out,
output not_out
);
mux_2_1 mand({b, 1'b0}, a, and_out);
mux_2_1 mor({1'b1, b}, a, or_out);
mux_2_1 mnot({1'b0, 1'b1}, a, not_out);
endmodule |
module ALU(
input [7:0] a,b,
input [3:0] sel,
output reg [15:0] result,
output reg e_bit
);
always@(*)
begin
case(sel)
4'b0000: begin {e_bit,result}<= a+b; $display("1-Addition operation"); end
4'b0001: begin {e_bit,result}<= a-b; $display("2-Subtraction operation"); end
4'b0010: begin result<= a*b; $display("3-Multiplication operation"); end
4'b0011: begin result<= a/b; $display("4-Division operation"); end
4'b0100: begin result<=a<<1; $display("5-Left Shift operation"); end
4'b0101: begin result<=a>>1; $display("6-Right Shift operation"); end
4'b0110: begin result<=a<<1; e_bit <=a[7];
result[0]<=e_bit; $display("7-Left Rotation operation"); end
4'b0111: begin result<=a>>1; e_bit <=a[0];
result[7]<=e_bit; $display("8-Right Rotation operation"); end
4'b1000 : begin result <= a&b; $display("9-AND operation"); end
4'b1001 : begin result <= a|b; $display("10-OR operation"); end
4'b1010 : begin result <= ~(a&b); $display("11-NAND operation"); end
4'b1011 : begin result <= ~(a|b); $display("12-NOR operation"); end
4'b1100 : begin result <= a ^ b; $display("13-XOR operation"); end
4'b1101 : begin result <= a ~^ b; $display("14-XNOR operation"); end
4'b1110 : begin result <= (a>b)? 1'b1:1'b0; $display("15-Equality operation"); end
4'b1111 : begin result <= ~a + 8'b00000001; $display("16-2's Compliment operation"); end
endcase
end
endmodule |
module test_bench;
reg [7:0] a;
reg [7:0] b;
reg [3:0] sel;
wire [7:0] result;
wire e_bit;
ALU dut(a, b, sel, result, e_bit);
initial begin
a = 8'd15;
b = 8'd3;
sel = 0;
$display(" Inputs are: %b and %b \n", a,b);
end
always #20 sel=sel+1;
initial begin
$monitor("\t Result= %b \n", result);
#320 $finish;
end
endmodule |
module binary2gray(
input [3:0] binary_in,
output [3:0] gray_out
);
buf buf1(gray_out[3], binary_in[3]);
xor xor1(gray_out[2], binary_in[3], binary_in[2]),
xor2(gray_out[1], binary_in[2], binary_in[1]),
xor3(gray_out[0], binary_in[1], binary_in[0]);
endmodule |
module test_bench;
reg [7:0]data;
wire [3:0] bit0, bit1, bit2;
wire [11:0] BCD;
binary2bcd dut(data, bit0, bit1, bit2, BCD);
always
begin
data=$random;
#10;
end
initial
begin $monitor("data: %d BCD: %b",data,BCD);
#80 $finish;
end
endmodule |
module binary2bcd(
input [7:0]data,
output reg [3:0] bit0,bit1,bit2,
output reg[11:0] BCD
);
integer n;
always@(data)
begin
bit0=0; bit1=0; bit2=0;
for(n=0; n<8; n=n+1)
begin
if(bit0>4) bit0 = bit0+3;
if(bit1>4) bit1 = bit1+3;
if(bit2>4) bit2 = bit2+3;
{bit2,bit1,bit0} = {bit2,bit1,bit0,data[7-n]};
end
BCD= {bit2, bit1, bit0};
end
endmodule |
module test_bench;
reg [1:0] i;
reg select;
wire y_out;
mux_2_1 dut(i, select, y_out);
always begin
i=$random;
select=$random;
#10;
end
initial
begin $monitor("Input Data : %0d Select Line : %0d Output : %0d ",i, select, y_out);
#100 $finish;
end
endmodule |
module rom(
input clk, r_en,
input [3:0] addr,
output reg [15:0] data);
reg [15:0] mem [15:0];
always@(posedge clk) begin
if(r_en)
data <= mem[addr];
else
data <= 'bz;
end
endmodule |
module test_bench;
reg a, b;
wire xor_out, xnor_out;
gates_mux dut(a, b, xor_out, xnor_out);
initial begin
a= 1'b0; b= 1'b0;
#10 a= 1'b0; b= 1'b1;
#10 a= 1'b1; b= 1'b0;
#10 a= 1'b1; b= 1'b1;
end
initial
begin $monitor("a: %b b: %b xor: %b xnor: %b ",a, b, xor_out, xnor_out );
#40 $finish;
end
endmodule |
Subsets and Splits