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module sirv_AsyncResetRegVec_129(
input clock,
input reset,
input [19:0] io_d,
output [19:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire [1:0] T_28;
wire [1:0] T_29;
wire [2:0] T_30;
wire [4:0] T_31;
wire [1:0] T_32;
wire [1:0] T_33;
wire [2:0] T_34;
wire [4:0] T_35;
wire [9:0] T_36;
wire [1:0] T_37;
wire [1:0] T_38;
wire [2:0] T_39;
wire [4:0] T_40;
wire [1:0] T_41;
wire [1:0] T_42;
wire [2:0] T_43;
wire [4:0] T_44;
wire [9:0] T_45;
wire [19:0] T_46;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
assign io_q = T_46;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = {reg_1_q,reg_0_q};
assign T_29 = {reg_4_q,reg_3_q};
assign T_30 = {T_29,reg_2_q};
assign T_31 = {T_30,T_28};
assign T_32 = {reg_6_q,reg_5_q};
assign T_33 = {reg_9_q,reg_8_q};
assign T_34 = {T_33,reg_7_q};
assign T_35 = {T_34,T_32};
assign T_36 = {T_35,T_31};
assign T_37 = {reg_11_q,reg_10_q};
assign T_38 = {reg_14_q,reg_13_q};
assign T_39 = {T_38,reg_12_q};
assign T_40 = {T_39,T_37};
assign T_41 = {reg_16_q,reg_15_q};
assign T_42 = {reg_19_q,reg_18_q};
assign T_43 = {T_42,reg_17_q};
assign T_44 = {T_43,T_41};
assign T_45 = {T_44,T_40};
assign T_46 = {T_45,T_36};
endmodule |
module e203_lsu(
input commit_mret,
input commit_trap,
input excp_active,
output lsu_active,
`ifdef E203_HAS_ITCM //{
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
output lsu_o_valid, // Handshake valid
input lsu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] lsu_o_wbck_wdat,
output [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag,
output lsu_o_wbck_err ,
output lsu_o_cmt_ld,
output lsu_o_cmt_st,
output [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr,
output lsu_o_cmt_buserr , // The bus-error exception generated
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
input agu_icb_cmd_valid, // Handshake valid
output agu_icb_cmd_ready, // Handshake ready
input [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
input agu_icb_cmd_read, // Read or write
input [`E203_XLEN-1:0] agu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
input agu_icb_cmd_lock,
input agu_icb_cmd_excl,
input [1:0] agu_icb_cmd_size,
// Several additional side channel signals
// Indicate LSU-ctrl module to
// return the ICB response channel back to AGU
// this is only used by AMO or unaligned load/store 1st uop
// to return the response
input agu_icb_cmd_back2agu,
// Sign extension or not
input agu_icb_cmd_usign,
input [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
output agu_icb_rsp_valid, // Response valid
input agu_icb_rsp_ready, // Response ready
output agu_icb_rsp_err , // Response error
output agu_icb_rsp_excl_ok, // Response error
output [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output itcm_icb_cmd_valid,
input itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] itcm_icb_cmd_addr,
output itcm_icb_cmd_read,
output [`E203_XLEN-1:0] itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] itcm_icb_cmd_wmask,
output itcm_icb_cmd_lock,
output itcm_icb_cmd_excl,
output [1:0] itcm_icb_cmd_size,
//
// * Bus RSP channel
input itcm_icb_rsp_valid,
output itcm_icb_rsp_ready,
input itcm_icb_rsp_err ,
input itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output dtcm_icb_cmd_valid,
input dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] dtcm_icb_cmd_addr,
output dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] dtcm_icb_cmd_wmask,
output dtcm_icb_cmd_lock,
output dtcm_icb_cmd_excl,
output [1:0] dtcm_icb_cmd_size,
//
// * Bus RSP channel
input dtcm_icb_rsp_valid,
output dtcm_icb_rsp_ready,
input dtcm_icb_rsp_err ,
input dtcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to BIU
//
// * Bus cmd channel
output biu_icb_cmd_valid,
input biu_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] biu_icb_cmd_addr,
output biu_icb_cmd_read,
output [`E203_XLEN-1:0] biu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] biu_icb_cmd_wmask,
output biu_icb_cmd_lock,
output biu_icb_cmd_excl,
output [1:0] biu_icb_cmd_size,
//
// * Bus RSP channel
input biu_icb_rsp_valid,
output biu_icb_rsp_ready,
input biu_icb_rsp_err ,
input biu_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] biu_icb_rsp_rdata,
input clk,
input rst_n
);
`ifdef E203_HAS_DCACHE //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DCache
//
// * Bus cmd channel
wire dcache_icb_cmd_valid;
wire dcache_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] dcache_icb_cmd_addr;
wire dcache_icb_cmd_read;
wire [`E203_XLEN-1:0] dcache_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] dcache_icb_cmd_wmask;
wire dcache_icb_cmd_lock;
wire dcache_icb_cmd_excl;
wire [1:0] dcache_icb_cmd_size;
//
// * Bus RSP channel
wire dcache_icb_rsp_valid;
wire dcache_icb_rsp_ready;
wire dcache_icb_rsp_err ;
wire dcache_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] dcache_icb_rsp_rdata;
`endif//}
wire lsu_ctrl_active;
e203_lsu_ctrl u_e203_lsu_ctrl(
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_ctrl_active (lsu_ctrl_active),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat),
.lsu_o_wbck_itag (lsu_o_wbck_itag),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld ),
.lsu_o_cmt_st (lsu_o_cmt_st ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock),
.agu_icb_cmd_excl (agu_icb_cmd_excl),
.agu_icb_cmd_size (agu_icb_cmd_size),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifndef E203_HAS_EAI
.eai_mem_holdup (1'b0),
.eai_icb_cmd_valid (1'b0),
.eai_icb_cmd_ready (),
.eai_icb_cmd_addr (`E203_ADDR_SIZE'b0 ),
.eai_icb_cmd_read (1'b0 ),
.eai_icb_cmd_wdata (`E203_XLEN'b0),
.eai_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.eai_icb_cmd_lock (1'b0),
.eai_icb_cmd_excl (1'b0),
.eai_icb_cmd_size (2'b0),
.eai_icb_rsp_valid (),
.eai_icb_rsp_ready (1'b0),
.eai_icb_rsp_err (),
.eai_icb_rsp_excl_ok (),
.eai_icb_rsp_rdata (),
`endif
`ifdef E203_HAS_DCACHE
.dcache_icb_cmd_valid (dcache_icb_cmd_valid),
.dcache_icb_cmd_ready (dcache_icb_cmd_ready),
.dcache_icb_cmd_addr (dcache_icb_cmd_addr ),
.dcache_icb_cmd_read (dcache_icb_cmd_read ),
.dcache_icb_cmd_wdata (dcache_icb_cmd_wdata),
.dcache_icb_cmd_wmask (dcache_icb_cmd_wmask),
.dcache_icb_cmd_lock (dcache_icb_cmd_lock),
.dcache_icb_cmd_excl (dcache_icb_cmd_excl),
.dcache_icb_cmd_size (dcache_icb_cmd_size),
.dcache_icb_rsp_valid (dcache_icb_rsp_valid),
.dcache_icb_rsp_ready (dcache_icb_rsp_ready),
.dcache_icb_rsp_err (dcache_icb_rsp_err ),
.dcache_icb_rsp_excl_ok(dcache_icb_rsp_excl_ok ),
.dcache_icb_rsp_rdata (dcache_icb_rsp_rdata),
`endif
`ifdef E203_HAS_DTCM
.dtcm_icb_cmd_valid (dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (dtcm_icb_cmd_lock),
.dtcm_icb_cmd_excl (dtcm_icb_cmd_excl),
.dtcm_icb_cmd_size (dtcm_icb_cmd_size),
.dtcm_icb_rsp_valid (dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok (dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (dtcm_icb_rsp_rdata),
`endif
`ifdef E203_HAS_ITCM
.itcm_icb_cmd_valid (itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (itcm_icb_cmd_lock),
.itcm_icb_cmd_excl (itcm_icb_cmd_excl),
.itcm_icb_cmd_size (itcm_icb_cmd_size),
.itcm_icb_rsp_valid (itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (itcm_icb_rsp_ready),
.itcm_icb_rsp_err (itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok (itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (itcm_icb_rsp_rdata),
`endif
.biu_icb_cmd_valid (biu_icb_cmd_valid),
.biu_icb_cmd_ready (biu_icb_cmd_ready),
.biu_icb_cmd_addr (biu_icb_cmd_addr ),
.biu_icb_cmd_read (biu_icb_cmd_read ),
.biu_icb_cmd_wdata (biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (biu_icb_cmd_wmask),
.biu_icb_cmd_lock (biu_icb_cmd_lock),
.biu_icb_cmd_excl (biu_icb_cmd_excl),
.biu_icb_cmd_size (biu_icb_cmd_size),
.biu_icb_rsp_valid (biu_icb_rsp_valid),
.biu_icb_rsp_ready (biu_icb_rsp_ready),
.biu_icb_rsp_err (biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok (biu_icb_rsp_excl_ok ),
.biu_icb_rsp_rdata (biu_icb_rsp_rdata),
.clk (clk),
.rst_n (rst_n)
);
assign lsu_active = lsu_ctrl_active
// When interrupts comes, need to update the exclusive monitor
// so also need to turn on the clock
| excp_active;
endmodule |
module e203_exu_longpwbck(
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
input lsu_wbck_i_valid, // Handshake valid
output lsu_wbck_i_ready, // Handshake ready
input [`E203_XLEN-1:0] lsu_wbck_i_wdat,
input [`E203_ITAG_WIDTH -1:0] lsu_wbck_i_itag,
input lsu_wbck_i_err , // The error exception generated
input lsu_cmt_i_buserr ,
input [`E203_ADDR_SIZE -1:0] lsu_cmt_i_badaddr,
input lsu_cmt_i_ld,
input lsu_cmt_i_st,
//////////////////////////////////////////////////////////////
// The Long pipe instruction Wback interface to final wbck module
output longp_wbck_o_valid, // Handshake valid
input longp_wbck_o_ready, // Handshake ready
output [`E203_FLEN-1:0] longp_wbck_o_wdat,
output [5-1:0] longp_wbck_o_flags,
output [`E203_RFIDX_WIDTH -1:0] longp_wbck_o_rdidx,
output longp_wbck_o_rdfpu,
//
// The Long pipe instruction Exception interface to commit stage
output longp_excp_o_valid,
input longp_excp_o_ready,
output longp_excp_o_insterr,
output longp_excp_o_ld,
output longp_excp_o_st,
output longp_excp_o_buserr , // The load/store bus-error exception generated
output [`E203_ADDR_SIZE-1:0] longp_excp_o_badaddr,
output [`E203_PC_SIZE -1:0] longp_excp_o_pc,
//
//The itag of toppest entry of OITF
input oitf_empty,
input [`E203_ITAG_WIDTH -1:0] oitf_ret_ptr,
input [`E203_RFIDX_WIDTH-1:0] oitf_ret_rdidx,
input [`E203_PC_SIZE-1:0] oitf_ret_pc,
input oitf_ret_rdwen,
input oitf_ret_rdfpu,
output oitf_ret_ena,
input clk,
input rst_n
);
// The Long-pipe instruction can write-back only when it's itag
// is same as the itag of toppest entry of OITF
wire wbck_ready4lsu = (lsu_wbck_i_itag == oitf_ret_ptr) & (~oitf_empty);
wire wbck_sel_lsu = lsu_wbck_i_valid & wbck_ready4lsu;
//assign longp_excp_o_ld = wbck_sel_lsu & lsu_cmt_i_ld;
//assign longp_excp_o_st = wbck_sel_lsu & lsu_cmt_i_st;
//assign longp_excp_o_buserr = wbck_sel_lsu & lsu_cmt_i_buserr;
//assign longp_excp_o_badaddr = wbck_sel_lsu ? lsu_cmt_i_badaddr : `E203_ADDR_SIZE'b0;
assign {
longp_excp_o_insterr
,longp_excp_o_ld
,longp_excp_o_st
,longp_excp_o_buserr
,longp_excp_o_badaddr } =
({`E203_ADDR_SIZE+4{wbck_sel_lsu}} &
{
1'b0,
lsu_cmt_i_ld,
lsu_cmt_i_st,
lsu_cmt_i_buserr,
lsu_cmt_i_badaddr
})
;
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface
wire wbck_i_ready;
wire wbck_i_valid;
wire [`E203_FLEN-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
wire [`E203_PC_SIZE-1:0] wbck_i_pc;
wire wbck_i_rdwen;
wire wbck_i_rdfpu;
wire wbck_i_err ;
assign lsu_wbck_i_ready = wbck_ready4lsu & wbck_i_ready;
assign wbck_i_valid = ({1{wbck_sel_lsu}} & lsu_wbck_i_valid)
;
`ifdef E203_FLEN_IS_32 //{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = lsu_wbck_i_wdat;
`else//}{
wire [`E203_FLEN-1:0] lsu_wbck_i_wdat_exd = {{`E203_FLEN-`E203_XLEN{1'b0}},lsu_wbck_i_wdat};
`endif//}
assign wbck_i_wdat = ({`E203_FLEN{wbck_sel_lsu}} & lsu_wbck_i_wdat_exd )
;
assign wbck_i_flags = 5'b0
;
assign wbck_i_err = wbck_sel_lsu & lsu_wbck_i_err
;
assign wbck_i_pc = oitf_ret_pc;
assign wbck_i_rdidx = oitf_ret_rdidx;
assign wbck_i_rdwen = oitf_ret_rdwen;
assign wbck_i_rdfpu = oitf_ret_rdfpu;
// If the instruction have no error and it have the rdwen, then it need to
// write back into regfile, otherwise, it does not need to write regfile
wire need_wbck = wbck_i_rdwen & (~wbck_i_err);
// If the long pipe instruction have error result, then it need to handshake
// with the commit module.
wire need_excp = wbck_i_err;
assign wbck_i_ready =
(need_wbck ? longp_wbck_o_ready : 1'b1)
& (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_wbck_o_valid = need_wbck & wbck_i_valid & (need_excp ? longp_excp_o_ready : 1'b1);
assign longp_excp_o_valid = need_excp & wbck_i_valid & (need_wbck ? longp_wbck_o_ready : 1'b1);
assign longp_wbck_o_wdat = wbck_i_wdat ;
assign longp_wbck_o_flags = wbck_i_flags ;
assign longp_wbck_o_rdfpu = wbck_i_rdfpu ;
assign longp_wbck_o_rdidx = wbck_i_rdidx;
assign longp_excp_o_pc = wbck_i_pc;
assign oitf_ret_ena = wbck_i_valid & wbck_i_ready;
endmodule |
module sirv_flash_qspi_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
wire io_tl_f_0_a_ready;
assign f_icb_cmd_ready = io_tl_f_0_a_ready;
wire io_tl_f_0_a_valid = f_icb_cmd_valid;
wire [2:0] io_tl_f_0_a_bits_opcode = f_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_f_0_a_bits_param = 3'b0;
wire [2:0] io_tl_f_0_a_bits_size = 3'd2;
wire [1:0] io_tl_f_0_a_bits_source = 2'b0;
// We must force the address to be aligned to 32bits
wire [29:0] io_tl_f_0_a_bits_address = {f_icb_cmd_addr[29:2],2'b0};
wire [3:0] io_tl_f_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_f_0_a_bits_data = f_icb_cmd_wdata;
wire io_tl_f_0_d_ready = f_icb_rsp_ready;
wire [2:0] io_tl_f_0_d_bits_opcode;
wire [1:0] io_tl_f_0_d_bits_param;
wire [2:0] io_tl_f_0_d_bits_size;
wire [1:0] io_tl_f_0_d_bits_source;
wire io_tl_f_0_d_bits_sink;
wire [1:0] io_tl_f_0_d_bits_addr_lo;
wire [31:0] io_tl_f_0_d_bits_data;
wire io_tl_f_0_d_bits_error;
wire io_tl_f_0_d_valid;
assign f_icb_rsp_valid = io_tl_f_0_d_valid;
assign f_icb_rsp_rdata = io_tl_f_0_d_bits_data;
// Not used
wire io_tl_f_0_b_ready = 1'b0;
wire io_tl_f_0_b_valid;
wire [2:0] io_tl_f_0_b_bits_opcode;
wire [1:0] io_tl_f_0_b_bits_param;
wire [2:0] io_tl_f_0_b_bits_size;
wire [1:0] io_tl_f_0_b_bits_source;
wire [29:0] io_tl_f_0_b_bits_address;
wire [3:0] io_tl_f_0_b_bits_mask;
wire [31:0] io_tl_f_0_b_bits_data;
// Not used
wire io_tl_f_0_c_ready;
wire io_tl_f_0_c_valid = 1'b0;
wire [2:0] io_tl_f_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_f_0_c_bits_param = 3'b0;
wire [2:0] io_tl_f_0_c_bits_size = 3'd2;
wire [1:0] io_tl_f_0_c_bits_source = 2'b0;
wire [29:0] io_tl_f_0_c_bits_address = 30'b0;
wire [31:0] io_tl_f_0_c_bits_data = 32'b0;
wire io_tl_f_0_c_bits_error = 1'b0;
// Not used
wire io_tl_f_0_e_ready;
wire io_tl_f_0_e_valid = 1'b0;
wire io_tl_f_0_e_bits_sink = 1'b0;
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
wire tl_f_0_a_ready;
wire tl_f_0_a_valid;
wire [2:0] tl_f_0_a_bits_opcode;
wire [2:0] tl_f_0_a_bits_param;
wire [2:0] tl_f_0_a_bits_size;
wire [6:0] tl_f_0_a_bits_source;
wire [29:0] tl_f_0_a_bits_address;
wire tl_f_0_a_bits_mask;
wire [7:0] tl_f_0_a_bits_data;
wire io_in_0_a_ready;
wire io_in_0_a_valid;
wire [2:0] io_in_0_a_bits_opcode;
wire [2:0] io_in_0_a_bits_param;
wire [2:0] io_in_0_a_bits_size;
wire [1:0] io_in_0_a_bits_source;
wire [29:0] io_in_0_a_bits_address;
wire io_in_0_a_bits_mask;
wire [7:0] io_in_0_a_bits_data;
wire io_in_0_b_ready;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [1:0] io_in_0_b_bits_source;
wire [29:0] io_in_0_b_bits_address;
wire io_in_0_b_bits_mask;
wire [7:0] io_in_0_b_bits_data;
wire io_in_0_c_ready;
wire io_in_0_c_valid;
wire [2:0] io_in_0_c_bits_opcode;
wire [2:0] io_in_0_c_bits_param;
wire [2:0] io_in_0_c_bits_size;
wire [1:0] io_in_0_c_bits_source;
wire [29:0] io_in_0_c_bits_address;
wire [7:0] io_in_0_c_bits_data;
wire io_in_0_c_bits_error;
wire io_in_0_d_ready;
wire io_in_0_d_valid;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [1:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire io_in_0_d_bits_addr_lo;
wire [7:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_e_ready;
wire io_in_0_e_valid;
wire io_in_0_e_bits_sink;
wire io_out_0_a_ready;
wire io_out_0_a_valid;
wire [2:0] io_out_0_a_bits_opcode;
wire [2:0] io_out_0_a_bits_param;
wire [2:0] io_out_0_a_bits_size;
wire [6:0] io_out_0_a_bits_source;
wire [29:0] io_out_0_a_bits_address;
wire io_out_0_a_bits_mask;
wire [7:0] io_out_0_a_bits_data;
wire io_out_0_b_ready;
wire io_out_0_b_valid;
wire [2:0] io_out_0_b_bits_opcode;
wire [1:0] io_out_0_b_bits_param;
wire [2:0] io_out_0_b_bits_size;
wire [6:0] io_out_0_b_bits_source;
wire [29:0] io_out_0_b_bits_address;
wire io_out_0_b_bits_mask;
wire [7:0] io_out_0_b_bits_data;
wire io_out_0_c_ready;
wire io_out_0_c_valid;
wire [2:0] io_out_0_c_bits_opcode;
wire [2:0] io_out_0_c_bits_param;
wire [2:0] io_out_0_c_bits_size;
wire [6:0] io_out_0_c_bits_source;
wire [29:0] io_out_0_c_bits_address;
wire [7:0] io_out_0_c_bits_data;
wire io_out_0_c_bits_error;
wire io_out_0_d_ready;
wire io_out_0_d_valid;
wire [2:0] io_out_0_d_bits_opcode;
wire [1:0] io_out_0_d_bits_param;
wire [2:0] io_out_0_d_bits_size;
wire [6:0] io_out_0_d_bits_source;
wire io_out_0_d_bits_sink;
wire io_out_0_d_bits_addr_lo;
wire [7:0] io_out_0_d_bits_data;
wire io_out_0_d_bits_error;
wire io_out_0_e_ready;
wire io_out_0_e_valid;
wire io_out_0_e_bits_sink;
sirv_tlwidthwidget_qspi qspi_TLWidthWidget (
.clock(clk),
.reset(~rst_n),
.io_in_0_a_ready(io_tl_f_0_a_ready),
.io_in_0_a_valid(io_tl_f_0_a_valid),
.io_in_0_a_bits_opcode(io_tl_f_0_a_bits_opcode),
.io_in_0_a_bits_param(io_tl_f_0_a_bits_param),
.io_in_0_a_bits_size(io_tl_f_0_a_bits_size),
.io_in_0_a_bits_source(io_tl_f_0_a_bits_source),
.io_in_0_a_bits_address(io_tl_f_0_a_bits_address),
.io_in_0_a_bits_mask(io_tl_f_0_a_bits_mask),
.io_in_0_a_bits_data(io_tl_f_0_a_bits_data),
.io_in_0_b_ready(io_tl_f_0_b_ready),
.io_in_0_b_valid(io_tl_f_0_b_valid),
.io_in_0_b_bits_opcode(io_tl_f_0_b_bits_opcode),
.io_in_0_b_bits_param(io_tl_f_0_b_bits_param),
.io_in_0_b_bits_size(io_tl_f_0_b_bits_size),
.io_in_0_b_bits_source(io_tl_f_0_b_bits_source),
.io_in_0_b_bits_address(io_tl_f_0_b_bits_address),
.io_in_0_b_bits_mask(io_tl_f_0_b_bits_mask),
.io_in_0_b_bits_data(io_tl_f_0_b_bits_data),
.io_in_0_c_ready(io_tl_f_0_c_ready),
.io_in_0_c_valid(io_tl_f_0_c_valid),
.io_in_0_c_bits_opcode(io_tl_f_0_c_bits_opcode),
.io_in_0_c_bits_param(io_tl_f_0_c_bits_param),
.io_in_0_c_bits_size(io_tl_f_0_c_bits_size),
.io_in_0_c_bits_source(io_tl_f_0_c_bits_source),
.io_in_0_c_bits_address(io_tl_f_0_c_bits_address),
.io_in_0_c_bits_data(io_tl_f_0_c_bits_data),
.io_in_0_c_bits_error(io_tl_f_0_c_bits_error),
.io_in_0_d_ready(io_tl_f_0_d_ready),
.io_in_0_d_valid(io_tl_f_0_d_valid),
.io_in_0_d_bits_opcode(io_tl_f_0_d_bits_opcode),
.io_in_0_d_bits_param(io_tl_f_0_d_bits_param),
.io_in_0_d_bits_size(io_tl_f_0_d_bits_size),
.io_in_0_d_bits_source(io_tl_f_0_d_bits_source),
.io_in_0_d_bits_sink(io_tl_f_0_d_bits_sink),
.io_in_0_d_bits_addr_lo(io_tl_f_0_d_bits_addr_lo),
.io_in_0_d_bits_data(io_tl_f_0_d_bits_data),
.io_in_0_d_bits_error(io_tl_f_0_d_bits_error),
.io_in_0_e_ready(io_tl_f_0_e_ready),
.io_in_0_e_valid(io_tl_f_0_e_valid),
.io_in_0_e_bits_sink(io_tl_f_0_e_bits_sink),
.io_out_0_a_ready(io_in_0_a_ready),
.io_out_0_a_valid(io_in_0_a_valid),
.io_out_0_a_bits_opcode(io_in_0_a_bits_opcode),
.io_out_0_a_bits_param(io_in_0_a_bits_param),
.io_out_0_a_bits_size(io_in_0_a_bits_size),
.io_out_0_a_bits_source(io_in_0_a_bits_source),
.io_out_0_a_bits_address(io_in_0_a_bits_address),
.io_out_0_a_bits_mask(io_in_0_a_bits_mask),
.io_out_0_a_bits_data(io_in_0_a_bits_data),
.io_out_0_b_ready(io_in_0_b_ready),
.io_out_0_b_valid(io_in_0_b_valid),
.io_out_0_b_bits_opcode(io_in_0_b_bits_opcode),
.io_out_0_b_bits_param(io_in_0_b_bits_param),
.io_out_0_b_bits_size(io_in_0_b_bits_size),
.io_out_0_b_bits_source(io_in_0_b_bits_source),
.io_out_0_b_bits_address(io_in_0_b_bits_address),
.io_out_0_b_bits_mask(io_in_0_b_bits_mask),
.io_out_0_b_bits_data(io_in_0_b_bits_data),
.io_out_0_c_ready(io_in_0_c_ready),
.io_out_0_c_valid(io_in_0_c_valid),
.io_out_0_c_bits_opcode(io_in_0_c_bits_opcode),
.io_out_0_c_bits_param(io_in_0_c_bits_param),
.io_out_0_c_bits_size(io_in_0_c_bits_size),
.io_out_0_c_bits_source(io_in_0_c_bits_source),
.io_out_0_c_bits_address(io_in_0_c_bits_address),
.io_out_0_c_bits_data(io_in_0_c_bits_data),
.io_out_0_c_bits_error(io_in_0_c_bits_error),
.io_out_0_d_ready(io_in_0_d_ready),
.io_out_0_d_valid(io_in_0_d_valid),
.io_out_0_d_bits_opcode(io_in_0_d_bits_opcode),
.io_out_0_d_bits_param(io_in_0_d_bits_param),
.io_out_0_d_bits_size(io_in_0_d_bits_size),
.io_out_0_d_bits_source(io_in_0_d_bits_source),
.io_out_0_d_bits_sink(io_in_0_d_bits_sink),
.io_out_0_d_bits_addr_lo(io_in_0_d_bits_addr_lo),
.io_out_0_d_bits_data(io_in_0_d_bits_data),
.io_out_0_d_bits_error(io_in_0_d_bits_error),
.io_out_0_e_ready(io_in_0_e_ready),
.io_out_0_e_valid(io_in_0_e_valid),
.io_out_0_e_bits_sink(io_in_0_e_bits_sink)
);
sirv_tlfragmenter_qspi_1 qspi_TLFragmenter_1 (
.clock (clk ),
.reset (~rst_n),
.io_in_0_a_ready(io_in_0_a_ready),
.io_in_0_a_valid(io_in_0_a_valid),
.io_in_0_a_bits_opcode(io_in_0_a_bits_opcode),
.io_in_0_a_bits_param(io_in_0_a_bits_param),
.io_in_0_a_bits_size(io_in_0_a_bits_size),
.io_in_0_a_bits_source(io_in_0_a_bits_source),
.io_in_0_a_bits_address(io_in_0_a_bits_address),
.io_in_0_a_bits_mask(io_in_0_a_bits_mask),
.io_in_0_a_bits_data(io_in_0_a_bits_data),
.io_in_0_b_ready(io_in_0_b_ready),
.io_in_0_b_valid(io_in_0_b_valid),
.io_in_0_b_bits_opcode(io_in_0_b_bits_opcode),
.io_in_0_b_bits_param(io_in_0_b_bits_param),
.io_in_0_b_bits_size(io_in_0_b_bits_size),
.io_in_0_b_bits_source(io_in_0_b_bits_source),
.io_in_0_b_bits_address(io_in_0_b_bits_address),
.io_in_0_b_bits_mask(io_in_0_b_bits_mask),
.io_in_0_b_bits_data(io_in_0_b_bits_data),
.io_in_0_c_ready(io_in_0_c_ready),
.io_in_0_c_valid(io_in_0_c_valid),
.io_in_0_c_bits_opcode(io_in_0_c_bits_opcode),
.io_in_0_c_bits_param(io_in_0_c_bits_param),
.io_in_0_c_bits_size(io_in_0_c_bits_size),
.io_in_0_c_bits_source(io_in_0_c_bits_source),
.io_in_0_c_bits_address(io_in_0_c_bits_address),
.io_in_0_c_bits_data(io_in_0_c_bits_data),
.io_in_0_c_bits_error(io_in_0_c_bits_error),
.io_in_0_d_ready(io_in_0_d_ready),
.io_in_0_d_valid(io_in_0_d_valid),
.io_in_0_d_bits_opcode(io_in_0_d_bits_opcode),
.io_in_0_d_bits_param(io_in_0_d_bits_param),
.io_in_0_d_bits_size(io_in_0_d_bits_size),
.io_in_0_d_bits_source(io_in_0_d_bits_source),
.io_in_0_d_bits_sink(io_in_0_d_bits_sink),
.io_in_0_d_bits_addr_lo(io_in_0_d_bits_addr_lo),
.io_in_0_d_bits_data(io_in_0_d_bits_data),
.io_in_0_d_bits_error(io_in_0_d_bits_error),
.io_in_0_e_ready(io_in_0_e_ready),
.io_in_0_e_valid(io_in_0_e_valid),
.io_in_0_e_bits_sink(io_in_0_e_bits_sink),
.io_out_0_a_ready(io_out_0_a_ready),
.io_out_0_a_valid(io_out_0_a_valid),
.io_out_0_a_bits_opcode(io_out_0_a_bits_opcode),
.io_out_0_a_bits_param(io_out_0_a_bits_param),
.io_out_0_a_bits_size(io_out_0_a_bits_size),
.io_out_0_a_bits_source(io_out_0_a_bits_source),
.io_out_0_a_bits_address(io_out_0_a_bits_address),
.io_out_0_a_bits_mask(io_out_0_a_bits_mask),
.io_out_0_a_bits_data(io_out_0_a_bits_data),
.io_out_0_b_ready(io_out_0_b_ready),
.io_out_0_b_valid(io_out_0_b_valid),
.io_out_0_b_bits_opcode(io_out_0_b_bits_opcode),
.io_out_0_b_bits_param(io_out_0_b_bits_param),
.io_out_0_b_bits_size(io_out_0_b_bits_size),
.io_out_0_b_bits_source(io_out_0_b_bits_source),
.io_out_0_b_bits_address(io_out_0_b_bits_address),
.io_out_0_b_bits_mask(io_out_0_b_bits_mask),
.io_out_0_b_bits_data(io_out_0_b_bits_data),
.io_out_0_c_ready(io_out_0_c_ready),
.io_out_0_c_valid(io_out_0_c_valid),
.io_out_0_c_bits_opcode(io_out_0_c_bits_opcode),
.io_out_0_c_bits_param(io_out_0_c_bits_param),
.io_out_0_c_bits_size(io_out_0_c_bits_size),
.io_out_0_c_bits_source(io_out_0_c_bits_source),
.io_out_0_c_bits_address(io_out_0_c_bits_address),
.io_out_0_c_bits_data(io_out_0_c_bits_data),
.io_out_0_c_bits_error(io_out_0_c_bits_error),
.io_out_0_d_ready(io_out_0_d_ready),
.io_out_0_d_valid(io_out_0_d_valid),
.io_out_0_d_bits_opcode(io_out_0_d_bits_opcode),
.io_out_0_d_bits_param(io_out_0_d_bits_param),
.io_out_0_d_bits_size(io_out_0_d_bits_size),
.io_out_0_d_bits_source(io_out_0_d_bits_source),
.io_out_0_d_bits_sink(io_out_0_d_bits_sink),
.io_out_0_d_bits_addr_lo(io_out_0_d_bits_addr_lo),
.io_out_0_d_bits_data(io_out_0_d_bits_data),
.io_out_0_d_bits_error(io_out_0_d_bits_error),
.io_out_0_e_ready(io_out_0_e_ready),
.io_out_0_e_valid(io_out_0_e_valid),
.io_out_0_e_bits_sink(io_out_0_e_bits_sink)
);
sirv_flash_qspi u_sirv_flash_qspi(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_tl_f_0_a_ready (io_out_0_a_ready ),
.io_tl_f_0_a_valid (io_out_0_a_valid ),
.io_tl_f_0_a_bits_opcode (io_out_0_a_bits_opcode ),
.io_tl_f_0_a_bits_param (io_out_0_a_bits_param ),
.io_tl_f_0_a_bits_size (io_out_0_a_bits_size ),
.io_tl_f_0_a_bits_source (io_out_0_a_bits_source ),
.io_tl_f_0_a_bits_address (io_out_0_a_bits_address ),
.io_tl_f_0_a_bits_mask (io_out_0_a_bits_mask ),
.io_tl_f_0_a_bits_data (io_out_0_a_bits_data ),
.io_tl_f_0_b_ready (io_out_0_b_ready ),
.io_tl_f_0_b_valid (io_out_0_b_valid ),
.io_tl_f_0_b_bits_opcode (io_out_0_b_bits_opcode ),
.io_tl_f_0_b_bits_param (io_out_0_b_bits_param ),
.io_tl_f_0_b_bits_size (io_out_0_b_bits_size ),
.io_tl_f_0_b_bits_source (io_out_0_b_bits_source ),
.io_tl_f_0_b_bits_address (io_out_0_b_bits_address ),
.io_tl_f_0_b_bits_mask (io_out_0_b_bits_mask ),
.io_tl_f_0_b_bits_data (io_out_0_b_bits_data ),
.io_tl_f_0_c_ready (io_out_0_c_ready ),
.io_tl_f_0_c_valid (io_out_0_c_valid ),
.io_tl_f_0_c_bits_opcode (io_out_0_c_bits_opcode ),
.io_tl_f_0_c_bits_param (io_out_0_c_bits_param ),
.io_tl_f_0_c_bits_size (io_out_0_c_bits_size ),
.io_tl_f_0_c_bits_source (io_out_0_c_bits_source ),
.io_tl_f_0_c_bits_address (io_out_0_c_bits_address ),
.io_tl_f_0_c_bits_data (io_out_0_c_bits_data ),
.io_tl_f_0_c_bits_error (io_out_0_c_bits_error ),
.io_tl_f_0_d_ready (io_out_0_d_ready ),
.io_tl_f_0_d_valid (io_out_0_d_valid ),
.io_tl_f_0_d_bits_opcode (io_out_0_d_bits_opcode ),
.io_tl_f_0_d_bits_param (io_out_0_d_bits_param ),
.io_tl_f_0_d_bits_size (io_out_0_d_bits_size ),
.io_tl_f_0_d_bits_source (io_out_0_d_bits_source ),
.io_tl_f_0_d_bits_sink (io_out_0_d_bits_sink ),
.io_tl_f_0_d_bits_addr_lo (io_out_0_d_bits_addr_lo ),
.io_tl_f_0_d_bits_data (io_out_0_d_bits_data ),
.io_tl_f_0_d_bits_error (io_out_0_d_bits_error ),
.io_tl_f_0_e_ready (io_out_0_e_ready ),
.io_tl_f_0_e_valid (io_out_0_e_valid ),
.io_tl_f_0_e_bits_sink (io_out_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule |
module sirv_tlwidthwidget_qspi(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [1:0] io_in_0_a_bits_source,
input [29:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [1:0] io_in_0_b_bits_source,
output [29:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [1:0] io_in_0_c_bits_source,
input [29:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [1:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_out_0_a_ready,
output io_out_0_a_valid,
output [2:0] io_out_0_a_bits_opcode,
output [2:0] io_out_0_a_bits_param,
output [2:0] io_out_0_a_bits_size,
output [1:0] io_out_0_a_bits_source,
output [29:0] io_out_0_a_bits_address,
output io_out_0_a_bits_mask,
output [7:0] io_out_0_a_bits_data,
output io_out_0_b_ready,
input io_out_0_b_valid,
input [2:0] io_out_0_b_bits_opcode,
input [1:0] io_out_0_b_bits_param,
input [2:0] io_out_0_b_bits_size,
input [1:0] io_out_0_b_bits_source,
input [29:0] io_out_0_b_bits_address,
input io_out_0_b_bits_mask,
input [7:0] io_out_0_b_bits_data,
input io_out_0_c_ready,
output io_out_0_c_valid,
output [2:0] io_out_0_c_bits_opcode,
output [2:0] io_out_0_c_bits_param,
output [2:0] io_out_0_c_bits_size,
output [1:0] io_out_0_c_bits_source,
output [29:0] io_out_0_c_bits_address,
output [7:0] io_out_0_c_bits_data,
output io_out_0_c_bits_error,
output io_out_0_d_ready,
input io_out_0_d_valid,
input [2:0] io_out_0_d_bits_opcode,
input [1:0] io_out_0_d_bits_param,
input [2:0] io_out_0_d_bits_size,
input [1:0] io_out_0_d_bits_source,
input io_out_0_d_bits_sink,
input io_out_0_d_bits_addr_lo,
input [7:0] io_out_0_d_bits_data,
input io_out_0_d_bits_error,
input io_out_0_e_ready,
output io_out_0_e_valid,
output io_out_0_e_bits_sink
);
wire T_1403;
wire Repeater_5_1_clock;
wire Repeater_5_1_reset;
wire Repeater_5_1_io_repeat;
wire Repeater_5_1_io_full;
wire Repeater_5_1_io_enq_ready;
wire Repeater_5_1_io_enq_valid;
wire [2:0] Repeater_5_1_io_enq_bits_opcode;
wire [2:0] Repeater_5_1_io_enq_bits_param;
wire [2:0] Repeater_5_1_io_enq_bits_size;
wire [1:0] Repeater_5_1_io_enq_bits_source;
wire [29:0] Repeater_5_1_io_enq_bits_address;
wire [3:0] Repeater_5_1_io_enq_bits_mask;
wire [31:0] Repeater_5_1_io_enq_bits_data;
wire Repeater_5_1_io_deq_ready;
wire Repeater_5_1_io_deq_valid;
wire [2:0] Repeater_5_1_io_deq_bits_opcode;
wire [2:0] Repeater_5_1_io_deq_bits_param;
wire [2:0] Repeater_5_1_io_deq_bits_size;
wire [1:0] Repeater_5_1_io_deq_bits_source;
wire [29:0] Repeater_5_1_io_deq_bits_address;
wire [3:0] Repeater_5_1_io_deq_bits_mask;
wire [31:0] Repeater_5_1_io_deq_bits_data;
wire [7:0] T_1408;
wire [7:0] T_1409;
wire [7:0] T_1410;
wire [7:0] T_1411;
wire [7:0] T_1419_0;
wire [7:0] T_1419_1;
wire [7:0] T_1419_2;
wire [7:0] T_1419_3;
wire T_1426;
wire T_1427;
wire T_1428;
wire T_1429;
wire T_1437_0;
wire T_1437_1;
wire T_1437_2;
wire T_1437_3;
reg [3:0] T_1447;
reg [31:0] GEN_28;
wire [8:0] T_1458;
wire [1:0] T_1459;
wire [1:0] T_1460;
wire T_1463;
wire T_1465;
wire T_1466;
wire T_1468;
wire T_1472;
wire [1:0] T_1473;
wire [1:0] T_1474;
wire [3:0] T_1475;
wire [4:0] GEN_12;
wire [4:0] T_1476;
wire [4:0] T_1477;
wire T_1482;
wire [4:0] GEN_2;
wire [1:0] T_1487;
wire [1:0] T_1488;
wire [3:0] T_1489;
wire [4:0] GEN_13;
wire [4:0] T_1490;
wire T_1492;
wire T_1493;
wire T_1494;
wire T_1495;
wire T_1497;
wire T_1499;
wire T_1501;
wire T_1503;
wire T_1505;
wire T_1506;
wire T_1507;
wire T_1508;
reg [23:0] T_1512;
reg [31:0] GEN_29;
reg [2:0] T_1514;
reg [31:0] GEN_30;
wire [31:0] T_1515;
wire [3:0] T_1523;
reg [1:0] T_1527;
reg [31:0] GEN_31;
wire [8:0] T_1532;
wire [1:0] T_1533;
wire [1:0] T_1534;
wire T_1536;
wire T_1540;
wire [23:0] T_1541;
wire [2:0] T_1542;
wire [2:0] T_1544;
wire [1:0] T_1545;
wire [1:0] GEN_3;
wire [23:0] GEN_4;
wire [2:0] GEN_5;
wire [1:0] GEN_6;
wire [7:0] T_1547;
wire [15:0] T_1548;
wire [31:0] T_1549;
wire T_1550;
wire [3:0] T_1554;
wire [15:0] T_1555;
wire [31:0] T_1556;
wire [1:0] T_1557;
wire [3:0] T_1558;
wire [31:0] T_1570_0;
wire [31:0] T_1570_1;
wire [31:0] T_1570_2;
wire [31:0] T_1570_3;
wire [31:0] T_1570_4;
wire [31:0] T_1570_5;
wire [3:0] T_1588_0;
wire [3:0] T_1588_1;
wire [3:0] T_1588_2;
wire [3:0] T_1588_3;
wire [3:0] T_1588_4;
wire [3:0] T_1588_5;
wire T_1599;
wire T_1600;
wire T_1601;
wire [31:0] GEN_0;
wire [31:0] GEN_7;
wire [31:0] GEN_8;
wire [31:0] GEN_9;
wire [31:0] GEN_10;
wire [31:0] GEN_11;
wire [2:0] GEN_1 = 3'b0;
reg [31:0] GEN_32;
wire [1:0] GEN_14 = 2'b0;
reg [31:0] GEN_33;
wire [2:0] GEN_15 = 3'b0;
reg [31:0] GEN_34;
wire [1:0] GEN_16 = 2'b0;
reg [31:0] GEN_35;
wire [29:0] GEN_17 = 30'b0;
reg [31:0] GEN_36;
wire [3:0] GEN_18 = 4'b0;
reg [31:0] GEN_37;
wire [31:0] GEN_19 = 32'b0;
reg [31:0] GEN_38;
wire [2:0] GEN_20 = 3'b0;
reg [31:0] GEN_39;
wire [2:0] GEN_21 = 3'b0;
reg [31:0] GEN_40;
wire [2:0] GEN_22 = 3'b0;
reg [31:0] GEN_41;
wire [1:0] GEN_23 = 2'b0;
reg [31:0] GEN_42;
wire [29:0] GEN_24 = 30'b0;
reg [31:0] GEN_43;
wire [7:0] GEN_25 = 8'b0;
reg [31:0] GEN_44;
wire GEN_26 = 1'b0;
reg [31:0] GEN_45;
wire GEN_27 = 1'b0;
reg [31:0] GEN_46;
sirv_tl_repeater_5 Repeater_5_1 (
.clock(Repeater_5_1_clock),
.reset(Repeater_5_1_reset),
.io_repeat(Repeater_5_1_io_repeat),
.io_full(Repeater_5_1_io_full),
.io_enq_ready(Repeater_5_1_io_enq_ready),
.io_enq_valid(Repeater_5_1_io_enq_valid),
.io_enq_bits_opcode(Repeater_5_1_io_enq_bits_opcode),
.io_enq_bits_param(Repeater_5_1_io_enq_bits_param),
.io_enq_bits_size(Repeater_5_1_io_enq_bits_size),
.io_enq_bits_source(Repeater_5_1_io_enq_bits_source),
.io_enq_bits_address(Repeater_5_1_io_enq_bits_address),
.io_enq_bits_mask(Repeater_5_1_io_enq_bits_mask),
.io_enq_bits_data(Repeater_5_1_io_enq_bits_data),
.io_deq_ready(Repeater_5_1_io_deq_ready),
.io_deq_valid(Repeater_5_1_io_deq_valid),
.io_deq_bits_opcode(Repeater_5_1_io_deq_bits_opcode),
.io_deq_bits_param(Repeater_5_1_io_deq_bits_param),
.io_deq_bits_size(Repeater_5_1_io_deq_bits_size),
.io_deq_bits_source(Repeater_5_1_io_deq_bits_source),
.io_deq_bits_address(Repeater_5_1_io_deq_bits_address),
.io_deq_bits_mask(Repeater_5_1_io_deq_bits_mask),
.io_deq_bits_data(Repeater_5_1_io_deq_bits_data)
);
assign io_in_0_a_ready = Repeater_5_1_io_enq_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_1;
assign io_in_0_b_bits_param = GEN_14;
assign io_in_0_b_bits_size = GEN_15;
assign io_in_0_b_bits_source = GEN_16;
assign io_in_0_b_bits_address = GEN_17;
assign io_in_0_b_bits_mask = GEN_18;
assign io_in_0_b_bits_data = GEN_19;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_1601;
assign io_in_0_d_bits_opcode = io_out_0_d_bits_opcode;
assign io_in_0_d_bits_param = io_out_0_d_bits_param;
assign io_in_0_d_bits_size = io_out_0_d_bits_size;
assign io_in_0_d_bits_source = io_out_0_d_bits_source;
assign io_in_0_d_bits_sink = io_out_0_d_bits_sink;
assign io_in_0_d_bits_addr_lo = {{1'd0}, io_out_0_d_bits_addr_lo};
assign io_in_0_d_bits_data = GEN_0;
assign io_in_0_d_bits_error = io_out_0_d_bits_error;
assign io_in_0_e_ready = 1'h1;
assign io_out_0_a_valid = Repeater_5_1_io_deq_valid;
assign io_out_0_a_bits_opcode = Repeater_5_1_io_deq_bits_opcode;
assign io_out_0_a_bits_param = Repeater_5_1_io_deq_bits_param;
assign io_out_0_a_bits_size = Repeater_5_1_io_deq_bits_size;
assign io_out_0_a_bits_source = Repeater_5_1_io_deq_bits_source;
assign io_out_0_a_bits_address = Repeater_5_1_io_deq_bits_address;
assign io_out_0_a_bits_mask = T_1508;
assign io_out_0_a_bits_data = 8'h0;
assign io_out_0_b_ready = 1'h1;
assign io_out_0_c_valid = 1'h0;
assign io_out_0_c_bits_opcode = GEN_20;
assign io_out_0_c_bits_param = GEN_21;
assign io_out_0_c_bits_size = GEN_22;
assign io_out_0_c_bits_source = GEN_23;
assign io_out_0_c_bits_address = GEN_24;
assign io_out_0_c_bits_data = GEN_25;
assign io_out_0_c_bits_error = GEN_26;
assign io_out_0_d_ready = T_1600;
assign io_out_0_e_valid = 1'h0;
assign io_out_0_e_bits_sink = GEN_27;
assign T_1403 = 1'h0;
assign Repeater_5_1_clock = clock;
assign Repeater_5_1_reset = reset;
assign Repeater_5_1_io_repeat = T_1403;
assign Repeater_5_1_io_enq_valid = io_in_0_a_valid;
assign Repeater_5_1_io_enq_bits_opcode = io_in_0_a_bits_opcode;
assign Repeater_5_1_io_enq_bits_param = io_in_0_a_bits_param;
assign Repeater_5_1_io_enq_bits_size = io_in_0_a_bits_size;
assign Repeater_5_1_io_enq_bits_source = io_in_0_a_bits_source;
assign Repeater_5_1_io_enq_bits_address = io_in_0_a_bits_address;
assign Repeater_5_1_io_enq_bits_mask = io_in_0_a_bits_mask;
assign Repeater_5_1_io_enq_bits_data = io_in_0_a_bits_data;
assign Repeater_5_1_io_deq_ready = io_out_0_a_ready;
assign T_1408 = Repeater_5_1_io_deq_bits_data[7:0];
assign T_1409 = Repeater_5_1_io_deq_bits_data[15:8];
assign T_1410 = Repeater_5_1_io_deq_bits_data[23:16];
assign T_1411 = Repeater_5_1_io_deq_bits_data[31:24];
assign T_1419_0 = T_1408;
assign T_1419_1 = T_1409;
assign T_1419_2 = T_1410;
assign T_1419_3 = T_1411;
assign T_1426 = Repeater_5_1_io_deq_bits_mask[0];
assign T_1427 = Repeater_5_1_io_deq_bits_mask[1];
assign T_1428 = Repeater_5_1_io_deq_bits_mask[2];
assign T_1429 = Repeater_5_1_io_deq_bits_mask[3];
assign T_1437_0 = T_1426;
assign T_1437_1 = T_1427;
assign T_1437_2 = T_1428;
assign T_1437_3 = T_1429;
assign T_1458 = 9'h3 << Repeater_5_1_io_deq_bits_size;
assign T_1459 = T_1458[1:0];
assign T_1460 = ~ T_1459;
assign T_1463 = T_1460[0];
assign T_1465 = T_1463 == 1'h0;
assign T_1466 = T_1460[1];
assign T_1468 = T_1466 == 1'h0;
assign T_1472 = T_1447[3];
assign T_1473 = {T_1465,1'h1};
assign T_1474 = {T_1465,T_1468};
assign T_1475 = {T_1474,T_1473};
assign GEN_12 = {{1'd0}, T_1447};
assign T_1476 = GEN_12 << 1;
assign T_1477 = T_1472 ? {{1'd0}, T_1475} : T_1476;
assign T_1482 = io_out_0_a_ready & io_out_0_a_valid;
assign GEN_2 = T_1482 ? 5'hf : {{1'd0}, T_1447};
assign T_1487 = {T_1437_1,T_1437_0};
assign T_1488 = {T_1437_3,T_1437_2};
assign T_1489 = {T_1488,T_1487};
assign GEN_13 = {{1'd0}, T_1489};
assign T_1490 = GEN_13 & T_1477;
assign T_1492 = T_1490[0];
assign T_1493 = T_1490[1];
assign T_1494 = T_1490[2];
assign T_1495 = T_1490[3];
assign T_1497 = T_1492 ? T_1437_0 : 1'h0;
assign T_1499 = T_1493 ? T_1437_1 : 1'h0;
assign T_1501 = T_1494 ? T_1437_2 : 1'h0;
assign T_1503 = T_1495 ? T_1437_3 : 1'h0;
assign T_1505 = T_1497 | T_1499;
assign T_1506 = T_1505 | T_1501;
assign T_1507 = T_1506 | T_1503;
assign T_1508 = T_1507;
assign T_1515 = {io_out_0_d_bits_data,T_1512};
assign T_1523 = {1'h1,T_1514};
assign T_1532 = 9'h3 << io_out_0_d_bits_size;
assign T_1533 = T_1532[1:0];
assign T_1534 = ~ T_1533;
assign T_1536 = T_1527 == T_1534;
assign T_1540 = io_out_0_d_ready & io_out_0_d_valid;
assign T_1541 = T_1515[31:8];
assign T_1542 = T_1523[3:1];
assign T_1544 = T_1527 + 2'h1;
assign T_1545 = T_1544[1:0];
assign GEN_3 = T_1536 ? 2'h0 : T_1545;
assign GEN_4 = T_1540 ? T_1541 : T_1512;
assign GEN_5 = T_1540 ? T_1542 : T_1514;
assign GEN_6 = T_1540 ? GEN_3 : T_1527;
assign T_1547 = T_1515[31:24];
assign T_1548 = {T_1547,T_1547};
assign T_1549 = {T_1548,T_1548};
assign T_1550 = T_1523[3];
assign T_1554 = T_1550 ? 4'hf : 4'h0;
assign T_1555 = T_1515[31:16];
assign T_1556 = {T_1555,T_1555};
assign T_1557 = T_1523[3:2];
assign T_1558 = {T_1557,T_1557};
assign T_1570_0 = T_1549;
assign T_1570_1 = T_1556;
assign T_1570_2 = T_1515;
assign T_1570_3 = T_1515;
assign T_1570_4 = T_1515;
assign T_1570_5 = T_1515;
assign T_1588_0 = T_1554;
assign T_1588_1 = T_1558;
assign T_1588_2 = T_1523;
assign T_1588_3 = T_1523;
assign T_1588_4 = T_1523;
assign T_1588_5 = T_1523;
assign T_1599 = T_1536 == 1'h0;
assign T_1600 = io_in_0_d_ready | T_1599;
assign T_1601 = io_out_0_d_valid & T_1536;
assign GEN_0 = GEN_11;
assign GEN_7 = 3'h1 == io_out_0_d_bits_size ? T_1570_1 : T_1570_0;
assign GEN_8 = 3'h2 == io_out_0_d_bits_size ? T_1570_2 : GEN_7;
assign GEN_9 = 3'h3 == io_out_0_d_bits_size ? T_1570_3 : GEN_8;
assign GEN_10 = 3'h4 == io_out_0_d_bits_size ? T_1570_4 : GEN_9;
assign GEN_11 = 3'h5 == io_out_0_d_bits_size ? T_1570_5 : GEN_10;
always @(posedge clock or posedge reset)
if (reset) begin
T_1447 <= 4'hf;
end else begin
T_1447 <= GEN_2[3:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
T_1512 <= 24'b0;
T_1514 <= 3'b0;
end
else begin
if (T_1540) begin
T_1512 <= T_1541;
end
if (T_1540) begin
T_1514 <= T_1542;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_1527 <= 2'h0;
end else begin
if (T_1540) begin
if (T_1536) begin
T_1527 <= 2'h0;
end else begin
T_1527 <= T_1545;
end
end
end
endmodule |
module sirv_aon_porrst(
output porrst_n
);
`ifdef FPGA_SOURCE//{
// In FPGA, we have no PORRST circult
assign porrst_n = 1'b1;
`else //}{
assign porrst_n = 1'b1;
`endif//}
endmodule |
module e203_exu_alu(
//////////////////////////////////////////////////////////////
// The operands and decode info from dispatch
input i_valid,
output i_ready,
output i_longpipe, // Indicate this instruction is
// issued as a long pipe instruction
`ifdef E203_HAS_CSR_EAI//{
`ifndef E203_HAS_EAI
input eai_xs_off,
`endif//
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
output amo_wait,
input oitf_empty,
input [`E203_ITAG_WIDTH-1:0] i_itag,
input [`E203_XLEN-1:0] i_rs1,
input [`E203_XLEN-1:0] i_rs2,
input [`E203_XLEN-1:0] i_imm,
input [`E203_DECINFO_WIDTH-1:0] i_info,
input [`E203_PC_SIZE-1:0] i_pc,
input [`E203_INSTR_SIZE-1:0] i_instr,
input i_pc_vld,
input [`E203_RFIDX_WIDTH-1:0] i_rdidx,
input i_rdwen,
input i_ilegl,
input i_buserr,
input i_misalgn,
input flush_req,
input flush_pulse,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Commit Interface
output cmt_o_valid, // Handshake valid
input cmt_o_ready, // Handshake ready
output cmt_o_pc_vld,
output [`E203_PC_SIZE-1:0] cmt_o_pc,
output [`E203_INSTR_SIZE-1:0] cmt_o_instr,
output [`E203_XLEN-1:0] cmt_o_imm,// The resolved ture/false
// The Branch and Jump Commit
output cmt_o_rv32,// The predicted ture/false
output cmt_o_bjp,
output cmt_o_mret,
output cmt_o_dret,
output cmt_o_ecall,
output cmt_o_ebreak,
output cmt_o_fencei,
output cmt_o_wfi,
output cmt_o_ifu_misalgn,
output cmt_o_ifu_buserr,
output cmt_o_ifu_ilegl,
output cmt_o_bjp_prdt,// The predicted ture/false
output cmt_o_bjp_rslv,// The resolved ture/false
// The AGU Exception
output cmt_o_misalgn, // The misalign exception generated
output cmt_o_ld,
output cmt_o_stamo,
output cmt_o_buserr , // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] cmt_o_badaddr,
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
output wbck_o_valid, // Handshake valid
input wbck_o_ready, // Handshake ready
output [`E203_XLEN-1:0] wbck_o_wdat,
output [`E203_RFIDX_WIDTH-1:0] wbck_o_rdidx,
input mdv_nob2b,
//////////////////////////////////////////////////////////////
// The CSR Interface
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input nonflush_cmt_ena,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_usign,
output [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
input clk,
input rst_n
);
//////////////////////////////////////////////////////////////
// Dispatch to different sub-modules according to their types
wire ifu_excp_op = i_ilegl | i_buserr | i_misalgn;
wire alu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_ALU);
wire agu_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_AGU);
wire bjp_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_BJP);
wire csr_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_CSR);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_op = (~ifu_excp_op) & (i_info[`E203_DECINFO_GRP] == `E203_DECINFO_GRP_MULDIV);
`endif//E203_SUPPORT_SHARE_MULDIV}
// The ALU incoming instruction may go to several different targets:
// * The ALUDATAPATH if it is a regular ALU instructions
// * The Branch-cmp if it is a BJP instructions
// * The AGU if it is a load/store relevant instructions
// * The MULDIV if it is a MUL/DIV relevant instructions and MULDIV
// is reusing the ALU adder
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_valid = i_valid & mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_valid = i_valid & agu_op;
wire alu_i_valid = i_valid & alu_op;
wire bjp_i_valid = i_valid & bjp_op;
wire csr_i_valid = i_valid & csr_op;
wire ifu_excp_i_valid = i_valid & ifu_excp_op;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
wire agu_i_ready;
wire alu_i_ready;
wire bjp_i_ready;
wire csr_i_ready;
wire ifu_excp_i_ready;
assign i_ready = (agu_i_ready & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_ready & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
| (alu_i_ready & alu_op)
| (ifu_excp_i_ready & ifu_excp_op)
| (bjp_i_ready & bjp_op)
| (csr_i_ready & csr_op)
;
wire agu_i_longpipe;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire mdv_i_longpipe;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign i_longpipe = (agu_i_longpipe & agu_op)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (mdv_i_longpipe & mdv_op)
`endif//E203_SUPPORT_SHARE_MULDIV}
;
//////////////////////////////////////////////////////////////
// Instantiate the CSR module
//
wire csr_o_valid;
wire csr_o_ready;
wire [`E203_XLEN-1:0] csr_o_wbck_wdat;
wire csr_o_wbck_err;
wire [`E203_XLEN-1:0] csr_i_rs1 = {`E203_XLEN {csr_op}} & i_rs1;
wire [`E203_XLEN-1:0] csr_i_rs2 = {`E203_XLEN {csr_op}} & i_rs2;
wire [`E203_XLEN-1:0] csr_i_imm = {`E203_XLEN {csr_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] csr_i_info = {`E203_DECINFO_WIDTH{csr_op}} & i_info;
wire csr_i_rdwen = csr_op & i_rdwen;
`ifndef E203_HAS_EAI//{
wire eai_o_cmt_wr_reg;
wire csr_sel_eai;
`endif//}
e203_exu_alu_csrctrl u_e203_exu_alu_csrctrl(
`ifdef E203_HAS_CSR_EAI//{
.csr_sel_eai (csr_sel_eai),
.eai_xs_off (eai_xs_off),
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.csr_access_ilgl (csr_access_ilgl),
.csr_i_valid (csr_i_valid),
.csr_i_ready (csr_i_ready),
.csr_i_rs1 (csr_i_rs1 ),
.csr_i_info (csr_i_info[`E203_DECINFO_CSR_WIDTH-1:0]),
.csr_i_rdwen (csr_i_rdwen),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.csr_o_valid (csr_o_valid ),
.csr_o_ready (csr_o_ready ),
.csr_o_wbck_wdat (csr_o_wbck_wdat ),
.csr_o_wbck_err (csr_o_wbck_err ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the BJP module
//
wire bjp_o_valid;
wire bjp_o_ready;
wire [`E203_XLEN-1:0] bjp_o_wbck_wdat;
wire bjp_o_wbck_err;
wire bjp_o_cmt_bjp;
wire bjp_o_cmt_mret;
wire bjp_o_cmt_dret;
wire bjp_o_cmt_fencei;
wire bjp_o_cmt_prdt;
wire bjp_o_cmt_rslv;
wire [`E203_XLEN-1:0] bjp_req_alu_op1;
wire [`E203_XLEN-1:0] bjp_req_alu_op2;
wire bjp_req_alu_cmp_eq ;
wire bjp_req_alu_cmp_ne ;
wire bjp_req_alu_cmp_lt ;
wire bjp_req_alu_cmp_gt ;
wire bjp_req_alu_cmp_ltu;
wire bjp_req_alu_cmp_gtu;
wire bjp_req_alu_add;
wire bjp_req_alu_cmp_res;
wire [`E203_XLEN-1:0] bjp_req_alu_add_res;
wire [`E203_XLEN-1:0] bjp_i_rs1 = {`E203_XLEN {bjp_op}} & i_rs1;
wire [`E203_XLEN-1:0] bjp_i_rs2 = {`E203_XLEN {bjp_op}} & i_rs2;
wire [`E203_XLEN-1:0] bjp_i_imm = {`E203_XLEN {bjp_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] bjp_i_info = {`E203_DECINFO_WIDTH{bjp_op}} & i_info;
wire [`E203_PC_SIZE-1:0] bjp_i_pc = {`E203_PC_SIZE {bjp_op}} & i_pc;
e203_exu_alu_bjp u_e203_exu_alu_bjp(
.bjp_i_valid (bjp_i_valid ),
.bjp_i_ready (bjp_i_ready ),
.bjp_i_rs1 (bjp_i_rs1 ),
.bjp_i_rs2 (bjp_i_rs2 ),
.bjp_i_info (bjp_i_info[`E203_DECINFO_BJP_WIDTH-1:0]),
.bjp_i_imm (bjp_i_imm ),
.bjp_i_pc (bjp_i_pc ),
.bjp_o_valid (bjp_o_valid ),
.bjp_o_ready (bjp_o_ready ),
.bjp_o_wbck_wdat (bjp_o_wbck_wdat ),
.bjp_o_wbck_err (bjp_o_wbck_err ),
.bjp_o_cmt_bjp (bjp_o_cmt_bjp ),
.bjp_o_cmt_mret (bjp_o_cmt_mret ),
.bjp_o_cmt_dret (bjp_o_cmt_dret ),
.bjp_o_cmt_fencei (bjp_o_cmt_fencei ),
.bjp_o_cmt_prdt (bjp_o_cmt_prdt ),
.bjp_o_cmt_rslv (bjp_o_cmt_rslv ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the AGU module
//
wire agu_o_valid;
wire agu_o_ready;
wire [`E203_XLEN-1:0] agu_o_wbck_wdat;
wire agu_o_wbck_err;
wire agu_o_cmt_misalgn;
wire agu_o_cmt_ld;
wire agu_o_cmt_stamo;
wire agu_o_cmt_buserr ;
wire [`E203_ADDR_SIZE-1:0]agu_o_cmt_badaddr ;
wire [`E203_XLEN-1:0] agu_req_alu_op1;
wire [`E203_XLEN-1:0] agu_req_alu_op2;
wire agu_req_alu_swap;
wire agu_req_alu_add ;
wire agu_req_alu_and ;
wire agu_req_alu_or ;
wire agu_req_alu_xor ;
wire agu_req_alu_max ;
wire agu_req_alu_min ;
wire agu_req_alu_maxu;
wire agu_req_alu_minu;
wire [`E203_XLEN-1:0] agu_req_alu_res;
wire agu_sbf_0_ena;
wire [`E203_XLEN-1:0] agu_sbf_0_nxt;
wire [`E203_XLEN-1:0] agu_sbf_0_r;
wire agu_sbf_1_ena;
wire [`E203_XLEN-1:0] agu_sbf_1_nxt;
wire [`E203_XLEN-1:0] agu_sbf_1_r;
wire [`E203_XLEN-1:0] agu_i_rs1 = {`E203_XLEN {agu_op}} & i_rs1;
wire [`E203_XLEN-1:0] agu_i_rs2 = {`E203_XLEN {agu_op}} & i_rs2;
wire [`E203_XLEN-1:0] agu_i_imm = {`E203_XLEN {agu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] agu_i_info = {`E203_DECINFO_WIDTH{agu_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] agu_i_itag = {`E203_ITAG_WIDTH {agu_op}} & i_itag;
e203_exu_alu_lsuagu u_e203_exu_alu_lsuagu(
.agu_i_valid (agu_i_valid ),
.agu_i_ready (agu_i_ready ),
.agu_i_rs1 (agu_i_rs1 ),
.agu_i_rs2 (agu_i_rs2 ),
.agu_i_imm (agu_i_imm ),
.agu_i_info (agu_i_info[`E203_DECINFO_AGU_WIDTH-1:0]),
.agu_i_longpipe (agu_i_longpipe ),
.agu_i_itag (agu_i_itag ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.amo_wait (amo_wait),
.oitf_empty (oitf_empty),
.agu_o_valid (agu_o_valid ),
.agu_o_ready (agu_o_ready ),
.agu_o_wbck_wdat (agu_o_wbck_wdat ),
.agu_o_wbck_err (agu_o_wbck_err ),
.agu_o_cmt_misalgn (agu_o_cmt_misalgn ),
.agu_o_cmt_ld (agu_o_cmt_ld ),
.agu_o_cmt_stamo (agu_o_cmt_stamo ),
.agu_o_cmt_buserr (agu_o_cmt_buserr ),
.agu_o_cmt_badaddr (agu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
.clk (clk),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the regular ALU module
//
wire alu_o_valid;
wire alu_o_ready;
wire [`E203_XLEN-1:0] alu_o_wbck_wdat;
wire alu_o_wbck_err;
wire alu_o_cmt_ecall;
wire alu_o_cmt_ebreak;
wire alu_o_cmt_wfi;
wire alu_req_alu_add ;
wire alu_req_alu_sub ;
wire alu_req_alu_xor ;
wire alu_req_alu_sll ;
wire alu_req_alu_srl ;
wire alu_req_alu_sra ;
wire alu_req_alu_or ;
wire alu_req_alu_and ;
wire alu_req_alu_slt ;
wire alu_req_alu_sltu;
wire alu_req_alu_lui ;
wire [`E203_XLEN-1:0] alu_req_alu_op1;
wire [`E203_XLEN-1:0] alu_req_alu_op2;
wire [`E203_XLEN-1:0] alu_req_alu_res;
wire [`E203_XLEN-1:0] alu_i_rs1 = {`E203_XLEN {alu_op}} & i_rs1;
wire [`E203_XLEN-1:0] alu_i_rs2 = {`E203_XLEN {alu_op}} & i_rs2;
wire [`E203_XLEN-1:0] alu_i_imm = {`E203_XLEN {alu_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] alu_i_info = {`E203_DECINFO_WIDTH{alu_op}} & i_info;
wire [`E203_PC_SIZE-1:0] alu_i_pc = {`E203_PC_SIZE {alu_op}} & i_pc;
e203_exu_alu_rglr u_e203_exu_alu_rglr(
.alu_i_valid (alu_i_valid ),
.alu_i_ready (alu_i_ready ),
.alu_i_rs1 (alu_i_rs1 ),
.alu_i_rs2 (alu_i_rs2 ),
.alu_i_info (alu_i_info[`E203_DECINFO_ALU_WIDTH-1:0]),
.alu_i_imm (alu_i_imm ),
.alu_i_pc (alu_i_pc ),
.alu_o_valid (alu_o_valid ),
.alu_o_ready (alu_o_ready ),
.alu_o_wbck_wdat (alu_o_wbck_wdat ),
.alu_o_wbck_err (alu_o_wbck_err ),
.alu_o_cmt_ecall (alu_o_cmt_ecall ),
.alu_o_cmt_ebreak (alu_o_cmt_ebreak),
.alu_o_cmt_wfi (alu_o_cmt_wfi ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.clk (clk ),
.rst_n (rst_n )
);
`ifdef E203_SUPPORT_SHARE_MULDIV //{
//////////////////////////////////////////////////////
// Instantiate the MULDIV module
wire [`E203_XLEN-1:0] mdv_i_rs1 = {`E203_XLEN {mdv_op}} & i_rs1;
wire [`E203_XLEN-1:0] mdv_i_rs2 = {`E203_XLEN {mdv_op}} & i_rs2;
wire [`E203_XLEN-1:0] mdv_i_imm = {`E203_XLEN {mdv_op}} & i_imm;
wire [`E203_DECINFO_WIDTH-1:0] mdv_i_info = {`E203_DECINFO_WIDTH{mdv_op}} & i_info;
wire [`E203_ITAG_WIDTH-1:0] mdv_i_itag = {`E203_ITAG_WIDTH {mdv_op}} & i_itag;
wire mdv_o_valid;
wire mdv_o_ready;
wire [`E203_XLEN-1:0] mdv_o_wbck_wdat;
wire mdv_o_wbck_err;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op1;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_op2;
wire muldiv_req_alu_add ;
wire muldiv_req_alu_sub ;
wire [`E203_ALU_ADDER_WIDTH-1:0] muldiv_req_alu_res;
wire muldiv_sbf_0_ena;
wire [33-1:0] muldiv_sbf_0_nxt;
wire [33-1:0] muldiv_sbf_0_r;
wire muldiv_sbf_1_ena;
wire [33-1:0] muldiv_sbf_1_nxt;
wire [33-1:0] muldiv_sbf_1_r;
e203_exu_alu_muldiv u_e203_exu_alu_muldiv(
.mdv_nob2b (mdv_nob2b),
.muldiv_i_valid (mdv_i_valid ),
.muldiv_i_ready (mdv_i_ready ),
.muldiv_i_rs1 (mdv_i_rs1 ),
.muldiv_i_rs2 (mdv_i_rs2 ),
.muldiv_i_imm (mdv_i_imm ),
.muldiv_i_info (mdv_i_info[`E203_DECINFO_MULDIV_WIDTH-1:0]),
.muldiv_i_longpipe (mdv_i_longpipe ),
.muldiv_i_itag (mdv_i_itag ),
.flush_pulse (flush_pulse ),
.muldiv_o_valid (mdv_o_valid ),
.muldiv_o_ready (mdv_o_ready ),
.muldiv_o_wbck_wdat (mdv_o_wbck_wdat),
.muldiv_o_wbck_err (mdv_o_wbck_err ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
.clk (clk ),
.rst_n (rst_n )
);
`endif//E203_SUPPORT_SHARE_MULDIV}
//////////////////////////////////////////////////////////////
// Instantiate the Shared Datapath module
//
wire alu_req_alu = alu_op & i_rdwen;// Regular ALU only req datapath when it need to write-back
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire muldiv_req_alu = mdv_op;// Since MULDIV have no point to let rd=0, so always need ALU datapath
`endif//E203_SUPPORT_SHARE_MULDIV}
wire bjp_req_alu = bjp_op;// Since BJP may not write-back, but still need ALU datapath
wire agu_req_alu = agu_op;// Since AGU may have some other features, so always need ALU datapath
e203_exu_alu_dpath u_e203_exu_alu_dpath(
.alu_req_alu (alu_req_alu ),
.alu_req_alu_add (alu_req_alu_add ),
.alu_req_alu_sub (alu_req_alu_sub ),
.alu_req_alu_xor (alu_req_alu_xor ),
.alu_req_alu_sll (alu_req_alu_sll ),
.alu_req_alu_srl (alu_req_alu_srl ),
.alu_req_alu_sra (alu_req_alu_sra ),
.alu_req_alu_or (alu_req_alu_or ),
.alu_req_alu_and (alu_req_alu_and ),
.alu_req_alu_slt (alu_req_alu_slt ),
.alu_req_alu_sltu (alu_req_alu_sltu ),
.alu_req_alu_lui (alu_req_alu_lui ),
.alu_req_alu_op1 (alu_req_alu_op1 ),
.alu_req_alu_op2 (alu_req_alu_op2 ),
.alu_req_alu_res (alu_req_alu_res ),
.bjp_req_alu (bjp_req_alu ),
.bjp_req_alu_op1 (bjp_req_alu_op1 ),
.bjp_req_alu_op2 (bjp_req_alu_op2 ),
.bjp_req_alu_cmp_eq (bjp_req_alu_cmp_eq ),
.bjp_req_alu_cmp_ne (bjp_req_alu_cmp_ne ),
.bjp_req_alu_cmp_lt (bjp_req_alu_cmp_lt ),
.bjp_req_alu_cmp_gt (bjp_req_alu_cmp_gt ),
.bjp_req_alu_cmp_ltu (bjp_req_alu_cmp_ltu ),
.bjp_req_alu_cmp_gtu (bjp_req_alu_cmp_gtu ),
.bjp_req_alu_add (bjp_req_alu_add ),
.bjp_req_alu_cmp_res (bjp_req_alu_cmp_res ),
.bjp_req_alu_add_res (bjp_req_alu_add_res ),
.agu_req_alu (agu_req_alu ),
.agu_req_alu_op1 (agu_req_alu_op1 ),
.agu_req_alu_op2 (agu_req_alu_op2 ),
.agu_req_alu_swap (agu_req_alu_swap ),
.agu_req_alu_add (agu_req_alu_add ),
.agu_req_alu_and (agu_req_alu_and ),
.agu_req_alu_or (agu_req_alu_or ),
.agu_req_alu_xor (agu_req_alu_xor ),
.agu_req_alu_max (agu_req_alu_max ),
.agu_req_alu_min (agu_req_alu_min ),
.agu_req_alu_maxu (agu_req_alu_maxu ),
.agu_req_alu_minu (agu_req_alu_minu ),
.agu_req_alu_res (agu_req_alu_res ),
.agu_sbf_0_ena (agu_sbf_0_ena ),
.agu_sbf_0_nxt (agu_sbf_0_nxt ),
.agu_sbf_0_r (agu_sbf_0_r ),
.agu_sbf_1_ena (agu_sbf_1_ena ),
.agu_sbf_1_nxt (agu_sbf_1_nxt ),
.agu_sbf_1_r (agu_sbf_1_r ),
`ifdef E203_SUPPORT_SHARE_MULDIV //{
.muldiv_req_alu (muldiv_req_alu ),
.muldiv_req_alu_op1 (muldiv_req_alu_op1),
.muldiv_req_alu_op2 (muldiv_req_alu_op2),
.muldiv_req_alu_add (muldiv_req_alu_add),
.muldiv_req_alu_sub (muldiv_req_alu_sub),
.muldiv_req_alu_res (muldiv_req_alu_res),
.muldiv_sbf_0_ena (muldiv_sbf_0_ena ),
.muldiv_sbf_0_nxt (muldiv_sbf_0_nxt ),
.muldiv_sbf_0_r (muldiv_sbf_0_r ),
.muldiv_sbf_1_ena (muldiv_sbf_1_ena ),
.muldiv_sbf_1_nxt (muldiv_sbf_1_nxt ),
.muldiv_sbf_1_r (muldiv_sbf_1_r ),
`endif//E203_SUPPORT_SHARE_MULDIV}
.clk (clk ),
.rst_n (rst_n )
);
wire ifu_excp_o_valid;
wire ifu_excp_o_ready;
wire [`E203_XLEN-1:0] ifu_excp_o_wbck_wdat;
wire ifu_excp_o_wbck_err;
assign ifu_excp_i_ready = ifu_excp_o_ready;
assign ifu_excp_o_valid = ifu_excp_i_valid;
assign ifu_excp_o_wbck_wdat = `E203_XLEN'b0;
assign ifu_excp_o_wbck_err = 1'b1;// IFU illegal instruction always treat as error
//////////////////////////////////////////////////////////////
// Aribtrate the Result and generate output interfaces
//
wire o_valid;
wire o_ready;
wire o_sel_ifu_excp = ifu_excp_op;
wire o_sel_alu = alu_op;
wire o_sel_bjp = bjp_op;
wire o_sel_csr = csr_op;
wire o_sel_agu = agu_op;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
wire o_sel_mdv = mdv_op;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign o_valid = (o_sel_alu & alu_o_valid )
| (o_sel_bjp & bjp_o_valid )
| (o_sel_csr & csr_o_valid )
| (o_sel_agu & agu_o_valid )
| (o_sel_ifu_excp & ifu_excp_o_valid)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| (o_sel_mdv & mdv_o_valid )
`endif//E203_SUPPORT_SHARE_MULDIV}
;
assign ifu_excp_o_ready = o_sel_ifu_excp & o_ready;
assign alu_o_ready = o_sel_alu & o_ready;
assign agu_o_ready = o_sel_agu & o_ready;
`ifdef E203_SUPPORT_SHARE_MULDIV //{
assign mdv_o_ready = o_sel_mdv & o_ready;
`endif//E203_SUPPORT_SHARE_MULDIV}
assign bjp_o_ready = o_sel_bjp & o_ready;
assign csr_o_ready = o_sel_csr & o_ready;
assign wbck_o_wdat =
({`E203_XLEN{o_sel_alu}} & alu_o_wbck_wdat)
| ({`E203_XLEN{o_sel_bjp}} & bjp_o_wbck_wdat)
| ({`E203_XLEN{o_sel_csr}} & csr_o_wbck_wdat)
| ({`E203_XLEN{o_sel_agu}} & agu_o_wbck_wdat)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({`E203_XLEN{o_sel_mdv}} & mdv_o_wbck_wdat)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({`E203_XLEN{o_sel_ifu_excp}} & ifu_excp_o_wbck_wdat)
;
assign wbck_o_rdidx = i_rdidx;
wire wbck_o_rdwen = i_rdwen;
wire wbck_o_err =
({1{o_sel_alu}} & alu_o_wbck_err)
| ({1{o_sel_bjp}} & bjp_o_wbck_err)
| ({1{o_sel_csr}} & csr_o_wbck_err)
| ({1{o_sel_agu}} & agu_o_wbck_err)
`ifdef E203_SUPPORT_SHARE_MULDIV //{
| ({1{o_sel_mdv}} & mdv_o_wbck_err)
`endif//E203_SUPPORT_SHARE_MULDIV}
| ({1{o_sel_ifu_excp}} & ifu_excp_o_wbck_err)
;
// Each Instruction need to commit or write-back
// * The write-back only needed when the unit need to write-back
// the result (need to write RD), and it is not a long-pipe uop
// (need to be write back by its long-pipe write-back, not here)
// * Each instruction need to be commited
wire o_need_wbck = wbck_o_rdwen & (~i_longpipe) & (~wbck_o_err);
wire o_need_cmt = 1'b1;
assign o_ready =
(o_need_cmt ? cmt_o_ready : 1'b1)
& (o_need_wbck ? wbck_o_ready : 1'b1);
assign wbck_o_valid = o_need_wbck & o_valid & (o_need_cmt ? cmt_o_ready : 1'b1);
assign cmt_o_valid = o_need_cmt & o_valid & (o_need_wbck ? wbck_o_ready : 1'b1);
//
// The commint interface have some special signals
assign cmt_o_instr = i_instr;
assign cmt_o_pc = i_pc;
assign cmt_o_imm = i_imm;
assign cmt_o_rv32 = i_info[`E203_DECINFO_RV32];
// The cmt_o_pc_vld is used by the commit stage to check
// if current instruction is outputing a valid current PC
// to guarante the commit to flush pipeline safely, this
// vld only be asserted when:
// * There is a valid instruction here
// --- otherwise, the commit stage may use wrong PC
// value to stored in DPC or EPC
assign cmt_o_pc_vld =
// Otherwise, just use the i_pc_vld
i_pc_vld;
assign cmt_o_misalgn = (o_sel_agu & agu_o_cmt_misalgn)
;
assign cmt_o_ld = (o_sel_agu & agu_o_cmt_ld)
;
assign cmt_o_badaddr = ({`E203_ADDR_SIZE{o_sel_agu}} & agu_o_cmt_badaddr)
;
assign cmt_o_buserr = o_sel_agu & agu_o_cmt_buserr;
assign cmt_o_stamo = o_sel_agu & agu_o_cmt_stamo ;
assign cmt_o_bjp = o_sel_bjp & bjp_o_cmt_bjp;
assign cmt_o_mret = o_sel_bjp & bjp_o_cmt_mret;
assign cmt_o_dret = o_sel_bjp & bjp_o_cmt_dret;
assign cmt_o_bjp_prdt = o_sel_bjp & bjp_o_cmt_prdt;
assign cmt_o_bjp_rslv = o_sel_bjp & bjp_o_cmt_rslv;
assign cmt_o_fencei = o_sel_bjp & bjp_o_cmt_fencei;
assign cmt_o_ecall = o_sel_alu & alu_o_cmt_ecall;
assign cmt_o_ebreak = o_sel_alu & alu_o_cmt_ebreak;
assign cmt_o_wfi = o_sel_alu & alu_o_cmt_wfi;
assign cmt_o_ifu_misalgn = i_misalgn;
assign cmt_o_ifu_buserr = i_buserr;
assign cmt_o_ifu_ilegl = i_ilegl
| (o_sel_csr & csr_access_ilgl)
;
endmodule |
module e203_exu_alu_rglr(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input alu_i_valid, // Handshake valid
output alu_i_ready, // Handshake ready
input [`E203_XLEN-1:0] alu_i_rs1,
input [`E203_XLEN-1:0] alu_i_rs2,
input [`E203_XLEN-1:0] alu_i_imm,
input [`E203_PC_SIZE-1:0] alu_i_pc,
input [`E203_DECINFO_ALU_WIDTH-1:0] alu_i_info,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ALU Write-back/Commit Interface
output alu_o_valid, // Handshake valid
input alu_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] alu_o_wbck_wdat,
output alu_o_wbck_err,
output alu_o_cmt_ecall,
output alu_o_cmt_ebreak,
output alu_o_cmt_wfi,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath
//
// The operands and info to ALU
output alu_req_alu_add ,
output alu_req_alu_sub ,
output alu_req_alu_xor ,
output alu_req_alu_sll ,
output alu_req_alu_srl ,
output alu_req_alu_sra ,
output alu_req_alu_or ,
output alu_req_alu_and ,
output alu_req_alu_slt ,
output alu_req_alu_sltu,
output alu_req_alu_lui ,
output [`E203_XLEN-1:0] alu_req_alu_op1,
output [`E203_XLEN-1:0] alu_req_alu_op2,
input [`E203_XLEN-1:0] alu_req_alu_res,
input clk,
input rst_n
);
wire op2imm = alu_i_info [`E203_DECINFO_ALU_OP2IMM ];
wire op1pc = alu_i_info [`E203_DECINFO_ALU_OP1PC ];
assign alu_req_alu_op1 = op1pc ? alu_i_pc : alu_i_rs1;
assign alu_req_alu_op2 = op2imm ? alu_i_imm : alu_i_rs2;
wire nop = alu_i_info [`E203_DECINFO_ALU_NOP ] ;
wire ecall = alu_i_info [`E203_DECINFO_ALU_ECAL ];
wire ebreak = alu_i_info [`E203_DECINFO_ALU_EBRK ];
wire wfi = alu_i_info [`E203_DECINFO_ALU_WFI ];
// The NOP is encoded as ADDI, so need to uncheck it
assign alu_req_alu_add = alu_i_info [`E203_DECINFO_ALU_ADD ] & (~nop);
assign alu_req_alu_sub = alu_i_info [`E203_DECINFO_ALU_SUB ];
assign alu_req_alu_xor = alu_i_info [`E203_DECINFO_ALU_XOR ];
assign alu_req_alu_sll = alu_i_info [`E203_DECINFO_ALU_SLL ];
assign alu_req_alu_srl = alu_i_info [`E203_DECINFO_ALU_SRL ];
assign alu_req_alu_sra = alu_i_info [`E203_DECINFO_ALU_SRA ];
assign alu_req_alu_or = alu_i_info [`E203_DECINFO_ALU_OR ];
assign alu_req_alu_and = alu_i_info [`E203_DECINFO_ALU_AND ];
assign alu_req_alu_slt = alu_i_info [`E203_DECINFO_ALU_SLT ];
assign alu_req_alu_sltu = alu_i_info [`E203_DECINFO_ALU_SLTU];
assign alu_req_alu_lui = alu_i_info [`E203_DECINFO_ALU_LUI ];
assign alu_o_valid = alu_i_valid;
assign alu_i_ready = alu_o_ready;
assign alu_o_wbck_wdat = alu_req_alu_res;
assign alu_o_cmt_ecall = ecall;
assign alu_o_cmt_ebreak = ebreak;
assign alu_o_cmt_wfi = wfi;
// The exception or error result cannot write-back
assign alu_o_wbck_err = alu_o_cmt_ecall | alu_o_cmt_ebreak | alu_o_cmt_wfi;
endmodule |
module e203_exu_branchslv(
// The BJP condition final result need to be resolved at ALU
input cmt_i_valid,
output cmt_i_ready,
input cmt_i_rv32,
input cmt_i_dret,// The dret instruction
input cmt_i_mret,// The ret instruction
input cmt_i_fencei,// The fencei instruction
input cmt_i_bjp,
input cmt_i_bjp_prdt,// The predicted ture/false
input cmt_i_bjp_rslv,// The resolved ture/false
input [`E203_PC_SIZE-1:0] cmt_i_pc,
input [`E203_XLEN-1:0] cmt_i_imm,// The resolved ture/false
input [`E203_PC_SIZE-1:0] csr_epc_r,
input [`E203_PC_SIZE-1:0] csr_dpc_r,
input nonalu_excpirq_flush_req_raw,
input brchmis_flush_ack,
output brchmis_flush_req,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op1,
output [`E203_PC_SIZE-1:0] brchmis_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] brchmis_flush_pc,
`endif//}
output cmt_mret_ena,
output cmt_dret_ena,
output cmt_fencei_ena,
input clk,
input rst_n
);
wire brchmis_flush_ack_pre;
wire brchmis_flush_req_pre;
assign brchmis_flush_req = brchmis_flush_req_pre & (~nonalu_excpirq_flush_req_raw);
assign brchmis_flush_ack_pre = brchmis_flush_ack & (~nonalu_excpirq_flush_req_raw);
// In Two stage impelmentation, several branch instructions are handled as below:
// * It is predicted at IFU, and target is handled in IFU. But
// we need to check if it is predicted correctly or not. If not,
// we need to flush the pipeline
// Note: the JUMP instrution will always jump, hence they will be
// both predicted and resolved as true
wire brchmis_need_flush = (
(cmt_i_bjp & (cmt_i_bjp_prdt ^ cmt_i_bjp_rslv))
// If it is a FenceI instruction, it is always Flush
| cmt_i_fencei
// If it is a RET instruction, it is always jump
| cmt_i_mret
// If it is a DRET instruction, it is always jump
| cmt_i_dret
);
wire cmt_i_is_branch = (
cmt_i_bjp
| cmt_i_fencei
| cmt_i_mret
| cmt_i_dret
);
assign brchmis_flush_req_pre = cmt_i_valid & brchmis_need_flush;
// * If it is a DRET instruction, the new target PC is DPC register
// * If it is a RET instruction, the new target PC is EPC register
// * If predicted as taken, but actually it is not taken, then
// The new target PC should caculated by PC+2/4
// * If predicted as not taken, but actually it is taken, then
// The new target PC should caculated by PC+offset
assign brchmis_flush_add_op1 = cmt_i_dret ? csr_dpc_r : cmt_i_mret ? csr_epc_r : cmt_i_pc;
assign brchmis_flush_add_op2 = cmt_i_dret ? `E203_PC_SIZE'b0 : cmt_i_mret ? `E203_PC_SIZE'b0 :
(cmt_i_fencei | cmt_i_bjp_prdt) ? (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)
: cmt_i_imm[`E203_PC_SIZE-1:0];
`ifdef E203_TIMING_BOOST//}
// Replicated two adders here to trade area with timing
assign brchmis_flush_pc =
// The fenceI is also need to trigger the flush to its next instructions
(cmt_i_fencei | (cmt_i_bjp & cmt_i_bjp_prdt)) ? (cmt_i_pc + (cmt_i_rv32 ? `E203_PC_SIZE'd4 : `E203_PC_SIZE'd2)) :
(cmt_i_bjp & (~cmt_i_bjp_prdt)) ? (cmt_i_pc + cmt_i_imm[`E203_PC_SIZE-1:0]) :
cmt_i_dret ? csr_dpc_r :
//cmt_i_mret ? csr_epc_r :
csr_epc_r ;// Last condition cmt_i_mret commented
// to save gatecount and timing
`endif//}
wire brchmis_flush_hsked = brchmis_flush_req & brchmis_flush_ack;
assign cmt_mret_ena = cmt_i_mret & brchmis_flush_hsked;
assign cmt_dret_ena = cmt_i_dret & brchmis_flush_hsked;
assign cmt_fencei_ena = cmt_i_fencei & brchmis_flush_hsked;
assign cmt_i_ready = (~cmt_i_is_branch) |
(
(brchmis_need_flush ? brchmis_flush_ack_pre : 1'b1)
// The Non-ALU flush will override the ALU flush
& (~nonalu_excpirq_flush_req_raw)
);
endmodule |
module sirv_expl_axi_slv #(
parameter AW = 32,
parameter DW = 32
)(
input axi_arvalid,
output axi_arready,
input [AW-1:0] axi_araddr,
input [3:0] axi_arcache,
input [2:0] axi_arprot,
input [1:0] axi_arlock,
input [1:0] axi_arburst,
input [3:0] axi_arlen,
input [2:0] axi_arsize,
input axi_awvalid,
output axi_awready,
input [AW-1:0] axi_awaddr,
input [3:0] axi_awcache,
input [2:0] axi_awprot,
input [1:0] axi_awlock,
input [1:0] axi_awburst,
input [3:0] axi_awlen,
input [2:0] axi_awsize,
output axi_rvalid,
input axi_rready,
output [DW-1:0] axi_rdata,
output [1:0] axi_rresp,
output axi_rlast,
input axi_wvalid,
output axi_wready,
input [DW-1:0] axi_wdata,
input [(DW/8)-1:0] axi_wstrb,
input axi_wlast,
output axi_bvalid,
input axi_bready,
output [1:0] axi_bresp,
input clk,
input rst_n
);
assign axi_rvalid = axi_arvalid;
assign axi_arready = axi_rready;
assign axi_rdata = {DW{1'b0}};
assign axi_rresp = 2'b0;
assign axi_rlast = 1'b1;
assign axi_bvalid = axi_wvalid;
assign axi_wready = axi_bready;
assign axi_bresp = 2'b0;
assign axi_awready = 1'b1;
endmodule |
module sirv_repeater_6(
input clock,
input reset,
input io_repeat,
output io_full,
output io_enq_ready,
input io_enq_valid,
input [2:0] io_enq_bits_opcode,
input [2:0] io_enq_bits_param,
input [2:0] io_enq_bits_size,
input [1:0] io_enq_bits_source,
input [29:0] io_enq_bits_address,
input io_enq_bits_mask,
input [7:0] io_enq_bits_data,
input io_deq_ready,
output io_deq_valid,
output [2:0] io_deq_bits_opcode,
output [2:0] io_deq_bits_param,
output [2:0] io_deq_bits_size,
output [1:0] io_deq_bits_source,
output [29:0] io_deq_bits_address,
output io_deq_bits_mask,
output [7:0] io_deq_bits_data
);
reg full;
reg [31:0] GEN_9;
reg [2:0] saved_opcode;
reg [31:0] GEN_10;
reg [2:0] saved_param;
reg [31:0] GEN_11;
reg [2:0] saved_size;
reg [31:0] GEN_12;
reg [1:0] saved_source;
reg [31:0] GEN_13;
reg [29:0] saved_address;
reg [31:0] GEN_14;
reg saved_mask;
reg [31:0] GEN_15;
reg [7:0] saved_data;
reg [31:0] GEN_16;
wire T_77;
wire T_79;
wire T_80;
wire [2:0] T_81_opcode;
wire [2:0] T_81_param;
wire [2:0] T_81_size;
wire [1:0] T_81_source;
wire [29:0] T_81_address;
wire T_81_mask;
wire [7:0] T_81_data;
wire T_89;
wire T_90;
wire GEN_0;
wire [2:0] GEN_1;
wire [2:0] GEN_2;
wire [2:0] GEN_3;
wire [1:0] GEN_4;
wire [29:0] GEN_5;
wire GEN_6;
wire [7:0] GEN_7;
wire T_92;
wire T_94;
wire T_95;
wire GEN_8;
assign io_full = full;
assign io_enq_ready = T_80;
assign io_deq_valid = T_77;
assign io_deq_bits_opcode = T_81_opcode;
assign io_deq_bits_param = T_81_param;
assign io_deq_bits_size = T_81_size;
assign io_deq_bits_source = T_81_source;
assign io_deq_bits_address = T_81_address;
assign io_deq_bits_mask = T_81_mask;
assign io_deq_bits_data = T_81_data;
assign T_77 = io_enq_valid | full;
assign T_79 = full == 1'h0;
assign T_80 = io_deq_ready & T_79;
assign T_81_opcode = full ? saved_opcode : io_enq_bits_opcode;
assign T_81_param = full ? saved_param : io_enq_bits_param;
assign T_81_size = full ? saved_size : io_enq_bits_size;
assign T_81_source = full ? saved_source : io_enq_bits_source;
assign T_81_address = full ? saved_address : io_enq_bits_address;
assign T_81_mask = full ? saved_mask : io_enq_bits_mask;
assign T_81_data = full ? saved_data : io_enq_bits_data;
assign T_89 = io_enq_ready & io_enq_valid;
assign T_90 = T_89 & io_repeat;
assign GEN_0 = T_90 ? 1'h1 : full;
assign GEN_1 = T_90 ? io_enq_bits_opcode : saved_opcode;
assign GEN_2 = T_90 ? io_enq_bits_param : saved_param;
assign GEN_3 = T_90 ? io_enq_bits_size : saved_size;
assign GEN_4 = T_90 ? io_enq_bits_source : saved_source;
assign GEN_5 = T_90 ? io_enq_bits_address : saved_address;
assign GEN_6 = T_90 ? io_enq_bits_mask : saved_mask;
assign GEN_7 = T_90 ? io_enq_bits_data : saved_data;
assign T_92 = io_deq_ready & io_deq_valid;
assign T_94 = io_repeat == 1'h0;
assign T_95 = T_92 & T_94;
assign GEN_8 = T_95 ? 1'h0 : GEN_0;
always @(posedge clock or posedge reset)
if (reset) begin
full <= 1'h0;
end else begin
if (T_95) begin
full <= 1'h0;
end else begin
if (T_90) begin
full <= 1'h1;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
saved_opcode <= 3'b0;
saved_param <= 3'b0;
saved_size <= 3'b0;
saved_source <= 2'b0;
saved_address <= 30'b0;
saved_mask <= 1'b0;
saved_data <= 8'b0;
end
else begin
if (T_90) begin
saved_opcode <= io_enq_bits_opcode;
end
if (T_90) begin
saved_param <= io_enq_bits_param;
end
if (T_90) begin
saved_size <= io_enq_bits_size;
end
if (T_90) begin
saved_source <= io_enq_bits_source;
end
if (T_90) begin
saved_address <= io_enq_bits_address;
end
if (T_90) begin
saved_mask <= io_enq_bits_mask;
end
if (T_90) begin
saved_data <= io_enq_bits_data;
end
end
endmodule |
module e203_subsys_mems(
input mem_icb_cmd_valid,
output mem_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
input mem_icb_cmd_read,
input [`E203_XLEN-1:0] mem_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
output mem_icb_rsp_valid,
input mem_icb_rsp_ready,
output mem_icb_rsp_err,
output [`E203_XLEN-1:0] mem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output sysmem_icb_cmd_valid,
input sysmem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] sysmem_icb_cmd_addr,
output sysmem_icb_cmd_read,
output [`E203_XLEN-1:0] sysmem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] sysmem_icb_cmd_wmask,
//
input sysmem_icb_rsp_valid,
output sysmem_icb_rsp_ready,
input sysmem_icb_rsp_err,
input [`E203_XLEN-1:0] sysmem_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output qspi0_ro_icb_cmd_valid,
input qspi0_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] qspi0_ro_icb_cmd_addr,
output qspi0_ro_icb_cmd_read,
output [`E203_XLEN-1:0] qspi0_ro_icb_cmd_wdata,
//
input qspi0_ro_icb_rsp_valid,
output qspi0_ro_icb_rsp_ready,
input qspi0_ro_icb_rsp_err,
input [`E203_XLEN-1:0] qspi0_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output otp_ro_icb_cmd_valid,
input otp_ro_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] otp_ro_icb_cmd_addr,
output otp_ro_icb_cmd_read,
output [`E203_XLEN-1:0] otp_ro_icb_cmd_wdata,
//
input otp_ro_icb_rsp_valid,
output otp_ro_icb_rsp_ready,
input otp_ro_icb_rsp_err,
input [`E203_XLEN-1:0] otp_ro_icb_rsp_rdata,
//////////////////////////////////////////////////////////
output dm_icb_cmd_valid,
input dm_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] dm_icb_cmd_addr,
output dm_icb_cmd_read,
output [`E203_XLEN-1:0] dm_icb_cmd_wdata,
//
input dm_icb_rsp_valid,
output dm_icb_rsp_ready,
input [`E203_XLEN-1:0] dm_icb_rsp_rdata,
input clk,
input bus_rst_n,
input rst_n
);
wire mrom_icb_cmd_valid;
wire mrom_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] mrom_icb_cmd_addr;
wire mrom_icb_cmd_read;
wire mrom_icb_rsp_valid;
wire mrom_icb_rsp_ready;
wire mrom_icb_rsp_err ;
wire [`E203_XLEN-1:0] mrom_icb_rsp_rdata;
wire expl_axi_icb_cmd_valid;
wire expl_axi_icb_cmd_ready;
wire [32-1:0] expl_axi_icb_cmd_addr;
wire expl_axi_icb_cmd_read;
wire [32-1:0] expl_axi_icb_cmd_wdata;
wire [4 -1:0] expl_axi_icb_cmd_wmask;
wire expl_axi_icb_rsp_valid;
wire expl_axi_icb_rsp_ready;
wire [32-1:0] expl_axi_icb_rsp_rdata;
wire expl_axi_icb_rsp_err;
localparam MROM_AW = 12 ;
localparam MROM_DP = 1024;
// There are several slaves for Mem bus, including:
// * DM : 0x0000 0000 -- 0x0000 0FFF
// * MROM : 0x0000 1000 -- 0x0000 1FFF
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
sirv_icb1to8_bus # (
.ICB_FIFO_DP (2),// We add a ping-pong buffer here to cut down the timing path
.ICB_FIFO_CUT_READY (1),// We configure it to cut down the back-pressure ready signal
.AW (32),
.DW (`E203_XLEN),
.SPLT_FIFO_OUTS_NUM (1),// The Mem only allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// The Mem always cut ready
// * DM : 0x0000 0000 -- 0x0000 0FFF
.O0_BASE_ADDR (32'h0000_0000),
.O0_BASE_REGION_LSB (12),
// * MROM : 0x0000 1000 -- 0x0000 1FFF
.O1_BASE_ADDR (32'h0000_1000),
.O1_BASE_REGION_LSB (12),
// * OTP-RO : 0x0002 0000 -- 0x0003 FFFF
.O2_BASE_ADDR (32'h0002_0000),
.O2_BASE_REGION_LSB (17),
// * QSPI0-RO : 0x2000 0000 -- 0x3FFF FFFF
.O3_BASE_ADDR (32'h2000_0000),
.O3_BASE_REGION_LSB (29),
// * SysMem : 0x8000 0000 -- 0xFFFF FFFF
// Actually since the 0xFxxx xxxx have been occupied by FIO,
// sysmem have no chance to access it
.O4_BASE_ADDR (32'h8000_0000),
.O4_BASE_REGION_LSB (31),
// * Here is an example AXI Peripheral
.O5_BASE_ADDR (32'h4000_0000),
.O5_BASE_REGION_LSB (28),
// Not used
.O6_BASE_ADDR (32'h0000_0000),
.O6_BASE_REGION_LSB (0),
// Not used
.O7_BASE_ADDR (32'h0000_0000),
.O7_BASE_REGION_LSB (0)
)u_sirv_mem_fab(
.i_icb_cmd_valid (mem_icb_cmd_valid),
.i_icb_cmd_ready (mem_icb_cmd_ready),
.i_icb_cmd_addr (mem_icb_cmd_addr ),
.i_icb_cmd_read (mem_icb_cmd_read ),
.i_icb_cmd_wdata (mem_icb_cmd_wdata),
.i_icb_cmd_wmask (mem_icb_cmd_wmask),
.i_icb_cmd_lock (1'b0 ),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (mem_icb_rsp_valid),
.i_icb_rsp_ready (mem_icb_rsp_ready),
.i_icb_rsp_err (mem_icb_rsp_err ),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (mem_icb_rsp_rdata),
// * DM
.o0_icb_enable (1'b1),
.o0_icb_cmd_valid (dm_icb_cmd_valid),
.o0_icb_cmd_ready (dm_icb_cmd_ready),
.o0_icb_cmd_addr (dm_icb_cmd_addr ),
.o0_icb_cmd_read (dm_icb_cmd_read ),
.o0_icb_cmd_wdata (dm_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (dm_icb_rsp_valid),
.o0_icb_rsp_ready (dm_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0),
.o0_icb_rsp_rdata (dm_icb_rsp_rdata),
// * MROM
.o1_icb_enable (1'b1),
.o1_icb_cmd_valid (mrom_icb_cmd_valid),
.o1_icb_cmd_ready (mrom_icb_cmd_ready),
.o1_icb_cmd_addr (mrom_icb_cmd_addr ),
.o1_icb_cmd_read (mrom_icb_cmd_read ),
.o1_icb_cmd_wdata (),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (mrom_icb_rsp_valid),
.o1_icb_rsp_ready (mrom_icb_rsp_ready),
.o1_icb_rsp_err (mrom_icb_rsp_err),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (mrom_icb_rsp_rdata),
// * OTP-RO
.o2_icb_enable (1'b1),
.o2_icb_cmd_valid (otp_ro_icb_cmd_valid),
.o2_icb_cmd_ready (otp_ro_icb_cmd_ready),
.o2_icb_cmd_addr (otp_ro_icb_cmd_addr ),
.o2_icb_cmd_read (otp_ro_icb_cmd_read ),
.o2_icb_cmd_wdata (otp_ro_icb_cmd_wdata),
.o2_icb_cmd_wmask (),
.o2_icb_cmd_lock (),
.o2_icb_cmd_excl (),
.o2_icb_cmd_size (),
.o2_icb_cmd_burst (),
.o2_icb_cmd_beat (),
.o2_icb_rsp_valid (otp_ro_icb_rsp_valid),
.o2_icb_rsp_ready (otp_ro_icb_rsp_ready),
.o2_icb_rsp_err (otp_ro_icb_rsp_err),
.o2_icb_rsp_excl_ok(1'b0 ),
.o2_icb_rsp_rdata (otp_ro_icb_rsp_rdata),
// * QSPI0-RO
.o3_icb_enable (1'b1),
.o3_icb_cmd_valid (qspi0_ro_icb_cmd_valid),
.o3_icb_cmd_ready (qspi0_ro_icb_cmd_ready),
.o3_icb_cmd_addr (qspi0_ro_icb_cmd_addr ),
.o3_icb_cmd_read (qspi0_ro_icb_cmd_read ),
.o3_icb_cmd_wdata (qspi0_ro_icb_cmd_wdata),
.o3_icb_cmd_wmask (),
.o3_icb_cmd_lock (),
.o3_icb_cmd_excl (),
.o3_icb_cmd_size (),
.o3_icb_cmd_burst (),
.o3_icb_cmd_beat (),
.o3_icb_rsp_valid (qspi0_ro_icb_rsp_valid),
.o3_icb_rsp_ready (qspi0_ro_icb_rsp_ready),
.o3_icb_rsp_err (qspi0_ro_icb_rsp_err),
.o3_icb_rsp_excl_ok(1'b0 ),
.o3_icb_rsp_rdata (qspi0_ro_icb_rsp_rdata),
// * SysMem
.o4_icb_enable (1'b1),
.o4_icb_cmd_valid (sysmem_icb_cmd_valid),
.o4_icb_cmd_ready (sysmem_icb_cmd_ready),
.o4_icb_cmd_addr (sysmem_icb_cmd_addr ),
.o4_icb_cmd_read (sysmem_icb_cmd_read ),
.o4_icb_cmd_wdata (sysmem_icb_cmd_wdata),
.o4_icb_cmd_wmask (sysmem_icb_cmd_wmask),
.o4_icb_cmd_lock (),
.o4_icb_cmd_excl (),
.o4_icb_cmd_size (),
.o4_icb_cmd_burst (),
.o4_icb_cmd_beat (),
.o4_icb_rsp_valid (sysmem_icb_rsp_valid),
.o4_icb_rsp_ready (sysmem_icb_rsp_ready),
.o4_icb_rsp_err (sysmem_icb_rsp_err ),
.o4_icb_rsp_excl_ok(1'b0),
.o4_icb_rsp_rdata (sysmem_icb_rsp_rdata),
// * Example AXI
.o5_icb_enable (1'b1),
.o5_icb_cmd_valid (expl_axi_icb_cmd_valid),
.o5_icb_cmd_ready (expl_axi_icb_cmd_ready),
.o5_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.o5_icb_cmd_read (expl_axi_icb_cmd_read ),
.o5_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.o5_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.o5_icb_cmd_lock (),
.o5_icb_cmd_excl (),
.o5_icb_cmd_size (),
.o5_icb_cmd_burst (),
.o5_icb_cmd_beat (),
.o5_icb_rsp_valid (expl_axi_icb_rsp_valid),
.o5_icb_rsp_ready (expl_axi_icb_rsp_ready),
.o5_icb_rsp_err (expl_axi_icb_rsp_err),
.o5_icb_rsp_excl_ok(1'b0 ),
.o5_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
// * Not used
.o6_icb_enable (1'b0),
.o6_icb_cmd_valid (),
.o6_icb_cmd_ready (1'b0),
.o6_icb_cmd_addr (),
.o6_icb_cmd_read (),
.o6_icb_cmd_wdata (),
.o6_icb_cmd_wmask (),
.o6_icb_cmd_lock (),
.o6_icb_cmd_excl (),
.o6_icb_cmd_size (),
.o6_icb_cmd_burst (),
.o6_icb_cmd_beat (),
.o6_icb_rsp_valid (1'b0),
.o6_icb_rsp_ready (),
.o6_icb_rsp_err (1'b0 ),
.o6_icb_rsp_excl_ok(1'b0 ),
.o6_icb_rsp_rdata (`E203_XLEN'b0),
// * Not used
.o7_icb_enable (1'b0),
.o7_icb_cmd_valid (),
.o7_icb_cmd_ready (1'b0),
.o7_icb_cmd_addr (),
.o7_icb_cmd_read (),
.o7_icb_cmd_wdata (),
.o7_icb_cmd_wmask (),
.o7_icb_cmd_lock (),
.o7_icb_cmd_excl (),
.o7_icb_cmd_size (),
.o7_icb_cmd_burst (),
.o7_icb_cmd_beat (),
.o7_icb_rsp_valid (1'b0),
.o7_icb_rsp_ready (),
.o7_icb_rsp_err (1'b0 ),
.o7_icb_rsp_excl_ok(1'b0 ),
.o7_icb_rsp_rdata (`E203_XLEN'b0),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_mrom_top #(
.AW(MROM_AW),
.DW(32),
.DP(MROM_DP)
)u_sirv_mrom_top(
.rom_icb_cmd_valid (mrom_icb_cmd_valid),
.rom_icb_cmd_ready (mrom_icb_cmd_ready),
.rom_icb_cmd_addr (mrom_icb_cmd_addr [MROM_AW-1:0]),
.rom_icb_cmd_read (mrom_icb_cmd_read ),
.rom_icb_rsp_valid (mrom_icb_rsp_valid),
.rom_icb_rsp_ready (mrom_icb_rsp_ready),
.rom_icb_rsp_err (mrom_icb_rsp_err ),
.rom_icb_rsp_rdata (mrom_icb_rsp_rdata),
.clk (clk ),
.rst_n (rst_n)
);
// * Here is an example AXI Peripheral
wire expl_axi_arvalid;
wire expl_axi_arready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_araddr;
wire [3:0] expl_axi_arcache;
wire [2:0] expl_axi_arprot;
wire [1:0] expl_axi_arlock;
wire [1:0] expl_axi_arburst;
wire [3:0] expl_axi_arlen;
wire [2:0] expl_axi_arsize;
wire expl_axi_awvalid;
wire expl_axi_awready;
wire [`E203_ADDR_SIZE-1:0] expl_axi_awaddr;
wire [3:0] expl_axi_awcache;
wire [2:0] expl_axi_awprot;
wire [1:0] expl_axi_awlock;
wire [1:0] expl_axi_awburst;
wire [3:0] expl_axi_awlen;
wire [2:0] expl_axi_awsize;
wire expl_axi_rvalid;
wire expl_axi_rready;
wire [`E203_XLEN-1:0] expl_axi_rdata;
wire [1:0] expl_axi_rresp;
wire expl_axi_rlast;
wire expl_axi_wvalid;
wire expl_axi_wready;
wire [`E203_XLEN-1:0] expl_axi_wdata;
wire [(`E203_XLEN/8)-1:0] expl_axi_wstrb;
wire expl_axi_wlast;
wire expl_axi_bvalid;
wire expl_axi_bready;
wire [1:0] expl_axi_bresp;
sirv_gnrl_icb2axi # (
.AXI_FIFO_DP (2), // We just add ping-pong buffer here to avoid any potential timing loops
// User can change it to 0 if dont care
.AXI_FIFO_CUT_READY (1), // This is to cut the back-pressure signal if you set as 1
.AW (32),
.FIFO_OUTS_NUM (4),// We only allow 4 oustandings at most for mem, user can configure it to any value
.FIFO_CUT_READY(1),
.DW (`E203_XLEN)
) u_expl_axi_icb2axi(
.i_icb_cmd_valid (expl_axi_icb_cmd_valid),
.i_icb_cmd_ready (expl_axi_icb_cmd_ready),
.i_icb_cmd_addr (expl_axi_icb_cmd_addr ),
.i_icb_cmd_read (expl_axi_icb_cmd_read ),
.i_icb_cmd_wdata (expl_axi_icb_cmd_wdata),
.i_icb_cmd_wmask (expl_axi_icb_cmd_wmask),
.i_icb_cmd_size (),
.i_icb_rsp_valid (expl_axi_icb_rsp_valid),
.i_icb_rsp_ready (expl_axi_icb_rsp_ready),
.i_icb_rsp_rdata (expl_axi_icb_rsp_rdata),
.i_icb_rsp_err (expl_axi_icb_rsp_err),
.o_axi_arvalid (expl_axi_arvalid),
.o_axi_arready (expl_axi_arready),
.o_axi_araddr (expl_axi_araddr ),
.o_axi_arcache (expl_axi_arcache),
.o_axi_arprot (expl_axi_arprot ),
.o_axi_arlock (expl_axi_arlock ),
.o_axi_arburst (expl_axi_arburst),
.o_axi_arlen (expl_axi_arlen ),
.o_axi_arsize (expl_axi_arsize ),
.o_axi_awvalid (expl_axi_awvalid),
.o_axi_awready (expl_axi_awready),
.o_axi_awaddr (expl_axi_awaddr ),
.o_axi_awcache (expl_axi_awcache),
.o_axi_awprot (expl_axi_awprot ),
.o_axi_awlock (expl_axi_awlock ),
.o_axi_awburst (expl_axi_awburst),
.o_axi_awlen (expl_axi_awlen ),
.o_axi_awsize (expl_axi_awsize ),
.o_axi_rvalid (expl_axi_rvalid ),
.o_axi_rready (expl_axi_rready ),
.o_axi_rdata (expl_axi_rdata ),
.o_axi_rresp (expl_axi_rresp ),
.o_axi_rlast (expl_axi_rlast ),
.o_axi_wvalid (expl_axi_wvalid ),
.o_axi_wready (expl_axi_wready ),
.o_axi_wdata (expl_axi_wdata ),
.o_axi_wstrb (expl_axi_wstrb ),
.o_axi_wlast (expl_axi_wlast ),
.o_axi_bvalid (expl_axi_bvalid ),
.o_axi_bready (expl_axi_bready ),
.o_axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (bus_rst_n)
);
sirv_expl_axi_slv # (
.AW (32),
.DW (`E203_XLEN)
) u_perips_expl_axi_slv (
.axi_arvalid (expl_axi_arvalid),
.axi_arready (expl_axi_arready),
.axi_araddr (expl_axi_araddr ),
.axi_arcache (expl_axi_arcache),
.axi_arprot (expl_axi_arprot ),
.axi_arlock (expl_axi_arlock ),
.axi_arburst (expl_axi_arburst),
.axi_arlen (expl_axi_arlen ),
.axi_arsize (expl_axi_arsize ),
.axi_awvalid (expl_axi_awvalid),
.axi_awready (expl_axi_awready),
.axi_awaddr (expl_axi_awaddr ),
.axi_awcache (expl_axi_awcache),
.axi_awprot (expl_axi_awprot ),
.axi_awlock (expl_axi_awlock ),
.axi_awburst (expl_axi_awburst),
.axi_awlen (expl_axi_awlen ),
.axi_awsize (expl_axi_awsize ),
.axi_rvalid (expl_axi_rvalid ),
.axi_rready (expl_axi_rready ),
.axi_rdata (expl_axi_rdata ),
.axi_rresp (expl_axi_rresp ),
.axi_rlast (expl_axi_rlast ),
.axi_wvalid (expl_axi_wvalid ),
.axi_wready (expl_axi_wready ),
.axi_wdata (expl_axi_wdata ),
.axi_wstrb (expl_axi_wstrb ),
.axi_wlast (expl_axi_wlast ),
.axi_bvalid (expl_axi_bvalid ),
.axi_bready (expl_axi_bready ),
.axi_bresp (expl_axi_bresp ),
.clk (clk ),
.rst_n (rst_n)
);
endmodule |
module sirv_AsyncResetRegVec_1(
input clock,
input reset,
input [4:0] io_d,
output [4:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire [1:0] T_13;
wire [1:0] T_14;
wire [2:0] T_15;
wire [4:0] T_16;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
assign io_q = T_16;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = {reg_1_q,reg_0_q};
assign T_14 = {reg_4_q,reg_3_q};
assign T_15 = {T_14,reg_2_q};
assign T_16 = {T_15,T_13};
endmodule |
module sirv_queue_1(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input [7:0] io_enq_bits,
input io_deq_ready,
output io_deq_valid,
output [7:0] io_deq_bits,
output [3:0] io_count
);
reg [7:0] ram [0:7];
reg [31:0] GEN_0;
wire [7:0] ram_T_51_data;
wire [2:0] ram_T_51_addr;
wire [7:0] ram_T_35_data;
wire [2:0] ram_T_35_addr;
wire ram_T_35_mask;
wire ram_T_35_en;
reg [2:0] T_27;
reg [31:0] GEN_1;
reg [2:0] T_29;
reg [31:0] GEN_2;
reg maybe_full;
reg [31:0] GEN_3;
wire ptr_match;
wire T_32;
wire empty;
wire full;
wire T_33;
wire do_enq;
wire T_34;
wire do_deq;
wire [3:0] T_39;
wire [2:0] T_40;
wire [2:0] GEN_4;
wire [3:0] T_44;
wire [2:0] T_45;
wire [2:0] GEN_5;
wire T_46;
wire GEN_6;
wire T_48;
wire T_50;
wire [3:0] T_52;
wire [2:0] ptr_diff;
wire T_53;
wire [3:0] T_54;
assign io_enq_ready = T_50;
assign io_deq_valid = T_48;
assign io_deq_bits = ram_T_51_data;
assign io_count = T_54;
assign ram_T_51_addr = T_29;
assign ram_T_51_data = ram[ram_T_51_addr];
assign ram_T_35_data = io_enq_bits;
assign ram_T_35_addr = T_27;
assign ram_T_35_mask = do_enq;
assign ram_T_35_en = do_enq;
assign ptr_match = T_27 == T_29;
assign T_32 = maybe_full == 1'h0;
assign empty = ptr_match & T_32;
assign full = ptr_match & maybe_full;
assign T_33 = io_enq_ready & io_enq_valid;
assign do_enq = T_33;
assign T_34 = io_deq_ready & io_deq_valid;
assign do_deq = T_34;
assign T_39 = T_27 + 3'h1;
assign T_40 = T_39[2:0];
assign GEN_4 = do_enq ? T_40 : T_27;
assign T_44 = T_29 + 3'h1;
assign T_45 = T_44[2:0];
assign GEN_5 = do_deq ? T_45 : T_29;
assign T_46 = do_enq != do_deq;
assign GEN_6 = T_46 ? do_enq : maybe_full;
assign T_48 = empty == 1'h0;
assign T_50 = full == 1'h0;
assign T_52 = T_27 - T_29;
assign ptr_diff = T_52[2:0];
assign T_53 = maybe_full & ptr_match;
assign T_54 = {T_53,ptr_diff};
always @(posedge clock) begin // The RAM block does not need reset
if(ram_T_35_en & ram_T_35_mask) begin
ram[ram_T_35_addr] <= ram_T_35_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_27 <= 3'h0;
end else begin
if (do_enq) begin
T_27 <= T_40;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_29 <= 3'h0;
end else begin
if (do_deq) begin
T_29 <= T_45;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (T_46) begin
maybe_full <= do_enq;
end
end
endmodule |
module sirv_gnrl_ram
#(parameter DP = 32,
parameter DW = 32,
parameter FORCE_X2ZERO = 1,
parameter MW = 4,
parameter AW = 15
) (
input sd,
input ds,
input ls,
input rst_n,
input clk,
input cs,
input we,
input [AW-1:0] addr,
input [DW-1:0] din,
input [MW-1:0] wem,
output[DW-1:0] dout
);
//To add the ASIC or FPGA or Sim-model control here
// This is the Sim-model
//
`ifdef FPGA_SOURCE
sirv_sim_ram #(
.FORCE_X2ZERO (1'b0),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`else
sirv_sim_ram #(
.FORCE_X2ZERO (FORCE_X2ZERO),
.DP (DP),
.AW (AW),
.MW (MW),
.DW (DW)
)u_sirv_sim_ram (
.clk (clk),
.din (din),
.addr (addr),
.cs (cs),
.we (we),
.wem (wem),
.dout (dout)
);
`endif
endmodule |
module e203_cpu_top(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
// If this signal is high, then indicate the Core have executed WFI instruction
// and entered into the sleep state
output core_wfi,
// This signal is from our self-defined COUNTERSTOP (0xBFF) CSR's TM field
// software can programe this CSR to turn off the MTIME timer to save power
// If this signal is high, then the MTIME timer from CLINT module will stop counting
output tm_stop,
// This signal can be used to indicate the PC value for the core after reset
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// The interface to Debug Module: Begin
//
// The synced debug interrupt back to Debug module
output dbg_irq_r,
// The debug mode CSR registers control interface from/to Debug module
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
// The debug mode control signals from Debug Module
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
input dbg_irq_a,
// The interface to Debug Module: End
// This signal can be used to indicate the HART ID for this core
input [`E203_HART_ID_W-1:0] core_mhartid,
// The External Interrupt signal from PLIC
input ext_irq_a,
// The Software Interrupt signal from CLINT
input sft_irq_a,
// The Timer Interrupt signal from CLINT
input tmr_irq_a,
// The PMU control signal from PMU to control the TCM Shutdown
input tcm_sd,
// The PMU control signal from PMU to control the TCM Deep-Sleep
input tcm_ds,
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access ITCM: Begin
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
// External interface (ICB) to access ITCM: End
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
// External interface (ICB) to access DTCM: Start
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
// External interface (ICB) to access DTCM: End
`endif//}
//////////////////////////////////////////////////////////////
// The Private Peripheral Interface (ICB): Begin
//
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
// The Private Peripheral Interface (ICB): End
//////////////////////////////////////////////////////////////
// The CLINT Interface (ICB): Begin
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
// The CLINT Interface (ICB): End
//////////////////////////////////////////////////////////////
// The PLIC Interface (ICB): Begin
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
// The PLIC Interface (ICB): End
//////////////////////////////////////////////////////////////
// The Fast IO Interface (ICB): Begin
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
// The Fast IO Interface (ICB): End
//////////////////////////////////////////////////////////////
// The System Memory Interface (ICB): Begin
//
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
// The System Memory Interface (ICB): End
// The test mode signal
input test_mode,
// The Clock
input clk,
// The low-level active reset signal, treated as async
input rst_n
);
`ifdef E203_HAS_ITCM //{
wire itcm_ls;
wire rst_itcm;
wire itcm_ram_cs ;
wire itcm_ram_we ;
wire [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr;
wire [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem ;
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout;
`endif//}
wire clk_itcm_ram ;
`endif//}
`ifdef E203_HAS_DTCM //{
wire dtcm_ls;
wire rst_dtcm;
wire dtcm_ram_cs ;
wire dtcm_ram_we ;
wire [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr;
wire [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem ;
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din ;
`ifndef E203_HAS_LOCKSTEP//{
wire [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout;
`endif//}
wire clk_dtcm_ram ;
`endif//}
`ifndef E203_HAS_LOCKSTEP//{
wire ppi_icb_rsp_excl_ok ;
wire fio_icb_rsp_excl_ok ;
wire plic_icb_rsp_excl_ok ;
wire clint_icb_rsp_excl_ok ;
wire mem_icb_rsp_excl_ok ;
`ifdef E203_HAS_PPI
wire ppi_icb_enable;
wire [`E203_ADDR_SIZE-1:0] ppi_region_indic;
`endif
`ifdef E203_HAS_PLIC
wire plic_icb_enable;
wire [`E203_ADDR_SIZE-1:0] plic_region_indic;
`endif
`ifdef E203_HAS_CLINT
wire clint_icb_enable;
wire [`E203_ADDR_SIZE-1:0] clint_region_indic;
`endif
`ifdef E203_HAS_MEM_ITF
wire mem_icb_enable;
`endif
`ifdef E203_HAS_FIO
wire fio_icb_enable;
wire [`E203_ADDR_SIZE-1:0] fio_region_indic;
`endif
`endif//}
assign ppi_icb_rsp_excl_ok = 1'b0;
assign fio_icb_rsp_excl_ok = 1'b0;
assign plic_icb_rsp_excl_ok = 1'b0;
assign clint_icb_rsp_excl_ok = 1'b0;
assign mem_icb_rsp_excl_ok = 1'b0;
`ifdef E203_HAS_PPI
assign ppi_icb_enable = 1'b1;
assign ppi_region_indic = `E203_PPI_ADDR_BASE;
`else
assign ppi_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_PLIC
assign plic_icb_enable = 1'b1;
assign plic_region_indic = `E203_PLIC_ADDR_BASE;
`else
assign plic_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_CLINT
assign clint_icb_enable = 1'b1;
assign clint_region_indic = `E203_CLINT_ADDR_BASE;
`else
assign clint_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_MEM_ITF
assign mem_icb_enable = 1'b1;
`else
assign mem_icb_enable = 1'b0;
`endif
`ifdef E203_HAS_FIO
assign fio_icb_enable = 1'b1;
assign fio_region_indic = `E203_FIO_ADDR_BASE;
`else
assign fio_icb_enable = 1'b0;
`endif
e203_cpu #(.MASTER(1)) u_e203_cpu(
.inspect_pc (inspect_pc),
.inspect_dbg_irq (inspect_dbg_irq ),
.inspect_mem_cmd_valid (inspect_mem_cmd_valid),
.inspect_mem_cmd_ready (inspect_mem_cmd_ready),
.inspect_mem_rsp_valid (inspect_mem_rsp_valid),
.inspect_mem_rsp_ready (inspect_mem_rsp_ready),
.inspect_core_clk (inspect_core_clk ),
.core_csr_clk (core_csr_clk ),
.tm_stop (tm_stop),
.pc_rtvec(pc_rtvec),
`ifdef E203_HAS_ITCM //{
.itcm_ls (itcm_ls),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ls (dtcm_ls),
`endif//}
.core_wfi (core_wfi),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.core_mhartid (core_mhartid),
.dbg_irq_a (dbg_irq_a),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (),
.ppi_icb_cmd_excl (),
.ppi_icb_cmd_size (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok ),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.clint_region_indic (clint_region_indic),
.clint_icb_enable (clint_icb_enable),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (),
.clint_icb_cmd_excl (),
.clint_icb_cmd_size (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok ),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
.plic_region_indic (plic_region_indic),
.plic_icb_enable (plic_icb_enable),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (),
.plic_icb_cmd_excl (),
.plic_icb_cmd_size (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok ),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (),
.fio_icb_cmd_excl (),
.fio_icb_cmd_size (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (),
.mem_icb_cmd_excl (),
.mem_icb_cmd_size (),
.mem_icb_cmd_burst (),
.mem_icb_cmd_beat (),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
.test_mode (test_mode),
`ifndef E203_HAS_LOCKSTEP//{
`endif//}
.rst_n (rst_n),
.clk (clk )
);
e203_srams u_e203_srams(
`ifdef E203_HAS_DTCM //{
.dtcm_ram_sd (tcm_sd),
.dtcm_ram_ds (tcm_ds),
.dtcm_ram_ls (dtcm_ls),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
.rst_dtcm(rst_dtcm),
`endif//}
`ifdef E203_HAS_ITCM //{
.itcm_ram_sd (tcm_sd),
.itcm_ram_ds (tcm_ds),
.itcm_ram_ls (itcm_ls),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
.rst_itcm(rst_itcm),
`endif//}
.test_mode (test_mode)
);
endmodule |
module sirv_uartgpioport(
input clock,
input reset,
input io_uart_txd,
output io_uart_rxd,
input io_pins_rxd_i_ival,
output io_pins_rxd_o_oval,
output io_pins_rxd_o_oe,
output io_pins_rxd_o_ie,
output io_pins_rxd_o_pue,
output io_pins_rxd_o_ds,
input io_pins_txd_i_ival,
output io_pins_txd_o_oval,
output io_pins_txd_o_oe,
output io_pins_txd_o_ie,
output io_pins_txd_o_pue,
output io_pins_txd_o_ds
);
assign io_uart_rxd = io_pins_rxd_i_ival;
assign io_pins_rxd_o_oval = 1'h0;
assign io_pins_rxd_o_oe = 1'h0;
assign io_pins_rxd_o_ie = 1'h1;
assign io_pins_rxd_o_pue = 1'h0;
assign io_pins_rxd_o_ds = 1'h0;
assign io_pins_txd_o_oval = io_uart_txd;
assign io_pins_txd_o_oe = 1'h1;
assign io_pins_txd_o_ie = 1'h0;
assign io_pins_txd_o_pue = 1'h0;
assign io_pins_txd_o_ds = 1'h0;
endmodule |
module e203_exu_excp(
output commit_trap,
output core_wfi,
output wfi_halt_ifu_req,
output wfi_halt_exu_req,
input wfi_halt_ifu_ack,
input wfi_halt_exu_ack,
input amo_wait,
output alu_excp_i_ready,
input alu_excp_i_valid ,
input alu_excp_i_ld ,
input alu_excp_i_stamo ,
input alu_excp_i_misalgn ,
input alu_excp_i_buserr ,
input alu_excp_i_ecall ,
input alu_excp_i_ebreak ,
input alu_excp_i_wfi ,
input alu_excp_i_ifu_misalgn ,
input alu_excp_i_ifu_buserr ,
input alu_excp_i_ifu_ilegl ,
input [`E203_ADDR_SIZE-1:0] alu_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] alu_excp_i_pc,
input [`E203_INSTR_SIZE-1:0] alu_excp_i_instr,
input alu_excp_i_pc_vld,
output longp_excp_i_ready,
input longp_excp_i_valid,
input longp_excp_i_ld,
input longp_excp_i_st,// 1: load, 0: store
input longp_excp_i_buserr , // The load/store bus-error exception generated
input longp_excp_i_insterr,
input [`E203_ADDR_SIZE-1:0] longp_excp_i_badaddr,
input [`E203_PC_SIZE-1:0] longp_excp_i_pc,
input excpirq_flush_ack,
output excpirq_flush_req,
output nonalu_excpirq_flush_req_raw,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op1,
output [`E203_PC_SIZE-1:0] excpirq_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] excpirq_flush_pc,
`endif//}
input [`E203_XLEN-1:0] csr_mtvec_r,
input cmt_dret_ena,
input cmt_ena,
output [`E203_ADDR_SIZE-1:0] cmt_badaddr,
output [`E203_PC_SIZE-1:0] cmt_epc,
output [`E203_XLEN-1:0] cmt_cause,
output cmt_badaddr_ena,
output cmt_epc_ena,
output cmt_cause_ena,
output cmt_status_ena,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
input status_mie_r,
input mtie_r,
input msie_r,
input meie_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input oitf_empty,
input u_mode,
input s_mode,
input h_mode,
input m_mode,
output excp_active,
input clk,
input rst_n
);
////////////////////////////////////////////////////////////////////////////
// Because the core's clock may be gated when it is idle, we need to check
// if the interrupts is coming, and generate an active indication, and use
// this active signal to turn on core's clock
wire irq_req_active;
wire nonalu_dbg_entry_req_raw;
assign excp_active = irq_req_active | nonalu_dbg_entry_req_raw;
////////////////////////////////////////////////////////////////////////////
// WFI flag generation
//
wire wfi_req_hsked = (wfi_halt_ifu_req & wfi_halt_ifu_ack & wfi_halt_exu_req & wfi_halt_exu_ack)
;
// The wfi_flag will be set if there is a new WFI instruction halt req handshaked
wire wfi_flag_set = wfi_req_hsked;
// The wfi_flag will be cleared if there is interrupt pending, or debug entry request
wire wfi_irq_req;
wire dbg_entry_req;
wire wfi_flag_r;
wire wfi_flag_clr = (wfi_irq_req | dbg_entry_req);// & wfi_flag_r;// Here we cannot use this flag_r
wire wfi_flag_ena = wfi_flag_set | wfi_flag_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_flag_nxt = wfi_flag_set & (~wfi_flag_clr);
sirv_gnrl_dfflr #(1) wfi_flag_dfflr (wfi_flag_ena, wfi_flag_nxt, wfi_flag_r, clk, rst_n);
assign core_wfi = wfi_flag_r & (~wfi_flag_clr);
// The wfi_halt_req will be set if there is a new WFI instruction committed
// And note in debug mode WFI is treated as nop
wire wfi_cmt_ena = alu_excp_i_wfi & cmt_ena;
wire wfi_halt_req_set = wfi_cmt_ena & (~dbg_mode);
// The wfi_halt_req will be cleared same as wfi_flag_r
wire wfi_halt_req_clr = wfi_flag_clr;
wire wfi_halt_req_ena = wfi_halt_req_set | wfi_halt_req_clr;
// If meanwhile set and clear, then clear preempt
wire wfi_halt_req_nxt = wfi_halt_req_set & (~wfi_halt_req_clr);
wire wfi_halt_req_r;
sirv_gnrl_dfflr #(1) wfi_halt_req_dfflr (wfi_halt_req_ena, wfi_halt_req_nxt, wfi_halt_req_r, clk, rst_n);
// In order to make sure the flush to IFU and halt to IFU is not asserte at same cycle
// we use the clr signal here to qualify it
assign wfi_halt_ifu_req = (wfi_halt_req_r & (~wfi_halt_req_clr))
;
// To cut the comb loops, we dont use the clr signal here to qualify,
// the outcome is the halt-to-exu will be deasserted 1 cycle later than to-IFU
// but it doesnt matter much.
assign wfi_halt_exu_req = wfi_halt_req_r
;
wire irq_req;
wire longp_need_flush;
wire alu_need_flush;
wire dbg_ebrk_req;
wire dbg_trig_req;
////////////////////////////////////////////////////////////////////////////
// The Exception generate included several cases, priority from top to down
// *** Long-pipe triggered exception
// ---- Must wait the PC vld
// *** DebugMode-entry triggered exception (included ALU ebreakm)
// ---- Must wait the OITF empty and PC vld
// *** IRQ triggered exception
// ---- Must wait the OITF empty and PC vld
// *** ALU triggered exception (excluded the ebreakm into debug-mode)
// ---- Must wait the OITF empty
// Exclude the pc_vld for longp, to just always make sure the longp can always accepted
wire longp_excp_flush_req = longp_need_flush ;
assign longp_excp_i_ready = excpirq_flush_ack;
// ^^^ Below we qualified the pc_vld signal to IRQ and Debug-entry req, why?
// -- The Asyn-precise-excp (include IRQ and Debug-entry exception)
// need to use the next upcoming (not yet commited) instruction's PC
// for the mepc value, so we must wait next valid instruction coming
// and use its PC.
// -- The pc_vld indicate is just used to indicate next instruction's valid
// PC value.
// ^^^ Then the questions are coming, is there a possible that there is no pc_vld
// comes forever? and then this async-precise-exception never
// get served, and then become a deadlock?
// -- It should not be. Becuase:
// The IFU is always actively fetching next instructions, never stop,
// so ideally it will always provide next valid instructions as
// long as the Ifetch-path (bus to external memory or ITCM) is not hang
// (no bus response returned).
// ^^^ Then if there possible the Ifetch-path is hang? For examples:
// -- The Ifetched external memory does not provide response because of the External IRQ is not
// accepted by core.
// ** How could it be? This should not happen, otherwise it is a SoC bug.
//
wire dbg_entry_flush_req = dbg_entry_req & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush);
wire alu_excp_i_ready4dbg = (excpirq_flush_ack & oitf_empty & alu_excp_i_pc_vld & (~longp_need_flush));
wire irq_flush_req = irq_req & oitf_empty & alu_excp_i_pc_vld
& (~dbg_entry_req)
& (~longp_need_flush);
wire alu_excp_flush_req = alu_excp_i_valid & alu_need_flush & oitf_empty
& (~irq_req)
& (~dbg_entry_req)
& (~longp_need_flush);
wire nonalu_dbg_entry_req;
wire alu_excp_i_ready4nondbg = alu_need_flush ?
(excpirq_flush_ack & oitf_empty & (~irq_req) & (~nonalu_dbg_entry_req) & (~longp_need_flush))
: ( // The other higher priorty flush will override ALU commit
(~irq_req)
& (~nonalu_dbg_entry_req)
& (~longp_need_flush)
);
wire alu_ebreakm_flush_req_novld;
wire alu_dbgtrig_flush_req_novld;
assign alu_excp_i_ready = (alu_ebreakm_flush_req_novld | alu_dbgtrig_flush_req_novld) ? alu_excp_i_ready4dbg : alu_excp_i_ready4nondbg;
assign excpirq_flush_req = longp_excp_flush_req | dbg_entry_flush_req | irq_flush_req | alu_excp_flush_req;
wire all_excp_flush_req = longp_excp_flush_req | alu_excp_flush_req;
assign nonalu_excpirq_flush_req_raw =
longp_need_flush |
nonalu_dbg_entry_req_raw |
irq_req ;
wire excpirq_taken_ena = excpirq_flush_req & excpirq_flush_ack;
assign commit_trap = excpirq_taken_ena;
wire excp_taken_ena = all_excp_flush_req & excpirq_taken_ena;
wire irq_taken_ena = irq_flush_req & excpirq_taken_ena;
wire dbg_entry_taken_ena = dbg_entry_flush_req & excpirq_taken_ena;
assign excpirq_flush_add_op1 = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
assign excpirq_flush_add_op2 = dbg_entry_flush_req ? `E203_PC_SIZE'h0 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h0 : `E203_PC_SIZE'b0;
`ifdef E203_TIMING_BOOST//}
assign excpirq_flush_pc = dbg_entry_flush_req ? `E203_PC_SIZE'h800 : (all_excp_flush_req & dbg_mode) ? `E203_PC_SIZE'h808 : csr_mtvec_r;
`endif//}
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The Long-pipe triggered Exception
//
assign longp_need_flush = longp_excp_i_valid;// The longp come to excp
// module always ask for excepiton
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The DebugMode-entry triggered Exception
//
wire step_req_r;
wire alu_ebreakm_flush_req;
wire alu_dbgtrig_flush_req;
// The priority from top to down
// dbg_trig_req ? 3'd2 :
// dbg_ebrk_req ? 3'd1 :
// dbg_irq_req ? 3'd3 :
// dbg_step_req ? 3'd4 :
// dbg_halt_req ? 3'd5 :
// Since the step_req_r is last cycle generated indicated, means last instruction is single-step
// and it have been commited in non debug-mode, and then this cyclc step_req_r is the of the highest priority
wire dbg_step_req = step_req_r;
assign dbg_trig_req = alu_dbgtrig_flush_req & (~step_req_r);
assign dbg_ebrk_req = alu_ebreakm_flush_req & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire dbg_irq_req = dbg_irq_r & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r);
wire nonalu_dbg_irq_req = dbg_irq_r & (~step_req_r);
// The step have higher priority, and will preempt the halt
wire dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~alu_ebreakm_flush_req) & (~alu_dbgtrig_flush_req) & (~step_req_r) & (~dbg_step_r);
wire nonalu_dbg_halt_req = dbg_halt_r & (~dbg_irq_r) & (~step_req_r) & (~dbg_step_r);
// The debug-step request will be set when currently the step_r is high, and one
// instruction (in non debug_mode) have been executed
// The step request will be clear when
// core enter into the debug-mode
wire step_req_set = (~dbg_mode) & dbg_step_r & cmt_ena & (~dbg_entry_taken_ena);
wire step_req_clr = dbg_entry_taken_ena;
wire step_req_ena = step_req_set | step_req_clr;
wire step_req_nxt = step_req_set | (~step_req_clr);
sirv_gnrl_dfflr #(1) step_req_dfflr (step_req_ena, step_req_nxt, step_req_r, clk, rst_n);
// The debug-mode will mask off the debug-mode-entry
wire dbg_entry_mask = dbg_mode;
assign dbg_entry_req = (~dbg_entry_mask) & (
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
//
// Note: Only the async irq and halt and trig need to have this amo_wait to check
// others are sync event, no need to check with this
(dbg_irq_req & (~amo_wait))
| (dbg_halt_req & (~amo_wait))
| dbg_step_req
| (dbg_trig_req & (~amo_wait))
| dbg_ebrk_req
);
assign nonalu_dbg_entry_req = (~dbg_entry_mask) & (
(nonalu_dbg_irq_req & (~amo_wait))
| (nonalu_dbg_halt_req & (~amo_wait))
| dbg_step_req
//| (dbg_trig_req & (~amo_wait))
//| dbg_ebrk_req
);
assign nonalu_dbg_entry_req_raw = (~dbg_entry_mask) & (
dbg_irq_r
| dbg_halt_r
| step_req_r
//| dbg_trig_req
//| dbg_ebrk_req
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The IRQ triggered Exception
//
// The debug mode will mask off the interrupts
// The single-step mode will mask off the interrupts
wire irq_mask = dbg_mode | dbg_step_r | (~status_mie_r)
// Why do we put a AMO_wait here, because the AMO instructions
// is atomic, we must wait it to complete its all atomic operations
// and during wait cycles irq must be masked, otherwise the irq_req
// will block ALU commit (including AMO) and cause a deadlock
// Dont need to worry about the clock gating issue, if amo_wait,
// then defefinitely the ALU is active, and clock on
| amo_wait;
wire wfi_irq_mask = dbg_mode | dbg_step_r;
// Why dont we put amo_wait here, because this is for IRQ to wake
// up the core from sleep mode, the core was in sleep mode, then
// means there is no chance for it to still executing the AMO instructions
// with oustanding uops, so we dont need to worry about it.
wire irq_req_raw = (
//(|lcl_irq_r) // not support this now
(ext_irq_r & meie_r)
| (sft_irq_r & msie_r)
| (tmr_irq_r & mtie_r)
);
assign irq_req = (~irq_mask) & irq_req_raw;
assign wfi_irq_req = (~wfi_irq_mask) & irq_req_raw;
assign irq_req_active = wfi_flag_r ? wfi_irq_req : irq_req;
wire [`E203_XLEN-1:0] irq_cause;
assign irq_cause[31] = 1'b1;
assign irq_cause[30:4] = 27'b0;
assign irq_cause[3:0] = (sft_irq_r & msie_r) ? 4'd3 : // 3 Machine software interrupt
(tmr_irq_r & mtie_r) ? 4'd7 : // 7 Machine timer interrupt
(ext_irq_r & meie_r) ? 4'd11 : // 11 Machine external interrupt
4'b0;
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// The ALU triggered Exception
// The ebreak instruction will generated regular exception when the ebreakm
// bit of DCSR reg is not set
wire alu_excp_i_ebreak4excp = (alu_excp_i_ebreak & ((~dbg_ebreakm_r) | dbg_mode))
;
// The ebreak instruction will enter into the debug-mode when the ebreakm
// bit of DCSR reg is set
wire alu_excp_i_ebreak4dbg = alu_excp_i_ebreak
& (~alu_need_flush)// override by other alu exceptions
& dbg_ebreakm_r
& (~dbg_mode);//Not in debug mode
assign alu_ebreakm_flush_req = alu_excp_i_valid & alu_excp_i_ebreak4dbg;
assign alu_ebreakm_flush_req_novld = alu_excp_i_ebreak4dbg;
`ifndef E203_SUPPORT_TRIGM//{
// We dont support the HW Trigger Module yet
assign alu_dbgtrig_flush_req_novld = 1'b0;
assign alu_dbgtrig_flush_req = 1'b0;
`endif
assign alu_need_flush =
( alu_excp_i_misalgn
| alu_excp_i_buserr
| alu_excp_i_ebreak4excp
| alu_excp_i_ecall
| alu_excp_i_ifu_misalgn
| alu_excp_i_ifu_buserr
| alu_excp_i_ifu_ilegl
);
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////
// Update the CSRs (Mcause, .etc)
wire longp_excp_flush_req_ld = longp_excp_flush_req & longp_excp_i_ld;
wire longp_excp_flush_req_st = longp_excp_flush_req & longp_excp_i_st;
wire longp_excp_flush_req_insterr = longp_excp_flush_req & longp_excp_i_insterr;
wire alu_excp_flush_req_ld = alu_excp_flush_req & alu_excp_i_ld;
wire alu_excp_flush_req_stamo = alu_excp_flush_req & alu_excp_i_stamo;
wire alu_excp_flush_req_ebreak = (alu_excp_flush_req & alu_excp_i_ebreak4excp);
wire alu_excp_flush_req_ecall = (alu_excp_flush_req & alu_excp_i_ecall);
wire alu_excp_flush_req_ifu_misalgn = (alu_excp_flush_req & alu_excp_i_ifu_misalgn);
wire alu_excp_flush_req_ifu_buserr = (alu_excp_flush_req & alu_excp_i_ifu_buserr);
wire alu_excp_flush_req_ifu_ilegl = (alu_excp_flush_req & alu_excp_i_ifu_ilegl);
wire alu_excp_flush_req_ld_misalgn = (alu_excp_flush_req_ld & alu_excp_i_misalgn);// ALU load misalign
wire alu_excp_flush_req_ld_buserr = (alu_excp_flush_req_ld & alu_excp_i_buserr);// ALU load bus error
wire alu_excp_flush_req_stamo_misalgn = (alu_excp_flush_req_stamo & alu_excp_i_misalgn);// ALU store/AMO misalign
wire alu_excp_flush_req_stamo_buserr = (alu_excp_flush_req_stamo & alu_excp_i_buserr);// ALU store/AMO bus error
wire longp_excp_flush_req_ld_buserr = (longp_excp_flush_req_ld & longp_excp_i_buserr);// Longpipe load bus error
wire longp_excp_flush_req_st_buserr = (longp_excp_flush_req_st & longp_excp_i_buserr);// Longpipe store bus error
wire excp_flush_by_alu_agu =
alu_excp_flush_req_ld_misalgn
| alu_excp_flush_req_ld_buserr
| alu_excp_flush_req_stamo_misalgn
| alu_excp_flush_req_stamo_buserr;
wire excp_flush_by_longp_ldst =
longp_excp_flush_req_ld_buserr
| longp_excp_flush_req_st_buserr;
wire [`E203_XLEN-1:0] excp_cause;
assign excp_cause[31:5] = 27'b0;
assign excp_cause[4:0] =
alu_excp_flush_req_ifu_misalgn? 5'd0 //Instruction address misaligned
: alu_excp_flush_req_ifu_buserr ? 5'd1 //Instruction access fault
: alu_excp_flush_req_ifu_ilegl ? 5'd2 //Illegal instruction
: alu_excp_flush_req_ebreak ? 5'd3 //Breakpoint
: alu_excp_flush_req_ld_misalgn ? 5'd4 //load address misalign
: (longp_excp_flush_req_ld_buserr | alu_excp_flush_req_ld_buserr) ? 5'd5 //load access fault
: alu_excp_flush_req_stamo_misalgn ? 5'd6 //Store/AMO address misalign
: (longp_excp_flush_req_st_buserr | alu_excp_flush_req_stamo_buserr) ? 5'd7 //Store/AMO access fault
: (alu_excp_flush_req_ecall & u_mode) ? 5'd8 //Environment call from U-mode
: (alu_excp_flush_req_ecall & s_mode) ? 5'd9 //Environment call from S-mode
: (alu_excp_flush_req_ecall & h_mode) ? 5'd10 //Environment call from H-mode
: (alu_excp_flush_req_ecall & m_mode) ? 5'd11 //Environment call from M-mode
: longp_excp_flush_req_insterr ? 5'd16// This only happened for the EAI long instructions actually
: 5'h1F;//Otherwise a reserved value
// mbadaddr is an XLEN-bit read-write register formatted as shown in Figure 3.21. When
// * a hardware breakpoint is triggered,
// * an instruction-fetch address-misaligned or access exception
// * load address-misaligned or access exception
// * store address-misaligned or access exception
// occurs, mbadaddr is written with the faulting address.
// In Priv SPEC v1.10, the mbadaddr have been replaced to mtval, and added following points:
// * On an illegal instruction trap, mtval is written with the first XLEN bits of the faulting
// instruction .
// * For other exceptions, mtval is set to zero, but a future standard may redefine mtval's
// setting for other exceptions.
//
wire excp_flush_req_ld_misalgn = alu_excp_flush_req_ld_misalgn;
wire excp_flush_req_ld_buserr = alu_excp_flush_req_ld_buserr | longp_excp_flush_req_ld_buserr;
//wire cmt_badaddr_update = all_excp_flush_req &
// (
// alu_excp_flush_req_ebreak
// | alu_excp_flush_req_ifu_misalgn
// | alu_excp_flush_req_ifu_buserr
// | excp_flush_by_alu_agu
// | excp_flush_by_longp_ldst);
// Per Priv Spec v1.10, all trap need to update this register
// * When a trap is taken into M-mode, mtval is written with exception-specific
// information to assist software in handling the trap.
wire cmt_badaddr_update = excpirq_flush_req;
assign cmt_badaddr = excp_flush_by_longp_ldst ? longp_excp_i_badaddr :
excp_flush_by_alu_agu ? alu_excp_i_badaddr :
(alu_excp_flush_req_ebreak
| alu_excp_flush_req_ifu_misalgn
| alu_excp_flush_req_ifu_buserr) ? alu_excp_i_pc :
alu_excp_flush_req_ifu_ilegl ? alu_excp_i_instr :
`E203_ADDR_SIZE'b0;
// We use the exact PC of long-instruction when exception happened, but
// to note since the later instruction may already commited, so long-pipe
// excpetion is async-imprecise exceptions
assign cmt_epc = longp_excp_i_valid ? longp_excp_i_pc : alu_excp_i_pc;
assign cmt_cause = excp_taken_ena ? excp_cause : irq_cause;
// Any trap include exception and irq (exclude dbg_irq) will update mstatus register
// In the debug mode, epc/cause/status/badaddr will not update badaddr
assign cmt_epc_ena = (~dbg_mode) & (excp_taken_ena | irq_taken_ena);
assign cmt_cause_ena = cmt_epc_ena;
assign cmt_status_ena = cmt_epc_ena;
assign cmt_badaddr_ena = cmt_epc_ena & cmt_badaddr_update;
assign cmt_dpc = alu_excp_i_pc;// The ALU PC is the current next commiting PC (not yet commited)
assign cmt_dpc_ena = dbg_entry_taken_ena;
wire cmt_dcause_set = dbg_entry_taken_ena;
wire cmt_dcause_clr = cmt_dret_ena;
wire [2:0] set_dcause_nxt =
dbg_trig_req ? 3'd2 :
dbg_ebrk_req ? 3'd1 :
dbg_irq_req ? 3'd3 :
dbg_step_req ? 3'd4 :
dbg_halt_req ? 3'd5 :
3'd0;
assign cmt_dcause_ena = cmt_dcause_set | cmt_dcause_clr;
assign cmt_dcause = cmt_dcause_set ? set_dcause_nxt : 3'd0;
endmodule |
module IOBUF(
input I,
input T,
output O,
inout IO
);
assign IO = ~T ? I:1'bz;
assign O = IO;
endmodule |
module e203_subsys_gfcm(
input test_mode,
input clk0_rst_n,
input clk1_rst_n,
input sel1 ,
input clk0 ,
input clk1 ,
output clkout
);
wire clk0_sel = ~sel1;
wire clk1_sel = sel1;
localparam SYNC_LEVEL = 3;
wire clk0_sync_in;
reg [SYNC_LEVEL-1:0] clk0_sync_r;
always @(posedge clk0 or negedge clk0_rst_n)
begin:clk0_sync_PROC
if(clk0_rst_n == 1'b0)
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk0_sync_r[SYNC_LEVEL-1:0] <= {clk0_sync_r[SYNC_LEVEL-2:0],clk0_sync_in};
end
end
wire clk1_sync_in;
reg [SYNC_LEVEL-1:0] clk1_sync_r;
always @(posedge clk1 or negedge clk1_rst_n)
begin:clk1_sync_PROC
if(clk1_rst_n == 1'b0)
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {SYNC_LEVEL{1'b0}};
end
else
begin
clk1_sync_r[SYNC_LEVEL-1:0] <= {clk1_sync_r[SYNC_LEVEL-2:0],clk1_sync_in};
end
end
assign clk0_sync_in = (~clk1_sync_r[SYNC_LEVEL-1]) & clk0_sel;
assign clk1_sync_in = (~clk0_sync_r[SYNC_LEVEL-1]) & clk1_sel;
wire clk0_gated;
wire clk1_gated;
wire clk0_gate_en = clk0_sync_r[1];
e203_clkgate u_clk0_clkgate(
.clk_in (clk0 ),
.test_mode(test_mode ),
.clock_en (clk0_gate_en),
.clk_out (clk0_gated)
);
wire clk1_gate_en = clk1_sync_r[1];
e203_clkgate u_clk1_clkgate(
.clk_in (clk1 ),
.test_mode(test_mode ),
.clock_en (clk1_gate_en),
.clk_out (clk1_gated)
);
assign clkout = clk0_gated | clk1_gated;
endmodule |
module e203_dtcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_DTCM_RAM_AW-1:0] addr,
input [`E203_DTCM_RAM_MW-1:0] wem,
input [`E203_DTCM_RAM_DW-1:0] din,
output [`E203_DTCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
wire wren = we & cs;
wire [3:0]wea;
assign wea = (wren) ? wem : 4'b0;
wire rden;
assign rden = (~we) & cs;
// bram_32 u_e203_dtcm_gnrl_ram(
//
// .doa (dout),
// .dia (din ),
// .addra (addr),
// .wea (wea ),
// .cea (cs ),
// .clka (clk ),
// .rsta (1'b0)
// );
riscv_ram32 u_e203_dtcm_gnrl_ram
(
.address(addr),
.byteena(wea),
.clock (clk),
.data (din),
.rden (rden),
.wren (wren),
.q (dout)
);
// sirv_gnrl_ram #(
// `ifndef E203_HAS_ECC//{
// .FORCE_X2ZERO(0),
// `endif//}
// .DP(`E203_DTCM_RAM_DP),
// .DW(`E203_DTCM_RAM_DW),
// .MW(`E203_DTCM_RAM_MW),
// .AW(`E203_DTCM_RAM_AW)
// ) u_e203_dtcm_gnrl_ram(
// .sd (sd ),
// .ds (ds ),
// .ls (ls ),
//
// .rst_n (rst_n ),
// .clk (clk ),
// .cs (cs ),
// .we (we ),
// .addr(addr),
// .din (din ),
// .wem (wem ),
// .dout(dout)
// );
endmodule |
module e203_subsys_clint(
input clint_icb_cmd_valid,
output clint_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
input clint_icb_cmd_read,
input [`E203_XLEN-1:0] clint_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
//
output clint_icb_rsp_valid,
input clint_icb_rsp_ready,
output clint_icb_rsp_err,
output [`E203_XLEN-1:0] clint_icb_rsp_rdata,
output clint_tmr_irq,
output clint_sft_irq,
input aon_rtcToggle_a,
input tm_stop,
input clk,
input rst_n
);
wire aon_rtcToggle_r;
wire aon_rtcToggle;
sirv_gnrl_sync # (
.DP(`E203_ASYNC_FF_LEVELS),
.DW(1)
) u_aon_rtctoggle_sync(
.din_a (aon_rtcToggle_a),
.dout (aon_rtcToggle_r),
.clk (clk ),
.rst_n (rst_n)
);
sirv_clint_top u_sirv_clint_top(
.clk (clk ),
.rst_n (rst_n ),
.i_icb_cmd_valid (clint_icb_cmd_valid),
.i_icb_cmd_ready (clint_icb_cmd_ready),
.i_icb_cmd_addr (clint_icb_cmd_addr ),
.i_icb_cmd_read (clint_icb_cmd_read ),
.i_icb_cmd_wdata (clint_icb_cmd_wdata),
.i_icb_rsp_valid (clint_icb_rsp_valid),
.i_icb_rsp_ready (clint_icb_rsp_ready),
.i_icb_rsp_rdata (clint_icb_rsp_rdata),
.io_tiles_0_mtip (clint_tmr_irq),
.io_tiles_0_msip (clint_sft_irq),
.io_rtcToggle (aon_rtcToggle)
);
// We self-defined a mcounterstop CSR which contained a tm_stop field, this
// field can be use to disable different counters to save dynamic powers
// in the case where they dont really need the counters
assign aon_rtcToggle = aon_rtcToggle_r & (~tm_stop);
assign clint_icb_rsp_err = 1'b0;
endmodule |
module e203_subsys_pllclkdiv(
input rst_n,
input test_mode,
input divby1,
input [5:0] div,
input clk,// The PLL clock
output clkout // The divided Clock
);
wire [5:0] div_cnt_r;
wire div_cnt_sat = (div_cnt_r == div);
wire [5:0] div_cnt_nxt = div_cnt_sat ? 6'b0 : (div_cnt_r + 1'b1);
wire div_cnt_ena = (~divby1);
sirv_gnrl_dfflr #(6) div_cnt_dfflr (div_cnt_ena, div_cnt_nxt, div_cnt_r, clk, rst_n);
wire flag_r;
wire flag_nxt = ~flag_r;
wire flag_ena = div_cnt_ena & div_cnt_sat;
sirv_gnrl_dfflr #(1) flag_dfflr (flag_ena, flag_nxt, flag_r, clk, rst_n);
wire plloutdiv_en = divby1 |
((~flag_r) & div_cnt_sat);
e203_clkgate u_pllclkdiv_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (plloutdiv_en),
.clk_out (clkout)
);
endmodule |
module sirv_uart_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_port_txd,
input io_port_rxd
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_uart u_sirv_uart(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink ),
.io_port_txd (io_port_txd ),
.io_port_rxd (io_port_rxd )
);
endmodule |
module sirv_tlfragmenter_qspi_1(
input clock,
input reset,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [1:0] io_in_0_a_bits_source,
input [29:0] io_in_0_a_bits_address,
input io_in_0_a_bits_mask,
input [7:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [1:0] io_in_0_b_bits_source,
output [29:0] io_in_0_b_bits_address,
output io_in_0_b_bits_mask,
output [7:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [1:0] io_in_0_c_bits_source,
input [29:0] io_in_0_c_bits_address,
input [7:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [1:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output io_in_0_d_bits_addr_lo,
output [7:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_out_0_a_ready,
output io_out_0_a_valid,
output [2:0] io_out_0_a_bits_opcode,
output [2:0] io_out_0_a_bits_param,
output [2:0] io_out_0_a_bits_size,
output [6:0] io_out_0_a_bits_source,
output [29:0] io_out_0_a_bits_address,
output io_out_0_a_bits_mask,
output [7:0] io_out_0_a_bits_data,
output io_out_0_b_ready,
input io_out_0_b_valid,
input [2:0] io_out_0_b_bits_opcode,
input [1:0] io_out_0_b_bits_param,
input [2:0] io_out_0_b_bits_size,
input [6:0] io_out_0_b_bits_source,
input [29:0] io_out_0_b_bits_address,
input io_out_0_b_bits_mask,
input [7:0] io_out_0_b_bits_data,
input io_out_0_c_ready,
output io_out_0_c_valid,
output [2:0] io_out_0_c_bits_opcode,
output [2:0] io_out_0_c_bits_param,
output [2:0] io_out_0_c_bits_size,
output [6:0] io_out_0_c_bits_source,
output [29:0] io_out_0_c_bits_address,
output [7:0] io_out_0_c_bits_data,
output io_out_0_c_bits_error,
output io_out_0_d_ready,
input io_out_0_d_valid,
input [2:0] io_out_0_d_bits_opcode,
input [1:0] io_out_0_d_bits_param,
input [2:0] io_out_0_d_bits_size,
input [6:0] io_out_0_d_bits_source,
input io_out_0_d_bits_sink,
input io_out_0_d_bits_addr_lo,
input [7:0] io_out_0_d_bits_data,
input io_out_0_d_bits_error,
input io_out_0_e_ready,
output io_out_0_e_valid,
output io_out_0_e_bits_sink
);
reg [4:0] acknum;
reg [31:0] GEN_25;
reg [2:0] dOrig;
reg [31:0] GEN_26;
wire [4:0] dFragnum;
wire dFirst;
wire [7:0] T_1410;
wire T_1411;
wire dsizeOH1;
wire T_1414;
wire [4:0] GEN_5;
wire [4:0] T_1415;
wire T_1417;
wire T_1418;
wire T_1419;
wire T_1421;
wire [4:0] dFirst_acknum;
wire [5:0] GEN_8;
wire [5:0] T_1428;
wire [5:0] T_1430;
wire [5:0] T_1432;
wire [5:0] T_1433;
wire [5:0] T_1434;
wire [1:0] T_1435;
wire [3:0] T_1436;
wire T_1438;
wire [3:0] GEN_9;
wire [3:0] T_1439;
wire [1:0] T_1440;
wire [1:0] T_1441;
wire T_1443;
wire [1:0] T_1444;
wire T_1445;
wire [1:0] T_1446;
wire [2:0] dFirst_size;
wire T_1447;
wire [5:0] T_1448;
wire [4:0] T_1449;
wire [4:0] T_1450;
wire [2:0] GEN_0;
wire [4:0] GEN_1;
wire [2:0] GEN_2;
wire T_1459;
wire T_1460;
wire [1:0] T_1461;
reg r_error;
reg [31:0] GEN_27;
wire d_error;
wire GEN_3;
wire repeater_clock;
wire repeater_reset;
wire repeater_io_repeat;
wire repeater_io_full;
wire repeater_io_enq_ready;
wire repeater_io_enq_valid;
wire [2:0] repeater_io_enq_bits_opcode;
wire [2:0] repeater_io_enq_bits_param;
wire [2:0] repeater_io_enq_bits_size;
wire [1:0] repeater_io_enq_bits_source;
wire [29:0] repeater_io_enq_bits_address;
wire repeater_io_enq_bits_mask;
wire [7:0] repeater_io_enq_bits_data;
wire repeater_io_deq_ready;
wire repeater_io_deq_valid;
wire [2:0] repeater_io_deq_bits_opcode;
wire [2:0] repeater_io_deq_bits_param;
wire [2:0] repeater_io_deq_bits_size;
wire [1:0] repeater_io_deq_bits_source;
wire [29:0] repeater_io_deq_bits_address;
wire repeater_io_deq_bits_mask;
wire [7:0] repeater_io_deq_bits_data;
wire find_0;
wire T_1494;
wire [2:0] aFrag;
wire [11:0] T_1497;
wire [4:0] T_1498;
wire [4:0] aOrigOH1;
wire [7:0] T_1501;
wire T_1502;
wire aFragOH1;
reg [4:0] gennum;
reg [31:0] GEN_28;
wire aFirst;
wire [5:0] T_1511;
wire [4:0] T_1512;
wire [4:0] old_gennum1;
wire [4:0] T_1513;
wire [4:0] GEN_10;
wire [4:0] T_1515;
wire [4:0] new_gennum;
wire T_1520;
wire [4:0] GEN_4;
wire T_1524;
wire [4:0] T_1526;
wire [4:0] T_1528;
wire [29:0] GEN_12;
wire [29:0] T_1529;
wire [6:0] T_1530;
wire T_1532;
wire T_1541;
wire T_1542;
wire T_1543;
wire T_1545;
wire T_1546;
wire [2:0] GEN_6 = 3'b0;
reg [31:0] GEN_29;
wire [1:0] GEN_7 = 2'b0;
reg [31:0] GEN_30;
wire [2:0] GEN_11 = 3'b0;
reg [31:0] GEN_31;
wire [1:0] GEN_13 = 2'b0;
reg [31:0] GEN_32;
wire [29:0] GEN_14 = 30'b0;
reg [31:0] GEN_33;
wire GEN_15 = 1'b0;
reg [31:0] GEN_34;
wire [7:0] GEN_16 = 8'b0;
reg [31:0] GEN_35;
wire [2:0] GEN_17 = 3'b0;
reg [31:0] GEN_36;
wire [2:0] GEN_18 = 3'b0;
reg [31:0] GEN_37;
wire [2:0] GEN_19 = 3'b0;
reg [31:0] GEN_38;
wire [6:0] GEN_20 = 7'b0;
reg [31:0] GEN_39;
wire [29:0] GEN_21 = 30'b0;
reg [31:0] GEN_40;
wire [7:0] GEN_22 = 8'b0;
reg [31:0] GEN_41;
wire GEN_23 = 1'b0;
reg [31:0] GEN_42;
wire GEN_24 = 1'b0;
reg [31:0] GEN_43;
sirv_repeater_6 u_repeater (
.clock(repeater_clock),
.reset(repeater_reset),
.io_repeat(repeater_io_repeat),
.io_full(repeater_io_full),
.io_enq_ready(repeater_io_enq_ready),
.io_enq_valid(repeater_io_enq_valid),
.io_enq_bits_opcode(repeater_io_enq_bits_opcode),
.io_enq_bits_param(repeater_io_enq_bits_param),
.io_enq_bits_size(repeater_io_enq_bits_size),
.io_enq_bits_source(repeater_io_enq_bits_source),
.io_enq_bits_address(repeater_io_enq_bits_address),
.io_enq_bits_mask(repeater_io_enq_bits_mask),
.io_enq_bits_data(repeater_io_enq_bits_data),
.io_deq_ready(repeater_io_deq_ready),
.io_deq_valid(repeater_io_deq_valid),
.io_deq_bits_opcode(repeater_io_deq_bits_opcode),
.io_deq_bits_param(repeater_io_deq_bits_param),
.io_deq_bits_size(repeater_io_deq_bits_size),
.io_deq_bits_source(repeater_io_deq_bits_source),
.io_deq_bits_address(repeater_io_deq_bits_address),
.io_deq_bits_mask(repeater_io_deq_bits_mask),
.io_deq_bits_data(repeater_io_deq_bits_data)
);
assign io_in_0_a_ready = repeater_io_enq_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_6;
assign io_in_0_b_bits_param = GEN_7;
assign io_in_0_b_bits_size = GEN_11;
assign io_in_0_b_bits_source = GEN_13;
assign io_in_0_b_bits_address = GEN_14;
assign io_in_0_b_bits_mask = GEN_15;
assign io_in_0_b_bits_data = GEN_16;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = io_out_0_d_valid;
assign io_in_0_d_bits_opcode = io_out_0_d_bits_opcode;
assign io_in_0_d_bits_param = io_out_0_d_bits_param;
assign io_in_0_d_bits_size = GEN_0;
assign io_in_0_d_bits_source = T_1461;
assign io_in_0_d_bits_sink = io_out_0_d_bits_sink;
assign io_in_0_d_bits_addr_lo = T_1460;
assign io_in_0_d_bits_data = io_out_0_d_bits_data;
assign io_in_0_d_bits_error = d_error;
assign io_in_0_e_ready = 1'h1;
assign io_out_0_a_valid = repeater_io_deq_valid;
assign io_out_0_a_bits_opcode = repeater_io_deq_bits_opcode;
assign io_out_0_a_bits_param = repeater_io_deq_bits_param;
assign io_out_0_a_bits_size = aFrag;
assign io_out_0_a_bits_source = T_1530;
assign io_out_0_a_bits_address = T_1529;
assign io_out_0_a_bits_mask = T_1546;
assign io_out_0_a_bits_data = io_in_0_a_bits_data;
assign io_out_0_b_ready = 1'h1;
assign io_out_0_c_valid = 1'h0;
assign io_out_0_c_bits_opcode = GEN_17;
assign io_out_0_c_bits_param = GEN_18;
assign io_out_0_c_bits_size = GEN_19;
assign io_out_0_c_bits_source = GEN_20;
assign io_out_0_c_bits_address = GEN_21;
assign io_out_0_c_bits_data = GEN_22;
assign io_out_0_c_bits_error = GEN_23;
assign io_out_0_d_ready = io_in_0_d_ready;
assign io_out_0_e_valid = 1'h0;
assign io_out_0_e_bits_sink = GEN_24;
assign dFragnum = io_out_0_d_bits_source[4:0];
assign dFirst = acknum == 5'h0;
assign T_1410 = 8'h1 << io_out_0_d_bits_size;
assign T_1411 = T_1410[0];
assign dsizeOH1 = ~ T_1411;
assign T_1414 = io_out_0_d_valid == 1'h0;
assign GEN_5 = {{4'd0}, dsizeOH1};
assign T_1415 = dFragnum & GEN_5;
assign T_1417 = T_1415 == 5'h0;
assign T_1418 = T_1414 | T_1417;
assign T_1419 = T_1418 | reset;
assign T_1421 = T_1419 == 1'h0;
assign dFirst_acknum = dFragnum | GEN_5;
assign GEN_8 = {{1'd0}, dFirst_acknum};
assign T_1428 = GEN_8 << 1;
assign T_1430 = T_1428 | 6'h1;
assign T_1432 = {1'h0,dFirst_acknum};
assign T_1433 = ~ T_1432;
assign T_1434 = T_1430 & T_1433;
assign T_1435 = T_1434[5:4];
assign T_1436 = T_1434[3:0];
assign T_1438 = T_1435 != 2'h0;
assign GEN_9 = {{2'd0}, T_1435};
assign T_1439 = GEN_9 | T_1436;
assign T_1440 = T_1439[3:2];
assign T_1441 = T_1439[1:0];
assign T_1443 = T_1440 != 2'h0;
assign T_1444 = T_1440 | T_1441;
assign T_1445 = T_1444[1];
assign T_1446 = {T_1443,T_1445};
assign dFirst_size = {T_1438,T_1446};
assign T_1447 = io_out_0_d_ready & io_out_0_d_valid;
assign T_1448 = acknum - 5'h1;
assign T_1449 = T_1448[4:0];
assign T_1450 = dFirst ? dFirst_acknum : T_1449;
assign GEN_0 = dFirst ? dFirst_size : dOrig;
assign GEN_1 = T_1447 ? T_1450 : acknum;
assign GEN_2 = T_1447 ? GEN_0 : dOrig;
assign T_1459 = ~ dsizeOH1;
assign T_1460 = io_out_0_d_bits_addr_lo & T_1459;
assign T_1461 = io_out_0_d_bits_source[6:5];
assign d_error = r_error | io_out_0_d_bits_error;
assign GEN_3 = T_1447 ? 1'h0 : r_error;
assign repeater_clock = clock;
assign repeater_reset = reset;
assign repeater_io_repeat = T_1524;
assign repeater_io_enq_valid = io_in_0_a_valid;
assign repeater_io_enq_bits_opcode = io_in_0_a_bits_opcode;
assign repeater_io_enq_bits_param = io_in_0_a_bits_param;
assign repeater_io_enq_bits_size = io_in_0_a_bits_size;
assign repeater_io_enq_bits_source = io_in_0_a_bits_source;
assign repeater_io_enq_bits_address = io_in_0_a_bits_address;
assign repeater_io_enq_bits_mask = io_in_0_a_bits_mask;
assign repeater_io_enq_bits_data = io_in_0_a_bits_data;
assign repeater_io_deq_ready = io_out_0_a_ready;
assign find_0 = 1'h1;
assign T_1494 = repeater_io_deq_bits_size > 3'h0;
assign aFrag = T_1494 ? 3'h0 : repeater_io_deq_bits_size;
assign T_1497 = 12'h1f << repeater_io_deq_bits_size;
assign T_1498 = T_1497[4:0];
assign aOrigOH1 = ~ T_1498;
assign T_1501 = 8'h1 << aFrag;
assign T_1502 = T_1501[0];
assign aFragOH1 = ~ T_1502;
assign aFirst = gennum == 5'h0;
assign T_1511 = gennum - 5'h1;
assign T_1512 = T_1511[4:0];
assign old_gennum1 = aFirst ? aOrigOH1 : T_1512;
assign T_1513 = ~ old_gennum1;
assign GEN_10 = {{4'd0}, aFragOH1};
assign T_1515 = T_1513 | GEN_10;
assign new_gennum = ~ T_1515;
assign T_1520 = io_out_0_a_ready & io_out_0_a_valid;
assign GEN_4 = T_1520 ? new_gennum : gennum;
assign T_1524 = new_gennum != 5'h0;
assign T_1526 = ~ new_gennum;
assign T_1528 = T_1526 & aOrigOH1;
assign GEN_12 = {{25'd0}, T_1528};
assign T_1529 = repeater_io_deq_bits_address | GEN_12;
assign T_1530 = {repeater_io_deq_bits_source,new_gennum};
assign T_1532 = repeater_io_full == 1'h0;
assign T_1541 = repeater_io_deq_bits_mask;
assign T_1542 = T_1532 | T_1541;
assign T_1543 = T_1542 | reset;
assign T_1545 = T_1543 == 1'h0;
assign T_1546 = repeater_io_full ? 1'h1 : io_in_0_a_bits_mask;
always @(posedge clock or posedge reset)
if (reset) begin
acknum <= 5'h0;
end else begin
if (T_1447) begin
if (dFirst) begin
acknum <= dFirst_acknum;
end else begin
acknum <= T_1449;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
dOrig <= 3'b0;
end
else begin
if (T_1447) begin
if (dFirst) begin
dOrig <= dFirst_size;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
r_error <= 1'h0;
end else begin
if (T_1447) begin
r_error <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
gennum <= 5'h0;
end else begin
if (T_1520) begin
gennum <= new_gennum;
end
end
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1421) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1421) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (1'h0) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (1'h0) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef PRINTF_COND
// if (`PRINTF_COND) begin
// `endif
// if (T_1545) begin
// $fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
// end
// `ifdef PRINTF_COND
// end
// `endif
// `endif
// `ifndef SYNTHESIS
// `ifdef STOP_COND
// if (`STOP_COND) begin
// `endif
// if (T_1545) begin
// $fatal;
// end
// `ifdef STOP_COND
// end
// `endif
// `endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_1421) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:149 assert (!out.d.valid || (acknum_fragment & acknum_size) === UInt(0))\n");
end
if (T_1545) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:240 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n");
end
if (1'h0) begin
$fwrite(32'h80000002,"Assertion failed\n at Fragmenter.scala:237 assert (!repeater.io.full || !aHasData)\n");
end
end
//synopsys translate_on
endmodule |
module e203_subsys_hclkgen_rstsync (
input clk, // clock
input rst_n_a, // async reset
input test_mode, // test mode
output rst_n
);
localparam RST_SYNC_LEVEL = `E203_ASYNC_FF_LEVELS;
reg [RST_SYNC_LEVEL-1:0] rst_sync_r;
always @(posedge clk or negedge rst_n_a)
begin:rst_sync_PROC
if(rst_n_a == 1'b0)
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {RST_SYNC_LEVEL{1'b0}};
end
else
begin
rst_sync_r[RST_SYNC_LEVEL-1:0] <= {rst_sync_r[RST_SYNC_LEVEL-2:0],1'b1};
end
end
assign rst_n = test_mode ? rst_n_a : rst_sync_r[`E203_ASYNC_FF_LEVELS-1];
endmodule |
module e203_ifu_litebpu(
// Current PC
input [`E203_PC_SIZE-1:0] pc,
// The mini-decoded info
input dec_jal,
input dec_jalr,
input dec_bxx,
input [`E203_XLEN-1:0] dec_bjp_imm,
input [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
// The IR index and OITF status to be used for checking dependency
input oitf_empty,
input ir_empty,
input ir_rs1en,
input jalr_rs1idx_cam_irrdidx,
// The add op to next-pc adder
output bpu_wait,
output prdt_taken,
output [`E203_PC_SIZE-1:0] prdt_pc_add_op1,
output [`E203_PC_SIZE-1:0] prdt_pc_add_op2,
input dec_i_valid,
// The RS1 to read regfile
output bpu2rf_rs1_ena,
input ir_valid_clr,
input [`E203_XLEN-1:0] rf2bpu_x1,
input [`E203_XLEN-1:0] rf2bpu_rs1,
input clk,
input rst_n
);
// BPU of E201 utilize very simple static branch prediction logics
// * JAL: The target address of JAL is calculated based on current PC value
// and offset, and JAL is unconditionally always jump
// * JALR with rs1 == x0: The target address of JALR is calculated based on
// x0+offset, and JALR is unconditionally always jump
// * JALR with rs1 = x1: The x1 register value is directly wired from regfile
// when the x1 have no dependency with ongoing instructions by checking
// two conditions:
// ** (1) The OTIF in EXU must be empty
// ** (2) The instruction in IR have no x1 as destination register
// * If there is dependency, then hold up IFU until the dependency is cleared
// * JALR with rs1 != x0 or x1: The target address of JALR need to be resolved
// at EXU stage, hence have to be forced halted, wait the EXU to be
// empty and then read the regfile to grab the value of xN.
// This will exert 1 cycle performance lost for JALR instruction
// * Bxxx: Conditional branch is always predicted as taken if it is backward
// jump, and not-taken if it is forward jump. The target address of JAL
// is calculated based on current PC value and offset
// The JAL and JALR is always jump, bxxx backward is predicted as taken
assign prdt_taken = (dec_jal | dec_jalr | (dec_bxx & dec_bjp_imm[`E203_XLEN-1]));
// The JALR with rs1 == x1 have dependency or xN have dependency
wire dec_jalr_rs1x0 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd0);
wire dec_jalr_rs1x1 = (dec_jalr_rs1idx == `E203_RFIDX_WIDTH'd1);
wire dec_jalr_rs1xn = (~dec_jalr_rs1x0) & (~dec_jalr_rs1x1);
wire jalr_rs1x1_dep = dec_i_valid & dec_jalr & dec_jalr_rs1x1 & ((~oitf_empty) | (jalr_rs1idx_cam_irrdidx));
wire jalr_rs1xn_dep = dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~oitf_empty) | (~ir_empty));
// If only depend to IR stage (OITF is empty), then if IR is under clearing, or
// it does not use RS1 index, then we can also treat it as non-dependency
wire jalr_rs1xn_dep_ir_clr = (jalr_rs1xn_dep & oitf_empty & (~ir_empty)) & (ir_valid_clr | (~ir_rs1en));
wire rs1xn_rdrf_r;
wire rs1xn_rdrf_set = (~rs1xn_rdrf_r) & dec_i_valid & dec_jalr & dec_jalr_rs1xn & ((~jalr_rs1xn_dep) | jalr_rs1xn_dep_ir_clr);
wire rs1xn_rdrf_clr = rs1xn_rdrf_r;
wire rs1xn_rdrf_ena = rs1xn_rdrf_set | rs1xn_rdrf_clr;
wire rs1xn_rdrf_nxt = rs1xn_rdrf_set | (~rs1xn_rdrf_clr);
sirv_gnrl_dfflr #(1) rs1xn_rdrf_dfflrs(rs1xn_rdrf_ena, rs1xn_rdrf_nxt, rs1xn_rdrf_r, clk, rst_n);
assign bpu2rf_rs1_ena = rs1xn_rdrf_set;
assign bpu_wait = jalr_rs1x1_dep | jalr_rs1xn_dep | rs1xn_rdrf_set;
assign prdt_pc_add_op1 = (dec_bxx | dec_jal) ? pc[`E203_PC_SIZE-1:0]
: (dec_jalr & dec_jalr_rs1x0) ? `E203_PC_SIZE'b0
: (dec_jalr & dec_jalr_rs1x1) ? rf2bpu_x1[`E203_PC_SIZE-1:0]
: rf2bpu_rs1[`E203_PC_SIZE-1:0];
assign prdt_pc_add_op2 = dec_bjp_imm[`E203_PC_SIZE-1:0];
endmodule |
module sirv_plic_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_devices_0_0,
input io_devices_0_1,
input io_devices_0_2,
input io_devices_0_3,
input io_devices_0_4,
input io_devices_0_5,
input io_devices_0_6,
input io_devices_0_7,
input io_devices_0_8,
input io_devices_0_9,
input io_devices_0_10,
input io_devices_0_11,
input io_devices_0_12,
input io_devices_0_13,
input io_devices_0_14,
input io_devices_0_15,
input io_devices_0_16,
input io_devices_0_17,
input io_devices_0_18,
input io_devices_0_19,
input io_devices_0_20,
input io_devices_0_21,
input io_devices_0_22,
input io_devices_0_23,
input io_devices_0_24,
input io_devices_0_25,
input io_devices_0_26,
input io_devices_0_27,
input io_devices_0_28,
input io_devices_0_29,
input io_devices_0_30,
input io_devices_0_31,
input io_devices_0_32,
input io_devices_0_33,
input io_devices_0_34,
input io_devices_0_35,
input io_devices_0_36,
input io_devices_0_37,
input io_devices_0_38,
input io_devices_0_39,
input io_devices_0_40,
input io_devices_0_41,
input io_devices_0_42,
input io_devices_0_43,
input io_devices_0_44,
input io_devices_0_45,
input io_devices_0_46,
input io_devices_0_47,
input io_devices_0_48,
input io_devices_0_49,
input io_devices_0_50,
input io_devices_0_51,
output io_harts_0_0
);
wire plic_irq;
assign io_harts_0_0 = plic_irq;
localparam PLIC_IRQ_NUM = 53;// The number can be enlarged as long as not larger than 1024
wire [PLIC_IRQ_NUM-1:0] plic_irq_i = {
io_devices_0_51 ,
io_devices_0_50 ,
io_devices_0_49 ,
io_devices_0_48 ,
io_devices_0_47 ,
io_devices_0_46 ,
io_devices_0_45 ,
io_devices_0_44 ,
io_devices_0_43 ,
io_devices_0_42 ,
io_devices_0_41 ,
io_devices_0_40 ,
io_devices_0_39 ,
io_devices_0_38 ,
io_devices_0_37 ,
io_devices_0_36 ,
io_devices_0_35 ,
io_devices_0_34 ,
io_devices_0_33 ,
io_devices_0_32 ,
io_devices_0_31 ,
io_devices_0_30 ,
io_devices_0_29 ,
io_devices_0_28 ,
io_devices_0_27 ,
io_devices_0_26 ,
io_devices_0_25 ,
io_devices_0_24 ,
io_devices_0_23 ,
io_devices_0_22 ,
io_devices_0_21 ,
io_devices_0_20 ,
io_devices_0_19 ,
io_devices_0_18 ,
io_devices_0_17 ,
io_devices_0_16 ,
io_devices_0_15 ,
io_devices_0_14 ,
io_devices_0_13 ,
io_devices_0_12 ,
io_devices_0_11 ,
io_devices_0_10 ,
io_devices_0_9 ,
io_devices_0_8 ,
io_devices_0_7 ,
io_devices_0_6 ,
io_devices_0_5 ,
io_devices_0_4 ,
io_devices_0_3 ,
io_devices_0_2 ,
io_devices_0_1 ,
io_devices_0_0 ,
1'b0 };// The IRQ0 must be tied to zero
sirv_plic_man #(
.PLIC_PRIO_WIDTH (3),
.PLIC_IRQ_NUM (PLIC_IRQ_NUM),
.PLIC_IRQ_NUM_LOG2 (6),
.PLIC_ICB_RSP_FLOP (1),
.PLIC_IRQ_I_FLOP (1),
.PLIC_IRQ_O_FLOP (1)
) u_sirv_plic_man(
.clk (clk ),
.rst_n (rst_n ),
.icb_cmd_valid (i_icb_cmd_valid),
.icb_cmd_addr (i_icb_cmd_addr[24-1:0] ),
.icb_cmd_read (i_icb_cmd_read ),
.icb_cmd_wdata (i_icb_cmd_wdata),
.icb_rsp_ready (i_icb_rsp_ready),
.icb_rsp_valid (i_icb_rsp_valid),
.icb_cmd_ready (i_icb_cmd_ready),
.icb_rsp_rdata (i_icb_rsp_rdata),
.plic_irq_i (plic_irq_i),
.plic_irq_o (plic_irq )
);
endmodule |
module sirv_gnrl_dfflrs # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFLRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffl # (
parameter DW = 32
) (
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk
);
reg [DW-1:0] qout_r;
always @(posedge clk)
begin : DFFL_PROC
if (lden == 1'b1)
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffrs # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFRS_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b1}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_dffr # (
parameter DW = 32
) (
input [DW-1:0] dnxt,
output [DW-1:0] qout,
input clk,
input rst_n
);
reg [DW-1:0] qout_r;
always @(posedge clk or negedge rst_n)
begin : DFFR_PROC
if (rst_n == 1'b0)
qout_r <= {DW{1'b0}};
else
qout_r <= #1 dnxt;
end
assign qout = qout_r;
endmodule |
module sirv_gnrl_ltch # (
parameter DW = 32
) (
//input test_mode,
input lden,
input [DW-1:0] dnxt,
output [DW-1:0] qout
);
reg [DW-1:0] qout_r;
always @ *
begin : LTCH_PROC
if (lden == 1'b1)
qout_r <= dnxt;
end
//assign qout = test_mode ? dnxt : qout_r;
assign qout = qout_r;
endmodule |
module sirv_icb1to2_bus # (
parameter ICB_FIFO_DP = 0, // This is to optionally add the pipeline stage for ICB bus
// if the depth is 0, then means pass through, not add pipeline
// if the depth is 2, then means added one ping-pong buffer stage
parameter ICB_FIFO_CUT_READY = 1, // This is to cut the back-pressure signal if you set as 1
parameter AW = 32,
parameter DW = 32,
parameter SPLT_FIFO_OUTS_NUM = 1,
parameter SPLT_FIFO_CUT_READY = 1,
parameter O0_BASE_ADDR = 32'h0000_1000,
parameter O0_BASE_REGION_LSB = 12
)(
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [ AW-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [2-1:0] i_icb_cmd_burst,
input [2-1:0] i_icb_cmd_beat,
input [ DW-1:0] i_icb_cmd_wdata,
input [ DW/8-1:0] i_icb_cmd_wmask,
input i_icb_cmd_lock,
input i_icb_cmd_excl,
input [1:0] i_icb_cmd_size,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output i_icb_rsp_err ,
output i_icb_rsp_excl_ok,
output [ DW-1:0] i_icb_rsp_rdata,
output o0_icb_cmd_valid,
input o0_icb_cmd_ready,
output [ AW-1:0] o0_icb_cmd_addr,
output o0_icb_cmd_read,
output [2-1:0] o0_icb_cmd_burst,
output [2-1:0] o0_icb_cmd_beat,
output [ DW-1:0] o0_icb_cmd_wdata,
output [ DW/8-1:0] o0_icb_cmd_wmask,
output o0_icb_cmd_lock,
output o0_icb_cmd_excl,
output [1:0] o0_icb_cmd_size,
input o0_icb_rsp_valid,
output o0_icb_rsp_ready,
input o0_icb_rsp_err ,
input o0_icb_rsp_excl_ok,
input [ DW-1:0] o0_icb_rsp_rdata,
output o1_icb_cmd_valid,
input o1_icb_cmd_ready,
output [ AW-1:0] o1_icb_cmd_addr,
output o1_icb_cmd_read,
output [2-1:0] o1_icb_cmd_burst,
output [2-1:0] o1_icb_cmd_beat,
output [ DW-1:0] o1_icb_cmd_wdata,
output [ DW/8-1:0] o1_icb_cmd_wmask,
output o1_icb_cmd_lock,
output o1_icb_cmd_excl,
output [1:0] o1_icb_cmd_size,
input o1_icb_rsp_valid,
output o1_icb_rsp_ready,
input o1_icb_rsp_err ,
input o1_icb_rsp_excl_ok,
input [ DW-1:0] o1_icb_rsp_rdata,
input clk,
input rst_n
);
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [ AW-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [2-1:0] buf_icb_cmd_burst;
wire [2-1:0] buf_icb_cmd_beat;
wire [ DW-1:0] buf_icb_cmd_wdata;
wire [ DW/8-1:0] buf_icb_cmd_wmask;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err ;
wire buf_icb_rsp_excl_ok;
wire [ DW-1:0] buf_icb_rsp_rdata;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (SPLT_FIFO_OUTS_NUM),
.AW (AW),
.DW (DW),
.CMD_DP(ICB_FIFO_DP),
.RSP_DP(ICB_FIFO_DP),
.CMD_CUT_READY (ICB_FIFO_CUT_READY),
.RSP_CUT_READY (ICB_FIFO_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (),
.i_icb_cmd_valid (i_icb_cmd_valid),
.i_icb_cmd_ready (i_icb_cmd_ready),
.i_icb_cmd_read (i_icb_cmd_read ),
.i_icb_cmd_addr (i_icb_cmd_addr ),
.i_icb_cmd_wdata (i_icb_cmd_wdata),
.i_icb_cmd_wmask (i_icb_cmd_wmask),
.i_icb_cmd_lock (i_icb_cmd_lock ),
.i_icb_cmd_excl (i_icb_cmd_excl ),
.i_icb_cmd_size (i_icb_cmd_size ),
.i_icb_cmd_burst (i_icb_cmd_burst),
.i_icb_cmd_beat (i_icb_cmd_beat ),
.i_icb_cmd_usr (1'b0 ),
.i_icb_rsp_valid (i_icb_rsp_valid),
.i_icb_rsp_ready (i_icb_rsp_ready),
.i_icb_rsp_err (i_icb_rsp_err ),
.i_icb_rsp_excl_ok (i_icb_rsp_excl_ok),
.i_icb_rsp_rdata (i_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
localparam BASE_REGION_MSB = (AW-1);
localparam SPLT_I_NUM = 2;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [SPLT_I_NUM* AW-1:0] splt_bus_icb_cmd_addr;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_cmd_wdata;
wire [SPLT_I_NUM* DW/8-1:0] splt_bus_icb_cmd_wmask;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [SPLT_I_NUM* DW-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
o0_icb_cmd_valid
, o1_icb_cmd_valid
} = splt_bus_icb_cmd_valid;
assign {
o0_icb_cmd_addr
, o1_icb_cmd_addr
} = splt_bus_icb_cmd_addr;
assign {
o0_icb_cmd_read
, o1_icb_cmd_read
} = splt_bus_icb_cmd_read;
assign {
o0_icb_cmd_burst
, o1_icb_cmd_burst
} = splt_bus_icb_cmd_burst;
assign {
o0_icb_cmd_beat
, o1_icb_cmd_beat
} = splt_bus_icb_cmd_beat;
assign {
o0_icb_cmd_wdata
, o1_icb_cmd_wdata
} = splt_bus_icb_cmd_wdata;
assign {
o0_icb_cmd_wmask
, o1_icb_cmd_wmask
} = splt_bus_icb_cmd_wmask;
assign {
o0_icb_cmd_lock
, o1_icb_cmd_lock
} = splt_bus_icb_cmd_lock;
assign {
o0_icb_cmd_excl
, o1_icb_cmd_excl
} = splt_bus_icb_cmd_excl;
assign {
o0_icb_cmd_size
, o1_icb_cmd_size
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
o0_icb_cmd_ready
, o1_icb_cmd_ready
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
o0_icb_rsp_valid
, o1_icb_rsp_valid
};
assign splt_bus_icb_rsp_err = {
o0_icb_rsp_err
, o1_icb_rsp_err
};
assign splt_bus_icb_rsp_excl_ok = {
o0_icb_rsp_excl_ok
, o1_icb_rsp_excl_ok
};
assign splt_bus_icb_rsp_rdata = {
o0_icb_rsp_rdata
, o1_icb_rsp_rdata
};
assign {
o0_icb_rsp_ready
, o1_icb_rsp_ready
} = splt_bus_icb_rsp_ready;
wire icb_cmd_o0 = buf_icb_cmd_valid & (buf_icb_cmd_addr [BASE_REGION_MSB:O0_BASE_REGION_LSB]
== O0_BASE_ADDR [BASE_REGION_MSB:O0_BASE_REGION_LSB]
);
wire icb_cmd_o1 = ~icb_cmd_o0;
wire [SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
icb_cmd_o0
, icb_cmd_o1
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (SPLT_FIFO_OUTS_NUM ),
.FIFO_CUT_READY (SPLT_FIFO_CUT_READY),
.SPLT_NUM (SPLT_I_NUM),
.SPLT_PTR_W (SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.VLD_MSK_PAYLOAD(1),
.USR_W (1),
.AW (AW),
.DW (DW)
) u_i_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
endmodule |
module sirv_queue(
input clock,
input reset,
output io_enq_ready,
input io_enq_valid,
input io_enq_bits_read,
input [9:0] io_enq_bits_index,
input [31:0] io_enq_bits_data,
input [3:0] io_enq_bits_mask,
input [9:0] io_enq_bits_extra,
input io_deq_ready,
output io_deq_valid,
output io_deq_bits_read,
output [9:0] io_deq_bits_index,
output [31:0] io_deq_bits_data,
output [3:0] io_deq_bits_mask,
output [9:0] io_deq_bits_extra,
output io_count
);
reg ram_read [0:0];
reg [31:0] GEN_0;
wire ram_read_T_83_data;
wire ram_read_T_83_addr;
wire ram_read_T_69_data;
wire ram_read_T_69_addr;
wire ram_read_T_69_mask;
wire ram_read_T_69_en;
reg [9:0] ram_index [0:0];
reg [31:0] GEN_1;
wire [9:0] ram_index_T_83_data;
wire ram_index_T_83_addr;
wire [9:0] ram_index_T_69_data;
wire ram_index_T_69_addr;
wire ram_index_T_69_mask;
wire ram_index_T_69_en;
reg [31:0] ram_data [0:0];
reg [31:0] GEN_2;
wire [31:0] ram_data_T_83_data;
wire ram_data_T_83_addr;
wire [31:0] ram_data_T_69_data;
wire ram_data_T_69_addr;
wire ram_data_T_69_mask;
wire ram_data_T_69_en;
reg [3:0] ram_mask [0:0];
reg [31:0] GEN_3;
wire [3:0] ram_mask_T_83_data;
wire ram_mask_T_83_addr;
wire [3:0] ram_mask_T_69_data;
wire ram_mask_T_69_addr;
wire ram_mask_T_69_mask;
wire ram_mask_T_69_en;
reg [9:0] ram_extra [0:0];
reg [31:0] GEN_4;
wire [9:0] ram_extra_T_83_data;
wire ram_extra_T_83_addr;
wire [9:0] ram_extra_T_69_data;
wire ram_extra_T_69_addr;
wire ram_extra_T_69_mask;
wire ram_extra_T_69_en;
reg maybe_full;
reg [31:0] GEN_5;
wire T_65;
wire T_66;
wire do_enq;
wire T_67;
wire do_deq;
wire T_77;
wire GEN_8;
wire T_79;
wire GEN_9;
wire [1:0] T_90;
wire ptr_diff;
wire [1:0] T_92;
assign io_enq_ready = GEN_9;
assign io_deq_valid = T_79;
assign io_deq_bits_read = ram_read_T_83_data;
assign io_deq_bits_index = ram_index_T_83_data;
assign io_deq_bits_data = ram_data_T_83_data;
assign io_deq_bits_mask = ram_mask_T_83_data;
assign io_deq_bits_extra = ram_extra_T_83_data;
assign io_count = T_92[0];
assign ram_read_T_83_addr = 1'h0;
assign ram_read_T_83_data = ram_read[ram_read_T_83_addr];
assign ram_read_T_69_data = io_enq_bits_read;
assign ram_read_T_69_addr = 1'h0;
assign ram_read_T_69_mask = do_enq;
assign ram_read_T_69_en = do_enq;
assign ram_index_T_83_addr = 1'h0;
assign ram_index_T_83_data = ram_index[ram_index_T_83_addr];
assign ram_index_T_69_data = io_enq_bits_index;
assign ram_index_T_69_addr = 1'h0;
assign ram_index_T_69_mask = do_enq;
assign ram_index_T_69_en = do_enq;
assign ram_data_T_83_addr = 1'h0;
assign ram_data_T_83_data = ram_data[ram_data_T_83_addr];
assign ram_data_T_69_data = io_enq_bits_data;
assign ram_data_T_69_addr = 1'h0;
assign ram_data_T_69_mask = do_enq;
assign ram_data_T_69_en = do_enq;
assign ram_mask_T_83_addr = 1'h0;
assign ram_mask_T_83_data = ram_mask[ram_mask_T_83_addr];
assign ram_mask_T_69_data = io_enq_bits_mask;
assign ram_mask_T_69_addr = 1'h0;
assign ram_mask_T_69_mask = do_enq;
assign ram_mask_T_69_en = do_enq;
assign ram_extra_T_83_addr = 1'h0;
assign ram_extra_T_83_data = ram_extra[ram_extra_T_83_addr];
assign ram_extra_T_69_data = io_enq_bits_extra;
assign ram_extra_T_69_addr = 1'h0;
assign ram_extra_T_69_mask = do_enq;
assign ram_extra_T_69_en = do_enq;
assign T_65 = maybe_full == 1'h0;
assign T_66 = io_enq_ready & io_enq_valid;
assign do_enq = T_66;
assign T_67 = io_deq_ready & io_deq_valid;
assign do_deq = T_67;
assign T_77 = do_enq != do_deq;
assign GEN_8 = T_77 ? do_enq : maybe_full;
assign T_79 = T_65 == 1'h0;
assign GEN_9 = io_deq_ready ? 1'h1 : T_65;
assign T_90 = 1'h0 - 1'h0;
assign ptr_diff = T_90[0:0];
assign T_92 = {maybe_full,ptr_diff};
always @(posedge clock) begin// The ram block does not need reset
if(ram_read_T_69_en & ram_read_T_69_mask) begin
ram_read[ram_read_T_69_addr] <= ram_read_T_69_data;
end
if(ram_index_T_69_en & ram_index_T_69_mask) begin
ram_index[ram_index_T_69_addr] <= ram_index_T_69_data;
end
if(ram_data_T_69_en & ram_data_T_69_mask) begin
ram_data[ram_data_T_69_addr] <= ram_data_T_69_data;
end
if(ram_mask_T_69_en & ram_mask_T_69_mask) begin
ram_mask[ram_mask_T_69_addr] <= ram_mask_T_69_data;
end
if(ram_extra_T_69_en & ram_extra_T_69_mask) begin
ram_extra[ram_extra_T_69_addr] <= ram_extra_T_69_data;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
maybe_full <= 1'h0;
end else begin
if (T_77) begin
maybe_full <= do_enq;
end
end
end
endmodule |
module sirv_debug_rom(
input [7-1:2] rom_addr,
output [32-1:0] rom_dout
);
// These ROM contents support only RV32
// See $RISCV/riscv-tools/riscv-isa-sim/debug_rom/debug_rom.h/S
// The code assumes only 28 bytes of Debug RAM.
// def xlen32OnlyRomContents : Array[Byte] = Array(
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
wire [31:0] debug_rom [0:28]; // 29 words in total
assign rom_dout = debug_rom[rom_addr];
// 0x6f, 0x00, 0xc0, 0x03, 0x6f, 0x00, 0xc0, 0x00, 0x13, 0x04, 0xf0, 0xff,
assign debug_rom[ 0][7 : 0] = 8'h6f;
assign debug_rom[ 0][15: 8] = 8'h00;
assign debug_rom[ 0][23:16] = 8'hc0;
assign debug_rom[ 0][31:24] = 8'h03;
assign debug_rom[ 1][7 : 0] = 8'h6f;
assign debug_rom[ 1][15: 8] = 8'h00;
assign debug_rom[ 1][23:16] = 8'hc0;
assign debug_rom[ 1][31:24] = 8'h00;
assign debug_rom[ 2][7 : 0] = 8'h13;
assign debug_rom[ 2][15: 8] = 8'h04;
assign debug_rom[ 2][23:16] = 8'hf0;
assign debug_rom[ 2][31:24] = 8'hff;
// 0x6f, 0x00, 0x80, 0x00, 0x13, 0x04, 0x00, 0x00, 0x0f, 0x00, 0xf0, 0x0f,
assign debug_rom[ 3][7 : 0] = 8'h6f;
assign debug_rom[ 3][15: 8] = 8'h00;
assign debug_rom[ 3][23:16] = 8'h80;
assign debug_rom[ 3][31:24] = 8'h00;
assign debug_rom[ 4][7 : 0] = 8'h13;
assign debug_rom[ 4][15: 8] = 8'h04;
assign debug_rom[ 4][23:16] = 8'h00;
assign debug_rom[ 4][31:24] = 8'h00;
assign debug_rom[ 5][7 : 0] = 8'h0f;
assign debug_rom[ 5][15: 8] = 8'h00;
assign debug_rom[ 5][23:16] = 8'hf0;
assign debug_rom[ 5][31:24] = 8'h0f;
// 0x83, 0x24, 0x80, 0x41, 0x23, 0x2c, 0x80, 0x40, 0x73, 0x24, 0x40, 0xf1,
assign debug_rom[ 6][7 : 0] = 8'h83;
assign debug_rom[ 6][15: 8] = 8'h24;
assign debug_rom[ 6][23:16] = 8'h80;
assign debug_rom[ 6][31:24] = 8'h41;
assign debug_rom[ 7][7 : 0] = 8'h23;
assign debug_rom[ 7][15: 8] = 8'h2c;
assign debug_rom[ 7][23:16] = 8'h80;
assign debug_rom[ 7][31:24] = 8'h40;
assign debug_rom[ 8][7 : 0] = 8'h73;
assign debug_rom[ 8][15: 8] = 8'h24;
assign debug_rom[ 8][23:16] = 8'h40;
assign debug_rom[ 8][31:24] = 8'hf1;
// 0x23, 0x20, 0x80, 0x10, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x84, 0x00,
assign debug_rom[ 9][7 : 0] = 8'h23;
assign debug_rom[ 9][15: 8] = 8'h20;
assign debug_rom[ 9][23:16] = 8'h80;
assign debug_rom[ 9][31:24] = 8'h10;
assign debug_rom[10][7 : 0] = 8'h73;
assign debug_rom[10][15: 8] = 8'h24;
assign debug_rom[10][23:16] = 8'h00;
assign debug_rom[10][31:24] = 8'h7b;
assign debug_rom[11][7 : 0] = 8'h13;
assign debug_rom[11][15: 8] = 8'h74;
assign debug_rom[11][23:16] = 8'h84;
assign debug_rom[11][31:24] = 8'h00;
// 0x63, 0x1a, 0x04, 0x02, 0x73, 0x24, 0x20, 0x7b, 0x73, 0x00, 0x20, 0x7b,
assign debug_rom[12][7 : 0] = 8'h63;
assign debug_rom[12][15: 8] = 8'h1a;
assign debug_rom[12][23:16] = 8'h04;
assign debug_rom[12][31:24] = 8'h02;
assign debug_rom[13][7 : 0] = 8'h73;
assign debug_rom[13][15: 8] = 8'h24;
assign debug_rom[13][23:16] = 8'h20;
assign debug_rom[13][31:24] = 8'h7b;
assign debug_rom[14][7 : 0] = 8'h73;
assign debug_rom[14][15: 8] = 8'h00;
assign debug_rom[14][23:16] = 8'h20;
assign debug_rom[14][31:24] = 8'h7b;
// 0x73, 0x10, 0x24, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x1c,
assign debug_rom[15][7 : 0] = 8'h73;
assign debug_rom[15][15: 8] = 8'h10;
assign debug_rom[15][23:16] = 8'h24;
assign debug_rom[15][31:24] = 8'h7b;
assign debug_rom[16][7 : 0] = 8'h73;
assign debug_rom[16][15: 8] = 8'h24;
assign debug_rom[16][23:16] = 8'h00;
assign debug_rom[16][31:24] = 8'h7b;
assign debug_rom[17][7 : 0] = 8'h13;
assign debug_rom[17][15: 8] = 8'h74;
assign debug_rom[17][23:16] = 8'h04;
assign debug_rom[17][31:24] = 8'h1c;
// 0x13, 0x04, 0x04, 0xf4, 0x63, 0x16, 0x04, 0x00, 0x23, 0x2c, 0x90, 0x40,
assign debug_rom[18][7 : 0] = 8'h13;
assign debug_rom[18][15: 8] = 8'h04;
assign debug_rom[18][23:16] = 8'h04;
assign debug_rom[18][31:24] = 8'hf4;
assign debug_rom[19][7 : 0] = 8'h63;
assign debug_rom[19][15: 8] = 8'h16;
assign debug_rom[19][23:16] = 8'h04;
assign debug_rom[19][31:24] = 8'h00;
assign debug_rom[20][7 : 0] = 8'h23;
assign debug_rom[20][15: 8] = 8'h2c;
assign debug_rom[20][23:16] = 8'h90;
assign debug_rom[20][31:24] = 8'h40;
// 0x67, 0x00, 0x00, 0x40, 0x73, 0x24, 0x40, 0xf1, 0x23, 0x26, 0x80, 0x10,
assign debug_rom[21][7 : 0] = 8'h67;
assign debug_rom[21][15: 8] = 8'h00;
assign debug_rom[21][23:16] = 8'h00;
assign debug_rom[21][31:24] = 8'h40;
assign debug_rom[22][7 : 0] = 8'h73;
assign debug_rom[22][15: 8] = 8'h24;
assign debug_rom[22][23:16] = 8'h40;
assign debug_rom[22][31:24] = 8'hf1;
assign debug_rom[23][7 : 0] = 8'h23;
assign debug_rom[23][15: 8] = 8'h26;
assign debug_rom[23][23:16] = 8'h80;
assign debug_rom[23][31:24] = 8'h10;
// 0x73, 0x60, 0x04, 0x7b, 0x73, 0x24, 0x00, 0x7b, 0x13, 0x74, 0x04, 0x02,
assign debug_rom[24][7 : 0] = 8'h73;
assign debug_rom[24][15: 8] = 8'h60;
assign debug_rom[24][23:16] = 8'h04;
assign debug_rom[24][31:24] = 8'h7b;
assign debug_rom[25][7 : 0] = 8'h73;
assign debug_rom[25][15: 8] = 8'h24;
assign debug_rom[25][23:16] = 8'h00;
assign debug_rom[25][31:24] = 8'h7b;
assign debug_rom[26][7 : 0] = 8'h13;
assign debug_rom[26][15: 8] = 8'h74;
assign debug_rom[26][23:16] = 8'h04;
assign debug_rom[26][31:24] = 8'h02;
// 0xe3, 0x0c, 0x04, 0xfe, 0x6f, 0xf0, 0x1f, 0xfe).map(_.toByte)
assign debug_rom[27][7 : 0] = 8'he3;
assign debug_rom[27][15: 8] = 8'h0c;
assign debug_rom[27][23:16] = 8'h04;
assign debug_rom[27][31:24] = 8'hfe;
assign debug_rom[28][7 : 0] = 8'h6f;
assign debug_rom[28][15: 8] = 8'hf0;
assign debug_rom[28][23:16] = 8'h1f;
assign debug_rom[28][31:24] = 8'hfe;
endmodule |
module sirv_qspi_media(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [7:0] io_ctrl_dla_cssck,
input [7:0] io_ctrl_dla_sckcs,
input [7:0] io_ctrl_dla_intercs,
input [7:0] io_ctrl_dla_interxfr,
input io_ctrl_cs_id,
input io_ctrl_cs_dflt_0,
output io_link_tx_ready,
input io_link_tx_valid,
input [7:0] io_link_tx_bits,
output io_link_rx_valid,
output [7:0] io_link_rx_bits,
input [7:0] io_link_cnt,
input [1:0] io_link_fmt_proto,
input io_link_fmt_endian,
input io_link_fmt_iodir,
input io_link_cs_set,
input io_link_cs_clear,
input io_link_cs_hold,
output io_link_active
);
wire phy_clock;
wire phy_reset;
wire phy_io_port_sck;
wire phy_io_port_dq_0_i;
wire phy_io_port_dq_0_o;
wire phy_io_port_dq_0_oe;
wire phy_io_port_dq_1_i;
wire phy_io_port_dq_1_o;
wire phy_io_port_dq_1_oe;
wire phy_io_port_dq_2_i;
wire phy_io_port_dq_2_o;
wire phy_io_port_dq_2_oe;
wire phy_io_port_dq_3_i;
wire phy_io_port_dq_3_o;
wire phy_io_port_dq_3_oe;
wire phy_io_port_cs_0;
wire [11:0] phy_io_ctrl_sck_div;
wire phy_io_ctrl_sck_pol;
wire phy_io_ctrl_sck_pha;
wire [1:0] phy_io_ctrl_fmt_proto;
wire phy_io_ctrl_fmt_endian;
wire phy_io_ctrl_fmt_iodir;
wire phy_io_op_ready;
wire phy_io_op_valid;
wire phy_io_op_bits_fn;
wire phy_io_op_bits_stb;
wire [7:0] phy_io_op_bits_cnt;
wire [7:0] phy_io_op_bits_data;
wire phy_io_rx_valid;
wire [7:0] phy_io_rx_bits;
reg cs_id;
reg [31:0] GEN_5;
reg cs_dflt_0;
reg [31:0] GEN_52;
reg cs_set;
reg [31:0] GEN_53;
wire [1:0] GEN_48;
wire [1:0] T_162;
wire [1:0] GEN_49;
wire [1:0] T_163;
wire T_164;
wire cs_active_0;
wire cs_update;
reg clear;
reg [31:0] GEN_54;
reg cs_assert;
reg [31:0] GEN_55;
wire T_175;
wire T_176;
wire cs_deassert;
wire T_177;
wire T_178;
wire continuous;
reg [1:0] state;
reg [31:0] GEN_56;
wire T_182;
wire [1:0] GEN_0;
wire [7:0] GEN_1;
wire [1:0] GEN_2;
wire T_184;
wire T_186;
wire [1:0] GEN_3;
wire GEN_4;
wire GEN_6;
wire GEN_7;
wire [1:0] GEN_8;
wire [7:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire T_188;
wire T_189;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire [7:0] GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire T_194;
wire T_195;
wire [7:0] GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire [7:0] GEN_26;
wire [1:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire T_198;
wire T_200;
wire T_201;
wire [1:0] GEN_36;
wire GEN_37;
wire [7:0] GEN_38;
wire [1:0] GEN_39;
wire T_202;
wire [1:0] GEN_50;
wire [1:0] T_206;
wire [1:0] GEN_51;
wire [1:0] T_207;
wire T_208;
wire T_213_0;
wire GEN_40;
wire [1:0] GEN_41;
wire [7:0] GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_46;
wire [1:0] GEN_47;
sirv_qspi_physical phy (
.clock(phy_clock),
.reset(phy_reset),
.io_port_sck(phy_io_port_sck),
.io_port_dq_0_i(phy_io_port_dq_0_i),
.io_port_dq_0_o(phy_io_port_dq_0_o),
.io_port_dq_0_oe(phy_io_port_dq_0_oe),
.io_port_dq_1_i(phy_io_port_dq_1_i),
.io_port_dq_1_o(phy_io_port_dq_1_o),
.io_port_dq_1_oe(phy_io_port_dq_1_oe),
.io_port_dq_2_i(phy_io_port_dq_2_i),
.io_port_dq_2_o(phy_io_port_dq_2_o),
.io_port_dq_2_oe(phy_io_port_dq_2_oe),
.io_port_dq_3_i(phy_io_port_dq_3_i),
.io_port_dq_3_o(phy_io_port_dq_3_o),
.io_port_dq_3_oe(phy_io_port_dq_3_oe),
.io_port_cs_0(phy_io_port_cs_0),
.io_ctrl_sck_div(phy_io_ctrl_sck_div),
.io_ctrl_sck_pol(phy_io_ctrl_sck_pol),
.io_ctrl_sck_pha(phy_io_ctrl_sck_pha),
.io_ctrl_fmt_proto(phy_io_ctrl_fmt_proto),
.io_ctrl_fmt_endian(phy_io_ctrl_fmt_endian),
.io_ctrl_fmt_iodir(phy_io_ctrl_fmt_iodir),
.io_op_ready(phy_io_op_ready),
.io_op_valid(phy_io_op_valid),
.io_op_bits_fn(phy_io_op_bits_fn),
.io_op_bits_stb(phy_io_op_bits_stb),
.io_op_bits_cnt(phy_io_op_bits_cnt),
.io_op_bits_data(phy_io_op_bits_data),
.io_rx_valid(phy_io_rx_valid),
.io_rx_bits(phy_io_rx_bits)
);
assign io_port_sck = phy_io_port_sck;
assign io_port_dq_0_o = phy_io_port_dq_0_o;
assign io_port_dq_0_oe = phy_io_port_dq_0_oe;
assign io_port_dq_1_o = phy_io_port_dq_1_o;
assign io_port_dq_1_oe = phy_io_port_dq_1_oe;
assign io_port_dq_2_o = phy_io_port_dq_2_o;
assign io_port_dq_2_oe = phy_io_port_dq_2_oe;
assign io_port_dq_3_o = phy_io_port_dq_3_o;
assign io_port_dq_3_oe = phy_io_port_dq_3_oe;
assign io_port_cs_0 = cs_dflt_0;
assign io_link_tx_ready = GEN_31;
assign io_link_rx_valid = phy_io_rx_valid;
assign io_link_rx_bits = phy_io_rx_bits;
assign io_link_active = cs_assert;
assign phy_clock = clock;
assign phy_reset = reset;
assign phy_io_port_dq_0_i = io_port_dq_0_i;
assign phy_io_port_dq_1_i = io_port_dq_1_i;
assign phy_io_port_dq_2_i = io_port_dq_2_i;
assign phy_io_port_dq_3_i = io_port_dq_3_i;
assign phy_io_ctrl_sck_div = io_ctrl_sck_div;
assign phy_io_ctrl_sck_pol = io_ctrl_sck_pol;
assign phy_io_ctrl_sck_pha = io_ctrl_sck_pha;
assign phy_io_ctrl_fmt_proto = io_link_fmt_proto;
assign phy_io_ctrl_fmt_endian = io_link_fmt_endian;
assign phy_io_ctrl_fmt_iodir = io_link_fmt_iodir;
assign phy_io_op_valid = GEN_37;
assign phy_io_op_bits_fn = GEN_28;
assign phy_io_op_bits_stb = GEN_43;
assign phy_io_op_bits_cnt = GEN_42;
assign phy_io_op_bits_data = io_link_tx_bits;
assign GEN_48 = {{1'd0}, io_link_cs_set};
assign T_162 = GEN_48 << io_ctrl_cs_id;
assign GEN_49 = {{1'd0}, io_ctrl_cs_dflt_0};
assign T_163 = GEN_49 ^ T_162;
assign T_164 = T_163[0];
assign cs_active_0 = T_164;
assign cs_update = cs_active_0 != cs_dflt_0;
assign T_175 = io_link_cs_hold == 1'h0;
assign T_176 = cs_update & T_175;
assign cs_deassert = clear | T_176;
assign T_177 = io_link_cs_clear & cs_assert;
assign T_178 = clear | T_177;
assign continuous = io_ctrl_dla_interxfr == 8'h0;
assign T_182 = 2'h0 == state;
assign GEN_0 = phy_io_op_ready ? 2'h2 : state;
assign GEN_1 = cs_deassert ? io_ctrl_dla_sckcs : io_link_cnt;
assign GEN_2 = cs_deassert ? GEN_0 : state;
assign T_184 = cs_deassert == 1'h0;
assign T_186 = phy_io_op_ready & phy_io_op_valid;
assign GEN_3 = T_186 ? 2'h1 : GEN_2;
assign GEN_4 = T_184 ? 1'h0 : 1'h1;
assign GEN_6 = T_184 ? io_link_tx_valid : 1'h1;
assign GEN_7 = T_184 ? phy_io_op_ready : 1'h0;
assign GEN_8 = T_184 ? GEN_3 : GEN_2;
assign GEN_9 = cs_assert ? GEN_1 : io_link_cnt;
assign GEN_10 = cs_assert ? GEN_8 : state;
assign GEN_11 = cs_assert ? GEN_4 : 1'h1;
assign GEN_12 = cs_assert ? T_184 : 1'h0;
assign GEN_13 = cs_assert ? GEN_6 : 1'h1;
assign GEN_14 = cs_assert ? GEN_7 : 1'h0;
assign T_188 = cs_assert == 1'h0;
assign T_189 = T_188 & io_link_tx_valid;
assign GEN_15 = phy_io_op_ready ? 1'h1 : cs_assert;
assign GEN_16 = phy_io_op_ready ? io_link_cs_set : cs_set;
assign GEN_17 = phy_io_op_ready ? cs_active_0 : cs_dflt_0;
assign GEN_18 = T_189 ? io_ctrl_dla_cssck : GEN_9;
assign GEN_19 = T_189 ? GEN_15 : cs_assert;
assign GEN_20 = T_189 ? GEN_16 : cs_set;
assign GEN_21 = T_189 ? GEN_17 : cs_dflt_0;
assign T_194 = io_link_tx_valid == 1'h0;
assign T_195 = T_188 & T_194;
assign GEN_22 = T_195 ? 8'h0 : GEN_18;
assign GEN_23 = T_195 ? 1'h1 : GEN_12;
assign GEN_24 = T_195 ? io_ctrl_cs_id : cs_id;
assign GEN_25 = T_195 ? io_ctrl_cs_dflt_0 : GEN_21;
assign GEN_26 = T_182 ? GEN_22 : io_link_cnt;
assign GEN_27 = T_182 ? GEN_10 : state;
assign GEN_28 = T_182 ? GEN_11 : 1'h1;
assign GEN_29 = T_182 ? GEN_23 : 1'h0;
assign GEN_30 = T_182 ? GEN_13 : 1'h1;
assign GEN_31 = T_182 ? GEN_14 : 1'h0;
assign GEN_32 = T_182 ? GEN_19 : cs_assert;
assign GEN_33 = T_182 ? GEN_20 : cs_set;
assign GEN_34 = T_182 ? GEN_25 : cs_dflt_0;
assign GEN_35 = T_182 ? GEN_24 : cs_id;
assign T_198 = 2'h1 == state;
assign T_200 = continuous == 1'h0;
assign T_201 = phy_io_op_ready | continuous;
assign GEN_36 = T_201 ? 2'h0 : GEN_27;
assign GEN_37 = T_198 ? T_200 : GEN_30;
assign GEN_38 = T_198 ? io_ctrl_dla_interxfr : GEN_26;
assign GEN_39 = T_198 ? GEN_36 : GEN_27;
assign T_202 = 2'h2 == state;
assign GEN_50 = {{1'd0}, cs_set};
assign T_206 = GEN_50 << cs_id;
assign GEN_51 = {{1'd0}, cs_dflt_0};
assign T_207 = GEN_51 ^ T_206;
assign T_208 = T_207[0];
assign T_213_0 = T_208;
assign GEN_40 = phy_io_op_ready ? T_213_0 : GEN_34;
assign GEN_41 = phy_io_op_ready ? 2'h0 : GEN_39;
assign GEN_42 = T_202 ? io_ctrl_dla_intercs : GEN_38;
assign GEN_43 = T_202 ? 1'h1 : GEN_29;
assign GEN_44 = T_202 ? 1'h0 : GEN_32;
assign GEN_45 = T_202 ? 1'h0 : T_178;
assign GEN_46 = T_202 ? GEN_40 : GEN_34;
assign GEN_47 = T_202 ? GEN_41 : GEN_39;
always @(posedge clock or posedge reset)
if(reset) begin
cs_id <= 2'b0;
cs_dflt_0 <= 1'b1;
cs_set <= 1'b0;
end
else begin//{
if (T_182) begin
if (T_195) begin
cs_id <= io_ctrl_cs_id;
end
end
if (T_202) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= T_213_0;
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
end else begin
if (T_182) begin
if (T_195) begin
cs_dflt_0 <= io_ctrl_cs_dflt_0;
end else begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_dflt_0 <= cs_active_0;
end
end
end
end
end
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_set <= io_link_cs_set;
end
end
end
end//}
always @(posedge clock or posedge reset)
if (reset) begin
clear <= 1'h0;
end else begin
if (T_202) begin
clear <= 1'h0;
end else begin
clear <= T_178;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_assert <= 1'h0;
end else begin
if (T_202) begin
cs_assert <= 1'h0;
end else begin
if (T_182) begin
if (T_189) begin
if (phy_io_op_ready) begin
cs_assert <= 1'h1;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_202) begin
if (phy_io_op_ready) begin
state <= 2'h0;
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end else begin
if (cs_deassert) begin
if (phy_io_op_ready) begin
state <= 2'h2;
end
end
end
end
end
end
end
end else begin
if (T_198) begin
if (T_201) begin
state <= 2'h0;
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end else begin
if (T_182) begin
if (cs_assert) begin
if (T_184) begin
if (T_186) begin
state <= 2'h1;
end else begin
state <= GEN_2;
end
end else begin
state <= GEN_2;
end
end
end
end
end
end
endmodule |
module sirv_jtaggpioport(
input clock,
input reset,
output io_jtag_TCK,
output io_jtag_TMS,
output io_jtag_TDI,
input io_jtag_TDO,
output io_jtag_TRST,
input io_jtag_DRV_TDO,
input io_pins_TCK_i_ival,
output io_pins_TCK_o_oval,
output io_pins_TCK_o_oe,
output io_pins_TCK_o_ie,
output io_pins_TCK_o_pue,
output io_pins_TCK_o_ds,
input io_pins_TMS_i_ival,
output io_pins_TMS_o_oval,
output io_pins_TMS_o_oe,
output io_pins_TMS_o_ie,
output io_pins_TMS_o_pue,
output io_pins_TMS_o_ds,
input io_pins_TDI_i_ival,
output io_pins_TDI_o_oval,
output io_pins_TDI_o_oe,
output io_pins_TDI_o_ie,
output io_pins_TDI_o_pue,
output io_pins_TDI_o_ds,
input io_pins_TDO_i_ival,
output io_pins_TDO_o_oval,
output io_pins_TDO_o_oe,
output io_pins_TDO_o_ie,
output io_pins_TDO_o_pue,
output io_pins_TDO_o_ds,
input io_pins_TRST_n_i_ival,
output io_pins_TRST_n_o_oval,
output io_pins_TRST_n_o_oe,
output io_pins_TRST_n_o_ie,
output io_pins_TRST_n_o_pue,
output io_pins_TRST_n_o_ds
);
wire T_101;
wire T_117;
assign io_jtag_TCK = T_101;
assign io_jtag_TMS = io_pins_TMS_i_ival;
assign io_jtag_TDI = io_pins_TDI_i_ival;
assign io_jtag_TRST = T_117;
assign io_pins_TCK_o_oval = 1'h0;
assign io_pins_TCK_o_oe = 1'h0;
assign io_pins_TCK_o_ie = 1'h1;
assign io_pins_TCK_o_pue = 1'h1;
assign io_pins_TCK_o_ds = 1'h0;
assign io_pins_TMS_o_oval = 1'h0;
assign io_pins_TMS_o_oe = 1'h0;
assign io_pins_TMS_o_ie = 1'h1;
assign io_pins_TMS_o_pue = 1'h1;
assign io_pins_TMS_o_ds = 1'h0;
assign io_pins_TDI_o_oval = 1'h0;
assign io_pins_TDI_o_oe = 1'h0;
assign io_pins_TDI_o_ie = 1'h1;
assign io_pins_TDI_o_pue = 1'h1;
assign io_pins_TDI_o_ds = 1'h0;
assign io_pins_TDO_o_oval = io_jtag_TDO;
assign io_pins_TDO_o_oe = io_jtag_DRV_TDO;
assign io_pins_TDO_o_ie = 1'h0;
assign io_pins_TDO_o_pue = 1'h0;
assign io_pins_TDO_o_ds = 1'h0;
assign io_pins_TRST_n_o_oval = 1'h0;
assign io_pins_TRST_n_o_oe = 1'h0;
assign io_pins_TRST_n_o_ie = 1'h1;
assign io_pins_TRST_n_o_pue = 1'h1;
assign io_pins_TRST_n_o_ds = 1'h0;
assign T_101 = $unsigned(io_pins_TCK_i_ival);
assign T_117 = ~ io_pins_TRST_n_i_ival;
endmodule |
module sirv_debug_module
# (
parameter SUPPORT_JTAG_DTM = 1,
parameter ASYNC_FF_LEVELS = 2,
parameter PC_SIZE = 32,
parameter HART_NUM = 1,
parameter HART_ID_W = 1
) (
output inspect_jtag_clk,
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
// The system memory bus interface
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [12-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_pads_jtag_TCK_i_ival,
output io_pads_jtag_TCK_o_oval,
output io_pads_jtag_TCK_o_oe,
output io_pads_jtag_TCK_o_ie,
output io_pads_jtag_TCK_o_pue,
output io_pads_jtag_TCK_o_ds,
input io_pads_jtag_TMS_i_ival,
output io_pads_jtag_TMS_o_oval,
output io_pads_jtag_TMS_o_oe,
output io_pads_jtag_TMS_o_ie,
output io_pads_jtag_TMS_o_pue,
output io_pads_jtag_TMS_o_ds,
input io_pads_jtag_TDI_i_ival,
output io_pads_jtag_TDI_o_oval,
output io_pads_jtag_TDI_o_oe,
output io_pads_jtag_TDI_o_ie,
output io_pads_jtag_TDI_o_pue,
output io_pads_jtag_TDI_o_ds,
input io_pads_jtag_TDO_i_ival,
output io_pads_jtag_TDO_o_oval,
output io_pads_jtag_TDO_o_oe,
output io_pads_jtag_TDO_o_ie,
output io_pads_jtag_TDO_o_pue,
output io_pads_jtag_TDO_o_ds,
input io_pads_jtag_TRST_n_i_ival,
output io_pads_jtag_TRST_n_o_oval,
output io_pads_jtag_TRST_n_o_oe,
output io_pads_jtag_TRST_n_o_ie,
output io_pads_jtag_TRST_n_o_pue,
output io_pads_jtag_TRST_n_o_ds,
// To the target hart
output [HART_NUM-1:0] o_dbg_irq,
output [HART_NUM-1:0] o_ndreset,
output [HART_NUM-1:0] o_fullreset,
input core_csr_clk,
input hfclk,
input corerst,
input test_mode
);
wire dm_rst;
wire dm_rst_n;
//This is to reset Debug module's logic, the debug module have same clock domain
// as the main domain, so just use the same reset.
sirv_ResetCatchAndSync_2 u_dm_ResetCatchAndSync_2_1 (
.test_mode(test_mode),
.clock(hfclk),// Use same clock as main domain
.reset(corerst),
.io_sync_reset(dm_rst)
);
assign dm_rst_n = ~dm_rst;
//This is to reset the JTAG_CLK relevant logics, since the chip does not
// have the JTAG_RST used really, so we need to use the global chip reset to reset
// JTAG relevant logics
wire jtag_TCK;
wire jtag_reset;
sirv_ResetCatchAndSync u_jtag_ResetCatchAndSync_3_1 (
.test_mode(test_mode),
.clock(jtag_TCK),
.reset(corerst),
.io_sync_reset(jtag_reset)
);
wire dm_clk = hfclk;// Currently Debug Module have same clock domain as core
wire jtag_TDI;
wire jtag_TDO;
wire jtag_TMS;
wire jtag_TRST;
wire jtag_DRV_TDO;
sirv_jtaggpioport u_jtag_pins (
.clock(1'b0),
.reset(1'b1),
.io_jtag_TCK(jtag_TCK),
.io_jtag_TMS(jtag_TMS),
.io_jtag_TDI(jtag_TDI),
.io_jtag_TDO(jtag_TDO),
.io_jtag_TRST(jtag_TRST),
.io_jtag_DRV_TDO(jtag_DRV_TDO),
.io_pins_TCK_i_ival(io_pads_jtag_TCK_i_ival),
.io_pins_TCK_o_oval(io_pads_jtag_TCK_o_oval),
.io_pins_TCK_o_oe(io_pads_jtag_TCK_o_oe),
.io_pins_TCK_o_ie(io_pads_jtag_TCK_o_ie),
.io_pins_TCK_o_pue(io_pads_jtag_TCK_o_pue),
.io_pins_TCK_o_ds(io_pads_jtag_TCK_o_ds),
.io_pins_TMS_i_ival(io_pads_jtag_TMS_i_ival),
.io_pins_TMS_o_oval(io_pads_jtag_TMS_o_oval),
.io_pins_TMS_o_oe(io_pads_jtag_TMS_o_oe),
.io_pins_TMS_o_ie(io_pads_jtag_TMS_o_ie),
.io_pins_TMS_o_pue(io_pads_jtag_TMS_o_pue),
.io_pins_TMS_o_ds(io_pads_jtag_TMS_o_ds),
.io_pins_TDI_i_ival(io_pads_jtag_TDI_i_ival),
.io_pins_TDI_o_oval(io_pads_jtag_TDI_o_oval),
.io_pins_TDI_o_oe(io_pads_jtag_TDI_o_oe),
.io_pins_TDI_o_ie(io_pads_jtag_TDI_o_ie),
.io_pins_TDI_o_pue(io_pads_jtag_TDI_o_pue),
.io_pins_TDI_o_ds(io_pads_jtag_TDI_o_ds),
.io_pins_TDO_i_ival(io_pads_jtag_TDO_i_ival),
.io_pins_TDO_o_oval(io_pads_jtag_TDO_o_oval),
.io_pins_TDO_o_oe(io_pads_jtag_TDO_o_oe),
.io_pins_TDO_o_ie(io_pads_jtag_TDO_o_ie),
.io_pins_TDO_o_pue(io_pads_jtag_TDO_o_pue),
.io_pins_TDO_o_ds(io_pads_jtag_TDO_o_ds),
.io_pins_TRST_n_i_ival(io_pads_jtag_TRST_n_i_ival),
.io_pins_TRST_n_o_oval(io_pads_jtag_TRST_n_o_oval),
.io_pins_TRST_n_o_oe(io_pads_jtag_TRST_n_o_oe),
.io_pins_TRST_n_o_ie(io_pads_jtag_TRST_n_o_ie),
.io_pins_TRST_n_o_pue(io_pads_jtag_TRST_n_o_pue),
.io_pins_TRST_n_o_ds(io_pads_jtag_TRST_n_o_ds)
);
sirv_debug_csr # (
.PC_SIZE(PC_SIZE)
) u_sirv_debug_csr (
.dbg_stopcycle (dbg_stopcycle ),
.dbg_irq_r (dbg_irq_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.clk (core_csr_clk),
.rst_n (dm_rst_n )
);
// The debug bus interface
wire dtm_req_valid;
wire dtm_req_ready;
wire [41-1 :0] dtm_req_bits;
wire dtm_resp_valid;
wire dtm_resp_ready;
wire [36-1 : 0] dtm_resp_bits;
generate
if(SUPPORT_JTAG_DTM == 1) begin: jtag_dtm_gen
sirv_jtag_dtm # (
.ASYNC_FF_LEVELS(ASYNC_FF_LEVELS)
) u_sirv_jtag_dtm (
.jtag_TDI (jtag_TDI ),
.jtag_TDO (jtag_TDO ),
.jtag_TCK (jtag_TCK ),
.jtag_TMS (jtag_TMS ),
.jtag_TRST (jtag_reset ),
.jtag_DRV_TDO (jtag_DRV_TDO ),
.dtm_req_valid (dtm_req_valid ),
.dtm_req_ready (dtm_req_ready ),
.dtm_req_bits (dtm_req_bits ),
.dtm_resp_valid (dtm_resp_valid),
.dtm_resp_ready (dtm_resp_ready),
.dtm_resp_bits (dtm_resp_bits )
);
end
else begin: no_jtag_dtm_gen
assign jtag_TDI = 1'b0;
assign jtag_TDO = 1'b0;
assign jtag_TCK = 1'b0;
assign jtag_TMS = 1'b0;
assign jtag_DRV_TDO = 1'b0;
assign dtm_req_valid = 1'b0;
assign dtm_req_bits = 41'b0;
assign dtm_resp_ready = 1'b0;
end
endgenerate
wire i_dtm_req_valid;
wire i_dtm_req_ready;
wire [41-1 :0] i_dtm_req_bits;
wire i_dtm_resp_valid;
wire i_dtm_resp_ready;
wire [36-1 : 0] i_dtm_resp_bits;
sirv_gnrl_cdc_tx
# (
.DW (36),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_dm2dtm_cdc_tx (
.o_vld (dtm_resp_valid),
.o_rdy_a(dtm_resp_ready),
.o_dat (dtm_resp_bits ),
.i_vld (i_dtm_resp_valid),
.i_rdy (i_dtm_resp_ready),
.i_dat (i_dtm_resp_bits ),
.clk (dm_clk),
.rst_n (dm_rst_n)
);
sirv_gnrl_cdc_rx
# (
.DW (41),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_dm2dtm_cdc_rx (
.i_vld_a(dtm_req_valid),
.i_rdy (dtm_req_ready),
.i_dat (dtm_req_bits ),
.o_vld (i_dtm_req_valid),
.o_rdy (i_dtm_req_ready),
.o_dat (i_dtm_req_bits ),
.clk (dm_clk),
.rst_n (dm_rst_n)
);
wire i_dtm_req_hsked = i_dtm_req_valid & i_dtm_req_ready;
wire [ 4:0] dtm_req_bits_addr;
wire [33:0] dtm_req_bits_data;
wire [ 1:0] dtm_req_bits_op;
wire [33:0] dtm_resp_bits_data;
wire [ 1:0] dtm_resp_bits_resp;
assign dtm_req_bits_addr = i_dtm_req_bits[40:36];
assign dtm_req_bits_data = i_dtm_req_bits[35:2];
assign dtm_req_bits_op = i_dtm_req_bits[1:0];
assign i_dtm_resp_bits = {dtm_resp_bits_data, dtm_resp_bits_resp};
// The OP field
// 0: Ignore data. (nop)
// 1: Read from address. (read)
// 2: Read from address. Then write data to address. (write)
// 3: Reserved.
wire dtm_req_rd = (dtm_req_bits_op == 2'd1);
wire dtm_req_wr = (dtm_req_bits_op == 2'd2);
wire dtm_req_sel_dbgram = (dtm_req_bits_addr[4:3] == 2'b0) & (~(dtm_req_bits_addr[2:0] == 3'b111));//0x00-0x06
wire dtm_req_sel_dmcontrl = (dtm_req_bits_addr == 5'h10);
wire dtm_req_sel_dminfo = (dtm_req_bits_addr == 5'h11);
wire dtm_req_sel_haltstat = (dtm_req_bits_addr == 5'h1C);
wire [33:0] dminfo_r;
wire [33:0] dmcontrol_r;
wire [HART_NUM-1:0] dm_haltnot_r;
wire [HART_NUM-1:0] dm_debint_r;
//In the future if it is multi-core, then we need to add the core ID, to support this
// text from the debug_spec_v0.11
// At the cost of more hardware, this can be resolved in two ways. If
// the bus knows an ID for the originator, then the Debug Module can refuse write
// accesses to originators that don't match the hart ID set in hartid of dmcontrol.
//
// The Resp field
// 0: The previous operation completed successfully.
// 1: Reserved.
// 2: The previous operation failed. The data scanned into dbus in this access
// will be ignored. This status is sticky and can be cleared by writing dbusreset in dtmcontrol.
// 3: The previous operation is still in progress. The data scanned into dbus
// in this access will be ignored.
wire [31:0] ram_dout;
assign dtm_resp_bits_data =
({34{dtm_req_sel_dbgram }} & {dmcontrol_r[33:32],ram_dout})
| ({34{dtm_req_sel_dmcontrl}} & dmcontrol_r)
| ({34{dtm_req_sel_dminfo }} & dminfo_r)
| ({34{dtm_req_sel_haltstat}} & {{34-HART_ID_W{1'b0}},dm_haltnot_r});
assign dtm_resp_bits_resp = 2'd0;
wire icb_access_dbgram_ena;
wire i_dtm_req_condi = dtm_req_sel_dbgram ? (~icb_access_dbgram_ena) : 1'b1;
assign i_dtm_req_ready = i_dtm_req_condi & i_dtm_resp_ready;
assign i_dtm_resp_valid = i_dtm_req_condi & i_dtm_req_valid;
// DMINFORdData_reserved0 = 2'h0;
// DMINFORdData_abussize = 7'h0;
// DMINFORdData_serialcount = 4'h0;
// DMINFORdData_access128 = 1'h0;
// DMINFORdData_access64 = 1'h0;
// DMINFORdData_access32 = 1'h0;
// DMINFORdData_access16 = 1'h0;
// DMINFORdData_accesss8 = 1'h0;
// DMINFORdData_dramsize = 6'h6;
// DMINFORdData_haltsum = 1'h0;
// DMINFORdData_reserved1 = 3'h0;
// DMINFORdData_authenticated = 1'h1;
// DMINFORdData_authbusy = 1'h0;
// DMINFORdData_authtype = 2'h0;
// DMINFORdData_version = 2'h1;
assign dminfo_r[33:16] = 18'b0;
assign dminfo_r[15:10] = 6'h6;
assign dminfo_r[9:6] = 4'b0;
assign dminfo_r[5] = 1'h1;
assign dminfo_r[4:2] = 3'b0;
assign dminfo_r[1:0] = 2'h1;
wire [HART_ID_W-1:0] dm_hartid_r;
wire [1:0] dm_debint_arr = {1'b0,dm_debint_r };
wire [1:0] dm_haltnot_arr = {1'b0,dm_haltnot_r};
assign dmcontrol_r[33] = dm_debint_arr [dm_hartid_r];
assign dmcontrol_r[32] = dm_haltnot_arr[dm_hartid_r];
assign dmcontrol_r[31:12] = 20'b0;
assign dmcontrol_r[11:2] = {{10-HART_ID_W{1'b0}},dm_hartid_r};
assign dmcontrol_r[1:0] = 2'b0;
wire dtm_wr_dmcontrol = dtm_req_sel_dmcontrl & dtm_req_wr;
wire dtm_wr_dbgram = dtm_req_sel_dbgram & dtm_req_wr;
wire dtm_wr_interrupt_ena = i_dtm_req_hsked & (dtm_wr_dmcontrol | dtm_wr_dbgram) & dtm_req_bits_data[33];//W1
wire dtm_wr_haltnot_ena = i_dtm_req_hsked & (dtm_wr_dmcontrol | dtm_wr_dbgram) & (~dtm_req_bits_data[32]);//W0
wire dtm_wr_hartid_ena = i_dtm_req_hsked & dtm_wr_dmcontrol;
wire dtm_wr_dbgram_ena = i_dtm_req_hsked & dtm_wr_dbgram;
wire dtm_access_dbgram_ena = i_dtm_req_hsked & dtm_req_sel_dbgram;
wire dm_hartid_ena = dtm_wr_hartid_ena;
wire [HART_ID_W-1:0] dm_hartid_nxt = dtm_req_bits_data[HART_ID_W+2-1:2];
sirv_gnrl_dfflr #(HART_ID_W) dm_hartid_dfflr (dm_hartid_ena, dm_hartid_nxt, dm_hartid_r, dm_clk, dm_rst_n);
//////////////////////////////////////////////////////////////
// Impelement the DM ICB system bus agent
// 0x100 - 0x2ff Debug Module registers described in Section 7.12.
// * Only two registers needed, others are not supported
// cleardebint, at 0x100
// sethaltnot, at 0x10c
// 0x400 - 0x4ff Up to 256 bytes of Debug RAM. Each unique address species 8 bits.
// * Since this is remapped to each core's ITCM, we dont handle it at this module
// 0x800 - 0x9ff Up to 512 bytes of Debug ROM.
//
//
wire i_icb_cmd_hsked = i_icb_cmd_valid & i_icb_cmd_ready;
wire icb_wr_ena = i_icb_cmd_hsked & (~i_icb_cmd_read);
wire icb_sel_cleardebint = (i_icb_cmd_addr == 12'h100);
wire icb_sel_sethaltnot = (i_icb_cmd_addr == 12'h10c);
wire icb_sel_dbgrom = (i_icb_cmd_addr[12-1:8] == 4'h8);
wire icb_sel_dbgram = (i_icb_cmd_addr[12-1:8] == 4'h4);
wire icb_wr_cleardebint_ena = icb_wr_ena & icb_sel_cleardebint;
wire icb_wr_sethaltnot_ena = icb_wr_ena & icb_sel_sethaltnot ;
assign icb_access_dbgram_ena = i_icb_cmd_hsked & icb_sel_dbgram;
wire cleardebint_ena = icb_wr_cleardebint_ena;
wire [HART_ID_W-1:0] cleardebint_r;
wire [HART_ID_W-1:0] cleardebint_nxt = i_icb_cmd_wdata[HART_ID_W-1:0];
sirv_gnrl_dfflr #(HART_ID_W) cleardebint_dfflr (cleardebint_ena, cleardebint_nxt, cleardebint_r, dm_clk, dm_rst_n);
wire sethaltnot_ena = icb_wr_sethaltnot_ena;
wire [HART_ID_W-1:0] sethaltnot_r;
wire [HART_ID_W-1:0] sethaltnot_nxt = i_icb_cmd_wdata[HART_ID_W-1:0];
sirv_gnrl_dfflr #(HART_ID_W) sethaltnot_dfflr (sethaltnot_ena, sethaltnot_nxt, sethaltnot_r, dm_clk, dm_rst_n);
assign i_icb_rsp_valid = i_icb_cmd_valid;// Just directly pass back the valid in 0 cycle
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire [31:0] rom_dout;
assign i_icb_rsp_rdata =
({32{icb_sel_cleardebint}} & {{32-HART_ID_W{1'b0}}, cleardebint_r})
| ({32{icb_sel_sethaltnot }} & {{32-HART_ID_W{1'b0}}, sethaltnot_r})
| ({32{icb_sel_dbgrom }} & rom_dout)
| ({32{icb_sel_dbgram }} & ram_dout);
sirv_debug_rom u_sirv_debug_rom (
.rom_addr (i_icb_cmd_addr[7-1:2]),
.rom_dout (rom_dout)
);
//sirv_debug_rom_64 u_sirv_debug_rom_64(
// .rom_addr (i_icb_cmd_addr[8-1:2]),
// .rom_dout (rom_dout)
//);
wire ram_cs = dtm_access_dbgram_ena | icb_access_dbgram_ena;
wire [3-1:0] ram_addr = dtm_access_dbgram_ena ? dtm_req_bits_addr[2:0] : i_icb_cmd_addr[4:2];
wire ram_rd = dtm_access_dbgram_ena ? dtm_req_rd : i_icb_cmd_read;
wire [32-1:0]ram_wdat = dtm_access_dbgram_ena ? dtm_req_bits_data[31:0]: i_icb_cmd_wdata;
sirv_debug_ram u_sirv_debug_ram(
.clk (dm_clk),
.rst_n (dm_rst_n),
.ram_cs (ram_cs),
.ram_rd (ram_rd),
.ram_addr (ram_addr),
.ram_wdat (ram_wdat),
.ram_dout (ram_dout)
);
wire [HART_NUM-1:0] dm_haltnot_set;
wire [HART_NUM-1:0] dm_haltnot_clr;
wire [HART_NUM-1:0] dm_haltnot_ena;
wire [HART_NUM-1:0] dm_haltnot_nxt;
wire [HART_NUM-1:0] dm_debint_set;
wire [HART_NUM-1:0] dm_debint_clr;
wire [HART_NUM-1:0] dm_debint_ena;
wire [HART_NUM-1:0] dm_debint_nxt;
genvar i;
generate
for(i = 0; i < HART_NUM; i = i+1)//{
begin:dm_halt_int_gen
// The haltnot will be set by system bus set its ID to sethaltnot_r
assign dm_haltnot_set[i] = icb_wr_sethaltnot_ena & (i_icb_cmd_wdata[HART_ID_W-1:0] == i[HART_ID_W-1:0]);
// The haltnot will be cleared by DTM write 0 to haltnot
assign dm_haltnot_clr[i] = dtm_wr_haltnot_ena & (dm_hartid_r == i[HART_ID_W-1:0]);
assign dm_haltnot_ena[i] = dm_haltnot_set[i] | dm_haltnot_clr[i];
assign dm_haltnot_nxt[i] = dm_haltnot_set[i] | (~dm_haltnot_clr[i]);
sirv_gnrl_dfflr #(1) dm_haltnot_dfflr (dm_haltnot_ena[i], dm_haltnot_nxt[i], dm_haltnot_r[i], dm_clk, dm_rst_n);
// The debug intr will be set by DTM write 1 to interrupt
assign dm_debint_set[i] = dtm_wr_interrupt_ena & (dm_hartid_r == i[HART_ID_W-1:0]);
// The debug intr will be clear by system bus set its ID to cleardebint_r
assign dm_debint_clr[i] = icb_wr_cleardebint_ena & (i_icb_cmd_wdata[HART_ID_W-1:0] == i[HART_ID_W-1:0]);
assign dm_debint_ena[i] = dm_debint_set[i] | dm_debint_clr[i];
assign dm_debint_nxt[i] = dm_debint_set[i] | (~dm_debint_clr[i]);
sirv_gnrl_dfflr #(1) dm_debint_dfflr ( dm_debint_ena[i], dm_debint_nxt[i], dm_debint_r[i], dm_clk, dm_rst_n);
end//}
endgenerate
assign o_dbg_irq = dm_debint_r;
assign o_ndreset = {HART_NUM{1'b0}};
assign o_fullreset = {HART_NUM{1'b0}};
assign inspect_jtag_clk = jtag_TCK;
endmodule |
module sirv_AsyncResetReg (
input d,
output reg q,
input en,
input clk,
input rst);
always @(posedge clk or posedge rst) begin
if (rst) begin
q <= 1'b0;
end else if (en) begin
q <= d;
end
end
endmodule // AsyncResetReg |
module sirv_pmu_core(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_valid,
output io_control_bits_hfclkrst,
output io_control_bits_corerst,
output io_control_bits_reserved1,
output io_control_bits_vddpaden,
output io_control_bits_reserved0,
input [1:0] io_resetCause,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read
);
reg wantSleep;
reg run;
reg [31:0] GEN_37;
reg awake;
reg [31:0] GEN_38;
wire T_364;
wire T_365;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
wire T_371;
wire T_372;
wire T_373;
wire T_374;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire T_380;
wire T_381;
wire T_383;
wire T_385;
wire T_386;
wire T_388;
reg unlocked;
reg [31:0] GEN_39;
wire GEN_0;
wire T_391;
reg [31:0] GEN_40;
wire GEN_1;
reg [2:0] pc;
reg [31:0] GEN_41;
reg [1:0] wakeupCause;
reg [31:0] GEN_42;
wire T_394;
reg [3:0] T_396;
reg [31:0] GEN_43;
wire [3:0] GEN_2;
wire [3:0] ie;
reg [8:0] wakeupProgram_0;
reg [31:0] GEN_44;
reg [8:0] wakeupProgram_1;
reg [31:0] GEN_45;
reg [8:0] wakeupProgram_2;
reg [31:0] GEN_46;
reg [8:0] wakeupProgram_3;
reg [31:0] GEN_47;
reg [8:0] wakeupProgram_4;
reg [31:0] GEN_48;
reg [8:0] wakeupProgram_5;
reg [31:0] GEN_49;
reg [8:0] wakeupProgram_6;
reg [31:0] GEN_50;
reg [8:0] wakeupProgram_7;
reg [31:0] GEN_51;
reg [8:0] sleepProgram_0;
reg [31:0] GEN_52;
reg [8:0] sleepProgram_1;
reg [31:0] GEN_53;
reg [8:0] sleepProgram_2;
reg [31:0] GEN_54;
reg [8:0] sleepProgram_3;
reg [31:0] GEN_55;
reg [8:0] sleepProgram_4;
reg [31:0] GEN_56;
reg [8:0] sleepProgram_5;
reg [31:0] GEN_57;
reg [8:0] sleepProgram_6;
reg [31:0] GEN_58;
reg [8:0] sleepProgram_7;
reg [31:0] GEN_59;
wire [2:0] T_423;
wire T_425;
wire [2:0] T_427;
wire T_429;
wire T_433;
wire [8:0] T_434;
wire [8:0] T_439;
wire [8:0] T_440;
wire [8:0] T_449;
wire [8:0] T_454;
wire [8:0] T_455;
wire [8:0] T_456;
wire [8:0] T_469;
wire [8:0] T_474;
wire [8:0] T_475;
wire [8:0] T_484;
wire [8:0] T_489;
wire [8:0] T_490;
wire [8:0] T_491;
wire [8:0] insnBits;
wire insn_sigs_hfclkrst;
wire insn_sigs_corerst;
wire insn_sigs_reserved1;
wire insn_sigs_vddpaden;
wire insn_sigs_reserved0;
wire [3:0] insn_dt;
wire [3:0] T_515;
wire T_516;
wire T_517;
wire T_518;
wire T_519;
wire T_520;
reg [15:0] count;
reg [31:0] GEN_60;
wire [16:0] T_523;
wire [15:0] T_524;
wire [15:0] T_525;
wire [15:0] T_526;
wire tick;
wire [3:0] npc;
wire last;
wire T_530;
wire T_531;
wire T_532;
wire [15:0] GEN_3;
wire GEN_4;
wire [3:0] GEN_5;
wire [15:0] GEN_6;
wire GEN_7;
wire [3:0] GEN_8;
wire T_540;
wire [1:0] T_541;
wire [1:0] T_542;
wire [3:0] T_543;
wire [3:0] T_544;
wire T_546;
wire T_548;
wire T_549;
wire T_552;
wire T_553;
wire T_554;
wire [1:0] T_560;
wire [1:0] T_561;
wire [1:0] T_562;
wire GEN_9;
wire GEN_10;
wire [1:0] GEN_11;
wire T_563;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire GEN_16;
wire [1:0] GEN_17;
wire GEN_18;
wire [9:0] GEN_35;
wire [9:0] T_567;
wire [9:0] GEN_36;
wire [9:0] T_568;
wire T_570;
wire [31:0] GEN_19;
wire T_571;
wire [31:0] GEN_20;
wire T_572;
wire [31:0] GEN_21;
wire T_573;
wire [31:0] GEN_22;
wire T_574;
wire [31:0] GEN_23;
wire T_575;
wire [31:0] GEN_24;
wire T_576;
wire [31:0] GEN_25;
wire T_577;
wire [31:0] GEN_26;
wire T_578;
wire [31:0] GEN_27;
wire T_579;
wire [31:0] GEN_28;
wire T_580;
wire [31:0] GEN_29;
wire T_581;
wire [31:0] GEN_30;
wire T_582;
wire [31:0] GEN_31;
wire T_583;
wire [31:0] GEN_32;
wire T_584;
wire [31:0] GEN_33;
wire T_585;
wire [31:0] GEN_34;
assign io_control_valid = T_532;
assign io_control_bits_hfclkrst = insn_sigs_hfclkrst;
assign io_control_bits_corerst = insn_sigs_corerst;
assign io_control_bits_reserved1 = insn_sigs_reserved1;
assign io_control_bits_vddpaden = insn_sigs_vddpaden;
assign io_control_bits_reserved0 = insn_sigs_reserved0;
assign io_regs_ie_read = ie;
assign io_regs_cause_read = {{22'd0}, T_568};
assign io_regs_sleep_read = {31'h0,wantSleep};
assign io_regs_key_read = {{31'd0}, unlocked};
assign io_regs_wakeupProgram_0_read = {{23'd0}, wakeupProgram_0};
assign io_regs_wakeupProgram_1_read = {{23'd0}, wakeupProgram_1};
assign io_regs_wakeupProgram_2_read = {{23'd0}, wakeupProgram_2};
assign io_regs_wakeupProgram_3_read = {{23'd0}, wakeupProgram_3};
assign io_regs_wakeupProgram_4_read = {{23'd0}, wakeupProgram_4};
assign io_regs_wakeupProgram_5_read = {{23'd0}, wakeupProgram_5};
assign io_regs_wakeupProgram_6_read = {{23'd0}, wakeupProgram_6};
assign io_regs_wakeupProgram_7_read = {{23'd0}, wakeupProgram_7};
assign io_regs_sleepProgram_0_read = {{23'd0}, sleepProgram_0};
assign io_regs_sleepProgram_1_read = {{23'd0}, sleepProgram_1};
assign io_regs_sleepProgram_2_read = {{23'd0}, sleepProgram_2};
assign io_regs_sleepProgram_3_read = {{23'd0}, sleepProgram_3};
assign io_regs_sleepProgram_4_read = {{23'd0}, sleepProgram_4};
assign io_regs_sleepProgram_5_read = {{23'd0}, sleepProgram_5};
assign io_regs_sleepProgram_6_read = {{23'd0}, sleepProgram_6};
assign io_regs_sleepProgram_7_read = {{23'd0}, sleepProgram_7};
assign T_364 = io_regs_sleepProgram_0_write_valid | io_regs_sleepProgram_1_write_valid;
assign T_365 = T_364 | io_regs_sleepProgram_2_write_valid;
assign T_366 = T_365 | io_regs_sleepProgram_3_write_valid;
assign T_367 = T_366 | io_regs_sleepProgram_4_write_valid;
assign T_368 = T_367 | io_regs_sleepProgram_5_write_valid;
assign T_369 = T_368 | io_regs_sleepProgram_6_write_valid;
assign T_370 = T_369 | io_regs_sleepProgram_7_write_valid;
assign T_371 = io_regs_wakeupProgram_0_write_valid | io_regs_wakeupProgram_1_write_valid;
assign T_372 = T_371 | io_regs_wakeupProgram_2_write_valid;
assign T_373 = T_372 | io_regs_wakeupProgram_3_write_valid;
assign T_374 = T_373 | io_regs_wakeupProgram_4_write_valid;
assign T_375 = T_374 | io_regs_wakeupProgram_5_write_valid;
assign T_376 = T_375 | io_regs_wakeupProgram_6_write_valid;
assign T_377 = T_376 | io_regs_wakeupProgram_7_write_valid;
assign T_378 = T_370 | T_377;
assign T_379 = T_378 | io_regs_sleep_write_valid;
assign T_380 = T_379 | io_regs_cause_write_valid;
assign T_381 = T_380 | io_regs_ie_write_valid;
assign T_383 = io_regs_key_write_bits == 32'h51f15e;
assign T_385 = T_381 == 1'h0;
assign T_386 = T_383 & T_385;
assign T_388 = io_regs_key_write_valid | T_381;
assign GEN_0 = T_388 ? T_386 : unlocked;
assign T_391 = io_regs_sleep_write_valid & unlocked;
assign GEN_1 = T_391 ? 1'h1 : wantSleep;
assign T_394 = io_regs_ie_write_valid & unlocked;
assign GEN_2 = T_394 ? io_regs_ie_write_bits : T_396;
assign ie = T_396 | 4'h1;
assign T_423 = pc & 3'h3;
assign T_425 = pc >= 3'h4;
assign T_427 = T_423 & 3'h1;
assign T_429 = T_423 >= 3'h2;
assign T_433 = T_427 >= 3'h1;
assign T_434 = T_433 ? wakeupProgram_7 : wakeupProgram_6;
assign T_439 = T_433 ? wakeupProgram_5 : wakeupProgram_4;
assign T_440 = T_429 ? T_434 : T_439;
assign T_449 = T_433 ? wakeupProgram_3 : wakeupProgram_2;
assign T_454 = T_433 ? wakeupProgram_1 : wakeupProgram_0;
assign T_455 = T_429 ? T_449 : T_454;
assign T_456 = T_425 ? T_440 : T_455;
assign T_469 = T_433 ? sleepProgram_7 : sleepProgram_6;
assign T_474 = T_433 ? sleepProgram_5 : sleepProgram_4;
assign T_475 = T_429 ? T_469 : T_474;
assign T_484 = T_433 ? sleepProgram_3 : sleepProgram_2;
assign T_489 = T_433 ? sleepProgram_1 : sleepProgram_0;
assign T_490 = T_429 ? T_484 : T_489;
assign T_491 = T_425 ? T_475 : T_490;
assign insnBits = awake ? T_456 : T_491;
assign insn_sigs_hfclkrst = T_520;
assign insn_sigs_corerst = T_519;
assign insn_sigs_reserved1 = T_518;
assign insn_sigs_vddpaden = T_517;
assign insn_sigs_reserved0 = T_516;
assign insn_dt = T_515;
assign T_515 = insnBits[3:0];
assign T_516 = insnBits[4];
assign T_517 = insnBits[5];
assign T_518 = insnBits[6];
assign T_519 = insnBits[7];
assign T_520 = insnBits[8];
assign T_523 = count + 16'h1;
assign T_524 = T_523[15:0];
assign T_525 = count ^ T_524;
assign T_526 = T_525 >> insn_dt;
assign tick = T_526[0];
assign npc = pc + 3'h1;
assign last = npc >= 4'h8;
assign T_530 = last == 1'h0;
assign T_531 = run & T_530;
assign T_532 = T_531 & tick;
assign GEN_3 = tick ? 16'h0 : T_524;
assign GEN_4 = tick ? T_530 : run;
assign GEN_5 = tick ? npc : {{1'd0}, pc};
assign GEN_6 = run ? GEN_3 : count;
assign GEN_7 = run ? GEN_4 : run;
assign GEN_8 = run ? GEN_5 : {{1'd0}, pc};
assign T_540 = run == 1'h0;
assign T_541 = {io_wakeup_rtc,io_wakeup_reset};
assign T_542 = {io_wakeup_awakeup,io_wakeup_dwakeup};
assign T_543 = {T_542,T_541};
assign T_544 = ie & T_543;
assign T_546 = awake == 1'h0;
assign T_548 = T_544 != 4'h0;
assign T_549 = T_546 & T_548;
assign T_552 = T_544[0];
assign T_553 = T_544[1];
assign T_554 = T_544[2];
assign T_560 = T_554 ? 2'h2 : 2'h3;
assign T_561 = T_553 ? 2'h1 : T_560;
assign T_562 = T_552 ? 2'h0 : T_561;
assign GEN_9 = T_549 ? 1'h1 : GEN_7;
assign GEN_10 = T_549 ? 1'h1 : awake;
assign GEN_11 = T_549 ? T_562 : wakeupCause;
//Bob: here we introduce a core_wfi signal to make sure when the PMU is
// going to power down MOFF, the core is really idle (executed wfi)
//assign T_563 = awake & wantSleep & core_wfi;
assign T_563 = awake & wantSleep;// Current we dont add it
assign GEN_12 = T_563 ? 1'h1 : GEN_9;
assign GEN_13 = T_563 ? 1'h0 : GEN_10;
assign GEN_14 = T_563 ? 1'h0 : GEN_1;
assign GEN_15 = T_540 ? GEN_12 : GEN_7;
assign GEN_16 = T_540 ? GEN_13 : awake;
assign GEN_17 = T_540 ? GEN_11 : wakeupCause;
assign GEN_18 = T_540 ? GEN_14 : GEN_1;
assign GEN_35 = {{8'd0}, io_resetCause};
assign T_567 = GEN_35 << 8;
assign GEN_36 = {{8'd0}, wakeupCause};
assign T_568 = GEN_36 | T_567;
assign T_570 = io_regs_wakeupProgram_0_write_valid & unlocked;
assign GEN_19 = T_570 ? io_regs_wakeupProgram_0_write_bits : {{23'd0}, wakeupProgram_0};
assign T_571 = io_regs_wakeupProgram_1_write_valid & unlocked;
assign GEN_20 = T_571 ? io_regs_wakeupProgram_1_write_bits : {{23'd0}, wakeupProgram_1};
assign T_572 = io_regs_wakeupProgram_2_write_valid & unlocked;
assign GEN_21 = T_572 ? io_regs_wakeupProgram_2_write_bits : {{23'd0}, wakeupProgram_2};
assign T_573 = io_regs_wakeupProgram_3_write_valid & unlocked;
assign GEN_22 = T_573 ? io_regs_wakeupProgram_3_write_bits : {{23'd0}, wakeupProgram_3};
assign T_574 = io_regs_wakeupProgram_4_write_valid & unlocked;
assign GEN_23 = T_574 ? io_regs_wakeupProgram_4_write_bits : {{23'd0}, wakeupProgram_4};
assign T_575 = io_regs_wakeupProgram_5_write_valid & unlocked;
assign GEN_24 = T_575 ? io_regs_wakeupProgram_5_write_bits : {{23'd0}, wakeupProgram_5};
assign T_576 = io_regs_wakeupProgram_6_write_valid & unlocked;
assign GEN_25 = T_576 ? io_regs_wakeupProgram_6_write_bits : {{23'd0}, wakeupProgram_6};
assign T_577 = io_regs_wakeupProgram_7_write_valid & unlocked;
assign GEN_26 = T_577 ? io_regs_wakeupProgram_7_write_bits : {{23'd0}, wakeupProgram_7};
assign T_578 = io_regs_sleepProgram_0_write_valid & unlocked;
assign GEN_27 = T_578 ? io_regs_sleepProgram_0_write_bits : {{23'd0}, sleepProgram_0};
assign T_579 = io_regs_sleepProgram_1_write_valid & unlocked;
assign GEN_28 = T_579 ? io_regs_sleepProgram_1_write_bits : {{23'd0}, sleepProgram_1};
assign T_580 = io_regs_sleepProgram_2_write_valid & unlocked;
assign GEN_29 = T_580 ? io_regs_sleepProgram_2_write_bits : {{23'd0}, sleepProgram_2};
assign T_581 = io_regs_sleepProgram_3_write_valid & unlocked;
assign GEN_30 = T_581 ? io_regs_sleepProgram_3_write_bits : {{23'd0}, sleepProgram_3};
assign T_582 = io_regs_sleepProgram_4_write_valid & unlocked;
assign GEN_31 = T_582 ? io_regs_sleepProgram_4_write_bits : {{23'd0}, sleepProgram_4};
assign T_583 = io_regs_sleepProgram_5_write_valid & unlocked;
assign GEN_32 = T_583 ? io_regs_sleepProgram_5_write_bits : {{23'd0}, sleepProgram_5};
assign T_584 = io_regs_sleepProgram_6_write_valid & unlocked;
assign GEN_33 = T_584 ? io_regs_sleepProgram_6_write_bits : {{23'd0}, sleepProgram_6};
assign T_585 = io_regs_sleepProgram_7_write_valid & unlocked;
assign GEN_34 = T_585 ? io_regs_sleepProgram_7_write_bits : {{23'd0}, sleepProgram_7};
always @(posedge clock or posedge reset)
if (reset) begin
run <= 1'h1;
end else begin
if (T_540) begin
if (T_563) begin
run <= 1'h1;
end else begin
if (T_549) begin
run <= 1'h1;
end else begin
if (run) begin
if (tick) begin
run <= T_530;
end
end
end
end
end else begin
if (run) begin
if (tick) begin
run <= T_530;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
awake <= 1'h1;
end else begin
if (T_540) begin
if (T_563) begin
awake <= 1'h0;
end else begin
if (T_549) begin
awake <= 1'h1;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
unlocked <= 1'h0;
end else begin
if (T_388) begin
unlocked <= T_386;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
wantSleep <= 1'h0;
end else begin
if (T_540) begin
if (T_563) begin
wantSleep <= 1'h0;
end else begin
if (T_391) begin
wantSleep <= io_regs_sleep_write_bits[0];
end
end
end else begin
if (T_391) begin
wantSleep <= io_regs_sleep_write_bits[0];
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
pc <= 3'h0;
end else begin
pc <= GEN_8[2:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupCause <= 2'h0;
end else begin
if (T_540) begin
if (T_549) begin
if (T_552) begin
wakeupCause <= 2'h0;
end else begin
if (T_553) begin
wakeupCause <= 2'h1;
end else begin
if (T_554) begin
wakeupCause <= 2'h2;
end else begin
wakeupCause <= 2'h3;
end
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_396 <= 4'b0;
end
else if (T_394) begin
T_396 <= io_regs_ie_write_bits;
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_0 <= 9'h1f0;
end else begin
wakeupProgram_0 <= GEN_19[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_1 <= 9'hf8;
end else begin
wakeupProgram_1 <= GEN_20[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_2 <= 9'h30;
end else begin
wakeupProgram_2 <= GEN_21[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_3 <= 9'h30;
end else begin
wakeupProgram_3 <= GEN_22[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_4 <= 9'h30;
end else begin
wakeupProgram_4 <= GEN_23[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_5 <= 9'h30;
end else begin
wakeupProgram_5 <= GEN_24[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_6 <= 9'h30;
end else begin
wakeupProgram_6 <= GEN_25[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
wakeupProgram_7 <= 9'h30;
end else begin
wakeupProgram_7 <= GEN_26[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_0 <= 9'hf0;
end else begin
sleepProgram_0 <= GEN_27[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_1 <= 9'h1f0;
end else begin
sleepProgram_1 <= GEN_28[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_2 <= 9'h1d0;
end else begin
sleepProgram_2 <= GEN_29[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_3 <= 9'h1c0;
end else begin
sleepProgram_3 <= GEN_30[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_4 <= 9'h1c0;
end else begin
sleepProgram_4 <= GEN_31[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_5 <= 9'h1c0;
end else begin
sleepProgram_5 <= GEN_32[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_6 <= 9'h1c0;
end else begin
sleepProgram_6 <= GEN_33[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
sleepProgram_7 <= 9'h1c0;
end else begin
sleepProgram_7 <= GEN_34[8:0];
end
always @(posedge clock or posedge reset)
if (reset) begin
count <= 16'h0;
end else begin
if (run) begin
if (tick) begin
count <= 16'h0;
end else begin
count <= T_524;
end
end
end
endmodule |
module e203_itcm_ram(
input sd,
input ds,
input ls,
input cs,
input we,
input [`E203_ITCM_RAM_AW-1:0] addr,
input [`E203_ITCM_RAM_MW-1:0] wem,
input [`E203_ITCM_RAM_DW-1:0] din,
output [`E203_ITCM_RAM_DW-1:0] dout,
input rst_n,
input clk
);
wire wren = we & cs;
wire [7:0]wea;
assign wea = (wren) ? wem : 8'b0;
wire rden;
assign rden = (~we) & cs;
// bram u_e203_itcm_gnrl_ram(
//
// .doa (dout),
// .dia (din ),
// .addra (addr),
// .wea (wea ),
// .cea (cs ),
// .clka (clk ),
// .rsta (1'b0),
//
// .dob (),
// .dib (`E203_ITCM_RAM_DW'b0),
// .addrb (13'b0),
// .web (8'b0),
// .ceb (1'b0),
// .clkb (1'b0),
// .rstb (1'b0)
// );
riscv_ram64 u_e203_itcm_gnrl_ram
(
.address(addr),
.byteena(wea),
.clock (clk),
.data (din),
.rden (rden),
.wren (wren),
.q (dout)
);
// sirv_gnrl_ram #(
// `ifndef E203_HAS_ECC//{
// .FORCE_X2ZERO(0),
// `endif//}
// .DP(`E203_ITCM_RAM_DP),
// .DW(`E203_ITCM_RAM_DW),
// .MW(`E203_ITCM_RAM_MW),
// .AW(`E203_ITCM_RAM_AW)
// ) u_e203_itcm_gnrl_ram(
// .sd (sd ),
// .ds (ds ),
// .ls (ls ),
//
// .rst_n (rst_n ),
// .clk (clk ),
// .cs (cs ),
// .we (we ),
// .addr(addr),
// .din (din ),
// .wem (wem ),
// .dout(dout)
// );
endmodule |
module sirv_spigpioport_1(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
wire T_270;
wire T_273;
wire T_276;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_270;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_273;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_276;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_270 = ~ io_spi_dq_1_oe;
assign T_273 = ~ io_spi_dq_2_oe;
assign T_276 = ~ io_spi_dq_3_oe;
endmodule |
module sirv_AsyncResetRegVec_67(
input clock,
input reset,
input [31:0] io_d,
output [31:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire reg_3_rst;
wire reg_3_clk;
wire reg_3_en;
wire reg_3_q;
wire reg_3_d;
wire reg_4_rst;
wire reg_4_clk;
wire reg_4_en;
wire reg_4_q;
wire reg_4_d;
wire reg_5_rst;
wire reg_5_clk;
wire reg_5_en;
wire reg_5_q;
wire reg_5_d;
wire reg_6_rst;
wire reg_6_clk;
wire reg_6_en;
wire reg_6_q;
wire reg_6_d;
wire reg_7_rst;
wire reg_7_clk;
wire reg_7_en;
wire reg_7_q;
wire reg_7_d;
wire reg_8_rst;
wire reg_8_clk;
wire reg_8_en;
wire reg_8_q;
wire reg_8_d;
wire reg_9_rst;
wire reg_9_clk;
wire reg_9_en;
wire reg_9_q;
wire reg_9_d;
wire reg_10_rst;
wire reg_10_clk;
wire reg_10_en;
wire reg_10_q;
wire reg_10_d;
wire reg_11_rst;
wire reg_11_clk;
wire reg_11_en;
wire reg_11_q;
wire reg_11_d;
wire reg_12_rst;
wire reg_12_clk;
wire reg_12_en;
wire reg_12_q;
wire reg_12_d;
wire reg_13_rst;
wire reg_13_clk;
wire reg_13_en;
wire reg_13_q;
wire reg_13_d;
wire reg_14_rst;
wire reg_14_clk;
wire reg_14_en;
wire reg_14_q;
wire reg_14_d;
wire reg_15_rst;
wire reg_15_clk;
wire reg_15_en;
wire reg_15_q;
wire reg_15_d;
wire reg_16_rst;
wire reg_16_clk;
wire reg_16_en;
wire reg_16_q;
wire reg_16_d;
wire reg_17_rst;
wire reg_17_clk;
wire reg_17_en;
wire reg_17_q;
wire reg_17_d;
wire reg_18_rst;
wire reg_18_clk;
wire reg_18_en;
wire reg_18_q;
wire reg_18_d;
wire reg_19_rst;
wire reg_19_clk;
wire reg_19_en;
wire reg_19_q;
wire reg_19_d;
wire reg_20_rst;
wire reg_20_clk;
wire reg_20_en;
wire reg_20_q;
wire reg_20_d;
wire reg_21_rst;
wire reg_21_clk;
wire reg_21_en;
wire reg_21_q;
wire reg_21_d;
wire reg_22_rst;
wire reg_22_clk;
wire reg_22_en;
wire reg_22_q;
wire reg_22_d;
wire reg_23_rst;
wire reg_23_clk;
wire reg_23_en;
wire reg_23_q;
wire reg_23_d;
wire reg_24_rst;
wire reg_24_clk;
wire reg_24_en;
wire reg_24_q;
wire reg_24_d;
wire reg_25_rst;
wire reg_25_clk;
wire reg_25_en;
wire reg_25_q;
wire reg_25_d;
wire reg_26_rst;
wire reg_26_clk;
wire reg_26_en;
wire reg_26_q;
wire reg_26_d;
wire reg_27_rst;
wire reg_27_clk;
wire reg_27_en;
wire reg_27_q;
wire reg_27_d;
wire reg_28_rst;
wire reg_28_clk;
wire reg_28_en;
wire reg_28_q;
wire reg_28_d;
wire reg_29_rst;
wire reg_29_clk;
wire reg_29_en;
wire reg_29_q;
wire reg_29_d;
wire reg_30_rst;
wire reg_30_clk;
wire reg_30_en;
wire reg_30_q;
wire reg_30_d;
wire reg_31_rst;
wire reg_31_clk;
wire reg_31_en;
wire reg_31_q;
wire reg_31_d;
wire T_8;
wire T_9;
wire T_10;
wire T_11;
wire T_12;
wire T_13;
wire T_14;
wire T_15;
wire T_16;
wire T_17;
wire T_18;
wire T_19;
wire T_20;
wire T_21;
wire T_22;
wire T_23;
wire T_24;
wire T_25;
wire T_26;
wire T_27;
wire T_28;
wire T_29;
wire T_30;
wire T_31;
wire T_32;
wire T_33;
wire T_34;
wire T_35;
wire T_36;
wire T_37;
wire T_38;
wire T_39;
wire [1:0] T_40;
wire [1:0] T_41;
wire [3:0] T_42;
wire [1:0] T_43;
wire [1:0] T_44;
wire [3:0] T_45;
wire [7:0] T_46;
wire [1:0] T_47;
wire [1:0] T_48;
wire [3:0] T_49;
wire [1:0] T_50;
wire [1:0] T_51;
wire [3:0] T_52;
wire [7:0] T_53;
wire [15:0] T_54;
wire [1:0] T_55;
wire [1:0] T_56;
wire [3:0] T_57;
wire [1:0] T_58;
wire [1:0] T_59;
wire [3:0] T_60;
wire [7:0] T_61;
wire [1:0] T_62;
wire [1:0] T_63;
wire [3:0] T_64;
wire [1:0] T_65;
wire [1:0] T_66;
wire [3:0] T_67;
wire [7:0] T_68;
wire [15:0] T_69;
wire [31:0] T_70;
sirv_AsyncResetReg u_reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg u_reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg u_reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
sirv_AsyncResetReg u_reg_3 (
.rst(reg_3_rst),
.clk(reg_3_clk),
.en(reg_3_en),
.q(reg_3_q),
.d(reg_3_d)
);
sirv_AsyncResetReg u_reg_4 (
.rst(reg_4_rst),
.clk(reg_4_clk),
.en(reg_4_en),
.q(reg_4_q),
.d(reg_4_d)
);
sirv_AsyncResetReg u_reg_5 (
.rst(reg_5_rst),
.clk(reg_5_clk),
.en(reg_5_en),
.q(reg_5_q),
.d(reg_5_d)
);
sirv_AsyncResetReg u_reg_6 (
.rst(reg_6_rst),
.clk(reg_6_clk),
.en(reg_6_en),
.q(reg_6_q),
.d(reg_6_d)
);
sirv_AsyncResetReg u_reg_7 (
.rst(reg_7_rst),
.clk(reg_7_clk),
.en(reg_7_en),
.q(reg_7_q),
.d(reg_7_d)
);
sirv_AsyncResetReg u_reg_8 (
.rst(reg_8_rst),
.clk(reg_8_clk),
.en(reg_8_en),
.q(reg_8_q),
.d(reg_8_d)
);
sirv_AsyncResetReg u_reg_9 (
.rst(reg_9_rst),
.clk(reg_9_clk),
.en(reg_9_en),
.q(reg_9_q),
.d(reg_9_d)
);
sirv_AsyncResetReg u_reg_10 (
.rst(reg_10_rst),
.clk(reg_10_clk),
.en(reg_10_en),
.q(reg_10_q),
.d(reg_10_d)
);
sirv_AsyncResetReg u_reg_11 (
.rst(reg_11_rst),
.clk(reg_11_clk),
.en(reg_11_en),
.q(reg_11_q),
.d(reg_11_d)
);
sirv_AsyncResetReg u_reg_12 (
.rst(reg_12_rst),
.clk(reg_12_clk),
.en(reg_12_en),
.q(reg_12_q),
.d(reg_12_d)
);
sirv_AsyncResetReg u_reg_13 (
.rst(reg_13_rst),
.clk(reg_13_clk),
.en(reg_13_en),
.q(reg_13_q),
.d(reg_13_d)
);
sirv_AsyncResetReg u_reg_14 (
.rst(reg_14_rst),
.clk(reg_14_clk),
.en(reg_14_en),
.q(reg_14_q),
.d(reg_14_d)
);
sirv_AsyncResetReg u_reg_15 (
.rst(reg_15_rst),
.clk(reg_15_clk),
.en(reg_15_en),
.q(reg_15_q),
.d(reg_15_d)
);
sirv_AsyncResetReg u_reg_16 (
.rst(reg_16_rst),
.clk(reg_16_clk),
.en(reg_16_en),
.q(reg_16_q),
.d(reg_16_d)
);
sirv_AsyncResetReg u_reg_17 (
.rst(reg_17_rst),
.clk(reg_17_clk),
.en(reg_17_en),
.q(reg_17_q),
.d(reg_17_d)
);
sirv_AsyncResetReg u_reg_18 (
.rst(reg_18_rst),
.clk(reg_18_clk),
.en(reg_18_en),
.q(reg_18_q),
.d(reg_18_d)
);
sirv_AsyncResetReg u_reg_19 (
.rst(reg_19_rst),
.clk(reg_19_clk),
.en(reg_19_en),
.q(reg_19_q),
.d(reg_19_d)
);
sirv_AsyncResetReg u_reg_20 (
.rst(reg_20_rst),
.clk(reg_20_clk),
.en(reg_20_en),
.q(reg_20_q),
.d(reg_20_d)
);
sirv_AsyncResetReg u_reg_21 (
.rst(reg_21_rst),
.clk(reg_21_clk),
.en(reg_21_en),
.q(reg_21_q),
.d(reg_21_d)
);
sirv_AsyncResetReg u_reg_22 (
.rst(reg_22_rst),
.clk(reg_22_clk),
.en(reg_22_en),
.q(reg_22_q),
.d(reg_22_d)
);
sirv_AsyncResetReg u_reg_23 (
.rst(reg_23_rst),
.clk(reg_23_clk),
.en(reg_23_en),
.q(reg_23_q),
.d(reg_23_d)
);
sirv_AsyncResetReg u_reg_24 (
.rst(reg_24_rst),
.clk(reg_24_clk),
.en(reg_24_en),
.q(reg_24_q),
.d(reg_24_d)
);
sirv_AsyncResetReg u_reg_25 (
.rst(reg_25_rst),
.clk(reg_25_clk),
.en(reg_25_en),
.q(reg_25_q),
.d(reg_25_d)
);
sirv_AsyncResetReg u_reg_26 (
.rst(reg_26_rst),
.clk(reg_26_clk),
.en(reg_26_en),
.q(reg_26_q),
.d(reg_26_d)
);
sirv_AsyncResetReg u_reg_27 (
.rst(reg_27_rst),
.clk(reg_27_clk),
.en(reg_27_en),
.q(reg_27_q),
.d(reg_27_d)
);
sirv_AsyncResetReg u_reg_28 (
.rst(reg_28_rst),
.clk(reg_28_clk),
.en(reg_28_en),
.q(reg_28_q),
.d(reg_28_d)
);
sirv_AsyncResetReg u_reg_29 (
.rst(reg_29_rst),
.clk(reg_29_clk),
.en(reg_29_en),
.q(reg_29_q),
.d(reg_29_d)
);
sirv_AsyncResetReg u_reg_30 (
.rst(reg_30_rst),
.clk(reg_30_clk),
.en(reg_30_en),
.q(reg_30_q),
.d(reg_30_d)
);
sirv_AsyncResetReg u_reg_31 (
.rst(reg_31_rst),
.clk(reg_31_clk),
.en(reg_31_en),
.q(reg_31_q),
.d(reg_31_d)
);
assign io_q = T_70;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign reg_3_rst = reset;
assign reg_3_clk = clock;
assign reg_3_en = io_en;
assign reg_3_d = T_11;
assign reg_4_rst = reset;
assign reg_4_clk = clock;
assign reg_4_en = io_en;
assign reg_4_d = T_12;
assign reg_5_rst = reset;
assign reg_5_clk = clock;
assign reg_5_en = io_en;
assign reg_5_d = T_13;
assign reg_6_rst = reset;
assign reg_6_clk = clock;
assign reg_6_en = io_en;
assign reg_6_d = T_14;
assign reg_7_rst = reset;
assign reg_7_clk = clock;
assign reg_7_en = io_en;
assign reg_7_d = T_15;
assign reg_8_rst = reset;
assign reg_8_clk = clock;
assign reg_8_en = io_en;
assign reg_8_d = T_16;
assign reg_9_rst = reset;
assign reg_9_clk = clock;
assign reg_9_en = io_en;
assign reg_9_d = T_17;
assign reg_10_rst = reset;
assign reg_10_clk = clock;
assign reg_10_en = io_en;
assign reg_10_d = T_18;
assign reg_11_rst = reset;
assign reg_11_clk = clock;
assign reg_11_en = io_en;
assign reg_11_d = T_19;
assign reg_12_rst = reset;
assign reg_12_clk = clock;
assign reg_12_en = io_en;
assign reg_12_d = T_20;
assign reg_13_rst = reset;
assign reg_13_clk = clock;
assign reg_13_en = io_en;
assign reg_13_d = T_21;
assign reg_14_rst = reset;
assign reg_14_clk = clock;
assign reg_14_en = io_en;
assign reg_14_d = T_22;
assign reg_15_rst = reset;
assign reg_15_clk = clock;
assign reg_15_en = io_en;
assign reg_15_d = T_23;
assign reg_16_rst = reset;
assign reg_16_clk = clock;
assign reg_16_en = io_en;
assign reg_16_d = T_24;
assign reg_17_rst = reset;
assign reg_17_clk = clock;
assign reg_17_en = io_en;
assign reg_17_d = T_25;
assign reg_18_rst = reset;
assign reg_18_clk = clock;
assign reg_18_en = io_en;
assign reg_18_d = T_26;
assign reg_19_rst = reset;
assign reg_19_clk = clock;
assign reg_19_en = io_en;
assign reg_19_d = T_27;
assign reg_20_rst = reset;
assign reg_20_clk = clock;
assign reg_20_en = io_en;
assign reg_20_d = T_28;
assign reg_21_rst = reset;
assign reg_21_clk = clock;
assign reg_21_en = io_en;
assign reg_21_d = T_29;
assign reg_22_rst = reset;
assign reg_22_clk = clock;
assign reg_22_en = io_en;
assign reg_22_d = T_30;
assign reg_23_rst = reset;
assign reg_23_clk = clock;
assign reg_23_en = io_en;
assign reg_23_d = T_31;
assign reg_24_rst = reset;
assign reg_24_clk = clock;
assign reg_24_en = io_en;
assign reg_24_d = T_32;
assign reg_25_rst = reset;
assign reg_25_clk = clock;
assign reg_25_en = io_en;
assign reg_25_d = T_33;
assign reg_26_rst = reset;
assign reg_26_clk = clock;
assign reg_26_en = io_en;
assign reg_26_d = T_34;
assign reg_27_rst = reset;
assign reg_27_clk = clock;
assign reg_27_en = io_en;
assign reg_27_d = T_35;
assign reg_28_rst = reset;
assign reg_28_clk = clock;
assign reg_28_en = io_en;
assign reg_28_d = T_36;
assign reg_29_rst = reset;
assign reg_29_clk = clock;
assign reg_29_en = io_en;
assign reg_29_d = T_37;
assign reg_30_rst = reset;
assign reg_30_clk = clock;
assign reg_30_en = io_en;
assign reg_30_d = T_38;
assign reg_31_rst = reset;
assign reg_31_clk = clock;
assign reg_31_en = io_en;
assign reg_31_d = T_39;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = io_d[3];
assign T_12 = io_d[4];
assign T_13 = io_d[5];
assign T_14 = io_d[6];
assign T_15 = io_d[7];
assign T_16 = io_d[8];
assign T_17 = io_d[9];
assign T_18 = io_d[10];
assign T_19 = io_d[11];
assign T_20 = io_d[12];
assign T_21 = io_d[13];
assign T_22 = io_d[14];
assign T_23 = io_d[15];
assign T_24 = io_d[16];
assign T_25 = io_d[17];
assign T_26 = io_d[18];
assign T_27 = io_d[19];
assign T_28 = io_d[20];
assign T_29 = io_d[21];
assign T_30 = io_d[22];
assign T_31 = io_d[23];
assign T_32 = io_d[24];
assign T_33 = io_d[25];
assign T_34 = io_d[26];
assign T_35 = io_d[27];
assign T_36 = io_d[28];
assign T_37 = io_d[29];
assign T_38 = io_d[30];
assign T_39 = io_d[31];
assign T_40 = {reg_1_q,reg_0_q};
assign T_41 = {reg_3_q,reg_2_q};
assign T_42 = {T_41,T_40};
assign T_43 = {reg_5_q,reg_4_q};
assign T_44 = {reg_7_q,reg_6_q};
assign T_45 = {T_44,T_43};
assign T_46 = {T_45,T_42};
assign T_47 = {reg_9_q,reg_8_q};
assign T_48 = {reg_11_q,reg_10_q};
assign T_49 = {T_48,T_47};
assign T_50 = {reg_13_q,reg_12_q};
assign T_51 = {reg_15_q,reg_14_q};
assign T_52 = {T_51,T_50};
assign T_53 = {T_52,T_49};
assign T_54 = {T_53,T_46};
assign T_55 = {reg_17_q,reg_16_q};
assign T_56 = {reg_19_q,reg_18_q};
assign T_57 = {T_56,T_55};
assign T_58 = {reg_21_q,reg_20_q};
assign T_59 = {reg_23_q,reg_22_q};
assign T_60 = {T_59,T_58};
assign T_61 = {T_60,T_57};
assign T_62 = {reg_25_q,reg_24_q};
assign T_63 = {reg_27_q,reg_26_q};
assign T_64 = {T_63,T_62};
assign T_65 = {reg_29_q,reg_28_q};
assign T_66 = {reg_31_q,reg_30_q};
assign T_67 = {T_66,T_65};
assign T_68 = {T_67,T_64};
assign T_69 = {T_68,T_61};
assign T_70 = {T_69,T_54};
endmodule |
module sirv_expl_apb_slv #(
parameter AW = 32,
parameter DW = 32
)(
input [AW-1:0] apb_paddr,
input apb_pwrite,
input apb_pselx,
input apb_penable,
input [DW-1:0] apb_pwdata,
output [DW-1:0] apb_prdata,
input clk,
input rst_n
);
assign apb_prdata = {DW{1'b0}};
endmodule |
module e203_ifu(
output[`E203_PC_SIZE-1:0] inspect_pc,
output ifu_active,
input itcm_nohold,
input [`E203_PC_SIZE-1:0] pc_rtvec,
`ifdef E203_HAS_ITCM //{
input ifu2itcm_holdup,
//input ifu2itcm_replay,
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to System Memory, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2biu_icb_cmd_valid, // Handshake valid
input ifu2biu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2biu_icb_rsp_valid, // Response valid
output ifu2biu_icb_rsp_ready, // Response ready
input ifu2biu_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata,
//input ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_muldiv_b2b,
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rden,
input dec2ifu_rs1en,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_valid;
wire ifu_req_ready;
wire [`E203_PC_SIZE-1:0] ifu_req_pc;
wire ifu_req_seq;
wire ifu_req_seq_rv32;
wire [`E203_PC_SIZE-1:0] ifu_req_last_pc;
wire ifu_rsp_valid;
wire ifu_rsp_ready;
wire ifu_rsp_err;
//wire ifu_rsp_replay;
wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr;
e203_ifu_ifetch u_e203_ifu_ifetch(
.inspect_pc (inspect_pc),
.pc_rtvec (pc_rtvec),
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx),
.ifu_o_rs2idx (ifu_o_rs2idx),
.ifu_o_prdt_taken(ifu_o_prdt_taken),
.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.pipe_flush_add_op2 (pipe_flush_add_op2),
.ifu_halt_req (ifu_halt_req ),
.ifu_halt_ack (ifu_halt_ack ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu(dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk ),
.rst_n (rst_n )
);
e203_ifu_ift2icb u_e203_ifu_ift2icb (
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready(ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid(ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata(ifu2biu_icb_rsp_rdata),
//.ifu2biu_replay (ifu2biu_replay),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
assign ifu_active = 1'b1;// Seems the IFU never rest at block level
endmodule |
module e203_exu_wbck(
//////////////////////////////////////////////////////////////
// The ALU Write-Back Interface
input alu_wbck_i_valid, // Handshake valid
output alu_wbck_i_ready, // Handshake ready
input [`E203_XLEN-1:0] alu_wbck_i_wdat,
input [`E203_RFIDX_WIDTH-1:0] alu_wbck_i_rdidx,
// If ALU have error, it will not generate the wback_valid to wback module
// so we dont need the alu_wbck_i_err here
//////////////////////////////////////////////////////////////
// The Longp Write-Back Interface
input longp_wbck_i_valid, // Handshake valid
output longp_wbck_i_ready, // Handshake ready
input [`E203_FLEN-1:0] longp_wbck_i_wdat,
input [5-1:0] longp_wbck_i_flags,
input [`E203_RFIDX_WIDTH-1:0] longp_wbck_i_rdidx,
input longp_wbck_i_rdfpu,
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface to Regfile
output rf_wbck_o_ena,
output [`E203_XLEN-1:0] rf_wbck_o_wdat,
output [`E203_RFIDX_WIDTH-1:0] rf_wbck_o_rdidx,
input clk,
input rst_n
);
// The ALU instruction can write-back only when there is no any
// long pipeline instruction writing-back
// * Since ALU is the 1 cycle instructions, it have lowest
// priority in arbitration
wire wbck_ready4alu = (~longp_wbck_i_valid);
wire wbck_sel_alu = alu_wbck_i_valid & wbck_ready4alu;
// The Long-pipe instruction can always write-back since it have high priority
wire wbck_ready4longp = 1'b1;
wire wbck_sel_longp = longp_wbck_i_valid & wbck_ready4longp;
//////////////////////////////////////////////////////////////
// The Final arbitrated Write-Back Interface
wire rf_wbck_o_ready = 1'b1; // Regfile is always ready to be write because it just has 1 w-port
wire wbck_i_ready;
wire wbck_i_valid;
wire [`E203_FLEN-1:0] wbck_i_wdat;
wire [5-1:0] wbck_i_flags;
wire [`E203_RFIDX_WIDTH-1:0] wbck_i_rdidx;
wire wbck_i_rdfpu;
assign alu_wbck_i_ready = wbck_ready4alu & wbck_i_ready;
assign longp_wbck_i_ready = wbck_ready4longp & wbck_i_ready;
assign wbck_i_valid = wbck_sel_alu ? alu_wbck_i_valid : longp_wbck_i_valid;
`ifdef E203_FLEN_IS_32//{
assign wbck_i_wdat = wbck_sel_alu ? alu_wbck_i_wdat : longp_wbck_i_wdat;
`else//}{
assign wbck_i_wdat = wbck_sel_alu ? {{`E203_FLEN-`E203_XLEN{1'b0}},alu_wbck_i_wdat} : longp_wbck_i_wdat;
`endif//}
assign wbck_i_flags = wbck_sel_alu ? 5'b0 : longp_wbck_i_flags;
assign wbck_i_rdidx = wbck_sel_alu ? alu_wbck_i_rdidx : longp_wbck_i_rdidx;
assign wbck_i_rdfpu = wbck_sel_alu ? 1'b0 : longp_wbck_i_rdfpu;
// If it have error or non-rdwen it will not be send to this module
// instead have been killed at EU level, so it is always need to
// write back into regfile at here
assign wbck_i_ready = rf_wbck_o_ready;
wire rf_wbck_o_valid = wbck_i_valid;
wire wbck_o_ena = rf_wbck_o_valid & rf_wbck_o_ready;
assign rf_wbck_o_ena = wbck_o_ena & (~wbck_i_rdfpu);
assign rf_wbck_o_wdat = wbck_i_wdat[`E203_XLEN-1:0];
assign rf_wbck_o_rdidx = wbck_i_rdidx;
endmodule |
module e203_exu_disp(
input wfi_halt_exu_req,
output wfi_halt_exu_ack,
input oitf_empty,
input amo_wait,
//////////////////////////////////////////////////////////////
// The operands and decode info from dispatch
input disp_i_valid, // Handshake valid
output disp_i_ready, // Handshake ready
// The operand 1/2 read-enable signals and indexes
input disp_i_rs1x0,
input disp_i_rs2x0,
input disp_i_rs1en,
input disp_i_rs2en,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs1idx,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rs2idx,
input [`E203_XLEN-1:0] disp_i_rs1,
input [`E203_XLEN-1:0] disp_i_rs2,
input disp_i_rdwen,
input [`E203_RFIDX_WIDTH-1:0] disp_i_rdidx,
input [`E203_DECINFO_WIDTH-1:0] disp_i_info,
input [`E203_XLEN-1:0] disp_i_imm,
input [`E203_PC_SIZE-1:0] disp_i_pc,
input disp_i_misalgn,
input disp_i_buserr ,
input disp_i_ilegl ,
//////////////////////////////////////////////////////////////
// Dispatch to ALU
output disp_o_alu_valid,
input disp_o_alu_ready,
input disp_o_alu_longpipe,
output [`E203_XLEN-1:0] disp_o_alu_rs1,
output [`E203_XLEN-1:0] disp_o_alu_rs2,
output disp_o_alu_rdwen,
output [`E203_RFIDX_WIDTH-1:0] disp_o_alu_rdidx,
output [`E203_DECINFO_WIDTH-1:0] disp_o_alu_info,
output [`E203_XLEN-1:0] disp_o_alu_imm,
output [`E203_PC_SIZE-1:0] disp_o_alu_pc,
output [`E203_ITAG_WIDTH-1:0] disp_o_alu_itag,
output disp_o_alu_misalgn,
output disp_o_alu_buserr ,
output disp_o_alu_ilegl ,
//////////////////////////////////////////////////////////////
// Dispatch to OITF
input oitfrd_match_disprs1,
input oitfrd_match_disprs2,
input oitfrd_match_disprs3,
input oitfrd_match_disprd,
input [`E203_ITAG_WIDTH-1:0] disp_oitf_ptr ,
output disp_oitf_ena,
input disp_oitf_ready,
output disp_oitf_rs1fpu,
output disp_oitf_rs2fpu,
output disp_oitf_rs3fpu,
output disp_oitf_rdfpu ,
output disp_oitf_rs1en ,
output disp_oitf_rs2en ,
output disp_oitf_rs3en ,
output disp_oitf_rdwen ,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs2idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs3idx,
output [`E203_RFIDX_WIDTH-1:0] disp_oitf_rdidx ,
output [`E203_PC_SIZE-1:0] disp_oitf_pc ,
input clk,
input rst_n
);
wire [`E203_DECINFO_GRP_WIDTH-1:0] disp_i_info_grp = disp_i_info [`E203_DECINFO_GRP];
// Based on current 2 pipe stage implementation, the 2nd stage need to have all instruction
// to be commited via ALU interface, so every instruction need to be dispatched to ALU,
// regardless it is long pipe or not, and inside ALU it will issue instructions to different
// other longpipes
//wire disp_alu = (disp_i_info_grp == `E203_DECINFO_GRP_ALU)
// | (disp_i_info_grp == `E203_DECINFO_GRP_BJP)
// | (disp_i_info_grp == `E203_DECINFO_GRP_CSR)
// `ifdef E203_SUPPORT_SHARE_MULDIV //{
// | (disp_i_info_grp == `E203_DECINFO_GRP_MULDIV)
// `endif//E203_SUPPORT_SHARE_MULDIV}
// | (disp_i_info_grp == `E203_DECINFO_GRP_AGU);
wire disp_csr = (disp_i_info_grp == `E203_DECINFO_GRP_CSR);
wire disp_alu_longp_prdt = (disp_i_info_grp == `E203_DECINFO_GRP_AGU)
;
wire disp_alu_longp_real = disp_o_alu_longpipe;
// Both fence and fencei need to make sure all outstanding instruction have been completed
wire disp_fence_fencei = (disp_i_info_grp == `E203_DECINFO_GRP_BJP) &
( disp_i_info [`E203_DECINFO_BJP_FENCE] | disp_i_info [`E203_DECINFO_BJP_FENCEI]);
// Since any instruction will need to be dispatched to ALU, we dont need the gate here
// wire disp_i_ready_pos = disp_alu & disp_o_alu_ready;
// assign disp_o_alu_valid = disp_alu & disp_i_valid_pos;
wire disp_i_valid_pos;
wire disp_i_ready_pos = disp_o_alu_ready;
assign disp_o_alu_valid = disp_i_valid_pos;
//////////////////////////////////////////////////////////////
// The Dispatch Scheme Introduction for two-pipeline stage
// #1: The instruction after dispatched must have already have operand fetched, so
// there is no any WAR dependency happened.
// #2: The ALU-instruction are dispatched and executed in-order inside ALU, so
// there is no any WAW dependency happened among ALU instructions.
// Note: LSU since its AGU is handled inside ALU, so it is treated as a ALU instruction
// #3: The non-ALU-instruction are all tracked by OITF, and must be write-back in-order, so
// it is like ALU in-ordered. So there is no any WAW dependency happened among
// non-ALU instructions.
// Then what dependency will we have?
// * RAW: This is the real dependency
// * WAW: The WAW between ALU an non-ALU instructions
//
// So #1, The dispatching ALU instruction can not proceed and must be stalled when
// ** RAW: The ALU reading operands have data dependency with OITF entries
// *** Note: since it is 2 pipeline stage, any last ALU instruction have already
// write-back into the regfile. So there is no chance for ALU instr to depend
// on last ALU instructions as RAW.
// Note: if it is 3 pipeline stages, then we also need to consider the ALU-to-ALU
// RAW dependency.
// ** WAW: The ALU writing result have no any data dependency with OITF entries
// Note: Since the ALU instruction handled by ALU may surpass non-ALU OITF instructions
// so we must check this.
// And #2, The dispatching non-ALU instruction can not proceed and must be stalled when
// ** RAW: The non-ALU reading operands have data dependency with OITF entries
// *** Note: since it is 2 pipeline stage, any last ALU instruction have already
// write-back into the regfile. So there is no chance for non-ALU instr to depend
// on last ALU instructions as RAW.
// Note: if it is 3 pipeline stages, then we also need to consider the non-ALU-to-ALU
// RAW dependency.
wire raw_dep = ((oitfrd_match_disprs1) |
(oitfrd_match_disprs2) |
(oitfrd_match_disprs3));
// Only check the longp instructions (non-ALU) for WAW, here if we
// use the precise version (disp_alu_longp_real), it will hurt timing very much, but
// if we use imprecise version of disp_alu_longp_prdt, it is kind of tricky and in
// some corner case. For example, the AGU (treated as longp) will actually not dispatch
// to longp but just directly commited, then it become a normal ALU instruction, and should
// check the WAW dependency, but this only happened when it is AMO or unaligned-uop, so
// ideally we dont need to worry about it, because
// * We dont support AMO in 2 stage CPU here
// * We dont support Unalign load-store in 2 stage CPU here, which
// will be triggered as exception, so will not really write-back
// into regfile
// * But it depends on some assumption, so it is still risky if in the future something changed.
// Nevertheless: using this condition only waiver the longpipe WAW case, that is, two
// longp instruction write-back same reg back2back. Is it possible or is it common?
// after we checking the benmark result we found if we remove this complexity here
// it just does not change any benchmark number, so just remove that condition out. Means
// all of the instructions will check waw_dep
//wire alu_waw_dep = (~disp_alu_longp_prdt) & (oitfrd_match_disprd & disp_i_rdwen);
wire waw_dep = (oitfrd_match_disprd);
wire dep = raw_dep | waw_dep;
// The WFI halt exu ack will be asserted when the OITF is empty
// and also there is no AMO oustanding uops
assign wfi_halt_exu_ack = oitf_empty & (~amo_wait);
wire disp_condition =
// To be more conservtive, any accessing CSR instruction need to wait the oitf to be empty.
// Theoretically speaking, it should also flush pipeline after the CSR have been updated
// to make sure the subsequent instruction get correct CSR values, but in our 2-pipeline stage
// implementation, CSR is updated after EXU stage, and subsequent are all executed at EXU stage,
// no chance to got wrong CSR values, so we dont need to worry about this.
(disp_csr ? oitf_empty : 1'b1)
// To handle the Fence: just stall dispatch until the OITF is empty
& (disp_fence_fencei ? oitf_empty : 1'b1)
// If it was a WFI instruction commited halt req, then it will stall the disaptch
& (~wfi_halt_exu_req)
// No dependency
& (~dep)
//// // If dispatch to ALU as long pipeline, then must check
//// // the OITF is ready
//// & ((disp_alu & disp_o_alu_longpipe) ? disp_oitf_ready : 1'b1);
// To cut the critical timing path from longpipe signal
// we always assume the LSU will need oitf ready
& (disp_alu_longp_prdt ? disp_oitf_ready : 1'b1);
assign disp_i_valid_pos = disp_condition & disp_i_valid;
assign disp_i_ready = disp_condition & disp_i_ready_pos;
wire [`E203_XLEN-1:0] disp_i_rs1_msked = disp_i_rs1 & {`E203_XLEN{~disp_i_rs1x0}};
wire [`E203_XLEN-1:0] disp_i_rs2_msked = disp_i_rs2 & {`E203_XLEN{~disp_i_rs2x0}};
// Since we always dispatch any instructions into ALU, so we dont need to gate ops here
//assign disp_o_alu_rs1 = {`E203_XLEN{disp_alu}} & disp_i_rs1_msked;
//assign disp_o_alu_rs2 = {`E203_XLEN{disp_alu}} & disp_i_rs2_msked;
//assign disp_o_alu_rdwen = disp_alu & disp_i_rdwen;
//assign disp_o_alu_rdidx = {`E203_RFIDX_WIDTH{disp_alu}} & disp_i_rdidx;
//assign disp_o_alu_info = {`E203_DECINFO_WIDTH{disp_alu}} & disp_i_info;
assign disp_o_alu_rs1 = disp_i_rs1_msked;
assign disp_o_alu_rs2 = disp_i_rs2_msked;
assign disp_o_alu_rdwen = disp_i_rdwen;
assign disp_o_alu_rdidx = disp_i_rdidx;
assign disp_o_alu_info = disp_i_info;
// Why we use precise version of disp_longp here, because
// only when it is really dispatched as long pipe then allocate the OITF
assign disp_oitf_ena = disp_o_alu_valid & disp_o_alu_ready & disp_alu_longp_real;
assign disp_o_alu_imm = disp_i_imm;
assign disp_o_alu_pc = disp_i_pc;
assign disp_o_alu_itag = disp_oitf_ptr;
assign disp_o_alu_misalgn= disp_i_misalgn;
assign disp_o_alu_buserr = disp_i_buserr ;
assign disp_o_alu_ilegl = disp_i_ilegl ;
`ifndef E203_HAS_FPU//{
wire disp_i_fpu = 1'b0;
wire disp_i_fpu_rs1en = 1'b0;
wire disp_i_fpu_rs2en = 1'b0;
wire disp_i_fpu_rs3en = 1'b0;
wire disp_i_fpu_rdwen = 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs1idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs2idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rs3idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] disp_i_fpu_rdidx = `E203_RFIDX_WIDTH'b0;
wire disp_i_fpu_rs1fpu = 1'b0;
wire disp_i_fpu_rs2fpu = 1'b0;
wire disp_i_fpu_rs3fpu = 1'b0;
wire disp_i_fpu_rdfpu = 1'b0;
`endif//}
assign disp_oitf_rs1fpu = disp_i_fpu ? (disp_i_fpu_rs1en & disp_i_fpu_rs1fpu) : 1'b0;
assign disp_oitf_rs2fpu = disp_i_fpu ? (disp_i_fpu_rs2en & disp_i_fpu_rs2fpu) : 1'b0;
assign disp_oitf_rs3fpu = disp_i_fpu ? (disp_i_fpu_rs3en & disp_i_fpu_rs3fpu) : 1'b0;
assign disp_oitf_rdfpu = disp_i_fpu ? (disp_i_fpu_rdwen & disp_i_fpu_rdfpu ) : 1'b0;
assign disp_oitf_rs1en = disp_i_fpu ? disp_i_fpu_rs1en : disp_i_rs1en;
assign disp_oitf_rs2en = disp_i_fpu ? disp_i_fpu_rs2en : disp_i_rs2en;
assign disp_oitf_rs3en = disp_i_fpu ? disp_i_fpu_rs3en : 1'b0;
assign disp_oitf_rdwen = disp_i_fpu ? disp_i_fpu_rdwen : disp_i_rdwen;
assign disp_oitf_rs1idx = disp_i_fpu ? disp_i_fpu_rs1idx : disp_i_rs1idx;
assign disp_oitf_rs2idx = disp_i_fpu ? disp_i_fpu_rs2idx : disp_i_rs2idx;
assign disp_oitf_rs3idx = disp_i_fpu ? disp_i_fpu_rs3idx : `E203_RFIDX_WIDTH'b0;
assign disp_oitf_rdidx = disp_i_fpu ? disp_i_fpu_rdidx : disp_i_rdidx;
assign disp_oitf_pc = disp_i_pc;
endmodule |
module sirv_LevelGateway(
input clock,
input reset,
input io_interrupt,
output io_plic_valid,
input io_plic_ready,
input io_plic_complete
);
reg inFlight;
reg [31:0] GEN_2;
wire T_12;
wire GEN_0;
wire GEN_1;
wire T_16;
wire T_17;
assign io_plic_valid = T_17;
assign T_12 = io_interrupt & io_plic_ready;
assign GEN_0 = T_12 ? 1'h1 : inFlight;
assign GEN_1 = io_plic_complete ? 1'h0 : GEN_0;
assign T_16 = inFlight == 1'h0;
assign T_17 = io_interrupt & T_16;
always @(posedge clock or posedge reset) begin
if (reset) begin
inFlight <= 1'h0;
end else begin
if (io_plic_complete) begin
inFlight <= 1'h0;
end else begin
if (T_12) begin
inFlight <= 1'h1;
end
end
end
end
endmodule |
module sirv_pwm16_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire io_in_0_a_ready;
assign i_icb_cmd_ready = io_in_0_a_ready;
wire io_in_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_in_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_in_0_a_bits_param = 3'b0;
wire [2:0] io_in_0_a_bits_size = 3'd2;
wire [4:0] io_in_0_a_bits_source = 5'b0;
wire [28:0] io_in_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_in_0_a_bits_data = i_icb_cmd_wdata;
wire io_in_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_in_0_d_bits_opcode;
wire [1:0] io_in_0_d_bits_param;
wire [2:0] io_in_0_d_bits_size;
wire [4:0] io_in_0_d_bits_source;
wire io_in_0_d_bits_sink;
wire [1:0] io_in_0_d_bits_addr_lo;
wire [31:0] io_in_0_d_bits_data;
wire io_in_0_d_bits_error;
wire io_in_0_d_valid;
assign i_icb_rsp_valid = io_in_0_d_valid;
assign i_icb_rsp_rdata = io_in_0_d_bits_data;
// Not used
wire io_in_0_b_ready = 1'b0;
wire io_in_0_b_valid;
wire [2:0] io_in_0_b_bits_opcode;
wire [1:0] io_in_0_b_bits_param;
wire [2:0] io_in_0_b_bits_size;
wire [4:0] io_in_0_b_bits_source;
wire [28:0] io_in_0_b_bits_address;
wire [3:0] io_in_0_b_bits_mask;
wire [31:0] io_in_0_b_bits_data;
// Not used
wire io_in_0_c_ready;
wire io_in_0_c_valid = 1'b0;
wire [2:0] io_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_in_0_c_bits_param = 3'b0;
wire [2:0] io_in_0_c_bits_size = 3'd2;
wire [4:0] io_in_0_c_bits_source = 5'b0;
wire [28:0] io_in_0_c_bits_address = 29'b0;
wire [31:0] io_in_0_c_bits_data = 32'b0;
wire io_in_0_c_bits_error = 1'b0;
// Not used
wire io_in_0_e_ready;
wire io_in_0_e_valid = 1'b0;
wire io_in_0_e_bits_sink = 1'b0;
sirv_pwm16 u_sirv_pwm16(
.clock (clk ),
.reset (~rst_n ),
.io_interrupts_0_0 (io_interrupts_0_0 ),
.io_interrupts_0_1 (io_interrupts_0_1 ),
.io_interrupts_0_2 (io_interrupts_0_2 ),
.io_interrupts_0_3 (io_interrupts_0_3 ),
.io_gpio_0 (io_gpio_0 ),
.io_gpio_1 (io_gpio_1 ),
.io_gpio_2 (io_gpio_2 ),
.io_gpio_3 (io_gpio_3 ),
.io_in_0_a_ready (io_in_0_a_ready ),
.io_in_0_a_valid (io_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_in_0_a_bits_data ),
.io_in_0_b_ready (io_in_0_b_ready ),
.io_in_0_b_valid (io_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_in_0_b_bits_data ),
.io_in_0_c_ready (io_in_0_c_ready ),
.io_in_0_c_valid (io_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_in_0_c_bits_error ),
.io_in_0_d_ready (io_in_0_d_ready ),
.io_in_0_d_valid (io_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_in_0_d_bits_error ),
.io_in_0_e_ready (io_in_0_e_ready ),
.io_in_0_e_valid (io_in_0_e_valid ),
.io_in_0_e_bits_sink (io_in_0_e_bits_sink )
);
endmodule |
module sirv_qspi_4cs_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
output io_tl_i_0_0
);
wire io_tl_r_0_a_ready;
assign i_icb_cmd_ready = io_tl_r_0_a_ready;
wire io_tl_r_0_a_valid = i_icb_cmd_valid;
wire [2:0] io_tl_r_0_a_bits_opcode = i_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_r_0_a_bits_param = 3'b0;
wire [2:0] io_tl_r_0_a_bits_size = 3'd2;
wire [4:0] io_tl_r_0_a_bits_source = 5'b0;
wire [28:0] io_tl_r_0_a_bits_address = i_icb_cmd_addr[28:0];
wire [3:0] io_tl_r_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_r_0_a_bits_data = i_icb_cmd_wdata;
wire io_tl_r_0_d_ready = i_icb_rsp_ready;
wire [2:0] io_tl_r_0_d_bits_opcode;
wire [1:0] io_tl_r_0_d_bits_param;
wire [2:0] io_tl_r_0_d_bits_size;
wire [4:0] io_tl_r_0_d_bits_source;
wire io_tl_r_0_d_bits_sink;
wire [1:0] io_tl_r_0_d_bits_addr_lo;
wire [31:0] io_tl_r_0_d_bits_data;
wire io_tl_r_0_d_bits_error;
wire io_tl_r_0_d_valid;
assign i_icb_rsp_valid = io_tl_r_0_d_valid;
assign i_icb_rsp_rdata = io_tl_r_0_d_bits_data;
// Not used
wire io_tl_r_0_b_ready = 1'b0;
wire io_tl_r_0_b_valid;
wire [2:0] io_tl_r_0_b_bits_opcode;
wire [1:0] io_tl_r_0_b_bits_param;
wire [2:0] io_tl_r_0_b_bits_size;
wire [4:0] io_tl_r_0_b_bits_source;
wire [28:0] io_tl_r_0_b_bits_address;
wire [3:0] io_tl_r_0_b_bits_mask;
wire [31:0] io_tl_r_0_b_bits_data;
// Not used
wire io_tl_r_0_c_ready;
wire io_tl_r_0_c_valid = 1'b0;
wire [2:0] io_tl_r_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_r_0_c_bits_param = 3'b0;
wire [2:0] io_tl_r_0_c_bits_size = 3'd2;
wire [4:0] io_tl_r_0_c_bits_source = 5'b0;
wire [28:0] io_tl_r_0_c_bits_address = 29'b0;
wire [31:0] io_tl_r_0_c_bits_data = 32'b0;
wire io_tl_r_0_c_bits_error = 1'b0;
// Not used
wire io_tl_r_0_e_ready;
wire io_tl_r_0_e_valid = 1'b0;
wire io_tl_r_0_e_bits_sink = 1'b0;
sirv_qspi_4cs u_sirv_qspi_4cs(
.clock (clk ),
.reset (~rst_n ),
.io_tl_r_0_a_ready (io_tl_r_0_a_ready ),
.io_tl_r_0_a_valid (io_tl_r_0_a_valid ),
.io_tl_r_0_a_bits_opcode (io_tl_r_0_a_bits_opcode ),
.io_tl_r_0_a_bits_param (io_tl_r_0_a_bits_param ),
.io_tl_r_0_a_bits_size (io_tl_r_0_a_bits_size ),
.io_tl_r_0_a_bits_source (io_tl_r_0_a_bits_source ),
.io_tl_r_0_a_bits_address (io_tl_r_0_a_bits_address ),
.io_tl_r_0_a_bits_mask (io_tl_r_0_a_bits_mask ),
.io_tl_r_0_a_bits_data (io_tl_r_0_a_bits_data ),
.io_tl_r_0_b_ready (io_tl_r_0_b_ready ),
.io_tl_r_0_b_valid (io_tl_r_0_b_valid ),
.io_tl_r_0_b_bits_opcode (io_tl_r_0_b_bits_opcode ),
.io_tl_r_0_b_bits_param (io_tl_r_0_b_bits_param ),
.io_tl_r_0_b_bits_size (io_tl_r_0_b_bits_size ),
.io_tl_r_0_b_bits_source (io_tl_r_0_b_bits_source ),
.io_tl_r_0_b_bits_address (io_tl_r_0_b_bits_address ),
.io_tl_r_0_b_bits_mask (io_tl_r_0_b_bits_mask ),
.io_tl_r_0_b_bits_data (io_tl_r_0_b_bits_data ),
.io_tl_r_0_c_ready (io_tl_r_0_c_ready ),
.io_tl_r_0_c_valid (io_tl_r_0_c_valid ),
.io_tl_r_0_c_bits_opcode (io_tl_r_0_c_bits_opcode ),
.io_tl_r_0_c_bits_param (io_tl_r_0_c_bits_param ),
.io_tl_r_0_c_bits_size (io_tl_r_0_c_bits_size ),
.io_tl_r_0_c_bits_source (io_tl_r_0_c_bits_source ),
.io_tl_r_0_c_bits_address (io_tl_r_0_c_bits_address ),
.io_tl_r_0_c_bits_data (io_tl_r_0_c_bits_data ),
.io_tl_r_0_c_bits_error (io_tl_r_0_c_bits_error ),
.io_tl_r_0_d_ready (io_tl_r_0_d_ready ),
.io_tl_r_0_d_valid (io_tl_r_0_d_valid ),
.io_tl_r_0_d_bits_opcode (io_tl_r_0_d_bits_opcode ),
.io_tl_r_0_d_bits_param (io_tl_r_0_d_bits_param ),
.io_tl_r_0_d_bits_size (io_tl_r_0_d_bits_size ),
.io_tl_r_0_d_bits_source (io_tl_r_0_d_bits_source ),
.io_tl_r_0_d_bits_sink (io_tl_r_0_d_bits_sink ),
.io_tl_r_0_d_bits_addr_lo (io_tl_r_0_d_bits_addr_lo ),
.io_tl_r_0_d_bits_data (io_tl_r_0_d_bits_data ),
.io_tl_r_0_d_bits_error (io_tl_r_0_d_bits_error ),
.io_tl_r_0_e_ready (io_tl_r_0_e_ready ),
.io_tl_r_0_e_valid (io_tl_r_0_e_valid ),
.io_tl_r_0_e_bits_sink (io_tl_r_0_e_bits_sink ),
.io_port_sck (io_port_sck ),
.io_port_dq_0_i (io_port_dq_0_i ),
.io_port_dq_0_o (io_port_dq_0_o ),
.io_port_dq_0_oe (io_port_dq_0_oe),
.io_port_dq_1_i (io_port_dq_1_i ),
.io_port_dq_1_o (io_port_dq_1_o ),
.io_port_dq_1_oe (io_port_dq_1_oe),
.io_port_dq_2_i (io_port_dq_2_i ),
.io_port_dq_2_o (io_port_dq_2_o ),
.io_port_dq_2_oe (io_port_dq_2_oe),
.io_port_dq_3_i (io_port_dq_3_i ),
.io_port_dq_3_o (io_port_dq_3_o ),
.io_port_dq_3_oe (io_port_dq_3_oe),
.io_port_cs_0 (io_port_cs_0 ),
.io_port_cs_1 (io_port_cs_1 ),
.io_port_cs_2 (io_port_cs_2 ),
.io_port_cs_3 (io_port_cs_3 ),
.io_tl_i_0_0 (io_tl_i_0_0 )
);
endmodule |
module sirv_aon_lclkgen_regs(
input clk,
input rst_n,
output lfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [8 -1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata
);
// Directly connect the command channel with response channel
assign i_icb_rsp_valid = i_icb_cmd_valid;
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire icb_wr_en = i_icb_cmd_valid & i_icb_cmd_ready & (~i_icb_cmd_read);
wire [32-1:0] icb_wdata = i_icb_cmd_wdata;
wire [32-1:0] lfxosccfg_r;
// Addr selection
wire sel_lfxosccfg = (i_icb_cmd_addr == 8'h00);
wire icb_wr_en_lfxosccfg = icb_wr_en & sel_lfxosccfg ;
assign i_icb_rsp_rdata = ({32{sel_lfxosccfg}} & lfxosccfg_r);
/////////////////////////////////////////////////////////////////////////////////////////
// LFXOSCCFG
wire lfxoscen_ena = icb_wr_en_lfxosccfg;
// The reset value is 1
sirv_gnrl_dfflrs #(1) lfxoscen_dfflrs (lfxoscen_ena, icb_wdata[30], lfxoscen, clk, rst_n);
assign lfxosccfg_r = {1'b0, lfxoscen, 30'b0};
endmodule |
module sirv_pmu(
input clock,
input reset,
input io_wakeup_awakeup,
input io_wakeup_dwakeup,
input io_wakeup_rtc,
input io_wakeup_reset,
output io_control_hfclkrst,
output io_control_corerst,
output io_control_reserved1,
output io_control_vddpaden,
output io_control_reserved0,
input io_regs_ie_write_valid,
input [3:0] io_regs_ie_write_bits,
output [3:0] io_regs_ie_read,
input io_regs_cause_write_valid,
input [31:0] io_regs_cause_write_bits,
output [31:0] io_regs_cause_read,
input io_regs_sleep_write_valid,
input [31:0] io_regs_sleep_write_bits,
output [31:0] io_regs_sleep_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
input io_regs_wakeupProgram_0_write_valid,
input [31:0] io_regs_wakeupProgram_0_write_bits,
output [31:0] io_regs_wakeupProgram_0_read,
input io_regs_wakeupProgram_1_write_valid,
input [31:0] io_regs_wakeupProgram_1_write_bits,
output [31:0] io_regs_wakeupProgram_1_read,
input io_regs_wakeupProgram_2_write_valid,
input [31:0] io_regs_wakeupProgram_2_write_bits,
output [31:0] io_regs_wakeupProgram_2_read,
input io_regs_wakeupProgram_3_write_valid,
input [31:0] io_regs_wakeupProgram_3_write_bits,
output [31:0] io_regs_wakeupProgram_3_read,
input io_regs_wakeupProgram_4_write_valid,
input [31:0] io_regs_wakeupProgram_4_write_bits,
output [31:0] io_regs_wakeupProgram_4_read,
input io_regs_wakeupProgram_5_write_valid,
input [31:0] io_regs_wakeupProgram_5_write_bits,
output [31:0] io_regs_wakeupProgram_5_read,
input io_regs_wakeupProgram_6_write_valid,
input [31:0] io_regs_wakeupProgram_6_write_bits,
output [31:0] io_regs_wakeupProgram_6_read,
input io_regs_wakeupProgram_7_write_valid,
input [31:0] io_regs_wakeupProgram_7_write_bits,
output [31:0] io_regs_wakeupProgram_7_read,
input io_regs_sleepProgram_0_write_valid,
input [31:0] io_regs_sleepProgram_0_write_bits,
output [31:0] io_regs_sleepProgram_0_read,
input io_regs_sleepProgram_1_write_valid,
input [31:0] io_regs_sleepProgram_1_write_bits,
output [31:0] io_regs_sleepProgram_1_read,
input io_regs_sleepProgram_2_write_valid,
input [31:0] io_regs_sleepProgram_2_write_bits,
output [31:0] io_regs_sleepProgram_2_read,
input io_regs_sleepProgram_3_write_valid,
input [31:0] io_regs_sleepProgram_3_write_bits,
output [31:0] io_regs_sleepProgram_3_read,
input io_regs_sleepProgram_4_write_valid,
input [31:0] io_regs_sleepProgram_4_write_bits,
output [31:0] io_regs_sleepProgram_4_read,
input io_regs_sleepProgram_5_write_valid,
input [31:0] io_regs_sleepProgram_5_write_bits,
output [31:0] io_regs_sleepProgram_5_read,
input io_regs_sleepProgram_6_write_valid,
input [31:0] io_regs_sleepProgram_6_write_bits,
output [31:0] io_regs_sleepProgram_6_read,
input io_regs_sleepProgram_7_write_valid,
input [31:0] io_regs_sleepProgram_7_write_bits,
output [31:0] io_regs_sleepProgram_7_read,
input io_resetCauses_wdogrst,
input io_resetCauses_erst,
input io_resetCauses_porrst
);
reg T_355;
reg [31:0] GEN_1;
reg T_356;
reg [31:0] GEN_2;
wire core_clock;
wire core_reset;
wire core_io_wakeup_awakeup;
wire core_io_wakeup_dwakeup;
wire core_io_wakeup_rtc;
wire core_io_wakeup_reset;
wire core_io_control_valid;
wire core_io_control_bits_hfclkrst;
wire core_io_control_bits_corerst;
wire core_io_control_bits_reserved1;
wire core_io_control_bits_vddpaden;
wire core_io_control_bits_reserved0;
wire [1:0] core_io_resetCause;
wire core_io_regs_ie_write_valid;
wire [3:0] core_io_regs_ie_write_bits;
wire [3:0] core_io_regs_ie_read;
wire core_io_regs_cause_write_valid;
wire [31:0] core_io_regs_cause_write_bits;
wire [31:0] core_io_regs_cause_read;
wire core_io_regs_sleep_write_valid;
wire [31:0] core_io_regs_sleep_write_bits;
wire [31:0] core_io_regs_sleep_read;
wire core_io_regs_key_write_valid;
wire [31:0] core_io_regs_key_write_bits;
wire [31:0] core_io_regs_key_read;
wire core_io_regs_wakeupProgram_0_write_valid;
wire [31:0] core_io_regs_wakeupProgram_0_write_bits;
wire [31:0] core_io_regs_wakeupProgram_0_read;
wire core_io_regs_wakeupProgram_1_write_valid;
wire [31:0] core_io_regs_wakeupProgram_1_write_bits;
wire [31:0] core_io_regs_wakeupProgram_1_read;
wire core_io_regs_wakeupProgram_2_write_valid;
wire [31:0] core_io_regs_wakeupProgram_2_write_bits;
wire [31:0] core_io_regs_wakeupProgram_2_read;
wire core_io_regs_wakeupProgram_3_write_valid;
wire [31:0] core_io_regs_wakeupProgram_3_write_bits;
wire [31:0] core_io_regs_wakeupProgram_3_read;
wire core_io_regs_wakeupProgram_4_write_valid;
wire [31:0] core_io_regs_wakeupProgram_4_write_bits;
wire [31:0] core_io_regs_wakeupProgram_4_read;
wire core_io_regs_wakeupProgram_5_write_valid;
wire [31:0] core_io_regs_wakeupProgram_5_write_bits;
wire [31:0] core_io_regs_wakeupProgram_5_read;
wire core_io_regs_wakeupProgram_6_write_valid;
wire [31:0] core_io_regs_wakeupProgram_6_write_bits;
wire [31:0] core_io_regs_wakeupProgram_6_read;
wire core_io_regs_wakeupProgram_7_write_valid;
wire [31:0] core_io_regs_wakeupProgram_7_write_bits;
wire [31:0] core_io_regs_wakeupProgram_7_read;
wire core_io_regs_sleepProgram_0_write_valid;
wire [31:0] core_io_regs_sleepProgram_0_write_bits;
wire [31:0] core_io_regs_sleepProgram_0_read;
wire core_io_regs_sleepProgram_1_write_valid;
wire [31:0] core_io_regs_sleepProgram_1_write_bits;
wire [31:0] core_io_regs_sleepProgram_1_read;
wire core_io_regs_sleepProgram_2_write_valid;
wire [31:0] core_io_regs_sleepProgram_2_write_bits;
wire [31:0] core_io_regs_sleepProgram_2_read;
wire core_io_regs_sleepProgram_3_write_valid;
wire [31:0] core_io_regs_sleepProgram_3_write_bits;
wire [31:0] core_io_regs_sleepProgram_3_read;
wire core_io_regs_sleepProgram_4_write_valid;
wire [31:0] core_io_regs_sleepProgram_4_write_bits;
wire [31:0] core_io_regs_sleepProgram_4_read;
wire core_io_regs_sleepProgram_5_write_valid;
wire [31:0] core_io_regs_sleepProgram_5_write_bits;
wire [31:0] core_io_regs_sleepProgram_5_read;
wire core_io_regs_sleepProgram_6_write_valid;
wire [31:0] core_io_regs_sleepProgram_6_write_bits;
wire [31:0] core_io_regs_sleepProgram_6_read;
wire core_io_regs_sleepProgram_7_write_valid;
wire [31:0] core_io_regs_sleepProgram_7_write_bits;
wire [31:0] core_io_regs_sleepProgram_7_read;
wire [1:0] T_358;
wire [1:0] T_359;
wire [2:0] T_360;
wire [4:0] T_361;
wire [4:0] T_362;
wire AsyncResetRegVec_1_1_clock;
wire AsyncResetRegVec_1_1_reset;
wire [4:0] AsyncResetRegVec_1_1_io_d;
wire [4:0] AsyncResetRegVec_1_1_io_q;
wire AsyncResetRegVec_1_1_io_en;
//wire [4:0] latch;
//Bob: the naming as latch is not good, which will introduce some confusing, so we give it renames here
wire [4:0] core_io_control_bits;
wire T_369_hfclkrst;
wire T_369_corerst;
wire T_369_reserved1;
wire T_369_vddpaden;
wire T_369_reserved0;
wire T_375;
wire T_376;
wire T_377;
wire T_378;
wire T_379;
wire [1:0] T_380;
wire [2:0] T_381;
//Bob: Name as Latch is not good, give it new name here
//wire SRLatch_3_q;
//wire SRLatch_3_reset;
//wire SRLatch_3_set;
wire T_382;
wire T_383;
wire T_384;
wire T_385;
//wire SRLatch_1_1_q;
//wire SRLatch_1_1_reset;
//wire SRLatch_1_1_set;
wire T_389;
//wire SRLatch_2_1_q;
//wire SRLatch_2_1_reset;
//wire SRLatch_2_1_set;
wire T_393;
wire [1:0] T_394;
wire [2:0] T_395;
wire T_396;
wire [1:0] T_397;
wire [1:0] GEN_0;
wire [1:0] T_400;
wire T_401;
wire [1:0] T_402;
sirv_pmu_core u_pmu_core (
.clock(core_clock),
.reset(core_reset),
.io_wakeup_awakeup(core_io_wakeup_awakeup),
.io_wakeup_dwakeup(core_io_wakeup_dwakeup),
.io_wakeup_rtc(core_io_wakeup_rtc),
.io_wakeup_reset(core_io_wakeup_reset),
.io_control_valid(core_io_control_valid),
.io_control_bits_hfclkrst(core_io_control_bits_hfclkrst),
.io_control_bits_corerst(core_io_control_bits_corerst),
.io_control_bits_reserved1(core_io_control_bits_reserved1),
.io_control_bits_vddpaden(core_io_control_bits_vddpaden),
.io_control_bits_reserved0(core_io_control_bits_reserved0),
.io_resetCause(core_io_resetCause),
.io_regs_ie_write_valid(core_io_regs_ie_write_valid),
.io_regs_ie_write_bits(core_io_regs_ie_write_bits),
.io_regs_ie_read(core_io_regs_ie_read),
.io_regs_cause_write_valid(core_io_regs_cause_write_valid),
.io_regs_cause_write_bits(core_io_regs_cause_write_bits),
.io_regs_cause_read(core_io_regs_cause_read),
.io_regs_sleep_write_valid(core_io_regs_sleep_write_valid),
.io_regs_sleep_write_bits(core_io_regs_sleep_write_bits),
.io_regs_sleep_read(core_io_regs_sleep_read),
.io_regs_key_write_valid(core_io_regs_key_write_valid),
.io_regs_key_write_bits(core_io_regs_key_write_bits),
.io_regs_key_read(core_io_regs_key_read),
.io_regs_wakeupProgram_0_write_valid(core_io_regs_wakeupProgram_0_write_valid),
.io_regs_wakeupProgram_0_write_bits(core_io_regs_wakeupProgram_0_write_bits),
.io_regs_wakeupProgram_0_read(core_io_regs_wakeupProgram_0_read),
.io_regs_wakeupProgram_1_write_valid(core_io_regs_wakeupProgram_1_write_valid),
.io_regs_wakeupProgram_1_write_bits(core_io_regs_wakeupProgram_1_write_bits),
.io_regs_wakeupProgram_1_read(core_io_regs_wakeupProgram_1_read),
.io_regs_wakeupProgram_2_write_valid(core_io_regs_wakeupProgram_2_write_valid),
.io_regs_wakeupProgram_2_write_bits(core_io_regs_wakeupProgram_2_write_bits),
.io_regs_wakeupProgram_2_read(core_io_regs_wakeupProgram_2_read),
.io_regs_wakeupProgram_3_write_valid(core_io_regs_wakeupProgram_3_write_valid),
.io_regs_wakeupProgram_3_write_bits(core_io_regs_wakeupProgram_3_write_bits),
.io_regs_wakeupProgram_3_read(core_io_regs_wakeupProgram_3_read),
.io_regs_wakeupProgram_4_write_valid(core_io_regs_wakeupProgram_4_write_valid),
.io_regs_wakeupProgram_4_write_bits(core_io_regs_wakeupProgram_4_write_bits),
.io_regs_wakeupProgram_4_read(core_io_regs_wakeupProgram_4_read),
.io_regs_wakeupProgram_5_write_valid(core_io_regs_wakeupProgram_5_write_valid),
.io_regs_wakeupProgram_5_write_bits(core_io_regs_wakeupProgram_5_write_bits),
.io_regs_wakeupProgram_5_read(core_io_regs_wakeupProgram_5_read),
.io_regs_wakeupProgram_6_write_valid(core_io_regs_wakeupProgram_6_write_valid),
.io_regs_wakeupProgram_6_write_bits(core_io_regs_wakeupProgram_6_write_bits),
.io_regs_wakeupProgram_6_read(core_io_regs_wakeupProgram_6_read),
.io_regs_wakeupProgram_7_write_valid(core_io_regs_wakeupProgram_7_write_valid),
.io_regs_wakeupProgram_7_write_bits(core_io_regs_wakeupProgram_7_write_bits),
.io_regs_wakeupProgram_7_read(core_io_regs_wakeupProgram_7_read),
.io_regs_sleepProgram_0_write_valid(core_io_regs_sleepProgram_0_write_valid),
.io_regs_sleepProgram_0_write_bits(core_io_regs_sleepProgram_0_write_bits),
.io_regs_sleepProgram_0_read(core_io_regs_sleepProgram_0_read),
.io_regs_sleepProgram_1_write_valid(core_io_regs_sleepProgram_1_write_valid),
.io_regs_sleepProgram_1_write_bits(core_io_regs_sleepProgram_1_write_bits),
.io_regs_sleepProgram_1_read(core_io_regs_sleepProgram_1_read),
.io_regs_sleepProgram_2_write_valid(core_io_regs_sleepProgram_2_write_valid),
.io_regs_sleepProgram_2_write_bits(core_io_regs_sleepProgram_2_write_bits),
.io_regs_sleepProgram_2_read(core_io_regs_sleepProgram_2_read),
.io_regs_sleepProgram_3_write_valid(core_io_regs_sleepProgram_3_write_valid),
.io_regs_sleepProgram_3_write_bits(core_io_regs_sleepProgram_3_write_bits),
.io_regs_sleepProgram_3_read(core_io_regs_sleepProgram_3_read),
.io_regs_sleepProgram_4_write_valid(core_io_regs_sleepProgram_4_write_valid),
.io_regs_sleepProgram_4_write_bits(core_io_regs_sleepProgram_4_write_bits),
.io_regs_sleepProgram_4_read(core_io_regs_sleepProgram_4_read),
.io_regs_sleepProgram_5_write_valid(core_io_regs_sleepProgram_5_write_valid),
.io_regs_sleepProgram_5_write_bits(core_io_regs_sleepProgram_5_write_bits),
.io_regs_sleepProgram_5_read(core_io_regs_sleepProgram_5_read),
.io_regs_sleepProgram_6_write_valid(core_io_regs_sleepProgram_6_write_valid),
.io_regs_sleepProgram_6_write_bits(core_io_regs_sleepProgram_6_write_bits),
.io_regs_sleepProgram_6_read(core_io_regs_sleepProgram_6_read),
.io_regs_sleepProgram_7_write_valid(core_io_regs_sleepProgram_7_write_valid),
.io_regs_sleepProgram_7_write_bits(core_io_regs_sleepProgram_7_write_bits),
.io_regs_sleepProgram_7_read(core_io_regs_sleepProgram_7_read)
);
sirv_AsyncResetRegVec_1 AsyncResetRegVec_1_1 (
.clock(AsyncResetRegVec_1_1_clock),
.reset(AsyncResetRegVec_1_1_reset),
.io_d(AsyncResetRegVec_1_1_io_d),
.io_q(AsyncResetRegVec_1_1_io_q),
.io_en(AsyncResetRegVec_1_1_io_en)
);
//Bob: Since the SR Latch is not friend to the ASIC flow, so I just replace it to the DFF
// And the name as Latch is not good, so give it a new name here
wire por_reset = T_382;// POR
wire erst_reset = T_383;// ERST
wire wdog_reset = T_384;// WDOG
// In case we lost the reset, we need to just use two-dff syncer to catch up the reset, and until the clock
// is there to clear it
reg por_reset_r;
reg por_reset_r_r;
always @(posedge clock or posedge por_reset) begin
if(por_reset) begin
por_reset_r <= 1'b1;
por_reset_r_r <= 1'b1;
end
else begin
por_reset_r <= 1'b0;
por_reset_r_r <= por_reset_r;
end
end
reg erst_reset_r;
reg erst_reset_r_r;
always @(posedge clock or posedge erst_reset) begin
if(erst_reset) begin
erst_reset_r <= 1'b1;
erst_reset_r_r <= 1'b1;
end
else begin
erst_reset_r <= 1'b0;
erst_reset_r_r <= erst_reset_r;
end
end
reg wdog_reset_r;
reg wdog_reset_r_r;
always @(posedge clock or posedge wdog_reset) begin
if(wdog_reset) begin
wdog_reset_r <= 1'b1;
wdog_reset_r_r <= 1'b1;
end
else begin
wdog_reset_r <= 1'b0;
wdog_reset_r_r <= wdog_reset_r;
end
end
// Reset cause priority if they are coming at same time:
// POR
// Erst
// Wdog
wire rstcause_por_set = por_reset_r_r;
wire rstcause_erst_set = erst_reset_r_r & (~por_reset_r_r);
wire rstcause_wdog_set = wdog_reset_r_r & (~erst_reset_r_r) & (~por_reset_r_r);
// The POR only clear if:
// there is no POR reset,
// And there are other two resets
wire rstcause_por_clr = (~por_reset_r_r) & (erst_reset_r_r | wdog_reset_r_r);
// The Erst only clear if:
// there is POR reset,
// or, there is no erst reset and there is wdog reset
wire rstcause_erst_clr = por_reset_r_r | ((~erst_reset_r_r) & wdog_reset_r_r);
// The Wdog only clear if:
// there is POR or Erst reset,
wire rstcause_wdog_clr = por_reset_r_r | erst_reset_r_r;
wire rstcause_por_ena = rstcause_por_set | rstcause_por_clr ;
wire rstcause_erst_ena = rstcause_erst_set | rstcause_erst_clr;
wire rstcause_wdog_ena = rstcause_wdog_set | rstcause_wdog_clr;
wire rstcause_por_nxt = rstcause_por_set | (~rstcause_por_clr );
wire rstcause_erst_nxt = rstcause_erst_set | (~rstcause_erst_clr);
wire rstcause_wdog_nxt = rstcause_wdog_set | (~rstcause_wdog_clr);
reg rstcause_por_r;
reg rstcause_wdog_r;
reg rstcause_erst_r;
// The reset cause itself cannot have reset signal
always @(posedge clock) begin
if(rstcause_por_ena) begin
rstcause_por_r <= rstcause_por_nxt;
end
end
always @(posedge clock) begin
if(rstcause_erst_ena) begin
rstcause_erst_r <= rstcause_erst_nxt;
end
end
always @(posedge clock) begin
if(rstcause_wdog_ena) begin
rstcause_wdog_r <= rstcause_wdog_nxt;
end
end
//sirv_SRLatch SRLatch_3 ( // POR
// .q(SRLatch_3_q),
// .reset(SRLatch_3_reset),
// .set(SRLatch_3_set)
//);
//sirv_SRLatch SRLatch_1_1 (// ERST
// .q(SRLatch_1_1_q),
// .reset(SRLatch_1_1_reset),
// .set(SRLatch_1_1_set)
//);
//sirv_SRLatch SRLatch_2_1 (//WDOG
// .q(SRLatch_2_1_q),
// .reset(SRLatch_2_1_reset),
// .set(SRLatch_2_1_set)
//);
assign io_control_hfclkrst = T_369_hfclkrst;
assign io_control_corerst = T_369_corerst;
assign io_control_reserved1 = T_369_reserved1;
assign io_control_vddpaden = T_369_vddpaden;
assign io_control_reserved0 = T_369_reserved0;
assign io_regs_ie_read = core_io_regs_ie_read;
assign io_regs_cause_read = core_io_regs_cause_read;
assign io_regs_sleep_read = core_io_regs_sleep_read;
assign io_regs_key_read = core_io_regs_key_read;
assign io_regs_wakeupProgram_0_read = core_io_regs_wakeupProgram_0_read;
assign io_regs_wakeupProgram_1_read = core_io_regs_wakeupProgram_1_read;
assign io_regs_wakeupProgram_2_read = core_io_regs_wakeupProgram_2_read;
assign io_regs_wakeupProgram_3_read = core_io_regs_wakeupProgram_3_read;
assign io_regs_wakeupProgram_4_read = core_io_regs_wakeupProgram_4_read;
assign io_regs_wakeupProgram_5_read = core_io_regs_wakeupProgram_5_read;
assign io_regs_wakeupProgram_6_read = core_io_regs_wakeupProgram_6_read;
assign io_regs_wakeupProgram_7_read = core_io_regs_wakeupProgram_7_read;
assign io_regs_sleepProgram_0_read = core_io_regs_sleepProgram_0_read;
assign io_regs_sleepProgram_1_read = core_io_regs_sleepProgram_1_read;
assign io_regs_sleepProgram_2_read = core_io_regs_sleepProgram_2_read;
assign io_regs_sleepProgram_3_read = core_io_regs_sleepProgram_3_read;
assign io_regs_sleepProgram_4_read = core_io_regs_sleepProgram_4_read;
assign io_regs_sleepProgram_5_read = core_io_regs_sleepProgram_5_read;
assign io_regs_sleepProgram_6_read = core_io_regs_sleepProgram_6_read;
assign io_regs_sleepProgram_7_read = core_io_regs_sleepProgram_7_read;
assign core_clock = clock;
assign core_reset = T_356;
assign core_io_wakeup_awakeup = io_wakeup_awakeup;
assign core_io_wakeup_dwakeup = io_wakeup_dwakeup;
assign core_io_wakeup_rtc = io_wakeup_rtc;
assign core_io_wakeup_reset = 1'h0;
assign core_io_resetCause = T_402;
assign core_io_regs_ie_write_valid = io_regs_ie_write_valid;
assign core_io_regs_ie_write_bits = io_regs_ie_write_bits;
assign core_io_regs_cause_write_valid = io_regs_cause_write_valid;
assign core_io_regs_cause_write_bits = io_regs_cause_write_bits;
assign core_io_regs_sleep_write_valid = io_regs_sleep_write_valid;
assign core_io_regs_sleep_write_bits = io_regs_sleep_write_bits;
assign core_io_regs_key_write_valid = io_regs_key_write_valid;
assign core_io_regs_key_write_bits = io_regs_key_write_bits;
assign core_io_regs_wakeupProgram_0_write_valid = io_regs_wakeupProgram_0_write_valid;
assign core_io_regs_wakeupProgram_0_write_bits = io_regs_wakeupProgram_0_write_bits;
assign core_io_regs_wakeupProgram_1_write_valid = io_regs_wakeupProgram_1_write_valid;
assign core_io_regs_wakeupProgram_1_write_bits = io_regs_wakeupProgram_1_write_bits;
assign core_io_regs_wakeupProgram_2_write_valid = io_regs_wakeupProgram_2_write_valid;
assign core_io_regs_wakeupProgram_2_write_bits = io_regs_wakeupProgram_2_write_bits;
assign core_io_regs_wakeupProgram_3_write_valid = io_regs_wakeupProgram_3_write_valid;
assign core_io_regs_wakeupProgram_3_write_bits = io_regs_wakeupProgram_3_write_bits;
assign core_io_regs_wakeupProgram_4_write_valid = io_regs_wakeupProgram_4_write_valid;
assign core_io_regs_wakeupProgram_4_write_bits = io_regs_wakeupProgram_4_write_bits;
assign core_io_regs_wakeupProgram_5_write_valid = io_regs_wakeupProgram_5_write_valid;
assign core_io_regs_wakeupProgram_5_write_bits = io_regs_wakeupProgram_5_write_bits;
assign core_io_regs_wakeupProgram_6_write_valid = io_regs_wakeupProgram_6_write_valid;
assign core_io_regs_wakeupProgram_6_write_bits = io_regs_wakeupProgram_6_write_bits;
assign core_io_regs_wakeupProgram_7_write_valid = io_regs_wakeupProgram_7_write_valid;
assign core_io_regs_wakeupProgram_7_write_bits = io_regs_wakeupProgram_7_write_bits;
assign core_io_regs_sleepProgram_0_write_valid = io_regs_sleepProgram_0_write_valid;
assign core_io_regs_sleepProgram_0_write_bits = io_regs_sleepProgram_0_write_bits;
assign core_io_regs_sleepProgram_1_write_valid = io_regs_sleepProgram_1_write_valid;
assign core_io_regs_sleepProgram_1_write_bits = io_regs_sleepProgram_1_write_bits;
assign core_io_regs_sleepProgram_2_write_valid = io_regs_sleepProgram_2_write_valid;
assign core_io_regs_sleepProgram_2_write_bits = io_regs_sleepProgram_2_write_bits;
assign core_io_regs_sleepProgram_3_write_valid = io_regs_sleepProgram_3_write_valid;
assign core_io_regs_sleepProgram_3_write_bits = io_regs_sleepProgram_3_write_bits;
assign core_io_regs_sleepProgram_4_write_valid = io_regs_sleepProgram_4_write_valid;
assign core_io_regs_sleepProgram_4_write_bits = io_regs_sleepProgram_4_write_bits;
assign core_io_regs_sleepProgram_5_write_valid = io_regs_sleepProgram_5_write_valid;
assign core_io_regs_sleepProgram_5_write_bits = io_regs_sleepProgram_5_write_bits;
assign core_io_regs_sleepProgram_6_write_valid = io_regs_sleepProgram_6_write_valid;
assign core_io_regs_sleepProgram_6_write_bits = io_regs_sleepProgram_6_write_bits;
assign core_io_regs_sleepProgram_7_write_valid = io_regs_sleepProgram_7_write_valid;
assign core_io_regs_sleepProgram_7_write_bits = io_regs_sleepProgram_7_write_bits;
assign T_358 = {core_io_control_bits_vddpaden,core_io_control_bits_reserved0};
assign T_359 = {core_io_control_bits_hfclkrst,core_io_control_bits_corerst};
assign T_360 = {T_359,core_io_control_bits_reserved1};
assign T_361 = {T_360,T_358};
assign T_362 = ~ T_361;
assign AsyncResetRegVec_1_1_clock = clock;
assign AsyncResetRegVec_1_1_reset = reset;
assign AsyncResetRegVec_1_1_io_d = T_362;
assign AsyncResetRegVec_1_1_io_en = core_io_control_valid;
assign core_io_control_bits = ~ AsyncResetRegVec_1_1_io_q;
assign T_369_hfclkrst = T_379;
assign T_369_corerst = T_378;
assign T_369_reserved1 = T_377;
assign T_369_vddpaden = T_376;
assign T_369_reserved0 = T_375;
assign T_375 = core_io_control_bits[0];
assign T_376 = core_io_control_bits[1];
assign T_377 = core_io_control_bits[2];
assign T_378 = core_io_control_bits[3];
assign T_379 = core_io_control_bits[4];
assign T_380 = {io_resetCauses_wdogrst,io_resetCauses_erst};
assign T_381 = {T_380,io_resetCauses_porrst};
//assign SRLatch_3_reset = T_385;
//assign SRLatch_3_set = T_382;// POR
assign T_382 = T_381[0];// The POR
assign T_383 = T_381[1];// The ERST
assign T_384 = T_381[2];// The WDOG
assign T_385 = T_383 | T_384;
//assign SRLatch_1_1_reset = T_389;
//assign SRLatch_1_1_set = T_383;// ERST
assign T_389 = T_382 | T_384;
//assign SRLatch_2_1_reset = T_393;
//assign SRLatch_2_1_set = T_384;// WDOG
assign T_393 = T_382 | T_383;
//assign T_394 = {SRLatch_2_1_q,SRLatch_1_1_q};
//Bob assign T_395 = {T_394,SRLatch_3_q};
assign T_394 = {rstcause_wdog_r,rstcause_erst_r};
assign T_395 = {T_394,rstcause_por_r};
assign T_396 = T_395[2];
assign T_397 = T_395[1:0];
assign GEN_0 = {{1'd0}, T_396};
assign T_400 = GEN_0 | T_397;
assign T_401 = T_400[1];
assign T_402 = {T_396,T_401};
//Bob: The original code is here
//always @(posedge clock) begin
// T_355 <= reset;
// T_356 <= T_355;
//end
//Bob: Why here need to flop the reset twice? this is not allowed in coding style so just comment it out
always @(posedge clock or posedge reset) begin
if(reset) begin
T_355 <= 1'b1;
T_356 <= T_355;
end
else begin
T_355 <= 1'b0;
T_356 <= T_355;
end
end
endmodule |
module sirv_hclkgen_regs(
input clk,
input rst_n,
output pllbypass ,
output pll_RESET ,
output pll_ASLEEP ,
output [1:0] pll_OD,
output [7:0] pll_M,
output [4:0] pll_N,
output plloutdivby1,
output [5:0] plloutdiv,
output hfxoscen,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [12-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata
);
// Directly connect the command channel with response channel
assign i_icb_rsp_valid = i_icb_cmd_valid;
assign i_icb_cmd_ready = i_icb_rsp_ready;
wire icb_wr_en = i_icb_cmd_valid & i_icb_cmd_ready & (~i_icb_cmd_read);
wire [32-1:0] icb_wdata = i_icb_cmd_wdata;
wire [32-1:0] hfxosccfg_r;
wire [32-1:0] pllcfg_r;
wire [32-1:0] plloutdiv_r;
// Addr selection
wire sel_hfxosccfg = (i_icb_cmd_addr == 12'h004);
wire sel_pllcfg = (i_icb_cmd_addr == 12'h008);
wire sel_plloutdiv = (i_icb_cmd_addr == 12'h00C);
wire icb_wr_en_hfxosccfg = icb_wr_en & sel_hfxosccfg ;
wire icb_wr_en_pllcfg = icb_wr_en & sel_pllcfg ;
wire icb_wr_en_plloutdiv = icb_wr_en & sel_plloutdiv ;
assign i_icb_rsp_rdata =
({32{sel_hfxosccfg}} & hfxosccfg_r)
| ({32{sel_pllcfg }} & pllcfg_r )
| ({32{sel_plloutdiv}} & plloutdiv_r);
/////////////////////////////////////////////////////////////////////////////////////////
// HFXOSCCFG
wire hfxoscen_ena = icb_wr_en_hfxosccfg;
// The reset value is 1
sirv_gnrl_dfflrs #(1) hfxoscen_dfflrs (hfxoscen_ena, icb_wdata[30], hfxoscen, clk, rst_n);
assign hfxosccfg_r = {1'b0, hfxoscen, 30'b0};
/////////////////////////////////////////////////////////////////////////////////////////
// PLLCFG
//
// N: The reset value is 2 = 5'h2 = 5'b0_0010
sirv_gnrl_dfflr #(3) pll_N_42_dfflr (icb_wr_en_pllcfg, icb_wdata[4:2], pll_N[4:2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_N_1_dfflr (icb_wr_en_pllcfg, icb_wdata[1], pll_N[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_N_0_dfflr (icb_wr_en_pllcfg, icb_wdata[0], pll_N[0], clk, rst_n);
//
// M: The reset value is 50 = 8'h32 = 8'b0011_0010
sirv_gnrl_dfflr #(1) pll_M_7_dfflr (icb_wr_en_pllcfg, icb_wdata[12], pll_M[7], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_6_dfflr (icb_wr_en_pllcfg, icb_wdata[11], pll_M[6], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_5_dfflr (icb_wr_en_pllcfg, icb_wdata[10], pll_M[5], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_4_dfflr (icb_wr_en_pllcfg, icb_wdata[09], pll_M[4], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_3_dfflr (icb_wr_en_pllcfg, icb_wdata[08], pll_M[3], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_2_dfflr (icb_wr_en_pllcfg, icb_wdata[07], pll_M[2], clk, rst_n);
sirv_gnrl_dfflrs#(1) pll_M_1_dfflr (icb_wr_en_pllcfg, icb_wdata[06], pll_M[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_M_0_dfflr (icb_wr_en_pllcfg, icb_wdata[05], pll_M[0], clk, rst_n);
// OD: The reset value is 2 = 2'b10
sirv_gnrl_dfflrs #(1) pll_OD_1_dfflrs(icb_wr_en_pllcfg, icb_wdata[14], pll_OD[1], clk, rst_n);
sirv_gnrl_dfflr #(1) pll_OD_0_dfflr (icb_wr_en_pllcfg, icb_wdata[13], pll_OD[0], clk, rst_n);
// Bypass: The reset value is 1
sirv_gnrl_dfflrs #(1) pllbypass_dfflrs (icb_wr_en_pllcfg, icb_wdata[18], pllbypass, clk, rst_n);
// RESET: The reset value is 0
sirv_gnrl_dfflr #(1) pll_RESET_dfflrs (icb_wr_en_pllcfg, icb_wdata[30], pll_RESET, clk, rst_n);
// ASLEEP: The asleep value is 0
sirv_gnrl_dfflr #(1) pll_ASLEEP_dfflrs (icb_wr_en_pllcfg, icb_wdata[29], pll_ASLEEP, clk, rst_n);
assign pllcfg_r[31] = 1'b0;
assign pllcfg_r[30] = pll_RESET;
assign pllcfg_r[29] = pll_ASLEEP;
assign pllcfg_r[28:19] = 10'b0;
assign pllcfg_r[18] = pllbypass;
assign pllcfg_r[17:15] = 3'b0;
assign pllcfg_r[14:13] = pll_OD;
assign pllcfg_r[12:5] = pll_M;
assign pllcfg_r[4:0] = pll_N;
/////////////////////////////////////////////////////////////////////////////////////////
// PLLOUTDIV
//
wire plloutdiv_ena = icb_wr_en_plloutdiv;
sirv_gnrl_dfflr #(6) plloutdiv_dfflr (plloutdiv_ena, icb_wdata[5:0], plloutdiv, clk, rst_n);
wire plloutdivby1_ena = icb_wr_en_plloutdiv;
// The reset value is 1
sirv_gnrl_dfflrs #(1) plloutdivby1_dfflrs (plloutdivby1_ena, icb_wdata[8], plloutdivby1, clk, rst_n);
assign plloutdiv_r[31:9] = 23'b0;
assign plloutdiv_r[8] = plloutdivby1;
assign plloutdiv_r[7:6] = 2'b0;
assign plloutdiv_r[5:0] = plloutdiv;
endmodule |
module sirv_rtc(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [31:0] io_regs_s_write_bits,
output [31:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [31:0] io_regs_cmp_0_write_bits,
output [31:0] io_regs_cmp_0_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0
);
wire [3:0] T_134;
reg [3:0] scale;
reg [31:0] GEN_7;
wire [3:0] GEN_0;
reg [31:0] cmp_0;
reg [31:0] GEN_8;
wire [31:0] GEN_1;
wire T_141;
wire AsyncResetRegVec_1_clock;
wire AsyncResetRegVec_1_reset;
wire AsyncResetRegVec_1_io_d;
wire AsyncResetRegVec_1_io_q;
wire AsyncResetRegVec_1_io_en;
wire countAlways;
reg [5:0] T_145;
reg [31:0] GEN_10;
wire [5:0] GEN_9;
wire [6:0] T_146;
reg [41:0] T_148;
reg [63:0] GEN_11;
wire T_149;
wire [42:0] T_151;
wire [42:0] GEN_2;
wire [47:0] T_152;
wire [15:0] T_155;
wire [47:0] T_156;
wire [41:0] T_157;
wire [47:0] GEN_3;
wire [42:0] GEN_4;
wire [31:0] T_160;
wire [63:0] T_161;
wire [57:0] T_162;
wire [63:0] GEN_5;
wire [57:0] GEN_6;
wire [47:0] T_163;
wire [31:0] s;
wire elapsed_0;
reg ip;
reg [31:0] GEN_12;
wire [8:0] T_191;
wire [11:0] T_194;
wire [3:0] T_196;
wire [4:0] T_198;
wire [12:0] T_199;
wire [16:0] T_200;
wire [28:0] T_201;
wire T_207_0;
sirv_AsyncResetRegVec AsyncResetRegVec_1 (
.clock(AsyncResetRegVec_1_clock),
.reset(AsyncResetRegVec_1_reset),
.io_d(AsyncResetRegVec_1_io_d),
.io_q(AsyncResetRegVec_1_io_q),
.io_en(AsyncResetRegVec_1_io_en)
);
assign io_regs_cfg_read = {{3'd0}, T_201};
assign io_regs_countLo_read = T_152[31:0];
assign io_regs_countHi_read = {{16'd0}, T_155};
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_207_0;
assign T_134 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_134 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign T_141 = io_regs_cfg_write_bits[12];
assign AsyncResetRegVec_1_clock = clock;
assign AsyncResetRegVec_1_reset = reset;
assign AsyncResetRegVec_1_io_d = T_141;
assign AsyncResetRegVec_1_io_en = io_regs_cfg_write_valid;
assign countAlways = AsyncResetRegVec_1_io_q;
assign GEN_9 = {{5'd0}, countAlways};
assign T_146 = T_145 + GEN_9;
assign T_149 = T_146[6];
assign T_151 = T_148 + 42'h1;
assign GEN_2 = T_149 ? T_151 : {{1'd0}, T_148};
assign T_152 = {T_148,T_145};
assign T_155 = T_152[47:32];
assign T_156 = {T_155,io_regs_countLo_write_bits};
assign T_157 = T_156[47:6];
assign GEN_3 = io_regs_countLo_write_valid ? T_156 : {{41'd0}, T_146};
assign GEN_4 = io_regs_countLo_write_valid ? {{1'd0}, T_157} : GEN_2;
assign T_160 = T_152[31:0];
assign T_161 = {io_regs_countHi_write_bits,T_160};
assign T_162 = T_161[63:6];
assign GEN_5 = io_regs_countHi_write_valid ? T_161 : {{16'd0}, GEN_3};
assign GEN_6 = io_regs_countHi_write_valid ? T_162 : {{15'd0}, GEN_4};
assign T_163 = T_152 >> scale;
assign s = T_163[31:0];
assign elapsed_0 = s >= cmp_0;
assign T_191 = {5'h0,scale};
assign T_194 = {3'h0,T_191};
assign T_196 = {3'h0,countAlways};
assign T_198 = {ip,4'h0};
assign T_199 = {T_198,8'h0};
assign T_200 = {T_199,T_196};
assign T_201 = {T_200,T_194};
assign T_207_0 = ip;
always @(posedge clock or posedge reset) begin
if(reset) begin
scale <= 4'b0;
cmp_0 <= 32'hFFFF_FFFF;
T_145 <= 6'b0;
T_148 <= 42'b0;
ip <= 1'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_134;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
T_145 <= GEN_5[5:0];
T_148 <= GEN_6[41:0];
ip <= elapsed_0;
end
end
endmodule |
module sirv_qspi_physical_1(
input clock,
input reset,
output io_port_sck,
input io_port_dq_0_i,
output io_port_dq_0_o,
output io_port_dq_0_oe,
input io_port_dq_1_i,
output io_port_dq_1_o,
output io_port_dq_1_oe,
input io_port_dq_2_i,
output io_port_dq_2_o,
output io_port_dq_2_oe,
input io_port_dq_3_i,
output io_port_dq_3_o,
output io_port_dq_3_oe,
output io_port_cs_0,
output io_port_cs_1,
output io_port_cs_2,
output io_port_cs_3,
input [11:0] io_ctrl_sck_div,
input io_ctrl_sck_pol,
input io_ctrl_sck_pha,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
output io_op_ready,
input io_op_valid,
input io_op_bits_fn,
input io_op_bits_stb,
input [7:0] io_op_bits_cnt,
input [7:0] io_op_bits_data,
output io_rx_valid,
output [7:0] io_rx_bits
);
reg [11:0] ctrl_sck_div;
reg [31:0] GEN_2;
reg ctrl_sck_pol;
reg [31:0] GEN_31;
reg ctrl_sck_pha;
reg [31:0] GEN_52;
reg [1:0] ctrl_fmt_proto;
reg [31:0] GEN_67;
reg ctrl_fmt_endian;
reg [31:0] GEN_68;
reg ctrl_fmt_iodir;
reg [31:0] GEN_69;
wire proto_0;
wire proto_1;
wire proto_2;
wire accept;
wire sample;
wire setup;
wire last;
reg setup_d;
reg [31:0] GEN_70;
reg T_119;
reg [31:0] GEN_71;
reg T_120;
reg [31:0] GEN_72;
reg sample_d;
reg [31:0] GEN_73;
reg T_122;
reg [31:0] GEN_74;
reg T_123;
reg [31:0] GEN_75;
reg last_d;
reg [31:0] GEN_76;
reg [7:0] scnt;
reg [31:0] GEN_77;
reg [11:0] tcnt;
reg [31:0] GEN_78;
wire stop;
wire beat;
wire [11:0] T_127;
wire [12:0] T_129;
wire [11:0] decr;
wire sched;
wire [11:0] T_130;
reg sck;
reg [31:0] GEN_79;
reg cref;
reg [31:0] GEN_80;
wire cinv;
wire [1:0] T_133;
wire [1:0] T_134;
wire [3:0] rxd;
wire samples_0;
wire [1:0] samples_1;
reg [7:0] buffer;
reg [31:0] GEN_81;
wire T_135;
wire T_136;
wire T_137;
wire T_138;
wire T_139;
wire T_140;
wire T_141;
wire T_142;
wire T_143;
wire [1:0] T_144;
wire [1:0] T_145;
wire [3:0] T_146;
wire [1:0] T_147;
wire [1:0] T_148;
wire [3:0] T_149;
wire [7:0] T_150;
wire [7:0] buffer_in;
wire T_151;
wire shift;
wire [6:0] T_152;
wire [6:0] T_153;
wire [6:0] T_154;
wire T_155;
wire T_157;
wire [7:0] T_158;
wire [5:0] T_159;
wire [5:0] T_160;
wire [5:0] T_161;
wire [1:0] T_162;
wire [1:0] T_163;
wire [7:0] T_164;
wire [3:0] T_165;
wire [3:0] T_166;
wire [3:0] T_167;
wire [3:0] T_169;
wire [7:0] T_170;
wire [7:0] T_172;
wire [7:0] T_174;
wire [7:0] T_176;
wire [7:0] T_178;
wire [7:0] T_179;
wire [7:0] T_180;
reg [3:0] txd;
reg [31:0] GEN_82;
wire [3:0] T_182;
wire [3:0] txd_in;
wire [1:0] T_184;
wire txd_sel_0;
wire txd_sel_1;
wire txd_sel_2;
wire txd_shf_0;
wire [1:0] txd_shf_1;
wire T_186;
wire [1:0] T_188;
wire [3:0] T_190;
wire [1:0] GEN_65;
wire [1:0] T_192;
wire [3:0] GEN_66;
wire [3:0] T_193;
wire [3:0] T_194;
wire [3:0] GEN_0;
wire T_195;
wire T_196;
wire txen_1;
wire txen_0;
wire T_208_0;
wire T_208_1;
wire T_208_2;
wire T_208_3;
wire T_215;
wire T_216;
wire T_217;
wire T_218;
reg done;
reg [31:0] GEN_83;
wire T_221;
wire T_222;
wire T_224;
wire T_225;
wire T_226;
wire T_227;
wire T_228;
wire T_229;
wire T_230;
wire [1:0] T_231;
wire [1:0] T_232;
wire [3:0] T_233;
wire [1:0] T_234;
wire [1:0] T_235;
wire [3:0] T_236;
wire [7:0] T_237;
wire [7:0] T_238;
reg xfr;
reg [31:0] GEN_84;
wire GEN_1;
wire T_243;
wire T_245;
wire T_246;
wire GEN_3;
wire GEN_4;
wire GEN_5;
wire [11:0] GEN_6;
wire GEN_7;
wire GEN_8;
wire GEN_9;
wire GEN_10;
wire [11:0] GEN_11;
wire GEN_12;
wire GEN_13;
wire GEN_14;
wire GEN_15;
wire [11:0] GEN_16;
wire T_252;
wire T_253;
wire T_254;
wire T_257;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire T_260;
wire [1:0] GEN_24;
wire GEN_25;
wire GEN_26;
wire T_263;
wire T_266;
wire [7:0] GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_32;
wire [11:0] GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire [11:0] GEN_37;
wire GEN_38;
wire GEN_39;
wire [11:0] GEN_40;
wire [1:0] GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire [7:0] GEN_45;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire [11:0] GEN_49;
wire GEN_50;
wire GEN_51;
wire [11:0] GEN_53;
wire [1:0] GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire [7:0] GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire [11:0] GEN_62;
wire GEN_63;
wire GEN_64;
assign io_port_sck = sck;
assign io_port_dq_0_o = T_215;
assign io_port_dq_0_oe = txen_0;
assign io_port_dq_1_o = T_216;
assign io_port_dq_1_oe = txen_1;
assign io_port_dq_2_o = T_217;
assign io_port_dq_2_oe = T_196;
assign io_port_dq_3_o = T_218;
assign io_port_dq_3_oe = 1'h0;
assign io_port_cs_0 = T_208_0;
assign io_port_cs_1 = T_208_1;
assign io_port_cs_2 = T_208_2;
assign io_port_cs_3 = T_208_3;
assign io_op_ready = T_260;
assign io_rx_valid = done;
assign io_rx_bits = T_238;
assign proto_0 = 2'h0 == ctrl_fmt_proto;
assign proto_1 = 2'h1 == ctrl_fmt_proto;
assign proto_2 = 2'h2 == ctrl_fmt_proto;
assign accept = GEN_21;
assign sample = GEN_14;
assign setup = GEN_60;
assign last = GEN_20;
assign stop = scnt == 8'h0;
assign beat = tcnt == 12'h0;
assign T_127 = beat ? {{4'd0}, scnt} : tcnt;
assign T_129 = T_127 - 12'h1;
assign decr = T_129[11:0];
assign sched = GEN_1;
assign T_130 = sched ? ctrl_sck_div : decr;
assign cinv = ctrl_sck_pha ^ ctrl_sck_pol;
assign T_133 = {io_port_dq_1_i,io_port_dq_0_i};
assign T_134 = {io_port_dq_3_i,io_port_dq_2_i};
assign rxd = {T_134,T_133};
assign samples_0 = rxd[1];
assign samples_1 = rxd[1:0];
assign T_135 = io_ctrl_fmt_endian == 1'h0;
assign T_136 = io_op_bits_data[0];
assign T_137 = io_op_bits_data[1];
assign T_138 = io_op_bits_data[2];
assign T_139 = io_op_bits_data[3];
assign T_140 = io_op_bits_data[4];
assign T_141 = io_op_bits_data[5];
assign T_142 = io_op_bits_data[6];
assign T_143 = io_op_bits_data[7];
assign T_144 = {T_142,T_143};
assign T_145 = {T_140,T_141};
assign T_146 = {T_145,T_144};
assign T_147 = {T_138,T_139};
assign T_148 = {T_136,T_137};
assign T_149 = {T_148,T_147};
assign T_150 = {T_149,T_146};
assign buffer_in = T_135 ? io_op_bits_data : T_150;
assign T_151 = sample_d & stop;
assign shift = setup_d | T_151;
assign T_152 = buffer[6:0];
assign T_153 = buffer[7:1];
assign T_154 = shift ? T_152 : T_153;
assign T_155 = buffer[0];
assign T_157 = sample_d ? samples_0 : T_155;
assign T_158 = {T_154,T_157};
assign T_159 = buffer[5:0];
assign T_160 = buffer[7:2];
assign T_161 = shift ? T_159 : T_160;
assign T_162 = buffer[1:0];
assign T_163 = sample_d ? samples_1 : T_162;
assign T_164 = {T_161,T_163};
assign T_165 = buffer[3:0];
assign T_166 = buffer[7:4];
assign T_167 = shift ? T_165 : T_166;
assign T_169 = sample_d ? rxd : T_165;
assign T_170 = {T_167,T_169};
assign T_172 = proto_0 ? T_158 : 8'h0;
assign T_174 = proto_1 ? T_164 : 8'h0;
assign T_176 = proto_2 ? T_170 : 8'h0;
assign T_178 = T_172 | T_174;
assign T_179 = T_178 | T_176;
assign T_180 = T_179;
assign T_182 = buffer_in[7:4];
assign txd_in = accept ? T_182 : T_166;
assign T_184 = accept ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign txd_sel_0 = 2'h0 == T_184;
assign txd_sel_1 = 2'h1 == T_184;
assign txd_sel_2 = 2'h2 == T_184;
assign txd_shf_0 = txd_in[3];
assign txd_shf_1 = txd_in[3:2];
assign T_186 = txd_sel_0 ? txd_shf_0 : 1'h0;
assign T_188 = txd_sel_1 ? txd_shf_1 : 2'h0;
assign T_190 = txd_sel_2 ? txd_in : 4'h0;
assign GEN_65 = {{1'd0}, T_186};
assign T_192 = GEN_65 | T_188;
assign GEN_66 = {{2'd0}, T_192};
assign T_193 = GEN_66 | T_190;
assign T_194 = T_193;
assign GEN_0 = setup ? T_194 : txd;
assign T_195 = proto_1 & ctrl_fmt_iodir;
assign T_196 = proto_2 & ctrl_fmt_iodir;
assign txen_1 = T_195 | T_196;
assign txen_0 = proto_0 | txen_1;
assign T_208_0 = 1'h1;
assign T_208_1 = 1'h1;
assign T_208_2 = 1'h1;
assign T_208_3 = 1'h1;
assign T_215 = txd[0];
assign T_216 = txd[1];
assign T_217 = txd[2];
assign T_218 = txd[3];
assign T_221 = done | last_d;
assign T_222 = ctrl_fmt_endian == 1'h0;
assign T_224 = buffer[1];
assign T_225 = buffer[2];
assign T_226 = buffer[3];
assign T_227 = buffer[4];
assign T_228 = buffer[5];
assign T_229 = buffer[6];
assign T_230 = buffer[7];
assign T_231 = {T_229,T_230};
assign T_232 = {T_227,T_228};
assign T_233 = {T_232,T_231};
assign T_234 = {T_225,T_226};
assign T_235 = {T_155,T_224};
assign T_236 = {T_235,T_234};
assign T_237 = {T_236,T_233};
assign T_238 = T_222 ? buffer : T_237;
assign GEN_1 = stop ? 1'h1 : beat;
assign T_243 = stop == 1'h0;
assign T_245 = cref == 1'h0;
assign T_246 = cref ^ cinv;
assign GEN_3 = xfr ? T_246 : sck;
assign GEN_4 = xfr ? cref : 1'h0;
assign GEN_5 = xfr ? T_245 : 1'h0;
assign GEN_6 = T_245 ? decr : {{4'd0}, scnt};
assign GEN_7 = beat ? T_245 : cref;
assign GEN_8 = beat ? GEN_3 : sck;
assign GEN_9 = beat ? GEN_4 : 1'h0;
assign GEN_10 = beat ? GEN_5 : 1'h0;
assign GEN_11 = beat ? GEN_6 : {{4'd0}, scnt};
assign GEN_12 = T_243 ? GEN_7 : cref;
assign GEN_13 = T_243 ? GEN_8 : sck;
assign GEN_14 = T_243 ? GEN_9 : 1'h0;
assign GEN_15 = T_243 ? GEN_10 : 1'h0;
assign GEN_16 = T_243 ? GEN_11 : {{4'd0}, scnt};
assign T_252 = scnt == 8'h1;
assign T_253 = beat & cref;
assign T_254 = T_253 & xfr;
assign T_257 = beat & T_245;
assign GEN_17 = T_257 ? 1'h1 : stop;
assign GEN_18 = T_257 ? 1'h0 : GEN_15;
assign GEN_19 = T_257 ? ctrl_sck_pol : GEN_13;
assign GEN_20 = T_252 ? T_254 : 1'h0;
assign GEN_21 = T_252 ? GEN_17 : stop;
assign GEN_22 = T_252 ? GEN_18 : GEN_15;
assign GEN_23 = T_252 ? GEN_19 : GEN_13;
assign T_260 = accept & done;
assign GEN_24 = io_op_bits_stb ? io_ctrl_fmt_proto : ctrl_fmt_proto;
assign GEN_25 = io_op_bits_stb ? io_ctrl_fmt_endian : ctrl_fmt_endian;
assign GEN_26 = io_op_bits_stb ? io_ctrl_fmt_iodir : ctrl_fmt_iodir;
assign T_263 = 1'h0 == io_op_bits_fn;
assign T_266 = io_op_bits_cnt == 8'h0;
assign GEN_27 = T_263 ? buffer_in : T_180;
assign GEN_28 = T_263 ? cinv : GEN_23;
assign GEN_29 = T_263 ? 1'h1 : GEN_22;
assign GEN_30 = T_263 ? T_266 : T_221;
assign GEN_32 = io_op_bits_stb ? io_ctrl_sck_pol : GEN_28;
assign GEN_33 = io_op_bits_stb ? io_ctrl_sck_div : ctrl_sck_div;
assign GEN_34 = io_op_bits_stb ? io_ctrl_sck_pol : ctrl_sck_pol;
assign GEN_35 = io_op_bits_stb ? io_ctrl_sck_pha : ctrl_sck_pha;
assign GEN_36 = io_op_bits_fn ? GEN_32 : GEN_28;
assign GEN_37 = io_op_bits_fn ? GEN_33 : ctrl_sck_div;
assign GEN_38 = io_op_bits_fn ? GEN_34 : ctrl_sck_pol;
assign GEN_39 = io_op_bits_fn ? GEN_35 : ctrl_sck_pha;
assign GEN_40 = io_op_valid ? {{4'd0}, io_op_bits_cnt} : GEN_16;
assign GEN_41 = io_op_valid ? GEN_24 : ctrl_fmt_proto;
assign GEN_42 = io_op_valid ? GEN_25 : ctrl_fmt_endian;
assign GEN_43 = io_op_valid ? GEN_26 : ctrl_fmt_iodir;
assign GEN_44 = io_op_valid ? T_263 : xfr;
assign GEN_45 = io_op_valid ? GEN_27 : T_180;
assign GEN_46 = io_op_valid ? GEN_36 : GEN_23;
assign GEN_47 = io_op_valid ? GEN_29 : GEN_22;
assign GEN_48 = io_op_valid ? GEN_30 : T_221;
assign GEN_49 = io_op_valid ? GEN_37 : ctrl_sck_div;
assign GEN_50 = io_op_valid ? GEN_38 : ctrl_sck_pol;
assign GEN_51 = io_op_valid ? GEN_39 : ctrl_sck_pha;
assign GEN_53 = T_260 ? GEN_40 : GEN_16;
assign GEN_54 = T_260 ? GEN_41 : ctrl_fmt_proto;
assign GEN_55 = T_260 ? GEN_42 : ctrl_fmt_endian;
assign GEN_56 = T_260 ? GEN_43 : ctrl_fmt_iodir;
assign GEN_57 = T_260 ? GEN_44 : xfr;
assign GEN_58 = T_260 ? GEN_45 : T_180;
assign GEN_59 = T_260 ? GEN_46 : GEN_23;
assign GEN_60 = T_260 ? GEN_47 : GEN_22;
assign GEN_61 = T_260 ? GEN_48 : T_221;
assign GEN_62 = T_260 ? GEN_49 : ctrl_sck_div;
assign GEN_63 = T_260 ? GEN_50 : ctrl_sck_pol;
assign GEN_64 = T_260 ? GEN_51 : ctrl_sck_pha;
always @(posedge clock or posedge reset)
if (reset) begin
ctrl_sck_div <= 12'b0;
ctrl_sck_pol <= 1'b0;
ctrl_sck_pha <= 1'b0;
ctrl_fmt_proto <= 2'b0;
ctrl_fmt_endian <= 1'b0;
ctrl_fmt_iodir <= 1'b0;
setup_d <= 1'b0;
tcnt <= 12'b0;
sck <= 1'b0;
buffer <= 8'b0;
xfr <= 1'b0;
end
else begin
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_div <= io_ctrl_sck_div;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pol <= io_ctrl_sck_pol;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
ctrl_sck_pha <= io_ctrl_sck_pha;
end
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_proto <= io_ctrl_fmt_proto;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_endian <= io_ctrl_fmt_endian;
end
end
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_stb) begin
ctrl_fmt_iodir <= io_ctrl_fmt_iodir;
end
end
end
setup_d <= setup;
if (sched) begin
tcnt <= ctrl_sck_div;
end else begin
tcnt <= decr;
end
if (T_260) begin
if (io_op_valid) begin
if (io_op_bits_fn) begin
if (io_op_bits_stb) begin
sck <= io_ctrl_sck_pol;
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_263) begin
sck <= cinv;
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end else begin
if (T_243) begin
if (beat) begin
if (xfr) begin
sck <= T_246;
end
end
end
end
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
end else begin
if (T_252) begin
if (T_257) begin
sck <= ctrl_sck_pol;
end else begin
sck <= GEN_13;
end
end else begin
sck <= GEN_13;
end
end
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
if (T_135) begin
buffer <= io_op_bits_data;
end else begin
buffer <= T_150;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
end else begin
buffer <= T_180;
end
if (T_260) begin
if (io_op_valid) begin
xfr <= T_263;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cref <= 1'h1;
end else begin
if (T_243) begin
if (beat) begin
cref <= T_245;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
txd <= 4'h0;
end else begin
if (setup) begin
txd <= T_194;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
done <= 1'h1;
end else begin
if (T_260) begin
if (io_op_valid) begin
if (T_263) begin
done <= T_266;
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end else begin
done <= T_221;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
T_119 <= 1'h0;
end else begin
T_119 <= sample;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_120 <= 1'h0;
end else begin
T_120 <= T_119;
end
always @(posedge clock or posedge reset)
if (reset) begin
sample_d <= 1'h0;
end else begin
sample_d <= T_120;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_122 <= 1'h0;
end else begin
T_122 <= last;
end
always @(posedge clock or posedge reset)
if (reset) begin
T_123 <= 1'h0;
end else begin
T_123 <= T_122;
end
always @(posedge clock or posedge reset)
if (reset) begin
last_d <= 1'h0;
end else begin
last_d <= T_123;
end
always @(posedge clock or posedge reset)
if (reset) begin
scnt <= 8'h0;
end else begin
scnt <= GEN_53[7:0];
end
endmodule |
module e203_clkgate (
input clk_in,
input test_mode,
input clock_en,
output clk_out
);
`ifdef FPGA_SOURCE//{
// In the FPGA, the clock gating is just pass through
assign clk_out = clk_in;
`endif//}
`ifndef FPGA_SOURCE//{
reg enb;
always@(*)
if (!clk_in)
enb = (clock_en | test_mode);
assign clk_out = enb & clk_in;
`endif//}
endmodule |
module e203_subsys_pll(
input pll_asleep, // The asleep signal to PLL to power down it
input pllrefclk, // The reference clock into PLL
output plloutclk, // The PLL generated clock
input pll_RESET,
input [1:0] pll_OD,
input [7:0] pll_M,
input [4:0] pll_N
);
wire pllout;
`ifdef FPGA_SOURCE//{
// In FPGA, we have no PLL, so just diretly let it pass through
assign pllout = pllrefclk;
`else //}{
assign pllout = pllrefclk;
`endif//}
assign plloutclk = pllout;
endmodule |
module sirv_uarttx(
input clock,
input reset,
input io_en,
output io_in_ready,
input io_in_valid,
input [7:0] io_in_bits,
output io_out,
input [15:0] io_div,
input io_nstop
);
reg [15:0] prescaler;
reg [31:0] GEN_6;
wire pulse;
reg [3:0] counter;
reg [31:0] GEN_7;
reg [8:0] shifter;
reg [31:0] GEN_8;
reg out;
reg [31:0] GEN_9;
wire busy;
wire T_32;
wire T_33;
wire T_34;
wire T_36;
wire [8:0] T_38;
wire T_40;
wire [3:0] T_46;
wire [3:0] T_48;
wire [3:0] T_50;
wire [3:0] T_51;
wire [8:0] GEN_0;
wire [3:0] GEN_1;
wire [16:0] T_53;
wire [15:0] T_54;
wire [15:0] T_55;
wire [15:0] GEN_2;
wire T_56;
wire [4:0] T_58;
wire [3:0] T_59;
wire [7:0] T_61;
wire [8:0] T_62;
wire T_63;
wire [3:0] GEN_3;
wire [8:0] GEN_4;
wire GEN_5;
assign io_in_ready = T_33;
assign io_out = out;
assign pulse = prescaler == 16'h0;
assign busy = counter != 4'h0;
assign T_32 = busy == 1'h0;
assign T_33 = io_en & T_32;
assign T_34 = io_in_ready & io_in_valid;
assign T_36 = reset == 1'h0;
assign T_38 = {io_in_bits,1'h0};
assign T_40 = io_nstop == 1'h0;
assign T_46 = T_40 ? 4'ha : 4'h0;
assign T_48 = io_nstop ? 4'hb : 4'h0;
assign T_50 = T_46 | T_48;
assign T_51 = T_50;
assign GEN_0 = T_34 ? T_38 : shifter;
assign GEN_1 = T_34 ? T_51 : counter;
assign T_53 = prescaler - 16'h1;
assign T_54 = T_53[15:0];
assign T_55 = pulse ? io_div : T_54;
assign GEN_2 = busy ? T_55 : prescaler;
assign T_56 = pulse & busy;
assign T_58 = counter - 4'h1;
assign T_59 = T_58[3:0];
assign T_61 = shifter[8:1];
assign T_62 = {1'h1,T_61};
assign T_63 = shifter[0];
assign GEN_3 = T_56 ? T_59 : GEN_1;
assign GEN_4 = T_56 ? T_62 : GEN_0;
assign GEN_5 = T_56 ? T_63 : out;
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 16'h0;
end else begin
if (busy) begin
if (pulse) begin
prescaler <= io_div;
end else begin
prescaler <= T_54;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
counter <= 4'h0;
end else begin
if (T_56) begin
counter <= T_59;
end else begin
if (T_34) begin
counter <= T_51;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
shifter <= 9'b0;
end
else begin
if (T_56) begin
shifter <= T_62;
end else begin
if (T_34) begin
shifter <= T_38;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
out <= 1'h1;
end else begin
if (T_56) begin
out <= T_63;
end
end
//`ifndef SYNTHESIS
//`ifdef PRINTF_COND
// if (`PRINTF_COND) begin
//`endif
// if (T_34 & T_36) begin
// $fwrite(32'h80000002,"%c",io_in_bits);
// end
//`ifdef PRINTF_COND
// end
//`endif
//`endif
//synopsys translate_off
always @(posedge clock or posedge reset) begin
if (T_34 & T_36) begin
$fwrite(32'h80000002,"%c",io_in_bits);
end
end
//synopsys translate_on
endmodule |
module sirv_pwm8_core(
input clock,
input reset,
input io_regs_cfg_write_valid,
input [31:0] io_regs_cfg_write_bits,
output [31:0] io_regs_cfg_read,
input io_regs_countLo_write_valid,
input [31:0] io_regs_countLo_write_bits,
output [31:0] io_regs_countLo_read,
input io_regs_countHi_write_valid,
input [31:0] io_regs_countHi_write_bits,
output [31:0] io_regs_countHi_read,
input io_regs_s_write_valid,
input [7:0] io_regs_s_write_bits,
output [7:0] io_regs_s_read,
input io_regs_cmp_0_write_valid,
input [7:0] io_regs_cmp_0_write_bits,
output [7:0] io_regs_cmp_0_read,
input io_regs_cmp_1_write_valid,
input [7:0] io_regs_cmp_1_write_bits,
output [7:0] io_regs_cmp_1_read,
input io_regs_cmp_2_write_valid,
input [7:0] io_regs_cmp_2_write_bits,
output [7:0] io_regs_cmp_2_read,
input io_regs_cmp_3_write_valid,
input [7:0] io_regs_cmp_3_write_bits,
output [7:0] io_regs_cmp_3_read,
input io_regs_feed_write_valid,
input [31:0] io_regs_feed_write_bits,
output [31:0] io_regs_feed_read,
input io_regs_key_write_valid,
input [31:0] io_regs_key_write_bits,
output [31:0] io_regs_key_read,
output io_ip_0,
output io_ip_1,
output io_ip_2,
output io_ip_3,
output io_gpio_0,
output io_gpio_1,
output io_gpio_2,
output io_gpio_3
);
wire [3:0] T_178;
reg [3:0] scale;
reg [31:0] GEN_21;
wire [3:0] GEN_0;
reg [7:0] cmp_0;
reg [31:0] GEN_22;
wire [7:0] GEN_1;
reg [7:0] cmp_1;
reg [31:0] GEN_23;
wire [7:0] GEN_2;
reg [7:0] cmp_2;
reg [31:0] GEN_24;
wire [7:0] GEN_3;
reg [7:0] cmp_3;
reg [31:0] GEN_25;
wire [7:0] GEN_4;
wire countEn;
reg [4:0] T_196;
reg [31:0] GEN_26;
wire [4:0] GEN_18;
wire [5:0] T_197;
reg [17:0] T_199;
reg [31:0] GEN_27;
wire T_200;
wire [18:0] T_202;
wire [18:0] GEN_5;
wire [22:0] T_203;
wire [32:0] T_207;
wire [27:0] T_208;
wire [32:0] GEN_6;
wire [27:0] GEN_7;
wire [22:0] T_209;
wire [7:0] s;
wire T_210;
wire [3:0] T_211;
reg [3:0] center;
reg [31:0] GEN_28;
wire [3:0] GEN_8;
wire T_215;
wire T_216;
wire [7:0] T_217;
wire [7:0] T_218;
wire elapsed_0;
wire T_220;
wire T_221;
wire [7:0] T_223;
wire elapsed_1;
wire T_225;
wire T_226;
wire [7:0] T_228;
wire elapsed_2;
wire T_230;
wire T_231;
wire [7:0] T_233;
wire elapsed_3;
wire [5:0] GEN_19;
wire [5:0] T_234;
wire [4:0] T_235;
wire [18:0] GEN_20;
wire [18:0] T_239;
wire [18:0] T_241;
wire [17:0] T_242;
wire [22:0] T_243;
wire [4:0] T_245;
wire [3:0] T_246;
wire [22:0] T_247;
wire feed;
wire T_248;
reg zerocmp;
reg [31:0] GEN_29;
wire GEN_9;
wire T_252;
wire countReset;
wire [32:0] GEN_10;
wire [27:0] GEN_11;
wire T_255;
reg T_259;
reg [31:0] GEN_30;
wire GEN_12;
wire T_261;
wire T_262;
wire T_263;
reg T_267;
reg [31:0] GEN_31;
wire GEN_13;
wire T_268;
reg T_269;
reg [31:0] GEN_32;
wire [1:0] T_282;
wire [1:0] T_283;
wire [3:0] T_284;
reg [3:0] ip;
reg [31:0] GEN_33;
wire [1:0] T_286;
wire [1:0] T_287;
wire [3:0] T_288;
wire [3:0] T_289;
wire [3:0] T_290;
wire [3:0] T_297;
wire [3:0] T_298;
wire [3:0] T_299;
wire [3:0] T_300;
wire [3:0] T_301;
wire [3:0] T_304;
wire [3:0] GEN_14;
wire [3:0] T_305;
reg [3:0] gang;
reg [31:0] GEN_34;
wire [3:0] GEN_15;
wire T_316;
wire T_319;
wire T_323;
reg oneShot;
reg [31:0] GEN_35;
wire GEN_16;
wire T_325;
reg countAlways;
reg [31:0] GEN_36;
wire GEN_17;
wire [4:0] T_333;
wire [8:0] T_334;
wire [1:0] T_335;
wire [2:0] T_336;
wire [11:0] T_337;
wire [2:0] T_338;
wire [3:0] T_339;
wire [7:0] T_340;
wire [7:0] T_341;
wire [15:0] T_342;
wire [19:0] T_343;
wire [31:0] T_344;
wire T_350_0;
wire T_350_1;
wire T_350_2;
wire T_350_3;
wire T_352;
wire T_353;
wire T_354;
wire T_355;
wire [2:0] T_357;
wire [3:0] T_358;
wire [3:0] T_359;
wire [3:0] T_360;
wire [3:0] T_361;
wire T_364_0;
wire T_364_1;
wire T_364_2;
wire T_364_3;
wire T_366;
wire T_367;
wire T_368;
wire T_369;
wire T_370;
assign io_regs_cfg_read = T_344;
assign io_regs_countLo_read = {{9'd0}, T_203};
assign io_regs_countHi_read = 32'h0;
assign io_regs_s_read = s;
assign io_regs_cmp_0_read = cmp_0;
assign io_regs_cmp_1_read = cmp_1;
assign io_regs_cmp_2_read = cmp_2;
assign io_regs_cmp_3_read = cmp_3;
assign io_regs_feed_read = 32'h0;
assign io_regs_key_read = 32'h1;
assign io_ip_0 = T_350_0;
assign io_ip_1 = T_350_1;
assign io_ip_2 = T_350_2;
assign io_ip_3 = T_350_3;
assign io_gpio_0 = T_364_0;
assign io_gpio_1 = T_364_1;
assign io_gpio_2 = T_364_2;
assign io_gpio_3 = T_364_3;
assign T_178 = io_regs_cfg_write_bits[3:0];
assign GEN_0 = io_regs_cfg_write_valid ? T_178 : scale;
assign GEN_1 = io_regs_cmp_0_write_valid ? io_regs_cmp_0_write_bits : cmp_0;
assign GEN_2 = io_regs_cmp_1_write_valid ? io_regs_cmp_1_write_bits : cmp_1;
assign GEN_3 = io_regs_cmp_2_write_valid ? io_regs_cmp_2_write_bits : cmp_2;
assign GEN_4 = io_regs_cmp_3_write_valid ? io_regs_cmp_3_write_bits : cmp_3;
assign countEn = T_370;
assign GEN_18 = {{4'd0}, countEn};
assign T_197 = T_196 + GEN_18;
assign T_200 = T_197[5];
assign T_202 = T_199 + 18'h1;
assign GEN_5 = T_200 ? T_202 : {{1'd0}, T_199};
assign T_203 = {T_199,T_196};
assign T_207 = {1'h0,io_regs_countLo_write_bits};
assign T_208 = T_207[32:5];
assign GEN_6 = io_regs_countLo_write_valid ? T_207 : {{27'd0}, T_197};
assign GEN_7 = io_regs_countLo_write_valid ? T_208 : {{9'd0}, GEN_5};
assign T_209 = T_203 >> scale;
assign s = T_209[7:0];
assign T_210 = s[7];
assign T_211 = io_regs_cfg_write_bits[19:16];
assign GEN_8 = io_regs_cfg_write_valid ? T_211 : center;
assign T_215 = center[0];
assign T_216 = T_210 & T_215;
assign T_217 = ~ s;
assign T_218 = T_216 ? T_217 : s;
assign elapsed_0 = T_218 >= cmp_0;
assign T_220 = center[1];
assign T_221 = T_210 & T_220;
assign T_223 = T_221 ? T_217 : s;
assign elapsed_1 = T_223 >= cmp_1;
assign T_225 = center[2];
assign T_226 = T_210 & T_225;
assign T_228 = T_226 ? T_217 : s;
assign elapsed_2 = T_228 >= cmp_2;
assign T_230 = center[3];
assign T_231 = T_210 & T_230;
assign T_233 = T_231 ? T_217 : s;
assign elapsed_3 = T_233 >= cmp_3;
assign GEN_19 = {{1'd0}, T_196};
assign T_234 = GEN_19 ^ T_197;
assign T_235 = T_234[5:1];
assign GEN_20 = {{1'd0}, T_199};
assign T_239 = GEN_20 ^ T_202;
assign T_241 = T_200 ? T_239 : 19'h0;
assign T_242 = T_241[18:1];
assign T_243 = {T_242,T_235};
assign T_245 = scale + 4'h8;
assign T_246 = T_245[3:0];
assign T_247 = T_243 >> T_246;
assign feed = T_247[0];
assign T_248 = io_regs_cfg_write_bits[9];
assign GEN_9 = io_regs_cfg_write_valid ? T_248 : zerocmp;
assign T_252 = zerocmp & elapsed_0;
assign countReset = feed | T_252;
assign GEN_10 = countReset ? 33'h0 : GEN_6;
assign GEN_11 = countReset ? 28'h0 : GEN_7;
assign T_255 = io_regs_cfg_write_bits[10];
assign GEN_12 = io_regs_cfg_write_valid ? T_255 : T_259;
assign T_261 = countReset == 1'h0;
assign T_262 = T_259 & T_261;
assign T_263 = io_regs_cfg_write_bits[8];
assign GEN_13 = io_regs_cfg_write_valid ? T_263 : T_267;
assign T_268 = T_262 | T_267;
assign T_282 = {T_221,T_216};
assign T_283 = {T_231,T_226};
assign T_284 = {T_283,T_282};
assign T_286 = {elapsed_1,elapsed_0};
assign T_287 = {elapsed_3,elapsed_2};
assign T_288 = {T_287,T_286};
assign T_289 = T_284 & T_288;
assign T_290 = ~ T_284;
assign T_297 = T_269 ? 4'hf : 4'h0;
assign T_298 = T_297 & ip;
assign T_299 = T_288 | T_298;
assign T_300 = T_290 & T_299;
assign T_301 = T_289 | T_300;
assign T_304 = io_regs_cfg_write_bits[31:28];
assign GEN_14 = io_regs_cfg_write_valid ? T_304 : T_301;
assign T_305 = io_regs_cfg_write_bits[27:24];
assign GEN_15 = io_regs_cfg_write_valid ? T_305 : gang;
assign T_316 = io_regs_cfg_write_bits[13];
assign T_319 = T_316 & T_261;
assign T_323 = io_regs_cfg_write_valid | countReset;
assign GEN_16 = T_323 ? T_319 : oneShot;
assign T_325 = io_regs_cfg_write_bits[12];
assign GEN_17 = io_regs_cfg_write_valid ? T_325 : countAlways;
assign T_333 = {T_267,4'h0};
assign T_334 = {T_333,scale};
assign T_335 = {1'h0,T_259};
assign T_336 = {T_335,zerocmp};
assign T_337 = {T_336,T_334};
assign T_338 = {2'h0,oneShot};
assign T_339 = {T_338,countAlways};
assign T_340 = {4'h0,center};
assign T_341 = {ip,gang};
assign T_342 = {T_341,T_340};
assign T_343 = {T_342,T_339};
assign T_344 = {T_343,T_337};
assign T_350_0 = T_352;
assign T_350_1 = T_353;
assign T_350_2 = T_354;
assign T_350_3 = T_355;
assign T_352 = ip[0];
assign T_353 = ip[1];
assign T_354 = ip[2];
assign T_355 = ip[3];
assign T_357 = ip[3:1];
assign T_358 = {T_352,T_357};
assign T_359 = gang & T_358;
assign T_360 = ~ T_359;
assign T_361 = ip & T_360;
assign T_364_0 = T_366;
assign T_364_1 = T_367;
assign T_364_2 = T_368;
assign T_364_3 = T_369;
assign T_366 = T_361[0];
assign T_367 = T_361[1];
assign T_368 = T_361[2];
assign T_369 = T_361[3];
assign T_370 = countAlways | oneShot;
always @(posedge clock or posedge reset)
if(reset) begin
scale <= 4'b0;
cmp_0 <= 8'b0;
cmp_1 <= 8'b0;
cmp_2 <= 8'b0;
cmp_3 <= 8'b0;
T_196 <= 5'b0;
T_199 <= 18'b0;
center <= 4'b0;
zerocmp <= 1'b0;
T_259 <= 1'b0;
T_267 <= 1'b0;
T_269 <= 1'b0;
ip <= 4'b0;
gang <= 4'b0;
end
else begin
if (io_regs_cfg_write_valid) begin
scale <= T_178;
end
if (io_regs_cmp_0_write_valid) begin
cmp_0 <= io_regs_cmp_0_write_bits;
end
if (io_regs_cmp_1_write_valid) begin
cmp_1 <= io_regs_cmp_1_write_bits;
end
if (io_regs_cmp_2_write_valid) begin
cmp_2 <= io_regs_cmp_2_write_bits;
end
if (io_regs_cmp_3_write_valid) begin
cmp_3 <= io_regs_cmp_3_write_bits;
end
T_196 <= GEN_10[4:0];
T_199 <= GEN_11[17:0];
if (io_regs_cfg_write_valid) begin
center <= T_211;
end
if (io_regs_cfg_write_valid) begin
zerocmp <= T_248;
end
if (io_regs_cfg_write_valid) begin
T_259 <= T_255;
end
if (io_regs_cfg_write_valid) begin
T_267 <= T_263;
end
T_269 <= T_268;
if (io_regs_cfg_write_valid) begin
ip <= T_304;
end else begin
ip <= T_301;
end
if (io_regs_cfg_write_valid) begin
gang <= T_305;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
oneShot <= 1'h0;
end else begin
if (T_323) begin
oneShot <= T_319;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
countAlways <= 1'h0;
end else begin
if (io_regs_cfg_write_valid) begin
countAlways <= T_325;
end
end
endmodule |
module i2c_master_bit_ctrl(
clk, rst, nReset,
clk_cnt, ena, cmd, cmd_ack, busy, al, din, dout,
scl_i, scl_o, scl_oen, sda_i, sda_o, sda_oen
);
//
// inputs & outputs
//
input clk;
input rst;
input nReset;
input ena; // core enable signal
input [15:0] clk_cnt; // clock prescale value
input [3:0] cmd;
output cmd_ack; // command complete acknowledge
reg cmd_ack;
output busy; // i2c bus busy
reg busy;
output al; // i2c bus arbitration lost
reg al;
input din;
output dout;
reg dout;
// I2C lines
input scl_i; // i2c clock line input
output scl_o; // i2c clock line output
output scl_oen; // i2c clock line output enable (active low)
reg scl_oen;
input sda_i; // i2c data line input
output sda_o; // i2c data line output
output sda_oen; // i2c data line output enable (active low)
reg sda_oen;
//
// variable declarations
//
reg sSCL, sSDA; // synchronized SCL and SDA inputs
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
wire slave_wait;
// reg [15:0] cnt = clk_cnt; // clock divider counter (simulation)
reg [15:0] cnt; // clock divider counter (synthesis)
// state machine variable
reg [16:0] c_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= #1 scl_oen;
assign slave_wait = dscl_oen && !sSCL;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if(~nReset)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if (rst)
begin
cnt <= #1 16'h0;
clk_en <= #1 1'b1;
end
else if ( ~|cnt || ~ena)
if (~slave_wait)
begin
cnt <= #1 clk_cnt;
clk_en <= #1 1'b1;
end
else
begin
cnt <= #1 cnt;
clk_en <= #1 1'b0;
end
else
begin
cnt <= #1 cnt - 16'h1;
clk_en <= #1 1'b0;
end
// generate bus status controller
reg dSCL, dSDA;
reg sta_condition;
reg sto_condition;
// synchronize SCL and SDA inputs
// reduce metastability risc
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else if (rst)
begin
sSCL <= #1 1'b1;
sSDA <= #1 1'b1;
dSCL <= #1 1'b1;
dSDA <= #1 1'b1;
end
else
begin
sSCL <= #1 scl_i;
sSDA <= #1 sda_i;
dSCL <= #1 sSCL;
dSDA <= #1 sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else if (rst)
begin
sta_condition <= #1 1'b0;
sto_condition <= #1 1'b0;
end
else
begin
sta_condition <= #1 ~sSDA & dSDA & sSCL;
sto_condition <= #1 sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if(!nReset)
busy <= #1 1'b0;
else if (rst)
busy <= #1 1'b0;
else
busy <= #1 (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= #1 1'b0;
else if (rst)
cmd_stop <= #1 1'b0;
else if (clk_en)
cmd_stop <= #1 cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= #1 1'b0;
else if (rst)
al <= #1 1'b0;
else
al <= #1 (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if(sSCL & ~dSCL)
dout <= #1 sSDA;
// generate statemachine
// nxt_state decoder
parameter [16:0] idle = 17'b0_0000_0000_0000_0000;
parameter [16:0] start_a = 17'b0_0000_0000_0000_0001;
parameter [16:0] start_b = 17'b0_0000_0000_0000_0010;
parameter [16:0] start_c = 17'b0_0000_0000_0000_0100;
parameter [16:0] start_d = 17'b0_0000_0000_0000_1000;
parameter [16:0] start_e = 17'b0_0000_0000_0001_0000;
parameter [16:0] stop_a = 17'b0_0000_0000_0010_0000;
parameter [16:0] stop_b = 17'b0_0000_0000_0100_0000;
parameter [16:0] stop_c = 17'b0_0000_0000_1000_0000;
parameter [16:0] stop_d = 17'b0_0000_0001_0000_0000;
parameter [16:0] rd_a = 17'b0_0000_0010_0000_0000;
parameter [16:0] rd_b = 17'b0_0000_0100_0000_0000;
parameter [16:0] rd_c = 17'b0_0000_1000_0000_0000;
parameter [16:0] rd_d = 17'b0_0001_0000_0000_0000;
parameter [16:0] wr_a = 17'b0_0010_0000_0000_0000;
parameter [16:0] wr_b = 17'b0_0100_0000_0000_0000;
parameter [16:0] wr_c = 17'b0_1000_0000_0000_0000;
parameter [16:0] wr_d = 17'b1_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else if (rst | al)
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b0;
scl_oen <= #1 1'b1;
sda_oen <= #1 1'b1;
sda_chk <= #1 1'b0;
end
else
begin
cmd_ack <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state) // synopsys full_case parallel_case
// idle state
idle:
begin
case (cmd) // synopsys full_case parallel_case
`I2C_CMD_START:
c_state <= #1 start_a;
`I2C_CMD_STOP:
c_state <= #1 stop_a;
`I2C_CMD_WRITE:
c_state <= #1 wr_a;
`I2C_CMD_READ:
c_state <= #1 rd_a;
default:
c_state <= #1 idle;
endcase
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 sda_oen; // keep SDA in same state
sda_chk <= #1 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= #1 start_b;
scl_oen <= #1 scl_oen; // keep SCL in same state
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= #1 start_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= #1 start_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= #1 start_e;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= #1 stop_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b0; // set SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= #1 stop_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= #1 stop_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b0; // keep SDA low
sda_chk <= #1 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // set SDA high
sda_chk <= #1 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= #1 rd_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 1'b1; // tri-state SDA
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= #1 rd_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= #1 rd_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 1'b1; // keep SDA tri-stated
sda_chk <= #1 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= #1 wr_b;
scl_oen <= #1 1'b0; // keep SCL low
sda_oen <= #1 din; // set SDA
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= #1 wr_c;
scl_oen <= #1 1'b1; // set SCL high
sda_oen <= #1 din; // keep SDA
sda_chk <= #1 1'b1; // check SDA output
end
wr_c:
begin
c_state <= #1 wr_d;
scl_oen <= #1 1'b1; // keep SCL high
sda_oen <= #1 din;
sda_chk <= #1 1'b1; // check SDA output
end
wr_d:
begin
c_state <= #1 idle;
cmd_ack <= #1 1'b1;
scl_oen <= #1 1'b0; // set SCL low
sda_oen <= #1 din;
sda_chk <= #1 1'b0; // don't check SDA output (SCL low)
end
endcase
end
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule |
module e203_clk_ctrl (
input clk, // clock
input rst_n, // async reset
input test_mode, // test mode
// The cgstop is coming from CSR (0xBFE mcgstop)'s filed 0
// // This register is our self-defined CSR register to disable the
// automaticall clock gating for CPU logics for debugging purpose
input core_cgstop,
// The Top always on clk and rst
output clk_aon,
input core_ifu_active,
input core_exu_active,
input core_lsu_active,
input core_biu_active,
`ifdef E203_HAS_ITCM
input itcm_active,
output itcm_ls,
`endif
`ifdef E203_HAS_DTCM
input dtcm_active,
output dtcm_ls,
`endif
// The core's clk and rst
output clk_core_ifu,
output clk_core_exu,
output clk_core_lsu,
output clk_core_biu,
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
output clk_itcm,
`endif
`ifdef E203_HAS_DTCM
output clk_dtcm,
`endif
input core_wfi
);
// The CSR control bit CGSTOP will override the automatical clock gating here for special debug purpose
// The IFU is always actively fetching unless it is WFI to override it
wire ifu_clk_en = core_cgstop | (core_ifu_active & (~core_wfi));
// The EXU, LSU and BIU module's clock gating does not need to check
// WFI because it may have request from external agent
// and also, it actually will automactically become inactive regardess
// currently is WFI or not, hence we dont need WFI here
wire exu_clk_en = core_cgstop | (core_exu_active);
wire lsu_clk_en = core_cgstop | (core_lsu_active);
wire biu_clk_en = core_cgstop | (core_biu_active);
e203_clkgate u_ifu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (ifu_clk_en),
.clk_out (clk_core_ifu)
);
e203_clkgate u_exu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (exu_clk_en),
.clk_out (clk_core_exu)
);
e203_clkgate u_lsu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (lsu_clk_en),
.clk_out (clk_core_lsu)
);
e203_clkgate u_biu_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (biu_clk_en),
.clk_out (clk_core_biu)
);
`ifdef E203_HAS_ITCM
// The ITCM and DTCM Ctrl module's clock gating does not need to check
// WFI because it may have request from external agent
// and also, it actually will automactically become inactive regardess
// currently is WFI or not, hence we dont need WFI here
wire itcm_active_r;
sirv_gnrl_dffr #(1)itcm_active_dffr(itcm_active, itcm_active_r, clk, rst_n);
wire itcm_clk_en = core_cgstop | itcm_active | itcm_active_r;
assign itcm_ls = ~itcm_clk_en;
e203_clkgate u_itcm_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (itcm_clk_en),
.clk_out (clk_itcm)
);
`endif
`ifdef E203_HAS_DTCM
wire dtcm_active_r;
sirv_gnrl_dffr #(1)dtcm_active_dffr(dtcm_active, dtcm_active_r, clk, rst_n);
wire dtcm_clk_en = core_cgstop | dtcm_active | dtcm_active_r;
assign dtcm_ls = ~dtcm_clk_en;
e203_clkgate u_dtcm_clkgate(
.clk_in (clk ),
.test_mode(test_mode ),
.clock_en (dtcm_clk_en),
.clk_out (clk_dtcm)
);
`endif
// The Top always on clk and rst
assign clk_aon = clk;
endmodule |
module sirv_debug_ram(
input clk,
input rst_n,
input ram_cs,
input ram_rd,
input [ 3-1:0] ram_addr,
input [32-1:0] ram_wdat,
output [32-1:0] ram_dout
);
wire [31:0] debug_ram_r [0:6];
wire [6:0] ram_wen;
assign ram_dout = debug_ram_r[ram_addr];
genvar i;
generate //{
for (i=0; i<7; i=i+1) begin:debug_ram_gen//{
assign ram_wen[i] = ram_cs & (~ram_rd) & (ram_addr == i) ;
sirv_gnrl_dfflr #(32) ram_dfflr (ram_wen[i], ram_wdat, debug_ram_r[i], clk, rst_n);
end//}
endgenerate//}
endmodule |
module sirv_qspi_fifo(
input clock,
input reset,
input [1:0] io_ctrl_fmt_proto,
input io_ctrl_fmt_endian,
input io_ctrl_fmt_iodir,
input [3:0] io_ctrl_fmt_len,
input [1:0] io_ctrl_cs_mode,
input [3:0] io_ctrl_wm_tx,
input [3:0] io_ctrl_wm_rx,
input io_link_tx_ready,
output io_link_tx_valid,
output [7:0] io_link_tx_bits,
input io_link_rx_valid,
input [7:0] io_link_rx_bits,
output [7:0] io_link_cnt,
output [1:0] io_link_fmt_proto,
output io_link_fmt_endian,
output io_link_fmt_iodir,
output io_link_cs_set,
output io_link_cs_clear,
output io_link_cs_hold,
input io_link_active,
output io_link_lock,
output io_tx_ready,
input io_tx_valid,
input [7:0] io_tx_bits,
input io_rx_ready,
output io_rx_valid,
output [7:0] io_rx_bits,
output io_ip_txwm,
output io_ip_rxwm
);
wire txq_clock;
wire txq_reset;
wire txq_io_enq_ready;
wire txq_io_enq_valid;
wire [7:0] txq_io_enq_bits;
wire txq_io_deq_ready;
wire txq_io_deq_valid;
wire [7:0] txq_io_deq_bits;
wire [3:0] txq_io_count;
wire rxq_clock;
wire rxq_reset;
wire rxq_io_enq_ready;
wire rxq_io_enq_valid;
wire [7:0] rxq_io_enq_bits;
wire rxq_io_deq_ready;
wire rxq_io_deq_valid;
wire [7:0] rxq_io_deq_bits;
wire [3:0] rxq_io_count;
wire fire_tx;
reg rxen;
reg [31:0] GEN_5;
wire T_94;
wire GEN_0;
wire T_96;
wire GEN_1;
wire T_97;
wire T_98;
wire T_99;
wire [2:0] T_101;
wire [1:0] T_102;
wire [3:0] T_104;
wire [2:0] T_106;
wire [1:0] T_108;
wire [3:0] GEN_2;
wire [3:0] T_110;
wire [3:0] GEN_3;
wire [3:0] T_111;
wire [3:0] cnt_quot;
wire T_112;
wire [1:0] T_115;
wire T_117;
wire [2:0] T_118;
wire T_120;
wire T_123;
wire T_126;
wire T_129;
wire T_131;
wire T_132;
wire cnt_rmdr;
wire [3:0] GEN_4;
wire [4:0] T_133;
wire [3:0] T_134;
reg [1:0] cs_mode;
reg [31:0] GEN_6;
wire cs_mode_hold;
wire cs_mode_off;
wire cs_update;
wire T_135;
wire cs_clear;
wire T_138;
wire T_139;
wire T_140;
wire T_142;
wire T_143;
wire T_144;
sirv_queue_1 txq (
.clock(txq_clock),
.reset(txq_reset),
.io_enq_ready(txq_io_enq_ready),
.io_enq_valid(txq_io_enq_valid),
.io_enq_bits(txq_io_enq_bits),
.io_deq_ready(txq_io_deq_ready),
.io_deq_valid(txq_io_deq_valid),
.io_deq_bits(txq_io_deq_bits),
.io_count(txq_io_count)
);
sirv_queue_1 rxq (
.clock(rxq_clock),
.reset(rxq_reset),
.io_enq_ready(rxq_io_enq_ready),
.io_enq_valid(rxq_io_enq_valid),
.io_enq_bits(rxq_io_enq_bits),
.io_deq_ready(rxq_io_deq_ready),
.io_deq_valid(rxq_io_deq_valid),
.io_deq_bits(rxq_io_deq_bits),
.io_count(rxq_io_count)
);
assign io_link_tx_valid = txq_io_deq_valid;
assign io_link_tx_bits = txq_io_deq_bits;
assign io_link_cnt = {{4'd0}, T_134};
assign io_link_fmt_proto = io_ctrl_fmt_proto;
assign io_link_fmt_endian = io_ctrl_fmt_endian;
assign io_link_fmt_iodir = io_ctrl_fmt_iodir;
assign io_link_cs_set = T_138;
assign io_link_cs_clear = T_140;
assign io_link_cs_hold = 1'h0;
assign io_link_lock = T_142;
assign io_tx_ready = txq_io_enq_ready;
assign io_rx_valid = rxq_io_deq_valid;
assign io_rx_bits = rxq_io_deq_bits;
assign io_ip_txwm = T_143;
assign io_ip_rxwm = T_144;
assign txq_clock = clock;
assign txq_reset = reset;
assign txq_io_enq_valid = io_tx_valid;
assign txq_io_enq_bits = io_tx_bits;
assign txq_io_deq_ready = io_link_tx_ready;
assign rxq_clock = clock;
assign rxq_reset = reset;
assign rxq_io_enq_valid = T_94;
assign rxq_io_enq_bits = io_link_rx_bits;
assign rxq_io_deq_ready = io_rx_ready;
assign fire_tx = io_link_tx_ready & io_link_tx_valid;
assign T_94 = io_link_rx_valid & rxen;
assign GEN_0 = io_link_rx_valid ? 1'h0 : rxen;
assign T_96 = io_link_fmt_iodir == 1'h0;
assign GEN_1 = fire_tx ? T_96 : GEN_0;
assign T_97 = 2'h0 == io_link_fmt_proto;
assign T_98 = 2'h1 == io_link_fmt_proto;
assign T_99 = 2'h2 == io_link_fmt_proto;
assign T_101 = io_ctrl_fmt_len[3:1];
assign T_102 = io_ctrl_fmt_len[3:2];
assign T_104 = T_97 ? io_ctrl_fmt_len : 4'h0;
assign T_106 = T_98 ? T_101 : 3'h0;
assign T_108 = T_99 ? T_102 : 2'h0;
assign GEN_2 = {{1'd0}, T_106};
assign T_110 = T_104 | GEN_2;
assign GEN_3 = {{2'd0}, T_108};
assign T_111 = T_110 | GEN_3;
assign cnt_quot = T_111;
assign T_112 = io_ctrl_fmt_len[0];
assign T_115 = io_ctrl_fmt_len[1:0];
assign T_117 = T_115 != 2'h0;
assign T_118 = io_ctrl_fmt_len[2:0];
assign T_120 = T_118 != 3'h0;
assign T_123 = T_97 ? T_112 : 1'h0;
assign T_126 = T_98 ? T_117 : 1'h0;
assign T_129 = T_99 ? T_120 : 1'h0;
assign T_131 = T_123 | T_126;
assign T_132 = T_131 | T_129;
assign cnt_rmdr = T_132;
assign GEN_4 = {{3'd0}, cnt_rmdr};
assign T_133 = cnt_quot + GEN_4;
assign T_134 = T_133[3:0];
assign cs_mode_hold = cs_mode == 2'h2;
assign cs_mode_off = cs_mode == 2'h3;
assign cs_update = cs_mode != io_ctrl_cs_mode;
assign T_135 = cs_mode_hold | cs_mode_off;
assign cs_clear = T_135 == 1'h0;
assign T_138 = cs_mode_off == 1'h0;
assign T_139 = fire_tx & cs_clear;
assign T_140 = cs_update | T_139;
assign T_142 = io_link_tx_valid | rxen;
assign T_143 = txq_io_count < io_ctrl_wm_tx;
assign T_144 = rxq_io_count > io_ctrl_wm_rx;
always @(posedge clock or posedge reset)
if (reset) begin
rxen <= 1'h0;
end else begin
if (fire_tx) begin
rxen <= T_96;
end else begin
if (io_link_rx_valid) begin
rxen <= 1'h0;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
cs_mode <= 2'h0;
end else begin
cs_mode <= io_ctrl_cs_mode;
end
endmodule |
module e203_ifu_ifetch(
output[`E203_PC_SIZE-1:0] inspect_pc,
input [`E203_PC_SIZE-1:0] pc_rtvec,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Fetch Interface to memory system, internal protocol
// * IFetch REQ channel
output ifu_req_valid, // Handshake valid
input ifu_req_ready, // Handshake ready
// Note: the req-addr can be unaligned with the length indicated
// by req_len signal.
// The targetd (ITCM, ICache or Sys-MEM) ctrl modules
// will handle the unalign cases and split-and-merge works
output [`E203_PC_SIZE-1:0] ifu_req_pc, // Fetch PC
output ifu_req_seq, // This request is a sequential instruction fetch
output ifu_req_seq_rv32, // This request is incremented 32bits fetch
output [`E203_PC_SIZE-1:0] ifu_req_last_pc, // The last accessed
// PC address (i.e., pc_r)
// * IFetch RSP channel
input ifu_rsp_valid, // Response valid
output ifu_rsp_ready, // Response ready
input ifu_rsp_err, // Response error
// Note: the RSP channel always return a valid instruction
// fetched from the fetching start PC address.
// The targetd (ITCM, ICache or Sys-MEM) ctrl modules
// will handle the unalign cases and split-and-merge works
//input ifu_rsp_replay,
input [`E203_INSTR_SIZE-1:0] ifu_rsp_instr, // Response instruction
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output ifu_o_muldiv_b2b, // The mul/div back2back case
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rs1en,
input dec2ifu_rden,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_hsked = (ifu_req_valid & ifu_req_ready) ;
wire ifu_rsp_hsked = (ifu_rsp_valid & ifu_rsp_ready) ;
wire ifu_ir_o_hsked = (ifu_o_valid & ifu_o_ready) ;
wire pipe_flush_hsked = pipe_flush_req & pipe_flush_ack;
// The rst_flag is the synced version of rst_n
// * rst_n is asserted
// The rst_flag will be clear when
// * rst_n is de-asserted
wire reset_flag_r;
sirv_gnrl_dffrs #(1) reset_flag_dffrs (1'b0, reset_flag_r, clk, rst_n);
//
// The reset_req valid is set when
// * Currently reset_flag is asserting
// The reset_req valid is clear when
// * Currently reset_req is asserting
// * Currently the flush can be accepted by IFU
wire reset_req_r;
wire reset_req_set = (~reset_req_r) & reset_flag_r;
wire reset_req_clr = reset_req_r & ifu_req_hsked;
wire reset_req_ena = reset_req_set | reset_req_clr;
wire reset_req_nxt = reset_req_set | (~reset_req_clr);
sirv_gnrl_dfflr #(1) reset_req_dfflr (reset_req_ena, reset_req_nxt, reset_req_r, clk, rst_n);
wire ifu_reset_req = reset_req_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The halt ack generation
wire halt_ack_set;
wire halt_ack_clr;
wire halt_ack_ena;
wire halt_ack_r;
wire halt_ack_nxt;
// The halt_ack will be set when
// * Currently halt_req is asserting
// * Currently halt_ack is not asserting
// * Currently the ifetch REQ channel is ready, means
// there is no oustanding transactions
wire ifu_no_outs;
assign halt_ack_set = ifu_halt_req & (~halt_ack_r) & ifu_no_outs;
// The halt_ack_r valid is cleared when
// * Currently halt_ack is asserting
// * Currently halt_req is de-asserting
assign halt_ack_clr = halt_ack_r & (~ifu_halt_req);
assign halt_ack_ena = halt_ack_set | halt_ack_clr;
assign halt_ack_nxt = halt_ack_set | (~halt_ack_clr);
sirv_gnrl_dfflr #(1) halt_ack_dfflr (halt_ack_ena, halt_ack_nxt, halt_ack_r, clk, rst_n);
assign ifu_halt_ack = halt_ack_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The flush ack signal generation
//
// Ideally the flush is acked when the ifetch interface is ready
// or there is rsponse valid
// But to cut the comb loop between EXU and IFU, we always accept
// the flush, when it is not really acknowledged, we use a
// delayed flush indication to remember this flush
// Note: Even if there is a delayed flush pending there, we
// still can accept new flush request
assign pipe_flush_ack = 1'b1;
wire dly_flush_set;
wire dly_flush_clr;
wire dly_flush_ena;
wire dly_flush_nxt;
// The dly_flush will be set when
// * There is a flush requst is coming, but the ifu
// is not ready to accept new fetch request
wire dly_flush_r;
assign dly_flush_set = pipe_flush_req & (~ifu_req_hsked);
// The dly_flush_r valid is cleared when
// * The delayed flush is issued
assign dly_flush_clr = dly_flush_r & ifu_req_hsked;
assign dly_flush_ena = dly_flush_set | dly_flush_clr;
assign dly_flush_nxt = dly_flush_set | (~dly_flush_clr);
sirv_gnrl_dfflr #(1) dly_flush_dfflr (dly_flush_ena, dly_flush_nxt, dly_flush_r, clk, rst_n);
wire dly_pipe_flush_req = dly_flush_r;
wire pipe_flush_req_real = pipe_flush_req | dly_pipe_flush_req;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR register to be used in EXU for decoding
wire ir_valid_set;
wire ir_valid_clr;
wire ir_valid_ena;
wire ir_valid_r;
wire ir_valid_nxt;
wire ir_pc_vld_set;
wire ir_pc_vld_clr;
wire ir_pc_vld_ena;
wire ir_pc_vld_r;
wire ir_pc_vld_nxt;
// The ir valid is set when there is new instruction fetched *and*
// no flush happening
wire ifu_rsp_need_replay;
wire pc_newpend_r;
wire ifu_ir_i_ready;
assign ir_valid_set = ifu_rsp_hsked & (~pipe_flush_req_real) & (~ifu_rsp_need_replay);
assign ir_pc_vld_set = pc_newpend_r & ifu_ir_i_ready & (~pipe_flush_req_real) & (~ifu_rsp_need_replay);
// The ir valid is cleared when it is accepted by EXU stage *or*
// the flush happening
assign ir_valid_clr = ifu_ir_o_hsked | (pipe_flush_hsked & ir_valid_r);
assign ir_pc_vld_clr = ir_valid_clr;
assign ir_valid_ena = ir_valid_set | ir_valid_clr;
assign ir_valid_nxt = ir_valid_set | (~ir_valid_clr);
assign ir_pc_vld_ena = ir_pc_vld_set | ir_pc_vld_clr;
assign ir_pc_vld_nxt = ir_pc_vld_set | (~ir_pc_vld_clr);
sirv_gnrl_dfflr #(1) ir_valid_dfflr (ir_valid_ena, ir_valid_nxt, ir_valid_r, clk, rst_n);
sirv_gnrl_dfflr #(1) ir_pc_vld_dfflr (ir_pc_vld_ena, ir_pc_vld_nxt, ir_pc_vld_r, clk, rst_n);
// IFU-IR loaded with the returned instruction from the IFetch RSP channel
wire [`E203_INSTR_SIZE-1:0] ifu_ir_nxt = ifu_rsp_instr;
// IFU-PC loaded with the current PC
wire ifu_err_nxt = ifu_rsp_err;
// IFU-IR and IFU-PC as the datapath register, only loaded and toggle when the valid reg is set
wire ifu_err_r;
sirv_gnrl_dfflr #(1) ifu_err_dfflr(ir_valid_set, ifu_err_nxt, ifu_err_r, clk, rst_n);
wire prdt_taken;
wire ifu_prdt_taken_r;
sirv_gnrl_dfflr #(1) ifu_prdt_taken_dfflr (ir_valid_set, prdt_taken, ifu_prdt_taken_r, clk, rst_n);
wire ifu_muldiv_b2b_nxt;
wire ifu_muldiv_b2b_r;
sirv_gnrl_dfflr #(1) ir_muldiv_b2b_dfflr (ir_valid_set, ifu_muldiv_b2b_nxt, ifu_muldiv_b2b_r, clk, rst_n);
//To save power the H-16bits only loaded when it is 32bits length instru
wire [`E203_INSTR_SIZE-1:0] ifu_ir_r;// The instruction register
wire minidec_rv32;
wire ir_hi_ena = ir_valid_set & minidec_rv32;
wire ir_lo_ena = ir_valid_set;
sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_hi_ir_dfflr (ir_hi_ena, ifu_ir_nxt[31:16], ifu_ir_r[31:16], clk, rst_n);
sirv_gnrl_dfflr #(`E203_INSTR_SIZE/2) ifu_lo_ir_dfflr (ir_lo_ena, ifu_ir_nxt[15: 0], ifu_ir_r[15: 0], clk, rst_n);
wire minidec_rs1en;
wire minidec_rs2en;
wire [`E203_RFIDX_WIDTH-1:0] minidec_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] minidec_rs2idx;
`ifndef E203_HAS_FPU//}
wire minidec_fpu = 1'b0;
wire minidec_fpu_rs1en = 1'b0;
wire minidec_fpu_rs2en = 1'b0;
wire minidec_fpu_rs3en = 1'b0;
wire minidec_fpu_rs1fpu = 1'b0;
wire minidec_fpu_rs2fpu = 1'b0;
wire minidec_fpu_rs3fpu = 1'b0;
wire [`E203_RFIDX_WIDTH-1:0] minidec_fpu_rs1idx = `E203_RFIDX_WIDTH'b0;
wire [`E203_RFIDX_WIDTH-1:0] minidec_fpu_rs2idx = `E203_RFIDX_WIDTH'b0;
`endif//}
wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_r;
wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_r;
wire bpu2rf_rs1_ena;
//FPU: if it is FPU instruction. we still need to put it into the IR register, but we need to mask off the non-integer regfile index to save power
wire ir_rs1idx_ena = (minidec_fpu & ir_valid_set & minidec_fpu_rs1en & (~minidec_fpu_rs1fpu)) | ((~minidec_fpu) & ir_valid_set & minidec_rs1en) | bpu2rf_rs1_ena;
wire ir_rs2idx_ena = (minidec_fpu & ir_valid_set & minidec_fpu_rs2en & (~minidec_fpu_rs2fpu)) | ((~minidec_fpu) & ir_valid_set & minidec_rs2en);
wire [`E203_RFIDX_WIDTH-1:0] ir_rs1idx_nxt = minidec_fpu ? minidec_fpu_rs1idx : minidec_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ir_rs2idx_nxt = minidec_fpu ? minidec_fpu_rs2idx : minidec_rs2idx;
sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs1idx_dfflr (ir_rs1idx_ena, ir_rs1idx_nxt, ir_rs1idx_r, clk, rst_n);
sirv_gnrl_dfflr #(`E203_RFIDX_WIDTH) ir_rs2idx_dfflr (ir_rs2idx_ena, ir_rs2idx_nxt, ir_rs2idx_r, clk, rst_n);
wire [`E203_PC_SIZE-1:0] pc_r;
wire [`E203_PC_SIZE-1:0] ifu_pc_nxt = pc_r;
wire [`E203_PC_SIZE-1:0] ifu_pc_r;
sirv_gnrl_dfflr #(`E203_PC_SIZE) ifu_pc_dfflr (ir_pc_vld_set, ifu_pc_nxt, ifu_pc_r, clk, rst_n);
assign ifu_o_ir = ifu_ir_r;
assign ifu_o_pc = ifu_pc_r;
// Instruction fetch misaligned exceptions are not possible on machines that support extensions
// with 16-bit aligned instructions, such as the compressed instruction set extension, C.
assign ifu_o_misalgn = 1'b0;// Never happen in RV32C configuration
assign ifu_o_buserr = ifu_err_r;
assign ifu_o_rs1idx = ir_rs1idx_r;
assign ifu_o_rs2idx = ir_rs2idx_r;
assign ifu_o_prdt_taken = ifu_prdt_taken_r;
assign ifu_o_muldiv_b2b = ifu_muldiv_b2b_r;
assign ifu_o_valid = ir_valid_r;
assign ifu_o_pc_vld = ir_pc_vld_r;
// The IFU-IR stage will be ready when it is empty or under-clearing
assign ifu_ir_i_ready = (~ir_valid_r) | ir_valid_clr;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// JALR instruction dependency check
wire ir_empty = ~ir_valid_r;
wire ir_rs1en = dec2ifu_rs1en;
wire ir_rden = dec2ifu_rden;
wire [`E203_RFIDX_WIDTH-1:0] ir_rdidx = dec2ifu_rdidx;
wire [`E203_RFIDX_WIDTH-1:0] minidec_jalr_rs1idx;
wire jalr_rs1idx_cam_irrdidx = ir_rden & (minidec_jalr_rs1idx == ir_rdidx) & ir_valid_r;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// MULDIV BACK2BACK Fusing
// To detect the sequence of MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2
// To detect the sequence of DIV[U] rdq, rs1, rs2; REM[U] rdr, rs1, rs2
wire minidec_mul ;
wire minidec_div ;
wire minidec_rem ;
wire minidec_divu;
wire minidec_remu;
assign ifu_muldiv_b2b_nxt =
(
// For multiplicaiton, only the MUL instruction following
// MULH/MULHU/MULSU can be treated as back2back
( minidec_mul & dec2ifu_mulhsu)
// For divider and reminder instructions, only the following cases
// can be treated as back2back
// * DIV--REM
// * REM--DIV
// * DIVU--REMU
// * REMU--DIVU
| ( minidec_div & dec2ifu_rem)
| ( minidec_rem & dec2ifu_div)
| ( minidec_divu & dec2ifu_remu)
| ( minidec_remu & dec2ifu_divu)
)
// The last rs1 and rs2 indexes are same as this instruction
& (ir_rs1idx_r == ir_rs1idx_nxt)
& (ir_rs2idx_r == ir_rs2idx_nxt)
// The last rs1 and rs2 indexes are not same as last RD index
& (~(ir_rs1idx_r == ir_rdidx))
& (~(ir_rs2idx_r == ir_rdidx))
;
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Next PC generation
wire minidec_bjp;
wire minidec_jal;
wire minidec_jalr;
wire minidec_bxx;
wire [`E203_XLEN-1:0] minidec_bjp_imm;
// The mini-decoder to check instruciton length and branch type
e203_ifu_minidec u_e203_ifu_minidec (
.instr (ifu_ir_nxt ),
.dec_rs1en (minidec_rs1en ),
.dec_rs2en (minidec_rs2en ),
.dec_rs1idx (minidec_rs1idx ),
.dec_rs2idx (minidec_rs2idx ),
.dec_rv32 (minidec_rv32 ),
.dec_bjp (minidec_bjp ),
.dec_jal (minidec_jal ),
.dec_jalr (minidec_jalr ),
.dec_bxx (minidec_bxx ),
.dec_mulhsu (),
.dec_mul (minidec_mul ),
.dec_div (minidec_div ),
.dec_rem (minidec_rem ),
.dec_divu (minidec_divu),
.dec_remu (minidec_remu),
.dec_jalr_rs1idx (minidec_jalr_rs1idx),
.dec_bjp_imm (minidec_bjp_imm )
);
wire bpu_wait;
wire [`E203_PC_SIZE-1:0] prdt_pc_add_op1;
wire [`E203_PC_SIZE-1:0] prdt_pc_add_op2;
e203_ifu_litebpu u_e203_ifu_litebpu(
.pc (pc_r),
.dec_jal (minidec_jal ),
.dec_jalr (minidec_jalr ),
.dec_bxx (minidec_bxx ),
.dec_bjp_imm (minidec_bjp_imm ),
.dec_jalr_rs1idx (minidec_jalr_rs1idx ),
.dec_i_valid (ifu_rsp_valid),
.ir_valid_clr (ir_valid_clr),
.oitf_empty (oitf_empty),
.ir_empty (ir_empty ),
.ir_rs1en (ir_rs1en ),
.jalr_rs1idx_cam_irrdidx (jalr_rs1idx_cam_irrdidx),
.bpu_wait (bpu_wait ),
.prdt_taken (prdt_taken ),
.prdt_pc_add_op1 (prdt_pc_add_op1),
.prdt_pc_add_op2 (prdt_pc_add_op2),
.bpu2rf_rs1_ena (bpu2rf_rs1_ena),
.rf2bpu_x1 (rf2ifu_x1 ),
.rf2bpu_rs1 (rf2ifu_rs1 ),
.clk (clk ) ,
.rst_n (rst_n )
);
// If the instruciton is 32bits length, increament 4, otherwise 2
wire [2:0] pc_incr_ofst = minidec_rv32 ? 3'd4 : 3'd2;
wire [`E203_PC_SIZE-1:0] pc_nxt_pre;
wire [`E203_PC_SIZE-1:0] pc_nxt;
wire bjp_req = minidec_bjp & prdt_taken;
wire ifetch_replay_req;
wire [`E203_PC_SIZE-1:0] pc_add_op1 =
`ifndef E203_TIMING_BOOST//}
pipe_flush_req ? pipe_flush_add_op1 :
dly_pipe_flush_req ? pc_r :
`endif//}
ifetch_replay_req ? pc_r :
bjp_req ? prdt_pc_add_op1 :
ifu_reset_req ? pc_rtvec :
pc_r;
wire [`E203_PC_SIZE-1:0] pc_add_op2 =
`ifndef E203_TIMING_BOOST//}
pipe_flush_req ? pipe_flush_add_op2 :
dly_pipe_flush_req ? `E203_PC_SIZE'b0 :
`endif//}
ifetch_replay_req ? `E203_PC_SIZE'b0 :
bjp_req ? prdt_pc_add_op2 :
ifu_reset_req ? `E203_PC_SIZE'b0 :
pc_incr_ofst ;
assign ifu_req_seq = (~pipe_flush_req_real) & (~ifu_reset_req) & (~ifetch_replay_req) & (~bjp_req);
assign ifu_req_seq_rv32 = minidec_rv32;
assign ifu_req_last_pc = pc_r;
assign pc_nxt_pre = pc_add_op1 + pc_add_op2;
`ifndef E203_TIMING_BOOST//}
assign pc_nxt = {pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};
`else//}{
assign pc_nxt =
pipe_flush_req ? {pipe_flush_pc[`E203_PC_SIZE-1:1],1'b0} :
dly_pipe_flush_req ? {pc_r[`E203_PC_SIZE-1:1],1'b0} :
{pc_nxt_pre[`E203_PC_SIZE-1:1],1'b0};
`endif//}
// The Ifetch issue new ifetch request when
// * If it is a bjp insturction, and it does not need to wait, and it is not a replay-set cycle
// * and there is no halt_request
wire ifu_new_req = (~bpu_wait) & (~ifu_halt_req) & (~reset_flag_r) & (~ifu_rsp_need_replay);
// The fetch request valid is triggering when
// * New ifetch request
// * or The flush-request is pending
wire ifu_req_valid_pre = ifu_new_req | ifu_reset_req | pipe_flush_req_real | ifetch_replay_req;
// The new request ready condition is:
// * No outstanding reqeusts
// * Or if there is outstanding, but it is reponse valid back
wire out_flag_clr;
wire out_flag_r;
wire new_req_condi = (~out_flag_r) | out_flag_clr;
assign ifu_no_outs = (~out_flag_r) | ifu_rsp_valid;
// Here we use the rsp_valid rather than the out_flag_clr (ifu_rsp_hsked) because
// as long as the rsp_valid is asserting then means last request have returned the
// response back, in WFI case, we cannot expect it to be handshaked (otherwise deadlock)
assign ifu_req_valid = ifu_req_valid_pre & new_req_condi;
//wire ifu_rsp2ir_ready = (ifu_rsp_replay | pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & (~bpu_wait));
wire ifu_rsp2ir_ready = (pipe_flush_req_real) ? 1'b1 : (ifu_ir_i_ready & ifu_req_ready & (~bpu_wait));
// Response channel only ready when:
// * IR is ready to accept new instructions
assign ifu_rsp_ready = ifu_rsp2ir_ready;
// The PC will need to be updated when ifu req channel handshaked or a flush is incoming
wire pc_ena = ifu_req_hsked | pipe_flush_hsked;
sirv_gnrl_dfflr #(`E203_PC_SIZE) pc_dfflr (pc_ena, pc_nxt, pc_r, clk, rst_n);
assign inspect_pc = pc_r;
assign ifu_req_pc = pc_nxt;
// The out_flag will be set if there is a new request handshaked
wire out_flag_set = ifu_req_hsked;
// The out_flag will be cleared if there is a request response handshaked
assign out_flag_clr = ifu_rsp_hsked;
wire out_flag_ena = out_flag_set | out_flag_clr;
// If meanwhile set and clear, then set preempt
wire out_flag_nxt = out_flag_set | (~out_flag_clr);
sirv_gnrl_dfflr #(1) out_flag_dfflr (out_flag_ena, out_flag_nxt, out_flag_r, clk, rst_n);
// The pc_newpend will be set if there is a new PC loaded
wire pc_newpend_set = pc_ena;
// The pc_newpend will be cleared if have already loaded into the IR-PC stage
wire pc_newpend_clr = ir_pc_vld_set;
wire pc_newpend_ena = pc_newpend_set | pc_newpend_clr;
// If meanwhile set and clear, then set preempt
wire pc_newpend_nxt = pc_newpend_set | (~pc_newpend_clr);
sirv_gnrl_dfflr #(1) pc_newpend_dfflr (pc_newpend_ena, pc_newpend_nxt, pc_newpend_r, clk, rst_n);
assign ifu_rsp_need_replay = 1'b0;
assign ifetch_replay_req = 1'b0;
`ifndef FPGA_SOURCE//{
`ifndef DISABLE_SV_ASSERTION//{
//synopsys translate_off
CHECK_IFU_REQ_VALID_NO_X:
assert property (@(posedge clk) disable iff (~rst_n)
(ifu_req_valid !== 1'bx)
)
else $fatal ("\n Error: Oops, detected X value for ifu_req_valid !!! This should never happen. \n");
//synopsys translate_on
`endif//}
`endif//}
endmodule |
module e203_exu_alu_csrctrl(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input csr_i_valid, // Handshake valid
output csr_i_ready, // Handshake ready
input [`E203_XLEN-1:0] csr_i_rs1,
input [`E203_DECINFO_CSR_WIDTH-1:0] csr_i_info,
input csr_i_rdwen,
output csr_ena,
output csr_wr_en,
output csr_rd_en,
output [12-1:0] csr_idx,
input csr_access_ilgl,
input [`E203_XLEN-1:0] read_csr_dat,
output [`E203_XLEN-1:0] wbck_csr_dat,
`ifdef E203_HAS_CSR_EAI//{
output csr_sel_eai,
input eai_xs_off,
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The CSR Write-back/Commit Interface
output csr_o_valid, // Handshake valid
input csr_o_ready, // Handshake ready
// The Write-Back Interface for Special (unaligned ldst and AMO instructions)
output [`E203_XLEN-1:0] csr_o_wbck_wdat,
output csr_o_wbck_err,
input clk,
input rst_n
);
`ifdef E203_HAS_CSR_EAI//{
// If accessed the EAI CSR range then we need to check if the EAI CSR is ready
assign csr_sel_eai = (csr_idx[11:8] == 4'hE);
wire sel_eai = csr_sel_eai & (~eai_xs_off);
wire addi_condi = sel_eai ? eai_csr_ready : 1'b1;
assign csr_o_valid = csr_i_valid
& addi_condi; // Need to make sure the eai_csr-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign eai_csr_valid = sel_eai & csr_i_valid &
csr_o_ready;// Need to make sure the o-ready is ready to make sure
// it can be sent to EAI and O interface same cycle
assign csr_i_ready = sel_eai ? (eai_csr_ready & csr_o_ready) : csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = sel_eai ? eai_csr_rdata : read_csr_dat;
assign eai_csr_addr = csr_idx;
assign eai_csr_wr = csr_wr_en;
assign eai_csr_wdata = wbck_csr_dat;
`else//}{
assign sel_eai = 1'b0;
assign csr_o_valid = csr_i_valid;
assign csr_i_ready = csr_o_ready;
assign csr_o_wbck_err = csr_access_ilgl;
assign csr_o_wbck_wdat = read_csr_dat;
`endif//}
wire csrrw = csr_i_info[`E203_DECINFO_CSR_CSRRW ];
wire csrrs = csr_i_info[`E203_DECINFO_CSR_CSRRS ];
wire csrrc = csr_i_info[`E203_DECINFO_CSR_CSRRC ];
wire rs1imm = csr_i_info[`E203_DECINFO_CSR_RS1IMM];
wire rs1is0 = csr_i_info[`E203_DECINFO_CSR_RS1IS0];
wire [4:0] zimm = csr_i_info[`E203_DECINFO_CSR_ZIMMM ];
wire [11:0] csridx = csr_i_info[`E203_DECINFO_CSR_CSRIDX];
wire [`E203_XLEN-1:0] csr_op1 = rs1imm ? {27'b0,zimm} : csr_i_rs1;
assign csr_rd_en = csr_i_valid &
(
(csrrw ? csr_i_rdwen : 1'b0) // the CSRRW only read when the destination reg need to be writen
| csrrs | csrrc // The set and clear operation always need to read CSR
);
assign csr_wr_en = csr_i_valid & (
csrrw // CSRRW always write the original RS1 value into the CSR
| ((csrrs | csrrc) & (~rs1is0)) // for CSRRS/RC, if the RS is x0, then should not really write
);
assign csr_idx = csridx;
assign csr_ena = csr_o_valid & csr_o_ready & (~sel_eai);
assign wbck_csr_dat =
({`E203_XLEN{csrrw}} & csr_op1)
| ({`E203_XLEN{csrrs}} & ( csr_op1 | read_csr_dat))
| ({`E203_XLEN{csrrc}} & ((~csr_op1) & read_csr_dat));
endmodule |
module sirv_ResetCatchAndSync(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [2:0] reset_n_catch_reg_io_d;
wire [2:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [1:0] T_6;
wire [2:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_36 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[2:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule |
module sirv_AsyncResetRegVec_36(
input clock,
input reset,
input [2:0] io_d,
output [2:0] io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
wire reg_1_rst;
wire reg_1_clk;
wire reg_1_en;
wire reg_1_q;
wire reg_1_d;
wire reg_2_rst;
wire reg_2_clk;
wire reg_2_en;
wire reg_2_q;
wire reg_2_d;
wire T_8;
wire T_9;
wire T_10;
wire [1:0] T_11;
wire [2:0] T_12;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
sirv_AsyncResetReg reg_1 (
.rst(reg_1_rst),
.clk(reg_1_clk),
.en(reg_1_en),
.q(reg_1_q),
.d(reg_1_d)
);
sirv_AsyncResetReg reg_2 (
.rst(reg_2_rst),
.clk(reg_2_clk),
.en(reg_2_en),
.q(reg_2_q),
.d(reg_2_d)
);
assign io_q = T_12;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = T_8;
assign reg_1_rst = reset;
assign reg_1_clk = clock;
assign reg_1_en = io_en;
assign reg_1_d = T_9;
assign reg_2_rst = reset;
assign reg_2_clk = clock;
assign reg_2_en = io_en;
assign reg_2_d = T_10;
assign T_8 = io_d[0];
assign T_9 = io_d[1];
assign T_10 = io_d[2];
assign T_11 = {reg_2_q,reg_1_q};
assign T_12 = {T_11,reg_0_q};
endmodule |
module sirv_otp_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata
);
assign i_icb_cmd_ready = 1'b0;
assign i_icb_rsp_valid = 1'b0;
assign i_icb_rsp_rdata = 32'b0;
assign f_icb_cmd_ready = 1'b0;
assign f_icb_rsp_valid = 1'b0;
assign f_icb_rsp_rdata = 32'b0;
// In FPGA platform this module is just an empty wrapper
endmodule |
module e203_exu_alu_bjp(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Handshake Interface
//
input bjp_i_valid, // Handshake valid
output bjp_i_ready, // Handshake ready
input [`E203_XLEN-1:0] bjp_i_rs1,
input [`E203_XLEN-1:0] bjp_i_rs2,
input [`E203_XLEN-1:0] bjp_i_imm,
input [`E203_PC_SIZE-1:0] bjp_i_pc,
input [`E203_DECINFO_BJP_WIDTH-1:0] bjp_i_info,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The BJP Commit Interface
output bjp_o_valid, // Handshake valid
input bjp_o_ready, // Handshake ready
// The Write-Back Result for JAL and JALR
output [`E203_XLEN-1:0] bjp_o_wbck_wdat,
output bjp_o_wbck_err,
// The Commit Result for BJP
output bjp_o_cmt_bjp,
output bjp_o_cmt_mret,
output bjp_o_cmt_dret,
output bjp_o_cmt_fencei,
output bjp_o_cmt_prdt,// The predicted ture/false
output bjp_o_cmt_rslv,// The resolved ture/false
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath
//
// The operands and info to ALU
output [`E203_XLEN-1:0] bjp_req_alu_op1,
output [`E203_XLEN-1:0] bjp_req_alu_op2,
output bjp_req_alu_cmp_eq ,
output bjp_req_alu_cmp_ne ,
output bjp_req_alu_cmp_lt ,
output bjp_req_alu_cmp_gt ,
output bjp_req_alu_cmp_ltu,
output bjp_req_alu_cmp_gtu,
output bjp_req_alu_add,
input bjp_req_alu_cmp_res,
input [`E203_XLEN-1:0] bjp_req_alu_add_res,
input clk,
input rst_n
);
wire mret = bjp_i_info [`E203_DECINFO_BJP_MRET ];
wire dret = bjp_i_info [`E203_DECINFO_BJP_DRET ];
wire fencei = bjp_i_info [`E203_DECINFO_BJP_FENCEI ];
wire bxx = bjp_i_info [`E203_DECINFO_BJP_BXX ];
wire jump = bjp_i_info [`E203_DECINFO_BJP_JUMP ];
wire rv32 = bjp_i_info [`E203_DECINFO_RV32];
wire wbck_link = jump;
wire bjp_i_bprdt = bjp_i_info [`E203_DECINFO_BJP_BPRDT ];
assign bjp_req_alu_op1 = wbck_link ?
bjp_i_pc
: bjp_i_rs1;
assign bjp_req_alu_op2 = wbck_link ?
(rv32 ? `E203_XLEN'd4 : `E203_XLEN'd2)
: bjp_i_rs2;
assign bjp_o_cmt_bjp = bxx | jump;
assign bjp_o_cmt_mret = mret;
assign bjp_o_cmt_dret = dret;
assign bjp_o_cmt_fencei = fencei;
assign bjp_req_alu_cmp_eq = bjp_i_info [`E203_DECINFO_BJP_BEQ ];
assign bjp_req_alu_cmp_ne = bjp_i_info [`E203_DECINFO_BJP_BNE ];
assign bjp_req_alu_cmp_lt = bjp_i_info [`E203_DECINFO_BJP_BLT ];
assign bjp_req_alu_cmp_gt = bjp_i_info [`E203_DECINFO_BJP_BGT ];
assign bjp_req_alu_cmp_ltu = bjp_i_info [`E203_DECINFO_BJP_BLTU ];
assign bjp_req_alu_cmp_gtu = bjp_i_info [`E203_DECINFO_BJP_BGTU ];
assign bjp_req_alu_add = wbck_link;
assign bjp_o_valid = bjp_i_valid;
assign bjp_i_ready = bjp_o_ready;
assign bjp_o_cmt_prdt = bjp_i_bprdt;
assign bjp_o_cmt_rslv = jump ? 1'b1 : bjp_req_alu_cmp_res;
assign bjp_o_wbck_wdat = bjp_req_alu_add_res;
assign bjp_o_wbck_err = 1'b0;
endmodule |
module sirv_mrom_top #(
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
// * Bus cmd channel
input rom_icb_cmd_valid, // Handshake valid
output rom_icb_cmd_ready, // Handshake ready
input [AW-1:0] rom_icb_cmd_addr, // Bus transaction start addr
input rom_icb_cmd_read, // Read or write
// * Bus RSP channel
output rom_icb_rsp_valid, // Response valid
input rom_icb_rsp_ready, // Response ready
output rom_icb_rsp_err, // Response error
output [DW-1:0] rom_icb_rsp_rdata,
input clk,
input rst_n
);
wire [DW-1:0] rom_dout;
assign rom_icb_rsp_valid = rom_icb_cmd_valid;
assign rom_icb_cmd_ready = rom_icb_rsp_ready;
assign rom_icb_rsp_err = ~rom_icb_cmd_read;
assign rom_icb_rsp_rdata = rom_dout;
sirv_mrom # (
.AW(AW),
.DW(DW),
.DP(DP)
)u_sirv_mrom (
.rom_addr (rom_icb_cmd_addr[AW-1:2]),
.rom_dout (rom_dout)
);
endmodule |
module e203_subsys_hclkgen(
input test_mode,
input hfclkrst,// To reset the PLL Clock
input hfextclk,// The original clock from crystal
input pllbypass ,
input pll_RESET ,
input pll_ASLEEP ,
input [1:0] pll_OD,
input [7:0] pll_M,
input [4:0] pll_N,
input plloutdivby1,
input [5:0] plloutdiv,
output inspect_16m_clk,
output inspect_pll_clk,
output hfclk// The generated clock by this module
);
wire hfclkrst_n = ~hfclkrst;
// The PLL module
wire plloutclk;
wire pll_powerd = pll_ASLEEP | hfclkrst; // Power down by PMU or the register programmed
e203_subsys_pll u_e203_subsys_pll(
.pll_asleep (pll_powerd ),
.pll_RESET (pll_RESET),
.pll_OD (pll_OD),
.pll_M (pll_M ),
.pll_N (pll_N ),
.pllrefclk (hfextclk ),
.plloutclk (plloutclk )
);
// The Reset syncer for the PLLout clk
wire plloutclk_rst_n;
e203_subsys_hclkgen_rstsync plloutclk_rstsync(
.clk (plloutclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (plloutclk_rst_n)
);
// The Reset syncer for the HFextclk
wire hfextclk_rst_n;
e203_subsys_hclkgen_rstsync hfextclk_rstsync(
.clk (hfextclk),
.rst_n_a (hfclkrst_n),
.test_mode(test_mode),
.rst_n (hfextclk_rst_n)
);
// The PLL divider
wire plloutdivclk;
e203_subsys_pllclkdiv u_e203_subsys_pllclkdiv(
.test_mode(test_mode),
.rst_n (plloutclk_rst_n),
.divby1(plloutdivby1),
.div (plloutdiv ),
.clk (plloutclk),// The PLL clock
.clkout(plloutdivclk) // The divided Clock
);
// The glitch free clock mux
wire gfcm_clk;
e203_subsys_gfcm u_e203_subsys_gfcm(
.test_mode(test_mode),
.clk0_rst_n (plloutclk_rst_n),
.clk1_rst_n (hfextclk_rst_n),
.sel1 (pllbypass),
.clk0 (plloutdivclk),// The divided PLL clock
.clk1 (hfextclk),// The original Crystal clock
.clkout (gfcm_clk)
);
assign hfclk = test_mode ? hfextclk : gfcm_clk;
assign inspect_16m_clk = hfextclk ;
assign inspect_pll_clk = plloutclk;
endmodule |
module e203_exu(
output commit_mret,
output commit_trap,
output exu_active,
output excp_active,
output core_wfi,
output tm_stop,
output itcm_nohold,
output core_cgstop,
output tcm_cgstop,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [`E203_XLEN-1:0] wr_csr_nxt ,
input [`E203_XLEN-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [`E203_XLEN-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IFU IR stage to EXU interface
input i_valid, // Handshake signals with EXU stage
output i_ready,
input [`E203_INSTR_SIZE-1:0] i_ir,// The instruction register
input [`E203_PC_SIZE-1:0] i_pc, // The PC register along with
input i_pc_vld,
input i_misalgn, // The fetch misalign
input i_buserr, // The fetch bus error
input i_prdt_taken,
input i_muldiv_b2b,
input [`E203_RFIDX_WIDTH-1:0] i_rs1idx, // The RS1 index
input [`E203_RFIDX_WIDTH-1:0] i_rs2idx, // The RS2 index
//////////////////////////////////////////////////////////////
// The Flush interface to IFU
//
// To save the gatecount, when we need to flush pipeline with new PC,
// we want to reuse the adder in IFU, so we will not pass flush-PC
// to IFU, instead, we pass the flush-pc-adder-op1/op2 to IFU
// and IFU will just use its adder to caculate the flush-pc-adder-result
//
input pipe_flush_ack,
output pipe_flush_req,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
output [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
output [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The LSU Write-Back Interface
input lsu_o_valid, // Handshake valid
output lsu_o_ready, // Handshake ready
input [`E203_XLEN-1:0] lsu_o_wbck_wdat,
input [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag,
input lsu_o_wbck_err ,
input lsu_o_cmt_ld,
input lsu_o_cmt_st,
input [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr,
input lsu_o_cmt_buserr , // The bus-error exception generated
output wfi_halt_ifu_req,
input wfi_halt_ifu_ack,
output oitf_empty,
output [`E203_XLEN-1:0] rf2ifu_x1,
output [`E203_XLEN-1:0] rf2ifu_rs1,
output dec2ifu_rden,
output dec2ifu_rs1en,
output [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
output dec2ifu_mulhsu,
output dec2ifu_div ,
output dec2ifu_rem ,
output dec2ifu_divu ,
output dec2ifu_remu ,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
// Several additional side channel signals
// Indicate LSU-ctrl module to
// return the ICB response channel back to AGU
// this is only used by AMO or unaligned load/store 1st uop
// to return the response
output agu_icb_cmd_back2agu,
// Sign extension or not
output agu_icb_cmd_usign,
output [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
input test_mode,
input clk_aon,
input clk,
input rst_n
);
//////////////////////////////////////////////////////////////
// Instantiate the Regfile
wire [`E203_XLEN-1:0] rf_rs1;
wire [`E203_XLEN-1:0] rf_rs2;
wire rf_wbck_ena;
wire [`E203_XLEN-1:0] rf_wbck_wdat;
wire [`E203_RFIDX_WIDTH-1:0] rf_wbck_rdidx;
e203_exu_regfile u_e203_exu_regfile(
.read_src1_idx (i_rs1idx ),
.read_src2_idx (i_rs2idx ),
.read_src1_dat (rf_rs1),
.read_src2_dat (rf_rs2),
.x1_r (rf2ifu_x1),
.wbck_dest_wen (rf_wbck_ena),
.wbck_dest_idx (rf_wbck_rdidx),
.wbck_dest_dat (rf_wbck_wdat),
.test_mode (test_mode),
.clk (clk ),
.rst_n (rst_n )
);
wire dec_rs1en;
wire dec_rs2en;
//////////////////////////////////////////////////////////////
// Instantiate the Decode
wire [`E203_DECINFO_WIDTH-1:0] dec_info;
wire [`E203_XLEN-1:0] dec_imm;
wire [`E203_PC_SIZE-1:0] dec_pc;
wire dec_rs1x0;
wire dec_rs2x0;
wire dec_rdwen;
wire [`E203_RFIDX_WIDTH-1:0] dec_rdidx;
wire dec_misalgn;
wire dec_buserr;
wire dec_ilegl;
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
e203_exu_decode u_e203_exu_decode (
.dbg_mode (dbg_mode),
.i_instr (i_ir ),
.i_pc (i_pc ),
.i_misalgn (i_misalgn),
.i_buserr (i_buserr ),
.i_prdt_taken (i_prdt_taken),
.i_muldiv_b2b (i_muldiv_b2b),
.dec_rv32 (),
.dec_bjp (),
.dec_jal (),
.dec_jalr (),
.dec_bxx (),
.dec_jalr_rs1idx(),
.dec_bjp_imm(),
.dec_mulhsu (dec2ifu_mulhsu),
.dec_mul (),
.dec_div (dec2ifu_div ),
.dec_rem (dec2ifu_rem ),
.dec_divu (dec2ifu_divu ),
.dec_remu (dec2ifu_remu ),
.dec_info (dec_info ),
.dec_rs1x0 (dec_rs1x0),
.dec_rs2x0 (dec_rs2x0),
.dec_rs1en (dec_rs1en),
.dec_rs2en (dec_rs2en),
.dec_rdwen (dec_rdwen),
.dec_rs1idx(),
.dec_rs2idx(),
.dec_misalgn(dec_misalgn),
.dec_buserr (dec_buserr ),
.dec_ilegl (dec_ilegl),
.dec_rdidx (dec_rdidx),
.dec_pc (dec_pc),
.dec_imm (dec_imm)
);
//////////////////////////////////////////////////////////////
// Instantiate the Dispatch
wire disp_alu_valid;
wire disp_alu_ready;
wire disp_alu_longpipe;
wire [`E203_ITAG_WIDTH-1:0] disp_alu_itag;
wire [`E203_XLEN-1:0] disp_alu_rs1;
wire [`E203_XLEN-1:0] disp_alu_rs2;
wire [`E203_XLEN-1:0] disp_alu_imm;
wire [`E203_DECINFO_WIDTH-1:0] disp_alu_info;
wire [`E203_PC_SIZE-1:0] disp_alu_pc;
wire [`E203_RFIDX_WIDTH-1:0] disp_alu_rdidx;
wire disp_alu_rdwen;
wire disp_alu_ilegl;
wire disp_alu_misalgn;
wire disp_alu_buserr;
wire [`E203_ITAG_WIDTH-1:0] disp_oitf_ptr;
wire disp_oitf_ready;
wire disp_oitf_rs1fpu;
wire disp_oitf_rs2fpu;
wire disp_oitf_rs3fpu;
wire disp_oitf_rdfpu;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs2idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rs3idx;
wire [`E203_RFIDX_WIDTH-1:0] disp_oitf_rdidx;
wire disp_oitf_rs1en;
wire disp_oitf_rs2en;
wire disp_oitf_rs3en;
wire disp_oitf_rdwen;
wire [`E203_PC_SIZE-1:0] disp_oitf_pc;
wire oitfrd_match_disprs1;
wire oitfrd_match_disprs2;
wire oitfrd_match_disprs3;
wire oitfrd_match_disprd;
wire disp_oitf_ena;
wire wfi_halt_exu_req;
wire wfi_halt_exu_ack;
wire amo_wait;
e203_exu_disp u_e203_exu_disp(
.wfi_halt_exu_req (wfi_halt_exu_req),
.wfi_halt_exu_ack (wfi_halt_exu_ack),
.oitf_empty (oitf_empty),
.amo_wait (amo_wait),
.disp_i_valid (i_valid ),
.disp_i_ready (i_ready ),
.disp_i_rs1x0 (dec_rs1x0 ),
.disp_i_rs2x0 (dec_rs2x0 ),
.disp_i_rs1en (dec_rs1en ),
.disp_i_rs2en (dec_rs2en ),
.disp_i_rs1idx (i_rs1idx ),
.disp_i_rs2idx (i_rs2idx ),
.disp_i_rdwen (dec_rdwen ),
.disp_i_rdidx (dec_rdidx ),
.disp_i_info (dec_info ),
.disp_i_rs1 (rf_rs1 ),
.disp_i_rs2 (rf_rs2 ),
.disp_i_imm (dec_imm ),
.disp_i_pc (dec_pc ),
.disp_i_misalgn (dec_misalgn ),
.disp_i_buserr (dec_buserr ),
.disp_i_ilegl (dec_ilegl ),
.disp_o_alu_valid (disp_alu_valid ),
.disp_o_alu_ready (disp_alu_ready ),
.disp_o_alu_longpipe (disp_alu_longpipe),
.disp_o_alu_itag (disp_alu_itag ),
.disp_o_alu_rs1 (disp_alu_rs1 ),
.disp_o_alu_rs2 (disp_alu_rs2 ),
.disp_o_alu_rdwen (disp_alu_rdwen ),
.disp_o_alu_rdidx (disp_alu_rdidx ),
.disp_o_alu_info (disp_alu_info ),
.disp_o_alu_pc (disp_alu_pc ),
.disp_o_alu_imm (disp_alu_imm ),
.disp_o_alu_misalgn (disp_alu_misalgn ),
.disp_o_alu_buserr (disp_alu_buserr ),
.disp_o_alu_ilegl (disp_alu_ilegl ),
.disp_oitf_ena (disp_oitf_ena ),
.disp_oitf_ptr (disp_oitf_ptr ),
.disp_oitf_ready (disp_oitf_ready ),
.disp_oitf_rs1en (disp_oitf_rs1en),
.disp_oitf_rs2en (disp_oitf_rs2en),
.disp_oitf_rs3en (disp_oitf_rs3en),
.disp_oitf_rdwen (disp_oitf_rdwen ),
.disp_oitf_rs1idx (disp_oitf_rs1idx),
.disp_oitf_rs2idx (disp_oitf_rs2idx),
.disp_oitf_rs3idx (disp_oitf_rs3idx),
.disp_oitf_rdidx (disp_oitf_rdidx ),
.disp_oitf_rs1fpu (disp_oitf_rs1fpu),
.disp_oitf_rs2fpu (disp_oitf_rs2fpu),
.disp_oitf_rs3fpu (disp_oitf_rs3fpu),
.disp_oitf_rdfpu (disp_oitf_rdfpu),
.disp_oitf_pc (disp_oitf_pc),
.oitfrd_match_disprs1(oitfrd_match_disprs1),
.oitfrd_match_disprs2(oitfrd_match_disprs2),
.oitfrd_match_disprs3(oitfrd_match_disprs3),
.oitfrd_match_disprd (oitfrd_match_disprd ),
.clk (clk ),
.rst_n (rst_n)
);
//////////////////////////////////////////////////////////////
// Instantiate the OITF
wire oitf_ret_ena;
wire [`E203_ITAG_WIDTH-1:0] oitf_ret_ptr;
wire [`E203_RFIDX_WIDTH-1:0] oitf_ret_rdidx;
wire [`E203_PC_SIZE-1:0] oitf_ret_pc;
wire oitf_ret_rdwen;
wire oitf_ret_rdfpu;
e203_exu_oitf u_e203_exu_oitf(
.dis_ready (disp_oitf_ready),
.dis_ena (disp_oitf_ena ),
.ret_ena (oitf_ret_ena ),
.dis_ptr (disp_oitf_ptr ),
.ret_ptr (oitf_ret_ptr ),
.ret_rdidx (oitf_ret_rdidx),
.ret_rdwen (oitf_ret_rdwen),
.ret_rdfpu (oitf_ret_rdfpu),
.ret_pc (oitf_ret_pc),
.disp_i_rs1en (disp_oitf_rs1en),
.disp_i_rs2en (disp_oitf_rs2en),
.disp_i_rs3en (disp_oitf_rs3en),
.disp_i_rdwen (disp_oitf_rdwen ),
.disp_i_rs1idx (disp_oitf_rs1idx),
.disp_i_rs2idx (disp_oitf_rs2idx),
.disp_i_rs3idx (disp_oitf_rs3idx),
.disp_i_rdidx (disp_oitf_rdidx ),
.disp_i_rs1fpu (disp_oitf_rs1fpu),
.disp_i_rs2fpu (disp_oitf_rs2fpu),
.disp_i_rs3fpu (disp_oitf_rs3fpu),
.disp_i_rdfpu (disp_oitf_rdfpu ),
.disp_i_pc (disp_oitf_pc ),
.oitfrd_match_disprs1 (oitfrd_match_disprs1),
.oitfrd_match_disprs2 (oitfrd_match_disprs2),
.oitfrd_match_disprs3 (oitfrd_match_disprs3),
.oitfrd_match_disprd (oitfrd_match_disprd ),
.oitf_empty (oitf_empty ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the ALU
wire alu_wbck_o_valid;
wire alu_wbck_o_ready;
wire [`E203_XLEN-1:0] alu_wbck_o_wdat;
wire [`E203_RFIDX_WIDTH-1:0] alu_wbck_o_rdidx;
wire alu_cmt_valid;
wire alu_cmt_ready;
wire alu_cmt_pc_vld;
wire [`E203_PC_SIZE-1:0] alu_cmt_pc;
wire [`E203_INSTR_SIZE-1:0] alu_cmt_instr;
wire [`E203_XLEN-1:0] alu_cmt_imm;
wire alu_cmt_rv32;
wire alu_cmt_bjp;
wire alu_cmt_mret;
wire alu_cmt_dret;
wire alu_cmt_ecall;
wire alu_cmt_ebreak;
wire alu_cmt_wfi;
wire alu_cmt_fencei;
wire alu_cmt_ifu_misalgn;
wire alu_cmt_ifu_buserr;
wire alu_cmt_ifu_ilegl;
wire alu_cmt_bjp_prdt;
wire alu_cmt_bjp_rslv;
wire alu_cmt_misalgn;
wire alu_cmt_ld;
wire alu_cmt_stamo;
wire alu_cmt_buserr;
wire [`E203_ADDR_SIZE-1:0] alu_cmt_badaddr;
wire csr_ena;
wire csr_wr_en;
wire csr_rd_en;
wire [12-1:0] csr_idx;
wire [`E203_XLEN-1:0] read_csr_dat;
wire [`E203_XLEN-1:0] wbck_csr_dat;
wire flush_pulse;
wire flush_req;
wire nonflush_cmt_ena;
wire eai_xs_off;
wire csr_access_ilgl;
wire mdv_nob2b;
e203_exu_alu u_e203_exu_alu(
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.csr_access_ilgl (csr_access_ilgl),
.nonflush_cmt_ena (nonflush_cmt_ena),
.i_valid (disp_alu_valid ),
.i_ready (disp_alu_ready ),
.i_longpipe (disp_alu_longpipe),
.i_itag (disp_alu_itag ),
.i_rs1 (disp_alu_rs1 ),
.i_rs2 (disp_alu_rs2 ),
.eai_xs_off (eai_xs_off),
.i_rdwen (disp_alu_rdwen ),
.i_rdidx (disp_alu_rdidx ),
.i_info (disp_alu_info ),
.i_pc (i_pc ),
.i_pc_vld (i_pc_vld),
.i_instr (i_ir ),
.i_imm (disp_alu_imm ),
.i_misalgn (disp_alu_misalgn ),
.i_buserr (disp_alu_buserr ),
.i_ilegl (disp_alu_ilegl ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.oitf_empty (oitf_empty),
.amo_wait (amo_wait),
.cmt_o_valid (alu_cmt_valid ),
.cmt_o_ready (alu_cmt_ready ),
.cmt_o_pc_vld (alu_cmt_pc_vld ),
.cmt_o_pc (alu_cmt_pc ),
.cmt_o_instr (alu_cmt_instr ),
.cmt_o_imm (alu_cmt_imm ),
.cmt_o_rv32 (alu_cmt_rv32 ),
.cmt_o_bjp (alu_cmt_bjp ),
.cmt_o_dret (alu_cmt_dret ),
.cmt_o_mret (alu_cmt_mret ),
.cmt_o_ecall (alu_cmt_ecall ),
.cmt_o_ebreak (alu_cmt_ebreak ),
.cmt_o_fencei (alu_cmt_fencei ),
.cmt_o_wfi (alu_cmt_wfi ),
.cmt_o_ifu_misalgn (alu_cmt_ifu_misalgn),
.cmt_o_ifu_buserr (alu_cmt_ifu_buserr ),
.cmt_o_ifu_ilegl (alu_cmt_ifu_ilegl ),
.cmt_o_bjp_prdt (alu_cmt_bjp_prdt ),
.cmt_o_bjp_rslv (alu_cmt_bjp_rslv ),
.cmt_o_misalgn (alu_cmt_misalgn),
.cmt_o_ld (alu_cmt_ld),
.cmt_o_stamo (alu_cmt_stamo),
.cmt_o_buserr (alu_cmt_buserr),
.cmt_o_badaddr (alu_cmt_badaddr),
.wbck_o_valid (alu_wbck_o_valid ),
.wbck_o_ready (alu_wbck_o_ready ),
.wbck_o_wdat (alu_wbck_o_wdat ),
.wbck_o_rdidx (alu_wbck_o_rdidx ),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock),
.agu_icb_cmd_excl (agu_icb_cmd_excl),
.agu_icb_cmd_size (agu_icb_cmd_size),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
.mdv_nob2b (mdv_nob2b),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Long-pipe Write-Back
wire longp_wbck_o_valid;
wire longp_wbck_o_ready;
wire [`E203_FLEN-1:0] longp_wbck_o_wdat;
wire [`E203_RFIDX_WIDTH-1:0] longp_wbck_o_rdidx;
wire longp_wbck_o_rdfpu;
wire [4:0] longp_wbck_o_flags;
wire longp_excp_o_ready;
wire longp_excp_o_valid;
wire longp_excp_o_ld;
wire longp_excp_o_st;
wire longp_excp_o_buserr ;
wire[`E203_ADDR_SIZE-1:0]longp_excp_o_badaddr;
wire longp_excp_o_insterr;
wire[`E203_PC_SIZE-1:0]longp_excp_o_pc;
e203_exu_longpwbck u_e203_exu_longpwbck(
.lsu_wbck_i_valid (lsu_o_valid ),
.lsu_wbck_i_ready (lsu_o_ready ),
.lsu_wbck_i_wdat (lsu_o_wbck_wdat ),
.lsu_wbck_i_itag (lsu_o_wbck_itag ),
.lsu_wbck_i_err (lsu_o_wbck_err ),
.lsu_cmt_i_ld (lsu_o_cmt_ld ),
.lsu_cmt_i_st (lsu_o_cmt_st ),
.lsu_cmt_i_badaddr (lsu_o_cmt_badaddr),
.lsu_cmt_i_buserr (lsu_o_cmt_buserr ),
.longp_wbck_o_valid (longp_wbck_o_valid ),
.longp_wbck_o_ready (longp_wbck_o_ready ),
.longp_wbck_o_wdat (longp_wbck_o_wdat ),
.longp_wbck_o_rdidx (longp_wbck_o_rdidx ),
.longp_wbck_o_rdfpu (longp_wbck_o_rdfpu ),
.longp_wbck_o_flags (longp_wbck_o_flags ),
.longp_excp_o_ready (longp_excp_o_ready ),
.longp_excp_o_valid (longp_excp_o_valid ),
.longp_excp_o_ld (longp_excp_o_ld ),
.longp_excp_o_st (longp_excp_o_st ),
.longp_excp_o_buserr (longp_excp_o_buserr ),
.longp_excp_o_badaddr (longp_excp_o_badaddr),
.longp_excp_o_insterr (longp_excp_o_insterr),
.longp_excp_o_pc (longp_excp_o_pc),
.oitf_ret_rdidx (oitf_ret_rdidx),
.oitf_ret_rdwen (oitf_ret_rdwen),
.oitf_ret_rdfpu (oitf_ret_rdfpu),
.oitf_ret_pc (oitf_ret_pc),
.oitf_empty (oitf_empty ),
.oitf_ret_ptr (oitf_ret_ptr ),
.oitf_ret_ena (oitf_ret_ena ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Final Write-Back
e203_exu_wbck u_e203_exu_wbck(
.alu_wbck_i_valid (alu_wbck_o_valid ),
.alu_wbck_i_ready (alu_wbck_o_ready ),
.alu_wbck_i_wdat (alu_wbck_o_wdat ),
.alu_wbck_i_rdidx (alu_wbck_o_rdidx ),
.longp_wbck_i_valid (longp_wbck_o_valid ),
.longp_wbck_i_ready (longp_wbck_o_ready ),
.longp_wbck_i_wdat (longp_wbck_o_wdat ),
.longp_wbck_i_rdidx (longp_wbck_o_rdidx ),
.longp_wbck_i_rdfpu (longp_wbck_o_rdfpu ),
.longp_wbck_i_flags (longp_wbck_o_flags ),
.rf_wbck_o_ena (rf_wbck_ena ),
.rf_wbck_o_wdat (rf_wbck_wdat ),
.rf_wbck_o_rdidx (rf_wbck_rdidx ),
.clk (clk ),
.rst_n (rst_n )
);
//////////////////////////////////////////////////////////////
// Instantiate the Commit
wire [`E203_ADDR_SIZE-1:0] cmt_badaddr;
wire cmt_badaddr_ena;
wire [`E203_PC_SIZE-1:0] cmt_epc;
wire cmt_epc_ena;
wire [`E203_XLEN-1:0] cmt_cause;
wire cmt_cause_ena;
wire cmt_instret_ena;
wire cmt_status_ena;
wire cmt_mret_ena;
wire [`E203_PC_SIZE-1:0] csr_epc_r;
wire [`E203_PC_SIZE-1:0] csr_dpc_r;
wire [`E203_XLEN-1:0] csr_mtvec_r;
wire u_mode;
wire s_mode;
wire h_mode;
wire m_mode;
wire status_mie_r;
wire mtie_r;
wire msie_r;
wire meie_r;
e203_exu_commit u_e203_exu_commit(
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.core_wfi (core_wfi ),
.nonflush_cmt_ena (nonflush_cmt_ena),
.excp_active (excp_active),
.amo_wait (amo_wait ),
.wfi_halt_exu_req (wfi_halt_exu_req),
.wfi_halt_exu_ack (wfi_halt_exu_ack),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (evt_r ),
.status_mie_r (status_mie_r),
.mtie_r (mtie_r ),
.msie_r (msie_r ),
.meie_r (meie_r ),
.alu_cmt_i_valid (alu_cmt_valid ),
.alu_cmt_i_ready (alu_cmt_ready ),
.alu_cmt_i_pc (alu_cmt_pc ),
.alu_cmt_i_instr (alu_cmt_instr ),
.alu_cmt_i_pc_vld (alu_cmt_pc_vld ),
.alu_cmt_i_imm (alu_cmt_imm ),
.alu_cmt_i_rv32 (alu_cmt_rv32 ),
.alu_cmt_i_bjp (alu_cmt_bjp ),
.alu_cmt_i_mret (alu_cmt_mret ),
.alu_cmt_i_dret (alu_cmt_dret ),
.alu_cmt_i_ecall (alu_cmt_ecall ),
.alu_cmt_i_ebreak (alu_cmt_ebreak ),
.alu_cmt_i_fencei (alu_cmt_fencei ),
.alu_cmt_i_wfi (alu_cmt_wfi ),
.alu_cmt_i_ifu_misalgn (alu_cmt_ifu_misalgn),
.alu_cmt_i_ifu_buserr (alu_cmt_ifu_buserr ),
.alu_cmt_i_ifu_ilegl (alu_cmt_ifu_ilegl ),
.alu_cmt_i_bjp_prdt (alu_cmt_bjp_prdt ),
.alu_cmt_i_bjp_rslv (alu_cmt_bjp_rslv ),
.alu_cmt_i_misalgn (alu_cmt_misalgn),
.alu_cmt_i_ld (alu_cmt_ld),
.alu_cmt_i_stamo (alu_cmt_stamo),
.alu_cmt_i_buserr (alu_cmt_buserr),
.alu_cmt_i_badaddr (alu_cmt_badaddr),
.longp_excp_i_ready (longp_excp_o_ready ),
.longp_excp_i_valid (longp_excp_o_valid ),
.longp_excp_i_ld (longp_excp_o_ld ),
.longp_excp_i_st (longp_excp_o_st ),
.longp_excp_i_buserr (longp_excp_o_buserr ),
.longp_excp_i_badaddr (longp_excp_o_badaddr),
.longp_excp_i_insterr (longp_excp_o_insterr),
.longp_excp_i_pc (longp_excp_o_pc ),
.dbg_mode (dbg_mode),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.oitf_empty (oitf_empty),
.u_mode (u_mode),
.s_mode (s_mode),
.h_mode (h_mode),
.m_mode (m_mode),
.cmt_badaddr (cmt_badaddr ),
.cmt_badaddr_ena (cmt_badaddr_ena),
.cmt_epc (cmt_epc ),
.cmt_epc_ena (cmt_epc_ena ),
.cmt_cause (cmt_cause ),
.cmt_cause_ena (cmt_cause_ena ),
.cmt_instret_ena (cmt_instret_ena ),
.cmt_status_ena (cmt_status_ena ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.cmt_mret_ena (cmt_mret_ena ),
.csr_epc_r (csr_epc_r ),
.csr_dpc_r (csr_dpc_r ),
.csr_mtvec_r (csr_mtvec_r ),
.flush_pulse (flush_pulse ),
.flush_req (flush_req ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
.pipe_flush_add_op2 (pipe_flush_add_op2),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
// The Decode to IFU read-en used for the branch dependency check
// only need to check the integer regfile, so here we need to exclude
// the FPU condition out
assign dec2ifu_rden = disp_oitf_rdwen & (~disp_oitf_rdfpu);
assign dec2ifu_rs1en = disp_oitf_rs1en & (~disp_oitf_rs1fpu);
assign dec2ifu_rdidx = dec_rdidx;
assign rf2ifu_rs1 = rf_rs1;
e203_exu_csr u_e203_exu_csr(
.csr_access_ilgl (csr_access_ilgl),
.eai_xs_off (eai_xs_off),
.nonflush_cmt_ena (nonflush_cmt_ena),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.mdv_nob2b (mdv_nob2b),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop ),
.csr_ena (csr_ena),
.csr_idx (csr_idx),
.csr_rd_en (csr_rd_en),
.csr_wr_en (csr_wr_en),
.read_csr_dat (read_csr_dat),
.wbck_csr_dat (wbck_csr_dat),
.cmt_badaddr (cmt_badaddr ),
.cmt_badaddr_ena (cmt_badaddr_ena),
.cmt_epc (cmt_epc ),
.cmt_epc_ena (cmt_epc_ena ),
.cmt_cause (cmt_cause ),
.cmt_cause_ena (cmt_cause_ena ),
.cmt_instret_ena (cmt_instret_ena ),
.cmt_status_ena (cmt_status_ena ),
.cmt_mret_ena (cmt_mret_ena ),
.csr_epc_r (csr_epc_r ),
.csr_dpc_r (csr_dpc_r ),
.csr_mtvec_r (csr_mtvec_r ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_stopcycle (dbg_stopcycle),
.u_mode (u_mode),
.s_mode (s_mode),
.h_mode (h_mode),
.m_mode (m_mode),
.core_mhartid (core_mhartid),
.status_mie_r (status_mie_r),
.mtie_r (mtie_r ),
.msie_r (msie_r ),
.meie_r (meie_r ),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.clk_aon (clk_aon ),
.clk (clk ),
.rst_n (rst_n )
);
assign exu_active = (~oitf_empty) | i_valid | excp_active;
endmodule |
module sirv_spigpioport_2(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds
);
wire T_267;
reg T_271;
reg [31:0] GEN_0;
reg T_272;
reg [31:0] GEN_1;
reg T_273;
reg [31:0] GEN_2;
wire T_274;
reg T_278;
reg [31:0] GEN_3;
reg T_279;
reg [31:0] GEN_4;
reg T_280;
reg [31:0] GEN_5;
wire T_281;
reg T_285;
reg [31:0] GEN_6;
reg T_286;
reg [31:0] GEN_7;
reg T_287;
reg [31:0] GEN_8;
wire T_288;
reg T_292;
reg [31:0] GEN_9;
reg T_293;
reg [31:0] GEN_10;
reg T_294;
reg [31:0] GEN_11;
assign io_spi_dq_0_i = T_273;
assign io_spi_dq_1_i = T_280;
assign io_spi_dq_2_i = T_287;
assign io_spi_dq_3_i = T_294;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h1;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_267;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h1;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_274;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h1;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_281;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h1;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_288;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h1;
assign io_pins_cs_0_o_oval = io_spi_cs_0;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h1;
assign T_267 = ~ io_spi_dq_0_oe;
assign T_274 = ~ io_spi_dq_1_oe;
assign T_281 = ~ io_spi_dq_2_oe;
assign T_288 = ~ io_spi_dq_3_oe;
always @(posedge clock or posedge reset) begin
if(reset) begin
T_271 <= 1'b0;
T_272 <= 1'b0;
T_273 <= 1'b0;
T_278 <= 1'b0;
T_279 <= 1'b0;
T_280 <= 1'b0;
T_285 <= 1'b0;
T_286 <= 1'b0;
T_287 <= 1'b0;
T_292 <= 1'b0;
T_293 <= 1'b0;
T_294 <= 1'b0;
end
else begin
T_271 <= io_pins_dq_0_i_ival;
T_272 <= T_271;
T_273 <= T_272;
T_278 <= io_pins_dq_1_i_ival;
T_279 <= T_278;
T_280 <= T_279;
T_285 <= io_pins_dq_2_i_ival;
T_286 <= T_285;
T_287 <= T_286;
T_292 <= io_pins_dq_3_i_ival;
T_293 <= T_292;
T_294 <= T_293;
end
end
endmodule |
module e203_ifu_minidec(
//////////////////////////////////////////////////////////////
// The IR stage to Decoder
input [`E203_INSTR_SIZE-1:0] instr,
//////////////////////////////////////////////////////////////
// The Decoded Info-Bus
output dec_rs1en,
output dec_rs2en,
output [`E203_RFIDX_WIDTH-1:0] dec_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] dec_rs2idx,
output dec_mulhsu,
output dec_mul ,
output dec_div ,
output dec_rem ,
output dec_divu ,
output dec_remu ,
output dec_rv32,
output dec_bjp,
output dec_jal,
output dec_jalr,
output dec_bxx,
output [`E203_RFIDX_WIDTH-1:0] dec_jalr_rs1idx,
output [`E203_XLEN-1:0] dec_bjp_imm
);
e203_exu_decode u_e203_exu_decode(
.i_instr(instr),
.i_pc(`E203_PC_SIZE'b0),
.i_prdt_taken(1'b0),
.i_muldiv_b2b(1'b0),
.i_misalgn (1'b0),
.i_buserr (1'b0),
.dbg_mode (1'b0),
.dec_misalgn(),
.dec_buserr(),
.dec_ilegl(),
.dec_rs1x0(),
.dec_rs2x0(),
.dec_rs1en(dec_rs1en),
.dec_rs2en(dec_rs2en),
.dec_rdwen(),
.dec_rs1idx(dec_rs1idx),
.dec_rs2idx(dec_rs2idx),
.dec_rdidx(),
.dec_info(),
.dec_imm(),
.dec_pc(),
.dec_mulhsu(dec_mulhsu),
.dec_mul (dec_mul ),
.dec_div (dec_div ),
.dec_rem (dec_rem ),
.dec_divu (dec_divu ),
.dec_remu (dec_remu ),
.dec_rv32(dec_rv32),
.dec_bjp (dec_bjp ),
.dec_jal (dec_jal ),
.dec_jalr(dec_jalr),
.dec_bxx (dec_bxx ),
.dec_jalr_rs1idx(dec_jalr_rs1idx),
.dec_bjp_imm (dec_bjp_imm )
);
endmodule |
module sirv_AsyncResetRegVec(
input clock,
input reset,
input io_d,
output io_q,
input io_en
);
wire reg_0_rst;
wire reg_0_clk;
wire reg_0_en;
wire reg_0_q;
wire reg_0_d;
sirv_AsyncResetReg reg_0 (
.rst(reg_0_rst),
.clk(reg_0_clk),
.en(reg_0_en),
.q(reg_0_q),
.d(reg_0_d)
);
assign io_q = reg_0_q;
assign reg_0_rst = reset;
assign reg_0_clk = clock;
assign reg_0_en = io_en;
assign reg_0_d = io_d;
endmodule |
module e203_biu(
output biu_active,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from LSU
input lsu2biu_icb_cmd_valid,
output lsu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr,
input lsu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask,
input [1:0] lsu2biu_icb_cmd_burst,
input [1:0] lsu2biu_icb_cmd_beat,
input lsu2biu_icb_cmd_lock,
input lsu2biu_icb_cmd_excl,
input [1:0] lsu2biu_icb_cmd_size,
output lsu2biu_icb_rsp_valid,
input lsu2biu_icb_rsp_ready,
output lsu2biu_icb_rsp_err ,
output lsu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata,
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// the icb interface from ifetch
//
// * bus cmd channel
input ifu2biu_icb_cmd_valid,
output ifu2biu_icb_cmd_ready,
input [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr,
input ifu2biu_icb_cmd_read,
input [`E203_XLEN-1:0] ifu2biu_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ifu2biu_icb_cmd_wmask,
input [1:0] ifu2biu_icb_cmd_burst,
input [1:0] ifu2biu_icb_cmd_beat,
input ifu2biu_icb_cmd_lock,
input ifu2biu_icb_cmd_excl,
input [1:0] ifu2biu_icb_cmd_size,
//
// * bus rsp channel
output ifu2biu_icb_rsp_valid,
input ifu2biu_icb_rsp_ready,
output ifu2biu_icb_rsp_err ,
output ifu2biu_icb_rsp_excl_ok,
output [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata,
//output ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
//
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output [1:0] ppi_icb_cmd_burst,
output [1:0] ppi_icb_cmd_beat,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
// * Bus cmd channel
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output [1:0] clint_icb_cmd_burst,
output [1:0] clint_icb_cmd_beat,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
//
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
// * Bus cmd channel
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output [1:0] plic_icb_cmd_burst,
output [1:0] plic_icb_cmd_beat,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
input fio_icb_enable,
//
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output [1:0] fio_icb_cmd_burst,
output [1:0] fio_icb_cmd_beat,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
input clk,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_ARBT_I_NUM = 2;
localparam BIU_ARBT_I_PTR_W = 1;
`else//}{
localparam BIU_ARBT_I_NUM = 1;
localparam BIU_ARBT_I_PTR_W = 1;
`endif//}
// The SPLT_NUM is the sum of following components
// * ppi, clint, plic, SystemITF, Fast-IO, IFU-err
localparam BIU_SPLT_I_NUM_0 = 4;
`ifdef E203_HAS_MEM_ITF //{
localparam BIU_SPLT_I_NUM_1 = (BIU_SPLT_I_NUM_0 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_1 = BIU_SPLT_I_NUM_0;
`endif//}
`ifdef E203_HAS_FIO //{
localparam BIU_SPLT_I_NUM_2 = (BIU_SPLT_I_NUM_1 + 1);
`else//}{
localparam BIU_SPLT_I_NUM_2 = BIU_SPLT_I_NUM_1;
`endif//}
localparam BIU_SPLT_I_NUM = BIU_SPLT_I_NUM_2;
wire ifuerr_icb_cmd_valid;
wire ifuerr_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifuerr_icb_cmd_addr;
wire ifuerr_icb_cmd_read;
wire [2-1:0] ifuerr_icb_cmd_burst;
wire [2-1:0] ifuerr_icb_cmd_beat;
wire [`E203_XLEN-1:0] ifuerr_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] ifuerr_icb_cmd_wmask;
wire ifuerr_icb_cmd_lock;
wire ifuerr_icb_cmd_excl;
wire [1:0] ifuerr_icb_cmd_size;
wire ifuerr_icb_rsp_valid;
wire ifuerr_icb_rsp_ready;
wire ifuerr_icb_rsp_err ;
wire ifuerr_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifuerr_icb_rsp_rdata;
wire arbt_icb_cmd_valid;
wire arbt_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] arbt_icb_cmd_addr;
wire arbt_icb_cmd_read;
wire [`E203_XLEN-1:0] arbt_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] arbt_icb_cmd_wmask;
wire [1:0] arbt_icb_cmd_burst;
wire [1:0] arbt_icb_cmd_beat;
wire arbt_icb_cmd_lock;
wire arbt_icb_cmd_excl;
wire [1:0] arbt_icb_cmd_size;
wire arbt_icb_cmd_usr;
wire arbt_icb_rsp_valid;
wire arbt_icb_rsp_ready;
wire arbt_icb_rsp_err;
wire arbt_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] arbt_icb_rsp_rdata;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_ready;
wire [BIU_ARBT_I_NUM*`E203_ADDR_SIZE-1:0] arbt_bus_icb_cmd_addr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_read;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_cmd_wdata;
wire [BIU_ARBT_I_NUM*`E203_XLEN/8-1:0] arbt_bus_icb_cmd_wmask;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_burst;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_beat;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_lock;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_excl;
wire [BIU_ARBT_I_NUM*2-1:0] arbt_bus_icb_cmd_size;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_cmd_usr;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_valid;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_ready;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_err;
wire [BIU_ARBT_I_NUM*1-1:0] arbt_bus_icb_rsp_excl_ok;
wire [BIU_ARBT_I_NUM*`E203_XLEN-1:0] arbt_bus_icb_rsp_rdata;
//CMD Channel
assign arbt_bus_icb_cmd_valid =
// The LSU take higher priority
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_valid,
`endif//}
lsu2biu_icb_cmd_valid
} ;
assign arbt_bus_icb_cmd_addr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_addr,
`endif//}
lsu2biu_icb_cmd_addr
} ;
assign arbt_bus_icb_cmd_read =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_read,
`endif//}
lsu2biu_icb_cmd_read
} ;
assign arbt_bus_icb_cmd_wdata =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wdata,
`endif//}
lsu2biu_icb_cmd_wdata
} ;
assign arbt_bus_icb_cmd_wmask =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_wmask,
`endif//}
lsu2biu_icb_cmd_wmask
} ;
assign arbt_bus_icb_cmd_burst =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_burst,
`endif//}
lsu2biu_icb_cmd_burst
} ;
assign arbt_bus_icb_cmd_beat =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_beat,
`endif//}
lsu2biu_icb_cmd_beat
} ;
assign arbt_bus_icb_cmd_lock =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_lock,
`endif//}
lsu2biu_icb_cmd_lock
} ;
assign arbt_bus_icb_cmd_excl =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_excl,
`endif//}
lsu2biu_icb_cmd_excl
} ;
assign arbt_bus_icb_cmd_size =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_size,
`endif//}
lsu2biu_icb_cmd_size
} ;
wire ifu2biu_icb_cmd_ifu = 1'b1;
wire lsu2biu_icb_cmd_ifu = 1'b0;
assign arbt_bus_icb_cmd_usr =
{
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ifu,
`endif//}
lsu2biu_icb_cmd_ifu
} ;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_cmd_ready,
`endif//}
lsu2biu_icb_cmd_ready
} = arbt_bus_icb_cmd_ready;
//RSP Channel
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_valid,
`endif//}
lsu2biu_icb_rsp_valid
} = arbt_bus_icb_rsp_valid;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_err,
`endif//}
lsu2biu_icb_rsp_err
} = arbt_bus_icb_rsp_err;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_excl_ok,
`endif//}
lsu2biu_icb_rsp_excl_ok
} = arbt_bus_icb_rsp_excl_ok;
assign {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_rdata,
`endif//}
lsu2biu_icb_rsp_rdata
} = arbt_bus_icb_rsp_rdata;
assign arbt_bus_icb_rsp_ready = {
`ifdef E203_HAS_MEM_ITF //{
ifu2biu_icb_rsp_ready,
`endif//}
lsu2biu_icb_rsp_ready
};
sirv_gnrl_icb_arbt # (
.ARBT_SCHEME (0),// Priority based
.ALLOW_0CYCL_RSP (0),// Dont allow the 0 cycle response because in BIU we always have CMD_DP larger than 0
// when the response come back from the external bus, it is at least 1 cycle later
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.ARBT_NUM (BIU_ARBT_I_NUM),
.ARBT_PTR_W (BIU_ARBT_I_PTR_W),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_arbt(
.o_icb_cmd_valid (arbt_icb_cmd_valid ) ,
.o_icb_cmd_ready (arbt_icb_cmd_ready ) ,
.o_icb_cmd_read (arbt_icb_cmd_read ) ,
.o_icb_cmd_addr (arbt_icb_cmd_addr ) ,
.o_icb_cmd_wdata (arbt_icb_cmd_wdata ) ,
.o_icb_cmd_wmask (arbt_icb_cmd_wmask) ,
.o_icb_cmd_burst (arbt_icb_cmd_burst) ,
.o_icb_cmd_beat (arbt_icb_cmd_beat ) ,
.o_icb_cmd_excl (arbt_icb_cmd_excl ) ,
.o_icb_cmd_lock (arbt_icb_cmd_lock ) ,
.o_icb_cmd_size (arbt_icb_cmd_size ) ,
.o_icb_cmd_usr (arbt_icb_cmd_usr ) ,
.o_icb_rsp_valid (arbt_icb_rsp_valid ) ,
.o_icb_rsp_ready (arbt_icb_rsp_ready ) ,
.o_icb_rsp_err (arbt_icb_rsp_err) ,
.o_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok) ,
.o_icb_rsp_rdata (arbt_icb_rsp_rdata ) ,
.o_icb_rsp_usr (1'b0 ) ,
.i_bus_icb_cmd_ready (arbt_bus_icb_cmd_ready ) ,
.i_bus_icb_cmd_valid (arbt_bus_icb_cmd_valid ) ,
.i_bus_icb_cmd_read (arbt_bus_icb_cmd_read ) ,
.i_bus_icb_cmd_addr (arbt_bus_icb_cmd_addr ) ,
.i_bus_icb_cmd_wdata (arbt_bus_icb_cmd_wdata ) ,
.i_bus_icb_cmd_wmask (arbt_bus_icb_cmd_wmask) ,
.i_bus_icb_cmd_burst (arbt_bus_icb_cmd_burst),
.i_bus_icb_cmd_beat (arbt_bus_icb_cmd_beat ),
.i_bus_icb_cmd_excl (arbt_bus_icb_cmd_excl ),
.i_bus_icb_cmd_lock (arbt_bus_icb_cmd_lock ),
.i_bus_icb_cmd_size (arbt_bus_icb_cmd_size ),
.i_bus_icb_cmd_usr (arbt_bus_icb_cmd_usr ),
.i_bus_icb_rsp_valid (arbt_bus_icb_rsp_valid ) ,
.i_bus_icb_rsp_ready (arbt_bus_icb_rsp_ready ) ,
.i_bus_icb_rsp_err (arbt_bus_icb_rsp_err) ,
.i_bus_icb_rsp_excl_ok (arbt_bus_icb_rsp_excl_ok),
.i_bus_icb_rsp_rdata (arbt_bus_icb_rsp_rdata ) ,
.i_bus_icb_rsp_usr () ,
.clk (clk ) ,
.rst_n (rst_n)
);
//// To breakup the dead-lock cases, when incoming load/store request to the BIU but not granted
//// This kind of potential deadlock case only happened at the low end core, where the ifetch response
//// provided to IFU, but IFU cannot accept it because it is waiting the IR stage to be cleared, and IR
//// stage is waiting the LSU to be cleared, and LSU is waiting this BIU to be cleared.
//// At any mid of high end core (or with multiple oustandings), we definitely will update IFU
//// to make sure it always can accept any oustanding transactions traded with area cost.
//// So back to this very low end core, to save areas, we prefetch without knowing if IR can accept
//// the response or not, and also in very low end core it is just 1 oustanding (multiple oustanding
//// belong to mid or high end core), so to cut off this deadlocks, we just let the BIU to trigger
//// and replay indication if LSU cannot get granted, if IFU just overkilly forced to be replayed, it
//// just lost performance, but we dont care, because in low end core, ifetch to system mem is not
//// guranteed by performance. If IFU really suppose to be replayed, then good luck to break this deadlock.
//wire ifu_replay_r;
//// The IFU replay will be set when:
//// * Accessed by non-IFU access
//// * Or non-IFU access is to access ITCM, but not granted
//wire ifu_replay_set = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & lsu2biu_icb_cmd_valid)
// | (lsu2biu_icb_cmd_valid & (~lsu2biu_icb_cmd_ready));
//// The IFU replay will be cleared after accessed by a IFU access
//wire ifu_replay_clr = (arbt_icb_cmd_valid & arbt_icb_cmd_ready & ifu2biu_icb_cmd_valid);
//wire ifu_replay_ena = ifu_replay_set | ifu_replay_clr;
//wire ifu_replay_nxt = ifu_replay_set | (~ifu_replay_clr);
//sirv_gnrl_dfflr #(1)ifu_replay_dffl(ifu_replay_ena, ifu_replay_nxt, ifu_replay_r, clk, rst_n);
//assign ifu2biu_replay = ifu_replay_r;
wire buf_icb_cmd_valid;
wire buf_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] buf_icb_cmd_addr;
wire buf_icb_cmd_read;
wire [`E203_XLEN-1:0] buf_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] buf_icb_cmd_wmask;
wire [1:0] buf_icb_cmd_burst;
wire [1:0] buf_icb_cmd_beat;
wire buf_icb_cmd_lock;
wire buf_icb_cmd_excl;
wire [1:0] buf_icb_cmd_size;
wire buf_icb_cmd_usr;
wire buf_icb_cmd_ifu = buf_icb_cmd_usr;
wire buf_icb_rsp_valid;
wire buf_icb_rsp_ready;
wire buf_icb_rsp_err;
wire buf_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] buf_icb_rsp_rdata;
wire icb_buffer_active;
sirv_gnrl_icb_buffer # (
.OUTS_CNT_W (`E203_BIU_OUTS_CNT_W),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN),
.CMD_DP(`E203_BIU_CMD_DP),
.RSP_DP(`E203_BIU_RSP_DP),
.CMD_CUT_READY (`E203_BIU_CMD_CUT_READY),
.RSP_CUT_READY (`E203_BIU_RSP_CUT_READY),
.USR_W (1)
)u_sirv_gnrl_icb_buffer(
.icb_buffer_active (icb_buffer_active),
.i_icb_cmd_valid (arbt_icb_cmd_valid),
.i_icb_cmd_ready (arbt_icb_cmd_ready),
.i_icb_cmd_read (arbt_icb_cmd_read ),
.i_icb_cmd_addr (arbt_icb_cmd_addr ),
.i_icb_cmd_wdata (arbt_icb_cmd_wdata),
.i_icb_cmd_wmask (arbt_icb_cmd_wmask),
.i_icb_cmd_lock (arbt_icb_cmd_lock ),
.i_icb_cmd_excl (arbt_icb_cmd_excl ),
.i_icb_cmd_size (arbt_icb_cmd_size ),
.i_icb_cmd_burst (arbt_icb_cmd_burst),
.i_icb_cmd_beat (arbt_icb_cmd_beat ),
.i_icb_cmd_usr (arbt_icb_cmd_usr ),
.i_icb_rsp_valid (arbt_icb_rsp_valid),
.i_icb_rsp_ready (arbt_icb_rsp_ready),
.i_icb_rsp_err (arbt_icb_rsp_err ),
.i_icb_rsp_excl_ok (arbt_icb_rsp_excl_ok),
.i_icb_rsp_rdata (arbt_icb_rsp_rdata),
.i_icb_rsp_usr (),
.o_icb_cmd_valid (buf_icb_cmd_valid),
.o_icb_cmd_ready (buf_icb_cmd_ready),
.o_icb_cmd_read (buf_icb_cmd_read ),
.o_icb_cmd_addr (buf_icb_cmd_addr ),
.o_icb_cmd_wdata (buf_icb_cmd_wdata),
.o_icb_cmd_wmask (buf_icb_cmd_wmask),
.o_icb_cmd_lock (buf_icb_cmd_lock ),
.o_icb_cmd_excl (buf_icb_cmd_excl ),
.o_icb_cmd_size (buf_icb_cmd_size ),
.o_icb_cmd_burst (buf_icb_cmd_burst),
.o_icb_cmd_beat (buf_icb_cmd_beat ),
.o_icb_cmd_usr (buf_icb_cmd_usr),
.o_icb_rsp_valid (buf_icb_rsp_valid),
.o_icb_rsp_ready (buf_icb_rsp_ready),
.o_icb_rsp_err (buf_icb_rsp_err ),
.o_icb_rsp_excl_ok (buf_icb_rsp_excl_ok),
.o_icb_rsp_rdata (buf_icb_rsp_rdata),
.o_icb_rsp_usr (1'b0 ),
.clk (clk ),
.rst_n (rst_n)
);
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_ready;
wire [BIU_SPLT_I_NUM*`E203_ADDR_SIZE-1:0] splt_bus_icb_cmd_addr;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_read;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_cmd_wdata;
wire [BIU_SPLT_I_NUM*`E203_XLEN/8-1:0] splt_bus_icb_cmd_wmask;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_burst;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_beat;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_lock;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_cmd_excl;
wire [BIU_SPLT_I_NUM*2-1:0] splt_bus_icb_cmd_size;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_valid;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_ready;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_err;
wire [BIU_SPLT_I_NUM*1-1:0] splt_bus_icb_rsp_excl_ok;
wire [BIU_SPLT_I_NUM*`E203_XLEN-1:0] splt_bus_icb_rsp_rdata;
//CMD Channel
assign {
ifuerr_icb_cmd_valid
, ppi_icb_cmd_valid
, clint_icb_cmd_valid
, plic_icb_cmd_valid
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_valid
`endif//}
} = splt_bus_icb_cmd_valid;
assign {
ifuerr_icb_cmd_addr
, ppi_icb_cmd_addr
, clint_icb_cmd_addr
, plic_icb_cmd_addr
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_addr
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_addr
`endif//}
} = splt_bus_icb_cmd_addr;
assign {
ifuerr_icb_cmd_read
, ppi_icb_cmd_read
, clint_icb_cmd_read
, plic_icb_cmd_read
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_read
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_read
`endif//}
} = splt_bus_icb_cmd_read;
assign {
ifuerr_icb_cmd_wdata
, ppi_icb_cmd_wdata
, clint_icb_cmd_wdata
, plic_icb_cmd_wdata
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wdata
`endif//}
} = splt_bus_icb_cmd_wdata;
assign {
ifuerr_icb_cmd_wmask
, ppi_icb_cmd_wmask
, clint_icb_cmd_wmask
, plic_icb_cmd_wmask
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_wmask
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_wmask
`endif//}
} = splt_bus_icb_cmd_wmask;
assign {
ifuerr_icb_cmd_burst
, ppi_icb_cmd_burst
, clint_icb_cmd_burst
, plic_icb_cmd_burst
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_burst
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_burst
`endif//}
} = splt_bus_icb_cmd_burst;
assign {
ifuerr_icb_cmd_beat
, ppi_icb_cmd_beat
, clint_icb_cmd_beat
, plic_icb_cmd_beat
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_beat
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_beat
`endif//}
} = splt_bus_icb_cmd_beat;
assign {
ifuerr_icb_cmd_lock
, ppi_icb_cmd_lock
, clint_icb_cmd_lock
, plic_icb_cmd_lock
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_lock
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_lock
`endif//}
} = splt_bus_icb_cmd_lock;
assign {
ifuerr_icb_cmd_excl
, ppi_icb_cmd_excl
, clint_icb_cmd_excl
, plic_icb_cmd_excl
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_excl
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_excl
`endif//}
} = splt_bus_icb_cmd_excl;
assign {
ifuerr_icb_cmd_size
, ppi_icb_cmd_size
, clint_icb_cmd_size
, plic_icb_cmd_size
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_size
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_size
`endif//}
} = splt_bus_icb_cmd_size;
assign splt_bus_icb_cmd_ready = {
ifuerr_icb_cmd_ready
, ppi_icb_cmd_ready
, clint_icb_cmd_ready
, plic_icb_cmd_ready
`ifdef E203_HAS_FIO //{
, fio_icb_cmd_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_cmd_ready
`endif//}
};
//RSP Channel
assign splt_bus_icb_rsp_valid = {
ifuerr_icb_rsp_valid
, ppi_icb_rsp_valid
, clint_icb_rsp_valid
, plic_icb_rsp_valid
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_valid
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_valid
`endif//}
};
assign splt_bus_icb_rsp_err = {
ifuerr_icb_rsp_err
, ppi_icb_rsp_err
, clint_icb_rsp_err
, plic_icb_rsp_err
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_err
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_err
`endif//}
};
assign splt_bus_icb_rsp_excl_ok = {
ifuerr_icb_rsp_excl_ok
, ppi_icb_rsp_excl_ok
, clint_icb_rsp_excl_ok
, plic_icb_rsp_excl_ok
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_excl_ok
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_excl_ok
`endif//}
};
assign splt_bus_icb_rsp_rdata = {
ifuerr_icb_rsp_rdata
, ppi_icb_rsp_rdata
, clint_icb_rsp_rdata
, plic_icb_rsp_rdata
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_rdata
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_rdata
`endif//}
};
assign {
ifuerr_icb_rsp_ready
, ppi_icb_rsp_ready
, clint_icb_rsp_ready
, plic_icb_rsp_ready
`ifdef E203_HAS_FIO //{
, fio_icb_rsp_ready
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, mem_icb_rsp_ready
`endif//}
} = splt_bus_icb_rsp_ready;
wire buf_icb_cmd_ppi = ppi_icb_enable & (buf_icb_cmd_addr[`E203_PPI_BASE_REGION] == ppi_region_indic[`E203_PPI_BASE_REGION]);
wire buf_icb_sel_ppi = buf_icb_cmd_ppi & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_clint = clint_icb_enable & (buf_icb_cmd_addr[`E203_CLINT_BASE_REGION] == clint_region_indic[`E203_CLINT_BASE_REGION]);
wire buf_icb_sel_clint = buf_icb_cmd_clint & (~buf_icb_cmd_ifu);
wire buf_icb_cmd_plic = plic_icb_enable & (buf_icb_cmd_addr[`E203_PLIC_BASE_REGION] == plic_region_indic[`E203_PLIC_BASE_REGION]);
wire buf_icb_sel_plic = buf_icb_cmd_plic & (~buf_icb_cmd_ifu);
`ifdef E203_HAS_FIO //{
wire buf_icb_cmd_fio = fio_icb_enable & (buf_icb_cmd_addr[`E203_FIO_BASE_REGION] == fio_region_indic[`E203_FIO_BASE_REGION]);
wire buf_icb_sel_fio = buf_icb_cmd_fio & (~buf_icb_cmd_ifu);
`endif//}
wire buf_icb_sel_ifuerr =(
buf_icb_cmd_ppi
| buf_icb_cmd_clint
| buf_icb_cmd_plic
`ifdef E203_HAS_FIO //{
| buf_icb_cmd_fio
`endif//}
) & buf_icb_cmd_ifu;
`ifdef E203_HAS_MEM_ITF //{
wire buf_icb_sel_mem = mem_icb_enable
& (~buf_icb_sel_ifuerr)
& (~buf_icb_sel_ppi)
& (~buf_icb_sel_clint)
& (~buf_icb_sel_plic)
`ifdef E203_HAS_FIO //{
& (~buf_icb_sel_fio)
`endif//}
;
`endif//}
wire [BIU_SPLT_I_NUM-1:0] buf_icb_splt_indic =
{
buf_icb_sel_ifuerr
, buf_icb_sel_ppi
, buf_icb_sel_clint
, buf_icb_sel_plic
`ifdef E203_HAS_FIO //{
, buf_icb_sel_fio
`endif//}
`ifdef E203_HAS_MEM_ITF //{
, buf_icb_sel_mem
`endif//}
};
sirv_gnrl_icb_splt # (
.ALLOW_DIFF (0),// Dont allow different branches oustanding
.ALLOW_0CYCL_RSP (1),// Allow the 0 cycle response because in BIU the splt
// is after the buffer, and will directly talk to the external
// bus, where maybe the ROM is 0 cycle responsed.
.FIFO_OUTS_NUM (`E203_BIU_OUTS_NUM),
.FIFO_CUT_READY (`E203_BIU_CMD_CUT_READY),
.SPLT_NUM (BIU_SPLT_I_NUM),
.SPLT_PTR_W (BIU_SPLT_I_NUM),
.SPLT_PTR_1HOT (1),
.USR_W (1),
.AW (`E203_ADDR_SIZE),
.DW (`E203_XLEN)
) u_biu_icb_splt(
.i_icb_splt_indic (buf_icb_splt_indic),
.i_icb_cmd_valid (buf_icb_cmd_valid ) ,
.i_icb_cmd_ready (buf_icb_cmd_ready ) ,
.i_icb_cmd_read (buf_icb_cmd_read ) ,
.i_icb_cmd_addr (buf_icb_cmd_addr ) ,
.i_icb_cmd_wdata (buf_icb_cmd_wdata ) ,
.i_icb_cmd_wmask (buf_icb_cmd_wmask) ,
.i_icb_cmd_burst (buf_icb_cmd_burst) ,
.i_icb_cmd_beat (buf_icb_cmd_beat ) ,
.i_icb_cmd_excl (buf_icb_cmd_excl ) ,
.i_icb_cmd_lock (buf_icb_cmd_lock ) ,
.i_icb_cmd_size (buf_icb_cmd_size ) ,
.i_icb_cmd_usr (1'b0 ) ,
.i_icb_rsp_valid (buf_icb_rsp_valid ) ,
.i_icb_rsp_ready (buf_icb_rsp_ready ) ,
.i_icb_rsp_err (buf_icb_rsp_err) ,
.i_icb_rsp_excl_ok (buf_icb_rsp_excl_ok) ,
.i_icb_rsp_rdata (buf_icb_rsp_rdata ) ,
.i_icb_rsp_usr ( ) ,
.o_bus_icb_cmd_ready (splt_bus_icb_cmd_ready ) ,
.o_bus_icb_cmd_valid (splt_bus_icb_cmd_valid ) ,
.o_bus_icb_cmd_read (splt_bus_icb_cmd_read ) ,
.o_bus_icb_cmd_addr (splt_bus_icb_cmd_addr ) ,
.o_bus_icb_cmd_wdata (splt_bus_icb_cmd_wdata ) ,
.o_bus_icb_cmd_wmask (splt_bus_icb_cmd_wmask) ,
.o_bus_icb_cmd_burst (splt_bus_icb_cmd_burst),
.o_bus_icb_cmd_beat (splt_bus_icb_cmd_beat ),
.o_bus_icb_cmd_excl (splt_bus_icb_cmd_excl ),
.o_bus_icb_cmd_lock (splt_bus_icb_cmd_lock ),
.o_bus_icb_cmd_size (splt_bus_icb_cmd_size ),
.o_bus_icb_cmd_usr () ,
.o_bus_icb_rsp_valid (splt_bus_icb_rsp_valid ) ,
.o_bus_icb_rsp_ready (splt_bus_icb_rsp_ready ) ,
.o_bus_icb_rsp_err (splt_bus_icb_rsp_err) ,
.o_bus_icb_rsp_excl_ok (splt_bus_icb_rsp_excl_ok),
.o_bus_icb_rsp_rdata (splt_bus_icb_rsp_rdata ) ,
.o_bus_icb_rsp_usr ({BIU_SPLT_I_NUM{1'b0}}) ,
.clk (clk ) ,
.rst_n (rst_n)
);
assign biu_active = ifu2biu_icb_cmd_valid | lsu2biu_icb_cmd_valid | icb_buffer_active;
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////
// Implement the IFU-accessed-Peripheral region error
assign ifuerr_icb_cmd_ready = ifuerr_icb_rsp_ready;
// 0 Cycle response
assign ifuerr_icb_rsp_valid = ifuerr_icb_cmd_valid;
assign ifuerr_icb_rsp_err = 1'b1;
assign ifuerr_icb_rsp_excl_ok = 1'b0;
assign ifuerr_icb_rsp_rdata = {`E203_XLEN{1'b0}};
endmodule |
module sirv_sim_ram
#(parameter DP = 512,
parameter FORCE_X2ZERO = 0,
parameter DW = 32,
parameter MW = 4,
parameter AW = 32
)
(
input clk,
input [DW-1 :0] din,
input [AW-1 :0] addr,
input cs,
input we,
input [MW-1:0] wem,
output [DW-1:0] dout
);
reg [DW-1:0] mem_r [0:DP-1];
reg [AW-1:0] addr_r;
wire [MW-1:0] wen;
wire ren;
assign ren = cs & (~we);
assign wen = ({MW{cs & we}} & wem);
genvar i;
always @(posedge clk)
begin
if (ren) begin
addr_r <= addr;
end
end
generate
for (i = 0; i < MW; i = i+1) begin :mem
if((8*i+8) > DW ) begin: last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][DW-1:8*i] <= din[DW-1:8*i];
end
end
end
else begin: non_last
always @(posedge clk) begin
if (wen[i]) begin
mem_r[addr][8*i+7:8*i] <= din[8*i+7:8*i];
end
end
end
end
endgenerate
wire [DW-1:0] dout_pre;
assign dout_pre = mem_r[addr_r];
generate
if(FORCE_X2ZERO == 1) begin: force_x_to_zero
for (i = 0; i < DW; i = i+1) begin:force_x_gen
`ifndef SYNTHESIS//{
assign dout[i] = (dout_pre[i] === 1'bx) ? 1'b0 : dout_pre[i];
`else//}{
assign dout[i] = dout_pre[i];
`endif//}
end
end
else begin:no_force_x_to_zero
assign dout = dout_pre;
end
endgenerate
endmodule |
module sirv_debug_csr
#(
parameter PC_SIZE = 32
)(
// The interface with commit stage
input [PC_SIZE-1:0] cmt_dpc,
input cmt_dpc_ena,
input [3-1:0] cmt_dcause,
input cmt_dcause_ena,
input dbg_irq_r,
// The interface with CSR control
input wr_dcsr_ena ,
input wr_dpc_ena ,
input wr_dscratch_ena,
input [32-1:0] wr_csr_nxt ,
output[32-1:0] dcsr_r ,
output[PC_SIZE-1:0] dpc_r ,
output[32-1:0] dscratch_r,
output dbg_mode,
output dbg_halt_r,
output dbg_step_r,
output dbg_ebreakm_r,
output dbg_stopcycle,
input clk,
input rst_n
);
// Implement DPC reg
wire dpc_ena = wr_dpc_ena | cmt_dpc_ena;
wire [PC_SIZE-1:0] dpc_nxt;
assign dpc_nxt[PC_SIZE-1:1] =
cmt_dpc_ena ? cmt_dpc[PC_SIZE-1:1]
: wr_csr_nxt[PC_SIZE-1:1];
assign dpc_nxt[0] = 1'b0;
sirv_gnrl_dfflr #(PC_SIZE) dpc_dfflr (dpc_ena, dpc_nxt, dpc_r, clk, rst_n);
// Implement Dbg Scratch reg
wire dscratch_ena = wr_dscratch_ena;
wire [32-1:0] dscratch_nxt;
assign dscratch_nxt = wr_csr_nxt;
sirv_gnrl_dfflr #(32) dscratch_dfflr (dscratch_ena, dscratch_nxt, dscratch_r, clk, rst_n);
// We dont support the HW Trigger Module yet now
// Implement dcsr reg
//
// The ndreset field
wire ndreset_ena = wr_dcsr_ena & wr_csr_nxt[29];
wire ndreset_nxt;
wire ndreset_r;
assign ndreset_nxt = wr_csr_nxt[29];
sirv_gnrl_dfflr #(1) ndreset_dfflr (ndreset_ena, ndreset_nxt, ndreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The fullreset field
wire fullreset_ena = wr_dcsr_ena & wr_csr_nxt[28];
wire fullreset_nxt;
wire fullreset_r;
assign fullreset_nxt = wr_csr_nxt[28];
sirv_gnrl_dfflr #(1) fullreset_dfflr (fullreset_ena, fullreset_nxt, fullreset_r, clk, rst_n);
// This bit is not used as rocket impelmentation
//
// The cause field
wire dcause_ena = cmt_dcause_ena;
wire [3-1:0] dcause_r;
wire [3-1:0] dcause_nxt = cmt_dcause;
sirv_gnrl_dfflr #(3) dcause_dfflr (dcause_ena, dcause_nxt, dcause_r, clk, rst_n);
//
// The halt field
wire halt_ena = wr_dcsr_ena;
wire halt_nxt;
wire halt_r;
assign halt_nxt = wr_csr_nxt[3];
sirv_gnrl_dfflr #(1) halt_dfflr (halt_ena, halt_nxt, halt_r, clk, rst_n);
//
// The step field
wire step_ena = wr_dcsr_ena;
wire step_nxt;
wire step_r;
assign step_nxt = wr_csr_nxt[2];
sirv_gnrl_dfflr #(1) step_dfflr (step_ena, step_nxt, step_r, clk, rst_n);
//
// The ebreakm field
wire ebreakm_ena = wr_dcsr_ena;
wire ebreakm_nxt;
wire ebreakm_r;
assign ebreakm_nxt = wr_csr_nxt[15];
sirv_gnrl_dfflr #(1) ebreakm_dfflr (ebreakm_ena, ebreakm_nxt, ebreakm_r, clk, rst_n);
//
// // The stopcycle field
//wire stopcycle_ena = wr_dcsr_ena;
//wire stopcycle_nxt;
//wire stopcycle_r;
//assign stopcycle_nxt = wr_csr_nxt[10];
//sirv_gnrl_dfflr #(1) stopcycle_dfflr (stopcycle_ena, stopcycle_nxt, stopcycle_r, clk, rst_n);
// //
// // The stoptime field
//wire stoptime_ena = wr_dcsr_ena;
//wire stoptime_nxt;
//wire stoptime_r;
//assign stoptime_nxt = wr_csr_nxt[9];
//sirv_gnrl_dfflr #(1) stoptime_dfflr (stoptime_ena, stoptime_nxt, stoptime_r, clk, rst_n);
assign dbg_stopcycle = 1'b1;
assign dcsr_r [31:30] = 2'd1;
assign dcsr_r [29:16] = 14'b0;
assign dcsr_r [15:12] = {4{ebreakm_r}};// we replicated the ebreakm for all ebreakh/s/u
assign dcsr_r [11] = 1'b0;
assign dcsr_r [10] = dbg_stopcycle;// Not writeable this bit is constant
assign dcsr_r [9] = 1'b0;//stoptime_r; Not use this bit same as rocket implmementation
assign dcsr_r [8:6] = dcause_r;
assign dcsr_r [5] = dbg_irq_r;
assign dcsr_r [4] = 1'b0;
assign dcsr_r [3] = halt_r;
assign dcsr_r [2] = step_r;
assign dcsr_r [1:0] = 2'b11;
assign dbg_mode = ~(dcause_r == 3'b0);
assign dbg_halt_r = halt_r;
assign dbg_step_r = step_r;
assign dbg_ebreakm_r = ebreakm_r;
endmodule |
module i2c_master_top(
wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_inta_o,
scl_pad_i, scl_pad_o, scl_padoen_o, sda_pad_i, sda_pad_o, sda_padoen_o );
// parameters
parameter ARST_LVL = 1'b0; // asynchronous reset level
//
// inputs & outputs
//
// wishbone signals
input wb_clk_i; // master clock input
input wb_rst_i; // synchronous active high reset
input arst_i; // asynchronous reset
input [2:0] wb_adr_i; // lower address bits
input [7:0] wb_dat_i; // databus input
output [7:0] wb_dat_o; // databus output
input wb_we_i; // write enable input
input wb_stb_i; // stobe/core select signal
input wb_cyc_i; // valid bus cycle input
output wb_ack_o; // bus cycle acknowledge output
output wb_inta_o; // interrupt request signal output
reg [7:0] wb_dat_o;
reg wb_ack_o;
reg wb_inta_o;
// I2C signals
// i2c clock line
input scl_pad_i; // SCL-line input
output scl_pad_o; // SCL-line output (always 1'b0)
output scl_padoen_o; // SCL-line output enable (active low)
// i2c data line
input sda_pad_i; // SDA-line input
output sda_pad_o; // SDA-line output (always 1'b0)
output sda_padoen_o; // SDA-line output enable (active low)
//
// variable declarations
//
// registers
reg [15:0] prer; // clock prescale register
reg [ 7:0] ctr; // control register
reg [ 7:0] txr; // transmit register
wire [ 7:0] rxr; // receive register
reg [ 7:0] cr; // command register
wire [ 7:0] sr; // status register
// done signal: command completed, clear command register
wire done;
// core enable signal
wire core_en;
wire ien;
// status register signals
wire irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
// generate internal reset
wire rst_i = arst_i ^ ARST_LVL;
// generate wishbone signals
wire wb_wacc = wb_cyc_i & wb_stb_i & wb_we_i;
// generate acknowledge output signal
always @(posedge wb_clk_i or negedge rst_i)
//always @(posedge wb_clk_i)//Bob: Here the ack is X by default, so add the rst here
if (!rst_i)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & ~wb_ack_o; // because timing is always honored
// assign DAT_O
always @(posedge wb_clk_i)
begin
case (wb_adr_i) // synopsis parallel_case
3'b000: wb_dat_o <= #1 prer[ 7:0];
3'b001: wb_dat_o <= #1 prer[15:8];
3'b010: wb_dat_o <= #1 ctr;
3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
3'b101: wb_dat_o <= #1 txr;
3'b110: wb_dat_o <= #1 cr;
3'b111: wb_dat_o <= #1 0; // reserved
endcase
end
// generate registers
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else if (wb_rst_i)
begin
prer <= #1 16'hffff;
ctr <= #1 8'h0;
txr <= #1 8'h0;
end
else
if (wb_wacc)
case (wb_adr_i) // synopsis parallel_case
3'b000 : prer [ 7:0] <= #1 wb_dat_i;
3'b001 : prer [15:8] <= #1 wb_dat_i;
3'b010 : ctr <= #1 wb_dat_i;
3'b011 : txr <= #1 wb_dat_i;
//default: ; //Bob: here have a lint warning, so commented it out
endcase
// generate command register (special case)
always @(posedge wb_clk_i or negedge rst_i)
if (~rst_i)
cr <= #1 8'h0;
else if (wb_rst_i)
cr <= #1 8'h0;
else if (wb_wacc)
begin
if (core_en & (wb_adr_i == 3'b100) )
cr <= #1 wb_dat_i;
end
else
begin
if (done | i2c_al)
cr[7:4] <= #1 4'h0; // clear command bits when done
// or when aribitration lost
cr[2:1] <= #1 2'b0; // reserved bits
cr[0] <= #1 2'b0; // clear IRQ_ACK bit
end
// decode command register
wire sta = cr[7];
wire sto = cr[6];
wire rd = cr[5];
wire wr = cr[4];
wire ack = cr[3];
wire iack = cr[0];
// decode control register
assign core_en = ctr[7];
assign ien = ctr[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( wb_clk_i ),
.rst ( wb_rst_i ),
.nReset ( rst_i ),
.ena ( core_en ),
.clk_cnt ( prer ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( txr ),
.cmd_ack ( done ),
.ack_out ( irxack ),
.dout ( rxr ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else if (wb_rst_i)
begin
al <= #1 1'b0;
rxack <= #1 1'b0;
tip <= #1 1'b0;
irq_flag <= #1 1'b0;
end
else
begin
al <= #1 i2c_al | (al & ~sta);
rxack <= #1 irxack;
tip <= #1 (rd | wr);
irq_flag <= #1 (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
end
// generate interrupt request signals
always @(posedge wb_clk_i or negedge rst_i)
if (!rst_i)
wb_inta_o <= #1 1'b0;
else if (wb_rst_i)
wb_inta_o <= #1 1'b0;
else
wb_inta_o <= #1 irq_flag && ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
// assign status register bits
assign sr[7] = rxack;
assign sr[6] = i2c_busy;
assign sr[5] = al;
assign sr[4:2] = 3'h0; // reserved
assign sr[1] = tip;
assign sr[0] = irq_flag;
endmodule |
module sirv_jtag_dtm (
//JTAG Interface
jtag_TDI,
jtag_TDO,
jtag_TCK,
jtag_TMS,
jtag_TRST,
jtag_DRV_TDO,
dtm_req_valid,
dtm_req_ready,
dtm_req_bits,
dtm_resp_valid,
dtm_resp_ready,
dtm_resp_bits
);
//--------------------------------------------------------
// Parameter Declarations
parameter ASYNC_FF_LEVELS = 2;
parameter DEBUG_DATA_BITS = 34;
parameter DEBUG_ADDR_BITS = 5; // Spec allows values are 5-7
parameter DEBUG_OP_BITS = 2; // OP and RESP are the same size.
parameter JTAG_VERSION = 4'h1;
parameter JTAG_PART_NUM = 16'h0E31; // E31
parameter JTAG_MANUF_ID = 11'h489; // As Assigned by JEDEC
// Number of cycles which must remain in IDLE
// The software should handle even if the
// answer is actually higher than this, or
// the software may choose to ignore it entirely
// and just check for busy.
parameter DBUS_IDLE_CYCLES = 3'h5;
localparam IR_BITS = 5;
localparam DEBUG_VERSION = 0;
// JTAG State Machine
localparam TEST_LOGIC_RESET = 4'h0;
localparam RUN_TEST_IDLE = 4'h1;
localparam SELECT_DR = 4'h2;
localparam CAPTURE_DR = 4'h3;
localparam SHIFT_DR = 4'h4;
localparam EXIT1_DR = 4'h5;
localparam PAUSE_DR = 4'h6;
localparam EXIT2_DR = 4'h7;
localparam UPDATE_DR = 4'h8;
localparam SELECT_IR = 4'h9;
localparam CAPTURE_IR = 4'hA;
localparam SHIFT_IR = 4'hB;
localparam EXIT1_IR = 4'hC;
localparam PAUSE_IR = 4'hD;
localparam EXIT2_IR = 4'hE;
localparam UPDATE_IR = 4'hF;
//RISCV DTM Registers (see RISC-V Debug Specification)
// All others are treated as 'BYPASS'.
localparam REG_BYPASS = 5'b11111;
localparam REG_IDCODE = 5'b00001;
localparam REG_DEBUG_ACCESS = 5'b10001;
localparam REG_DTM_INFO = 5'b10000;
localparam DBUS_REG_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
localparam DBUS_REQ_BITS = DEBUG_OP_BITS + DEBUG_ADDR_BITS + DEBUG_DATA_BITS;
localparam DBUS_RESP_BITS = DEBUG_OP_BITS + DEBUG_DATA_BITS;
localparam SHIFT_REG_BITS = DBUS_REG_BITS;
//--------------------------------------------------------
// I/O Declarations
//JTAG SIDE
input jtag_TDI;
output reg jtag_TDO;
input jtag_TCK;
input jtag_TMS;
input jtag_TRST;
// To allow tri-state outside of this block.
output reg jtag_DRV_TDO;
// RISC-V Core Side
output dtm_req_valid;
input dtm_req_ready;
output [DBUS_REQ_BITS - 1 :0] dtm_req_bits;
input dtm_resp_valid;
output dtm_resp_ready;
input [DBUS_RESP_BITS - 1 : 0] dtm_resp_bits;
wire i_dtm_req_valid;
wire i_dtm_req_ready;
wire [DBUS_REQ_BITS - 1 :0] i_dtm_req_bits;
wire i_dtm_resp_valid;
wire i_dtm_resp_ready;
wire[DBUS_RESP_BITS - 1 : 0] i_dtm_resp_bits;
//--------------------------------------------------------
// Reg and Wire Declarations
reg [IR_BITS -1 : 0 ] irReg;
wire [31:0] idcode;
wire [31:0] dtminfo;
reg [DBUS_REG_BITS - 1 : 0] dbusReg;
reg dbusValidReg;
reg [3:0] jtagStateReg;
reg [SHIFT_REG_BITS -1 : 0] shiftReg;
reg doDbusWriteReg;
reg doDbusReadReg;
reg busyReg;
reg stickyBusyReg;
reg stickyNonzeroRespReg;
reg skipOpReg; // Skip op because we're busy.
reg downgradeOpReg; // Downgrade op because prev. op failed.
wire busy;
wire nonzeroResp;
wire [SHIFT_REG_BITS -1 : 0] busyResponse;
wire [SHIFT_REG_BITS -1 : 0] nonbusyResponse;
//--------------------------------------------------------
// Combo Logic
assign idcode = {JTAG_VERSION, JTAG_PART_NUM, JTAG_MANUF_ID, 1'h1};
wire [3:0] debugAddrBits = DEBUG_ADDR_BITS[3:0];
wire [3:0] debugVersion = DEBUG_VERSION[3:0];
wire [1:0] dbusStatus;
wire [2:0] dbusIdleCycles;
wire dbusReset;
assign dbusIdleCycles = DBUS_IDLE_CYCLES;
assign dbusStatus = {stickyNonzeroRespReg, stickyNonzeroRespReg | stickyBusyReg};
assign dbusReset = shiftReg[16];
assign dtminfo = {15'b0,
1'b0, // dbusreset goes here but is write-only
3'b0,
dbusIdleCycles,
dbusStatus,
debugAddrBits,
debugVersion};
//busy, dtm_resp* is only valid during CAPTURE_DR,
// so these signals should only be used at that time.
// This assumes there is only one transaction in flight at a time.
assign busy = (busyReg & ~i_dtm_resp_valid) | stickyBusyReg;
// This is needed especially for the first request.
assign nonzeroResp = (i_dtm_resp_valid ? | {i_dtm_resp_bits[DEBUG_OP_BITS-1:0]} : 1'b0) | stickyNonzeroRespReg;
// Interface to DM.
// Note that this means i_dtm_resp_bits must only be used during CAPTURE_DR.
assign i_dtm_resp_ready = (jtagStateReg == CAPTURE_DR) &&
(irReg == REG_DEBUG_ACCESS) &&
i_dtm_resp_valid;
assign i_dtm_req_valid = dbusValidReg;
assign i_dtm_req_bits = dbusReg;
assign busyResponse = {{(DEBUG_ADDR_BITS + DEBUG_DATA_BITS){1'b0}},
{(DEBUG_OP_BITS){1'b1}}}; // Generalizing 'busy' to 'all-1'
assign nonbusyResponse = {dbusReg[(DEBUG_DATA_BITS + DEBUG_OP_BITS) +: DEBUG_ADDR_BITS] , // retain address bits from Req.
i_dtm_resp_bits[DEBUG_OP_BITS +: DEBUG_DATA_BITS] , // data
i_dtm_resp_bits[0 +: DEBUG_OP_BITS] // response
};
//--------------------------------------------------------
// Sequential Logic
// JTAG STATE MACHINE
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
jtagStateReg <= TEST_LOGIC_RESET;
end else begin
case (jtagStateReg)
TEST_LOGIC_RESET : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : RUN_TEST_IDLE;
RUN_TEST_IDLE : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
SELECT_DR : jtagStateReg <= jtag_TMS ? SELECT_IR : CAPTURE_DR;
CAPTURE_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
SHIFT_DR : jtagStateReg <= jtag_TMS ? EXIT1_DR : SHIFT_DR;
EXIT1_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : PAUSE_DR;
PAUSE_DR : jtagStateReg <= jtag_TMS ? EXIT2_DR : PAUSE_DR;
EXIT2_DR : jtagStateReg <= jtag_TMS ? UPDATE_DR : SHIFT_DR;
UPDATE_DR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
SELECT_IR : jtagStateReg <= jtag_TMS ? TEST_LOGIC_RESET : CAPTURE_IR;
CAPTURE_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
SHIFT_IR : jtagStateReg <= jtag_TMS ? EXIT1_IR : SHIFT_IR;
EXIT1_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : PAUSE_IR;
PAUSE_IR : jtagStateReg <= jtag_TMS ? EXIT2_IR : PAUSE_IR;
EXIT2_IR : jtagStateReg <= jtag_TMS ? UPDATE_IR : SHIFT_IR;
UPDATE_IR : jtagStateReg <= jtag_TMS ? SELECT_DR : RUN_TEST_IDLE;
endcase // case (jtagStateReg)
end // else: !if(jtag_TRST)
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
// SHIFT REG
always @(posedge jtag_TCK) begin
case (jtagStateReg)
CAPTURE_IR : shiftReg <= {{(SHIFT_REG_BITS-1){1'b0}}, 1'b1}; //JTAG spec only says must end with 'b01.
SHIFT_IR : shiftReg <= {{(SHIFT_REG_BITS-IR_BITS){1'b0}}, jtag_TDI, shiftReg[IR_BITS-1 : 1]};
CAPTURE_DR : case (irReg)
REG_BYPASS : shiftReg <= {(SHIFT_REG_BITS){1'b0}};
REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, idcode};
REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, dtminfo};
REG_DEBUG_ACCESS : shiftReg <= busy ? busyResponse : nonbusyResponse;
default : //BYPASS
shiftReg <= {(SHIFT_REG_BITS){1'b0}};
endcase
SHIFT_DR : case (irReg)
REG_BYPASS : shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}}, jtag_TDI};
REG_IDCODE : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
REG_DTM_INFO : shiftReg <= {{(SHIFT_REG_BITS-32){1'b0}}, jtag_TDI, shiftReg[31:1]};
REG_DEBUG_ACCESS : shiftReg <= {jtag_TDI, shiftReg[SHIFT_REG_BITS -1 : 1 ]};
default: // BYPASS
shiftReg <= {{(SHIFT_REG_BITS- 1){1'b0}} , jtag_TDI};
endcase // case (irReg)
endcase // case (jtagStateReg)
end
// IR
always @(negedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
irReg <= REG_IDCODE;
end else if (jtagStateReg == TEST_LOGIC_RESET) begin
irReg <= REG_IDCODE;
end else if (jtagStateReg == UPDATE_IR) begin
irReg <= shiftReg[IR_BITS-1:0];
end
end
// Busy. We become busy when we first try to send a request.
// We stop being busy when we accept a response.
// This means that busyReg will still be set when we check it,
// so the logic for checking busy looks ahead.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
busyReg <= 1'b0;
end else if (i_dtm_req_valid) begin //UPDATE_DR onwards
busyReg <= 1'b1;
end else if (i_dtm_resp_valid & i_dtm_resp_ready) begin //only in CAPTURE_DR
busyReg <= 1'b0;
end
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
// Downgrade/Skip. We make the decision to downgrade or skip
// during every CAPTURE_DR, and use the result in UPDATE_DR.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
skipOpReg <= 1'b0;
downgradeOpReg <= 1'b0;
stickyBusyReg <= 1'b0;
stickyNonzeroRespReg <= 1'b0;
end else if (irReg == REG_DEBUG_ACCESS) begin
case(jtagStateReg)
CAPTURE_DR: begin
skipOpReg <= busy;
downgradeOpReg <= (~busy & nonzeroResp);
stickyBusyReg <= busy;
stickyNonzeroRespReg <= nonzeroResp;
end
UPDATE_DR: begin
skipOpReg <= 1'b0;
downgradeOpReg <= 1'b0;
end
endcase // case (jtagStateReg)
end else if (irReg == REG_DTM_INFO) begin
case(jtagStateReg)
UPDATE_DR: begin
if (dbusReset) begin
stickyNonzeroRespReg <= 1'b0;
stickyBusyReg <= 1'b0;
end
end
endcase // case (jtagStateReg)
end
end // always @ (posedge jtag_TCK or posedge jtag_TRST)
//dbusReg, dbusValidReg.
always @(posedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
dbusReg <= {(DBUS_REG_BITS) {1'b0}};
dbusValidReg <= 1'b0;
end else if (jtagStateReg == UPDATE_DR) begin
if (irReg == REG_DEBUG_ACCESS) begin
if (skipOpReg) begin
// do nothing.
end else if (downgradeOpReg) begin
dbusReg <= {(DBUS_REG_BITS){1'b0}}; // NOP has encoding 2'b00.
dbusValidReg <= 1'b1;
end else begin
dbusReg <= shiftReg[DBUS_REG_BITS-1:0];
dbusValidReg <= 1'b1;
end
end
end else if (i_dtm_req_ready) begin
dbusValidReg <= 1'b0;
end
end // always @ (negedge jtag_TCK or posedge jtag_TRST)
//TDO
always @(negedge jtag_TCK or posedge jtag_TRST) begin
if (jtag_TRST) begin
jtag_TDO <= 1'b0;
jtag_DRV_TDO <= 1'b0;
end else if (jtagStateReg == SHIFT_IR) begin
jtag_TDO <= shiftReg[0];
jtag_DRV_TDO <= 1'b1;
end else if (jtagStateReg == SHIFT_DR) begin
jtag_TDO <= shiftReg[0];
jtag_DRV_TDO <= 1'b1;
end else begin
jtag_TDO <= 1'b0;
jtag_DRV_TDO <= 1'b0;
end
end // always @ (negedge jtag_TCK or posedge jtag_TRST)
sirv_gnrl_cdc_tx
# (
.DW (41),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_jtag2debug_cdc_tx (
.o_vld (dtm_req_valid),
.o_rdy_a(dtm_req_ready),
.o_dat (dtm_req_bits ),
.i_vld (i_dtm_req_valid),
.i_rdy (i_dtm_req_ready),
.i_dat (i_dtm_req_bits ),
.clk (jtag_TCK),
.rst_n (~jtag_TRST)
);
sirv_gnrl_cdc_rx
# (
.DW (36),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_jtag2debug_cdc_rx (
.i_vld_a(dtm_resp_valid),
.i_rdy (dtm_resp_ready),
.i_dat (dtm_resp_bits ),
.o_vld (i_dtm_resp_valid),
.o_rdy (i_dtm_resp_ready),
.o_dat (i_dtm_resp_bits ),
.clk (jtag_TCK),
.rst_n (~jtag_TRST)
);
endmodule |
module sirv_spigpioport(
input clock,
input reset,
input io_spi_sck,
output io_spi_dq_0_i,
input io_spi_dq_0_o,
input io_spi_dq_0_oe,
output io_spi_dq_1_i,
input io_spi_dq_1_o,
input io_spi_dq_1_oe,
output io_spi_dq_2_i,
input io_spi_dq_2_o,
input io_spi_dq_2_oe,
output io_spi_dq_3_i,
input io_spi_dq_3_o,
input io_spi_dq_3_oe,
input io_spi_cs_0,
input io_spi_cs_1,
input io_spi_cs_2,
input io_spi_cs_3,
input io_pins_sck_i_ival,
output io_pins_sck_o_oval,
output io_pins_sck_o_oe,
output io_pins_sck_o_ie,
output io_pins_sck_o_pue,
output io_pins_sck_o_ds,
input io_pins_dq_0_i_ival,
output io_pins_dq_0_o_oval,
output io_pins_dq_0_o_oe,
output io_pins_dq_0_o_ie,
output io_pins_dq_0_o_pue,
output io_pins_dq_0_o_ds,
input io_pins_dq_1_i_ival,
output io_pins_dq_1_o_oval,
output io_pins_dq_1_o_oe,
output io_pins_dq_1_o_ie,
output io_pins_dq_1_o_pue,
output io_pins_dq_1_o_ds,
input io_pins_dq_2_i_ival,
output io_pins_dq_2_o_oval,
output io_pins_dq_2_o_oe,
output io_pins_dq_2_o_ie,
output io_pins_dq_2_o_pue,
output io_pins_dq_2_o_ds,
input io_pins_dq_3_i_ival,
output io_pins_dq_3_o_oval,
output io_pins_dq_3_o_oe,
output io_pins_dq_3_o_ie,
output io_pins_dq_3_o_pue,
output io_pins_dq_3_o_ds,
input io_pins_cs_0_i_ival,
output io_pins_cs_0_o_oval,
output io_pins_cs_0_o_oe,
output io_pins_cs_0_o_ie,
output io_pins_cs_0_o_pue,
output io_pins_cs_0_o_ds,
input io_pins_cs_1_i_ival,
output io_pins_cs_1_o_oval,
output io_pins_cs_1_o_oe,
output io_pins_cs_1_o_ie,
output io_pins_cs_1_o_pue,
output io_pins_cs_1_o_ds,
input io_pins_cs_2_i_ival,
output io_pins_cs_2_o_oval,
output io_pins_cs_2_o_oe,
output io_pins_cs_2_o_ie,
output io_pins_cs_2_o_pue,
output io_pins_cs_2_o_ds,
input io_pins_cs_3_i_ival,
output io_pins_cs_3_o_oval,
output io_pins_cs_3_o_oe,
output io_pins_cs_3_o_ie,
output io_pins_cs_3_o_pue,
output io_pins_cs_3_o_ds
);
wire T_312;
wire T_315;
wire T_318;
wire T_321;
wire [1:0] T_324;
wire [1:0] T_325;
wire [3:0] T_326;
wire T_330;
wire T_331;
wire T_332;
wire T_333;
assign io_spi_dq_0_i = io_pins_dq_0_i_ival;
assign io_spi_dq_1_i = io_pins_dq_1_i_ival;
assign io_spi_dq_2_i = io_pins_dq_2_i_ival;
assign io_spi_dq_3_i = io_pins_dq_3_i_ival;
assign io_pins_sck_o_oval = io_spi_sck;
assign io_pins_sck_o_oe = 1'h1;
assign io_pins_sck_o_ie = 1'h0;
assign io_pins_sck_o_pue = 1'h0;
assign io_pins_sck_o_ds = 1'h0;
assign io_pins_dq_0_o_oval = io_spi_dq_0_o;
assign io_pins_dq_0_o_oe = io_spi_dq_0_oe;
assign io_pins_dq_0_o_ie = T_312;
assign io_pins_dq_0_o_pue = 1'h1;
assign io_pins_dq_0_o_ds = 1'h0;
assign io_pins_dq_1_o_oval = io_spi_dq_1_o;
assign io_pins_dq_1_o_oe = io_spi_dq_1_oe;
assign io_pins_dq_1_o_ie = T_315;
assign io_pins_dq_1_o_pue = 1'h1;
assign io_pins_dq_1_o_ds = 1'h0;
assign io_pins_dq_2_o_oval = io_spi_dq_2_o;
assign io_pins_dq_2_o_oe = io_spi_dq_2_oe;
assign io_pins_dq_2_o_ie = T_318;
assign io_pins_dq_2_o_pue = 1'h1;
assign io_pins_dq_2_o_ds = 1'h0;
assign io_pins_dq_3_o_oval = io_spi_dq_3_o;
assign io_pins_dq_3_o_oe = io_spi_dq_3_oe;
assign io_pins_dq_3_o_ie = T_321;
assign io_pins_dq_3_o_pue = 1'h1;
assign io_pins_dq_3_o_ds = 1'h0;
assign io_pins_cs_0_o_oval = T_330;
assign io_pins_cs_0_o_oe = 1'h1;
assign io_pins_cs_0_o_ie = 1'h0;
assign io_pins_cs_0_o_pue = 1'h0;
assign io_pins_cs_0_o_ds = 1'h0;
assign io_pins_cs_1_o_oval = T_331;
assign io_pins_cs_1_o_oe = 1'h1;
assign io_pins_cs_1_o_ie = 1'h0;
assign io_pins_cs_1_o_pue = 1'h0;
assign io_pins_cs_1_o_ds = 1'h0;
assign io_pins_cs_2_o_oval = T_332;
assign io_pins_cs_2_o_oe = 1'h1;
assign io_pins_cs_2_o_ie = 1'h0;
assign io_pins_cs_2_o_pue = 1'h0;
assign io_pins_cs_2_o_ds = 1'h0;
assign io_pins_cs_3_o_oval = T_333;
assign io_pins_cs_3_o_oe = 1'h1;
assign io_pins_cs_3_o_ie = 1'h0;
assign io_pins_cs_3_o_pue = 1'h0;
assign io_pins_cs_3_o_ds = 1'h0;
assign T_312 = ~ io_spi_dq_0_oe;
assign T_315 = ~ io_spi_dq_1_oe;
assign T_318 = ~ io_spi_dq_2_oe;
assign T_321 = ~ io_spi_dq_3_oe;
assign T_324 = {io_spi_cs_1,io_spi_cs_0};
assign T_325 = {io_spi_cs_3,io_spi_cs_2};
assign T_326 = {T_325,T_324};
assign T_330 = T_326[0];
assign T_331 = T_326[1];
assign T_332 = T_326[2];
assign T_333 = T_326[3];
endmodule |
module e203_exu_csr(
input nonflush_cmt_ena,
output eai_xs_off,
input csr_ena,
input csr_wr_en,
input csr_rd_en,
input [12-1:0] csr_idx,
output csr_access_ilgl,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
output itcm_nohold,
output mdv_nob2b,
output [`E203_XLEN-1:0] read_csr_dat,
input [`E203_XLEN-1:0] wbck_csr_dat,
input [`E203_HART_ID_W-1:0] core_mhartid,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
output status_mie_r,
output mtie_r,
output msie_r,
output meie_r,
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
input [`E203_XLEN-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [`E203_XLEN-1:0] dscratch_r,
output [`E203_XLEN-1:0] wr_csr_nxt ,
input dbg_mode,
input dbg_stopcycle,
output u_mode,
output s_mode,
output h_mode,
output m_mode,
input [`E203_ADDR_SIZE-1:0] cmt_badaddr,
input cmt_badaddr_ena,
input [`E203_PC_SIZE-1:0] cmt_epc,
input cmt_epc_ena,
input [`E203_XLEN-1:0] cmt_cause,
input cmt_cause_ena,
input cmt_status_ena,
input cmt_instret_ena,
input cmt_mret_ena,
output[`E203_PC_SIZE-1:0] csr_epc_r,
output[`E203_PC_SIZE-1:0] csr_dpc_r,
output[`E203_XLEN-1:0] csr_mtvec_r,
input clk_aon,
input clk,
input rst_n
);
assign csr_access_ilgl = 1'b0
;
// Only toggle when need to read or write to save power
wire wbck_csr_wen = csr_wr_en & csr_ena & (~csr_access_ilgl);
wire read_csr_ena = csr_rd_en & csr_ena & (~csr_access_ilgl);
wire [1:0] priv_mode = u_mode ? 2'b00 :
s_mode ? 2'b01 :
h_mode ? 2'b10 :
m_mode ? 2'b11 :
2'b11;
//0x000 URW ustatus User status register.
// * Since we support the user-level interrupt, hence we need to support UIE
//0x300 MRW mstatus Machine status register.
wire sel_ustatus = (csr_idx == 12'h000);
wire sel_mstatus = (csr_idx == 12'h300);
wire rd_ustatus = sel_ustatus & csr_rd_en;
wire rd_mstatus = sel_mstatus & csr_rd_en;
wire wr_ustatus = sel_ustatus & csr_wr_en;
wire wr_mstatus = sel_mstatus & csr_wr_en;
/////////////////////////////////////////////////////////////////////
// Note: the below implementation only apply to Machine-mode config,
// if other mode is also supported, these logics need to be updated
//////////////////////////
// Implement MPIE field
//
wire status_mpie_r;
// The MPIE Feilds will be updates when:
wire status_mpie_ena =
// The CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) |
// The MRET instruction commited
cmt_mret_ena |
// The Trap is taken
cmt_status_ena;
wire status_mpie_nxt =
// See Priv SPEC:
// When a trap is taken from privilege mode y into privilege
// mode x, xPIE is set to the value of xIE;
// So, When the Trap is taken, the MPIE is updated with the current MIE value
cmt_status_ena ? status_mie_r :
// See Priv SPEC:
// When executing an xRET instruction, supposing xPP holds the value y, xIE
// is set to xPIE; the privilege mode is changed to y;
// xPIE is set to 1;
// So, When the MRET instruction commited, the MPIE is updated with 1
cmt_mret_ena ? 1'b1 :
// When the CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) ? wbck_csr_dat[7] : // MPIE is in field 7 of mstatus
status_mpie_r; // Unchanged
sirv_gnrl_dfflr #(1) status_mpie_dfflr (status_mpie_ena, status_mpie_nxt, status_mpie_r, clk, rst_n);
//////////////////////////
// Implement MIE field
//
// The MIE Feilds will be updates same as MPIE
wire status_mie_ena = status_mpie_ena;
wire status_mie_nxt =
// See Priv SPEC:
// When a trap is taken from privilege mode y into privilege
// mode x, xPIE is set to the value of xIE,
// xIE is set to 0;
// So, When the Trap is taken, the MIE is updated with 0
cmt_status_ena ? 1'b0 :
// See Priv SPEC:
// When executing an xRET instruction, supposing xPP holds the value y, xIE
// is set to xPIE; the privilege mode is changed to y, xPIE is set to 1;
// So, When the MRET instruction commited, the MIE is updated with MPIE
cmt_mret_ena ? status_mpie_r :
// When the CSR is written by CSR instructions
(wr_mstatus & wbck_csr_wen) ? wbck_csr_dat[3] : // MIE is in field 3 of mstatus
status_mie_r; // Unchanged
sirv_gnrl_dfflr #(1) status_mie_dfflr (status_mie_ena, status_mie_nxt, status_mie_r, clk, rst_n);
//////////////////////////
// Implement SD field
//
// See Priv SPEC:
// The SD bit is read-only
// And is set when either the FS or XS bits encode a Dirty
// state (i.e., SD=((FS==11) OR (XS==11))).
wire [1:0] status_fs_r;
wire [1:0] status_xs_r;
wire status_sd_r = (status_fs_r == 2'b11) | (status_xs_r == 2'b11);
//////////////////////////
// Implement XS field
//
// See Priv SPEC:
// XS field is read-only
// The XS field represents a summary of all extensions' status
// But in E200 we implement XS exactly same as FS to make it usable by software to
// disable extended accelerators
`ifndef E203_HAS_EAI
// If no EAI coprocessor interface configured, the XS is just hardwired to 0
assign status_xs_r = 2'b0;
assign eai_xs_off = 1'b0;// We just make this signal to 0
`endif
//////////////////////////
// Implement FS field
//
`ifndef E203_HAS_FPU
// If no FPU configured, the FS is just hardwired to 0
assign status_fs_r = 2'b0;
`endif
//////////////////////////
// Pack to the full mstatus register
//
wire [`E203_XLEN-1:0] status_r;
assign status_r[31] = status_sd_r; //SD
assign status_r[30:23] = 8'b0; // Reserved
assign status_r[22:17] = 6'b0; // TSR--MPRV
assign status_r[16:15] = status_xs_r; // XS
assign status_r[14:13] = status_fs_r; // FS
assign status_r[12:11] = 2'b11; // MPP
assign status_r[10:9] = 2'b0; // Reserved
assign status_r[8] = 1'b0; // SPP
assign status_r[7] = status_mpie_r; // MPIE
assign status_r[6] = 1'b0; // Reserved
assign status_r[5] = 1'b0; // SPIE
assign status_r[4] = 1'b0; // UPIE
assign status_r[3] = status_mie_r; // MIE
assign status_r[2] = 1'b0; // Reserved
assign status_r[1] = 1'b0; // SIE
assign status_r[0] = 1'b0; // UIE
wire [`E203_XLEN-1:0] csr_mstatus = status_r;
//0x004 URW uie User interrupt-enable register.
// * Since we dont delegate interrupt to user mode, hence it is as all 0s
//0x304 MRW mie Machine interrupt-enable register.
wire sel_mie = (csr_idx == 12'h304);
wire rd_mie = sel_mie & csr_rd_en;
wire wr_mie = sel_mie & csr_wr_en;
wire mie_ena = wr_mie & wbck_csr_wen;
wire [`E203_XLEN-1:0] mie_r;
wire [`E203_XLEN-1:0] mie_nxt;
assign mie_nxt[31:12] = 20'b0;
assign mie_nxt[11] = wbck_csr_dat[11];//MEIE
assign mie_nxt[10:8] = 3'b0;
assign mie_nxt[ 7] = wbck_csr_dat[ 7];//MTIE
assign mie_nxt[6:4] = 3'b0;
assign mie_nxt[ 3] = wbck_csr_dat[ 3];//MSIE
assign mie_nxt[2:0] = 3'b0;
sirv_gnrl_dfflr #(`E203_XLEN) mie_dfflr (mie_ena, mie_nxt, mie_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mie = mie_r;
assign meie_r = csr_mie[11];
assign mtie_r = csr_mie[ 7];
assign msie_r = csr_mie[ 3];
//0x044 URW uip User interrupt pending.
// We dont support delegation scheme, so no need to support the uip
//0x344 MRW mip Machine interrupt pending
wire sel_mip = (csr_idx == 12'h344);
wire rd_mip = sel_mip & csr_rd_en;
//wire wr_mip = sel_mip & csr_wr_en;
// The MxIP is read-only
wire meip_r;
wire msip_r;
wire mtip_r;
sirv_gnrl_dffr #(1) meip_dffr (ext_irq_r, meip_r, clk, rst_n);
sirv_gnrl_dffr #(1) msip_dffr (sft_irq_r, msip_r, clk, rst_n);
sirv_gnrl_dffr #(1) mtip_dffr (tmr_irq_r, mtip_r, clk, rst_n);
wire [`E203_XLEN-1:0] ip_r;
assign ip_r[31:12] = 20'b0;
assign ip_r[11] = meip_r;
assign ip_r[10:8] = 3'b0;
assign ip_r[ 7] = mtip_r;
assign ip_r[6:4] = 3'b0;
assign ip_r[ 3] = msip_r;
assign ip_r[2:0] = 3'b0;
wire [`E203_XLEN-1:0] csr_mip = ip_r;
//
//0x005 URW utvec User trap handler base address.
// We dont support user trap, so no utvec needed
//0x305 MRW mtvec Machine trap-handler base address.
wire sel_mtvec = (csr_idx == 12'h305);
wire rd_mtvec = csr_rd_en & sel_mtvec;
`ifdef E203_SUPPORT_MTVEC //{
wire wr_mtvec = sel_mtvec & csr_wr_en;
wire mtvec_ena = (wr_mtvec & wbck_csr_wen);
wire [`E203_XLEN-1:0] mtvec_r;
wire [`E203_XLEN-1:0] mtvec_nxt = wbck_csr_dat;
sirv_gnrl_dfflr #(`E203_XLEN) mtvec_dfflr (mtvec_ena, mtvec_nxt, mtvec_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mtvec = mtvec_r;
`else//}{
// THe vector table base is a configurable parameter, so we dont support writeable to it
wire [`E203_XLEN-1:0] csr_mtvec = `E203_MTVEC_TRAP_BASE;
`endif//}
assign csr_mtvec_r = csr_mtvec;
//0x340 MRW mscratch
wire sel_mscratch = (csr_idx == 12'h340);
wire rd_mscratch = sel_mscratch & csr_rd_en;
`ifdef E203_SUPPORT_MSCRATCH //{
wire wr_mscratch = sel_mscratch & csr_wr_en;
wire mscratch_ena = (wr_mscratch & wbck_csr_wen);
wire [`E203_XLEN-1:0] mscratch_r;
wire [`E203_XLEN-1:0] mscratch_nxt = wbck_csr_dat;
sirv_gnrl_dfflr #(`E203_XLEN) mscratch_dfflr (mscratch_ena, mscratch_nxt, mscratch_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mscratch = mscratch_r;
`else//}{
wire [`E203_XLEN-1:0] csr_mscratch = `E203_XLEN'b0;
`endif//}
// 0xB00 MRW mcycle
// 0xB02 MRW minstret
// 0xB80 MRW mcycleh
// 0xB82 MRW minstreth
wire sel_mcycle = (csr_idx == 12'hB00);
wire sel_mcycleh = (csr_idx == 12'hB80);
wire sel_minstret = (csr_idx == 12'hB02);
wire sel_minstreth = (csr_idx == 12'hB82);
// 0xBFF MRW counterstop
// This register is our self-defined register to stop
// the cycle/time/instret counters to save dynamic powers
wire sel_counterstop = (csr_idx == 12'hBFF);// This address is not used by ISA
// 0xBFE MRW mcgstop
// This register is our self-defined register to disable the
// automaticall clock gating for CPU logics for debugging purpose
wire sel_mcgstop = (csr_idx == 12'hBFE);// This address is not used by ISA
// 0xBFD MRW itcmnohold
// This register is our self-defined register to disble the
// ITCM SRAM output holdup feature, if set, then we assume
// ITCM SRAM output cannot holdup last read value
wire sel_itcmnohold = (csr_idx == 12'hBFD);// This address is not used by ISA
// 0xBF0 MRW mdvnob2b
// This register is our self-defined register to disble the
// Mul/div back2back feature
wire sel_mdvnob2b = (csr_idx == 12'hBF0);// This address is not used by ISA
wire rd_mcycle = csr_rd_en & sel_mcycle ;
wire rd_mcycleh = csr_rd_en & sel_mcycleh ;
wire rd_minstret = csr_rd_en & sel_minstret ;
wire rd_minstreth = csr_rd_en & sel_minstreth;
wire rd_itcmnohold = csr_rd_en & sel_itcmnohold;
wire rd_mdvnob2b = csr_rd_en & sel_mdvnob2b;
wire rd_counterstop = csr_rd_en & sel_counterstop;
wire rd_mcgstop = csr_rd_en & sel_mcgstop;
`ifdef E203_SUPPORT_MCYCLE_MINSTRET //{
wire wr_mcycle = csr_wr_en & sel_mcycle ;
wire wr_mcycleh = csr_wr_en & sel_mcycleh ;
wire wr_minstret = csr_wr_en & sel_minstret ;
wire wr_minstreth = csr_wr_en & sel_minstreth;
wire wr_itcmnohold = csr_wr_en & sel_itcmnohold ;
wire wr_mdvnob2b = csr_wr_en & sel_mdvnob2b ;
wire wr_counterstop = csr_wr_en & sel_counterstop;
wire wr_mcgstop = csr_wr_en & sel_mcgstop ;
wire mcycle_wr_ena = (wr_mcycle & wbck_csr_wen);
wire mcycleh_wr_ena = (wr_mcycleh & wbck_csr_wen);
wire minstret_wr_ena = (wr_minstret & wbck_csr_wen);
wire minstreth_wr_ena = (wr_minstreth & wbck_csr_wen);
wire itcmnohold_wr_ena = (wr_itcmnohold & wbck_csr_wen);
wire mdvnob2b_wr_ena = (wr_mdvnob2b & wbck_csr_wen);
wire counterstop_wr_ena = (wr_counterstop & wbck_csr_wen);
wire mcgstop_wr_ena = (wr_mcgstop & wbck_csr_wen);
wire [`E203_XLEN-1:0] mcycle_r ;
wire [`E203_XLEN-1:0] mcycleh_r ;
wire [`E203_XLEN-1:0] minstret_r ;
wire [`E203_XLEN-1:0] minstreth_r;
wire cy_stop;
wire ir_stop;
wire stop_cycle_in_dbg = dbg_stopcycle & dbg_mode;
wire mcycle_ena = mcycle_wr_ena |
((~cy_stop) & (~stop_cycle_in_dbg) & (1'b1));
wire mcycleh_ena = mcycleh_wr_ena |
((~cy_stop) & (~stop_cycle_in_dbg) & ((mcycle_r == (~(`E203_XLEN'b0)))));
wire minstret_ena = minstret_wr_ena |
((~ir_stop) & (~stop_cycle_in_dbg) & (cmt_instret_ena));
wire minstreth_ena = minstreth_wr_ena |
((~ir_stop) & (~stop_cycle_in_dbg) & ((cmt_instret_ena & (minstret_r == (~(`E203_XLEN'b0))))));
wire [`E203_XLEN-1:0] mcycle_nxt = mcycle_wr_ena ? wbck_csr_dat : (mcycle_r + 1'b1);
wire [`E203_XLEN-1:0] mcycleh_nxt = mcycleh_wr_ena ? wbck_csr_dat : (mcycleh_r + 1'b1);
wire [`E203_XLEN-1:0] minstret_nxt = minstret_wr_ena ? wbck_csr_dat : (minstret_r + 1'b1);
wire [`E203_XLEN-1:0] minstreth_nxt = minstreth_wr_ena ? wbck_csr_dat : (minstreth_r + 1'b1);
//We need to use the always-on clock for this counter
sirv_gnrl_dfflr #(`E203_XLEN) mcycle_dfflr (mcycle_ena, mcycle_nxt, mcycle_r , clk_aon, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) mcycleh_dfflr (mcycleh_ena, mcycleh_nxt, mcycleh_r , clk_aon, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) minstret_dfflr (minstret_ena, minstret_nxt, minstret_r , clk, rst_n);
sirv_gnrl_dfflr #(`E203_XLEN) minstreth_dfflr (minstreth_ena, minstreth_nxt, minstreth_r, clk, rst_n);
wire [`E203_XLEN-1:0] counterstop_r;
wire counterstop_ena = counterstop_wr_ena;
wire [`E203_XLEN-1:0] counterstop_nxt = {29'b0,wbck_csr_dat[2:0]};// Only LSB 3bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) counterstop_dfflr (counterstop_ena, counterstop_nxt, counterstop_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcycle = mcycle_r;
wire [`E203_XLEN-1:0] csr_mcycleh = mcycleh_r;
wire [`E203_XLEN-1:0] csr_minstret = minstret_r;
wire [`E203_XLEN-1:0] csr_minstreth = minstreth_r;
wire [`E203_XLEN-1:0] csr_counterstop = counterstop_r;
`else//}{
wire [`E203_XLEN-1:0] csr_mcycle = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_mcycleh = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_minstret = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_minstreth = `E203_XLEN'b0;
wire [`E203_XLEN-1:0] csr_counterstop = `E203_XLEN'b0;
`endif//}
wire [`E203_XLEN-1:0] itcmnohold_r;
wire itcmnohold_ena = itcmnohold_wr_ena;
wire [`E203_XLEN-1:0] itcmnohold_nxt = {31'b0,wbck_csr_dat[0]};// Only LSB 1bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) itcmnohold_dfflr (itcmnohold_ena, itcmnohold_nxt, itcmnohold_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_itcmnohold = itcmnohold_r;
wire [`E203_XLEN-1:0] mdvnob2b_r;
wire mdvnob2b_ena = mdvnob2b_wr_ena;
wire [`E203_XLEN-1:0] mdvnob2b_nxt = {31'b0,wbck_csr_dat[0]};// Only LSB 1bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) mdvnob2b_dfflr (mdvnob2b_ena, mdvnob2b_nxt, mdvnob2b_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mdvnob2b = mdvnob2b_r;
assign cy_stop = counterstop_r[0];// Stop CYCLE counter
assign tm_stop = counterstop_r[1];// Stop TIME counter
assign ir_stop = counterstop_r[2];// Stop INSTRET counter
assign itcm_nohold = itcmnohold_r[0];// ITCM no-hold up feature
assign mdv_nob2b = mdvnob2b_r[0];// Mul/Div no back2back feature
wire [`E203_XLEN-1:0] mcgstop_r;
wire mcgstop_ena = mcgstop_wr_ena;
wire [`E203_XLEN-1:0] mcgstop_nxt = {30'b0,wbck_csr_dat[1:0]};// Only LSB 2bits are useful
sirv_gnrl_dfflr #(`E203_XLEN) mcgstop_dfflr (mcgstop_ena, mcgstop_nxt, mcgstop_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcgstop = mcgstop_r;
assign core_cgstop = mcgstop_r[0];// Stop Core clock gating
assign tcm_cgstop = mcgstop_r[1];// Stop TCM clock gating
//`ifdef E203_SUPPORT_CYCLE //{
////0xC00 URO cycle
////0xC80 URO cycleh
//wire sel_cycle = (csr_idx == 12'hc00);
//wire sel_cycleh = (csr_idx == 12'hc80);
//wire rd_cycle = sel_cycle & csr_rd_en;
//wire wr_cycle = sel_cycle & csr_wr_en;
//wire cycle_ena = (wr_cycle & wbck_csr_wen);
//wire rd_cycleh = sel_cycleh & csr_rd_en;
//wire wr_cycleh = sel_cycleh & csr_wr_en;
//wire cycleh_ena = (wr_cycleh & wbck_csr_wen);
//wire [`E203_XLEN-1:0] cycle_r;
//wire [`E203_XLEN-1:0] cycleh_r;
//wire [`E203_XLEN-1:0] cycle_nxt = wbck_csr_dat;
//wire [`E203_XLEN-1:0] cycleh_nxt = wbck_csr_dat;
//sirv_gnrl_dfflr #(`E203_XLEN) cycle_dfflr (cycle_ena, cycle_nxt, cycle_r, clk, rst_n);
//sirv_gnrl_dfflr #(`E203_XLEN) cycleh_dfflr(cycleh_ena,cycleh_nxt,cycleh_r,clk, rst_n);
//wire [`E203_XLEN-1:0] csr_cycle = cycle_r;
//wire [`E203_XLEN-1:0] csr_cycleh = cycleh_r;
//`else//}{
//wire [`E203_XLEN-1:0] csr_cycle = `E203_XLEN'b0;
//wire [`E203_XLEN-1:0] csr_cycleh = `E203_XLEN'b0;
//`endif//}
//
//0x041 URW uepc User exception program counter.
// We dont support user trap, so no uepc needed
//0x341 MRW mepc Machine exception program counter.
wire sel_mepc = (csr_idx == 12'h341);
wire rd_mepc = sel_mepc & csr_rd_en;
wire wr_mepc = sel_mepc & csr_wr_en;
wire epc_ena = (wr_mepc & wbck_csr_wen) | cmt_epc_ena;
wire [`E203_PC_SIZE-1:0] epc_r;
wire [`E203_PC_SIZE-1:0] epc_nxt;
assign epc_nxt[`E203_PC_SIZE-1:1] = cmt_epc_ena ? cmt_epc[`E203_PC_SIZE-1:1] : wbck_csr_dat[`E203_PC_SIZE-1:1];
assign epc_nxt[0] = 1'b0;// Must not hold PC which will generate the misalign exception according to ISA
sirv_gnrl_dfflr #(`E203_PC_SIZE) epc_dfflr (epc_ena, epc_nxt, epc_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mepc;
wire dummy_0;
assign {dummy_0,csr_mepc} = {{`E203_XLEN+1-`E203_PC_SIZE{1'b0}},epc_r};
assign csr_epc_r = csr_mepc;
//0x042 URW ucause User trap cause.
// We dont support user trap, so no ucause needed
//0x342 MRW mcause Machine trap cause.
wire sel_mcause = (csr_idx == 12'h342);
wire rd_mcause = sel_mcause & csr_rd_en;
wire wr_mcause = sel_mcause & csr_wr_en;
wire cause_ena = (wr_mcause & wbck_csr_wen) | cmt_cause_ena;
wire [`E203_XLEN-1:0] cause_r;
wire [`E203_XLEN-1:0] cause_nxt;
assign cause_nxt[31] = cmt_cause_ena ? cmt_cause[31] : wbck_csr_dat[31];
assign cause_nxt[30:4] = 27'b0;
assign cause_nxt[3:0] = cmt_cause_ena ? cmt_cause[3:0] : wbck_csr_dat[3:0];
sirv_gnrl_dfflr #(`E203_XLEN) cause_dfflr (cause_ena, cause_nxt, cause_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mcause = cause_r;
//0x043 URW ubadaddr User bad address.
// We dont support user trap, so no ubadaddr needed
//0x343 MRW mbadaddr Machine bad address.
wire sel_mbadaddr = (csr_idx == 12'h343);
wire rd_mbadaddr = sel_mbadaddr & csr_rd_en;
wire wr_mbadaddr = sel_mbadaddr & csr_wr_en;
wire cmt_trap_badaddr_ena = cmt_badaddr_ena;
wire badaddr_ena = (wr_mbadaddr & wbck_csr_wen) | cmt_trap_badaddr_ena;
wire [`E203_ADDR_SIZE-1:0] badaddr_r;
wire [`E203_ADDR_SIZE-1:0] badaddr_nxt;
assign badaddr_nxt = cmt_trap_badaddr_ena ? cmt_badaddr : wbck_csr_dat[`E203_ADDR_SIZE-1:0];
sirv_gnrl_dfflr #(`E203_ADDR_SIZE) badaddr_dfflr (badaddr_ena, badaddr_nxt, badaddr_r, clk, rst_n);
wire [`E203_XLEN-1:0] csr_mbadaddr;
wire dummy_1;
assign {dummy_1,csr_mbadaddr} = {{`E203_XLEN+1-`E203_ADDR_SIZE{1'b0}},badaddr_r};
// We dont support the delegation scheme, so no need to implement
// delegete registers
//0x301 MRW misa ISA and extensions
wire sel_misa = (csr_idx == 12'h301);
wire rd_misa = sel_misa & csr_rd_en;
// Only implemented the M mode, IMC or EMC
wire [`E203_XLEN-1:0] csr_misa = {
2'b1
,4'b0 //WIRI
,1'b0 // 25 Z Reserved
,1'b0 // 24 Y Reserved
,1'b0 // 23 X Non-standard extensions present
,1'b0 // 22 W Reserved
,1'b0 // 21 V Tentatively reserved for Vector extension 20 U User mode implemented
,1'b0 // 20 U User mode implemented
,1'b0 // 19 T Tentatively reserved for Transactional Memory extension
,1'b0 // 18 S Supervisor mode implemented
,1'b0 // 17 R Reserved
,1'b0 // 16 Q Quad-precision floating-point extension
,1'b0 // 15 P Tentatively reserved for Packed-SIMD extension
,1'b0 // 14 O Reserved
,1'b0 // 13 N User-level interrupts supported
,1'b1 // 12 M Integer Multiply/Divide extension
,1'b0 // 11 L Tentatively reserved for Decimal Floating-Point extension
,1'b0 // 10 K Reserved
,1'b0 // 9 J Reserved
`ifdef E203_RFREG_NUM_IS_32
,1'b1 // 8 I RV32I/64I/128I base ISA
`else
,1'b0
`endif
,1'b0 // 7 H Hypervisor mode implemented
,1'b0 // 6 G Additional standard extensions present
`ifndef E203_HAS_FPU//{
,1'b0 // 5 F Single-precision floating-point extension
`endif//
`ifdef E203_RFREG_NUM_IS_32
,1'b0 // 4 E RV32E base ISA
`else
,1'b1 //
`endif
`ifndef E203_HAS_FPU//{
,1'b0 // 3 D Double-precision floating-point extension
`endif//
,1'b1 // 2 C Compressed extension
,1'b0 // 1 B Tentatively reserved for Bit operations extension
`ifdef E203_SUPPORT_AMO//{
,1'b1 // 0 A Atomic extension
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
,1'b0 // 0 A Atomic extension
`endif//}
};
//Machine Information Registers
//0xF11 MRO mvendorid Vendor ID.
//0xF12 MRO marchid Architecture ID.
//0xF13 MRO mimpid Implementation ID.
//0xF14 MRO mhartid Hardware thread ID.
wire [`E203_XLEN-1:0] csr_mvendorid = `E203_XLEN'h`E203_MVENDORID;
wire [`E203_XLEN-1:0] csr_marchid = `E203_XLEN'h`E203_MARCHID ;
wire [`E203_XLEN-1:0] csr_mimpid = `E203_XLEN'h`E203_MIMPID ;
wire [`E203_XLEN-1:0] csr_mhartid = {{`E203_XLEN-`E203_HART_ID_W{1'b0}},core_mhartid};
wire rd_mvendorid = csr_rd_en & (csr_idx == 12'hF11);
wire rd_marchid = csr_rd_en & (csr_idx == 12'hF12);
wire rd_mimpid = csr_rd_en & (csr_idx == 12'hF13);
wire rd_mhartid = csr_rd_en & (csr_idx == 12'hF14);
//0x7b0 Debug Control and Status
//0x7b1 Debug PC
//0x7b2 Debug Scratch Register
//0x7a0 Trigger selection register
wire sel_dcsr = (csr_idx == 12'h7b0);
wire sel_dpc = (csr_idx == 12'h7b1);
wire sel_dscratch = (csr_idx == 12'h7b2);
wire rd_dcsr = dbg_mode & csr_rd_en & sel_dcsr ;
wire rd_dpc = dbg_mode & csr_rd_en & sel_dpc ;
wire rd_dscratch = dbg_mode & csr_rd_en & sel_dscratch;
assign wr_dcsr_ena = dbg_mode & csr_wr_en & sel_dcsr ;
assign wr_dpc_ena = dbg_mode & csr_wr_en & sel_dpc ;
assign wr_dscratch_ena = dbg_mode & csr_wr_en & sel_dscratch;
assign wr_csr_nxt = wbck_csr_dat;
wire [`E203_XLEN-1:0] csr_dcsr = dcsr_r ;
`ifdef E203_PC_SIZE_IS_16
wire [`E203_XLEN-1:0] csr_dpc = {{`E203_XLEN-`E203_PC_SIZE{1'b0}},dpc_r};
`endif
`ifdef E203_PC_SIZE_IS_24
wire [`E203_XLEN-1:0] csr_dpc = {{`E203_XLEN-`E203_PC_SIZE{1'b0}},dpc_r};
`endif
`ifdef E203_PC_SIZE_IS_32
wire [`E203_XLEN-1:0] csr_dpc = dpc_r ;
`endif
wire [`E203_XLEN-1:0] csr_dscratch = dscratch_r;
assign csr_dpc_r = dpc_r;
/////////////////////////////////////////////////////////////////////
// Generate the Read path
//Currently we only support the M mode to simplify the implementation and
// reduce the gatecount because we are a privite core
assign u_mode = 1'b0;
assign s_mode = 1'b0;
assign h_mode = 1'b0;
assign m_mode = 1'b1;
assign read_csr_dat = `E203_XLEN'b0
//| ({`E203_XLEN{rd_ustatus }} & csr_ustatus )
| ({`E203_XLEN{rd_mstatus }} & csr_mstatus )
| ({`E203_XLEN{rd_mie }} & csr_mie )
| ({`E203_XLEN{rd_mtvec }} & csr_mtvec )
| ({`E203_XLEN{rd_mepc }} & csr_mepc )
| ({`E203_XLEN{rd_mscratch }} & csr_mscratch )
| ({`E203_XLEN{rd_mcause }} & csr_mcause )
| ({`E203_XLEN{rd_mbadaddr }} & csr_mbadaddr )
| ({`E203_XLEN{rd_mip }} & csr_mip )
| ({`E203_XLEN{rd_misa }} & csr_misa )
| ({`E203_XLEN{rd_mvendorid}} & csr_mvendorid)
| ({`E203_XLEN{rd_marchid }} & csr_marchid )
| ({`E203_XLEN{rd_mimpid }} & csr_mimpid )
| ({`E203_XLEN{rd_mhartid }} & csr_mhartid )
| ({`E203_XLEN{rd_mcycle }} & csr_mcycle )
| ({`E203_XLEN{rd_mcycleh }} & csr_mcycleh )
| ({`E203_XLEN{rd_minstret }} & csr_minstret )
| ({`E203_XLEN{rd_minstreth}} & csr_minstreth)
| ({`E203_XLEN{rd_counterstop}} & csr_counterstop)// Self-defined
| ({`E203_XLEN{rd_mcgstop}} & csr_mcgstop)// Self-defined
| ({`E203_XLEN{rd_itcmnohold}} & csr_itcmnohold)// Self-defined
| ({`E203_XLEN{rd_mdvnob2b}} & csr_mdvnob2b)// Self-defined
| ({`E203_XLEN{rd_dcsr }} & csr_dcsr )
| ({`E203_XLEN{rd_dpc }} & csr_dpc )
| ({`E203_XLEN{rd_dscratch }} & csr_dscratch)
;
endmodule |
module sirv_aon_top #(
parameter ASYNC_FF_LEVELS = 2
)(
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input io_pads_aon_erst_n_i_ival,
output io_pads_aon_erst_n_o_oval,
output io_pads_aon_erst_n_o_oe,
output io_pads_aon_erst_n_o_ie,
output io_pads_aon_erst_n_o_pue,
output io_pads_aon_erst_n_o_ds,
input io_pads_aon_pmu_dwakeup_n_i_ival,
output io_pads_aon_pmu_dwakeup_n_o_oval,
output io_pads_aon_pmu_dwakeup_n_o_oe,
output io_pads_aon_pmu_dwakeup_n_o_ie,
output io_pads_aon_pmu_dwakeup_n_o_pue,
output io_pads_aon_pmu_dwakeup_n_o_ds,
input io_pads_aon_pmu_vddpaden_i_ival,
output io_pads_aon_pmu_vddpaden_o_oval,
output io_pads_aon_pmu_vddpaden_o_oe,
output io_pads_aon_pmu_vddpaden_o_ie,
output io_pads_aon_pmu_vddpaden_o_pue,
output io_pads_aon_pmu_vddpaden_o_ds,
input io_pads_aon_pmu_padrst_i_ival,
output io_pads_aon_pmu_padrst_o_oval,
output io_pads_aon_pmu_padrst_o_oe,
output io_pads_aon_pmu_padrst_o_ie,
output io_pads_aon_pmu_padrst_o_pue,
output io_pads_aon_pmu_padrst_o_ds,
input io_pads_dbgmode0_n_i_ival,
input io_pads_dbgmode1_n_i_ival,
input io_pads_dbgmode2_n_i_ival,
input io_pads_bootrom_n_i_ival,
output io_pads_bootrom_n_o_oval,
output io_pads_bootrom_n_o_oe,
output io_pads_bootrom_n_o_ie,
output io_pads_bootrom_n_o_pue,
output io_pads_bootrom_n_o_ds,
input io_pads_jtagpwd_n_i_ival,
output io_pads_jtagpwd_n_o_oval,
output io_pads_jtagpwd_n_o_oe,
output io_pads_jtagpwd_n_o_ie,
output io_pads_jtagpwd_n_o_pue,
output io_pads_jtagpwd_n_o_ds,
output hfclkrst,
output corerst,
output jtagpwd_iso,
output inspect_mode,
output inspect_por_rst,
output inspect_32k_clk,
input inspect_pc_29b,
input inspect_dbg_irq,
output [32-1:0] pc_rtvec,
output aon_wdg_irq,
output aon_rtc_irq,
output aon_rtcToggle,
input lfextclk,
output lfxoscen,
input test_mode,
input test_iso_override
);
// Since the Aon module need to handle the path from the MOFF domain, which
// maybe powered down, so we need to have the isolation cells here
// it can be handled by UPF flow, but we can also add them mannually here
// The inputs from MOFF to aon domain need to be isolated
// The outputs does not need to be isolated
wire isl_icb_cmd_valid;
wire isl_icb_cmd_ready;
wire [32-1:0] isl_icb_cmd_addr;
wire isl_icb_cmd_read;
wire [32-1:0] isl_icb_cmd_wdata;
wire isl_icb_rsp_valid;
wire isl_icb_rsp_ready;
wire [32-1:0] isl_icb_rsp_rdata;
wire aon_iso;
assign isl_icb_cmd_valid = aon_iso ? 1'b0 : i_icb_cmd_valid;
assign isl_icb_cmd_addr = aon_iso ? 32'b0 : i_icb_cmd_addr ;
assign isl_icb_cmd_read = aon_iso ? 1'b0 : i_icb_cmd_read ;
assign isl_icb_cmd_wdata = aon_iso ? 32'b0 : i_icb_cmd_wdata;
assign isl_icb_rsp_ready = aon_iso ? 1'b0 : i_icb_rsp_ready;
assign i_icb_rsp_valid = isl_icb_rsp_valid;
assign i_icb_cmd_ready = isl_icb_cmd_ready;
assign i_icb_rsp_rdata = isl_icb_rsp_rdata;
wire synced_icb_cmd_valid;
wire synced_icb_cmd_ready;
wire [32-1:0] synced_icb_cmd_addr;
wire synced_icb_cmd_read;
wire [32-1:0] synced_icb_cmd_wdata;
wire synced_icb_rsp_valid;
wire synced_icb_rsp_ready;
wire [32-1:0] synced_icb_rsp_rdata;
wire lclkgen_icb_cmd_valid;
wire lclkgen_icb_cmd_ready;
wire [15-1:0] lclkgen_icb_cmd_addr;
wire lclkgen_icb_cmd_read;
wire [32-1:0] lclkgen_icb_cmd_wdata;
wire lclkgen_icb_rsp_valid;
wire lclkgen_icb_rsp_ready;
wire [32-1:0] lclkgen_icb_rsp_rdata;
wire aon_icb_cmd_valid;
wire aon_icb_cmd_ready;
wire [15-1:0] aon_icb_cmd_addr;
wire aon_icb_cmd_read;
wire [32-1:0] aon_icb_cmd_wdata;
wire aon_icb_rsp_valid;
wire aon_icb_rsp_ready;
wire [32-1:0] aon_icb_rsp_rdata;
localparam CMD_PACK_W = 65;
wire [CMD_PACK_W-1:0] synced_icb_cmd_pack;
wire [CMD_PACK_W-1:0] isl_icb_cmd_pack;
assign isl_icb_cmd_pack = {
isl_icb_cmd_addr,
isl_icb_cmd_read,
isl_icb_cmd_wdata};
assign {synced_icb_cmd_addr,
synced_icb_cmd_read,
synced_icb_cmd_wdata} = synced_icb_cmd_pack;
wire crossing_clock;
wire crossing_reset;
wire crossing_reset_n = ~crossing_reset;
sirv_gnrl_cdc_tx
# (
.DW (32),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_tx (
.o_vld (isl_icb_rsp_valid ),
.o_rdy_a(isl_icb_rsp_ready ),
.o_dat (isl_icb_rsp_rdata ),
.i_vld (synced_icb_rsp_valid ),
.i_rdy (synced_icb_rsp_ready ),
.i_dat (synced_icb_rsp_rdata ),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_gnrl_cdc_rx
# (
.DW (CMD_PACK_W),
.SYNC_DP (ASYNC_FF_LEVELS)
) u_aon_icb_cdc_rx (
.i_vld_a(isl_icb_cmd_valid),
.i_rdy (isl_icb_cmd_ready),
.i_dat (isl_icb_cmd_pack),
.o_vld (synced_icb_cmd_valid),
.o_rdy (synced_icb_cmd_ready),
.o_dat (synced_icb_cmd_pack),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
sirv_icb1to2_bus # (
.ICB_FIFO_DP (0),//Pass through
.ICB_FIFO_CUT_READY (1),//
.AW (15),
.DW (32),
.SPLT_FIFO_OUTS_NUM (1),// Allow 1 oustanding
.SPLT_FIFO_CUT_READY (1),// Always cut ready
// * LCLKGEN : 0x200 -- 0x2FF
.O0_BASE_ADDR (15'h200),
.O0_BASE_REGION_LSB (8)
)u_aon_1to2_icb(
.i_icb_cmd_valid (synced_icb_cmd_valid),
.i_icb_cmd_ready (synced_icb_cmd_ready),
.i_icb_cmd_addr (synced_icb_cmd_addr[14:0] ),
.i_icb_cmd_read (synced_icb_cmd_read ),
.i_icb_cmd_wdata (synced_icb_cmd_wdata),
.i_icb_cmd_wmask (4'hF),
.i_icb_cmd_lock (1'b0),
.i_icb_cmd_excl (1'b0 ),
.i_icb_cmd_size (2'b0 ),
.i_icb_cmd_burst (2'b0 ),
.i_icb_cmd_beat (2'b0 ),
.i_icb_rsp_valid (synced_icb_rsp_valid),
.i_icb_rsp_ready (synced_icb_rsp_ready),
.i_icb_rsp_err (),
.i_icb_rsp_excl_ok(),
.i_icb_rsp_rdata (synced_icb_rsp_rdata),
// * LCLKGEN
//
.o0_icb_cmd_valid (lclkgen_icb_cmd_valid),
.o0_icb_cmd_ready (lclkgen_icb_cmd_ready),
.o0_icb_cmd_addr (lclkgen_icb_cmd_addr ),
.o0_icb_cmd_read (lclkgen_icb_cmd_read ),
.o0_icb_cmd_wdata (lclkgen_icb_cmd_wdata),
.o0_icb_cmd_wmask (),
.o0_icb_cmd_lock (),
.o0_icb_cmd_excl (),
.o0_icb_cmd_size (),
.o0_icb_cmd_burst (),
.o0_icb_cmd_beat (),
.o0_icb_rsp_valid (lclkgen_icb_rsp_valid),
.o0_icb_rsp_ready (lclkgen_icb_rsp_ready),
.o0_icb_rsp_err (1'b0),
.o0_icb_rsp_excl_ok(1'b0 ),
.o0_icb_rsp_rdata (lclkgen_icb_rsp_rdata),
// * AON
.o1_icb_cmd_valid (aon_icb_cmd_valid),
.o1_icb_cmd_ready (aon_icb_cmd_ready),
.o1_icb_cmd_addr (aon_icb_cmd_addr ),
.o1_icb_cmd_read (aon_icb_cmd_read ),
.o1_icb_cmd_wdata (aon_icb_cmd_wdata),
.o1_icb_cmd_wmask (),
.o1_icb_cmd_lock (),
.o1_icb_cmd_excl (),
.o1_icb_cmd_size (),
.o1_icb_cmd_burst (),
.o1_icb_cmd_beat (),
.o1_icb_rsp_valid (aon_icb_rsp_valid),
.o1_icb_rsp_ready (aon_icb_rsp_ready),
.o1_icb_rsp_err (1'b0 ),
.o1_icb_rsp_excl_ok(1'b0 ),
.o1_icb_rsp_rdata (aon_icb_rsp_rdata),
.clk (crossing_clock),
.rst_n (crossing_reset_n)
);
wire aon_reset;
wire aon_reset_n = ~aon_reset;
sirv_aon_lclkgen_regs u_aon_lclkgen_regs(
.clk (crossing_clock),// Crossing clock is actually the aon_clk
.rst_n (aon_reset_n),// Here we need to use the aon_rst rather than the crossing reset
.lfxoscen (lfxoscen ),
.i_icb_cmd_valid(lclkgen_icb_cmd_valid),
.i_icb_cmd_ready(lclkgen_icb_cmd_ready),
.i_icb_cmd_addr (lclkgen_icb_cmd_addr[7:0]),
.i_icb_cmd_read (lclkgen_icb_cmd_read ),
.i_icb_cmd_wdata(lclkgen_icb_cmd_wdata),
.i_icb_rsp_valid(lclkgen_icb_rsp_valid),
.i_icb_rsp_ready(lclkgen_icb_rsp_ready),
.i_icb_rsp_rdata(lclkgen_icb_rsp_rdata)
);
wire io_tl_in_0_a_ready;
assign aon_icb_cmd_ready = io_tl_in_0_a_ready;
wire io_tl_in_0_a_valid = aon_icb_cmd_valid;
wire [2:0] io_tl_in_0_a_bits_opcode = aon_icb_cmd_read ? 3'h4 : 3'h0;
wire [2:0] io_tl_in_0_a_bits_param = 3'b0;
wire [2:0] io_tl_in_0_a_bits_size = 3'd2;
wire [4:0] io_tl_in_0_a_bits_source = 5'b0;
wire [28:0] io_tl_in_0_a_bits_address = {14'b0,aon_icb_cmd_addr[14:0]};
wire [3:0] io_tl_in_0_a_bits_mask = 4'b1111;
wire [31:0] io_tl_in_0_a_bits_data = aon_icb_cmd_wdata;
wire io_tl_in_0_d_ready = aon_icb_rsp_ready;
wire [2:0] io_tl_in_0_d_bits_opcode;
wire [1:0] io_tl_in_0_d_bits_param;
wire [2:0] io_tl_in_0_d_bits_size;
wire [4:0] io_tl_in_0_d_bits_source;
wire io_tl_in_0_d_bits_sink;
wire [1:0] io_tl_in_0_d_bits_addr_lo;
wire [31:0] io_tl_in_0_d_bits_data;
wire io_tl_in_0_d_bits_error;
wire io_tl_in_0_d_valid;
assign aon_icb_rsp_valid = io_tl_in_0_d_valid;
assign aon_icb_rsp_rdata = io_tl_in_0_d_bits_data;
// Not used
wire io_tl_in_0_b_ready = 1'b0;
wire io_tl_in_0_b_valid;
wire [2:0] io_tl_in_0_b_bits_opcode;
wire [1:0] io_tl_in_0_b_bits_param;
wire [2:0] io_tl_in_0_b_bits_size;
wire [4:0] io_tl_in_0_b_bits_source;
wire [28:0] io_tl_in_0_b_bits_address;
wire [3:0] io_tl_in_0_b_bits_mask;
wire [31:0] io_tl_in_0_b_bits_data;
// Not used
wire io_tl_in_0_c_ready;
wire io_tl_in_0_c_valid = 1'b0;
wire [2:0] io_tl_in_0_c_bits_opcode = 3'b0;
wire [2:0] io_tl_in_0_c_bits_param = 3'b0;
wire [2:0] io_tl_in_0_c_bits_size = 3'd2;
wire [4:0] io_tl_in_0_c_bits_source = 5'b0;
wire [28:0] io_tl_in_0_c_bits_address = 29'b0;
wire [31:0] io_tl_in_0_c_bits_data = 32'b0;
wire io_tl_in_0_c_bits_error = 1'b0;
// Not used
wire io_tl_in_0_e_ready;
wire io_tl_in_0_e_valid = 1'b0;
wire io_tl_in_0_e_bits_sink = 1'b0;
sirv_aon_wrapper u_sirv_aon_wrapper(
.aon_reset (aon_reset),
.aon_iso (aon_iso),
.jtagpwd_iso (jtagpwd_iso),
.crossing_clock (crossing_clock),
.crossing_reset (crossing_reset),
.io_in_0_a_ready (io_tl_in_0_a_ready ),
.io_in_0_a_valid (io_tl_in_0_a_valid ),
.io_in_0_a_bits_opcode (io_tl_in_0_a_bits_opcode ),
.io_in_0_a_bits_param (io_tl_in_0_a_bits_param ),
.io_in_0_a_bits_size (io_tl_in_0_a_bits_size ),
.io_in_0_a_bits_source (io_tl_in_0_a_bits_source ),
.io_in_0_a_bits_address (io_tl_in_0_a_bits_address ),
.io_in_0_a_bits_mask (io_tl_in_0_a_bits_mask ),
.io_in_0_a_bits_data (io_tl_in_0_a_bits_data ),
.io_in_0_b_ready (io_tl_in_0_b_ready ),
.io_in_0_b_valid (io_tl_in_0_b_valid ),
.io_in_0_b_bits_opcode (io_tl_in_0_b_bits_opcode ),
.io_in_0_b_bits_param (io_tl_in_0_b_bits_param ),
.io_in_0_b_bits_size (io_tl_in_0_b_bits_size ),
.io_in_0_b_bits_source (io_tl_in_0_b_bits_source ),
.io_in_0_b_bits_address (io_tl_in_0_b_bits_address ),
.io_in_0_b_bits_mask (io_tl_in_0_b_bits_mask ),
.io_in_0_b_bits_data (io_tl_in_0_b_bits_data ),
.io_in_0_c_ready (io_tl_in_0_c_ready ),
.io_in_0_c_valid (io_tl_in_0_c_valid ),
.io_in_0_c_bits_opcode (io_tl_in_0_c_bits_opcode ),
.io_in_0_c_bits_param (io_tl_in_0_c_bits_param ),
.io_in_0_c_bits_size (io_tl_in_0_c_bits_size ),
.io_in_0_c_bits_source (io_tl_in_0_c_bits_source ),
.io_in_0_c_bits_address (io_tl_in_0_c_bits_address ),
.io_in_0_c_bits_data (io_tl_in_0_c_bits_data ),
.io_in_0_c_bits_error (io_tl_in_0_c_bits_error ),
.io_in_0_d_ready (io_tl_in_0_d_ready ),
.io_in_0_d_valid (io_tl_in_0_d_valid ),
.io_in_0_d_bits_opcode (io_tl_in_0_d_bits_opcode ),
.io_in_0_d_bits_param (io_tl_in_0_d_bits_param ),
.io_in_0_d_bits_size (io_tl_in_0_d_bits_size ),
.io_in_0_d_bits_source (io_tl_in_0_d_bits_source ),
.io_in_0_d_bits_sink (io_tl_in_0_d_bits_sink ),
.io_in_0_d_bits_addr_lo (io_tl_in_0_d_bits_addr_lo ),
.io_in_0_d_bits_data (io_tl_in_0_d_bits_data ),
.io_in_0_d_bits_error (io_tl_in_0_d_bits_error ),
.io_in_0_e_ready (io_tl_in_0_e_ready ),
.io_in_0_e_valid (io_tl_in_0_e_valid ),
.io_in_0_e_bits_sink (io_tl_in_0_e_bits_sink ),
.io_ip_0_0 (aon_wdg_irq),
.io_ip_0_1 (aon_rtc_irq),
.io_pads_erst_n_i_ival (io_pads_aon_erst_n_i_ival ),
.io_pads_erst_n_o_oval (io_pads_aon_erst_n_o_oval ),
.io_pads_erst_n_o_oe (io_pads_aon_erst_n_o_oe ),
.io_pads_erst_n_o_ie (io_pads_aon_erst_n_o_ie ),
.io_pads_erst_n_o_pue (io_pads_aon_erst_n_o_pue ),
.io_pads_erst_n_o_ds (io_pads_aon_erst_n_o_ds ),
.io_pads_lfextclk_i_ival (lfextclk ),
.io_pads_lfextclk_o_oval (),
.io_pads_lfextclk_o_oe (),
.io_pads_lfextclk_o_ie (),
.io_pads_lfextclk_o_pue (),
.io_pads_lfextclk_o_ds (),
.io_pads_pmu_dwakeup_n_i_ival(io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_pmu_dwakeup_n_o_oval(io_pads_aon_pmu_dwakeup_n_o_oval),
.io_pads_pmu_dwakeup_n_o_oe (io_pads_aon_pmu_dwakeup_n_o_oe ),
.io_pads_pmu_dwakeup_n_o_ie (io_pads_aon_pmu_dwakeup_n_o_ie ),
.io_pads_pmu_dwakeup_n_o_pue (io_pads_aon_pmu_dwakeup_n_o_pue ),
.io_pads_pmu_dwakeup_n_o_ds (io_pads_aon_pmu_dwakeup_n_o_ds ),
.io_pads_pmu_vddpaden_i_ival (io_pads_aon_pmu_vddpaden_i_ival ),
.io_pads_pmu_vddpaden_o_oval (io_pads_aon_pmu_vddpaden_o_oval ),
.io_pads_pmu_vddpaden_o_oe (io_pads_aon_pmu_vddpaden_o_oe ),
.io_pads_pmu_vddpaden_o_ie (io_pads_aon_pmu_vddpaden_o_ie ),
.io_pads_pmu_vddpaden_o_pue (io_pads_aon_pmu_vddpaden_o_pue ),
.io_pads_pmu_vddpaden_o_ds (io_pads_aon_pmu_vddpaden_o_ds ),
.io_pads_pmu_padrst_i_ival (io_pads_aon_pmu_padrst_i_ival ),
.io_pads_pmu_padrst_o_oval (io_pads_aon_pmu_padrst_o_oval ),
.io_pads_pmu_padrst_o_oe (io_pads_aon_pmu_padrst_o_oe ),
.io_pads_pmu_padrst_o_ie (io_pads_aon_pmu_padrst_o_ie ),
.io_pads_pmu_padrst_o_pue (io_pads_aon_pmu_padrst_o_pue ),
.io_pads_pmu_padrst_o_ds (io_pads_aon_pmu_padrst_o_ds ),
.io_pads_jtagpwd_n_i_ival (io_pads_jtagpwd_n_i_ival),
.io_pads_jtagpwd_n_o_oval (io_pads_jtagpwd_n_o_oval),
.io_pads_jtagpwd_n_o_oe (io_pads_jtagpwd_n_o_oe ),
.io_pads_jtagpwd_n_o_ie (io_pads_jtagpwd_n_o_ie ),
.io_pads_jtagpwd_n_o_pue (io_pads_jtagpwd_n_o_pue ),
.io_pads_jtagpwd_n_o_ds (io_pads_jtagpwd_n_o_ds ),
.io_pads_bootrom_n_i_ival (io_pads_bootrom_n_i_ival),
.io_pads_bootrom_n_o_oval (io_pads_bootrom_n_o_oval),
.io_pads_bootrom_n_o_oe (io_pads_bootrom_n_o_oe ),
.io_pads_bootrom_n_o_ie (io_pads_bootrom_n_o_ie ),
.io_pads_bootrom_n_o_pue (io_pads_bootrom_n_o_pue ),
.io_pads_bootrom_n_o_ds (io_pads_bootrom_n_o_ds ),
.io_pads_dbgmode0_n_i_ival (io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (io_pads_dbgmode2_n_i_ival),
.inspect_mode (inspect_mode ),
.inspect_pc_29b (inspect_pc_29b ),
.inspect_por_rst (inspect_por_rst ),
.inspect_32k_clk (inspect_32k_clk ),
.inspect_dbg_irq (inspect_dbg_irq ),
.pc_rtvec (pc_rtvec),
.io_rsts_hfclkrst(hfclkrst),
.io_rsts_corerst (corerst ),
.io_rtc (aon_rtcToggle),
.test_mode (test_mode ),
.test_iso_override(test_iso_override)
);
endmodule |
module e203_cpu #(
parameter MASTER = 1
)(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
output core_wfi,
output tm_stop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// With the interface to debug module
//
// The interface with commit stage
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output dbg_irq_r,
// The interface with CSR control
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
/////////////////////////////////////////////////////
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_a,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
`ifdef E203_HAS_ITCM //{
//input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
//input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM//{
output itcm_ls,
output itcm_ram_cs,
output itcm_ram_we,
output [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
output [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
output clk_itcm_ram,
`endif//}
`ifdef E203_HAS_DTCM//{
output dtcm_ls,
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
`endif//}
input test_mode,
input clk,
input rst_n
);
wire core_cgstop;
wire tcm_cgstop;
wire core_ifu_active;
wire core_exu_active;
wire core_lsu_active;
wire core_biu_active;
// The core's clk and rst
wire rst_core;
wire clk_core_ifu;
wire clk_core_exu;
wire clk_core_lsu;
wire clk_core_biu;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
wire clk_itcm;
wire itcm_active;
`endif
`ifdef E203_HAS_DTCM
wire clk_dtcm;
wire dtcm_active;
`endif
// The Top always on clk and rst
wire rst_aon;
wire clk_aon;
// The reset ctrl and clock ctrl should be in the power always-on domain
e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
.clk (clk_aon ),
.rst_n (rst_n ),
.test_mode (test_mode),
.rst_core (rst_core),
`ifdef E203_HAS_ITCM
.rst_itcm (rst_itcm),
`endif
`ifdef E203_HAS_DTCM
.rst_dtcm (rst_dtcm),
`endif
.rst_aon (rst_aon)
);
e203_clk_ctrl u_e203_clk_ctrl(
.clk (clk ),
.rst_n (rst_aon ),
.test_mode (test_mode ),
.clk_aon (clk_aon ),
.core_cgstop (core_cgstop),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
`ifdef E203_HAS_ITCM
.clk_itcm (clk_itcm ),
.itcm_active (itcm_active),
.itcm_ls (itcm_ls ),
`endif
`ifdef E203_HAS_DTCM
.clk_dtcm (clk_dtcm ),
.dtcm_active (dtcm_active),
.dtcm_ls (dtcm_ls ),
`endif
.core_ifu_active(core_ifu_active),
.core_exu_active(core_exu_active),
.core_lsu_active(core_lsu_active),
.core_biu_active(core_biu_active),
.core_wfi (core_wfi )
);
wire ext_irq_r;
wire sft_irq_r;
wire tmr_irq_r;
e203_irq_sync #(.MASTER(MASTER)) u_e203_irq_sync(
.clk (clk_aon ),
.rst_n (rst_aon ),
.dbg_irq_a (dbg_irq_a),
.dbg_irq_r (dbg_irq_r),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r)
);
`ifdef E203_HAS_ITCM //{
wire ifu2itcm_holdup;
//wire ifu2itcm_replay;
wire ifu2itcm_icb_cmd_valid;
wire ifu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr;
wire ifu2itcm_icb_rsp_valid;
wire ifu2itcm_icb_rsp_ready;
wire ifu2itcm_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata;
wire lsu2itcm_icb_cmd_valid;
wire lsu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr;
wire lsu2itcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask;
wire lsu2itcm_icb_cmd_lock;
wire lsu2itcm_icb_cmd_excl;
wire [1:0] lsu2itcm_icb_cmd_size;
wire lsu2itcm_icb_rsp_valid;
wire lsu2itcm_icb_rsp_ready;
wire lsu2itcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_DTCM //{
wire lsu2dtcm_icb_cmd_valid;
wire lsu2dtcm_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr;
wire lsu2dtcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask;
wire lsu2dtcm_icb_cmd_lock;
wire lsu2dtcm_icb_cmd_excl;
wire [1:0] lsu2dtcm_icb_cmd_size;
wire lsu2dtcm_icb_rsp_valid;
wire lsu2dtcm_icb_rsp_ready;
wire lsu2dtcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_CSR_EAI//{
wire eai_csr_valid;
wire eai_csr_ready;
wire [31:0] eai_csr_addr;
wire eai_csr_wr;
wire [31:0] eai_csr_wdata;
wire [31:0] eai_csr_rdata;
// This is an empty module to just connect the EAI CSR interface,
// user can hack it to become a real one
e203_extend_csr u_e203_extend_csr(
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
.clk (clk_core_exu ),
.rst_n (rst_core )
);
`endif//}
e203_core u_e203_core(
.inspect_pc (inspect_pc),
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.tcm_cgstop (tcm_cgstop),
.core_cgstop (core_cgstop),
.tm_stop (tm_stop),
.pc_rtvec (pc_rtvec),
.ifu_active (core_ifu_active),
.exu_active (core_exu_active),
.lsu_active (core_lsu_active),
.biu_active (core_biu_active),
.core_wfi (core_wfi),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (`E203_LIRQ_NUM'b0),// Not implemented now
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (`E203_EVT_NUM'b0),// Not implemented now
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r ),
.dbg_step_r (dbg_step_r ),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
`ifdef E203_HAS_ITCM //{
//.itcm_region_indic (itcm_region_indic),
.itcm_region_indic (`E203_ITCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_DTCM //{
//.dtcm_region_indic (dtcm_region_indic),
.dtcm_region_indic (`E203_DTCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.lsu2itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.lsu2itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_excl_ok(1'b0),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.lsu2dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.lsu2dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_excl_ok(1'b0),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.ppi_icb_enable (ppi_icb_enable),
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic ),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst ),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk_aon (clk_aon ),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
.test_mode (test_mode),
.rst_n (rst_core )
);
`ifdef E203_HAS_ITCM //{
e203_itcm_ctrl u_e203_itcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.itcm_active (itcm_active),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_cmd_read (1'b1 ),
.ifu2itcm_icb_cmd_wdata ({`E203_ITCM_DATA_WIDTH{1'b0}}),
.ifu2itcm_icb_cmd_wmask ({`E203_ITCM_DATA_WIDTH/8{1'b0}}),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_itcm),
.rst_n (rst_itcm)
);
`endif//}
`ifdef E203_HAS_DTCM //{
e203_dtcm_ctrl u_e203_dtcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.dtcm_active (dtcm_active),
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_dtcm),
.rst_n (rst_dtcm)
);
`endif//}
assign inspect_dbg_irq = dbg_irq_a;
assign inspect_mem_cmd_valid = mem_icb_cmd_valid;
assign inspect_mem_cmd_ready = mem_icb_cmd_ready;
assign inspect_mem_rsp_valid = mem_icb_rsp_valid;
assign inspect_mem_rsp_ready = mem_icb_rsp_ready;
assign inspect_core_clk = clk;
assign core_csr_clk = clk_core_exu;
endmodule |
module sirv_mrom # (
parameter AW = 12,
parameter DW = 32,
parameter DP = 1024
)(
input [AW-1:2] rom_addr,
output [DW-1:0] rom_dout
);
wire [31:0] mask_rom [0:DP-1];// 4KB = 1KW
assign rom_dout = mask_rom[rom_addr];
/*
assign mask_rom[ 0] = 32'h0280006f;
assign mask_rom[ 1] = 32'h00000013;
assign mask_rom[ 2] = 32'h00000013;
assign mask_rom[ 3] = 32'h00000013;
assign mask_rom[ 4] = 32'h00000013;
assign mask_rom[ 5] = 32'h00000013;
assign mask_rom[ 6] = 32'h00000013;
assign mask_rom[ 7] = 32'h00000013;
assign mask_rom[ 8] = 32'h00000013;
assign mask_rom[ 9] = 32'h00000013;
assign mask_rom[10] = 32'h00700093;
assign mask_rom[11] = 32'h10012137;
assign mask_rom[12] = 32'h00810113;
assign mask_rom[13] = 32'h00112023;
assign mask_rom[14] = 32'h00000193;
assign mask_rom[15] = 32'h00100293;
assign mask_rom[16] = 32'h00500093;
assign mask_rom[17] = 32'h10012137;
assign mask_rom[18] = 32'h00c10113;
assign mask_rom[19] = 32'h00112023;
assign mask_rom[20] = 32'h00150237;
assign mask_rom[21] = 32'h40520233;
assign mask_rom[22] = 32'hfe321ee3;
assign mask_rom[23] = 32'h00000093;
assign mask_rom[24] = 32'h10012137;
assign mask_rom[25] = 32'h00c10113;
assign mask_rom[26] = 32'h00112023;
assign mask_rom[27] = 32'h00150237;
assign mask_rom[28] = 32'h40520233;
assign mask_rom[29] = 32'hfe321ee3;
assign mask_rom[30] = 32'hfc1ff06f;
assign mask_rom[31] = 32'h00000013;
assign mask_rom[32] = 32'h00000013;
*/
genvar i;
generate
if(1) begin: jump_to_ram_gen
// Just jump to the ITCM base address
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h7ffff297; //auipc t0, 0x7ffff
end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h00028067; //jr t0
end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000013;
end
end
end
else begin: jump_to_non_ram_gen
// This is the freedom bootrom version, put here have a try
// The actual executed trace is as below:
// CYC: 8615 PC:00001000 IR:0100006f DASM: j pc + 0x10
// CYC: 8618 PC:00001010 IR:204002b7 DASM: lui t0, 0x20400 xpr[5] = 0x20400000
// CYC: 8621 PC:00001014 IR:00028067 DASM: jr t0
// The 20400000 is the flash address
//MEMORY
//{
// flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 512M
// ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
//}
for (i=0;i<1024;i=i+1) begin: rom_gen
if(i==0) begin: rom0_gen
assign mask_rom[i] = 32'h100006f;
end
else if(i==1) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==2) begin: rom1_gen
assign mask_rom[i] = 32'h13;
end
else if(i==3) begin: rom1_gen
assign mask_rom[i] = 32'h6661;// our config code
end
else if(i==4) begin: rom1_gen
//assign mask_rom[i] = 32'h204002b7;
assign mask_rom[i] = 32'h20400000 | 32'h000002b7;
end
else if(i==5) begin: rom1_gen
assign mask_rom[i] = 32'h28067;
end
else begin: rom_non01_gen
assign mask_rom[i] = 32'h00000000;
end
end
// In the https://github.com/sifive/freedom/blob/master/bootrom/xip/xip.S
// ASM code is as below:
// // // See LICENSE for license details.
//// Execute in place
//// Jump directly to XIP_TARGET_ADDR
//
// .text
// .option norvc
// .globl _start
//_start:
// j 1f
// nop
// nop
//#ifdef CONFIG_STRING
// .word cfg_string
//#else
// .word 0 // Filled in by GenerateBootROM in Chisel
//#endif
//
//1:
// li t0, XIP_TARGET_ADDR
// jr t0
//
// .section .rodata
//#ifdef CONFIG_STRING
//cfg_string:
// .incbin CONFIG_STRING
//#endif
end
endgenerate
endmodule |
module e203_exu_alu_lsuagu(
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The Issue Handshake Interface to AGU
//
input agu_i_valid, // Handshake valid
output agu_i_ready, // Handshake ready
input [`E203_XLEN-1:0] agu_i_rs1,
input [`E203_XLEN-1:0] agu_i_rs2,
input [`E203_XLEN-1:0] agu_i_imm,
input [`E203_DECINFO_AGU_WIDTH-1:0] agu_i_info,
input [`E203_ITAG_WIDTH-1:0] agu_i_itag,
output agu_i_longpipe,
input flush_req,
input flush_pulse,
output amo_wait,
input oitf_empty,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The AGU Write-Back/Commit Interface
output agu_o_valid, // Handshake valid
input agu_o_ready, // Handshake ready
output [`E203_XLEN-1:0] agu_o_wbck_wdat,
output agu_o_wbck_err,
// The Commit Interface for all ldst and amo instructions
output agu_o_cmt_misalgn, // The misalign exception generated
output agu_o_cmt_ld,
output agu_o_cmt_stamo,
output agu_o_cmt_buserr, // The bus-error exception generated
output [`E203_ADDR_SIZE-1:0] agu_o_cmt_badaddr,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to LSU-ctrl
// * Bus cmd channel
output agu_icb_cmd_valid, // Handshake valid
input agu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr, // Bus transaction start addr
output agu_icb_cmd_read, // Read or write
output [`E203_XLEN-1:0] agu_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] agu_icb_cmd_wmask,
output agu_icb_cmd_back2agu,
output agu_icb_cmd_lock,
output agu_icb_cmd_excl,
output [1:0] agu_icb_cmd_size,
output [`E203_ITAG_WIDTH-1:0]agu_icb_cmd_itag,
output agu_icb_cmd_usign,
// * Bus RSP channel
input agu_icb_rsp_valid, // Response valid
output agu_icb_rsp_ready, // Response ready
input agu_icb_rsp_err , // Response error
input agu_icb_rsp_excl_ok,
// Note: the RSP rdata is inline with AXI definition
input [`E203_XLEN-1:0] agu_icb_rsp_rdata,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// To share the ALU datapath, generate interface to ALU
// for single-issue machine, seems the AGU must be shared with ALU, otherwise
// it wasted the area for no points
//
// The operands and info to ALU
output [`E203_XLEN-1:0] agu_req_alu_op1,
output [`E203_XLEN-1:0] agu_req_alu_op2,
output agu_req_alu_swap,
output agu_req_alu_add ,
output agu_req_alu_and ,
output agu_req_alu_or ,
output agu_req_alu_xor ,
output agu_req_alu_max ,
output agu_req_alu_min ,
output agu_req_alu_maxu,
output agu_req_alu_minu,
input [`E203_XLEN-1:0] agu_req_alu_res,
// The Shared-Buffer interface to ALU-Shared-Buffer
output agu_sbf_0_ena,
output [`E203_XLEN-1:0] agu_sbf_0_nxt,
input [`E203_XLEN-1:0] agu_sbf_0_r,
output agu_sbf_1_ena,
output [`E203_XLEN-1:0] agu_sbf_1_nxt,
input [`E203_XLEN-1:0] agu_sbf_1_r,
input clk,
input rst_n
);
//
// When there is a nonalu_flush which is going to flush the ALU, then we need to mask off it
wire icb_sta_is_idle;
wire flush_block = flush_req & icb_sta_is_idle;
wire agu_i_load = agu_i_info [`E203_DECINFO_AGU_LOAD ] & (~flush_block);
wire agu_i_store = agu_i_info [`E203_DECINFO_AGU_STORE ] & (~flush_block);
wire agu_i_amo = agu_i_info [`E203_DECINFO_AGU_AMO ] & (~flush_block);
wire [1:0] agu_i_size = agu_i_info [`E203_DECINFO_AGU_SIZE ];
wire agu_i_usign = agu_i_info [`E203_DECINFO_AGU_USIGN ];
wire agu_i_excl = agu_i_info [`E203_DECINFO_AGU_EXCL ];
wire agu_i_amoswap = agu_i_info [`E203_DECINFO_AGU_AMOSWAP];
wire agu_i_amoadd = agu_i_info [`E203_DECINFO_AGU_AMOADD ];
wire agu_i_amoand = agu_i_info [`E203_DECINFO_AGU_AMOAND ];
wire agu_i_amoor = agu_i_info [`E203_DECINFO_AGU_AMOOR ];
wire agu_i_amoxor = agu_i_info [`E203_DECINFO_AGU_AMOXOR ];
wire agu_i_amomax = agu_i_info [`E203_DECINFO_AGU_AMOMAX ];
wire agu_i_amomin = agu_i_info [`E203_DECINFO_AGU_AMOMIN ];
wire agu_i_amomaxu = agu_i_info [`E203_DECINFO_AGU_AMOMAXU];
wire agu_i_amominu = agu_i_info [`E203_DECINFO_AGU_AMOMINU];
wire agu_icb_cmd_hsked = agu_icb_cmd_valid & agu_icb_cmd_ready;
`ifdef E203_SUPPORT_AMO//{
wire agu_icb_rsp_hsked = agu_icb_rsp_valid & agu_icb_rsp_ready;
`endif//E203_SUPPORT_AMO}
// These strange ifdef/ifndef rather than the ifdef-else, because of
// our internal text processing scripts need this style
`ifndef E203_SUPPORT_AMO//{
`ifndef E203_SUPPORT_UNALGNLDST//{
wire agu_icb_rsp_hsked = 1'b0;
`endif//}
`endif//}
wire agu_i_size_b = (agu_i_size == 2'b00);
wire agu_i_size_hw = (agu_i_size == 2'b01);
wire agu_i_size_w = (agu_i_size == 2'b10);
wire agu_i_addr_unalgn =
(agu_i_size_hw & agu_icb_cmd_addr[0])
| (agu_i_size_w & (|agu_icb_cmd_addr[1:0]));
wire state_last_exit_ena;
`ifdef E203_SUPPORT_AMO//{
wire state_idle_exit_ena;
wire unalgn_flg_r;
// Set when the ICB state is starting and it is unalign
wire unalgn_flg_set = agu_i_addr_unalgn & state_idle_exit_ena;
// Clear when the ICB state is entering
wire unalgn_flg_clr = unalgn_flg_r & state_last_exit_ena;
wire unalgn_flg_ena = unalgn_flg_set | unalgn_flg_clr;
wire unalgn_flg_nxt = unalgn_flg_set | (~unalgn_flg_clr);
sirv_gnrl_dfflr #(1) unalgn_flg_dffl (unalgn_flg_ena, unalgn_flg_nxt, unalgn_flg_r, clk, rst_n);
`endif//E203_SUPPORT_AMO}
wire agu_addr_unalgn =
`ifndef E203_SUPPORT_UNALGNLDST//{
`ifdef E203_SUPPORT_AMO//{
icb_sta_is_idle ? agu_i_addr_unalgn : unalgn_flg_r;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
agu_i_addr_unalgn;
`endif//}
`endif//}
wire agu_i_unalgnld = (agu_addr_unalgn & agu_i_load)
;
wire agu_i_unalgnst = (agu_addr_unalgn & agu_i_store)
;
wire agu_i_unalgnldst = (agu_i_unalgnld | agu_i_unalgnst)
;
wire agu_i_algnld = (~agu_addr_unalgn) & agu_i_load
;
wire agu_i_algnst = (~agu_addr_unalgn) & agu_i_store
;
wire agu_i_algnldst = (agu_i_algnld | agu_i_algnst)
;
`ifdef E203_SUPPORT_AMO//{
wire agu_i_unalgnamo = (agu_addr_unalgn & agu_i_amo)
;
wire agu_i_algnamo = ((~agu_addr_unalgn) & agu_i_amo)
;
`endif//E203_SUPPORT_AMO}
wire agu_i_ofst0 = agu_i_amo | ((agu_i_load | agu_i_store) & agu_i_excl);
localparam ICB_STATE_WIDTH = 4;
wire icb_state_ena;
wire [ICB_STATE_WIDTH-1:0] icb_state_nxt;
wire [ICB_STATE_WIDTH-1:0] icb_state_r;
// State 0: The idle state, means there is no any oustanding ifetch request
localparam ICB_STATE_IDLE = 4'd0;
`ifdef E203_SUPPORT_AMO//{
// State : Issued first request and wait response
localparam ICB_STATE_1ST = 4'd1;
// State : Wait to issue second request
localparam ICB_STATE_WAIT2ND = 4'd2;
// State : Issued second request and wait response
localparam ICB_STATE_2ND = 4'd3;
// State : For AMO instructions, in this state, read-data was in leftover
// buffer for ALU calculation
localparam ICB_STATE_AMOALU = 4'd4;
// State : For AMO instructions, in this state, ALU have caculated the new
// result and put into leftover buffer again
localparam ICB_STATE_AMORDY = 4'd5;
// State : For AMO instructions, in this state, the response data have been returned
// and the write back result to commit/wback interface
localparam ICB_STATE_WBCK = 4'd6;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire [ICB_STATE_WIDTH-1:0] state_idle_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_1st_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wait2nd_nxt;
wire [ICB_STATE_WIDTH-1:0] state_2nd_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amoalu_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_amordy_nxt ;
wire [ICB_STATE_WIDTH-1:0] state_wbck_nxt ;
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
wire state_1st_exit_ena ;
wire state_wait2nd_exit_ena ;
wire state_2nd_exit_ena ;
wire state_amoalu_exit_ena ;
wire state_amordy_exit_ena ;
wire state_wbck_exit_ena ;
`endif//E203_SUPPORT_AMO}
// Define some common signals and reused later to save gatecounts
assign icb_sta_is_idle = (icb_state_r == ICB_STATE_IDLE );
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_1st = (icb_state_r == ICB_STATE_1ST );
wire icb_sta_is_amoalu = (icb_state_r == ICB_STATE_AMOALU );
wire icb_sta_is_amordy = (icb_state_r == ICB_STATE_AMORDY );
wire icb_sta_is_wait2nd = (icb_state_r == ICB_STATE_WAIT2ND);
wire icb_sta_is_2nd = (icb_state_r == ICB_STATE_2ND );
wire icb_sta_is_wbck = (icb_state_r == ICB_STATE_WBCK );
`endif//E203_SUPPORT_AMO}
`ifdef E203_SUPPORT_AMO//{
// **** If the current state is idle,
// If a new load-store come and the ICB cmd channel is handshaked, next
// state is ICB_STATE_1ST
wire state_idle_to_exit = (( agu_i_algnamo
// Why do we add an oitf empty signal here? because
// it is better to start AMO state-machine when the
// long-pipes are completed, to avoid the long-pipes
// have error-return which need to flush the pipeline
// and which also need to wait the AMO state-machine
// to complete first, in corner cases it may end
// up with deadlock.
// Force to wait oitf empty before doing amo state-machine
// may hurt performance, but we dont care it. In e200 implementation
// the AMO was not target for performance.
& oitf_empty)
);
assign state_idle_exit_ena = icb_sta_is_idle & state_idle_to_exit
& agu_icb_cmd_hsked & (~flush_pulse);
assign state_idle_nxt = ICB_STATE_1ST;
// **** If the current state is 1st,
// If a response come, exit this state
assign state_1st_exit_ena = icb_sta_is_1st & (agu_icb_rsp_hsked | flush_pulse);
assign state_1st_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// (agu_i_algnamo) ? // No need this condition, because it will be either
// amo or unalgn load-store in this state
ICB_STATE_AMOALU
);
// **** If the current state is AMOALU
// Since the ALU is must be holdoff now, it can always be
// served and then enter into next state
assign state_amoalu_exit_ena = icb_sta_is_amoalu & ( 1'b1 | flush_pulse);
assign state_amoalu_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_AMORDY;
// **** If the current state is AMORDY
// It always enter into next state
assign state_amordy_exit_ena = icb_sta_is_amordy & ( 1'b1 | flush_pulse);
assign state_amordy_nxt = flush_pulse ? ICB_STATE_IDLE :
(
// AMO after caculated read-modify-result, need to issue 2nd uop as store
// back to memory, hence two ICB needed and we dont care the performance,
// so always let it jump to wait2nd state
ICB_STATE_WAIT2ND
);
// **** If the current state is wait-2nd,
assign state_wait2nd_exit_ena = icb_sta_is_wait2nd & (agu_icb_cmd_ready | flush_pulse);
// If the ICB CMD is ready, then next state is ICB_STATE_2ND
assign state_wait2nd_nxt = flush_pulse ? ICB_STATE_IDLE : ICB_STATE_2ND;
// **** If the current state is 2nd,
// If a response come, exit this state
assign state_2nd_exit_ena = icb_sta_is_2nd & (agu_icb_rsp_hsked | flush_pulse);
assign state_2nd_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_WBCK
);
// **** If the current state is wbck,
// If it can be write back, exit this state
assign state_wbck_exit_ena = icb_sta_is_wbck & (agu_o_ready | flush_pulse);
assign state_wbck_nxt = flush_pulse ? ICB_STATE_IDLE :
(
ICB_STATE_IDLE
);
`endif//E203_SUPPORT_AMO}
// The state will only toggle when each state is meeting the condition to exit:
assign icb_state_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| state_idle_exit_ena | state_1st_exit_ena
| state_amoalu_exit_ena | state_amordy_exit_ena
| state_wait2nd_exit_ena | state_2nd_exit_ena
| state_wbck_exit_ena
`endif//E203_SUPPORT_AMO}
;
// The next-state is onehot mux to select different entries
assign icb_state_nxt =
({ICB_STATE_WIDTH{1'b0}})
`ifdef E203_SUPPORT_AMO//{
| ({ICB_STATE_WIDTH{state_idle_exit_ena }} & state_idle_nxt )
| ({ICB_STATE_WIDTH{state_1st_exit_ena }} & state_1st_nxt )
| ({ICB_STATE_WIDTH{state_amoalu_exit_ena }} & state_amoalu_nxt )
| ({ICB_STATE_WIDTH{state_amordy_exit_ena }} & state_amordy_nxt )
| ({ICB_STATE_WIDTH{state_wait2nd_exit_ena}} & state_wait2nd_nxt)
| ({ICB_STATE_WIDTH{state_2nd_exit_ena }} & state_2nd_nxt )
| ({ICB_STATE_WIDTH{state_wbck_exit_ena }} & state_wbck_nxt )
`endif//E203_SUPPORT_AMO}
;
sirv_gnrl_dfflr #(ICB_STATE_WIDTH) icb_state_dfflr (icb_state_ena, icb_state_nxt, icb_state_r, clk, rst_n);
`ifdef E203_SUPPORT_AMO//{
wire icb_sta_is_last = icb_sta_is_wbck;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
wire icb_sta_is_last = 1'b0;
`endif//}
`ifdef E203_SUPPORT_AMO//{
assign state_last_exit_ena = state_wbck_exit_ena;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign state_last_exit_ena = 1'b0;
`endif//}
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
`ifndef E203_SUPPORT_AMO
!!!! ERROR: This config is not supported, must be something wrong
`endif//}
`endif//
// Indicate there is no oustanding memory transactions
`ifdef E203_SUPPORT_AMO//{
// As long as the statemachine started, we must wait it to be empty
// We cannot really kill this instruction when IRQ comes, becuase
// the AMO uop alreay write data into the memory, and we must commit
// this instructions
assign amo_wait = ~icb_sta_is_idle;
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign amo_wait = 1'b0;// If no AMO or UNaligned supported, then always 0
`endif//}
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the leftover 0 buffer
wire leftover_ena;
wire [`E203_XLEN-1:0] leftover_nxt;
wire [`E203_XLEN-1:0] leftover_r;
wire leftover_err_nxt;
wire leftover_err_r;
wire [`E203_XLEN-1:0] leftover_1_r;
wire leftover_1_ena;
wire [`E203_XLEN-1:0] leftover_1_nxt;
//
`ifdef E203_SUPPORT_AMO//{
wire amo_1stuop = icb_sta_is_1st & agu_i_algnamo;
wire amo_2nduop = icb_sta_is_2nd & agu_i_algnamo;
`endif//E203_SUPPORT_AMO}
assign leftover_ena = agu_icb_rsp_hsked & (
1'b0
`ifdef E203_SUPPORT_AMO//{
| amo_1stuop
| amo_2nduop
`endif//E203_SUPPORT_AMO}
);
assign leftover_nxt =
{`E203_XLEN{1'b0}}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{amo_1stuop }} & agu_icb_rsp_rdata)// Load the data from bus
| ({`E203_XLEN{amo_2nduop }} & leftover_r)// Unchange the value of leftover_r
`endif//E203_SUPPORT_AMO}
;
assign leftover_err_nxt = 1'b0
`ifdef E203_SUPPORT_AMO//{
| ({{amo_1stuop }} & agu_icb_rsp_err)// 1st error from the bus
| ({{amo_2nduop }} & (agu_icb_rsp_err | leftover_err_r))// second error merged
`endif//E203_SUPPORT_AMO}
;
//
// The instantiation of leftover buffer is actually shared with the ALU SBF-0 Buffer
assign agu_sbf_0_ena = leftover_ena;
assign agu_sbf_0_nxt = leftover_nxt;
assign leftover_r = agu_sbf_0_r;
// The error bit is implemented here
sirv_gnrl_dfflr #(1) icb_leftover_err_dfflr (leftover_ena, leftover_err_nxt, leftover_err_r, clk, rst_n);
assign leftover_1_ena = 1'b0
`ifdef E203_SUPPORT_AMO//{
| icb_sta_is_amoalu
`endif//E203_SUPPORT_AMO}
;
assign leftover_1_nxt = agu_req_alu_res;
//
// The instantiation of last_icb_addr buffer is actually shared with the ALU SBF-1 Buffer
assign agu_sbf_1_ena = leftover_1_ena;
assign agu_sbf_1_nxt = leftover_1_nxt;
assign leftover_1_r = agu_sbf_1_r;
assign agu_req_alu_add = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (icb_sta_is_amoalu & agu_i_amoadd)
// In order to let AMO 2nd uop have correct address
| (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck))
`endif//E203_SUPPORT_AMO}
// To cut down the timing loop from agu_i_valid // | (icb_sta_is_idle & agu_i_valid)
// we dont need this signal at all
| icb_sta_is_idle
;
assign agu_req_alu_op1 = icb_sta_is_idle ? agu_i_rs1
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? leftover_r
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_i_rs1
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
wire [`E203_XLEN-1:0] agu_addr_gen_op2 = agu_i_ofst0 ? `E203_XLEN'b0 : agu_i_imm;
assign agu_req_alu_op2 = icb_sta_is_idle ? agu_addr_gen_op2
`ifdef E203_SUPPORT_AMO//{
: icb_sta_is_amoalu ? agu_i_rs2
// In order to let AMO 2nd uop have correct address
: (agu_i_amo & (icb_sta_is_wait2nd | icb_sta_is_2nd | icb_sta_is_wbck)) ? agu_addr_gen_op2
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_UNALGNLDST//{
: `E203_XLEN'd0
`endif//}
;
`ifdef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = (icb_sta_is_amoalu & agu_i_amoswap );
assign agu_req_alu_and = (icb_sta_is_amoalu & agu_i_amoand );
assign agu_req_alu_or = (icb_sta_is_amoalu & agu_i_amoor );
assign agu_req_alu_xor = (icb_sta_is_amoalu & agu_i_amoxor );
assign agu_req_alu_max = (icb_sta_is_amoalu & agu_i_amomax );
assign agu_req_alu_min = (icb_sta_is_amoalu & agu_i_amomin );
assign agu_req_alu_maxu = (icb_sta_is_amoalu & agu_i_amomaxu );
assign agu_req_alu_minu = (icb_sta_is_amoalu & agu_i_amominu );
`endif//E203_SUPPORT_AMO}
`ifndef E203_SUPPORT_AMO//{
assign agu_req_alu_swap = 1'b0;
assign agu_req_alu_and = 1'b0;
assign agu_req_alu_or = 1'b0;
assign agu_req_alu_xor = 1'b0;
assign agu_req_alu_max = 1'b0;
assign agu_req_alu_min = 1'b0;
assign agu_req_alu_maxu = 1'b0;
assign agu_req_alu_minu = 1'b0;
`endif//}
/////////////////////////////////////////////////////////////////////////////////
// Implement the AGU op handshake ready signal
//
// The AGU op handshakeke interface will be ready when
// * If it is unaligned instructions, then it will just
// directly pass out the write-back interface, hence it will only be
// ready when the write-back interface is ready
// * If it is not unaligned load/store instructions, then it will just
// directly pass out the instruction to LSU-ctrl interface, hence it need to check
// the AGU ICB interface is ready, but it also need to ask write-back interface
// for commit, so, also need to check if write-back interfac is ready
//
`ifndef E203_SUPPORT_UNALGNLDST//{
`else//}{
!!!! ERROR: This UNALIGNED load/store is not supported, must be something wrong
`endif//}
assign agu_i_ready =
( 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
) ? state_last_exit_ena :
(agu_icb_cmd_ready & agu_o_ready) ;
// The aligned load/store instruction will be dispatched to LSU as long pipeline
// instructions
assign agu_i_longpipe = agu_i_algnldst;
//
/////////////////////////////////////////////////////////////////////////////////
// Implement the Write-back interfaces (unaligned and AMO instructions)
// The AGU write-back will be valid when:
// * For the aligned load/store
// Directly passed to ICB interface, but also need to pass
// to write-back interface asking for commit
assign agu_o_valid =
`ifdef E203_SUPPORT_AMO//{
// For the unaligned load/store and aligned AMO, it will enter
// into the state machine and let the last state to send back
// to the commit stage
icb_sta_is_last
`endif//E203_SUPPORT_AMO}
// For the aligned load/store and unaligned AMO, it will be send
// to the commit stage right the same cycle of agu_i_valid
|(
agu_i_valid & ( agu_i_algnldst
`ifndef E203_SUPPORT_UNALGNLDST//{
// If not support the unaligned load/store by hardware, then
// the unaligned load/store will be treated as exception
// and it will also be send to the commit stage right the
// same cycle of agu_i_valid
| agu_i_unalgnldst
`endif//}
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
)
//// // Since it is issuing to commit stage and
//// // LSU at same cycle, so we must qualify the icb_cmd_ready signal from LSU
//// // to make sure it is out to commit/LSU at same cycle
// To cut the critical timing path from longpipe signal
// we always assume the AGU will need icb_cmd_ready
& agu_icb_cmd_ready
);
assign agu_o_wbck_wdat = {`E203_XLEN{1'b0 }}
`ifdef E203_SUPPORT_AMO//{
| ({`E203_XLEN{agu_i_algnamo }} & leftover_r)
| ({`E203_XLEN{agu_i_unalgnamo}} & `E203_XLEN'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_o_cmt_buserr = (1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & leftover_err_r)
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
)
;
assign agu_o_cmt_badaddr = agu_icb_cmd_addr;
assign agu_o_cmt_misalgn = (1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_unalgnamo
`endif//E203_SUPPORT_AMO}
| (agu_i_unalgnldst) //& agu_i_excl) We dont support unaligned load/store regardless it is AMO or not
)
;
assign agu_o_cmt_ld = agu_i_load & (~agu_i_excl);
assign agu_o_cmt_stamo = agu_i_store | agu_i_amo | agu_i_excl;
// The exception or error result cannot write-back
assign agu_o_wbck_err = agu_o_cmt_buserr | agu_o_cmt_misalgn
;
assign agu_icb_rsp_ready = 1'b1;
assign agu_icb_cmd_valid =
((agu_i_algnldst & agu_i_valid)
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& (agu_o_ready)
)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & (
(icb_sta_is_idle & agu_i_valid
// We must qualify the agu_o_ready signal from commit stage
// to make sure it is out to commit/LSU at same cycle
& agu_o_ready)
| (icb_sta_is_wait2nd)))
| (agu_i_unalgnamo & 1'b0)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_addr = agu_req_alu_res[`E203_ADDR_SIZE-1:0];
assign agu_icb_cmd_read =
(agu_i_algnldst & agu_i_load)
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle & 1'b1)
| (agu_i_algnamo & icb_sta_is_wait2nd & 1'b0)
`endif//E203_SUPPORT_AMO}
;
// The AGU ICB CMD Wdata sources:
// * For the aligned store instructions
// Directly passed to AGU ICB, wdata is op2 repetitive form,
// wmask is generated according to the LSB and size
wire [`E203_XLEN-1:0] algnst_wdata =
({`E203_XLEN{agu_i_size_b }} & {4{agu_i_rs2[ 7:0]}})
| ({`E203_XLEN{agu_i_size_hw}} & {2{agu_i_rs2[15:0]}})
| ({`E203_XLEN{agu_i_size_w }} & {1{agu_i_rs2[31:0]}});
wire [`E203_XLEN/8-1:0] algnst_wmask =
({`E203_XLEN/8{agu_i_size_b }} & (4'b0001 << agu_icb_cmd_addr[1:0]))
| ({`E203_XLEN/8{agu_i_size_hw}} & (4'b0011 << {agu_icb_cmd_addr[1],1'b0}))
| ({`E203_XLEN/8{agu_i_size_w }} & (4'b1111));
assign agu_icb_cmd_wdata =
`ifdef E203_SUPPORT_AMO//{
agu_i_amo ? leftover_1_r :
`endif//E203_SUPPORT_AMO}
algnst_wdata;
assign agu_icb_cmd_wmask =
`ifdef E203_SUPPORT_AMO//{
// If the 1st uop have bus-error, then not write the data for 2nd uop
agu_i_amo ? (leftover_err_r ? 4'h0 : 4'hF) :
`endif//E203_SUPPORT_AMO}
algnst_wmask;
assign agu_icb_cmd_back2agu = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_algnamo
`endif//E203_SUPPORT_AMO}
;
//We dont support lock and exclusive in such 2 stage simple implementation
assign agu_icb_cmd_lock = 1'b0
`ifdef E203_SUPPORT_AMO//{
| (agu_i_algnamo & icb_sta_is_idle)
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_excl = 1'b0
`ifdef E203_SUPPORT_AMO//{
| agu_i_excl
`endif//E203_SUPPORT_AMO}
;
assign agu_icb_cmd_itag = agu_i_itag;
assign agu_icb_cmd_usign = agu_i_usign;
assign agu_icb_cmd_size =
agu_i_size;
endmodule |
module sirv_pwmgpioport(
input clock,
input reset,
input io_pwm_port_0,
input io_pwm_port_1,
input io_pwm_port_2,
input io_pwm_port_3,
input io_pins_pwm_0_i_ival,
output io_pins_pwm_0_o_oval,
output io_pins_pwm_0_o_oe,
output io_pins_pwm_0_o_ie,
output io_pins_pwm_0_o_pue,
output io_pins_pwm_0_o_ds,
input io_pins_pwm_1_i_ival,
output io_pins_pwm_1_o_oval,
output io_pins_pwm_1_o_oe,
output io_pins_pwm_1_o_ie,
output io_pins_pwm_1_o_pue,
output io_pins_pwm_1_o_ds,
input io_pins_pwm_2_i_ival,
output io_pins_pwm_2_o_oval,
output io_pins_pwm_2_o_oe,
output io_pins_pwm_2_o_ie,
output io_pins_pwm_2_o_pue,
output io_pins_pwm_2_o_ds,
input io_pins_pwm_3_i_ival,
output io_pins_pwm_3_o_oval,
output io_pins_pwm_3_o_oe,
output io_pins_pwm_3_o_ie,
output io_pins_pwm_3_o_pue,
output io_pins_pwm_3_o_ds
);
wire [1:0] T_108;
wire [1:0] T_109;
wire [3:0] T_110;
wire T_114;
wire T_115;
wire T_116;
wire T_117;
assign io_pins_pwm_0_o_oval = T_114;
assign io_pins_pwm_0_o_oe = 1'h1;
assign io_pins_pwm_0_o_ie = 1'h0;
assign io_pins_pwm_0_o_pue = 1'h0;
assign io_pins_pwm_0_o_ds = 1'h0;
assign io_pins_pwm_1_o_oval = T_115;
assign io_pins_pwm_1_o_oe = 1'h1;
assign io_pins_pwm_1_o_ie = 1'h0;
assign io_pins_pwm_1_o_pue = 1'h0;
assign io_pins_pwm_1_o_ds = 1'h0;
assign io_pins_pwm_2_o_oval = T_116;
assign io_pins_pwm_2_o_oe = 1'h1;
assign io_pins_pwm_2_o_ie = 1'h0;
assign io_pins_pwm_2_o_pue = 1'h0;
assign io_pins_pwm_2_o_ds = 1'h0;
assign io_pins_pwm_3_o_oval = T_117;
assign io_pins_pwm_3_o_oe = 1'h1;
assign io_pins_pwm_3_o_ie = 1'h0;
assign io_pins_pwm_3_o_pue = 1'h0;
assign io_pins_pwm_3_o_ds = 1'h0;
assign T_108 = {io_pwm_port_1,io_pwm_port_0};
assign T_109 = {io_pwm_port_3,io_pwm_port_2};
assign T_110 = {T_109,T_108};
assign T_114 = T_110[0];
assign T_115 = T_110[1];
assign T_116 = T_110[2];
assign T_117 = T_110[3];
endmodule |
module sirv_gnrl_pipe_stage # (
// When the depth is 1, the ready signal may relevant to next stage's ready, hence become logic
// chains. Use CUT_READY to control it
parameter CUT_READY = 0,
parameter DP = 1,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
genvar i;
generate //{
if(DP == 0) begin: dp_eq_0//{ pass through
assign o_vld = i_vld;
assign i_rdy = o_rdy;
assign o_dat = i_dat;
end//}
else begin: dp_gt_0//{
wire vld_set;
wire vld_clr;
wire vld_ena;
wire vld_r;
wire vld_nxt;
// The valid will be set when input handshaked
assign vld_set = i_vld & i_rdy;
// The valid will be clr when output handshaked
assign vld_clr = o_vld & o_rdy;
assign vld_ena = vld_set | vld_clr;
assign vld_nxt = vld_set | (~vld_clr);
sirv_gnrl_dfflr #(1) vld_dfflr (vld_ena, vld_nxt, vld_r, clk, rst_n);
assign o_vld = vld_r;
sirv_gnrl_dffl #(DW) dat_dfflr (vld_set, i_dat, o_dat, clk);
if(CUT_READY == 1) begin:cut_ready//{
// If cut ready, then only accept when stage is not full
assign i_rdy = (~vld_r);
end//}
else begin:no_cut_ready//{
// If not cut ready, then can accept when stage is not full or it is popping
assign i_rdy = (~vld_r) | vld_clr;
end//}
end//}
endgenerate//}
endmodule |
module sirv_gnrl_sync # (
parameter DP = 2,
parameter DW = 32
) (
input [DW-1:0] din_a,
output [DW-1:0] dout,
input rst_n,
input clk
);
wire [DW-1:0] sync_dat [DP-1:0];
genvar i;
generate
for(i=0;i<DP;i=i+1) begin:sync_gen
if(i==0) begin:i_is_0
sirv_gnrl_dffr #(DW) sync_dffr(din_a, sync_dat[0], clk, rst_n);
end
else begin:i_is_not_0
sirv_gnrl_dffr #(DW) sync_dffr(sync_dat[i-1], sync_dat[i], clk, rst_n);
end
end
endgenerate
assign dout = sync_dat[DP-1];
endmodule |
module sirv_gnrl_cdc_rx
# (
parameter DW = 32,
parameter SYNC_DP = 2
) (
// The 4-phases handshake interface at in-side
// There are 4 steps required for a full transaction.
// (1) The i_vld is asserted high
// (2) The i_rdy is asserted high
// (3) The i_vld is asserted low
// (4) The i_rdy is asserted low
input i_vld_a,
output i_rdy,
input [DW-1:0] i_dat,
// The regular handshake interface at out-side
// Just the regular handshake o_vld & o_rdy like AXI
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire i_vld_sync;
// Sync the async signal first
sirv_gnrl_sync #(.DP(SYNC_DP), .DW(1)) u_i_vld_sync (
.clk (clk),
.rst_n (rst_n),
.din_a (i_vld_a),
.dout (i_vld_sync)
);
wire i_vld_sync_r;
sirv_gnrl_dffr #(1) i_vld_sync_dffr(i_vld_sync, i_vld_sync_r, clk, rst_n);
wire i_vld_sync_nedge = (~i_vld_sync) & i_vld_sync_r;
wire buf_rdy;
wire i_rdy_r;
// Because it is a 4-phases handshake, so
// The i_rdy is set (assert to high) when the buf is ready (can save data) and incoming valid detected
// The i_rdy is clear when i_vld neg-edge is detected
wire i_rdy_set = buf_rdy & i_vld_sync & (~i_rdy_r);
wire i_rdy_clr = i_vld_sync_nedge;
wire i_rdy_ena = i_rdy_set | i_rdy_clr;
wire i_rdy_nxt = i_rdy_set | (~i_rdy_clr);
sirv_gnrl_dfflr #(1) i_rdy_dfflr(i_rdy_ena, i_rdy_nxt, i_rdy_r, clk, rst_n);
assign i_rdy = i_rdy_r;
wire buf_vld_r;
wire [DW-1:0] buf_dat_r;
// The buf is loaded with data when i_rdy is set high (i.e.,
// when the buf is ready (can save data) and incoming valid detected
wire buf_dat_ena = i_rdy_set;
sirv_gnrl_dfflr #(DW) buf_dat_dfflr(buf_dat_ena, i_dat, buf_dat_r, clk, rst_n);
// The buf_vld is set when the buf is loaded with data
wire buf_vld_set = buf_dat_ena;
// The buf_vld is clr when the buf is handshaked at the out-end
wire buf_vld_clr = o_vld & o_rdy;
wire buf_vld_ena = buf_vld_set | buf_vld_clr;
wire buf_vld_nxt = buf_vld_set | (~buf_vld_clr);
sirv_gnrl_dfflr #(1) buf_vld_dfflr(buf_vld_ena, buf_vld_nxt, buf_vld_r, clk, rst_n);
// The buf is ready when the buf is empty
assign buf_rdy = (~buf_vld_r);
assign o_vld = buf_vld_r;
assign o_dat = buf_dat_r;
endmodule |
module sirv_gnrl_cdc_tx
# (
parameter DW = 32,
parameter SYNC_DP = 2
) (
// The regular handshake interface at in-side
// Just the regular handshake o_vld & o_rdy like AXI
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
// The 4-phases handshake interface at out-side
// There are 4 steps required for a full transaction.
// (1) The i_vld is asserted high
// (2) The i_rdy is asserted high
// (3) The i_vld is asserted low
// (4) The i_rdy is asserted low
output o_vld,
input o_rdy_a,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire o_rdy_sync;
// Sync the async signal first
sirv_gnrl_sync #(
.DP(SYNC_DP),
.DW(1)
) u_o_rdy_sync (
.clk (clk),
.rst_n (rst_n),
.din_a (o_rdy_a),
.dout (o_rdy_sync)
);
wire vld_r;
wire [DW-1:0] dat_r;
// Valid set when it is handshaked
wire vld_set = i_vld & i_rdy;
// Valid clr when the TX o_rdy is high
wire vld_clr = o_vld & o_rdy_sync;
wire vld_ena = vld_set | vld_clr;
wire vld_nxt = vld_set | (~vld_clr);
sirv_gnrl_dfflr #(1) vld_dfflr(vld_ena, vld_nxt, vld_r, clk, rst_n);
// The data buf is only loaded when the vld is set
sirv_gnrl_dfflr #(DW) dat_dfflr(vld_set, i_dat, dat_r, clk, rst_n);
// Detect the neg-edge
wire o_rdy_sync_r;
sirv_gnrl_dffr #(1) o_rdy_sync_dffr(o_rdy_sync, o_rdy_sync_r, clk, rst_n);
wire o_rdy_nedge = (~o_rdy_sync) & o_rdy_sync_r;
// Not-ready indication
wire nrdy_r;
// Not-ready is set when the vld_r is set
wire nrdy_set = vld_set;
// Not-ready is clr when the o_rdy neg-edge is detected
wire nrdy_clr = o_rdy_nedge;
wire nrdy_ena = nrdy_set | nrdy_clr;
wire nrdy_nxt = nrdy_set | (~nrdy_clr);
sirv_gnrl_dfflr #(1) buf_nrdy_dfflr(nrdy_ena, nrdy_nxt, nrdy_r, clk, rst_n);
// The output valid
assign o_vld = vld_r;
// The output data
assign o_dat = dat_r;
// The input is ready when the Not-ready indication is low or under clearing
assign i_rdy = (~nrdy_r) | nrdy_clr;
endmodule |
module sirv_gnrl_bypbuf # (
parameter DP = 8,
parameter DW = 32
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
wire fifo_i_vld;
wire fifo_i_rdy;
wire [DW-1:0] fifo_i_dat;
wire fifo_o_vld;
wire fifo_o_rdy;
wire [DW-1:0] fifo_o_dat;
sirv_gnrl_fifo # (
.DP(DP),
.DW(DW),
.CUT_READY(1)
) u_bypbuf_fifo(
.i_vld (fifo_i_vld),
.i_rdy (fifo_i_rdy),
.i_dat (fifo_i_dat),
.o_vld (fifo_o_vld),
.o_rdy (fifo_o_rdy),
.o_dat (fifo_o_dat),
.clk (clk ),
.rst_n (rst_n)
);
// This module is a super-weapon for timing fix,
// but it is tricky, think it harder when you are reading, or contact Bob Hu
assign i_rdy = fifo_i_rdy;
// The FIFO is bypassed when:
// * fifo is empty, and o_rdy is high
wire byp = i_vld & o_rdy & (~fifo_o_vld);
// FIFO o-ready just use the o_rdy
assign fifo_o_rdy = o_rdy;
// The output is valid if FIFO or input have valid
assign o_vld = fifo_o_vld | i_vld;
// The output data select the FIFO as high priority
assign o_dat = fifo_o_vld ? fifo_o_dat : i_dat;
assign fifo_i_dat = i_dat;
// Only pass to FIFO i-valid if FIFO is not bypassed
assign fifo_i_vld = i_vld & (~byp);
endmodule |
module sirv_gnrl_fifo # (
// When the depth is 1, the ready signal may relevant to next stage's ready, hence become logic
// chains. Use CUT_READY to control it
// When fifo depth is 1, the fifo is a signle stage
// if CUT_READY is set, then the back-pressure ready signal will be cut
// off, and it can only pass 1 data every 2 cycles
// When fifo depth is > 1, then it is actually a really fifo
// The CUT_READY parameter have no impact to any logics
parameter CUT_READY = 0,
parameter MSKO = 0,// Mask out the data with valid or not
parameter DP = 8,// FIFO depth
parameter DW = 32// FIFO width
) (
input i_vld,
output i_rdy,
input [DW-1:0] i_dat,
output o_vld,
input o_rdy,
output [DW-1:0] o_dat,
input clk,
input rst_n
);
genvar i;
generate //{
if(DP == 0) begin: dp_eq1//{ pass through when it is 0 entries
assign o_vld = i_vld;
assign i_rdy = o_rdy;
assign o_dat = i_dat;
end//}
else begin: dp_gt0//{
// FIFO registers
wire [DW-1:0] fifo_rf_r [DP-1:0];
wire [DP-1:0] fifo_rf_en;
// read/write enable
wire wen = i_vld & i_rdy;
wire ren = o_vld & o_rdy;
////////////////
///////// Read-Pointer and Write-Pointer
wire [DP-1:0] rptr_vec_nxt;
wire [DP-1:0] rptr_vec_r;
wire [DP-1:0] wptr_vec_nxt;
wire [DP-1:0] wptr_vec_r;
if(DP == 1) begin:rptr_dp_1
assign rptr_vec_nxt = 1'b1;
end
else begin:rptr_dp_not_1
assign rptr_vec_nxt =
rptr_vec_r[DP-1] ? {{DP-1{1'b0}}, 1'b1} :
(rptr_vec_r << 1);
end
if(DP == 1) begin:wptr_dp_1
assign wptr_vec_nxt = 1'b1;
end
else begin:wptr_dp_not_1
assign wptr_vec_nxt =
wptr_vec_r[DP-1] ? {{DP-1{1'b0}}, 1'b1} :
(wptr_vec_r << 1);
end
sirv_gnrl_dfflrs #(1) rptr_vec_0_dfflrs (ren, rptr_vec_nxt[0] , rptr_vec_r[0] , clk, rst_n);
sirv_gnrl_dfflrs #(1) wptr_vec_0_dfflrs (wen, wptr_vec_nxt[0] , wptr_vec_r[0] , clk, rst_n);
if(DP > 1) begin:dp_gt1
sirv_gnrl_dfflr #(DP-1) rptr_vec_31_dfflr (ren, rptr_vec_nxt[DP-1:1], rptr_vec_r[DP-1:1], clk, rst_n);
sirv_gnrl_dfflr #(DP-1) wptr_vec_31_dfflr (wen, wptr_vec_nxt[DP-1:1], wptr_vec_r[DP-1:1], clk, rst_n);
end
////////////////
///////// Vec register to easy full and empty and the o_vld generation with flop-clean
wire [DP:0] i_vec;
wire [DP:0] o_vec;
wire [DP:0] vec_nxt;
wire [DP:0] vec_r;
wire vec_en = (ren ^ wen );
assign vec_nxt = wen ? {vec_r[DP-1:0], 1'b1} : (vec_r >> 1);
sirv_gnrl_dfflrs #(1) vec_0_dfflrs (vec_en, vec_nxt[0] , vec_r[0] , clk, rst_n);
sirv_gnrl_dfflr #(DP) vec_31_dfflr (vec_en, vec_nxt[DP:1], vec_r[DP:1], clk, rst_n);
assign i_vec = {1'b0,vec_r[DP:1]};
assign o_vec = {1'b0,vec_r[DP:1]};
if(DP == 1) begin:cut_dp_eq1//{
if(CUT_READY == 1) begin:cut_ready//{
// If cut ready, then only accept when fifo is not full
assign i_rdy = (~i_vec[DP-1]);
end//}
else begin:no_cut_ready//{
// If not cut ready, then can accept when fifo is not full or it is popping
assign i_rdy = (~i_vec[DP-1]) | ren;
end//}
end//}
else begin : no_cut_dp_gt1//}{
assign i_rdy = (~i_vec[DP-1]);
end//}
///////// write fifo
for (i=0; i<DP; i=i+1) begin:fifo_rf//{
assign fifo_rf_en[i] = wen & wptr_vec_r[i];
// Write the FIFO registers
sirv_gnrl_dffl #(DW) fifo_rf_dffl (fifo_rf_en[i], i_dat, fifo_rf_r[i], clk);
end//}
/////////One-Hot Mux as the read path
integer j;
reg [DW-1:0] mux_rdat;
always @*
begin : rd_port_PROC//{
mux_rdat = {DW{1'b0}};
for(j=0; j<DP; j=j+1) begin
mux_rdat = mux_rdat | ({DW{rptr_vec_r[j]}} & fifo_rf_r[j]);
end
end//}
if(MSKO == 1) begin:mask_output//{
// Mask the data with valid since the FIFO register is not reset and as X
assign o_dat = {DW{o_vld}} & mux_rdat;
end//}
else begin:no_mask_output//{
// Not Mask the data with valid since no care with X for datapth
assign o_dat = mux_rdat;
end//}
// o_vld as flop-clean
assign o_vld = (o_vec[0]);
end//}
endgenerate//}
endmodule |
module e203_exu_regfile(
input [`E203_RFIDX_WIDTH-1:0] read_src1_idx,
input [`E203_RFIDX_WIDTH-1:0] read_src2_idx,
output [`E203_XLEN-1:0] read_src1_dat,
output [`E203_XLEN-1:0] read_src2_dat,
input wbck_dest_wen,
input [`E203_RFIDX_WIDTH-1:0] wbck_dest_idx,
input [`E203_XLEN-1:0] wbck_dest_dat,
output [`E203_XLEN-1:0] x1_r,
input test_mode,
input clk,
input rst_n
);
wire [`E203_XLEN-1:0] rf_r [`E203_RFREG_NUM-1:0];
wire [`E203_RFREG_NUM-1:0] rf_wen;
`ifdef E203_REGFILE_LATCH_BASED //{
// Use DFF to buffer the write-port
wire [`E203_XLEN-1:0] wbck_dest_dat_r;
sirv_gnrl_dffl #(`E203_XLEN) wbck_dat_dffl (wbck_dest_wen, wbck_dest_dat, wbck_dest_dat_r, clk);
wire [`E203_RFREG_NUM-1:0] clk_rf_ltch;
`endif//}
genvar i;
generate //{
for (i=0; i<`E203_RFREG_NUM; i=i+1) begin:regfile//{
if(i==0) begin: rf0
// x0 cannot be wrote since it is constant-zeros
assign rf_wen[i] = 1'b0;
assign rf_r[i] = `E203_XLEN'b0;
`ifdef E203_REGFILE_LATCH_BASED //{
assign clk_rf_ltch[i] = 1'b0;
`endif//}
end
else begin: rfno0
assign rf_wen[i] = wbck_dest_wen & (wbck_dest_idx == i) ;
`ifdef E203_REGFILE_LATCH_BASED //{
e203_clkgate u_e203_clkgate(
.clk_in (clk ),
.test_mode(test_mode),
.clock_en(rf_wen[i]),
.clk_out (clk_rf_ltch[i])
);
//from write-enable to clk_rf_ltch to rf_ltch
sirv_gnrl_ltch #(`E203_XLEN) rf_ltch (clk_rf_ltch[i], wbck_dest_dat_r, rf_r[i]);
`else//}{
sirv_gnrl_dffl #(`E203_XLEN) rf_dffl (rf_wen[i], wbck_dest_dat, rf_r[i], clk);
`endif//}
end
end//}
endgenerate//}
assign read_src1_dat = rf_r[read_src1_idx];
assign read_src2_dat = rf_r[read_src2_idx];
// wire [`E203_XLEN-1:0] x0 = rf_r[0];
// wire [`E203_XLEN-1:0] x1 = rf_r[1];
// wire [`E203_XLEN-1:0] x2 = rf_r[2];
// wire [`E203_XLEN-1:0] x3 = rf_r[3];
// wire [`E203_XLEN-1:0] x4 = rf_r[4];
// wire [`E203_XLEN-1:0] x5 = rf_r[5];
// wire [`E203_XLEN-1:0] x6 = rf_r[6];
// wire [`E203_XLEN-1:0] x7 = rf_r[7];
// wire [`E203_XLEN-1:0] x8 = rf_r[8];
// wire [`E203_XLEN-1:0] x9 = rf_r[9];
// wire [`E203_XLEN-1:0] x10 = rf_r[10];
// wire [`E203_XLEN-1:0] x11 = rf_r[11];
// wire [`E203_XLEN-1:0] x12 = rf_r[12];
// wire [`E203_XLEN-1:0] x13 = rf_r[13];
// wire [`E203_XLEN-1:0] x14 = rf_r[14];
// wire [`E203_XLEN-1:0] x15 = rf_r[15];
// `ifdef E203_RFREG_NUM_IS_32 //{
// wire [`E203_XLEN-1:0] x16 = rf_r[16];
// wire [`E203_XLEN-1:0] x17 = rf_r[17];
// wire [`E203_XLEN-1:0] x18 = rf_r[18];
// wire [`E203_XLEN-1:0] x19 = rf_r[19];
// wire [`E203_XLEN-1:0] x20 = rf_r[20];
// wire [`E203_XLEN-1:0] x21 = rf_r[21];
// wire [`E203_XLEN-1:0] x22 = rf_r[22];
// wire [`E203_XLEN-1:0] x23 = rf_r[23];
// wire [`E203_XLEN-1:0] x24 = rf_r[24];
// wire [`E203_XLEN-1:0] x25 = rf_r[25];
// wire [`E203_XLEN-1:0] x26 = rf_r[26];
// wire [`E203_XLEN-1:0] x27 = rf_r[27];
// wire [`E203_XLEN-1:0] x28 = rf_r[28];
// wire [`E203_XLEN-1:0] x29 = rf_r[29];
// wire [`E203_XLEN-1:0] x30 = rf_r[30];
// wire [`E203_XLEN-1:0] x31 = rf_r[31];
// `endif//}
assign x1_r = rf_r[1];
endmodule |
module e203_core(
output[`E203_PC_SIZE-1:0] inspect_pc,
`ifdef E203_HAS_CSR_EAI//{
output eai_csr_valid,
input eai_csr_ready,
output [31:0] eai_csr_addr,
output eai_csr_wr,
output [31:0] eai_csr_wdata,
input [31:0] eai_csr_rdata,
`endif//}
output core_wfi,
output tm_stop,
output core_cgstop,
output tcm_cgstop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_r,
input [`E203_LIRQ_NUM-1:0] lcl_irq_r,
input [`E203_EVT_NUM-1:0] evt_r,
input ext_irq_r,
input sft_irq_r,
input tmr_irq_r,
//////////////////////////////////////////////////////////////
// From/To debug ctrl module
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
`ifdef E203_HAS_ITCM //{
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
input ifu2itcm_holdup,
//input ifu2itcm_replay,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to ITCM
//
// * Bus cmd channel
output lsu2itcm_icb_cmd_valid,
input lsu2itcm_icb_cmd_ready,
output [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr,
output lsu2itcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask,
output lsu2itcm_icb_cmd_lock,
output lsu2itcm_icb_cmd_excl,
output [1:0] lsu2itcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2itcm_icb_rsp_valid,
output lsu2itcm_icb_rsp_ready,
input lsu2itcm_icb_rsp_err ,
input lsu2itcm_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM //{
input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to DTCM
//
// * Bus cmd channel
output lsu2dtcm_icb_cmd_valid,
input lsu2dtcm_icb_cmd_ready,
output [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr,
output lsu2dtcm_icb_cmd_read,
output [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask,
output lsu2dtcm_icb_cmd_lock,
output lsu2dtcm_icb_cmd_excl,
output [1:0] lsu2dtcm_icb_cmd_size,
//
// * Bus RSP channel
input lsu2dtcm_icb_rsp_valid,
output lsu2dtcm_icb_rsp_ready,
input lsu2dtcm_icb_rsp_err ,
input lsu2dtcm_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata,
`endif//}
output exu_active,
output ifu_active,
output lsu_active,
output biu_active,
input clk_core_ifu,
input clk_core_exu,
input clk_core_lsu,
input clk_core_biu,
input clk_aon,
input test_mode,
input rst_n
);
`ifdef E203_HAS_MEM_ITF //{
wire ifu2biu_icb_cmd_valid;
wire ifu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr;
wire ifu2biu_icb_rsp_valid;
wire ifu2biu_icb_rsp_ready;
wire ifu2biu_icb_rsp_err ;
wire ifu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] ifu2biu_icb_rsp_rdata;
`endif//}
wire ifu_o_valid;
wire ifu_o_ready;
wire [`E203_INSTR_SIZE-1:0] ifu_o_ir;
wire [`E203_PC_SIZE-1:0] ifu_o_pc;
wire ifu_o_pc_vld;
wire ifu_o_misalgn;
wire ifu_o_buserr;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx;
wire [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx;
wire ifu_o_prdt_taken;
wire ifu_o_muldiv_b2b;
wire wfi_halt_ifu_req;
wire wfi_halt_ifu_ack;
wire pipe_flush_ack;
wire pipe_flush_req;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op1;
wire [`E203_PC_SIZE-1:0] pipe_flush_add_op2;
`ifdef E203_TIMING_BOOST//}
wire [`E203_PC_SIZE-1:0] pipe_flush_pc;
`endif//}
wire oitf_empty;
wire [`E203_XLEN-1:0] rf2ifu_x1;
wire [`E203_XLEN-1:0] rf2ifu_rs1;
wire dec2ifu_rden;
wire dec2ifu_rs1en;
wire [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx;
wire dec2ifu_mulhsu;
wire dec2ifu_div ;
wire dec2ifu_rem ;
wire dec2ifu_divu ;
wire dec2ifu_remu ;
wire itcm_nohold;
e203_ifu u_e203_ifu(
.inspect_pc (inspect_pc),
.ifu_active (ifu_active),
.pc_rtvec (pc_rtvec),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
// The ITCM address region indication signal
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn ),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx ),
.ifu_o_rs2idx (ifu_o_rs2idx ),
.ifu_o_prdt_taken (ifu_o_prdt_taken ),
.ifu_o_muldiv_b2b (ifu_o_muldiv_b2b ),
.ifu_halt_req (wfi_halt_ifu_req),
.ifu_halt_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk_core_ifu ),
.rst_n (rst_n )
);
wire lsu_o_valid;
wire lsu_o_ready;
wire [`E203_XLEN-1:0] lsu_o_wbck_wdat;
wire [`E203_ITAG_WIDTH -1:0] lsu_o_wbck_itag;
wire lsu_o_wbck_err ;
wire lsu_o_cmt_buserr ;
wire lsu_o_cmt_ld;
wire lsu_o_cmt_st;
wire [`E203_ADDR_SIZE -1:0] lsu_o_cmt_badaddr;
wire agu_icb_cmd_valid;
wire agu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] agu_icb_cmd_addr;
wire agu_icb_cmd_read;
wire [`E203_XLEN-1:0] agu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] agu_icb_cmd_wmask;
wire agu_icb_cmd_lock;
wire agu_icb_cmd_excl;
wire [1:0] agu_icb_cmd_size;
wire agu_icb_cmd_back2agu;
wire agu_icb_cmd_usign;
wire [`E203_ITAG_WIDTH -1:0] agu_icb_cmd_itag;
wire agu_icb_rsp_valid;
wire agu_icb_rsp_ready;
wire agu_icb_rsp_err ;
wire agu_icb_rsp_excl_ok ;
wire [`E203_XLEN-1:0] agu_icb_rsp_rdata;
wire commit_mret;
wire commit_trap;
wire excp_active;
e203_exu u_e203_exu(
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.test_mode (test_mode),
.core_wfi (core_wfi),
.tm_stop (tm_stop),
.itcm_nohold (itcm_nohold),
.core_cgstop (core_cgstop),
.tcm_cgstop (tcm_cgstop),
.exu_active (exu_active),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (lcl_irq_r ),
.ext_irq_r (ext_irq_r ),
.sft_irq_r (sft_irq_r ),
.tmr_irq_r (tmr_irq_r ),
.evt_r (evt_r ),
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r),
.dbg_step_r (dbg_step_r),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
.i_valid (ifu_o_valid ),
.i_ready (ifu_o_ready ),
.i_ir (ifu_o_ir ),
.i_pc (ifu_o_pc ),
.i_pc_vld (ifu_o_pc_vld ),
.i_misalgn (ifu_o_misalgn ),
.i_buserr (ifu_o_buserr ),
.i_rs1idx (ifu_o_rs1idx ),
.i_rs2idx (ifu_o_rs2idx ),
.i_prdt_taken (ifu_o_prdt_taken ),
.i_muldiv_b2b (ifu_o_muldiv_b2b ),
.wfi_halt_ifu_req (wfi_halt_ifu_req),
.wfi_halt_ifu_ack (wfi_halt_ifu_ack),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1 ),
.pipe_flush_add_op2 (pipe_flush_add_op2 ),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu (agu_icb_cmd_back2agu),
.agu_icb_cmd_usign (agu_icb_cmd_usign ),
.agu_icb_cmd_itag (agu_icb_cmd_itag ),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok ),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu (dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk_aon (clk_aon),
.clk (clk_core_exu),
.rst_n (rst_n )
);
wire lsu2biu_icb_cmd_valid;
wire lsu2biu_icb_cmd_ready;
wire [`E203_ADDR_SIZE-1:0] lsu2biu_icb_cmd_addr;
wire lsu2biu_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2biu_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2biu_icb_cmd_wmask;
wire lsu2biu_icb_cmd_lock;
wire lsu2biu_icb_cmd_excl;
wire [1:0] lsu2biu_icb_cmd_size;
wire lsu2biu_icb_rsp_valid;
wire lsu2biu_icb_rsp_ready;
wire lsu2biu_icb_rsp_err ;
wire lsu2biu_icb_rsp_excl_ok;
wire [`E203_XLEN-1:0] lsu2biu_icb_rsp_rdata;
e203_lsu u_e203_lsu(
.excp_active (excp_active),
.commit_mret (commit_mret),
.commit_trap (commit_trap),
.lsu_active (lsu_active),
.lsu_o_valid (lsu_o_valid ),
.lsu_o_ready (lsu_o_ready ),
.lsu_o_wbck_wdat (lsu_o_wbck_wdat ),
.lsu_o_wbck_itag (lsu_o_wbck_itag ),
.lsu_o_wbck_err (lsu_o_wbck_err ),
.lsu_o_cmt_buserr (lsu_o_cmt_buserr ),
.lsu_o_cmt_ld (lsu_o_cmt_ld),
.lsu_o_cmt_st (lsu_o_cmt_st),
.lsu_o_cmt_badaddr (lsu_o_cmt_badaddr ),
.agu_icb_cmd_valid (agu_icb_cmd_valid ),
.agu_icb_cmd_ready (agu_icb_cmd_ready ),
.agu_icb_cmd_addr (agu_icb_cmd_addr ),
.agu_icb_cmd_read (agu_icb_cmd_read ),
.agu_icb_cmd_wdata (agu_icb_cmd_wdata ),
.agu_icb_cmd_wmask (agu_icb_cmd_wmask ),
.agu_icb_cmd_lock (agu_icb_cmd_lock ),
.agu_icb_cmd_excl (agu_icb_cmd_excl ),
.agu_icb_cmd_size (agu_icb_cmd_size ),
.agu_icb_cmd_back2agu(agu_icb_cmd_back2agu ),
.agu_icb_cmd_usign (agu_icb_cmd_usign),
.agu_icb_cmd_itag (agu_icb_cmd_itag),
.agu_icb_rsp_valid (agu_icb_rsp_valid ),
.agu_icb_rsp_ready (agu_icb_rsp_ready ),
.agu_icb_rsp_err (agu_icb_rsp_err ),
.agu_icb_rsp_excl_ok (agu_icb_rsp_excl_ok),
.agu_icb_rsp_rdata (agu_icb_rsp_rdata),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.itcm_icb_rsp_excl_ok(lsu2itcm_icb_rsp_excl_ok ),
.itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.dtcm_region_indic (dtcm_region_indic),
.dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.dtcm_icb_rsp_excl_ok(lsu2dtcm_icb_rsp_excl_ok ),
.dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
.clk (clk_core_lsu ),
.rst_n (rst_n )
);
e203_biu u_e203_biu(
.biu_active (biu_active),
.lsu2biu_icb_cmd_valid (lsu2biu_icb_cmd_valid),
.lsu2biu_icb_cmd_ready (lsu2biu_icb_cmd_ready),
.lsu2biu_icb_cmd_addr (lsu2biu_icb_cmd_addr ),
.lsu2biu_icb_cmd_read (lsu2biu_icb_cmd_read ),
.lsu2biu_icb_cmd_wdata (lsu2biu_icb_cmd_wdata),
.lsu2biu_icb_cmd_wmask (lsu2biu_icb_cmd_wmask),
.lsu2biu_icb_cmd_lock (lsu2biu_icb_cmd_lock ),
.lsu2biu_icb_cmd_excl (lsu2biu_icb_cmd_excl ),
.lsu2biu_icb_cmd_size (lsu2biu_icb_cmd_size ),
.lsu2biu_icb_cmd_burst (2'b0),
.lsu2biu_icb_cmd_beat (2'b0 ),
.lsu2biu_icb_rsp_valid (lsu2biu_icb_rsp_valid),
.lsu2biu_icb_rsp_ready (lsu2biu_icb_rsp_ready),
.lsu2biu_icb_rsp_err (lsu2biu_icb_rsp_err ),
.lsu2biu_icb_rsp_excl_ok(lsu2biu_icb_rsp_excl_ok),
.lsu2biu_icb_rsp_rdata (lsu2biu_icb_rsp_rdata),
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid (ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready (ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_cmd_read (1'b1 ),
.ifu2biu_icb_cmd_wdata (`E203_XLEN'b0),
.ifu2biu_icb_cmd_wmask ({`E203_XLEN/8{1'b0}}),
.ifu2biu_icb_cmd_lock (1'b0 ),
.ifu2biu_icb_cmd_excl (1'b0 ),
.ifu2biu_icb_cmd_size (2'b10),
.ifu2biu_icb_cmd_burst (2'b0),
.ifu2biu_icb_cmd_beat (2'b0),
.ifu2biu_icb_rsp_valid (ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready (ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_excl_ok(ifu2biu_icb_rsp_excl_ok),
.ifu2biu_icb_rsp_rdata (ifu2biu_icb_rsp_rdata),
`endif//}
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_enable (ppi_icb_enable),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_cmd_burst (),
.ppi_icb_cmd_beat (),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_cmd_burst (),
.plic_icb_cmd_beat (),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_cmd_burst (),
.clint_icb_cmd_beat (),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_region_indic (fio_region_indic ),
.fio_icb_enable (fio_icb_enable),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_cmd_burst (),
.fio_icb_cmd_beat (),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok ),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok (mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk (clk_core_biu ),
.rst_n (rst_n )
);
endmodule |
module sirv_plic_man # (
parameter PLIC_PRIO_WIDTH = 3,
parameter PLIC_IRQ_NUM = 8,// Must larger than 1, if just 1 interrupt, please go without PLIC
parameter PLIC_IRQ_NUM_LOG2 = 3,// If the irq is 1<N<=2, then log2 value is 1;
// If the irq is 2<N<=4, then log2 value is 2;
// If the irq is 4<N<=8, then log2 value is 3;
// ....etc
// We at most support 10 levels, then 1024 interrupt sources
// But the source 0 is just always tied to zero
parameter PLIC_ICB_RSP_FLOP = 0, // Do we flop the ICB response channel to easy timing
parameter PLIC_IRQ_I_FLOP = 0, // Do we flop the input interrupts from sources
parameter PLIC_IRQ_O_FLOP = 0 // Do we flop the output interrupt to the Core target
)(
input clk,
input rst_n,
input icb_cmd_valid,
output icb_cmd_ready,
input [24-1:0] icb_cmd_addr,
input icb_cmd_read,
input [32-1:0] icb_cmd_wdata,
output icb_rsp_valid,
input icb_rsp_ready,
output [32-1:0] icb_rsp_rdata,
input [PLIC_IRQ_NUM-1:0] plic_irq_i,
output plic_irq_o
);
// If there are 32 irq, then we need 1 pend-array ([31:0])
// If there are 40 irq, then we need 2 pend-array ([39:32],[31:0])
// If there are 64 irq, then we need 2 pend-array ([63:32],[31:0])
localparam PLIC_PEND_ARRAY = (((PLIC_IRQ_NUM-1)/32) + 1);
wire icb_cmd_hsked = icb_cmd_valid & icb_cmd_ready;
wire icb_cmd_wr_hsked = icb_cmd_hsked & (~icb_cmd_read);
wire icb_cmd_rd_hsked = icb_cmd_hsked & icb_cmd_read;
wire [PLIC_IRQ_NUM-1:0] plic_irq_i_r;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_valid;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_ready;
wire [PLIC_IRQ_NUM-1:0] irq_i_gated_hsked;
reg [PLIC_IRQ_NUM-1:0] icb_claim_irq;
reg [PLIC_IRQ_NUM-1:0] icb_complete_irq;
wire irq_o;
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id ;
wire [PLIC_IRQ_NUM_LOG2-1:0] plic_irq_id ;
wire [PLIC_PRIO_WIDTH-1:0] plic_irq_prio ;
wire [PLIC_IRQ_NUM-1:0] irq_pend_set;
wire [PLIC_IRQ_NUM-1:0] irq_pend_clr;
wire [PLIC_IRQ_NUM-1:0] irq_pend_ena;
wire [PLIC_IRQ_NUM-1:0] irq_pend_nxt;
wire [PLIC_PEND_ARRAY*32-1:0] irq_pend_r; // The IP bit per interrupt source
wire [PLIC_PEND_ARRAY-1:0] icb_cmd_sel_pend;
wire icb_cmd_sel_clam;
wire icb_cmd_sel_thod;
wire irq_thod_ena;
wire [PLIC_PRIO_WIDTH-1:0] irq_thod_nxt;
wire [PLIC_PRIO_WIDTH-1:0] irq_thod_r ; // The priority per interrupt source
wire [PLIC_IRQ_NUM-1:0] icb_cmd_sel_prio;
wire [PLIC_IRQ_NUM-1:0] irq_prio_ena;
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_nxt [PLIC_IRQ_NUM-1:0];
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_r [PLIC_IRQ_NUM-1:0]; // The priority per interrupt source
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_masked [PLIC_IRQ_NUM-1:0]; // The masked priority per interrupt source
wire irq_prio_lvl_10_lt [1024-1:0]; // The level-10 max priority array
wire irq_prio_lvl_9_lt [512-1:0] ; // The level-9 max priority array
wire irq_prio_lvl_8_lt [256-1:0] ; // The level-8 max priority array
wire irq_prio_lvl_7_lt [128-1:0] ; // The level-7 max priority array
wire irq_prio_lvl_6_lt [64-1:0] ; // The level-6 max priority array
wire irq_prio_lvl_5_lt [32-1:0] ; // The level-5 max priority array
wire irq_prio_lvl_4_lt [16-1:0] ; // The level-4 max priority array
wire irq_prio_lvl_3_lt [8-1:0] ; // The level-3 max priority array
wire irq_prio_lvl_2_lt [4-1:0] ; // The level-2 max priority array
wire irq_prio_lvl_1_lt [2-1:0] ; // The level-1 max priority array
wire irq_prio_top_lt ; // The level-0 max priority
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_10 [1024-1:0] ; // The level-10 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_9 [512-1:0] ; // The level-9 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_8 [256-1:0] ; // The level-8 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_7 [128-1:0] ; // The level-7 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_6 [64-1:0] ; // The level-6 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_5 [32-1:0] ; // The level-5 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_4 [16-1:0] ; // The level-4 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_3 [8-1:0] ; // The level-3 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_2 [4-1:0] ; // The level-2 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_lvl_1 [2-1:0] ; // The level-1 max priority array
wire [PLIC_PRIO_WIDTH-1:0] irq_prio_top ; // The level-0 max priority
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_10 [1024-1:0] ; // The level-10 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_9 [512-1:0] ; // The level-9 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_8 [256-1:0] ; // The level-8 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_7 [128-1:0] ; // The level-7 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_6 [64-1:0] ; // The level-6 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_5 [32-1:0] ; // The level-5 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_4 [16-1:0] ; // The level-4 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_3 [8-1:0] ; // The level-3 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_2 [4-1:0] ; // The level-2 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_lvl_1 [2-1:0] ; // The level-1 max id array
wire [PLIC_IRQ_NUM_LOG2-1:0] irq_id_top ; // The level-0 max id
wire irq_ip_lvl_10 [1024-1:0] ; // The level-10 IP array
wire irq_ip_lvl_9 [512-1:0] ; // The level-9 IP array
wire irq_ip_lvl_8 [256-1:0] ; // The level-8 IP array
wire irq_ip_lvl_7 [128-1:0] ; // The level-7 IP array
wire irq_ip_lvl_6 [64-1:0] ; // The level-6 IP array
wire irq_ip_lvl_5 [32-1:0] ; // The level-5 IP array
wire irq_ip_lvl_4 [16-1:0] ; // The level-4 IP array
wire irq_ip_lvl_3 [8-1:0] ; // The level-3 IP array
wire irq_ip_lvl_2 [4-1:0] ; // The level-2 IP array
wire irq_ip_lvl_1 [2-1:0] ; // The level-1 IP array
wire irq_ip_top ; // The level-0 IP
wire icb_cmd_sel_enab [PLIC_PEND_ARRAY-1:0];
wire irq_enab_ena [PLIC_PEND_ARRAY-1:0];
wire [32-1:0] irq_enab_nxt [PLIC_PEND_ARRAY-1:0];
wire [32-1:0] irq_enab_r [PLIC_PEND_ARRAY-1:0];
wire plic_irq_o_pre;
genvar i;
integer ii;
generate
if(PLIC_IRQ_I_FLOP == 1) begin: flop_i_irq
sirv_gnrl_dffr #(PLIC_IRQ_NUM) plic_irq_i_dffr(plic_irq_i , plic_irq_i_r, clk, rst_n);
end
else begin: no_flop_i_irq
assign plic_irq_i_r = plic_irq_i;
end
if(PLIC_IRQ_O_FLOP == 1) begin: flop_o_irq
sirv_gnrl_dffr #(1) plic_irq_o_dffr(irq_o , plic_irq_o_pre, clk, rst_n);
sirv_gnrl_dffr #(PLIC_IRQ_NUM_LOG2) plic_irq_id_dffr(irq_id , plic_irq_id, clk, rst_n);
sirv_gnrl_dffr #(PLIC_PRIO_WIDTH) plic_irq_prio_dffr(irq_prio_top , plic_irq_prio, clk, rst_n);
end
else begin: no_flop_o_irq
assign plic_irq_o_pre = irq_o ;
assign plic_irq_id = irq_id;
assign plic_irq_prio = irq_prio_top;
end
assign plic_irq_o = plic_irq_o_pre;// & (plic_irq_prio > irq_thod_r);
assign irq_i_gated_hsked[0] = 1'b0;
assign irq_i_gated_valid[0] = 1'b0;
assign irq_i_gated_ready[0] = 1'b0;
assign irq_pend_set[0] = 1'b0;
assign irq_pend_clr[0] = 1'b0;
assign irq_pend_ena[0] = 1'b0;
assign irq_pend_nxt[0] = 1'b0;
assign irq_pend_r [0] = 1'b0;
assign irq_prio_ena[0] = 1'b0;
assign irq_prio_nxt[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_prio_r[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_prio_masked[0] = {PLIC_PRIO_WIDTH{1'b0}};
for(i=1; i<PLIC_IRQ_NUM;i=i+1) begin: source_gen//{
///////////////////////////////////////////////////////////////////
// Implment the gateway for each interrupt source
//
sirv_LevelGateway u_LevelGateway_1_1 (
.clock (clk ),
.reset (~rst_n),
.io_interrupt (plic_irq_i_r[i]),
.io_plic_valid (irq_i_gated_valid[i]),
.io_plic_ready (irq_i_gated_ready[i]),
.io_plic_complete(icb_complete_irq[i])
);
assign irq_i_gated_hsked[i] = irq_i_gated_valid[i] & irq_i_gated_ready[i];
///////////////////////////////////////////////////////////////////
// Implment the IP bit for each interrupt source
//
// If the pending irq is cleared, then it is ready to accept new interrupt from gateway
assign irq_i_gated_ready[i] = (~irq_pend_r[i]);
// The IRQ pend is set when the gateway output handshaked
assign irq_pend_set[i] = irq_i_gated_hsked[i];
// The IRQ pend is cleared when the interrupt is claimed, according to the spec:
// After the highest-priority pending interrupt is claimed by a target and the
// corresponding IP bit is cleared.
assign irq_pend_clr[i] = icb_claim_irq[i];
assign irq_pend_ena[i] = (irq_pend_set[i] | irq_pend_clr[i]);
assign irq_pend_nxt[i] = (irq_pend_set[i] | (~irq_pend_clr[i]));
sirv_gnrl_dfflr #(1) irq_pend_dfflr(irq_pend_ena[i] , irq_pend_nxt[i], irq_pend_r[i], clk, rst_n);
///////////////////////////////////////////////////////////////////
// Implment the Priority for each interrupt source
//
// The priority will be set by bus writting
assign irq_prio_ena[i] = icb_cmd_wr_hsked & icb_cmd_sel_prio[i];
assign irq_prio_nxt[i] = icb_cmd_wdata[PLIC_PRIO_WIDTH-1:0];
sirv_gnrl_dfflr #(PLIC_PRIO_WIDTH) irq_prio_dfflr(irq_prio_ena[i] , irq_prio_nxt[i], irq_prio_r[i], clk, rst_n);
///////////////////////////////////////////////////////////////////
// The priority will be masked to zero, if the IP is not set
//
assign irq_prio_masked[i] = irq_prio_r[i] & {PLIC_PRIO_WIDTH{irq_pend_r[i]}};
end//}
for(i=PLIC_IRQ_NUM; i<(PLIC_PEND_ARRAY*32);i=i+1) begin: pend_gen//{
assign irq_pend_r[i] = 1'b0;
end//}
///////////////////////////////////////////////////////////////////
// Implment the IE for each interrupt source and target
//
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: enab_r_i//{
// The IE will be set by bus writting
assign irq_enab_ena[i] = icb_cmd_sel_enab[i] & icb_cmd_wr_hsked;
sirv_gnrl_dfflr #(32) irq_enab_dfflr(irq_enab_ena[i], irq_enab_nxt[i], irq_enab_r[i], clk, rst_n);
if(i == 0)begin: i0_ena
assign irq_enab_nxt[i] = {icb_cmd_wdata[31:1],1'b0};// The 0-interrupt is always 0
end
else if((PLIC_PEND_ARRAY-1) == i) begin:last_one
if((PLIC_IRQ_NUM%32) == 0) begin:irq_num_div_32
assign irq_enab_nxt[i] = icb_cmd_wdata[31:0];
end
else begin:irq_num_not_div_32
assign irq_enab_nxt[i] = icb_cmd_wdata[(PLIC_IRQ_NUM%32)-1:0];
end
end
else begin:no_last_one
assign irq_enab_nxt[i] = icb_cmd_wdata[31:0];
end
end//}
///////////////////////////////////////////////////////////////////
// Implment the Threshold for each interrupt target
//
//
// The Threshold will be set by bus writting
assign irq_thod_ena = icb_cmd_wr_hsked & icb_cmd_sel_thod;
assign irq_thod_nxt = icb_cmd_wdata[PLIC_PRIO_WIDTH-1:0];
sirv_gnrl_dfflr #(PLIC_PRIO_WIDTH) irq_thod_dfflr(irq_thod_ena , irq_thod_nxt, irq_thod_r, clk, rst_n);
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Use the binary-tree structure to compare and select the pending interrupt
// source with the max priority and its ID
//
// Generate the level-10 signals
// We need to tie the unused signals to zeros
// and the synthesis tools will automatically
// optimize unused logics to zeros
//
// Tie the irq0 relevant logics to 0
assign irq_prio_lvl_10[0] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_id_lvl_10 [0] = {PLIC_IRQ_NUM_LOG2{1'b0}};
assign irq_ip_lvl_10 [0] = 1'b0;
for(i=1; i<PLIC_IRQ_NUM;i=i+1) begin: tie_input//{
// The priority will be masked to zero, if the IE is not set
assign irq_prio_lvl_10[i] = irq_prio_masked[i] & {PLIC_PRIO_WIDTH{irq_enab_r[i/32][i%32]}};
assign irq_id_lvl_10 [i] = i[PLIC_IRQ_NUM_LOG2-1:0];
assign irq_ip_lvl_10 [i] = irq_pend_r[i] & irq_enab_r[i/32][i%32];
end//}
for(i=PLIC_IRQ_NUM; i<1024;i=i+1) begin: tie_unused_tozero//{
assign irq_prio_lvl_10[i] = {PLIC_PRIO_WIDTH{1'b0}};
assign irq_id_lvl_10 [i] = i[PLIC_IRQ_NUM_LOG2-1:0];
assign irq_ip_lvl_10 [i] = 1'b0;
end//}
// Generate the level-9 comp
for(i=0; i<512;i=i+1) begin: lvl_9_comp_gen//{
assign irq_prio_lvl_9_lt[i] = (irq_prio_lvl_10[2*i] < irq_prio_lvl_10[(2*i)+1]);
assign irq_prio_lvl_9[i] = irq_prio_lvl_9_lt[i] ? irq_prio_lvl_10[(2*i)+1] : irq_prio_lvl_10[2*i];
assign irq_id_lvl_9 [i] = irq_prio_lvl_9_lt[i] ? irq_id_lvl_10 [(2*i)+1] : irq_id_lvl_10 [2*i];
assign irq_ip_lvl_9 [i] = irq_prio_lvl_9_lt[i] ? irq_ip_lvl_10 [(2*i)+1] : irq_ip_lvl_10 [2*i];
end//}
// Generate the level-8 comp
for(i=0; i<256;i=i+1) begin: lvl_8_comp_gen//{
assign irq_prio_lvl_8_lt[i] = (irq_prio_lvl_9[2*i] < irq_prio_lvl_9[(2*i)+1]);
assign irq_prio_lvl_8[i] = irq_prio_lvl_8_lt[i] ? irq_prio_lvl_9[(2*i)+1] : irq_prio_lvl_9[2*i];
assign irq_id_lvl_8 [i] = irq_prio_lvl_8_lt[i] ? irq_id_lvl_9 [(2*i)+1] : irq_id_lvl_9 [2*i];
assign irq_ip_lvl_8 [i] = irq_prio_lvl_8_lt[i] ? irq_ip_lvl_9 [(2*i)+1] : irq_ip_lvl_9 [2*i];
end//}
// Generate the level-7 comp
for(i=0; i<128;i=i+1) begin: lvl_7_comp_gen//{
assign irq_prio_lvl_7_lt[i] = (irq_prio_lvl_8[2*i] < irq_prio_lvl_8[(2*i)+1]);
assign irq_prio_lvl_7[i] = irq_prio_lvl_7_lt[i] ? irq_prio_lvl_8[(2*i)+1] : irq_prio_lvl_8[2*i];
assign irq_id_lvl_7 [i] = irq_prio_lvl_7_lt[i] ? irq_id_lvl_8 [(2*i)+1] : irq_id_lvl_8 [2*i];
assign irq_ip_lvl_7 [i] = irq_prio_lvl_7_lt[i] ? irq_ip_lvl_8 [(2*i)+1] : irq_ip_lvl_8 [2*i];
end//}
// Generate the level-6 comp
for(i=0; i<64;i=i+1) begin: lvl_6_comp_gen//{
assign irq_prio_lvl_6_lt[i] = (irq_prio_lvl_7[2*i] < irq_prio_lvl_7[(2*i)+1]);
assign irq_prio_lvl_6[i] = irq_prio_lvl_6_lt[i] ? irq_prio_lvl_7[(2*i)+1] : irq_prio_lvl_7[2*i];
assign irq_id_lvl_6 [i] = irq_prio_lvl_6_lt[i] ? irq_id_lvl_7 [(2*i)+1] : irq_id_lvl_7 [2*i];
assign irq_ip_lvl_6 [i] = irq_prio_lvl_6_lt[i] ? irq_ip_lvl_7 [(2*i)+1] : irq_ip_lvl_7 [2*i];
end//}
// Generate the level-5 comp
for(i=0; i<32;i=i+1) begin: lvl_5_comp_gen//{
assign irq_prio_lvl_5_lt[i] = (irq_prio_lvl_6[2*i] < irq_prio_lvl_6[(2*i)+1]);
assign irq_prio_lvl_5[i] = irq_prio_lvl_5_lt[i] ? irq_prio_lvl_6[(2*i)+1] : irq_prio_lvl_6[2*i];
assign irq_id_lvl_5 [i] = irq_prio_lvl_5_lt[i] ? irq_id_lvl_6 [(2*i)+1] : irq_id_lvl_6 [2*i];
assign irq_ip_lvl_5 [i] = irq_prio_lvl_5_lt[i] ? irq_ip_lvl_6 [(2*i)+1] : irq_ip_lvl_6 [2*i];
end//}
// Generate the level-4 comp
for(i=0; i<16;i=i+1) begin: lvl_4_comp_gen//{
assign irq_prio_lvl_4_lt[i] = (irq_prio_lvl_5[2*i] < irq_prio_lvl_5[(2*i)+1]);
assign irq_prio_lvl_4[i] = irq_prio_lvl_4_lt[i] ? irq_prio_lvl_5[(2*i)+1] : irq_prio_lvl_5[2*i];
assign irq_id_lvl_4 [i] = irq_prio_lvl_4_lt[i] ? irq_id_lvl_5 [(2*i)+1] : irq_id_lvl_5 [2*i];
assign irq_ip_lvl_4 [i] = irq_prio_lvl_4_lt[i] ? irq_ip_lvl_5 [(2*i)+1] : irq_ip_lvl_5 [2*i];
end//}
// Generate the level-3 comp
for(i=0; i<8;i=i+1) begin: lvl_3_comp_gen//{
assign irq_prio_lvl_3_lt[i] = (irq_prio_lvl_4[2*i] < irq_prio_lvl_4[(2*i)+1]);
assign irq_prio_lvl_3[i] = irq_prio_lvl_3_lt[i] ? irq_prio_lvl_4[(2*i)+1] : irq_prio_lvl_4[2*i];
assign irq_id_lvl_3 [i] = irq_prio_lvl_3_lt[i] ? irq_id_lvl_4 [(2*i)+1] : irq_id_lvl_4 [2*i];
assign irq_ip_lvl_3 [i] = irq_prio_lvl_3_lt[i] ? irq_ip_lvl_4 [(2*i)+1] : irq_ip_lvl_4 [2*i];
end//}
// Generate the level-2 comp
for(i=0; i<4;i=i+1) begin: lvl_2_comp_gen//{
assign irq_prio_lvl_2_lt[i] = (irq_prio_lvl_3[2*i] < irq_prio_lvl_3[(2*i)+1]);
assign irq_prio_lvl_2[i] = irq_prio_lvl_2_lt[i] ? irq_prio_lvl_3[(2*i)+1] : irq_prio_lvl_3[2*i];
assign irq_id_lvl_2 [i] = irq_prio_lvl_2_lt[i] ? irq_id_lvl_3 [(2*i)+1] : irq_id_lvl_3 [2*i];
assign irq_ip_lvl_2 [i] = irq_prio_lvl_2_lt[i] ? irq_ip_lvl_3 [(2*i)+1] : irq_ip_lvl_3 [2*i];
end//}
// Generate the level-1 comp
for(i=0; i<2;i=i+1) begin: lvl_1_comp_gen//{
assign irq_prio_lvl_1_lt[i] = (irq_prio_lvl_2[2*i] < irq_prio_lvl_2[(2*i)+1]);
assign irq_prio_lvl_1[i] = irq_prio_lvl_1_lt[i] ? irq_prio_lvl_2[(2*i)+1] : irq_prio_lvl_2[2*i];
assign irq_id_lvl_1 [i] = irq_prio_lvl_1_lt[i] ? irq_id_lvl_2 [(2*i)+1] : irq_id_lvl_2 [2*i];
assign irq_ip_lvl_1 [i] = irq_prio_lvl_1_lt[i] ? irq_ip_lvl_2 [(2*i)+1] : irq_ip_lvl_2 [2*i];
end//}
assign irq_prio_top_lt = (irq_prio_lvl_1[0] < irq_prio_lvl_1[1]);
assign irq_prio_top = irq_prio_top_lt ? irq_prio_lvl_1[1] : irq_prio_lvl_1[0];
assign irq_id_top = irq_prio_top_lt ? irq_id_lvl_1 [1] : irq_id_lvl_1 [0];
assign irq_ip_top = irq_prio_top_lt ? irq_ip_lvl_1 [1] : irq_ip_lvl_1 [0];
assign irq_o = irq_ip_top & (irq_prio_top > irq_thod_r);
assign irq_id = irq_id_top;
endgenerate
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Implement the ICB bus
//
// The address map
generate
//
// 0x0C00_0004 source 1 priority
// 0x0C00_0008 source 2 priority
// ...
// 0x0C00_0FFC source 1023 priority
for(i=0; i<PLIC_IRQ_NUM;i=i+1) begin: sel_prio//{
assign icb_cmd_sel_prio[i] = (icb_cmd_addr == ($unsigned(i) * 4));
end//}
//
//0x0C00 1000 Start of pending array
//... (read-only)
//0x0C00 107C End of pending array
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: sel_pend//{
assign icb_cmd_sel_pend[i] = (icb_cmd_addr == (($unsigned(i) * 4) + 24'h1000));
end//}
//
//0x0C00 1000 Start of target 0 enable array
//0x0C00 107C End of target 0 enable array
//.... target 1
//.... target 2
for(i=0; i<(PLIC_PEND_ARRAY);i=i+1) begin: sel_enab_i//{
assign icb_cmd_sel_enab[i] = (icb_cmd_addr == (($unsigned(i) * 4) + 24'h2000));
end//}
//
// 0x0C20 0000 target 0 priority threshold
// 0x0C20 0004 target 0 claim/complete
// 0x0C20 1000 target 1 priority threshold
// 0x0C20 1004 target 1 claim/complete
assign icb_cmd_sel_thod = (icb_cmd_addr == (24'h20_0000));
assign icb_cmd_sel_clam = (icb_cmd_addr == (24'h20_0004));
endgenerate
///////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////
// Implement the rdata mux
//
reg [32-1:0] rsp_rdata_prio;
reg [32-1:0] rsp_rdata_pend;
reg [32-1:0] rsp_rdata_targ;
always @* begin:rdat_prio_mux//{
rsp_rdata_prio = 32'b0;
for(ii=0; ii<PLIC_IRQ_NUM;ii=ii+1) begin: sel_prio//{
rsp_rdata_prio = rsp_rdata_prio | ({32{icb_cmd_sel_prio[ii]}} & irq_prio_r[ii] );
end//}
end//}
always @* begin:rdat_pend_mux//{
rsp_rdata_pend = 32'b0;
for(ii=0; ii<(PLIC_PEND_ARRAY);ii=ii+1) begin: sel_pend//{
rsp_rdata_pend = rsp_rdata_pend | ({32{icb_cmd_sel_pend[ii]}} &
{
irq_pend_r[ii*32+31], irq_pend_r[ii*32+30], irq_pend_r[ii*32+29], irq_pend_r[ii*32+28],
irq_pend_r[ii*32+27], irq_pend_r[ii*32+26], irq_pend_r[ii*32+25], irq_pend_r[ii*32+24],
irq_pend_r[ii*32+23], irq_pend_r[ii*32+22], irq_pend_r[ii*32+21], irq_pend_r[ii*32+20],
irq_pend_r[ii*32+19], irq_pend_r[ii*32+18], irq_pend_r[ii*32+17], irq_pend_r[ii*32+16],
irq_pend_r[ii*32+15], irq_pend_r[ii*32+14], irq_pend_r[ii*32+13], irq_pend_r[ii*32+12],
irq_pend_r[ii*32+11], irq_pend_r[ii*32+10], irq_pend_r[ii*32+09], irq_pend_r[ii*32+08],
irq_pend_r[ii*32+07], irq_pend_r[ii*32+06], irq_pend_r[ii*32+05], irq_pend_r[ii*32+04],
irq_pend_r[ii*32+03], irq_pend_r[ii*32+02], irq_pend_r[ii*32+01], irq_pend_r[ii*32+00]
});
end//}
end//}
always @* begin:rdat_targ_mux//{
rsp_rdata_targ = 32'b0;
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_thod}} & irq_thod_r );
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_clam}} & plic_irq_id);
for(ii=0; ii<(PLIC_PEND_ARRAY);ii=ii+1) begin: sel_enab_i//{
rsp_rdata_targ = rsp_rdata_targ | ({32{icb_cmd_sel_enab[ii]}} & irq_enab_r[ii]);
end//}
//
end//}
wire [32-1:0] rsp_rdata = rsp_rdata_prio | rsp_rdata_pend | rsp_rdata_targ;
generate
if(PLIC_ICB_RSP_FLOP == 1) begin: flop_icb_rsp
sirv_gnrl_pipe_stage # (
.CUT_READY(1),
.DP(1),
.DW(32)
) u_buf_icb_rsp_buf(
.i_vld(icb_cmd_valid),
.i_rdy(icb_cmd_ready),
.i_dat(rsp_rdata),
.o_vld(icb_rsp_valid),
.o_rdy(icb_rsp_ready),
.o_dat(icb_rsp_rdata),
.clk (clk ),
.rst_n(rst_n)
);
end
else begin: no_flop_icb_rsp
// Directly connect the response channel with the command channel for handshake
assign icb_rsp_valid = icb_cmd_valid;
assign icb_cmd_ready = icb_rsp_ready;
assign icb_rsp_rdata = rsp_rdata;
end
endgenerate
generate
//
for(i=0; i<PLIC_IRQ_NUM;i=i+1) begin: claim_complete_gen//{
always @* begin:claim_complete//{
icb_claim_irq [i] = 1'b0;
icb_complete_irq[i] = 1'b0;
// The read data (claimed ID) is equal to the interrupt source ID
icb_claim_irq [i] = icb_claim_irq[i] | ((icb_rsp_rdata == i) & icb_cmd_sel_clam & icb_cmd_rd_hsked);
// The write data (complete ID) is equal to the interrupt source ID
icb_complete_irq[i] = icb_complete_irq[i] | ((icb_cmd_wdata[PLIC_IRQ_NUM_LOG2-1:0] == i) & icb_cmd_sel_clam & icb_cmd_wr_hsked);
end//}
end//}
endgenerate
endmodule |
module e203_extend_csr(
// The Handshake Interface
input eai_csr_valid,
output eai_csr_ready,
input [31:0] eai_csr_addr,
input eai_csr_wr,
input [31:0] eai_csr_wdata,
output [31:0] eai_csr_rdata,
input clk,
input rst_n
);
assign eai_csr_ready = 1'b1;
assign eai_csr_rdata = 32'b0;
endmodule |
module sirv_ResetCatchAndSync_2(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [19:0] reset_n_catch_reg_io_d;
wire [19:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [18:0] T_6;
wire [19:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_129 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[19:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule |
module sirv_uartrx(
input clock,
input reset,
input io_en,
input io_in,
output io_out_valid,
output [7:0] io_out_bits,
input [15:0] io_div
);
reg [1:0] debounce;
reg [31:0] GEN_7;
wire debounce_max;
wire debounce_min;
reg [11:0] prescaler;
reg [31:0] GEN_20;
wire start;
wire busy;
wire T_21;
wire pulse;
wire [12:0] T_23;
wire [11:0] T_24;
wire [11:0] GEN_0;
wire T_25;
wire [11:0] T_26;
wire [11:0] GEN_1;
reg [2:0] sample;
reg [31:0] GEN_23;
wire T_28;
wire T_29;
wire T_30;
wire T_31;
wire T_32;
wire T_33;
wire T_34;
wire T_35;
wire [3:0] T_36;
wire [3:0] GEN_2;
reg [4:0] timer;
reg [31:0] GEN_28;
reg [3:0] counter;
reg [31:0] GEN_43;
reg [7:0] shifter;
reg [31:0] GEN_44;
wire T_41;
wire expire;
wire sched;
wire [5:0] T_44;
wire [4:0] T_45;
wire [4:0] GEN_3;
wire [4:0] GEN_4;
reg valid;
reg [31:0] GEN_45;
reg [1:0] state;
reg [31:0] GEN_46;
wire T_50;
wire T_52;
wire T_54;
wire T_56;
wire T_57;
wire [2:0] T_59;
wire [1:0] T_60;
wire [1:0] GEN_5;
wire [2:0] T_64;
wire [1:0] T_65;
wire [1:0] GEN_6;
wire [4:0] GEN_8;
wire [1:0] GEN_9;
wire [1:0] GEN_10;
wire GEN_11;
wire [4:0] GEN_12;
wire [1:0] GEN_13;
wire [1:0] GEN_14;
wire GEN_15;
wire [4:0] GEN_16;
wire T_68;
wire [1:0] GEN_17;
wire T_72;
wire [1:0] GEN_18;
wire [3:0] GEN_19;
wire [1:0] GEN_21;
wire [3:0] GEN_22;
wire GEN_24;
wire [1:0] GEN_25;
wire [3:0] GEN_26;
wire T_74;
wire [4:0] T_77;
wire [3:0] T_78;
wire T_80;
wire [1:0] GEN_27;
wire T_83;
wire [6:0] T_84;
wire [7:0] T_85;
wire [7:0] GEN_29;
wire GEN_30;
wire [3:0] GEN_31;
wire [1:0] GEN_32;
wire GEN_33;
wire [7:0] GEN_34;
wire GEN_35;
wire GEN_36;
wire [3:0] GEN_37;
wire [1:0] GEN_38;
wire GEN_39;
wire [7:0] GEN_40;
wire GEN_41;
wire T_88;
wire [1:0] GEN_42;
assign io_out_valid = valid;
assign io_out_bits = shifter;
assign debounce_max = debounce == 2'h3;
assign debounce_min = debounce == 2'h0;
assign start = GEN_15;
assign busy = GEN_36;
assign T_21 = prescaler == 12'h0;
assign pulse = T_21 & busy;
assign T_23 = prescaler - 12'h1;
assign T_24 = T_23[11:0];
assign GEN_0 = busy ? T_24 : prescaler;
assign T_25 = start | pulse;
assign T_26 = io_div[15:4];
assign GEN_1 = T_25 ? T_26 : GEN_0;
assign T_28 = sample[0];
assign T_29 = sample[1];
assign T_30 = sample[2];
assign T_31 = T_28 & T_29;
assign T_32 = T_28 & T_30;
assign T_33 = T_31 | T_32;
assign T_34 = T_29 & T_30;
assign T_35 = T_33 | T_34;
assign T_36 = {sample,io_in};
assign GEN_2 = pulse ? T_36 : {{1'd0}, sample};
assign T_41 = timer == 5'h0;
assign expire = T_41 & pulse;
assign sched = GEN_41;
assign T_44 = timer - 5'h1;
assign T_45 = T_44[4:0];
assign GEN_3 = pulse ? T_45 : timer;
assign GEN_4 = sched ? 5'hf : GEN_3;
assign T_50 = 2'h0 == state;
assign T_52 = io_in == 1'h0;
assign T_54 = T_52 == 1'h0;
assign T_56 = debounce_min == 1'h0;
assign T_57 = T_54 & T_56;
assign T_59 = debounce - 2'h1;
assign T_60 = T_59[1:0];
assign GEN_5 = T_57 ? T_60 : debounce;
assign T_64 = debounce + 2'h1;
assign T_65 = T_64[1:0];
assign GEN_6 = debounce_max ? 2'h1 : state;
assign GEN_8 = debounce_max ? 5'h8 : GEN_4;
assign GEN_9 = T_52 ? T_65 : GEN_5;
assign GEN_10 = T_52 ? GEN_6 : state;
assign GEN_11 = T_52 ? debounce_max : 1'h0;
assign GEN_12 = T_52 ? GEN_8 : GEN_4;
assign GEN_13 = T_50 ? GEN_9 : debounce;
assign GEN_14 = T_50 ? GEN_10 : state;
assign GEN_15 = T_50 ? GEN_11 : 1'h0;
assign GEN_16 = T_50 ? GEN_12 : GEN_4;
assign T_68 = 2'h1 == state;
assign GEN_17 = T_35 ? 2'h0 : GEN_14;
assign T_72 = T_35 == 1'h0;
assign GEN_18 = T_72 ? 2'h2 : GEN_17;
assign GEN_19 = T_72 ? 4'h8 : counter;
assign GEN_21 = expire ? GEN_18 : GEN_14;
assign GEN_22 = expire ? GEN_19 : counter;
assign GEN_24 = T_68 ? expire : 1'h0;
assign GEN_25 = T_68 ? GEN_21 : GEN_14;
assign GEN_26 = T_68 ? GEN_22 : counter;
assign T_74 = 2'h2 == state;
assign T_77 = counter - 4'h1;
assign T_78 = T_77[3:0];
assign T_80 = counter == 4'h0;
assign GEN_27 = T_80 ? 2'h0 : GEN_25;
assign T_83 = T_80 == 1'h0;
assign T_84 = shifter[7:1];
assign T_85 = {T_35,T_84};
assign GEN_29 = T_83 ? T_85 : shifter;
assign GEN_30 = T_83 ? 1'h1 : GEN_24;
assign GEN_31 = expire ? T_78 : GEN_26;
assign GEN_32 = expire ? GEN_27 : GEN_25;
assign GEN_33 = expire ? T_80 : 1'h0;
assign GEN_34 = expire ? GEN_29 : shifter;
assign GEN_35 = expire ? GEN_30 : GEN_24;
assign GEN_36 = T_74 ? 1'h1 : T_68;
assign GEN_37 = T_74 ? GEN_31 : GEN_26;
assign GEN_38 = T_74 ? GEN_32 : GEN_25;
assign GEN_39 = T_74 ? GEN_33 : 1'h0;
assign GEN_40 = T_74 ? GEN_34 : shifter;
assign GEN_41 = T_74 ? GEN_35 : GEN_24;
assign T_88 = io_en == 1'h0;
assign GEN_42 = T_88 ? 2'h0 : GEN_13;
always @(posedge clock or posedge reset)
if (reset) begin
debounce <= 2'h0;
end else begin
if (T_88) begin
debounce <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
debounce <= T_65;
end else begin
if (T_57) begin
debounce <= T_60;
end
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
prescaler <= 12'h0;
end else begin
if (T_25) begin
prescaler <= T_26;
end else begin
if (busy) begin
prescaler <= T_24;
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
sample <= 3'b0;
timer <= 5'h0;
counter <= 4'b0;
shifter <= 8'b0;
end
else begin
sample <= GEN_2[2:0];
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
timer <= 5'h8;
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
end else begin
if (sched) begin
timer <= 5'hf;
end else begin
if (pulse) begin
timer <= T_45;
end
end
end
if (T_74) begin
if (expire) begin
counter <= T_78;
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
counter <= 4'h8;
end
end
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
counter <= 4'h8;
end
end
end
end
if (T_74) begin
if (expire) begin
if (T_83) begin
shifter <= T_85;
end
end
end
end
always @(posedge clock or posedge reset)
if (reset) begin
valid <= 1'h0;
end else begin
if (T_74) begin
if (expire) begin
valid <= T_80;
end else begin
valid <= 1'h0;
end
end else begin
valid <= 1'h0;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
state <= 2'h0;
end else begin
if (T_74) begin
if (expire) begin
if (T_80) begin
state <= 2'h0;
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
if (T_50) begin
if (T_52) begin
if (debounce_max) begin
state <= 2'h1;
end
end
end
end
end
end else begin
state <= GEN_14;
end
end else begin
state <= GEN_14;
end
end
end else begin
if (T_68) begin
if (expire) begin
if (T_72) begin
state <= 2'h2;
end else begin
if (T_35) begin
state <= 2'h0;
end else begin
state <= GEN_14;
end
end
end else begin
state <= GEN_14;
end
end else begin
state <= GEN_14;
end
end
end
endmodule |
Subsets and Splits