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module uart_tx (
input wire clk_i,
input wire rstn_i,
output reg tx_o,
output wire busy_o,
input wire cfg_en_i,
input wire [15:0] cfg_div_i,
input wire cfg_parity_en_i,
input wire [1:0] cfg_parity_sel_i,
input wire [1:0] cfg_bits_i,
input wire cfg_stop_bits_i,
input wire [7:0] tx_data_i,
input wire tx_valid_i,
output reg tx_ready_o
);
localparam [2:0] IDLE = 0;
localparam [2:0] START_BIT = 1;
localparam [2:0] DATA = 2;
localparam [2:0] PARITY = 3;
localparam [2:0] STOP_BIT_FIRST = 4;
localparam [2:0] STOP_BIT_LAST = 5;
reg [2:0] CS,NS;
reg [7:0] reg_data;
reg [7:0] reg_data_next;
reg [2:0] reg_bit_count;
reg [2:0] reg_bit_count_next;
reg [2:0] s_target_bits;
reg parity_bit;
reg parity_bit_next;
reg sampleData;
reg [15:0] baud_cnt;
reg baudgen_en;
reg bit_done;
assign busy_o = (CS != IDLE);
always @(*) begin
case (cfg_bits_i)
2'b00: s_target_bits = 3'h4;
2'b01: s_target_bits = 3'h5;
2'b10: s_target_bits = 3'h6;
2'b11: s_target_bits = 3'h7;
endcase
end
always @(*) begin
NS = CS;
tx_o = 1'b1;
sampleData = 1'b0;
reg_bit_count_next = reg_bit_count;
reg_data_next = {1'b1, reg_data[7:1]};
tx_ready_o = 1'b0;
baudgen_en = 1'b0;
parity_bit_next = parity_bit;
case (CS)
IDLE: begin
if (cfg_en_i)
tx_ready_o = 1'b1;
if (tx_valid_i) begin
NS = START_BIT;
sampleData = 1'b1;
reg_data_next = tx_data_i;
end
end
START_BIT: begin
tx_o = 1'b0;
parity_bit_next = 1'b0;
baudgen_en = 1'b1;
if (bit_done)
NS = DATA;
end
DATA: begin
tx_o = reg_data[0];
baudgen_en = 1'b1;
parity_bit_next = parity_bit ^ reg_data[0];
if (bit_done) begin
if (reg_bit_count == s_target_bits) begin
reg_bit_count_next = 'h0;
if (cfg_parity_en_i)
NS = PARITY;
else
NS = STOP_BIT_FIRST;
end else begin
reg_bit_count_next = reg_bit_count + 1;
sampleData = 1'b1;
end
end
end
PARITY: begin
case (cfg_parity_sel_i)
2'b00: tx_o = ~parity_bit;
2'b01: tx_o = parity_bit;
2'b10: tx_o = 1'b0;
2'b11: tx_o = 1'b1;
endcase
baudgen_en = 1'b1;
if (bit_done)
NS = STOP_BIT_FIRST;
end
STOP_BIT_FIRST: begin
tx_o = 1'b1;
baudgen_en = 1'b1;
if (bit_done) begin
if (cfg_stop_bits_i)
NS = STOP_BIT_LAST;
else
NS = IDLE;
end
end
STOP_BIT_LAST: begin
tx_o = 1'b1;
baudgen_en = 1'b1;
if (bit_done)
NS = IDLE;
end
default: NS = IDLE;
endcase
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
CS <= IDLE;
reg_data <= 8'hff;
reg_bit_count <= 'h0;
parity_bit <= 1'b0;
end else begin
if (bit_done)
parity_bit <= parity_bit_next;
if (sampleData)
reg_data <= reg_data_next;
reg_bit_count <= reg_bit_count_next;
if (cfg_en_i)
CS <= NS;
else
CS <= IDLE;
end
end
always @(posedge clk_i or negedge rstn_i) begin
if (rstn_i == 1'b0) begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end else if (baudgen_en) begin
if (baud_cnt == cfg_div_i) begin
baud_cnt <= 'h0;
bit_done <= 1'b1;
end
else begin
baud_cnt <= baud_cnt + 1;
bit_done <= 1'b0;
end
end else begin
baud_cnt <= 'h0;
bit_done <= 1'b0;
end
end
//synopsys translate_off
always @(posedge clk_i or negedge rstn_i) begin
if ((tx_valid_i & tx_ready_o) & rstn_i)
$fwrite(32'h80000002, "%c", tx_data_i);
end
//synopsys translate_on
endmodule |
module apb_uart_sv
#(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
)
(
input wire CLK,
input wire RSTN,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
input wire rx_i, // Receiver input
output wire tx_o, // Transmitter output
output wire event_o // interrupt/event output
);
// register addresses
parameter RBR = 3'h0, THR = 3'h0, DLL = 3'h0, IER = 3'h1, DLM = 3'h1, IIR = 3'h2,
FCR = 3'h2, LCR = 3'h3, MCR = 3'h4, LSR = 3'h5, MSR = 3'h6, SCR = 3'h7;
parameter TX_FIFO_DEPTH = 16; // in bytes
parameter RX_FIFO_DEPTH = 16; // in bytes
wire [2:0] register_adr;
reg [79:0] regs_q, regs_n;
reg [1:0] trigger_level_n, trigger_level_q;
// receive buffer register, read only
wire [7:0] rx_data;
// parity error
wire parity_error;
wire [3:0] IIR_o;
reg [3:0] clr_int;
// tx flow control
wire tx_ready;
// rx flow control
reg apb_rx_ready;
wire rx_valid;
reg tx_fifo_clr_n, tx_fifo_clr_q;
reg rx_fifo_clr_n, rx_fifo_clr_q;
reg fifo_tx_valid;
wire tx_valid;
wire fifo_rx_valid;
reg fifo_rx_ready;
wire rx_ready;
reg [7:0] fifo_tx_data;
wire [8:0] fifo_rx_data;
wire [7:0] tx_data;
wire [$clog2(TX_FIFO_DEPTH):0] tx_elements;
wire [$clog2(RX_FIFO_DEPTH):0] rx_elements;
// TODO: check that stop bits are really not necessary here
uart_rx uart_rx_i(
.clk_i ( CLK ),
.rstn_i ( RSTN ),
.rx_i ( rx_i ),
.cfg_en_i ( 1'b1 ),
.cfg_div_i ( {regs_q[(DLM + 'd8) * 8+:8], regs_q[(DLL + 'd8) * 8+:8]} ),
.cfg_parity_en_i ( regs_q[(LCR * 8) + 3] ),
.cfg_parity_sel_i ( regs_q[(LCR * 8) + 5-:2] ),
.cfg_bits_i ( regs_q[(LCR * 8) + 1-:2] ),
// .cfg_stop_bits_i ( regs_q[(LCR * 8) + 2] ),
.busy_o ( ),
.err_o ( parity_error ),
.err_clr_i ( 1'b0 ),
.rx_data_o ( rx_data ),
.rx_valid_o ( rx_valid ),
.rx_ready_i ( rx_ready )
);
uart_tx uart_tx_i(
.clk_i ( CLK ),
.rstn_i ( RSTN ),
.tx_o ( tx_o ),
.busy_o ( ),
.cfg_en_i ( 1'b1 ),
.cfg_div_i ( {regs_q[(DLM + 'd8) * 8+:8], regs_q[(DLL + 'd8) * 8+:8]} ),
.cfg_parity_en_i ( regs_q[(LCR * 8) + 3] ),
.cfg_parity_sel_i ( regs_q[(LCR * 8) + 5-:2] ),
.cfg_bits_i ( regs_q[(LCR * 8) + 1-:2] ),
.cfg_stop_bits_i ( regs_q[(LCR * 8) + 2] ),
.tx_data_i ( tx_data ),
.tx_valid_i ( tx_valid ),
.tx_ready_o ( tx_ready )
);
io_generic_fifo #(
.DATA_WIDTH (9),
.BUFFER_DEPTH (RX_FIFO_DEPTH)
) uart_rx_fifo_i(
.clk_i ( CLK ),
.rstn_i ( RSTN ),
.clr_i ( rx_fifo_clr_q ),
.elements_o ( rx_elements ),
.data_o ( fifo_rx_data ),
.valid_o ( fifo_rx_valid ),
.ready_i ( fifo_rx_ready ),
.valid_i ( rx_valid ),
.data_i ( {parity_error, rx_data} ),
.ready_o ( rx_ready )
);
io_generic_fifo #(
.DATA_WIDTH (8),
.BUFFER_DEPTH (TX_FIFO_DEPTH)
) uart_tx_fifo_i(
.clk_i ( CLK ),
.rstn_i ( RSTN ),
.clr_i ( tx_fifo_clr_q ),
.elements_o ( tx_elements ),
.data_o ( tx_data ),
.valid_o ( tx_valid ),
.ready_i ( tx_ready ),
.valid_i ( fifo_tx_valid ),
.data_i ( fifo_tx_data ),
// not needed since we are getting the status via the fifo population
.ready_o ( )
);
uart_interrupt #(
.TX_FIFO_DEPTH (TX_FIFO_DEPTH),
.RX_FIFO_DEPTH (RX_FIFO_DEPTH)
) uart_interrupt_i(
.clk_i ( CLK ),
.rstn_i ( RSTN ),
.IER_i ( regs_q[(IER * 8) + 2-:3] ), // interrupt enable register
.error_i ( regs_n[(LSR * 8) + 2] ),
.rx_elements_i ( rx_elements ),
.tx_elements_i ( tx_elements ),
.trigger_level_i ( trigger_level_q ),
.clr_int_i ( clr_int ), // one hot
.interrupt_o ( event_o ),
.IIR_o ( IIR_o )
);
// UART Registers
// register write and update logic
always @(*) begin
regs_n = regs_q;
trigger_level_n = trigger_level_q;
fifo_tx_valid = 1'b0;
tx_fifo_clr_n = 1'b0; // self clearing
rx_fifo_clr_n = 1'b0; // self clearing
// rx status
regs_n[LSR * 8] = fifo_rx_valid; // fifo is empty
// parity error on receiving part has occured
regs_n[(LSR * 8) + 2] = fifo_rx_data[8]; // parity error is detected when element is retrieved
// tx status register
regs_n[(LSR * 8) + 5] = ~(|tx_elements); // fifo is empty
regs_n[(LSR * 8) + 6] = tx_ready & ~(|tx_elements); // shift register and fifo are empty
if (PSEL && PENABLE && PWRITE)
begin
case (register_adr)
THR: // either THR or DLL
begin
if (regs_q[(LCR * 8) + 7]) begin // Divisor Latch Access Bit (DLAB)
regs_n[(DLL + 'd8) * 8+:8] = PWDATA[7:0];
end else begin
fifo_tx_data = PWDATA[7:0];
fifo_tx_valid = 1'b1;
end
end
IER: // either IER or DLM
begin
if (regs_q[(LCR * 8) + 7]) // Divisor Latch Access Bit (DLAB)
regs_n[(DLM + 'd8) * 8+:8] = PWDATA[7:0];
else
regs_n[IER * 8+:8] = PWDATA[7:0];
end
LCR:
regs_n[LCR * 8+:8] = PWDATA[7:0];
FCR: // write only register, fifo control register
begin
rx_fifo_clr_n = PWDATA[1];
tx_fifo_clr_n = PWDATA[2];
trigger_level_n = PWDATA[7:6];
end
endcase
end
end
// register read logic
always @(*) begin
PRDATA = 'b0;
apb_rx_ready = 1'b0;
fifo_rx_ready = 1'b0;
clr_int = 4'b0;
if (PSEL && PENABLE && !PWRITE)
begin
case (register_adr)
RBR: // either RBR or DLL
begin
if (regs_q[(LCR * 8) + 7]) // Divisor Latch Access Bit (DLAB)
PRDATA = {24'b0, regs_q[(DLL + 'd8) * 8+:8]};
else begin
fifo_rx_ready = 1'b1;
PRDATA = {24'b0, fifo_rx_data[7:0]};
clr_int = 4'b1000; // clear Received Data Available interrupt
end
end
LSR: // Line Status Register
begin
PRDATA = {24'b0, regs_q[LSR * 8+:8]};
clr_int = 4'b1100; // clear parrity interrupt error
end
LCR: // Line Control Register
PRDATA = {24'b0, regs_q[LCR * 8+:8]};
IER: // either IER or DLM
begin
if (regs_q[(LCR * 8) + 7]) // Divisor Latch Access Bit (DLAB)
PRDATA = {24'b0, regs_q[(DLM + 'd8) * 8+:8]};
else
PRDATA = {24'b0, regs_q[IER * 8+:8]};
end
IIR: // interrupt identification register read only
begin
PRDATA = {24'b0, 1'b1, 1'b1, 2'b0, IIR_o};
clr_int = 4'b0100; // clear Transmitter Holding Register Empty
end
default:
PRDATA = 'b0;
endcase
end
end
// synchronouse part
always @(posedge CLK or negedge RSTN) begin
if(~RSTN) begin
regs_q[IER * 8+:8] <= 8'h00;
regs_q[IIR * 8+:8] <= 8'h01;
regs_q[LCR * 8+:8] <= 8'h00;
regs_q[MCR * 8+:8] <= 8'h00;
regs_q[LSR * 8+:8] <= 8'h60;
regs_q[MSR * 8+:8] <= 8'h00;
regs_q[SCR * 8+:8] <= 8'h00;
regs_q[(DLM + 'd8) * 8+:8] <= 8'h00;
regs_q[(DLL + 'd8) * 8+:8] <= 8'h00;
trigger_level_q <= 2'b00;
tx_fifo_clr_q <= 1'b0;
rx_fifo_clr_q <= 1'b0;
end else begin
regs_q <= regs_n;
trigger_level_q <= trigger_level_n;
tx_fifo_clr_q <= tx_fifo_clr_n;
rx_fifo_clr_q <= rx_fifo_clr_n;
end
end
assign register_adr = {PADDR[4:2]};
// APB logic: we are always ready to capture the data into our regs
// not supporting transfare failure
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule |
module apb_spi_master
#(
parameter BUFFER_DEPTH = 10,
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
)
(
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output wire events_o,
output wire spi_clk,
output wire spi_csn0,
output wire spi_csn1,
output wire spi_csn2,
output wire spi_csn3,
output wire spi_sdo0,
output wire spi_sdo1,
output wire spi_sdo2,
output wire spi_sdo3,
output reg spi_oe0,
output reg spi_oe1,
output reg spi_oe2,
output reg spi_oe3,
input wire spi_sdi0,
input wire spi_sdi1,
input wire spi_sdi2,
input wire spi_sdi3
);
localparam LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH);
wire [7:0] spi_clk_div;
wire spi_clk_div_valid;
wire [31:0] spi_status;
wire [31:0] spi_addr;
wire [5:0] spi_addr_len;
wire [31:0] spi_cmd;
wire [5:0] spi_cmd_len;
wire [15:0] spi_data_len;
wire [15:0] spi_dummy_rd;
wire [15:0] spi_dummy_wr;
wire spi_swrst;
wire spi_rd;
wire spi_wr;
wire spi_qrd;
wire spi_qwr;
wire [3:0] spi_csreg;
wire [31:0] spi_data_tx;
wire spi_data_tx_valid;
wire spi_data_tx_ready;
wire [31:0] spi_data_rx;
wire spi_data_rx_valid;
wire spi_data_rx_ready;
wire [6:0] spi_ctrl_status;
wire [31:0] spi_ctrl_data_tx;
wire spi_ctrl_data_tx_valid;
wire spi_ctrl_data_tx_ready;
wire [31:0] spi_ctrl_data_rx;
wire spi_ctrl_data_rx_valid;
wire spi_ctrl_data_rx_ready;
wire [1:0] spi_mode;
wire s_eot;
wire [LOG_BUFFER_DEPTH:0] elements_tx;
wire [LOG_BUFFER_DEPTH:0] elements_rx;
wire [LOG_BUFFER_DEPTH:0] s_th_tx;
wire [LOG_BUFFER_DEPTH:0] s_th_rx;
wire s_rise_int_tx;
wire s_rise_int_rx;
wire s_int_tx;
wire s_int_rx;
wire s_int_en;
wire [31:0] s_int_status;
localparam FILL_BITS = 7 - LOG_BUFFER_DEPTH;
assign spi_status = {{FILL_BITS {1'b0}}, elements_tx, {FILL_BITS {1'b0}}, elements_rx, 9'h000, spi_ctrl_status};
assign s_rise_int_tx = s_int_en & (elements_tx < s_th_tx);
assign s_rise_int_rx = s_int_en & (elements_rx > s_th_rx);
assign events_o = s_rise_int_tx | s_rise_int_rx;
assign s_int_status = {s_rise_int_rx, s_rise_int_tx};
always @(*) begin
spi_oe0 = 1'b0;
spi_oe1 = 1'b0;
spi_oe2 = 1'b0;
spi_oe3 = 1'b0;
case (spi_mode)
`SPI_STD: begin
spi_oe0 = 1'b1;
spi_oe1 = 1'b0;
spi_oe2 = 1'b0;
spi_oe3 = 1'b0;
end
`SPI_QUAD_TX: begin
spi_oe0 = 1'b1;
spi_oe1 = 1'b1;
spi_oe2 = 1'b1;
spi_oe3 = 1'b1;
end
`SPI_QUAD_RX: begin
spi_oe0 = 1'b0;
spi_oe1 = 1'b0;
spi_oe2 = 1'b0;
spi_oe3 = 1'b0;
end
endcase
end
spi_master_apb_if
#(
.BUFFER_DEPTH ( BUFFER_DEPTH ),
.APB_ADDR_WIDTH ( APB_ADDR_WIDTH )
)
u_axiregs
(
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.PADDR ( PADDR ),
.PWDATA ( PWDATA ),
.PWRITE ( PWRITE ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PRDATA ( PRDATA ),
.PREADY ( PREADY ),
.PSLVERR ( PSLVERR ),
.spi_clk_div ( spi_clk_div ),
.spi_clk_div_valid ( spi_clk_div_valid ),
.spi_status ( spi_status ),
.spi_addr ( spi_addr ),
.spi_addr_len ( spi_addr_len ),
.spi_cmd ( spi_cmd ),
.spi_cmd_len ( spi_cmd_len ),
.spi_data_len ( spi_data_len ),
.spi_dummy_rd ( spi_dummy_rd ),
.spi_dummy_wr ( spi_dummy_wr ),
.spi_swrst ( spi_swrst ),
.spi_rd ( spi_rd ),
.spi_wr ( spi_wr ),
.spi_qrd ( spi_qrd ),
.spi_qwr ( spi_qwr ),
.spi_csreg ( spi_csreg ),
.spi_int_th_rx ( s_th_rx ),
.spi_int_th_tx ( s_th_tx ),
.spi_int_en ( s_int_en ),
.spi_int_status ( s_int_status ),
.spi_data_tx ( spi_data_tx ),
.spi_data_tx_valid ( spi_data_tx_valid ),
.spi_data_tx_ready ( spi_data_tx_ready ), //FIXME not used inside thhis module
.spi_data_rx ( spi_data_rx ),
.spi_data_rx_valid ( spi_data_rx_valid ),
.spi_data_rx_ready ( spi_data_rx_ready )
);
spi_master_fifo
#(
.DATA_WIDTH ( 32 ),
.BUFFER_DEPTH ( BUFFER_DEPTH )
)
u_txfifo
(
.clk_i ( HCLK ),
.rst_ni ( HRESETn ),
.clr_i ( spi_swrst ),
.elements_o ( elements_tx ),
.data_o ( spi_ctrl_data_tx ),
.valid_o ( spi_ctrl_data_tx_valid ),
.ready_i ( spi_ctrl_data_tx_ready ),
.valid_i ( spi_data_tx_valid ),
.data_i ( spi_data_tx ),
.ready_o ( spi_data_tx_ready )
);
spi_master_fifo
#(
.DATA_WIDTH ( 32 ),
.BUFFER_DEPTH ( BUFFER_DEPTH )
)
u_rxfifo
(
.clk_i ( HCLK ),
.rst_ni ( HRESETn ),
.clr_i ( spi_swrst ),
.elements_o ( elements_rx ),
.data_o ( spi_data_rx ),
.valid_o ( spi_data_rx_valid ),
.ready_i ( spi_data_rx_ready ),
.valid_i ( spi_ctrl_data_rx_valid ),
.data_i ( spi_ctrl_data_rx ),
.ready_o ( spi_ctrl_data_rx_ready )
);
spi_master_controller u_spictrl
(
.clk ( HCLK ),
.rstn ( HRESETn ),
.eot ( s_eot ),
.spi_clk_div ( spi_clk_div ),
.spi_clk_div_valid ( spi_clk_div_valid ),
.spi_status ( spi_ctrl_status ),
.spi_addr ( spi_addr ),
.spi_addr_len ( spi_addr_len ),
.spi_cmd ( spi_cmd ),
.spi_cmd_len ( spi_cmd_len ),
.spi_data_len ( spi_data_len ),
.spi_dummy_rd ( spi_dummy_rd ),
.spi_dummy_wr ( spi_dummy_wr ),
.spi_swrst ( spi_swrst ),
.spi_rd ( spi_rd ),
.spi_wr ( spi_wr ),
.spi_qrd ( spi_qrd ),
.spi_qwr ( spi_qwr ),
.spi_csreg ( spi_csreg ),
.spi_ctrl_data_tx ( spi_ctrl_data_tx ),
.spi_ctrl_data_tx_valid ( spi_ctrl_data_tx_valid ),
.spi_ctrl_data_tx_ready ( spi_ctrl_data_tx_ready ),
.spi_ctrl_data_rx ( spi_ctrl_data_rx ),
.spi_ctrl_data_rx_valid ( spi_ctrl_data_rx_valid ),
.spi_ctrl_data_rx_ready ( spi_ctrl_data_rx_ready ),
.spi_clk ( spi_clk ),
.spi_csn0 ( spi_csn0 ),
.spi_csn1 ( spi_csn1 ),
.spi_csn2 ( spi_csn2 ),
.spi_csn3 ( spi_csn3 ),
.spi_mode ( spi_mode ),
.spi_sdo0 ( spi_sdo0 ),
.spi_sdo1 ( spi_sdo1 ),
.spi_sdo2 ( spi_sdo2 ),
.spi_sdo3 ( spi_sdo3 ),
.spi_sdi0 ( spi_sdi0 ),
.spi_sdi1 ( spi_sdi1 ),
.spi_sdi2 ( spi_sdi2 ),
.spi_sdi3 ( spi_sdi3 )
);
endmodule |
module spi_master_apb_if
#(
parameter BUFFER_DEPTH = 10,
parameter APB_ADDR_WIDTH = 12, //APB slaves are 4KB by default
parameter LOG_BUFFER_DEPTH = `log2(BUFFER_DEPTH)
)
(
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output reg [7:0] spi_clk_div,
output reg spi_clk_div_valid,
input wire [31:0] spi_status,
output reg [31:0] spi_addr,
output reg [5:0] spi_addr_len,
output reg [31:0] spi_cmd,
output reg [5:0] spi_cmd_len,
output reg [3:0] spi_csreg,
output reg [15:0] spi_data_len,
output reg [15:0] spi_dummy_rd,
output reg [15:0] spi_dummy_wr,
output reg [LOG_BUFFER_DEPTH:0] spi_int_th_tx,
output reg [LOG_BUFFER_DEPTH:0] spi_int_th_rx,
output reg spi_int_en,
input wire [31:0] spi_int_status,
output reg spi_swrst,
output reg spi_rd,
output reg spi_wr,
output reg spi_qrd,
output reg spi_qwr,
output wire [31:0] spi_data_tx,
output wire spi_data_tx_valid,
input wire spi_data_tx_ready,
input wire [31:0] spi_data_rx,
input wire spi_data_rx_valid,
output wire spi_data_rx_ready
);
wire [3:0] write_address;
wire [3:0] read_address;
assign write_address = PADDR[5:2];
assign read_address = PADDR[5:2];
assign PSLVERR = 1'b0;
assign PREADY = 1'b1;
always @(posedge HCLK or negedge HRESETn) begin
if (HRESETn == 1'b0) begin
spi_swrst <= 1'b0;
spi_rd <= 1'b0;
spi_wr <= 1'b0;
spi_qrd <= 1'b0;
spi_qwr <= 1'b0;
spi_clk_div_valid <= 1'b0;
spi_clk_div <= 'b0;
spi_cmd <= 'b0;
spi_addr <= 'b0;
spi_cmd_len <= 'b0;
spi_addr_len <= 'b0;
spi_data_len <= 'b0;
spi_dummy_rd <= 'b0;
spi_dummy_wr <= 'b0;
spi_csreg <= 'b0;
spi_int_th_tx <= 'b0;
spi_int_th_rx <= 'b0;
spi_int_en <= 1'b0;
end else if (PSEL && PENABLE && PWRITE) begin
spi_swrst <= 1'b0;
spi_rd <= 1'b0;
spi_wr <= 1'b0;
spi_qrd <= 1'b0;
spi_qwr <= 1'b0;
spi_clk_div_valid <= 1'b0;
case (write_address)
`REG_STATUS: begin
spi_rd <= PWDATA[0];
spi_wr <= PWDATA[1];
spi_qrd <= PWDATA[2];
spi_qwr <= PWDATA[3];
spi_swrst <= PWDATA[4];
spi_csreg <= PWDATA[11:8];
end
`REG_CLKDIV: begin
spi_clk_div <= PWDATA[7:0];
spi_clk_div_valid <= 1'b1;
end
`REG_SPICMD: spi_cmd <= PWDATA;
`REG_SPIADR: spi_addr <= PWDATA;
`REG_SPILEN: begin
spi_cmd_len <= PWDATA[5:0];
spi_addr_len <= PWDATA[13:8];
spi_data_len[7:0] <= PWDATA[23:16];
spi_data_len[15:8] <= PWDATA[31:24];
end
`REG_SPIDUM: begin
spi_dummy_rd[7:0] <= PWDATA[7:0];
spi_dummy_rd[15:8] <= PWDATA[15:8];
spi_dummy_wr[7:0] <= PWDATA[23:16];
spi_dummy_wr[15:8] <= PWDATA[31:24];
end
`REG_INTCFG: begin
spi_int_th_tx <= PWDATA[LOG_BUFFER_DEPTH:0];
spi_int_th_rx <= PWDATA[8 + LOG_BUFFER_DEPTH:8];
spi_int_en <= PWDATA[31];
end
endcase
end else begin
spi_swrst <= 1'b0;
spi_rd <= 1'b0;
spi_wr <= 1'b0;
spi_qrd <= 1'b0;
spi_qwr <= 1'b0;
spi_clk_div_valid <= 1'b0;
end
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @(*) begin
case (read_address)
`REG_STATUS: PRDATA = spi_status;
`REG_CLKDIV: PRDATA = {24'h0, spi_clk_div};
`REG_SPICMD: PRDATA = spi_cmd;
`REG_SPIADR: PRDATA = spi_addr;
`REG_SPILEN: PRDATA = {spi_data_len, 2'b00, spi_addr_len, 2'b00, spi_cmd_len};
`REG_SPIDUM: PRDATA = {spi_dummy_wr, spi_dummy_rd};
`REG_RXFIFO: PRDATA = spi_data_rx;
`REG_INTCFG: begin
PRDATA = 'b0;
PRDATA[LOG_BUFFER_DEPTH:0] = spi_int_th_tx;
PRDATA[8 + LOG_BUFFER_DEPTH:8] = spi_int_th_rx;
PRDATA[31] = spi_int_en;
end
`REG_INTSTA: PRDATA = spi_int_status;
default: PRDATA = 'b0;
endcase
end // SLAVE_REG_READ_PROC
assign spi_data_tx = PWDATA;
assign spi_data_tx_valid = ((PSEL & PENABLE) & PWRITE) & (write_address == `REG_TXFIFO);
assign spi_data_rx_ready = ((PSEL & PENABLE) & ~PWRITE) & (read_address == `REG_RXFIFO);
endmodule |
module spi_master_controller (
input wire clk,
input wire rstn,
output reg eot,
input wire [7:0] spi_clk_div,
input wire spi_clk_div_valid,
output reg [6:0] spi_status,
input wire [31:0] spi_addr,
input wire [5:0] spi_addr_len,
input wire [31:0] spi_cmd,
input wire [5:0] spi_cmd_len,
input wire [15:0] spi_data_len,
input wire [15:0] spi_dummy_rd,
input wire [15:0] spi_dummy_wr,
input wire [3:0] spi_csreg,
input wire spi_swrst, //FIXME Not used at all
input wire spi_rd,
input wire spi_wr,
input wire spi_qrd,
input wire spi_qwr,
input wire [31:0] spi_ctrl_data_tx,
input wire spi_ctrl_data_tx_valid,
output reg spi_ctrl_data_tx_ready,
output wire [31:0] spi_ctrl_data_rx,
output wire spi_ctrl_data_rx_valid,
input wire spi_ctrl_data_rx_ready,
output wire spi_clk,
output wire spi_csn0,
output wire spi_csn1,
output wire spi_csn2,
output wire spi_csn3,
output reg [1:0] spi_mode,
output wire spi_sdo0,
output wire spi_sdo1,
output wire spi_sdo2,
output wire spi_sdo3,
input wire spi_sdi0,
input wire spi_sdi1,
input wire spi_sdi2,
input wire spi_sdi3
);
localparam [2:0] DATA_NULL = 0;
localparam [2:0] DATA_EMPTY = 1;
localparam [2:0] DATA_CMD = 2;
localparam [2:0] DATA_ADDR = 3;
localparam [2:0] DATA_FIFO = 4;
localparam [4:0] IDLE = 0;
localparam [4:0] CMD = 1;
localparam [4:0] ADDR = 2;
localparam [4:0] MODE = 3;
localparam [4:0] DUMMY = 4;
localparam [4:0] DATA_TX = 5;
localparam [4:0] DATA_RX = 6;
localparam [4:0] WAIT_EDGE = 7;
wire spi_rise;
wire spi_fall;
reg spi_clock_en;
reg spi_en_tx;
reg spi_en_rx;
reg [15:0] counter_tx;
reg counter_tx_valid;
reg [15:0] counter_rx;
reg counter_rx_valid;
reg [31:0] data_to_tx;
reg data_to_tx_valid;
wire data_to_tx_ready;
wire en_quad;
reg en_quad_int;
reg do_tx; //FIXME NOT USED at all!!
reg do_rx;
wire tx_done;
wire rx_done;
reg [1:0] s_spi_mode;
reg ctrl_data_valid;
reg spi_cs;
wire tx_clk_en;
wire rx_clk_en;
reg [2:0] ctrl_data_mux;
reg [4:0] state;
reg [4:0] state_next;
assign en_quad = (spi_qrd | spi_qwr) | en_quad_int;
spi_master_clkgen u_clkgen
(
.clk ( clk ),
.rstn ( rstn ),
.en ( spi_clock_en ),
.clk_div ( spi_clk_div ),
.clk_div_valid ( spi_clk_div_valid ),
.spi_clk ( spi_clk ),
.spi_fall ( spi_fall ),
.spi_rise ( spi_rise )
);
spi_master_tx u_txreg
(
.clk ( clk ),
.rstn ( rstn ),
.en ( spi_en_tx ),
.tx_edge ( spi_fall ),
.tx_done ( tx_done ),
.sdo0 ( spi_sdo0 ),
.sdo1 ( spi_sdo1 ),
.sdo2 ( spi_sdo2 ),
.sdo3 ( spi_sdo3 ),
.en_quad_in ( en_quad ),
.counter_in ( counter_tx ),
.counter_in_upd ( counter_tx_valid ),
.data ( data_to_tx ),
.data_valid ( data_to_tx_valid ),
.data_ready ( data_to_tx_ready ),
.clk_en_o ( tx_clk_en )
);
spi_master_rx u_rxreg
(
.clk ( clk ),
.rstn ( rstn ),
.en ( spi_en_rx ),
.rx_edge ( spi_rise ),
.rx_done ( rx_done ),
.sdi0 ( spi_sdi0 ),
.sdi1 ( spi_sdi1 ),
.sdi2 ( spi_sdi2 ),
.sdi3 ( spi_sdi3 ),
.en_quad_in ( en_quad ),
.counter_in ( counter_rx ),
.counter_in_upd ( counter_rx_valid ),
.data ( spi_ctrl_data_rx ),
.data_valid ( spi_ctrl_data_rx_valid ),
.data_ready ( spi_ctrl_data_rx_ready ),
.clk_en_o ( rx_clk_en )
);
always @(*) begin
data_to_tx = 'h0;
data_to_tx_valid = 1'b0;
spi_ctrl_data_tx_ready = 1'b0;
case (ctrl_data_mux)
DATA_NULL: begin
data_to_tx = 'b0;
data_to_tx_valid = 1'b0;
spi_ctrl_data_tx_ready = 1'b0;
end
DATA_EMPTY: begin
data_to_tx = 'b0;
data_to_tx_valid = 1'b1;
end
DATA_CMD: begin
data_to_tx = spi_cmd;
data_to_tx_valid = ctrl_data_valid;
spi_ctrl_data_tx_ready = 1'b0;
end
DATA_ADDR: begin
data_to_tx = spi_addr;
data_to_tx_valid = ctrl_data_valid;
spi_ctrl_data_tx_ready = 1'b0;
end
DATA_FIFO: begin
data_to_tx = spi_ctrl_data_tx;
data_to_tx_valid = spi_ctrl_data_tx_valid;
spi_ctrl_data_tx_ready = data_to_tx_ready;
end
endcase
end
always @(*) begin
spi_cs = 1'b1;
spi_clock_en = 1'b0;
counter_tx = 'b0;
counter_tx_valid = 1'b0;
counter_rx = 'b0;
counter_rx_valid = 1'b0;
state_next = state;
ctrl_data_mux = DATA_NULL;
ctrl_data_valid = 1'b0;
spi_en_rx = 1'b0;
spi_en_tx = 1'b0;
spi_status = 'b0;
s_spi_mode = `SPI_QUAD_RX;
eot = 1'b0;
case (state)
IDLE: begin
spi_status[0] = 1'b1;
s_spi_mode = `SPI_QUAD_RX;
if (spi_rd || spi_wr || spi_qrd || spi_qwr) begin
spi_cs = 1'b0;
spi_clock_en = 1'b1;
if (spi_cmd_len != 0) begin
s_spi_mode = (spi_qrd | spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
counter_tx = {8'h00, spi_cmd_len};
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_CMD;
ctrl_data_valid = 1'b1;
spi_en_tx = 1'b1;
state_next = CMD;
end else if (spi_addr_len != 0) begin
s_spi_mode = (spi_qrd | spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
counter_tx = {8'h00, spi_addr_len};
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_ADDR;
ctrl_data_valid = 1'b1;
spi_en_tx = 1'b1;
state_next = ADDR;
end else if (spi_data_len != 0)
if (spi_rd || spi_qrd) begin
s_spi_mode = (spi_qrd) ? `SPI_QUAD_RX : `SPI_STD;
if (spi_dummy_rd != 0) begin
counter_tx = (en_quad) ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd;
counter_tx_valid = 1'b1;
spi_en_tx = 1'b1;
ctrl_data_mux = DATA_EMPTY;
state_next = DUMMY;
end else begin
counter_rx = spi_data_len;
counter_rx_valid = 1'b1;
spi_en_rx = 1'b1;
state_next = DATA_RX;
end
end else begin
s_spi_mode = (spi_qwr) ? `SPI_QUAD_TX : `SPI_STD;
if (spi_dummy_wr != 0) begin
counter_tx = (en_quad) ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_EMPTY;
spi_en_tx = 1'b1;
state_next = DUMMY;
end else begin
counter_tx = spi_data_len;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_FIFO;
ctrl_data_valid = 1'b0;
spi_en_tx = 1'b1;
state_next = DATA_TX;
end
end
end else begin
spi_cs = 1'b1;
state_next = IDLE;
end
end
CMD: begin
spi_status[1] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = 1'b1;
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
if (tx_done) begin
if (spi_addr_len != 0) begin
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
counter_tx = {8'h00, spi_addr_len};
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_ADDR;
ctrl_data_valid = 1'b1;
spi_en_tx = 1'b1;
state_next = ADDR;
end else if (spi_data_len != 0) begin
if (do_rx) begin
s_spi_mode = (en_quad) ? `SPI_QUAD_RX : `SPI_STD;
if (spi_dummy_rd != 0) begin
counter_tx = (en_quad) ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd;
counter_tx_valid = 1'b1;
spi_en_tx = 1'b1;
ctrl_data_mux = DATA_EMPTY;
state_next = DUMMY;
end else begin
counter_rx = spi_data_len;
counter_rx_valid = 1'b1;
spi_en_rx = 1'b1;
state_next = DATA_RX;
end
end else begin
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
if (spi_dummy_wr != 0) begin
counter_tx = (en_quad) ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_EMPTY;
spi_en_tx = 1'b1;
state_next = DUMMY;
end else begin
counter_tx = spi_data_len;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_FIFO;
ctrl_data_valid = 1'b1;
spi_en_tx = 1'b1;
state_next = DATA_TX;
end
end
end else begin
state_next = IDLE;
end
end else begin
spi_en_tx = 1'b1;
state_next = CMD;
end
end
ADDR: begin
spi_en_tx = 1'b1;
spi_status[2] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = 1'b1;
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
if (tx_done) begin
if (spi_data_len != 0) begin
if (do_rx) begin
s_spi_mode = (en_quad) ? `SPI_QUAD_RX : `SPI_STD;
if (spi_dummy_rd != 0) begin
counter_tx = (en_quad) ? {spi_dummy_rd[13:0], 2'b00} : spi_dummy_rd;
counter_tx_valid = 1'b1;
spi_en_tx = 1'b1;
ctrl_data_mux = DATA_EMPTY;
state_next = DUMMY;
end else begin
counter_rx = spi_data_len;
counter_rx_valid = 1'b1;
spi_en_rx = 1'b1;
state_next = DATA_RX;
end
end else begin
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
spi_en_tx = 1'b1;
if (spi_dummy_wr != 0) begin
counter_tx = (en_quad) ? {spi_dummy_wr[13:0], 2'b00} : spi_dummy_wr;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_EMPTY;
state_next = DUMMY;
end else begin
counter_tx = spi_data_len;
counter_tx_valid = 1'b1;
ctrl_data_mux = DATA_FIFO;
ctrl_data_valid = 1'b1;
state_next = DATA_TX;
end
end
end else begin
state_next = IDLE;
end
end
end
MODE: begin
spi_status[3] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = 1'b1;
spi_en_tx = 1'b1;
end
DUMMY: begin
spi_en_tx = 1'b1;
spi_status[4] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = 1'b1;
s_spi_mode = (en_quad) ? `SPI_QUAD_RX : `SPI_STD;
if (tx_done) begin
if (spi_data_len != 0) begin
if (do_rx) begin
counter_rx = spi_data_len;
counter_rx_valid = 1'b1;
spi_en_rx = 1'b1;
state_next = DATA_RX;
end else begin
counter_tx = spi_data_len;
counter_tx_valid = 1'b1;
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
spi_clock_en = tx_clk_en;
spi_en_tx = 1'b1;
state_next = DATA_TX;
end
end else begin
eot = 1'b1;
state_next = IDLE;
end
end else begin
ctrl_data_mux = DATA_EMPTY;
spi_en_tx = 1'b1;
state_next = DUMMY;
end
end
DATA_TX: begin
spi_status[5] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = tx_clk_en;
ctrl_data_mux = DATA_FIFO;
ctrl_data_valid = 1'b1;
spi_en_tx = 1'b1;
s_spi_mode = (en_quad) ? `SPI_QUAD_TX : `SPI_STD;
if (tx_done) begin
eot = 1'b1;
state_next = IDLE;
spi_clock_en = 1'b0;
end else begin
state_next = DATA_TX;
end
end
DATA_RX: begin
spi_status[6] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = rx_clk_en;
s_spi_mode = (en_quad) ? `SPI_QUAD_RX : `SPI_STD;
if (rx_done) begin
state_next = WAIT_EDGE;
end else begin
spi_en_rx = 1'b1;
state_next = DATA_RX;
end
end
WAIT_EDGE: begin
spi_status[6] = 1'b1;
spi_cs = 1'b0;
spi_clock_en = 1'b0;
s_spi_mode = (en_quad) ? `SPI_QUAD_RX : `SPI_STD;
if (spi_fall) begin
eot = 1'b1;
state_next = IDLE;
end else begin
state_next = WAIT_EDGE;
end
end
endcase
end
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
state <= IDLE;
en_quad_int <= 1'b0;
do_rx <= 1'b0;
do_tx <= 1'b0;
spi_mode <= `SPI_QUAD_RX;
end else begin
state <= state_next;
spi_mode <= s_spi_mode;
if (spi_qrd || spi_qwr)
en_quad_int <= 1'b1;
else if (state_next == IDLE)
en_quad_int <= 1'b0;
if (spi_rd || spi_qrd) begin
do_rx <= 1'b1;
do_tx <= 1'b0;
end else if (spi_wr || spi_qwr) begin
do_rx <= 1'b0;
do_tx <= 1'b1;
end else if (state_next == IDLE) begin
do_rx <= 1'b0;
do_tx <= 1'b0;
end
end
end
assign spi_csn0 = ~spi_csreg[0] | spi_cs;
assign spi_csn1 = ~spi_csreg[1] | spi_cs;
assign spi_csn2 = ~spi_csreg[2] | spi_cs;
assign spi_csn3 = ~spi_csreg[3] | spi_cs;
endmodule |
module spi_master_rx (
input wire clk,
input wire rstn,
input wire en,
input wire rx_edge,
output wire rx_done,
input wire sdi0,
input wire sdi1,
input wire sdi2,
input wire sdi3,
input wire en_quad_in,
input wire [15:0] counter_in,
input wire counter_in_upd,
output wire [31:0] data,
input wire data_ready,
output reg data_valid,
output reg clk_en_o
);
localparam [1:0] IDLE = 0;
localparam [1:0] RECEIVE = 1;
localparam [1:0] WAIT_FIFO = 2;
localparam [1:0] WAIT_FIFO_DONE = 3;
reg [31:0] data_int;
reg [31:0] data_int_next;
reg [15:0] counter;
reg [15:0] counter_trgt;
reg [15:0] counter_next;
reg [15:0] counter_trgt_next;
wire done;
wire reg_done;
reg [1:0] rx_CS;
reg [1:0] rx_NS;
assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
assign data = data_int_next;
assign rx_done = done;
always @(*) begin
if (counter_in_upd)
counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in);
else
counter_trgt_next = counter_trgt;
end
assign done = (counter == (counter_trgt - 1)) && rx_edge;
always @(*) begin
rx_NS = rx_CS;
clk_en_o = 1'b0;
data_int_next = data_int;
data_valid = 1'b0;
counter_next = counter;
case (rx_CS)
IDLE: begin
clk_en_o = 1'b0;
// check first if there is available space instead of later
if (en) rx_NS = RECEIVE;
end
RECEIVE: begin
clk_en_o = 1'b1;
if (rx_edge) begin
counter_next = counter + 1;
if (en_quad_in)
data_int_next = {data_int[27:0], sdi3, sdi2, sdi1, sdi0};
else
data_int_next = {data_int[30:0], sdi1};
if (rx_done) begin
counter_next = 0;
data_valid = 1'b1;
if (data_ready)
rx_NS = IDLE;
else
rx_NS = WAIT_FIFO_DONE;
end else if (reg_done) begin
data_valid = 1'b1;
if (~data_ready) begin
// no space in the FIFO, wait for free space
clk_en_o = 1'b0;
rx_NS = WAIT_FIFO;
end
end
end
end
WAIT_FIFO_DONE: begin
data_valid = 1'b1;
if (data_ready) rx_NS = IDLE;
end
WAIT_FIFO: begin
data_valid = 1'b1;
if (data_ready) rx_NS = RECEIVE;
end
endcase
end
always @(posedge clk or negedge rstn) begin
if (rstn == 0) begin
counter <= 0;
counter_trgt <= 'h8;
data_int <= 'b0;
rx_CS <= IDLE;
end else begin
counter <= counter_next;
counter_trgt <= counter_trgt_next;
data_int <= data_int_next;
rx_CS <= rx_NS;
end
end
endmodule |
module spi_master_tx (
input wire clk,
input wire rstn,
input wire en,
input wire tx_edge,
output wire tx_done,
output wire sdo0,
output wire sdo1,
output wire sdo2,
output wire sdo3,
input wire en_quad_in,
input wire [15:0] counter_in,
input wire counter_in_upd,
input wire [31:0] data,
input wire data_valid,
output reg data_ready,
output reg clk_en_o
);
localparam [0:0] IDLE = 0;
localparam [0:0] TRANSMIT = 1;
reg [31:0] data_int;
reg [31:0] data_int_next;
reg [15:0] counter;
reg [15:0] counter_trgt;
reg [15:0] counter_next;
reg [15:0] counter_trgt_next;
wire done;
wire reg_done;
reg [0:0] tx_CS;
reg [0:0] tx_NS;
assign sdo0 = (en_quad_in ? data_int[28] : data_int[31]);
assign sdo1 = data_int[29];
assign sdo2 = data_int[30];
assign sdo3 = data_int[31];
assign tx_done = done;
assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
always @(*) begin
if (counter_in_upd)
counter_trgt_next = (en_quad_in ? {2'b00, counter_in[15:2]} : counter_in);
else
counter_trgt_next = counter_trgt;
end
assign done = (counter == (counter_trgt - 1)) && tx_edge;
always @(*) begin
tx_NS = tx_CS;
clk_en_o = 1'b0;
data_int_next = data_int;
data_ready = 1'b0;
counter_next = counter;
case (tx_CS)
IDLE: begin
clk_en_o = 1'b0;
if (en && data_valid) begin
data_int_next = data;
data_ready = 1'b1;
tx_NS = TRANSMIT;
end
end
TRANSMIT: begin
clk_en_o = 1'b1;
if (tx_edge) begin
counter_next = counter + 1;
data_int_next = (en_quad_in ? {data_int[27:0], 4'b0000} : {data_int[30:0], 1'b0});
if (tx_done) begin
counter_next = 0;
if (en && data_valid) begin
data_int_next = data;
data_ready = 1'b1;
tx_NS = TRANSMIT;
end else begin
clk_en_o = 1'b0;
tx_NS = IDLE;
end
end else if (reg_done) begin
if (data_valid) begin
data_int_next = data;
data_ready = 1'b1;
end else begin
clk_en_o = 1'b0;
tx_NS = IDLE;
end
end
end
end
endcase
end
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
counter <= 0;
counter_trgt <= 'h8;
data_int <= 'h0;
tx_CS <= IDLE;
end else begin
counter <= counter_next;
counter_trgt <= counter_trgt_next;
data_int <= data_int_next;
tx_CS <= tx_NS;
end
end
endmodule |
module spi_master_clkgen (
input wire clk,
input wire rstn,
input wire en,
input wire [7:0] clk_div,
input wire clk_div_valid,
output reg spi_clk,
output reg spi_fall,
output reg spi_rise
);
reg [7:0] counter_trgt;
reg [7:0] counter_trgt_next;
reg [7:0] counter;
reg [7:0] counter_next;
reg spi_clk_next;
reg running;
always @(*) begin
spi_rise = 1'b0;
spi_fall = 1'b0;
if (clk_div_valid)
counter_trgt_next = clk_div;
else
counter_trgt_next = counter_trgt;
if (counter == counter_trgt) begin
counter_next = 0;
spi_clk_next = ~spi_clk;
if (spi_clk == 1'b0)
spi_rise = running;
else
spi_fall = running;
end else begin
counter_next = counter + 1;
spi_clk_next = spi_clk;
end
end
always @(posedge clk or negedge rstn) begin
if (rstn == 1'b0) begin
counter_trgt <= 'h0;
counter <= 'h0;
spi_clk <= 1'b0;
running <= 1'b0;
end else begin
counter_trgt <= counter_trgt_next;
if (!((spi_clk == 1'b0) && ~en)) begin
running <= 1'b1;
spi_clk <= spi_clk_next;
counter <= counter_next;
end else
running <= 1'b0;
end
end
endmodule |
module timer_cntrl (
input wire clk_i,
input wire rstn_i,
input wire cfg_start_i,
input wire cfg_stop_i,
input wire cfg_rst_i,
input wire cfg_update_i,
input wire cfg_arm_i,
output reg ctrl_cnt_upd_o,
output reg ctrl_all_upd_o,
output wire ctrl_active_o,
output reg ctrl_rst_o,
output wire ctrl_arm_o,
input wire cnt_update_i,
output wire [7:0] status_o
);
reg r_active;
reg r_pending;
assign ctrl_arm_o = cfg_arm_i;
assign status_o = {6'h00, r_pending};
assign ctrl_active_o = r_active;
always @(*) begin : proc_sm
if (cfg_start_i && !r_active) begin
ctrl_rst_o = 1'b1;
ctrl_cnt_upd_o = 1'b1;
ctrl_all_upd_o = 1'b1;
end else begin
ctrl_rst_o = cfg_rst_i;
ctrl_cnt_upd_o = cfg_update_i;
ctrl_all_upd_o = cnt_update_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_active
if (~rstn_i) begin
r_active <= 0;
r_pending <= 0;
end else begin
if (cfg_start_i)
r_active <= 1;
else if (cfg_stop_i)
r_active <= 0;
if (cnt_update_i && !cfg_update_i)
r_pending <= 0;
else if (cfg_update_i)
r_pending <= 1;
end
end
endmodule |
module adv_timer_apb_if #(
parameter APB_ADDR_WIDTH = 12
) (
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output wire [3:0] events_en_o,
output wire [3:0] events_sel_0_o,
output wire [3:0] events_sel_1_o,
output wire [3:0] events_sel_2_o,
output wire [3:0] events_sel_3_o,
input wire [15:0] timer0_counter_i,
input wire [15:0] timer1_counter_i,
input wire [15:0] timer2_counter_i,
input wire [15:0] timer3_counter_i,
output wire timer0_start_o,
output wire timer0_stop_o,
output wire timer0_update_o,
output wire timer0_arm_o,
output wire timer0_rst_o,
output wire timer0_saw_o,
output wire [2:0] timer0_in_mode_o,
output wire [7:0] timer0_in_sel_o,
output wire timer0_in_clk_o,
output wire [7:0] timer0_presc_o,
output wire [15:0] timer0_th_hi_o,
output wire [15:0] timer0_th_low_o,
output wire [2:0] timer0_ch0_mode_o,
output wire [1:0] timer0_ch0_flt_o,
output wire [15:0] timer0_ch0_th_o,
output wire [15:0] timer0_ch0_lut_o,
output wire [2:0] timer0_ch1_mode_o,
output wire [1:0] timer0_ch1_flt_o,
output wire [15:0] timer0_ch1_th_o,
output wire [15:0] timer0_ch1_lut_o,
output wire [2:0] timer0_ch2_mode_o,
output wire [1:0] timer0_ch2_flt_o,
output wire [15:0] timer0_ch2_th_o,
output wire [15:0] timer0_ch2_lut_o,
output wire [2:0] timer0_ch3_mode_o,
output wire [1:0] timer0_ch3_flt_o,
output wire [15:0] timer0_ch3_th_o,
output wire [15:0] timer0_ch3_lut_o,
output wire timer1_start_o,
output wire timer1_stop_o,
output wire timer1_update_o,
output wire timer1_arm_o,
output wire timer1_rst_o,
output wire timer1_saw_o,
output wire [2:0] timer1_in_mode_o,
output wire [7:0] timer1_in_sel_o,
output wire timer1_in_clk_o,
output wire [7:0] timer1_presc_o,
output wire [15:0] timer1_th_hi_o,
output wire [15:0] timer1_th_low_o,
output wire [2:0] timer1_ch0_mode_o,
output wire [1:0] timer1_ch0_flt_o,
output wire [15:0] timer1_ch0_th_o,
output wire [15:0] timer1_ch0_lut_o,
output wire [2:0] timer1_ch1_mode_o,
output wire [1:0] timer1_ch1_flt_o,
output wire [15:0] timer1_ch1_th_o,
output wire [15:0] timer1_ch1_lut_o,
output wire [2:0] timer1_ch2_mode_o,
output wire [1:0] timer1_ch2_flt_o,
output wire [15:0] timer1_ch2_th_o,
output wire [15:0] timer1_ch2_lut_o,
output wire [2:0] timer1_ch3_mode_o,
output wire [1:0] timer1_ch3_flt_o,
output wire [15:0] timer1_ch3_th_o,
output wire [15:0] timer1_ch3_lut_o,
output wire timer2_start_o,
output wire timer2_stop_o,
output wire timer2_update_o,
output wire timer2_arm_o,
output wire timer2_rst_o,
output wire timer2_saw_o,
output wire [2:0] timer2_in_mode_o,
output wire [7:0] timer2_in_sel_o,
output wire timer2_in_clk_o,
output wire [7:0] timer2_presc_o,
output wire [15:0] timer2_th_hi_o,
output wire [15:0] timer2_th_low_o,
output wire [2:0] timer2_ch0_mode_o,
output wire [1:0] timer2_ch0_flt_o,
output wire [15:0] timer2_ch0_th_o,
output wire [15:0] timer2_ch0_lut_o,
output wire [2:0] timer2_ch1_mode_o,
output wire [1:0] timer2_ch1_flt_o,
output wire [15:0] timer2_ch1_th_o,
output wire [15:0] timer2_ch1_lut_o,
output wire [2:0] timer2_ch2_mode_o,
output wire [1:0] timer2_ch2_flt_o,
output wire [15:0] timer2_ch2_th_o,
output wire [15:0] timer2_ch2_lut_o,
output wire [2:0] timer2_ch3_mode_o,
output wire [1:0] timer2_ch3_flt_o,
output wire [15:0] timer2_ch3_th_o,
output wire [15:0] timer2_ch3_lut_o,
output wire timer3_start_o,
output wire timer3_stop_o,
output wire timer3_update_o,
output wire timer3_arm_o,
output wire timer3_rst_o,
output wire timer3_saw_o,
output wire [2:0] timer3_in_mode_o,
output wire [7:0] timer3_in_sel_o,
output wire timer3_in_clk_o,
output wire [7:0] timer3_presc_o,
output wire [15:0] timer3_th_hi_o,
output wire [15:0] timer3_th_low_o,
output wire [2:0] timer3_ch0_mode_o,
output wire [1:0] timer3_ch0_flt_o,
output wire [15:0] timer3_ch0_th_o,
output wire [15:0] timer3_ch0_lut_o,
output wire [2:0] timer3_ch1_mode_o,
output wire [1:0] timer3_ch1_flt_o,
output wire [15:0] timer3_ch1_th_o,
output wire [15:0] timer3_ch1_lut_o,
output wire [2:0] timer3_ch2_mode_o,
output wire [1:0] timer3_ch2_flt_o,
output wire [15:0] timer3_ch2_th_o,
output wire [15:0] timer3_ch2_lut_o,
output wire [2:0] timer3_ch3_mode_o,
output wire [1:0] timer3_ch3_flt_o,
output wire [15:0] timer3_ch3_th_o,
output wire [15:0] timer3_ch3_lut_o,
output wire timer0_clk_en_o,
output wire timer1_clk_en_o,
output wire timer2_clk_en_o,
output wire timer3_clk_en_o
);
wire s_timer1_apb_in_clk;
wire s_timer2_apb_in_clk;
wire s_timer3_apb_in_clk;
wire s_timer1_apb_start;
wire s_timer1_apb_stop;
wire s_timer2_apb_start;
wire s_timer2_apb_stop;
wire s_timer3_apb_start;
wire s_timer3_apb_stop;
reg [31:0] r_timer0_th;
reg [7:0] r_timer0_presc;
reg [7:0] r_timer0_in_sel;
reg r_timer0_in_clk;
reg [2:0] r_timer0_in_mode;
reg r_timer0_start;
reg r_timer0_stop;
reg r_timer0_update;
reg r_timer0_arm;
reg r_timer0_rst;
reg r_timer0_saw;
reg [15:0] r_timer0_ch0_th;
reg [2:0] r_timer0_ch0_mode;
reg [15:0] r_timer0_ch0_lut;
reg [1:0] r_timer0_ch0_flt;
reg [15:0] r_timer0_ch1_th;
reg [2:0] r_timer0_ch1_mode;
reg [15:0] r_timer0_ch1_lut;
reg [1:0] r_timer0_ch1_flt;
reg [15:0] r_timer0_ch2_th;
reg [2:0] r_timer0_ch2_mode;
reg [15:0] r_timer0_ch2_lut;
reg [1:0] r_timer0_ch2_flt;
reg [15:0] r_timer0_ch3_th;
reg [2:0] r_timer0_ch3_mode;
reg [15:0] r_timer0_ch3_lut;
reg [1:0] r_timer0_ch3_flt;
reg [31:0] r_timer1_th;
reg [7:0] r_timer1_presc;
reg [7:0] r_timer1_in_sel;
reg r_timer1_in_clk;
reg [2:0] r_timer1_in_mode;
reg r_timer1_start;
reg r_timer1_stop;
reg r_timer1_update;
reg r_timer1_arm;
reg r_timer1_rst;
reg r_timer1_saw;
reg [15:0] r_timer1_ch0_th;
reg [2:0] r_timer1_ch0_mode;
reg [15:0] r_timer1_ch0_lut;
reg [1:0] r_timer1_ch0_flt;
reg [15:0] r_timer1_ch1_th;
reg [2:0] r_timer1_ch1_mode;
reg [15:0] r_timer1_ch1_lut;
reg [1:0] r_timer1_ch1_flt;
reg [15:0] r_timer1_ch2_th;
reg [2:0] r_timer1_ch2_mode;
reg [15:0] r_timer1_ch2_lut;
reg [1:0] r_timer1_ch2_flt;
reg [15:0] r_timer1_ch3_th;
reg [2:0] r_timer1_ch3_mode;
reg [15:0] r_timer1_ch3_lut;
reg [1:0] r_timer1_ch3_flt;
reg [31:0] r_timer2_th;
reg [7:0] r_timer2_presc;
reg [7:0] r_timer2_in_sel;
reg r_timer2_in_clk;
reg [2:0] r_timer2_in_mode;
reg r_timer2_start;
reg r_timer2_stop;
reg r_timer2_update;
reg r_timer2_arm;
reg r_timer2_rst;
reg r_timer2_saw;
reg [15:0] r_timer2_ch0_th;
reg [2:0] r_timer2_ch0_mode;
reg [15:0] r_timer2_ch0_lut;
reg [1:0] r_timer2_ch0_flt;
reg [15:0] r_timer2_ch1_th;
reg [2:0] r_timer2_ch1_mode;
reg [15:0] r_timer2_ch1_lut;
reg [1:0] r_timer2_ch1_flt;
reg [15:0] r_timer2_ch2_th;
reg [2:0] r_timer2_ch2_mode;
reg [15:0] r_timer2_ch2_lut;
reg [1:0] r_timer2_ch2_flt;
reg [15:0] r_timer2_ch3_th;
reg [2:0] r_timer2_ch3_mode;
reg [15:0] r_timer2_ch3_lut;
reg [1:0] r_timer2_ch3_flt;
reg [31:0] r_timer3_th;
reg [7:0] r_timer3_presc;
reg [7:0] r_timer3_in_sel;
reg r_timer3_in_clk;
reg [2:0] r_timer3_in_mode;
reg r_timer3_start;
reg r_timer3_stop;
reg r_timer3_update;
reg r_timer3_arm;
reg r_timer3_rst;
reg r_timer3_saw;
reg [15:0] r_timer3_ch0_th;
reg [2:0] r_timer3_ch0_mode;
reg [15:0] r_timer3_ch0_lut;
reg [1:0] r_timer3_ch0_flt;
reg [15:0] r_timer3_ch1_th;
reg [2:0] r_timer3_ch1_mode;
reg [15:0] r_timer3_ch1_lut;
reg [1:0] r_timer3_ch1_flt;
reg [15:0] r_timer3_ch2_th;
reg [2:0] r_timer3_ch2_mode;
reg [15:0] r_timer3_ch2_lut;
reg [1:0] r_timer3_ch2_flt;
reg [15:0] r_timer3_ch3_th;
reg [2:0] r_timer3_ch3_mode;
reg [15:0] r_timer3_ch3_lut;
reg [1:0] r_timer3_ch3_flt;
reg [3:0] r_event_sel_0;
reg [3:0] r_event_sel_1;
reg [3:0] r_event_sel_2;
reg [3:0] r_event_sel_3;
reg [3:0] r_event_en;
reg [3:0] r_clk_en;
wire [7:0] s_apb_addr;
assign events_en_o = r_event_en;
assign events_sel_0_o = r_event_sel_0;
assign events_sel_1_o = r_event_sel_1;
assign events_sel_2_o = r_event_sel_2;
assign events_sel_3_o = r_event_sel_3;
assign timer0_start_o = r_timer0_start;
assign timer0_stop_o = r_timer0_stop;
assign timer0_update_o = r_timer0_update;
assign timer0_rst_o = r_timer0_rst;
assign timer0_arm_o = r_timer0_arm;
assign timer0_saw_o = r_timer0_saw;
assign timer0_in_mode_o = r_timer0_in_mode;
assign timer0_in_sel_o = r_timer0_in_sel;
assign timer0_in_clk_o = r_timer0_in_clk;
assign timer0_presc_o = r_timer0_presc;
assign timer0_th_hi_o = r_timer0_th[31:16];
assign timer0_th_low_o = r_timer0_th[15:0];
assign timer0_ch0_mode_o = r_timer0_ch0_mode;
assign timer0_ch0_flt_o = r_timer0_ch0_flt;
assign timer0_ch0_th_o = r_timer0_ch0_th;
assign timer0_ch0_lut_o = r_timer0_ch0_lut;
assign timer0_ch1_mode_o = r_timer0_ch1_mode;
assign timer0_ch1_flt_o = r_timer0_ch1_flt;
assign timer0_ch1_th_o = r_timer0_ch1_th;
assign timer0_ch1_lut_o = r_timer0_ch1_lut;
assign timer0_ch2_mode_o = r_timer0_ch2_mode;
assign timer0_ch2_flt_o = r_timer0_ch2_flt;
assign timer0_ch2_th_o = r_timer0_ch2_th;
assign timer0_ch2_lut_o = r_timer0_ch2_lut;
assign timer0_ch3_mode_o = r_timer0_ch3_mode;
assign timer0_ch3_flt_o = r_timer0_ch3_flt;
assign timer0_ch3_th_o = r_timer0_ch3_th;
assign timer0_ch3_lut_o = r_timer0_ch3_lut;
assign timer1_start_o = r_timer1_start;
assign timer1_stop_o = r_timer1_stop;
assign timer1_update_o = r_timer1_update;
assign timer1_rst_o = r_timer1_rst;
assign timer1_arm_o = r_timer1_arm;
assign timer1_saw_o = r_timer1_saw;
assign timer1_in_mode_o = r_timer1_in_mode;
assign timer1_in_sel_o = r_timer1_in_sel;
assign timer1_in_clk_o = r_timer1_in_clk;
assign timer1_presc_o = r_timer1_presc;
assign timer1_th_hi_o = r_timer1_th[31:16];
assign timer1_th_low_o = r_timer1_th[15:0];
assign timer1_ch0_mode_o = r_timer1_ch0_mode;
assign timer1_ch0_flt_o = r_timer1_ch0_flt;
assign timer1_ch0_th_o = r_timer1_ch0_th;
assign timer1_ch0_lut_o = r_timer1_ch0_lut;
assign timer1_ch1_mode_o = r_timer1_ch1_mode;
assign timer1_ch1_flt_o = r_timer1_ch1_flt;
assign timer1_ch1_th_o = r_timer1_ch1_th;
assign timer1_ch1_lut_o = r_timer1_ch1_lut;
assign timer1_ch2_mode_o = r_timer1_ch2_mode;
assign timer1_ch2_flt_o = r_timer1_ch2_flt;
assign timer1_ch2_th_o = r_timer1_ch2_th;
assign timer1_ch2_lut_o = r_timer1_ch2_lut;
assign timer1_ch3_mode_o = r_timer1_ch3_mode;
assign timer1_ch3_flt_o = r_timer1_ch3_flt;
assign timer1_ch3_th_o = r_timer1_ch3_th;
assign timer1_ch3_lut_o = r_timer1_ch3_lut;
assign timer2_start_o = r_timer2_start;
assign timer2_stop_o = r_timer2_stop;
assign timer2_update_o = r_timer2_update;
assign timer2_rst_o = r_timer2_rst;
assign timer2_arm_o = r_timer2_arm;
assign timer2_saw_o = r_timer2_saw;
assign timer2_in_mode_o = r_timer2_in_mode;
assign timer2_in_sel_o = r_timer2_in_sel;
assign timer2_in_clk_o = r_timer2_in_clk;
assign timer2_presc_o = r_timer2_presc;
assign timer2_th_hi_o = r_timer2_th[31:16];
assign timer2_th_low_o = r_timer2_th[15:0];
assign timer2_ch0_mode_o = r_timer2_ch0_mode;
assign timer2_ch0_flt_o = r_timer2_ch0_flt;
assign timer2_ch0_th_o = r_timer2_ch0_th;
assign timer2_ch0_lut_o = r_timer2_ch0_lut;
assign timer2_ch1_mode_o = r_timer2_ch1_mode;
assign timer2_ch1_flt_o = r_timer2_ch1_flt;
assign timer2_ch1_th_o = r_timer2_ch1_th;
assign timer2_ch1_lut_o = r_timer2_ch1_lut;
assign timer2_ch2_mode_o = r_timer2_ch2_mode;
assign timer2_ch2_flt_o = r_timer2_ch2_flt;
assign timer2_ch2_th_o = r_timer2_ch2_th;
assign timer2_ch2_lut_o = r_timer2_ch2_lut;
assign timer2_ch3_mode_o = r_timer2_ch3_mode;
assign timer2_ch3_flt_o = r_timer2_ch3_flt;
assign timer2_ch3_th_o = r_timer2_ch3_th;
assign timer2_ch3_lut_o = r_timer2_ch3_lut;
assign timer3_start_o = r_timer3_start;
assign timer3_stop_o = r_timer3_stop;
assign timer3_update_o = r_timer3_update;
assign timer3_rst_o = r_timer3_rst;
assign timer3_arm_o = r_timer3_arm;
assign timer3_saw_o = r_timer3_saw;
assign timer3_in_mode_o = r_timer3_in_mode;
assign timer3_in_sel_o = r_timer3_in_sel;
assign timer3_in_clk_o = r_timer3_in_clk;
assign timer3_presc_o = r_timer3_presc;
assign timer3_th_hi_o = r_timer3_th[31:16];
assign timer3_th_low_o = r_timer3_th[15:0];
assign timer3_ch0_mode_o = r_timer3_ch0_mode;
assign timer3_ch0_flt_o = r_timer3_ch0_flt;
assign timer3_ch0_th_o = r_timer3_ch0_th;
assign timer3_ch0_lut_o = r_timer3_ch0_lut;
assign timer3_ch1_mode_o = r_timer3_ch1_mode;
assign timer3_ch1_flt_o = r_timer3_ch1_flt;
assign timer3_ch1_th_o = r_timer3_ch1_th;
assign timer3_ch1_lut_o = r_timer3_ch1_lut;
assign timer3_ch2_mode_o = r_timer3_ch2_mode;
assign timer3_ch2_flt_o = r_timer3_ch2_flt;
assign timer3_ch2_th_o = r_timer3_ch2_th;
assign timer3_ch2_lut_o = r_timer3_ch2_lut;
assign timer3_ch3_mode_o = r_timer3_ch3_mode;
assign timer3_ch3_flt_o = r_timer3_ch3_flt;
assign timer3_ch3_th_o = r_timer3_ch3_th;
assign timer3_ch3_lut_o = r_timer3_ch3_lut;
assign timer0_clk_en_o = r_clk_en[0];
assign timer1_clk_en_o = r_clk_en[1];
assign timer2_clk_en_o = r_clk_en[2];
assign timer3_clk_en_o = r_clk_en[3];
assign s_apb_addr = PADDR[9:2];
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
r_timer0_th <= 'h0;
r_timer0_in_sel <= 'h0;
r_timer0_in_clk <= 'h0;
r_timer0_in_mode <= 'h0;
r_timer0_presc <= 'h0;
r_timer0_start <= 1'b0;
r_timer0_stop <= 1'b0;
r_timer0_update <= 1'b0;
r_timer0_arm <= 1'b0;
r_timer0_rst <= 1'b0;
r_timer0_saw <= 1'b1;
r_timer0_ch0_th <= 'h0;
r_timer0_ch0_mode <= 'h0;
r_timer0_ch0_lut <= 'h0;
r_timer0_ch0_flt <= 'h0;
r_timer0_ch1_th <= 'h0;
r_timer0_ch1_mode <= 'h0;
r_timer0_ch1_lut <= 'h0;
r_timer0_ch1_flt <= 'h0;
r_timer0_ch2_th <= 'h0;
r_timer0_ch2_mode <= 'h0;
r_timer0_ch2_lut <= 'h0;
r_timer0_ch2_flt <= 'h0;
r_timer0_ch3_th <= 'h0;
r_timer0_ch3_mode <= 'h0;
r_timer0_ch3_lut <= 'h0;
r_timer0_ch3_flt <= 'h0;
r_timer1_th <= 'h0;
r_timer1_in_sel <= 'h0;
r_timer1_in_clk <= 'h0;
r_timer1_in_mode <= 'h0;
r_timer1_presc <= 'h0;
r_timer1_start <= 1'b0;
r_timer1_stop <= 1'b0;
r_timer1_update <= 1'b0;
r_timer1_rst <= 1'b0;
r_timer1_arm <= 1'b0;
r_timer1_saw <= 1'b1;
r_timer1_ch0_th <= 'h0;
r_timer1_ch0_mode <= 'h0;
r_timer1_ch0_lut <= 'h0;
r_timer1_ch0_flt <= 'h0;
r_timer1_ch1_th <= 'h0;
r_timer1_ch1_mode <= 'h0;
r_timer1_ch1_lut <= 'h0;
r_timer1_ch1_flt <= 'h0;
r_timer1_ch2_th <= 'h0;
r_timer1_ch2_mode <= 'h0;
r_timer1_ch2_lut <= 'h0;
r_timer1_ch2_flt <= 'h0;
r_timer1_ch3_th <= 'h0;
r_timer1_ch3_mode <= 'h0;
r_timer1_ch3_lut <= 'h0;
r_timer1_ch3_flt <= 'h0;
r_timer2_th <= 'h0;
r_timer2_in_sel <= 'h0;
r_timer2_in_clk <= 'h0;
r_timer2_in_mode <= 'h0;
r_timer2_presc <= 'h0;
r_timer2_start <= 1'b0;
r_timer2_stop <= 1'b0;
r_timer2_update <= 1'b0;
r_timer2_rst <= 1'b0;
r_timer2_arm <= 1'b0;
r_timer2_saw <= 1'b1;
r_timer2_ch0_th <= 'h0;
r_timer2_ch0_mode <= 'h0;
r_timer2_ch0_lut <= 'h0;
r_timer2_ch0_flt <= 'h0;
r_timer2_ch1_th <= 'h0;
r_timer2_ch1_mode <= 'h0;
r_timer2_ch1_lut <= 'h0;
r_timer2_ch1_flt <= 'h0;
r_timer2_ch2_th <= 'h0;
r_timer2_ch2_mode <= 'h0;
r_timer2_ch2_lut <= 'h0;
r_timer2_ch2_flt <= 'h0;
r_timer2_ch3_th <= 'h0;
r_timer2_ch3_mode <= 'h0;
r_timer2_ch3_lut <= 'h0;
r_timer2_ch3_flt <= 'h0;
r_timer3_th <= 'h0;
r_timer3_in_sel <= 'h0;
r_timer3_in_clk <= 'h0;
r_timer3_in_mode <= 'h0;
r_timer3_presc <= 'h0;
r_timer3_start <= 1'b0;
r_timer3_stop <= 1'b0;
r_timer3_update <= 1'b0;
r_timer3_rst <= 1'b0;
r_timer3_arm <= 1'b0;
r_timer3_saw <= 1'b1;
r_timer3_ch0_th <= 'h0;
r_timer3_ch0_mode <= 'h0;
r_timer3_ch0_lut <= 'h0;
r_timer3_ch0_flt <= 'h0;
r_timer3_ch1_th <= 'h0;
r_timer3_ch1_mode <= 'h0;
r_timer3_ch1_lut <= 'h0;
r_timer3_ch1_flt <= 'h0;
r_timer3_ch2_th <= 'h0;
r_timer3_ch2_mode <= 'h0;
r_timer3_ch2_lut <= 'h0;
r_timer3_ch2_flt <= 'h0;
r_timer3_ch3_th <= 'h0;
r_timer3_ch3_mode <= 'h0;
r_timer3_ch3_lut <= 'h0;
r_timer3_ch3_flt <= 'h0;
r_event_sel_0 <= 'h0;
r_event_sel_1 <= 'h0;
r_event_sel_2 <= 'h0;
r_event_sel_3 <= 'h0;
r_event_en <= 'h0;
r_clk_en <= 'h0;
end else if ((PSEL && PENABLE) && PWRITE) begin
case (s_apb_addr)
`REG_TIM0_TH:
r_timer0_th <= PWDATA;
`REG_TIM0_CMD:
begin
r_timer0_start <= PWDATA[0];
r_timer0_stop <= PWDATA[1];
r_timer0_update <= PWDATA[2];
r_timer0_rst <= PWDATA[3];
r_timer0_arm <= PWDATA[4];
end
`REG_TIM0_CFG:
begin
r_timer0_in_sel <= PWDATA[7:0];
r_timer0_in_mode<= PWDATA[10:8];
r_timer0_in_clk <= PWDATA[11];
r_timer0_saw <= PWDATA[12];
r_timer0_presc <= PWDATA[23:16];
end
`REG_TIM0_CH0_TH:
begin
r_timer0_ch0_th <= PWDATA[15:0];
r_timer0_ch0_mode <= PWDATA[18:16];
end
`REG_TIM0_CH0_LUT:
begin
r_timer0_ch0_lut <= PWDATA[15:0];
r_timer0_ch0_flt <= PWDATA[17:16];
end
`REG_TIM0_CH1_TH:
begin
r_timer0_ch1_th <= PWDATA[15:0];
r_timer0_ch1_mode <= PWDATA[18:16];
end
`REG_TIM0_CH1_LUT:
begin
r_timer0_ch1_lut <= PWDATA[15:0];
r_timer0_ch1_flt <= PWDATA[17:16];
end
`REG_TIM0_CH2_TH:
begin
r_timer0_ch2_th <= PWDATA[15:0];
r_timer0_ch2_mode <= PWDATA[18:16];
end
`REG_TIM0_CH2_LUT:
begin
r_timer0_ch2_lut <= PWDATA[15:0];
r_timer0_ch2_flt <= PWDATA[17:16];
end
`REG_TIM0_CH3_TH:
begin
r_timer0_ch3_th <= PWDATA[15:0];
r_timer0_ch3_mode <= PWDATA[18:16];
end
`REG_TIM0_CH3_LUT:
begin
r_timer0_ch3_lut <= PWDATA[15:0];
r_timer0_ch3_flt <= PWDATA[17:16];
end
`REG_TIM1_TH:
r_timer1_th <= PWDATA;
`REG_TIM1_CMD:
begin
r_timer1_start <= PWDATA[0];
r_timer1_stop <= PWDATA[1];
r_timer1_update <= PWDATA[2];
r_timer1_rst <= PWDATA[3];
r_timer1_arm <= PWDATA[4];
end
`REG_TIM1_CFG:
begin
r_timer1_in_sel <= PWDATA[7:0];
r_timer1_in_mode<= PWDATA[10:8];
r_timer1_in_clk <= PWDATA[11];
r_timer1_saw <= PWDATA[12];
r_timer1_presc <= PWDATA[23:16];
end
`REG_TIM1_CH0_TH:
begin
r_timer1_ch0_th <= PWDATA[15:0];
r_timer1_ch0_mode <= PWDATA[18:16];
end
`REG_TIM1_CH0_LUT:
begin
r_timer1_ch0_lut <= PWDATA[15:0];
r_timer1_ch0_flt <= PWDATA[17:16];
end
`REG_TIM1_CH1_TH:
begin
r_timer1_ch1_th <= PWDATA[15:0];
r_timer1_ch1_mode <= PWDATA[18:16];
end
`REG_TIM1_CH1_LUT:
begin
r_timer1_ch1_lut <= PWDATA[15:0];
r_timer1_ch1_flt <= PWDATA[17:16];
end
`REG_TIM1_CH2_TH:
begin
r_timer1_ch2_th <= PWDATA[15:0];
r_timer1_ch2_mode <= PWDATA[18:16];
end
`REG_TIM1_CH2_LUT:
begin
r_timer1_ch2_lut <= PWDATA[15:0];
r_timer1_ch2_flt <= PWDATA[17:16];
end
`REG_TIM1_CH3_TH:
begin
r_timer1_ch3_th <= PWDATA[15:0];
r_timer1_ch3_mode <= PWDATA[18:16];
end
`REG_TIM1_CH3_LUT:
begin
r_timer1_ch3_lut <= PWDATA[15:0];
r_timer1_ch3_flt <= PWDATA[17:16];
end
`REG_TIM2_TH:
r_timer2_th <= PWDATA;
`REG_TIM2_CMD:
begin
r_timer2_start <= PWDATA[0];
r_timer2_stop <= PWDATA[1];
r_timer2_update <= PWDATA[2];
r_timer2_rst <= PWDATA[3];
r_timer2_arm <= PWDATA[4];
end
`REG_TIM2_CFG:
begin
r_timer2_in_sel <= PWDATA[7:0];
r_timer2_in_mode<= PWDATA[10:8];
r_timer2_in_clk <= PWDATA[11];
r_timer2_saw <= PWDATA[12];
r_timer2_presc <= PWDATA[23:16];
end
`REG_TIM2_CH0_TH:
begin
r_timer2_ch0_th <= PWDATA[15:0];
r_timer2_ch0_mode <= PWDATA[18:16];
end
`REG_TIM2_CH0_LUT:
begin
r_timer2_ch0_lut <= PWDATA[15:0];
r_timer2_ch0_flt <= PWDATA[17:16];
end
`REG_TIM2_CH1_TH:
begin
r_timer2_ch1_th <= PWDATA[15:0];
r_timer2_ch1_mode <= PWDATA[18:16];
end
`REG_TIM2_CH1_LUT:
begin
r_timer2_ch1_lut <= PWDATA[15:0];
r_timer2_ch1_flt <= PWDATA[17:16];
end
`REG_TIM2_CH2_TH:
begin
r_timer2_ch2_th <= PWDATA[15:0];
r_timer2_ch2_mode <= PWDATA[18:16];
end
`REG_TIM2_CH2_LUT:
begin
r_timer2_ch2_lut <= PWDATA[15:0];
r_timer2_ch2_flt <= PWDATA[17:16];
end
`REG_TIM2_CH3_TH:
begin
r_timer2_ch3_th <= PWDATA[15:0];
r_timer2_ch3_mode <= PWDATA[18:16];
end
`REG_TIM2_CH3_LUT:
begin
r_timer2_ch3_lut <= PWDATA[15:0];
r_timer2_ch3_flt <= PWDATA[17:16];
end
`REG_TIM3_TH:
r_timer3_th <= PWDATA;
`REG_TIM3_CMD:
begin
r_timer3_start <= PWDATA[0];
r_timer3_stop <= PWDATA[1];
r_timer3_update <= PWDATA[2];
r_timer3_rst <= PWDATA[3];
r_timer3_arm <= PWDATA[4];
end
`REG_TIM3_CFG:
begin
r_timer3_in_sel <= PWDATA[7:0];
r_timer3_in_mode<= PWDATA[10:8];
r_timer3_in_clk <= PWDATA[11];
r_timer3_saw <= PWDATA[12];
r_timer3_presc <= PWDATA[23:16];
end
`REG_TIM3_CH0_TH:
begin
r_timer3_ch0_th <= PWDATA[15:0];
r_timer3_ch0_mode <= PWDATA[18:16];
end
`REG_TIM3_CH0_LUT:
begin
r_timer3_ch0_lut <= PWDATA[15:0];
r_timer3_ch0_flt <= PWDATA[17:16];
end
`REG_TIM3_CH1_TH:
begin
r_timer3_ch1_th <= PWDATA[15:0];
r_timer3_ch1_mode <= PWDATA[18:16];
end
`REG_TIM3_CH1_LUT:
begin
r_timer3_ch1_lut <= PWDATA[15:0];
r_timer3_ch1_flt <= PWDATA[17:16];
end
`REG_TIM3_CH2_TH:
begin
r_timer3_ch2_th <= PWDATA[15:0];
r_timer3_ch2_mode <= PWDATA[18:16];
end
`REG_TIM3_CH2_LUT:
begin
r_timer3_ch2_lut <= PWDATA[15:0];
r_timer3_ch2_flt <= PWDATA[17:16];
end
`REG_TIM3_CH3_TH:
begin
r_timer3_ch3_th <= PWDATA[15:0];
r_timer3_ch3_mode <= PWDATA[18:16];
end
`REG_TIM3_CH3_LUT:
begin
r_timer3_ch3_lut <= PWDATA[15:0];
r_timer3_ch3_flt <= PWDATA[17:16];
end
`REG_EVENT_CFG:
begin
r_event_sel_0 <= PWDATA[3:0];
r_event_sel_1 <= PWDATA[7:4];
r_event_sel_2 <= PWDATA[11:8];
r_event_sel_3 <= PWDATA[15:12];
r_event_en <= PWDATA[19:16];
end
`REG_CH_EN:
begin
r_clk_en <= PWDATA[3:0];
end
endcase // s_apb_addr
end else begin
r_timer0_start <= 1'b0;
r_timer0_stop <= 1'b0;
r_timer0_rst <= 1'b0;
r_timer0_update <= 1'b0;
r_timer0_arm <= 1'b0;
r_timer1_start <= 1'b0;
r_timer1_stop <= 1'b0;
r_timer1_rst <= 1'b0;
r_timer1_update <= 1'b0;
r_timer1_arm <= 1'b0;
r_timer2_start <= 1'b0;
r_timer2_stop <= 1'b0;
r_timer2_rst <= 1'b0;
r_timer2_update <= 1'b0;
r_timer2_arm <= 1'b0;
r_timer3_start <= 1'b0;
r_timer3_stop <= 1'b0;
r_timer3_rst <= 1'b0;
r_timer3_update <= 1'b0;
r_timer3_arm <= 1'b0;
end
end
always @(*) begin
case (s_apb_addr)
`REG_TIM0_TH:
PRDATA = r_timer0_th;
`REG_TIM1_TH:
PRDATA = r_timer1_th;
`REG_TIM2_TH:
PRDATA = r_timer2_th;
`REG_TIM3_TH:
PRDATA = r_timer3_th;
`REG_TIM0_CFG:
PRDATA = {8'h0,r_timer0_presc,3'h0,r_timer0_saw,r_timer0_in_clk,r_timer0_in_mode,r_timer0_in_sel};
`REG_TIM0_CH0_TH:
PRDATA = {13'h0,r_timer0_ch0_mode,r_timer0_ch0_th};
`REG_TIM0_CH0_LUT:
PRDATA = {14'h0,r_timer0_ch0_flt,r_timer0_ch0_lut};
`REG_TIM0_CH1_TH:
PRDATA = {13'h0,r_timer0_ch1_mode,r_timer0_ch1_th};
`REG_TIM0_CH1_LUT:
PRDATA = {14'h0,r_timer0_ch1_flt,r_timer0_ch1_lut};
`REG_TIM0_CH2_TH:
PRDATA = {13'h0,r_timer0_ch2_mode,r_timer0_ch2_th};
`REG_TIM0_CH2_LUT:
PRDATA = {14'h0,r_timer0_ch2_flt,r_timer0_ch2_lut};
`REG_TIM0_CH3_TH:
PRDATA = {13'h0,r_timer0_ch3_mode,r_timer0_ch3_th};
`REG_TIM0_CH3_LUT:
PRDATA = {14'h0,r_timer0_ch3_flt,r_timer0_ch3_lut};
`REG_TIM1_CFG:
PRDATA = {8'h0,r_timer1_presc,3'h0,r_timer1_saw,r_timer1_in_clk,r_timer1_in_mode,r_timer1_in_sel};
`REG_TIM1_CH0_TH:
PRDATA = {13'h0,r_timer1_ch0_mode,r_timer1_ch0_th};
`REG_TIM1_CH0_LUT:
PRDATA = {14'h0,r_timer1_ch0_flt,r_timer1_ch0_lut};
`REG_TIM1_CH1_TH:
PRDATA = {13'h0,r_timer1_ch1_mode,r_timer1_ch1_th};
`REG_TIM1_CH1_LUT:
PRDATA = {14'h0,r_timer1_ch1_flt,r_timer1_ch1_lut};
`REG_TIM1_CH2_TH:
PRDATA = {13'h0,r_timer1_ch2_mode,r_timer1_ch2_th};
`REG_TIM1_CH2_LUT:
PRDATA = {14'h0,r_timer1_ch2_flt,r_timer1_ch2_lut};
`REG_TIM1_CH3_TH:
PRDATA = {13'h0,r_timer1_ch3_mode,r_timer1_ch3_th};
`REG_TIM1_CH3_LUT:
PRDATA = {14'h0,r_timer1_ch3_flt,r_timer1_ch3_lut};
`REG_TIM2_CFG:
PRDATA = {8'h0,r_timer2_presc,3'h0,r_timer2_saw,r_timer2_in_clk,r_timer2_in_mode,r_timer2_in_sel};
`REG_TIM2_CH0_TH:
PRDATA = {13'h0,r_timer2_ch0_mode,r_timer2_ch0_th};
`REG_TIM2_CH0_LUT:
PRDATA = {14'h0,r_timer2_ch0_flt,r_timer2_ch0_lut};
`REG_TIM2_CH1_TH:
PRDATA = {13'h0,r_timer2_ch1_mode,r_timer2_ch1_th};
`REG_TIM2_CH1_LUT:
PRDATA = {14'h0,r_timer2_ch1_flt,r_timer2_ch1_lut};
`REG_TIM2_CH2_TH:
PRDATA = {13'h0,r_timer2_ch2_mode,r_timer2_ch2_th};
`REG_TIM2_CH2_LUT:
PRDATA = {14'h0,r_timer2_ch2_flt,r_timer2_ch2_lut};
`REG_TIM2_CH3_TH:
PRDATA = {13'h0,r_timer2_ch3_mode,r_timer2_ch3_th};
`REG_TIM2_CH3_LUT:
PRDATA = {14'h0,r_timer2_ch3_flt,r_timer2_ch3_lut};
`REG_TIM3_CFG:
PRDATA = {8'h0,r_timer3_presc,3'h0,r_timer3_saw,r_timer3_in_clk,r_timer3_in_mode,r_timer3_in_sel};
`REG_TIM3_CH0_TH:
PRDATA = {13'h0,r_timer3_ch0_mode,r_timer3_ch0_th};
`REG_TIM3_CH0_LUT:
PRDATA = {14'h0,r_timer3_ch0_flt,r_timer3_ch0_lut};
`REG_TIM3_CH1_TH:
PRDATA = {13'h0,r_timer3_ch1_mode,r_timer3_ch1_th};
`REG_TIM3_CH1_LUT:
PRDATA = {14'h0,r_timer3_ch1_flt,r_timer3_ch1_lut};
`REG_TIM3_CH2_TH:
PRDATA = {13'h0,r_timer3_ch2_mode,r_timer3_ch2_th};
`REG_TIM3_CH2_LUT:
PRDATA = {14'h0,r_timer3_ch2_flt,r_timer3_ch2_lut};
`REG_TIM3_CH3_TH:
PRDATA = {13'h0,r_timer3_ch3_mode,r_timer3_ch3_th};
`REG_TIM3_CH3_LUT:
PRDATA = {14'h0,r_timer3_ch3_flt,r_timer3_ch3_lut};
`REG_TIM0_COUNTER:
PRDATA = {16'h0,timer0_counter_i};
`REG_TIM1_COUNTER:
PRDATA = {16'h0,timer1_counter_i};
`REG_TIM2_COUNTER:
PRDATA = {16'h0,timer2_counter_i};
`REG_TIM3_COUNTER:
PRDATA = {16'h0,timer3_counter_i};
`REG_EVENT_CFG:
PRDATA = {12'h0,r_event_en,r_event_sel_3,r_event_sel_2,r_event_sel_1,r_event_sel_0};
`REG_CH_EN:
PRDATA = {28'h0,r_clk_en};
default:
PRDATA = 'h0;
endcase
end
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule |
module up_down_counter #(
parameter NUM_BITS = 16
)
(
input wire clk_i,
input wire rstn_i,
input wire cfg_sawtooth_i,
input wire [NUM_BITS - 1:0] cfg_start_i,
input wire [NUM_BITS - 1:0] cfg_end_i,
input wire ctrl_update_i,
input wire ctrl_rst_i,
input wire ctrl_active_i,
input wire counter_event_i,
output wire counter_end_o,
output wire counter_saw_o,
output wire counter_evt_o,
output wire [NUM_BITS - 1:0] counter_o
);
reg [NUM_BITS - 1:0] r_counter;
reg [NUM_BITS - 1:0] r_start;
reg [NUM_BITS - 1:0] r_end;
reg [NUM_BITS - 1:0] s_counter;
reg [NUM_BITS - 1:0] s_start;
reg [NUM_BITS - 1:0] s_end;
reg r_direction; //0 = count up | 1 = count down
reg r_sawtooth;
reg r_event;
reg s_direction; //0 = count up | 1 = count down
reg s_sawtooth;
wire s_is_update;
reg s_do_update;
reg s_pending_update;
reg r_pending_update;
assign counter_o = r_counter;
assign counter_saw_o = r_sawtooth;
assign counter_evt_o = ctrl_active_i & r_event;
assign counter_end_o = (ctrl_active_i & r_event) & s_is_update;
assign s_is_update = r_sawtooth ? (r_counter == r_end) : (r_direction && (r_counter == (r_start - 1)));
always @(posedge clk_i or negedge rstn_i) begin : proc_r_event
if (~rstn_i) begin
r_event <= 0;
r_pending_update <= 0;
end else begin
r_pending_update <= s_pending_update;
if (ctrl_active_i)
r_event <= counter_event_i;
end
end
always @(*) begin : proc_s_do_update
s_pending_update = r_pending_update;
s_do_update = 0;
if (ctrl_update_i || r_pending_update) begin
if (ctrl_update_i && !ctrl_active_i) begin
s_pending_update = 0;
s_do_update = 1;
end else if (s_is_update) begin
s_pending_update = 0;
s_do_update = counter_event_i;
end else begin
s_pending_update = 1;
s_do_update = 0;
end
end else if (ctrl_rst_i) begin
s_pending_update = 0;
s_do_update = 1;
end
end
always @(*) begin : proc_s_counter
s_counter = r_counter;
s_start = r_start;
s_sawtooth = r_sawtooth;
s_end = r_end;
s_direction = r_direction;
if (s_do_update) begin
s_counter = cfg_start_i;
s_start = cfg_start_i;
s_sawtooth = cfg_sawtooth_i;
s_end = cfg_end_i;
s_direction = 1'b0;
end else if (counter_event_i && ctrl_active_i) begin
if (!r_direction && (r_counter == r_end)) begin
if (r_sawtooth) begin
s_counter = r_start;
s_direction = 1'b0;
end else begin
s_counter = r_counter - 1;
s_direction = 1'b1;
end
end else if (r_direction && (r_counter == r_start)) begin
s_counter = r_counter + 1;
s_direction = 1'b0;
end else if (r_direction) begin
s_counter = r_counter - 1;
end else begin
s_counter = r_counter + 1;
end
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_counter
if (~rstn_i) begin
r_counter <= 0;
r_start <= 0;
r_end <= 0;
r_direction <= 0;
r_sawtooth <= 1'b1;
end else begin
if (s_do_update || (counter_event_i && ctrl_active_i)) begin
r_counter <= s_counter;
r_direction <= s_direction;
end
if (s_do_update) begin
r_start <= s_start;
r_end <= s_end;
r_sawtooth <= s_sawtooth;
end
end
end
endmodule |
module apb_adv_timer #(
parameter APB_ADDR_WIDTH = 12,
parameter EXTSIG_NUM = 32,
parameter TIMER_NBITS = 16
)
(
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
input wire dft_cg_enable_i,
input wire low_speed_clk_i,
input wire [EXTSIG_NUM - 1:0] ext_sig_i,
output wire [3:0] events_o,
output wire [3:0] ch_0_o,
output wire [3:0] ch_1_o,
output wire [3:0] ch_2_o,
output wire [3:0] ch_3_o
);
localparam N_TIMEREXTSIG = EXTSIG_NUM + 16;
wire s_timer0_apb_start;
wire s_timer0_apb_stop;
wire s_timer0_apb_arm;
wire s_timer0_apb_update;
wire s_timer0_apb_rst;
wire s_timer0_apb_saw;
wire [7:0] s_timer0_apb_in_sel;
wire [2:0] s_timer0_apb_in_mode;
wire [7:0] s_timer0_apb_presc;
wire [15:0] s_timer0_apb_th_hi;
wire [15:0] s_timer0_apb_th_low;
wire [2:0] s_timer0_apb_ch0_mode;
wire [1:0] s_timer0_apb_ch0_flt;
wire [15:0] s_timer0_apb_ch0_th;
wire [15:0] s_timer0_apb_ch0_lut;
wire [2:0] s_timer0_apb_ch1_mode;
wire [1:0] s_timer0_apb_ch1_flt;
wire [15:0] s_timer0_apb_ch1_th;
wire [15:0] s_timer0_apb_ch1_lut;
wire [2:0] s_timer0_apb_ch2_mode;
wire [1:0] s_timer0_apb_ch2_flt;
wire [15:0] s_timer0_apb_ch2_th;
wire [15:0] s_timer0_apb_ch2_lut;
wire [2:0] s_timer0_apb_ch3_mode;
wire [1:0] s_timer0_apb_ch3_flt;
wire [15:0] s_timer0_apb_ch3_th;
wire [15:0] s_timer0_apb_ch3_lut;
wire s_timer1_apb_start;
wire s_timer1_apb_stop;
wire s_timer1_apb_arm;
wire s_timer1_apb_update;
wire s_timer1_apb_rst;
wire s_timer1_apb_saw;
wire [7:0] s_timer1_apb_in_sel;
wire [2:0] s_timer1_apb_in_mode;
wire [7:0] s_timer1_apb_presc;
wire [15:0] s_timer1_apb_th_hi;
wire [15:0] s_timer1_apb_th_low;
wire [2:0] s_timer1_apb_ch0_mode;
wire [1:0] s_timer1_apb_ch0_flt;
wire [15:0] s_timer1_apb_ch0_th;
wire [15:0] s_timer1_apb_ch0_lut;
wire [2:0] s_timer1_apb_ch1_mode;
wire [1:0] s_timer1_apb_ch1_flt;
wire [15:0] s_timer1_apb_ch1_th;
wire [15:0] s_timer1_apb_ch1_lut;
wire [2:0] s_timer1_apb_ch2_mode;
wire [1:0] s_timer1_apb_ch2_flt;
wire [15:0] s_timer1_apb_ch2_th;
wire [15:0] s_timer1_apb_ch2_lut;
wire [2:0] s_timer1_apb_ch3_mode;
wire [1:0] s_timer1_apb_ch3_flt;
wire [15:0] s_timer1_apb_ch3_th;
wire [15:0] s_timer1_apb_ch3_lut;
wire s_timer2_apb_start;
wire s_timer2_apb_stop;
wire s_timer2_apb_arm;
wire s_timer2_apb_update;
wire s_timer2_apb_rst;
wire s_timer2_apb_saw;
wire [7:0] s_timer2_apb_in_sel;
wire [2:0] s_timer2_apb_in_mode;
wire [7:0] s_timer2_apb_presc;
wire [15:0] s_timer2_apb_th_hi;
wire [15:0] s_timer2_apb_th_low;
wire [2:0] s_timer2_apb_ch0_mode;
wire [1:0] s_timer2_apb_ch0_flt;
wire [15:0] s_timer2_apb_ch0_th;
wire [15:0] s_timer2_apb_ch0_lut;
wire [2:0] s_timer2_apb_ch1_mode;
wire [1:0] s_timer2_apb_ch1_flt;
wire [15:0] s_timer2_apb_ch1_th;
wire [15:0] s_timer2_apb_ch1_lut;
wire [2:0] s_timer2_apb_ch2_mode;
wire [1:0] s_timer2_apb_ch2_flt;
wire [15:0] s_timer2_apb_ch2_th;
wire [15:0] s_timer2_apb_ch2_lut;
wire [2:0] s_timer2_apb_ch3_mode;
wire [1:0] s_timer2_apb_ch3_flt;
wire [15:0] s_timer2_apb_ch3_th;
wire [15:0] s_timer2_apb_ch3_lut;
wire s_timer3_apb_start;
wire s_timer3_apb_stop;
wire s_timer3_apb_arm;
wire s_timer3_apb_update;
wire s_timer3_apb_rst;
wire s_timer3_apb_saw;
wire [7:0] s_timer3_apb_in_sel;
wire [2:0] s_timer3_apb_in_mode;
wire [7:0] s_timer3_apb_presc;
wire [15:0] s_timer3_apb_th_hi;
wire [15:0] s_timer3_apb_th_low;
wire [2:0] s_timer3_apb_ch0_mode;
wire [1:0] s_timer3_apb_ch0_flt;
wire [15:0] s_timer3_apb_ch0_th;
wire [15:0] s_timer3_apb_ch0_lut;
wire [2:0] s_timer3_apb_ch1_mode;
wire [1:0] s_timer3_apb_ch1_flt;
wire [15:0] s_timer3_apb_ch1_th;
wire [15:0] s_timer3_apb_ch1_lut;
wire [2:0] s_timer3_apb_ch2_mode;
wire [1:0] s_timer3_apb_ch2_flt;
wire [15:0] s_timer3_apb_ch2_th;
wire [15:0] s_timer3_apb_ch2_lut;
wire [2:0] s_timer3_apb_ch3_mode;
wire [1:0] s_timer3_apb_ch3_flt;
wire [15:0] s_timer3_apb_ch3_th;
wire [15:0] s_timer3_apb_ch3_lut;
wire [3:0] s_event_en;
wire [3:0] s_event_sel_0;
wire [3:0] s_event_sel_1;
wire [3:0] s_event_sel_2;
wire [3:0] s_event_sel_3;
wire s_timer0_apb_in_clk;
wire s_timer1_apb_in_clk;
wire s_timer2_apb_in_clk;
wire s_timer3_apb_in_clk;
wire [15:0] s_timer0_counter;
wire [15:0] s_timer1_counter;
wire [15:0] s_timer2_counter;
wire [15:0] s_timer3_counter;
wire s_timer0_clk_en;
wire s_timer1_clk_en;
wire s_timer2_clk_en;
wire s_timer3_clk_en;
wire s_clk_timer0;
wire s_clk_timer1;
wire s_clk_timer2;
wire s_clk_timer3;
adv_timer_apb_if #(
.APB_ADDR_WIDTH ( APB_ADDR_WIDTH )
) u_apb_if (
.HCLK ( HCLK ),
.HRESETn ( HRESETn ),
.PADDR ( PADDR ),
.PWDATA ( PWDATA ),
.PWRITE ( PWRITE ),
.PSEL ( PSEL ),
.PENABLE ( PENABLE ),
.PRDATA ( PRDATA ),
.PREADY ( PREADY ),
.PSLVERR ( PSLVERR ),
.events_en_o ( s_event_en ),
.events_sel_0_o ( s_event_sel_0 ),
.events_sel_1_o ( s_event_sel_1 ),
.events_sel_2_o ( s_event_sel_2 ),
.events_sel_3_o ( s_event_sel_3 ),
.timer0_start_o ( s_timer0_apb_start ),
.timer0_stop_o ( s_timer0_apb_stop ),
.timer0_arm_o ( s_timer0_apb_arm ),
.timer0_update_o ( s_timer0_apb_update ),
.timer0_rst_o ( s_timer0_apb_rst ),
.timer0_saw_o ( s_timer0_apb_saw ),
.timer0_in_sel_o ( s_timer0_apb_in_sel ),
.timer0_in_clk_o ( s_timer0_apb_in_clk ),
.timer0_in_mode_o ( s_timer0_apb_in_mode ),
.timer0_presc_o ( s_timer0_apb_presc ),
.timer0_th_hi_o ( s_timer0_apb_th_hi ),
.timer0_th_low_o ( s_timer0_apb_th_low ),
.timer0_ch0_mode_o ( s_timer0_apb_ch0_mode ),
.timer0_ch0_flt_o ( s_timer0_apb_ch0_flt ),
.timer0_ch0_th_o ( s_timer0_apb_ch0_th ),
.timer0_ch0_lut_o ( s_timer0_apb_ch0_lut ),
.timer0_ch1_mode_o ( s_timer0_apb_ch1_mode ),
.timer0_ch1_flt_o ( s_timer0_apb_ch1_flt ),
.timer0_ch1_th_o ( s_timer0_apb_ch1_th ),
.timer0_ch1_lut_o ( s_timer0_apb_ch1_lut ),
.timer0_ch2_mode_o ( s_timer0_apb_ch2_mode ),
.timer0_ch2_flt_o ( s_timer0_apb_ch2_flt ),
.timer0_ch2_th_o ( s_timer0_apb_ch2_th ),
.timer0_ch2_lut_o ( s_timer0_apb_ch2_lut ),
.timer0_ch3_mode_o ( s_timer0_apb_ch3_mode ),
.timer0_ch3_flt_o ( s_timer0_apb_ch3_flt ),
.timer0_ch3_th_o ( s_timer0_apb_ch3_th ),
.timer0_ch3_lut_o ( s_timer0_apb_ch3_lut ),
.timer0_counter_i ( s_timer0_counter ),
.timer1_start_o ( s_timer1_apb_start ),
.timer1_stop_o ( s_timer1_apb_stop ),
.timer1_arm_o ( s_timer1_apb_arm ),
.timer1_update_o ( s_timer1_apb_update ),
.timer1_rst_o ( s_timer1_apb_rst ),
.timer1_saw_o ( s_timer1_apb_saw ),
.timer1_in_sel_o ( s_timer1_apb_in_sel ),
.timer1_in_clk_o ( s_timer1_apb_in_clk ),
.timer1_in_mode_o ( s_timer1_apb_in_mode ),
.timer1_presc_o ( s_timer1_apb_presc ),
.timer1_th_hi_o ( s_timer1_apb_th_hi ),
.timer1_th_low_o ( s_timer1_apb_th_low ),
.timer1_ch0_mode_o ( s_timer1_apb_ch0_mode ),
.timer1_ch0_flt_o ( s_timer1_apb_ch0_flt ),
.timer1_ch0_th_o ( s_timer1_apb_ch0_th ),
.timer1_ch0_lut_o ( s_timer1_apb_ch0_lut ),
.timer1_ch1_mode_o ( s_timer1_apb_ch1_mode ),
.timer1_ch1_flt_o ( s_timer1_apb_ch1_flt ),
.timer1_ch1_th_o ( s_timer1_apb_ch1_th ),
.timer1_ch1_lut_o ( s_timer1_apb_ch1_lut ),
.timer1_ch2_mode_o ( s_timer1_apb_ch2_mode ),
.timer1_ch2_flt_o ( s_timer1_apb_ch2_flt ),
.timer1_ch2_th_o ( s_timer1_apb_ch2_th ),
.timer1_ch2_lut_o ( s_timer1_apb_ch2_lut ),
.timer1_ch3_mode_o ( s_timer1_apb_ch3_mode ),
.timer1_ch3_flt_o ( s_timer1_apb_ch3_flt ),
.timer1_ch3_th_o ( s_timer1_apb_ch3_th ),
.timer1_ch3_lut_o ( s_timer1_apb_ch3_lut ),
.timer1_counter_i ( s_timer1_counter ),
.timer2_start_o ( s_timer2_apb_start ),
.timer2_stop_o ( s_timer2_apb_stop ),
.timer2_arm_o ( s_timer2_apb_arm ),
.timer2_update_o ( s_timer2_apb_update ),
.timer2_rst_o ( s_timer2_apb_rst ),
.timer2_saw_o ( s_timer2_apb_saw ),
.timer2_in_sel_o ( s_timer2_apb_in_sel ),
.timer2_in_clk_o ( s_timer2_apb_in_clk ),
.timer2_in_mode_o ( s_timer2_apb_in_mode ),
.timer2_presc_o ( s_timer2_apb_presc ),
.timer2_th_hi_o ( s_timer2_apb_th_hi ),
.timer2_th_low_o ( s_timer2_apb_th_low ),
.timer2_ch0_mode_o ( s_timer2_apb_ch0_mode ),
.timer2_ch0_flt_o ( s_timer2_apb_ch0_flt ),
.timer2_ch0_th_o ( s_timer2_apb_ch0_th ),
.timer2_ch0_lut_o ( s_timer2_apb_ch0_lut ),
.timer2_ch1_mode_o ( s_timer2_apb_ch1_mode ),
.timer2_ch1_flt_o ( s_timer2_apb_ch1_flt ),
.timer2_ch1_th_o ( s_timer2_apb_ch1_th ),
.timer2_ch1_lut_o ( s_timer2_apb_ch1_lut ),
.timer2_ch2_mode_o ( s_timer2_apb_ch2_mode ),
.timer2_ch2_flt_o ( s_timer2_apb_ch2_flt ),
.timer2_ch2_th_o ( s_timer2_apb_ch2_th ),
.timer2_ch2_lut_o ( s_timer2_apb_ch2_lut ),
.timer2_ch3_mode_o ( s_timer2_apb_ch3_mode ),
.timer2_ch3_flt_o ( s_timer2_apb_ch3_flt ),
.timer2_ch3_th_o ( s_timer2_apb_ch3_th ),
.timer2_ch3_lut_o ( s_timer2_apb_ch3_lut ),
.timer2_counter_i ( s_timer2_counter ),
.timer3_start_o ( s_timer3_apb_start ),
.timer3_stop_o ( s_timer3_apb_stop ),
.timer3_arm_o ( s_timer3_apb_arm ),
.timer3_update_o ( s_timer3_apb_update ),
.timer3_rst_o ( s_timer3_apb_rst ),
.timer3_saw_o ( s_timer3_apb_saw ),
.timer3_in_sel_o ( s_timer3_apb_in_sel ),
.timer3_in_clk_o ( s_timer3_apb_in_clk ),
.timer3_in_mode_o ( s_timer3_apb_in_mode ),
.timer3_presc_o ( s_timer3_apb_presc ),
.timer3_th_hi_o ( s_timer3_apb_th_hi ),
.timer3_th_low_o ( s_timer3_apb_th_low ),
.timer3_ch0_mode_o ( s_timer3_apb_ch0_mode ),
.timer3_ch0_flt_o ( s_timer3_apb_ch0_flt ),
.timer3_ch0_th_o ( s_timer3_apb_ch0_th ),
.timer3_ch0_lut_o ( s_timer3_apb_ch0_lut ),
.timer3_ch1_mode_o ( s_timer3_apb_ch1_mode ),
.timer3_ch1_flt_o ( s_timer3_apb_ch1_flt ),
.timer3_ch1_th_o ( s_timer3_apb_ch1_th ),
.timer3_ch1_lut_o ( s_timer3_apb_ch1_lut ),
.timer3_ch2_mode_o ( s_timer3_apb_ch2_mode ),
.timer3_ch2_flt_o ( s_timer3_apb_ch2_flt ),
.timer3_ch2_th_o ( s_timer3_apb_ch2_th ),
.timer3_ch2_lut_o ( s_timer3_apb_ch2_lut ),
.timer3_ch3_mode_o ( s_timer3_apb_ch3_mode ),
.timer3_ch3_flt_o ( s_timer3_apb_ch3_flt ),
.timer3_ch3_th_o ( s_timer3_apb_ch3_th ),
.timer3_ch3_lut_o ( s_timer3_apb_ch3_lut ),
.timer3_counter_i ( s_timer3_counter ),
.timer0_clk_en_o ( s_timer0_clk_en ),
.timer1_clk_en_o ( s_timer1_clk_en ),
.timer2_clk_en_o ( s_timer2_clk_en ),
.timer3_clk_en_o ( s_timer3_clk_en )
);
/////////////////////////////////////////////////////////////////////
//
// TIMER0
//
/////////////////////////////////////////////////////////////////////
wire [7:0] s_timer0_status;
wire [N_TIMEREXTSIG - 1:0] s_timer0_signal;
assign s_timer0_signal = {ch_3_o, ch_2_o, ch_1_o, ch_0_o, ext_sig_i};
e203_clkgate i_clk_gate_timer0(
.clk_in (HCLK ),
.clock_en (s_timer0_clk_en),
.test_mode(dft_cg_enable_i),
.clk_out (s_clk_timer0 )
);
timer_module #(
.NUM_BITS ( TIMER_NBITS ),
.N_EXTSIG ( N_TIMEREXTSIG )
) u_tim0 (
.clk_i ( s_clk_timer0 ),
.rstn_i ( HRESETn ),
.cfg_start_i ( s_timer0_apb_start ),
.cfg_stop_i ( s_timer0_apb_stop ),
.cfg_rst_i ( s_timer0_apb_rst ),
.cfg_update_i ( s_timer0_apb_update ),
.cfg_arm_i ( s_timer0_apb_arm ),
.cfg_sel_i ( s_timer0_apb_in_sel ),
.cfg_sel_clk_i ( s_timer0_apb_in_clk ),
.cfg_mode_i ( s_timer0_apb_in_mode ),
.cfg_presc_i ( s_timer0_apb_presc ),
.cfg_sawtooth_i ( s_timer0_apb_saw ),
.cfg_cnt_start_i ( s_timer0_apb_th_low ),
.cfg_cnt_end_i ( s_timer0_apb_th_hi ),
.cfg_comp_ch0_i ( s_timer0_apb_ch0_th ),
.cfg_comp_op_ch0_i( s_timer0_apb_ch0_mode ),
.cfg_comp_ch1_i ( s_timer0_apb_ch1_th ),
.cfg_comp_op_ch1_i( s_timer0_apb_ch1_mode ),
.cfg_comp_ch2_i ( s_timer0_apb_ch2_th ),
.cfg_comp_op_ch2_i( s_timer0_apb_ch2_mode ),
.cfg_comp_ch3_i ( s_timer0_apb_ch3_th ),
.cfg_comp_op_ch3_i( s_timer0_apb_ch3_mode ),
.ls_clk_i ( low_speed_clk_i ),
.signal_i ( s_timer0_signal ),
.counter_o ( s_timer0_counter ),
.pwm_o ( ch_0_o ),
.status_o ( s_timer0_status )
);
/////////////////////////////////////////////////////////////////////
//
// TIMER1
//
/////////////////////////////////////////////////////////////////////
wire [7:0] s_timer1_status;
wire [N_TIMEREXTSIG - 1:0] s_timer1_signal;
assign s_timer1_signal = {ch_3_o, ch_2_o, ch_1_o, ch_0_o, ext_sig_i};
e203_clkgate i_clk_gate_timer1(
.clk_in (HCLK ),
.clock_en (s_timer1_clk_en),
.test_mode(dft_cg_enable_i),
.clk_out (s_clk_timer1 )
);
timer_module #(
.NUM_BITS ( TIMER_NBITS ),
.N_EXTSIG ( N_TIMEREXTSIG )
) u_tim1 (
.clk_i ( s_clk_timer1 ),
.rstn_i ( HRESETn ),
.cfg_start_i ( s_timer1_apb_start ),
.cfg_stop_i ( s_timer1_apb_stop ),
.cfg_rst_i ( s_timer1_apb_rst ),
.cfg_update_i ( s_timer1_apb_update ),
.cfg_arm_i ( s_timer1_apb_arm ),
.cfg_sel_i ( s_timer1_apb_in_sel ),
.cfg_sel_clk_i ( s_timer1_apb_in_clk ),
.cfg_mode_i ( s_timer1_apb_in_mode ),
.cfg_presc_i ( s_timer1_apb_presc ),
.cfg_sawtooth_i ( s_timer1_apb_saw ),
.cfg_cnt_start_i ( s_timer1_apb_th_low ),
.cfg_cnt_end_i ( s_timer1_apb_th_hi ),
.cfg_comp_ch0_i ( s_timer1_apb_ch0_th ),
.cfg_comp_op_ch0_i( s_timer1_apb_ch0_mode ),
.cfg_comp_ch1_i ( s_timer1_apb_ch1_th ),
.cfg_comp_op_ch1_i( s_timer1_apb_ch1_mode ),
.cfg_comp_ch2_i ( s_timer1_apb_ch2_th ),
.cfg_comp_op_ch2_i( s_timer1_apb_ch2_mode ),
.cfg_comp_ch3_i ( s_timer1_apb_ch3_th ),
.cfg_comp_op_ch3_i( s_timer1_apb_ch3_mode ),
.ls_clk_i ( low_speed_clk_i ),
.signal_i ( s_timer1_signal ),
.counter_o ( s_timer1_counter ),
.pwm_o ( ch_1_o ),
.status_o ( s_timer1_status )
);
/////////////////////////////////////////////////////////////////////
//
// TIMER2
//
/////////////////////////////////////////////////////////////////////
wire [7:0] s_timer2_status;
wire [N_TIMEREXTSIG - 1:0] s_timer2_signal;
assign s_timer2_signal = {ch_3_o, ch_2_o, ch_1_o, ch_0_o, ext_sig_i};
e203_clkgate i_clk_gate_timer2(
.clk_in (HCLK ),
.clock_en (s_timer2_clk_en),
.test_mode(dft_cg_enable_i),
.clk_out (s_clk_timer2 )
);
timer_module #(
.NUM_BITS ( TIMER_NBITS ),
.N_EXTSIG ( N_TIMEREXTSIG )
) u_tim2 (
.clk_i ( s_clk_timer2 ),
.rstn_i ( HRESETn ),
.cfg_start_i ( s_timer2_apb_start ),
.cfg_stop_i ( s_timer2_apb_stop ),
.cfg_rst_i ( s_timer2_apb_rst ),
.cfg_update_i ( s_timer2_apb_update ),
.cfg_arm_i ( s_timer2_apb_arm ),
.cfg_sel_i ( s_timer2_apb_in_sel ),
.cfg_sel_clk_i ( s_timer2_apb_in_clk ),
.cfg_mode_i ( s_timer2_apb_in_mode ),
.cfg_presc_i ( s_timer2_apb_presc ),
.cfg_sawtooth_i ( s_timer2_apb_saw ),
.cfg_cnt_start_i ( s_timer2_apb_th_low ),
.cfg_cnt_end_i ( s_timer2_apb_th_hi ),
.cfg_comp_ch0_i ( s_timer2_apb_ch0_th ),
.cfg_comp_op_ch0_i( s_timer2_apb_ch0_mode ),
.cfg_comp_ch1_i ( s_timer2_apb_ch1_th ),
.cfg_comp_op_ch1_i( s_timer2_apb_ch1_mode ),
.cfg_comp_ch2_i ( s_timer2_apb_ch2_th ),
.cfg_comp_op_ch2_i( s_timer2_apb_ch2_mode ),
.cfg_comp_ch3_i ( s_timer2_apb_ch3_th ),
.cfg_comp_op_ch3_i( s_timer2_apb_ch3_mode ),
.ls_clk_i ( low_speed_clk_i ),
.signal_i ( s_timer2_signal ),
.counter_o ( s_timer2_counter ),
.pwm_o ( ch_2_o ),
.status_o ( s_timer2_status )
);
/////////////////////////////////////////////////////////////////////
//
// TIMER3
//
/////////////////////////////////////////////////////////////////////
wire [7:0] s_timer3_status;
wire [N_TIMEREXTSIG - 1:0] s_timer3_signal;
assign s_timer3_signal = {ch_3_o, ch_2_o, ch_1_o, ch_0_o, ext_sig_i};
e203_clkgate i_clk_gate_timer3(
.clk_in (HCLK ),
.clock_en (s_timer3_clk_en),
.test_mode(dft_cg_enable_i),
.clk_out (s_clk_timer3 )
);
timer_module #(
.NUM_BITS ( TIMER_NBITS ),
.N_EXTSIG ( N_TIMEREXTSIG )
) u_tim3 (
.clk_i ( s_clk_timer3 ),
.rstn_i ( HRESETn ),
.cfg_start_i ( s_timer3_apb_start ),
.cfg_stop_i ( s_timer3_apb_stop ),
.cfg_rst_i ( s_timer3_apb_rst ),
.cfg_update_i ( s_timer3_apb_update ),
.cfg_arm_i ( s_timer3_apb_arm ),
.cfg_sel_i ( s_timer3_apb_in_sel ),
.cfg_sel_clk_i ( s_timer3_apb_in_clk ),
.cfg_mode_i ( s_timer3_apb_in_mode ),
.cfg_presc_i ( s_timer3_apb_presc ),
.cfg_sawtooth_i ( s_timer3_apb_saw ),
.cfg_cnt_start_i ( s_timer3_apb_th_low ),
.cfg_cnt_end_i ( s_timer3_apb_th_hi ),
.cfg_comp_ch0_i ( s_timer3_apb_ch0_th ),
.cfg_comp_op_ch0_i( s_timer3_apb_ch0_mode ),
.cfg_comp_ch1_i ( s_timer3_apb_ch1_th ),
.cfg_comp_op_ch1_i( s_timer3_apb_ch1_mode ),
.cfg_comp_ch2_i ( s_timer3_apb_ch2_th ),
.cfg_comp_op_ch2_i( s_timer3_apb_ch2_mode ),
.cfg_comp_ch3_i ( s_timer3_apb_ch3_th ),
.cfg_comp_op_ch3_i( s_timer3_apb_ch3_mode ),
.ls_clk_i ( low_speed_clk_i ),
.signal_i ( s_timer3_signal ),
.counter_o ( s_timer3_counter ),
.pwm_o ( ch_3_o ),
.status_o ( s_timer3_status )
);
wire [15:0] s_event_signals;
reg [1:0] r_event_sync_0;
reg [1:0] r_event_sync_1;
reg [1:0] r_event_sync_2;
reg [1:0] r_event_sync_3;
assign s_event_signals = {ch_3_o, ch_2_o, ch_1_o, ch_0_o};
assign events_o[0] = (s_event_en[0] & r_event_sync_0[1]) & ~r_event_sync_0[0];
assign events_o[1] = (s_event_en[1] & r_event_sync_1[1]) & ~r_event_sync_1[0];
assign events_o[2] = (s_event_en[2] & r_event_sync_2[1]) & ~r_event_sync_2[0];
assign events_o[3] = (s_event_en[3] & r_event_sync_3[1]) & ~r_event_sync_3[0];
always @(posedge HCLK or negedge HRESETn) begin : proc_edgedet
if (~HRESETn) begin
r_event_sync_0 <= 0;
r_event_sync_1 <= 0;
r_event_sync_2 <= 0;
r_event_sync_3 <= 0;
end else begin
if (s_event_en[0]) r_event_sync_0 <= {s_event_signals[s_event_sel_0], r_event_sync_0[1]};
if (s_event_en[1]) r_event_sync_1 <= {s_event_signals[s_event_sel_1], r_event_sync_1[1]};
if (s_event_en[2]) r_event_sync_2 <= {s_event_signals[s_event_sel_2], r_event_sync_2[1]};
if (s_event_en[3]) r_event_sync_3 <= {s_event_signals[s_event_sel_3], r_event_sync_3[1]};
end
end
endmodule |
module timer_module #(
parameter NUM_BITS = 16,
parameter N_EXTSIG = 32
) (
input wire clk_i,
input wire rstn_i,
input wire cfg_start_i,
input wire cfg_stop_i,
input wire cfg_rst_i,
input wire cfg_update_i,
input wire cfg_arm_i,
input wire [7:0] cfg_sel_i,
input wire cfg_sel_clk_i,
input wire [2:0] cfg_mode_i,
input wire [7:0] cfg_presc_i,
input wire cfg_sawtooth_i,
input wire [NUM_BITS - 1:0] cfg_cnt_start_i,
input wire [NUM_BITS - 1:0] cfg_cnt_end_i,
input wire [NUM_BITS - 1:0] cfg_comp_ch0_i,
input wire [2:0] cfg_comp_op_ch0_i,
input wire [NUM_BITS - 1:0] cfg_comp_ch1_i,
input wire [2:0] cfg_comp_op_ch1_i,
input wire [NUM_BITS - 1:0] cfg_comp_ch2_i,
input wire [2:0] cfg_comp_op_ch2_i,
input wire [NUM_BITS - 1:0] cfg_comp_ch3_i,
input wire [2:0] cfg_comp_op_ch3_i,
input wire ls_clk_i,
input wire [N_EXTSIG - 1:0] signal_i,
output wire [NUM_BITS - 1:0] counter_o,
output wire [3:0] pwm_o,
output wire [7:0] status_o
);
wire s_ctrl_update_cnt;
wire s_ctrl_update_all;
wire s_ctrl_active;
wire s_ctrl_rst;
wire s_ctrl_arm;
wire s_cnt_update; //FIXME ANTONIO CONNECT ME
wire s_in_evt;
wire s_presc_evt;
wire s_cnt_end;
wire s_cnt_saw;
wire s_cnt_evt;
wire [NUM_BITS - 1:0] s_cnt;
assign counter_o = s_cnt;
timer_cntrl u_controller
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.cfg_start_i ( cfg_start_i ),
.cfg_stop_i ( cfg_stop_i ),
.cfg_rst_i ( cfg_rst_i ),
.cfg_update_i ( cfg_update_i ),
.cfg_arm_i ( cfg_arm_i ),
.ctrl_cnt_upd_o ( s_ctrl_update_cnt ),
.ctrl_all_upd_o ( s_ctrl_update_all ),
.ctrl_active_o ( s_ctrl_active ),
.ctrl_rst_o ( s_ctrl_rst ),
.ctrl_arm_o ( s_ctrl_arm ),
.cnt_update_i ( s_cnt_evt ),
.status_o ( status_o )
);
input_stage #(
.EXTSIG_NUM(N_EXTSIG)
) u_in_stage (
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_arm_i ( s_ctrl_arm ),
.cnt_end_i ( s_cnt_end ),
.cfg_sel_i ( cfg_sel_i ),
.cfg_sel_clk_i ( cfg_sel_clk_i ),
.cfg_mode_i ( cfg_mode_i ),
.ls_clk_i ( ls_clk_i ),
.signal_i ( signal_i ),
.event_o ( s_in_evt )
);
prescaler u_prescaler
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_rst_i ( s_ctrl_rst ),
.cfg_presc_i ( cfg_presc_i ),
.event_i ( s_in_evt ),
.event_o ( s_presc_evt )
);
up_down_counter u_counter
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_cnt ),
.ctrl_rst_i ( s_ctrl_rst ),
.ctrl_active_i ( s_ctrl_active ),
.cfg_sawtooth_i ( cfg_sawtooth_i ),
.cfg_start_i ( cfg_cnt_start_i ),
.cfg_end_i ( cfg_cnt_end_i ),
.counter_event_i ( s_presc_evt ),
.counter_end_o ( s_cnt_end ),
.counter_saw_o ( s_cnt_saw ),
.counter_evt_o ( s_cnt_evt ),
.counter_o ( s_cnt )
);
comparator u_comp_ch0
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_rst_i ( s_ctrl_rst ),
.timer_end_i ( s_cnt_end ),
.timer_valid_i ( s_cnt_evt ),
.timer_sawtooth_i ( s_cnt_saw ),
.timer_count_i ( s_cnt ),
.cfg_comp_op_i ( cfg_comp_op_ch0_i ),
.cfg_comp_i ( cfg_comp_ch0_i ),
.result_o ( pwm_o[0] )
);
comparator u_comp_ch1
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_rst_i ( s_ctrl_rst ),
.timer_end_i ( s_cnt_end ),
.timer_valid_i ( s_cnt_evt ),
.timer_sawtooth_i ( s_cnt_saw ),
.timer_count_i ( s_cnt ),
.cfg_comp_op_i ( cfg_comp_op_ch1_i ),
.cfg_comp_i ( cfg_comp_ch1_i ),
.result_o ( pwm_o[1] )
);
comparator u_comp_ch2
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_rst_i ( s_ctrl_rst ),
.timer_end_i ( s_cnt_end ),
.timer_valid_i ( s_cnt_evt ),
.timer_sawtooth_i ( s_cnt_saw ),
.timer_count_i ( s_cnt ),
.cfg_comp_op_i ( cfg_comp_op_ch2_i ),
.cfg_comp_i ( cfg_comp_ch2_i ),
.result_o ( pwm_o[2] )
);
comparator u_comp_ch3
(
.clk_i ( clk_i ),
.rstn_i ( rstn_i ),
.ctrl_update_i ( s_ctrl_update_all ),
.ctrl_active_i ( s_ctrl_active ),
.ctrl_rst_i ( s_ctrl_rst ),
.timer_end_i ( s_cnt_end ),
.timer_valid_i ( s_cnt_evt ),
.timer_sawtooth_i ( s_cnt_saw ),
.timer_count_i ( s_cnt ),
.cfg_comp_op_i ( cfg_comp_op_ch3_i ),
.cfg_comp_i ( cfg_comp_ch3_i ),
.result_o ( pwm_o[3] )
);
endmodule |
module prescaler (
input wire clk_i,
input wire rstn_i,
input wire ctrl_active_i,
input wire ctrl_update_i,
input wire ctrl_rst_i,
input wire [7:0] cfg_presc_i,
input wire event_i,
output reg event_o
);
reg [7:0] r_presc;
reg [7:0] r_counter;
always @(posedge clk_i or negedge rstn_i) begin : proc_r_presc
if (~rstn_i)
r_presc <= 0;
else if (ctrl_update_i) //if first enable or explicit update is iven
r_presc <= cfg_presc_i;
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_counter
if (~rstn_i) begin
r_counter <= 0;
event_o <= 0;
end else if (ctrl_rst_i) begin
r_counter <= 0;
event_o <= 0;
end else if (ctrl_active_i) begin
if (event_i) begin
if (r_presc == 0) begin
event_o <= 1'b1;
end else if (r_counter == r_presc) begin
event_o <= 1'b1;
r_counter <= 0;
end else begin
event_o <= 1'b0;
r_counter <= r_counter + 1;
end
end else begin
event_o <= 1'b0;
end
end else begin
r_counter <= 0;
event_o <= 0;
end
end
endmodule |
module input_stage #(
parameter EXTSIG_NUM = 32
) (
input wire clk_i,
input wire rstn_i,
input wire ctrl_active_i,
input wire ctrl_update_i,
input wire ctrl_arm_i,
input wire cnt_end_i,
input wire [7:0] cfg_sel_i,
input wire cfg_sel_clk_i,
input wire [2:0] cfg_mode_i,
input wire ls_clk_i,
input wire [EXTSIG_NUM - 1:0] signal_i,
output reg event_o
);
wire s_rise;
wire s_rise_ls_clk;
wire s_fall;
reg s_int_evnt;
wire s_event;
wire r_active;
reg r_event;
reg r_oldval;
reg s_int_sig;
reg [7:0] r_sel;
reg [2:0] r_mode;
reg r_armed;
reg [2:0] r_ls_clk_sync;
assign s_rise = ~r_oldval & s_int_sig;
assign s_fall = r_oldval & ~s_int_sig;
assign s_rise_ls_clk = ~r_ls_clk_sync[2] & r_ls_clk_sync[1];
always @(posedge clk_i or negedge rstn_i) begin : proc_r_ls_clk_sync
if (~rstn_i)
r_ls_clk_sync <= 'h0;
else
r_ls_clk_sync <= {r_ls_clk_sync[1:0], ls_clk_i};
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_mode
if (~rstn_i) begin
r_mode <= 0;
r_sel <= 0;
end else if (ctrl_update_i) begin
r_mode <= cfg_mode_i;
r_sel <= cfg_sel_i;
end
end
always @(*) begin : proc_event_o
if (cfg_sel_clk_i)
event_o = s_int_evnt & s_rise_ls_clk;
else
event_o = s_int_evnt;
end
always @(*) begin : proc_s_int_evnt
case (r_mode)
3'b000: s_int_evnt = 1'b1;
3'b001: s_int_evnt = ~s_int_sig;
3'b010: s_int_evnt = s_int_sig;
3'b011: s_int_evnt = s_rise;
3'b100: s_int_evnt = s_fall;
3'b101: s_int_evnt = s_rise | s_fall;
3'b110:
begin
if (r_armed)
s_int_evnt = (s_rise ? 1'b1 : r_event);
else
s_int_evnt = 1'b0;
end
3'b111:
begin
if (r_armed)
s_int_evnt = (s_fall ? 1'b1 : r_event);
else
s_int_evnt = 1'b0;
end
endcase
end
integer i;
always @(*) begin : proc_int_sig
s_int_sig = 0;
for (i = 0; i < EXTSIG_NUM; i = i + 1) begin
if (r_sel == i) s_int_sig = signal_i[i];
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_event
if (~rstn_i) begin
r_event <= 1'b0;
r_armed <= 1'b0;
end else begin
if (r_armed)
r_event <= s_int_evnt;
else if (cnt_end_i)
r_event <= 1'b0;
if (ctrl_arm_i)
r_armed <= 1'b1;
else if (cnt_end_i)
r_armed <= 1'b0;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_sync
if (~rstn_i) begin
r_oldval <= 0;
end else if (ctrl_active_i) begin
if (!cfg_sel_clk_i || (cfg_sel_clk_i && s_rise_ls_clk))
r_oldval <= s_int_sig;
end
end
endmodule |
module comparator #(
parameter NUM_BITS = 16
) (
input wire clk_i,
input wire rstn_i,
input wire ctrl_active_i,
input wire ctrl_update_i,
input wire ctrl_rst_i,
input wire [NUM_BITS - 1:0] cfg_comp_i,
input wire [2:0] cfg_comp_op_i,
input wire timer_end_i,
input wire timer_valid_i,
input wire timer_sawtooth_i,
input wire [NUM_BITS - 1:0] timer_count_i,
output wire result_o
);
reg [NUM_BITS - 1:0] r_comp;
reg [2:0] r_comp_op;
reg r_value;
wire r_active;
reg r_is_2nd_event;
wire s_match;
wire s_2nd_event;
assign s_match = timer_valid_i & (r_comp == timer_count_i);
assign s_2nd_event = timer_sawtooth_i ? timer_end_i : s_match;
assign result_o = r_value;
always @(posedge clk_i or negedge rstn_i) begin : proc_r_comp
if (~rstn_i) begin
r_comp <= 0;
r_comp_op <= 0;
end else if (ctrl_update_i) begin //if first enable or explicit update is iven
r_comp <= cfg_comp_i;
r_comp_op <= cfg_comp_op_i;
end
end
always @(posedge clk_i or negedge rstn_i) begin : proc_r_value
if (~rstn_i) begin
r_value <= 0;
r_is_2nd_event <= 1'b0;
end else if (ctrl_rst_i) begin
r_value <= 1'b0;
r_is_2nd_event <= 1'b0;
end else if (timer_valid_i && ctrl_active_i) begin
case(r_comp_op)
`OP_SET:
r_value <= s_match ? 1'b1 : r_value;
`OP_TOGRST:
begin
if(timer_sawtooth_i) begin
if(s_match)
r_value <= ~r_value;
else if(s_2nd_event)
r_value <= 1'b0;
end else begin
if(s_match && !r_is_2nd_event) begin
r_value <= ~r_value;
r_is_2nd_event <= 1'b1;
end else if(s_match && r_is_2nd_event) begin
r_value <= 1'b0;
r_is_2nd_event <= 1'b0;
end
end
end
`OP_SETRST:
begin
if(timer_sawtooth_i) begin
if(s_match)
r_value <= 1'b1;
else if(s_2nd_event)
r_value <= 1'b0;
end else begin
if(s_match && !r_is_2nd_event) begin
r_value <= 1'b1;
r_is_2nd_event <= 1'b1;
end else if(s_match && r_is_2nd_event) begin
r_value <= 1'b0;
r_is_2nd_event <= 1'b0;
end
end
end
`OP_TOG:
r_value <= s_match ? ~r_value : r_value;
`OP_RST:
r_value <= s_match ? 1'b0 : r_value;
`OP_TOGSET:
begin
if(timer_sawtooth_i) begin
if(s_match)
r_value <= ~r_value;
else if(s_2nd_event)
r_value <= 1'b1;
end else begin
if(s_match && !r_is_2nd_event) begin
r_value <= ~r_value;
r_is_2nd_event <= 1'b1;
end else if(s_match && r_is_2nd_event) begin
r_value <= 1'b1;
r_is_2nd_event <= 1'b0;
end
end
end
`OP_RSTSET:
begin
if(timer_sawtooth_i) begin
if(s_match)
r_value <= 1'b0;
else if(s_2nd_event)
r_value <= 1'b1;
end else begin
if(s_match && !r_is_2nd_event) begin
r_value <= 1'b0;
r_is_2nd_event <= 1'b1;
end else if(s_match && r_is_2nd_event) begin
r_value <= 1'b1;
r_is_2nd_event <= 1'b0;
end
end
end
default:
begin
r_value <= r_value;
r_is_2nd_event <= 1'b0;
end
endcase // r_comp_op
end
end
endmodule |
module apb_gpio
#(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
)
(
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
input wire [31:0] gpio_in,
output wire [31:0] gpio_in_sync,
output wire [31:0] gpio_out,
output wire [31:0] gpio_dir,
output reg [191:0] gpio_padcfg,
output wire [31:0] gpio_iof,
output reg interrupt
);
reg [31:0] r_gpio_inten;
reg [31:0] r_gpio_inttype0;
reg [31:0] r_gpio_inttype1;
reg [31:0] r_gpio_out;
reg [31:0] r_gpio_dir;
reg [31:0] r_gpio_sync0;
reg [31:0] r_gpio_sync1;
reg [31:0] r_gpio_in;
reg [31:0] r_iofcfg;
wire [31:0] s_gpio_rise;
wire [31:0] s_gpio_fall;
wire [31:0] s_is_int_rise;
wire [31:0] s_is_int_fall;
wire [31:0] s_is_int_lev0;
wire [31:0] s_is_int_lev1;
wire [31:0] s_is_int_all;
wire s_rise_int;
wire [3:0] s_apb_addr;
reg [31:0] r_status;
assign s_apb_addr = PADDR[5:2];
assign gpio_in_sync = r_gpio_sync1;
assign s_gpio_rise = r_gpio_sync1 & ~r_gpio_in; //foreach input check if rising edge
assign s_gpio_fall = ~r_gpio_sync1 & r_gpio_in; //foreach input check if falling edge
assign s_is_int_rise = (r_gpio_inttype1 & ~r_gpio_inttype0) & s_gpio_rise; // inttype 01 rise
assign s_is_int_fall = (r_gpio_inttype1 & r_gpio_inttype0) & s_gpio_fall; // inttype 00 fall
assign s_is_int_lev0 = (~r_gpio_inttype1 & r_gpio_inttype0) & ~r_gpio_in; // inttype 10 level 0
assign s_is_int_lev1 = (~r_gpio_inttype1 & ~r_gpio_inttype0) & r_gpio_in; // inttype 11 level 1
//check if bit if interrupt is enable and if interrupt specified by inttype occurred
assign s_is_int_all = r_gpio_inten & (((s_is_int_rise | s_is_int_fall) | s_is_int_lev0) | s_is_int_lev1);
//is any bit enabled and specified interrupt happened?
assign s_rise_int = |s_is_int_all;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
interrupt <= 1'b0;
r_status <= 'h0;
end else if (!interrupt && s_rise_int) begin //rise interrupt if not already rise
interrupt <= 1'b1;
r_status <= s_is_int_all;
end else if ((((interrupt && PSEL) && PENABLE) && !PWRITE) && (s_apb_addr == `REG_INTSTATUS)) begin //clears int if status is read
interrupt <= 1'b0;
r_status <= 'h0;
end
end
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
r_gpio_sync0 <= 'h0;
r_gpio_sync1 <= 'h0;
r_gpio_in <= 'h0;
end else begin
r_gpio_sync0 <= gpio_in; //first 2 sync for metastability resolving
r_gpio_sync1 <= r_gpio_sync0;
r_gpio_in <= r_gpio_sync1; //last reg used for edge detection
end
end
integer i;
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
r_gpio_inten <= 'b0;
r_gpio_inttype0 <= 'b0;
r_gpio_inttype1 <= 'b0;
r_gpio_out <= 'b0;
r_gpio_dir <= 'b0;
r_iofcfg <= 'b0;
for (i = 0; i < 32; i = i + 1)
gpio_padcfg[i * 6+:6] <= 6'b000010;
end else if ((PSEL && PENABLE) && PWRITE) begin
case (s_apb_addr)
`REG_PADDIR: r_gpio_dir <= PWDATA;
`REG_PADOUT: r_gpio_out <= PWDATA;
`REG_INTEN: r_gpio_inten <= PWDATA;
`REG_INTTYPE0: r_gpio_inttype0 <= PWDATA;
`REG_INTTYPE1: r_gpio_inttype1 <= PWDATA;
`REG_IOFCFG: r_iofcfg <= PWDATA;
`REG_PADCFG0: begin
gpio_padcfg[0+:6] <= PWDATA[5:0];
gpio_padcfg[6+:6] <= PWDATA[13:8];
gpio_padcfg[12+:6] <= PWDATA[21:16];
gpio_padcfg[18+:6] <= PWDATA[29:24];
end
`REG_PADCFG1: begin
gpio_padcfg[24+:6] <= PWDATA[5:0];
gpio_padcfg[30+:6] <= PWDATA[13:8];
gpio_padcfg[36+:6] <= PWDATA[21:16];
gpio_padcfg[42+:6] <= PWDATA[29:24];
end
`REG_PADCFG2: begin
gpio_padcfg[48+:6] <= PWDATA[5:0];
gpio_padcfg[54+:6] <= PWDATA[13:8];
gpio_padcfg[60+:6] <= PWDATA[21:16];
gpio_padcfg[66+:6] <= PWDATA[29:24];
end
`REG_PADCFG3: begin
gpio_padcfg[72+:6] <= PWDATA[5:0];
gpio_padcfg[78+:6] <= PWDATA[13:8];
gpio_padcfg[84+:6] <= PWDATA[21:16];
gpio_padcfg[90+:6] <= PWDATA[29:24];
end
`REG_PADCFG4: begin
gpio_padcfg[96+:6] <= PWDATA[5:0];
gpio_padcfg[102+:6] <= PWDATA[13:8];
gpio_padcfg[108+:6] <= PWDATA[21:16];
gpio_padcfg[114+:6] <= PWDATA[29:24];
end
`REG_PADCFG5: begin
gpio_padcfg[120+:6] <= PWDATA[5:0];
gpio_padcfg[126+:6] <= PWDATA[13:8];
gpio_padcfg[132+:6] <= PWDATA[21:16];
gpio_padcfg[138+:6] <= PWDATA[29:24];
end
`REG_PADCFG6: begin
gpio_padcfg[144+:6] <= PWDATA[5:0];
gpio_padcfg[150+:6] <= PWDATA[13:8];
gpio_padcfg[156+:6] <= PWDATA[21:16];
gpio_padcfg[162+:6] <= PWDATA[29:24];
end
`REG_PADCFG7: begin
gpio_padcfg[168+:6] <= PWDATA[5:0];
gpio_padcfg[174+:6] <= PWDATA[13:8];
gpio_padcfg[180+:6] <= PWDATA[21:16];
gpio_padcfg[186+:6] <= PWDATA[29:24];
end
endcase
end
end
always @(*) begin
case (s_apb_addr)
`REG_PADDIR: PRDATA = r_gpio_dir;
`REG_PADIN: PRDATA = r_gpio_in;
`REG_PADOUT: PRDATA = r_gpio_out;
`REG_INTEN: PRDATA = r_gpio_inten;
`REG_INTTYPE0: PRDATA = r_gpio_inttype0;
`REG_INTTYPE1: PRDATA = r_gpio_inttype1;
`REG_INTSTATUS: PRDATA = r_status;
`REG_IOFCFG: PRDATA = r_iofcfg;
`REG_PADCFG0: PRDATA = {2'b00, gpio_padcfg[18+:6], 2'b00, gpio_padcfg[12+:6], 2'b00, gpio_padcfg[6+:6], 2'b00, gpio_padcfg[0+:6]};
`REG_PADCFG1: PRDATA = {2'b00, gpio_padcfg[42+:6], 2'b00, gpio_padcfg[36+:6], 2'b00, gpio_padcfg[30+:6], 2'b00, gpio_padcfg[24+:6]};
`REG_PADCFG2: PRDATA = {2'b00, gpio_padcfg[66+:6], 2'b00, gpio_padcfg[60+:6], 2'b00, gpio_padcfg[54+:6], 2'b00, gpio_padcfg[48+:6]};
`REG_PADCFG3: PRDATA = {2'b00, gpio_padcfg[90+:6], 2'b00, gpio_padcfg[84+:6], 2'b00, gpio_padcfg[78+:6], 2'b00, gpio_padcfg[72+:6]};
`REG_PADCFG4: PRDATA = {2'b00, gpio_padcfg[114+:6], 2'b00, gpio_padcfg[108+:6], 2'b00, gpio_padcfg[102+:6], 2'b00, gpio_padcfg[96+:6]};
`REG_PADCFG5: PRDATA = {2'b00, gpio_padcfg[138+:6], 2'b00, gpio_padcfg[132+:6], 2'b00, gpio_padcfg[126+:6], 2'b00, gpio_padcfg[120+:6]};
`REG_PADCFG6: PRDATA = {2'b00, gpio_padcfg[162+:6], 2'b00, gpio_padcfg[156+:6], 2'b00, gpio_padcfg[150+:6], 2'b00, gpio_padcfg[144+:6]};
`REG_PADCFG7: PRDATA = {2'b00, gpio_padcfg[186+:6], 2'b00, gpio_padcfg[180+:6], 2'b00, gpio_padcfg[174+:6], 2'b00, gpio_padcfg[168+:6]};
default: PRDATA = 'h0;
endcase
end
assign gpio_iof = r_iofcfg;
assign gpio_out = r_gpio_out;
assign gpio_dir = r_gpio_dir;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule |
module i2c_master_bit_ctrl
(
input clk, // system clock
input nReset, // asynchronous active low reset
input ena, // core enable signal
input [15:0] clk_cnt, // clock prescale value
input [ 3:0] cmd, // command (from byte controller)
output reg cmd_ack, // command complete acknowledge
output reg busy, // i2c bus busy
output reg al, // i2c bus arbitration lost
input din,
output reg dout,
input scl_i, // i2c clock line input
output scl_o, // i2c clock line output
output reg scl_oen, // i2c clock line output enable (active low)
input sda_i, // i2c data line input
output sda_o, // i2c data line output
output reg sda_oen // i2c data line output enable (active low)
);
//
// variable declarations
//
reg [ 1:0] cSCL, cSDA; // capture SCL and SDA
reg [ 2:0] fSCL, fSDA; // SCL and SDA filter inputs
reg sSCL, sSDA; // filtered and synchronized SCL and SDA inputs
reg dSCL, dSDA; // delayed versions of sSCL and sSDA
reg dscl_oen; // delayed scl_oen
reg sda_chk; // check SDA output (Multi-master arbitration)
reg clk_en; // clock generation signals
reg slave_wait; // slave inserts wait states
reg [15:0] cnt; // clock divider counter (synthesis)
reg [13:0] filter_cnt; // clock divider for filter
// state machine variable
reg [17:0] c_state;
//
// module body
//
// whenever the slave is not ready it can delay the cycle by pulling SCL low
// delay scl_oen
always @(posedge clk)
dscl_oen <= scl_oen;
// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
// slave_wait remains asserted until the slave releases SCL
always @(posedge clk or negedge nReset)
if (!nReset) slave_wait <= 1'b0;
else slave_wait <= (scl_oen & ~dscl_oen & ~sSCL) | (slave_wait & ~sSCL);
// master drives SCL high, but another master pulls it low
// master start counting down its low cycle now (clock synchronization)
wire scl_sync = dSCL & ~sSCL & scl_oen;
// generate clk enable signal
always @(posedge clk or negedge nReset)
if (~nReset)
begin
cnt <= 16'h0;
clk_en <= 1'b1;
end
else if (~|cnt || !ena || scl_sync)
begin
cnt <= clk_cnt;
clk_en <= 1'b1;
end
else if (slave_wait)
begin
cnt <= cnt;
clk_en <= 1'b0;
end
else
begin
cnt <= cnt - 16'h1;
clk_en <= 1'b0;
end
// generate bus status controller
// capture SDA and SCL
// reduce metastability risk
always @(posedge clk or negedge nReset)
if (!nReset)
begin
cSCL <= 2'b00;
cSDA <= 2'b00;
end
else
begin
cSCL <= {cSCL[0],scl_i};
cSDA <= {cSDA[0],sda_i};
end
// filter SCL and SDA signals; (attempt to) remove glitches
always @(posedge clk or negedge nReset)
if (!nReset ) filter_cnt <= 14'h0;
else if (!ena ) filter_cnt <= 14'h0;
else if (~|filter_cnt) filter_cnt <= clk_cnt >> 2; //16x I2C bus frequency
else filter_cnt <= filter_cnt -1;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
fSCL <= 3'b111;
fSDA <= 3'b111;
end
else if (~|filter_cnt)
begin
fSCL <= {fSCL[1:0],cSCL[1]};
fSDA <= {fSDA[1:0],cSDA[1]};
end
// generate filtered SCL and SDA signals
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sSCL <= 1'b1;
sSDA <= 1'b1;
dSCL <= 1'b1;
dSDA <= 1'b1;
end
else
begin
sSCL <= &fSCL[2:1] | &fSCL[1:0] | (fSCL[2] & fSCL[0]);
sSDA <= &fSDA[2:1] | &fSDA[1:0] | (fSDA[2] & fSDA[0]);
dSCL <= sSCL;
dSDA <= sSDA;
end
// detect start condition => detect falling edge on SDA while SCL is high
// detect stop condition => detect rising edge on SDA while SCL is high
reg sta_condition;
reg sto_condition;
always @(posedge clk or negedge nReset)
if (~nReset)
begin
sta_condition <= 1'b0;
sto_condition <= 1'b0;
end
else
begin
sta_condition <= ~sSDA & dSDA & sSCL;
sto_condition <= sSDA & ~dSDA & sSCL;
end
// generate i2c bus busy signal
always @(posedge clk or negedge nReset)
if (!nReset) busy <= 1'b0;
else busy <= (sta_condition | busy) & ~sto_condition;
// generate arbitration lost signal
// aribitration lost when:
// 1) master drives SDA high, but the i2c bus is low
// 2) stop detected while not requested
reg cmd_stop;
always @(posedge clk or negedge nReset)
if (~nReset)
cmd_stop <= 1'b0;
else if (clk_en)
cmd_stop <= cmd == `I2C_CMD_STOP;
always @(posedge clk or negedge nReset)
if (~nReset)
al <= 1'b0;
else
al <= (sda_chk & ~sSDA & sda_oen) | (|c_state & sto_condition & ~cmd_stop);
// generate dout signal (store SDA on rising edge of SCL)
always @(posedge clk)
if (sSCL & ~dSCL) dout <= sSDA;
// generate statemachine
// nxt_state decoder
parameter [17:0] idle = 18'b0_0000_0000_0000_0000;
parameter [17:0] start_a = 18'b0_0000_0000_0000_0001;
parameter [17:0] start_b = 18'b0_0000_0000_0000_0010;
parameter [17:0] start_c = 18'b0_0000_0000_0000_0100;
parameter [17:0] start_d = 18'b0_0000_0000_0000_1000;
parameter [17:0] start_e = 18'b0_0000_0000_0001_0000;
parameter [17:0] stop_a = 18'b0_0000_0000_0010_0000;
parameter [17:0] stop_b = 18'b0_0000_0000_0100_0000;
parameter [17:0] stop_c = 18'b0_0000_0000_1000_0000;
parameter [17:0] stop_d = 18'b0_0000_0001_0000_0000;
parameter [17:0] rd_a = 18'b0_0000_0010_0000_0000;
parameter [17:0] rd_b = 18'b0_0000_0100_0000_0000;
parameter [17:0] rd_c = 18'b0_0000_1000_0000_0000;
parameter [17:0] rd_d = 18'b0_0001_0000_0000_0000;
parameter [17:0] wr_a = 18'b0_0010_0000_0000_0000;
parameter [17:0] wr_b = 18'b0_0100_0000_0000_0000;
parameter [17:0] wr_c = 18'b0_1000_0000_0000_0000;
parameter [17:0] wr_d = 18'b1_0000_0000_0000_0000;
always @(posedge clk or negedge nReset)
if (!nReset)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen <= 1'b1;
sda_oen <= 1'b1;
sda_chk <= 1'b0;
end
else if (al)
begin
c_state <= idle;
cmd_ack <= 1'b0;
scl_oen <= 1'b1;
sda_oen <= 1'b1;
sda_chk <= 1'b0;
end
else
begin
cmd_ack <= 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
if (clk_en)
case (c_state) // synopsys full_case parallel_case
// idle state
idle:
begin
case (cmd) // synopsys full_case parallel_case
`I2C_CMD_START: c_state <= start_a;
`I2C_CMD_STOP: c_state <= stop_a;
`I2C_CMD_WRITE: c_state <= wr_a;
`I2C_CMD_READ: c_state <= rd_a;
default: c_state <= idle;
endcase
scl_oen <= scl_oen; // keep SCL in same state
sda_oen <= sda_oen; // keep SDA in same state
sda_chk <= 1'b0; // don't check SDA output
end
// start
start_a:
begin
c_state <= start_b;
scl_oen <= scl_oen; // keep SCL in same state
sda_oen <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_b:
begin
c_state <= start_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b1; // keep SDA high
sda_chk <= 1'b0; // don't check SDA output
end
start_c:
begin
c_state <= start_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_d:
begin
c_state <= start_e;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
start_e:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
// stop
stop_a:
begin
c_state <= stop_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= 1'b0; // set SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_b:
begin
c_state <= stop_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_c:
begin
c_state <= stop_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b0; // keep SDA low
sda_chk <= 1'b0; // don't check SDA output
end
stop_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b1; // set SDA high
sda_chk <= 1'b0; // don't check SDA output
end
// read
rd_a:
begin
c_state <= rd_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= 1'b1; // tri-state SDA
sda_chk <= 1'b0; // don't check SDA output
end
rd_b:
begin
c_state <= rd_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_c:
begin
c_state <= rd_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
rd_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= 1'b1; // keep SDA tri-stated
sda_chk <= 1'b0; // don't check SDA output
end
// write
wr_a:
begin
c_state <= wr_b;
scl_oen <= 1'b0; // keep SCL low
sda_oen <= din; // set SDA
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
wr_b:
begin
c_state <= wr_c;
scl_oen <= 1'b1; // set SCL high
sda_oen <= din; // keep SDA
sda_chk <= 1'b0; // don't check SDA output yet
// allow some time for SDA and SCL to settle
end
wr_c:
begin
c_state <= wr_d;
scl_oen <= 1'b1; // keep SCL high
sda_oen <= din;
sda_chk <= 1'b1; // check SDA output
end
wr_d:
begin
c_state <= idle;
cmd_ack <= 1'b1;
scl_oen <= 1'b0; // set SCL low
sda_oen <= din;
sda_chk <= 1'b0; // don't check SDA output (SCL low)
end
endcase
end
//FIXME ANTONIO CHECK
// assign scl and sda output (always gnd)
assign scl_o = 1'b0;
assign sda_o = 1'b0;
endmodule |
module apb_i2c
#(
parameter APB_ADDR_WIDTH = 12 //APB slaves are 4KB by default
)
(
input wire HCLK,
input wire HRESETn,
input wire [APB_ADDR_WIDTH - 1:0] PADDR,
input wire [31:0] PWDATA,
input wire PWRITE,
input wire PSEL,
input wire PENABLE,
output reg [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output reg interrupt_o,
input wire scl_pad_i,
output wire scl_pad_o,
output wire scl_padoen_o,
input wire sda_pad_i,
output wire sda_pad_o,
output wire sda_padoen_o
);
//
// variable declarations
//
wire [3:0] s_apb_addr;
// registers
reg [15:0] r_pre; // clock prescale register
reg [7:0] r_ctrl; // control register
reg [7:0] r_tx; // transmit register
wire [7:0] s_rx; // receive register
reg [7:0] r_cmd; // command register
wire [7:0] s_status; // status register
// done signal: command completed, clear command register
wire s_done;
// core enable signal
wire s_core_en;
wire s_ien;
// status register signals
wire s_irxack;
reg rxack; // received aknowledge from slave
reg tip; // transfer in progress
reg irq_flag; // interrupt pending flag
wire i2c_busy; // bus busy (start signal detected)
wire i2c_al; // i2c bus arbitration lost
reg al; // status register arbitration lost bit
//
// module body
//
assign s_apb_addr = PADDR[5:2];
always @(posedge HCLK or negedge HRESETn) begin
if (~HRESETn) begin
r_pre <= 'h0;
r_ctrl <= 'h0;
r_tx <= 'h0;
r_cmd <= 'h0;
end else if (PSEL && PENABLE && PWRITE) begin
if (s_done | i2c_al)
r_cmd[7:4] <= 4'h0; // clear command bits when done
// or when aribitration lost
r_cmd[2:1] <= 2'b00; // reserved bits
r_cmd[0] <= 1'b0; // clear IRQ_ACK bit
case (s_apb_addr)
`I2C_REG_CLK_PRESCALER: r_pre <= PWDATA[15:0];
`I2C_REG_CTRL: r_ctrl <= PWDATA[7:0];
`I2C_REG_TX: r_tx <= PWDATA[7:0];
`I2C_REG_CMD:
if (s_core_en)
r_cmd <= PWDATA[7:0];
endcase
end else begin
if (s_done | i2c_al)
r_cmd[7:4] <= 4'h0; // clear command bits when done
// or when aribitration lost
r_cmd[2:1] <= 2'b00; // reserved bits
r_cmd[0] <= 1'b0; // clear IRQ_ACK bit
end
end
always @(*) begin
case (s_apb_addr)
`I2C_REG_CLK_PRESCALER: PRDATA = {16'h0, r_pre};
`I2C_REG_CTRL: PRDATA = {24'h0, r_ctrl};
`I2C_REG_RX: PRDATA = {24'h0, s_rx};
`I2C_REG_STATUS: PRDATA = {24'h0, s_status};
`I2C_REG_TX: PRDATA = {24'h0, r_tx};
`I2C_REG_CMD: PRDATA = {24'h0, r_cmd};
default: PRDATA = 'h0;
endcase
end
// decode command register
wire sta = r_cmd[7];
wire sto = r_cmd[6];
wire rd = r_cmd[5];
wire wr = r_cmd[4];
wire ack = r_cmd[3];
wire iack = r_cmd[0];
// decode control register
assign s_core_en = r_ctrl[7];
assign s_ien = r_ctrl[6];
// hookup byte controller block
i2c_master_byte_ctrl byte_controller (
.clk ( HCLK ),
.nReset ( HRESETn ),
.ena ( s_core_en ),
.clk_cnt ( r_pre ),
.start ( sta ),
.stop ( sto ),
.read ( rd ),
.write ( wr ),
.ack_in ( ack ),
.din ( r_tx ),
.cmd_ack ( s_done ),
.ack_out ( s_irxack ),
.dout ( s_rx ),
.i2c_busy ( i2c_busy ),
.i2c_al ( i2c_al ),
.scl_i ( scl_pad_i ),
.scl_o ( scl_pad_o ),
.scl_oen ( scl_padoen_o ),
.sda_i ( sda_pad_i ),
.sda_o ( sda_pad_o ),
.sda_oen ( sda_padoen_o )
);
// status register block + interrupt request signal
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn) begin
al <= 1'b0;
rxack <= 1'b0;
tip <= 1'b0;
irq_flag <= 1'b0;
end else begin
al <= i2c_al | (al & ~sta);
rxack <= s_irxack;
tip <= rd | wr;
irq_flag <= ((s_done | i2c_al) | irq_flag) & ~iack; // interrupt request flag is always generated
end
end
// generate interrupt request signals
always @(posedge HCLK or negedge HRESETn) begin
if (!HRESETn)
interrupt_o <= 1'b0;
else
interrupt_o <= irq_flag && s_ien; // interrupt signal is only generated when IEN (interrupt enable bit is set)
end
// assign status register bits
assign s_status[7] = rxack;
assign s_status[6] = i2c_busy;
assign s_status[5] = al;
assign s_status[4:2] = 3'h0; // reserved
assign s_status[1] = tip;
assign s_status[0] = irq_flag;
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
endmodule |
module system
(
input wire CLK100MHZ,//GCLK-W19
input wire CLK32768KHZ,//RTC_CLK-Y18
input wire fpga_rst,//FPGA_RESET-T6
input wire mcu_rst,//MCU_RESET-P20
// Dedicated QSPI interface
output wire qspi0_cs,
output wire qspi0_sck,
inout wire [3:0] qspi0_dq,
//gpioA
inout wire [31:0] gpioA,//GPIOA00~GPIOA31
//gpioB
inout wire [31:0] gpioB,//GPIOB00~GPIOB31
// JD (used for JTAG connection)
inout wire mcu_TDO,//MCU_TDO-N17
inout wire mcu_TCK,//MCU_TCK-P15
inout wire mcu_TDI,//MCU_TDI-T18
inout wire mcu_TMS,//MCU_TMS-P17
//pmu_wakeup
inout wire pmu_paden, //PMU_VDDPADEN-U15
inout wire pmu_padrst, //PMU_VADDPARST_V15
inout wire mcu_wakeup //MCU_WAKE-N15
);
wire clk_out1;
wire mmcm_locked;
wire reset_periph;
wire ck_rst;
// All wires connected to the chip top
wire dut_clock;
wire dut_reset;
wire dut_io_pads_jtag_TCK_i_ival;
wire dut_io_pads_jtag_TMS_i_ival;
wire dut_io_pads_jtag_TMS_o_oval;
wire dut_io_pads_jtag_TMS_o_oe;
wire dut_io_pads_jtag_TMS_o_ie;
wire dut_io_pads_jtag_TMS_o_pue;
wire dut_io_pads_jtag_TMS_o_ds;
wire dut_io_pads_jtag_TDI_i_ival;
wire dut_io_pads_jtag_TDO_o_oval;
wire dut_io_pads_jtag_TDO_o_oe;
wire [32-1:0] dut_io_pads_gpioA_i_ival;
wire [32-1:0] dut_io_pads_gpioA_o_oval;
wire [32-1:0] dut_io_pads_gpioA_o_oe;
wire [32-1:0] dut_io_pads_gpioB_i_ival;
wire [32-1:0] dut_io_pads_gpioB_o_oval;
wire [32-1:0] dut_io_pads_gpioB_o_oe;
wire dut_io_pads_qspi0_sck_o_oval;
wire dut_io_pads_qspi0_cs_0_o_oval;
wire dut_io_pads_qspi0_dq_0_i_ival;
wire dut_io_pads_qspi0_dq_0_o_oval;
wire dut_io_pads_qspi0_dq_0_o_oe;
wire dut_io_pads_qspi0_dq_1_i_ival;
wire dut_io_pads_qspi0_dq_1_o_oval;
wire dut_io_pads_qspi0_dq_1_o_oe;
wire dut_io_pads_qspi0_dq_2_i_ival;
wire dut_io_pads_qspi0_dq_2_o_oval;
wire dut_io_pads_qspi0_dq_2_o_oe;
wire dut_io_pads_qspi0_dq_3_i_ival;
wire dut_io_pads_qspi0_dq_3_o_oval;
wire dut_io_pads_qspi0_dq_3_o_oe;
wire dut_io_pads_aon_erst_n_i_ival;
wire dut_io_pads_aon_pmu_dwakeup_n_i_ival;
wire dut_io_pads_aon_pmu_vddpaden_o_oval;
wire dut_io_pads_aon_pmu_padrst_o_oval ;
wire dut_io_pads_bootrom_n_i_ival;
wire dut_io_pads_dbgmode0_n_i_ival;
wire dut_io_pads_dbgmode1_n_i_ival;
wire dut_io_pads_dbgmode2_n_i_ival;
//=================================================
// Clock & Reset
wire clk_8388;
wire clk_16M;
mmcm ip_mmcm
(
.resetn(ck_rst),
.clk_in1(CLK100MHZ),
.clk_out2(clk_16M), // 16 MHz, this clock we set to 16MHz
.locked(mmcm_locked)
);
assign ck_rst = fpga_rst & mcu_rst;
reset_sys ip_reset_sys
(
.slowest_sync_clk(clk_16M),
.ext_reset_in(ck_rst), // Active-low
.aux_reset_in(1'b1),
.mb_debug_sys_rst(1'b0),
.dcm_locked(mmcm_locked),
.mb_reset(),
.bus_struct_reset(),
.peripheral_reset(reset_periph),
.interconnect_aresetn(),
.peripheral_aresetn()
);
//=================================================
// SPI0 Interface
wire [3:0] qspi0_ui_dq_o;
wire [3:0] qspi0_ui_dq_oe;
wire [3:0] qspi0_ui_dq_i;
PULLUP qspi0_pullup[3:0]
(
.O(qspi0_dq)
);
IOBUF qspi0_iobuf[3:0]
(
.IO(qspi0_dq),
.O(qspi0_ui_dq_i),
.I(qspi0_ui_dq_o),
.T(~qspi0_ui_dq_oe)
);
//=================================================
// IOBUF instantiation for GPIOs
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
gpioA_iobuf[31:0]
(
.O(dut_io_pads_gpioA_i_ival),
.IO(gpioA),
.I(dut_io_pads_gpioA_o_oval),
.T(~dut_io_pads_gpioA_o_oe)
);
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
gpioB_iobuf[31:0]
(
.O(dut_io_pads_gpioB_i_ival),
.IO(gpioB),
.I(dut_io_pads_gpioB_o_oval),
.T(~dut_io_pads_gpioB_o_oe)
);
//=================================================
// JTAG IOBUFs
wire iobuf_jtag_TCK_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TCK
(
.O(iobuf_jtag_TCK_o),
.IO(mcu_TCK),
.I(1'b0),
.T(1'b1)
);
assign dut_io_pads_jtag_TCK_i_ival = iobuf_jtag_TCK_o ;
PULLUP pullup_TCK (.O(mcu_TCK));
wire iobuf_jtag_TMS_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TMS
(
.O(iobuf_jtag_TMS_o),
.IO(mcu_TMS),
.I(1'b0),
.T(1'b1)
);
assign dut_io_pads_jtag_TMS_i_ival = iobuf_jtag_TMS_o;
PULLUP pullup_TMS (.O(mcu_TMS));
wire iobuf_jtag_TDI_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDI
(
.O(iobuf_jtag_TDI_o),
.IO(mcu_TDI),
.I(1'b0),
.T(1'b1)
);
assign dut_io_pads_jtag_TDI_i_ival = iobuf_jtag_TDI_o;
PULLUP pullup_TDI (.O(mcu_TDI));
wire iobuf_jtag_TDO_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_jtag_TDO
(
.O(iobuf_jtag_TDO_o),
.IO(mcu_TDO),
.I(dut_io_pads_jtag_TDO_o_oval),
.T(~dut_io_pads_jtag_TDO_o_oe)
);
//wire iobuf_jtag_TRST_n_o;
//IOBUF
//#(
// .DRIVE(12),
// .IBUF_LOW_PWR("TRUE"),
// .IOSTANDARD("DEFAULT"),
// .SLEW("SLOW")
//)
//=================================================
// Assignment of IOBUF "IO" pins to package pins
// Pins IO0-IO13
// Shield header row 0: PD0-PD7
// Use the LEDs for some more useful debugging things.
assign pmu_paden = dut_io_pads_aon_pmu_vddpaden_o_oval;
assign pmu_padrst = dut_io_pads_aon_pmu_padrst_o_oval;
// model select
assign dut_io_pads_bootrom_n_i_ival = 1'b1; //
assign dut_io_pads_dbgmode0_n_i_ival = 1'b1;
assign dut_io_pads_dbgmode1_n_i_ival = 1'b1;
assign dut_io_pads_dbgmode2_n_i_ival = 1'b1;
//
e203_soc_top dut
(
.hfextclk(clk_16M),
.hfxoscen(),
.lfextclk(CLK32768KHZ),
.lfxoscen(),
// Note: this is the real SoC top AON domain slow clock
.io_pads_jtag_TCK_i_ival(dut_io_pads_jtag_TCK_i_ival),
.io_pads_jtag_TMS_i_ival(dut_io_pads_jtag_TMS_i_ival),
.io_pads_jtag_TDI_i_ival(dut_io_pads_jtag_TDI_i_ival),
.io_pads_jtag_TDO_o_oval(dut_io_pads_jtag_TDO_o_oval),
.io_pads_jtag_TDO_o_oe (dut_io_pads_jtag_TDO_o_oe),
.io_pads_gpioA_i_ival(dut_io_pads_gpioA_i_ival),
.io_pads_gpioA_o_oval(dut_io_pads_gpioA_o_oval),
.io_pads_gpioA_o_oe (dut_io_pads_gpioA_o_oe),
.io_pads_gpioB_i_ival(dut_io_pads_gpioB_i_ival),
.io_pads_gpioB_o_oval(dut_io_pads_gpioB_o_oval),
.io_pads_gpioB_o_oe (dut_io_pads_gpioB_o_oe),
.io_pads_qspi0_sck_o_oval (dut_io_pads_qspi0_sck_o_oval),
.io_pads_qspi0_cs_0_o_oval(dut_io_pads_qspi0_cs_0_o_oval),
.io_pads_qspi0_dq_0_i_ival(dut_io_pads_qspi0_dq_0_i_ival),
.io_pads_qspi0_dq_0_o_oval(dut_io_pads_qspi0_dq_0_o_oval),
.io_pads_qspi0_dq_0_o_oe (dut_io_pads_qspi0_dq_0_o_oe),
.io_pads_qspi0_dq_1_i_ival(dut_io_pads_qspi0_dq_1_i_ival),
.io_pads_qspi0_dq_1_o_oval(dut_io_pads_qspi0_dq_1_o_oval),
.io_pads_qspi0_dq_1_o_oe (dut_io_pads_qspi0_dq_1_o_oe),
.io_pads_qspi0_dq_2_i_ival(dut_io_pads_qspi0_dq_2_i_ival),
.io_pads_qspi0_dq_2_o_oval(dut_io_pads_qspi0_dq_2_o_oval),
.io_pads_qspi0_dq_2_o_oe (dut_io_pads_qspi0_dq_2_o_oe),
.io_pads_qspi0_dq_3_i_ival(dut_io_pads_qspi0_dq_3_i_ival),
.io_pads_qspi0_dq_3_o_oval(dut_io_pads_qspi0_dq_3_o_oval),
.io_pads_qspi0_dq_3_o_oe (dut_io_pads_qspi0_dq_3_o_oe),
// Note: this is the real SoC top level reset signal
.io_pads_aon_erst_n_i_ival(ck_rst),
.io_pads_aon_pmu_dwakeup_n_i_ival(dut_io_pads_aon_pmu_dwakeup_n_i_ival),
.io_pads_aon_pmu_vddpaden_o_oval(dut_io_pads_aon_pmu_vddpaden_o_oval),
.io_pads_aon_pmu_padrst_o_oval (dut_io_pads_aon_pmu_padrst_o_oval ),
.io_pads_bootrom_n_i_ival (dut_io_pads_bootrom_n_i_ival),
.io_pads_dbgmode0_n_i_ival (dut_io_pads_dbgmode0_n_i_ival),
.io_pads_dbgmode1_n_i_ival (dut_io_pads_dbgmode1_n_i_ival),
.io_pads_dbgmode2_n_i_ival (dut_io_pads_dbgmode2_n_i_ival)
);
// Assign reasonable values to otherwise unconnected inputs to chip top
wire iobuf_dwakeup_o;
IOBUF
#(
.DRIVE(12),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("DEFAULT"),
.SLEW("SLOW")
)
IOBUF_dwakeup_n
(
.O(iobuf_dwakeup_o),
.IO(mcu_wakeup),
.I(1'b1),
.T(1'b1)
);
assign dut_io_pads_aon_pmu_dwakeup_n_i_ival = (~iobuf_dwakeup_o);
assign dut_io_pads_aon_pmu_vddpaden_i_ival = 1'b1;
assign qspi0_sck = dut_io_pads_qspi0_sck_o_oval;
assign qspi0_cs = dut_io_pads_qspi0_cs_0_o_oval;
assign qspi0_ui_dq_o = {
dut_io_pads_qspi0_dq_3_o_oval,
dut_io_pads_qspi0_dq_2_o_oval,
dut_io_pads_qspi0_dq_1_o_oval,
dut_io_pads_qspi0_dq_0_o_oval
};
assign qspi0_ui_dq_oe = {
dut_io_pads_qspi0_dq_3_o_oe,
dut_io_pads_qspi0_dq_2_o_oe,
dut_io_pads_qspi0_dq_1_o_oe,
dut_io_pads_qspi0_dq_0_o_oe
};
assign dut_io_pads_qspi0_dq_0_i_ival = qspi0_ui_dq_i[0];
assign dut_io_pads_qspi0_dq_1_i_ival = qspi0_ui_dq_i[1];
assign dut_io_pads_qspi0_dq_2_i_ival = qspi0_ui_dq_i[2];
assign dut_io_pads_qspi0_dq_3_i_ival = qspi0_ui_dq_i[3];
endmodule |
module ram_2p_wrapper #(
parameter RAM_TYPE = -1,
parameter RAM_DEPTH = -1,
parameter RAM_ADDR_WIDTH = -1,
parameter RAM_DATA_WIDTH = -1
)(
input rst_n,
input clka,
input ena,
input wea,
input [RAM_ADDR_WIDTH-1:0] addra,
input [RAM_DATA_WIDTH-1:0] dina,
output [RAM_DATA_WIDTH-1:0] douta,
input clkb,
input enb,
input web,
input [RAM_ADDR_WIDTH-1:0] addrb,
input [RAM_DATA_WIDTH-1:0] dinb,
output [RAM_DATA_WIDTH-1:0] doutb
);
`ifdef VCS_SIMULATION
reg [RAM_DATA_WIDTH-1:0] mem [RAM_DEPTH-1:0];
reg [RAM_DATA_WIDTH-1:0] douta_f;
reg [RAM_DATA_WIDTH-1:0] doutb_f;
genvar ii;
assign douta = douta_f;
assign doutb = doutb_f;
generate
for (ii = 0; ii < RAM_DEPTH; ii = ii + 1) begin: mem_gen
always @(posedge clka) begin
if (~rst_n) begin
mem[ii] <= {RAM_DATA_WIDTH{1'b0}};
end
else begin
mem[ii] <= ena & wea & (ii == addra) ? dina :
enb & web & (ii == addrb) ? dinb : mem[ii];
end
end
end
endgenerate
always @(posedge clka) begin
douta_f <= ena & ~wea ? mem[addra] : {RAM_DATA_WIDTH{1'bx}};
doutb_f <= enb & ~web ? mem[addrb] : {RAM_DATA_WIDTH{1'bx}};
end
`else // VCS_SIMULATION
// Vivado IP
generate
if (RAM_TYPE == 0) begin
ram_2p_type_0 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 1) begin
ram_2p_type_1 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 2) begin
ram_2p_type_2 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 3) begin
ram_2p_type_3 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 4) begin
ram_2p_type_4 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 5) begin
ram_2p_type_5 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
else if (RAM_TYPE == 6) begin
ram_2p_type_6 ram_2p (
.clka (clka ),
.ena (ena ),
.wea (wea ),
.addra (addra ),
.dina (dina ),
.douta (douta ),
.clkb (clkb ),
.enb (enb ),
.web (web ),
.addrb (addrb ),
.dinb (dinb ),
.doutb (doutb )
);
end
endgenerate
`endif // VCS_SIMULATION
//-----------------------------------------------------------
// Functions
//-----------------------------------------------------------
// clogb2 function
`include "clogb2.vh"
endmodule |
module ram_2w2r #(
parameter RAM_TYPE = -1,
parameter RAM_DEPTH = -1,
parameter RAM_ADDR_WIDTH = -1,
parameter RAM_DATA_WIDTH = -1
) (
input clk,
input rst_n,
input r0_val,
input [RAM_ADDR_WIDTH-1:0] r0_addr,
output [RAM_DATA_WIDTH-1:0] r0_data,
input r1_val,
input [RAM_ADDR_WIDTH-1:0] r1_addr,
output [RAM_DATA_WIDTH-1:0] r1_data,
input w0_val,
input [RAM_ADDR_WIDTH-1:0] w0_addr,
input [RAM_DATA_WIDTH-1:0] w0_data,
input w1_val,
input [RAM_ADDR_WIDTH-1:0] w1_addr,
input [RAM_DATA_WIDTH-1:0] w1_data
);
// MRB - most recent bank storage for every address
reg [RAM_DEPTH-1:0] mrb;
reg r0_mrb_f;
reg r1_mrb_f;
wire r0_mrb;
wire r1_mrb;
wire w0_bank;
wire w1_bank;
wire b0_ena;
wire b0_wea;
wire [RAM_ADDR_WIDTH-1:0] b0_addra;
wire [RAM_DATA_WIDTH-1:0] b0_dina;
wire [RAM_DATA_WIDTH-1:0] b0_douta;
wire b0_enb;
wire b0_web;
wire [RAM_ADDR_WIDTH-1:0] b0_addrb;
wire [RAM_DATA_WIDTH-1:0] b0_dinb;
wire [RAM_DATA_WIDTH-1:0] b0_doutb;
wire b1_ena;
wire b1_wea;
wire [RAM_ADDR_WIDTH-1:0] b1_addra;
wire [RAM_DATA_WIDTH-1:0] b1_dina;
wire [RAM_DATA_WIDTH-1:0] b1_douta;
wire b1_enb;
wire b1_web;
wire [RAM_ADDR_WIDTH-1:0] b1_addrb;
wire [RAM_DATA_WIDTH-1:0] b1_dinb;
wire [RAM_DATA_WIDTH-1:0] b1_doutb;
genvar ii;
//-----------------------------------------------------------
// Logic
//-----------------------------------------------------------
assign r0_mrb = mrb[r0_addr];
assign r1_mrb = mrb[r1_addr];
// write data to bank 1 only if there is a read from bank 0
assign w0_bank = r0_val & ~r0_mrb;
assign w1_bank = r1_val & ~r1_mrb;
// Bank 0 Port a
assign b0_ena = (r0_val & ~r0_mrb) | (w0_val & ~w0_bank);
assign b0_wea = w0_val & ~w0_bank;
assign b0_addra = (r0_val & ~r0_mrb) ? r0_addr : w0_addr;
assign b0_dina = w0_data;
// Bank 0 Port b
assign b0_enb = (r1_val & ~r1_mrb) | (w1_val & ~w1_bank);
assign b0_web = w1_val & ~w1_bank;
assign b0_addrb = (r1_val & ~r1_mrb) ? r1_addr : w1_addr;
assign b0_dinb = w1_data;
// Bank 1 Port a
assign b1_ena = (r0_val & r0_mrb) | (w0_val & w0_bank);
assign b1_wea = w0_val & w0_bank;
assign b1_addra = (r0_val & r0_mrb) ? r0_addr : w0_addr;
assign b1_dina = w0_data;
// Bank 1 Port b
assign b1_enb = (r1_val & r1_mrb) | (w1_val & w1_bank);
assign b1_web = w1_val & w1_bank;
assign b1_addrb = (r1_val & r1_mrb) ? r1_addr : w1_addr;
assign b1_dinb = w1_data;
assign r0_data = ~r0_mrb_f ? b0_douta : b1_douta;
assign r1_data = ~r1_mrb_f ? b0_doutb : b1_doutb;
generate
for (ii = 0; ii < RAM_DEPTH; ii = ii + 1) begin: mrb_gen
always @(posedge clk) begin
if (~rst_n) begin
mrb[ii] <= 1'b0;
end
else begin
// TODO: change to parallel logic
mrb[ii] <= w0_val & (ii == w0_addr) ? w0_bank :
w1_val & (ii == w1_addr) ? w1_bank : mrb[ii];
end
end
end
endgenerate
always @(posedge clk) begin
r0_mrb_f <= r0_mrb;
r1_mrb_f <= r1_mrb;
end
ram_2p_wrapper #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) bank0 (
.rst_n (rst_n ),
.clka (clk ),
.ena (b0_ena ),
.wea (b0_wea ),
.addra (b0_addra ),
.dina (b0_dina ),
.douta (b0_douta ),
.clkb (clk ),
.enb (b0_enb ),
.web (b0_web ),
.addrb (b0_addrb ),
.dinb (b0_dinb ),
.doutb (b0_doutb )
);
ram_2p_wrapper #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) bank1 (
.rst_n (rst_n ),
.clka (clk ),
.ena (b1_ena ),
.wea (b1_wea ),
.addra (b1_addra ),
.dina (b1_dina ),
.douta (b1_douta ),
.clkb (clk ),
.enb (b1_enb ),
.web (b1_web ),
.addrb (b1_addrb ),
.dinb (b1_dinb ),
.doutb (b1_doutb )
);
//-----------------------------------------------------------
// Checker
//-----------------------------------------------------------
`ifdef RAM_CHECKER
// No more than one write to the same address
always @(posedge clk) begin
if (w0_val & w1_val & (w0_addr == w1_addr)) begin
$display("ERROR Checker: %m: two write to address 0x%h in the same cycle @%t. No particular ordering between writes is guaranteed", w0_addr, $time);
$stop;
end
end
`endif
endmodule |
module ram_4w4r #(
parameter RAM_TYPE = -1,
parameter RAM_DEPTH = -1,
parameter RAM_ADDR_WIDTH = -1,
parameter RAM_DATA_WIDTH = -1
)(
input clk,
input rst_n,
input r0_val,
input [RAM_ADDR_WIDTH-1:0] r0_addr,
output [RAM_DATA_WIDTH-1:0] r0_data,
input r1_val,
input [RAM_ADDR_WIDTH-1:0] r1_addr,
output [RAM_DATA_WIDTH-1:0] r1_data,
input r2_val,
input [RAM_ADDR_WIDTH-1:0] r2_addr,
output [RAM_DATA_WIDTH-1:0] r2_data,
input r3_val,
input [RAM_ADDR_WIDTH-1:0] r3_addr,
output [RAM_DATA_WIDTH-1:0] r3_data,
input w0_val,
input [RAM_ADDR_WIDTH-1:0] w0_addr,
input [RAM_DATA_WIDTH-1:0] w0_data,
input w1_val,
input [RAM_ADDR_WIDTH-1:0] w1_addr,
input [RAM_DATA_WIDTH-1:0] w1_data,
input w2_val,
input [RAM_ADDR_WIDTH-1:0] w2_addr,
input [RAM_DATA_WIDTH-1:0] w2_data,
input w3_val,
input [RAM_ADDR_WIDTH-1:0] w3_addr,
input [RAM_DATA_WIDTH-1:0] w3_data
);
reg [RAM_DEPTH-1:0] mrb;
reg r0_mrb_f;
reg r1_mrb_f;
reg r2_mrb_f;
reg r3_mrb_f;
wire b0r0_val;
wire [RAM_ADDR_WIDTH-1:0] b0r0_addr;
wire [RAM_DATA_WIDTH-1:0] b0r0_data;
wire b0r1_val;
wire [RAM_ADDR_WIDTH-1:0] b0r1_addr;
wire [RAM_DATA_WIDTH-1:0] b0r1_data;
wire b0r2_val;
wire [RAM_ADDR_WIDTH-1:0] b0r2_addr;
wire [RAM_DATA_WIDTH-1:0] b0r2_data;
wire b0r3_val;
wire [RAM_ADDR_WIDTH-1:0] b0r3_addr;
wire [RAM_DATA_WIDTH-1:0] b0r3_data;
wire b0w0_val;
wire [RAM_ADDR_WIDTH-1:0] b0w0_addr;
wire [RAM_DATA_WIDTH-1:0] b0w0_data;
wire b0w1_val;
wire [RAM_ADDR_WIDTH-1:0] b0w1_addr;
wire [RAM_DATA_WIDTH-1:0] b0w1_data;
wire b1r0_val;
wire [RAM_ADDR_WIDTH-1:0] b1r0_addr;
wire [RAM_DATA_WIDTH-1:0] b1r0_data;
wire b1r1_val;
wire [RAM_ADDR_WIDTH-1:0] b1r1_addr;
wire [RAM_DATA_WIDTH-1:0] b1r1_data;
wire b1r2_val;
wire [RAM_ADDR_WIDTH-1:0] b1r2_addr;
wire [RAM_DATA_WIDTH-1:0] b1r2_data;
wire b1r3_val;
wire [RAM_ADDR_WIDTH-1:0] b1r3_addr;
wire [RAM_DATA_WIDTH-1:0] b1r3_data;
wire b1w0_val;
wire [RAM_ADDR_WIDTH-1:0] b1w0_addr;
wire [RAM_DATA_WIDTH-1:0] b1w0_data;
wire b1w1_val;
wire [RAM_ADDR_WIDTH-1:0] b1w1_addr;
wire [RAM_DATA_WIDTH-1:0] b1w1_data;
genvar ii;
//-----------------------------------------------------------
// Logic
//-----------------------------------------------------------
assign b0r0_val = r0_val;
assign b0r0_addr = r0_addr;
assign b0r1_val = r1_val;
assign b0r1_addr = r1_addr;
assign b0r2_val = r2_val;
assign b0r2_addr = r2_addr;
assign b0r3_val = r3_val;
assign b0r3_addr = r3_addr;
assign b0w0_val = w0_val;
assign b0w0_addr = w0_addr;
assign b0w0_data = w0_data;
assign b0w1_val = w1_val;
assign b0w1_addr = w1_addr;
assign b0w1_data = w1_data;
assign b1r0_val = r0_val;
assign b1r0_addr = r0_addr;
assign b1r1_val = r1_val;
assign b1r1_addr = r1_addr;
assign b1r2_val = r2_val;
assign b1r2_addr = r2_addr;
assign b1r3_val = r3_val;
assign b1r3_addr = r3_addr;
assign b1w0_val = w2_val;
assign b1w0_addr = w2_addr;
assign b1w0_data = w2_data;
assign b1w1_val = w3_val;
assign b1w1_addr = w3_addr;
assign b1w1_data = w3_data;
assign r0_data = ~r0_mrb_f ? b0r0_data : b1r0_data;
assign r1_data = ~r1_mrb_f ? b0r1_data : b1r1_data;
assign r2_data = ~r2_mrb_f ? b0r2_data : b1r2_data;
assign r3_data = ~r3_mrb_f ? b0r3_data : b1r3_data;
generate
for (ii = 0; ii < RAM_DEPTH; ii = ii + 1) begin: mrb_gen
always @(posedge clk) begin
if (~rst_n) begin
mrb[ii] <= 1'b0;
end
else begin
// TODO: change to parallel logic?
mrb[ii] <= (w0_val & (ii == w0_addr)) |
(w1_val & (ii == w1_addr)) ? 1'b0 :
(w2_val & (ii == w2_addr)) |
(w3_val & (ii == w3_addr)) ? 1'b1 : mrb[ii];
end
end
end
endgenerate
always @(posedge clk) begin
r0_mrb_f <= mrb[r0_addr];
r1_mrb_f <= mrb[r1_addr];
r2_mrb_f <= mrb[r2_addr];
r3_mrb_f <= mrb[r3_addr];
end
ram_2w4r #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) bank0 (
.clk (clk ),
.rst_n (rst_n ),
.r0_val (b0r0_val ),
.r0_addr (b0r0_addr ),
.r0_data (b0r0_data ),
.r1_val (b0r1_val ),
.r1_addr (b0r1_addr ),
.r1_data (b0r1_data ),
.r2_val (b0r2_val ),
.r2_addr (b0r2_addr ),
.r2_data (b0r2_data ),
.r3_val (b0r3_val ),
.r3_addr (b0r3_addr ),
.r3_data (b0r3_data ),
.w0_val (b0w0_val ),
.w0_addr (b0w0_addr ),
.w0_data (b0w0_data ),
.w1_val (b0w1_val ),
.w1_addr (b0w1_addr ),
.w1_data (b0w1_data )
);
ram_2w4r #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) bank1 (
.clk (clk ),
.rst_n (rst_n ),
.r0_val (b1r0_val ),
.r0_addr (b1r0_addr ),
.r0_data (b1r0_data ),
.r1_val (b1r1_val ),
.r1_addr (b1r1_addr ),
.r1_data (b1r1_data ),
.r2_val (b1r2_val ),
.r2_addr (b1r2_addr ),
.r2_data (b1r2_data ),
.r3_val (b1r3_val ),
.r3_addr (b1r3_addr ),
.r3_data (b1r3_data ),
.w0_val (b1w0_val ),
.w0_addr (b1w0_addr ),
.w0_data (b1w0_data ),
.w1_val (b1w1_val ),
.w1_addr (b1w1_addr ),
.w1_data (b1w1_data )
);
//-----------------------------------------------------------
// Checker
//-----------------------------------------------------------
`ifdef RAM_CHECKER
// No concurrent read/write or write/write to the same address
always @(posedge clk) begin
check_collision(w0_val, w0_addr, w1_val, w1_addr);
check_collision(w0_val, w0_addr, w2_val, w2_addr);
check_collision(w0_val, w0_addr, w3_val, w3_addr);
check_collision(w1_val, w1_addr, w2_val, w2_addr);
check_collision(w1_val, w1_addr, w3_val, w3_addr);
check_collision(w2_val, w2_addr, w3_val, w3_addr);
end
task check_collision;
input p0_val;
input [RAM_ADDR_WIDTH-1:0] p0_addr;
input p1_val;
input [RAM_ADDR_WIDTH-1:0] p1_addr;
begin
if (p0_val & p1_val & (p0_addr == p1_addr)) begin
$display("ERROR Checker: %m: Collission at address 0x%h at @%t. No ordering is guaranteed!", p0_addr, $time);
$stop;
end
end
endtask
`endif // RAM_CHECKER
endmodule |
module ram_2w4r #(
parameter RAM_TYPE = -1,
parameter RAM_DEPTH = -1,
parameter RAM_ADDR_WIDTH = -1,
parameter RAM_DATA_WIDTH = -1
)(
input clk,
input rst_n,
input r0_val,
input [RAM_ADDR_WIDTH-1:0] r0_addr,
output [RAM_DATA_WIDTH-1:0] r0_data,
input r1_val,
input [RAM_ADDR_WIDTH-1:0] r1_addr,
output [RAM_DATA_WIDTH-1:0] r1_data,
input r2_val,
input [RAM_ADDR_WIDTH-1:0] r2_addr,
output [RAM_DATA_WIDTH-1:0] r2_data,
input r3_val,
input [RAM_ADDR_WIDTH-1:0] r3_addr,
output [RAM_DATA_WIDTH-1:0] r3_data,
input w0_val,
input [RAM_ADDR_WIDTH-1:0] w0_addr,
input [RAM_DATA_WIDTH-1:0] w0_data,
input w1_val,
input [RAM_ADDR_WIDTH-1:0] w1_addr,
input [RAM_DATA_WIDTH-1:0] w1_data
);
ram_2w2r #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) mem0 (
.clk (clk ),
.rst_n (rst_n ),
.r0_val (r0_val ),
.r0_addr (r0_addr ),
.r0_data (r0_data ),
.r1_val (r1_val ),
.r1_addr (r1_addr ),
.r1_data (r1_data ),
.w0_val (w0_val ),
.w0_addr (w0_addr ),
.w0_data (w0_data ),
.w1_val (w1_val ),
.w1_addr (w1_addr ),
.w1_data (w1_data )
);
ram_2w2r #(
.RAM_TYPE (RAM_TYPE ),
.RAM_DEPTH (RAM_DEPTH ),
.RAM_ADDR_WIDTH (RAM_ADDR_WIDTH ),
.RAM_DATA_WIDTH (RAM_DATA_WIDTH )
) mem1 (
.clk (clk ),
.rst_n (rst_n ),
.r0_val (r2_val ),
.r0_addr (r2_addr ),
.r0_data (r2_data ),
.r1_val (r3_val ),
.r1_addr (r3_addr ),
.r1_data (r3_data ),
.w0_val (w0_val ),
.w0_addr (w0_addr ),
.w0_data (w0_data ),
.w1_val (w1_val ),
.w1_addr (w1_addr ),
.w1_data (w1_data )
);
endmodule |
module cnt_block #(
parameter BLOCK_WIDTH = 2,
parameter BLOCK_IND_WIDTH = 10,
parameter BLOCK_LEVEL = -1,
parameter BLOCK_WIDTH_LOG = clogb2(BLOCK_WIDTH)
)(
input [BLOCK_IND_WIDTH*BLOCK_WIDTH-1:0] cnts_in,
output [BLOCK_IND_WIDTH+BLOCK_WIDTH_LOG-1:0] cnt_out
);
generate
if (BLOCK_WIDTH == 2) begin
assign cnt_out = {{BLOCK_WIDTH_LOG{1'b0}}, cnts_in[BLOCK_IND_WIDTH * BLOCK_WIDTH - 1 -: BLOCK_IND_WIDTH]} +
{{BLOCK_WIDTH_LOG{1'b0}}, cnts_in[BLOCK_IND_WIDTH-1:0]};
end
else begin
assign cnt_out = {(BLOCK_IND_WIDTH+BLOCK_WIDTH_LOG){1'b0}};
end
endgenerate
function integer clogb2;
input integer val;
begin
clogb2 = 1;
for (val = val/2; val > 1; val = val/2) begin
clogb2 = clogb2 + 1;
end
end
endfunction
endmodule |
module cnt_wnd # (
parameter VECT_WIDTH = -1,
parameter VECT_IND_WIDTH = -1,
parameter BLOCK_WIDTH = 2
) (
input [VECT_WIDTH-1:0] vect_in,
input select_set_in,
output [VECT_IND_WIDTH-1:0] cnt_out
);
wire [VECT_WIDTH-1:0] vect_wnd_set_bits;
genvar ii;
generate
for (ii = 0; ii < VECT_WIDTH; ii = ii + 1) begin: vect_wnd_set_bits_gen
assign vect_wnd_set_bits[ii] = (vect_in[ii] == select_set_in);
end
endgenerate
cnt_set #(
.VECT_WIDTH (VECT_WIDTH ),
.VECT_IND_WIDTH (VECT_IND_WIDTH ),
.BLOCK_WIDTH (BLOCK_WIDTH )
) cnt_set (
.vect_in (vect_wnd_set_bits ),
.cnt_out (cnt_out )
);
endmodule |
module cnt_set #(
parameter VECT_WIDTH = 64,
parameter VECT_IND_WIDTH = 4,
parameter BLOCK_WIDTH = 2
)(
input [VECT_WIDTH-1:0] vect_in,
output [VECT_IND_WIDTH-1:0] cnt_out
);
localparam BLOCK_DEPTH = clog(VECT_WIDTH, BLOCK_WIDTH);
localparam BLOCK_WIDTH_LOG = clog(BLOCK_WIDTH, 2);
wire [VECT_WIDTH-1:0] cnt_level[BLOCK_DEPTH:0];
assign cnt_out = cnt_level[BLOCK_DEPTH][VECT_IND_WIDTH-1:0];
genvar ii, jj;
generate begin
for (ii = 0; ii < BLOCK_DEPTH; ii = ii + 1) begin: level_gen
if (ii == 0) begin
assign cnt_level[ii] = vect_in;
end
// wire [VECT_WIDTH/pow(BLOCK_WIDTH,ii)-1:0] val_out_prev_level;
for (jj = 0; jj < pow(BLOCK_WIDTH, BLOCK_DEPTH-ii-1); jj = jj + 1) begin: block_gen
cnt_block # (
.BLOCK_WIDTH (BLOCK_WIDTH ),
.BLOCK_IND_WIDTH (ii + 1 ),
.BLOCK_LEVEL (ii )
) cnt_block (
.cnts_in (cnt_level[ii][(jj+1)*(BLOCK_WIDTH*(ii+1))-1 :jj*BLOCK_WIDTH*(ii+1)]),
.cnt_out (cnt_level[ii+1][(jj+1)*(ii+1+BLOCK_WIDTH_LOG)-1:jj*(ii+1+BLOCK_WIDTH_LOG)])
);
end
end
end
endgenerate
function integer clog;
input integer val;
input integer base;
begin
clog = 1;
for (val = val/base; val > 1; val = val/base) begin
clog = clog + 1;
end
end
endfunction
function integer pow;
input integer base;
input integer val;
begin
pow = 1;
for (val = val; val > 0; val = val - 1) begin
pow = pow*base;
end
end
endfunction
endmodule |
module ff_wnd # (
parameter VECT_WIDTH = -1,
parameter VECT_IND_WIDTH = -1,
parameter BLOCK_WIDTH = 2
) (
input [VECT_WIDTH-1:0] vect_in,
input select_set_in,
input [VECT_IND_WIDTH-1:0] head_in,
output val_out,
output [VECT_IND_WIDTH-1:0] ind_out
);
wire [VECT_WIDTH-1:0] vect_wnd_set_bits_1;
wire val_out_1;
wire [VECT_IND_WIDTH-1:0] ind_out_1;
wire [VECT_WIDTH-1:0] vect_wnd_set_bits_2;
wire val_out_2;
wire [VECT_IND_WIDTH-1:0] ind_out_2;
genvar ii;
generate
for (ii = 0; ii < VECT_WIDTH; ii = ii + 1) begin: vect_wnd_set_bits_gen
assign vect_wnd_set_bits_1[ii] = (vect_in[ii] == select_set_in) &
(ii >= head_in);
assign vect_wnd_set_bits_2[ii] = (vect_in[ii] == select_set_in);
end
endgenerate
ff_set #(
.VECT_WIDTH (VECT_WIDTH ),
.VECT_IND_WIDTH (VECT_IND_WIDTH ),
.BLOCK_WIDTH (BLOCK_WIDTH )
) sfs1 (
.vect_in (vect_wnd_set_bits_1 ),
.val_out (val_out_1 ),
.ind_out (ind_out_1 )
);
ff_set #(
.VECT_WIDTH (VECT_WIDTH ),
.VECT_IND_WIDTH (VECT_IND_WIDTH ),
.BLOCK_WIDTH (BLOCK_WIDTH )
) sfs2 (
.vect_in (vect_wnd_set_bits_2 ),
.val_out (val_out_2 ),
.ind_out (ind_out_2 )
);
assign val_out = val_out_1 | val_out_2;
assign ind_out = val_out_1 ? ind_out_1 : ind_out_2;
endmodule |
module ff_set #(
parameter VECT_WIDTH = 64,
parameter VECT_IND_WIDTH = 4,
parameter BLOCK_WIDTH = 2
)(
input [VECT_WIDTH-1:0] vect_in,
output val_out,
output [VECT_IND_WIDTH-1:0] ind_out
);
localparam BLOCK_DEPTH = clog(VECT_WIDTH, BLOCK_WIDTH);
localparam IND_VAL_ARR_SIZE = VECT_WIDTH * (BLOCK_DEPTH + 1);
localparam FLAT_ARR_ITEM_WIDTH = VECT_WIDTH * VECT_IND_WIDTH;
localparam IND_FLAT_ARR_SIZE = FLAT_ARR_ITEM_WIDTH * (BLOCK_DEPTH + 1);
wire [IND_VAL_ARR_SIZE-1:0] ind_val_level;
wire [IND_FLAT_ARR_SIZE-1:0] ind_flat_level;
assign val_out = ind_val_level[BLOCK_DEPTH * VECT_WIDTH];
assign ind_out = ind_flat_level[BLOCK_DEPTH * FLAT_ARR_ITEM_WIDTH + VECT_IND_WIDTH - 1 -: VECT_IND_WIDTH];
genvar ii, jj;
generate begin
for (ii = 0; ii < BLOCK_DEPTH; ii = ii + 1) begin: level_gen
if (ii == 0) begin
assign ind_val_level[(ii + 1) * VECT_WIDTH - 1 -: VECT_WIDTH] = vect_in;
// Generate flat level 0 indexes
for (jj = 0; jj < VECT_WIDTH; jj = jj + 1) begin: ind_flat_level_gen
assign ind_flat_level[(jj+1)*VECT_IND_WIDTH-1:jj*VECT_IND_WIDTH] = {VECT_IND_WIDTH{1'b0}};
end
end
for (jj = 0; jj < num_blks(VECT_WIDTH, ii, BLOCK_WIDTH); jj = jj + 1) begin: block_gen
ff_block # (
.BLOCK_WIDTH (BLOCK_WIDTH ),
.BLOCK_IND_WIDTH (VECT_IND_WIDTH ),
.BLOCK_LEVEL (ii )
) ff_block (
.ind_val_in (ind_val_level[(ii * VECT_WIDTH) + (jj+1)*BLOCK_WIDTH-1: (ii * VECT_WIDTH) + jj*BLOCK_WIDTH]),
.ind_flat_in(ind_flat_level[(ii * FLAT_ARR_ITEM_WIDTH) + (jj+1)*VECT_IND_WIDTH*BLOCK_WIDTH-1: (ii * FLAT_ARR_ITEM_WIDTH) + jj*VECT_IND_WIDTH*BLOCK_WIDTH]),
.val_out(ind_val_level[(ii+1) * VECT_WIDTH + jj]),
.ind_out(ind_flat_level[((ii+1) * FLAT_ARR_ITEM_WIDTH) + (jj+1)*VECT_IND_WIDTH-1:
((ii+1) * FLAT_ARR_ITEM_WIDTH) + jj*VECT_IND_WIDTH])
);
end
assign ind_val_level[(ii + 1) * VECT_WIDTH + VECT_WIDTH - 1 : (ii + 1) * VECT_WIDTH + num_blks(VECT_WIDTH, ii, BLOCK_WIDTH)] = {(VECT_WIDTH - num_blks(VECT_WIDTH, ii, BLOCK_WIDTH)){1'b0}};
assign ind_flat_level[(ii + 1) * FLAT_ARR_ITEM_WIDTH + FLAT_ARR_ITEM_WIDTH - 1 : (ii + 1) * FLAT_ARR_ITEM_WIDTH + (num_blks(VECT_WIDTH, ii, BLOCK_WIDTH))*VECT_IND_WIDTH] = {(VECT_IND_WIDTH * (VECT_WIDTH - num_blks(VECT_WIDTH, ii, BLOCK_WIDTH))){1'b0}};
end
end
endgenerate
function integer clog;
input integer val;
input integer base;
begin
clog = 1;
for (val = val/base; val > 1; val = val/base) begin
clog = clog + 1;
end
end
endfunction
function integer pow;
input integer base;
input integer val;
begin
pow = 1;
for (val = val; val > 0; val = val - 1) begin
pow = pow*base;
end
end
endfunction
function integer num_blks;
input integer w;
input integer i;
input integer bw;
begin
num_blks = pow(bw, i + 1) > w ? 1 : w/pow(bw, i + 1);
end
endfunction
endmodule |
module ff_block #(
parameter BLOCK_WIDTH = 4,
parameter BLOCK_IND_WIDTH = 10,
parameter BLOCK_LEVEL = -1
)(
input [BLOCK_WIDTH-1:0] ind_val_in,
input [BLOCK_IND_WIDTH*BLOCK_WIDTH-1:0] ind_flat_in,
output val_out,
output [BLOCK_IND_WIDTH-1:0] ind_out
);
localparam INPUT_DIR_NUM_WIDTH = clogb2(BLOCK_WIDTH);
localparam INPUT_DIR_SHIFT = clogb2(BLOCK_WIDTH)*BLOCK_LEVEL;
wire [BLOCK_WIDTH-1:0] single_valid_bus;
wire [BLOCK_IND_WIDTH-1:0] selected_ind;
wire [BLOCK_IND_WIDTH-1:0] ind_matr[BLOCK_WIDTH-1:0];
wire [INPUT_DIR_NUM_WIDTH-1:0] selected_direction;
wire [BLOCK_WIDTH-1:0] ind_in_revert_matrix[BLOCK_IND_WIDTH-1:0];
wire [INPUT_DIR_NUM_WIDTH-1:0] direction_matrix[BLOCK_WIDTH-1:0];
wire [BLOCK_WIDTH-1:0] direction_matrix_inv[INPUT_DIR_NUM_WIDTH-1:0];
genvar ii, jj;
assign val_out = |ind_val_in;
//assign ind_out = (selected_direction << INPUT_DIR_SHIFT) + selected_ind;
assign ind_out = (selected_direction << INPUT_DIR_SHIFT) + selected_ind;
// Vector with at most one valid bit set
generate begin
for (ii = 0; ii < BLOCK_WIDTH; ii = ii + 1) begin: single_valid_bus_gen
if (ii == 0) begin
assign single_valid_bus[ii] = ind_val_in[ii];
end
else begin
assign single_valid_bus[ii] = ~(|ind_val_in[ii-1:0]) & ind_val_in[ii];
end
end
end
endgenerate
// Parallel OR input indexes masked by a vector with at most one valid bit set
generate begin
for (ii = 0; ii < BLOCK_WIDTH; ii = ii + 1) begin: ind_matr_gen
assign ind_matr[ii] = ind_flat_in[(ii+1)*BLOCK_IND_WIDTH-1:ii*BLOCK_IND_WIDTH];
end
for (ii = 0; ii < BLOCK_IND_WIDTH; ii = ii + 1) begin: selected_ind_gen
for (jj = 0; jj < BLOCK_WIDTH; jj = jj + 1) begin: ind_in_revert_gen
assign ind_in_revert_matrix[ii][jj] = ind_matr[jj][ii] & single_valid_bus[jj];
end
assign selected_ind[ii] = |ind_in_revert_matrix[ii];
end
end
endgenerate
// Get Input Direction number curresponding to a set bit in single_valid_bus
generate begin
for (ii = 0; ii < BLOCK_WIDTH; ii = ii + 1) begin: direction_matrix_gen
wire [31:0] tmp_index = ii;
assign direction_matrix[ii] = tmp_index[INPUT_DIR_NUM_WIDTH-1:0];
end
for (ii = 0; ii < INPUT_DIR_NUM_WIDTH; ii = ii + 1) begin: selected_direction_gen
for (jj = 0; jj < BLOCK_WIDTH; jj = jj + 1) begin: direction_matrix_gen
assign direction_matrix_inv[ii][jj] = direction_matrix[jj][ii] & single_valid_bus[jj];
end
assign selected_direction[ii] = |direction_matrix_inv[ii];
end
end
endgenerate
// clogb2 function
`include "clogb2.vh"
endmodule |
module top (
\totalcoeffs[0] , \totalcoeffs[1] , \totalcoeffs[2] , \totalcoeffs[3] ,
\totalcoeffs[4] , \ctable[0] , \ctable[1] , \ctable[2] ,
\trailingones[0] , \trailingones[1] ,
\coeff_token[0] , \coeff_token[1] , \coeff_token[2] , \coeff_token[3] ,
\coeff_token[4] , \coeff_token[5] , \ctoken_len[0] , \ctoken_len[1] ,
\ctoken_len[2] , \ctoken_len[3] , \ctoken_len[4] );
input \totalcoeffs[0] , \totalcoeffs[1] , \totalcoeffs[2] ,
\totalcoeffs[3] , \totalcoeffs[4] , \ctable[0] , \ctable[1] ,
\ctable[2] , \trailingones[0] , \trailingones[1] ;
output \coeff_token[0] , \coeff_token[1] , \coeff_token[2] ,
\coeff_token[3] , \coeff_token[4] , \coeff_token[5] , \ctoken_len[0] ,
\ctoken_len[1] , \ctoken_len[2] , \ctoken_len[3] , \ctoken_len[4] ;
wire n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188, n189,
n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201,
n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274,
n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286,
n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309, n310,
n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321, n322,
n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380, n381, n382, n383,
n384, n385, n386, n387, n388, n389, n390, n391, n392, n393, n394, n395,
n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419,
n420, n422, n423, n424, n425, n426, n427, n428, n430, n431, n432, n433,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445, n446,
n447, n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
n495, n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554, n555,
n556, n557, n558, n559, n560, n561, n562, n563, n564, n565, n566, n567,
n568, n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651, n652,
n653, n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n669, n670, n671, n672, n673, n674, n675, n676, n677,
n678, n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n708, n709, n710, n711, n712, n713;
assign n22 = ~\totalcoeffs[3] & ~\ctable[0] ;
assign n23 = ~\totalcoeffs[1] & \trailingones[1] ;
assign n24 = ~\totalcoeffs[0] & \trailingones[1] ;
assign n25 = \totalcoeffs[1] & ~n24;
assign n26 = ~n23 & ~n25;
assign n27 = n22 & n26;
assign n28 = \totalcoeffs[0] & ~\trailingones[1] ;
assign n29 = ~\totalcoeffs[1] & ~n28;
assign n30 = \totalcoeffs[1] & ~\trailingones[1] ;
assign n31 = ~\ctable[2] & ~n30;
assign n32 = ~n29 & n31;
assign n33 = ~n27 & ~n32;
assign n34 = ~\totalcoeffs[2] & ~n33;
assign n35 = ~\totalcoeffs[2] & ~\ctable[0] ;
assign n36 = ~\totalcoeffs[0] & ~n35;
assign n37 = \totalcoeffs[1] & \totalcoeffs[2] ;
assign n38 = ~n36 & ~n37;
assign n39 = ~\trailingones[1] & ~n38;
assign n40 = ~\totalcoeffs[2] & ~\totalcoeffs[3] ;
assign n41 = \trailingones[1] & ~n40;
assign n42 = \totalcoeffs[0] & \totalcoeffs[3] ;
assign n43 = ~n41 & ~n42;
assign n44 = ~\totalcoeffs[1] & ~n43;
assign n45 = \totalcoeffs[1] & ~\totalcoeffs[3] ;
assign n46 = ~n44 & ~n45;
assign n47 = ~n39 & n46;
assign n48 = ~\ctable[2] & ~n47;
assign n49 = ~n34 & ~n48;
assign n50 = ~\trailingones[0] & ~n49;
assign n51 = \ctable[2] & \trailingones[0] ;
assign n52 = ~\ctable[0] & n51;
assign n53 = ~\ctable[2] & \trailingones[1] ;
assign n54 = ~n52 & ~n53;
assign n55 = \totalcoeffs[1] & ~n54;
assign n56 = \totalcoeffs[1] & ~\ctable[2] ;
assign n57 = ~\ctable[0] & ~\trailingones[1] ;
assign n58 = ~n56 & n57;
assign n59 = ~n55 & ~n58;
assign n60 = \totalcoeffs[0] & ~\totalcoeffs[2] ;
assign n61 = ~n59 & n60;
assign n62 = \totalcoeffs[2] & ~\trailingones[1] ;
assign n63 = ~\totalcoeffs[0] & ~\totalcoeffs[1] ;
assign n64 = n62 & n63;
assign n65 = n52 & n64;
assign n66 = ~n61 & ~n65;
assign n67 = ~\totalcoeffs[3] & ~n66;
assign n68 = ~n50 & ~n67;
assign n69 = ~\ctable[1] & ~n68;
assign n70 = ~\totalcoeffs[0] & ~\totalcoeffs[2] ;
assign n71 = n23 & n70;
assign n72 = ~\ctable[0] & ~n71;
assign n73 = \ctable[1] & ~n72;
assign n74 = ~\totalcoeffs[0] & ~\trailingones[1] ;
assign n75 = \totalcoeffs[0] & \trailingones[1] ;
assign n76 = ~n74 & ~n75;
assign n77 = \totalcoeffs[1] & ~n76;
assign n78 = \totalcoeffs[2] & n77;
assign n79 = \ctable[0] & n78;
assign n80 = ~n73 & ~n79;
assign n81 = \trailingones[0] & ~n80;
assign n82 = ~\totalcoeffs[1] & ~n24;
assign n83 = ~\trailingones[0] & ~n82;
assign n84 = ~\totalcoeffs[1] & \totalcoeffs[2] ;
assign n85 = n28 & n84;
assign n86 = ~n83 & ~n85;
assign n87 = ~\ctable[0] & ~n86;
assign n88 = ~n81 & ~n87;
assign n89 = \totalcoeffs[3] & ~n88;
assign n90 = ~\totalcoeffs[2] & ~n28;
assign n91 = \ctable[1] & ~n90;
assign n92 = n40 & n77;
assign n93 = ~n91 & ~n92;
assign n94 = \ctable[0] & ~n93;
assign n95 = \totalcoeffs[2] & \trailingones[1] ;
assign n96 = ~\totalcoeffs[2] & n30;
assign n97 = ~n95 & ~n96;
assign n98 = ~\totalcoeffs[0] & ~\totalcoeffs[3] ;
assign n99 = ~n97 & n98;
assign n100 = \ctable[1] & n99;
assign n101 = ~n94 & ~n100;
assign n102 = \trailingones[0] & ~n101;
assign n103 = \totalcoeffs[2] & ~\totalcoeffs[3] ;
assign n104 = n23 & n103;
assign n105 = \totalcoeffs[1] & ~\trailingones[0] ;
assign n106 = ~n104 & ~n105;
assign n107 = ~\totalcoeffs[0] & ~n106;
assign n108 = ~\totalcoeffs[1] & ~\trailingones[1] ;
assign n109 = ~\totalcoeffs[2] & \ctable[1] ;
assign n110 = \totalcoeffs[3] & ~n109;
assign n111 = n108 & ~n110;
assign n112 = ~n95 & ~n111;
assign n113 = ~\trailingones[0] & ~n112;
assign n114 = ~n107 & ~n113;
assign n115 = ~\ctable[0] & ~n114;
assign n116 = ~\totalcoeffs[0] & n40;
assign n117 = ~\trailingones[0] & n108;
assign n118 = n116 & n117;
assign n119 = ~n115 & ~n118;
assign n120 = ~n102 & n119;
assign n121 = ~n89 & n120;
assign n122 = ~\ctable[2] & ~n121;
assign n123 = ~n69 & ~n122;
assign n124 = ~\totalcoeffs[4] & ~n123;
assign n125 = ~\trailingones[0] & ~\trailingones[1] ;
assign n126 = ~\ctable[1] & n125;
assign n127 = \totalcoeffs[4] & \trailingones[0] ;
assign n128 = \ctable[1] & n127;
assign n129 = ~n126 & ~n128;
assign n130 = \ctable[0] & ~n129;
assign n131 = \ctable[1] & ~\trailingones[1] ;
assign n132 = \totalcoeffs[4] & \trailingones[1] ;
assign n133 = ~n131 & ~n132;
assign n134 = \ctable[0] & \ctable[1] ;
assign n135 = ~n133 & ~n134;
assign n136 = ~\trailingones[0] & n135;
assign n137 = ~n130 & ~n136;
assign n138 = ~\ctable[2] & ~n137;
assign n139 = ~\totalcoeffs[1] & ~\totalcoeffs[3] ;
assign n140 = ~\totalcoeffs[2] & n139;
assign n141 = n138 & n140;
assign n142 = ~\totalcoeffs[0] & n141;
assign \coeff_token[0] = n124 | n142;
assign n144 = \totalcoeffs[0] & \trailingones[0] ;
assign n145 = n95 & n144;
assign n146 = ~\totalcoeffs[2] & ~\trailingones[0] ;
assign n147 = n74 & n146;
assign n148 = ~n145 & ~n147;
assign n149 = \ctable[0] & ~n148;
assign n150 = ~\ctable[0] & \trailingones[0] ;
assign n151 = \ctable[1] & \trailingones[1] ;
assign n152 = ~n150 & ~n151;
assign n153 = ~\totalcoeffs[0] & ~n152;
assign n154 = \trailingones[0] & n151;
assign n155 = ~\trailingones[0] & n57;
assign n156 = ~n154 & ~n155;
assign n157 = ~n153 & n156;
assign n158 = \totalcoeffs[2] & ~n157;
assign n159 = ~n149 & ~n158;
assign n160 = ~\totalcoeffs[4] & ~n159;
assign n161 = ~\ctable[1] & \trailingones[1] ;
assign n162 = \ctable[0] & ~\trailingones[0] ;
assign n163 = ~n127 & ~n162;
assign n164 = ~\ctable[1] & ~n163;
assign n165 = ~n132 & ~n164;
assign n166 = ~n161 & ~n165;
assign n167 = n70 & n166;
assign n168 = ~n160 & ~n167;
assign n169 = ~\totalcoeffs[1] & ~n168;
assign n170 = \ctable[1] & \trailingones[0] ;
assign n171 = ~n152 & ~n170;
assign n172 = \totalcoeffs[0] & n171;
assign n173 = ~\totalcoeffs[0] & \ctable[0] ;
assign n174 = ~\trailingones[0] & \trailingones[1] ;
assign n175 = n173 & n174;
assign n176 = ~n172 & ~n175;
assign n177 = ~\totalcoeffs[2] & ~n176;
assign n178 = ~\ctable[1] & ~\trailingones[0] ;
assign n179 = ~\totalcoeffs[0] & \ctable[1] ;
assign n180 = ~\totalcoeffs[2] & ~n179;
assign n181 = n150 & ~n180;
assign n182 = ~n178 & ~n181;
assign n183 = ~\trailingones[1] & ~n182;
assign n184 = ~n177 & ~n183;
assign n185 = \totalcoeffs[1] & ~n184;
assign n186 = ~\ctable[1] & \trailingones[0] ;
assign n187 = n62 & n186;
assign n188 = ~n185 & ~n187;
assign n189 = ~\totalcoeffs[4] & ~n188;
assign n190 = ~n169 & ~n189;
assign n191 = ~\totalcoeffs[3] & ~n190;
assign n192 = \ctable[0] & n146;
assign n193 = ~\totalcoeffs[3] & ~\trailingones[0] ;
assign n194 = ~n150 & ~n193;
assign n195 = \totalcoeffs[0] & n194;
assign n196 = ~n192 & ~n195;
assign n197 = ~\totalcoeffs[1] & ~n196;
assign n198 = \totalcoeffs[3] & \trailingones[0] ;
assign n199 = ~\totalcoeffs[2] & ~n198;
assign n200 = ~\totalcoeffs[0] & ~n199;
assign n201 = ~\totalcoeffs[2] & \trailingones[0] ;
assign n202 = \totalcoeffs[0] & n201;
assign n203 = \totalcoeffs[0] & ~\ctable[0] ;
assign n204 = ~n173 & ~n203;
assign n205 = ~n202 & n204;
assign n206 = \totalcoeffs[1] & ~n205;
assign n207 = ~n200 & ~n206;
assign n208 = ~n197 & n207;
assign n209 = ~\ctable[1] & ~n208;
assign n210 = ~\totalcoeffs[1] & \ctable[1] ;
assign n211 = \totalcoeffs[2] & ~n210;
assign n212 = ~\totalcoeffs[1] & ~\trailingones[0] ;
assign n213 = ~n211 & ~n212;
assign n214 = \totalcoeffs[3] & n213;
assign n215 = ~\totalcoeffs[0] & \trailingones[0] ;
assign n216 = ~\totalcoeffs[1] & ~\ctable[1] ;
assign n217 = \totalcoeffs[0] & \totalcoeffs[1] ;
assign n218 = ~n216 & ~n217;
assign n219 = ~n215 & n218;
assign n220 = ~\totalcoeffs[2] & n219;
assign n221 = ~n214 & ~n220;
assign n222 = ~\ctable[0] & ~n221;
assign n223 = ~n209 & ~n222;
assign n224 = ~\trailingones[1] & ~n223;
assign n225 = \totalcoeffs[1] & \ctable[0] ;
assign n226 = \totalcoeffs[3] & ~\trailingones[0] ;
assign n227 = ~\totalcoeffs[1] & ~\totalcoeffs[2] ;
assign n228 = n226 & n227;
assign n229 = ~n225 & ~n228;
assign n230 = \totalcoeffs[0] & ~n229;
assign n231 = \ctable[0] & ~n40;
assign n232 = \totalcoeffs[3] & n37;
assign n233 = ~n231 & ~n232;
assign n234 = ~n230 & n233;
assign n235 = \ctable[1] & ~n234;
assign n236 = n162 & n232;
assign n237 = ~n235 & ~n236;
assign n238 = \trailingones[1] & ~n237;
assign n239 = ~n224 & ~n238;
assign n240 = ~\totalcoeffs[4] & ~n239;
assign n241 = ~n191 & ~n240;
assign n242 = ~\ctable[2] & ~n241;
assign n243 = \totalcoeffs[2] & ~n63;
assign n244 = n90 & ~n217;
assign n245 = ~n243 & ~n244;
assign n246 = ~\trailingones[0] & n245;
assign n247 = n30 & n201;
assign n248 = ~n246 & ~n247;
assign n249 = \ctable[2] & ~n248;
assign n250 = ~n64 & ~n249;
assign n251 = ~\totalcoeffs[4] & ~n250;
assign n252 = ~\ctable[1] & n251;
assign n253 = n22 & n252;
assign \coeff_token[1] = n242 | n253;
assign n255 = ~\totalcoeffs[3] & \trailingones[1] ;
assign n256 = ~n45 & ~n174;
assign n257 = ~n255 & ~n256;
assign n258 = ~\ctable[1] & n257;
assign n259 = \totalcoeffs[3] & ~n201;
assign n260 = \ctable[0] & ~n259;
assign n261 = \totalcoeffs[2] & ~\ctable[0] ;
assign n262 = \totalcoeffs[3] & ~n261;
assign n263 = \trailingones[0] & ~n262;
assign n264 = ~n260 & ~n263;
assign n265 = \totalcoeffs[1] & ~n264;
assign n266 = ~\ctable[0] & \ctable[1] ;
assign n267 = ~\trailingones[0] & n266;
assign n268 = n139 & n267;
assign n269 = ~n265 & ~n268;
assign n270 = ~\trailingones[1] & ~n269;
assign n271 = ~\totalcoeffs[1] & ~n199;
assign n272 = \totalcoeffs[2] & ~n186;
assign n273 = ~n271 & ~n272;
assign n274 = \ctable[0] & ~n273;
assign n275 = \totalcoeffs[1] & \trailingones[0] ;
assign n276 = \ctable[1] & ~n275;
assign n277 = ~\trailingones[1] & ~n276;
assign n278 = ~\totalcoeffs[2] & ~n277;
assign n279 = ~\totalcoeffs[1] & n174;
assign n280 = ~n278 & ~n279;
assign n281 = \totalcoeffs[3] & ~n280;
assign n282 = \ctable[1] & ~\trailingones[0] ;
assign n283 = \totalcoeffs[1] & n255;
assign n284 = n282 & n283;
assign n285 = ~n281 & ~n284;
assign n286 = ~n274 & n285;
assign n287 = ~n270 & n286;
assign n288 = ~n258 & n287;
assign n289 = ~\totalcoeffs[4] & ~n288;
assign n290 = \trailingones[0] & ~\trailingones[1] ;
assign n291 = ~n178 & ~n290;
assign n292 = ~\ctable[0] & n291;
assign n293 = ~\totalcoeffs[3] & \totalcoeffs[4] ;
assign n294 = ~\totalcoeffs[1] & n293;
assign n295 = ~n292 & n294;
assign n296 = ~\totalcoeffs[2] & n295;
assign n297 = ~n289 & ~n296;
assign n298 = ~\totalcoeffs[0] & ~n297;
assign n299 = \trailingones[0] & n75;
assign n300 = ~n125 & ~n299;
assign n301 = \ctable[0] & ~n300;
assign n302 = ~\ctable[0] & n95;
assign n303 = ~n301 & ~n302;
assign n304 = \totalcoeffs[1] & ~n303;
assign n305 = ~n174 & ~n290;
assign n306 = ~n108 & n305;
assign n307 = \totalcoeffs[2] & ~n306;
assign n308 = ~n304 & ~n307;
assign n309 = ~\totalcoeffs[3] & ~n308;
assign n310 = ~\totalcoeffs[1] & \totalcoeffs[3] ;
assign n311 = \ctable[0] & ~n310;
assign n312 = ~\totalcoeffs[2] & n125;
assign n313 = ~n311 & n312;
assign n314 = ~\totalcoeffs[1] & \trailingones[0] ;
assign n315 = n41 & n314;
assign n316 = ~n313 & ~n315;
assign n317 = \totalcoeffs[0] & ~n316;
assign n318 = ~n309 & ~n317;
assign n319 = ~\ctable[1] & ~n318;
assign n320 = \totalcoeffs[1] & \trailingones[1] ;
assign n321 = \totalcoeffs[2] & n320;
assign n322 = ~n314 & ~n321;
assign n323 = \ctable[1] & ~n322;
assign n324 = \trailingones[0] & ~n62;
assign n325 = \totalcoeffs[2] & n125;
assign n326 = ~n324 & ~n325;
assign n327 = ~n323 & n326;
assign n328 = \totalcoeffs[3] & ~n327;
assign n329 = \ctable[1] & ~n23;
assign n330 = ~n30 & ~n329;
assign n331 = \trailingones[0] & ~n330;
assign n332 = ~n108 & ~n320;
assign n333 = n193 & ~n332;
assign n334 = ~n331 & ~n333;
assign n335 = ~\totalcoeffs[2] & ~n334;
assign n336 = ~n328 & ~n335;
assign n337 = n203 & ~n336;
assign n338 = ~n319 & ~n337;
assign n339 = ~\totalcoeffs[4] & ~n338;
assign n340 = ~n298 & ~n339;
assign n341 = ~\ctable[2] & ~n340;
assign n342 = ~\ctable[0] & ~\ctable[1] ;
assign n343 = n51 & n75;
assign n344 = ~n74 & ~n343;
assign n345 = \totalcoeffs[1] & ~n344;
assign n346 = n28 & n212;
assign n347 = ~n345 & ~n346;
assign n348 = ~\totalcoeffs[4] & ~n347;
assign n349 = n40 & n348;
assign n350 = n342 & n349;
assign \coeff_token[2] = n341 | n350;
assign n352 = \totalcoeffs[3] & ~n161;
assign n353 = \totalcoeffs[2] & \ctable[1] ;
assign n354 = ~n352 & ~n353;
assign n355 = ~\totalcoeffs[4] & ~n354;
assign n356 = \trailingones[0] & \trailingones[1] ;
assign n357 = n342 & n356;
assign n358 = ~n134 & ~n357;
assign n359 = ~\totalcoeffs[2] & n293;
assign n360 = ~n358 & n359;
assign n361 = ~n355 & ~n360;
assign n362 = ~\totalcoeffs[1] & ~n361;
assign n363 = \ctable[0] & \trailingones[0] ;
assign n364 = n161 & n363;
assign n365 = ~n155 & ~n364;
assign n366 = \totalcoeffs[2] & ~n365;
assign n367 = \ctable[0] & ~n186;
assign n368 = \totalcoeffs[3] & ~n367;
assign n369 = ~n267 & ~n368;
assign n370 = ~n366 & n369;
assign n371 = \totalcoeffs[1] & ~n370;
assign n372 = \totalcoeffs[2] & n266;
assign n373 = ~n371 & ~n372;
assign n374 = ~\totalcoeffs[4] & ~n373;
assign n375 = ~n362 & ~n374;
assign n376 = ~\totalcoeffs[0] & ~n375;
assign n377 = \totalcoeffs[2] & ~n194;
assign n378 = ~\totalcoeffs[2] & n363;
assign n379 = ~n377 & ~n378;
assign n380 = ~\trailingones[1] & ~n379;
assign n381 = \ctable[0] & \trailingones[1] ;
assign n382 = ~\trailingones[0] & n381;
assign n383 = ~\totalcoeffs[3] & ~n382;
assign n384 = ~\totalcoeffs[2] & ~n383;
assign n385 = ~\ctable[1] & ~n226;
assign n386 = \totalcoeffs[3] & ~\ctable[0] ;
assign n387 = ~n385 & ~n386;
assign n388 = ~n384 & ~n387;
assign n389 = ~n380 & n388;
assign n390 = \totalcoeffs[1] & ~n389;
assign n391 = ~\totalcoeffs[3] & n266;
assign n392 = n192 & n216;
assign n393 = ~n391 & ~n392;
assign n394 = ~\trailingones[1] & ~n393;
assign n395 = ~n390 & ~n394;
assign n396 = \totalcoeffs[0] & ~n395;
assign n397 = ~n40 & n266;
assign n398 = \totalcoeffs[3] & ~\ctable[1] ;
assign n399 = \totalcoeffs[2] & n398;
assign n400 = ~n397 & ~n399;
assign n401 = \trailingones[1] & ~n400;
assign n402 = ~\trailingones[1] & n266;
assign n403 = ~n398 & ~n402;
assign n404 = ~\trailingones[0] & ~n403;
assign n405 = ~n401 & ~n404;
assign n406 = ~\totalcoeffs[1] & ~n405;
assign n407 = ~n57 & ~n178;
assign n408 = ~\totalcoeffs[2] & ~n407;
assign n409 = ~\ctable[1] & ~n381;
assign n410 = ~n320 & ~n363;
assign n411 = n409 & ~n410;
assign n412 = ~n408 & ~n411;
assign n413 = \totalcoeffs[3] & ~n412;
assign n414 = \totalcoeffs[1] & n290;
assign n415 = n266 & n414;
assign n416 = ~n413 & ~n415;
assign n417 = ~n406 & n416;
assign n418 = ~n396 & n417;
assign n419 = ~\totalcoeffs[4] & ~n418;
assign n420 = ~n376 & ~n419;
assign \coeff_token[3] = ~\ctable[2] & ~n420;
assign n422 = ~\totalcoeffs[4] & n243;
assign n423 = \totalcoeffs[3] & ~\totalcoeffs[4] ;
assign n424 = ~n293 & ~n423;
assign n425 = ~\totalcoeffs[0] & n227;
assign n426 = ~n424 & n425;
assign n427 = ~n422 & ~n426;
assign n428 = ~\ctable[2] & ~n427;
assign \coeff_token[4] = n134 & n428;
assign n430 = n63 & n359;
assign n431 = n423 & ~n425;
assign n432 = ~n430 & ~n431;
assign n433 = ~\ctable[2] & ~n432;
assign \coeff_token[5] = n134 & n433;
assign n435 = ~\totalcoeffs[1] & ~\ctable[0] ;
assign n436 = \totalcoeffs[2] & ~n435;
assign n437 = ~\trailingones[1] & ~n436;
assign n438 = ~\ctable[1] & n437;
assign n439 = \ctable[0] & n320;
assign n440 = ~n438 & ~n439;
assign n441 = \totalcoeffs[0] & ~n440;
assign n442 = ~\totalcoeffs[0] & ~n57;
assign n443 = \totalcoeffs[2] & n442;
assign n444 = ~n441 & ~n443;
assign n445 = \trailingones[0] & ~n444;
assign n446 = \totalcoeffs[2] & n24;
assign n447 = ~n117 & ~n446;
assign n448 = \ctable[0] & ~n447;
assign n449 = ~n445 & ~n448;
assign n450 = ~n125 & ~n356;
assign n451 = \ctable[1] & ~n450;
assign n452 = ~\totalcoeffs[2] & \trailingones[1] ;
assign n453 = ~n62 & ~n452;
assign n454 = n451 & n453;
assign n455 = n449 & ~n454;
assign n456 = ~\ctable[2] & ~n455;
assign n457 = \ctable[2] & ~\trailingones[1] ;
assign n458 = \trailingones[0] & ~n457;
assign n459 = n84 & ~n458;
assign n460 = ~n96 & ~n459;
assign n461 = ~\totalcoeffs[0] & ~n460;
assign n462 = n144 & n320;
assign n463 = ~n125 & ~n462;
assign n464 = \ctable[2] & ~n463;
assign n465 = ~\totalcoeffs[2] & n464;
assign n466 = ~n461 & ~n465;
assign n467 = n342 & ~n466;
assign n468 = ~n456 & ~n467;
assign n469 = ~\totalcoeffs[3] & ~n468;
assign n470 = ~n117 & ~n320;
assign n471 = \totalcoeffs[0] & ~n470;
assign n472 = \totalcoeffs[2] & n30;
assign n473 = ~n471 & ~n472;
assign n474 = ~\totalcoeffs[0] & ~\ctable[1] ;
assign n475 = ~n212 & n332;
assign n476 = n474 & n475;
assign n477 = n473 & ~n476;
assign n478 = ~\ctable[0] & ~n477;
assign n479 = ~\trailingones[0] & n217;
assign n480 = \totalcoeffs[0] & n170;
assign n481 = ~n105 & ~n480;
assign n482 = ~\totalcoeffs[2] & ~n481;
assign n483 = ~n479 & ~n482;
assign n484 = \trailingones[1] & ~n483;
assign n485 = ~\totalcoeffs[0] & ~\trailingones[0] ;
assign n486 = ~n203 & ~n485;
assign n487 = n30 & n486;
assign n488 = ~n484 & ~n487;
assign n489 = ~n478 & n488;
assign n490 = \totalcoeffs[3] & ~n489;
assign n491 = ~\totalcoeffs[2] & \ctable[0] ;
assign n492 = ~n76 & n491;
assign n493 = ~\ctable[1] & ~n261;
assign n494 = n24 & ~n493;
assign n495 = ~n492 & ~n494;
assign n496 = ~\trailingones[0] & ~n495;
assign n497 = \totalcoeffs[2] & ~n125;
assign n498 = ~n299 & ~n497;
assign n499 = \ctable[1] & ~n498;
assign n500 = ~n496 & ~n499;
assign n501 = \totalcoeffs[1] & ~n500;
assign n502 = ~\trailingones[0] & ~n474;
assign n503 = ~n203 & ~n502;
assign n504 = ~\trailingones[1] & ~n503;
assign n505 = ~\totalcoeffs[2] & n504;
assign n506 = \totalcoeffs[2] & \trailingones[0] ;
assign n507 = n24 & n506;
assign n508 = ~n505 & ~n507;
assign n509 = ~\totalcoeffs[1] & ~n508;
assign n510 = ~n501 & ~n509;
assign n511 = ~n490 & n510;
assign n512 = ~\ctable[2] & ~n511;
assign n513 = ~n469 & ~n512;
assign n514 = ~\totalcoeffs[4] & ~n513;
assign n515 = ~\totalcoeffs[1] & \totalcoeffs[4] ;
assign n516 = n116 & n515;
assign n517 = ~n134 & ~n516;
assign n518 = ~\ctable[2] & ~n517;
assign \ctoken_len[0] = ~n514 & ~n518;
assign n520 = ~\totalcoeffs[3] & \trailingones[0] ;
assign n521 = ~n151 & ~n520;
assign n522 = \totalcoeffs[0] & ~n521;
assign n523 = n215 & n398;
assign n524 = ~n282 & ~n523;
assign n525 = \trailingones[1] & ~n524;
assign n526 = ~\trailingones[1] & n170;
assign n527 = ~n525 & ~n526;
assign n528 = ~n522 & n527;
assign n529 = ~\totalcoeffs[2] & ~n528;
assign n530 = ~\totalcoeffs[3] & n356;
assign n531 = \totalcoeffs[3] & ~n356;
assign n532 = ~n144 & ~n531;
assign n533 = ~\ctable[1] & ~n532;
assign n534 = ~n530 & ~n533;
assign n535 = \totalcoeffs[2] & ~n534;
assign n536 = ~\totalcoeffs[3] & n126;
assign n537 = ~n535 & ~n536;
assign n538 = ~n529 & n537;
assign n539 = \totalcoeffs[1] & ~n538;
assign n540 = ~n74 & ~n174;
assign n541 = ~\ctable[1] & ~n540;
assign n542 = ~\totalcoeffs[2] & n541;
assign n543 = ~\totalcoeffs[0] & n451;
assign n544 = ~n542 & ~n543;
assign n545 = \totalcoeffs[3] & ~n544;
assign n546 = ~\totalcoeffs[0] & n146;
assign n547 = ~n480 & ~n546;
assign n548 = ~\trailingones[1] & ~n547;
assign n549 = ~\ctable[1] & ~n193;
assign n550 = n497 & ~n549;
assign n551 = ~n548 & ~n550;
assign n552 = ~n545 & n551;
assign n553 = ~\totalcoeffs[1] & ~n552;
assign n554 = ~\totalcoeffs[2] & \totalcoeffs[3] ;
assign n555 = ~\trailingones[1] & n282;
assign n556 = n554 & n555;
assign n557 = ~n553 & ~n556;
assign n558 = ~n539 & n557;
assign n559 = ~\ctable[0] & ~n558;
assign n560 = \totalcoeffs[0] & ~n453;
assign n561 = \ctable[0] & ~\trailingones[1] ;
assign n562 = ~\totalcoeffs[0] & n561;
assign n563 = ~n560 & ~n562;
assign n564 = \trailingones[0] & ~n563;
assign n565 = n95 & n162;
assign n566 = ~n564 & ~n565;
assign n567 = ~\totalcoeffs[3] & ~n566;
assign n568 = \totalcoeffs[3] & \ctable[0] ;
assign n569 = ~n62 & ~n568;
assign n570 = ~\totalcoeffs[0] & ~n569;
assign n571 = \totalcoeffs[3] & n491;
assign n572 = ~n570 & ~n571;
assign n573 = ~\trailingones[0] & ~n572;
assign n574 = n554 & n561;
assign n575 = ~n573 & ~n574;
assign n576 = ~n567 & n575;
assign n577 = \totalcoeffs[1] & ~n576;
assign n578 = \totalcoeffs[2] & \totalcoeffs[3] ;
assign n579 = ~\totalcoeffs[2] & ~n42;
assign n580 = ~n450 & ~n579;
assign n581 = ~n578 & ~n580;
assign n582 = \ctable[0] & ~n581;
assign n583 = n42 & n325;
assign n584 = ~n582 & ~n583;
assign n585 = ~\totalcoeffs[1] & ~n584;
assign n586 = \trailingones[0] & n381;
assign n587 = n578 & n586;
assign n588 = ~n585 & ~n587;
assign n589 = ~n577 & n588;
assign n590 = ~\ctable[1] & ~n589;
assign n591 = ~n559 & ~n590;
assign n592 = ~\ctable[2] & ~n591;
assign n593 = \totalcoeffs[2] & ~n305;
assign n594 = ~\totalcoeffs[0] & n593;
assign n595 = ~\trailingones[1] & n51;
assign n596 = n60 & n595;
assign n597 = ~n594 & ~n596;
assign n598 = n216 & ~n597;
assign n599 = n22 & n598;
assign n600 = ~n592 & ~n599;
assign n601 = ~\totalcoeffs[4] & ~n600;
assign n602 = n35 & n98;
assign n603 = \totalcoeffs[4] & ~\ctable[2] ;
assign n604 = n216 & n603;
assign n605 = n602 & n604;
assign \ctoken_len[1] = ~n601 & ~n605;
assign n607 = n227 & n561;
assign n608 = ~n283 & ~n607;
assign n609 = ~\totalcoeffs[0] & ~n608;
assign n610 = ~\totalcoeffs[1] & \ctable[0] ;
assign n611 = ~n22 & ~n610;
assign n612 = ~n108 & ~n255;
assign n613 = ~n611 & n612;
assign n614 = ~\totalcoeffs[2] & n613;
assign n615 = n332 & ~n435;
assign n616 = n103 & ~n615;
assign n617 = ~n614 & ~n616;
assign n618 = ~n609 & n617;
assign n619 = ~\trailingones[0] & ~n618;
assign n620 = ~n98 & ~n611;
assign n621 = ~\totalcoeffs[2] & n620;
assign n622 = n139 & n203;
assign n623 = ~n621 & ~n622;
assign n624 = \trailingones[0] & ~n623;
assign n625 = ~\ctable[0] & ~n215;
assign n626 = ~n568 & ~n625;
assign n627 = n37 & n626;
assign n628 = ~n624 & ~n627;
assign n629 = ~\trailingones[1] & ~n628;
assign n630 = ~n261 & ~n568;
assign n631 = ~n259 & ~n630;
assign n632 = \totalcoeffs[1] & n631;
assign n633 = ~n173 & n310;
assign n634 = n201 & n633;
assign n635 = ~n632 & ~n634;
assign n636 = \trailingones[1] & ~n635;
assign n637 = ~n629 & ~n636;
assign n638 = ~n619 & n637;
assign n639 = ~\ctable[1] & ~n638;
assign n640 = ~\totalcoeffs[1] & ~n125;
assign n641 = \totalcoeffs[2] & ~n640;
assign n642 = ~n329 & ~n641;
assign n643 = \totalcoeffs[0] & ~n642;
assign n644 = ~\ctable[1] & ~n105;
assign n645 = \totalcoeffs[2] & ~n644;
assign n646 = \trailingones[0] & ~n30;
assign n647 = n329 & ~n646;
assign n648 = ~n645 & ~n647;
assign n649 = ~n643 & n648;
assign n650 = n386 & ~n649;
assign n651 = ~n639 & ~n650;
assign n652 = ~\ctable[2] & ~n651;
assign n653 = ~n146 & ~n506;
assign n654 = ~\totalcoeffs[0] & ~n653;
assign n655 = ~n202 & ~n654;
assign n656 = ~\trailingones[1] & ~n655;
assign n657 = n95 & n485;
assign n658 = ~n656 & ~n657;
assign n659 = ~\totalcoeffs[1] & ~n658;
assign n660 = n320 & n546;
assign n661 = ~n659 & ~n660;
assign n662 = n22 & ~n661;
assign n663 = ~\ctable[1] & n662;
assign n664 = ~n652 & ~n663;
assign n665 = ~\totalcoeffs[4] & ~n664;
assign n666 = n22 & n603;
assign n667 = n425 & n666;
assign \ctoken_len[2] = ~n665 & ~n667;
assign n669 = \totalcoeffs[4] & ~n140;
assign n670 = n203 & n399;
assign n671 = ~\ctable[2] & ~n670;
assign n672 = ~n640 & ~n671;
assign n673 = ~\ctable[2] & ~n140;
assign n674 = \totalcoeffs[0] & ~n673;
assign n675 = \ctable[2] & ~n103;
assign n676 = ~\totalcoeffs[3] & ~n57;
assign n677 = \totalcoeffs[3] & ~n151;
assign n678 = n215 & ~n677;
assign n679 = ~n676 & ~n678;
assign n680 = ~\totalcoeffs[2] & ~n679;
assign n681 = ~n356 & n399;
assign n682 = ~\ctable[0] & n681;
assign n683 = ~\ctable[1] & ~n586;
assign n684 = ~\totalcoeffs[3] & ~n683;
assign n685 = ~n682 & ~n684;
assign n686 = ~n680 & n685;
assign n687 = \totalcoeffs[1] & ~n686;
assign n688 = n215 & ~n409;
assign n689 = ~n151 & ~n688;
assign n690 = \totalcoeffs[3] & ~n689;
assign n691 = \totalcoeffs[4] & ~n342;
assign n692 = ~\totalcoeffs[3] & ~n691;
assign n693 = ~n690 & ~n692;
assign n694 = ~\totalcoeffs[2] & ~n693;
assign n695 = ~\trailingones[0] & ~n381;
assign n696 = n676 & ~n695;
assign n697 = \totalcoeffs[2] & n696;
assign n698 = ~n694 & ~n697;
assign n699 = ~\totalcoeffs[1] & ~n698;
assign n700 = ~\ctable[0] & ~n103;
assign n701 = \ctable[1] & ~n700;
assign n702 = ~n699 & ~n701;
assign n703 = ~n687 & n702;
assign n704 = ~n675 & n703;
assign n705 = ~n674 & n704;
assign n706 = ~n672 & n705;
assign \ctoken_len[3] = ~n669 & n706;
assign n708 = ~\trailingones[0] & ~n29;
assign n709 = ~n25 & ~n708;
assign n710 = n423 & ~n709;
assign n711 = \totalcoeffs[2] & n710;
assign n712 = ~n430 & ~n711;
assign n713 = ~\ctable[2] & ~n712;
assign \ctoken_len[4] = n342 & n713;
endmodule |
module dec (
\count[0] , \count[1] , \count[2] , \count[3] , \count[4] , \count[5] ,
\count[6] , \count[7] ,
\selectp1[0] , \selectp1[1] , \selectp1[2] , \selectp1[3] ,
\selectp1[4] , \selectp1[5] , \selectp1[6] , \selectp1[7] ,
\selectp1[8] , \selectp1[9] , \selectp1[10] , \selectp1[11] ,
\selectp1[12] , \selectp1[13] , \selectp1[14] , \selectp1[15] ,
\selectp1[16] , \selectp1[17] , \selectp1[18] , \selectp1[19] ,
\selectp1[20] , \selectp1[21] , \selectp1[22] , \selectp1[23] ,
\selectp1[24] , \selectp1[25] , \selectp1[26] , \selectp1[27] ,
\selectp1[28] , \selectp1[29] , \selectp1[30] , \selectp1[31] ,
\selectp1[32] , \selectp1[33] , \selectp1[34] , \selectp1[35] ,
\selectp1[36] , \selectp1[37] , \selectp1[38] , \selectp1[39] ,
\selectp1[40] , \selectp1[41] , \selectp1[42] , \selectp1[43] ,
\selectp1[44] , \selectp1[45] , \selectp1[46] , \selectp1[47] ,
\selectp1[48] , \selectp1[49] , \selectp1[50] , \selectp1[51] ,
\selectp1[52] , \selectp1[53] , \selectp1[54] , \selectp1[55] ,
\selectp1[56] , \selectp1[57] , \selectp1[58] , \selectp1[59] ,
\selectp1[60] , \selectp1[61] , \selectp1[62] , \selectp1[63] ,
\selectp1[64] , \selectp1[65] , \selectp1[66] , \selectp1[67] ,
\selectp1[68] , \selectp1[69] , \selectp1[70] , \selectp1[71] ,
\selectp1[72] , \selectp1[73] , \selectp1[74] , \selectp1[75] ,
\selectp1[76] , \selectp1[77] , \selectp1[78] , \selectp1[79] ,
\selectp1[80] , \selectp1[81] , \selectp1[82] , \selectp1[83] ,
\selectp1[84] , \selectp1[85] , \selectp1[86] , \selectp1[87] ,
\selectp1[88] , \selectp1[89] , \selectp1[90] , \selectp1[91] ,
\selectp1[92] , \selectp1[93] , \selectp1[94] , \selectp1[95] ,
\selectp1[96] , \selectp1[97] , \selectp1[98] , \selectp1[99] ,
\selectp1[100] , \selectp1[101] , \selectp1[102] , \selectp1[103] ,
\selectp1[104] , \selectp1[105] , \selectp1[106] , \selectp1[107] ,
\selectp1[108] , \selectp1[109] , \selectp1[110] , \selectp1[111] ,
\selectp1[112] , \selectp1[113] , \selectp1[114] , \selectp1[115] ,
\selectp1[116] , \selectp1[117] , \selectp1[118] , \selectp1[119] ,
\selectp1[120] , \selectp1[121] , \selectp1[122] , \selectp1[123] ,
\selectp1[124] , \selectp1[125] , \selectp1[126] , \selectp1[127] ,
\selectp2[0] , \selectp2[1] , \selectp2[2] , \selectp2[3] ,
\selectp2[4] , \selectp2[5] , \selectp2[6] , \selectp2[7] ,
\selectp2[8] , \selectp2[9] , \selectp2[10] , \selectp2[11] ,
\selectp2[12] , \selectp2[13] , \selectp2[14] , \selectp2[15] ,
\selectp2[16] , \selectp2[17] , \selectp2[18] , \selectp2[19] ,
\selectp2[20] , \selectp2[21] , \selectp2[22] , \selectp2[23] ,
\selectp2[24] , \selectp2[25] , \selectp2[26] , \selectp2[27] ,
\selectp2[28] , \selectp2[29] , \selectp2[30] , \selectp2[31] ,
\selectp2[32] , \selectp2[33] , \selectp2[34] , \selectp2[35] ,
\selectp2[36] , \selectp2[37] , \selectp2[38] , \selectp2[39] ,
\selectp2[40] , \selectp2[41] , \selectp2[42] , \selectp2[43] ,
\selectp2[44] , \selectp2[45] , \selectp2[46] , \selectp2[47] ,
\selectp2[48] , \selectp2[49] , \selectp2[50] , \selectp2[51] ,
\selectp2[52] , \selectp2[53] , \selectp2[54] , \selectp2[55] ,
\selectp2[56] , \selectp2[57] , \selectp2[58] , \selectp2[59] ,
\selectp2[60] , \selectp2[61] , \selectp2[62] , \selectp2[63] ,
\selectp2[64] , \selectp2[65] , \selectp2[66] , \selectp2[67] ,
\selectp2[68] , \selectp2[69] , \selectp2[70] , \selectp2[71] ,
\selectp2[72] , \selectp2[73] , \selectp2[74] , \selectp2[75] ,
\selectp2[76] , \selectp2[77] , \selectp2[78] , \selectp2[79] ,
\selectp2[80] , \selectp2[81] , \selectp2[82] , \selectp2[83] ,
\selectp2[84] , \selectp2[85] , \selectp2[86] , \selectp2[87] ,
\selectp2[88] , \selectp2[89] , \selectp2[90] , \selectp2[91] ,
\selectp2[92] , \selectp2[93] , \selectp2[94] , \selectp2[95] ,
\selectp2[96] , \selectp2[97] , \selectp2[98] , \selectp2[99] ,
\selectp2[100] , \selectp2[101] , \selectp2[102] , \selectp2[103] ,
\selectp2[104] , \selectp2[105] , \selectp2[106] , \selectp2[107] ,
\selectp2[108] , \selectp2[109] , \selectp2[110] , \selectp2[111] ,
\selectp2[112] , \selectp2[113] , \selectp2[114] , \selectp2[115] ,
\selectp2[116] , \selectp2[117] , \selectp2[118] , \selectp2[119] ,
\selectp2[120] , \selectp2[121] , \selectp2[122] , \selectp2[123] ,
\selectp2[124] , \selectp2[125] , \selectp2[126] , \selectp2[127] );
input \count[0] , \count[1] , \count[2] , \count[3] , \count[4] ,
\count[5] , \count[6] , \count[7] ;
output \selectp1[0] , \selectp1[1] , \selectp1[2] , \selectp1[3] ,
\selectp1[4] , \selectp1[5] , \selectp1[6] , \selectp1[7] ,
\selectp1[8] , \selectp1[9] , \selectp1[10] , \selectp1[11] ,
\selectp1[12] , \selectp1[13] , \selectp1[14] , \selectp1[15] ,
\selectp1[16] , \selectp1[17] , \selectp1[18] , \selectp1[19] ,
\selectp1[20] , \selectp1[21] , \selectp1[22] , \selectp1[23] ,
\selectp1[24] , \selectp1[25] , \selectp1[26] , \selectp1[27] ,
\selectp1[28] , \selectp1[29] , \selectp1[30] , \selectp1[31] ,
\selectp1[32] , \selectp1[33] , \selectp1[34] , \selectp1[35] ,
\selectp1[36] , \selectp1[37] , \selectp1[38] , \selectp1[39] ,
\selectp1[40] , \selectp1[41] , \selectp1[42] , \selectp1[43] ,
\selectp1[44] , \selectp1[45] , \selectp1[46] , \selectp1[47] ,
\selectp1[48] , \selectp1[49] , \selectp1[50] , \selectp1[51] ,
\selectp1[52] , \selectp1[53] , \selectp1[54] , \selectp1[55] ,
\selectp1[56] , \selectp1[57] , \selectp1[58] , \selectp1[59] ,
\selectp1[60] , \selectp1[61] , \selectp1[62] , \selectp1[63] ,
\selectp1[64] , \selectp1[65] , \selectp1[66] , \selectp1[67] ,
\selectp1[68] , \selectp1[69] , \selectp1[70] , \selectp1[71] ,
\selectp1[72] , \selectp1[73] , \selectp1[74] , \selectp1[75] ,
\selectp1[76] , \selectp1[77] , \selectp1[78] , \selectp1[79] ,
\selectp1[80] , \selectp1[81] , \selectp1[82] , \selectp1[83] ,
\selectp1[84] , \selectp1[85] , \selectp1[86] , \selectp1[87] ,
\selectp1[88] , \selectp1[89] , \selectp1[90] , \selectp1[91] ,
\selectp1[92] , \selectp1[93] , \selectp1[94] , \selectp1[95] ,
\selectp1[96] , \selectp1[97] , \selectp1[98] , \selectp1[99] ,
\selectp1[100] , \selectp1[101] , \selectp1[102] , \selectp1[103] ,
\selectp1[104] , \selectp1[105] , \selectp1[106] , \selectp1[107] ,
\selectp1[108] , \selectp1[109] , \selectp1[110] , \selectp1[111] ,
\selectp1[112] , \selectp1[113] , \selectp1[114] , \selectp1[115] ,
\selectp1[116] , \selectp1[117] , \selectp1[118] , \selectp1[119] ,
\selectp1[120] , \selectp1[121] , \selectp1[122] , \selectp1[123] ,
\selectp1[124] , \selectp1[125] , \selectp1[126] , \selectp1[127] ,
\selectp2[0] , \selectp2[1] , \selectp2[2] , \selectp2[3] ,
\selectp2[4] , \selectp2[5] , \selectp2[6] , \selectp2[7] ,
\selectp2[8] , \selectp2[9] , \selectp2[10] , \selectp2[11] ,
\selectp2[12] , \selectp2[13] , \selectp2[14] , \selectp2[15] ,
\selectp2[16] , \selectp2[17] , \selectp2[18] , \selectp2[19] ,
\selectp2[20] , \selectp2[21] , \selectp2[22] , \selectp2[23] ,
\selectp2[24] , \selectp2[25] , \selectp2[26] , \selectp2[27] ,
\selectp2[28] , \selectp2[29] , \selectp2[30] , \selectp2[31] ,
\selectp2[32] , \selectp2[33] , \selectp2[34] , \selectp2[35] ,
\selectp2[36] , \selectp2[37] , \selectp2[38] , \selectp2[39] ,
\selectp2[40] , \selectp2[41] , \selectp2[42] , \selectp2[43] ,
\selectp2[44] , \selectp2[45] , \selectp2[46] , \selectp2[47] ,
\selectp2[48] , \selectp2[49] , \selectp2[50] , \selectp2[51] ,
\selectp2[52] , \selectp2[53] , \selectp2[54] , \selectp2[55] ,
\selectp2[56] , \selectp2[57] , \selectp2[58] , \selectp2[59] ,
\selectp2[60] , \selectp2[61] , \selectp2[62] , \selectp2[63] ,
\selectp2[64] , \selectp2[65] , \selectp2[66] , \selectp2[67] ,
\selectp2[68] , \selectp2[69] , \selectp2[70] , \selectp2[71] ,
\selectp2[72] , \selectp2[73] , \selectp2[74] , \selectp2[75] ,
\selectp2[76] , \selectp2[77] , \selectp2[78] , \selectp2[79] ,
\selectp2[80] , \selectp2[81] , \selectp2[82] , \selectp2[83] ,
\selectp2[84] , \selectp2[85] , \selectp2[86] , \selectp2[87] ,
\selectp2[88] , \selectp2[89] , \selectp2[90] , \selectp2[91] ,
\selectp2[92] , \selectp2[93] , \selectp2[94] , \selectp2[95] ,
\selectp2[96] , \selectp2[97] , \selectp2[98] , \selectp2[99] ,
\selectp2[100] , \selectp2[101] , \selectp2[102] , \selectp2[103] ,
\selectp2[104] , \selectp2[105] , \selectp2[106] , \selectp2[107] ,
\selectp2[108] , \selectp2[109] , \selectp2[110] , \selectp2[111] ,
\selectp2[112] , \selectp2[113] , \selectp2[114] , \selectp2[115] ,
\selectp2[116] , \selectp2[117] , \selectp2[118] , \selectp2[119] ,
\selectp2[120] , \selectp2[121] , \selectp2[122] , \selectp2[123] ,
\selectp2[124] , \selectp2[125] , \selectp2[126] , \selectp2[127] ;
wire n265, n266, n267, n268, n269, n270, n272, n273, n275, n276, n278,
n280, n281, n283, n284, n286, n288, n290, n291, n293, n295, n296, n298,
n300, n302, n304, n306, n308, n309, n326, n327, n344, n345, n362, n363,
n380, n397, n414, n431, n432, n449, n466, n483, n500, n501, n518, n535,
n552;
assign n265 = ~\count[4] & ~\count[5] ;
assign n266 = ~\count[6] & \count[7] ;
assign n267 = n265 & n266;
assign n268 = ~\count[0] & ~\count[2] ;
assign n269 = ~\count[1] & ~\count[3] ;
assign n270 = n268 & n269;
assign \selectp1[0] = n267 & n270;
assign n272 = \count[0] & ~\count[2] ;
assign n273 = n269 & n272;
assign \selectp1[1] = n267 & n273;
assign n275 = \count[1] & ~\count[3] ;
assign n276 = n268 & n275;
assign \selectp1[2] = n267 & n276;
assign n278 = n272 & n275;
assign \selectp1[3] = n267 & n278;
assign n280 = ~\count[0] & \count[2] ;
assign n281 = n269 & n280;
assign \selectp1[4] = n267 & n281;
assign n283 = \count[0] & \count[2] ;
assign n284 = n269 & n283;
assign \selectp1[5] = n267 & n284;
assign n286 = n275 & n280;
assign \selectp1[6] = n267 & n286;
assign n288 = n275 & n283;
assign \selectp1[7] = n267 & n288;
assign n290 = ~\count[1] & \count[3] ;
assign n291 = n268 & n290;
assign \selectp1[8] = n267 & n291;
assign n293 = n272 & n290;
assign \selectp1[9] = n267 & n293;
assign n295 = \count[1] & \count[3] ;
assign n296 = n268 & n295;
assign \selectp1[10] = n267 & n296;
assign n298 = n272 & n295;
assign \selectp1[11] = n267 & n298;
assign n300 = n280 & n290;
assign \selectp1[12] = n267 & n300;
assign n302 = n283 & n290;
assign \selectp1[13] = n267 & n302;
assign n304 = n280 & n295;
assign \selectp1[14] = n267 & n304;
assign n306 = n283 & n295;
assign \selectp1[15] = n267 & n306;
assign n308 = \count[4] & ~\count[5] ;
assign n309 = n266 & n308;
assign \selectp1[16] = n270 & n309;
assign \selectp1[17] = n273 & n309;
assign \selectp1[18] = n276 & n309;
assign \selectp1[19] = n278 & n309;
assign \selectp1[20] = n281 & n309;
assign \selectp1[21] = n284 & n309;
assign \selectp1[22] = n286 & n309;
assign \selectp1[23] = n288 & n309;
assign \selectp1[24] = n291 & n309;
assign \selectp1[25] = n293 & n309;
assign \selectp1[26] = n296 & n309;
assign \selectp1[27] = n298 & n309;
assign \selectp1[28] = n300 & n309;
assign \selectp1[29] = n302 & n309;
assign \selectp1[30] = n304 & n309;
assign \selectp1[31] = n306 & n309;
assign n326 = ~\count[4] & \count[5] ;
assign n327 = n266 & n326;
assign \selectp1[32] = n270 & n327;
assign \selectp1[33] = n273 & n327;
assign \selectp1[34] = n276 & n327;
assign \selectp1[35] = n278 & n327;
assign \selectp1[36] = n281 & n327;
assign \selectp1[37] = n284 & n327;
assign \selectp1[38] = n286 & n327;
assign \selectp1[39] = n288 & n327;
assign \selectp1[40] = n291 & n327;
assign \selectp1[41] = n293 & n327;
assign \selectp1[42] = n296 & n327;
assign \selectp1[43] = n298 & n327;
assign \selectp1[44] = n300 & n327;
assign \selectp1[45] = n302 & n327;
assign \selectp1[46] = n304 & n327;
assign \selectp1[47] = n306 & n327;
assign n344 = \count[4] & \count[5] ;
assign n345 = n266 & n344;
assign \selectp1[48] = n270 & n345;
assign \selectp1[49] = n273 & n345;
assign \selectp1[50] = n276 & n345;
assign \selectp1[51] = n278 & n345;
assign \selectp1[52] = n281 & n345;
assign \selectp1[53] = n284 & n345;
assign \selectp1[54] = n286 & n345;
assign \selectp1[55] = n288 & n345;
assign \selectp1[56] = n291 & n345;
assign \selectp1[57] = n293 & n345;
assign \selectp1[58] = n296 & n345;
assign \selectp1[59] = n298 & n345;
assign \selectp1[60] = n300 & n345;
assign \selectp1[61] = n302 & n345;
assign \selectp1[62] = n304 & n345;
assign \selectp1[63] = n306 & n345;
assign n362 = \count[6] & \count[7] ;
assign n363 = n265 & n362;
assign \selectp1[64] = n270 & n363;
assign \selectp1[65] = n273 & n363;
assign \selectp1[66] = n276 & n363;
assign \selectp1[67] = n278 & n363;
assign \selectp1[68] = n281 & n363;
assign \selectp1[69] = n284 & n363;
assign \selectp1[70] = n286 & n363;
assign \selectp1[71] = n288 & n363;
assign \selectp1[72] = n291 & n363;
assign \selectp1[73] = n293 & n363;
assign \selectp1[74] = n296 & n363;
assign \selectp1[75] = n298 & n363;
assign \selectp1[76] = n300 & n363;
assign \selectp1[77] = n302 & n363;
assign \selectp1[78] = n304 & n363;
assign \selectp1[79] = n306 & n363;
assign n380 = n308 & n362;
assign \selectp1[80] = n270 & n380;
assign \selectp1[81] = n273 & n380;
assign \selectp1[82] = n276 & n380;
assign \selectp1[83] = n278 & n380;
assign \selectp1[84] = n281 & n380;
assign \selectp1[85] = n284 & n380;
assign \selectp1[86] = n286 & n380;
assign \selectp1[87] = n288 & n380;
assign \selectp1[88] = n291 & n380;
assign \selectp1[89] = n293 & n380;
assign \selectp1[90] = n296 & n380;
assign \selectp1[91] = n298 & n380;
assign \selectp1[92] = n300 & n380;
assign \selectp1[93] = n302 & n380;
assign \selectp1[94] = n304 & n380;
assign \selectp1[95] = n306 & n380;
assign n397 = n326 & n362;
assign \selectp1[96] = n270 & n397;
assign \selectp1[97] = n273 & n397;
assign \selectp1[98] = n276 & n397;
assign \selectp1[99] = n278 & n397;
assign \selectp1[100] = n281 & n397;
assign \selectp1[101] = n284 & n397;
assign \selectp1[102] = n286 & n397;
assign \selectp1[103] = n288 & n397;
assign \selectp1[104] = n291 & n397;
assign \selectp1[105] = n293 & n397;
assign \selectp1[106] = n296 & n397;
assign \selectp1[107] = n298 & n397;
assign \selectp1[108] = n300 & n397;
assign \selectp1[109] = n302 & n397;
assign \selectp1[110] = n304 & n397;
assign \selectp1[111] = n306 & n397;
assign n414 = n344 & n362;
assign \selectp1[112] = n270 & n414;
assign \selectp1[113] = n273 & n414;
assign \selectp1[114] = n276 & n414;
assign \selectp1[115] = n278 & n414;
assign \selectp1[116] = n281 & n414;
assign \selectp1[117] = n284 & n414;
assign \selectp1[118] = n286 & n414;
assign \selectp1[119] = n288 & n414;
assign \selectp1[120] = n291 & n414;
assign \selectp1[121] = n293 & n414;
assign \selectp1[122] = n296 & n414;
assign \selectp1[123] = n298 & n414;
assign \selectp1[124] = n300 & n414;
assign \selectp1[125] = n302 & n414;
assign \selectp1[126] = n304 & n414;
assign \selectp1[127] = n306 & n414;
assign n431 = ~\count[6] & ~\count[7] ;
assign n432 = n265 & n431;
assign \selectp2[0] = n270 & n432;
assign \selectp2[1] = n273 & n432;
assign \selectp2[2] = n276 & n432;
assign \selectp2[3] = n278 & n432;
assign \selectp2[4] = n281 & n432;
assign \selectp2[5] = n284 & n432;
assign \selectp2[6] = n286 & n432;
assign \selectp2[7] = n288 & n432;
assign \selectp2[8] = n291 & n432;
assign \selectp2[9] = n293 & n432;
assign \selectp2[10] = n296 & n432;
assign \selectp2[11] = n298 & n432;
assign \selectp2[12] = n300 & n432;
assign \selectp2[13] = n302 & n432;
assign \selectp2[14] = n304 & n432;
assign \selectp2[15] = n306 & n432;
assign n449 = n308 & n431;
assign \selectp2[16] = n270 & n449;
assign \selectp2[17] = n273 & n449;
assign \selectp2[18] = n276 & n449;
assign \selectp2[19] = n278 & n449;
assign \selectp2[20] = n281 & n449;
assign \selectp2[21] = n284 & n449;
assign \selectp2[22] = n286 & n449;
assign \selectp2[23] = n288 & n449;
assign \selectp2[24] = n291 & n449;
assign \selectp2[25] = n293 & n449;
assign \selectp2[26] = n296 & n449;
assign \selectp2[27] = n298 & n449;
assign \selectp2[28] = n300 & n449;
assign \selectp2[29] = n302 & n449;
assign \selectp2[30] = n304 & n449;
assign \selectp2[31] = n306 & n449;
assign n466 = n326 & n431;
assign \selectp2[32] = n270 & n466;
assign \selectp2[33] = n273 & n466;
assign \selectp2[34] = n276 & n466;
assign \selectp2[35] = n278 & n466;
assign \selectp2[36] = n281 & n466;
assign \selectp2[37] = n284 & n466;
assign \selectp2[38] = n286 & n466;
assign \selectp2[39] = n288 & n466;
assign \selectp2[40] = n291 & n466;
assign \selectp2[41] = n293 & n466;
assign \selectp2[42] = n296 & n466;
assign \selectp2[43] = n298 & n466;
assign \selectp2[44] = n300 & n466;
assign \selectp2[45] = n302 & n466;
assign \selectp2[46] = n304 & n466;
assign \selectp2[47] = n306 & n466;
assign n483 = n344 & n431;
assign \selectp2[48] = n270 & n483;
assign \selectp2[49] = n273 & n483;
assign \selectp2[50] = n276 & n483;
assign \selectp2[51] = n278 & n483;
assign \selectp2[52] = n281 & n483;
assign \selectp2[53] = n284 & n483;
assign \selectp2[54] = n286 & n483;
assign \selectp2[55] = n288 & n483;
assign \selectp2[56] = n291 & n483;
assign \selectp2[57] = n293 & n483;
assign \selectp2[58] = n296 & n483;
assign \selectp2[59] = n298 & n483;
assign \selectp2[60] = n300 & n483;
assign \selectp2[61] = n302 & n483;
assign \selectp2[62] = n304 & n483;
assign \selectp2[63] = n306 & n483;
assign n500 = \count[6] & ~\count[7] ;
assign n501 = n265 & n500;
assign \selectp2[64] = n270 & n501;
assign \selectp2[65] = n273 & n501;
assign \selectp2[66] = n276 & n501;
assign \selectp2[67] = n278 & n501;
assign \selectp2[68] = n281 & n501;
assign \selectp2[69] = n284 & n501;
assign \selectp2[70] = n286 & n501;
assign \selectp2[71] = n288 & n501;
assign \selectp2[72] = n291 & n501;
assign \selectp2[73] = n293 & n501;
assign \selectp2[74] = n296 & n501;
assign \selectp2[75] = n298 & n501;
assign \selectp2[76] = n300 & n501;
assign \selectp2[77] = n302 & n501;
assign \selectp2[78] = n304 & n501;
assign \selectp2[79] = n306 & n501;
assign n518 = n308 & n500;
assign \selectp2[80] = n270 & n518;
assign \selectp2[81] = n273 & n518;
assign \selectp2[82] = n276 & n518;
assign \selectp2[83] = n278 & n518;
assign \selectp2[84] = n281 & n518;
assign \selectp2[85] = n284 & n518;
assign \selectp2[86] = n286 & n518;
assign \selectp2[87] = n288 & n518;
assign \selectp2[88] = n291 & n518;
assign \selectp2[89] = n293 & n518;
assign \selectp2[90] = n296 & n518;
assign \selectp2[91] = n298 & n518;
assign \selectp2[92] = n300 & n518;
assign \selectp2[93] = n302 & n518;
assign \selectp2[94] = n304 & n518;
assign \selectp2[95] = n306 & n518;
assign n535 = n326 & n500;
assign \selectp2[96] = n270 & n535;
assign \selectp2[97] = n273 & n535;
assign \selectp2[98] = n276 & n535;
assign \selectp2[99] = n278 & n535;
assign \selectp2[100] = n281 & n535;
assign \selectp2[101] = n284 & n535;
assign \selectp2[102] = n286 & n535;
assign \selectp2[103] = n288 & n535;
assign \selectp2[104] = n291 & n535;
assign \selectp2[105] = n293 & n535;
assign \selectp2[106] = n296 & n535;
assign \selectp2[107] = n298 & n535;
assign \selectp2[108] = n300 & n535;
assign \selectp2[109] = n302 & n535;
assign \selectp2[110] = n304 & n535;
assign \selectp2[111] = n306 & n535;
assign n552 = n344 & n500;
assign \selectp2[112] = n270 & n552;
assign \selectp2[113] = n273 & n552;
assign \selectp2[114] = n276 & n552;
assign \selectp2[115] = n278 & n552;
assign \selectp2[116] = n281 & n552;
assign \selectp2[117] = n284 & n552;
assign \selectp2[118] = n286 & n552;
assign \selectp2[119] = n288 & n552;
assign \selectp2[120] = n291 & n552;
assign \selectp2[121] = n293 & n552;
assign \selectp2[122] = n296 & n552;
assign \selectp2[123] = n298 & n552;
assign \selectp2[124] = n300 & n552;
assign \selectp2[125] = n302 & n552;
assign \selectp2[126] = n304 & n552;
assign \selectp2[127] = n306 & n552;
endmodule |
module top (
\opcode[0] , \opcode[1] , \opcode[2] , \opcode[3] , \opcode[4] ,
\op_ext[0] , \op_ext[1] ,
\sel_reg_dst[0] , \sel_reg_dst[1] , \sel_alu_opB[0] , \sel_alu_opB[1] ,
\alu_op[0] , \alu_op[1] , \alu_op[2] , \alu_op_ext[0] ,
\alu_op_ext[1] , \alu_op_ext[2] , \alu_op_ext[3] , halt, reg_write,
sel_pc_opA, sel_pc_opB, beqz, bnez, bgez, bltz, jump, Cin, invA, invB,
sign, mem_write, sel_wb );
input \opcode[0] , \opcode[1] , \opcode[2] , \opcode[3] , \opcode[4] ,
\op_ext[0] , \op_ext[1] ;
output \sel_reg_dst[0] , \sel_reg_dst[1] , \sel_alu_opB[0] ,
\sel_alu_opB[1] , \alu_op[0] , \alu_op[1] , \alu_op[2] ,
\alu_op_ext[0] , \alu_op_ext[1] , \alu_op_ext[2] , \alu_op_ext[3] ,
halt, reg_write, sel_pc_opA, sel_pc_opB, beqz, bnez, bgez, bltz, jump,
Cin, invA, invB, sign, mem_write, sel_wb;
wire n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n63, n64,
n65, n66, n67, n68, n69, n71, n72, n73, n74, n75, n76, n77, n78, n80,
n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94,
n95, n96, n97, n99, n100, n101, n102, n103, n104, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n117, n118, n119, n120, n121,
n123, n124, n125, n126, n127, n128, n129, n131, n132, n134, n135, n136,
n137, n139, n140, n141, n142, n143, n145, n146, n147, n148, n149, n150,
n151, n153, n154, n156, n158, n159, n160, n161, n162, n164, n165, n166,
n167, n169, n170, n171, n173, n174, n175, n177, n179, n180, n181, n182,
n183, n184, n185, n186, n188, n189, n190, n191, n192, n193, n194, n195,
n197, n198, n200, n201, n202, n203, n205, n206, n207;
assign n35 = \opcode[0] & ~\opcode[1] ;
assign n36 = \opcode[3] & \opcode[4] ;
assign n37 = n35 & n36;
assign n38 = \opcode[1] & \opcode[3] ;
assign n39 = \opcode[4] & n38;
assign n40 = ~n37 & ~n39;
assign n41 = ~\opcode[2] & ~n40;
assign n42 = ~\opcode[1] & \opcode[3] ;
assign n43 = \opcode[4] & n42;
assign n44 = ~\opcode[3] & ~\opcode[4] ;
assign n45 = ~n36 & ~n44;
assign n46 = \opcode[1] & ~n45;
assign n47 = ~n43 & ~n46;
assign n48 = \opcode[2] & ~n47;
assign \sel_reg_dst[0] = n41 | n48;
assign n50 = ~\opcode[0] & ~n36;
assign n51 = ~\opcode[0] & ~n50;
assign n52 = ~\opcode[1] & ~n51;
assign n53 = ~\opcode[3] & ~n44;
assign n54 = \opcode[1] & ~n53;
assign n55 = ~n52 & ~n54;
assign n56 = ~\opcode[2] & ~n55;
assign n57 = ~\opcode[3] & \opcode[4] ;
assign n58 = ~\opcode[3] & ~n57;
assign n59 = \opcode[1] & ~n58;
assign n60 = \opcode[1] & ~n59;
assign n61 = \opcode[2] & ~n60;
assign \sel_reg_dst[1] = ~n56 & ~n61;
assign n63 = ~\opcode[0] & ~n45;
assign n64 = \opcode[3] & ~n36;
assign n65 = \opcode[0] & ~n64;
assign n66 = ~n63 & ~n65;
assign n67 = \opcode[1] & ~n66;
assign n68 = ~n52 & ~n67;
assign n69 = ~\opcode[2] & ~n68;
assign \sel_alu_opB[0] = ~\opcode[2] & ~n69;
assign n71 = ~\opcode[0] & ~\opcode[3] ;
assign n72 = ~n57 & n71;
assign n73 = \opcode[0] & ~n45;
assign n74 = ~n72 & ~n73;
assign n75 = ~\opcode[1] & ~n74;
assign n76 = ~n54 & ~n75;
assign n77 = ~\opcode[2] & ~n76;
assign n78 = \opcode[2] & ~n53;
assign \sel_alu_opB[1] = ~n77 & ~n78;
assign n80 = ~\opcode[0] & \opcode[3] ;
assign n81 = \opcode[4] & \op_ext[0] ;
assign n82 = n80 & n81;
assign n83 = \opcode[3] & ~\op_ext[1] ;
assign n84 = ~n36 & n83;
assign n85 = \opcode[3] & ~\op_ext[0] ;
assign n86 = ~n36 & n85;
assign n87 = \opcode[3] & \op_ext[0] ;
assign n88 = ~n86 & ~n87;
assign n89 = \op_ext[1] & ~n88;
assign n90 = ~n84 & ~n89;
assign n91 = \opcode[0] & ~n90;
assign n92 = ~n82 & ~n91;
assign n93 = \opcode[1] & ~n92;
assign n94 = ~\opcode[2] & ~n93;
assign n95 = \opcode[0] & ~n53;
assign n96 = \opcode[0] & ~n95;
assign n97 = \opcode[2] & ~n96;
assign \alu_op[0] = ~n94 & ~n97;
assign n99 = \opcode[3] & \op_ext[1] ;
assign n100 = ~n84 & ~n99;
assign n101 = \opcode[1] & ~n100;
assign n102 = ~\opcode[2] & ~n101;
assign n103 = \opcode[1] & ~n54;
assign n104 = \opcode[2] & ~n103;
assign \alu_op[1] = ~n102 & ~n104;
assign n106 = ~\opcode[1] & ~n36;
assign n107 = ~n44 & n106;
assign n108 = ~n44 & n50;
assign n109 = \opcode[0] & ~n58;
assign n110 = ~n108 & ~n109;
assign n111 = \opcode[1] & ~n110;
assign n112 = ~n107 & ~n111;
assign n113 = ~\opcode[2] & ~n112;
assign n114 = \opcode[2] & \opcode[3] ;
assign n115 = \opcode[4] & n114;
assign \alu_op[2] = n113 | n115;
assign n117 = ~\opcode[1] & ~\opcode[2] ;
assign n118 = ~n52 & n117;
assign n119 = \opcode[1] & ~n74;
assign n120 = ~n37 & ~n119;
assign n121 = \opcode[2] & ~n120;
assign \alu_op_ext[0] = n118 | n121;
assign n123 = ~\opcode[0] & ~n53;
assign n124 = ~\opcode[0] & ~n123;
assign n125 = \opcode[1] & ~n124;
assign n126 = \opcode[1] & ~\opcode[2] ;
assign n127 = ~n125 & n126;
assign n128 = \opcode[1] & \opcode[2] ;
assign n129 = ~n45 & n128;
assign \alu_op_ext[1] = n127 | n129;
assign n131 = ~n106 & ~n125;
assign n132 = ~\opcode[2] & ~n131;
assign \alu_op_ext[2] = ~n61 & ~n132;
assign n134 = ~n80 & ~n109;
assign n135 = \opcode[1] & ~n134;
assign n136 = ~\opcode[2] & ~n107;
assign n137 = ~n135 & n136;
assign \alu_op_ext[3] = ~n78 & ~n137;
assign n139 = ~\opcode[0] & ~n58;
assign n140 = ~\opcode[0] & ~n139;
assign n141 = ~\opcode[1] & ~n140;
assign n142 = ~\opcode[1] & ~n141;
assign n143 = ~\opcode[2] & ~n142;
assign halt = ~\opcode[2] & ~n143;
assign n145 = ~\opcode[1] & ~n134;
assign n146 = ~n59 & ~n145;
assign n147 = ~\opcode[2] & ~n146;
assign n148 = ~\opcode[1] & \opcode[4] ;
assign n149 = \opcode[1] & ~n64;
assign n150 = ~n148 & ~n149;
assign n151 = \opcode[2] & ~n150;
assign reg_write = n147 | n151;
assign n153 = \opcode[0] & ~n109;
assign n154 = \opcode[2] & ~n153;
assign sel_pc_opA = \opcode[2] & ~n154;
assign n156 = \opcode[2] & ~n140;
assign sel_pc_opB = \opcode[2] & ~n156;
assign n158 = ~\opcode[0] & ~n64;
assign n159 = ~\opcode[0] & ~n158;
assign n160 = ~\opcode[1] & ~n159;
assign n161 = ~\opcode[1] & ~n160;
assign n162 = \opcode[2] & ~n161;
assign beqz = \opcode[2] & ~n162;
assign n164 = \opcode[0] & ~n65;
assign n165 = ~\opcode[1] & ~n164;
assign n166 = ~\opcode[1] & ~n165;
assign n167 = \opcode[2] & ~n166;
assign bnez = \opcode[2] & ~n167;
assign n169 = \opcode[1] & ~n164;
assign n170 = \opcode[1] & ~n169;
assign n171 = \opcode[2] & ~n170;
assign bgez = \opcode[2] & ~n171;
assign n173 = \opcode[1] & ~n159;
assign n174 = \opcode[1] & ~n173;
assign n175 = \opcode[2] & ~n174;
assign bltz = \opcode[2] & ~n175;
assign n177 = \opcode[2] & ~n58;
assign jump = \opcode[2] & ~n177;
assign n179 = \opcode[0] & \opcode[1] ;
assign n180 = ~n88 & n179;
assign n181 = n35 & ~n65;
assign n182 = ~\opcode[2] & ~n181;
assign n183 = ~n180 & n182;
assign n184 = \opcode[1] & ~n51;
assign n185 = ~n106 & ~n184;
assign n186 = \opcode[2] & ~n185;
assign Cin = ~n183 & ~n186;
assign n188 = \op_ext[0] & n36;
assign n189 = ~\op_ext[1] & ~n188;
assign n190 = ~\op_ext[1] & ~n189;
assign n191 = \opcode[0] & ~n190;
assign n192 = \opcode[0] & ~n191;
assign n193 = \opcode[1] & ~n192;
assign n194 = ~n165 & ~n193;
assign n195 = ~\opcode[2] & ~n194;
assign invA = ~\opcode[2] & ~n195;
assign n197 = ~n90 & n179;
assign n198 = ~\opcode[2] & ~n197;
assign invB = ~n186 & ~n198;
assign n200 = ~\opcode[1] & ~n124;
assign n201 = \opcode[1] & ~n96;
assign n202 = ~n200 & ~n201;
assign n203 = ~\opcode[2] & ~n202;
assign mem_write = ~\opcode[2] & ~n203;
assign n205 = ~\opcode[1] & ~n96;
assign n206 = ~\opcode[1] & ~n205;
assign n207 = ~\opcode[2] & ~n206;
assign sel_wb = ~\opcode[2] & ~n207;
assign sign = 1'b1;
endmodule |
module top (
\dest_x[0] , \dest_x[1] , \dest_x[2] , \dest_x[3] , \dest_x[4] ,
\dest_x[5] , \dest_x[6] , \dest_x[7] , \dest_x[8] , \dest_x[9] ,
\dest_x[10] , \dest_x[11] , \dest_x[12] , \dest_x[13] , \dest_x[14] ,
\dest_x[15] , \dest_x[16] , \dest_x[17] , \dest_x[18] , \dest_x[19] ,
\dest_x[20] , \dest_x[21] , \dest_x[22] , \dest_x[23] , \dest_x[24] ,
\dest_x[25] , \dest_x[26] , \dest_x[27] , \dest_x[28] , \dest_x[29] ,
\dest_y[0] , \dest_y[1] , \dest_y[2] , \dest_y[3] , \dest_y[4] ,
\dest_y[5] , \dest_y[6] , \dest_y[7] , \dest_y[8] , \dest_y[9] ,
\dest_y[10] , \dest_y[11] , \dest_y[12] , \dest_y[13] , \dest_y[14] ,
\dest_y[15] , \dest_y[16] , \dest_y[17] , \dest_y[18] , \dest_y[19] ,
\dest_y[20] , \dest_y[21] , \dest_y[22] , \dest_y[23] , \dest_y[24] ,
\dest_y[25] , \dest_y[26] , \dest_y[27] , \dest_y[28] , \dest_y[29] ,
\outport[0] , \outport[1] , \outport[2] , \outport[3] , \outport[4] ,
\outport[5] , \outport[6] , \outport[7] , \outport[8] , \outport[9] ,
\outport[10] , \outport[11] , \outport[12] , \outport[13] ,
\outport[14] , \outport[15] , \outport[16] , \outport[17] ,
\outport[18] , \outport[19] , \outport[20] , \outport[21] ,
\outport[22] , \outport[23] , \outport[24] , \outport[25] ,
\outport[26] , \outport[27] , \outport[28] , \outport[29] );
input \dest_x[0] , \dest_x[1] , \dest_x[2] , \dest_x[3] , \dest_x[4] ,
\dest_x[5] , \dest_x[6] , \dest_x[7] , \dest_x[8] , \dest_x[9] ,
\dest_x[10] , \dest_x[11] , \dest_x[12] , \dest_x[13] , \dest_x[14] ,
\dest_x[15] , \dest_x[16] , \dest_x[17] , \dest_x[18] , \dest_x[19] ,
\dest_x[20] , \dest_x[21] , \dest_x[22] , \dest_x[23] , \dest_x[24] ,
\dest_x[25] , \dest_x[26] , \dest_x[27] , \dest_x[28] , \dest_x[29] ,
\dest_y[0] , \dest_y[1] , \dest_y[2] , \dest_y[3] , \dest_y[4] ,
\dest_y[5] , \dest_y[6] , \dest_y[7] , \dest_y[8] , \dest_y[9] ,
\dest_y[10] , \dest_y[11] , \dest_y[12] , \dest_y[13] , \dest_y[14] ,
\dest_y[15] , \dest_y[16] , \dest_y[17] , \dest_y[18] , \dest_y[19] ,
\dest_y[20] , \dest_y[21] , \dest_y[22] , \dest_y[23] , \dest_y[24] ,
\dest_y[25] , \dest_y[26] , \dest_y[27] , \dest_y[28] , \dest_y[29] ;
output \outport[0] , \outport[1] , \outport[2] , \outport[3] , \outport[4] ,
\outport[5] , \outport[6] , \outport[7] , \outport[8] , \outport[9] ,
\outport[10] , \outport[11] , \outport[12] , \outport[13] ,
\outport[14] , \outport[15] , \outport[16] , \outport[17] ,
\outport[18] , \outport[19] , \outport[20] , \outport[21] ,
\outport[22] , \outport[23] , \outport[24] , \outport[25] ,
\outport[26] , \outport[27] , \outport[28] , \outport[29] ;
wire n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115, n116,
n117, n118, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133, n134, n135, n136, n137, n138, n139, n140,
n141, n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199, n200,
n201, n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212,
n213, n214, n215, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261,
n262, n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320, n321,
n322, n323, n324, n325, n326, n327, n328, n329, n330, n331, n332, n333,
n334, n335, n336, n337, n338, n339, n340, n341, n342, n343, n345, n346,
n347;
assign n92 = ~\dest_x[9] & ~\dest_x[10] ;
assign n93 = \dest_x[9] & \dest_x[10] ;
assign n94 = ~n92 & ~n93;
assign n95 = \dest_x[11] & ~n92;
assign n96 = ~\dest_x[11] & n92;
assign n97 = ~n95 & ~n96;
assign n98 = ~\dest_x[12] & ~n95;
assign n99 = \dest_x[12] & n95;
assign n100 = ~n98 & ~n99;
assign n101 = ~\dest_x[13] & n98;
assign n102 = \dest_x[13] & ~n98;
assign n103 = ~n101 & ~n102;
assign n104 = \dest_x[14] & ~n101;
assign n105 = ~\dest_x[14] & n101;
assign n106 = ~n104 & ~n105;
assign n107 = \dest_x[15] & ~n104;
assign n108 = ~\dest_x[15] & n104;
assign n109 = ~n107 & ~n108;
assign n110 = \dest_x[15] & n104;
assign n111 = ~\dest_x[16] & ~n110;
assign n112 = \dest_x[16] & n110;
assign n113 = ~n111 & ~n112;
assign n114 = \dest_x[17] & ~n111;
assign n115 = ~\dest_x[17] & n111;
assign n116 = ~n114 & ~n115;
assign n117 = ~\dest_x[18] & ~n114;
assign n118 = \dest_x[18] & n114;
assign n119 = ~n117 & ~n118;
assign n120 = \dest_x[19] & ~n117;
assign n121 = ~\dest_x[19] & n117;
assign n122 = ~n120 & ~n121;
assign n123 = \dest_x[20] & ~n120;
assign n124 = ~\dest_x[20] & n120;
assign n125 = ~n123 & ~n124;
assign n126 = \dest_x[20] & n120;
assign n127 = ~\dest_x[21] & ~n126;
assign n128 = \dest_x[21] & n126;
assign n129 = ~n127 & ~n128;
assign n130 = ~\dest_x[22] & n127;
assign n131 = \dest_x[22] & ~n127;
assign n132 = ~n130 & ~n131;
assign n133 = \dest_x[23] & ~n130;
assign n134 = ~\dest_x[23] & n130;
assign n135 = ~n133 & ~n134;
assign n136 = \dest_x[24] & ~n133;
assign n137 = ~\dest_x[24] & n133;
assign n138 = ~n136 & ~n137;
assign n139 = \dest_x[24] & n133;
assign n140 = \dest_x[25] & ~n139;
assign n141 = ~\dest_x[25] & n139;
assign n142 = ~n140 & ~n141;
assign n143 = \dest_x[25] & n139;
assign n144 = ~\dest_x[26] & ~n143;
assign n145 = \dest_x[26] & n143;
assign n146 = ~n144 & ~n145;
assign n147 = \dest_x[27] & ~n144;
assign n148 = ~\dest_x[27] & n144;
assign n149 = ~n147 & ~n148;
assign n150 = \dest_x[28] & ~n147;
assign n151 = ~\dest_x[28] & n147;
assign n152 = ~n150 & ~n151;
assign n153 = \dest_x[28] & n147;
assign n154 = ~\dest_x[29] & n153;
assign n155 = \dest_x[29] & ~n153;
assign n156 = ~n154 & ~n155;
assign n157 = ~\dest_x[9] & ~n156;
assign n158 = ~n152 & n157;
assign n159 = n149 & n158;
assign n160 = ~n146 & n159;
assign n161 = ~n142 & n160;
assign n162 = ~n138 & n161;
assign n163 = n135 & n162;
assign n164 = ~n132 & n163;
assign n165 = ~n129 & n164;
assign n166 = ~n125 & n165;
assign n167 = n122 & n166;
assign n168 = ~n119 & n167;
assign n169 = n116 & n168;
assign n170 = ~n113 & n169;
assign n171 = ~n109 & n170;
assign n172 = n106 & n171;
assign n173 = ~n103 & n172;
assign n174 = ~n100 & n173;
assign n175 = n97 & n174;
assign n176 = ~n94 & n175;
assign n177 = \dest_x[8] & n176;
assign n178 = \dest_x[7] & n177;
assign n179 = \dest_x[6] & n178;
assign n180 = \dest_x[5] & n179;
assign n181 = \dest_x[4] & n180;
assign n182 = \dest_x[3] & n181;
assign n183 = \dest_x[2] & n182;
assign n184 = \dest_x[1] & n183;
assign n185 = \dest_x[0] & n184;
assign n186 = \dest_x[29] & n153;
assign n187 = ~n185 & ~n186;
assign n188 = ~\dest_x[1] & ~\dest_x[2] ;
assign n189 = ~\dest_x[3] & n188;
assign n190 = ~\dest_x[4] & n189;
assign n191 = ~\dest_x[5] & n190;
assign n192 = ~\dest_x[6] & n191;
assign n193 = ~\dest_x[7] & n192;
assign n194 = ~\dest_x[8] & n193;
assign n195 = n94 & n194;
assign n196 = ~n97 & n195;
assign n197 = n100 & n196;
assign n198 = n103 & n197;
assign n199 = ~n106 & n198;
assign n200 = n109 & n199;
assign n201 = n113 & n200;
assign n202 = ~n116 & n201;
assign n203 = n119 & n202;
assign n204 = ~n122 & n203;
assign n205 = n125 & n204;
assign n206 = n129 & n205;
assign n207 = n132 & n206;
assign n208 = ~n135 & n207;
assign n209 = n138 & n208;
assign n210 = n142 & n209;
assign n211 = n146 & n210;
assign n212 = ~n149 & n211;
assign n213 = n152 & n212;
assign n214 = \dest_x[9] & n213;
assign n215 = n186 & ~n214;
assign \outport[0] = n187 | n215;
assign n217 = ~\dest_y[9] & ~\dest_y[10] ;
assign n218 = \dest_y[11] & ~n217;
assign n219 = ~\dest_y[12] & ~n218;
assign n220 = ~\dest_y[13] & n219;
assign n221 = \dest_y[14] & ~n220;
assign n222 = \dest_y[15] & n221;
assign n223 = ~\dest_y[16] & ~n222;
assign n224 = \dest_y[17] & ~n223;
assign n225 = ~\dest_y[18] & ~n224;
assign n226 = \dest_y[19] & ~n225;
assign n227 = \dest_y[20] & n226;
assign n228 = ~\dest_y[21] & ~n227;
assign n229 = ~\dest_y[22] & n228;
assign n230 = \dest_y[23] & ~n229;
assign n231 = \dest_y[24] & n230;
assign n232 = \dest_y[25] & n231;
assign n233 = ~\dest_y[26] & ~n232;
assign n234 = \dest_y[27] & ~n233;
assign n235 = \dest_y[28] & n234;
assign n236 = \dest_y[29] & n235;
assign n237 = \dest_x[0] & ~n236;
assign n238 = ~\dest_x[0] & ~\dest_y[0] ;
assign n239 = n236 & ~n238;
assign n240 = \dest_y[9] & \dest_y[10] ;
assign n241 = ~n217 & ~n240;
assign n242 = ~\dest_y[11] & n217;
assign n243 = ~n218 & ~n242;
assign n244 = \dest_y[12] & n218;
assign n245 = ~n219 & ~n244;
assign n246 = \dest_y[13] & ~n219;
assign n247 = ~n220 & ~n246;
assign n248 = ~\dest_y[14] & n220;
assign n249 = ~n221 & ~n248;
assign n250 = \dest_y[15] & ~n221;
assign n251 = ~\dest_y[15] & n221;
assign n252 = ~n250 & ~n251;
assign n253 = \dest_y[16] & n222;
assign n254 = ~n223 & ~n253;
assign n255 = ~\dest_y[17] & n223;
assign n256 = ~n224 & ~n255;
assign n257 = \dest_y[18] & n224;
assign n258 = ~n225 & ~n257;
assign n259 = ~\dest_y[19] & n225;
assign n260 = ~n226 & ~n259;
assign n261 = \dest_y[20] & ~n226;
assign n262 = ~\dest_y[20] & n226;
assign n263 = ~n261 & ~n262;
assign n264 = \dest_y[21] & n227;
assign n265 = ~n228 & ~n264;
assign n266 = \dest_y[22] & ~n228;
assign n267 = ~n229 & ~n266;
assign n268 = ~\dest_y[23] & n229;
assign n269 = ~n230 & ~n268;
assign n270 = \dest_y[24] & ~n230;
assign n271 = ~\dest_y[24] & n230;
assign n272 = ~n270 & ~n271;
assign n273 = \dest_y[25] & ~n231;
assign n274 = ~\dest_y[25] & n231;
assign n275 = ~n273 & ~n274;
assign n276 = \dest_y[26] & n232;
assign n277 = ~n233 & ~n276;
assign n278 = ~\dest_y[27] & n233;
assign n279 = ~n234 & ~n278;
assign n280 = \dest_y[28] & ~n234;
assign n281 = ~\dest_y[28] & n234;
assign n282 = ~n280 & ~n281;
assign n283 = \dest_y[0] & ~\dest_y[9] ;
assign n284 = \dest_y[29] & n283;
assign n285 = ~n282 & n284;
assign n286 = n279 & n285;
assign n287 = ~n277 & n286;
assign n288 = ~n275 & n287;
assign n289 = ~n272 & n288;
assign n290 = n269 & n289;
assign n291 = ~n267 & n290;
assign n292 = ~n265 & n291;
assign n293 = ~n263 & n292;
assign n294 = n260 & n293;
assign n295 = ~n258 & n294;
assign n296 = n256 & n295;
assign n297 = ~n254 & n296;
assign n298 = ~n252 & n297;
assign n299 = n249 & n298;
assign n300 = ~n247 & n299;
assign n301 = ~n245 & n300;
assign n302 = n243 & n301;
assign n303 = ~n241 & n302;
assign n304 = \dest_y[8] & n303;
assign n305 = \dest_y[7] & n304;
assign n306 = \dest_y[6] & n305;
assign n307 = \dest_y[5] & n306;
assign n308 = \dest_y[4] & n307;
assign n309 = \dest_y[3] & n308;
assign n310 = \dest_y[2] & n309;
assign n311 = \dest_y[1] & n310;
assign n312 = ~\dest_y[1] & ~\dest_y[2] ;
assign n313 = ~\dest_y[3] & n312;
assign n314 = ~\dest_y[4] & n313;
assign n315 = ~\dest_y[5] & n314;
assign n316 = ~\dest_y[6] & n315;
assign n317 = ~\dest_y[7] & n316;
assign n318 = ~\dest_y[8] & n317;
assign n319 = n241 & n318;
assign n320 = ~n243 & n319;
assign n321 = n245 & n320;
assign n322 = n247 & n321;
assign n323 = ~n249 & n322;
assign n324 = n252 & n323;
assign n325 = n254 & n324;
assign n326 = ~n256 & n325;
assign n327 = n258 & n326;
assign n328 = ~n260 & n327;
assign n329 = n263 & n328;
assign n330 = n265 & n329;
assign n331 = n267 & n330;
assign n332 = ~n269 & n331;
assign n333 = n272 & n332;
assign n334 = n275 & n333;
assign n335 = n277 & n334;
assign n336 = ~n279 & n335;
assign n337 = n282 & n336;
assign n338 = \dest_y[9] & n337;
assign n339 = n236 & ~n338;
assign n340 = ~n311 & ~n339;
assign n341 = ~n239 & n340;
assign n342 = ~n187 & ~n341;
assign n343 = ~n237 & n342;
assign \outport[1] = ~n215 & ~n343;
assign n345 = \dest_x[0] & n236;
assign n346 = \dest_y[0] & n345;
assign n347 = ~n339 & ~n346;
assign \outport[2] = ~\outport[0] & ~n347;
assign \outport[3] = 1'b0;
assign \outport[4] = 1'b0;
assign \outport[5] = 1'b0;
assign \outport[6] = 1'b0;
assign \outport[7] = 1'b0;
assign \outport[8] = 1'b0;
assign \outport[9] = 1'b0;
assign \outport[10] = 1'b0;
assign \outport[11] = 1'b0;
assign \outport[12] = 1'b0;
assign \outport[13] = 1'b0;
assign \outport[14] = 1'b0;
assign \outport[15] = 1'b0;
assign \outport[16] = 1'b0;
assign \outport[17] = 1'b0;
assign \outport[18] = 1'b0;
assign \outport[19] = 1'b0;
assign \outport[20] = 1'b0;
assign \outport[21] = 1'b0;
assign \outport[22] = 1'b0;
assign \outport[23] = 1'b0;
assign \outport[24] = 1'b0;
assign \outport[25] = 1'b0;
assign \outport[26] = 1'b0;
assign \outport[27] = 1'b0;
assign \outport[28] = 1'b0;
assign \outport[29] = 1'b0;
endmodule |
module top (
\B[0] , \B[1] , \B[2] , \B[3] , \B[4] , \B[5] , \B[6] , \B[7] , \B[8] ,
\B[9] , \B[10] ,
\M[0] , \M[1] , \M[2] , \M[3] , \E[0] , \E[1] , \E[2] );
input \B[0] , \B[1] , \B[2] , \B[3] , \B[4] , \B[5] , \B[6] , \B[7] ,
\B[8] , \B[9] , \B[10] ;
output \M[0] , \M[1] , \M[2] , \M[3] , \E[0] , \E[1] , \E[2] ;
wire n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32,
n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89,
n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102,
n103, n104, n105, n106, n107, n108, n109, n110, n111, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143, n144, n145, n147, n148, n149, n150, n151,
n152, n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187,
n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n210, n211, n212,
n213, n214, n215, n216, n217, n218, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236, n237,
n238, n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n274, n275,
n276, n277;
assign n19 = ~\B[1] & \B[4] ;
assign n20 = ~\B[4] & ~\B[8] ;
assign n21 = ~n19 & ~n20;
assign n22 = \B[0] & ~n21;
assign n23 = \B[1] & \B[4] ;
assign n24 = ~\B[0] & n23;
assign n25 = ~n22 & ~n24;
assign n26 = ~\B[6] & ~n25;
assign n27 = ~\B[7] & n26;
assign n28 = \B[4] & \B[8] ;
assign n29 = ~n27 & ~n28;
assign n30 = ~\B[5] & ~n29;
assign n31 = ~\B[4] & \B[7] ;
assign n32 = \B[1] & ~\B[2] ;
assign n33 = \B[5] & ~\B[7] ;
assign n34 = n32 & n33;
assign n35 = ~n31 & ~n34;
assign n36 = \B[3] & ~n35;
assign n37 = \B[4] & \B[7] ;
assign n38 = ~\B[3] & n37;
assign n39 = ~n36 & ~n38;
assign n40 = ~\B[8] & ~n39;
assign n41 = \B[5] & \B[8] ;
assign n42 = ~\B[4] & n41;
assign n43 = ~n40 & ~n42;
assign n44 = ~n30 & n43;
assign n45 = ~\B[9] & ~n44;
assign n46 = \B[4] & ~\B[8] ;
assign n47 = ~\B[3] & n46;
assign n48 = ~\B[4] & ~\B[7] ;
assign n49 = ~n47 & ~n48;
assign n50 = ~\B[2] & ~n49;
assign n51 = \B[1] & n50;
assign n52 = ~\B[1] & \B[2] ;
assign n53 = ~\B[7] & ~\B[8] ;
assign n54 = n52 & n53;
assign n55 = ~\B[9] & ~n54;
assign n56 = ~n51 & n55;
assign n57 = ~\B[6] & ~n56;
assign n58 = \B[5] & n57;
assign n59 = \B[6] & \B[9] ;
assign n60 = ~\B[5] & n59;
assign n61 = ~n58 & ~n60;
assign n62 = ~n45 & n61;
assign n63 = ~\B[10] & ~n62;
assign n64 = ~\B[2] & \B[3] ;
assign n65 = \B[2] & ~\B[3] ;
assign n66 = ~n64 & ~n65;
assign n67 = ~\B[9] & ~n66;
assign n68 = ~\B[8] & n67;
assign n69 = ~\B[10] & ~n68;
assign n70 = ~\B[7] & ~n69;
assign n71 = \B[9] & \B[10] ;
assign n72 = \B[8] & n71;
assign n73 = ~n70 & ~n72;
assign n74 = \B[6] & ~n73;
assign n75 = ~\B[6] & \B[10] ;
assign n76 = \B[7] & n75;
assign n77 = ~n74 & ~n76;
assign \M[0] = n63 | ~n77;
assign n79 = ~\B[4] & ~\B[9] ;
assign n80 = ~\B[2] & ~\B[7] ;
assign n81 = ~n79 & ~n80;
assign n82 = ~\B[1] & ~n81;
assign n83 = \B[1] & \B[2] ;
assign n84 = \B[0] & n83;
assign n85 = ~\B[0] & ~\B[2] ;
assign n86 = ~n84 & ~n85;
assign n87 = ~\B[7] & ~n86;
assign n88 = \B[4] & n87;
assign n89 = \B[8] & ~\B[9] ;
assign n90 = ~n88 & ~n89;
assign n91 = ~n82 & n90;
assign n92 = ~\B[6] & ~n91;
assign n93 = \B[3] & \B[4] ;
assign n94 = \B[7] & ~n93;
assign n95 = ~\B[9] & n94;
assign n96 = ~\B[8] & n95;
assign n97 = ~\B[7] & \B[9] ;
assign n98 = ~n96 & ~n97;
assign n99 = ~n92 & n98;
assign n100 = ~\B[5] & ~n99;
assign n101 = ~\B[8] & ~\B[9] ;
assign n102 = \B[4] & n101;
assign n103 = ~\B[6] & ~\B[7] ;
assign n104 = ~\B[4] & n103;
assign n105 = ~n102 & ~n104;
assign n106 = \B[2] & ~n105;
assign n107 = \B[1] & n106;
assign n108 = \B[7] & ~\B[9] ;
assign n109 = n46 & n108;
assign n110 = ~n107 & ~n109;
assign n111 = \B[3] & ~n110;
assign n112 = \B[4] & n89;
assign n113 = \B[7] & \B[9] ;
assign n114 = ~n112 & ~n113;
assign n115 = \B[6] & ~n114;
assign n116 = ~n111 & ~n115;
assign n117 = \B[5] & ~n116;
assign n118 = ~\B[4] & n89;
assign n119 = ~n97 & ~n118;
assign n120 = ~\B[6] & ~n119;
assign n121 = ~n117 & ~n120;
assign n122 = ~n100 & n121;
assign n123 = ~\B[10] & ~n122;
assign n124 = \B[6] & ~\B[9] ;
assign n125 = ~\B[4] & n124;
assign n126 = \B[5] & ~\B[6] ;
assign n127 = ~\B[3] & n126;
assign n128 = ~n125 & ~n127;
assign n129 = ~\B[2] & ~n128;
assign n130 = ~\B[1] & n126;
assign n131 = ~n125 & ~n130;
assign n132 = ~\B[3] & ~n131;
assign n133 = \B[2] & \B[3] ;
assign n134 = \B[4] & n124;
assign n135 = n133 & n134;
assign n136 = ~\B[10] & ~n135;
assign n137 = ~n132 & n136;
assign n138 = ~n129 & n137;
assign n139 = ~\B[7] & ~n138;
assign n140 = ~n75 & ~n139;
assign n141 = ~\B[8] & ~n140;
assign n142 = \B[6] & \B[10] ;
assign n143 = \B[7] & n142;
assign n144 = n89 & n143;
assign n145 = ~n141 & ~n144;
assign \M[1] = ~n123 & n145;
assign n147 = \B[4] & ~\B[6] ;
assign n148 = \B[0] & ~\B[3] ;
assign n149 = n147 & n148;
assign n150 = ~\B[4] & \B[5] ;
assign n151 = \B[3] & n150;
assign n152 = ~n149 & ~n151;
assign n153 = \B[1] & ~n152;
assign n154 = ~\B[4] & ~\B[6] ;
assign n155 = \B[0] & \B[1] ;
assign n156 = \B[4] & ~n155;
assign n157 = \B[3] & n156;
assign n158 = ~n154 & ~n157;
assign n159 = ~\B[5] & ~n158;
assign n160 = ~n153 & ~n159;
assign n161 = \B[2] & ~n160;
assign n162 = \B[3] & ~\B[6] ;
assign n163 = ~\B[2] & n162;
assign n164 = ~\B[3] & \B[5] ;
assign n165 = ~n163 & ~n164;
assign n166 = \B[4] & ~n165;
assign n167 = ~n161 & ~n166;
assign n168 = ~\B[7] & ~n167;
assign n169 = ~\B[5] & \B[6] ;
assign n170 = \B[2] & n169;
assign n171 = ~n130 & ~n170;
assign n172 = \B[4] & ~n171;
assign n173 = \B[3] & n172;
assign n174 = \B[5] & ~n93;
assign n175 = \B[6] & n174;
assign n176 = ~n173 & ~n175;
assign n177 = ~n168 & n176;
assign n178 = ~\B[8] & ~n177;
assign n179 = ~\B[6] & \B[7] ;
assign n180 = \B[3] & n179;
assign n181 = \B[6] & ~\B[7] ;
assign n182 = ~\B[2] & n181;
assign n183 = ~n180 & ~n182;
assign n184 = \B[5] & ~n183;
assign n185 = \B[4] & n184;
assign n186 = \B[4] & \B[5] ;
assign n187 = \B[7] & ~n186;
assign n188 = \B[6] & n187;
assign n189 = ~n185 & ~n188;
assign n190 = ~n178 & n189;
assign n191 = ~\B[9] & ~n190;
assign n192 = \B[4] & \B[6] ;
assign n193 = n33 & n192;
assign n194 = ~n179 & ~n193;
assign n195 = \B[8] & ~n194;
assign n196 = ~n191 & ~n195;
assign n197 = ~\B[10] & ~n196;
assign n198 = \B[8] & \B[10] ;
assign n199 = ~\B[8] & \B[9] ;
assign n200 = \B[5] & n199;
assign n201 = ~n198 & ~n200;
assign n202 = \B[7] & ~n201;
assign n203 = \B[6] & n202;
assign n204 = \B[5] & \B[7] ;
assign n205 = \B[8] & ~n204;
assign n206 = ~\B[10] & ~n205;
assign n207 = \B[9] & ~n206;
assign n208 = ~n203 & ~n207;
assign \M[2] = n197 | ~n208;
assign n210 = \B[6] & \B[7] ;
assign n211 = ~\B[2] & n210;
assign n212 = \B[5] & n28;
assign n213 = n211 & n212;
assign n214 = ~\B[5] & n20;
assign n215 = n103 & n214;
assign n216 = ~n213 & ~n215;
assign n217 = ~\B[9] & ~n216;
assign n218 = ~\B[10] & n217;
assign \M[3] = \B[3] | ~n218;
assign n220 = \B[5] & \B[6] ;
assign n221 = \B[4] & ~\B[7] ;
assign n222 = n220 & n221;
assign n223 = ~\B[5] & ~\B[6] ;
assign n224 = n155 & n223;
assign n225 = ~n222 & ~n224;
assign n226 = \B[3] & ~n225;
assign n227 = \B[2] & n226;
assign n228 = ~\B[4] & ~n181;
assign n229 = ~\B[7] & ~n126;
assign n230 = ~\B[3] & ~n229;
assign n231 = \B[7] & ~n220;
assign n232 = ~\B[6] & ~n83;
assign n233 = \B[5] & n232;
assign n234 = ~\B[9] & ~n233;
assign n235 = ~n231 & n234;
assign n236 = ~n230 & n235;
assign n237 = ~n228 & n236;
assign n238 = ~n227 & n237;
assign n239 = ~\B[8] & ~n238;
assign n240 = \B[3] & \B[8] ;
assign n241 = ~n65 & ~n240;
assign n242 = \B[6] & ~n241;
assign n243 = \B[5] & n242;
assign n244 = \B[7] & n243;
assign n245 = ~\B[9] & n244;
assign n246 = \B[4] & n245;
assign n247 = \B[7] & n220;
assign n248 = \B[9] & ~n247;
assign n249 = ~n246 & ~n248;
assign n250 = ~n239 & n249;
assign \E[0] = \B[10] | n250;
assign n252 = \B[6] & \B[8] ;
assign n253 = n204 & n252;
assign n254 = \B[1] & \B[3] ;
assign n255 = \B[0] & n254;
assign n256 = ~\B[5] & ~\B[7] ;
assign n257 = ~\B[8] & n256;
assign n258 = n255 & n257;
assign n259 = ~n253 & ~n258;
assign n260 = \B[2] & ~n259;
assign n261 = \B[8] & n204;
assign n262 = \B[3] & \B[6] ;
assign n263 = n261 & n262;
assign n264 = ~n260 & ~n263;
assign n265 = \B[4] & ~n264;
assign n266 = n133 & n192;
assign n267 = \B[5] & ~n266;
assign n268 = ~n169 & ~n267;
assign n269 = ~\B[7] & ~n268;
assign n270 = ~\B[8] & n269;
assign n271 = ~\B[9] & ~\B[10] ;
assign n272 = ~n270 & n271;
assign \E[1] = n265 | ~n272;
assign n274 = \B[2] & n93;
assign n275 = n220 & n274;
assign n276 = ~\B[9] & ~n275;
assign n277 = ~\B[10] & n276;
assign \E[2] = ~n53 | ~n277;
endmodule |
module femtoPLL #(
parameter freq = 50
) (
input wire pclk,
output wire clk
);
wire clk_feedback;
wire clk_internal;
PLLE2_ADV #(
.CLKFBOUT_MULT(freq/10), // Multiply value for all CLKOUT (2-64)
.DIVCLK_DIVIDE(1), // Master division value , (1-56)
.CLKOUT0_DIVIDE(10), //
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360-360)
.CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999)
.STARTUP_WAIT("FALSE") // Delayu DONE until PLL Locks, ("TRUE"/"FALSE")
) genclock(
.CLKOUT0(clk_internal),
.CLKFBOUT(clk_feedback), // 1-bit output, feedback clock
.CLKIN1(pclk),
.PWRDWN(1'b0),
.RST(1'b0),
.CLKFBIN(clk_feedback), // 1-bit input, feedback clock
.CLKOUT1(), .CLKOUT2(), .CLKOUT3(), .CLKOUT4(), .CLKOUT5(),
.DO(), .DRDY(), .LOCKED(),
.CLKIN2(), .CLKINSEL(),
.DADDR(), .DCLK(), .DEN(), .DI(), .DWE()
);
BUFG bufg(
.I(clk_internal),
.O(clk)
);
endmodule |
module femtoPLL #(
parameter freq = 60
) (
input wire pclk,
output wire clk
);
assign clk = pclk;
endmodule |
module Clock_gen
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout1_unused;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (4),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (10.0),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule |
module rvsteel_gpio #(
parameter GPIO_WIDTH = 1
) (
// Global signals
input wire clock ,
input wire reset ,
// IO interface
input wire [4:0 ] rw_address ,
output reg [31:0] read_data ,
input wire read_request ,
output reg read_response ,
input wire [GPIO_WIDTH-1:0] write_data ,
input wire [3:0 ] write_strobe ,
input wire write_request ,
output reg write_response,
// I/O signals
input wire [GPIO_WIDTH-1:0] gpio_input ,
output wire [GPIO_WIDTH-1:0] gpio_oe ,
output wire [GPIO_WIDTH-1:0] gpio_output
);
// Map registers
localparam REG_ADDR_WIDTH = 2'd3;
localparam REG_IN = 3'd0;
localparam REG_OE = 3'd1;
localparam REG_OUT = 3'd2;
localparam REG_CLR = 3'd3;
localparam REG_SET = 3'd4;
// Output Enable
reg oe_update;
reg [GPIO_WIDTH-1:0] oe;
// Output data
reg out_update;
reg [GPIO_WIDTH-1:0] out;
// Clear mask
reg clr_update;
// Set mask
reg set_update;
assign gpio_oe = oe;
assign gpio_output = out;
// Bus
wire address_aligned;
assign address_aligned = (~|rw_address[1:0]);
wire write_word;
assign write_word = (&write_strobe);
wire [REG_ADDR_WIDTH-1:0] address;
assign address = rw_address[2 +:REG_ADDR_WIDTH];
always @(posedge clock) begin
if (reset) begin
oe <= {GPIO_WIDTH{1'b0}};
out <= {GPIO_WIDTH{1'b0}};
end else begin
if (oe_update) begin
oe <= write_data[0 +: GPIO_WIDTH];
end
if (out_update) begin
out <= write_data[0 +: GPIO_WIDTH];
end
if (clr_update) begin
out <= out & ~write_data[0 +: GPIO_WIDTH];
end
if (set_update) begin
out <= out | write_data[0 +: GPIO_WIDTH];
end
end
end
// Bus: Response to request
always @(posedge clock) begin
if (reset) begin
read_response <= 1'b0;
write_response <= 1'b0;
end else begin
read_response <= read_request;
write_response <= write_request;
end
end
// Bus: Read registers
always @(posedge clock) begin
if (reset) begin
read_data <= 32'd0;
end else begin
if (read_request && address_aligned) begin
case (address)
REG_IN : read_data <= {{32-GPIO_WIDTH{1'b0}}, gpio_input};
REG_OE : read_data <= {{32-GPIO_WIDTH{1'b0}}, oe};
REG_OUT : read_data <= {{32-GPIO_WIDTH{1'b0}}, out};
REG_CLR : read_data <= 32'd0;
REG_SET : read_data <= 32'd0;
default: begin end
endcase
end
end
end
// Bus: Update registers
always @(*) begin
oe_update = 1'b0;
out_update = 1'b0;
clr_update = 1'b0;
set_update = 1'b0;
if (write_request && address_aligned && write_word) begin
case (address)
REG_OE : oe_update = 1'b1;
REG_OUT : out_update = 1'b1;
REG_CLR : clr_update = 1'b1;
REG_SET : set_update = 1'b1;
default: begin end
endcase
end
end
endmodule |
module rvsteel_uart #(
parameter CLOCK_FREQUENCY = 50000000,
parameter UART_BAUD_RATE = 9600
)(
// Global signals
input wire clock,
input wire reset,
// IO interface
input wire [4:0 ] rw_address,
output reg [31:0] read_data,
input wire read_request,
output reg read_response,
input wire [7:0] write_data,
input wire write_request,
output reg write_response,
// RX/TX signals
input wire uart_rx,
output wire uart_tx,
// Interrupt signaling
output reg uart_irq,
input wire uart_irq_response
);
localparam CYCLES_PER_BAUD = CLOCK_FREQUENCY / UART_BAUD_RATE;
// Register Map
localparam REG_WDATA = 5'h00;
localparam REG_RDATA = 5'h04;
localparam REG_READY = 5'h08;
reg [31:0] tx_cycle_counter = 32'b0;
reg [31:0] rx_cycle_counter = 32'b0;
reg [3:0] tx_bit_counter = 4'b0;
reg [3:0] rx_bit_counter = 4'b0;
reg [9:0] tx_register = 10'b1111111111;
reg [7:0] rx_register = 8'b0;
reg [7:0] rx_data = 8'b0;
reg rx_active = 1'b0;
reg reset_reg = 1'b0;
wire reset_internal;
always @(posedge clock)
reset_reg <= reset;
assign reset_internal = reset | reset_reg;
assign uart_tx = tx_register[0];
always @(posedge clock) begin
if (reset_internal) begin
tx_cycle_counter <= 0;
tx_register <= 10'b1111111111;
tx_bit_counter <= 0;
end
else if (tx_bit_counter == 0 &&
rw_address == REG_WDATA &&
write_request == 1'b1) begin
tx_cycle_counter <= 0;
tx_register <= {1'b1, write_data[7:0], 1'b0};
tx_bit_counter <= 10;
end
else begin
if (tx_cycle_counter < CYCLES_PER_BAUD) begin
tx_cycle_counter <= tx_cycle_counter + 1;
tx_register <= tx_register;
tx_bit_counter <= tx_bit_counter;
end
else begin
tx_cycle_counter <= 0;
tx_register <= {1'b1, tx_register[9:1]};
tx_bit_counter <= tx_bit_counter > 0 ? tx_bit_counter - 1 : 0;
end
end
end
always @(posedge clock) begin
if (reset_internal) begin
rx_cycle_counter <= 0;
rx_register <= 8'h00;
rx_data <= 8'h00;
rx_bit_counter <= 0;
uart_irq <= 1'b0;
rx_active <= 1'b0;
end
else if (uart_irq == 1'b1) begin
if (uart_irq_response == 1'b1) begin
rx_cycle_counter <= 0;
rx_register <= 8'h00;
rx_data <= rx_data;
rx_bit_counter <= 0;
uart_irq <= 1'b0;
rx_active <= 1'b0;
end
else begin
rx_cycle_counter <= 0;
rx_register <= 8'h00;
rx_data <= rx_data;
rx_bit_counter <= 0;
uart_irq <= 1'b1;
rx_active <= 1'b0;
end
end
else if (rx_bit_counter == 0 && rx_active == 1'b0) begin
if (uart_rx == 1'b1) begin
rx_cycle_counter <= 0;
rx_register <= 8'h00;
rx_data <= rx_data;
rx_bit_counter <= 0;
uart_irq <= 1'b0;
rx_active <= 1'b0;
end
else if (uart_rx == 1'b0) begin
if (rx_cycle_counter < CYCLES_PER_BAUD / 2) begin
rx_cycle_counter <= rx_cycle_counter + 1;
rx_register <= 8'h00;
rx_data <= rx_data;
rx_bit_counter <= 0;
uart_irq <= 1'b0;
rx_active <= 1'b0;
end
else begin
rx_cycle_counter <= 0;
rx_register <= 8'h00;
rx_data <= rx_data;
rx_bit_counter <= 8;
uart_irq <= 1'b0;
rx_active <= 1'b1;
end
end
end
else begin
if (rx_cycle_counter < CYCLES_PER_BAUD) begin
rx_cycle_counter <= rx_cycle_counter + 1;
rx_register <= rx_register;
rx_data <= rx_data;
rx_bit_counter <= rx_bit_counter;
uart_irq <= 1'b0;
rx_active <= 1'b1;
end
else begin
rx_cycle_counter <= 0;
rx_register <= {uart_rx, rx_register[7:1]};
rx_data <= (rx_bit_counter == 0) ? rx_register : rx_data;
rx_bit_counter <= rx_bit_counter > 0 ? rx_bit_counter - 1 : 0;
uart_irq <= (rx_bit_counter == 0) ? 1'b1 : 1'b0;
rx_active <= 1'b1;
end
end
end
always @(posedge clock) begin
if (reset_internal) begin
read_response <= 1'b0;
write_response <= 1'b0;
end
else begin
read_response <= read_request;
write_response <= write_request;
end
end
always @(posedge clock) begin
if (reset_internal)
read_data <= 32'h00000000;
else if (rw_address == REG_RDATA && read_request == 1'b1)
read_data <= {24'b0, rx_data};
else if (rw_address == REG_READY && read_request == 1'b1)
read_data <= {31'b0, tx_bit_counter == 0};
else
read_data <= 32'h00000000;
end
endmodule |
module rvsteel_ram #(
// Memory size in bytes
parameter MEMORY_SIZE = 8192,
// File with program and data
parameter MEMORY_INIT_FILE = ""
) (
// Global signals
input wire clock,
input wire reset,
// IO interface
input wire [31:0] rw_address,
output reg [31:0] read_data,
input wire read_request,
output reg read_response,
input wire [31:0] write_data,
input wire [3:0 ] write_strobe,
input wire write_request,
output reg write_response
);
wire reset_internal;
wire [31:0] effective_address;
wire invalid_address;
reg reset_reg;
reg [31:0] ram [0:(MEMORY_SIZE/4)-1];
always @(posedge clock)
reset_reg <= reset;
assign reset_internal = reset | reset_reg;
assign invalid_address = $unsigned(rw_address) >= $unsigned(MEMORY_SIZE);
integer i;
initial begin
for (i = 0; i < MEMORY_SIZE/4; i = i + 1) ram[i] = 32'h00000000;
if (MEMORY_INIT_FILE != "")
$readmemh(MEMORY_INIT_FILE,ram);
end
assign effective_address =
$unsigned(rw_address[31:0] >> 2);
always @(posedge clock) begin
if (reset_internal | invalid_address)
read_data <= 32'h00000000;
else
read_data <= ram[effective_address];
end
always @(posedge clock) begin
if(write_request) begin
if(write_strobe[0])
ram[effective_address][7:0 ] <= write_data[7:0 ];
if(write_strobe[1])
ram[effective_address][15:8 ] <= write_data[15:8 ];
if(write_strobe[2])
ram[effective_address][23:16] <= write_data[23:16];
if(write_strobe[3])
ram[effective_address][31:24] <= write_data[31:24];
end
end
always @(posedge clock) begin
if (reset_internal) begin
read_response <= 1'b0;
write_response <= 1'b0;
end
else begin
read_response <= read_request;
write_response <= write_request;
end
end
// Avoid warnings about intentionally unused pins/wires
wire unused_ok =
&{1'b0,
effective_address[31:11],
1'b0};
endmodule |
module rvsteel_mcu #(
// Frequency of 'clock' signal
parameter CLOCK_FREQUENCY = 50000000 ,
// Desired baud rate for UART unit
parameter UART_BAUD_RATE = 9600 ,
// Memory size in bytes - must be a power of 2
parameter MEMORY_SIZE = 8192 ,
// Text file with program and data (one hex value per line)
parameter MEMORY_INIT_FILE = "" ,
// Address of the first instruction to fetch from memory
parameter BOOT_ADDRESS = 32'h00000000 ,
// Number of available I/O ports
parameter GPIO_WIDTH = 1 ,
// Number of CS (Chip Select) pins for the SPI controller
parameter SPI_NUM_CHIP_SELECT = 1
) (
input wire clock ,
input wire reset ,
input wire halt ,
input wire uart_rx ,
output wire uart_tx ,
input wire [GPIO_WIDTH-1:0] gpio_input ,
output wire [GPIO_WIDTH-1:0] gpio_oe ,
output wire [GPIO_WIDTH-1:0] gpio_output ,
output wire sclk ,
output wire pico ,
input wire poci ,
output wire [SPI_NUM_CHIP_SELECT-1:0] cs
);
// System bus configuration
localparam NUM_DEVICES = 5;
localparam D0_RAM = 0;
localparam D1_UART = 1;
localparam D2_MTIMER = 2;
localparam D3_GPIO = 3;
localparam D4_SPI = 4;
wire [NUM_DEVICES*32-1:0] device_start_address;
wire [NUM_DEVICES*32-1:0] device_region_size;
assign device_start_address [32*D0_RAM +: 32] = 32'h0000_0000;
assign device_region_size [32*D0_RAM +: 32] = MEMORY_SIZE;
assign device_start_address [32*D1_UART +: 32] = 32'h8000_0000;
assign device_region_size [32*D1_UART +: 32] = 16;
assign device_start_address [32*D2_MTIMER +: 32] = 32'h8001_0000;
assign device_region_size [32*D2_MTIMER +: 32] = 32;
assign device_start_address [32*D3_GPIO +: 32] = 32'h8002_0000;
assign device_region_size [32*D3_GPIO +: 32] = 32;
assign device_start_address [32*D4_SPI +: 32] = 32'h8003_0000;
assign device_region_size [32*D4_SPI +: 32] = 32;
// RISC-V Steel 32-bit Processor (Manager Device) <=> System Bus
wire [31:0] manager_rw_address ;
wire [31:0] manager_read_data ;
wire manager_read_request ;
wire manager_read_response ;
wire [31:0] manager_write_data ;
wire [3:0 ] manager_write_strobe ;
wire manager_write_request ;
wire manager_write_response ;
// System Bus <=> Managed Devices
wire [31:0] device_rw_address ;
wire [NUM_DEVICES*32-1:0] device_read_data ;
wire [NUM_DEVICES-1:0] device_read_request ;
wire [NUM_DEVICES-1:0] device_read_response ;
wire [31:0] device_write_data ;
wire [3:0] device_write_strobe ;
wire [NUM_DEVICES-1:0] device_write_request ;
wire [NUM_DEVICES-1:0] device_write_response ;
// Real-time clock (unused)
wire [63:0] real_time_clock;
assign real_time_clock = 64'b0;
// Interrupt signals
wire [15:0] irq_fast;
wire irq_external;
wire irq_timer;
wire irq_software;
wire [15:0] irq_fast_response;
wire irq_external_response;
wire irq_timer_response;
wire irq_software_response;
wire irq_uart;
wire irq_uart_response;
// Interrupt signals map
assign irq_fast = {15'b0, irq_uart}; // Give UART interrupts the highest priority
assign irq_uart_response = irq_fast_response[0];
assign irq_external = 1'b0; // unused
assign irq_software = 1'b0; // unused
rvsteel_core #(
.BOOT_ADDRESS (BOOT_ADDRESS )
) rvsteel_core_instance (
// Global signals
.clock (clock ),
.reset (reset ),
.halt (halt ),
// IO interface
.rw_address (manager_rw_address ),
.read_data (manager_read_data ),
.read_request (manager_read_request ),
.read_response (manager_read_response ),
.write_data (manager_write_data ),
.write_strobe (manager_write_strobe ),
.write_request (manager_write_request ),
.write_response (manager_write_response ),
// Interrupt request signals
.irq_fast (irq_fast ),
.irq_external (irq_external ),
.irq_timer (irq_timer ),
.irq_software (irq_software ),
// Interrupt response signals
.irq_fast_response (irq_fast_response ),
.irq_external_response (irq_external_response ),
.irq_timer_response (irq_timer_response ),
.irq_software_response (irq_software_response ),
// Real Time Clock
.real_time_clock (real_time_clock )
);
rvsteel_bus #(
.NUM_DEVICES(NUM_DEVICES)
) rvsteel_bus_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// Interface with the manager device (Processor Core IP)
.manager_rw_address (manager_rw_address ),
.manager_read_data (manager_read_data ),
.manager_read_request (manager_read_request ),
.manager_read_response (manager_read_response ),
.manager_write_data (manager_write_data ),
.manager_write_strobe (manager_write_strobe ),
.manager_write_request (manager_write_request ),
.manager_write_response (manager_write_response ),
// Interface with the managed devices
.device_rw_address (device_rw_address ),
.device_read_data (device_read_data ),
.device_read_request (device_read_request ),
.device_read_response (device_read_response ),
.device_write_data (device_write_data ),
.device_write_strobe (device_write_strobe ),
.device_write_request (device_write_request ),
.device_write_response (device_write_response ),
// Base addresses and masks of the managed devices
.device_start_address (device_start_address ),
.device_region_size (device_region_size )
);
rvsteel_ram #(
.MEMORY_SIZE (MEMORY_SIZE ),
.MEMORY_INIT_FILE (MEMORY_INIT_FILE )
) rvsteel_ram_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (device_rw_address ),
.read_data (device_read_data[32*D0_RAM +: 32] ),
.read_request (device_read_request[D0_RAM] ),
.read_response (device_read_response[D0_RAM] ),
.write_data (device_write_data ),
.write_strobe (device_write_strobe ),
.write_request (device_write_request[D0_RAM] ),
.write_response (device_write_response[D0_RAM] )
);
rvsteel_uart #(
.CLOCK_FREQUENCY (CLOCK_FREQUENCY ),
.UART_BAUD_RATE (UART_BAUD_RATE )
) rvsteel_uart_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (device_rw_address[4:0] ),
.read_data (device_read_data[32*D1_UART +: 32] ),
.read_request (device_read_request[D1_UART] ),
.read_response (device_read_response[D1_UART] ),
.write_data (device_write_data[7:0] ),
.write_request (device_write_request[D1_UART] ),
.write_response (device_write_response[D1_UART] ),
// RX/TX signals
.uart_tx (uart_tx ),
.uart_rx (uart_rx ),
// Interrupt signaling
.uart_irq (irq_uart ),
.uart_irq_response (irq_uart_response )
);
rvsteel_mtimer
rvsteel_mtimer_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (device_rw_address[4:0] ),
.read_data (device_read_data[32*D2_MTIMER +: 32] ),
.read_request (device_read_request[D2_MTIMER] ),
.read_response (device_read_response[D2_MTIMER] ),
.write_data (device_write_data ),
.write_strobe (device_write_strobe ),
.write_request (device_write_request[D2_MTIMER] ),
.write_response (device_write_response[D2_MTIMER] ),
// Interrupt signaling
.irq (irq_timer )
);
rvsteel_gpio #(
.GPIO_WIDTH (GPIO_WIDTH )
) rvsteel_gpio_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (device_rw_address[4:0] ),
.read_data (device_read_data[32*D3_GPIO +: 32] ),
.read_request (device_read_request[D3_GPIO] ),
.read_response (device_read_response[D3_GPIO] ),
.write_data (device_write_data[GPIO_WIDTH-1:0] ),
.write_strobe (device_write_strobe ),
.write_request (device_write_request[D3_GPIO] ),
.write_response (device_write_response[D3_GPIO] ),
// I/O signals
.gpio_input (gpio_input ),
.gpio_oe (gpio_oe ),
.gpio_output (gpio_output )
);
rvsteel_spi #(
.SPI_NUM_CHIP_SELECT (SPI_NUM_CHIP_SELECT )
) rvsteel_spi_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (device_rw_address[4:0] ),
.read_data (device_read_data[32*D4_SPI +: 32] ),
.read_request (device_read_request[D4_SPI] ),
.read_response (device_read_response[D4_SPI] ),
.write_data (device_write_data[7:0] ),
.write_strobe (device_write_strobe ),
.write_request (device_write_request[D4_SPI] ),
.write_response (device_write_response[D4_SPI] ),
// SPI signals
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs )
);
// Avoid warnings about intentionally unused pins/wires
wire unused_ok =
&{1'b0,
irq_external,
irq_software,
irq_external_response,
irq_software_response,
irq_timer_response,
irq_fast_response[15:1],
1'b0};
endmodule |
module rvsteel_mtimer (
// Global signals
input wire clock ,
input wire reset ,
// IO interface
input wire [4:0 ] rw_address ,
output reg [31:0] read_data ,
input wire read_request ,
output reg read_response ,
input wire [31:0] write_data ,
input wire [3:0 ] write_strobe ,
input wire write_request ,
output reg write_response,
// TODO: use it later
// output reg access_fault ,
// Side timer irq
// Interrupt signaling
output reg irq
);
localparam REG_ADDR_WIDTH = 2'd3;
// Map registers
localparam REG_CR = 3'd0;
localparam REG_MTIMEL = 3'd1;
localparam REG_MTIMEH = 3'd2;
localparam REG_MTIMECMPL = 3'd3;
localparam REG_MTIMECMPH = 3'd4;
// Map bits
// CR
localparam BIT_CR_EN = 5'd0;
localparam BIT_CR_WIDTH = 5'd1;
localparam CR_PADDING = {6'd32-BIT_CR_WIDTH{1'd0}};
// Control register
reg cr_update;
reg cr_en;
// mtime
reg mtime_l_update;
reg mtime_h_update;
reg [63:0] mtime;
// mtimecmp
reg mtimecmp_l_update;
reg mtimecmp_h_update;
reg [63:0] mtimecmp;
// Bus
wire address_aligned;
assign address_aligned = (~|rw_address[1:0]);
wire write_word;
assign write_word = (&write_strobe);
wire [REG_ADDR_WIDTH-1:0] address;
assign address = rw_address[2 +:REG_ADDR_WIDTH];
// Control register
always @(posedge clock) begin
if (reset) begin
cr_en <= 1'b0;
end else begin
if (cr_update) begin
cr_en <= write_data[BIT_CR_EN];
end
end
end
// mtime
wire [63:0] mtime_plus_1 = mtime + 1'd1;
always @(posedge clock) begin
if (reset) begin
mtime <= {64{1'b0}};
end else begin
if (mtime_l_update) begin
mtime[31:0] <= write_data;
mtime[63:32] <= mtime_plus_1[63:32];
end else if (mtime_h_update) begin
mtime[31:0] <= mtime_plus_1[31:0];
mtime[63:32] <= write_data;
end else if (cr_en) begin
mtime <= mtime_plus_1;
end
end
end
// mtimecmp
always @(posedge clock) begin
if (reset) begin
mtimecmp <= 64'hffff_ffff_ffff_ffff; // Initially, mtimecmp holds the biggest value so mtime is sure to be smaller than mtimecmp
end else begin
if (mtimecmp_l_update) begin
mtimecmp[31:0] <= write_data;
end
if (mtimecmp_h_update) begin
mtimecmp[63:32] <= write_data;
end
end
end
// IRQ
always @(posedge clock) begin
if (reset) begin
irq <= 1'b0;
end else begin
// Don't update while there is an update
if (~(mtime_l_update | mtime_h_update | mtimecmp_l_update | mtimecmp_h_update)) begin
// A machine timer interrupt becomes pending whenever mtime contains a
// value greater than or equal to mtimecmp
irq <= (mtime >= mtimecmp);
end
end
end
// Bus: Response to request
always @(posedge clock) begin
if (reset) begin
read_response <= 1'b0;
write_response <= 1'b0;
// access_fault <= 1'b0;
end else begin
read_response <= read_request;
write_response <= write_request;
// access_fault <= (read_request & !address_aligned) |
// (write_request & !address_aligned) |
// (write_request & !write_word);
end
end
// Bus: Read registers
always @(posedge clock) begin
if (reset) begin
read_data <= 32'd0;
end else begin
if (read_request && address_aligned) begin
case (address)
REG_CR : read_data <= {CR_PADDING, cr_en};
REG_MTIMEL : read_data <= mtime[31:0];
REG_MTIMEH : read_data <= mtime[63:32];
REG_MTIMECMPL : read_data <= mtimecmp[31:0];
REG_MTIMECMPH : read_data <= mtimecmp[63:32];
default: begin end
endcase
end
end
end
// Bus: Update registers
always @(*) begin
cr_update = 1'b0;
mtime_l_update = 1'b0;
mtime_h_update = 1'b0;
mtimecmp_l_update = 1'b0;
mtimecmp_h_update = 1'b0;
if (write_request && address_aligned && write_word) begin
case (address)
REG_CR : cr_update = 1'b1;
REG_MTIMEL : mtime_l_update = 1'b1;
REG_MTIMEH : mtime_h_update = 1'b1;
REG_MTIMECMPL : mtimecmp_l_update = 1'b1;
REG_MTIMECMPH : mtimecmp_h_update = 1'b1;
default: begin end
endcase
end
end
endmodule |
module rvsteel_spi #(
parameter SPI_NUM_CHIP_SELECT = 1
)(
// Global signals
input wire clock ,
input wire reset ,
// IO interface
input wire [4:0 ] rw_address ,
output reg [31:0] read_data ,
input wire read_request ,
output reg read_response ,
input wire [7:0 ] write_data ,
input wire [3:0 ] write_strobe ,
input wire write_request ,
output reg write_response ,
// SPI signals
output reg sclk ,
output reg pico ,
input wire poci ,
output reg [SPI_NUM_CHIP_SELECT-1:0] cs
);
reg tx_start;
reg cpol;
reg cpha;
reg clk_edge;
reg sclk_internal;
reg pico_internal;
reg [SPI_NUM_CHIP_SELECT-1:0] cs_internal;
reg [3:0] curr_state;
reg [3:0] next_state;
reg [3:0] bit_count;
reg [7:0] tx_reg;
reg [7:0] rx_reg;
reg [7:0] chip_select;
reg [7:0] cycle_counter;
reg [7:0] clock_div;
// SPI State Machine
localparam SPI_READY = 4'b0001;
localparam SPI_IDLE = 4'b0010;
localparam SPI_CPOL = 4'b0100;
localparam SPI_CPOL_N = 4'b1000;
// Register addresses
localparam REG_CPOL = 5'h00;
localparam REG_CPHA = 5'h04;
localparam REG_CHIP_SELECT = 5'h08;
localparam REG_CLOCK_CONF = 5'h0c;
localparam REG_WDATA = 5'h10;
localparam REG_RDATA = 5'h14;
localparam REG_BUSY = 5'h18;
wire busy_bit = curr_state == SPI_CPOL || curr_state == SPI_CPOL_N;
wire valid_write_request = write_request == 1'b1 && &write_strobe == 1'b1;
integer i;
always @(posedge clock) begin
if (reset) begin
read_response <= 1'b0;
write_response <= 1'b0;
end
else begin
read_response <= read_request;
write_response <= write_request;
end
end
always @(posedge clock) begin
if (reset)
read_data <= 32'hdeadbeef;
else if (read_request == 1'b1) begin
case (rw_address)
REG_CPOL: read_data <= {31'b0, cpol};
REG_CPHA: read_data <= {31'b0, cpha};
REG_CHIP_SELECT: read_data <= {24'b0, chip_select};
REG_CLOCK_CONF: read_data <= {24'b0, clock_div};
REG_RDATA: read_data <= {24'b0, rx_reg};
REG_BUSY: read_data <= {31'b0, busy_bit};
default: read_data <= 32'hdeadbeef;
endcase
end
else
read_data <= 32'hdeadbeef;
end
always @(posedge clock) begin
if (reset)
cpol <= 1'b0;
else if (rw_address == REG_CPOL && valid_write_request == 1'b1)
cpol <= write_data[0];
else
cpol <= cpol;
end
always @(posedge clock) begin
if (reset)
cpha <= 1'b0;
else if (rw_address == REG_CPHA && valid_write_request == 1'b1)
cpha <= write_data[0];
else
cpha <= cpha;
end
always @(posedge clock) begin
if (reset)
chip_select <= 8'hff;
else if (rw_address == REG_CHIP_SELECT && valid_write_request == 1'b1)
chip_select <= write_data[7:0];
else
chip_select <= chip_select;
end
always @(posedge clock) begin
if (reset)
clock_div <= 8'h00;
else if (rw_address == REG_CLOCK_CONF && valid_write_request == 1'b1)
clock_div <= write_data[7:0];
else
clock_div <= clock_div;
end
always @(posedge clock) begin
if (reset) begin
tx_reg <= 8'h00;
tx_start <= 1'b0;
end
else if (rw_address == REG_WDATA && valid_write_request == 1'b1) begin
tx_reg <= (curr_state == SPI_READY || curr_state == SPI_IDLE) ? write_data[7:0] : tx_reg;
tx_start <= (curr_state == SPI_READY || curr_state == SPI_IDLE) ? 1'b1 : tx_start;
end
else begin
tx_reg <= tx_reg;
tx_start <= (curr_state == SPI_CPOL || curr_state == SPI_CPOL_N) ? 1'b0 : tx_start;
end
end
always @(posedge clock) begin
if (reset | chip_select == 8'hff)
curr_state <= SPI_READY;
else
curr_state <= next_state;
end
always @(posedge clock) begin
if (reset || curr_state == SPI_READY || curr_state == SPI_IDLE)
cycle_counter <= 0;
else if (curr_state == SPI_CPOL && next_state == SPI_CPOL_N)
cycle_counter <= 0;
else if (curr_state == SPI_CPOL_N && next_state == SPI_CPOL)
cycle_counter <= 0;
else
cycle_counter <= cycle_counter + 1;
end
always @(posedge clock) begin
if (reset || curr_state == SPI_READY || curr_state == SPI_IDLE)
bit_count <= 7;
else if (cpha == 1'b0 && curr_state == SPI_CPOL_N && next_state == SPI_CPOL)
bit_count <= bit_count - 1;
else if (cpha == 1'b1 && curr_state == SPI_CPOL && next_state == SPI_CPOL_N)
bit_count <= bit_count - 1;
else
bit_count <= bit_count;
end
always @* begin
for (i = 0; i < SPI_NUM_CHIP_SELECT; i=i+1) begin
cs_internal[i] = ({24'd0, chip_select} == i) ? 1'b0 : 1'b1;
end
case (curr_state)
SPI_READY: begin
sclk_internal = cpol;
pico_internal = tx_reg[7];
next_state = tx_start == 1'b1 ? (cpha == 1'b1 ? SPI_CPOL_N : SPI_CPOL) : curr_state;
end
SPI_CPOL: begin
sclk_internal = cpol;
pico_internal = tx_reg[bit_count[2:0]];
next_state = cycle_counter < clock_div ? curr_state : (bit_count == 0 && cpha == 1'b1 ? SPI_IDLE : SPI_CPOL_N);
end
SPI_CPOL_N: begin
sclk_internal = !cpol;
pico_internal = tx_reg[bit_count[2:0]];
next_state = cycle_counter < clock_div ? curr_state : (bit_count == 0 && cpha == 1'b0 ? SPI_IDLE : SPI_CPOL);
end
SPI_IDLE: begin
sclk_internal = cpol;
pico_internal = tx_reg[0];
next_state = chip_select == 8'hff ? SPI_READY : (tx_start == 1'b1 ? (cpha == 1'b1 ? SPI_CPOL_N : SPI_CPOL) : curr_state);
end
default: begin
sclk_internal = cpol;
pico_internal = tx_reg[7];
next_state = tx_start == 1'b1 ? SPI_CPOL : curr_state;
end
endcase
end
always @(posedge clock) begin
if (reset) begin
sclk <= 1'b0;
pico <= 1'b0;
cs <= {SPI_NUM_CHIP_SELECT{1'b1}};
end
else begin
sclk <= sclk_internal;
pico <= pico_internal;
cs <= cs_internal;
end
end
always @(posedge clock) begin
clk_edge <= cpol ^ cpha ? !sclk_internal : sclk_internal;
end
always @(posedge clk_edge) begin
rx_reg[7:0] <= {rx_reg[6:0], poci};
end
endmodule |
module rvsteel_bus #(
parameter NUM_DEVICES = 1
)(
// Global signals
input wire clock ,
input wire reset ,
// Interface with the manager device (Processor Core IP)
input wire [31:0] manager_rw_address ,
output reg [31:0] manager_read_data ,
input wire manager_read_request ,
output reg manager_read_response ,
input wire [31:0] manager_write_data ,
input wire [3:0 ] manager_write_strobe ,
input wire manager_write_request ,
output reg manager_write_response,
// Interface with the managed devices
output wire [31:0] device_rw_address ,
input wire [NUM_DEVICES*32-1:0] device_read_data ,
output wire [NUM_DEVICES-1:0] device_read_request ,
input wire [NUM_DEVICES-1:0] device_read_response ,
output wire [31:0] device_write_data ,
output wire [3:0 ] device_write_strobe ,
output wire [NUM_DEVICES-1:0] device_write_request ,
input wire [NUM_DEVICES-1:0] device_write_response ,
// Base addresses and masks of the managed devices
input wire [NUM_DEVICES*32-1:0] device_start_address ,
input wire [NUM_DEVICES*32-1:0] device_region_size
);
integer i;
reg [NUM_DEVICES*32-1:0] device_mask_address;
reg [NUM_DEVICES-1:0] device_sel;
reg [NUM_DEVICES-1:0] device_sel_save;
// Manager request
assign device_rw_address = manager_rw_address;
assign device_read_request = device_sel & {NUM_DEVICES{manager_read_request}};
assign device_write_data = manager_write_data;
assign device_write_strobe = manager_write_strobe;
assign device_write_request = device_sel & {NUM_DEVICES{manager_write_request}};
// Device response selection
always @(*) begin
for (i = 0; i < NUM_DEVICES; i = i + 1) begin
device_mask_address[i*32 +:32] = ~(device_region_size[i*32 +:32] - 1);
if ((manager_rw_address & device_mask_address[i*32 +:32]) == device_start_address[i*32 +:32])
device_sel[i] = 1'b1;
else
device_sel[i] = 1'b0;
end
end
always @(posedge clock) begin
if (reset)
device_sel_save <= {NUM_DEVICES{1'b0}};
else if ((manager_read_request || manager_write_request) && (|device_sel))
device_sel_save <= device_sel;
else
device_sel_save <= {NUM_DEVICES{1'b0}};
end
always @(*) begin
manager_read_data = 32'b0;
manager_read_response = 1'b1;
manager_write_response = 1'b1;
for (i = 0; i < NUM_DEVICES; i = i + 1) begin
if (device_sel_save[i]) begin
manager_read_data = device_read_data[i*32 +: 32];
manager_read_response = device_read_response[i];
manager_write_response = device_write_response[i];
end
end
end
endmodule |
module mcu_sim #(
// Number of available I/O ports
parameter GPIO_WIDTH = 2,
// Number of CS (Chip Select) pins for the SPI controller
parameter SPI_NUM_CHIP_SELECT = 1
) (
input wire clock ,
input wire reset ,
input wire halt ,
input wire uart_rx ,
output wire uart_tx ,
input wire [GPIO_WIDTH-1:0] gpio_input ,
output wire [GPIO_WIDTH-1:0] gpio_oe ,
output wire [GPIO_WIDTH-1:0] gpio_output ,
output wire sclk ,
output wire pico ,
input wire poci ,
output wire [SPI_NUM_CHIP_SELECT-1:0] cs
);
rvsteel_mcu #(
.CLOCK_FREQUENCY (50000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (32768 ),
.MEMORY_INIT_FILE ("" ),
.BOOT_ADDRESS (32'h00000000 ),
.GPIO_WIDTH (GPIO_WIDTH )
) rvsteel_mcu_instance (
.clock (clock ),
.reset (reset ),
.halt (halt ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input (gpio_input ),
.gpio_oe (gpio_oe ),
.gpio_output (gpio_output ),
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs )
);
endmodule |
module unit_tests (
input wire clock,
input wire reset,
input wire halt,
input wire uart_rx,
output wire uart_tx
);
localparam SPI_NUM_CHIP_SELECT = 2;
wire sclk;
wire pico;
wire poci;
wire [SPI_NUM_CHIP_SELECT-1:0] cs;
// Divides the 100MHz board block by 4
reg clock_50mhz;
initial clock_50mhz = 1'b0;
always @(posedge clock) clock_50mhz <= !clock_50mhz;
// Buttons debouncing
reg reset_debounced;
reg halt_debounced;
always @(posedge clock_50mhz) begin
reset_debounced <= reset;
halt_debounced <= halt;
end
rvsteel_mcu #(
.CLOCK_FREQUENCY (50000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (8192 ),
.MEMORY_INIT_FILE ("unit_tests.hex" ),
.BOOT_ADDRESS (32'h00000000 ),
.SPI_NUM_CHIP_SELECT (2 )
) rvsteel_mcu_instance (
.clock (clock_50mhz ),
.reset (reset_debounced ),
.halt (halt_debounced ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input (1'b0 ),
.gpio_oe ( ),
.gpio_output ( ),
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs )
);
dummy_spi_peripheral_modes03
spi_modes03 (
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs[0] )
);
dummy_spi_peripheral_modes12
spi_modes12 (
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs[1] )
);
endmodule |
module dummy_spi_peripheral_modes03 (
input wire sclk,
input wire pico,
input wire cs,
output wire poci
);
reg [7:0] rx_data = 8'h00;
reg tx_bit = 1'b0;
reg [3:0] bit_count = 7;
always @(posedge sclk) begin
if (!cs) rx_data <= {rx_data[6:0], pico};
end
always @(negedge sclk) begin
if (!cs) tx_bit <= rx_data[7];
end
assign poci = cs ? 1'bZ : tx_bit;
endmodule |
module unit_tests #(
// Memory size in bytes
parameter MEMORY_SIZE = 2097152 ,
parameter BOOT_ADDRESS = 32'h00000000
)(
input clock ,
input reset ,
input halt
);
wire [31:0] rw_address;
wire [31:0] read_data;
wire read_request;
wire read_response;
wire [31:0] write_data;
wire [3:0 ] write_strobe;
wire write_request;
wire write_response;
// Real-time clock (unused)
wire [63:0] real_time_clock;
assign real_time_clock = 64'b0;
// Interrupt signals
wire [15:0] irq_fast;
wire irq_external;
wire irq_timer;
wire irq_software;
assign irq_fast = 16'd0;
assign irq_external = 1'd0;
assign irq_timer = 1'd0;
assign irq_software = 1'd0;
wire [15:0] irq_fast_response;
wire irq_external_response;
wire irq_timer_response;
wire irq_software_response;
rvsteel_core #(
.BOOT_ADDRESS(BOOT_ADDRESS)
) rvsteel_core_instance (
// Global signals
.clock (clock ),
.reset (reset ),
.halt (halt ),
// IO interface
.rw_address (rw_address ),
.read_data (read_data ),
.read_request (read_request ),
.read_response (read_response ),
.write_data (write_data ),
.write_strobe (write_strobe ),
.write_request (write_request ),
.write_response (write_response ),
// Interrupt request signals
.irq_fast (irq_fast ),
.irq_external (irq_external ),
.irq_timer (irq_timer ),
.irq_software (irq_software ),
// Interrupt response signals
.irq_fast_response (irq_fast_response ),
.irq_external_response (irq_external_response),
.irq_timer_response (irq_timer_response ),
.irq_software_response (irq_software_response),
// Real Time Clock (hardwire to zero if unused)
.real_time_clock (real_time_clock )
);
rvsteel_ram #(
.MEMORY_SIZE(MEMORY_SIZE)
) rvsteel_ram_instance (
// Global signals
.clock (clock ),
.reset (reset ),
// IO interface
.rw_address (rw_address ),
.read_data (read_data ),
.read_request (read_request ),
.read_response (read_response ),
.write_data (write_data ),
.write_strobe (write_strobe ),
.write_request (write_request ),
.write_response (write_response )
);
// Avoid warnings about intentionally unused pins/wires
wire unused_ok =
&{1'b0,
irq_fast_response,
irq_external_response,
irq_timer_response,
irq_software_response,
1'b0};
endmodule |
module gpio_cmod_a7 #(
parameter GPIO_WIDTH = 3
)(
input wire clock,
input wire reset,
input wire uart_rx,
output wire uart_tx,
inout wire [GPIO_WIDTH-1:0] gpio
);
// GPIO signals
wire [GPIO_WIDTH-1:0] gpio_input;
wire [GPIO_WIDTH-1:0] gpio_oe;
wire [GPIO_WIDTH-1:0] gpio_output;
genvar i;
for (i = 0; i < GPIO_WIDTH; i=i+1) begin
assign gpio_input[i] = gpio_oe[i] == 1'b1 ? gpio_output[i] : gpio[i];
assign gpio[i] = gpio_oe[i] == 1'b1 ? gpio_output[i] : 1'bZ;
end
// Buttons debouncing
reg reset_debounced;
always @(posedge clock) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
.CLOCK_FREQUENCY (12000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (131072 ),
.MEMORY_INIT_FILE ("gpio_demo.hex" ),
.BOOT_ADDRESS (32'h00000000 ),
.GPIO_WIDTH (3 )
) rvsteel_mcu_instance (
.clock (clock ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input (gpio_input ),
.gpio_oe (gpio_oe ),
.gpio_output (gpio_output ),
.sclk (), // unused
.pico (), // unused
.poci (1'b0 ),
.cs () // unused
);
endmodule |
module gpio_arty_a7 #(
parameter GPIO_WIDTH = 3
)(
input wire clock,
input wire reset,
input wire uart_rx,
output wire uart_tx,
inout wire [GPIO_WIDTH-1:0] gpio
);
// GPIO signals
wire [GPIO_WIDTH-1:0] gpio_input;
wire [GPIO_WIDTH-1:0] gpio_oe;
wire [GPIO_WIDTH-1:0] gpio_output;
genvar i;
for (i = 0; i < GPIO_WIDTH; i=i+1) begin
assign gpio_input[i] = gpio_oe[i] == 1'b1 ? gpio_output[i] : gpio[i];
assign gpio[i] = gpio_oe[i] == 1'b1 ? gpio_output[i] : 1'bZ;
end
// Divides the 100MHz board block by 2
reg clock_50mhz;
initial clock_50mhz = 1'b0;
always @(posedge clock) clock_50mhz <= !clock_50mhz;
// Buttons debouncing
reg reset_debounced;
always @(posedge clock_50mhz) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
.CLOCK_FREQUENCY (50000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (131072 ),
.MEMORY_INIT_FILE ("gpio_demo.hex" ),
.BOOT_ADDRESS (32'h00000000 ),
.GPIO_WIDTH (3 )
) rvsteel_mcu_instance (
.clock (clock_50mhz ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input (gpio_input ),
.gpio_oe (gpio_oe ),
.gpio_output (gpio_output ),
.sclk (), // unused
.pico (), // unused
.poci (1'b0 ),
.cs () // unused
);
endmodule |
module spi_cmod_a7 #(
parameter GPIO_WIDTH = 1,
parameter SPI_NUM_CHIP_SELECT = 1
)(
input wire clock,
input wire reset,
input wire uart_rx,
output wire uart_tx,
output wire sclk,
output wire pico,
input wire poci,
output wire cs
);
// Buttons debouncing
reg reset_debounced;
always @(posedge clock) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
.CLOCK_FREQUENCY (12000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (131072 ),
.MEMORY_INIT_FILE ("spi_demo.hex" ),
.BOOT_ADDRESS (32'h00000000 ),
.GPIO_WIDTH (GPIO_WIDTH ),
.SPI_NUM_CHIP_SELECT (SPI_NUM_CHIP_SELECT )
) rvsteel_mcu_instance (
.clock (clock ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input ({GPIO_WIDTH{1'b0}} ), // pull-down
.gpio_oe (), // unused
.gpio_output (), // unused
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs )
);
endmodule |
module spi_arty_a7 #(
parameter GPIO_WIDTH = 1,
parameter SPI_NUM_CHIP_SELECT = 1
)(
input wire clock,
input wire reset,
input wire uart_rx,
output wire uart_tx,
output wire sclk,
output wire pico,
input wire poci,
output wire cs
);
// Divides the 100MHz board block by 2
reg clock_50mhz;
initial clock_50mhz = 1'b0;
always @(posedge clock) clock_50mhz <= !clock_50mhz;
// Buttons debouncing
reg reset_debounced;
always @(posedge clock_50mhz) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
.CLOCK_FREQUENCY (50000000 ),
.UART_BAUD_RATE (9600 ),
.MEMORY_SIZE (131072 ),
.MEMORY_INIT_FILE ("spi_demo.hex" ),
.BOOT_ADDRESS (32'h00000000 ),
.GPIO_WIDTH (GPIO_WIDTH ),
.SPI_NUM_CHIP_SELECT (SPI_NUM_CHIP_SELECT )
) rvsteel_mcu_instance (
.clock (clock_50mhz ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (uart_rx ),
.uart_tx (uart_tx ),
.gpio_input ({GPIO_WIDTH{1'b0}} ), // pull-down
.gpio_oe (), // unused
.gpio_output (), // unused
.sclk (sclk ),
.pico (pico ),
.poci (poci ),
.cs (cs )
);
endmodule |
module hello_world_cmod_a7 (
input wire clock,
input wire reset,
output wire uart_tx
);
// Push-button debouncing
reg reset_debounced;
always @(posedge clock) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
// Please adjust these two parameters accordingly
.CLOCK_FREQUENCY (12000000 ),
.MEMORY_INIT_FILE ("hello_world.hex" )
) rvsteel_mcu_instance (
// Note that unused inputs are hardwired to zero,
// while unused outputs are left open.
.clock (clock ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (/* unused, leave open */ ),
.uart_tx (uart_tx ),
.gpio_input (1'b0 ),
.gpio_oe (/* unused, leave open */ ),
.gpio_output (/* unused, leave open */ ),
.sclk (/* unused, leave open */ ),
.pico (/* unused, leave open */ ),
.poci (1'b0 ),
.cs (/* unused, leave open */ )
);
endmodule |
module hello_world_arty_a7 (
input wire clock,
input wire reset,
output wire uart_tx
);
// Divides the 100MHz board block by 2
reg clock_50mhz;
initial clock_50mhz = 1'b0;
always @(posedge clock) clock_50mhz <= !clock_50mhz;
// Push-button debouncing
reg reset_debounced;
always @(posedge clock_50mhz) begin
reset_debounced <= reset;
end
rvsteel_mcu #(
// Please adjust these two parameters accordingly
.CLOCK_FREQUENCY (50000000 ),
.MEMORY_INIT_FILE ("hello_world.hex" )
) rvsteel_mcu_instance (
// Note that unused inputs are hardwired to zero,
// while unused outputs are left open.
.clock (clock_50mhz ),
.reset (reset_debounced ),
.halt (1'b0 ),
.uart_rx (/* unused, leave open */ ),
.uart_tx (uart_tx ),
.gpio_input (1'b0 ),
.gpio_oe (/* unused, leave open */ ),
.gpio_output (/* unused, leave open */ ),
.sclk (/* unused, leave open */ ),
.pico (/* unused, leave open */ ),
.poci (1'b0 ),
.cs (/* unused, leave open */ )
);
endmodule |
module iseq_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1,
CS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (
input clk,
input rst,
input periodic_read_lock,
input process_iseq,
output dispatcher_busy,
output instr0_fifo_rd,
input instr0_fifo_empty,
input[31:0] instr0_fifo_data,
output instr1_fifo_rd,
input instr1_fifo_empty,
input[31:0] instr1_fifo_data,
//DFI Interface
// DFI Control/Address
input dfi_ready,
input dfi_init_complete,
output [ROW_WIDTH-1:0] dfi_address0,
output [ROW_WIDTH-1:0] dfi_address1,
output [BANK_WIDTH-1:0] dfi_bank0,
output [BANK_WIDTH-1:0] dfi_bank1,
output dfi_cke0,
output dfi_cke1,
output dfi_cas_n0,
output dfi_cas_n1,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,
output dfi_ras_n0,
output dfi_ras_n1,
output dfi_we_n0,
output dfi_we_n1,
// DFI Write
output dfi_wrdata_en,
output [4*DQ_WIDTH-1:0] dfi_wrdata,
output [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,
// DFI Read
output dfi_rddata_en,
output dfi_rddata_en_even,
output dfi_rddata_en_odd,
//Bus Command
output io_config_strobe,
output[1:0] io_config,
//Misc.
output pr_rd_ack,
//auto-refresh
output aref_set_interval,
output[27:0] aref_interval,
output aref_set_trfc,
output[27:0] aref_trfc
);
reg dispatcher_busy_r = 1'b0, dispatcher_busy_ns;
//check conditions and start transaction
always@*
dispatcher_busy_ns = ~rst & process_iseq | (dispatcher_busy_r & (~(instr0_fifo_empty & instr1_fifo_empty)
| instr0_disp_en | instr1_disp_en));
always@(posedge clk)
dispatcher_busy_r <= dispatcher_busy_ns;
wire instr0_disp_en, instr1_disp_en;
wire instr0_disp_ack, instr1_disp_ack;
wire[31:0] instr0, instr1;
wire instr0_ready, instr1_ready;
assign instr0_fifo_rd = instr0_ready & dispatcher_busy_r;
assign instr1_fifo_rd = instr1_ready & dispatcher_busy_r;
pipe_reg #(.WIDTH(32)) i_instr0_reg(
.clk(clk),
.rst(rst),
.ready_in(instr0_disp_ack),
.valid_in(dispatcher_busy_r & !instr0_fifo_empty),
.data_in(instr0_fifo_data),
.valid_out(instr0_disp_en),
.data_out(instr0),
.ready_out(instr0_ready)
);
pipe_reg #(.WIDTH(32)) i_instr1_reg(
.clk(clk),
.rst(rst),
.ready_in(instr1_disp_ack),
.valid_in(dispatcher_busy_r & !instr1_fifo_empty),
.data_in(instr1_fifo_data),
.valid_out(instr1_disp_en),
.data_out(instr1),
.ready_out(instr1_ready)
);
//Command Dispatcher Instantiation
instr_dispatcher #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CKE_WIDTH(CKE_WIDTH),
.CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_instr_dispatcher(
.clk(clk),
.rst(rst),
.periodic_read_lock(periodic_read_lock),
.en_in0(instr0_disp_en),
.en_ack0(instr0_disp_ack),
.instr_in0(instr0),
.en_in1(instr1_disp_en),
.en_ack1(instr1_disp_ack),
.instr_in1(instr1),
//DFI Interface
// DFI Control/Address
.dfi_ready(dfi_ready),
.dfi_address0(dfi_address0),
.dfi_address1(dfi_address1),
.dfi_bank0(dfi_bank0),
.dfi_bank1(dfi_bank1),
.dfi_cke0(dfi_cke0),
.dfi_cke1(dfi_cke1),
.dfi_cas_n0(dfi_cas_n0),
.dfi_cas_n1(dfi_cas_n1),
.dfi_cs_n0(dfi_cs_n0),
.dfi_cs_n1(dfi_cs_n1),
.dfi_odt0(dfi_odt0),
.dfi_odt1(dfi_odt1),
.dfi_ras_n0(dfi_ras_n0),
.dfi_ras_n1(dfi_ras_n1),
.dfi_we_n0(dfi_we_n0),
.dfi_we_n1(dfi_we_n1),
// DFI Write
.dfi_wrdata_en(dfi_wrdata_en),
.dfi_wrdata(dfi_wrdata),
.dfi_wrdata_mask(dfi_wrdata_mask),
// DFI Read
.dfi_rddata_en(dfi_rddata_en),
.dfi_rddata_en_even(dfi_rddata_en_even),
.dfi_rddata_en_odd(dfi_rddata_en_odd),
//Bus Command
.io_config_strobe(io_config_strobe),
.io_config(io_config),
//Misc.
.pr_rd_ack(pr_rd_ack),
//auto-refresh
.aref_set_interval(aref_set_interval),
.aref_interval(aref_interval),
.aref_set_trfc(aref_set_trfc),
.aref_trfc(aref_trfc)
);
assign dispatcher_busy = dispatcher_busy_r;
endmodule |
module softMC_pcie_app #(
parameter C_PCI_DATA_WIDTH = 9'd32, DQ_WIDTH = 64
)(
input clk,
input rst,
output CHNL_RX_CLK,
input CHNL_RX,
output reg CHNL_RX_ACK,
input CHNL_RX_LAST,
input [31:0] CHNL_RX_LEN,
input [30:0] CHNL_RX_OFF,
input [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
input CHNL_RX_DATA_VALID,
output CHNL_RX_DATA_REN,
output CHNL_TX_CLK,
output reg CHNL_TX,
input CHNL_TX_ACK,
output CHNL_TX_LAST,
output reg [31:0] CHNL_TX_LEN,
output [30:0] CHNL_TX_OFF,
output [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA,
output reg CHNL_TX_DATA_VALID,
input CHNL_TX_DATA_REN,
output app_en,
input app_ack,
output[31:0] app_instr,
//Data read back Interface
input rdback_fifo_empty,
output rdback_fifo_rden,
input[DQ_WIDTH*4 - 1:0] rdback_data
);
assign CHNL_RX_CLK = clk;
assign CHNL_TX_CLK = clk;
assign CHNL_TX_OFF = 0;
assign CHNL_TX_LAST = 1'd1;
reg app_en_r;
reg[C_PCI_DATA_WIDTH-1:0] rx_data_r;
reg old_chnl_rx;
reg pending_ack = 0;
//always acknowledge transaction
always@(posedge clk) begin
old_chnl_rx <= CHNL_RX;
if(~old_chnl_rx & CHNL_RX)
pending_ack <= 1'b1;
if(CHNL_RX_ACK)
CHNL_RX_ACK <= 1'b0;
else begin
if(pending_ack /*& app_ack*/) begin
CHNL_RX_ACK <= 1'b1;
pending_ack <= 1'b0;
end
end
end
//register incoming data
assign CHNL_RX_DATA_REN = ~app_en_r | app_ack;
always@(posedge clk) begin
if(~app_en_r | app_ack) begin
app_en_r <= CHNL_RX_DATA_VALID;
rx_data_r <= CHNL_RX_DATA;
end
end
//send to the MC
assign app_en = app_en_r;
assign app_instr = rx_data_r;
//SEND DATA TO HOST
localparam RECV_IDLE = 1'b0;
localparam RECV_BUSY = 1'b1;
reg sender_ack;
reg[DQ_WIDTH*4 - 1:0] send_data_r;
reg recv_state = RECV_IDLE;
assign rdback_fifo_rden = (recv_state == RECV_IDLE);
always@(posedge clk) begin
if(rst) begin
recv_state <= RECV_IDLE;
end
else begin
case(recv_state)
RECV_IDLE: begin
if(~rdback_fifo_empty) begin
send_data_r <= rdback_data;
recv_state <= RECV_BUSY;
end
end //RECV_IDLE
RECV_BUSY: begin
if(sender_ack)
recv_state <= RECV_IDLE;
end //RECV_BUSY
endcase
end
end
reg[2:0] sender_state = 0; //edit this if DQ_WIDTH or C_PCI_DATA_WIDTH changes
reg[2:0] sender_state_ns;
always@* begin
sender_ack = 1'b0;
sender_state_ns = sender_state;
CHNL_TX = sender_state[2];
CHNL_TX_LEN = 16;
if(recv_state == RECV_BUSY) begin
CHNL_TX = 1'b1;
CHNL_TX_DATA_VALID = 1'b1;
if(CHNL_TX_DATA_REN) begin
sender_state_ns = sender_state + 3'd1;
if(sender_state[1:0] == 2'b11)
sender_ack = 1'b1;
end
end
end
always@(posedge clk) begin
if(rst) begin
sender_state <= 0;
end
else begin
sender_state <= sender_state_ns;
end
end
wire[7:0] offset = {6'd0, sender_state[1:0]} << 6;
assign CHNL_TX_DATA = send_data_r[offset +: 64];
endmodule |
module instr_receiver (
input clk,
input rst,
input dispatcher_ready,
input app_en,
output reg app_ack,
input[31:0] app_instr,
input maint_en,
output reg maint_ack,
input[31:0] maint_instr,
output instr0_fifo_en,
output[31:0] instr0_fifo_data,
output instr1_fifo_en,
output[31:0] instr1_fifo_data,
output process_iseq
);
reg process_iseq_r = 1'b0, process_iseq_ns;
localparam STATE_IDLE = 2'b00;
localparam STATE_APP = 2'b01;
localparam STATE_MAINT = 2'b10;
reg[1:0] state_ns, state_r;
reg sel_fifo = 1'b0;
reg instr_en_ns, instr_en_r;
reg[31:0] instr_ns, instr_r;
always@* begin
process_iseq_ns = 1'b0;
state_ns = state_r;
instr_en_ns = 1'b0;
instr_ns = instr_r;
app_ack = 1'b0;
maint_ack = 1'b0;
case(state_r)
STATE_IDLE: begin
if(dispatcher_ready & ~process_iseq_r) begin
if(app_en) begin
state_ns = STATE_APP;
instr_en_ns = app_en;
instr_ns = app_instr;
app_ack = 1'b1;
end
else if(maint_en) begin
state_ns = STATE_MAINT;
instr_en_ns = maint_en;
instr_ns = maint_instr;
maint_ack = 1'b1;
end
end //dispatcher_ready
end //STATE_IDLE
STATE_APP: begin
app_ack = 1'b1;
instr_en_ns = app_en;
instr_ns = app_instr;
if(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin
process_iseq_ns = 1'b1;
state_ns = STATE_IDLE;
end
end //STATE_APP
STATE_MAINT: begin
maint_ack = 1'b1;
instr_en_ns = maint_en;
instr_ns = maint_instr;
if(instr_en_ns & (instr_ns[31:28] == `END_ISEQ)) begin
instr_en_ns = 1'b0;
process_iseq_ns = 1'b1;
state_ns = STATE_IDLE;
end
end //STATE_MAINT
endcase //state_r
end //always
assign instr0_fifo_en = ~sel_fifo & instr_en_r;
assign instr0_fifo_data = instr_r;
assign instr1_fifo_en = sel_fifo & instr_en_r;
assign instr1_fifo_data = instr_r;
always@(posedge clk) begin
if(rst) begin
process_iseq_r <= 1'b0;
sel_fifo <= 1'b0;
state_r <= STATE_IDLE;
instr_en_r <= 1'b0;
instr_r <= 0;
end
else begin
state_r <= state_ns;
process_iseq_r <= process_iseq_ns;
instr_en_r <= instr_en_ns;
instr_r <= instr_ns;
if(process_iseq_r)
sel_fifo <= 1'b0;
else if(instr_en_r)
sel_fifo <= ~sel_fifo;
end //!rst
end
assign process_iseq = process_iseq_r;
endmodule |
module pipe_reg #(parameter WIDTH = 8) (
input clk,
input rst,
input ready_in,
input valid_in,
input[WIDTH - 1:0] data_in,
output valid_out,
output[WIDTH - 1:0] data_out,
output ready_out
);
(* keep = "true" *) reg r_ready, r_valid1, r_valid2;
(* keep = "true" *) reg[WIDTH - 1:0] r_data1, r_data2;
wire first_buf_ready = ready_in | ~r_valid1;
assign data_out = r_data1;
assign valid_out = r_valid1;
assign ready_out = r_ready;
always@(posedge clk)
begin
if(rst) begin
r_data1 <= 0;
r_data2 <= 0;
r_ready <= 0;
r_valid1 <= 0;
r_valid2 <= 0;
end
else begin
//data acquisition
if(r_ready) begin
if(first_buf_ready) begin
r_data1 <= data_in;
r_valid1 <= valid_in;
end
else begin
r_data2 <= data_in;
r_valid2 <= valid_in;
end
end //r_ready
//data shift
if(~r_ready & ready_in) begin
r_data1 <= r_data2;
r_valid1 <= r_valid2;
end
end
//control
r_ready <= first_buf_ready;
end
endmodule |
module instr_decoder #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CS_WIDTH = 1)(
input en,
input[31:0] instr,
output reg[ROW_WIDTH - 1:0] dfi_address,
output reg[BANK_WIDTH - 1:0] dfi_bank,
output reg dfi_cas_n,
output reg[CS_WIDTH - 1:0] dfi_cs_n,
output reg dfi_ras_n,
output reg dfi_we_n
);
localparam LOW = 1'b0;
localparam HIGH = 1'b1;
always@* begin
dfi_address = {ROW_WIDTH{1'bx}};
dfi_bank = {BANK_WIDTH{1'bx}};
dfi_cas_n = HIGH;
dfi_cs_n = {CS_WIDTH{HIGH}};
dfi_ras_n = HIGH;
dfi_we_n = HIGH;
if(en) begin
dfi_address = instr[ROW_WIDTH - 1:0];
dfi_bank = instr[`ROW_OFFSET +: BANK_WIDTH];
dfi_we_n = instr[`WE_OFFSET];
dfi_cas_n = instr[`CAS_OFFSET];
dfi_ras_n = instr[`RAS_OFFSET];
dfi_cs_n = instr[`CS_OFFSET +: CS_WIDTH];
end //en
end
endmodule |
module instr_dispatcher #(parameter ROW_WIDTH = 15, BANK_WIDTH = 3, CKE_WIDTH = 1, RANK_WIDTH = 1,
CS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (
input clk,
input rst,
input periodic_read_lock,
//There are two instructions queues to fetch from. Since PHY issues DDR commands at both pos and neg edges,
//we dispatch two instructions in the same cycle, running at half of the frequency of the DDR bus
input en_in0,
output en_ack0,
input[31:0] instr_in0,
input en_in1,
output en_ack1,
input[31:0] instr_in1,
//DFI Interface
// DFI Control/Address
input dfi_ready,
output[ROW_WIDTH-1:0] dfi_address0,
output[ROW_WIDTH-1:0] dfi_address1,
output[BANK_WIDTH-1:0] dfi_bank0,
output[BANK_WIDTH-1:0] dfi_bank1,
output dfi_cke0,
output dfi_cke1,
output dfi_cas_n0,
output dfi_cas_n1,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,
output[CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,
output dfi_ras_n0,
output dfi_ras_n1,
output dfi_we_n0,
output dfi_we_n1,
// DFI Write
output reg dfi_wrdata_en,
output [4*DQ_WIDTH-1:0] dfi_wrdata,
output [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,
// DFI Read
output reg dfi_rddata_en,
output reg dfi_rddata_en_even,
output reg dfi_rddata_en_odd,
//Bus Command
output reg io_config_strobe,
output reg[1:0] io_config,
//Misc.
output pr_rd_ack,
//auto-refresh
output reg aref_set_interval,
output reg[27:0] aref_interval,
output reg aref_set_trfc,
output reg[27:0] aref_trfc
);
localparam ONE = 1;
localparam TWO = 2;
localparam HIGH = 1'b1;
localparam LOW = 1'b0;
reg[9:0] wait_cycles_r = ONE[0 +: 10], wait_cycles_ns;
reg read_burst_r, read_burst_ns;
reg read_burst_even_r, read_burst_even_ns;
reg read_burst_odd_r, read_burst_odd_ns;
reg write_burst_r, write_burst_ns;
reg[7:0] write_burst_data_r, write_burst_data_ns;
reg bus_write, bus_write_r;
reg pr_rd_ack_r, pr_rd_ack_ns;
reg ack0, ack1;
reg instr_src_r, instr_src_ns;
reg dec0_en;
wire[31:0] dec0_instr;
reg dec1_en;
wire[31:0] dec1_instr;
wire en0 = instr_src_r ? en_in1 : en_in0;
wire[31:0] instr0 = instr_src_r ? instr_in1 : instr_in0;
assign en_ack0 = instr_src_r ? ack1 : ack0;
wire en1 = instr_src_r ? en_in0 : en_in1;
wire[31:0] instr1 = instr_src_r ? instr_in0 : instr_in1;
assign en_ack1 = instr_src_r ? ack0 : ack1;
assign dec0_instr = instr0;
assign dec1_instr = instr1;
reg block_other_slot;
reg cke0, cke0_r, cke1, cke1_r;
//auto-refresh
reg aref_set_interval_ns, aref_set_trfc_ns;
reg[27:0] aref_interval_ns, aref_trfc_ns;
//Counter saturating at zero
reg load_counter;
always@(posedge clk) begin
if(rst)
wait_cycles_r <= 10'd0;
else begin
if(load_counter) begin
wait_cycles_r <= wait_cycles_ns;
end //load_counter
else begin
if(|wait_cycles_r[9:1])
wait_cycles_r <= wait_cycles_r - TWO[0 +: 10];
else
wait_cycles_r <= 10'd0;
end
end
end
always@* begin
io_config_strobe = LOW;
io_config = 2'b00;
bus_write = bus_write_r;
instr_src_ns = ~(en_in0 | en_in1) ? LOW : instr_src_r;
ack0 = HIGH;
ack1 = HIGH;
dec0_en = LOW;
dec1_en = LOW;
read_burst_ns = LOW;
read_burst_even_ns = LOW;
read_burst_odd_ns = LOW;
write_burst_ns = LOW;
write_burst_data_ns = write_burst_data_r;
dfi_rddata_en = read_burst_r;
dfi_rddata_en_even = read_burst_even_r;
dfi_rddata_en_odd = read_burst_odd_r;
dfi_wrdata_en = write_burst_r;
pr_rd_ack_ns = LOW;
aref_set_interval_ns = 1'b0;
aref_interval_ns = {28{1'bx}};
aref_set_trfc_ns = 1'b0;
aref_trfc_ns = {28{1'bx}};
wait_cycles_ns = 10'dx;
load_counter = LOW;
block_other_slot = LOW;
cke0 = cke0_r;
cke1 = cke1_r;
if(dfi_ready & (wait_cycles_r <= 10'd1)) begin
if(en0) begin
casex(instr0[31:28])
`SET_BUSDIR: begin
io_config_strobe = HIGH;
io_config = instr0[1:0];
if(instr0[1:0] == `BUS_DIR_WRITE)
bus_write = 1'b1;
else
bus_write = 1'b0;
end //SET_BUSDIR
`DDR_INSTR: begin
dec0_en = HIGH;
cke0 = instr0[`CKE_OFFSET];
if(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&
instr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a read instruction
dfi_rddata_en = HIGH;
dfi_rddata_en_even = HIGH;
read_burst_ns = HIGH;
read_burst_even_ns = HIGH;
dfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response
read_burst_odd_ns = periodic_read_lock;
pr_rd_ack_ns = HIGH;
end
if(~|instr0[`CS_OFFSET +: CS_WIDTH] && instr0[`RAS_OFFSET] && ~instr0[`CAS_OFFSET] &&
~instr0[`WE_OFFSET] && cke0 && cke0_r) begin //check whether we have a write instruction
dfi_wrdata_en = HIGH;
write_burst_ns = HIGH;
write_burst_data_ns = {instr0[30:25], instr0[(`ROW_OFFSET - 1) -:2]};
end
end //DDR_INSTR
`WAIT: begin
load_counter = HIGH;
wait_cycles_ns = instr0[9:0] - 10'd1; //reducing by one for the second slot
if(instr0[9:0] > 10'd1)
block_other_slot = HIGH;
if(~instr0[0])
instr_src_ns = ~instr_src_r;
end //WAIT
`SET_TREFI: begin
aref_set_interval_ns = 1'b1;
aref_interval_ns = instr0[27:0];
end //SET_TREFI
`SET_TRFC: begin
aref_set_trfc_ns = 1'b1;
aref_trfc_ns = instr0[27:0];
end //SET_TRFC
endcase //instr0
end //en0
end
else begin
ack0 = LOW;
end
if(~(en0 & block_other_slot) & dfi_ready & (wait_cycles_r <= 10'd2)) begin
if(en1) begin
casex(instr1[31:28])
`SET_BUSDIR: begin
io_config_strobe = HIGH;
io_config = instr1[1:0];
if(instr1[1:0] == `BUS_DIR_WRITE)
bus_write = 1'b1;
else
bus_write = 1'b0;
end //SET_BUSDIR
`DDR_INSTR: begin
dec1_en = HIGH;
cke1 = instr1[`CKE_OFFSET];
if(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&
instr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a read command
dfi_rddata_en = HIGH;
read_burst_ns = HIGH;
dfi_rddata_en_odd = periodic_read_lock; //to indicate periodic read response
read_burst_odd_ns = periodic_read_lock;
pr_rd_ack_ns = HIGH;
end
if(~|instr1[`CS_OFFSET +: CS_WIDTH] && instr1[`RAS_OFFSET] && ~instr1[`CAS_OFFSET] &&
~instr1[`WE_OFFSET] && cke1 && cke1_r) begin //check whether we have a write command
dfi_wrdata_en = HIGH;
write_burst_ns = HIGH;
write_burst_data_ns = {instr1[30:25], instr1[(`ROW_OFFSET - 1) -:2]};
end
end //DDR_INSTR
`WAIT: begin
wait_cycles_ns = instr1[9:0];
load_counter = HIGH;
if(~instr1[0])
instr_src_ns = ~instr_src_r;
end //WAIT
`SET_TREFI: begin
aref_set_interval_ns = 1'b1;
aref_interval_ns = instr1[27:0];
end //SET_TREFI
`SET_TRFC: begin
aref_set_trfc_ns = 1'b1;
aref_trfc_ns = instr1[27:0];
end //SET_TRFC
endcase //instr1
end //en1
end
else begin
ack1 = LOW;
end
end
instr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) instr_dec0(
.en(dec0_en),
.instr(dec0_instr),
.dfi_address(dfi_address0),
.dfi_bank(dfi_bank0),
.dfi_cas_n(dfi_cas_n0),
.dfi_cs_n(dfi_cs_n0),
.dfi_ras_n(dfi_ras_n0),
.dfi_we_n(dfi_we_n0)
);
instr_decoder #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CS_WIDTH(CS_WIDTH)) i_instr_dec1(
.en(dec1_en),
.instr(dec1_instr),
.dfi_address(dfi_address1),
.dfi_bank(dfi_bank1),
.dfi_cas_n(dfi_cas_n1),
.dfi_cs_n(dfi_cs_n1),
.dfi_ras_n(dfi_ras_n1),
.dfi_we_n(dfi_we_n1)
);
assign dfi_wrdata_mask = 0;
assign dfi_wrdata = dfi_cas_n0 ? {4*(DQ_WIDTH/8){write_burst_data_r}} : {4*(DQ_WIDTH/8){write_burst_data_ns}};
always@(posedge clk) begin
pr_rd_ack_r <= pr_rd_ack_ns;
end
assign pr_rd_ack = pr_rd_ack_r;
always@(posedge clk) begin
if(rst) begin
aref_set_interval <= 0;
aref_set_trfc <= 0;
aref_interval <= 0;
aref_trfc <= 0;
cke0_r <= 1'b1; //not sure what would happen if the clock is disabled on reset
cke1_r <= 1'b1;
end
else begin
aref_set_interval <= aref_set_interval_ns;
aref_set_trfc <= aref_set_trfc_ns;
aref_interval <= aref_interval_ns;
aref_trfc <= aref_trfc_ns;
cke0_r <= cke0;
cke1_r <= cke1;
end
end
always@(posedge clk) begin
if(rst) begin
read_burst_r <= LOW;
read_burst_even_r <= LOW;
read_burst_odd_r <= LOW;
write_burst_r <= LOW;
write_burst_data_r <= 0;
bus_write_r <= LOW;
instr_src_r <= LOW;
end
else begin
read_burst_r <= read_burst_ns;
read_burst_even_r <= read_burst_even_ns;
read_burst_odd_r <= read_burst_odd_ns;
write_burst_r <= write_burst_ns;
write_burst_data_r <= write_burst_data_ns;
bus_write_r <= bus_write;
instr_src_r <= instr_src_ns;
end //!rst
end
assign dfi_odt0 = bus_write_r;
assign dfi_odt1 = bus_write_r;
assign dfi_cke0 = cke0_r;
assign dfi_cke1 = cke1_r;
endmodule |
module read_capturer #(parameter DQ_WIDTH = 64) (
input clk,
input rst,
//DFI Interface
input [4*DQ_WIDTH-1:0] dfi_rddata,
input dfi_rddata_valid,
input dfi_rddata_valid_even,
input dfi_rddata_valid_odd,
output dfi_clk_disable,
//FIFO interface
input rdback_fifo_almost_full,
input rdback_fifo_full,
output rdback_fifo_wren,
output[4*DQ_WIDTH-1:0] rdback_fifo_wrdata
);
reg[4*DQ_WIDTH-1:0] rd_data_r, rd_data_r2;
reg rd_data_en_r, rd_data_en_even_r, rd_data_en_odd_r;
reg rdback_fifo_full_r;
always@(posedge clk) begin
if(rst) begin
rd_data_r <= 0;
rd_data_r2 <= 0;
rd_data_en_r <= 0;
rd_data_en_even_r <= 0;
rd_data_en_odd_r <= 0;
rdback_fifo_full_r <= 0;
end
else begin
rd_data_r <= dfi_rddata;
rd_data_r2 <= rd_data_r;
rd_data_en_r <= dfi_rddata_valid;
rd_data_en_even_r <= dfi_rddata_valid_even;
rd_data_en_odd_r <= dfi_rddata_valid_odd;
rdback_fifo_full_r <= rdback_fifo_almost_full | rdback_fifo_full;
end
end
assign rdback_fifo_wren = ~rd_data_en_odd_r & rd_data_en_r;
assign rdback_fifo_wrdata = rd_data_en_even_r ? {rd_data_r[DQ_WIDTH*2 - 1:0], rd_data_r2[DQ_WIDTH*2 +: DQ_WIDTH*2]} : rd_data_r;
assign dfi_clk_disable = rdback_fifo_full_r;
endmodule |
module maint_handler #(parameter CS_WIDTH = 1)(
input clk,
input rst,
input pr_rd_req,
input zq_req,
input autoref_req,
input[1:0] cur_bus_dir,
output maint_instr_en,
input maint_ack,
output reg[31:0] maint_instr,
input pr_rd_ack, //comes from the instruction sequence (iseq) dispatcher
output reg zq_ack,
output reg autoref_ack,
output periodic_read_lock,
input[27:0] trfc
);
localparam HIGH = 1'b1;
localparam LOW = 1'b0;
//maintenance logic
reg pr_rd_process_ns, pr_rd_process_r = 1'b0;
reg zq_process_ns, zq_process_r = 1'b0;
reg autoref_process_ns, autoref_process_r = 1'b0;
wire maint_process;
localparam PR_RD_IO = 4'b0000;
localparam PR_RD_PRE = 4'b0001;
localparam PR_RD_WAIT_PRE = 4'b0010;
localparam PR_RD_ACT = 4'b0011;
localparam PR_RD_WAIT_ACT = 4'b0100;
localparam PR_RD_READ = 4'b0101;
localparam PR_RD_WAIT_READ = 4'b0110;
localparam PR_RD_PRE2 = 4'b0111;
localparam PR_RD_WAIT_PRE2 = 4'b1000;
localparam PR_RD_WR_IO = 4'b1001;
localparam MAINT_FIN = 4'b1010;
localparam ZQ_PRE = 4'b0000;
localparam ZQ_WAIT_PRE = 4'b0001;
localparam ZQ_ZQ = 4'b0010;
localparam ZQ_WAIT_ZQ = 4'b0011;
localparam AREF_PRE = 4'b0000;
localparam AREF_WAIT_PRE = 4'b0001;
localparam AREF_REF = 4'b0010;
localparam AREF_WAIT_REF = 4'b0011;
reg[3:0] maint_state, maint_state_ns;
reg lock_pr_rd_r, lock_pr_rd_ns;
reg[1:0] cur_bus_dir_r, cur_bus_dir_ns;
always@* begin
pr_rd_process_ns = pr_rd_process_r;
zq_process_ns = zq_process_r;
autoref_process_ns = autoref_process_r;
lock_pr_rd_ns = lock_pr_rd_r;
zq_ack = 1'b0;
autoref_ack = 1'b0;
maint_state_ns = maint_state;
maint_instr = {`END_ISEQ, 28'd0};
cur_bus_dir_ns = cur_bus_dir_r;
//enter maintenance
if(~maint_process) begin
if(pr_rd_req & ~lock_pr_rd_r) begin
pr_rd_process_ns = 1'b1;
maint_state_ns = PR_RD_IO;
end //pr_rd_req
else if(zq_req) begin
zq_process_ns = 1'b1;
maint_state_ns = ZQ_PRE;
end //zq_req
else if(autoref_req) begin
autoref_process_ns = 1'b1;
maint_state_ns = AREF_PRE;
end
end //~dispatcher_busy_r
//process maintenance
if(maint_process) begin
if(pr_rd_process_r) begin //TODO: optimize to reduce periodic dummy read latency when open bank is available
case(maint_state)
PR_RD_IO: begin
maint_instr[31:28] = `SET_BUSDIR;
cur_bus_dir_ns = cur_bus_dir;
if(maint_ack)
maint_state_ns = PR_RD_PRE;
end //PR_RD_IO
PR_RD_PRE: begin
//Precharge banks 0
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = LOW;
maint_instr[10] = LOW; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = PR_RD_WAIT_PRE;
end
PR_RD_WAIT_PRE: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRP;
if(maint_ack)
maint_state_ns = PR_RD_ACT;
end //PR_RD_WAIT_PRE
PR_RD_ACT: begin
//activate bank 0, row 0
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = HIGH;
if(maint_ack)
maint_state_ns = PR_RD_WAIT_ACT;
end //PR_RD_ACT
PR_RD_WAIT_ACT: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRCD;
if(maint_ack)
maint_state_ns = PR_RD_READ;
end //PR_RD_WAIT_ACT
PR_RD_READ: begin
//Read instruction
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = HIGH;
maint_instr[`CAS_OFFSET] = LOW;
maint_instr[`WE_OFFSET] = HIGH;
if(maint_ack)
maint_state_ns = PR_RD_WAIT_READ;
end //PR_RD_READ
PR_RD_WAIT_READ: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRAS - `DEF_TRCD;
if(maint_ack)
maint_state_ns = PR_RD_PRE2;
end //PR_RD_WAIT_READ
PR_RD_PRE2: begin
//Precharge banks 0
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = LOW;
maint_instr[10] = LOW; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = PR_RD_WAIT_PRE2;
end //PR_RD_PRE2
PR_RD_WAIT_PRE2: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRP;
if(maint_ack)
maint_state_ns = (cur_bus_dir_r == `BUS_DIR_READ) ? MAINT_FIN : PR_RD_WR_IO;
end //PR_RD_WAIT_PRE2
PR_RD_WR_IO: begin
maint_instr[31:28] = `SET_BUSDIR;
maint_instr[1:0] = `BUS_DIR_WRITE;
if(maint_ack)
maint_state_ns = MAINT_FIN;
end
MAINT_FIN: begin
maint_instr[31:28] = `END_ISEQ;
pr_rd_process_ns = 1'b0;
lock_pr_rd_ns = 1'b1;
end //MAINT_FIN
endcase //pr_rd_state
end //pr_rd_process_r
else if(zq_process_r) begin
case(maint_state)
ZQ_PRE: begin
//Precharge all banks
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = LOW;
maint_instr[10] = HIGH; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = ZQ_WAIT_PRE;
end //ZQ_INIT
ZQ_WAIT_PRE: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRP;
if(maint_ack)
maint_state_ns = ZQ_ZQ;
end //ZQ_WAIT_PRE
ZQ_ZQ: begin
//ZQ-Short Instruction
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = HIGH;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = LOW;
maint_instr[10] = LOW; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = ZQ_WAIT_ZQ;
end //ZQ_ZQ
ZQ_WAIT_ZQ: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TZQCS;
if(maint_ack)
maint_state_ns = MAINT_FIN;
end //ZQ_WAIT_ZQ
MAINT_FIN: begin
maint_instr[31:28] = `END_ISEQ;
zq_process_ns = 1'b0;
zq_ack = 1'b1;
end //MAINT_FIN
endcase //maint_state
end //zq_process_r
else if(autoref_process_r) begin
case(maint_state)
AREF_PRE: begin
//Precharge all banks
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = HIGH;
maint_instr[`WE_OFFSET] = LOW;
maint_instr[10] = HIGH; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = AREF_WAIT_PRE;
end //AREF_PRE
AREF_WAIT_PRE: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = `DEF_TRP;
if(maint_ack)
maint_state_ns = AREF_REF;
end //AREF_WAIT_PRE
AREF_REF: begin
//Refresh Instruction //TODO: assign CS appropriately when implementing multi-rank support
maint_instr[31:28] = `DDR_INSTR;
maint_instr[`CKE_OFFSET] = HIGH;
maint_instr[`CS_OFFSET +: CS_WIDTH] = {{CS_WIDTH-1{HIGH}}, LOW};
maint_instr[`RAS_OFFSET] = LOW;
maint_instr[`CAS_OFFSET] = LOW;
maint_instr[`WE_OFFSET] = HIGH;
maint_instr[10] = HIGH; //10th bit of the address field, A[10]
if(maint_ack)
maint_state_ns = AREF_WAIT_REF;
end //AREF_REF
AREF_WAIT_REF: begin
maint_instr[31:28] = `WAIT;
maint_instr[27:0] = trfc;
if(maint_ack)
maint_state_ns = MAINT_FIN;
end //AREF_WAIT_REF
MAINT_FIN: begin
maint_instr[31:28] = `END_ISEQ;
autoref_process_ns = 1'b0;
autoref_ack = 1'b1;
end //MAINT_FIN
endcase //maint_state
end //autoref_process_r
end //maint_process
if(pr_rd_ack) begin
lock_pr_rd_ns = 1'b0;
pr_rd_process_ns = 1'b0;
end
end //always maintenance
assign periodic_read_lock = lock_pr_rd_r;
always@(posedge clk) begin
if(rst) begin
lock_pr_rd_r <= 1'b0;
maint_state <= 4'd0;
cur_bus_dir_r <= `BUS_DIR_READ;
end
else begin
lock_pr_rd_r <= lock_pr_rd_ns;
maint_state <= maint_state_ns;
cur_bus_dir_r <= cur_bus_dir_ns;
end
end
assign maint_process = pr_rd_process_r | zq_process_r | autoref_process_r;
assign maint_instr_en = maint_process;
always@(posedge clk) begin
pr_rd_process_r <= pr_rd_process_ns;
zq_process_r <= zq_process_ns;
autoref_process_r <= autoref_process_ns;
end
endmodule |
module maint_ctrl_top #(parameter RANK_WIDTH = 1, TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, MAINT_PRESCALER_PERIOD = 200000) (
input clk,
input rst,
input dfi_init_complete,
input periodic_rd_ack,
output periodic_rd_req,
input zq_ack,
output zq_req,
//Auto-refresh
input autoref_en,
input[27:0] autoref_interval,
input autoref_ack,
output autoref_req
);
/*** MAINTENANCE CONTROLLER ***/
wire maint_prescaler_tick;
maint_ctrl #(.TCQ(TCQ), .tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_maint_ctrl(
.clk(clk),
.rst(rst),
.dfi_init_complete(dfi_init_complete),
.maint_prescaler_tick(maint_prescaler_tick)
);
/*** PERIODIC READ CONTROLLER ***/
periodic_rd_ctrl #(.tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .TCQ(TCQ), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_prrd_ctrl(
.clk(clk),
.rst(rst),
.maint_prescaler_tick(maint_prescaler_tick),
.dfi_init_complete(dfi_init_complete),
.periodic_rd_ack(periodic_rd_ack),
.periodic_rd_req(periodic_rd_req)
);
/*** ZQ CALIBRATION CONTROLLER ***/
zq_calib_ctrl #(.TCQ(TCQ), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD)) i_zq_calib_ctrl(
.clk(clk),
.rst(rst),
.maint_prescaler_tick(maint_prescaler_tick),
.dfi_init_complete(dfi_init_complete),
.zq_ack(zq_ack),
.zq_request(zq_req)
);
autoref_ctrl #(.TCQ(TCQ)) i_autoref_ctrl (
.clk(clk),
.rst(rst),
.autoref_en(autoref_en),
.autoref_interval(autoref_interval),
.maint_prescaler_tick(maint_prescaler_tick),
.dfi_init_complete(dfi_init_complete),
.autoref_ack(autoref_ack),
.autoref_req(autoref_req)
);
endmodule |
module maint_ctrl #(parameter TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, MAINT_PRESCALER_PERIOD = 200000) (
input clk,
input rst,
input dfi_init_complete,
output maint_prescaler_tick
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam MAINT_PRESCALER_DIV = MAINT_PRESCALER_PERIOD/(tCK * nCK_PER_CLK); // Round down.
localparam MAINT_PRESCALER_WIDTH = clogb2(MAINT_PRESCALER_DIV + 1);
localparam ONE = 1;
// Maintenance and periodic read prescaler. Nominally 200 nS.
reg maint_prescaler_tick_r_lcl;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_r;
reg [MAINT_PRESCALER_WIDTH-1:0] maint_prescaler_ns;
wire maint_prescaler_tick_ns = (maint_prescaler_r == ONE[MAINT_PRESCALER_WIDTH-1:0]);
always @(/*AS*/dfi_init_complete or maint_prescaler_r
or maint_prescaler_tick_ns) begin
maint_prescaler_ns = maint_prescaler_r;
if (~dfi_init_complete || maint_prescaler_tick_ns)
maint_prescaler_ns = MAINT_PRESCALER_DIV[MAINT_PRESCALER_WIDTH-1:0];
else if (|maint_prescaler_r)
maint_prescaler_ns = maint_prescaler_r - ONE[MAINT_PRESCALER_WIDTH-1:0];
end
always @(posedge clk) maint_prescaler_r <= #TCQ maint_prescaler_ns;
always @(posedge clk) maint_prescaler_tick_r_lcl <= #TCQ maint_prescaler_tick_ns;
assign maint_prescaler_tick = maint_prescaler_tick_r_lcl;
endmodule |
module periodic_rd_ctrl #(parameter tCK = 2500, nCK_PER_CLK = 2, TCQ = 100, MAINT_PRESCALER_PERIOD = 200000) (
input clk,
input rst,
input dfi_init_complete,
input maint_prescaler_tick,
input periodic_rd_ack, //NOTE: this also should be asserted for regular reads
output periodic_rd_req
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
localparam tPRDI = 1_000_000;
localparam PERIODIC_RD_TIMER_DIV = tPRDI/MAINT_PRESCALER_PERIOD;
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
localparam ONE = 1;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r, periodic_rd_timer;
reg periodic_rd_request_r;
always @* begin
periodic_rd_timer = periodic_rd_timer_r;
if(~dfi_init_complete) begin
periodic_rd_timer = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
end
else if (periodic_rd_ack) begin
periodic_rd_timer = PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
end
else if (|periodic_rd_timer_r && maint_prescaler_tick) begin
periodic_rd_timer = periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
end //always
wire periodic_rd_timer_one = maint_prescaler_tick && (periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
wire periodic_rd_request = ~rst && (/*((PERIODIC_RD_TIMER_DIV != 0) && ~dfi_init_complete) ||*/
(~periodic_rd_ack && (periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) begin
periodic_rd_timer_r <= #TCQ periodic_rd_timer;
periodic_rd_request_r <= #TCQ periodic_rd_request;
end //always
assign periodic_rd_req = periodic_rd_request_r;
endmodule |
module zq_calib_ctrl #(parameter TCQ = 100, MAINT_PRESCALER_PERIOD = 200000) (
input clk,
input rst,
input zq_ack,
output reg zq_request,
input dfi_init_complete,
input maint_prescaler_tick
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// ZQ timebase. Nominally 128 mS
localparam MAINT_PRESCALER_PERIOD_NS = MAINT_PRESCALER_PERIOD / 1000;
localparam tZQI = 128_000_000;
localparam ZQ_TIMER_DIV = tZQI/MAINT_PRESCALER_PERIOD_NS;
localparam ZQ_TIMER_WIDTH = clogb2(ZQ_TIMER_DIV + 1);
localparam ONE = 1;
generate
begin : zq_cntrl
reg zq_tick = 1'b0;
if (ZQ_TIMER_DIV !=0) begin : zq_timer
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_r;
reg [ZQ_TIMER_WIDTH-1:0] zq_timer_ns;
always @(/*AS*/dfi_init_complete or maint_prescaler_tick
or zq_tick or zq_timer_r) begin
zq_timer_ns = zq_timer_r;
if (~dfi_init_complete || zq_tick)
zq_timer_ns = ZQ_TIMER_DIV[ZQ_TIMER_WIDTH-1:0];
else if (|zq_timer_r && maint_prescaler_tick)
zq_timer_ns = zq_timer_r - ONE[ZQ_TIMER_WIDTH-1:0];
end
always @(posedge clk) zq_timer_r <= #TCQ zq_timer_ns;
always @(/*AS*/maint_prescaler_tick or zq_timer_r)
zq_tick = (zq_timer_r == ONE[ZQ_TIMER_WIDTH-1:0] && maint_prescaler_tick);
end // zq_timer
// ZQ request. Set request with timer tick, and when exiting PHY init. Never
// request if ZQ_TIMER_DIV == 0.
begin : zq_request_logic
wire zq_clears_zq_request = zq_ack;
reg zq_request_r;
wire zq_request_ns = ~rst && ((~dfi_init_complete && (ZQ_TIMER_DIV != 0)) ||
(zq_request_r && ~zq_clears_zq_request) || zq_tick);
always @(posedge clk) zq_request_r <= #TCQ zq_request_ns;
always @(/*AS*/dfi_init_complete or zq_request_r)
zq_request = dfi_init_complete && zq_request_r;
end // zq_request_logic
end
endgenerate
endmodule |
module autoref_ctrl #(parameter TCQ = 100) (
input clk,
input rst,
input autoref_en,
input[27:0] autoref_interval,
input autoref_ack,
output autoref_req,
input dfi_init_complete,
input maint_prescaler_tick
);
localparam ONE = 1;
reg [27:0] autoref_timer_r, autoref_timer;
reg autoref_request_r;
reg ref_en_r;
always @* begin
autoref_timer = autoref_timer_r;
if(~dfi_init_complete || autoref_ack || (~ref_en_r && autoref_en)) begin
autoref_timer = autoref_interval;
end
else if (|autoref_timer_r && maint_prescaler_tick) begin
autoref_timer = autoref_timer_r - ONE[0+:28];
end
end //always
wire autoref_timer_one = maint_prescaler_tick && (autoref_timer_r == ONE[0+:28]);
wire autoref_request = ~rst && dfi_init_complete && autoref_en && (
(~autoref_ack && (autoref_request_r || autoref_timer_one)));
always @(posedge clk) begin
autoref_timer_r <= #TCQ autoref_timer;
autoref_request_r <= #TCQ autoref_request;
ref_en_r <= #TCQ autoref_en;
end //always
assign autoref_req = autoref_request_r;
endmodule |
module tb_softMC_top;
parameter REFCLK_FREQ = 200;
// # = 200 for all design frequencies of
// -1 speed grade devices
// = 200 when design frequency < 480 MHz
// for -2 and -3 speed grade devices.
// = 300 when design frequency >= 480 MHz
// for -2 and -3 speed grade devices.
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "OFF" - Complete memory init &
// calibration sequence
// # = "SKIP" - Skip memory init &
// calibration sequence
// # = "FAST" - Skip memory init & use
// abbreviated calib sequence
parameter RST_ACT_LOW = 0;
// =1 for active low reset,
// =0 for active fhigh.
parameter IODELAY_GRP = "IODELAY_MIG";
//to phy_top
parameter nCK_PER_CLK = 2;
// # of memory CKs per fabric clock.
// # = 2, 1.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per Rank for
// phy.
parameter DQS_CNT_WIDTH = 3;
// # = ceil(log2(DQS_WIDTH)).
parameter RANK_WIDTH = 1;
// # = ceil(log2(RANKS)).
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 2;
// # of CK/CK# outputs to memory.
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter DM_WIDTH = 8;
// # of Data Mask bits.
parameter DQ_WIDTH = 64;
// # of Data (DQ) bits.
parameter DQS_WIDTH = 8;
// # of DQS/DQS# bits.
parameter ROW_WIDTH = 15;
// # of memory Row Address bits.
parameter BURST_MODE = "8";
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
parameter INPUT_CLK_TYPE = "DIFFERENTIAL";
// input clock type DIFFERENTIAL or SINGLE_ENDED
parameter BM_CNT_WIDTH = 2;
// # = ceil(log2(nBANK_MACHS)).
parameter ADDR_CMD_MODE = "1T" ;
// # = "2T", "1T".
parameter ORDERING = "STRICT";
// # = "NORM", "STRICT".
parameter RTT_NOM = "60";
// RTT_NOM (ODT) (Mode Register 1).
// # = "DISABLED" - RTT_NOM disabled,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
// = "40" - RZQ/6.
parameter RTT_WR = "OFF";
// RTT_WR (ODT) (Mode Register 2).
// # = "OFF" - Dynamic ODT off,
// = "120" - RZQ/2,
// = "60" - RZQ/4,
parameter OUTPUT_DRV = "HIGH";
// Output Driver Impedance Control (Mode Register 1).
// # = "HIGH" - RZQ/7,
// = "LOW" - RZQ/6.
parameter REG_CTRL = "OFF";
// # = "ON" - RDIMMs,
// = "OFF" - Components, SODIMMs, UDIMMs.
parameter CLKFBOUT_MULT_F = 6;
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 1;
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 3;
// VCO output divisor for fast (memory) clocks.
parameter tCK = 2500;
// memory tCK paramter.
// # = Clock Period.
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
parameter tPRDI = 1_000_000;
// memory tPRDI paramter.
parameter tREFI = 7800000;
// memory tREFI paramter.
parameter tZQI = 128_000_000;
// memory tZQI paramter.
parameter ADDR_WIDTH = 29;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
parameter STARVE_LIMIT = 2;
// # = 2,3,4.
parameter TCQ = 100;
parameter ECC = "OFF";
parameter ECC_TEST = "OFF";
parameter DATA_WIDTH = 64;
parameter PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
//***********************************************************************//
// Traffic Gen related parameters
//***********************************************************************//
parameter EYE_TEST = "FALSE";
// set EYE_TEST = "TRUE" to probe memory
// signals. Traffic Generator will only
// write to one single location and no
// read transactions will be generated.
parameter SIMULATION = "TRUE";
// PRBS_DATA_MODE can only be used together with either PRBS_ADDR or SEQUENTIAL_ADDR
// FIXED_DATA_MODE is designed to work with FIXED_ADDR
parameter ADDR_MODE = 3;
//FIXED_ADDR = 2'b01;
//PRBS_ADDR = 2'b10;
//SEQUENTIAL_ADDR = 2'b11;
parameter DATA_MODE = 2; // To change simulation data pattern
// FIXED_DATA_MODE = 4'b0001;
// ADDR_DATA_MODE = 4'b0010;
// HAMMER_DATA_MODE = 4'b0011;
// NEIGHBOR_DATA_MODE = 4'b0100;
// WALKING1_DATA_MODE = 4'b0101;
// WALKING0_DATA_MODE = 4'b0110;
// PRBS_DATA_MODE = 4'b0111;
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE";
// available instruction modes:
//"FIXED_INSTR_R_MODE"
// "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE"
parameter DATA_PATTERN = "DGEN_ALL";
// DATA_PATTERN shoule be set to "DGEN_ALL"
// unless it is targeted for S6 small device.
// "DGEN_HAMMER", "DGEN_WALKING1",
// "DGEN_WALKING0","DGEN_ADDR","
// "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL";
// CMD_PATTERN shoule be set to "CGEN_ALL"
// unless it is targeted for S6 small device.
// "CGEN_RPBS","CGEN_FIXED","CGEN_BRAM",
// "CGEN_SEQUENTIAL", "CGEN_ALL"
parameter BEGIN_ADDRESS = 32'h00000000;
parameter PRBS_SADDR_MASK_POS = 32'h00000000;
parameter END_ADDRESS = 32'h000003ff;
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00;
parameter SEL_VICTIM_LINE = 11;
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00; // Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00; // Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00; // Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00; // Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00; // Delay for data signal during Read operation
localparam MEMORY_WIDTH = 8;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam real CLK_PERIOD = tCK;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam DRAM_DEVICE = "SODIMM";
// DRAM_TYPE: "UDIMM", "RDIMM", "COMPS"
// VT delay change options/settings
localparam VT_ENABLE = "OFF";
// Enable VT delay var's
localparam VT_RATE = CLK_PERIOD/500;
// Size of each VT step
localparam VT_UPDATE_INTERVAL = CLK_PERIOD*50;
// Update interval
localparam VT_MAX = CLK_PERIOD/40;
// Maximum VT shift
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam APP_DATA_WIDTH = PAYLOAD_WIDTH * 4;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg app_en;
wire app_ack;
reg[31:0] app_instr;
wire iq_full;
wire processing_iseq;
//Data read back Interface
wire rdback_fifo_empty;
reg rdback_fifo_rden;
wire[255:0] rdback_data;
reg sys_clk;
reg clk_ref;
reg sys_rst_n;
wire sys_clk_p;
wire sys_clk_n;
wire clk_ref_p;
wire clk_ref_n;
reg [DM_WIDTH-1:0] ddr3_dm_sdram_tmp;
wire sys_rst;
wire error;
wire phy_init_done;
wire ddr3_parity;
wire ddr3_reset_n;
wire sda;
wire scl;
wire [DQ_WIDTH-1:0] ddr3_dq_fpga;
wire [ROW_WIDTH-1:0] ddr3_addr_fpga;
wire [BANK_WIDTH-1:0] ddr3_ba_fpga;
wire ddr3_ras_n_fpga;
wire ddr3_cas_n_fpga;
wire ddr3_we_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_fpga;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_fpga;
wire [CKE_WIDTH-1:0] ddr3_cke_fpga;
wire [DM_WIDTH-1:0] ddr3_dm_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr3_ck_n_fpga;
wire [DQ_WIDTH-1:0] ddr3_dq_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_sdram;
reg [BANK_WIDTH-1:0] ddr3_ba_sdram;
reg ddr3_ras_n_sdram;
reg ddr3_cas_n_sdram;
reg ddr3_we_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_sdram;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_sdram;
reg [CKE_WIDTH-1:0] ddr3_cke_sdram;
wire [DM_WIDTH-1:0] ddr3_dm_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr3_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr3_ck_n_sdram;
reg [ROW_WIDTH-1:0] ddr3_addr_r;
reg [BANK_WIDTH-1:0] ddr3_ba_r;
reg ddr3_ras_n_r;
reg ddr3_cas_n_r;
reg ddr3_we_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_cs_n_r;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr3_odt_r;
reg [CKE_WIDTH-1:0] ddr3_cke_r;
wire clk;
wire rst;
wire app_sz;
wire [ADDR_WIDTH-1:0] app_addr;
wire app_wdf_wren;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire app_wdf_end;
wire app_rd_data_end;
wire app_rd_data_valid;
wire [6:0] tg_wr_fifo_counts;
wire [6:0] tg_rd_fifo_counts;
wire tg_rd_en;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [31:0] tpt_hdata;
wire t_gen_run_traffic;
wire [31:0] t_gen_start_addr;
wire [31:0] t_gen_end_addr;
wire [31:0] t_gen_cmd_seed;
wire [31:0] t_gen_data_seed;
wire t_gen_load_seed;
wire [2:0] t_gen_addr_mode;
wire [3:0] t_gen_instr_mode;
wire [1:0] t_gen_bl_mode;
wire [3:0] t_gen_data_mode;
wire t_gen_mode_load;
wire [5:0] t_gen_fixed_bl;
wire [2:0] t_gen_fixed_instr;
wire [31:0] t_gen_fixed_addr;
wire manual_clear_error;
wire modify_enable_sel;
wire [2:0] vio_data_mode;
wire [2:0] vio_addr_mode;
//**************************************************************************//
// Clock generation and reset
//**************************************************************************//
initial begin
sys_clk = 1'b0;
clk_ref = 1'b1;
sys_rst_n = 1'b0;
#120000
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
// Generate system clock = twice rate of CLK
always
sys_clk = #(CLK_PERIOD/2.0) ~sys_clk;
// Generate IDELAYCTRL reference clock (200MHz)
always
clk_ref = #REFCLK_PERIOD ~clk_ref;
assign sys_clk_p = sys_clk;
assign sys_clk_n = ~sys_clk;
assign clk_ref_p = clk_ref;
assign clk_ref_n = ~clk_ref;
//**************************************************************************//
always @( * ) begin
ddr3_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_p_fpga;
ddr3_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ck_n_fpga;
ddr3_addr_sdram <= #(TPROP_PCB_CTRL) ddr3_addr_fpga;
ddr3_ba_sdram <= #(TPROP_PCB_CTRL) ddr3_ba_fpga;
ddr3_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr3_ras_n_fpga;
ddr3_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cas_n_fpga;
ddr3_we_n_sdram <= #(TPROP_PCB_CTRL) ddr3_we_n_fpga;
ddr3_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr3_cs_n_fpga;
ddr3_cke_sdram <= #(TPROP_PCB_CTRL) ddr3_cke_fpga;
ddr3_odt_sdram <= #(TPROP_PCB_CTRL) ddr3_odt_fpga;
ddr3_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr3_dm_fpga;//DM signal generation
end
assign ddr3_dm_sdram = {DM_WIDTH{1'b0}};
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr3_dq_fpga[dqwd]),
.B (ddr3_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (phy_init_done)
);
end
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ECC)
)
u_delay_dq_0
(
.A (ddr3_dq_fpga[0]),
.B (ddr3_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (phy_init_done)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr3_dqs_p_fpga[dqswd]),
.B (ddr3_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (phy_init_done)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr3_dqs_n_fpga[dqswd]),
.B (ddr3_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (phy_init_done)
);
end
endgenerate
assign sda = 1'b1;
assign scl = 1'b1;
// Instantiate the Unit Under Test (UUT)
softMC_top #
(
.nCK_PER_CLK (nCK_PER_CLK),
.tCK (tCK),
.RST_ACT_LOW (RST_ACT_LOW),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.CKE_WIDTH (CKE_WIDTH),
.COL_WIDTH (COL_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.CS_WIDTH (CS_WIDTH),
.BURST_MODE (BURST_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.DEBUG_PORT (DEBUG_PORT),
.tPRDI (tPRDI),
.tREFI (tREFI),
.tZQI (tZQI),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.ORDERING (ORDERING),
.STARVE_LIMIT (STARVE_LIMIT),
.ADDR_WIDTH (ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.TCQ (TCQ),
.DATA_WIDTH (DATA_WIDTH),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH)
) uut (
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.clk_ref_p(clk_ref_p),
.clk_ref_n(clk_ref_n),
.sys_rst(sys_rst),
.sys_reset_n(1'b1),
.ddr_ck_p(ddr3_ck_p_fpga),
.ddr_ck_n(ddr3_ck_n_fpga),
.ddr_addr(ddr3_addr_fpga),
.ddr_ba(ddr3_ba_fpga),
.ddr_ras_n(ddr3_ras_n_fpga),
.ddr_cas_n(ddr3_cas_n_fpga),
.ddr_we_n(ddr3_we_n_fpga),
.ddr_cs_n(ddr3_cs_n_fpga),
.ddr_cke(ddr3_cke_fpga),
.ddr_odt(ddr3_odt_fpga),
.ddr_reset_n(ddr3_reset_n),
//.ddr_parity(),
.ddr_dm(),
.ddr_dqs_p(ddr3_dqs_p_fpga),
.ddr_dqs_n(ddr3_dqs_n_fpga),
.ddr_dq(ddr3_dq_fpga),
.dfi_init_complete(phy_init_done),
.iq_full(iq_full),
.processing_iseq(processing_iseq),
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
.rdback_fifo_rden(rdback_fifo_rden),
.rdback_data(rdback_data),
.rdback_fifo_empty(rdback_fifo_empty)
);
// Extra one clock pipelining for RDIMM address and
// control signals is implemented here (Implemented external to memory model)
always @( posedge ddr3_ck_p_sdram[0] ) begin
if ( ddr3_reset_n == 1'b0 ) begin
ddr3_ras_n_r <= 1'b1;
ddr3_cas_n_r <= 1'b1;
ddr3_we_n_r <= 1'b1;
ddr3_cs_n_r <= {(CS_WIDTH*nCS_PER_RANK){1'b1}};
ddr3_odt_r <= 1'b0;
end
else begin
ddr3_addr_r <= #(CLK_PERIOD/2) ddr3_addr_sdram;
ddr3_ba_r <= #(CLK_PERIOD/2) ddr3_ba_sdram;
ddr3_ras_n_r <= #(CLK_PERIOD/2) ddr3_ras_n_sdram;
ddr3_cas_n_r <= #(CLK_PERIOD/2) ddr3_cas_n_sdram;
ddr3_we_n_r <= #(CLK_PERIOD/2) ddr3_we_n_sdram;
if (~(ddr3_cs_n_sdram[0] | ddr3_cs_n_sdram[1]) & ~phy_init_done)
ddr3_cs_n_r <= #(CLK_PERIOD/2) {(CS_WIDTH*nCS_PER_RANK){1'b1}};
else
ddr3_cs_n_r <= #(CLK_PERIOD/2) ddr3_cs_n_sdram;
ddr3_odt_r <= #(CLK_PERIOD/2) ddr3_odt_sdram;
end
end
// to avoid tIS violations on CKE when reset is deasserted
always @( posedge ddr3_ck_n_sdram[0] )
if ( ddr3_reset_n == 1'b0 )
ddr3_cke_r <= 1'b0;
else
ddr3_cke_r <= #(CLK_PERIOD) ddr3_cke_sdram;
//***************************************************************************
// Instantiate memories
//***************************************************************************
genvar r,i,dqs_x;
generate
if(DRAM_DEVICE == "COMP") begin : comp_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram),
.ck_n (ddr3_ck_n_sdram),
.cke (ddr3_cke_sdram[r]),
.cs_n (ddr3_cs_n_sdram[r]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[r])
);
end
end
end
end
else if(DRAM_DEVICE == "RDIMM") begin: rdimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_r),
.cas_n (ddr3_cas_n_r),
.we_n (ddr3_we_n_r),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_r),
.addr (ddr3_addr_r),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_r[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "UDIMM") begin: udimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
else if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
else if(DRAM_DEVICE == "SODIMM") begin: sodimm_inst
for (r = 0; r < CS_WIDTH; r = r+1) begin: mem_rnk
if(MEMORY_WIDTH == 16) begin: mem_16
if(DQ_WIDTH/16) begin: gen_mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr3_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(DQ_WIDTH-1)/72]),
.ck_n (ddr3_ck_n_sdram[(DQ_WIDTH-1)/72]),
.cke (ddr3_cke_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs ({ddr3_dm_sdram[DM_WIDTH-1],ddr3_dm_sdram[DM_WIDTH-1]}),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq ({ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr3_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr3_dqs_p_sdram[DQS_WIDTH-1],
ddr3_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr3_dqs_n_sdram[DQS_WIDTH-1],
ddr3_dqs_n_sdram[DQS_WIDTH-1]}),
.tdqs_n (),
.odt (ddr3_odt_sdram[((DQ_WIDTH-1)/72)+(nCS_PER_RANK*r)])
);
end
end
if((MEMORY_WIDTH == 8) || (MEMORY_WIDTH == 4)) begin: mem_8_4
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p_sdram[(i*MEMORY_WIDTH)/72]),
.ck_n (ddr3_ck_n_sdram[(i*MEMORY_WIDTH)/72]),
.cke (ddr3_cke_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.cs_n (ddr3_cs_n_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)]),
.ras_n (ddr3_ras_n_sdram),
.cas_n (ddr3_cas_n_sdram),
.we_n (ddr3_we_n_sdram),
.dm_tdqs (ddr3_dm_sdram[i]),
.ba (ddr3_ba_sdram),
.addr (ddr3_addr_sdram),
.dq (ddr3_dq_sdram[MEMORY_WIDTH*(i+1)-1:MEMORY_WIDTH*(i)]),
.dqs (ddr3_dqs_p_sdram[i]),
.dqs_n (ddr3_dqs_n_sdram[i]),
.tdqs_n (),
.odt (ddr3_odt_sdram[((i*MEMORY_WIDTH)/72)+(nCS_PER_RANK*r)])
);
end
end
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
//***************************************************************************
localparam APP_CLK_PERIOD = tCK * nCK_PER_CLK;
initial
begin : Logging
app_en = 0;
rdback_fifo_rden = 0;
begin : calibration_done
wait (phy_init_done);
$display("Calibration Done");
#1000000;
app_en = 0;
#(APP_CLK_PERIOD*1000);
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b00010000000000000000000000000010; //busdir
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101; //wait
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10010001000100110000000000000000; //act
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000110; //wait
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10010001000110110000000010110010; //read
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101; //wait
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10101101001000111000000000001110;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000110;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b11010011001000110100000000001000;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000001010;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10010001000100110000000000000000;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b00010000000000000000000000000000;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10010001000110110000000010110010;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10000001001010110000000000001000;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000001010;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000011;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b10010001000100110000000000000000;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b01000000000000000000000000000101;
#APP_CLK_PERIOD;
app_en = 1;
app_instr = 32'b00000000000000000000000000000000;
#APP_CLK_PERIOD;
app_en = 0;
end
end
endmodule |
module autoref_config(
input clk,
input rst,
input set_interval,
input[27:0] interval_in,
input set_trfc,
input[27:0] trfc_in,
output reg aref_en,
output reg[27:0] aref_interval,
output reg[27:0] trfc
);
always@(posedge clk) begin
if(rst) begin
aref_en <= 0;
aref_interval <= 0;
trfc <= 0;
end
else begin
if(set_interval) begin
aref_en <= |interval_in;
aref_interval <= interval_in;
end //set_interval
if(set_trfc) begin
trfc <= trfc_in;
end
end
end
endmodule |
module softMC_top #
(
parameter TCQ = 100,
parameter tCK = 2500, //ps, TODO: let memory clok be 400 Mhz for now
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter REFCLK_FREQ = 200.0, // IODELAY Reference Clock freq (MHz)
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter RST_ACT_LOW = 0,
parameter INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter CLKFBOUT_MULT_F =6,
parameter DIVCLK_DIVIDE = 1,
parameter CLKOUT_DIVIDE = 3,
// Slot Conifg parameters
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
// DRAM bus widths
parameter BANK_WIDTH = 3, // # of bank bits
parameter CK_WIDTH = 2, // # of CK/CK# outputs to memory
parameter COL_WIDTH = 10, // column address width
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter RANK_WIDTH = 1, // log2(CS_WIDTH)
parameter CS_WIDTH = 1, // # of DRAM ranks
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CAL_WIDTH = "HALF", // # of DRAM ranks to be calibrated
// CAL_WIDTH = CS_WIDTH when "FULL"
// CAL_WIDTH = CS_WIDTH/2 when "HALF"
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
// DRAM mode settings
parameter AL = "0", // Additive Latency option
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nCL = 5, // Read CAS latency (in clk cyc)
parameter nCWL = 5, // Write CAS latency (in clk cyc)
parameter tRFC = 110000, // Refresh-to-command delay
parameter OUTPUT_DRV = "HIGH", // DRAM reduced output drive option
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter RTT_NOM = "60", // ODT Nominal termination value
parameter RTT_WR = "OFF", // ODT Write termination value
parameter WRLVL = "ON", // Enable write leveling
// Phase Detector/Read Leveling options
parameter PHASE_DETECT = "ON", // Enable read phase detector
parameter PD_TAP_REQ = 0, // # of IODELAY taps reserved for PD
parameter PD_MSB_SEL = 8, // # of bits in PD response cntr
parameter PD_DQS0_ONLY = "ON", // Enable use of DQS[0] only for
// phase detector
parameter PD_LHC_WIDTH = 16, // sampling averaging cntr widths
parameter PD_CALIB_MODE = "PARALLEL", // parallel/seq PD calibration
// IODELAY/BUFFER options
parameter IBUF_LPWR_MODE = "OFF", // Input buffer low power mode
parameter IODELAY_HP_MODE = "ON", // IODELAY High Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name
// when mult IP cores in design
// Pin-out related parameters
parameter nDQS_COL0 = 3, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 5, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 24'h020100,
// DQS grps in col #1
parameter DQS_LOC_COL1 = 40'h0706050403, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0, // DQS grps in col #4
parameter USE_DM_PORT = 0, // DM instantation enable
// Simulation /debug options
parameter SIM_BYPASS_INIT_CAL = "NONE",
// Parameter used to force skipping
// or abbreviation of initialization
// and calibration. Overrides
// SIM_INIT_OPTION, SIM_CAL_OPTION,
// and disables various other blocks
parameter SIM_INIT_OPTION = "NONE", // Skip various initialization steps
parameter SIM_CAL_OPTION = "NONE", // Skip various calibration steps
parameter DEBUG_PORT = "OFF", // Enable debug port
parameter SIMULATION = "OFF"
)(
input sys_clk_p,
input sys_clk_n,
input clk_ref_p,
input clk_ref_n,
input sys_rst,
input sys_reset_n,
// DDRx Output Interface
output [CK_WIDTH-1:0] ddr_ck_p,
output [CK_WIDTH-1:0] ddr_ck_n,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_ras_n,
output ddr_cas_n,
output ddr_we_n,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_odt,
output ddr_reset_n,
//output ddr_parity,
output [DM_WIDTH-1:0] ddr_dm,
inout [DQS_WIDTH-1:0] ddr_dqs_p,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQ_WIDTH-1:0] ddr_dq,
output dfi_init_complete, //led 0
output processing_iseq, //led 1
output iq_full, //led 2
output rdback_fifo_empty, //led 3
//PCIE
`ifndef SIM //we dont want to simulate PCIe core
output [7:0] pci_exp_txp,
output [7:0] pci_exp_txn,
input [7:0] pci_exp_rxp,
input [7:0] pci_exp_rxn
`else
input app_en,
output app_ack,
input[31:0] app_instr,
//Data read back Interface
//output rdback_fifo_empty,
input rdback_fifo_rden,
output[DQ_WIDTH*4 - 1:0] rdback_data
`endif //SIM
);
assign ddr_dm = {DM_WIDTH{1'b0}};
/*** CLOCK MANAGEMENT ***/
localparam SYSCLK_PERIOD = tCK * nCK_PER_CLK;
localparam MMCM_ADV_BANDWIDTH = "OPTIMIZED";
wire clk_mem, clk, clk_rd_base;
wire clk_ref = 0;
wire rst;
wire pd_PSDONE, pd_PSEN, pd_PSINCDEC; //phase detector interface
wire iodelay_ctrl_rdy;
wire mmcm_clk;
wire sys_clk = 0;
//use 200MHZ refrence clock to generate mmcm_clk
iodelay_ctrl #
(
.TCQ (TCQ),
.IODELAY_GRP (IODELAY_GRP),
.INPUT_CLK_TYPE (INPUT_CLK_TYPE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_iodelay_ctrl
(
.clk_ref_p (clk_ref_p), //input
.clk_ref_n (clk_ref_n), //input
.clk_ref (clk_ref), //input
.sys_rst (sys_rst), //input
.clk_200 (mmcm_clk),
.iodelay_ctrl_rdy (iodelay_ctrl_rdy) //output
);
infrastructure #
(
.TCQ (TCQ),
.CLK_PERIOD (SYSCLK_PERIOD),
.nCK_PER_CLK (nCK_PER_CLK),
.MMCM_ADV_BANDWIDTH (MMCM_ADV_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKOUT_DIVIDE (CLKOUT_DIVIDE),
.RST_ACT_LOW (RST_ACT_LOW)
)
u_infrastructure
(
.clk_mem (clk_mem), //output
.clk (clk), //output
.clk_rd_base (clk_rd_base), //output
.rstdiv0 (rst), //output
.mmcm_clk (mmcm_clk), //input
.sys_rst (sys_rst), //input
.iodelay_ctrl_rdy (iodelay_ctrl_rdy), //input
.PSDONE (pd_PSDONE), //output
.PSEN (pd_PSEN), //input
.PSINCDEC (pd_PSINCDEC) //input
);
wire [ROW_WIDTH-1:0] dfi_address0;
wire [ROW_WIDTH-1:0] dfi_address1;
wire [BANK_WIDTH-1:0] dfi_bank0;
wire [BANK_WIDTH-1:0] dfi_bank1;
wire dfi_cas_n0;
wire dfi_cas_n1;
wire [CKE_WIDTH-1:0] dfi_cke0;
wire [CKE_WIDTH-1:0] dfi_cke1;
wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0;
wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1;
wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0;
wire [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1;
wire dfi_ras_n0;
wire dfi_ras_n1;
wire dfi_reset_n;
assign dfi_reset_n = 1;
wire dfi_we_n0;
wire dfi_we_n1;
// DFI Write
wire dfi_wrdata_en;
wire [4*DQ_WIDTH-1:0] dfi_wrdata;
wire [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask;
// DFI Read
wire dfi_rddata_en;
wire dfi_rddata_en_even;
wire dfi_rddata_en_odd;
wire [4*DQ_WIDTH-1:0] dfi_rddata;
wire dfi_rddata_valid;
wire dfi_rddata_valid_even;
wire dfi_rddata_valid_odd;
// DFI Initialization Status / CLK Disable
wire dfi_dram_clk_disable;
// sideband signals
wire io_config_strobe;
wire [RANK_WIDTH:0] io_config;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
phy_top #(
.TCQ (TCQ),
.REFCLK_FREQ (REFCLK_FREQ),
.nCS_PER_RANK (nCS_PER_RANK),
.CAL_WIDTH (CAL_WIDTH),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.CS_WIDTH (CS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.CKE_WIDTH (CKE_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CLK_PERIOD (CLK_PERIOD),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.AL (AL),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.nAL (nAL),
.nCL (nCL),
.nCWL (nCWL),
.tRFC (tRFC),
.OUTPUT_DRV (OUTPUT_DRV),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.WRLVL (WRLVL),
.PHASE_DETECT (PHASE_DETECT),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
// Prevent the following simulation-related parameters from
// being overridden for synthesis - for synthesis only the
// default values of these parameters should be used
// synthesis translate_off
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.SIM_INIT_OPTION(SIM_INIT_OPTION),
.SIM_CAL_OPTION(SIM_CAL_OPTION),
// synthesis translate_on
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3),
.USE_DM_PORT (USE_DM_PORT),
.DEBUG_PORT (DEBUG_PORT)
) xil_phy (
.clk_mem(clk_mem), //input
.clk(clk), //input
.clk_rd_base(clk_rd_base), //input
.rst(rst), //input
.slot_0_present(SLOT_0_CONFIG), //input
.slot_1_present(SLOT_1_CONFIG), //input
.dfi_address0(dfi_address0), //Note: '0' versions are used for row commands, '1' versions for column commands
.dfi_address1(dfi_address1),
.dfi_bank0(dfi_bank0),
.dfi_bank1(dfi_bank1),
.dfi_cas_n0(dfi_cas_n0),
.dfi_cas_n1(dfi_cas_n1),
.dfi_cke0(dfi_cke0),
.dfi_cke1(dfi_cke1),
.dfi_cs_n0(dfi_cs_n0),
.dfi_cs_n1(dfi_cs_n1),
.dfi_odt0(dfi_odt0),
.dfi_odt1(dfi_odt1),
.dfi_ras_n0(dfi_ras_n0),
.dfi_ras_n1(dfi_ras_n1),
.dfi_reset_n(dfi_reset_n),
.dfi_we_n0(dfi_we_n0),
.dfi_we_n1(dfi_we_n1),
.dfi_wrdata_en(dfi_wrdata_en),
.dfi_wrdata(dfi_wrdata),
.dfi_wrdata_mask(dfi_wrdata_mask),
.dfi_rddata_en(dfi_rddata_en),
.dfi_rddata_en_even(dfi_rddata_en_even),
.dfi_rddata_en_odd(dfi_rddata_en_odd),
.dfi_rddata(dfi_rddata),
.dfi_rddata_valid(dfi_rddata_valid),
.dfi_rddata_valid_even(dfi_rddata_valid_even),
.dfi_rddata_valid_odd(dfi_rddata_valid_odd),
.dfi_dram_clk_disable(dfi_dram_clk_disable),
.dfi_init_complete(dfi_init_complete),
//sideband signals
.io_config_strobe(io_config_strobe), //input
.io_config(io_config), //input [RANK_WIDTH:0]
//DRAM signals
.ddr_ck_p(ddr_ck_p),
.ddr_ck_n(ddr_ck_n),
.ddr_addr(ddr_addr),
.ddr_ba(ddr_ba),
.ddr_ras_n(ddr_ras_n),
.ddr_cas_n(ddr_cas_n),
.ddr_we_n(ddr_we_n),
.ddr_cs_n(ddr_cs_n),
.ddr_cke(ddr_cke),
.ddr_odt(ddr_odt),
.ddr_reset_n(ddr_reset_n),
//.ddr_parity(ddr_parity),
.ddr_dm(ddr_dm),
.ddr_dqs_p(ddr_dqs_p),
.ddr_dqs_n(ddr_dqs_n),
.ddr_dq(ddr_dq),
//phase detection signals
.pd_PSDONE(pd_PSDONE),
.pd_PSEN(pd_PSEN),
.pd_PSINCDEC(pd_PSINCDEC)
);
//App Command Interface
`ifndef SIM
wire app_en;
wire app_ack;
wire[31:0] app_instr;
//Data read back Interface
wire rdback_fifo_rden;
wire[DQ_WIDTH*4 - 1:0] rdback_data;
`endif //SIM
softMC #(.TCQ(TCQ), .tCK(tCK), .nCK_PER_CLK(nCK_PER_CLK), .RANK_WIDTH(RANK_WIDTH), .ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH),
.CKE_WIDTH(CKE_WIDTH), .CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_softmc(
.clk(clk),
.rst(rst),
//App Command Interface
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
.iq_full(iq_full),
.processing_iseq(processing_iseq),
// DFI Control/Address
.dfi_address0(dfi_address0),
.dfi_address1(dfi_address1),
.dfi_bank0(dfi_bank0),
.dfi_bank1(dfi_bank1),
.dfi_cas_n0(dfi_cas_n0),
.dfi_cas_n1(dfi_cas_n1),
.dfi_cke0(dfi_cke0),
.dfi_cke1(dfi_cke1),
.dfi_cs_n0(dfi_cs_n0),
.dfi_cs_n1(dfi_cs_n1),
.dfi_odt0(dfi_odt0),
.dfi_odt1(dfi_odt1),
.dfi_ras_n0(dfi_ras_n0),
.dfi_ras_n1(dfi_ras_n1),
.dfi_reset_n(dfi_reset_n),
.dfi_we_n0(dfi_we_n0),
.dfi_we_n1(dfi_we_n1),
// DFI Write
.dfi_wrdata_en(dfi_wrdata_en),
.dfi_wrdata(dfi_wrdata),
.dfi_wrdata_mask(dfi_wrdata_mask),
// DFI Read
.dfi_rddata_en(dfi_rddata_en),
.dfi_rddata_en_even(dfi_rddata_en_even),
.dfi_rddata_en_odd(dfi_rddata_en_odd),
.dfi_rddata(dfi_rddata),
.dfi_rddata_valid(dfi_rddata_valid),
.dfi_rddata_valid_even(dfi_rddata_valid_even),
.dfi_rddata_valid_odd(dfi_rddata_valid_odd),
// DFI Initialization Status / CLK Disable
.dfi_dram_clk_disable(dfi_dram_clk_disable),
.dfi_init_complete(dfi_init_complete),
// sideband signals
.io_config_strobe(io_config_strobe),
.io_config(io_config),
//Data read back Interface
.rdback_fifo_empty(rdback_fifo_empty),
.rdback_fifo_rden(rdback_fifo_rden),
.rdback_data(rdback_data)
);
`ifndef SIM
riffa_top_v6_pcie_v2_5 #(
.C_DATA_WIDTH(64), // RX/TX interface data width
.DQ_WIDTH(DQ_WIDTH)
) i_pcie_top
(
.pci_exp_txp(pci_exp_txp),
.pci_exp_txn(pci_exp_txn),
.pci_exp_rxp(pci_exp_rxp),
.pci_exp_rxn(pci_exp_rxn),
.sys_clk_p(sys_clk_p),
.sys_clk_n(sys_clk_n),
.sys_reset_n(sys_reset_n),
.app_clk(clk),
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
//Data read back Interface
.rdback_fifo_empty(rdback_fifo_empty),
.rdback_fifo_rden(rdback_fifo_rden),
.rdback_data(rdback_data)
);
`endif //SIM
endmodule |
module softMC #(parameter TCQ = 100, tCK = 2500, nCK_PER_CLK = 2, RANK_WIDTH = 1, ROW_WIDTH = 15, BANK_WIDTH = 3,
CKE_WIDTH = 1, CS_WIDTH = 1, nCS_PER_RANK = 1, DQ_WIDTH = 64) (
input clk,
input rst,
//App Command Interface
input app_en,
output app_ack,
input[31:0] app_instr,
output iq_full,
output processing_iseq,
// DFI Control/Address
output [ROW_WIDTH-1:0] dfi_address0,
output [ROW_WIDTH-1:0] dfi_address1,
output [BANK_WIDTH-1:0] dfi_bank0,
output [BANK_WIDTH-1:0] dfi_bank1,
output dfi_cas_n0,
output dfi_cas_n1,
output [CKE_WIDTH-1:0] dfi_cke0,
output [CKE_WIDTH-1:0] dfi_cke1,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n0,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_cs_n1,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt0,
output [CS_WIDTH*nCS_PER_RANK-1:0] dfi_odt1,
output dfi_ras_n0,
output dfi_ras_n1,
output dfi_reset_n,
output dfi_we_n0,
output dfi_we_n1,
// DFI Write
output dfi_wrdata_en,
output [4*DQ_WIDTH-1:0] dfi_wrdata,
output [4*(DQ_WIDTH/8)-1:0] dfi_wrdata_mask,
// DFI Read
output dfi_rddata_en,
output dfi_rddata_en_even,
output dfi_rddata_en_odd,
input [4*DQ_WIDTH-1:0] dfi_rddata,
input dfi_rddata_valid,
input dfi_rddata_valid_even,
input dfi_rddata_valid_odd,
// DFI Initialization Status / CLK Disable
output dfi_dram_clk_disable,
input dfi_init_complete,
// sideband signals
output io_config_strobe,
output [RANK_WIDTH:0] io_config,
//Data read back Interface
output rdback_fifo_empty,
input rdback_fifo_rden,
output[DQ_WIDTH*4 - 1:0] rdback_data
);
//DFI constants
assign dfi_reset_n = 1;
wire instr0_fifo_en, instr0_fifo_full, instr0_fifo_empty;
wire[31:0] instr0_fifo_data, instr0_fifo_out;
wire instr0_fifo_rd_en;
wire instr1_fifo_en, instr1_fifo_full, instr1_fifo_empty;
wire[31:0] instr1_fifo_data, instr1_fifo_out;
wire instr1_fifo_rd_en;
wire process_iseq;
//MAINTENANCE module
localparam MAINT_PRESCALER_PERIOD = 200000;
wire pr_rd_req, zq_req, autoref_req;
wire pr_rd_ack, zq_ack, autoref_ack;
//Auto-refresh signals
wire aref_en;
wire[27:0] aref_interval;
wire[27:0] aref_trfc;
wire aref_set_interval, aref_set_trfc;
wire[27:0] aref_interval_in;
wire[27:0] aref_trfc_in;
maint_ctrl_top #(.RANK_WIDTH(RANK_WIDTH), .TCQ (TCQ), .tCK(tCK),
.nCK_PER_CLK(nCK_PER_CLK), .MAINT_PRESCALER_PERIOD(MAINT_PRESCALER_PERIOD))
i_maint_ctrl(
.clk(clk),
.rst(rst),
.dfi_init_complete(dfi_init_complete),
.periodic_rd_ack(pr_rd_ack),
.periodic_rd_req(pr_rd_req),
.zq_ack(zq_ack),
.zq_req(zq_req),
//Auto-refresh
.autoref_en(aref_en),
.autoref_interval(aref_interval),
.autoref_ack(autoref_ack),
.autoref_req(autoref_req)
);
wire periodic_read_lock;
wire maint_en;
wire maint_ack;
wire[31:0] maint_instr;
maint_handler #(.CS_WIDTH(CS_WIDTH)) i_maint_handler(
.clk(clk),
.rst(rst),
.pr_rd_req(pr_rd_req),
.zq_req(zq_req),
.autoref_req(autoref_req),
.cur_bus_dir(dfi_odt0 ? `BUS_DIR_WRITE : `BUS_DIR_READ),
.maint_instr_en(maint_en),
.maint_ack(maint_ack),
.maint_instr(maint_instr),
.pr_rd_ack(pr_rd_ack), //comes from the transaction dispatcher
.zq_ack(zq_ack),
.autoref_ack(autoref_ack),
.periodic_read_lock(periodic_read_lock),
.trfc(aref_trfc)
);
autoref_config i_aref_config(
.clk(clk),
.rst(rst),
.set_interval(aref_set_interval),
.interval_in(aref_interval_in),
.set_trfc(aref_set_trfc),
.trfc_in(aref_trfc_in),
.aref_en(aref_en),
.aref_interval(aref_interval),
.trfc(aref_trfc)
);
instr_receiver i_instr_recv(
.clk(clk),
.rst(rst),
.dispatcher_ready(~dispatcher_busy),
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
.maint_en(maint_en),
.maint_ack(maint_ack),
.maint_instr(maint_instr),
.instr0_fifo_en(instr0_fifo_en),
.instr0_fifo_data(instr0_fifo_data),
.instr1_fifo_en(instr1_fifo_en),
.instr1_fifo_data(instr1_fifo_data),
.process_iseq(process_iseq)
);
instr_fifo i_instr0_fifo (
.srst(rst), // input rst
.clk(clk), // input clk
.din(instr0_fifo_data), // input [31 : 0] din
.wr_en(instr0_fifo_en), // input wr_en
.rd_en(instr0_fifo_rd_en), // input rd_en
.dout(instr0_fifo_out), // output [31 : 0] dout
.full(instr0_fifo_full), // output full
.empty(instr0_fifo_empty) // output empty
);
instr_fifo i_instr1_fifo (
.srst(rst), // input rst
.clk(clk), // input clk
.din(instr1_fifo_data), // input [31 : 0] din
.wr_en(instr1_fifo_en), // input wr_en
.rd_en(instr1_fifo_rd_en), // input rd_en
.dout(instr1_fifo_out), // output [31 : 0] dout
.full(instr1_fifo_full), // output full
.empty(instr1_fifo_empty) // output empty
);
wire dfi_ready;
iseq_dispatcher #(.ROW_WIDTH(ROW_WIDTH), .BANK_WIDTH(BANK_WIDTH), .CKE_WIDTH(CKE_WIDTH),
.CS_WIDTH(CS_WIDTH), .nCS_PER_RANK(nCS_PER_RANK), .DQ_WIDTH(DQ_WIDTH)) i_iseq_disp (
.clk(clk),
.rst(rst),
.periodic_read_lock(periodic_read_lock),
.process_iseq(process_iseq),
.dispatcher_busy(dispatcher_busy),
.instr0_fifo_rd(instr0_fifo_rd_en),
.instr0_fifo_empty(instr0_fifo_empty),
.instr0_fifo_data(instr0_fifo_out),
.instr1_fifo_rd(instr1_fifo_rd_en),
.instr1_fifo_empty(instr1_fifo_empty),
.instr1_fifo_data(instr1_fifo_out),
//DFI Interface
.dfi_ready(dfi_ready),
.dfi_init_complete(dfi_init_complete),
.dfi_address0(dfi_address0),
.dfi_address1(dfi_address1),
.dfi_bank0(dfi_bank0),
.dfi_bank1(dfi_bank1),
.dfi_cke0(dfi_cke0),
.dfi_cke1(dfi_cke1),
.dfi_cas_n0(dfi_cas_n0),
.dfi_cas_n1(dfi_cas_n1),
.dfi_cs_n0(dfi_cs_n0),
.dfi_cs_n1(dfi_cs_n1),
.dfi_odt0(dfi_odt0),
.dfi_odt1(dfi_odt1),
.dfi_ras_n0(dfi_ras_n0),
.dfi_ras_n1(dfi_ras_n1),
.dfi_we_n0(dfi_we_n0),
.dfi_we_n1(dfi_we_n1),
.dfi_wrdata_en(dfi_wrdata_en),
.dfi_wrdata(dfi_wrdata),
.dfi_wrdata_mask(dfi_wrdata_mask),
.dfi_rddata_en(dfi_rddata_en),
.dfi_rddata_en_even(dfi_rddata_en_even),
.dfi_rddata_en_odd(dfi_rddata_en_odd),
.io_config_strobe(io_config_strobe),
.io_config(io_config),
.pr_rd_ack(pr_rd_ack),
//auto-refresh
.aref_set_interval(aref_set_interval),
.aref_interval(aref_interval_in),
.aref_set_trfc(aref_set_trfc),
.aref_trfc(aref_trfc_in)
);
assign iq_full = instr0_fifo_full | instr1_fifo_full;
assign processing_iseq = dispatcher_busy;
wire[DQ_WIDTH*4 - 1: 0] rdback_fifo_wrdata, rdback_fifo_out;
wire rdback_fifo_full, rdback_fifo_almost_full;
wire rdback_fifo_wren;
rdback_fifo i_rdback_fifo (
.clk(clk), // input clk
.srst(rst), // input srst
.din(rdback_fifo_wrdata), // input [255 : 0] din
.wr_en(rdback_fifo_wren), // input wr_en
.rd_en(rdback_fifo_rden), // input rd_en
.dout(rdback_fifo_out), // output [255 : 0] dout
.full(rdback_fifo_full), // output full
.almost_full(rdback_fifo_almost_full),
.empty(rdback_fifo_empty) // output empty
);
assign rdback_data = rdback_fifo_out;
wire read_capturer_dfi_clk_disable;
read_capturer #(.DQ_WIDTH(DQ_WIDTH)) i_rd_capturer (
.clk(clk),
.rst(rst),
//DFI Interface
.dfi_rddata(dfi_rddata),
.dfi_rddata_valid(dfi_rddata_valid),
.dfi_rddata_valid_even(dfi_rddata_valid_even),
.dfi_rddata_valid_odd(dfi_rddata_valid_odd),
.dfi_clk_disable(read_capturer_dfi_clk_disable),
//FIFO interface
.rdback_fifo_full(rdback_fifo_full),
.rdback_fifo_almost_full(rdback_fifo_almost_full),
.rdback_fifo_wren(rdback_fifo_wren),
.rdback_fifo_wrdata(rdback_fifo_wrdata)
);
assign dfi_dram_clk_disable = read_capturer_dfi_clk_disable;
assign dfi_ready = ~dfi_dram_clk_disable;
endmodule |
module gtx_wrapper_v6 (
// TX
TX,
TX_,
TxData,
TxDataK,
TxElecIdle,
TxCompliance,
// RX
RX,
RX_,
RxData,
RxDataK,
RxPolarity,
RxValid,
RxElecIdle,
RxStatus,
// other
GTRefClkout,
plm_in_l0,
plm_in_rl,
plm_in_dt,
plm_in_rs,
RxPLLLkDet,
TxDetectRx,
PhyStatus,
TXPdownAsynch,
PowerDown,
Rate,
Reset_n,
GTReset_n,
PCLK,
REFCLK,
TxDeemph,
TxMargin,
TxSwing,
ChanIsAligned,
local_pcs_reset,
RxResetDone,
SyncDone,
DRPCLK,
TxOutClk
);
parameter NO_OF_LANES = 1;
parameter REF_CLK_FREQ = 0;
parameter PL_FAST_TRAIN = "FALSE";
localparam GTX_PLL_DIVSEL_FB = (REF_CLK_FREQ == 0) ? 5 :
(REF_CLK_FREQ == 1) ? 4 :
(REF_CLK_FREQ == 2) ? 2 : 0;
localparam SIMULATION = (PL_FAST_TRAIN == "TRUE") ? 1 : 0;
localparam RXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :
(REF_CLK_FREQ == 1) ? 8'h05 :
(REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;
localparam TXPLL_CP_CFG = (REF_CLK_FREQ == 0) ? 8'h05 :
(REF_CLK_FREQ == 1) ? 8'h05 :
(REF_CLK_FREQ == 2) ? 8'h05 : 8'h05;
localparam RX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
(REF_CLK_FREQ == 1) ? 5 :
(REF_CLK_FREQ == 2) ? 10 : 10 ;
localparam TX_CLK25_DIVIDER = (REF_CLK_FREQ == 0) ? 4 :
(REF_CLK_FREQ == 1) ? 5 :
(REF_CLK_FREQ == 2) ? 10 : 10 ;
// TX
output [NO_OF_LANES-1:0] TX;
output [NO_OF_LANES-1:0] TX_;
input [(NO_OF_LANES*16)-1:0] TxData;
input [(NO_OF_LANES*2)-1:0] TxDataK;
input [NO_OF_LANES-1:0] TxElecIdle;
input [NO_OF_LANES-1:0] TxCompliance;
// RX
input [NO_OF_LANES-1:0] RX;
input [NO_OF_LANES-1:0] RX_;
output [(NO_OF_LANES*16)-1:0] RxData;
output [(NO_OF_LANES*2)-1:0] RxDataK;
input [NO_OF_LANES-1:0] RxPolarity;
output [NO_OF_LANES-1:0] RxValid;
output [NO_OF_LANES-1:0] RxElecIdle;
output [(NO_OF_LANES*3)-1:0] RxStatus;
// other
output [NO_OF_LANES-1:0] GTRefClkout;
input plm_in_l0;
input plm_in_rl;
input plm_in_dt;
input plm_in_rs;
output [NO_OF_LANES-1:0] RxPLLLkDet;
input TxDetectRx;
output [NO_OF_LANES-1:0] PhyStatus;
input PCLK;
output [NO_OF_LANES-1:0] ChanIsAligned;
input TXPdownAsynch;
input [(NO_OF_LANES*2)-1:0] PowerDown;
input Rate;
input Reset_n;
input GTReset_n;
input REFCLK;
input TxDeemph;
input TxMargin;
input TxSwing;
input local_pcs_reset;
output RxResetDone;
output SyncDone;
input DRPCLK;
output TxOutClk;
genvar i;
// dummy signals to avoid port mismatch with DUAL_GTX
wire [15:0] RxData_dummy;
wire [1:0] RxDataK_dummy;
wire [15:0] TxData_dummy;
wire [1:0] TxDataK_dummy;
// inputs
wire [(NO_OF_LANES*16)-1:0] GTX_TxData = TxData;
wire [(NO_OF_LANES*2)-1:0] GTX_TxDataK = TxDataK;
wire [(NO_OF_LANES)-1:0] GTX_TxElecIdle = TxElecIdle;
wire [(NO_OF_LANES-1):0] GTX_TxCompliance = TxCompliance;
wire [(NO_OF_LANES)-1:0] GTX_RXP = RX[(NO_OF_LANES)-1:0];
wire [(NO_OF_LANES)-1:0] GTX_RXN = RX_[(NO_OF_LANES)-1:0];
// outputs
wire [(NO_OF_LANES)-1:0] GTX_TXP;
wire [(NO_OF_LANES)-1:0] GTX_TXN;
wire [(NO_OF_LANES*16)-1:0] GTX_RxData;
wire [(NO_OF_LANES*2)-1:0] GTX_RxDataK;
wire [(NO_OF_LANES)-1:0] GTX_RxPolarity = RxPolarity ;
wire [(NO_OF_LANES)-1:0] GTX_RxValid;
wire [(NO_OF_LANES)-1:0] GTX_RxElecIdle;
wire [(NO_OF_LANES-1):0] GTX_RxResetDone;
wire [(NO_OF_LANES*3)-1:0] GTX_RxChbondLevel;
wire [(NO_OF_LANES*3)-1:0] GTX_RxStatus;
wire [3:0] RXCHBOND [NO_OF_LANES+1:0];
wire [3:0] TXBYPASS8B10B = 4'b0000;
wire RXDEC8B10BUSE = 1'b1;
wire [NO_OF_LANES-1:0] GTX_PhyStatus;
wire RESETDONE [NO_OF_LANES-1:0];
wire REFCLK;
wire GTXRESET = 1'b0;
wire [NO_OF_LANES-1:0] SYNC_DONE;
wire [NO_OF_LANES-1:0] OUT_DIV_RESET;
wire [NO_OF_LANES-1:0] PCS_RESET;
wire [NO_OF_LANES-1:0] TXENPMAPHASEALIGN;
wire [NO_OF_LANES-1:0] TXPMASETPHASE;
wire [NO_OF_LANES-1:0] TXRESETDONE;
wire [NO_OF_LANES-1:0] TXRATEDONE;
wire [NO_OF_LANES-1:0] PHYSTATUS;
wire [NO_OF_LANES-1:0] RXVALID;
wire [NO_OF_LANES-1:0] RATE_CLK_SEL;
wire [NO_OF_LANES-1:0] TXOCLK;
wire [NO_OF_LANES-1:0] TXDLYALIGNDISABLE;
wire [NO_OF_LANES-1:0] TXDLYALIGNRESET;
reg [(NO_OF_LANES-1):0] GTX_RxResetDone_q;
reg [(NO_OF_LANES-1):0] TXRESETDONE_q;
wire [NO_OF_LANES-1:0] RxValid;
wire [(NO_OF_LANES*8-1):0] daddr;
wire [NO_OF_LANES-1:0] den;
wire [(NO_OF_LANES*16-1):0] din;
wire [NO_OF_LANES-1:0] dwe;
wire [(NO_OF_LANES*4-1):0] drpstate;
wire [NO_OF_LANES-1:0] drdy;
wire [(NO_OF_LANES*16-1):0] dout;
wire write_drp_cb_fts;
wire write_drp_cb_ts1;
assign RxResetDone = &(GTX_RxResetDone_q[(NO_OF_LANES)-1:0]);
assign TX[(NO_OF_LANES)-1:0] = GTX_TXP[(NO_OF_LANES)-1:0];
assign TX_[(NO_OF_LANES)-1:0] = GTX_TXN[(NO_OF_LANES)-1:0];
assign RXCHBOND[0] = 4'b0000;
assign TxData_dummy = 16'b0;
assign TxDataK_dummy = 2'b0;
assign SyncDone = &(SYNC_DONE[(NO_OF_LANES)-1:0]);
assign TxOutClk = TXOCLK[0];
assign write_drp_cb_fts = plm_in_l0;
assign write_drp_cb_ts1 = plm_in_rl | plm_in_dt;
// pipeline to improve timing
always @ (posedge PCLK) begin
GTX_RxResetDone_q[(NO_OF_LANES)-1:0] <= GTX_RxResetDone[(NO_OF_LANES)-1:0];
TXRESETDONE_q[(NO_OF_LANES)-1:0] <= TXRESETDONE[(NO_OF_LANES)-1:0];
end
generate
begin: no_of_lanes
for (i=0; i < NO_OF_LANES; i=i+1) begin: GTXD
assign GTX_RxChbondLevel[(3*i)+2:(3*i)] = (NO_OF_LANES-(i+1));
GTX_DRP_CHANALIGN_FIX_3752_V6 # (
.C_SIMULATION(SIMULATION)
) GTX_DRP_CHANALIGN_FIX_3752 (
.dwe(dwe[i]),
.din(din[(16*i)+15:(16*i)]),
.den(den[i]),
.daddr(daddr[(8*i)+7:(8*i)]),
.drpstate(drpstate[(4*i)+3:(4*i)]),
.write_ts1(write_drp_cb_ts1),
.write_fts(write_drp_cb_fts),
.dout(dout[(16*i)+15:(16*i)]),
.drdy(drdy[i]),
.Reset_n(Reset_n),
.drp_clk(DRPCLK)
);
GTX_RX_VALID_FILTER_V6 # (
.CLK_COR_MIN_LAT(28)
)
GTX_RX_VALID_FILTER (
.USER_RXCHARISK ( RxDataK[(2*i)+1:2*i] ), //O
.USER_RXDATA ( RxData[(16*i)+15:(16*i)+0] ), //O
.USER_RXVALID ( RxValid[i] ), //O
.USER_RXELECIDLE ( RxElecIdle[i] ), //O
.USER_RX_STATUS ( RxStatus[(3*i)+2:(3*i)] ), //O
.USER_RX_PHY_STATUS ( PhyStatus[i] ), //O
.GT_RXCHARISK ( GTX_RxDataK[(2*i)+1:2*i] ), //I
.GT_RXDATA ( GTX_RxData[(16*i)+15:(16*i)+0] ), //I
.GT_RXVALID ( GTX_RxValid[i] ), //I
.GT_RXELECIDLE ( GTX_RxElecIdle[i] ), //I
.GT_RX_STATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ), //I
.GT_RX_PHY_STATUS ( PHYSTATUS[i] ),
.PLM_IN_L0 ( plm_in_l0 ), //I
.PLM_IN_RS ( plm_in_rs ), //I
.USER_CLK ( PCLK ), //I
.RESET ( !Reset_n ) //I
);
GTX_TX_SYNC_RATE_V6 # (
.C_SIMULATION(SIMULATION)
)
GTX_TX_SYNC (
.ENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ), //O
.PMASETPHASE ( TXPMASETPHASE[i] ), //O
.SYNC_DONE ( SYNC_DONE[i] ), //O
.OUT_DIV_RESET ( OUT_DIV_RESET[i] ), //O
.PCS_RESET ( PCS_RESET[i] ), //O
.USER_PHYSTATUS ( PHYSTATUS[i] ), //O
.TXALIGNDISABLE ( TXDLYALIGNDISABLE[i] ), //O
.DELAYALIGNRESET ( TXDLYALIGNRESET[i] ), //O
.USER_CLK ( PCLK), //I
.RESET ( !Reset_n ), //I
.RATE ( Rate ), //I
.RATEDONE ( TXRATEDONE[i] ), //I
.GT_PHYSTATUS ( GTX_PhyStatus[i] ), //I
.RESETDONE ( TXRESETDONE_q[i] & GTX_RxResetDone_q[i] ) //I
);
GTXE1 # (
.TX_DRIVE_MODE("PIPE"),
.TX_DEEMPH_1(5'b10010),
.TX_MARGIN_FULL_0(7'b100_1101),
.TX_CLK_SOURCE("RXPLL"),
.POWER_SAVE(10'b0000110100),
.CM_TRIM ( 2'b01 ),
.PMA_CDR_SCAN ( 27'h640404C ),
.PMA_CFG( 76'h0040000040000000003 ),
.RCV_TERM_GND ("TRUE"),
.RCV_TERM_VTTRX ("FALSE"),
.RX_DLYALIGN_EDGESET(5'b00010),
.RX_DLYALIGN_LPFINC(4'b0110),
.RX_DLYALIGN_OVRDSETTING(8'b10000000),
.TERMINATION_CTRL(5'b00000),
.TERMINATION_OVRD("FALSE"),
.TX_DLYALIGN_LPFINC(4'b0110),
.TX_DLYALIGN_OVRDSETTING(8'b10000000),
.TXPLL_CP_CFG( TXPLL_CP_CFG ),
.OOBDETECT_THRESHOLD( 3'b011 ),
.RXPLL_CP_CFG ( RXPLL_CP_CFG ),
//.TX_DETECT_RX_CFG( 14'h1832 ),
.TX_TDCC_CFG ( 2'b11 ),
.BIAS_CFG ( 17'h00000 ),
.AC_CAP_DIS ( "FALSE" ),
.DFE_CFG ( 8'b00011011 ),
.SIM_TX_ELEC_IDLE_LEVEL("1"),
.SIM_RECEIVER_DETECT_PASS("TRUE"),
.RX_EN_REALIGN_RESET_BUF("FALSE"),
.TX_IDLE_ASSERT_DELAY(3'b100), // TX-idle-set-to-idle (13 UI)
.TX_IDLE_DEASSERT_DELAY(3'b010), // TX-idle-to-diff (7 UI)
.CHAN_BOND_SEQ_2_CFG(5'b11111), // 5'b11111 for PCIE mode, 5'b00000 for other modes
.CHAN_BOND_KEEP_ALIGN("TRUE"),
.RX_IDLE_HI_CNT(4'b1000),
.RX_IDLE_LO_CNT(4'b0000),
.RX_EN_IDLE_RESET_BUF("TRUE"),
.TX_DATA_WIDTH(20),
.RX_DATA_WIDTH(20),
.ALIGN_COMMA_WORD(1),
.CHAN_BOND_1_MAX_SKEW(7),
.CHAN_BOND_2_MAX_SKEW(1),
.CHAN_BOND_SEQ_1_1(10'b0001000101), // D5.2 (end TS2)
.CHAN_BOND_SEQ_1_2(10'b0001000101), // D5.2 (end TS2)
.CHAN_BOND_SEQ_1_3(10'b0001000101), // D5.2 (end TS2)
.CHAN_BOND_SEQ_1_4(10'b0110111100), // K28.5 (COM)
.CHAN_BOND_SEQ_1_ENABLE(4'b1111), // order is 4321
.CHAN_BOND_SEQ_2_1(10'b0100111100), // K28.1 (FTS)
.CHAN_BOND_SEQ_2_2(10'b0100111100), // K28.1 (FTS)
.CHAN_BOND_SEQ_2_3(10'b0110111100), // K28.5 (COM)
.CHAN_BOND_SEQ_2_4(10'b0100111100), // K28.1 (FTS)
.CHAN_BOND_SEQ_2_ENABLE(4'b1111), // order is 4321
.CHAN_BOND_SEQ_2_USE("TRUE"),
.CHAN_BOND_SEQ_LEN(4), // 1..4
.RX_CLK25_DIVIDER(RX_CLK25_DIVIDER),
.TX_CLK25_DIVIDER(TX_CLK25_DIVIDER),
.CLK_COR_ADJ_LEN(1), // 1..4
.CLK_COR_DET_LEN(1), // 1..4
.CLK_COR_INSERT_IDLE_FLAG("FALSE"),
.CLK_COR_KEEP_IDLE("FALSE"),
.CLK_COR_MAX_LAT(30),
.CLK_COR_MIN_LAT(28),
.CLK_COR_PRECEDENCE("TRUE"),
.CLK_CORRECT_USE("TRUE"),
.CLK_COR_REPEAT_WAIT(0),
.CLK_COR_SEQ_1_1(10'b0100011100), // K28.0 (SKP)
.CLK_COR_SEQ_1_2(10'b0000000000),
.CLK_COR_SEQ_1_3(10'b0000000000),
.CLK_COR_SEQ_1_4(10'b0000000000),
.CLK_COR_SEQ_1_ENABLE(4'b1111),
.CLK_COR_SEQ_2_1(10'b0000000000),
.CLK_COR_SEQ_2_2(10'b0000000000),
.CLK_COR_SEQ_2_3(10'b0000000000),
.CLK_COR_SEQ_2_4(10'b0000000000),
.CLK_COR_SEQ_2_ENABLE(4'b1111),
.CLK_COR_SEQ_2_USE("FALSE"),
.COMMA_10B_ENABLE(10'b1111111111),
.COMMA_DOUBLE("FALSE"),
.DEC_MCOMMA_DETECT("TRUE"),
.DEC_PCOMMA_DETECT("TRUE"),
.DEC_VALID_COMMA_ONLY("TRUE"),
.MCOMMA_10B_VALUE(10'b1010000011),
.MCOMMA_DETECT("TRUE"),
.PCI_EXPRESS_MODE("TRUE"),
.PCOMMA_10B_VALUE(10'b0101111100),
.PCOMMA_DETECT("TRUE"),
.RXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
.TXPLL_DIVSEL_FB(GTX_PLL_DIVSEL_FB), // 1..5, 8, 10
.RXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
.TXPLL_DIVSEL_REF(1), // 1..6, 8, 10, 12, 16, 20
.RXPLL_DIVSEL_OUT(2), // 1, 2, 4
.TXPLL_DIVSEL_OUT(2), // 1, 2, 4
.RXPLL_DIVSEL45_FB(5),
.TXPLL_DIVSEL45_FB(5),
.RX_BUFFER_USE("TRUE"),
.RX_DECODE_SEQ_MATCH("TRUE"),
.RX_LOS_INVALID_INCR(8), // power of 2: 1..128
.RX_LOSS_OF_SYNC_FSM("FALSE"),
.RX_LOS_THRESHOLD(128), // power of 2: 4..512
.RX_SLIDE_MODE("OFF"), // 00=OFF 01=AUTO 10=PCS 11=PMA
.RX_XCLK_SEL ("RXREC"),
.TX_BUFFER_USE("FALSE"), // Must be set to FALSE for use by PCIE
.TX_XCLK_SEL ("TXUSR"), // Must be set to TXUSR for use by PCIE
.TXPLL_LKDET_CFG (3'b101),
.RX_EYE_SCANMODE (2'b00),
.RX_EYE_OFFSET (8'h4C),
.PMA_RX_CFG ( 25'h05ce049 ),
.TRANS_TIME_NON_P2(8'h2), // Reduced simulation time
.TRANS_TIME_FROM_P2(12'h03c), // Reduced simulation time
.TRANS_TIME_TO_P2(10'h064), // Reduced simulation time
.TRANS_TIME_RATE(8'hD7), // Reduced simulation time
.SHOW_REALIGN_COMMA("FALSE"),
.TX_PMADATA_OPT(1'b1), // Lockup latch between PCS and PMA
.PMA_TX_CFG( 20'h80082 ), // Aligns posedge of USRCLK
.TXOUTCLK_CTRL("TXPLLREFCLK_DIV1")
)
GTX (
.COMFINISH (),
.COMINITDET (),
.COMSASDET (),
.COMWAKEDET (),
.DADDR (daddr[(8*i)+7:(8*i)]),
.DCLK (DRPCLK),
.DEN (den[i]),
.DFECLKDLYADJ ( 6'h0 ),
.DFECLKDLYADJMON (),
.DFEDLYOVRD ( 1'b0 ),
.DFEEYEDACMON (),
.DFESENSCAL (),
.DFETAP1 (0),
.DFETAP1MONITOR (),
.DFETAP2 (5'h0),
.DFETAP2MONITOR (),
.DFETAP3 (4'h0),
.DFETAP3MONITOR (),
.DFETAP4 (4'h0),
.DFETAP4MONITOR (),
.DFETAPOVRD ( 1'b1 ),
.DI (din[(16*i)+15:(16*i)]),
.DRDY (drdy[i]),
.DRPDO (dout[(16*i)+15:(16*i)]),
.DWE (dwe[i]),
.GATERXELECIDLE ( 1'b0 ),
.GREFCLKRX (0),
.GREFCLKTX (0),
.GTXRXRESET ( ~GTReset_n ),
.GTXTEST ( {11'b10000000000,OUT_DIV_RESET[i],1'b0} ),
.GTXTXRESET ( ~GTReset_n ),
.LOOPBACK ( 3'b000 ),
.MGTREFCLKFAB (),
.MGTREFCLKRX ( {1'b0,REFCLK} ),
.MGTREFCLKTX ( {1'b0,REFCLK} ),
.NORTHREFCLKRX (0),
.NORTHREFCLKTX (0),
.PHYSTATUS ( GTX_PhyStatus[i] ),
.PLLRXRESET ( 1'b0 ),
.PLLTXRESET ( 1'b0 ),
.PRBSCNTRESET ( 1'b0 ),
.RXBUFRESET ( 1'b0 ),
.RXBUFSTATUS (),
.RXBYTEISALIGNED (),
.RXBYTEREALIGN (),
.RXCDRRESET ( 1'b0 ),
.RXCHANBONDSEQ (),
.RXCHANISALIGNED ( ChanIsAligned[i] ),
.RXCHANREALIGN (),
.RXCHARISCOMMA (),
.RXCHARISK ( {RxDataK_dummy[1:0], GTX_RxDataK[(2*i)+1:2*i]} ),
.RXCHBONDI ( RXCHBOND[i] ),
.RXCHBONDLEVEL ( GTX_RxChbondLevel[(3*i)+2:(3*i)] ),
.RXCHBONDMASTER ( (i == 0) ),
.RXCHBONDO ( RXCHBOND[i+1] ),
.RXCHBONDSLAVE ( (i > 0) ),
.RXCLKCORCNT (),
.RXCOMMADET (),
.RXCOMMADETUSE ( 1'b1 ),
.RXDATA ( {RxData_dummy[15:0],GTX_RxData[(16*i)+15:(16*i)+0]} ),
.RXDATAVALID (),
.RXDEC8B10BUSE ( RXDEC8B10BUSE ),
.RXDISPERR (),
.RXDLYALIGNDISABLE ( 1'b1),
.RXELECIDLE ( GTX_RxElecIdle[i] ),
.RXENCHANSYNC ( 1'b1 ),
.RXENMCOMMAALIGN ( 1'b1 ),
.RXENPCOMMAALIGN ( 1'b1 ),
.RXENPMAPHASEALIGN ( 1'b0 ),
.RXENPRBSTST ( 3'b0 ),
.RXENSAMPLEALIGN ( 1'b0 ),
.RXDLYALIGNMONENB ( 1'b1 ),
.RXEQMIX ( 10'b0110000011 ),
.RXGEARBOXSLIP ( 1'b0 ),
.RXHEADER (),
.RXHEADERVALID (),
.RXLOSSOFSYNC (),
.RXN ( GTX_RXN[i] ),
.RXNOTINTABLE (),
.RXOVERSAMPLEERR (),
.RXP ( GTX_RXP[i] ),
.RXPLLLKDET ( RxPLLLkDet[i] ),
.RXPLLLKDETEN ( 1'b1 ),
.RXPLLPOWERDOWN ( 1'b0 ),
.RXPLLREFSELDY ( 3'b000 ),
.RXPMASETPHASE ( 1'b0 ),
.RXPOLARITY ( GTX_RxPolarity[i] ),
.RXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
.RXPRBSERR (),
.RXRATE ( {1'b1, Rate} ),
.RXRATEDONE ( ),
.RXRECCLK ( RXRECCLK ),
.RXRECCLKPCS ( ),
.RXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
.RXRESETDONE ( GTX_RxResetDone[i] ),
.RXRUNDISP (),
.RXSLIDE ( 1'b0 ),
.RXSTARTOFSEQ (),
.RXSTATUS ( GTX_RxStatus[(3*i)+2:(3*i)] ),
.RXUSRCLK ( PCLK ),
.RXUSRCLK2 ( PCLK ),
.RXVALID (GTX_RxValid[i]),
.SOUTHREFCLKRX (0),
.SOUTHREFCLKTX (0),
.TSTCLK0 ( 1'b0 ),
.TSTCLK1 ( 1'b0 ),
.TSTIN ( {20{1'b1}} ),
.TSTOUT (),
.TXBUFDIFFCTRL ( 3'b111 ),
.TXBUFSTATUS (),
.TXBYPASS8B10B ( TXBYPASS8B10B[3:0] ),
.TXCHARDISPMODE ( {3'b000, GTX_TxCompliance[i]} ),
.TXCHARDISPVAL ( 4'b0000 ),
.TXCHARISK ( {TxDataK_dummy[1:0], GTX_TxDataK[(2*i)+1:2*i]} ),
.TXCOMINIT ( 1'b0 ),
.TXCOMSAS ( 1'b0 ),
.TXCOMWAKE ( 1'b0 ),
.TXDATA ( {TxData_dummy[15:0], GTX_TxData[(16*i)+15:(16*i)+0]} ),
.TXDEEMPH ( TxDeemph ),
.TXDETECTRX ( TxDetectRx ),
.TXDIFFCTRL ( 4'b1111 ),
.TXDLYALIGNDISABLE ( TXDLYALIGNDISABLE[i] ),
.TXDLYALIGNRESET ( TXDLYALIGNRESET[i] ),
.TXELECIDLE ( GTX_TxElecIdle[i] ),
.TXENC8B10BUSE ( 1'b1 ),
.TXENPMAPHASEALIGN ( TXENPMAPHASEALIGN[i] ),
.TXENPRBSTST (),
.TXGEARBOXREADY (),
.TXHEADER (0),
.TXINHIBIT ( 1'b0 ),
.TXKERR (),
.TXMARGIN ( {TxMargin, 2'b00} ),
.TXN ( GTX_TXN[i] ),
.TXOUTCLK ( TXOCLK[i] ),
.TXOUTCLKPCS (),
.TXP ( GTX_TXP[i] ),
.TXPDOWNASYNCH ( TXPdownAsynch ),
.TXPLLLKDET ( ),
.TXPLLLKDETEN ( 1'b0 ),
.TXPLLPOWERDOWN ( 1'b0 ),
.TXPLLREFSELDY ( 3'b000 ),
.TXPMASETPHASE ( TXPMASETPHASE[i] ),
.TXPOLARITY ( 1'b0 ),
.TXPOSTEMPHASIS (0),
.TXPOWERDOWN ( PowerDown[(2*i)+1:(2*i)] ),
.TXPRBSFORCEERR (0),
.TXPREEMPHASIS (0),
.TXRATE ( {1'b1, Rate} ),
.TXRESET ( ~GTReset_n | local_pcs_reset | PCS_RESET[i] ),
.TXRESETDONE ( TXRESETDONE[i] ),
.TXRUNDISP (),
.TXSEQUENCE (0),
.TXSTARTSEQ (0),
.TXSWING ( TxSwing ),
.TXUSRCLK ( PCLK ),
.TXUSRCLK2 ( PCLK ),
.USRCODEERR (0),
.IGNORESIGDET (0),
.PERFCLKRX (0),
.PERFCLKTX (0),
.RXDLYALIGNMONITOR (),
.RXDLYALIGNOVERRIDE ( 1'b0 ),
.RXDLYALIGNRESET (0),
.RXDLYALIGNSWPPRECURB ( 1'b1 ),
.RXDLYALIGNUPDSW ( 1'b0 ),
.TXDLYALIGNMONITOR (),
.TXDLYALIGNOVERRIDE ( 1'b0 ),
.TXDLYALIGNUPDSW ( 1'b0 ),
.TXDLYALIGNMONENB ( 1'b1 ),
.TXRATEDONE ( TXRATEDONE[i] )
);
end
end
endgenerate
endmodule |
module pcie_upconfig_fix_3451_v6 # (
parameter UPSTREAM_FACING = "TRUE",
parameter PL_FAST_TRAIN = "FALSE",
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter TCQ = 1
)
(
input pipe_clk,
input pl_phy_lnkup_n,
input [5:0] pl_ltssm_state,
input pl_sel_lnk_rate,
input [1:0] pl_directed_link_change,
input [3:0] cfg_link_status_negotiated_width,
input [15:0] pipe_rx0_data,
input [1:0] pipe_rx0_char_isk,
output filter_pipe
);
reg reg_filter_pipe;
reg [15:0] reg_tsx_counter;
wire [15:0] tsx_counter;
wire [5:0] cap_link_width;
// Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
// the core to see the TS1s on all the lanes being configured at the same time
// R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
// 225 pipe_clk cycles-sim_fast_train
// 60000 pipe_clk cycles-without sim_fast_train
// Not taking any action when PLDIRECTEDLINKCHANGE is set
// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
// data0 will be the first symbol on lane 0, data1 will be the next symbol.
// Don't look for PAD on data1 since it's unnecessary.
// COM=0xbc and PAD=0xf7 (and isk).
// detect if (data & 0xb4) == 0xb4 and isk, and then
// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
// no more than a 6-input LUT, so should be "free".
reg reg_filter_used, reg_com_then_pad;
reg reg_data0_b4, reg_data0_08, reg_data0_43;
reg reg_data1_b4, reg_data1_08, reg_data1_43;
reg reg_data0_com, reg_data1_com, reg_data1_pad;
wire data0_b4 = pipe_rx0_char_isk[0] &&
((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);
wire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);
wire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);
wire data1_b4 = pipe_rx0_char_isk[1] &&
((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);
wire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);
wire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);
wire data0_com = reg_data0_b4 && reg_data0_08;
wire data1_com = reg_data1_b4 && reg_data1_08;
wire data0_pad = reg_data0_b4 && reg_data0_43;
wire data1_pad = reg_data1_b4 && reg_data1_43;
wire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;
wire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;
wire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;
wire filter_used = (pl_ltssm_state == 6'h20) &&
(reg_filter_pipe || reg_filter_used);
always @(posedge pipe_clk) begin
reg_data0_b4 <= #TCQ data0_b4;
reg_data0_08 <= #TCQ data0_08;
reg_data0_43 <= #TCQ data0_43;
reg_data1_b4 <= #TCQ data1_b4;
reg_data1_08 <= #TCQ data1_08;
reg_data1_43 <= #TCQ data1_43;
reg_data0_com <= #TCQ data0_com;
reg_data1_com <= #TCQ data1_com;
reg_data1_pad <= #TCQ data1_pad;
reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;
reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;
end
always @ (posedge pipe_clk) begin
if (pl_phy_lnkup_n) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end else if ((pl_ltssm_state == 6'h20) &&
reg_com_then_pad &&
(cfg_link_status_negotiated_width != cap_link_width) &&
(pl_directed_link_change[1:0] == 2'b00)) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b1;
end else if (filter_pipe == 1'b1) begin
if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin
reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
reg_filter_pipe <= #TCQ 1'b1;
end else begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end
end
end
assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
assign tsx_counter = reg_tsx_counter;
assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
endmodule |
module tx_port_monitor_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "common_functions.v"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [4:0] rState=`S_TXPORTMON64_NEXT, _rState=`S_TXPORTMON64_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE2Lo=0, _rLenLE2Lo=0;
reg rTxErr=0, _rTxErr=0;
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON64_READ
assign TXN = rState[1]; // S_TXPORTMON64_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[2]; // !S_TXPORTMON64_READ
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[2]); // S_TXPORTMON64_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE2Lo)) & wPayloadData);
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON64_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON64_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_TXN;
end
`S_TXPORTMON64_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON64_END_0 : `S_TXPORTMON64_READ);
end
`S_TXPORTMON64_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON64_END_0;
end
`S_TXPORTMON64_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_END_1;
end
`S_TXPORTMON64_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON64_NEXT;
end
default: begin
_rState = `S_TXPORTMON64_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE2Lo <= #1 _rLenLE2Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[1] & !wEventData & !rAlmostFull); // !S_TXPORTMON64_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[C_DATA_WIDTH-1:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 2, we want to trigger the almost all received flag
_rLenLE2Lo = (LEN[15:0] <= 16'd2);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<1));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<1));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
endmodule |
module tx_port_channel_gate_128 #(
parameter C_DATA_WIDTH = 9'd128,
// Local parameters
parameter C_FIFO_DEPTH = 8,
parameter C_FIFO_DATA_WIDTH = C_DATA_WIDTH+1
)
(
input RST,
input RD_CLK, // FIFO read clock
output [C_FIFO_DATA_WIDTH-1:0] RD_DATA, // FIFO read data
output RD_EMPTY, // FIFO is empty
input RD_EN, // FIFO read enable
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rState=`S_TXPORTGATE128_IDLE, _rState=`S_TXPORTGATE128_IDLE;
reg rFifoWen=0, _rFifoWen=0;
reg [C_FIFO_DATA_WIDTH-1:0] rFifoData=0, _rFifoData=0;
wire wFifoFull;
reg rChnlTx=0, _rChnlTx=0;
reg rChnlLast=0, _rChnlLast=0;
reg [31:0] rChnlLen=0, _rChnlLen=0;
reg [30:0] rChnlOff=0, _rChnlOff=0;
reg rAck=0, _rAck=0;
reg rPause=0, _rPause=0;
reg rClosed=0, _rClosed=0;
assign CHNL_TX_ACK = rAck;
assign CHNL_TX_DATA_REN = (rState[1] & !rState[0] & !wFifoFull); // S_TXPORTGATE128_OPEN
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CHNL_CLK) begin
rChnlTx <= #1 (RST ? 1'd0 : _rChnlTx);
rChnlLast <= #1 _rChnlLast;
rChnlLen <= #1 _rChnlLen;
rChnlOff <= #1 _rChnlOff;
end
always @ (*) begin
_rChnlTx = CHNL_TX;
_rChnlLast = CHNL_TX_LAST;
_rChnlLen = CHNL_TX_LEN;
_rChnlOff = CHNL_TX_OFF;
end
// FIFO for temporarily storing data from the channel.
(* RAM_STYLE="DISTRIBUTED" *)
async_fifo #(.C_WIDTH(C_FIFO_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.WR_CLK(CHNL_CLK),
.WR_RST(RST),
.WR_EN(rFifoWen),
.WR_DATA(rFifoData),
.WR_FULL(wFifoFull),
.RD_CLK(RD_CLK),
.RD_RST(RST),
.RD_EN(RD_EN),
.RD_DATA(RD_DATA),
.RD_EMPTY(RD_EMPTY)
);
// Pass the transaction open event, transaction data, and the transaction
// close event through to the RD_CLK domain via the async_fifo.
always @ (posedge CHNL_CLK) begin
rState <= #1 (RST ? `S_TXPORTGATE128_IDLE : _rState);
rFifoWen <= #1 (RST ? 1'd0 : _rFifoWen);
rFifoData <= #1 _rFifoData;
rAck <= #1 (RST ? 1'd0 : _rAck);
rPause <= #1 (RST ? 1'd0 : _rPause);
rClosed <= #1 (RST ? 1'd0 : _rClosed);
end
always @ (*) begin
_rState = rState;
_rFifoWen = rFifoWen;
_rFifoData = rFifoData;
_rPause = rPause;
_rAck = rAck;
_rClosed = rClosed;
case (rState)
`S_TXPORTGATE128_IDLE: begin // Write the len, off, last
_rPause = 0;
_rClosed = 0;
if (!wFifoFull) begin
_rAck = rChnlTx;
_rFifoWen = rChnlTx;
_rFifoData = {1'd1, 64'd0, rChnlLen, rChnlOff, rChnlLast};
if (rChnlTx)
_rState = `S_TXPORTGATE128_OPENING;
end
end
`S_TXPORTGATE128_OPENING: begin // Write the len, off, last (again)
_rAck = 0;
_rClosed = (rClosed | !rChnlTx);
if (!wFifoFull) begin
if (rClosed | !rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
else
_rState = `S_TXPORTGATE128_OPEN;
end
end
`S_TXPORTGATE128_OPEN: begin // Copy channel data into the FIFO
if (!wFifoFull) begin
_rFifoWen = CHNL_TX_DATA_VALID; // CHNL_TX_DATA_VALID & CHNL_TX_DATA should really be buffered
_rFifoData = {1'd0, CHNL_TX_DATA}; // but the VALID+REN model seem to make this difficult.
end
if (!rChnlTx)
_rState = `S_TXPORTGATE128_CLOSED;
end
`S_TXPORTGATE128_CLOSED: begin // Write the end marker (twice)
if (!wFifoFull) begin
_rPause = 1;
_rFifoWen = 1;
_rFifoData = {1'd1, {C_DATA_WIDTH{1'd0}}};
if (rPause)
_rState = `S_TXPORTGATE128_IDLE;
end
end
endcase
end
endmodule |
module tx_engine_32 #(
parameter C_PCI_DATA_WIDTH = 9'd32,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_ALTERA = 1'b1, // 1 if Altera, 0 if Xilinx
// Local parameters
parameter C_FIFO_DEPTH = 512,
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output [C_PCI_DATA_WIDTH-1:0] TX_DATA, // AXI data output
output [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE, // AXI data keep
output TX_TLP_END_FLAG, // AXI data last
output TX_TLP_START_FLAG, // AXI data first
output TX_DATA_VALID, // AXI data valid
output S_AXIS_SRC_DSC, // AXI data discontinue
input TX_DATA_READY, // AXI ready for data
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*64)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*10)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
output [C_NUM_CHNL-1:0] WR_SENT, // Pulsed at channel pos when write request sent
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*64)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*10)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
input COMPL_REQ, // RX Engine request for completion
output COMPL_DONE, // Completion done
input [2:0] REQ_TC,
input REQ_TD,
input REQ_EP,
input [1:0] REQ_ATTR,
input [9:0] REQ_LEN,
input [15:0] REQ_ID,
input [7:0] REQ_TAG,
input [3:0] REQ_BE,
input [29:0] REQ_ADDR,
input [31:0] REQ_DATA,
output [31:0] REQ_DATA_SENT // Actual completion data sent
);
`include "common_functions.v"
wire [C_PCI_DATA_WIDTH-1:0] wFifoWrData;
wire [C_PCI_DATA_WIDTH-1:0] wFifoRdData;
wire [C_FIFO_DEPTH_WIDTH-1:0] wFifoCount;
wire wFifoEmpty;
wire wFifoRen;
wire wFifoWen;
wire wAltera = C_ALTERA;
// Convert the read and write requests into PCI packet format and mux
// them together into a FIFO.
tx_engine_upper_32 #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .C_NUM_CHNL(C_NUM_CHNL), .C_FIFO_DEPTH(C_FIFO_DEPTH), .C_TAG_WIDTH(C_TAG_WIDTH)) upper (
.RST(RST),
.CLK(CLK),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.WR_REQ(WR_REQ),
.WR_ADDR(WR_ADDR),
.WR_LEN(WR_LEN),
.WR_DATA(WR_DATA),
.WR_DATA_REN(WR_DATA_REN),
.WR_ACK(WR_ACK),
.RD_REQ(RD_REQ),
.RD_SG_CHNL(RD_SG_CHNL),
.RD_ADDR(RD_ADDR),
.RD_LEN(RD_LEN),
.RD_ACK(RD_ACK),
.TX_ENG_RD_REQ_SENT(TX_ENG_RD_REQ_SENT),
.RXBUF_SPACE_AVAIL(RXBUF_SPACE_AVAIL | !wAltera),
.INT_TAG(INT_TAG),
.INT_TAG_VALID(INT_TAG_VALID),
.EXT_TAG(EXT_TAG),
.EXT_TAG_VALID(EXT_TAG_VALID),
.FIFO_DATA(wFifoWrData),
.FIFO_COUNT(wFifoCount),
.FIFO_WEN(wFifoWen)
);
// FIFO for storing outbound read/write requests.
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_PCI_DATA_WIDTH), .C_DEPTH(C_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) fifo (
.RST(RST),
.CLK(CLK),
.WR_EN(wFifoWen),
.WR_DATA(wFifoWrData),
.FULL(),
.COUNT(wFifoCount),
.RD_EN(wFifoRen),
.RD_DATA(wFifoRdData),
.EMPTY(wFifoEmpty)
);
// Process the formatted PCI packets in the FIFO and completions.
// Completions take top priority. Mux the data into the AXI interface
// for the PCIe Endpoint.
tx_engine_lower_32 #(.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH), .C_NUM_CHNL(C_NUM_CHNL)) lower (
.RST(RST),
.CLK(CLK),
.CONFIG_COMPLETER_ID(CONFIG_COMPLETER_ID),
.TX_DATA(TX_DATA),
.TX_DATA_BYTE_ENABLE(TX_DATA_BYTE_ENABLE),
.TX_TLP_END_FLAG(TX_TLP_END_FLAG),
.TX_TLP_START_FLAG(TX_TLP_START_FLAG),
.TX_DATA_VALID(TX_DATA_VALID),
.S_AXIS_SRC_DSC(S_AXIS_SRC_DSC),
.TX_DATA_READY(TX_DATA_READY),
.COMPL_REQ(COMPL_REQ),
.COMPL_DONE(COMPL_DONE),
.REQ_TC(REQ_TC),
.REQ_TD(REQ_TD),
.REQ_EP(REQ_EP),
.REQ_ATTR(REQ_ATTR),
.REQ_LEN(REQ_LEN),
.REQ_ID(REQ_ID),
.REQ_TAG(REQ_TAG),
.REQ_BE(REQ_BE),
.REQ_ADDR(REQ_ADDR),
.REQ_DATA(REQ_DATA),
.REQ_DATA_SENT(REQ_DATA_SENT),
.FIFO_DATA(wFifoRdData),
.FIFO_EMPTY(wFifoEmpty),
.FIFO_REN(wFifoRen),
.WR_SENT(WR_SENT)
);
endmodule |
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule |
module channel_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_RX_FIFO_DEPTH = 1024,
parameter C_TX_FIFO_DEPTH = 512,
parameter C_SG_FIFO_DEPTH = 1024,
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
input [31:0] PIO_DATA, // Single word programmed I/O data
input [C_DATA_WIDTH-1:0] ENG_DATA, // Main incoming data
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
input TXN_RX_LEN_VALID, // Read transaction length valid
input TXN_RX_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_RX_DONE_LEN, // Read transaction actual transfer length
output TXN_RX_DONE, // Read transaction done
input TXN_RX_DONE_ACK, // Read transaction actual transfer length read
output TXN_TX, // Write transaction notification
input TXN_TX_ACK, // Write transaction acknowledged
output [31:0] TXN_TX_LEN, // Write transaction length
output [31:0] TXN_TX_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_TX_DONE_LEN, // Write transaction actual transfer length
output TXN_TX_DONE, // Write transaction done
input TXN_TX_DONE_ACK, // Write transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_RX_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN, // Channel read data has been recieved
input CHNL_TX_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "common_functions.v"
wire [C_DATA_WIDTH-1:0] wTxSgData;
wire wTxSgDataEmpty;
wire wTxSgDataRen;
wire wTxSgDataErr;
wire wTxSgDataRst;
// Receiving port (data to the channel)
rx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_MAIN_FIFO_DEPTH(C_RX_FIFO_DEPTH),
.C_SG_FIFO_DEPTH(C_SG_FIFO_DEPTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
) rxPort (
.RST(RST),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.SG_RX_BUF_RECVD(SG_RX_BUF_RECVD),
.SG_RX_BUF_DATA(PIO_DATA),
.SG_RX_BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.SG_RX_BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.SG_RX_BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.SG_TX_BUF_RECVD(SG_TX_BUF_RECVD),
.SG_TX_BUF_DATA(PIO_DATA),
.SG_TX_BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.SG_TX_BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.SG_TX_BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TXN_DATA(PIO_DATA),
.TXN_LEN_VALID(TXN_RX_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_RX_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_RX_DONE_LEN),
.TXN_DONE(TXN_RX_DONE),
.TXN_DONE_ACK(TXN_RX_DONE_ACK),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.MAIN_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA(ENG_DATA),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA(ENG_DATA),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR),
.CHNL_CLK(CHNL_RX_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
// Sending port (data from the channel)
tx_port_64 #(
.C_DATA_WIDTH(C_DATA_WIDTH),
.C_FIFO_DEPTH(C_TX_FIFO_DEPTH)
) txPort (
.CLK(CLK),
.RST(RST),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN_TX),
.TXN_ACK(TXN_TX_ACK),
.TXN_LEN(TXN_TX_LEN),
.TXN_OFF_LAST(TXN_TX_OFF_LAST),
.TXN_DONE_LEN(TXN_TX_DONE_LEN),
.TXN_DONE(TXN_TX_DONE),
.TXN_DONE_ACK(TXN_TX_DONE_ACK),
.SG_DATA(wTxSgData),
.SG_DATA_EMPTY(wTxSgDataEmpty),
.SG_DATA_REN(wTxSgDataRen),
.SG_RST(wTxSgDataRst),
.SG_ERR(wTxSgDataErr),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_DATA(TX_DATA),
.TX_DATA_REN(TX_DATA_REN),
.TX_SENT(TX_SENT),
.CHNL_CLK(CHNL_TX_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
endmodule |
module pcie_gtx_v6 #
(
parameter TCQ = 1, // clock to out delay model
parameter NO_OF_LANES = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
parameter LINK_CAP_MAX_LINK_SPEED = 4'h1, // 1 - Gen1, 2 - Gen2
parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
parameter PL_FAST_TRAIN = "FALSE"
)
(
// Pipe Per-Link Signals
input wire pipe_tx_rcvr_det ,
input wire pipe_tx_reset ,
input wire pipe_tx_rate ,
input wire pipe_tx_deemph ,
input wire [2:0] pipe_tx_margin ,
input wire pipe_tx_swing ,
// Pipe Per-Lane Signals - Lane 0
output wire [ 1:0] pipe_rx0_char_is_k ,
output wire [15:0] pipe_rx0_data ,
output wire pipe_rx0_valid ,
output wire pipe_rx0_chanisaligned ,
output wire [ 2:0] pipe_rx0_status ,
output wire pipe_rx0_phy_status ,
output wire pipe_rx0_elec_idle ,
input wire pipe_rx0_polarity ,
input wire pipe_tx0_compliance ,
input wire [ 1:0] pipe_tx0_char_is_k ,
input wire [15:0] pipe_tx0_data ,
input wire pipe_tx0_elec_idle ,
input wire [ 1:0] pipe_tx0_powerdown ,
// Pipe Per-Lane Signals - Lane 1
output wire [ 1:0] pipe_rx1_char_is_k ,
output wire [15:0] pipe_rx1_data ,
output wire pipe_rx1_valid ,
output wire pipe_rx1_chanisaligned ,
output wire [ 2:0] pipe_rx1_status ,
output wire pipe_rx1_phy_status ,
output wire pipe_rx1_elec_idle ,
input wire pipe_rx1_polarity ,
input wire pipe_tx1_compliance ,
input wire [ 1:0] pipe_tx1_char_is_k ,
input wire [15:0] pipe_tx1_data ,
input wire pipe_tx1_elec_idle ,
input wire [ 1:0] pipe_tx1_powerdown ,
// Pipe Per-Lane Signals - Lane 2
output wire [ 1:0] pipe_rx2_char_is_k ,
output wire [15:0] pipe_rx2_data ,
output wire pipe_rx2_valid ,
output wire pipe_rx2_chanisaligned ,
output wire [ 2:0] pipe_rx2_status ,
output wire pipe_rx2_phy_status ,
output wire pipe_rx2_elec_idle ,
input wire pipe_rx2_polarity ,
input wire pipe_tx2_compliance ,
input wire [ 1:0] pipe_tx2_char_is_k ,
input wire [15:0] pipe_tx2_data ,
input wire pipe_tx2_elec_idle ,
input wire [ 1:0] pipe_tx2_powerdown ,
// Pipe Per-Lane Signals - Lane 3
output wire [ 1:0] pipe_rx3_char_is_k ,
output wire [15:0] pipe_rx3_data ,
output wire pipe_rx3_valid ,
output wire pipe_rx3_chanisaligned ,
output wire [ 2:0] pipe_rx3_status ,
output wire pipe_rx3_phy_status ,
output wire pipe_rx3_elec_idle ,
input wire pipe_rx3_polarity ,
input wire pipe_tx3_compliance ,
input wire [ 1:0] pipe_tx3_char_is_k ,
input wire [15:0] pipe_tx3_data ,
input wire pipe_tx3_elec_idle ,
input wire [ 1:0] pipe_tx3_powerdown ,
// Pipe Per-Lane Signals - Lane 4
output wire [ 1:0] pipe_rx4_char_is_k ,
output wire [15:0] pipe_rx4_data ,
output wire pipe_rx4_valid ,
output wire pipe_rx4_chanisaligned ,
output wire [ 2:0] pipe_rx4_status ,
output wire pipe_rx4_phy_status ,
output wire pipe_rx4_elec_idle ,
input wire pipe_rx4_polarity ,
input wire pipe_tx4_compliance ,
input wire [ 1:0] pipe_tx4_char_is_k ,
input wire [15:0] pipe_tx4_data ,
input wire pipe_tx4_elec_idle ,
input wire [ 1:0] pipe_tx4_powerdown ,
// Pipe Per-Lane Signals - Lane 5
output wire [ 1:0] pipe_rx5_char_is_k ,
output wire [15:0] pipe_rx5_data ,
output wire pipe_rx5_valid ,
output wire pipe_rx5_chanisaligned ,
output wire [ 2:0] pipe_rx5_status ,
output wire pipe_rx5_phy_status ,
output wire pipe_rx5_elec_idle ,
input wire pipe_rx5_polarity ,
input wire pipe_tx5_compliance ,
input wire [ 1:0] pipe_tx5_char_is_k ,
input wire [15:0] pipe_tx5_data ,
input wire pipe_tx5_elec_idle ,
input wire [ 1:0] pipe_tx5_powerdown ,
// Pipe Per-Lane Signals - Lane 6
output wire [ 1:0] pipe_rx6_char_is_k ,
output wire [15:0] pipe_rx6_data ,
output wire pipe_rx6_valid ,
output wire pipe_rx6_chanisaligned ,
output wire [ 2:0] pipe_rx6_status ,
output wire pipe_rx6_phy_status ,
output wire pipe_rx6_elec_idle ,
input wire pipe_rx6_polarity ,
input wire pipe_tx6_compliance ,
input wire [ 1:0] pipe_tx6_char_is_k ,
input wire [15:0] pipe_tx6_data ,
input wire pipe_tx6_elec_idle ,
input wire [ 1:0] pipe_tx6_powerdown ,
// Pipe Per-Lane Signals - Lane 7
output wire [ 1:0] pipe_rx7_char_is_k ,
output wire [15:0] pipe_rx7_data ,
output wire pipe_rx7_valid ,
output wire pipe_rx7_chanisaligned ,
output wire [ 2:0] pipe_rx7_status ,
output wire pipe_rx7_phy_status ,
output wire pipe_rx7_elec_idle ,
input wire pipe_rx7_polarity ,
input wire pipe_tx7_compliance ,
input wire [ 1:0] pipe_tx7_char_is_k ,
input wire [15:0] pipe_tx7_data ,
input wire pipe_tx7_elec_idle ,
input wire [ 1:0] pipe_tx7_powerdown ,
// PCI Express signals
output wire [ (NO_OF_LANES-1):0] pci_exp_txn ,
output wire [ (NO_OF_LANES-1):0] pci_exp_txp ,
input wire [ (NO_OF_LANES-1):0] pci_exp_rxn ,
input wire [ (NO_OF_LANES-1):0] pci_exp_rxp ,
// Non PIPE signals
input wire sys_clk ,
input wire sys_rst_n ,
input wire pipe_clk ,
input wire drp_clk ,
input wire clock_locked ,
output wire gt_pll_lock ,
input wire [ 5:0] pl_ltssm_state ,
output reg phy_rdy_n ,
output wire TxOutClk
);
wire [ 7:0] gt_rx_phy_status_wire ;
wire [ 7:0] gt_rxchanisaligned_wire ;
wire [127:0] gt_rx_data_k_wire ;
wire [127:0] gt_rx_data_wire ;
wire [ 7:0] gt_rx_elec_idle_wire ;
wire [ 23:0] gt_rx_status_wire ;
wire [ 7:0] gt_rx_valid_wire ;
wire [ 7:0] gt_rx_polarity ;
wire [ 15:0] gt_power_down ;
wire [ 7:0] gt_tx_char_disp_mode ;
wire [ 15:0] gt_tx_data_k ;
wire [127:0] gt_tx_data ;
wire gt_tx_detect_rx_loopback ;
wire [ 7:0] gt_tx_elec_idle ;
wire [ 7:0] gt_rx_elec_idle_reset ;
wire [NO_OF_LANES-1:0] plllkdet;
wire RxResetDone;
reg local_pcs_reset;
reg local_pcs_reset_done;
reg [3:0] cnt_local_pcs_reset;
reg [4:0] phy_rdy_pre_cnt;
reg [5:0] pl_ltssm_state_q;
wire plm_in_l0 = (pl_ltssm_state_q == 6'h16);
wire plm_in_rl = (pl_ltssm_state_q == 6'h1c);
wire plm_in_dt = (pl_ltssm_state_q == 6'h2d);
wire plm_in_rs = (pl_ltssm_state_q == 6'h1f);
gtx_wrapper_v6 #(
.NO_OF_LANES(NO_OF_LANES),
.REF_CLK_FREQ(REF_CLK_FREQ),
.PL_FAST_TRAIN(PL_FAST_TRAIN)
)
gtx_v6_i (
// TX
.TX(pci_exp_txp[((NO_OF_LANES)-1):0]),
.TX_(pci_exp_txn[((NO_OF_LANES)-1):0]),
.TxData(gt_tx_data[((16*NO_OF_LANES)-1):0]),
.TxDataK(gt_tx_data_k[((2*NO_OF_LANES)-1):0]),
.TxElecIdle(gt_tx_elec_idle[((NO_OF_LANES)-1):0]),
.TxCompliance(gt_tx_char_disp_mode[((NO_OF_LANES)-1):0]),
// RX
.RX(pci_exp_rxp[((NO_OF_LANES)-1):0]),
.RX_(pci_exp_rxn[((NO_OF_LANES)-1):0]),
.RxData(gt_rx_data_wire[((16*NO_OF_LANES)-1):0]),
.RxDataK(gt_rx_data_k_wire[((2*NO_OF_LANES)-1):0]),
.RxPolarity(gt_rx_polarity[((NO_OF_LANES)-1):0]),
.RxValid(gt_rx_valid_wire[((NO_OF_LANES)-1):0]),
.RxElecIdle(gt_rx_elec_idle_wire[((NO_OF_LANES)-1):0]),
.RxStatus(gt_rx_status_wire[((3*NO_OF_LANES)-1):0]),
// other
.GTRefClkout(),
.plm_in_l0(plm_in_l0),
.plm_in_rl(plm_in_rl),
.plm_in_dt(plm_in_dt),
.plm_in_rs(plm_in_rs),
.RxPLLLkDet(plllkdet),
.ChanIsAligned(gt_rxchanisaligned_wire[((NO_OF_LANES)-1):0]),
.TxDetectRx(gt_tx_detect_rx_loopback),
.PhyStatus(gt_rx_phy_status_wire[((NO_OF_LANES)-1):0]),
.TXPdownAsynch(~clock_locked),
.PowerDown(gt_power_down[((2*NO_OF_LANES)-1):0]),
.Rate(pipe_tx_rate),
.Reset_n(clock_locked),
.GTReset_n(sys_rst_n),
.PCLK(pipe_clk),
.REFCLK(sys_clk),
.DRPCLK(drp_clk),
.TxDeemph(pipe_tx_deemph),
.TxMargin(pipe_tx_margin[2]),
.TxSwing(pipe_tx_swing),
.local_pcs_reset(local_pcs_reset),
.RxResetDone(RxResetDone),
.SyncDone(SyncDone),
.TxOutClk(TxOutClk)
);
assign pipe_rx0_phy_status = gt_rx_phy_status_wire[0] ;
assign pipe_rx1_phy_status = (NO_OF_LANES >= 2 ) ? gt_rx_phy_status_wire[1] : 1'b0;
assign pipe_rx2_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[2] : 1'b0;
assign pipe_rx3_phy_status = (NO_OF_LANES >= 4 ) ? gt_rx_phy_status_wire[3] : 1'b0;
assign pipe_rx4_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[4] : 1'b0;
assign pipe_rx5_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[5] : 1'b0;
assign pipe_rx6_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[6] : 1'b0;
assign pipe_rx7_phy_status = (NO_OF_LANES >= 8 ) ? gt_rx_phy_status_wire[7] : 1'b0;
assign pipe_rx0_chanisaligned = gt_rxchanisaligned_wire[0];
assign pipe_rx1_chanisaligned = (NO_OF_LANES >= 2 ) ? gt_rxchanisaligned_wire[1] : 1'b0 ;
assign pipe_rx2_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[2] : 1'b0 ;
assign pipe_rx3_chanisaligned = (NO_OF_LANES >= 4 ) ? gt_rxchanisaligned_wire[3] : 1'b0 ;
assign pipe_rx4_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[4] : 1'b0 ;
assign pipe_rx5_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[5] : 1'b0 ;
assign pipe_rx6_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[6] : 1'b0 ;
assign pipe_rx7_chanisaligned = (NO_OF_LANES >= 8 ) ? gt_rxchanisaligned_wire[7] : 1'b0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_char_is_k = {gt_rx_data_k_wire[1], gt_rx_data_k_wire[0]};
assign pipe_rx1_char_is_k = (NO_OF_LANES >= 2 ) ? {gt_rx_data_k_wire[3], gt_rx_data_k_wire[2]} : 2'b0 ;
assign pipe_rx2_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[5], gt_rx_data_k_wire[4]} : 2'b0 ;
assign pipe_rx3_char_is_k = (NO_OF_LANES >= 4 ) ? {gt_rx_data_k_wire[7], gt_rx_data_k_wire[6]} : 2'b0 ;
assign pipe_rx4_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[9], gt_rx_data_k_wire[8]} : 2'b0 ;
assign pipe_rx5_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[11], gt_rx_data_k_wire[10]} : 2'b0 ;
assign pipe_rx6_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[13], gt_rx_data_k_wire[12]} : 2'b0 ;
assign pipe_rx7_char_is_k = (NO_OF_LANES >= 8 ) ? {gt_rx_data_k_wire[15], gt_rx_data_k_wire[14]} : 2'b0 ;
assign pipe_rx0_data = {gt_rx_data_wire[ 15: 8], gt_rx_data_wire[ 7: 0]};
assign pipe_rx1_data = (NO_OF_LANES >= 2 ) ? {gt_rx_data_wire[31:24], gt_rx_data_wire[23:16]} : 16'h0 ;
assign pipe_rx2_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[47:40], gt_rx_data_wire[39:32]} : 16'h0 ;
assign pipe_rx3_data = (NO_OF_LANES >= 4 ) ? {gt_rx_data_wire[63:56], gt_rx_data_wire[55:48]} : 16'h0 ;
assign pipe_rx4_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[79:72], gt_rx_data_wire[71:64]} : 16'h0 ;
assign pipe_rx5_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[95:88], gt_rx_data_wire[87:80]} : 16'h0 ;
assign pipe_rx6_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[111:104], gt_rx_data_wire[103:96]} : 16'h0 ;
assign pipe_rx7_data = (NO_OF_LANES >= 8 ) ? {gt_rx_data_wire[127:120], gt_rx_data_wire[119:112]} : 16'h0 ;
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
assign pipe_rx0_elec_idle = gt_rx_elec_idle_wire[0];
assign pipe_rx1_elec_idle = (NO_OF_LANES >= 2 ) ? gt_rx_elec_idle_wire[1] : 1'b1 ;
assign pipe_rx2_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[2] : 1'b1 ;
assign pipe_rx3_elec_idle = (NO_OF_LANES >= 4 ) ? gt_rx_elec_idle_wire[3] : 1'b1 ;
assign pipe_rx4_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[4] : 1'b1 ;
assign pipe_rx5_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[5] : 1'b1 ;
assign pipe_rx6_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[6] : 1'b1 ;
assign pipe_rx7_elec_idle = (NO_OF_LANES >= 8 ) ? gt_rx_elec_idle_wire[7] : 1'b1 ;
assign pipe_rx0_status = gt_rx_status_wire[ 2: 0];
assign pipe_rx1_status = (NO_OF_LANES >= 2 ) ? gt_rx_status_wire[ 5: 3] : 3'b0 ;
assign pipe_rx2_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[ 8: 6] : 3'b0 ;
assign pipe_rx3_status = (NO_OF_LANES >= 4 ) ? gt_rx_status_wire[11: 9] : 3'b0 ;
assign pipe_rx4_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[14:12] : 3'b0 ;
assign pipe_rx5_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[17:15] : 3'b0 ;
assign pipe_rx6_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[20:18] : 3'b0 ;
assign pipe_rx7_status = (NO_OF_LANES >= 8 ) ? gt_rx_status_wire[23:21] : 3'b0 ;
assign pipe_rx0_valid = gt_rx_valid_wire[0];
assign pipe_rx1_valid = (NO_OF_LANES >= 2 ) ? gt_rx_valid_wire[1] : 1'b0 ;
assign pipe_rx2_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[2] : 1'b0 ;
assign pipe_rx3_valid = (NO_OF_LANES >= 4 ) ? gt_rx_valid_wire[3] : 1'b0 ;
assign pipe_rx4_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[4] : 1'b0 ;
assign pipe_rx5_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[5] : 1'b0 ;
assign pipe_rx6_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[6] : 1'b0 ;
assign pipe_rx7_valid = (NO_OF_LANES >= 8 ) ? gt_rx_valid_wire[7] : 1'b0 ;
assign gt_rx_polarity[0] = pipe_rx0_polarity;
assign gt_rx_polarity[1] = pipe_rx1_polarity;
assign gt_rx_polarity[2] = pipe_rx2_polarity;
assign gt_rx_polarity[3] = pipe_rx3_polarity;
assign gt_rx_polarity[4] = pipe_rx4_polarity;
assign gt_rx_polarity[5] = pipe_rx5_polarity;
assign gt_rx_polarity[6] = pipe_rx6_polarity;
assign gt_rx_polarity[7] = pipe_rx7_polarity;
assign gt_power_down[ 1: 0] = pipe_tx0_powerdown;
assign gt_power_down[ 3: 2] = pipe_tx1_powerdown;
assign gt_power_down[ 5: 4] = pipe_tx2_powerdown;
assign gt_power_down[ 7: 6] = pipe_tx3_powerdown;
assign gt_power_down[ 9: 8] = pipe_tx4_powerdown;
assign gt_power_down[11:10] = pipe_tx5_powerdown;
assign gt_power_down[13:12] = pipe_tx6_powerdown;
assign gt_power_down[15:14] = pipe_tx7_powerdown;
assign gt_tx_char_disp_mode = {pipe_tx7_compliance,
pipe_tx6_compliance,
pipe_tx5_compliance,
pipe_tx4_compliance,
pipe_tx3_compliance,
pipe_tx2_compliance,
pipe_tx1_compliance,
pipe_tx0_compliance};
assign gt_tx_data_k = {pipe_tx7_char_is_k,
pipe_tx6_char_is_k,
pipe_tx5_char_is_k,
pipe_tx4_char_is_k,
pipe_tx3_char_is_k,
pipe_tx2_char_is_k,
pipe_tx1_char_is_k,
pipe_tx0_char_is_k};
assign gt_tx_data = {pipe_tx7_data,
pipe_tx6_data,
pipe_tx5_data,
pipe_tx4_data,
pipe_tx3_data,
pipe_tx2_data,
pipe_tx1_data,
pipe_tx0_data};
assign gt_tx_detect_rx_loopback = pipe_tx_rcvr_det;
assign gt_tx_elec_idle = {pipe_tx7_elec_idle,
pipe_tx6_elec_idle,
pipe_tx5_elec_idle,
pipe_tx4_elec_idle,
pipe_tx3_elec_idle,
pipe_tx2_elec_idle,
pipe_tx1_elec_idle,
pipe_tx0_elec_idle};
assign gt_pll_lock = &plllkdet[NO_OF_LANES-1:0] | ~phy_rdy_pre_cnt[4];
// Asserted after all workarounds have completed.
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
phy_rdy_n <= #TCQ 1'b1;
end else begin
if (~&plllkdet[NO_OF_LANES-1:0])
phy_rdy_n <= #TCQ 1'b1;
else if (local_pcs_reset_done && RxResetDone && phy_rdy_n && SyncDone)
phy_rdy_n <= #TCQ 1'b0;
end
end
// Handle the warm reset case, where sys_rst_n is asseted when
// phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
// before gt_pll_lock is de-asserted so that synnchronous
// logic see reset de-asset before clock is lost.
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
phy_rdy_pre_cnt <= #TCQ 5'b11111;
end else begin
if (gt_pll_lock && phy_rdy_n)
phy_rdy_pre_cnt <= #TCQ phy_rdy_pre_cnt + 1'b1;
end
end
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked) begin
cnt_local_pcs_reset <= #TCQ 4'hF;
local_pcs_reset <= #TCQ 1'b0;
local_pcs_reset_done <= #TCQ 1'b0;
end else begin
if ((local_pcs_reset == 1'b0) && (cnt_local_pcs_reset == 4'hF))
local_pcs_reset <= #TCQ 1'b1;
else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset != 4'h0)) begin
local_pcs_reset <= #TCQ 1'b1;
cnt_local_pcs_reset <= #TCQ cnt_local_pcs_reset - 1'b1;
end else if ((local_pcs_reset == 1'b1) && (cnt_local_pcs_reset == 4'h0)) begin
local_pcs_reset <= #TCQ 1'b0;
local_pcs_reset_done <= #TCQ 1'b1;
end
end
end
always @(posedge pipe_clk or negedge clock_locked) begin
if (!clock_locked)
pl_ltssm_state_q <= #TCQ 6'b0;
else
pl_ltssm_state_q <= #TCQ pl_ltssm_state;
end
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
endmodule |
module riffa_top_v6_pcie_v2_5 # (
parameter PL_FAST_TRAIN = "FALSE",
parameter C_DATA_WIDTH = 32, // RX/TX interface data width
parameter DQ_WIDTH = 64,
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
)
(
output [7:0] pci_exp_txp,
output [7:0] pci_exp_txn,
input [7:0] pci_exp_rxp,
input [7:0] pci_exp_rxn,
`ifdef ENABLE_LEDS
output led_0,
output led_1,
output led_2,
`endif
input sys_clk_p,
input sys_clk_n,
input sys_reset_n,
input app_clk,
output app_en,
input app_ack,
output[31:0] app_instr,
//Data read back Interface
input rdback_fifo_empty,
output rdback_fifo_rden,
input[DQ_WIDTH*4 - 1:0] rdback_data
);
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
wire [5:0] tx_buf_av;
wire tx_cfg_req;
wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
// Flow Control
wire [11:0] fc_cpld;
wire [7:0] fc_cplh;
wire [11:0] fc_npd;
wire [7:0] fc_nph;
wire [11:0] fc_pd;
wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire [31:0] cfg_do;
wire cfg_rd_wr_done;
wire [31:0] cfg_di;
wire [3:0] cfg_byte_en;
wire [9:0] cfg_dwaddr;
wire cfg_wr_en;
wire cfg_rd_en;
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire [63:0] cfg_dsn;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_capable;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_capable;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_link_rate;
wire [1:0] pl_sel_link_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_clk_c;
wire sys_reset_n_c;
//-------------------------------------------------------
IBUFDS_GTXE1 refclk_ibuf (.O(sys_clk_c), .ODIV2(), .I(sys_clk_p), .IB(sys_clk_n), .CEB(1'b0));
IBUF sys_reset_n_ibuf (.O(sys_reset_n_c), .I(sys_reset_n));
`ifdef ENABLE_LEDS
OBUF led_0_obuf (.O(led_0), .I(sys_reset_n_c));
OBUF led_1_obuf (.O(led_1), .I(user_reset));
OBUF led_2_obuf (.O(led_2), .I(!user_lnk_up));
`endif
FDCP #(
.INIT(1'b1)
) user_lnk_up_n_int_i (
.Q (user_lnk_up),
.D (user_lnk_up_int1),
.C (user_clk),
.CLR (1'b0),
.PRE (1'b0)
);
FDCP #(
.INIT(1'b1)
) user_reset_n_i (
.Q (user_reset),
.D (user_reset_int1),
.C (user_clk),
.CLR (1'b0),
.PRE (1'b0)
);
pcie_endpoint #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN )
) core (
//-------------------------------------------------------
// 1. PCI Express (pci_exp) Interface
//-------------------------------------------------------
// Tx
.pci_exp_txp( pci_exp_txp ),
.pci_exp_txn( pci_exp_txn ),
// Rx
.pci_exp_rxp( pci_exp_rxp ),
.pci_exp_rxn( pci_exp_rxn ),
//-------------------------------------------------------
// 2. AXI-S Interface
//-------------------------------------------------------
// Common
.user_clk_out( user_clk ),
.user_reset_out( user_reset_int1 ),
.user_lnk_up( user_lnk_up_int1 ),
// Tx
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.tx_cfg_gnt( tx_cfg_gnt ),
.tx_cfg_req( tx_cfg_req ),
.tx_buf_av( tx_buf_av ),
.tx_err_drop( tx_err_drop ),
// Rx
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok( rx_np_ok ),
// Flow Control
.fc_cpld( fc_cpld ),
.fc_cplh( fc_cplh ),
.fc_npd( fc_npd ),
.fc_nph( fc_nph ),
.fc_pd( fc_pd ),
.fc_ph( fc_ph ),
.fc_sel( fc_sel ),
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
.cfg_do( cfg_do ),
.cfg_rd_wr_done( cfg_rd_wr_done),
.cfg_di( cfg_di ),
.cfg_byte_en( cfg_byte_en ),
.cfg_dwaddr( cfg_dwaddr ),
.cfg_wr_en( cfg_wr_en ),
.cfg_rd_en( cfg_rd_en ),
.cfg_err_cor( cfg_err_cor ),
.cfg_err_ur( cfg_err_ur ),
.cfg_err_ecrc( cfg_err_ecrc ),
.cfg_err_cpl_timeout( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect( cfg_err_cpl_unexpect ),
.cfg_err_posted( cfg_err_posted ),
.cfg_err_locked( cfg_err_locked ),
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy( cfg_err_cpl_rdy ),
.cfg_interrupt( cfg_interrupt ),
.cfg_interrupt_rdy( cfg_interrupt_rdy ),
.cfg_interrupt_assert( cfg_interrupt_assert ),
.cfg_interrupt_di( cfg_interrupt_di ),
.cfg_interrupt_do( cfg_interrupt_do ),
.cfg_interrupt_mmenable( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm( cfg_interrupt_msixfm ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_trn_pending( cfg_trn_pending ),
.cfg_pm_wake( cfg_pm_wake ),
.cfg_bus_number( cfg_bus_number ),
.cfg_device_number( cfg_device_number ),
.cfg_function_number( cfg_function_number ),
.cfg_status( cfg_status ),
.cfg_command( cfg_command ),
.cfg_dstatus( cfg_dstatus ),
.cfg_dcommand( cfg_dcommand ),
.cfg_lstatus( cfg_lstatus ),
.cfg_lcommand( cfg_lcommand ),
.cfg_dcommand2( cfg_dcommand2 ),
.cfg_pcie_link_state( cfg_pcie_link_state ),
.cfg_dsn( cfg_dsn ),
.cfg_pmcsr_pme_en( ),
.cfg_pmcsr_pme_status( ),
.cfg_pmcsr_powerstate( ),
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
.pl_initial_link_width( pl_initial_link_width ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_received_hot_rst( pl_received_hot_rst ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_directed_link_change( pl_directed_link_change ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph ),
//-------------------------------------------------------
// 5. System (SYS) Interface
//-------------------------------------------------------
.sys_clk( sys_clk_c ),
.sys_reset( !sys_reset_n_c )
);
pcie_app_v6 #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.DQ_WIDTH(DQ_WIDTH)
)app (
//-------------------------------------------------------
// 1. AXI-S Interface
//-------------------------------------------------------
// Common
.user_clk( user_clk ),
.user_reset( user_reset_int1 ),
.user_lnk_up( user_lnk_up_int1 ),
// Tx
.tx_buf_av( tx_buf_av ),
.tx_cfg_req( tx_cfg_req ),
.tx_err_drop( tx_err_drop ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.tx_cfg_gnt( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok( rx_np_ok ),
// Flow Control
.fc_cpld( fc_cpld ),
.fc_cplh( fc_cplh ),
.fc_npd( fc_npd ),
.fc_nph( fc_nph ),
.fc_pd( fc_pd ),
.fc_ph( fc_ph ),
.fc_sel( fc_sel ),
//-------------------------------------------------------
// 2. Configuration (CFG) Interface
//-------------------------------------------------------
.cfg_do( cfg_do ),
.cfg_rd_wr_done( cfg_rd_wr_done),
.cfg_di( cfg_di ),
.cfg_byte_en( cfg_byte_en ),
.cfg_dwaddr( cfg_dwaddr ),
.cfg_wr_en( cfg_wr_en ),
.cfg_rd_en( cfg_rd_en ),
.cfg_err_cor( cfg_err_cor ),
.cfg_err_ur( cfg_err_ur ),
.cfg_err_ecrc( cfg_err_ecrc ),
.cfg_err_cpl_timeout( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect( cfg_err_cpl_unexpect ),
.cfg_err_posted( cfg_err_posted ),
.cfg_err_locked( cfg_err_locked ),
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy( cfg_err_cpl_rdy ),
.cfg_interrupt( cfg_interrupt ),
.cfg_interrupt_rdy( cfg_interrupt_rdy ),
.cfg_interrupt_assert( cfg_interrupt_assert ),
.cfg_interrupt_di( cfg_interrupt_di ),
.cfg_interrupt_do( cfg_interrupt_do ),
.cfg_interrupt_mmenable( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm( cfg_interrupt_msixfm ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_trn_pending( cfg_trn_pending ),
.cfg_pm_wake( cfg_pm_wake ),
.cfg_bus_number( cfg_bus_number ),
.cfg_device_number( cfg_device_number ),
.cfg_function_number( cfg_function_number ),
.cfg_status( cfg_status ),
.cfg_command( cfg_command ),
.cfg_dstatus( cfg_dstatus ),
.cfg_dcommand( cfg_dcommand ),
.cfg_lstatus( cfg_lstatus ),
.cfg_lcommand( cfg_lcommand ),
.cfg_dcommand2( cfg_dcommand2 ),
.cfg_pcie_link_state( cfg_pcie_link_state ),
.cfg_dsn( cfg_dsn ),
//-------------------------------------------------------
// 3. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
.pl_initial_link_width( pl_initial_link_width ),
.pl_lane_reversal_mode( pl_lane_reversal_mode ),
.pl_link_gen2_capable( pl_link_gen2_capable ),
.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
.pl_link_upcfg_capable( pl_link_upcfg_capable ),
.pl_ltssm_state( pl_ltssm_state ),
.pl_received_hot_rst( pl_received_hot_rst ),
.pl_sel_link_rate( pl_sel_link_rate ),
.pl_sel_link_width( pl_sel_link_width ),
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_directed_link_change( pl_directed_link_change ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph ),
.app_clk(app_clk),
.app_en(app_en),
.app_ack(app_ack),
.app_instr(app_instr),
//Data read back Interface
.rdback_fifo_empty(rdback_fifo_empty),
.rdback_fifo_rden(rdback_fifo_rden),
.rdback_data(rdback_data)
);
endmodule |
module rx_port_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "common_functions.v"
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_128 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_128 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_128 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_128 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
endmodule |
module tx_qword_aligner_128
#(
parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TX_READY_LATENCY = 3'd2
)
(
input CLK,
input RST_IN,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_VALID,
output TX_DATA_READY,
input TX_TLP_END_FLAG,
input TX_TLP_START_FLAG,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output TX_ST_EMPTY
);
reg [C_TX_READY_LATENCY-1:0] rTxStReady=0, _rTxStReady=0;
// Registers for first cycle of pipeline (upper)
// Capture
reg [C_PCI_DATA_WIDTH-1:0] rTxData=0,_rTxData=0;
reg rTxDataValid=0, _rTxDataValid=0;
reg rTxTlpEndFlag=0, _rTxTlpEndFlag=0;
reg rTxTlpStartFlag=0, _rTxTlpStartFlag=0;
// Computed
reg [1:0] rOverflow=0, _rOverflow=0;
reg [9:0] rRealLength=0, _rRealLength=0;
reg [9:0] rAdjLength=0, _rAdjLength=0;
reg rInsBlank=0,_rInsBlank=0;
// State (controls pipeline)
reg [1:0] rUpState=0, _rUpState=0;
// Second cycle of pipeline (lower)
reg [C_PCI_DATA_WIDTH+32-1:0] rAlignBuffer=0, _rAlignBuffer=0;
reg [1:0] rLowState=0, _rLowState=0;
reg rSel=0, _rSel=0;
reg rTrigger=0,_rTrigger=0;
// Registered outputs
reg rTxStValid=0,_rTxStValid=0;
reg rTxStEop=0,_rTxStEop=0;
reg rTxStSop=0,_rTxStSop=0;
reg rTxStEmpty=0,_rTxStEmpty=0;
wire [1:0] wRegEn;
// Wires (unregistered) from input
wire [2:0] wFMT;
wire [63:0] w4DWHAddr;
wire [31:0] w3DWHAddr;
wire w3DWH;
wire w4DWH;
wire wInsBlank;
wire w4DWHQWA;
wire w3DWHQWA;
wire [9:0] wLength;
wire wDataTLP;
wire w3DWHInsBlank;
wire w4DWHInsBlank;
// Overflow indicating wire to the second stage of the pipeline
wire wOverflow;
wire wSMLowEnable;
wire wSMUpEnable;
wire wTxStEopCondition;
wire [255:0] wAlignBufMux;
// Wires from the unregistered TLP Header
assign wFMT = TX_DATA[31:29];
assign w4DWHAddr = {TX_DATA[95:64],TX_DATA[127:96]};
assign w3DWHAddr = TX_DATA[95:64];
assign wLength = TX_DATA[9:0];
assign w4DWH = wFMT[0];
assign w3DWH = ~wFMT[0];
assign wDataTLP = wFMT[1];
assign w4DWHQWA = ~w4DWHAddr[2];
assign w3DWHQWA = ~w3DWHAddr[2];
assign w3DWHInsBlank = w3DWHQWA & w3DWH & wDataTLP;
assign w4DWHInsBlank = ~w4DWHQWA & w4DWH & wDataTLP;
assign wInsBlank = w3DWHInsBlank | w4DWHInsBlank; // Insert a blank DW after the header
assign wRegEn[0] = (~rTxDataValid | wRegEn[1]);
assign wSMUpEnable = wRegEn[0];
assign TX_DATA_READY = wRegEn[0];
// Unconditional input capture
always @(*) begin
_rTxStReady = (rTxStReady << 1) | TX_ST_READY;
end
always @(posedge CLK) begin
rTxStReady <= _rTxStReady;
end
// All of these signals are "valid" when rTxTlpStartFlag and rTxDataValid is high
always @(*) begin
_rInsBlank = wInsBlank & TX_TLP_START_FLAG & TX_DATA_VALID;
_rRealLength = wLength + {7'd0,{w4DWH,~w4DWH,~w4DWH}};
_rAdjLength = wLength + {9'd0,wInsBlank} + {7'd0,{w4DWH,~w4DWH,~w4DWH}};
_rTxData = TX_DATA;
_rTxTlpEndFlag = TX_TLP_END_FLAG & TX_DATA_VALID;
_rTxTlpStartFlag = TX_TLP_START_FLAG & TX_DATA_VALID;
end // always @ begin
always @(posedge CLK) begin
rInsBlank <= _rInsBlank;
rRealLength <= _rRealLength;
rAdjLength <= _rAdjLength;
if(wRegEn[0]) begin
rTxData <= _rTxData;
rTxTlpEndFlag <= _rTxTlpEndFlag;
rTxTlpStartFlag <= _rTxTlpStartFlag;
end
end
always @(*) begin
_rOverflow[0] = TX_TLP_START_FLAG & TX_TLP_END_FLAG & w3DWHInsBlank;
_rOverflow[1] = rTxTlpStartFlag & (rRealLength[9:2] < rAdjLength[9:2]);
end // always @ begin
always @(posedge CLK) begin
if(wSMUpEnable) begin
rOverflow[0] <= _rOverflow[0];
rOverflow[1] <= _rOverflow[1];
end
end
// State machine for the upper pipeline
// Valid never goes down inside of a TLP.
always @(*) begin
_rTxDataValid = rTxDataValid;
if(wSMUpEnable & TX_DATA_VALID) begin
_rTxDataValid = 1'b1;
end else if ( wSMUpEnable & rTxTlpEndFlag)begin
_rTxDataValid = 1'b0;
end
_rUpState = rUpState;
case (rUpState)
`S_TXALIGNER128UP_IDLE: begin
if (TX_DATA_VALID & wRegEn[0]) begin
_rUpState = `S_TXALIGNER128UP_HDR0;
end
end
`S_TXALIGNER128UP_HDR0: begin
if(wSMUpEnable) begin
casex ({rTxTlpEndFlag,TX_DATA_VALID})
2'b0x: _rUpState = `S_TXALIGNER128UP_PAY;
2'b10: _rUpState = `S_TXALIGNER128UP_IDLE;
2'b11: _rUpState = `S_TXALIGNER128UP_HDR0;
endcase // case (rTxTlpEndFlag)
end
end
`S_TXALIGNER128UP_PAY : begin
if(wSMUpEnable) begin
casex ({rTxTlpEndFlag,TX_DATA_VALID})
2'b0x: _rUpState = `S_TXALIGNER128UP_PAY;
2'b10: _rUpState = `S_TXALIGNER128UP_IDLE;
2'b11: _rUpState = `S_TXALIGNER128UP_HDR0;
endcase // case (rTxTlpEndFlag)
end
end
default: _rUpState = `S_TXALIGNER128UP_IDLE;
endcase // case (rUpState)
end // always @ begin
always @(posedge CLK) begin
if(RST_IN) begin
rTxDataValid <= 0;
rUpState <= `S_TXALIGNER128UP_IDLE;
end else begin
rTxDataValid <= _rTxDataValid;
rUpState <= _rUpState;
end
end // always @ (posedge CLK)
// These signals comprise the lower aligner
assign wSMLowEnable = rTxStReady[C_TX_READY_LATENCY-1] | ~rTxStValid;
assign wRegEn[1] = ~(rLowState == `S_TXALIGNER128LOW_PREOVFL & rTrigger) & (wSMLowEnable);
assign wOverflow = (rOverflow[0] | rOverflow[1]);
assign wAlignBufMux = ({{rTxData[95:0],rAlignBuffer[159:128]},rTxData}) >> ({rSel,7'd0});
always @(*) begin
_rAlignBuffer = {rTxData[127:96], wAlignBufMux[127:0]};
end // always @ begin
always @(posedge CLK) begin
if(wSMLowEnable) begin
rAlignBuffer <= _rAlignBuffer;
end
end
assign wTxStEopCondition = (rLowState == `S_TXALIGNER128LOW_PREOVFL & rTrigger) |
(rLowState != `S_TXALIGNER128LOW_PREOVFL & {rTxTlpEndFlag,wOverflow,rTxDataValid} == 3'b101);
// Valid never goes down inside of a TLP.
always @(*) begin
_rLowState = rLowState;
_rTrigger = rTrigger;
_rTxStValid = rTxStValid;
_rTxStEop = rTxStEop;
_rTxStSop = rTxStSop;
_rSel = rSel;
_rTxStEop = wTxStEopCondition;
_rTrigger = rTxTlpEndFlag & rTxDataValid;
_rTxStEmpty = (rAdjLength[1:0] == 2'b01) | (rAdjLength[1:0] == 2'b10);
// Take the next txDataValid if we are taking data
// and it's a start flag and the data is valid
if ( wRegEn[1] & rTxTlpStartFlag & rTxDataValid ) begin
_rTxStValid = 1;
end else if ( wSMLowEnable & rTxStEop ) begin
_rTxStValid = 0;
end
if ( wRegEn[1] & rTxDataValid ) begin // DOUBLE CHECK
_rTxStSop = rTxTlpStartFlag;
end else if ( wSMLowEnable ) begin
_rTxStSop = 0;
end
// rSel should be set on wInsBlank kept high until the end of the packet
// Note: rSel is only applicable in multi-cycle packets
if (wSMLowEnable & rInsBlank) begin
_rSel = 1'b1;
end else if (wSMLowEnable & wTxStEopCondition) begin
_rSel = 1'b0;
end
case (rLowState)
`S_TXALIGNER128LOW_IDLE : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // Stay here
3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Process
3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)
3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // Set rTxStEop
3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
`S_TXALIGNER128LOW_PROC : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle
3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Continue processing
3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)
3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // set rTxStEop
3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
`S_TXALIGNER128LOW_PREOVFL : begin
if(wSMLowEnable) begin
if(rTrigger) begin
_rLowState = `S_TXALIGNER128LOW_OVFL;
end
end
end
`S_TXALIGNER128LOW_OVFL : begin
if(wSMLowEnable) begin
casex({rTxTlpEndFlag,wOverflow,rTxDataValid}) // Set the state for the next cycle
3'bxx0: _rLowState = `S_TXALIGNER128LOW_IDLE; // If the next cycle is not valid Eop must have been set this cycle and we should go to idle
3'b001: _rLowState = `S_TXALIGNER128LOW_PROC; // Continue processing
3'b011: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (Don't set trigger)
3'b101: _rLowState = `S_TXALIGNER128LOW_PROC; // set rTxStEop
3'b111: _rLowState = `S_TXALIGNER128LOW_PREOVFL; // Don't set rTxStEop (set trigger)
endcase
end
end
endcase
end // always @ begin
always @(posedge CLK) begin
if(RST_IN) begin
rLowState <= `S_TXALIGNER128LOW_IDLE;
rTxStValid <= 0;
rTxStSop <= 0;
rSel <= 0;
end else begin
rTxStValid <= _rTxStValid;
rTxStSop <= _rTxStSop;
rSel <= _rSel;
rLowState <= _rLowState;
end // else: !if(RST_IN)
if (RST_IN) begin
rTxStEop <= 1'b0;
end else if (wSMLowEnable) begin
rTxStEop <= _rTxStEop;
end
if (RST_IN) begin
rTrigger <= 1'b0;
end else if (wRegEn[1]) begin
rTrigger <= _rTrigger;
end
if (RST_IN) begin
rTxStEmpty <= 1'b0;
end else if(wRegEn[1] & rTxTlpStartFlag) begin
rTxStEmpty <= _rTxStEmpty;
end
end // always @ (posedge CLK)
// Outputs from the aligner to the PCIe Core
assign TX_ST_VALID = (rTxStValid & rTxStReady[C_TX_READY_LATENCY-1]);
assign TX_ST_EOP = rTxStEop;
assign TX_ST_SOP = rTxStSop;
assign TX_ST_EMPTY = rTxStEmpty;
assign TX_ST_DATA = rAlignBuffer[127:0];
endmodule |
module GTX_TX_SYNC_RATE_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg ENPMAPHASEALIGN = 1'b0,
output reg PMASETPHASE = 1'b0,
output reg SYNC_DONE = 1'b0,
output reg OUT_DIV_RESET = 1'b0,
output reg PCS_RESET = 1'b0,
output reg USER_PHYSTATUS = 1'b0,
output reg TXALIGNDISABLE = 1'b0,
output reg DELAYALIGNRESET = 1'b0,
input USER_CLK,
input RESET,
input RATE,
input RATEDONE,
input GT_PHYSTATUS,
input RESETDONE
);
reg ENPMAPHASEALIGN_c;
reg PMASETPHASE_c;
reg SYNC_DONE_c;
reg OUT_DIV_RESET_c;
reg PCS_RESET_c;
reg USER_PHYSTATUS_c;
reg DELAYALIGNRESET_c;
reg TXALIGNDISABLE_c;
reg [7:0] waitcounter2;
reg [7:0] nextwaitcounter2;
reg [7:0] waitcounter;
reg [7:0] nextwaitcounter;
reg [24:0] state;
reg [24:0] nextstate;
reg ratedone_r, ratedone_r2;
wire ratedone_pulse_i;
reg gt_phystatus_q;
localparam IDLE = 25'b0000000000000000000000001;
localparam PHASEALIGN = 25'b0000000000000000000000010;
localparam RATECHANGE_DIVRESET = 25'b0000000000000000000000100;
localparam RATECHANGE_DIVRESET_POST = 25'b0000000000000000000001000;
localparam RATECHANGE_ENPMADISABLE = 25'b0000000000000000000010000;
localparam RATECHANGE_ENPMADISABLE_POST = 25'b0000000000000000000100000;
localparam RATECHANGE_PMARESET = 25'b0000000000000000001000000;
localparam RATECHANGE_IDLE = 25'b0000000000000000010000000;
localparam RATECHANGE_PCSRESET = 25'b0000000000000000100000000;
localparam RATECHANGE_PCSRESET_POST = 25'b0000000000000001000000000;
localparam RATECHANGE_ASSERTPHY = 25'b0000000000000010000000000;
localparam RESET_STATE = 25'b0000000000000100000000000;
localparam WAIT_PHYSTATUS = 25'b0000000000010000000000000;
localparam RATECHANGE_PMARESET_POST = 25'b0000000000100000000000000;
localparam RATECHANGE_DISABLEPHASE = 25'b0000000001000000000000000;
localparam DELAYALIGNRST = 25'b0000000010000000000000000;
localparam SETENPMAPHASEALIGN = 25'b0000000100000000000000000;
localparam TXALIGNDISABLEDEASSERT = 25'b0000001000000000000000000;
localparam RATECHANGE_TXDLYALIGNDISABLE = 25'b0000010000000000000000000;
localparam GTXTEST_PULSE_1 = 25'b0000100000000000000000000;
localparam RATECHANGE_DISABLE_TXALIGNDISABLE = 25'b0001000000000000000000000;
localparam BEFORE_GTXTEST_PULSE1_1024CLKS = 25'b0010000000000000000000000;
localparam BETWEEN_GTXTEST_PULSES = 25'b0100000000000000000000000;
localparam GTXTEST_PULSE_2 = 25'b1000000000000000000000000;
localparam SYNC_IDX = C_SIMULATION ? 0 : 2;
localparam PMARESET_IDX = C_SIMULATION ? 0: 7;
always @(posedge USER_CLK) begin
if(RESET) begin
state <= #(TCQ) RESET_STATE;
waitcounter2 <= #(TCQ) 8'b0;
waitcounter <= #(TCQ) 8'b0;
USER_PHYSTATUS <= #(TCQ) GT_PHYSTATUS;
SYNC_DONE <= #(TCQ) 1'b0;
ENPMAPHASEALIGN <= #(TCQ) 1'b1;
PMASETPHASE <= #(TCQ) 1'b0;
OUT_DIV_RESET <= #(TCQ) 1'b0;
PCS_RESET <= #(TCQ) 1'b0;
DELAYALIGNRESET <= #(TCQ) 1'b0;
TXALIGNDISABLE <= #(TCQ) 1'b1;
end else begin
state <= #(TCQ) nextstate;
waitcounter2 <= #(TCQ) nextwaitcounter2;
waitcounter <= #(TCQ) nextwaitcounter;
USER_PHYSTATUS <= #(TCQ) USER_PHYSTATUS_c;
SYNC_DONE <= #(TCQ) SYNC_DONE_c;
ENPMAPHASEALIGN <= #(TCQ) ENPMAPHASEALIGN_c;
PMASETPHASE <= #(TCQ) PMASETPHASE_c;
OUT_DIV_RESET <= #(TCQ) OUT_DIV_RESET_c;
PCS_RESET <= #(TCQ) PCS_RESET_c;
DELAYALIGNRESET <= #(TCQ) DELAYALIGNRESET_c;
TXALIGNDISABLE <= #(TCQ) TXALIGNDISABLE_c;
end
end
always @(*) begin
// DEFAULT CONDITIONS
DELAYALIGNRESET_c=0;
SYNC_DONE_c=0;
ENPMAPHASEALIGN_c=1;
PMASETPHASE_c=0;
OUT_DIV_RESET_c=0;
PCS_RESET_c=0;
TXALIGNDISABLE_c=0;
nextstate=state;
USER_PHYSTATUS_c=GT_PHYSTATUS;
nextwaitcounter=waitcounter+1'b1;
nextwaitcounter2= (waitcounter ==8'hff)? waitcounter2 + 1'b1 : waitcounter2 ;
case(state)
// START IN RESET
RESET_STATE : begin
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
nextstate=BEFORE_GTXTEST_PULSE1_1024CLKS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
// Have to hold for 1024 clocks before asserting GTXTEST[1]
BEFORE_GTXTEST_PULSE1_1024CLKS : begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter2[1]) begin
nextstate=GTXTEST_PULSE_1;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
GTXTEST_PULSE_1: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=BETWEEN_GTXTEST_PULSES;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// De-assert GTXTEST[1] for 256 clocks. Figure 3-9 UG366
BETWEEN_GTXTEST_PULSES: begin
OUT_DIV_RESET_c=0;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=GTXTEST_PULSE_2;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// Assert GTXTEST[1] for 256 clocks a second time. Figure 3-9 UG366
GTXTEST_PULSE_2: begin
OUT_DIV_RESET_c=1;
TXALIGNDISABLE_c=1;
ENPMAPHASEALIGN_c=0;
if(waitcounter[7]) begin
nextstate=DELAYALIGNRST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXDLYALIGNRESET FOR 16 CLOCK CYCLES
DELAYALIGNRST : begin
DELAYALIGNRESET_c=1;
ENPMAPHASEALIGN_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=SETENPMAPHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT ENPMAPHASEALIGN FOR 32 CLOCK CYCLES
SETENPMAPHASEALIGN : begin
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=PHASEALIGN;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMASETPHASE OUT OF RESET for 32K CYCLES
PHASEALIGN : begin
PMASETPHASE_c=1;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=TXALIGNDISABLEDEASSERT;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// KEEP TXALIGNDISABLE ASSERTED for 64 CYCLES
TXALIGNDISABLEDEASSERT : begin
TXALIGNDISABLE_c=1;
if(waitcounter[6]) begin
nextwaitcounter=0;
nextstate=IDLE;
nextwaitcounter2=0;
end
end
// NOW IN IDLE, ASSERT SYNC DONE, WAIT FOR RATECHANGE
IDLE : begin
SYNC_DONE_c=1;
if(ratedone_pulse_i) begin
USER_PHYSTATUS_c=0;
nextstate=WAIT_PHYSTATUS;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR PHYSTATUS
WAIT_PHYSTATUS : begin
USER_PHYSTATUS_c=0;
if(gt_phystatus_q) begin
nextstate=RATECHANGE_IDLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT 64 CYCLES BEFORE WE START THE RATE CHANGE
RATECHANGE_IDLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[6]) begin
nextstate=RATECHANGE_TXDLYALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_TXDLYALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DIVRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT DIV RESET FOR 16 CLOCK CYCLES
RATECHANGE_DIVRESET : begin
OUT_DIV_RESET_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[4]) begin
nextstate=RATECHANGE_DIVRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CLOCK CYCLES BEFORE NEXT STEP
RATECHANGE_DIVRESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PMARESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// ASSERT PMA RESET FOR 32K CYCLES
RATECHANGE_PMARESET : begin
PMASETPHASE_c=1;
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter2[PMARESET_IDX]) begin
nextstate=RATECHANGE_PMARESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR 32 CYCLES BEFORE DISABLING TXALIGNDISABLE
RATECHANGE_PMARESET_POST : begin
USER_PHYSTATUS_c=0;
TXALIGNDISABLE_c=1;
if(waitcounter[5]) begin
nextstate=RATECHANGE_DISABLE_TXALIGNDISABLE;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// DISABLE TXALIGNDISABLE FOR 32 CYCLES
RATECHANGE_DISABLE_TXALIGNDISABLE : begin
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// NOW ASSERT PCS RESET FOR 32 CYCLES
RATECHANGE_PCSRESET : begin
PCS_RESET_c=1;
USER_PHYSTATUS_c=0;
if(waitcounter[5]) begin
nextstate=RATECHANGE_PCSRESET_POST;
nextwaitcounter=0;
nextwaitcounter2=0;
end
end
// WAIT FOR RESETDONE BEFORE ASSERTING PHY_STATUS_OUT
RATECHANGE_PCSRESET_POST : begin
USER_PHYSTATUS_c=0;
if(RESETDONE) begin
nextstate=RATECHANGE_ASSERTPHY;
end
end
// ASSERT PHYSTATUSOUT MEANING RATECHANGE IS DONE AND GO BACK TO IDLE
RATECHANGE_ASSERTPHY : begin
USER_PHYSTATUS_c=1;
nextstate=IDLE;
end
endcase
end
// Generate Ratechange Pulse
always @(posedge USER_CLK) begin
if (RESET) begin
ratedone_r <= #(TCQ) 1'b0;
ratedone_r2 <= #(TCQ) 1'b0;
gt_phystatus_q <= #(TCQ) 1'b0;
end else begin
ratedone_r <= #(TCQ) RATE;
ratedone_r2 <= #(TCQ) ratedone_r;
gt_phystatus_q <= #(TCQ) GT_PHYSTATUS;
end
end
assign ratedone_pulse_i = (ratedone_r != ratedone_r2);
endmodule |
module tx_engine_lower_128 #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_ALTERA = 1'b1
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
output [C_PCI_DATA_WIDTH-1:0] TX_DATA, // AXI data output
output [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE, // AXI data keep
output TX_TLP_END_FLAG, // AXI data last
output TX_DATA_VALID, // AXI data valid
output S_AXIS_SRC_DSC, // AXI data discontinue
output TX_TLP_START_FLAG, // AXI data start
input TX_DATA_READY, // AXI ready for data
input COMPL_REQ, // RX Engine request for completion
output COMPL_DONE, // Completion done
input [2:0] REQ_TC,
input REQ_TD,
input REQ_EP,
input [1:0] REQ_ATTR,
input [9:0] REQ_LEN,
input [15:0] REQ_ID,
input [7:0] REQ_TAG,
input [3:0] REQ_BE,
input [29:0] REQ_ADDR,
input [31:0] REQ_DATA,
output [31:0] REQ_DATA_SENT, // Actual completion data sent
input [C_PCI_DATA_WIDTH-1:0] FIFO_DATA, // Read/Write FIFO requests + data
input FIFO_EMPTY, // Read/Write FIFO is empty
output FIFO_REN, // Read/Write FIFO read enable
output [C_NUM_CHNL-1:0] WR_SENT // Pulsed at channel pos when write request sent
);
reg [11:0] rByteCount=0;
reg [6:0] rLowerAddr=0;
reg rFifoRen=0, _rFifoRen=0;
reg rFifoRenIssued=0, _rFifoRenIssued=0;
reg rFifoDataEmpty=1, _rFifoDataEmpty=1;
reg [2:0] rFifoDataValid=0, _rFifoDataValid=0;
reg [(3*C_PCI_DATA_WIDTH)-1:0] rFifoData={3*C_PCI_DATA_WIDTH{1'd0}}, _rFifoData={3*C_PCI_DATA_WIDTH{1'd0}};
wire [(3*C_PCI_DATA_WIDTH)-1:0] wFifoData = (rFifoData>>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));
wire [2:0] wFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);
reg [1:0] rState=`S_TXENGLWR128_IDLE, _rState=`S_TXENGLWR128_IDLE;
reg rComplDone=0, _rComplDone=0;
reg rValid=0, _rValid=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg rLast=0, _rLast=0;
reg rFirst=0, _rFirst=0;
reg [3:0] rKeep=0, _rKeep=0;
reg [C_NUM_CHNL-1:0] rDone=0, _rDone=0;
reg [9:0] rLen=0, _rLen=0;
reg rIsLast=0, _rIsLast=0;
wire [31:0] wReqDataSwap;
wire [7:0] wKeep = (8'b00001111<<(rLen[2:0])) | {8{!rIsLast}};
assign TX_DATA = rData;
assign TX_DATA_BYTE_ENABLE = {{4{rKeep[3]}}, {4{rKeep[2]}}, {4{rKeep[1]}}, {4{rKeep[0]}}};
assign TX_TLP_END_FLAG = rLast;
assign TX_TLP_START_FLAG = rFirst;
assign TX_DATA_VALID = rValid;
assign S_AXIS_SRC_DSC = 0;
assign COMPL_DONE = rComplDone;
generate
if(C_ALTERA == 1'b1) begin : altera_data
assign REQ_DATA_SENT = rData[127:96];
assign wReqDataSwap = REQ_DATA[31:0];
end
else begin : xilinx_data
assign REQ_DATA_SENT = {rData[103:96], rData[111:104], rData[119:112], rData[127:120]};
assign wReqDataSwap = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};
end
endgenerate
assign FIFO_REN = rFifoRen;
assign WR_SENT = rDone;
// Calculate byte count based on byte enable
always @ (REQ_BE) begin
casex (REQ_BE)
4'b1xx1 : rByteCount = 12'h004;
4'b01x1 : rByteCount = 12'h003;
4'b1x10 : rByteCount = 12'h003;
4'b0011 : rByteCount = 12'h002;
4'b0110 : rByteCount = 12'h002;
4'b1100 : rByteCount = 12'h002;
4'b0001 : rByteCount = 12'h001;
4'b0010 : rByteCount = 12'h001;
4'b0100 : rByteCount = 12'h001;
4'b1000 : rByteCount = 12'h001;
4'b0000 : rByteCount = 12'h001;
endcase
end
// Calculate lower address based on byte enable
always @ (REQ_BE or REQ_ADDR) begin
casex (REQ_BE)
4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};
4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};
4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};
endcase
end
// Read in the pre-formatted PCIe data.
always @ (posedge CLK) begin
rFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);
rFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);
rFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoRenIssued = rFifoRen;
_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);
if (rFifoRenIssued) begin
_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);
_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));
end
else begin
_rFifoData = rFifoData;
_rFifoDataValid = rFifoDataValid;
end
end
// Multiplex completion requests and read/write pre-formatted PCIe data onto
// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at
// *any* time during transmission. So be sure to buffer enough data to
// accommodate starts and stops.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGLWR128_IDLE : _rState);
rComplDone <= #1 (RST ? 1'd0 : _rComplDone);
rValid <= #1 (RST ? 1'd0 : _rValid);
rFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);
rDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);
rData <= #1 _rData;
rLast <= #1 _rLast;
rKeep <= #1 _rKeep;
rLen <= #1 _rLen;
rIsLast <= #1 _rIsLast;
rFirst <= #1 _rFirst;
end
always @ (*) begin
_rState = rState;
_rComplDone = rComplDone;
_rValid = rValid;
_rFifoRen = rFifoRen;
_rData = rData;
_rLast = rLast;
_rKeep = rKeep;
_rDone = rDone;
_rLen = rLen;
_rIsLast = rIsLast;
_rFirst = rFirst;
case (rState)
`S_TXENGLWR128_IDLE : begin
_rFifoRen = (TX_DATA_READY & !COMPL_REQ);
_rDone = ((TX_DATA_READY & !COMPL_REQ & wFifoDataValid[0] & wFifoData[30])<<wFifoData[19:16]); // CHNL buried in header
if (TX_DATA_READY) begin // Check for throttling
_rData = {wFifoData[127:20], 4'd0, wFifoData[15:0]}; // Revert the reserved 4 bits back to 0.
_rValid = (!COMPL_REQ & wFifoDataValid[0]);
_rFirst = 1;
_rLast = (!wFifoData[30] | (!wFifoData[29] & !wFifoData[36])); // Not WRITE TLP or (!64 bit & !(LEN != 1))
_rKeep = (4'b1111>>(!wFifoData[30] & !wFifoData[29])); // Not WRITE TLP && !64 bit
_rLen = wFifoData[9:0] - !wFifoData[29]; // LEN - !64 bit
_rIsLast = (wFifoData[9:0] <= {1'b1, 1'b0, !wFifoData[29]}); // LEN <= 4 + !64 bit
if (COMPL_REQ) // PIO read completions
_rState = `S_TXENGLWR128_CPLD_0;
else if (wFifoDataValid[0]) // Read FIFO data if it's ready
_rState = (wFifoData[30] & (wFifoData[29] | wFifoData[36]) ? `S_TXENGLWR128_WR : `S_TXENGLWR128_IDLE); // WRITE TLP & (64 bit | LEN != 1)?
end
end
`S_TXENGLWR128_CPLD_0 : begin
if (TX_DATA_READY) begin // Check for throttling
_rComplDone = 1;
_rValid = 1;
_rLast = 1;
_rFirst = 1;
_rKeep = 4'b1111;
_rData = {wReqDataSwap, // DW3
REQ_ID, REQ_TAG, 1'b0, rLowerAddr, // DW2
CONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount, // DW1
1'b0, `FMT_TXENGLWR128_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,
REQ_EP, REQ_ATTR, 2'b0, REQ_LEN}; // DW0
_rState = `S_TXENGLWR128_CPLD_1;
end
end
`S_TXENGLWR128_CPLD_1 : begin
// Just wait a cycle for the COMP_REQ to drop.
_rComplDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rFirst = 0;
_rValid = 0;
_rState = `S_TXENGLWR128_IDLE;
end
end
`S_TXENGLWR128_WR : begin
_rFifoRen = TX_DATA_READY;
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rFirst = 0;
_rData = wFifoData[127:0];
_rValid = 1;
_rLast = rIsLast;
_rKeep = wKeep[7:4];
_rLen = rLen - 3'd4;
_rIsLast = (rLen <= 4'd8);
_rState = (rIsLast ? `S_TXENGLWR128_IDLE : `S_TXENGLWR128_WR);
end
end
endcase
end
endmodule |
module tx_engine_lower_64 #(
parameter C_PCI_DATA_WIDTH = 9'd64,
parameter C_NUM_CHNL = 4'd12,
parameter C_ALTERA = 1'b1
)
(
input CLK,
input RST,
input [15:0] CONFIG_COMPLETER_ID,
output [C_PCI_DATA_WIDTH-1:0] TX_DATA, // AXI data output
output [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE, // AXI data keep
output TX_TLP_END_FLAG, // AXI data last
output TX_TLP_START_FLAG, // AXI data start
output TX_DATA_VALID, // AXI data valid
output S_AXIS_SRC_DSC, // AXI data discontinue
input TX_DATA_READY, // AXI ready for data
input COMPL_REQ, // RX Engine request for completion
output COMPL_DONE, // Completion done
input [2:0] REQ_TC,
input REQ_TD,
input REQ_EP,
input [1:0] REQ_ATTR,
input [9:0] REQ_LEN,
input [15:0] REQ_ID,
input [7:0] REQ_TAG,
input [3:0] REQ_BE,
input [29:0] REQ_ADDR,
input [31:0] REQ_DATA,
output [31:0] REQ_DATA_SENT, // Actual completion data sent
input [C_PCI_DATA_WIDTH-1:0] FIFO_DATA, // Read/Write FIFO requests + data
input FIFO_EMPTY, // Read/Write FIFO is empty
output FIFO_REN, // Read/Write FIFO read enable
output [C_NUM_CHNL-1:0] WR_SENT // Pulsed at channel pos when write request sent
);
reg [11:0] rByteCount=0;
reg [6:0] rLowerAddr=0;
reg rFifoRen=0, _rFifoRen=0;
reg rFifoRenIssued=0, _rFifoRenIssued=0;
reg rFifoDataEmpty=1, _rFifoDataEmpty=1;
reg [2:0] rFifoDataValid=0, _rFifoDataValid=0;
reg [(3*C_PCI_DATA_WIDTH)-1:0] rFifoData={3*C_PCI_DATA_WIDTH{1'd0}}, _rFifoData={3*C_PCI_DATA_WIDTH{1'd0}};
wire [C_PCI_DATA_WIDTH-1:0] wFifoData = (rFifoData>>(C_PCI_DATA_WIDTH*(!rFifoRen)))>>(C_PCI_DATA_WIDTH*(!rFifoRenIssued));
wire wFifoDataValid = (rFifoDataValid>>(!rFifoRen))>>(!rFifoRenIssued);
reg [2:0] rState=`S_TXENGLWR64_IDLE, _rState=`S_TXENGLWR64_IDLE;
reg rComplDone=0, _rComplDone=0;
reg rValid=0, _rValid=0;
reg [C_PCI_DATA_WIDTH-1:0] rData={C_PCI_DATA_WIDTH{1'd0}}, _rData={C_PCI_DATA_WIDTH{1'd0}};
reg rLast=0, _rLast=0;
reg rFirst=0, _rFirst=0;
reg rKeep=0, _rKeep=0;
reg [C_NUM_CHNL-1:0] rDone=0, _rDone=0;
reg [9:0] rInitLen=0, _rInitLen=0;
reg [9:0] rLen=0, _rLen=0;
reg [3:0] rChnl=0, _rChnl=0;
reg r3DW=0, _r3DW=0;
reg rIsLast=0, _rIsLast=0;
reg rInitIsLast=0, _rInitIsLast=0;
wire [31:0] wReqDataSwap;
assign TX_DATA = rData;
assign TX_DATA_BYTE_ENABLE = {{4{rKeep}}, 4'hF};
assign TX_TLP_END_FLAG = rLast;
assign TX_TLP_START_FLAG = rFirst;
assign TX_DATA_VALID = rValid;
assign S_AXIS_SRC_DSC = 0;
assign COMPL_DONE = rComplDone;
generate
if(C_ALTERA == 1'b1) begin : altera_data
assign REQ_DATA_SENT = rData[63:32];
assign wReqDataSwap = REQ_DATA[31:0];
end
else begin : xilinx_data
assign REQ_DATA_SENT = {rData[39:32], rData[47:40], rData[55:48], rData[63:56]};
assign wReqDataSwap = {REQ_DATA[7:0], REQ_DATA[15:8], REQ_DATA[23:16], REQ_DATA[31:24]};
end
endgenerate
assign FIFO_REN = rFifoRen;
assign WR_SENT = rDone;
// Calculate byte count based on byte enable
always @ (REQ_BE) begin
casex (REQ_BE)
4'b1xx1 : rByteCount = 12'h004;
4'b01x1 : rByteCount = 12'h003;
4'b1x10 : rByteCount = 12'h003;
4'b0011 : rByteCount = 12'h002;
4'b0110 : rByteCount = 12'h002;
4'b1100 : rByteCount = 12'h002;
4'b0001 : rByteCount = 12'h001;
4'b0010 : rByteCount = 12'h001;
4'b0100 : rByteCount = 12'h001;
4'b1000 : rByteCount = 12'h001;
4'b0000 : rByteCount = 12'h001;
endcase
end
// Calculate lower address based on byte enable
always @ (REQ_BE or REQ_ADDR) begin
casex (REQ_BE)
4'b0000 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxxx1 : rLowerAddr = {REQ_ADDR[4:0], 2'b00};
4'bxx10 : rLowerAddr = {REQ_ADDR[4:0], 2'b01};
4'bx100 : rLowerAddr = {REQ_ADDR[4:0], 2'b10};
4'b1000 : rLowerAddr = {REQ_ADDR[4:0], 2'b11};
endcase
end
// Read in the pre-formatted PCIe data.
always @ (posedge CLK) begin
rFifoRenIssued <= #1 (RST ? 1'd0 : _rFifoRenIssued);
rFifoDataValid <= #1 (RST ? 1'd0 : _rFifoDataValid);
rFifoDataEmpty <= #1 (RST ? 1'd1 : _rFifoDataEmpty);
rFifoData <= #1 _rFifoData;
end
always @ (*) begin
_rFifoRenIssued = rFifoRen;
_rFifoDataEmpty = (rFifoRen ? FIFO_EMPTY : rFifoDataEmpty);
if (rFifoRenIssued) begin
_rFifoData = ((rFifoData<<(C_PCI_DATA_WIDTH)) | FIFO_DATA);
_rFifoDataValid = ((rFifoDataValid<<1) | (!rFifoDataEmpty));
end
else begin
_rFifoData = rFifoData;
_rFifoDataValid = rFifoDataValid;
end
end
// Multiplex completion requests and read/write pre-formatted PCIe data onto
// the AXI PCIe Endpoint interface. Remember that TX_DATA_READY may drop at
// *any* time during transmission. So be sure to buffer enough data to
// accommodate starts and stops.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXENGLWR64_IDLE : _rState);
rComplDone <= #1 (RST ? 1'd0 : _rComplDone);
rValid <= #1 (RST ? 1'd0 : _rValid);
rFifoRen <= #1 (RST ? 1'd0 : _rFifoRen);
rDone <= #1 (RST ? {C_NUM_CHNL{1'd0}} : _rDone);
rData <= #1 _rData;
rLast <= #1 _rLast;
rKeep <= #1 _rKeep;
rChnl <= #1 _rChnl;
r3DW <= #1 _r3DW;
rLen <= #1 _rLen;
rInitLen <= #1 _rInitLen;
rIsLast <= #1 _rIsLast;
rInitIsLast <= #1 _rInitIsLast;
rFirst <= #1 _rFirst;
end
always @ (*) begin
_rState = rState;
_rComplDone = rComplDone;
_rValid = rValid;
_rFifoRen = rFifoRen;
_rData = rData;
_rLast = rLast;
_rKeep = rKeep;
_rChnl = rChnl;
_rDone = rDone;
_r3DW = r3DW;
_rLen = rLen;
_rInitLen = rInitLen;
_rIsLast = rIsLast;
_rInitIsLast = rInitIsLast;
_rFirst = rFirst;
case (rState)
`S_TXENGLWR64_IDLE : begin
_rFifoRen = (TX_DATA_READY & !COMPL_REQ);
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rData = {wFifoData[63:20], 4'd0, wFifoData[15:0]}; // Revert the reserved 4 bits back to 0.
_rValid = (!COMPL_REQ & wFifoDataValid);
_rFirst = 1;
_rLast = 0;
_rKeep = 1;
_rChnl = wFifoData[19:16]; // CHNL buried in header
_r3DW = !wFifoData[29]; // !64 bit
_rInitLen = wFifoData[9:0]; // LEN
_rInitIsLast = (!wFifoData[29] & !wFifoData[36]); // !64 bit && !(LEN != 1)
if (COMPL_REQ) // PIO read completions
_rState = `S_TXENGLWR64_CPLD_0;
else if (wFifoDataValid) // Read FIFO data if it's ready
_rState = (wFifoData[30] ? `S_TXENGLWR64_WR_0 : `S_TXENGLWR64_RD_0); // WRITE TLP?
end
end
`S_TXENGLWR64_CPLD_0 : begin
if (TX_DATA_READY) begin // Check for throttling
_rFirst = 1;
_rValid = 1;
_rLast = 0;
_rKeep = 1;
_rData = {CONFIG_COMPLETER_ID[15:3], 3'b0, 3'b0, 1'b0, rByteCount, // DW1
1'b0, `FMT_TXENGLWR64_CPLD, 1'b0, REQ_TC, 4'b0, REQ_TD,
REQ_EP, REQ_ATTR, 2'b0, REQ_LEN}; // DW0
_rState = `S_TXENGLWR64_CPLD_1;
end
end
`S_TXENGLWR64_CPLD_1 : begin
// Send rest of header and requested data
if (TX_DATA_READY) begin // Check for throttling
_rComplDone = 1;
_rValid = 1;
_rFirst = 0;
_rLast = 1;
_rKeep = 1;
_rData = {wReqDataSwap, // DW3
REQ_ID, REQ_TAG, 1'b0, rLowerAddr}; // DW2
_rState = `S_TXENGLWR64_CPLD_2;
end
end
`S_TXENGLWR64_CPLD_2 : begin
// Just wait a cycle for the COMP_REQ to drop.
_rComplDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rValid = 0;
_rFirst = 0;
_rState = `S_TXENGLWR64_IDLE;
end
end
`S_TXENGLWR64_RD_0 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rFirst = 0;
_rLast = 1;
_rKeep = !r3DW;
_rState = `S_TXENGLWR64_IDLE;
end
end
`S_TXENGLWR64_WR_0 : begin
_rFifoRen = TX_DATA_READY;
if (TX_DATA_READY) begin // Check for throttling
_rDone = (1'd1<<rChnl);
_rData = wFifoData;
_rValid = 1;
_rFirst = 0;
_rLast = rInitIsLast;
_rKeep = 1;
_rLen = rInitLen - r3DW;
_rIsLast = (rInitLen <= {1'd1, r3DW});
_rState = (rInitIsLast ? `S_TXENGLWR64_IDLE : `S_TXENGLWR64_WR_1);
end
end
`S_TXENGLWR64_WR_1 : begin
_rFifoRen = TX_DATA_READY;
_rDone = 0;
if (TX_DATA_READY) begin // Check for throttling
_rData = wFifoData;
_rValid = 1;
_rFirst = 0;
_rLast = rIsLast;
_rKeep = !(rIsLast & rLen[0]);
_rLen = rLen - 2'd2;
_rIsLast = (rLen <= 3'd4);
_rState = (rIsLast ? `S_TXENGLWR64_IDLE : `S_TXENGLWR64_WR_1);
end
end
default : begin
_rState = `S_TXENGLWR64_IDLE;
end
endcase
end
endmodule |
module pcie_brams_v6
#(
// the number of BRAMs to use
// supported values are:
// 1,2,4,8,18
parameter NUM_BRAMS = 0,
// BRAM read address latency
//
// value meaning
// ====================================================
// 0 BRAM read address port sample
// 1 BRAM read address port sample and a pipeline stage on the address port
parameter RAM_RADDR_LATENCY = 1,
// BRAM read data latency
//
// value meaning
// ====================================================
// 1 no BRAM OREG
// 2 use BRAM OREG
// 3 use BRAM OREG and a pipeline stage on the data port
parameter RAM_RDATA_LATENCY = 1,
// BRAM write latency
// The BRAM write port is synchronous
//
// value meaning
// ====================================================
// 0 BRAM write port sample
// 1 BRAM write port sample plus pipeline stage
parameter RAM_WRITE_LATENCY = 1,
parameter TCQ = 1
)
(
input user_clk_i,
input reset_i,
input wen,
input [12:0] waddr,
input [71:0] wdata,
input ren,
input rce,
input [12:0] raddr,
output [71:0] rdata
);
// turn on the bram output register
localparam DOB_REG = (RAM_RDATA_LATENCY > 1) ? 1 : 0;
// calculate the data width of the individual brams
localparam [6:0] WIDTH = ((NUM_BRAMS == 1) ? 72 :
(NUM_BRAMS == 2) ? 36 :
(NUM_BRAMS == 4) ? 18 :
(NUM_BRAMS == 8) ? 9 :
4
);
//synthesis translate_off
initial begin
$display("[%t] %m NUM_BRAMS %0d DOB_REG %0d WIDTH %0d RAM_WRITE_LATENCY %0d RAM_RADDR_LATENCY %0d RAM_RDATA_LATENCY %0d",
$time, NUM_BRAMS, DOB_REG, WIDTH, RAM_WRITE_LATENCY, RAM_RADDR_LATENCY, RAM_RDATA_LATENCY);
case (NUM_BRAMS)
1,2,4,8,18:;
default:
begin
$display("[%t] %m Error NUM_BRAMS %0d not supported", $time, NUM_BRAMS);
$finish;
end
endcase // case(NUM_BRAMS)
case (RAM_RADDR_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RADDR_LATENCY);
$finish;
end
endcase // case (RAM_RADDR_LATENCY)
case (RAM_RDATA_LATENCY)
1,2,3:;
default:
begin
$display("[%t] %m Error RAM_READ_LATENCY %0d not supported", $time, RAM_RDATA_LATENCY);
$finish;
end
endcase // case (RAM_RDATA_LATENCY)
case (RAM_WRITE_LATENCY)
0,1:;
default:
begin
$display("[%t] %m Error RAM_WRITE_LATENCY %0d not supported", $time, RAM_WRITE_LATENCY);
$finish;
end
endcase // case(RAM_WRITE_LATENCY)
end
//synthesis translate_on
// model the delays for ram write latency
wire wen_int;
wire [12:0] waddr_int;
wire [71:0] wdata_int;
generate if (RAM_WRITE_LATENCY == 1) begin : wr_lat_2
reg wen_dly;
reg [12:0] waddr_dly;
reg [71:0] wdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
wen_dly <= #TCQ 1'b0;
waddr_dly <= #TCQ 13'b0;
wdata_dly <= #TCQ 72'b0;
end else begin
wen_dly <= #TCQ wen;
waddr_dly <= #TCQ waddr;
wdata_dly <= #TCQ wdata;
end
end
assign wen_int = wen_dly;
assign waddr_int = waddr_dly;
assign wdata_int = wdata_dly;
end // if (RAM_WRITE_LATENCY == 1)
else if (RAM_WRITE_LATENCY == 0) begin : wr_lat_1
assign wen_int = wen;
assign waddr_int = waddr;
assign wdata_int = wdata;
end
endgenerate
// model the delays for ram read latency
wire ren_int;
wire [12:0] raddr_int;
wire [71:0] rdata_int;
generate if (RAM_RADDR_LATENCY == 1) begin : raddr_lat_2
reg ren_dly;
reg [12:0] raddr_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
ren_dly <= #TCQ 1'b0;
raddr_dly <= #TCQ 13'b0;
end else begin
ren_dly <= #TCQ ren;
raddr_dly <= #TCQ raddr;
end // else: !if(reset_i)
end
assign ren_int = ren_dly;
assign raddr_int = raddr_dly;
end // block: rd_lat_addr_2
else begin : raddr_lat_1
assign ren_int = ren;
assign raddr_int = raddr;
end
endgenerate
generate if (RAM_RDATA_LATENCY == 3) begin : rdata_lat_3
reg [71:0] rdata_dly;
always @(posedge user_clk_i) begin
if (reset_i) begin
rdata_dly <= #TCQ 72'b0;
end else begin
rdata_dly <= #TCQ rdata_int;
end // else: !if(reset_i)
end
assign rdata = rdata_dly;
end // block: rd_lat_data_3
else begin : rdata_lat_1_2
assign #TCQ rdata = rdata_int;
end
endgenerate
// instantiate the brams
generate
begin: num_brams
genvar i;
for (i = 0; i < NUM_BRAMS; i = i + 1) begin : brams
pcie_bram_v6 #(.DOB_REG(DOB_REG), .WIDTH(WIDTH))
ram (.user_clk_i(user_clk_i), .reset_i(reset_i),
.wen_i(wen_int), .waddr_i(waddr_int), .wdata_i(wdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]),
.ren_i(ren_int), .raddr_i(raddr_int), .rdata_o(rdata_int[(((i + 1) * WIDTH) - 1): (i * WIDTH)]), .rce_i(rce));
end
end
endgenerate
endmodule // pcie_brams_v6 |
module translation_layer_128
#(
parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_RX_READY_LATENCY = 3'd2,
parameter C_TX_READY_LATENCY = 3'd2
)
(
input CLK,
input RST_IN,
// Xilinx Signals
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST, // Not used in the 128 bit interface
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,
input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,
input RERR_FWD,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
output S_AXIS_SRC_DSC,
input S_AXIS_TX_TREADY,
input [15:0] COMPLETER_ID,
input CFG_BUS_MSTR_ENABLE,
input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent
output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)
input RCB,
input [11:0] MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)
input [7:0] MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)
// Altera Signals
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_EMPTY,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
input [31:0] TL_CFG_CTL,
input [3:0] TL_CFG_ADD,
input [52:0] TL_CFG_STS,
input [7:0] KO_CPL_SPC_HEADER,
input [11:0] KO_CPL_SPC_DATA,
input APP_MSI_ACK,
output APP_MSI_REQ,
// Unified Signals
output [C_PCI_DATA_WIDTH-1:0] RX_DATA,
output RX_DATA_VALID,
input RX_DATA_READY,
output RX_TLP_END_FLAG,
output [3:0] RX_TLP_END_OFFSET,
output RX_TLP_START_FLAG,
output [3:0] RX_TLP_START_OFFSET,
output RX_TLP_ERROR_POISON,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,
input TX_TLP_END_FLAG,
input TX_TLP_START_FLAG,
input TX_DATA_VALID,
input TX_TLP_ERROR_POISON,
output TX_DATA_READY,
output [15:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
output [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
output CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byt
output INTR_MSI_RDY,
input INTR_MSI_REQUEST
);
generate
if(C_ALTERA == 1'b1) begin : altera_translator_128
wire [2:0] wFMT; // Format field of the TLP Header
wire [4:0] wType; // Type field of the TLP header
wire [9:0] wLength; // Length field of the TLP Header
wire wLenEven; // 1 if even number of TLP data words, else 0
wire wQWA4DWH, wQWA3DWH;
wire wMsgType;
wire wEP;
wire w3DWH;
wire w4DWH;
reg _r1CyTLP,r1CyTLP;
reg _rEven4DWH, rEven4DWH;
reg _rEven3DWH, rEven3DWH;
reg _rEvenMsg, rEvenMsg;
reg _rEP, rEP;
reg _rMSG, rMSG/* synthesis noprune */;
reg [3:0] rTlCfgAdd,_rTlCfgAdd;
reg [31:0] rTlCfgCtl,_rTlCfgCtl;
reg [52:0] rTlCfgSts,_rTlCfgSts;
reg [15:0] rCfgCompleterId;
reg rCfgBusMstrEnable;
reg [2:0] rCfgMaxReadRequestSize;
reg [2:0] rCfgMaxPayloadSize;
reg rCfgInterruptMsienable;
reg rReadCompletionBoundarySel;
reg [1:0] _rTlpEndOffset_I, rTlpEndOffset_I;
reg [1:0] _rTlpEndOffset_D, rTlpEndOffset_D;
reg [127:0] rRxStData;
reg rRxStValid;
reg rRxStEop;
reg rRxStSop;
assign wEP = RX_ST_DATA[14];
assign wLength = RX_ST_DATA[9:0];
assign wType = RX_ST_DATA[28:24];
assign wFMT = RX_ST_DATA[31:29];
assign wQWA3DWH = ~RX_ST_DATA[66];
assign wQWA4DWH = ~RX_ST_DATA[98];
assign w4DWH = wFMT[0];
assign w3DWH = ~wFMT[0];
assign wLenEven = ~wLength[0];
assign wMsgType = wType[4];
// Pre-calculating TLP End offset
always @(*) begin
// We expect to recieve three different types of packets
// 3 DWH Packets, 4 DWH Packets, and Messages (No address)
_rEven4DWH = w4DWH & ((wQWA4DWH & wLenEven) | (~wQWA4DWH & ~wLenEven));
_rEven3DWH = w3DWH & ((wQWA3DWH & wLenEven) | (~wQWA3DWH & ~wLenEven));
_rEvenMsg = wMsgType & wLenEven;
_rMSG = (RX_ST_SOP & RX_ST_DATA[28]) | (rMSG & ~RX_ST_EOP);
_rEP = (wEP & RX_ST_SOP) | (rEP & ~RX_TLP_END_FLAG);
_rTlpEndOffset_I = {1'b1, ((~wLenEven & w3DWH)| w4DWH)};
_rTlpEndOffset_D = {~RX_ST_EMPTY,rEven4DWH|rEven3DWH|rEvenMsg};
_r1CyTLP = RX_ST_SOP & RX_ST_EOP;
_rTlCfgCtl = TL_CFG_CTL;
_rTlCfgAdd = TL_CFG_ADD;
_rTlCfgSts = TL_CFG_STS;
end
always @(posedge CLK) begin // Should be the same clock as pld_clk
rTlCfgAdd <= _rTlCfgAdd;
rTlCfgCtl <= _rTlCfgCtl;
rTlCfgSts <= _rTlCfgSts;
rEP <= _rEP;
rTlpEndOffset_I <= _rTlpEndOffset_I;
rTlpEndOffset_D <= _rTlpEndOffset_D;
r1CyTLP <= _r1CyTLP;
rRxStData <= RX_ST_DATA;
rRxStValid <= RX_ST_VALID;
rRxStEop <= RX_ST_EOP;
rRxStSop <= RX_ST_SOP;
rMSG <= _rMSG;
if(RX_ST_SOP) begin
rEven4DWH <= _rEven4DWH;
rEven3DWH <= _rEven3DWH;
rEvenMsg <= _rEvenMsg;
end
if(rTlCfgAdd == 4'h0) begin
rCfgMaxReadRequestSize <= rTlCfgCtl[30:28];
rCfgMaxPayloadSize <= rTlCfgCtl[23:21];
end
if(rTlCfgAdd == 4'h2) begin
rReadCompletionBoundarySel <= rTlCfgCtl[19];
end
if(rTlCfgAdd == 4'h3) begin
rCfgBusMstrEnable <= rTlCfgCtl[10];
end
if(rTlCfgAdd == 4'hD) begin
rCfgInterruptMsienable <= rTlCfgCtl[0];
end
if(rTlCfgAdd == 4'hF) begin
rCfgCompleterId <= {rTlCfgCtl[12:0],3'b0};
end
end // always @ (posedge CLK)
// Rx Interface (To PCIe Core)
assign RX_ST_READY = RX_DATA_READY;
// Rx Interface (From PCIe Core)
assign RX_DATA = rRxStData;
assign RX_DATA_VALID = rRxStValid;
assign RX_TLP_END_FLAG = rRxStEop;
assign RX_TLP_END_OFFSET = {r1CyTLP?rTlpEndOffset_I:rTlpEndOffset_D,2'b11};
assign RX_TLP_START_FLAG = rRxStSop;
assign RX_TLP_START_OFFSET = 4'h0000;
assign RX_TLP_ERROR_POISON = rEP;
// Configuration Interface
assign CONFIG_COMPLETER_ID = rCfgCompleterId;
assign CONFIG_BUS_MASTER_ENABLE = rCfgBusMstrEnable;
assign CONFIG_LINK_WIDTH = rTlCfgSts[40:35];
assign CONFIG_LINK_RATE = rTlCfgSts[32:31];
assign CONFIG_MAX_READ_REQUEST_SIZE = rCfgMaxReadRequestSize;
assign CONFIG_MAX_PAYLOAD_SIZE = rCfgMaxPayloadSize;
assign CONFIG_INTERRUPT_MSIENABLE = rCfgInterruptMsienable;
assign CONFIG_CPL_BOUNDARY_SEL = rReadCompletionBoundarySel;
assign CONFIG_MAX_CPL_HDR = KO_CPL_SPC_HEADER;
assign CONFIG_MAX_CPL_DATA = KO_CPL_SPC_DATA;
// Interrupt interface
assign APP_MSI_REQ = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = APP_MSI_ACK;
tx_qword_aligner_128
#(
.C_ALTERA(C_ALTERA),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TX_READY_LATENCY(C_TX_READY_LATENCY)
)
aligner_inst
(
// Outputs
.TX_DATA_READY (TX_DATA_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_ST_READY (TX_ST_READY));
end else begin : xilinx_translator_128
// Rx Interface (From PCIe Core)
assign RX_DATA = M_AXIS_RX_TDATA;
assign RX_DATA_VALID = M_AXIS_RX_TVALID;
assign RX_TLP_END_FLAG = IS_EOF[4]; // Also, M_AXIS_RX_TLAST
assign RX_TLP_END_OFFSET = IS_EOF[3:0];
assign RX_TLP_START_FLAG = IS_SOF[4]; // Also, posedge M_AXIS_RX_TVALID or negedge M_AXIS_RX_TLAST and M_AXIS_RX_TVALID = 1
assign RX_TLP_START_OFFSET = IS_SOF[3:0];
assign RX_TLP_ERROR_POISON = RERR_FWD;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_DATA_READY;
// TX Interface (From PCIe Core)
assign TX_DATA_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_DATA;
assign S_AXIS_TX_TVALID = TX_DATA_VALID;
assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;
// Configuration Interface
assign CONFIG_COMPLETER_ID = COMPLETER_ID;
assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;
assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;
assign CONFIG_LINK_RATE = CFG_LINK_RATE;
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = RCB;
assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;
assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
end
endgenerate
endmodule |
module translation_layer
#(parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_TX_READY_LATENCY = 3'd1)
(
input CLK,
input RST_IN,
// Xilinx Signals
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST, // Not used in the 128 bit interface
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [4:0] IS_SOF,
input [4:0] IS_EOF,
input RERR_FWD,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
output S_AXIS_SRC_DSC,
input S_AXIS_TX_TREADY,
input [15:0] COMPLETER_ID,
input CFG_BUS_MSTR_ENABLE,
input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent
output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent);
input RCB,
input [11:0] MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)
input [7:0] MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)
// Altera Signals
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_EMPTY,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
input [31:0] TL_CFG_CTL,
input [3:0] TL_CFG_ADD,
input [52:0] TL_CFG_STS,
input [7:0] KO_CPL_SPC_HEADER,
input [11:0] KO_CPL_SPC_DATA,
input APP_MSI_ACK,
output APP_MSI_REQ,
// Unified Signals
output [C_PCI_DATA_WIDTH-1:0] RX_DATA,
output RX_DATA_VALID,
input RX_DATA_READY,
output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,
output RX_TLP_END_FLAG,
output [3:0] RX_TLP_END_OFFSET,
output RX_TLP_START_FLAG,
output [3:0] RX_TLP_START_OFFSET,
output RX_TLP_ERROR_POISON,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,
input TX_TLP_END_FLAG,
input TX_TLP_START_FLAG,
input TX_DATA_VALID,
input TX_TLP_ERROR_POISON,
output TX_DATA_READY,
output [15:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
output [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
output CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 bytes)w
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are hi
);
generate
if (C_PCI_DATA_WIDTH == 9'd32) begin : endpoint32
translation_layer_32
#(.C_ALTERA(1'b0),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH))
tl32_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_SRC_DSC (S_AXIS_SRC_DSC),
.CFG_INTERRUPT (CFG_INTERRUPT),
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
.RX_DATA (RX_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_DATA_VALID (RX_DATA_VALID),
.RX_DATA_BYTE_ENABLE (RX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[3:0]),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[3:0]),
.RX_TLP_ERROR_POISON (RX_TLP_ERROR_POISON),
.TX_DATA_READY (TX_DATA_READY),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[15:0]),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH (CONFIG_LINK_WIDTH[5:0]),
.CONFIG_LINK_RATE (CONFIG_LINK_RATE[1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY (INTR_MSI_RDY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.IS_SOF (IS_SOF[(C_PCI_DATA_WIDTH/32):0]),
.IS_EOF (IS_EOF[(C_PCI_DATA_WIDTH/32):0]),
.RERR_FWD (RERR_FWD),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.COMPLETER_ID (COMPLETER_ID[15:0]),
.CFG_BUS_MSTR_ENABLE (CFG_BUS_MSTR_ENABLE),
.CFG_LINK_WIDTH (CFG_LINK_WIDTH[5:0]),
.CFG_LINK_RATE (CFG_LINK_RATE[1:0]),
.CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),
.CFG_MAX_PAYLOAD_SIZE (CFG_MAX_PAYLOAD_SIZE[2:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY),
.RCB (RCB),
.MAX_RC_CPLD (MAX_RC_CPLD[11:0]),
.MAX_RC_CPLH (MAX_RC_CPLH[7:0]),
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[31:0]),
.TL_CFG_ADD (TL_CFG_ADD[3:0]),
.TL_CFG_STS (TL_CFG_STS[52:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[7:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[11:0]),
.APP_MSI_ACK (APP_MSI_ACK),
.RX_DATA_READY (RX_DATA_READY),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_BYTE_ENABLE (TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_ERROR_POISON (TX_TLP_ERROR_POISON),
.INTR_MSI_REQUEST (INTR_MSI_REQUEST));
end
else if (C_PCI_DATA_WIDTH == 9'd64) begin : endpoint64
translation_layer_64
#(.C_ALTERA(C_ALTERA),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TX_READY_LATENCY(C_TX_READY_LATENCY))
tl64_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_SRC_DSC (S_AXIS_SRC_DSC),
.CFG_INTERRUPT (CFG_INTERRUPT),
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
.RX_DATA (RX_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_DATA_VALID (RX_DATA_VALID),
.RX_DATA_BYTE_ENABLE (RX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[3:0]),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[3:0]),
.RX_TLP_ERROR_POISON (RX_TLP_ERROR_POISON),
.TX_DATA_READY (TX_DATA_READY),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[15:0]),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH (CONFIG_LINK_WIDTH[5:0]),
.CONFIG_LINK_RATE (CONFIG_LINK_RATE[1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY (INTR_MSI_RDY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.IS_SOF (IS_SOF[(C_PCI_DATA_WIDTH/32):0]),
.IS_EOF (IS_EOF[(C_PCI_DATA_WIDTH/32):0]),
.RERR_FWD (RERR_FWD),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.COMPLETER_ID (COMPLETER_ID[15:0]),
.CFG_BUS_MSTR_ENABLE (CFG_BUS_MSTR_ENABLE),
.CFG_LINK_WIDTH (CFG_LINK_WIDTH[5:0]),
.CFG_LINK_RATE (CFG_LINK_RATE[1:0]),
.CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),
.CFG_MAX_PAYLOAD_SIZE (CFG_MAX_PAYLOAD_SIZE[2:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY),
.RCB (RCB),
.MAX_RC_CPLD (MAX_RC_CPLD[11:0]),
.MAX_RC_CPLH (MAX_RC_CPLH[7:0]),
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[31:0]),
.TL_CFG_ADD (TL_CFG_ADD[3:0]),
.TL_CFG_STS (TL_CFG_STS[52:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[7:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[11:0]),
.APP_MSI_ACK (APP_MSI_ACK),
.RX_DATA_READY (RX_DATA_READY),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_BYTE_ENABLE (TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_ERROR_POISON (TX_TLP_ERROR_POISON),
.INTR_MSI_REQUEST (INTR_MSI_REQUEST));
end
else if (C_PCI_DATA_WIDTH == 9'd128) begin : endpoint128
translation_layer_128
#(.C_ALTERA(C_ALTERA),
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TX_READY_LATENCY(C_TX_READY_LATENCY))
tl128_inst
(/*AUTOINST*/
// Outputs
.M_AXIS_RX_TREADY (M_AXIS_RX_TREADY),
.S_AXIS_TX_TDATA (S_AXIS_TX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_TX_TKEEP (S_AXIS_TX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.S_AXIS_TX_TLAST (S_AXIS_TX_TLAST),
.S_AXIS_TX_TVALID (S_AXIS_TX_TVALID),
.S_AXIS_SRC_DSC (S_AXIS_SRC_DSC),
.CFG_INTERRUPT (CFG_INTERRUPT),
.RX_ST_READY (RX_ST_READY),
.TX_ST_DATA (TX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (TX_ST_VALID[0:0]),
.TX_ST_EOP (TX_ST_EOP[0:0]),
.TX_ST_SOP (TX_ST_SOP[0:0]),
.TX_ST_EMPTY (TX_ST_EMPTY[0:0]),
.APP_MSI_REQ (APP_MSI_REQ),
.RX_DATA (RX_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_DATA_VALID (RX_DATA_VALID),
.RX_TLP_END_FLAG (RX_TLP_END_FLAG),
.RX_TLP_END_OFFSET (RX_TLP_END_OFFSET[3:0]),
.RX_TLP_START_FLAG (RX_TLP_START_FLAG),
.RX_TLP_START_OFFSET (RX_TLP_START_OFFSET[3:0]),
.RX_TLP_ERROR_POISON (RX_TLP_ERROR_POISON),
.TX_DATA_READY (TX_DATA_READY),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[15:0]),
.CONFIG_BUS_MASTER_ENABLE(CONFIG_BUS_MASTER_ENABLE),
.CONFIG_LINK_WIDTH (CONFIG_LINK_WIDTH[5:0]),
.CONFIG_LINK_RATE (CONFIG_LINK_RATE[1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE[2:0]),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL(CONFIG_CPL_BOUNDARY_SEL),
.INTR_MSI_RDY (INTR_MSI_RDY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.M_AXIS_RX_TDATA (M_AXIS_RX_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RX_TKEEP (M_AXIS_RX_TKEEP[(C_PCI_DATA_WIDTH/8)-1:0]),
.M_AXIS_RX_TLAST (M_AXIS_RX_TLAST),
.M_AXIS_RX_TVALID (M_AXIS_RX_TVALID),
.IS_SOF (IS_SOF[(C_PCI_DATA_WIDTH/32):0]),
.IS_EOF (IS_EOF[(C_PCI_DATA_WIDTH/32):0]),
.RERR_FWD (RERR_FWD),
.S_AXIS_TX_TREADY (S_AXIS_TX_TREADY),
.COMPLETER_ID (COMPLETER_ID[15:0]),
.CFG_BUS_MSTR_ENABLE (CFG_BUS_MSTR_ENABLE),
.CFG_LINK_WIDTH (CFG_LINK_WIDTH[5:0]),
.CFG_LINK_RATE (CFG_LINK_RATE[1:0]),
.CFG_MAX_READ_REQUEST_SIZE(CFG_MAX_READ_REQUEST_SIZE[2:0]),
.CFG_MAX_PAYLOAD_SIZE (CFG_MAX_PAYLOAD_SIZE[2:0]),
.CFG_INTERRUPT_MSIEN (CFG_INTERRUPT_MSIEN),
.CFG_INTERRUPT_RDY (CFG_INTERRUPT_RDY),
.RCB (RCB),
.MAX_RC_CPLD (MAX_RC_CPLD[11:0]),
.MAX_RC_CPLH (MAX_RC_CPLH[7:0]),
.RX_ST_DATA (RX_ST_DATA[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (RX_ST_EOP[0:0]),
.RX_ST_VALID (RX_ST_VALID[0:0]),
.RX_ST_SOP (RX_ST_SOP[0:0]),
.RX_ST_EMPTY (RX_ST_EMPTY[0:0]),
.TX_ST_READY (TX_ST_READY),
.TL_CFG_CTL (TL_CFG_CTL[31:0]),
.TL_CFG_ADD (TL_CFG_ADD[3:0]),
.TL_CFG_STS (TL_CFG_STS[52:0]),
.KO_CPL_SPC_HEADER (KO_CPL_SPC_HEADER[7:0]),
.KO_CPL_SPC_DATA (KO_CPL_SPC_DATA[11:0]),
.APP_MSI_ACK (APP_MSI_ACK),
.RX_DATA_READY (RX_DATA_READY),
.TX_DATA (TX_DATA[C_PCI_DATA_WIDTH-1:0]),
.TX_DATA_BYTE_ENABLE (TX_DATA_BYTE_ENABLE[(C_PCI_DATA_WIDTH/8)-1:0]),
.TX_TLP_END_FLAG (TX_TLP_END_FLAG),
.TX_TLP_START_FLAG (TX_TLP_START_FLAG),
.TX_DATA_VALID (TX_DATA_VALID),
.TX_TLP_ERROR_POISON (TX_TLP_ERROR_POISON),
.INTR_MSI_REQUEST (INTR_MSI_REQUEST));
end
endgenerate
endmodule // translation_layer |
module rx_engine_req #(
parameter C_NUM_CHNL = 4'd12,
// Local parameters
parameter C_FIFO_DEPTH = 6*C_NUM_CHNL,
parameter C_WR_DATA_WIDTH = 30+32, // 62
parameter C_RD_DATA_WIDTH = 30+10+4+3+1+1+2+16+8, // 75
parameter C_FIFO_WIDTH = (C_WR_DATA_WIDTH > C_RD_DATA_WIDTH ? C_WR_DATA_WIDTH : C_RD_DATA_WIDTH) + 1
)
(
input CLK,
input RST,
// Received read/write memory requests
output REQ_WR, // Memory write request
input REQ_WR_DONE, // Memory write completed
output REQ_RD, // Memory read request
input REQ_RD_DONE, // Memory read complete
output [9:0] REQ_LEN, // Memory length (1DW)
output [29:0] REQ_ADDR, // Memory address (bottom 2 bits are always 00)
output [31:0] REQ_DATA, // Memory write data
output [3:0] REQ_BE, // Memory byte enables
output [2:0] REQ_TC, // Memory traffic class
output REQ_TD, // Memory packet digest
output REQ_EP, // Memory poisoned packet
output [1:0] REQ_ATTR, // Memory packet relaxed ordering, no snoop
output [15:0] REQ_ID, // Memory requestor id
output [7:0] REQ_TAG, // Memory packet tag
// Memory requests
input WEN, // Memory request write enable
input RNW, // Memory read (not write) request
input [9:0] LEN, // Memory length (1DW)
input [29:0] ADDR, // Memory address (bottom 2 bits are always 00)
input [31:0] DATA, // Memory write data
input [3:0] BE, // Memory byte enables
input [2:0] TC, // Memory traffic class
input TD, // Memory packet digest
input EP, // Memory poisoned packet
input [1:0] ATTR, // Memory packet relaxed ordering, no snoop
input [15:0] ID, // Memory requestor id
input [7:0] TAG // Memory packet tag
);
`include "common_functions.v"
reg [1:0] rState=`S_RXENGREQ_IDLE, _rState=`S_RXENGREQ_IDLE;
reg rRd=0, _rRd=0;
reg rWr=0, _rWr=0;
reg rRen=0, _rRen=0;
reg [29:0] rAddr=0, _rAddr=0;
reg [31:0] rData=0, _rData=0;
reg [2:0] rTC=0, _rTC=0;
reg rTD=0, _rTD=0;
reg rEP=0, _rEP=0;
reg [1:0] rAttr=0, _rAttr=0;
reg [9:0] rLen=0, _rLen=0;
reg [15:0] rId=0, _rId=0;
reg [7:0] rTag=0, _rTag=0;
reg [3:0] rBE=0, _rBE=0;
wire wFifoEmpty;
wire [C_FIFO_WIDTH-1:0] wDataOut;
wire [C_FIFO_WIDTH-1:0] wDataIn = ({LEN, BE, TC, TD, EP, ATTR, ID, TAG, ADDR, RNW, DATA, RNW})>>(33*RNW);
assign REQ_RD = rRd;
assign REQ_WR = rWr;
assign REQ_ADDR = rAddr;
assign REQ_DATA = rData;
assign REQ_BE = rBE;
assign REQ_TC = rTC;
assign REQ_TD = rTD;
assign REQ_EP = rEP;
assign REQ_ATTR = rAttr;
assign REQ_LEN = rLen;
assign REQ_ID = rId;
assign REQ_TAG = rTag;
// FIFO for storing data for read/write requests.
(* RAM_STYLE="DISTRIBUTED" *)
sync_fifo #(.C_WIDTH(C_FIFO_WIDTH), .C_DEPTH(C_FIFO_DEPTH)) fifo (
.RST(RST),
.CLK(CLK),
.WR_EN(WEN),
.WR_DATA(wDataIn),
.FULL(),
.COUNT(),
.RD_EN(rRen),
.RD_DATA(wDataOut),
.EMPTY(wFifoEmpty)
);
// Process writes and reads when the FIFOs are not empty. This will always
// process writes over reads.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_RXENGREQ_IDLE : _rState);
rRd <= #1 (RST ? 1'd0 : _rRd);
rWr <= #1 (RST ? 1'd0 : _rWr);
rRen <= #1 (RST ? 1'd0 : _rRen);
rAddr <= #1 _rAddr;
rData <= #1 _rData;
rLen <= #1 _rLen;
rBE <= #1 _rBE;
rTC <= #1 _rTC;
rTD <= #1 _rTD;
rEP <= #1 _rEP;
rAttr <= #1 _rAttr;
rId <= #1 _rId;
rTag <= #1 _rTag;
end
always @ (*) begin
_rState = rState;
_rRd = rRd;
_rWr = rWr;
_rRen = rRen;
_rAddr = rAddr;
_rData = rData;
_rLen = rLen;
_rBE = rBE;
_rTC = rTC;
_rTD = rTD;
_rEP = rEP;
_rAttr = rAttr;
_rId = rId;
_rTag = rTag;
case (rState)
`S_RXENGREQ_IDLE: begin
if (!wFifoEmpty) begin
_rRen = 1;
_rState = `S_RXENGREQ_PAUSE;
end
end
`S_RXENGREQ_PAUSE: begin
_rRen = 0;
_rState = `S_RXENGREQ_ASSIGN;
end
`S_RXENGREQ_ASSIGN: begin
_rWr = !wDataOut[0]; // !RNW
_rRd = wDataOut[0]; // RNW
if (wDataOut[0]) begin
{_rLen, _rBE, _rTC, _rTD, _rEP, _rAttr, _rId, _rTag, _rAddr} = wDataOut[C_FIFO_WIDTH-1:1];
end
else begin
_rAddr = wDataOut[63:34];
_rData = wDataOut[32:1];
end
_rState = `S_RXENGREQ_WAIT;
end
`S_RXENGREQ_WAIT: begin
if (rWr & REQ_WR_DONE) begin
_rWr = 0;
_rState = `S_RXENGREQ_IDLE;
end
else if (rRd & REQ_RD_DONE) begin
_rRd = 0;
_rState = `S_RXENGREQ_IDLE;
end
end
endcase
end
endmodule |
module pcie_pipe_misc_v6 #
(
parameter PIPE_PIPELINE_STAGES = 0 // 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
)
(
input wire pipe_tx_rcvr_det_i ,
input wire pipe_tx_reset_i ,
input wire pipe_tx_rate_i ,
input wire pipe_tx_deemph_i ,
input wire [2:0] pipe_tx_margin_i ,
input wire pipe_tx_swing_i ,
output wire pipe_tx_rcvr_det_o ,
output wire pipe_tx_reset_o ,
output wire pipe_tx_rate_o ,
output wire pipe_tx_deemph_o ,
output wire [2:0] pipe_tx_margin_o ,
output wire pipe_tx_swing_o ,
input wire pipe_clk ,
input wire rst_n
);
//******************************************************************//
// Reality check. //
//******************************************************************//
localparam TCQ = 1; // clock to out delay model
reg pipe_tx_rcvr_det_q ;
reg pipe_tx_reset_q ;
reg pipe_tx_rate_q ;
reg pipe_tx_deemph_q ;
reg [2:0] pipe_tx_margin_q ;
reg pipe_tx_swing_q ;
reg pipe_tx_rcvr_det_qq ;
reg pipe_tx_reset_qq ;
reg pipe_tx_rate_qq ;
reg pipe_tx_deemph_qq ;
reg [2:0] pipe_tx_margin_qq ;
reg pipe_tx_swing_qq ;
generate
if (PIPE_PIPELINE_STAGES == 0) begin
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_i;
assign pipe_tx_reset_o = pipe_tx_reset_i;
assign pipe_tx_rate_o = pipe_tx_rate_i;
assign pipe_tx_deemph_o = pipe_tx_deemph_i;
assign pipe_tx_margin_o = pipe_tx_margin_i;
assign pipe_tx_swing_o = pipe_tx_swing_i;
end else if (PIPE_PIPELINE_STAGES == 1) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_q;
assign pipe_tx_reset_o = pipe_tx_reset_q;
assign pipe_tx_rate_o = pipe_tx_rate_q;
assign pipe_tx_deemph_o = pipe_tx_deemph_q;
assign pipe_tx_margin_o = pipe_tx_margin_q;
assign pipe_tx_swing_o = pipe_tx_swing_q;
end else if (PIPE_PIPELINE_STAGES == 2) begin
always @(posedge pipe_clk) begin
if (rst_n) begin
pipe_tx_rcvr_det_q <= #TCQ 0;
pipe_tx_reset_q <= #TCQ 1'b1;
pipe_tx_rate_q <= #TCQ 0;
pipe_tx_deemph_q <= #TCQ 1'b1;
pipe_tx_margin_q <= #TCQ 0;
pipe_tx_swing_q <= #TCQ 0;
pipe_tx_rcvr_det_qq <= #TCQ 0;
pipe_tx_reset_qq <= #TCQ 1'b1;
pipe_tx_rate_qq <= #TCQ 0;
pipe_tx_deemph_qq <= #TCQ 1'b1;
pipe_tx_margin_qq <= #TCQ 0;
pipe_tx_swing_qq <= #TCQ 0;
end else begin
pipe_tx_rcvr_det_q <= #TCQ pipe_tx_rcvr_det_i;
pipe_tx_reset_q <= #TCQ pipe_tx_reset_i;
pipe_tx_rate_q <= #TCQ pipe_tx_rate_i;
pipe_tx_deemph_q <= #TCQ pipe_tx_deemph_i;
pipe_tx_margin_q <= #TCQ pipe_tx_margin_i;
pipe_tx_swing_q <= #TCQ pipe_tx_swing_i;
pipe_tx_rcvr_det_qq <= #TCQ pipe_tx_rcvr_det_q;
pipe_tx_reset_qq <= #TCQ pipe_tx_reset_q;
pipe_tx_rate_qq <= #TCQ pipe_tx_rate_q;
pipe_tx_deemph_qq <= #TCQ pipe_tx_deemph_q;
pipe_tx_margin_qq <= #TCQ pipe_tx_margin_q;
pipe_tx_swing_qq <= #TCQ pipe_tx_swing_q;
end
end
assign pipe_tx_rcvr_det_o = pipe_tx_rcvr_det_qq;
assign pipe_tx_reset_o = pipe_tx_reset_qq;
assign pipe_tx_rate_o = pipe_tx_rate_qq;
assign pipe_tx_deemph_o = pipe_tx_deemph_qq;
assign pipe_tx_margin_o = pipe_tx_margin_qq;
assign pipe_tx_swing_o = pipe_tx_swing_qq;
end
endgenerate
endmodule |
module interrupt #(
parameter C_NUM_CHNL = 4'd12
)
(
input CLK,
input RST,
input [C_NUM_CHNL-1:0] RX_SG_BUF_RECVD, // The scatter gather data for a rx_port transaction has been read
input [C_NUM_CHNL-1:0] RX_TXN_DONE, // The rx_port transaction is done
input [C_NUM_CHNL-1:0] TX_TXN, // New tx_port transaction
input [C_NUM_CHNL-1:0] TX_SG_BUF_RECVD, // The scatter gather data for a tx_port transaction has been read
input [C_NUM_CHNL-1:0] TX_TXN_DONE, // The tx_port transaction is done
input VECT_0_RST, // Interrupt vector 0 reset
input VECT_1_RST, // Interrupt vector 1 reset
input [31:0] VECT_RST, // Interrupt vector reset value
output [31:0] VECT_0, // Interrupt vector 0
output [31:0] VECT_1, // Interrupt vector 1
input INTR_LEGACY_CLR, // Pulsed high to ack the legacy interrupt and clear it
input CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_REQUEST are high, interrupt is sent
);
reg [1:0] rState=0;
reg [31:0] rVect0=0;
reg [31:0] rVect1=0;
wire [31:0] wVect0;
wire [31:0] wVect1;
wire wIntr = (rState == `S_INTR_INTR);
wire wIntrDone;
assign VECT_0 = rVect0;
assign VECT_1 = rVect1;
// Align the input signals to the interrupt vector.
// VECT_0/VECT_1 are organized from right to left (LSB to MSB) as:
// [ 0] TX_TXN for channel 0 in VECT_0, channel 6 in VECT_1
// [ 1] TX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
// [ 2] TX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
// [ 3] RX_SG_BUF_RECVD for channel 0 in VECT_0, channel 6 in VECT_1
// [ 4] RX_TXN_DONE for channel 0 in VECT_0, channel 6 in VECT_1
// ...
// [25] TX_TXN for channel 5 in VECT_0, channel 11 in VECT_1
// [26] TX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
// [27] TX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
// [28] RX_SG_BUF_RECVD for channel 5 in VECT_0, channel 11 in VECT_1
// [29] RX_TXN_DONE for channel 5 in VECT_0, channel 11 in VECT_1
// Positions 30 - 31 in both VECT_0 and VECT_1 are zero.
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin: vectMap
if (i < 6) begin : vectMap0
assign wVect0[(5*i)+0] = TX_TXN[i];
assign wVect0[(5*i)+1] = TX_SG_BUF_RECVD[i];
assign wVect0[(5*i)+2] = TX_TXN_DONE[i];
assign wVect0[(5*i)+3] = RX_SG_BUF_RECVD[i];
assign wVect0[(5*i)+4] = RX_TXN_DONE[i];
end
else begin : vectMap1
assign wVect1[(5*(i-6))+0] = TX_TXN[i];
assign wVect1[(5*(i-6))+1] = TX_SG_BUF_RECVD[i];
assign wVect1[(5*(i-6))+2] = TX_TXN_DONE[i];
assign wVect1[(5*(i-6))+3] = RX_SG_BUF_RECVD[i];
assign wVect1[(5*(i-6))+4] = RX_TXN_DONE[i];
end
end
for (i = C_NUM_CHNL; i < 12; i = i + 1) begin: vectZero
if (i < 6) begin : vectZero0
assign wVect0[(5*i)+0] = 1'b0;
assign wVect0[(5*i)+1] = 1'b0;
assign wVect0[(5*i)+2] = 1'b0;
assign wVect0[(5*i)+3] = 1'b0;
assign wVect0[(5*i)+4] = 1'b0;
end
else begin : vectZero1
assign wVect1[(5*(i-6))+0] = 1'b0;
assign wVect1[(5*(i-6))+1] = 1'b0;
assign wVect1[(5*(i-6))+2] = 1'b0;
assign wVect1[(5*(i-6))+3] = 1'b0;
assign wVect1[(5*(i-6))+4] = 1'b0;
end
end
assign wVect0[30] = 1'b0;
assign wVect0[31] = 1'b0;
assign wVect1[30] = 1'b0;
assign wVect1[31] = 1'b0;
endgenerate
// Interrupt controller
interrupt_controller intrCtlr (
.CLK(CLK),
.RST(RST),
.INTR(wIntr),
.INTR_LEGACY_CLR(INTR_LEGACY_CLR),
.INTR_DONE(wIntrDone),
.CFG_INTERRUPT_ASSERT(),
.CONFIG_INTERRUPT_MSIENABLE(CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY(INTR_MSI_RDY),
.INTR_MSI_REQUEST(INTR_MSI_REQUEST)
);
// Update the interrupt vector when new signals come in (pulse in) and on reset.
always @(posedge CLK) begin
if (RST) begin
rVect0 <= #1 0;
rVect1 <= #1 0;
end
else begin
if (VECT_0_RST) begin
rVect0 <= #1 (wVect0 | (rVect0 & ~VECT_RST));
rVect1 <= #1 (wVect1 | rVect1);
end
else if (VECT_1_RST) begin
rVect0 <= #1 (wVect0 | rVect0);
rVect1 <= #1 (wVect1 | (rVect1 & ~VECT_RST));
end
else begin
rVect0 <= #1 (wVect0 | rVect0);
rVect1 <= #1 (wVect1 | rVect1);
end
end
end
// Fire the interrupt when we have a non-zero vector.
always @(posedge CLK) begin
if (RST) begin
rState <= #1 `S_INTR_IDLE;
end
else begin
case (rState)
`S_INTR_IDLE : rState <= #1 ((rVect0 | rVect1) == 0 ? `S_INTR_IDLE : `S_INTR_INTR);
`S_INTR_INTR : rState <= #1 (wIntrDone ? `S_INTR_CLR_0 : `S_INTR_INTR);
`S_INTR_CLR_0 : rState <= #1 (VECT_0_RST ? (C_NUM_CHNL > 6 ? `S_INTR_CLR_1 : `S_INTR_IDLE) : `S_INTR_CLR_0);
`S_INTR_CLR_1 : rState <= #1 (VECT_1_RST ? `S_INTR_IDLE : `S_INTR_CLR_1);
endcase
end
end
endmodule |
module sg_list_reader_64 #(
parameter C_DATA_WIDTH = 9'd64
)
(
input CLK,
input RST,
input [C_DATA_WIDTH-1:0] BUF_DATA, // Scatter gather buffer data
input BUF_DATA_EMPTY, // Scatter gather buffer data empty
output BUF_DATA_REN, // Scatter gather buffer data read enable
output VALID, // Scatter gather element data is valid
output EMPTY, // Scatter gather elements empty
input REN, // Scatter gather element data read enable
output [63:0] ADDR, // Scatter gather element address
output [31:0] LEN // Scatter gather element length (in words)
);
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rRdState=`S_SGR64_RD_0, _rRdState=`S_SGR64_RD_0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [1:0] rCapState=`S_SGR64_CAP_0, _rCapState=`S_SGR64_CAP_0;
reg [C_DATA_WIDTH-1:0] rData={C_DATA_WIDTH{1'd0}}, _rData={C_DATA_WIDTH{1'd0}};
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [31:0] rLen=0, _rLen=0;
reg rFifoValid=0, _rFifoValid=0;
reg rDataValid=0, _rDataValid=0;
assign BUF_DATA_REN = rRdState[0]; // Not S_SGR64_RD_WAIT
assign VALID = rCapState[1]; // S_SGR64_CAP_RDY
assign EMPTY = (BUF_DATA_EMPTY & rRdState[0]); // Not S_SGR64_RD_WAIT
assign ADDR = rAddr;
assign LEN = rLen;
// Capture address and length as it comes out of the FIFO
always @ (posedge CLK) begin
rRdState <= #1 (RST ? `S_SGR64_RD_0 : _rRdState);
rCapState <= #1 (RST ? `S_SGR64_CAP_0 : _rCapState);
rData <= #1 _rData;
rFifoValid <= #1 (RST ? 1'd0 : _rFifoValid);
rDataValid <= #1 (RST ? 1'd0 : _rDataValid);
rAddr <= #1 _rAddr;
rLen <= #1 _rLen;
end
always @ (*) begin
_rRdState = rRdState;
_rCapState = rCapState;
_rAddr = rAddr;
_rLen = rLen;
_rData = BUF_DATA;
_rFifoValid = (BUF_DATA_REN & !BUF_DATA_EMPTY);
_rDataValid = rFifoValid;
case (rCapState)
`S_SGR64_CAP_0: begin
if (rDataValid) begin
_rAddr = rData;
_rCapState = `S_SGR64_CAP_1;
end
end
`S_SGR64_CAP_1: begin
if (rDataValid) begin
_rLen = rData[31:0];
_rCapState = `S_SGR64_CAP_RDY;
end
end
`S_SGR64_CAP_RDY: begin
if (REN)
_rCapState = `S_SGR64_CAP_0;
end
default: begin
_rCapState = `S_SGR64_CAP_0;
end
endcase
case (rRdState)
`S_SGR64_RD_0: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_1;
end
`S_SGR64_RD_1: begin // Read from the sg data FIFO
if (!BUF_DATA_EMPTY)
_rRdState = `S_SGR64_RD_WAIT;
end
`S_SGR64_RD_WAIT: begin // Wait for the data to be consumed
if (REN)
_rRdState = `S_SGR64_RD_0;
end
default: begin
_rRdState = `S_SGR64_RD_0;
end
endcase
end
endmodule |
module pcie_bram_v6
#(
parameter DOB_REG = 0,// 1 use the output register 0 don't use the output register
parameter WIDTH = 0 // supported WIDTH's are: 4, 9, 18, 36 (uses RAMB36) and 72 (uses RAMB36SDP)
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = "NO_CHANGE";
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if (WIDTH == 72) begin : use_ramb36sdp
// use RAMB36SDP if the width is 72
RAMB36SDP #(
.DO_REG (DOB_REG)
)
ramb36sdp(
.WRCLK (user_clk_i),
.SSR (1'b0),
.WRADDR (waddr_i[ADDR_MSB:0]),
.DI (wdata_i[D_MSB:0]),
.DIP (wdata_i[DP_MSB:DP_LSB]),
.WREN (wen_i),
.WE ({8{wen_i}}),
.DBITERR (),
.ECCPARITY (),
.SBITERR (),
.RDCLK (user_clk_i),
.RDADDR (raddr_i[ADDR_MSB:0]),
.DO (rdata_o[D_MSB:0]),
.DOP (rdata_o[DP_MSB:DP_LSB]),
.RDEN (ren_i),
.REGCE (rce_i)
);
// use RAMB36's if the width is 4, 9, 18, or 36
end else if (WIDTH == 36) begin : use_ramb36
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA (wdata_i[D_MSB:0]),
.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB (rdata_o[D_MSB:0]),
.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH < 36 && WIDTH > 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
wire [ 4 - DPW - 1 : 0] dopb_unused;
RAMB36 #(
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
.DIPA ({{ 4 - DPW {1'b0}},wdata_i[DP_MSB:DP_LSB]}),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.DIB (32'b0),
.DIPB ( 4'b0),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused, rdata_o[D_MSB:0]}),
.DOPB ({dopb_unused, rdata_o[DP_MSB:DP_LSB]}),
.ENB (ren_i),
.REGCEB (rce_i)
);
end else if (WIDTH == 4) begin : use_ramb36
wire [31 - D_MSB - 1 : 0] dob_unused;
RAMB36 #(
.DOB_REG (DOB_REG),
.READ_WIDTH_A (0),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (0),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.CLKA (user_clk_i),
.SSRA (1'b0),
.REGCEA (1'b0),
.CASCADEINLATA (1'b0),
.CASCADEINREGA (1'b0),
.CASCADEOUTLATA (),
.CASCADEOUTREGA (),
.DOA (),
.DOPA (),
.ADDRA ({1'b1, waddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DIA ({{31 - D_MSB{1'b0}},wdata_i[D_MSB:0]}),
//.DIPA (wdata_i[DP_MSB:DP_LSB]),
.ENA (wen_i),
.WEA ({4{wen_i}}),
.CLKB (user_clk_i),
.SSRB (1'b0),
.WEB (4'b0),
.CASCADEINLATB (1'b0),
.CASCADEINREGB (1'b0),
.CASCADEOUTLATB (),
.CASCADEOUTREGB (),
.ADDRB ({1'b1, raddr_i[ADDR_MSB:0], {ADDR_LO_BITS{1'b1}}}),
.DOB ({dob_unused,rdata_o[D_MSB:0]}),
//.DOPB (rdata_o[DP_MSB:DP_LSB]),
.ENB (ren_i),
.REGCEB (rce_i)
);
end // block: use_ramb36
endgenerate
endmodule // pcie_bram_v6 |
module translation_layer_32
#(parameter C_ALTERA = 1'b1,
parameter C_PCI_DATA_WIDTH = 10'd32)
(
input CLK,
input RST_IN,
// Xilinx Signals
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RX_TDATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] M_AXIS_RX_TKEEP,
input M_AXIS_RX_TLAST, // Not used in the 128 bit interface
input M_AXIS_RX_TVALID,
output M_AXIS_RX_TREADY,
input [(C_PCI_DATA_WIDTH/32):0] IS_SOF,
input [(C_PCI_DATA_WIDTH/32):0] IS_EOF,
input RERR_FWD,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_TX_TDATA,
output [(C_PCI_DATA_WIDTH/8)-1:0] S_AXIS_TX_TKEEP,
output S_AXIS_TX_TLAST,
output S_AXIS_TX_TVALID,
output S_AXIS_SRC_DSC,
input S_AXIS_TX_TREADY,
input [15:0] COMPLETER_ID,
input CFG_BUS_MSTR_ENABLE,
input [5:0] CFG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
input [1:0] CFG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
input [2:0] CFG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
input [2:0] CFG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
input CFG_INTERRUPT_MSIEN, // 1 if MSI interrupts are enable, 0 if only legacy are supported
input CFG_INTERRUPT_RDY, // High when interrupt is able to be sent
output CFG_INTERRUPT, // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high, interrupt is sent)
input RCB,
input [11:0] MAX_RC_CPLD, // Receive credit limit for data (be sure fc_sel == 001)
input [7:0] MAX_RC_CPLH, // Receive credit limit for headers (be sure fc_sel == 001)
// Altera Signals
input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA,
input [0:0] RX_ST_EOP,
input [0:0] RX_ST_VALID,
output RX_ST_READY,
input [0:0] RX_ST_SOP,
input [0:0] RX_ST_EMPTY,
output [C_PCI_DATA_WIDTH-1:0] TX_ST_DATA,
output [0:0] TX_ST_VALID,
input TX_ST_READY,
output [0:0] TX_ST_EOP,
output [0:0] TX_ST_SOP,
output [0:0] TX_ST_EMPTY,
input [31:0] TL_CFG_CTL,
input [3:0] TL_CFG_ADD,
input [52:0] TL_CFG_STS,
input [7:0] KO_CPL_SPC_HEADER,
input [11:0] KO_CPL_SPC_DATA,
input APP_MSI_ACK,
output APP_MSI_REQ,
// Unified Signals
output [C_PCI_DATA_WIDTH-1:0] RX_DATA,
output RX_DATA_VALID,
input RX_DATA_READY,
output [(C_PCI_DATA_WIDTH/8)-1:0] RX_DATA_BYTE_ENABLE,
output RX_TLP_END_FLAG,
output [3:0] RX_TLP_END_OFFSET,
output RX_TLP_START_FLAG,
output [3:0] RX_TLP_START_OFFSET,
output RX_TLP_ERROR_POISON,
input [C_PCI_DATA_WIDTH-1:0] TX_DATA,
input [(C_PCI_DATA_WIDTH/8)-1:0] TX_DATA_BYTE_ENABLE,
input TX_TLP_END_FLAG,
input TX_DATA_VALID,
input TX_TLP_ERROR_POISON,
output TX_DATA_READY,
output [15:0] CONFIG_COMPLETER_ID,
output CONFIG_BUS_MASTER_ENABLE,
output [5:0] CONFIG_LINK_WIDTH, // cfg_lstatus[9:4] (from Link Status Register): 000001=x1, 000010=x2, 000100=x4, 001000=x8, 001100=x12, 010000=x16, 100000=x32, others=?
output [1:0] CONFIG_LINK_RATE, // cfg_lstatus[1:0] (from Link Status Register): 01=2.5GT/s, 10=5.0GT/s, others=?
output [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // cfg_dcommand[14:12] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output [2:0] CONFIG_MAX_PAYLOAD_SIZE, // cfg_dcommand[7:5] (from Device Control Register): 000=128B, 001=256B, 010=512B, 011=1024B
output CONFIG_INTERRUPT_MSIENABLE, // 1 if MSI interrupts are enable, 0 if only legacy are supported
output [11:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
output [7:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
output CONFIG_CPL_BOUNDARY_SEL, // Read completion boundary (0=64 bytes, 1=128 byte
output INTR_MSI_RDY, // High when interrupt is able to be sent
input INTR_MSI_REQUEST // High to request interrupt, when both CFG_INTERRUPT_RDY and CFG_INTERRUPT are high
);
generate
if(C_ALTERA == 1'b1) begin : altera_translator_32
// If you have reached here, something has gone
// horrendously wrong. Altera does not have a 32-bit PCIE
// interface. Please adapt your application and try again.
end else begin : xilinx_translator_32
// Rx Interface (From PCIe Core)
assign RX_DATA = M_AXIS_RX_TDATA;
assign RX_DATA_VALID = M_AXIS_RX_TVALID;
assign RX_DATA_BYTE_ENABLE = M_AXIS_RX_TKEEP;
assign RX_TLP_END_FLAG = M_AXIS_RX_TLAST;
assign RX_TLP_END_OFFSET = M_AXIS_RX_TKEEP[3];
assign RX_TLP_START_FLAG = 1'd0;
assign RX_TLP_START_OFFSET = 4'h0;
assign RX_TLP_ERROR_POISON = RERR_FWD;
// Rx Interface (To PCIe Core)
assign M_AXIS_RX_TREADY = RX_DATA_READY;
// TX Interface (From PCIe Core)
assign TX_DATA_READY = S_AXIS_TX_TREADY;
// TX Interface (TO PCIe Core)
assign S_AXIS_TX_TDATA = TX_DATA;
assign S_AXIS_TX_TVALID = TX_DATA_VALID;
assign S_AXIS_TX_TKEEP = TX_DATA_BYTE_ENABLE;
assign S_AXIS_TX_TLAST = TX_TLP_END_FLAG;
assign S_AXIS_SRC_DSC = TX_TLP_ERROR_POISON;
// Configuration Interface
assign CONFIG_COMPLETER_ID = COMPLETER_ID;
assign CONFIG_BUS_MASTER_ENABLE = CFG_BUS_MSTR_ENABLE;
assign CONFIG_LINK_WIDTH = CFG_LINK_WIDTH;
assign CONFIG_LINK_RATE = CFG_LINK_RATE;
assign CONFIG_MAX_READ_REQUEST_SIZE = CFG_MAX_READ_REQUEST_SIZE;
assign CONFIG_MAX_PAYLOAD_SIZE = CFG_MAX_PAYLOAD_SIZE;
assign CONFIG_INTERRUPT_MSIENABLE = CFG_INTERRUPT_MSIEN;
assign CONFIG_CPL_BOUNDARY_SEL = RCB;
assign CONFIG_MAX_CPL_DATA = MAX_RC_CPLD;
assign CONFIG_MAX_CPL_HDR = MAX_RC_CPLH;
// Interrupt interface
assign CFG_INTERRUPT = INTR_MSI_REQUEST;
assign INTR_MSI_RDY = CFG_INTERRUPT_RDY;
end
endgenerate
endmodule |
module axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digist: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd2;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd2;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule |
module GTX_DRP_CHANALIGN_FIX_3752_V6
#(
parameter TCQ = 1,
parameter C_SIMULATION = 0 // Set to 1 for simulation
)
(
output reg dwe,
output reg [15:0] din, //THIS IS THE INPUT TO THE DRP
output reg den,
output reg [7:0] daddr,
output reg [3:0] drpstate,
input write_ts1,
input write_fts,
input [15:0] dout, //THIS IS THE OUTPUT OF THE DRP
input drdy,
input Reset_n,
input drp_clk
);
reg [7:0] next_daddr;
reg [3:0] next_drpstate;
reg write_ts1_gated;
reg write_fts_gated;
localparam DRP_IDLE_FTS = 1;
localparam DRP_IDLE_TS1 = 2;
localparam DRP_RESET = 3;
localparam DRP_WRITE_FTS = 6;
localparam DRP_WRITE_DONE_FTS = 7;
localparam DRP_WRITE_TS1 = 8;
localparam DRP_WRITE_DONE_TS1 = 9;
localparam DRP_COM = 10'b0110111100;
localparam DRP_FTS = 10'b0100111100;
localparam DRP_TS1 = 10'b0001001010;
always @(posedge drp_clk) begin
if ( ~Reset_n ) begin
daddr <= #(TCQ) 8'h8;
drpstate <= #(TCQ) DRP_RESET;
write_ts1_gated <= #(TCQ) 0;
write_fts_gated <= #(TCQ) 0;
end else begin
daddr <= #(TCQ) next_daddr;
drpstate <= #(TCQ) next_drpstate;
write_ts1_gated <= #(TCQ) write_ts1;
write_fts_gated <= #(TCQ) write_fts;
end
end
always @(*) begin
// DEFAULT CONDITIONS
next_drpstate=drpstate;
next_daddr=daddr;
den=0;
din=0;
dwe=0;
case(drpstate)
// RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
DRP_RESET : begin
next_drpstate= DRP_WRITE_TS1;
next_daddr=8'h8;
end
// WRITE FTS SEQUENCE
DRP_WRITE_FTS : begin
den=1;
dwe=1;
case (daddr)
8'h8 : din = 16'hFD3C;
8'h9 : din = 16'hC53C;
8'hA : din = 16'hFDBC;
8'hB : din = 16'h853C;
endcase
next_drpstate=DRP_WRITE_DONE_FTS;
end
// WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
DRP_WRITE_DONE_FTS : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_FTS;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=daddr+1'b1;
end
end
end
// FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
DRP_IDLE_FTS : begin
if(write_ts1_gated) begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=8'h8;
end
end
// WRITE TS1 SEQUENCE
DRP_WRITE_TS1 : begin
den=1;
dwe=1;
case (daddr)
8'h8 : din = 16'hFC4A;
8'h9 : din = 16'hDC4A;
8'hA : din = 16'hC04A;
8'hB : din = 16'h85BC;
endcase
next_drpstate=DRP_WRITE_DONE_TS1;
end
// WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
DRP_WRITE_DONE_TS1 : begin
if(drdy) begin
if(daddr==8'hB) begin
next_drpstate=DRP_IDLE_TS1;
next_daddr=8'h8;
end else begin
next_drpstate=DRP_WRITE_TS1;
next_daddr=daddr+1'b1;
end
end
end
// TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
DRP_IDLE_TS1 : begin
if(write_fts_gated) begin
next_drpstate=DRP_WRITE_FTS;
next_daddr=8'h8;
end
end
endcase
end
endmodule |
module axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule |
module axi_basic_tx_thrtl_ctl #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter TCQ = 1 // Clock to Q time
) (
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
input [3:0] s_axis_tx_tuser, // TX user signals
input s_axis_tx_tlast, // TX data is last
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
// TRN TX
//-----------
input [5:0] trn_tbuf_av, // TX buffers available
input trn_tdst_rdy, // TX destination ready
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // TX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output reg cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output reg tready_thrtl, // TREADY to pipeline
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Thrtl user when TBUF hits this val
localparam TBUF_AV_MIN = (C_DATA_WIDTH == 128) ? 5 :
(C_DATA_WIDTH == 64) ? 1 : 0;
// Pause user when TBUF hits this val
localparam TBUF_AV_GAP = TBUF_AV_MIN + 1;
// GAP pause time - the latency from the time a packet is accepted on the TRN
// interface to the time trn_tbuf_av from the Block will decrement.
localparam TBUF_GAP_TIME = (C_DATA_WIDTH == 128) ? 4 : 1;
// Latency time from when tcfg_gnt is asserted to when PCIe block will throttle
localparam TCFG_LATENCY_TIME = 2'd2;
// Number of pipeline stages to delay trn_tcfg_gnt. For V6 128-bit only
localparam TCFG_GNT_PIPE_STAGES = 3;
// Throttle condition registers and constants
reg lnk_up_thrtl;
wire lnk_up_trig;
wire lnk_up_exit;
reg tbuf_av_min_thrtl;
wire tbuf_av_min_trig;
reg tbuf_av_gap_thrtl;
reg [2:0] tbuf_gap_cnt;
wire tbuf_av_gap_trig;
wire tbuf_av_gap_exit;
wire gap_trig_tlast;
wire gap_trig_decr;
reg [5:0] tbuf_av_d;
reg tcfg_req_thrtl;
reg [1:0] tcfg_req_cnt;
reg trn_tdst_rdy_d;
wire tcfg_req_trig;
wire tcfg_req_exit;
reg tcfg_gnt_log;
wire pre_throttle;
wire reg_throttle;
wire exit_crit;
reg reg_tcfg_gnt;
reg trn_tcfg_req_d;
reg tcfg_gnt_pending;
wire wire_to_turnoff;
reg reg_turnoff_ok;
reg tready_thrtl_mux;
localparam LINKSTATE_L0 = 3'b000;
localparam LINKSTATE_PPM_L1 = 3'b001;
localparam LINKSTATE_PPM_L1_TRANS = 3'b101;
localparam LINKSTATE_PPM_L23R_TRANS = 3'b110;
localparam PM_ENTER_L1 = 8'h20;
localparam POWERSTATE_D0 = 2'b00;
reg ppm_L1_thrtl;
wire ppm_L1_trig;
wire ppm_L1_exit;
reg [2:0] cfg_pcie_link_state_d;
reg trn_rdllp_src_rdy_d;
reg ppm_L23_thrtl;
wire ppm_L23_trig;
reg cfg_turnoff_ok_pending;
reg reg_tlast;
// Throttle control state machine states and registers
localparam IDLE = 0;
localparam THROTTLE = 1;
reg cur_state;
reg next_state;
reg reg_axi_in_pkt;
wire axi_in_pkt;
wire axi_pkt_ending;
wire axi_throttled;
wire axi_thrtl_ok;
wire tx_ecrc_pause;
//----------------------------------------------------------------------------//
// THROTTLE REASON: PCIe link is down //
// - When to throttle: trn_lnk_up deasserted //
// - When to stop: trn_tdst_rdy assesrted //
//----------------------------------------------------------------------------//
assign lnk_up_trig = !trn_lnk_up;
assign lnk_up_exit = trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else begin
if(lnk_up_trig) begin
lnk_up_thrtl <= #TCQ 1'b1;
end
else if(lnk_up_exit) begin
lnk_up_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers depleted //
// - When to throttle: trn_tbuf_av falls to 0 //
// - When to stop: trn_tbuf_av rises above 0 again //
//----------------------------------------------------------------------------//
assign tbuf_av_min_trig = (trn_tbuf_av <= TBUF_AV_MIN);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
else begin
if(tbuf_av_min_trig) begin
tbuf_av_min_thrtl <= #TCQ 1'b1;
end
// The exit condition for tbuf_av_min_thrtl is !tbuf_av_min_trig
else begin
tbuf_av_min_thrtl <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Transmit buffers getting low //
// - When to throttle: trn_tbuf_av falls below "gap" threshold TBUF_AV_GAP //
// - When to stop: after TBUF_GAP_TIME cycles elapse //
// //
// If we're about to run out of transmit buffers, throttle the user for a //
// few clock cycles to give the PCIe block time to catch up. This is //
// needed to compensate for latency in decrementing trn_tbuf_av in the PCIe //
// Block transmit path. //
//----------------------------------------------------------------------------//
// Detect two different scenarios for buffers getting low:
// 1) If we see a TLAST. a new packet has been inserted into the buffer, and
// we need to pause and let that packet "soak in"
assign gap_trig_tlast = (trn_tbuf_av <= TBUF_AV_GAP) &&
s_axis_tx_tvalid && tready_thrtl && s_axis_tx_tlast;
// 2) Any time tbug_avail decrements to the TBUF_AV_GAP threshold, we need to
// pause and make sure no other packets are about to soak in and cause the
// buffer availability to drop further.
assign gap_trig_decr = (trn_tbuf_av == (TBUF_AV_GAP)) &&
(tbuf_av_d == (TBUF_AV_GAP+1));
assign gap_trig_tcfg = (tcfg_req_thrtl && tcfg_req_exit);
assign tbuf_av_gap_trig = gap_trig_tlast || gap_trig_decr || gap_trig_tcfg;
assign tbuf_av_gap_exit = (tbuf_gap_cnt == 0);
always @(posedge user_clk) begin
if(user_rst) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
tbuf_gap_cnt <= #TCQ 3'h0;
tbuf_av_d <= #TCQ 6'h00;
end
else begin
if(tbuf_av_gap_trig) begin
tbuf_av_gap_thrtl <= #TCQ 1'b1;
end
else if(tbuf_av_gap_exit) begin
tbuf_av_gap_thrtl <= #TCQ 1'b0;
end
// tbuf gap counter:
// This logic controls the length of the throttle condition when tbufs are
// getting low.
if(tbuf_av_gap_thrtl && (cur_state == THROTTLE)) begin
if(tbuf_gap_cnt > 0) begin
tbuf_gap_cnt <= #TCQ tbuf_gap_cnt - 3'd1;
end
end
else begin
tbuf_gap_cnt <= #TCQ TBUF_GAP_TIME;
end
tbuf_av_d <= #TCQ trn_tbuf_av;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to send a CFG response //
// - When to throttle: trn_tcfg_req and user_tcfg_gnt asserted //
// - When to stop: after trn_tdst_rdy transitions to unasserted //
// //
// If the block needs to send a response to a CFG packet, this will cause //
// the subsequent deassertion of trn_tdst_rdy. When the user design permits, //
// grant permission to the block to service request and throttle the user. //
//----------------------------------------------------------------------------//
assign tcfg_req_trig = trn_tcfg_req && reg_tcfg_gnt;
assign tcfg_req_exit = (tcfg_req_cnt == 2'd0) && !trn_tdst_rdy_d &&
trn_tdst_rdy;
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_req_thrtl <= #TCQ 1'b0;
trn_tcfg_req_d <= #TCQ 1'b0;
trn_tdst_rdy_d <= #TCQ 1'b1;
reg_tcfg_gnt <= #TCQ 1'b0;
tcfg_req_cnt <= #TCQ 2'd0;
tcfg_gnt_pending <= #TCQ 1'b0;
end
else begin
if(tcfg_req_trig) begin
tcfg_req_thrtl <= #TCQ 1'b1;
end
else if(tcfg_req_exit) begin
tcfg_req_thrtl <= #TCQ 1'b0;
end
// We need to wait the appropriate amount of time for the tcfg_gnt to
// "sink in" to the PCIe block. After that, we know that the PCIe block will
// not reassert trn_tdst_rdy until the CFG request has been serviced. If a
// new request is being service (tcfg_gnt_log == 1), then reset the timer.
if((trn_tcfg_req && !trn_tcfg_req_d) || tcfg_gnt_pending) begin
tcfg_req_cnt <= #TCQ TCFG_LATENCY_TIME;
end
else begin
if(tcfg_req_cnt > 0) begin
tcfg_req_cnt <= #TCQ tcfg_req_cnt - 2'd1;
end
end
// Make sure tcfg_gnt_log pulses once for one clock cycle for every
// cfg packet request.
if(trn_tcfg_req && !trn_tcfg_req_d) begin
tcfg_gnt_pending <= #TCQ 1'b1;
end
else if(tcfg_gnt_log) begin
tcfg_gnt_pending <= #TCQ 1'b0;
end
trn_tcfg_req_d <= #TCQ trn_tcfg_req;
trn_tdst_rdy_d <= #TCQ trn_tdst_rdy;
reg_tcfg_gnt <= #TCQ user_tcfg_gnt;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L1 //
// - When to throttle: appropriate low power state signal asserted //
// (architecture dependent) //
// - When to stop: cfg_pcie_link_state goes to proper value (C_ROOT_PORT //
// dependent) //
// //
// If the block needs to transition to PM state PPM L1, we need to finish //
// up what we're doing and throttle immediately. //
//----------------------------------------------------------------------------//
generate
// PPM L1 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L1_thrtl_rp
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for 7 Series in EP mode
else if((C_FAMILY == "X7") && (C_ROOT_PORT == "FALSE")) begin : x7_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pcie_link_state_d == LINKSTATE_L0) &&
(cfg_pcie_link_state == LINKSTATE_PPM_L1_TRANS);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L1_thrtl_rp
assign ppm_L1_trig = (trn_rdllp_data[31:24] == PM_ENTER_L1) &&
trn_rdllp_src_rdy && !trn_rdllp_src_rdy_d;
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_PPM_L1;
end
// PPM L1 signals for V6 in EP mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "FALSE")) begin : v6_L1_thrtl_ep
assign ppm_L1_trig = (cfg_pmcsr_powerstate != POWERSTATE_D0);
assign ppm_L1_exit = cfg_pcie_link_state == LINKSTATE_L0;
end
// PPM L1 detection not supported for S6
else begin : s6_L1_thrtl
assign ppm_L1_trig = 1'b0;
assign ppm_L1_exit = 1'b1;
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L1_thrtl <= #TCQ 1'b0;
cfg_pcie_link_state_d <= #TCQ 3'b0;
trn_rdllp_src_rdy_d <= #TCQ 1'b0;
end
else begin
if(ppm_L1_trig) begin
ppm_L1_thrtl <= #TCQ 1'b1;
end
else if(ppm_L1_exit) begin
ppm_L1_thrtl <= #TCQ 1'b0;
end
cfg_pcie_link_state_d <= #TCQ cfg_pcie_link_state;
trn_rdllp_src_rdy_d <= #TCQ trn_rdllp_src_rdy;
end
end
//----------------------------------------------------------------------------//
// THROTTLE REASON: Block needs to transition to low power state PPM L2/3 //
// - When to throttle: appropriate PM signal indicates a transition to //
// L2/3 is pending or in progress (family and role dependent) //
// - When to stop: never (the only path out of L2/3 is a full reset) //
// //
// If the block needs to transition to PM state PPM L2/3, we need to finish //
// up what we're doing and throttle when the user gives permission. //
//----------------------------------------------------------------------------//
generate
// PPM L2/3 signals for 7 Series in RC mode
if((C_FAMILY == "X7") && (C_ROOT_PORT == "TRUE")) begin : x7_L23_thrtl_rp
assign ppm_L23_trig = (cfg_pcie_link_state_d == LINKSTATE_PPM_L23R_TRANS);
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals for V6 in RC mode
else if((C_FAMILY == "V6") && (C_ROOT_PORT == "TRUE")) begin : v6_L23_thrtl_rp
assign ppm_L23_trig = cfg_pm_send_pme_to;
assign wire_to_turnoff = 1'b0;
end
// PPM L2/3 signals in EP mode
else begin : L23_thrtl_ep
assign ppm_L23_trig = wire_to_turnoff && reg_turnoff_ok;
// PPM L2/3 signals for 7 Series in EP mode
// For 7 Series, cfg_to_turnoff pulses once when a turnoff request is
// outstanding, so we need a "sticky" register that grabs the request.
if(C_FAMILY == "X7") begin : x7_L23_thrtl_ep
reg reg_to_turnoff;
always @(posedge user_clk) begin
if(user_rst) begin
reg_to_turnoff <= #TCQ 1'b0;
end
else begin
if(cfg_to_turnoff) begin
reg_to_turnoff <= #TCQ 1'b1;
end
end
end
assign wire_to_turnoff = reg_to_turnoff;
end
// PPM L2/3 signals for V6/S6 in EP mode
// In V6 and S6, the to_turnoff signal asserts and remains asserted until
// turnoff_ok is asserted, so a sticky reg is not necessary.
else begin : v6_s6_L23_thrtl_ep
assign wire_to_turnoff = cfg_to_turnoff;
end
always @(posedge user_clk) begin
if(user_rst) begin
reg_turnoff_ok <= #TCQ 1'b0;
end
else begin
reg_turnoff_ok <= #TCQ user_turnoff_ok;
end
end
end
endgenerate
always @(posedge user_clk) begin
if(user_rst) begin
ppm_L23_thrtl <= #TCQ 1'b0;
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
else begin
if(ppm_L23_trig) begin
ppm_L23_thrtl <= #TCQ 1'b1;
end
// Make sure cfg_turnoff_ok pulses once for one clock cycle for every
// turnoff request.
if(ppm_L23_trig && !ppm_L23_thrtl) begin
cfg_turnoff_ok_pending <= #TCQ 1'b1;
end
else if(cfg_turnoff_ok) begin
cfg_turnoff_ok_pending <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_thrtl_ok. This signal determines if it's OK to throttle the //
// user design on the AXI interface. Since TREADY is registered, this signal //
// needs to assert on the cycle ~before~ we actually intend to throttle. //
// The only time it's OK to throttle when TVALID is asserted is on the first //
// beat of a new packet. Therefore, assert axi_thrtl_ok if one of the //
// is true: //
// 1) The user is not in a packet and is not starting one //
// 2) The user is just finishing a packet //
// 3) We're already throttled, so it's OK to continue throttling //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else begin
if(s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_axi_in_pkt <= #TCQ 1'b0;
end
else if(tready_thrtl && s_axis_tx_tvalid) begin
reg_axi_in_pkt <= #TCQ 1'b1;
end
end
end
assign axi_in_pkt = s_axis_tx_tvalid || reg_axi_in_pkt;
assign axi_pkt_ending = s_axis_tx_tvalid && s_axis_tx_tlast;
assign axi_throttled = !tready_thrtl;
assign axi_thrtl_ok = !axi_in_pkt || axi_pkt_ending || axi_throttled;
//----------------------------------------------------------------------------//
// Throttle CTL State Machine: //
// Throttle user design when a throttle trigger (or triggers) occur. //
// Keep user throttled until all exit criteria have been met. //
//----------------------------------------------------------------------------//
// Immediate throttle signal. Used to "pounce" on a throttle opportunity when
// we're seeking one
assign pre_throttle = tbuf_av_min_trig || tbuf_av_gap_trig || lnk_up_trig
|| tcfg_req_trig || ppm_L1_trig || ppm_L23_trig;
// Registered throttle signals. Used to control throttle state machine
assign reg_throttle = tbuf_av_min_thrtl || tbuf_av_gap_thrtl || lnk_up_thrtl
|| tcfg_req_thrtl || ppm_L1_thrtl || ppm_L23_thrtl;
assign exit_crit = !tbuf_av_min_thrtl && !tbuf_av_gap_thrtl && !lnk_up_thrtl
&& !tcfg_req_thrtl && !ppm_L1_thrtl && !ppm_L23_thrtl;
always @(*) begin
case(cur_state)
// IDLE: in this state we're waiting for a trigger event to occur. As
// soon as an event occurs and the user isn't transmitting a packet, we
// throttle the PCIe block and the user and next state is THROTTLE.
IDLE: begin
if(reg_throttle && axi_thrtl_ok) begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(ppm_L23_thrtl) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
// If there's not throttle event, do nothing
else begin
// Throttle user as soon as possible
tready_thrtl_mux = !(axi_thrtl_ok && pre_throttle);
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
end
// THROTTLE: in this state the user is throttle and we're waiting for
// exit criteria, which tells us that the throttle event is over. When
// the exit criteria is satisfied, de-throttle the user and next state
// is IDLE.
THROTTLE: begin
if(exit_crit) begin
// Dethrottle user
tready_thrtl_mux = !pre_throttle;
next_state = IDLE;
end
else begin
// Throttle user
tready_thrtl_mux = 1'b0;
next_state = THROTTLE;
end
// Assert appropriate grant signal depending on the throttle type.
if(tcfg_req_thrtl && tcfg_gnt_pending) begin
tcfg_gnt_log = 1'b1; // For cfg request, grant the request
cfg_turnoff_ok = 1'b0; //
end
else if(cfg_turnoff_ok_pending) begin
tcfg_gnt_log = 1'b0; //
cfg_turnoff_ok = 1'b1; // For PM request, permit transition
end
else begin
tcfg_gnt_log = 1'b0; // Otherwise do nothing
cfg_turnoff_ok = 1'b0; //
end
end
default: begin
tready_thrtl_mux = 1'b0;
next_state = IDLE;
tcfg_gnt_log = 1'b0;
cfg_turnoff_ok = 1'b0;
end
endcase
end
// Synchronous logic
always @(posedge user_clk) begin
if(user_rst) begin
// Throttle user by default until link comes up
cur_state <= #TCQ THROTTLE;
reg_tlast <= #TCQ 1'b0;
tready_thrtl <= #TCQ 1'b0;
end
else begin
cur_state <= #TCQ next_state;
tready_thrtl <= #TCQ tready_thrtl_mux && !tx_ecrc_pause;
reg_tlast <= #TCQ s_axis_tx_tlast;
end
end
// For X7, the PCIe block will generate the ECRC for a packet if trn_tecrc_gen
// is asserted at SOF. In this case, the Block needs an extra data beat to
// calculate the ECRC, but only if the following conditions are met:
// 1) there is no empty DWORDS at the end of the packet
// (i.e. packet length % C_DATA_WIDTH == 0)
//
// 2) There isn't a ECRC in the TLP already, as indicated by the TD bit in the
// TLP header
//
// If both conditions are met, the Block will stall the TRN interface for one
// data beat after EOF. We need to predict this stall and preemptively stall the
// User for one beat.
generate
if(C_FAMILY == "X7") begin : ecrc_pause_enabled
wire tx_ecrc_pkt;
reg reg_tx_ecrc_pkt;
wire [1:0] packet_fmt;
wire packet_td;
wire [2:0] header_len;
wire [9:0] payload_len;
wire [13:0] packet_len;
wire pause_needed;
// Grab necessary packet fields
assign packet_fmt = s_axis_tx_tdata[30:29];
assign packet_td = s_axis_tx_tdata[15];
// Calculate total packet length
assign header_len = packet_fmt[0] ? 3'd4 : 3'd3;
assign payload_len = packet_fmt[1] ? s_axis_tx_tdata[9:0] : 10'h0;
assign packet_len = {10'h000, header_len} + {4'h0, payload_len};
// Determine if packet a ECRC pause is needed
if(C_DATA_WIDTH == 128) begin : packet_len_check_128
assign pause_needed = (packet_len[1:0] == 2'b00) && !packet_td;
end
else begin : packet_len_check_64
assign pause_needed = (packet_len[0] == 1'b0) && !packet_td;
end
// Create flag to alert TX pipeline to insert a stall
assign tx_ecrc_pkt = s_axis_tx_tuser[0] && pause_needed &&
tready_thrtl && s_axis_tx_tvalid && !reg_axi_in_pkt;
always @(posedge user_clk) begin
if(user_rst) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
else begin
if(tx_ecrc_pkt && !s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b1;
end
else if(tready_thrtl && s_axis_tx_tvalid && s_axis_tx_tlast) begin
reg_tx_ecrc_pkt <= #TCQ 1'b0;
end
end
end
// Insert the stall now
assign tx_ecrc_pause = ((tx_ecrc_pkt || reg_tx_ecrc_pkt) &&
s_axis_tx_tlast && s_axis_tx_tvalid && tready_thrtl);
end
else begin : ecrc_pause_disabled
assign tx_ecrc_pause = 1'b0;
end
endgenerate
// Logic for 128-bit single cycle bug fix.
// This tcfg_gnt pipeline addresses an issue with 128-bit V6 designs where a
// single cycle packet transmitted simultaneously with an assertion of tcfg_gnt
// from AXI Basic causes the packet to be dropped. The packet drop occurs
// because the 128-bit shim doesn't know about the tcfg_req/gnt, and therefor
// isn't expecting trn_tdst_rdy to go low. Since the 128-bit shim does throttle
// prediction just as we do, it ignores the value of trn_tdst_rdy, and
// ultimately drops the packet when transmitting the packet to the block.
generate
if(C_DATA_WIDTH == 128 && C_FAMILY == "V6") begin : tcfg_gnt_pipeline
genvar stage;
reg tcfg_gnt_pipe [TCFG_GNT_PIPE_STAGES:0];
// Create a configurable depth FF delay pipeline
for(stage = 0; stage < TCFG_GNT_PIPE_STAGES; stage = stage + 1)
begin : tcfg_gnt_pipeline_stage
always @(posedge user_clk) begin
if(user_rst) begin
tcfg_gnt_pipe[stage] <= #TCQ 1'b0;
end
else begin
// For stage 0, insert the actual tcfg_gnt signal from logic
if(stage == 0) begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_log;
end
// For stages 1+, chain together
else begin
tcfg_gnt_pipe[stage] <= #TCQ tcfg_gnt_pipe[stage - 1];
end
end
end
// tcfg_gnt output to block assigned the last pipeline stage
assign trn_tcfg_gnt = tcfg_gnt_pipe[TCFG_GNT_PIPE_STAGES-1];
end
end
else begin : tcfg_gnt_no_pipeline
// For all other architectures, no pipeline delay needed for tcfg_gnt
assign trn_tcfg_gnt = tcfg_gnt_log;
end
endgenerate
endmodule |
module pcie_bram_top_v6
#(
parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
parameter VC0_TX_LASTPACKET = 31,
parameter TLM_TX_OVERHEAD = 24,
parameter TL_TX_RAM_RADDR_LATENCY = 1,
parameter TL_TX_RAM_RDATA_LATENCY = 2,
parameter TL_TX_RAM_WRITE_LATENCY = 1,
parameter VC0_RX_LIMIT = 'h1FFF,
parameter TL_RX_RAM_RADDR_LATENCY = 1,
parameter TL_RX_RAM_RDATA_LATENCY = 2,
parameter TL_RX_RAM_WRITE_LATENCY = 1
)
(
input user_clk_i,
input reset_i,
input mim_tx_wen,
input [12:0] mim_tx_waddr,
input [71:0] mim_tx_wdata,
input mim_tx_ren,
input mim_tx_rce,
input [12:0] mim_tx_raddr,
output [71:0] mim_tx_rdata,
input mim_rx_wen,
input [12:0] mim_rx_waddr,
input [71:0] mim_rx_wdata,
input mim_rx_ren,
input mim_rx_rce,
input [12:0] mim_rx_raddr,
output [71:0] mim_rx_rdata
);
// TX calculations
localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
1024 );
localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
localparam ROWS_TX = 1;
localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
(BYTES_TX <= 8192) ? 2 :
(BYTES_TX <= 16384) ? 4 :
(BYTES_TX <= 32768) ? 8 :
18
);
// RX calculations
localparam ROWS_RX = 1;
localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
(VC0_RX_LIMIT < 'h0400) ? 2 :
(VC0_RX_LIMIT < 'h0800) ? 4 :
(VC0_RX_LIMIT < 'h1000) ? 8 :
18
);
initial begin
$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
end
pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
pcie_brams_tx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_tx_waddr),
.wen(mim_tx_wen),
.ren(mim_tx_ren),
.rce(mim_tx_rce),
.wdata(mim_tx_wdata),
.raddr(mim_tx_raddr),
.rdata(mim_tx_rdata)
);
pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
pcie_brams_rx
(
.user_clk_i(user_clk_i),
.reset_i(reset_i),
.waddr(mim_rx_waddr),
.wen(mim_rx_wen),
.ren(mim_rx_ren),
.rce(mim_rx_rce),
.wdata(mim_rx_wdata),
.raddr(mim_rx_raddr),
.rdata(mim_rx_rdata)
);
endmodule // pcie_bram_top |
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