module
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module add
(
input clk,
input signed [31:0] din_0,
input signed [31:0] din_1,
input ivalid,
output ovalid,
output signed [31:0] dout
);
reg [31:0] dout_r;
reg wren;
reg [31:0] din_0_delay;
reg wren_delay;
// 1周期完成计算
always@(posedge clk)
din_0_delay <= din_0;
always@(posedge clk)
dout_r = din_0_delay + din_1;
always@(posedge clk)
if(ivalid)
wren <= 1'b1;
else
wren <= 1'b0;
always@(posedge clk)
wren_delay <= wren;
assign ovalid = wren_delay;
assign dout = dout_r;
endmodule |
module maxpooling
(
input clk,
input rstn,
input ivalid, // ???????,?????
input state, // 0: ???24*24; 1: 8*8
input [7:0] din, // ???? 8bit
output ovalid, // ???????
output [7:0] dout // ????
);
reg [7:0] data [0:23]; // ??????,????? 24 or 8
reg [6:0] ptr;
reg cnt; //??0?¡À??¡À????¨¢????data_reg_0,??1?¡À??¡À????¨¢????data_reg_1
reg [7:0] data_reg_0;
reg [7:0] data_reg_1;
reg [7:0] dout_r;
reg wren;
// ????
reg [7:0] din_delay;
always@(posedge clk)
if(!rstn)
din_delay <= 0;
else
din_delay <= din;
// ????????,??2?
always@(posedge clk)begin
if(!rstn)
ptr <= 7'b0000000;
else
case(state)
1'b0:begin
if(ptr == 7'd48)
ptr <= 7'd0;
else
if(!ivalid)
ptr <= ptr;
else
ptr <= ptr + 7'd1;
end
1'b1:begin
if(ptr == 7'd16)
ptr <= 7'd0;
else
if(!ivalid)
ptr <= ptr;
else
ptr <= ptr + 7'd1;
end
endcase
end
// ???,?????????
always@(posedge clk or negedge rstn)begin
if(!rstn)
cnt <= 0;
else
case(state)
1'b0:begin
if(ptr <= 7'd23)
cnt <= 0;
else
if(ivalid)
cnt <= cnt + 1'b1;
else
cnt <= cnt;
end
1'b1:begin
if(ptr <= 7'd7)
cnt <= 0;
else
if(ivalid)
cnt <= cnt + 1'b1;
else
cnt <= cnt;
end
endcase
end
// ??????
always@(posedge clk)
begin
case(state)
1'b0:begin
if(ptr <= 7'd24 && ivalid)
data[ptr-1] <= din_delay;
end
1'b1:begin
if(ptr <= 7'd8 && ivalid)
data[ptr-1] <= din;
end
endcase
end
// ????????????????,?????
always@(*)
begin
case({state,cnt})
2'b00:begin
if(ptr >= 7'd25)
begin
if(din_delay>data[ptr-7'd25])
data_reg_1 <= din_delay;
else
data_reg_1 <= data[ptr-7'd25];
end
else
data_reg_1 <= 0;
end
2'b01:begin
if(ptr >= 7'd25)
begin
if(din_delay>data[ptr-7'd25])
data_reg_0 <= din_delay;
else
data_reg_0 <= data[ptr-7'd25];
end
else
data_reg_0 <= 0;
end
2'b10:begin
if(ptr >= 7'd9)
begin
if(din>data[ptr-7'd9])
data_reg_1 <= din;
else
data_reg_1 <= data[ptr-7'd9];
end
else
data_reg_1 <= 0;
end
2'b11:begin
if(ptr >= 7'd9)
begin
if(din>data[ptr-7'd9])
data_reg_0 <= din;
else
data_reg_0 <= data[ptr-7'd9];
end
else
data_reg_0 <= 0;
end
default:begin
data_reg_0 <= 0;
data_reg_1 <= 0;
end
endcase
end
// ??????
always@(posedge clk)begin
wren <= cnt;
end
// reg0 ? reg1 ??,?????
always@(posedge clk)begin
if(data_reg_0 > data_reg_1)
dout_r <= data_reg_0;
else
dout_r <= data_reg_1;
end
assign ovalid = wren; // ????
assign dout = dout_r; // ???(????)
endmodule |
module conv
#(
parameter K=5,
parameter S=1 //??
)
(
input clk,
input rstn,
input start, // ¾í»ý²Ù×÷¿ªÊ¼±ê־λ
input weight_en, // ȨÖضÁȡʹÄÜ
input signed [7:0] weight, // 8bit ȨÖزÎÊý
input [39:0] taps, // »¬´°·¨£¬Ò»ÁУ¬5¸öÊäÈëÊý¾Ý£¨5* 8bit£©
input state, // ¿ØÖÆÐźţ¬state = 0£¬±íʾÊäÈëΪ 28*28£»state = 1£¬±íʾÊäÈëΪ 12*12
output signed [31:0] dout, // ¾í»ý¼ÆËã½á¹û
output ovalid,
output done // µ±Ç°´°¿ÚµÄ¾í»ýÍê³É±ê־λ
);
reg [7:0] weight_addr = 8'd0;
reg [19:0] cnt1; //¹¤×÷ʱÖÓ¼ÆÊý
reg [9:0] cnt2; //???
reg [9:0] cnt2s; //?S???
reg [9:0] cnt3s; //?S???
reg [31:0] wr_data; // ¾í»ý¼ÆËã½á¹û
reg wren;
reg sum_valid;
reg sum_valid_ff;
reg [4:0] Ni; //fmap´óС£¬¼´ÊäÈëͼÏñ size
// ÊäÈëͼÏñµÄsize
always@(*)
if(!state)
Ni <= 5'd28;
else
Ni <= 5'd12;
// ¾í»ýȨÖؾØÕó£¨5*5£©
// ÿ¸öȨÖزÎÊýÁ¿»¯Îª 8bit
reg signed [7:0] k00,k01,k02,k03,k04,k10,k11,k12,k13,k14,k20,k21,k22,k23,k24,k30,k31,k32,k33,k34,k40,k41,k42,k43,k44;
// ÊäÈëÊý¾ÝÓëȨÖؾØÕóÖغϲ¿·Ö£¬5*5
wire signed [7:0] m04,m14,m24,m34,m44;
reg signed [7:0] m00,m01,m02,m03,m10,m11,m12,m13,m20,m21,m22,m23,m30,m31,m32,m33,m40,m41,m42,m43;
// µ¥¸öÏñËØÊý¾ÝÓë¶ÔӦλÖÃȨÖØÏà³ËµÄ½á¹û
reg signed [15:0] p00,p01,p02,p03,p04,p10,p11,p12,p13,p14,p20,p21,p22,p23,p24,p30,p31,p32,p33,p34,p40,p41,p42,p43,p44;
// Æß¼¶Á÷Ë®Ïß ÔÝ´æÖµ
reg signed [16:0] sum00,sum01,sum02,sum03,sum04,sum05,sum06,sum07,sum08,sum09,sum10,sum11,sum12,sum13,sum14;
reg signed [17:0] sum15,sum16,sum17,sum18,sum19,sum20,sum21,sum22,sum23,sum24;
reg signed [18:0] sum0,sum1,sum2,sum3,sum4;
reg signed [19:0] sum100,sum101,sum102;
reg signed [20:0] sum110,sum120;
// »¬´°·¨£¬stride = 1
assign m04=taps[39:32];
assign m14=taps[31:24];
assign m24=taps[23:16];
assign m34=taps[15:8];
assign m44=taps[7:0];
// Ò»¸öʱÖÓÖÜÆÚÒƶ¯Ò»²½³¤£¬×îÖյõ½ 24*24 Êä³öͼÏñ£¬ËùÒÔÒƶ¯ÁË 576 ²½£¬ÐèÒª576¸öʱÖÓÖÜÆÚ
always@(posedge clk)
begin
{m00,m01,m02,m03} <= {m01,m02,m03,m04};
{m10,m11,m12,m13} <= {m11,m12,m13,m14};
{m20,m21,m22,m23} <= {m21,m22,m23,m24};
{m30,m31,m32,m33} <= {m31,m32,m33,m34};
{m40,m41,m42,m43} <= {m41,m42,m43,m44};
end
//ȨÖØ*ÏñËØÊý¾Ý
// Á÷Ë®Ïß µÚÒ»¼¶
always@(posedge clk)
begin
p00<=k00*m00;
p01<=k01*m01;
p02<=k02*m02;
p03<=k03*m03;
p04<=k04*m04;
p10<=k10*m10;
p11<=k11*m11;
p12<=k12*m12;
p13<=k13*m13;
p14<=k14*m14;
p20<=k20*m20;
p21<=k21*m21;
p22<=k22*m22;
p23<=k23*m23;
p24<=k24*m24;
p30<=k30*m30;
p31<=k31*m31;
p32<=k32*m32;
p33<=k33*m33;
p34<=k34*m34;
p40<=k40*m40;
p41<=k41*m41;
p42<=k42*m42;
p43<=k43*m43;
p44<=k44*m44;
end
/*
//¼òµ¥Á÷Ë®Ïß
always@(posedge clk)
begin
sum0 <= p00+p10+p20+p30+p40;
sum1 <= p01+p11+p21+p31+p41;
sum2 <= p02+p12+p22+p32+p42;
sum3 <= p03+p13+p23+p33+p43;
sum4 <= p04+p14+p24+p34+p44;
end
*/
// Á÷Ë®Ïß µÚ¶þ¼¶
always@(posedge clk)
begin
sum00<=p00+p10;
sum01<=p20+p30;
sum02<=p40;
sum03<=p01+p11;
sum04<=p21+p31;
sum05<=p41;
sum06<=p02+p12;
sum07<=p22+p32;
sum08<=p42;
sum09<=p03+p13;
sum10<=p23+p33;
sum11<=p43;
sum12<=p04+p14;
sum13<=p24+p34;
sum14<=p44;
end
// Á÷Ë®Ïß µÚÈý¼¶
always@(posedge clk)
begin
sum15<=sum00+sum01;
sum16<=sum02;
sum17<=sum03+sum04;
sum18<=sum05;
sum19<=sum06+sum07;
sum20<=sum08;
sum21<=sum09+sum10;
sum22<=sum11;
sum23<=sum12+sum13;
sum24<=sum14;
end
// Á÷Ë®Ïß µÚËļ¶
always@(posedge clk)
begin
sum0<=sum15+sum16;
sum1<=sum17+sum18;
sum2<=sum19+sum20;
sum3<=sum21+sum22;
sum4<=sum23+sum24;
end
// Á÷Ë®Ïß µÚÎ弶
always@(posedge clk)
begin
sum100 <= sum0 + sum1;
sum101 <= sum2 + sum3;
sum102 <= sum4;
end
// Á÷Ë®Ïß µÚÁù¼¶
always@(posedge clk)
begin
sum110 <= sum100 + sum101;
sum120 <= sum102;
end
// Á÷Ë®Ïß µÚÆß¼¶
always@(posedge clk)begin
wr_data <= sum110 + sum120;
end
// ´Ó¾í»ý¿ªÊ¼¼ÆÊý25¸öʱÖÓÖÜÆÚ£¬ÓÃÓÚ¶ÁȡȨÖØ¡£
always@(posedge clk or negedge rstn)
begin
if(!rstn || !start) // start = 1 ÇÒ weight_en = 1Æô¶¯
weight_addr <= 0;
else
if(weight_addr == 8'd25)
weight_addr <= weight_addr;
else
if(!weight_en)
weight_addr <= weight_addr;
else
weight_addr <= weight_addr + 1;
end
//5*5 ȨÖؾØÕ󣬶ÁÈ¡»º´æµÄȨÖØ
always@(posedge clk)
begin
case(weight_addr)
8'd0: k00 <= weight;
8'd1: k01 <= weight;
8'd2: k02 <= weight;
8'd3: k03 <= weight;
8'd4: k04 <= weight;
8'd5: k10 <= weight;
8'd6: k11 <= weight;
8'd7: k12 <= weight;
8'd8: k13 <= weight;
8'd9: k14 <= weight;
8'd10: k20 <= weight;
8'd11: k21 <= weight;
8'd12: k22 <= weight;
8'd13: k23 <= weight;
8'd14: k24 <= weight;
8'd15: k30 <= weight;
8'd16: k31 <= weight;
8'd17: k32 <= weight;
8'd18: k33 <= weight;
8'd19: k34 <= weight;
8'd20: k40 <= weight;
8'd21: k41 <= weight;
8'd22: k42 <= weight;
8'd23: k43 <= weight;
8'd24: k44 <= weight;
default:;
endcase
end
//conv²Ù×÷¹¤×÷ʱÖÓ¼ÆÊý
always@(posedge clk)
begin
if(start)
cnt1<=cnt1+1'd1;
else
cnt1<=19'd0;
end
//ÁмÆÊý
always@(posedge clk)
if(sum_valid)
if(cnt2==Ni-1)
cnt2<=10'd0;
else
cnt2<=cnt2+10'd1;
else
cnt2<=10'd0;
//¾í»ýÁв½³¤
always@(posedge clk)
if(sum_valid)
if(cnt2==Ni-1)
if(cnt3s==S-1)
cnt3s<=10'd0;
else
cnt3s<=cnt3s+1'd1;
else
cnt3s<=cnt3s;
else
cnt3s<=10'd0;
//Ðв½³¤
always@(posedge clk)
if(sum_valid)
if(cnt2 == Ni-1|| cnt2s == S-1)
cnt2s<=10'd0;
else
cnt2s<=cnt2s+10'd1;
else
cnt2s<=10'd0;
//???
always@(posedge clk)
begin
if(sum_valid && cnt2<Ni-K+1 && cnt2s==0 && cnt3s==0)
wren<=1'b1;
else
wren<=1'b0;
end
/*
//????
always@(posedge clk)
begin
if(!start)
sum_valid<=1'b0;
else if(cnt1==8'd153) //??(150+K-1+1+2-2)???????????????? 150:6???????????????? 2????????????????? 1:??????? K-1:??????????????? -2:??????
sum_valid<=1'b1;
else
case(state) //state1:28x28 state2:12x12
1'b0:if(cnt1==10'd821) //??(150+2+1+(N-k+1)i*(Ni-k+1)-1)??????????????????????????????sum_valid??
sum_valid<=1'b0;
1'b1:if(cnt1==10'd247)
sum_valid<=1'b0;
endcase
end
*/
always@(posedge clk)
begin
if(!start)
sum_valid<=1'b0;
else
case(state)
// ÊäÈëͼÏñ Size Ϊ 28*28
1'b0:if(cnt1==10'd830) //??(150+2+1+(N-k+1)i*(Ni-k+1)-1)??????????????????????????????sum_valid??
sum_valid<=1'b0;
else if(cnt1==8'd162)
sum_valid<=1'b1;
// ÊäÈëͼÏñ Size Ϊ 12*12
1'b1:if(cnt1==10'd255)
sum_valid<=1'b0;
else if(cnt1==8'd163)
sum_valid<=1'b1;
endcase
end
// ÑÓ³ÙÒ»ÅÄ£¬ÓÃÓÚ²ÉÑØ£¬ÅжϾí»ýÊÇ·ñÍê³É
always@(posedge clk)begin
sum_valid_ff <= sum_valid;
end
assign done = ~sum_valid && sum_valid_ff; // ²ÉÑùϽµÑØ£¬³öÏÖ¼´±íʾµ±Ç°´°¿ÚµÄ¾í»ýÍê³É±ê־λ
assign ovalid = wren;
assign dout = wr_data; // ¾í»ý¼ÆËã½á¹û
endmodule |
module FIFO_fmap
(
input clk,
input rstn,
input [7:0] din,
input wr_en,
input rd_en,
input rd_rst,
output empty,
output full,
output [7:0] dout
);
reg [7:0] rd_ptr, wr_ptr;
reg [7:0] mem [0:149];// 深度为 150
reg [7:0] dout_r;
integer i;
assign empty = (wr_ptr == rd_ptr);
assign full = ((wr_ptr - rd_ptr) == 8'd150);
// 延迟一拍
reg wr_en_delay;
always@(posedge clk)begin
if(!rstn)
wr_en_delay <= 0;
else
wr_en_delay <= wr_en;
end
// 读操作
always @(posedge clk or negedge rstn)begin
if(!rstn)
dout_r <= 0;
else if(rd_en && !empty)
dout_r <= mem[rd_ptr];
end
// 写操作
always @(posedge clk)
begin
if(rstn && wr_en_delay && !full)
mem[wr_ptr] <= din;
end
// 写指针递增
always @(posedge clk or negedge rstn)
begin
if(!rstn)
wr_ptr <= 0;
else if(!full && wr_en_delay)// 非满且写使能
wr_ptr <= wr_ptr + 1;
end
// 读指针递增
always @(posedge clk or negedge rstn)
begin
if(!rstn)
rd_ptr <= 0;
else
if(rd_rst)
rd_ptr <= 0;
else if(!empty && rd_en)// 非空且读使能
rd_ptr <= rd_ptr + 1;
end
assign dout = dout_r;
endmodule |
module relu
(
input clk,
input signed [31:0] din,
input ivalid,
input state,
output reg ovalid,
output reg signed [7:0] dout
);
reg wren;
reg [31:0] dout_r;
reg [31:0] dout_delay;
// ????,?????
always@(posedge clk)begin
if(ivalid)
wren <= 1'b1;
else
wren <= 1'b0;
end
// ?????,?0????
always@(posedge clk)begin
if(din[31])
dout_r <= 0;
else
dout_r <= din;
end
// ????
always@(posedge clk)begin
dout_delay <= dout_r;
end
/*
assign dout = (state)?(dout_delay >>> 10):(dout_r >>> 10);
assign ovalid = wren;
*/
always@(posedge clk)begin
if(state)
dout <= (dout_delay >>> 10);
else
dout <= (dout_r >>> 10);
end
always@(posedge clk)begin
ovalid <= wren;
end
endmodule |
module scrambler_reset_inserter(
input clk,
input [71:0] in_data,
output reg [71:0] out_data
);
reg [8:0] bs_count;
reg substitue_next;
localparam [8:0] BS = 9'b110111100; // K28.5 0x1BC
localparam [8:0] SR = 9'b100011100; // K28.0 0x11C
initial begin
bs_count = 9'b0;
substitue_next = 1'b0;
out_data = 72'b0;
end
always @(posedge clk) begin
//----------------------------------------------
// Subsitute every 512nd Blank start (BS) symbol
// with a Scrambler Reset (SR) symbol.
//----------------------------------------------
out_data <= in_data;
if(substitue_next == 1'b1) begin
if(in_data[8:0] == BS) begin
out_data[8:0] <= SR;
end
if(in_data[26:18] == BS) begin
out_data[26:18] <= SR;
end
if(in_data[44:36] == BS) begin
out_data[44:36] <= SR;
end
if(in_data[62:54] == BS) begin
out_data[62:54] <= SR;
end
end
if(in_data[8:0] == BS) begin
if(bs_count == 1'b0) begin
substitue_next <= 1'b1;
end else begin
substitue_next <= 1'b0;
end
bs_count <= bs_count + 1;
end
end
endmodule |
module main_stream_processing (
input symbol_clk,
input tx_link_established,
input source_ready,
input tx_clock_train,
input tx_align_train,
input [72:0] in_data,
output [79:0] tx_symbols
);
wire [71:0] signal_data;
wire [71:0] sr_inserted_data;
wire [71:0] scrambled_data;
wire [79:0] before_skew;
wire [79:0] final_data;
localparam [7:0] delay_index = 8'b11100100;
/////////////////////////////////////////////////////////
// Flick between the idle pattern and a valid data stream
// at the time when the in_data's high bit is set
/////////////////////////////////////////////////////////
idle_pattern_inserter i_idle_pattern_inserter(
.clk (symbol_clk),
.channel_ready (tx_link_established),
.source_ready (source_ready),
.in_data (in_data),
.out_data (signal_data)
);
/////////////////////////////////////////////////////////
// Change the 512th Blank Start (BS) symbol into a
// Scrambler Reset (SR) symbol
/////////////////////////////////////////////////////////
scrambler_reset_inserter i_scrambler_reset_inserter(
.clk (symbol_clk),
.in_data (signal_data),
.out_data (sr_inserted_data)
);
/////////////////////////////////////////////////////////
// Now scramble the data stream - only scrambles the data
// symbols, the K symbols go through unscrambled.
/////////////////////////////////////////////////////////
scrambler_all_channels i_scrambler(
.clk (symbol_clk),
.bypass0 (1'b0),
.bypass1 (1'b0),
.in_data (sr_inserted_data),
.out_data (scrambled_data)
);
/////////////////////////////////////////////////////////
// This allows the controller to send the two training
// patterns, allowing the link drive levels to be set up
/////////////////////////////////////////////////////////
insert_training_pattern i_insert_training_pattern(
.clk (symbol_clk),
.clock_train (tx_clock_train),
.align_train (tx_align_train),
///////////////////////////////////////////////////////
// Adds one bit per symbol - the force_neg parity flag
// This takes the 72-bit wide data word to 80 bits.
///////////////////////////////////////////////////////
.in_data (scrambled_data),
.out_data (before_skew)
);
/////////////////////////////////////////////////////////
// The last step is to skew the data channels (zero cycles
// cycles for channel zero, two cycle for channel one,
// four for channel two and six for channel three.
/////////////////////////////////////////////////////////
skew_channels i_skew_channels(
.clk (symbol_clk),
.in_data (before_skew),
.out_data (tx_symbols)
);
endmodule |
module top_level_mimas_a7(
input clk100,
//////////////////////////////////////////
output [1:0] dp_tx_lane_p,
output [1:0] dp_tx_lane_n,
//////////////////////////////////////////
input dp_refclk_p,
input dp_refclk_n,
input mgtrefclk1_p,
input mgtrefclk1_n,
//////////////////////////////////////////
input dp_tx_hp_detect,
inout dp_tx_auxch_p,
inout dp_tx_auxch_n,
///////////////////////////////////////////
// output [7:0] debug,
input [3:0] sw,
// output [7:0] seg_segs,
// output [2:0] seg_en,
output [7:0] LED
);
reg [37:0] counter;
always @(posedge clk100) begin
counter <= counter + 1;
end
wire refclk0, odiv2_0;
wire refclk1, odiv2_1;
wire [3:0] tx_powerup_channel;
wire preemp_0p0;
wire preemp_3p5;
wire preemp_6p0;
wire swing_0p4;
wire swing_0p6;
wire swing_0p8;
wire [3:0] tx_running;
wire tx_symbol_clk;
wire [79:0] tx_symbols;
wire [7:0] debug_cm;
wire tx_align_train;
wire tx_clock_train;
wire tx_link_established;
wire [2:0] stream_channel_count;
wire [2:0] source_channel_count = 3'b010;
wire [72:0] msa_merged_data;
wire test_signal_ready;
wire auxch_in;
wire auxch_out;
wire auxch_tri;
initial begin
counter = 30'b0;
end
//assign debug = debug_cm;
///////////////////////////////////////////////////
// Debug infrastructure
///////////////////////////////////////////////////
wire [7:0] seg_segs;
wire [2:0] seg_en;
seven_segment_driver ssd(
.clk (clk100),
.value (counter[37:26]),
.segments (seg_segs),
.segment_enable (seg_en)
);
///////////////////////////////////////////////////
// Refclock buffers
///////////////////////////////////////////////////
IBUFDS_GTE2 ibufds_gte2_0 (
.O (refclk0),
.ODIV2 (odiv2_0),
.CEB (1'b0),
.I (dp_refclk_p),
.IB (dp_refclk_n)
);
IBUFDS_GTE2 ibufds_gte2_1 (
.O (refclk1),
.ODIV2 (odiv2_1),
.CEB (1'b0),
.I (mgtrefclk1_p),
.IB (mgtrefclk1_n)
);
///////////////////////////////////////////////////
// Aux channel interface
///////////////////////////////////////////////////
wire auxch_out_ignore;
IOBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) i_IOBUFDS_2 (
.O (auxch_in), // Buffer output
.IO (dp_tx_auxch_p), // Diff_p inout (connect directly to top-level port)
.IOB (dp_tx_auxch_n), // Diff_n inout (connect directly to top-level port)
.I (auxch_out), // Buffer input
.T (auxch_tri) // 3-state enable input, high=input, low=output
);
///////////////////////////////////////////////////
// Video pipeline
///////////////////////////////////////////////////
test_source i_test_source(
.clk (tx_symbol_clk),
.stream_channel_count (stream_channel_count),
.ready (test_signal_ready),
.data (msa_merged_data)
);
main_stream_processing i_main_stream_processing(
.symbol_clk (tx_symbol_clk),
.tx_link_established (tx_link_established),
.source_ready (test_signal_ready),
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
.in_data (msa_merged_data),
.tx_symbols (tx_symbols)
);
////////////////////////////////////////////////
// Transceivers
///////////////////////////////////////////////
transceiver_bank i_transciever_bank(
.mgmt_clk (clk100),
///////////////////////////////
// Master control
///////////////////////////////
.powerup_channel (tx_powerup_channel[1:0]),
///////////////////////////////
// Output signal control
///////////////////////////////
.preemp_0p0 (preemp_0p0),
.preemp_3p5 (preemp_3p5),
.preemp_6p0 (preemp_6p0),
.swing_0p4 (swing_0p4),
.swing_0p6 (swing_0p6),
.swing_0p8 (swing_0p8),
///////////////////////////////
// Status feedback
///////////////////////////////
.tx_running (tx_running[1:0]),
///////////////////////////////
// Reference clocks
///////////////////////////////
.refclk0 (refclk0),
.refclk1 (refclk1),
///////////////////////////////
// Symbols to transmit
///////////////////////////////
.tx_symbol_clk (tx_symbol_clk),
.tx_symbols (tx_symbols),
.gtptx_p (dp_tx_lane_p),
.gtptx_n (dp_tx_lane_n)
);
channel_management i_channel_management(
.clk100 (clk100),
.debug (debug_cm),
.hpd (dp_tx_hp_detect),
.auxch_in (auxch_in),
.auxch_out (auxch_out),
.auxch_tri (auxch_tri),
.stream_channel_count (stream_channel_count),
.source_channel_count (source_channel_count),
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
.tx_powerup_channel (tx_powerup_channel),
.tx_preemp_0p0 (preemp_0p0),
.tx_preemp_3p5 (preemp_3p5),
.tx_preemp_6p0 (preemp_6p0),
.tx_swing_0p4 (swing_0p4),
.tx_swing_0p6 (swing_0p6),
.tx_swing_0p8 (swing_0p8),
.tx_running (tx_running),
.tx_link_established (tx_link_established)
);
always @(posedge clk100) begin
counter = counter + 1;
end
assign LED = counter[29:22]; // {tx_running, tx_powerup_channel};
endmodule |
module skew_channels (
input clk,
input [79:0] in_data,
output [79:0] out_data
);
reg [59:0] delay0;
reg [39:0] delay1;
reg [19:0] delay2;
assign out_data[79:60] = delay2[19:0];
assign out_data[59:40] = delay1[19:0];
assign out_data[39:20] = delay0[19:0];
assign out_data[19:0] = in_data[19:0];
always @(posedge clk) begin
delay2 <= delay1[39:20];
delay1 <= delay0[59:20];
delay0 <= in_data[79:20];
end
endmodule |
module insert_training_pattern(
input clk,
input clock_train,
input align_train,
input [71:0] in_data,
output [79:0] out_data
);
////////////////////////////////////////////////////////
//
// This is designed so the change over from test patterns
// to data stream happens seamlessly - e.g. the value for
// presented on data_in when clock_train and align_train
// are both become zero is guaranteed to be sent
//
// +----+--------------------+--------------------+
// |Word| Training pattern 1 | Training pattern 2 |
// | | Code MSB LSB | Code MSB LSB |
// +----+--------------------+-------------------+
// | 0 | D10.2 1010101010 | K28.5- 0101111100 |
// | 1 | D10.2 1010101010 | D11.6 0110001011 |
// | 2 | D10.2 1010101010 | K28.5+ 1010000011 |
// | 3 | D10.2 1010101010 | D11.6 0110001011 |
// | 4 | D10.2 1010101010 | D10.2 1010101010 |
// | 5 | D10.2 1010101010 | D10.2 1010101010 |
// | 6 | D10.2 1010101010 | D10.2 1010101010 |
// | 7 | D10.2 1010101010 | D10.2 1010101010 |
// | 8 | D10.2 1010101010 | D10.2 1010101010 |
// | 9 | D10.2 1010101010 | D10.2 1010101010 |
// +----+--------------------+--------------------+
// Patterns are transmitted LSB first.
////////////////////////////////////////////////////////
reg clock_train_meta, clock_train_i; // TODO: NEED TO SET ASYNCREG!
reg align_train_meta, align_train_i; // TODO: NEED TO SET ASYNCREG!
reg [2:0] state;
reg [9:0] hold_at_state_one = 10'b1111111111;
reg [79:0] delay_line [5:0];
localparam [8:0] CODE_K28_5 = 9'b110111100;
localparam [8:0] CODE_D11_6 = 9'b011001011;
localparam [8:0] CODE_D10_2 = 9'b001001010;
localparam [19:0] p0 = {1'b0, CODE_D11_6, 1'b1, CODE_K28_5};
localparam [19:0] p1 = {1'b0, CODE_D11_6, 1'b0, CODE_K28_5};
localparam [19:0] p2 = {1'b0, CODE_D10_2, 1'b0, CODE_D10_2};
localparam [19:0] p3 = {1'b0, CODE_D10_2, 1'b0, CODE_D10_2};
localparam [19:0] p4 = {1'b0, CODE_D10_2, 1'b0, CODE_D10_2};
assign out_data = delay_line[5];
initial begin
clock_train_meta = 1'b0;
clock_train_i = 1'b0;
align_train_meta = 1'b0;
align_train_i = 1'b0;
delay_line[0] = 80'b0;
delay_line[1] = 80'b0;
delay_line[2] = 80'b0;
delay_line[3] = 80'b0;
delay_line[4] = 80'b0;
delay_line[5] = 80'b0;
end
always @(posedge clk) begin
// Move the delay line along
delay_line[5] <= delay_line[4];
delay_line[4] <= delay_line[3];
delay_line[3] <= delay_line[2];
delay_line[2] <= delay_line[1];
delay_line[1] <= delay_line[0];
delay_line[0] <= { 1'b0, in_data[71:63], 1'b0, in_data[62:54],
1'b0, in_data[53:45], 1'b0, in_data[44:36],
1'b0, in_data[35:27], 1'b0, in_data[26:18],
1'b0, in_data[17:9], 1'b0, in_data[8:0]};
// Do we need to hold at state 1 until valid data has filtered down the delay line?
if(align_train_i == 1'b1 || clock_train_i == 1'b1) begin
hold_at_state_one <= 10'b1111111111;
end else begin
hold_at_state_one <= {1'b0, hold_at_state_one[9:1] };
end
// Do we need to overwrite the data in slot 5 with the sync patterns?
case(state)
3'b101: begin
state <= 3'b100;
delay_line[5] <= {p0, p0, p0, p0};
end
3'b100: begin
state <= 3'b011;
delay_line[5] <= {p1, p1, p1, p1};
end
3'b011: begin
state <= 3'b010;
delay_line[5] <= {p2, p2, p2, p2};
end
3'b010: begin
state <= 3'b001;
delay_line[5] <= {p3, p3, p3, p3};
end
3'b001: begin
state <= 3'b000;
delay_line[5] <= {p4, p4, p4, p4};
if(align_train_i == 1'b1) begin
state <= 3'b101;
end else if(hold_at_state_one[0] == 1'b1) begin
state <= 3'b001;
end
end
default: begin
state <= 3'b000;
if(align_train_i == 1'b1) begin
state <= 3'b101;
end else if(hold_at_state_one[0] == 1'b1) begin
state <= 3'b001;
end
end
endcase
// Synchronize the control signals
clock_train_meta <= clock_train;
clock_train_i <= clock_train_meta;
align_train_meta <= align_train;
align_train_i <= align_train_meta;
end
endmodule |
module scrambler_all_channels(
input clk,
input bypass0,
input bypass1,
input [71:0] in_data,
output reg [71:0] out_data
);
//--------------------------------------------------------------------------------
// Should be verified against the table in Appendix C of the "PCI Express Base
// Specification 2.1" which uses the same polynomial.
//
// Here are the first 32 output words when data values of "00" are scrambled:
//
// | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
// ---+------------------------------------------------
// 00 | FF 17 C0 14 B2 E7 02 82 72 6E 28 A6 BE 6D BF 8D
// 10 | BE 40 A7 E6 2C D3 E2 B2 07 02 77 2A CD 34 BE E0
//
//--------------------------------------------------------------------------------
localparam [15:0] lfsr_reset_state = 16'b1111111111111111;
reg [15:0] lfsr_state = lfsr_reset_state;
localparam [8:0] SR = 9'b100011100; // K28.0 is used to signal a reset for the scrambler
wire [15:0] s0;
wire [15:0] s1;
wire [17:0] flipping;
assign s0 = lfsr_state;
// generate intermediate scrambler state
assign s1[0] = (in_data[8:0] == SR) ? lfsr_reset_state[0] : s0[8];
assign s1[1] = (in_data[8:0] == SR) ? lfsr_reset_state[1] : s0[9];
assign s1[2] = (in_data[8:0] == SR) ? lfsr_reset_state[2] : s0[10];
assign s1[3] = (in_data[8:0] == SR) ? lfsr_reset_state[3] : s0[11] ^ s0[8];
assign s1[4] = (in_data[8:0] == SR) ? lfsr_reset_state[4] : s0[12] ^ s0[8] ^ s0[9];
assign s1[5] = (in_data[8:0] == SR) ? lfsr_reset_state[5] : s0[13] ^ s0[8] ^ s0[9] ^ s0[10];
assign s1[6] = (in_data[8:0] == SR) ? lfsr_reset_state[6] : s0[14] ^ s0[9] ^ s0[10] ^ s0[11];
assign s1[7] = (in_data[8:0] == SR) ? lfsr_reset_state[7] : s0[15] ^ s0[10] ^ s0[11] ^ s0[12];
assign s1[8] = (in_data[8:0] == SR) ? lfsr_reset_state[8] : s0[0] ^ s0[11] ^ s0[12] ^ s0[13];
assign s1[9] = (in_data[8:0] == SR) ? lfsr_reset_state[9] : s0[1] ^ s0[12] ^ s0[13] ^ s0[14];
assign s1[10] = (in_data[8:0] == SR) ? lfsr_reset_state[10] : s0[2] ^ s0[13] ^ s0[14] ^ s0[15];
assign s1[11] = (in_data[8:0] == SR) ? lfsr_reset_state[11] : s0[3] ^ s0[14] ^ s0[15];
assign s1[12] = (in_data[8:0] == SR) ? lfsr_reset_state[12] : s0[4] ^ s0[15];
assign s1[13] = (in_data[8:0] == SR) ? lfsr_reset_state[13] : s0[5];
assign s1[14] = (in_data[8:0] == SR) ? lfsr_reset_state[14] : s0[6];
assign s1[15] = (in_data[8:0] == SR) ? lfsr_reset_state[15] : s0[7];
assign flipping[8:0] = (in_data[8] == 1'b0 && bypass0 == 1'b0) ? {1'b0, s0[8], s0[9], s0[10], s0[11], s0[12], s0[13], s0[14], s0[15]} : 9'b000000000;
assign flipping[17:9] = (in_data[17] == 1'b0 && bypass1 == 1'b0) ? {1'b0, s1[8], s1[9], s1[10], s1[11], s1[12], s1[13], s1[14], s1[15]} : 9'b000000000;
initial begin
out_data <= 72'b0;
lfsr_state = 16'hFFFF;
end
always @(posedge clk) begin
//------------------------------------------
// Apply vector to channel 0
//------------------------------------------
out_data <= in_data ^ {flipping, flipping, flipping, flipping};
lfsr_state[0] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[8];
lfsr_state[1] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[9];
lfsr_state[2] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[10];
lfsr_state[3] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[11] ^ s1[8];
lfsr_state[4] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[12] ^ s1[8] ^ s1[9];
lfsr_state[5] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[13] ^ s1[8] ^ s1[9] ^ s1[10];
lfsr_state[6] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[14] ^ s1[9] ^ s1[10] ^ s1[11];
lfsr_state[7] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[15] ^ s1[10] ^ s1[11] ^ s1[12];
lfsr_state[8] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[0] ^ s1[11] ^ s1[12] ^ s1[13];
lfsr_state[9] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[1] ^ s1[12] ^ s1[13] ^ s1[14];
lfsr_state[10] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[2] ^ s1[13] ^ s1[14] ^ s1[15];
lfsr_state[11] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[3] ^ s1[14] ^ s1[15];
lfsr_state[12] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[4] ^ s1[15];
lfsr_state[13] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[5];
lfsr_state[14] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[6];
lfsr_state[15] = (in_data[15:8] == SR) ? lfsr_reset_state[0] : s1[7];
end
endmodule |
module idle_pattern_inserter (
input clk,
input channel_ready,
input source_ready,
input [72:0] in_data, // Bit 72 is the switch point indicator
output reg [71:0] out_data
);
reg [16:0] count_to_switch;
reg source_ready_last;
reg idle_switch_point;
reg [12:0] idle_count;
localparam [8:0] BS = 9'b110111100; // K28.5
localparam [8:0] DUMMY = 9'b000000011; // 0x3
localparam [8:0] VB_ID = 9'b000001001; // 0x09 VB-ID with no video asserted
localparam [8:0] Mvid = 9'b000000000; // 0x00
localparam [8:0] Maud = 9'b000000000; // 0x00
reg [17:0] idle_data;
reg channel_ready_i;
reg channel_ready_meta; // TODO: NEED TO SET ASYNCREG
initial begin
channel_ready_i = 1'b0;
channel_ready_meta = 1'b0;
out_data = 72'b0;
idle_data = 18'b0;
count_to_switch = 17'b0;
idle_count = 13'b0;
end
always @(posedge clk) begin
if(count_to_switch[16] == 1'b1) begin
out_data <= in_data[71:0];
end else begin
// send idle pattern
out_data <= { idle_data, idle_data, idle_data, idle_data};
end
if(count_to_switch[16] == 1'b0) begin
//------------------------------------------------------
// The last tick over requires the source to be ready
// and to be asserting that it is in the switch point.
//------------------------------------------------------
if(count_to_switch[15:0] == 16'hFFFF) begin
//-------------------------------------
// Bit 72 is the switch point indicator
//-------------------------------------
if(source_ready == 1'b1 && in_data[72] == 1'b1 && idle_switch_point == 1'b1) begin
count_to_switch <= count_to_switch + 1;
end
end else begin
//------------------------------------------------------
// Wait while we send out at least 64k of idle patterns
//------------------------------------------------------
count_to_switch <= count_to_switch + 1;
end
end
//-----------------------------------------------------------------------
// If either the source drops or the channel is not ready, then reset
// to emitting the idle pattern.
//-----------------------------------------------------------------------
if(channel_ready_i == 1'b0 || (source_ready == 1'b0 && source_ready_last == 1'b1)) begin
count_to_switch <= 17'b0;
end
source_ready_last <= source_ready;
//------------------------------------------------------
// We can either be odd or even aligned, depending on
// where the last BS symbol was seen. We need to send
// the next one 8192 symbols later (4096 cycles)
//------------------------------------------------------
idle_switch_point <= 1'b0;
case(idle_count)
// For the even aligment
0: idle_data <= {DUMMY, DUMMY};
2: idle_data <= {VB_ID, BS };
4: idle_data <= {Maud, Mvid };
6: idle_data <= {Mvid, VB_ID};
8: idle_data <= {VB_ID, Maud };
10: idle_data <= {Maud, Mvid };
12: idle_data <= {Mvid, VB_ID};
14: idle_data <= {DUMMY, Maud };
// For the odd aligment
1: idle_data <= {BS, DUMMY};
3: idle_data <= {Mvid, VB_ID};
5: idle_data <= {VB_ID, Maud };
7: idle_data <= {Maud, Mvid };
9: idle_data <= {Mvid, VB_ID};
11: idle_data <= {VB_ID, Maud };
13: idle_data <= {Mvid, VB_ID};
15: idle_data <= {Maud, Mvid };
17: idle_data <= {DUMMY, DUMMY};
default: begin
idle_data <= DUMMY & DUMMY; // can switch to the actual video at any other time
idle_switch_point <= 1'b1; // other than when the BS, VB-ID, Mvid, Maud sequence
end
endcase
idle_count <= idle_count + 2;
//------------------------------------------------------
// Sync with the BS stream of the input signal but only
// if we are switched over to it (indicated by the high
// bit of count_to_switch being set)
//------------------------------------------------------
if(count_to_switch[16] == 1'b1) begin
if(in_data[8:0] == BS) begin
idle_count <= 13'b10;
end else if(in_data[17:9] == BS) begin
idle_count <= 13'b1;
end
end
channel_ready_i <= channel_ready_meta;
channel_ready_meta <= channel_ready;
end
endmodule |
module tb_test_source_800_600_RGB_444_ch1;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire ready = 1'b1;
wire [2:0] stream_channel_count = 3'b1;
wire [23:0] M_value;
wire [23:0] N_value;
wire [11:0] H_visible;
wire [11:0] V_visible;
wire [11:0] H_total;
wire [11:0] V_total;
wire [11:0] H_sync_width;
wire [11:0] V_sync_width;
wire [11:0] H_start;
wire [11:0] V_start;
wire H_vsync_active_high;
wire V_vsync_active_high;
wire flag_sync_clock;
wire flag_YCCnRGB;
wire flag_422n444;
wire flag_YCC_colour_709;
wire flag_range_reduced;
wire flag_interlaced_even;
wire [1:0] flags_3d_Indicators;
wire [4:0] bits_per_colour;
wire [72:0] raw_data;
test_source_800_600_RGB_444_ch1 i_test_source(
.M_value (M_value),
.N_value (N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width (H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even (flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
.stream_channel_count (stream_channel_count),
.clk (clk),
.ready (ready),
.data (raw_data)
);
endmodule |
module tb_transceiver;
reg clk = 1'b0;
reg mgmt_clk;
reg [1:0] powerup_channel;
reg preemp_0p0;
reg preemp_3p5;
reg preemp_6p0;
reg swing_0p4;
reg swing_0p6;
reg swing_0p8;
wire [1:0] tx_running;
reg refclk0;
reg refclk1;
wire tx_symbol_clk;
reg [79:0] tx_symbols;
wire [7:0] debug;
wire [1:0] gtptx_p;
wire [1:0] gtptx_n;
reg [15:0] count;
initial begin
mgmt_clk = 1'b0;
powerup_channel = 2'b11;
preemp_0p0 = 1'b1;
preemp_3p5 = 1'b0;
preemp_6p0 = 1'b0;
swing_0p4 = 1'b1;
swing_0p6 = 1'b0;
swing_0p8 = 1'b0;
refclk0 = 1'b0;
refclk1 = 1'b0;
tx_symbols = 80'h0000000000000003FCFF;
count = 16'b0;
forever begin
#2
refclk0 = ~refclk0;
#2
refclk0 = ~refclk0;
mgmt_clk = ~mgmt_clk; // generate a clock
if(count == 100) begin
powerup_channel = 2'b00;
end
count = count + 1;
end
end
transceiver i_transceiver(
.mgmt_clk (mgmt_clk),
.powerup_channel (powerup_channel),
.preemp_0p0 (preemp_0p0),
.preemp_3p5 (preemp_3p5),
.preemp_6p0 (preemp_6p0),
.swing_0p4 (swing_0p4),
.swing_0p6 (swing_0p6),
.swing_0p8 (swing_0p8),
.tx_running (tx_running),
.refclk0 (refclk0),
.refclk1 (refclk1),
.tx_symbol_clk (tx_symbol_clk),
.tx_symbols (tx_symbols),
.debug (debug),
.gtptx_p (gtptx_p),
.gtptx_n (gtptx_n)
);
endmodule |
module tb_scrambler_reset_inserter;
reg clk = 1'b1;
reg [71:0] in_data;
wire [71:0] out_data;
localparam [8:0] BS = 9'b110111100; // K28.5
initial begin
in_data = 72'b0;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
forever begin
#1
in_data[8:0] = BS;
#3
clk = ~clk;
#4
clk = ~clk;
#1
in_data = 72'b0;
#3
clk = ~clk;
#4
clk = ~clk;
end
end
scrambler_reset_inserter i_scrambler_reset_inserter(
.clk (clk),
.in_data (in_data),
.out_data (out_data)
);
endmodule |
module tb_hotplug_detect;
reg clk100;
wire [7:0] debug;
reg hpd;
reg auxch_in;
wire auxch_out;
wire auxch_tri;
// Datapath requirements
reg [2:0] stream_channel_count;
reg [2:0] source_channel_count;
// Datapath control
wire tx_clock_train;
wire tx_align_train;
// Transceiver management
wire [3:0] tx_powerup_channel;
wire tx_preemp_0p0;
wire tx_preemp_3p5;
wire tx_preemp_6p0;
wire tx_swing_0p4;
wire tx_swing_0p6;
wire tx_swing_0p8;
reg [3:0] tx_running;
wire tx_link_established;
reg [19:0] count;
initial begin
clk100 = 1'b0;
hpd = 1'b0;
auxch_in = 1'b0;
// Datapath requirements
stream_channel_count = 3'b001;
source_channel_count = 3'b001;
tx_running = 4'b0000;
count = 16'b0;
end
initial begin
forever begin
if(count == 100) begin
hpd = 1'b1;
end
if(count == 250000) begin // IRQ PULSE
hpd = 1'b0;
end
if(count == 400000) begin
hpd = 1'b1;
end
if(count == 750000) begin
hpd = 1'b0;
end
#5
clk100 = ~clk100; // generate a clock
#5
clk100 = ~clk100; // generate a clock
count = count +1;
end
end
channel_management i_channel_management(
.clk100 (clk100),
.debug (debug),
.hpd (hpd),
.auxch_in (auxch_in),
.auxch_out (auxch_out),
.auxch_tri (auxch_tri),
// Datapath requirements
.stream_channel_count (stream_channel_count),
.source_channel_count (source_channel_count),
// Datapath control
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
// Transceiver management
.tx_powerup_channel (tx_powerup_channel),
.tx_preemp_0p0 (tx_preemp_0p0),
.tx_preemp_3p5 (tx_preemp_3p5),
.tx_preemp_6p0 (tx_preemp_6p0),
.tx_swing_0p4 (tx_swing_0p4),
.tx_swing_0p6 (tx_swing_0p6),
.tx_swing_0p8 (tx_swing_0p8),
.tx_running (tx_running),
.tx_link_established (tx_link_established)
);
endmodule |
module tb_channel_management;
reg clk100;
wire [7:0] debug;
wire hpd;
wire auxch_in;
wire auxch_out;
wire auxch_tri;
// Datapath requirements
reg [2:0] stream_channel_count;
reg [2:0] source_channel_count;
// Datapath control
wire tx_clock_train;
wire tx_align_train;
// Transceiver management
wire [3:0] tx_powerup_channel;
wire tx_preemp_0p0;
wire tx_preemp_3p5;
wire tx_preemp_6p0;
wire tx_swing_0p4;
wire tx_swing_0p6;
wire tx_swing_0p8;
reg [3:0] tx_running;
wire tx_link_established;
reg [31:0] i, j;
initial begin
clk100 = 1'b0;
// Datapath requirements
stream_channel_count = 3'b001;
source_channel_count = 3'b001;
tx_running = 4'b0000;
end
always begin
#5 clk100 = ~clk100; // generate a clock
end
wire dp_tx_hp_detect;
tb_dummy_sink i_tb_dummy_sink(
.clk100 (clk100),
.auxch_data (auxch_in),
.hotplug_detect (hpd)
);
channel_management i_channel_management(
.clk100 (clk100),
.debug (debug),
.hpd (hpd),
.auxch_in (auxch_in),
.auxch_out (auxch_out),
.auxch_tri (auxch_tri),
// Datapath requirements
.stream_channel_count (stream_channel_count),
.source_channel_count (source_channel_count),
// Datapath control
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
// Transceiver management
.tx_powerup_channel (tx_powerup_channel),
.tx_preemp_0p0 (tx_preemp_0p0),
.tx_preemp_3p5 (tx_preemp_3p5),
.tx_preemp_6p0 (tx_preemp_6p0),
.tx_swing_0p4 (tx_swing_0p4),
.tx_swing_0p6 (tx_swing_0p6),
.tx_swing_0p8 (tx_swing_0p8),
.tx_running (tx_running),
.tx_link_established (tx_link_established)
);
endmodule |
module tb_compare;
reg clk = 1'b0;
initial begin
forever #10 clk = ~clk; // generate a clock
end
wire [2:0] stream_channel_count;
wire [72:0] data;
wire ready;
wire [2:0] v_stream_channel_count;
wire [72:0] v_data;
wire v_ready;
test_source i_test_source(
.clk (clk),
.stream_channel_count (stream_channel_count),
.ready (ready),
.data (data)
);
test_source_cmp i_v_test_source_cmp(
.clk (clk),
.stream_channel_count (v_stream_channel_count),
.ready (v_ready),
.data (v_data)
);
wire [72:0] diff = data ^ v_data;
endmodule |
module tb_skew_channels;
reg clk = 1'b1;
reg [79:0] in_data;
wire [79:0] out_data;
initial begin
in_data = 80'b0;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
forever begin
#1
in_data = 80'h44444333332222211111;
#3
clk = ~clk;
#4
clk = ~clk;
#1
in_data = 80'b0;
#3
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
end
end
skew_channels i_skew_channels(
.clk (clk),
.in_data (in_data),
.out_data (out_data)
);
endmodule |
module tb_test_source;
reg clk = 1'b0;
reg [8:0] ch1;
reg [8:0] ch2;
reg [8:0] ch3;
reg [8:0] ch4;
wire [2:0] stream_channel_count;
wire [72:0] data;
wire ready;
initial begin
forever begin
#4
clk = 1'b0; // generate a clock
ch1 <= data[8:0];
ch2 <= data[26:18];
ch3 <= data[44:36];
ch4 <= data[62:54];
#4
clk = 1'b1; // generate a clock
ch1 <= data[17:9];
ch2 <= data[35:27];
ch3 <= data[53:45];
ch4 <= data[71:63];
end
end
test_source i_test_source(
.clk (clk),
.stream_channel_count (stream_channel_count),
.ready (ready),
.data (data)
);
endmodule |
module tb_idle_pattern_inserter;
reg clk = 1'b1;
reg channel_ready = 1'b1;
reg source_ready = 1'b1;
reg [72:0] in_data;
wire [71:0] out_data;
reg [15:0] count;
initial begin
in_data = 80'b0;
channel_ready = 1'b1;
source_ready = 1'b1;
count = 0;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
forever begin
case(count)
100: in_data = 73'h1444333332222211111;
200: in_data = 73'h0444333332222211111;
endcase
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
count = count + 1;
end
end
idle_pattern_inserter i_idle_pattern_inserter(
.clk (clk),
.channel_ready (channel_ready),
.source_ready (source_ready),
.in_data (in_data),
.out_data (out_data)
);
endmodule |
module tb_insert_training_pattern;
reg clk = 1'b1;
reg clock_train = 1'b0;
reg align_train = 1'b0;
reg [71:0] in_data;
wire [79:0] out_data;
reg [11:0] count;
initial begin
count = 12'b0;
clock_train = 1'b1;
align_train = 1'b0;
in_data = 72'hFFFFFFFFFFFFFFFFFF;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
forever begin
#4
clk = ~clk;
#4
clk = ~clk;
#1
if(count == 100) begin clock_train = 1'b0; align_train = 1'b1; end
if(count == 200) begin clock_train = 1'b0; align_train = 1'b0; end
#3
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
count = count + 1;
end
end
insert_training_pattern i_insert_training_pattern(
.clk (clk),
.clock_train (clock_train),
.align_train (align_train),
.in_data (in_data),
.out_data (out_data)
);
endmodule |
module tb_data_stream;
reg tx_symbol_clk;
reg tx_align_train;
reg tx_clock_train;
reg tx_link_established;
reg f;
wire [72:0] msa_merged_data;
wire test_signal_ready;
wire [2:0] stream_channel_count;
initial begin
tx_symbol_clk = 1'b0;
tx_align_train = 1'b0;
tx_clock_train = 1'b0;
tx_link_established = 1'b1;
end
always begin
#4 // Should be 135MHz, but 125 is close enough for simulation
tx_symbol_clk = ~tx_symbol_clk;
#4 // Should be 135MHz, but 125 is close enough for simulation
tx_symbol_clk = ~tx_symbol_clk;
$display("%b %b",
msa_merged_data[8:0], msa_merged_data[26:18]
);
$display("%b %b",
msa_merged_data[17:9], msa_merged_data[35:27]
);
end
///////////////////////////////////////////////////
// Video pipeline
/////////////////////////////////////////%/////////
test_source i_test_source(
.clk (tx_symbol_clk),
.stream_channel_count (stream_channel_count),
.ready (test_signal_ready),
.data (msa_merged_data)
);
wire [79:0] tx_symbols;
main_stream_processing i_main_stream_processing(
.symbol_clk (tx_symbol_clk),
.tx_link_established (tx_link_established),
.source_ready (test_signal_ready),
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
.in_data (msa_merged_data),
.tx_symbols (tx_symbols)
);
endmodule |
module tb_scrambler_all_channels;
reg clk = 1'b0;
reg bypass0;
reg bypass1;
reg [71:0] in_data;
wire [71:0] out_data;
wire [8:0] data0;
wire [8:0] data1;
localparam [8:0] scrambler_reset = 9'b100011100;
assign data0 = out_data[8:0];
assign data1 = out_data[17:9];
//--------------------------------------------------------------------------------
// Should be verified against the table in Appendix C of the "PCI Express Base
// Specification 2.1" which uses the same polynomial.
//
// Here are the first 32 output words when data values of "00" are scrambled:
//
// If the Scramble reset code is in the first word:
//
// cycle | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
// ------+------------------------------------------------
// data0 |[SR]17 14 E7 82 6E A6 6D 8D 40 E6 D3 B2 02 2A 34 E0
// data1 | FF C0 B2 02 72 28 BE BF BE A7 2C E2 07 77 CD BE ...
//
// If the Scramble reset code is in the second word:
//
// cycle | 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
// ------+------------------------------------------------
// data0 | xx FF C0 B2 02 72 28 BE BF BE A7 2C E2 07 77 CD BE ...
// data1 |[SR]17 14 E7 82 6E A6 6D 8D 40 E6 D3 B2 02 2A 34 E0
//
//--------------------------------------------------------------------------------
initial begin
bypass0 = 0;
bypass1 = 0;
in_data = 72'b0;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
#4
clk = ~clk;
in_data[8:0] = scrambler_reset;
#4
clk = ~clk;
#4
clk = ~clk;
in_data = 72'b0;
#4
clk = ~clk;
#4
clk = ~clk;
forever #4 clk = ~clk; // generate a clock
end
scrambler_all_channels i_scrambler_all_channels(
.clk (clk),
.bypass0 (bypass0),
.bypass1 (bypass1),
.in_data (in_data),
.out_data (out_data)
);
endmodule |
module tb_gtx_tx_reset_controller;
reg clk = 1'b0;
reg powerup_channel;
reg plllock;
reg txresetdone;
reg ref_clk;
wire tx_running;
wire txreset;
wire txuserrdy;
wire txpmareset;
wire txpcsreset;
wire pllpd;
wire pllreset;
wire plllocken;
wire resetsel;
reg [15:0] count;
initial begin
count = 16'd0;
powerup_channel = 1'b1;
plllock = 1'b0;
txresetdone = 1'b0;
ref_clk = 1'b0;
forever begin
#1
if(count == 16'd500) begin
powerup_channel = 1'b0;
end
if(count == 16'd700) begin
plllock = 1'b1;
end
if(count == 16'd1000) begin
txresetdone = 1'b1;
end
#4
ref_clk = 1'b1;
clk = 1'b1;
#5
clk = 1'b0;
ref_clk = 1'b0;
count = count + 1;
end
end
gtx_tx_reset_controller i_gtx_tx_reset_controller(
.clk (clk),
.ref_clk (ref_clk),
.powerup_channel (powerup_channel),
.plllock (plllock),
.txresetdone (txresetdone),
.tx_running (tx_running),
.txreset (txreset),
.txuserrdy (txuserrdy),
.txpmareset (txpmareset),
.txpcsreset (txpcsreset),
.pllpd (pllpd),
.pllreset (pllreset),
.plllocken (plllocken),
.resetsel (resetsel)
);
endmodule |
module tb_top_level;
reg clk100;
wire [7:0] debug;
wire [1:0] dp_tx_lane_p;
wire [1:0] dp_tx_lane_n;
wire [7:0] LED;
//////////////////////////////////////////
reg dp_refclk_p;
reg dp_refclk_n;
reg mgtrefclk1_p;
reg mgtrefclk1_n;
//////////////////////////////////////////
wire dp_tx_hp_detect;
wire dp_tx_auxch_tx_p;
wire dp_tx_auxch_tx_n;
wire dp_tx_auxch_rx_p;
wire dp_tx_auxch_rx_n;
///////////////////////////////////////////
reg [3:0] sw;
wire auxch_data;
reg [31:0] i, j, k;
initial begin
clk100 = 1'b0;
dp_refclk_p = 1'b1;
dp_refclk_n = 1'b0;
mgtrefclk1_p = 1'b0;
mgtrefclk1_n = 1'b1;
sw = 3'b001;
i = 31'b0;
j = 31'b0;
k = 31'b0;
end
always begin
#5 clk100 = ~clk100; // generate a clock
end
always begin
#4 dp_refclk_p = ~dp_refclk_p; dp_refclk_n = ~dp_refclk_n;// generate a clock
end
assign dp_tx_auxch_rx_p = auxch_data;
assign dp_tx_auxch_rx_n = ~auxch_data;
tb_dummy_sink i_tb_dummy_sink(
.clk100 (clk100),
.auxch_data (auxch_data),
.hotplug_detect (dp_tx_hp_detect)
);
top_level_nexys_video i_top_level_nexys_video(
.clk100 (clk100),
//////////////////////////////////////////
.dp_tx_lane_p (dp_tx_lane_p),
.dp_tx_lane_n (dp_tx_lane_n),
//////////////////////////////////////////
.dp_refclk_p (dp_refclk_p),
.dp_refclk_n (dp_refclk_n),
.mgtrefclk1_p (mgtrefclk1_p),
.mgtrefclk1_n (mgtrefclk1_n),
//////////////////////////////////////////
.dp_tx_hp_detect (dp_tx_hp_detect),
.dp_tx_auxch_tx_p (dp_tx_auxch_tx_p),
.dp_tx_auxch_tx_n (dp_tx_auxch_tx_n),
.dp_tx_auxch_rx_p (dp_tx_auxch_rx_p),
.dp_tx_auxch_rx_n (dp_tx_auxch_rx_n),
///////////////////////////////////////////
.debug (debug),
.sw (sw),
.LED (LED)
);
endmodule |
module tb_dummy_sink(
input clk100,
output auxch_data,
output reg hotplug_detect
);
wire [7:0] sender_debug_pmod;
wire sender_aux_tri;
reg sender_wr_en;
reg [7:0] sender_wr_data;
wire sender_wr_full;
//----------------------------
reg sender_rd_en;
wire [7:0] sender_rd_data;
wire sender_rd_empty;
wire sender_busy;
wire sender_timeout;
reg sender_abort;
aux_interface sender(
.clk (clk100),
.debug_pmod (sender_debug_pmod),
//----------------------------
.aux_in (1'b1),
.aux_out (auxch_data),
.aux_tri (sender_aux_tri),
//----------------------------
.tx_wr_en (sender_wr_en),
.tx_data (sender_wr_data),
.tx_full (sender_wr_full),
//----------------------------
.rx_rd_en (sender_rd_en),
.rx_data (sender_rd_data),
.rx_empty (sender_rd_empty),
//----------------------------
.busy (sender_busy),
.abort (sender_abort),
.timeout (sender_timeout)
);
initial begin
hotplug_detect = 1'b0;
sender_wr_en = 1'b0;
sender_wr_data = 8'h00;
sender_rd_en = 1'b0;
sender_abort = 1'b0;
sender_rd_en = 1'b0;
sender_wr_en = 1'b0;
sender_abort = 1'b0;
#1000
hotplug_detect = 1'b1;
#200000
/////////////////////////////////////////////////////
// Reply to the read command
//////////////////////////////////////////////////////
sender_wr_data = 8'h00;
sender_wr_en = 1'b1;
#10
sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 0
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h5A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h63; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h2F; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hCE; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 1
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h29; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h18; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h04; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hB5; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h3E; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h22; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h78; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h3A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h08; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA5; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA2; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h57; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4F; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA2; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h28; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 2
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h0F; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h50; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h54; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA5; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4B; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h71; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4F; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h81; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h81; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h80; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA9; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h40; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hB3; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 3
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hD1; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hC0; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hD1; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA3; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h66; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA0; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hF0; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h70; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h1f; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h80; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h30; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 4
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h35; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h6D; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h55; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h21; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h1A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFF; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h55; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h32; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4E; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 5
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h31; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h34; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h34; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h31; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h30; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h30; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h30; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h38; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h38; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h0A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFC; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h56; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 6
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h58; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h32; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h38; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h38; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h30; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4D; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h4C; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h0A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hFD; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// EDID Bloack 7
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10
sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h18; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h55; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h1F; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h72; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h1E; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h0A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h42; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// REPLY to READ SINK COUNT 90 02 00 00 00 01
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// REPLY to READ CONFIG registers
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h11; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h0A; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'hA4; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h81; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET 8b/10b CODING
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET LINK BANDWIDTH
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET DOWNSPREAD
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET LANE COUNT
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET TRAINING PATTERN
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET VOLTAGE ( request retry)!
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h20; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET VOLTAGE
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to READ LINK STATUS (7 registers)
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h01; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h80; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to READ LINK ADJUST REQUST (2 regs)
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#300000
/////////////////////////////////////////////////////
// Reply to SET TRAINING PATTERN
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to SET VOLTAGE
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#600000
/////////////////////////////////////////////////////
// Reply to READ LINK STATUS (7 registers)
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h07; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h81; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// Reply to READ LINK ADJUST REQUST (2 regs)
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#400000
/////////////////////////////////////////////////////
// Reply to SET TRAINING PATTERN OFF
//////////////////////////////////////////////////////
sender_abort = 1'b1;
#10 sender_abort = 1'b0;
#10 sender_wr_data = 8'h00; sender_wr_en = 1'b1;
#10 sender_wr_en = 1'b0;
#200000
/////////////////////////////////////////////////////
// All done!
///////////////////////////////////////////////////
sender_wr_en = 1'b0;
#200000000
sender_wr_en = 1'b0;
end
endmodule |
module transceiver_bank(
input mgmt_clk,
input [1:0] powerup_channel,
input preemp_0p0,
input preemp_3p5,
input preemp_6p0,
input swing_0p4,
input swing_0p6,
input swing_0p8,
output [1:0] tx_running,
input refclk0,
input refclk1,
output tx_symbol_clk,
input [79:0] tx_symbols,
output [1:0] gtptx_p,
output [1:0] gtptx_n
);
reg [1:0] ref_clk_fabric;
wire pll0lock;
reg resetsel;
reg [4:0] preemp_level;
reg [3:0] swing_level;
localparam PLL0_FBDIV_IN = 4;
localparam PLL1_FBDIV_IN = 1;
localparam PLL0_FBDIV_45_IN = 5;
localparam PLL1_FBDIV_45_IN = 4;
localparam PLL0_REFCLK_DIV_IN = 1;
localparam PLL1_REFCLK_DIV_IN = 1;
wire pll0clk;
wire pll0refclk;
wire pll1clk;
wire pll1refclk;
wire [1:0] txusrclk;
wire [1:0] txusrclk2;
wire [1:0] tx_out_clk;
wire [1:0] pll_pd;
wire [1:0] pll_reset;
wire [1:0] pll_locken;
wire tx_symbol_clk_i;
assign tx_symbol_clk = tx_symbol_clk_i;
wire [7:0] ignore_dmonitorout;
wire [15:0] ignore_drpdo;
wire ignore_drprdy;
wire ignore_pll0fbclklost;
wire ignore_pll0refclklost;
wire ignore_pll1fbclklost;
wire ignore_pll1lock;
wire ignore_pll1refclklost;
wire ignore_refclkoutmonitor0;
wire ignore_refclkoutmonitor1;
wire [15:0] ignore_pmarsvdout;
BUFG i_bufg(
.I (tx_out_clk[0]),
.O (tx_symbol_clk_i)
);
always @(*) begin
if(preemp_6p0 == 1'b1) begin
preemp_level <= 5'b10100; // +6.0 db
end else if(preemp_3p5 == 1'b1) begin
preemp_level <= 5'b01101; // +3.5 db;
end else begin
preemp_level <= 5'b00000; // +0.0 db
end
if(swing_0p8 == 1'b1) begin
swing_level <= 4'b1000; // 0.8 V
end else if(swing_0p6 == 1'b1) begin
swing_level <= 4'b0101; // 0.6 V
end else begin
swing_level <= 4'b0010; // 0.4 V
end
end
GTPE2_COMMON #(
.PLL0_FBDIV (PLL0_FBDIV_IN),
.PLL0_FBDIV_45 (PLL0_FBDIV_45_IN),
.PLL0_REFCLK_DIV (PLL0_REFCLK_DIV_IN),
.PLL1_FBDIV (PLL1_FBDIV_IN),
.PLL1_FBDIV_45 (PLL1_FBDIV_45_IN),
.PLL1_REFCLK_DIV (PLL1_REFCLK_DIV_IN),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000000000050001),
.COMMON_CFG (32'h00000000),
//--------------------------PLL Attributes----------------------------
.PLL0_CFG (28'h01F03DC),
.PLL0_DMON_CFG (1'b0),
.PLL0_INIT_CFG (24'h00001E),
.PLL0_LOCK_CFG (12'h1E8),
.PLL1_CFG (28'h01F03DC),
.PLL1_DMON_CFG (1'b0),
.PLL1_INIT_CFG (24'h00001E),
.PLL1_LOCK_CFG (12'h1E8),
.PLL_CLKOUT_CFG (8'h00),
//---------------------------Reserved Attributes----------------------------
.RSVD_ATTR0 (16'h0000),
.RSVD_ATTR1 (16'h0000))
i_gtpe2_common
(
.DMONITOROUT (ignore_dmonitorout),
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (8'b00000000),
.DRPCLK (1'b0),
.DRPDI (16'h0000),
.DRPDO (ignore_drpdo),
.DRPEN (1'b0),
.DRPRDY (ignore_drprdy),
.DRPWE (1'b0),
//--------------- Common Block - GTPE2_COMMON Clocking Ports ---------------
.GTEASTREFCLK0 (1'b0),
.GTEASTREFCLK1 (1'b0),
.GTGREFCLK1 (1'b0),
.GTREFCLK0 (refclk0),
.GTREFCLK1 (refclk1),
.GTWESTREFCLK0 (1'b0),
.GTWESTREFCLK1 (1'b0),
.PLL0OUTCLK (pll0clk),
.PLL0OUTREFCLK (pll0refclk),
.PLL1OUTCLK (pll1clk),
.PLL1OUTREFCLK (pll1refclk),
//------------------------ Common Block - PLL Ports ------------------------
.PLL0FBCLKLOST (ignore_pll0fbclklost),
.PLL0LOCK (pll0lock),
.PLL0LOCKDETCLK (mgmt_clk),
.PLL0LOCKEN (1'b1),
.PLL0PD (pll_pd[0]),
.PLL0REFCLKLOST (ignore_pll0refclklost),
.PLL0REFCLKSEL (3'b001), // ref clock 0
.PLL0RESET (pll_reset[0]),
.PLL1FBCLKLOST (ignore_pll1fbclklost),
.PLL1LOCK (ignore_pll1lock),
.PLL1LOCKDETCLK (1'b0),
.PLL1LOCKEN (1'b1),
.PLL1PD (1'b1),
.PLL1REFCLKLOST (ignore_pll1refclklost),
.PLL1REFCLKSEL (3'b001),
.PLL1RESET (1'b0),
//-------------------------- Common Block - Ports --------------------------
.BGRCALOVRDENB (1'b1),
.GTGREFCLK0 (1'b0),
.PLLRSVD1 (16'b0000000000000000),
.PLLRSVD2 (5'b00000),
.REFCLKOUTMONITOR0 (ignore_refclkoutmonitor0),
.REFCLKOUTMONITOR1 (ignore_refclkoutmonitor1),
//---------------------- Common Block - RX AFE Ports -----------------------
.PMARSVDOUT (ignore_pmarsvdout),
//------------------------------- QPLL Ports -------------------------------
.BGBYPASSB (1'b1),
.BGMONITORENB (1'b1),
.BGPDB (1'b1),
.BGRCALOVRD (5'b11111),
.PMARSVD (8'b00000000),
.RCALENB (1'b1)
);
transceiver tx0(
.mgmt_clk (mgmt_clk),
.powerup_channel (powerup_channel[0]),
.preemp_level (preemp_level),
.swing_level (swing_level),
.tx_running (tx_running[0]),
.pll0clk (pll0clk),
.pll0refclk (pll0refclk),
.pll1clk (pll1clk),
.pll1refclk (pll1refclk),
.pll_pd (pll_pd[0]),
.pll_reset (pll_reset[0]),
.pll_locken (pll_locken[0]),
.pll_lock (pll0lock),
.tx_out_clk (tx_out_clk[0]),
.tx_symbol_clk (tx_symbol_clk_i),
.tx_symbol (tx_symbols[19:0]),
.gtptx_p (gtptx_p[0]),
.gtptx_n (gtptx_n[0])
);
transceiver tx1(
.mgmt_clk (mgmt_clk),
.powerup_channel (powerup_channel[1]),
.preemp_level (preemp_level),
.swing_level (swing_level),
.tx_running (tx_running[1]),
.pll0clk (pll0clk),
.pll0refclk (pll0refclk),
.pll1clk (pll1clk),
.pll1refclk (pll1refclk),
.pll_pd (pll_pd[1]),
.pll_reset (pll_reset[1]),
.pll_locken (pll_locken[1]),
.pll_lock (pll0lock),
.tx_out_clk (tx_out_clk[1]),
.tx_symbol_clk (tx_symbol_clk_i),
.tx_symbol (tx_symbols[39:20]),
.gtptx_p (gtptx_p[1]),
.gtptx_n (gtptx_n[1])
);
endmodule |
module transceiver(
input mgmt_clk,
input powerup_channel,
input [4:0] preemp_level,
input [3:0] swing_level,
output tx_running,
input pll0clk,
input pll0refclk,
output pll_pd ,
output pll_reset,
output pll_locken,
input pll_lock,
input pll1clk,
input pll1refclk,
output tx_out_clk,
input tx_symbol_clk,
input [19:0] tx_symbol,
output gtptx_p,
output gtptx_n);
wire [3:0] txchardispmode;
wire [3:0] txchardispval;
wire [31:0] txdata_for_tx;
wire [3:0] txdata_iskchark;
wire ref_clk_fabric;
wire txreset;
wire txresetdone;
wire txpcsreset;
wire txpmareset;
wire txuserrdy;
wire resetsel;
wire txusrclk;
wire txusrclk2;
wire [15:0] ignore_DRPDO;
wire ignore_DRPRDY;
wire ignore_PHYSTATUS;
wire ignore_RXVALID;
wire ignore_EYESCANDATAERROR;
wire ignore_RXPMARESETDONE;
wire ignore_RXCDRLOCK;
wire ignore_RXOSINTDONE;
wire ignore_RXOSINTSTARTED;
wire ignore_RXOSINTSTROBESTARTED;
wire [1:0] ignore_RXCLKCORCNT;
wire [31:0] ignore_RXDATA;
wire ignore_RXPRBSERR;
wire [3:0] ignore_RXCHARISCOMMA;
wire [3:0] ignore_RXCHARISK;
wire [3:0] ignore_RXDISPERR;
wire [3:0] ignore_RXNOTINTABLE;
wire ignore_PMARSVDOUT0;
wire ignore_PMARSVDOUT1;
wire [2:0] ignore_RXBUFSTATUS;
wire ignore_RXDLYSRESETDONE;
wire ignore_RXPHALIGNDONE;
wire [4:0] ignore_RXPHMONITOR;
wire [4:0] ignore_RXPHSLIPMONITOR;
wire [2:0] ignore_RXSTATUS;
wire ignore_RXSYNCDONE;
wire ignore_RXSYNCOUT;
wire ignore_RXBYTEISALIGNED;
wire ignore_RXBYTEREALIGN;
wire ignore_RXCOMMADET;
wire ignore_RXCHANBONDSEQ;
wire [3:0] ignore_RXCHBONDO;
wire ignore_RXCHANISALIGNED;
wire ignore_RXCHANREALIGN;
wire [14:0] ignore_DMONITOROUT;
wire ignore_RXOSINTSTROBEDONE;
wire ignore_RXRATEDONE;
wire ignore_RXOUTCLK;
wire ignore_RXOUTCLKFABRIC;
wire ignore_RXOUTCLKPCS;
wire [1:0] ignore_RXDATAVALID;
wire [2:0] ignore_RXHEADER;
wire ignore_RXHEADERVALID;
wire [1:0] ignore_RXSTARTOFSEQ;
wire ignore_RXCOMSASDET;
wire ignore_RXCOMWAKEDET;
wire ignore_RXCOMINITDET;
wire ignore_RXELECIDLE;
wire ignore_RXRESETDONE;
wire [15:0] ignore_PCSRSVDOUT;
wire ignore_TXPMARESETDONE;
wire ignore_TXDLYSRESETDONE;
wire ignore_TXPHALIGNDONE;
wire ignore_TXPHINITDONE;
wire [1:0] ignore_TXBUFSTATUS;
wire ignore_TXSYNCDONE;
wire ignore_TXSYNCOUT;
wire ignore_TXOUTCLKPCS;
wire ignore_TXRATEDONE;
wire ignore_TXGEARBOXREADY;
wire ignore_TXCOMFINISH;
assign txusrclk = tx_symbol_clk;
assign txusrclk2 = tx_symbol_clk;
assign txdata_for_tx[7:0] = tx_symbol[7:0];
assign txdata_iskchark[0] = tx_symbol[8];
assign txchardispval[0] = 1'b0;
assign txchardispmode[0] = tx_symbol[9];
assign txdata_for_tx[15:8] = tx_symbol[17:10];
assign txdata_iskchark[1] = tx_symbol[18];
assign txchardispval[1] = 1'b0;
assign txchardispmode[1] = tx_symbol[19];
gtx_tx_reset_controller i_gtx_tx_reset_controller(
.clk (mgmt_clk),
.ref_clk (ref_clk_fabric),
.powerup_channel (powerup_channel),
.tx_running (tx_running),
.pllpd (pll_pd),
.pllreset (pll_reset),
.plllocken (pll_locken),
.plllock (pll_lock),
.txreset (txreset),
.txpmareset (txpmareset),
.txpcsreset (txpcsreset),
.txuserrdy (txuserrdy),
.resetsel (resetsel),
.txresetdone (txresetdone));
GTPE2_CHANNEL #(
// Simulation-Only Attributes
.SIM_RECEIVER_DETECT_PASS ("TRUE"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_TX_EIDLE_DRIVE_LEVEL ("X"),
.SIM_VERSION ("2.0"),
// RX Byte and Word Alignment Attributes
.ALIGN_COMMA_DOUBLE ("FALSE"),
.ALIGN_COMMA_ENABLE (10'b1111111111),
.ALIGN_COMMA_WORD (1),
.ALIGN_MCOMMA_DET ("TRUE"),
.ALIGN_MCOMMA_VALUE (10'b1010000011),
.ALIGN_PCOMMA_DET ("TRUE"),
.ALIGN_PCOMMA_VALUE (10'b0101111100),
.SHOW_REALIGN_COMMA ("TRUE"),
.RXSLIDE_AUTO_WAIT (7),
.RXSLIDE_MODE ("OFF"),
.RX_SIG_VALID_DLY (10),
// RX 8B/10B Decoder Attributes
.RX_DISPERR_SEQ_MATCH ("FALSE"),
.DEC_MCOMMA_DETECT ("FALSE"),
.DEC_PCOMMA_DETECT ("FALSE"),
.DEC_VALID_COMMA_ONLY ("FALSE"),
// RX Clock Correction Attributes
.CBCC_DATA_SOURCE_SEL ("ENCODED"),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
.CLK_COR_MAX_LAT (9),
.CLK_COR_MIN_LAT (7),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_LEN (1),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_1_1 (10'b0100000000),
.CLK_COR_SEQ_1_2 (10'b0000000000),
.CLK_COR_SEQ_1_3 (10'b0000000000),
.CLK_COR_SEQ_1_4 (10'b0000000000),
.CLK_CORRECT_USE ("FALSE"),
.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0000000000),
.CLK_COR_SEQ_2_3 (10'b0000000000),
.CLK_COR_SEQ_2_4 (10'b0000000000),
// RX Channel Bonding Attributes
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_MAX_SKEW (1),
.CHAN_BOND_SEQ_LEN (1),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.FTS_DESKEW_SEQ_ENABLE (4'b1111),
.FTS_LANE_DESKEW_CFG (4'b1111),
.FTS_LANE_DESKEW_EN ("FALSE"),
// RX Margin Analysis Attributes
.ES_CONTROL (6'b000000),
.ES_ERRDET_EN ("FALSE"),
.ES_EYE_SCAN_EN ("FALSE"),
.ES_HORZ_OFFSET (3'b010),
.ES_PMA_CFG (10'b0000000000),
.ES_PRESCALE (5'b00000),
.ES_QUALIFIER (64'h00000000000000000000),
.ES_QUAL_MASK (64'h00000000000000000000),
.ES_SDATA_MASK (64'h00000000000000000000),
.ES_VERT_OFFSET (9'b000000000),
// FPGA RX Interface Attributes
.RX_DATA_WIDTH (20),
// PMA Attributes
.OUTREFCLK_SEL_INV (2'b11),
.PMA_RSV (32'h00000333),
.PMA_RSV2 (32'h00002040),
.PMA_RSV3 (2'b00),
.PMA_RSV4 (4'b0000),
.RX_BIAS_CFG (16'b0000111100110011),
.DMONITOR_CFG (24'h000A00),
.RX_CM_SEL (2'h01),
.RX_CM_TRIM (4'h0000),
.RX_DEBUG_CFG (56'h00000000000000),
.RX_OS_CFG (13'b0000010000000),
.TERM_RCAL_CFG (15'b100001000010000),
.TERM_RCAL_OVRD (3'h000),
.TST_RSV (32'h00000000),
.RX_CLK25_DIV (6),
.TX_CLK25_DIV (6),
.UCODEER_CLR (1'b0),
// PCI Express Attributes
.PCS_PCIE_EN ("FALSE"),
// PCS Attributes
.PCS_RSVD_ATTR (48'h000000000000),
// RX Buffer Attributes
.RXBUF_ADDR_MODE ("FAST"),
.RXBUF_EIDLE_HI_CNT (4'b1000),
.RXBUF_EIDLE_LO_CNT (4'b0000),
.RXBUF_EN ("TRUE"),
.RX_BUFFER_CFG (6'b000000),
.RXBUF_RESET_ON_CB_CHANGE ("TRUE"),
.RXBUF_RESET_ON_COMMAALIGN ("FALSE"),
.RXBUF_RESET_ON_EIDLE ("FALSE"),
.RXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.RXBUFRESET_TIME (5'b00001),
.RXBUF_THRESH_OVFLW (61),
.RXBUF_THRESH_OVRD ("FALSE"),
.RXBUF_THRESH_UNDFLW (4),
.RXDLY_CFG (16'h001F),
.RXDLY_LCFG (12'h030),
.RXDLY_TAP_CFG (16'h0000),
.RXPH_CFG (24'hC00002),
.RXPHDLY_CFG (24'h084020),
.RXPH_MONITOR_SEL (5'b00000),
.RX_XCLK_SEL ("RXREC"),
.RX_DDI_SEL (6'b000000),
.RX_DEFER_RESET_BUF_EN ("TRUE"),
// CDR Attributes
.RXCDR_CFG (84'h0001107FE206021081010),
.RXCDR_FR_RESET_ON_EIDLE (1'b0),
.RXCDR_HOLD_DURING_EIDLE (1'b0),
.RXCDR_PH_RESET_ON_EIDLE (1'b0),
.RXCDR_LOCK_CFG (6'b001001),
// RX Initialization and Reset Attributes
.RXCDRFREQRESET_TIME (5'b00001),
.RXCDRPHRESET_TIME (5'b00001),
.RXISCANRESET_TIME (5'b00001),
.RXPCSRESET_TIME (5'b00001),
.RXPMARESET_TIME (5'b00011),
// RX OOB Signaling Attributes
.RXOOB_CFG (7'b0000110),
// RX Gearbox Attributes
.RXGEARBOX_EN ("FALSE"),
.GEARBOX_MODE (3'b000),
// PRBS Detection Attribute
.RXPRBS_ERR_LOOPBACK (1'b0),
// Power-Down Attributes
.PD_TRANS_TIME_FROM_P2 (12'h03c),
.PD_TRANS_TIME_NONE_P2 (8'h3c),
.PD_TRANS_TIME_TO_P2 (8'h64),
// RX OOB Signaling Attributes
.SAS_MAX_COM (64),
.SAS_MIN_COM (36),
.SATA_BURST_SEQ_LEN (4'b0101),
.SATA_BURST_VAL (3'b100),
.SATA_EIDLE_VAL (3'b100),
.SATA_MAX_BURST (8),
.SATA_MAX_INIT (21),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
// RX Fabric Clock Output Control Attributes
.TRANS_TIME_RATE (8'h0E),
// TX Buffer Attributes
.TXBUF_EN ("TRUE"),
.TXBUF_RESET_ON_RATE_CHANGE ("TRUE"),
.TXDLY_CFG (16'h001F),
.TXDLY_LCFG (12'h030),
.TXDLY_TAP_CFG (16'h0000),
.TXPH_CFG (16'h0780),
.TXPHDLY_CFG (24'h084020),
.TXPH_MONITOR_SEL (5'b00000),
.TX_XCLK_SEL ("TXOUT"),
// FPGA TX Interface Attributes
.TX_DATA_WIDTH (20),
// TX Configurable Driver Attributes
.TX_DEEMPH0 (6'b000000),
.TX_DEEMPH1 (6'b000000),
.TX_EIDLE_ASSERT_DELAY (3'b110),
.TX_EIDLE_DEASSERT_DELAY (3'b100),
.TX_LOOPBACK_DRIVE_HIZ ("FALSE"),
.TX_MAINCURSOR_SEL (1'b0),
.TX_DRIVE_MODE ("DIRECT"),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
// TX Gearbox Attributes
.TXGEARBOX_EN ("FALSE"),
// TX Initialization and Reset Attributes
.TXPCSRESET_TIME (5'b00001),
.TXPMARESET_TIME (5'b00001),
// TX Receiver Detection Attributes
.TX_RXDETECT_CFG (16'h1832),
.TX_RXDETECT_REF (3'b100),
// JTAG Attributes
.ACJTAG_DEBUG_MODE (1'b0),
.ACJTAG_MODE (1'b0),
.ACJTAG_RESET (1'b0),
// CDR Attributes
.CFOK_CFG (44'h49000040E80),
.CFOK_CFG2 (7'b0100000),
.CFOK_CFG3 (7'b0100000),
.CFOK_CFG4 (1'b0),
.CFOK_CFG5 (4'h0),
.CFOK_CFG6 (4'b0000),
.RXOSCALRESET_TIME (5'b00011),
.RXOSCALRESET_TIMEOUT (5'b00000),
// PMA Attributes
.CLK_COMMON_SWING (1'b0),
.RX_CLKMUX_EN (1'b1),
.TX_CLKMUX_EN (1'b1),
.ES_CLK_PHASE_SEL (1'b0),
.USE_PCS_CLK_PHASE_SEL (1'b0),
.PMA_RSV6 (1'b0),
.PMA_RSV7 (1'b0),
// TX Configuration Driver Attributes
.TX_PREDRIVER_MODE (1'b0),
.PMA_RSV5 (1'b0),
.SATA_PLL_CFG ("VCO_3000MHZ"),
// RX Fabric Clock Outpu:t Control Attributes
.RXOUT_DIV (2),
// TX Fabric Clock Output Control Attributes
.TXOUT_DIV (2),
// RX Phase Interpolator Attributes
.RXPI_CFG0 (3'b000),
.RXPI_CFG1 (1'b1),
.RXPI_CFG2 (1'b1),
// RX Equalizer Attributes
.ADAPT_CFG0 (20'h00000),
.RXLPMRESET_TIME (7'b0001111),
.RXLPM_BIAS_STARTUP_DISABLE (1'b0),
.RXLPM_CFG (4'b0110),
.RXLPM_CFG1 (1'b0),
.RXLPM_CM_CFG (1'b0),
.RXLPM_GC_CFG (9'b111100010),
.RXLPM_GC_CFG2 (3'b001),
.RXLPM_HF_CFG (14'b00001111110000),
.RXLPM_HF_CFG2 (5'b01010),
.RXLPM_HF_CFG3 (4'b0000),
.RXLPM_HOLD_DURING_EIDLE (1'b0),
.RXLPM_INCM_CFG (1'b0),
.RXLPM_IPCM_CFG (1'b1),
.RXLPM_LF_CFG (18'b000000001111110000),
.RXLPM_LF_CFG2 (5'b01010),
.RXLPM_OSINT_CFG (3'b100),
// TX Phase Interpolator PPM Controller Attributes
.TXPI_CFG0 (2'b00),
.TXPI_CFG1 (2'b00),
.TXPI_CFG2 (2'b00),
.TXPI_CFG3 (1'b0),
.TXPI_CFG4 (1'b0),
.TXPI_CFG5 (3'b000),
.TXPI_GREY_SEL (1'b0),
.TXPI_INVSTROBE_SEL (1'b0),
.TXPI_PPMCLK_SEL ("TXUSRCLK2"),
.TXPI_PPM_CFG (8'h00),
.TXPI_SYNFREQ_PPM (3'b000),
// LOOPBACK Attributes
.LOOPBACK_CFG (1'b0),
.PMA_LOOPBACK_CFG (1'b0),
// RX OOB Signalling Attributes
.RXOOB_CLK_CFG ("PMA"),
// TX OOB Signalling Attributes
.TXOOB_CFG (1'b0),
// RX Buffer Attributes
.RXSYNC_MULTILANE (1'b1),
.RXSYNC_OVRD (1'b0),
.RXSYNC_SKIP_DA (1'b0),
// TX Buffer Attribute
.TXSYNC_MULTILANE (1'b0),
.TXSYNC_OVRD (1'b0),
.TXSYNC_SKIP_DA (1'b0)
)
i_gtpe2 (
// CPLL Ports
.GTRSVD (16'b0000000000000000),
.PCSRSVDIN (16'b0000000000000000),
.TSTIN (20'b11111111111111111111),
// Channel - DRP Ports
.DRPADDR (9'b0),
.DRPCLK (1'b0),
.DRPDI (16'h0000),
.DRPDO (ignore_DRPDO),
.DRPEN (1'b0),
.DRPRDY (ignore_DRPRDY),
.DRPWE (1'b0),
// Clocking Ports
.RXSYSCLKSEL (2'b11),
.TXSYSCLKSEL (2'b00),
// FPGA TX Interface Datapath Configuration
.TX8B10BEN (1'b1),
// GTPE2_CHANNEL Clocking Ports
.PLL0CLK (pll0clk),
.PLL0REFCLK (pll0refclk),
.PLL1CLK (pll1clk),
.PLL1REFCLK (pll1refclk),
// Loopback Ports
.LOOPBACK (3'b000),
// PCI Express Ports
.PHYSTATUS (ignore_PHYSTATUS),
.RXRATE (3'b000),
.RXVALID (ignore_RXVALID),
// PMA Reserved Ports
.PMARSVDIN3 (1'b0),
.PMARSVDIN4 (1'b0),
// Power-Down Ports
.RXPD (2'b11),
.TXPD (2'b00),
// RX 8B/10B Decoder Ports
.SETERRSTATUS (1'b0),
// RX Initialization and Reset Ports
.EYESCANRESET (1'b0),
.RXUSERRDY (1'b0),
// RX Margin Analysis Ports
.EYESCANDATAERROR (ignore_EYESCANDATAERROR),
.EYESCANMODE (1'b0),
.EYESCANTRIGGER (1'b0),
// Receive Ports
.CLKRSVD0 (1'b0),
.CLKRSVD1 (1'b0),
.DMONFIFORESET (1'b0),
.DMONITORCLK (1'b0),
.RXPMARESETDONE (ignore_RXPMARESETDONE),
.SIGVALIDCLK (1'b0),
// Receive Ports - CDR Ports
.RXCDRFREQRESET (1'b0),
.RXCDRHOLD (1'b0),
.RXCDRLOCK (ignore_RXCDRLOCK),
.RXCDROVRDEN (1'b0),
.RXCDRRESET (1'b0),
.RXCDRRESETRSV (1'b0),
.RXOSCALRESET (1'b0),
.RXOSINTCFG (4'b0010),
.RXOSINTDONE (ignore_RXOSINTDONE),
.RXOSINTHOLD (1'b0),
.RXOSINTOVRDEN (1'b0),
.RXOSINTPD (1'b0),
.RXOSINTSTARTED (ignore_RXOSINTSTARTED),
.RXOSINTSTROBE (1'b0),
.RXOSINTSTROBESTARTED (ignore_RXOSINTSTROBESTARTED),
.RXOSINTTESTOVRDEN (1'b0),
// Receive Ports - Clock Correction Ports
.RXCLKCORCNT (ignore_RXCLKCORCNT),
// Receive Ports - FPGA RX Interface Datapath Configuration
.RX8B10BEN (1'b0),
// Receive Ports - FPGA RX Interface Ports
.RXDATA (ignore_RXDATA),
.RXUSRCLK (1'b0),
.RXUSRCLK2 (1'b0),
// Receive Ports - Pattern Checker Ports
.RXPRBSERR (ignore_RXPRBSERR),
.RXPRBSSEL (3'b000),
// Receive Ports - Pattern Checker ports
.RXPRBSCNTRESET (1'b0),
// Receive Ports - RX 8B/10B Decoder Ports
.RXCHARISCOMMA (ignore_RXCHARISCOMMA),
.RXCHARISK (ignore_RXCHARISK),
.RXDISPERR (ignore_RXDISPERR),
.RXNOTINTABLE (ignore_RXNOTINTABLE),
// Receive Ports - RX AFE Ports
.GTPRXN (1'b0),
.GTPRXP (1'b0),
.PMARSVDIN2 (1'b0),
.PMARSVDOUT0 (ignore_PMARSVDOUT0),
.PMARSVDOUT1 (ignore_PMARSVDOUT1),
// Receive Ports - RX Buffer Bypass Ports
.RXBUFRESET (1'b0),
.RXBUFSTATUS (ignore_RXBUFSTATUS),
.RXDDIEN (1'b0),
.RXDLYBYPASS (1'b1),
.RXDLYEN (1'b0),
.RXDLYOVRDEN (1'b0),
.RXDLYSRESET (1'b0),
.RXDLYSRESETDONE (ignore_RXDLYSRESETDONE),
.RXPHALIGN (1'b0),
.RXPHALIGNDONE (ignore_RXPHALIGNDONE),
.RXPHALIGNEN (1'b0),
.RXPHDLYPD (1'b1),
.RXPHDLYRESET (1'b0),
.RXPHMONITOR (ignore_RXPHMONITOR),
.RXPHOVRDEN (1'b0),
.RXPHSLIPMONITOR (ignore_RXPHSLIPMONITOR),
.RXSTATUS (ignore_RXSTATUS),
.RXSYNCALLIN (1'b0),
.RXSYNCDONE (ignore_RXSYNCDONE),
.RXSYNCIN (1'b0),
.RXSYNCMODE (1'b0),
.RXSYNCOUT (ignore_RXSYNCOUT),
// Receive Ports - RX Byte and Word Alignment Ports
.RXBYTEISALIGNED (ignore_RXBYTEISALIGNED),
.RXBYTEREALIGN (ignore_RXBYTEREALIGN),
.RXCOMMADET (ignore_RXCOMMADET),
.RXCOMMADETEN (1'b0),
.RXMCOMMAALIGNEN (1'b0),
.RXPCOMMAALIGNEN (1'b0),
.RXSLIDE (1'b0),
// Receive Ports - RX Channel Bonding Ports
.RXCHANBONDSEQ (ignore_RXCHANBONDSEQ),
.RXCHBONDEN (1'b0),
.RXCHBONDI (4'b0000),
.RXCHBONDLEVEL (3'b000),
.RXCHBONDMASTER (1'b0),
.RXCHBONDO (ignore_RXCHBONDO),
.RXCHBONDSLAVE (1'b0),
// Receive Ports - RX Channel Bonding Ports
.RXCHANISALIGNED (ignore_RXCHANISALIGNED),
.RXCHANREALIGN (ignore_RXCHANREALIGN),
// Receive Ports - RX Decision Feedback Equalizer(DFE)
.DMONITOROUT (ignore_DMONITOROUT),
.RXADAPTSELTEST (14'b00000000000000),
.RXDFEXYDEN (1'b0),
.RXOSINTEN (1'b1),
.RXOSINTID0 (4'b0000),
.RXOSINTNTRLEN (1'b0),
.RXOSINTSTROBEDONE (ignore_RXOSINTSTROBEDONE),
// Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR
.RXLPMLFOVRDEN (1'b0),
.RXLPMOSINTNTRLEN (1'b0),
// Receive Ports - RX Equailizer Ports
.RXLPMHFHOLD (1'b0),
.RXLPMHFOVRDEN (1'b0),
.RXLPMLFHOLD (1'b0),
// Receive Ports - RX Equalizer Ports
.RXOSHOLD (1'b0),
.RXOSOVRDEN (1'b0),
// Receive Ports - RX Fabric ClocK Output Control Ports
.RXRATEDONE (ignore_RXRATEDONE),
// Receive Ports - RX Fabric Clock Output Control Ports
.RXRATEMODE (1'b0),
// Receive Ports - RX Fabric Output Control Ports
.RXOUTCLK (ignore_RXOUTCLK),
.RXOUTCLKFABRIC (ignore_RXOUTCLKFABRIC),
.RXOUTCLKPCS (ignore_RXOUTCLKPCS),
.RXOUTCLKSEL (3'b010),
// Receive Ports - RX Gearbox Ports
.RXDATAVALID (ignore_RXDATAVALID),
.RXHEADER (ignore_RXHEADER),
.RXHEADERVALID (ignore_RXHEADERVALID),
.RXSTARTOFSEQ (ignore_RXSTARTOFSEQ),
// Receive Ports - RX Gearbox Ports
.RXGEARBOXSLIP (1'b0),
// Receive Ports - RX Initialization and Reset Ports
.GTRXRESET (1'b1),
.RXLPMRESET (1'b1),
.RXOOBRESET (1'b0),
.RXPCSRESET (1'b0),
.RXPMARESET (1'b0),
// Receive Ports - RX OOB Signaling ports
.RXCOMSASDET (ignore_RXCOMSASDET),
.RXCOMWAKEDET (ignore_RXCOMWAKEDET),
// Receive Ports - RX OOB Signaling ports
.RXCOMINITDET (ignore_RXCOMINITDET),
// Receive Ports - RX OOB signalling Ports
.RXELECIDLE (ignore_RXELECIDLE),
.RXELECIDLEMODE (2'b11),
// Receive Ports - RX Polarity Control Ports
.RXPOLARITY (1'b0),
// Receive Ports -RX Initialization and Reset Ports
.RXRESETDONE (ignore_RXRESETDONE),
// TX Buffer Bypass Ports
.TXPHDLYTSTCLK (1'b0),
// TX Configurable Driver Ports
.TXPOSTCURSOR (5'b00000),
.TXPOSTCURSORINV (1'b0),
.TXPRECURSOR (preemp_level),
.TXPRECURSORINV (1'b0),
// TX Fabric Clock Output Control Ports
.TXRATEMODE (1'b0),
// TX Initialization and Reset Ports
.CFGRESET (1'b0),
.GTTXRESET (txreset),
.PCSRSVDOUT (ignore_PCSRSVDOUT),
.TXUSERRDY (txuserrdy),
// TX Phase Interpolator PPM Controller Ports
.TXPIPPMEN (1'b0),
.TXPIPPMOVRDEN (1'b0),
.TXPIPPMPD (1'b0),
.TXPIPPMSEL (1'b1),
.TXPIPPMSTEPSIZE (5'b00000),
// Transceiver Reset Mode Operation
.GTRESETSEL (resetsel),
.RESETOVRD (1'b0),
// Transmit Ports
.TXPMARESETDONE (ignore_TXPMARESETDONE),
// Transmit Ports - Configurable Driver Ports
.PMARSVDIN0 (1'b0),
.PMARSVDIN1 (1'b0),
// Transmit Ports - FPGA TX Interface Ports
.TXDATA (txdata_for_tx[31:0]),
.TXUSRCLK (txusrclk),
.TXUSRCLK2 (txusrclk2),
// Transmit Ports - PCI Express Ports
.TXELECIDLE (1'b0),
.TXMARGIN (3'b000),
.TXRATE (3'b000),
.TXSWING (1'b0),
// Transmit Ports - Pattern Generator Ports
.TXPRBSFORCEERR (1'b0),
// Transmit Ports - TX 8B/10B Encoder Ports
.TX8B10BBYPASS (4'b0000),
.TXCHARDISPMODE (txchardispmode[3:0]),
.TXCHARDISPVAL (txchardispval[3:0]),
.TXCHARISK (txdata_iskchark[3:0]),
// Transmit Ports - TX Buffer Bypass Ports
.TXDLYBYPASS (1'b1),
.TXDLYEN (1'b0),
.TXDLYHOLD (1'b0),
.TXDLYOVRDEN (1'b0),
.TXDLYSRESET (1'b0),
.TXDLYSRESETDONE (ignore_TXDLYSRESETDONE),
.TXDLYUPDOWN (1'b0),
.TXPHALIGN (1'b0),
.TXPHALIGNDONE (ignore_TXPHALIGNDONE),
.TXPHALIGNEN (1'b0),
.TXPHDLYPD (1'b0),
.TXPHDLYRESET (1'b0),
.TXPHINIT (1'b0),
.TXPHINITDONE (ignore_TXPHINITDONE),
.TXPHOVRDEN (1'b0),
// Transmit Ports - TX Buffer Ports
.TXBUFSTATUS (ignore_TXBUFSTATUS),
// Transmit Ports - TX Buffer and Phase Alignment Ports
.TXSYNCALLIN (1'b0),
.TXSYNCDONE (ignore_TXSYNCDONE),
.TXSYNCIN (1'b0),
.TXSYNCMODE (1'b0),
.TXSYNCOUT (ignore_TXSYNCOUT),
// Transmit Ports - TX Configurable Driver Ports
.GTPTXN (gtptx_n),
.GTPTXP (gtptx_p),
.TXBUFDIFFCTRL (3'b100),
.TXDEEMPH (1'b0),
.TXDIFFCTRL (swing_level),
.TXDIFFPD (1'b0),
.TXINHIBIT (1'b0),
.TXMAINCURSOR (7'b0000000),
.TXPISOPD (1'b0),
// Transmit Ports - TX Fabric Clock Output Control Ports
.TXOUTCLK (tx_out_clk),
.TXOUTCLKFABRIC (ref_clk_fabric),
.TXOUTCLKPCS (ignore_TXOUTCLKPCS),
.TXOUTCLKSEL (3'b010),
.TXRATEDONE (ignore_TXRATEDONE),
// Transmit Ports - TX Gearbox Ports
.TXGEARBOXREADY (ignore_TXGEARBOXREADY),
.TXHEADER (3'b000),
.TXSEQUENCE (7'b0000000),
.TXSTARTSEQ (1'b0),
// Transmit Ports - TX Initialization and Reset Ports
.TXPCSRESET (txpcsreset),
.TXPMARESET (txpmareset),
.TXRESETDONE (txresetdone),
// Transmit Ports - TX OOB signalling Ports
.TXCOMFINISH (ignore_TXCOMFINISH),
.TXCOMINIT (1'b0),
.TXCOMSAS (1'b0),
.TXCOMWAKE (1'b0),
.TXPDELECIDLEMODE (1'b0),
// Transmit Ports - TX Polarity Control Ports
.TXPOLARITY (1'b0),
// Transmit Ports - TX Receiver Detection Ports
.TXDETECTRX (1'b0),
// Transmit Ports - pattern Generator Ports
.TXPRBSSEL (3'b000)
);
endmodule |
module gtx_tx_reset_controller (
input wire clk,
input wire ref_clk,
input wire powerup_channel,
input wire plllock,
input wire txresetdone,
output reg tx_running, //: out std_logic := '0';
output reg txreset, //: out std_logic := '1';
output reg txuserrdy, //: out std_logic := '0';
output reg txpmareset, //: out std_logic := '1';
output reg txpcsreset, //: out std_logic := '1';
output reg pllpd, //: out std_logic := '1';
output reg pllreset, //: out std_logic;
output reg plllocken, //: out std_logic := '1';
output reg resetsel // out std_logic := '0'
);
reg [3:0] state;
reg [7:0] ref_clk_counter;
reg [7:0] counter;
reg ref_clk_detect_last;
reg ref_clk_detect;
reg ref_clk_detect_meta; // TODO: Neet to set ASYNCREG
reg txresetdone_meta; // TODO: Neet to set ASYNCREG
reg txresetdone_i;
initial begin
state = 4'b0000;
ref_clk_counter = 8'b00000000;
counter = 8'b00000000;
ref_clk_detect_last = 1'b0;
ref_clk_detect = 1'b0;
ref_clk_detect_meta = 1'b0;
txresetdone_meta = 1'b1;
txresetdone_i = 1'b1;
tx_running = 1'b1;
txreset <= 1'b1;
txuserrdy <= 1'b0;
txpmareset <= 1'b1;
txpcsreset <= 1'b1;
pllpd <= 1'b1;
pllreset <= 1'b1;
plllocken <= 1'b0;
resetsel <= 1'b0;
end
always @(posedge ref_clk) begin
ref_clk_counter <= ref_clk_counter + 1;
end
always @(posedge clk) begin
counter <= counter + 1;
case(state)
4'b0000: begin // reset
txreset <= 1'b1;
txuserrdy <= 1'b0;
txpmareset <= 1'b0;
txpcsreset <= 1'b0;
pllpd <= 1'b1;
pllreset <= 1'b1;
plllocken <= 1'b0;
resetsel <= 1'b0;
state <= 4'b0001;
end
4'b0001: begin // wait for reference clock
counter <= 8'b00000000;
if(ref_clk_detect == ref_clk_detect_last) begin
state <= 4'b0001;
end else begin
state <= 4'b0010;
end
end
4'b0010: begin // wait for 500ns
// counter will set high bit after 128 cycles
if(counter[7] == 1'b1) begin
state <= 4'b0011;
end
end
4'b0011: begin // start up the PLL
pllpd <= 1'b0;
pllreset <= 1'b0;
plllocken <= 1'b1;
state <= 4'b0100;
end
4'b0100: begin // Waiting for the PLL to lock
if(plllock == 1'b1) begin
state <= 4'b0101;
end
end
4'b0101: begin //- Starting up the GTX
txreset <= 1'b0;
state <= 4'b0110;
counter <= 8'b00000000;
end
4'b0110: begin // wait for 500ns
// counter will set high bit after 128 cycles
if(counter[7] == 1'b1) begin
state <= 4'b0111;
end
end
4'b0111: begin // power up the user data path
txuserrdy <= 1'b1;
if(txresetdone_i == 1'b1) begin
state <= 4'b1000;
end
end
4'b1000: begin // All running
tx_running <= 1'b1;
end
default: begin
state <= 4'b0000;
end
endcase
if(powerup_channel == 1'b0) begin
state <= 4'b0000;
end
ref_clk_detect_last <= ref_clk_detect;
ref_clk_detect <= ref_clk_detect_meta;
ref_clk_detect_meta <= ref_clk_counter[7];
txresetdone_i <= txresetdone_meta;
txresetdone_meta <= txresetdone;
end
endmodule |
module link_signal_mgmt(
input mgmt_clk,
input tx_powerup,
input status_de,
input adjust_de,
input [7:0] addr,
input [7:0] data,
//-----------------------------------------
input [2:0] sink_channel_count,
input [2:0] source_channel_count,
input [2:0] stream_channel_count,
output [2:0] active_channel_count,
//-----------------------------------------
output reg [3:0] powerup_channel,
//-----------------------------------------
output reg clock_locked,
output reg equ_locked,
output reg symbol_locked,
output reg align_locked,
output reg preemp_0p0,
output reg preemp_3p5,
output reg preemp_6p0,
output reg swing_0p4,
output reg swing_0p6,
output reg swing_0p8
);
reg [3:0] power_mask;
wire [1:0] preemp_level;
wire [1:0] voltage_level;
reg [23:0] channel_state;
reg [15:0] channel_adjust;
reg [2:0] active_channel_count_i;
reg [2:0] pipe_channel_count;
assign active_channel_count = active_channel_count_i;
assign voltage_level = channel_adjust[1:0];
assign preemp_level = channel_adjust[3:0];
initial begin
active_channel_count_i = 3'b0;
//-----------------------------------------
powerup_channel = 4'b0;
//-----------------------------------------
clock_locked = 3'b0;
equ_locked = 3'b0;
symbol_locked = 3'b0;
align_locked = 3'b0;
channel_adjust = 15'b0;
channel_state = 24'b0;
preemp_0p0 = 3'b0;
preemp_3p5 = 3'b0;
preemp_6p0 = 3'b0;
swing_0p4 = 3'b0;
swing_0p6 = 3'b0;
swing_0p8 = 3'b0;
end
always @(posedge mgmt_clk) begin
//--------------------------------------------------------
// Work out how many channels will be active
// (the min of source_channel_count and sink_channel_count
//
// Also work out the power-up mask for the transceivers
//---------------------------------------------------------
case(source_channel_count)
3'b100: begin
case(sink_channel_count)
3'b100: pipe_channel_count <= 3'b100;
3'b010: pipe_channel_count <= 3'b010;
default: pipe_channel_count <= 3'b001;
endcase
end
3'b010: begin
case(sink_channel_count)
3'b100: pipe_channel_count <= 3'b010;
3'b010: pipe_channel_count <= 3'b010;
default: pipe_channel_count <= 3'b001;
endcase
end
default: pipe_channel_count <= 3'b001;
endcase
case(stream_channel_count)
3'b100:
case(pipe_channel_count)
3'b100: begin active_channel_count_i <= 3'b100; power_mask <= 4'b1111; end
3'b010: begin active_channel_count_i <= 3'b010; power_mask <= 4'b0000; end
default: begin active_channel_count_i <= 3'b000; power_mask <= 4'b0000; end
endcase
3'b010:
case(pipe_channel_count)
3'b100: begin active_channel_count_i <= 3'b010; power_mask <= 4'b0011; end
3'b010: begin active_channel_count_i <= 3'b010; power_mask <= 4'b0011; end
default: begin active_channel_count_i <= 3'b000; power_mask <= 4'b0000; end
endcase
default: begin
active_channel_count_i <= 3'b001;
power_mask <= 4'b0001;
end
endcase
//-------------------------------------------
// If the powerup is not asserted, then reset
// everything.
//-------------------------------------------
if(tx_powerup == 1'b1) begin
powerup_channel <= power_mask;
end else begin
powerup_channel <= 0;
channel_adjust <= 15'b0;
channel_state <= 24'b0;
end
//-------------------------------------------
// Decode the power and pre-emphasis levels
//-------------------------------------------
case(preemp_level)
2'b00: begin preemp_0p0 <= 1'b1; preemp_3p5 <= 1'b0; preemp_6p0 <= 1'b0; end
2'b01: begin preemp_0p0 <= 1'b0; preemp_3p5 <= 1'b1; preemp_6p0 <= 1'b0; end
default: begin preemp_0p0 <= 1'b0; preemp_3p5 <= 1'b0; preemp_6p0 <= 1'b1; end
endcase
case(voltage_level)
2'b00: begin
swing_0p4 <= 1'b1;
swing_0p6 <= 1'b0;
swing_0p8 <= 1'b0;
end
2'b01: begin
swing_0p4 <= 1'b0;
swing_0p6 <= 1'b1;
swing_0p8 <= 1'b0;
end
default: begin
swing_0p4 <= 1'b0;
swing_0p6 <= 1'b0;
swing_0p8 <= 1'b1;
end
endcase
//---------------------------------------------
// Receive the status data from the AUX channel
//---------------------------------------------
if(status_de == 1'b1) begin
case(addr)
8'b00000010: channel_state[7:0] <= data;
8'b00000011: channel_state[15:8] <= data;
8'b00000100: channel_state[23:16] <= data;
endcase
end
//---------------------------------------------
// Receive the channel adjustment request
//---------------------------------------------
if(adjust_de == 1'b1) begin
case(addr)
8'b00000000: channel_adjust[7:0] <= data;
8'b00000001: channel_adjust[15:8] <= data;
endcase
end
//---------------------------------------------
// Update the status signals based on the
// register data recieved over from the AUX
// channel.
//---------------------------------------------
clock_locked <= 1'b0;
equ_locked <= 1'b0;
symbol_locked <= 1'b0;
case(active_channel_count_i)
3'b001: begin
if((channel_state[3:0] & 4'h1) == 4'h1) clock_locked <= 1'b1;
if((channel_state[3:0] & 4'h3) == 4'h3) equ_locked <= 1'b1;
if((channel_state[3:0] & 4'h7) == 4'h7) symbol_locked <= 1'b1;
end
3'b010: begin
if((channel_state[7:0] & 8'h11) == 8'h11) clock_locked <= 1'b1;
if((channel_state[7:0] & 8'h33) == 8'h33) equ_locked <= 1'b1;
if((channel_state[7:0] & 8'h77) == 8'h77) symbol_locked <= 1'b1;
end
3'b100: begin
if((channel_state[15:0] & 16'h1111) == 16'h1111) clock_locked <= 1'b1;
if((channel_state[15:0] & 16'h3333) == 16'h3333) equ_locked <= 1'b1;
if((channel_state[15:0] & 16'h7777) == 16'h7777) symbol_locked <= 1'b1;
end
endcase
align_locked <= channel_state[16];
end
endmodule |
module dp_register_decode(
input clk,
input de,
input [7:0] data,
input [7:0] addr,
input invalidate,
output reg valid,
output reg [7:0] revision,
output reg link_rate_2_70,
output reg link_rate_1_62,
output reg extended_framing,
output reg [3:0] link_count,
output reg [7:0] max_downspread,
output reg [7:0] coding_supported,
output reg [15:0] port0_capabilities,
output reg [15:0] port1_capabilities,
output reg [7:0] norp
);
initial begin
valid = 1'b0;
revision = 8'b0;
link_rate_2_70 = 1'b0;
link_rate_1_62 = 1'b0;
extended_framing = 1'b0;
link_count = 3'b0;
max_downspread = 8'b0;
coding_supported = 8'b0;
port0_capabilities = 16'b0;
port1_capabilities = 16'b0;
norp = 8'b0;
end
always @(posedge clk) begin
if(de == 1'b1) begin
valid <= 1'b0;
case(addr)
8'h00: begin
revision <= data;
end
8'h01: begin
case(data)
8'h0A: begin
link_rate_2_70 <= 1'b1;
link_rate_1_62 <= 1'b1;
end
8'h06: begin
link_rate_2_70 <= 1'b0;
link_rate_1_62 <= 1'b1;
end
default: begin
link_rate_2_70 <= 1'b0;
link_rate_1_62 <= 1'b0;
end
endcase
end
8'h02: begin
extended_framing <= data[7];
link_count <= data[3:0];
end
8'h03: begin
max_downspread <= data;
end
8'h04: begin
norp <= data;
end
8'h06: begin
coding_supported <= data;
end
8'h08: begin
port0_capabilities[7:0] <= data;
end
8'h09: begin
port0_capabilities[15:8]<= data;
end
8'h0A: begin
port1_capabilities[7:0] <= data;
end
8'h0B: begin
port1_capabilities[15:8]<= data;
valid <= 1'b1;
end
endcase
//----------------------------------------------
// Allow for an external event to invalidate the
// outputs (e.g. hot plug)
//----------------------------------------------
if(invalidate == 1'b1) begin
valid <= 1'b0;
end
end
end
endmodule |
module aux_interface(
input clk,
output [7:0] debug_pmod,
//----------------------------
input aux_in,
output reg aux_out,
output reg aux_tri,
//----------------------------
input tx_wr_en,
input [7:0] tx_data,
output tx_full,
//----------------------------
input rx_rd_en,
output reg [7:0] rx_data,
output rx_empty,
//----------------------------
output busy,
input abort,
output reg timeout
);
//----------------------------------------
// A small fifo to send data from
//----------------------------------------
localparam [2:0] tx_idle = 3'b000;
localparam [2:0] tx_sync = 3'b001;
localparam [2:0] tx_start = 3'b010;
localparam [2:3] tx_send_data = 3'b011;
localparam [2:0] tx_stop = 3'b100;
localparam [2:0] tx_flush = 3'b101;
localparam [2:0] tx_waiting = 3'b110;
reg [2:0] tx_state = tx_idle;
reg [7:0] tx_fifo [31:0];
reg [4:0] tx_rd_ptr;
reg [4:0] tx_wr_ptr;
wire [4:0] tx_wr_ptr_plus_1;
reg [15:0] timeout_count;
wire tx_empty;
wire tx_full_i;
reg [7:0] tx_rd_data;
reg tx_rd_en;
reg snoop;
reg [7:0] bit_counter;
localparam [7:0] bit_counter_max = 8'd49;
reg [15:0] data_sr;
reg [15:0] busy_sr;
localparam [2:0] rx_waiting = 3'b000;
localparam [2:0] rx_receiving_data = 3'b001;
localparam [2:0] rx_done = 3'b010;
reg [2:0] rx_state;
reg [7:0] rx_fifo [31:0];
reg [4:0] rx_wr_ptr;
wire [4:0] rx_wr_ptr_plus_1;
reg [4:0] rx_rd_ptr;
reg rx_reset;
wire rx_empty_i;
wire rx_full;
reg [7:0] rx_wr_data;
reg rx_wr_en;
reg [5:0] rx_count;
reg [15:0] rx_buffer;
reg [15:0] rx_bits;
reg rx_a_bit;
reg rx_last;
reg rx_synced;
reg rx_meta; // TODO: Need to set ASYNCREG attribute
reg rx_finished;
reg [9:0] rx_holdoff;
reg [3:0] debug_pmod_high;
initial begin
aux_out = 1'b0;
aux_tri = 1'b1;
rx_data = 8'b0;
timeout = 1'b0;
tx_state = tx_idle;
tx_rd_ptr = 4'b0000;
tx_wr_ptr = 4'b0000;
timeout_count = 16'b0;
tx_rd_data = 8'b0;
tx_rd_en = 1'b0;
snoop = 1'b0;
bit_counter = 8'b0;
data_sr = 16'b0;
busy_sr = 16'b0;
rx_state = rx_waiting;
rx_wr_ptr = 5'b0;
rx_rd_ptr = 5'b0;
rx_reset = 1'b0;
rx_wr_data = 8'b0;
rx_wr_en = 1'b0;
rx_wr_data = 8'b0;
rx_wr_en = 1'b0;
rx_count = 6'b0;
rx_buffer = 16'b0;
rx_bits = 16'b0;
rx_a_bit = 1'b0;
rx_last = 1'b0;
rx_synced = 1'b0;
rx_meta = 1'b0;
rx_finished = 1'b0;
rx_holdoff = 10'b0;
debug_pmod_high = 4'b0000;
end
assign debug_pmod = {debug_pmod_high, 3'b000, snoop};
//--------------------------------------------
// Async logic for the FIFO state and pointers
//--------------------------------------------
assign rx_wr_ptr_plus_1 = rx_wr_ptr + 5'b00001;
assign tx_wr_ptr_plus_1 = tx_wr_ptr + 5'b00001;
assign rx_empty_i = ((rx_wr_ptr == rx_rd_ptr) ? 1'b1 : 1'b0);
assign rx_full = ((rx_wr_ptr_plus_1 == rx_rd_ptr) ? 1'b1 : 1'b0);
assign tx_empty = ((tx_wr_ptr == tx_rd_ptr) ? 1'b1 : 1'b0);
assign tx_full_i = ((tx_wr_ptr_plus_1 == tx_rd_ptr) ? 1'b1 : 1'b0);
assign rx_empty = rx_empty_i;
assign tx_full = tx_full_i;
assign busy = ((tx_empty == 1'b1 && tx_state == tx_idle) ? 1'b0 : 1'b1);
always @(posedge clk) begin
//--------------------------------
// Defaults, overwritten as needed
//--------------------------------
tx_rd_en <= 1'b0;
rx_reset <= 1'b0;
timeout <= 1'b0;
//---------------------------------
// Is it time to send the next bit?
//---------------------------------
if(bit_counter == bit_counter_max) begin
bit_counter <= 8'h00;
aux_out <= data_sr[15];
aux_tri <= ~busy_sr[15];
data_sr <= { data_sr[14:0], 1'b0 };
busy_sr <= { busy_sr[14:0], 1'b0 };
//-------------------------------------------------
// Logic to signal the RX module ignore the data we
// are actually sending for 10 cycles. This is safe
// as the sync pattern is quite long.
//-----------------------------------------
if(tx_state == tx_waiting) begin
rx_holdoff <= {rx_holdoff[8:0], 1'b0};
end else begin
rx_holdoff <= 10'h3FF;
end
//------------------------------------------------
// Debug signals that are presented to the outside
//------------------------------------------------
case(tx_state)
tx_idle: debug_pmod_high <= 4'h0;
tx_sync: debug_pmod_high <= 4'h1;
tx_start: debug_pmod_high <= 4'h2;
tx_send_data: debug_pmod_high <= 4'h3;
tx_stop: debug_pmod_high <= 4'h4;
tx_flush: debug_pmod_high <= 4'h5;
tx_waiting: debug_pmod_high <= 4'h6;
default: debug_pmod_high <= 4'hA;
endcase
//-----------------------------------
// What to do with with the FSM state
// NOTE THAT HAPPENS WHEN BIT 14 OF BUSY_SR
// IS ZERO, as BIT 15 WILL JUST BE MOVED INTO
// THE OUTPUT REGISTERS.
//-----------------------------------
if(busy_sr[14] == 1'b0) begin
case(tx_state)
tx_idle: begin
if(tx_empty == 1'b0) begin
data_sr <= 16'b0101010101010101;
busy_sr <= 16'b1111111111111111;
tx_state <= tx_sync;
end
end
tx_sync: begin
data_sr <= 16'b0101010101010101;
busy_sr <= 16'b1111111111111111;
tx_state <= tx_start;
end
tx_start: begin
//---------------------------------------------------
// Just send the start pattern.
//
// The TX fifo must have something in it to get here.
//---------------------------------------------------
data_sr <= 16'b1111000000000000;
busy_sr <= 16'b1111111100000000;
tx_state <= tx_send_data;
rx_reset <= 1'b1;
tx_rd_en <= 1'b1;
end
tx_send_data: begin
data_sr <= {tx_rd_data[7], ~tx_rd_data[7], tx_rd_data[6], ~tx_rd_data[6],
tx_rd_data[5], ~tx_rd_data[5], tx_rd_data[4], ~tx_rd_data[4],
tx_rd_data[3], ~tx_rd_data[3], tx_rd_data[2], ~tx_rd_data[2],
tx_rd_data[1], ~tx_rd_data[1], tx_rd_data[0], ~tx_rd_data[0]};
busy_sr <= 16'b1111111111111111;
if(tx_empty == 1'b1) begin
// Send this word, and follow it up with a STOP
tx_state <= tx_stop;
end else begin
// Send this word, and also read the next one from the FIFO
tx_rd_en <= 1'b1;
end
end
tx_stop: begin
//----------------------
// Send the STOP pattern
//----------------------
data_sr <= 16'b1111000000000000;
busy_sr <= 16'b1111111100000000;
tx_state <= tx_flush;
end
tx_flush: begin
//-------------------------------------------
// Just wait here until we are no longer busy
//-------------------------------------------
tx_state <= tx_waiting;
end
endcase
end
end else begin
//----------------------------------
// Not time yet to send the next bit
//----------------------------------
bit_counter <= bit_counter + 1;
end
//---------------------------------------------
// How the RX process indicates that we are now
// free to send another transaction
//---------------------------------------------
if(tx_state == tx_waiting && rx_finished == 1'b1) begin
tx_state <= tx_idle;
end
//-------------------------------------------
// Managing the TX FIFO
// As soon as a word appears in the FIFO it
// is sent. As it takes 8us to send a byte, the
// FIFO can be filled quicker than data is sent,
// ensuring we don't have underrun the TX FIFO
// and send a short message.
//-------------------------------------------
if(tx_full_i == 1'b0 && tx_wr_en == 1'b1) begin
tx_fifo[tx_wr_ptr] <= tx_data;
tx_wr_ptr <= tx_wr_ptr+1;
end
if(tx_empty == 1'b0 && tx_rd_en == 1'b1) begin
tx_rd_data <= tx_fifo[tx_rd_ptr];
tx_rd_ptr <= tx_rd_ptr + 1;
end
//------------------------------------------------
// Managing the RX FIFO
//
// The contents of the FIFO is reset during the TX
// of a new transaction. Pointer updates are
// seperated from the data read / writes to allow
// the reset to work.
//------------------------------------------------
if(rx_full == 1'b0 && rx_wr_en == 1'b1) begin
rx_fifo[rx_wr_ptr] <= rx_wr_data;
end
if(rx_empty_i == 1'b0 && rx_rd_en == 1'b1) begin
rx_data <= rx_fifo[rx_rd_ptr];
end
if(rx_reset == 1'b1) begin
rx_wr_ptr <= rx_rd_ptr;
end else begin
if(rx_full == 1'b0 && rx_wr_en == 1'b1) begin
rx_wr_ptr <= rx_wr_ptr+1;
end
if(rx_empty_i == 1'b0 && rx_rd_en == 1'b1) begin
rx_rd_ptr <= rx_rd_ptr + 1;
end
end
//----------------------------------------
// Manage the timeout. If it is
// waiting for a reply for over 400us) begin
// signal a timeout to the upper FSM.
//----------------------------------------
if(bit_counter == bit_counter_max) begin
if(tx_state == tx_waiting && tx_state == tx_waiting) begin
if(timeout_count == 39999) begin
tx_state <= tx_idle;
timeout <= 1'b1;
end else begin
timeout_count <= timeout_count + 1;
end
end else begin
timeout_count <= 0;
end
end
if(abort == 1'b1) begin
tx_state <= tx_idle;
end
end
always @(posedge clk) begin
rx_wr_en <= 1'b0;
rx_finished <= 1'b0;
//--------------------------------
// Is it time to sample a new half-bit?
//--------------------------------
if(rx_count == 49) begin
rx_a_bit <= 1'b1;
rx_buffer <= { rx_buffer[14:0], rx_synced};
rx_bits <= { rx_bits[14:0], 1'b1};
rx_count <= 5'b00000;
end else begin
rx_count <= rx_count+1;
rx_a_bit <= 1'b0;
end
//--------------------------------------
// Have we just sampled a new half-bit?
//--------------------------------------
if(rx_a_bit == 1'b1) begin
case(rx_state)
rx_waiting: begin
//---------------------------------------------------
// Are we seeing the end of the SYNC/START sequence?
//---------------------------------------------------
if(rx_buffer == 16'b0101010111110000) begin
rx_bits <= 16'h0000;
if(rx_holdoff[9] == 1'b0) begin
//------------------------------------
// Yes, switch to receiving bits, but,
// but only if(the TX modules hasn't
// transmitted for a short while....
//------------------------------------
rx_state <= rx_receiving_data;
end
end
end
rx_receiving_data: begin
//-------------------------------------------------------
// Have we just received the 16th half-bit of the a byte?
//-------------------------------------------------------
if(rx_bits[15] == 1'b1) begin
rx_bits <= 16'h0000;
//----------------------------------------------
// Are we missing transistions that are required
// for valid data bytes?
//
// Or in other words, is this an error or (more
// usually) the STOP pattern?
//-----------------------------------------------
if(rx_buffer[15] == rx_buffer[14] || rx_buffer[13] == rx_buffer[12] ||
rx_buffer[11] == rx_buffer[10] || rx_buffer[9] == rx_buffer[8] ||
rx_buffer[7] == rx_buffer[6] || rx_buffer[5] == rx_buffer[4] ||
rx_buffer[3] == rx_buffer[2] || rx_buffer[1] == rx_buffer[0] ) begin
//--------------------------------------------------------
// Yes, We finished receiving data, or truncate any errors
//--------------------------------------------------------
rx_state <= rx_waiting;
if(rx_holdoff[9] == 1'b0) begin
rx_finished <= 1'b1;
end
end else begin
//-------------------------------------------------
// Looks like a valid byte, so write it to the FIFO
//--------------------------------------------------
rx_wr_data <= { rx_buffer[15], rx_buffer[13], rx_buffer[11], rx_buffer[9],
rx_buffer[7], rx_buffer[5], rx_buffer[3], rx_buffer[1]};
rx_wr_en <= 1'b1;
end
end
end
rx_done: begin
// waiting to be reset (so I ignore noise!)
rx_state <= rx_done;
end
default: begin
rx_state <= rx_waiting;
end
endcase
end
//-----------------------------------------------
// Detect the change on the AUX line, and
// make sure we sample the data mid-way through
// the half-bit (e.g 0.25us, 0.75us, 1.25 us...)
// from when the last transition was seen.
//----------------------------------------------
if(rx_synced != rx_last) begin
rx_count <= 5'b11001;
end
//-----------------------------------------------
// The transmitted resets the RX FSM when it is
// sending a request. This is a counter measure
// against line noise when neigher end is driving
// the link.
//-----------------------------------------------
if(rx_reset == 1'b1) begin
rx_state <= rx_waiting;
end
rx_last <= rx_synced;
//--------------------------
// Synchronise the RX signal
//--------------------------
rx_synced <= rx_meta;
snoop <= rx_meta;
//------------------------------------------------------
// This is done to convert Zs or Xs in simulations to 0s
//------------------------------------------------------
if(aux_in == 1'b1) begin
rx_meta <= 1'b1;
end else begin
rx_meta <= 1'b0;
end
if(abort == 1'b1) begin
rx_state <= rx_waiting;
end
end
endmodule |
module edid_decode(
input clk,
input edid_de,
input [7:0] edid_data,
input [7:0] edid_addr,
input invalidate,
output reg valid,
output reg support_RGB444,
output reg support_YCC444,
output reg support_YCC422,
output reg [15:0] pixel_clock_x10k,
output reg [11:0] h_visible_len,
output reg [11:0] h_blank_len,
output reg [11:0] h_front_len,
output reg [11:0] h_sync_len,
output reg [11:0] v_visible_len,
output reg [11:0] v_blank_len,
output reg [11:0] v_front_len,
output reg [11:0] v_sync_len,
output reg interlaced
);
reg [7:0] checksum;
wire [7:0] checksum_next;
assign checksum_next = checksum + edid_data;
initial begin
checksum = 8'b0;
valid = 1'b0;
support_RGB444 = 1'b0;
support_YCC444 = 1'b0;
support_YCC422 = 1'b0;
pixel_clock_x10k = 16'b0;
h_visible_len = 12'b0;
h_blank_len = 12'b0;
h_front_len = 12'b0;
h_sync_len = 12'b0;
v_visible_len = 12'b0;
v_blank_len = 12'b0;
v_front_len = 12'b0;
v_sync_len = 12'b0;
interlaced = 1'b0;
end
always @(posedge clk) begin
if(edid_de == 1'b1) begin
checksum <= checksum_next;
valid <= 1'b0;
case(edid_addr)
8'h00: begin // reset the checksum
checksum <= edid_data;
end
8'h18: begin // Colour modes supported
support_RGB444 <= 1'b1;
support_YCC444 <= edid_data[3];
support_YCC422 <= edid_data[4];
end
// Timing 0 - 1
8'h36: begin
pixel_clock_x10k[7:0] <= edid_data;
end
8'h37: begin
pixel_clock_x10k[15:8] <= edid_data;
end
// Timing 2 - 4
8'h38: begin
h_visible_len[7:0] <= edid_data;
end
8'h39: begin
h_blank_len[7:0] <= edid_data;
end
8'h3a: begin
h_visible_len[11:8] <= edid_data[7:4];
h_blank_len[11:8] <= edid_data[3:0];
end
// Timing 5 - 7
8'h3B: begin
v_visible_len[7:0] <= edid_data;
end
8'h3C: begin
v_blank_len[7:0] <= edid_data;
end
8'h3D: begin
v_visible_len[11:8] <= edid_data[7:4];
v_blank_len[11:8] <= edid_data[3:0];
end
// Timing 8 - 11
8'h3E: begin
h_front_len[ 7:0] <= edid_data;
end
8'h3F: begin
h_sync_len[ 7:0] <= edid_data;
end
8'h40: begin
v_front_len[ 3:0] <= edid_data[7:4];
v_sync_len[ 3:0] <= edid_data[3:0];
end
8'h41: begin
h_front_len[ 9:8] <= edid_data[7:6];
h_sync_len[ 9:8] <= edid_data[5:4];
v_front_len[ 5:4] <= edid_data[3:2];
v_sync_len[ 5:4] <= edid_data[1:0];
end
// Timing 11-16 not used - that is the physical
// size and boarder.
8'h7F: begin
if(checksum_next == 8'h00) begin
valid <= 1'b1;
end
end
endcase
//----------------------------------------------
// Allow for an external event to invalidate the
// outputs (e.g. hot plug)
//----------------------------------------------
if(invalidate == 1'b1) begin
valid <= 1'b0;
end
end
end
endmodule |
module hotplug_decode(
input clk,
input hpd,
output reg irq,
output reg present
);
reg hpd_meta1; // TODO Should also set ASYNC_REG
reg hpd_meta2; // TODO Should also set ASYNC_REG
reg hpd_synced;
reg hpd_last;
reg [17:0] pulse_count;
initial begin
hpd_meta1 = 1'b0;
hpd_meta2 = 1'b0;
hpd_synced = 1'b0;
hpd_last = 1'b1;
pulse_count = 18'b0;
present = 1'b0;
irq = 1'b0;
end
always @(posedge clk) begin
irq <= 1'b0;
if(hpd_last == 1'b0) begin
if(hpd_synced == 1'b0) begin
if(pulse_count == 200000) begin // TODO - should not be a constant!
//--------------------------------
// Sink has gone away for over 2ms
// No longer present
//--------------------------------
present <= 1'b0;
end else begin
pulse_count <= pulse_count + 1;
end
end else begin
//----------------------------------------
// Timing the pulse to see if it is an IRQ
//----------------------------------------
if(pulse_count > 100000) begin // TODO - should not be a constant!
//-----------------------------------
// Signal is back, but less than 2ms
// so signal an IRQ...
//-----------------------------------
if(present == 1'b1) begin
irq <= present;
end
end
pulse_count = 18'b0;
end
end else begin
if(hpd_synced == 1'b0) begin
pulse_count = 18'b0; // Flip to other state
end else begin
if(pulse_count == 220000) begin
present <= 1'b1; // Pulse seen long enough to be valid
end else begin
pulse_count <= pulse_count + 1; // Time till the signal is valid for > 2ms
end
end
end
hpd_last <= hpd_synced;
hpd_synced <= hpd_meta1;
hpd_meta1 <= hpd_meta2;
hpd_meta2 <= hpd;
end
endmodule |
module channel_management(
input clk100,
output [7:0] debug,
input hpd,
input auxch_in,
output auxch_out,
output auxch_tri,
// Datapath requirements
input [2:0] stream_channel_count,
input [2:0] source_channel_count,
// Datapath control
output tx_clock_train,
output tx_align_train,
// Transceiver management
output [3:0] tx_powerup_channel,
output tx_preemp_0p0,
output tx_preemp_3p5,
output tx_preemp_6p0,
output tx_swing_0p4,
output tx_swing_0p6,
output tx_swing_0p8,
input [3:0] tx_running,
output tx_link_established
);
wire edid_de;
wire dp_reg_de;
wire adjust_de;
wire status_de;
wire [7:0] aux_data;
wire [7:0] aux_addr;
wire invalidate;
wire tx_powerup;
wire preemp_0p0_i;
wire preemp_3p5_i;
wire preemp_6p0_i;
wire swing_0p4_i;
wire swing_0p6_i;
wire swing_0p8_i;
wire support_RGB444;
wire support_YCC444;
wire support_YCC422;
//------------------------------------------
// EDID data
//-------------------------------------------
wire edid_valid;
wire [15:0] pixel_clock_x10k;
wire [11:0] h_visible_len;
wire [11:0] h_blank_len;
wire [11:0] h_front_len;
wire [11:0] h_sync_len;
wire [11:0] v_visible_len;
wire [11:0] v_blank_len;
wire [11:0] v_front_len;
wire [11:0] v_sync_len;
wire interlaced;
//------------------------------------------
// Display port data
//-------------------------------------------
wire dp_valid;
wire [7:0] dp_revision;
wire dp_link_rate_2_70;
wire dp_link_rate_1_62;
wire dp_extended_framing;
wire [3:0] dp_link_count;
wire [7:0] dp_max_downspread;
wire [7:0] dp_coding_supported;
wire [15:0] dp_port0_capabilities;
wire [15:0] dp_port1_capabilities;
wire [7:0] dp_norp;
//------------------------------------------------------------------------
wire clock_locked;
wire equ_locked;
wire symbol_locked;
wire align_locked;
//----------------------------------------------
wire [7:0] interface_debug;
wire [7:0] mgmt_debug;
wire [2:0] sink_channel_count;
wire [2:0] active_channel_count;
wire hpd_irq;
wire hpd_present;
// Feed the number of links from the registers into the link management logic
assign sink_channel_count = dp_link_count[2:0];
assign tx_preemp_0p0 = preemp_0p0_i;
assign tx_preemp_3p5 = preemp_3p5_i;
assign tx_preemp_6p0 = preemp_6p0_i;
assign tx_swing_0p4 = swing_0p4_i;
assign tx_swing_0p6 = swing_0p6_i;
assign tx_swing_0p8 = swing_0p8_i;
hotplug_decode i_hotplug_decode(
.clk (clk100),
.hpd (hpd),
.irq (hpd_irq),
.present (hpd_present)
);
aux_channel i_aux_channel(
.clk (clk100),
.debug_pmod (debug),
//------------------------------
.edid_de (edid_de),
.dp_reg_de (dp_reg_de),
.adjust_de (adjust_de),
.status_de (status_de),
.aux_addr (aux_addr),
.aux_data (aux_data),
//----------------------------
.link_count (active_channel_count),
.hpd_irq (hpd_irq),
.hpd_present (hpd_present),
//------------------------------
.preemp_0p0 (preemp_0p0_i),
.preemp_3p5 (preemp_3p5_i),
.preemp_6p0 (preemp_6p0_i),
.swing_0p4 (swing_0p4_i),
.swing_0p6 (swing_0p6_i),
.swing_0p8 (swing_0p8_i),
.clock_locked (clock_locked),
.equ_locked (equ_locked),
.symbol_locked (symbol_locked),
.align_locked (align_locked),
//----------------------------
.tx_powerup (tx_powerup),
.tx_clock_train (tx_clock_train),
.tx_align_train (tx_align_train),
.tx_link_established (tx_link_established),
//----------------------------
.dp_tx_hp_detect (hpd),
.aux_in (auxch_in),
.aux_out (auxch_out),
.aux_tri (auxch_tri)
);
edid_decode i_edid_decode(
.clk (clk100),
.edid_de (edid_de),
.edid_addr (aux_addr),
.edid_data (aux_data),
.invalidate (1'b0),
.valid (edid_valid),
.support_RGB444 (support_RGB444),
.support_YCC444 (support_YCC444),
.support_YCC422 (support_YCC422),
.pixel_clock_x10k (pixel_clock_x10k),
.h_visible_len (h_visible_len),
.h_blank_len (h_blank_len),
.h_front_len (h_front_len),
.h_sync_len (h_sync_len),
.v_visible_len (v_visible_len),
.v_blank_len (v_blank_len),
.v_front_len (v_front_len),
.v_sync_len (v_sync_len),
.interlaced (interlaced));
dp_register_decode i_dp_reg_decode(
.clk (clk100),
.de (dp_reg_de),
.addr (aux_addr),
.data (aux_data),
.invalidate (1'b0),
.valid (dp_valid),
.revision (dp_revision),
.link_rate_2_70 (dp_link_rate_2_70),
.link_rate_1_62 (dp_link_rate_1_62),
.extended_framing (dp_extended_framing),
.link_count (dp_link_count),
.max_downspread (dp_max_downspread),
.coding_supported (dp_coding_supported),
.port0_capabilities (dp_port0_capabilities),
.port1_capabilities (dp_port1_capabilities),
.norp (dp_norp)
);
link_signal_mgmt i_link_signal_mgmt(
.mgmt_clk (clk100),
.tx_powerup (tx_powerup),
.status_de (status_de),
.adjust_de (adjust_de),
.addr (aux_addr),
.data (aux_data),
.sink_channel_count (sink_channel_count),
.source_channel_count (source_channel_count),
.active_channel_count (active_channel_count),
.stream_channel_count (stream_channel_count),
.powerup_channel (tx_powerup_channel),
.clock_locked (clock_locked),
.equ_locked (equ_locked),
.symbol_locked (symbol_locked),
.align_locked (align_locked),
.preemp_0p0 (preemp_0p0_i),
.preemp_3p5 (preemp_3p5_i),
.preemp_6p0 (preemp_6p0_i),
.swing_0p4 (swing_0p4_i),
.swing_0p6 (swing_0p6_i),
.swing_0p8 (swing_0p8_i)
);
endmodule |
module dp_aux_messages(
input clk,
// Interface to send messages
input msg_de,
input [7:0] msg,
output reg busy,
// Interface to the AUX Channel
output reg aux_tx_wr_en,
output reg [7:0] aux_tx_data
);
reg [11:0] counter;
initial begin
counter = 12'b0;
busy = 1'b0;
aux_tx_wr_en = 1'b0;
aux_tx_data = 8'b0;
end
always @(posedge clk) begin
case(counter)
// Write to I2C device at x50 (EDID)
12'h010: begin aux_tx_data <= 8'h40; aux_tx_wr_en <= 1'b1; end
12'h011: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h012: begin aux_tx_data <= 8'h50; aux_tx_wr_en <= 1'b1; end
12'h013: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h014: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
// Read a block of EDID data
12'h020: begin aux_tx_data <= 8'h50; aux_tx_wr_en <= 1'b1; end
12'h021: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h022: begin aux_tx_data <= 8'h50; aux_tx_wr_en <= 1'b1; end
12'h023: begin aux_tx_data <= 8'h0F; aux_tx_wr_en <= 1'b1; end
// Read Sink count
12'h030: begin aux_tx_data <= 8'h90; aux_tx_wr_en <= 1'b1; end
12'h031: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h032: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h033: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
// Read DP configuration registers (12 of them)
12'h040: begin aux_tx_data <= 8'h90; aux_tx_wr_en <= 1'b1; end
12'h041: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h042: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h043: begin aux_tx_data <= 8'h0B; aux_tx_wr_en <= 1'b1; end
// Write DPCD powerstate D3
12'h050: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h051: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
12'h052: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h053: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h054: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
// Set channel coding (8b/10b)
12'h060: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h061: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h062: begin aux_tx_data <= 8'h08; aux_tx_wr_en <= 1'b1; end
12'h063: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h064: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
// Set link bandwidth 2.70 Gb/s
12'h070: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h071: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h072: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h073: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h074: begin aux_tx_data <= 8'h0A; aux_tx_wr_en <= 1'b1; end
// Write Link Downspread
12'h080: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h081: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h082: begin aux_tx_data <= 8'h07; aux_tx_wr_en <= 1'b1; end
12'h083: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h084: begin aux_tx_data <= 8'h10; aux_tx_wr_en <= 1'b1; end
// Set link count 1
12'h090: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h091: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h092: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h093: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h094: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end // Standard framing, one channel
// Set link count 2
12'h0A0: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h0A1: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0A2: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0A3: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h0A4: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
// Set link count 4
12'h0B0: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h0B1: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0B2: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0B3: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h0B4: begin aux_tx_data <= 8'h04; aux_tx_wr_en <= 1'b1; end
// Set training pattern 1
12'h0C0: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h0C1: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0C2: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h0C3: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h0C4: begin aux_tx_data <= 8'h21; aux_tx_wr_en <= 1'b1; end
// Read link status for all four lanes
12'h0D0: begin aux_tx_data <= 8'h90; aux_tx_wr_en <= 1'b1; end
12'h0D1: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h0D2: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h0D3: begin aux_tx_data <= 8'h07; aux_tx_wr_en <= 1'b1; end
// Read the Adjust_Request registers
12'h0E0: begin aux_tx_data <= 8'h90; aux_tx_wr_en <= 1'b1; end
12'h0E1: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h0E2: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
12'h0E3: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
// Set training pattern 2
12'h0F0: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h0F1: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h0F2: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h0F3: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h0F4: begin aux_tx_data <= 8'h22; aux_tx_wr_en <= 1'b1; end
// Resd lane align status for all four lanes
12'h100: begin aux_tx_data <= 8'h90; aux_tx_wr_en <= 1'b1; end
12'h101: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h102: begin aux_tx_data <= 8'h04; aux_tx_wr_en <= 1'b1; end
12'h103: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
// Turn off training patterns / Switch to normal
12'h110: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h111: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h112: begin aux_tx_data <= 8'h02; aux_tx_wr_en <= 1'b1; end
12'h113: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h114: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end // Scrambler enabled
// Set Premp level 0, votage 0.4V
12'h140: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h141: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h142: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h143: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h144: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h145: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h146: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
12'h147: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b1; end
// Set Premp level 0, votage 0.6V
12'h160: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h161: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h162: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h163: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h164: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h165: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h166: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h167: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
// Set Premp level 0, votage 0.8V -- Max voltage
12'h180: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h181: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h182: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h183: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h184: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
12'h185: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
12'h186: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
12'h187: begin aux_tx_data <= 8'h06; aux_tx_wr_en <= 1'b1; end
// Set Premp level 1, votage 0.4V
12'h240: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h241: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h242: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h243: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h244: begin aux_tx_data <= 8'h10; aux_tx_wr_en <= 1'b1; end
12'h245: begin aux_tx_data <= 8'h10; aux_tx_wr_en <= 1'b1; end
12'h246: begin aux_tx_data <= 8'h10; aux_tx_wr_en <= 1'b1; end
12'h247: begin aux_tx_data <= 8'h10; aux_tx_wr_en <= 1'b1; end
// Set Premp level 1, votage 0.6V
12'h260: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h261: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h262: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h263: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h264: begin aux_tx_data <= 8'h11; aux_tx_wr_en <= 1'b1; end
12'h265: begin aux_tx_data <= 8'h11; aux_tx_wr_en <= 1'b1; end
12'h266: begin aux_tx_data <= 8'h11; aux_tx_wr_en <= 1'b1; end
12'h267: begin aux_tx_data <= 8'h11; aux_tx_wr_en <= 1'b1; end
// Set Premp level 1, votage 0.8V -- Max voltage
12'h280: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h281: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h282: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h283: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h284: begin aux_tx_data <= 8'h16; aux_tx_wr_en <= 1'b1; end
12'h285: begin aux_tx_data <= 8'h16; aux_tx_wr_en <= 1'b1; end
12'h286: begin aux_tx_data <= 8'h16; aux_tx_wr_en <= 1'b1; end
12'h287: begin aux_tx_data <= 8'h16; aux_tx_wr_en <= 1'b1; end
// Set Premp level 2, votage 0.4V -- Max pre-emphasis
12'h340: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h341: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h342: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h343: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h344: begin aux_tx_data <= 8'h60; aux_tx_wr_en <= 1'b1; end
12'h345: begin aux_tx_data <= 8'h60; aux_tx_wr_en <= 1'b1; end
12'h346: begin aux_tx_data <= 8'h60; aux_tx_wr_en <= 1'b1; end
12'h347: begin aux_tx_data <= 8'h60; aux_tx_wr_en <= 1'b1; end
// Set Premp level 2, votage 0.6V
12'h360: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h361: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h362: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h363: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h364: begin aux_tx_data <= 8'h61; aux_tx_wr_en <= 1'b1; end
12'h365: begin aux_tx_data <= 8'h61; aux_tx_wr_en <= 1'b1; end
12'h366: begin aux_tx_data <= 8'h61; aux_tx_wr_en <= 1'b1; end
12'h367: begin aux_tx_data <= 8'h61; aux_tx_wr_en <= 1'b1; end
// Set Premp level 2, votage 0.8V -- Max voltage -- Max pre-emphasis
// this condition should not be reached for the standard do not allow this pair
12'h380: begin aux_tx_data <= 8'h80; aux_tx_wr_en <= 1'b1; end
12'h381: begin aux_tx_data <= 8'h01; aux_tx_wr_en <= 1'b1; end
12'h382: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h383: begin aux_tx_data <= 8'h03; aux_tx_wr_en <= 1'b1; end
12'h384: begin aux_tx_data <= 8'h66; aux_tx_wr_en <= 1'b1; end
12'h385: begin aux_tx_data <= 8'h66; aux_tx_wr_en <= 1'b1; end
12'h386: begin aux_tx_data <= 8'h66; aux_tx_wr_en <= 1'b1; end
12'h387: begin aux_tx_data <= 8'h66; aux_tx_wr_en <= 1'b1; end
default: begin aux_tx_data <= 8'h00; aux_tx_wr_en <= 1'b0; end
endcase
//--------------------------
// Move on to the next word?
//--------------------------
if(counter[3:0] == 4'hF) begin
busy <= 1'b0;
end else begin
counter <= counter+1;
end
//--------------------------------------
// Are we being asked to send a message?
//
// But only do it of we are not already
// sending something!
//--------------------------------------
if(msg_de == 1'b1 && counter[3:0] == 4'hF) begin
counter <= {msg, 4'b0000};
busy <= 1'b1;
end
end
endmodule |
module aux_channel(
input clk,
output [7:0] debug_pmod,
//------------------------------
output reg edid_de,
output reg dp_reg_de,
output reg adjust_de,
output reg status_de,
output reg [7:0] aux_addr,
output reg [7:0] aux_data,
//------------------------------
input [2:0] link_count,
//----------------------------
input hpd_irq,
input hpd_present,
//------------------------------
output reg tx_powerup,
output reg tx_clock_train,
output reg tx_align_train,
output reg tx_link_established,
//-------------------------------
input swing_0p4,
input swing_0p6,
input swing_0p8,
input preemp_0p0,
input preemp_3p5,
input preemp_6p0,
input clock_locked,
input equ_locked,
input symbol_locked,
input align_locked,
//------------------------------
input dp_tx_hp_detect,
input aux_in,
output aux_out,
output aux_tri
);
localparam [7:0] error = 8'h00, reset = 8'h01, check_presence = 8'h02;
// Gathering Display information
localparam [7:0] edid_block0 = 8'h03, edid_block1 = 8'h04, edid_block2 = 8'h05, edid_block3 = 8'h06;
localparam [7:0] edid_block4 = 8'h08, edid_block5 = 8'h09, edid_block6 = 8'h0A, edid_block7 = 8'h0B;
// Gathering display Port information
localparam [7:0] read_sink_count = 8'h0C, read_registers = 8'h0D;
// Link configuration states
localparam [7:0] set_channel_coding = 8'h0E, set_speed_270 = 8'h0F, set_downspread = 8'h10;
localparam [7:0] set_link_count_1 = 8'h11, set_link_count_2 = 8'h12, set_link_count_4 = 8'h13;
// Link training - clock recovery
localparam [7:0] clock_training = 8'h14, clock_voltage_0p4 = 8'h15, clock_voltage_0p6 = 8'h16, clock_voltage_0p8 = 8'h17;
localparam [7:0] clock_wait = 8'h18, clock_test = 8'h19, clock_adjust = 8'h1A, clock_wait_after = 8'h1B;
// Link training - alignment and preemphasis
localparam [7:0] align_training = 8'h1C;
localparam [7:0] align_p0_V0p4 = 8'h1D, align_p0_V0p6 = 8'h1E, align_p0_V0p8 = 8'h1F;
localparam [7:0] align_p1_V0p4 = 8'h20, align_p1_V0p6 = 8'h21, align_p1_V0p8 = 8'h22;
localparam [7:0] align_p2_V0p4 = 8'h23, align_p2_V0p6 = 8'h24, align_p2_V0p8 = 8'h25;
localparam [7:0] align_wait0 = 8'h26, align_wait1 = 8'h27, align_wait2 = 8'h28, align_wait3 = 8'h29;
localparam [7:0] align_test = 8'h2A, align_adjust = 8'h2B, align_wait_after = 8'h2C;
// Link up.
localparam [7:0] switch_to_normal = 8'h2D, link_established = 8'h2E;
// Checking the state of the link
localparam [7:0] check_link = 8'h2F, check_wait = 8'h30;
reg [7:0] state = error;
reg [7:0] next_state = error;
reg [7:0] state_on_success = error;
reg retry_now;
reg [26:0] retry_count;
reg link_check_now;
reg [26:0] link_check_count;
reg [14:0] count_100us;
reg adjust_de_active;
reg dp_reg_de_active;
reg edid_de_active;
reg status_de_active;
reg msg_de;
reg [7:0] msg;
wire msg_busy;
wire aux_tx_wr_en;
wire [7:0] aux_tx_data;
wire aux_tx_full;
wire aux_rx_rd_en;
wire [7:0] aux_rx_data;
wire aux_rx_empty;
reg [7:0] link_count_sink;
wire channel_busy;
wire channel_timeout;
reg [7:0] expected;
reg [7:0] rx_byte_count;
reg [7:0] aux_addr_i;
reg reset_addr_on_change;
reg just_read_from_rx;
reg [3:0] powerup_mask;
initial begin
state = error;
next_state = error;
state_on_success = error;
retry_now = 1'b0;
retry_count = 27'h0200;
link_check_now = 1'b0;
link_check_count = 27'h0200;
count_100us = 15'd1000;
adjust_de_active = 1'b0;
dp_reg_de_active = 1'b0;
edid_de_active = 1'b0;
status_de_active = 1'b0;
msg_de = 1'b0;
msg = 8'b0;
link_count_sink = 8'b0;
expected = 8'b0;
rx_byte_count = 8'b0;
aux_addr_i = 8'b0;
reset_addr_on_change = 1'b0;
just_read_from_rx = 1'b0;
powerup_mask = 4'b0;
edid_de = 1'b0;
dp_reg_de = 1'b0;
adjust_de = 1'b0;
status_de = 1'b0;
aux_addr = 8'b0;
aux_data = 8'b0;
tx_powerup = 1'b0;
tx_clock_train = 1'b0;
tx_align_train = 1'b0;
tx_link_established = 1'b0;
end
dp_aux_messages i_aux_messages(
.clk (clk),
// Interface to send messages
.msg_de (msg_de),
.msg (msg),
.busy (msg_busy),
// Interface to the AUX Channel
.aux_tx_wr_en (aux_tx_wr_en),
.aux_tx_data (aux_tx_data)
);
aux_interface i_aux_interface(
.clk (clk),
.debug_pmod (debug_pmod),
//---------------------------
.aux_in (aux_in),
.aux_out (aux_out),
.aux_tri (aux_tri),
//----------------------------
.tx_wr_en (aux_tx_wr_en),
.tx_data (aux_tx_data),
.tx_full (aux_tx_full),
//------------------------------
.rx_rd_en (aux_rx_rd_en),
.rx_data (aux_rx_data),
.rx_empty (aux_rx_empty),
//------------------------------
.busy (channel_busy),
.abort (1'b0),
.timeout (channel_timeout)
);
assign aux_rx_rd_en = (!channel_busy) & (!aux_rx_empty); // CHECK THIS!
always @(posedge clk) begin
//-----------------------------------------
// Are we going to change state this cycle?
//-----------------------------------------
msg_de <= 1'b0;
if(next_state != state) begin
//-----------------------------------------------------------
// Get ready to count how many reply bytes have been received
//-----------------------------------------------------------
rx_byte_count <= 0;
//-------------------------------------------------
// Controlling which FSM state to go to on success
//-------------------------------------------------
case(next_state)
reset: state_on_success <= check_presence;
check_presence: state_on_success <= edid_block0;
edid_block0: state_on_success <= edid_block1;
edid_block1: state_on_success <= edid_block2;
edid_block2: state_on_success <= edid_block3;
edid_block3: state_on_success <= edid_block4;
edid_block4: state_on_success <= edid_block5;
edid_block5: state_on_success <= edid_block6;
edid_block6: state_on_success <= edid_block7;
edid_block7: state_on_success <= read_sink_count;
read_sink_count: state_on_success <= read_registers;
read_registers: state_on_success <= set_channel_coding;
set_channel_coding: state_on_success <= set_speed_270;
set_speed_270: state_on_success <= set_downspread;
set_downspread: case(link_count)
3'b001: state_on_success <= set_link_count_1;
3'b010: state_on_success <= set_link_count_2;
3'b100: state_on_success <= set_link_count_4;
default: state_on_success <= error;
endcase
set_link_count_1: state_on_success <= clock_training;
set_link_count_2: state_on_success <= clock_training;
set_link_count_4: state_on_success <= clock_training;
//----- Display Port clock training -------------------
clock_training: state_on_success <= clock_voltage_0p4;
clock_voltage_0p4: state_on_success <= clock_wait;
clock_voltage_0p6: state_on_success <= clock_wait;
clock_voltage_0p8: state_on_success <= clock_wait;
clock_wait: state_on_success <= clock_test;
clock_test: state_on_success <= clock_adjust;
clock_adjust: state_on_success <= clock_wait_after;
clock_wait_after: if(clock_locked == 1'b1) begin
state_on_success <= align_training;
end else if(swing_0p8 == 1'b1) begin
state_on_success <= clock_voltage_0p8;
end else if(swing_0p6 == 1'b1) begin
state_on_success <= clock_voltage_0p6;
end else begin
state_on_success <= clock_voltage_0p4;
end
//----- Display Port Alignment traning ------------
align_training: if(swing_0p8 == 1'b1) begin
state_on_success <= align_p0_V0p8;
end else if(swing_0p6 == 1'b1) begin
state_on_success <= align_p0_V0p6;
end else begin
state_on_success <= align_p0_V0p4;
end
align_p0_V0p4: state_on_success <= align_wait0;
align_p0_V0p6: state_on_success <= align_wait0;
align_p0_V0p8: state_on_success <= align_wait0;
align_p1_V0p4: state_on_success <= align_wait0;
align_p1_V0p6: state_on_success <= align_wait0;
align_p1_V0p8: state_on_success <= align_wait0;
align_p2_V0p4: state_on_success <= align_wait0;
align_p2_V0p6: state_on_success <= align_wait0;
align_p2_V0p8: state_on_success <= align_wait0;
align_wait0: state_on_success <= align_wait1;
align_wait1: state_on_success <= align_wait2;
align_wait2: state_on_success <= align_wait3;
align_wait3: state_on_success <= align_test;
align_test: state_on_success <= align_adjust;
align_adjust: state_on_success <= align_wait_after;
align_wait_after: if(symbol_locked == 1'b1) begin
state_on_success <= switch_to_normal;
end else if(swing_0p8 == 1'b1) begin
if(preemp_6p0 == 1'b1) begin
state_on_success <= align_p2_V0p8;
end else if(preemp_3p5 == 1'b1) begin
state_on_success <= align_p1_V0p8;
end else begin
state_on_success <= align_p0_V0p8;
end
end else if(swing_0p6 == 1'b1) begin
if(preemp_6p0 == 1'b1) begin
state_on_success <= align_p2_V0p6;
end else if(preemp_3p5 == 1'b1) begin
state_on_success <= align_p1_V0p6;
end else begin
state_on_success <= align_p0_V0p6;
end
end else begin
if(preemp_6p0 == 1'b1) begin
state_on_success <= align_p2_V0p4;
end else if(preemp_3p5 == 1'b1) begin
state_on_success <= align_p1_V0p4;
end else begin
state_on_success <= align_p0_V0p4;
end
end
switch_to_normal: state_on_success <= link_established;
link_established: state_on_success <= link_established;
check_link: state_on_success <= check_wait;
check_wait: if(clock_locked == 1'b1 && equ_locked == 1'b1 && symbol_locked == 1'b1 && align_locked == 1'b1) begin
state_on_success <= link_established;
end else begin
state_on_success <= error;
end
error: state_on_success <= error;
endcase
//----------------------------------------------------------
// Controlling what message will be sent, how many words are
// expected back, and where it will be routed
//
// NOTE: If you set 'expected' incorrectly then bytes will
// get left in the RX FIFO, potentially corrupting things
//----------------------------------------------------------
msg_de <= 1'b1;
status_de_active <= 1'b0;
adjust_de_active <= 1'b0;
dp_reg_de_active <= 1'b0;
edid_de_active <= 1'b0;
reset_addr_on_change <= 1'b0;
case(next_state)
reset: begin msg <= 8'h00; expected <= 8'h00; end
check_presence: begin msg <= 8'h01; expected <= 8'h01; reset_addr_on_change <= 1'b1; end
edid_block0: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block1: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block2: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block3: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block4: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block5: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block6: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
edid_block7: begin msg <= 8'h02; expected <= 8'h11; edid_de_active <= 1'b1; end
read_sink_count: begin msg <= 8'h03; expected <= 8'h02; reset_addr_on_change <= 1'b1; end
read_registers: begin msg <= 8'h04; expected <= 8'h0D; dp_reg_de_active <= 1'b1; end
set_channel_coding: begin msg <= 8'h06; expected <= 8'h01; end
set_speed_270: begin msg <= 8'h07; expected <= 8'h01; end
set_downspread: begin msg <= 8'h08; expected <= 8'h01; end
set_link_count_1: begin msg <= 8'h09; expected <= 8'h01; end
set_link_count_2: begin msg <= 8'h0A; expected <= 8'h01; end
set_link_count_4: begin msg <= 8'h0B; expected <= 8'h01; end
clock_training: begin msg <= 8'h0C; expected <= 8'h01; end
clock_voltage_0p4: begin msg <= 8'h14; expected <= 8'h01; end
clock_voltage_0p6: begin msg <= 8'h16; expected <= 8'h01; end
clock_voltage_0p8: begin msg <= 8'h18; expected <= 8'h01; end
clock_wait: begin msg <= 8'h00; expected <= 8'h00; reset_addr_on_change <= 1'b1; end
clock_test: begin msg <= 8'h0D; expected <= 8'h09; status_de_active <= 1'b1; reset_addr_on_change <= 1'b1; end
clock_adjust: begin msg <= 8'h0E; expected <= 8'h03; adjust_de_active <= 1'b1; end
clock_wait_after: begin msg <= 8'h00; expected <= 8'h00; end
align_training: begin msg <= 8'h0F; expected <= 8'h01; end
align_p0_V0p4: begin msg <= 8'h14; expected <= 8'h01; end
align_p0_V0p6: begin msg <= 8'h16; expected <= 8'h01; end
align_p0_V0p8: begin msg <= 8'h18; expected <= 8'h01; end
align_p1_V0p4: begin msg <= 8'h24; expected <= 8'h01; end
align_p1_V0p6: begin msg <= 8'h26; expected <= 8'h01; end
align_p1_V0p8: begin msg <= 8'h28; expected <= 8'h01; end
align_p2_V0p4: begin msg <= 8'h34; expected <= 8'h01; end
align_p2_V0p6: begin msg <= 8'h36; expected <= 8'h01; end
align_p2_V0p8: begin msg <= 8'h38; expected <= 8'h01; end
align_wait0: begin msg <= 8'h00; expected <= 8'h00; end
align_wait1: begin msg <= 8'h00; expected <= 8'h00; end
align_wait2: begin msg <= 8'h00; expected <= 8'h00; end
align_wait3: begin msg <= 8'h00; expected <= 8'h00; reset_addr_on_change <= 1'b1; end
align_test: begin msg <= 8'h0D; expected <= 8'h09; status_de_active <= 1'b1; reset_addr_on_change <= 1'b1; end
align_adjust: begin msg <= 8'h0E; expected <= 8'h03; adjust_de_active <= 1'b1; end
align_wait_after: begin msg <= 8'h00; expected <= 8'h00; end
switch_to_normal: begin msg <= 8'h11; expected <= 8'h01; end
link_established: begin msg <= 8'h00; expected <= 8'h00; reset_addr_on_change <= 1'b1; end
check_link: begin msg <= 8'h0D; expected <= 8'h09; status_de_active <= 1'b1; end
check_wait: begin msg <= 8'h00; expected <= 8'h00; end
error: begin msg <= 8'h00; end
default: begin msg <= 8'h00; end
endcase
//------------------------------------------------------
// Set the control signals the state for the link state,
// transceivers andmain channel pipeline
//------------------------------------------------------
tx_powerup <= 1'b0;
tx_clock_train <= 1'b0;
tx_align_train <= 1'b0;
tx_link_established <= 1'b0;
case(next_state)
clock_training: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_voltage_0p4: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_voltage_0p6: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_voltage_0p8: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_wait: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_test: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_adjust: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
clock_wait_after: begin tx_powerup <= 1'b1; tx_clock_train <= 1'b1; end
align_training: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p0_V0p4: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p0_V0p6: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p0_V0p8: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p1_V0p4: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p1_V0p6: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p1_V0p8: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p2_V0p4: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p2_V0p6: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_p2_V0p8: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_wait0: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_wait1: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_wait2: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_wait3: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_test: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_adjust: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
align_wait_after: begin tx_powerup <= 1'b1; tx_align_train <= 1'b1; end
switch_to_normal: begin tx_powerup <= 1'b1; end
link_established: begin tx_powerup <= 1'b1; tx_link_established <= 1'b1; end
check_link: begin tx_powerup <= 1'b1; tx_link_established <= 1'b1; end
check_wait: begin tx_powerup <= 1'b1; tx_link_established <= 1'b1; end
endcase
end
//------------------------------------------------------
// Manage the small timer that counts how long we have
// been in the current state (used for implementing
// short waits for some FSM states)
//------------------------------------------------------
if(state == next_state) begin
count_100us <= count_100us - 1;
end else begin
count_100us <= 15'd9999;
if(reset_addr_on_change == 1'b1) begin
aux_addr_i <= 8'h0;
end
end
state <= next_state;
//-----------------------------------------------------------
// How a short wait is implemented...
//
// Has the 100us pause expired, when no data was expected?
// If so, move to the next test.
//-----------------------------------------------------------
if(expected == 8'h00 && count_100us[14] == 1'b1) begin
next_state <= state_on_success;
end
//------------------------------------------------------------
// Processing the data that has been received from the sink
// over the AUX channel. The data bytes are just streamed out
// to a downstream component that uses the values, and may
// set flags that feed back in to control the FSM.
//------------------------------------------------------------
edid_de <= 1'b0;
adjust_de <= 1'b0;
dp_reg_de <= 1'b0;
status_de <= 1'b0;
if(channel_busy == 1'b0) begin
if(just_read_from_rx == 1'b1) begin
// Is this a short read?
if(rx_byte_count != expected-1 && aux_rx_empty == 1'b1) begin
next_state <= error;
end
if(rx_byte_count == 8'h00) begin
//------------------------------------------------
// Is the Ack missing? This doesn't work correctly
// if only byte is expected, as it gets overwritten
// by the following 'if' statement.
//
// Do not change this behaviour, by what it should do
// is test for "In progress" or "Again" requests, and
// retry the current operation.
//----------------------------------------------------
if(aux_rx_data != 8'h00) begin
next_state <= error;
end
if(rx_byte_count == expected-1 && aux_rx_empty == 1'b1) begin
next_state <= state_on_success;
end
//--------------------------------------------
// Has the Sink indicated that we should retry
// the current command, to allow the sink time
// to process the request?
//
// This only works if there is just one byte
// in the FIFO. This only works for DPCD
// transactions that aeert "AUX DEFER"
//--------------------------------------------
if(aux_rx_data == 8'h20) begin
// just flip states to force a retry.
state <= state_on_success;
next_state <= state;
end
end else begin
//-----------------------------------------------------------------
// Process a non-ack data byte, routing it out using the DE signals
//-----------------------------------------------------------------
edid_de <= edid_de_active;
adjust_de <= adjust_de_active;
dp_reg_de <= dp_reg_de_active;
status_de <= status_de_active;
aux_data <= aux_rx_data;
aux_addr <= aux_addr_i;
aux_addr_i <= aux_addr_i+1;
if(rx_byte_count == expected-1 && aux_rx_empty == 1'b1) begin
next_state <= state_on_success;
if(reset_addr_on_change == 1'b1) begin
aux_addr_i <= 8'h00;
end
end
end
end
end
//---------------------------------------------------
// Manage the AUX channel timeout and the retry to
// establish a link.
//-----------------------------------------------------------
// if channel_timeout = 1'b1 or (state /= reset and state /= link_established and retry_now = 1'b1) then
if(channel_timeout == 1'b1 || (state != reset && state != link_established &&
state != check_link && state != check_wait && retry_now == 1'b1)) begin
next_state <= reset;
state <= error;
end
//-----------------------------------------------
// If the link was established, then every
// now and then check the state of the link
//-----------------------------------------------
if(state == link_established && link_check_now == 1'b1) begin
next_state <= check_link;
end
//-----------------------------------------------
// If the full message has been received, then
// read any waiting data out of the FIFO.
// Also update the count of bytes read.
//-----------------------------------------------
if(channel_busy == 1'b0 && aux_rx_empty == 1'b0) begin
just_read_from_rx <= 1'b1;
end else begin
just_read_from_rx <= 1'b0;
end
if(just_read_from_rx == 1'b1) begin
rx_byte_count <= rx_byte_count+1;
end
//---------------------------------------
// Manage the reset timer
//---------------------------------------
if(retry_count == 0) begin
retry_now <= 1'b1;
retry_count <= 27'd49999999;
end else begin
retry_now <= 1'b0;
retry_count <= retry_count - 1;
end
if(link_check_count == 0) begin
link_check_now <= 1'b1;
// PPS actually became a 2Hz pulse....
link_check_count <= 27'd99999999;
end else begin
link_check_now <= 1'b0;
link_check_count <= link_check_count - 1;
end
end
endmodule |
module seven_segment_driver(
input wire clk,
input wire [11:0] value,
output reg [7:0] segments,
output reg [2:0] segment_enable
);
reg [39:0] counter;
reg [2:0] next_enable;
reg [3:0] to_decode;
always @(posedge clk) begin
// Top:RT:RB:Bot:LT:LB:mid:DP
case (to_decode)
4'b0000: segments <= 8'b00000011; // 0
4'b0001: segments <= 8'b10011111; // 1
4'b0010: segments <= 8'b00100101; // 2
4'b0011: segments <= 8'b00001101; // 3
4'b0100: segments <= 8'b10011001; // 4
4'b0101: segments <= 8'b01001001; // 5
4'b0110: segments <= 8'b01000001; // 6
4'b0111: segments <= 8'b00011111; // 7
4'b1000: segments <= 8'b00000001; // 8
4'b1001: segments <= 8'b00001001; // 9
4'b1010: segments <= 8'b00010001; // A
4'b1011: segments <= 8'b11000001; // B
4'b1100: segments <= 8'b01100011; // C
4'b1101: segments <= 8'b10000101; // D
4'b1110: segments <= 8'b01100001; // E
default: segments <= 8'b01110001; // F
endcase;
segment_enable <= next_enable;
case (counter[19:18])
2'b00: begin
next_enable <= 3'b110;
to_decode <= value[3:0];
end
2'b01: begin
next_enable <= 3'b101;
to_decode <= value[7:4];
end
2'b10: begin
next_enable <= 3'b011;
to_decode <= value[11:8];
end
default: begin
next_enable <= 3'b111;
to_decode <= 4'b0000;
end
endcase;
counter <= counter + 1;
end
endmodule |
module insert_main_stream_attrbutes_four_channels(
input clk,
//---------------------------------------------------
// This determines how the MSA is packed
//---------------------------------------------------
input active,
//---------------------------------------------------
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//---------------------------------------------------
input [23:0] M_value,
input [23:0] N_value,
input [11:0] H_visible,
input [11:0] V_visible,
input [11:0] H_total,
input [11:0] V_total,
input [11:0] H_sync_width,
input [11:0] V_sync_width,
input [11:0] H_start,
input [11:0] V_start,
input H_vsync_active_high,
input V_vsync_active_high,
input flag_sync_clock,
input flag_YCCnRGB,
input flag_422n444,
input flag_range_reduced,
input flag_interlaced_even,
input flag_YCC_colour_709,
input [1:0] flags_3d_Indicators,
input [4:0] bits_per_colour,
//---------------------------------------------------
// The stream of pixel data coming in and out
//---------------------------------------------------
input [72:0] in_data,
output reg [72:0] out_data);
localparam [8:0] SS = 9'b101011100; // K28.2
localparam [8:0] SE = 9'b111111101; // K29.7
localparam [8:0] BS = 9'b110111100; // K28.5
// wire [8:0] msa [39:0];
reg [7:0] misc0;
reg [7:0] misc1;
reg [3:0] count;
reg [0:0] last_was_bs;
reg [0:0] armed;
initial begin
count <= 4'b0000;
armed <= 1'b0;
last_was_bs <= 1'b0;
end
always @(*) begin
case(bits_per_colour)
5'b00110: misc0[7:5] = 3'b000; // 6 bpc
5'b01000: misc0[7:5] = 3'b001; // 8 bpp
5'b01010: misc0[7:5] = 3'b010; // 10 bpp
5'b01100: misc0[7:5] = 3'b011; // 12 bpp
5'b10000: misc0[7:5] = 3'b100; // 16 bpp
default: misc0[7:5] = 3'b001; // default to 8
endcase
misc0[4] = flag_YCC_colour_709;
misc0[3] = flag_range_reduced;
if(flag_YCCnRGB == 1'b0) begin
misc0[2:1] = 2'b00; // RGB444
end else if(flag_422n444 == 1'b1) begin
misc0[2:1] = 2'b01; // YCC422
end else begin
misc0[2:1] = 2'b10; // YCC444
end
misc0[0] = flag_sync_clock;
misc1 = {5'b00000, flags_3d_Indicators, flag_interlaced_even};
end
always @(posedge clk) begin
out_data[72] <= in_data[72];
// channel One
case(count)
// 4'b0000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid // Note the VB-ID Maud + Mvid are repeated once
// 4'b0010: // reserved for VB-ID, Maud, Mvid
4'b0011: out_data[17:0] <= { SS, SS };
4'b0100: out_data[17:0] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16] };
4'b0101: out_data[17:0] <= { 1'b0, 4'b0000, H_total[11:8], 1'b0, M_value[7:0] };
4'b0110: out_data[17:0] <= { 1'b0, 4'b0000, V_total[11:8], 1'b0, H_total[7:0] };
4'b0111: out_data[17:0] <= { 1'b0, H_vsync_active_high, 3'b000, H_sync_width[11:8], 1'b0, V_total[7:0] };
4'b1000: out_data[17:0] <= { 1'b0, SE, 1'b0, H_sync_width[7:0] };
default: out_data[17:0] <= { in_data[17:9], in_data[8:0]};
endcase
// channel Two
case(count)
// 4'b0000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid
// 4'b0010: // reserved for VB-ID, Maud, Mvid
4'b0011: out_data[35:18] <= { SS, SS};
4'b0100: out_data[35:18] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16]};
4'b0101: out_data[35:18] <= { 1'b0, 4'b0000, H_start[11:8], 1'b0, M_value[7:0]};
4'b0110: out_data[35:18] <= { 1'b0, 4'b0000, V_start[11:8], 1'b0, H_start[7:0]};
4'b0111: out_data[35:18] <= { 1'b0, V_vsync_active_high, 3'b000, V_sync_width[11:8], 1'b0, V_start[7:0]};
4'b1000: out_data[35:18] <= { 1'b0, SE, 1'b0, V_sync_width[7:0]};
default: out_data[35:18] <= { in_data[35:27], in_data[26:18] };
endcase
// Channel three
case(count)
// 4'b0000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid // Note the VB-ID Maud + Mvid are repeated once
// 4'b0010: // reserved for VB-ID, Maud, Mvid
4'b0011: out_data[53:36] <= { SS, SS };
4'b0100: out_data[53:36] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16] };
4'b0101: out_data[53:36] <= { 1'b0, 4'b0000, H_visible[11:8], 1'b0, M_value[7:0] };
4'b0110: out_data[53:36] <= { 1'b0, 4'b0000, V_visible[11:8], 1'b0, 4'b0000, H_visible[7:0] };
4'b0111: out_data[53:36] <= { 1'b0, 8'b00000000, 1'b0, 4'b0000, V_visible[7:0] };
4'b1000: out_data[53:36] <= { 1'b0, SE, 1'b0, 8'b00000000 };
default: out_data[53:36] <= { in_data[53:44], in_data[44:36]};
endcase
// channel Four
case(count)
// 4'b0000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid
// 4'b0010: // reserved for VB-ID, Maud, Mvid
4'b0011: out_data[71:54] <= { SS, SS};
4'b0100: out_data[71:54] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16]};
4'b0101: out_data[71:54] <= { 1'b0, N_value[23:16], 1'b0, M_value[7:0]};
4'b0110: out_data[71:54] <= { 1'b0, N_value[7:0], 1'b0, N_value[15:8]};
4'b0111: out_data[71:54] <= { 1'b0, misc1, 1'b0, misc0};
4'b1000: out_data[71:54] <= { 1'b0, SE, 1'b0, 8'b00000000};
default: out_data[71:54] <= { in_data[71:64], in_data[63:56] };
endcase
//---------------------------------------------------------
// Update the counter
//----------------------------------------------------------
if(count == 4'b1000) begin
count <= 4'b0000;
end else if(count != 4'b0000) begin
count <= count + 1;
end
//------------------------------------------
// Was the BS in the channel 0's data1 symbol
// during the last cycle?
//-------------------------------------------
if(last_was_bs == 1'b1) begin
//-------------------------------
// This time in_ch0_data0 = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[0] == 1'b1) begin
if(armed == 1'b1) begin
count <= 4'b0001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= active;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data0 symbol?
//-------------------------------------------
if(in_data[8:0] == BS) begin
//-------------------------------
// This time in_data[17:9] = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[9] == 1'b1) begin
if(armed == 1'b1) begin
count <= 4'b0001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= 1'b1;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data1 symbol?
//-------------------------------------------
last_was_bs <= (in_data[17:9] == BS) ? 1'b1 : 1'b0;
end
endmodule |
module test_source_1080p_RGB_444_gutted(
output reg [23:0] M_value,
output reg [23:0] N_value,
output reg [11:0] H_visible,
output reg [11:0] V_visible,
output reg [11:0] H_total,
output reg [11:0] V_total,
output reg [11:0] H_sync_width,
output reg [11:0] V_sync_width,
output reg [11:0] H_start,
output reg [11:0] V_start,
output reg H_vsync_active_high,
output reg V_vsync_active_high,
output reg flag_sync_clock,
output reg flag_YCCnRGB,
output reg flag_422n444,
output reg flag_YCC_colour_709,
output reg flag_range_reduced,
output reg flag_interlaced_even,
output reg [1:0] flags_3d_Indicators,
output reg [4:0] bits_per_colour,
output reg [2:0] stream_channel_count,
input clk,
output reg ready,
output [72:0] data
);
/////////////////////////////////////////////////////
//
// Transfer Units (TUs) are 0 to 19 pairs of symbols
// Making them 40 symbols long. Each normal TU transfers
// 11 pixels, making the pixel clock 11/40ths of the
// symbol rate. The symbol rate is 270M Symbols/s.
//
// So pixel clock is 11/40*270 = 74.25M pixels/sec
/////////////////////////////////////////////////////
localparam [8:0] DUMMY = 9'b000000000; // 0x03
localparam [8:0] SPARE = 9'b011111111; // 0xFF
localparam [8:0] ZERO = 9'b000000000; // 0x00
localparam [8:0] PIX = 9'b011001100; // Colour level 0xCC
localparam [8:0] BE = 9'b111111011; // K27.7 Blank End
localparam [8:0] BS = 9'b110111100; // K28.5 Blank Start
localparam [8:0] FS = 9'b111111110; // K30.7 Fill Start
localparam [8:0] FE = 9'b111110111; // K23.7 Fill End
localparam [8:0] VB_VS = 9'b000000001; // 0x00 VB-ID with Vertical blank asserted
localparam [8:0] VB_NVS = 9'b000000000; // 0x00 VB-ID without Vertical blank asserted
localparam [8:0] MVID = 9'b000010110; // 0x46 - low 8 bits of Mvid counter
localparam [8:0] MAUD = 9'b000000000; // 0x00
localparam [7:0] TUs_per_line = 8'd80; // 2200 / 2 channels / 27.5 clocks per TU
localparam [7:0] TU_length = 7'd50;
localparam [7:0] last_active_TU = 7'd70;
reg [7:0] index = 0;
reg [8:0] d0 = 0;
reg [8:0] d1 = 0;
reg [10:0] line_count = 0;
reg [7:0] block_count = 0;
reg switch_point = 0;
reg [47:0] pixels_next;
reg new_next;
initial begin
// Pixel clock ratio is 2200/4000 of the link speed.
// (i.e. it takes 4000 cycles of the 270MHz clock to
// transfer a horizontal scan line that is 2200 counts
// of the pixel clock.
// Because of this exact ratio, the Mvid value in the
// Stream is static.
M_value = 24'h004678;
N_value = 24'h008000;
H_visible = 12'd1920;
H_total = 12'd2200;
H_start = 12'd192;
H_sync_width = 12'd44;
V_visible = 12'd1080;
V_total = 12'd1125;
V_start = 12'd41;
V_sync_width = 12'd5;
H_vsync_active_high = 1'b0;
V_vsync_active_high = 1'b0;
flag_sync_clock = 1'b1;
flag_YCCnRGB = 1'b0;
flag_422n444 = 1'b0;
flag_range_reduced = 1'b0;
flag_interlaced_even = 1'b0;
flag_YCC_colour_709 = 1'b0;
flags_3d_Indicators = 2'b00;
bits_per_colour = 5'b01000;
stream_channel_count = 3'b010;
ready = 1'b1;
end
assign data[72] = switch_point;
assign data[71:36] = 36'b0;
assign data[35:27] = d1;
assign data[26:18] = d0;
assign data[17:9] = d1;
assign data[8:0] = d0;
always @(posedge clk) begin
// Load the next byte of the sequence into d0 and d1
case(index)
8'h00: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h01: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h02: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h03: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h04: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h05: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h06: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h07: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h08: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h09: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0B: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0C: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h10: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h11: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h12: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h13: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h14: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h15: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h16: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h17: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h18: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 1 - 17 white pixels and padding
8'h20: begin d0 <= PIX; d1 <= PIX; end
8'h21: begin d0 <= PIX; d1 <= PIX; end
8'h22: begin d0 <= PIX; d1 <= PIX; end
8'h23: begin d0 <= PIX; d1 <= PIX; end
8'h24: begin d0 <= PIX; d1 <= PIX; end
8'h25: begin d0 <= PIX; d1 <= PIX; end
8'h26: begin d0 <= PIX; d1 <= PIX; end
8'h27: begin d0 <= PIX; d1 <= PIX; end
8'h28: begin d0 <= PIX; d1 <= PIX; end
8'h29: begin d0 <= PIX; d1 <= PIX; end
8'h2A: begin d0 <= PIX; d1 <= PIX; end
8'h2B: begin d0 <= PIX; d1 <= PIX; end // 8 pixels
8'h2C: begin d0 <= PIX; d1 <= PIX; end
8'h2D: begin d0 <= PIX; d1 <= PIX; end
8'h2E: begin d0 <= PIX; d1 <= PIX; end // 10 more pixels
8'h2F: begin d0 <= PIX; d1 <= PIX; end
8'h30: begin d0 <= PIX; d1 <= PIX; end
8'h31: begin d0 <= PIX; d1 <= PIX; end // 12 Pixels
8'h32: begin d0 <= PIX; d1 <= PIX; end
8'h33: begin d0 <= PIX; d1 <= PIX; end
8'h34: begin d0 <= PIX; d1 <= FS; end // 1 more pixel
8'h35: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h36: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h37: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h38: begin d0 <= DUMMY; d1 <= FE; end
// Block 2 - 3 white pixels and padding; d1 <= VB-ID (-vblank); d1 <= Mvid; d1 <= MAud and junk
8'h40: begin d0 <= PIX; d1 <= PIX; end
8'h41: begin d0 <= PIX; d1 <= PIX; end
8'h42: begin d0 <= PIX; d1 <= PIX; end
8'h43: begin d0 <= PIX; d1 <= PIX; end
8'h44: begin d0 <= PIX; d1 <= PIX; end
8'h45: begin d0 <= PIX; d1 <= PIX; end
8'h46: begin d0 <= PIX; d1 <= PIX; end
8'h47: begin d0 <= PIX; d1 <= PIX; end
8'h48: begin d0 <= PIX; d1 <= PIX; end
8'h49: begin d0 <= PIX; d1 <= PIX; end
8'h4A: begin d0 <= PIX; d1 <= PIX; end
8'h4B: begin d0 <= PIX; d1 <= PIX; end // 8 pixels
8'h4C: begin d0 <= PIX; d1 <= PIX; end
8'h4D: begin d0 <= PIX; d1 <= PIX; end
8'h4E: begin d0 <= PIX; d1 <= PIX; end // 10 more pixels
8'h4F: begin d0 <= PIX; d1 <= PIX; end
8'h50: begin d0 <= PIX; d1 <= PIX; end
8'h51: begin d0 <= PIX; d1 <= PIX; end // 12 Pixels
8'h52: begin d0 <= PIX; d1 <= PIX; end
8'h53: begin d0 <= PIX; d1 <= PIX; end
8'h54: begin d0 <= PIX; d1 <= PIX; end
8'h55: begin d0 <= FS; d1 <= DUMMY; end
8'h56: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h57: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h58: begin d0 <= DUMMY; d1 <= FE; end
// Block 3 - 3 white pixels and padding; d1 <= VB-ID (-vblank); d1 <= Mvid; d1 <= MAud and junk
8'h60: begin d0 <= PIX; d1 <= PIX; end
8'h61: begin d0 <= PIX; d1 <= PIX; end
8'h62: begin d0 <= PIX; d1 <= PIX; end
8'h63: begin d0 <= PIX; d1 <= PIX; end
8'h64: begin d0 <= PIX; d1 <= PIX; end
8'h65: begin d0 <= PIX; d1 <= PIX; end
8'h66: begin d0 <= PIX; d1 <= PIX; end
8'h67: begin d0 <= PIX; d1 <= PIX; end
8'h68: begin d0 <= PIX; d1 <= PIX; end
8'h69: begin d0 <= PIX; d1 <= PIX; end
8'h6a: begin d0 <= PIX; d1 <= PIX; end
8'h6b: begin d0 <= PIX; d1 <= PIX; end
8'h6c: begin d0 <= PIX; d1 <= PIX; end
8'h6d: begin d0 <= PIX; d1 <= PIX; end
8'h6e: begin d0 <= PIX; d1 <= PIX; end
8'h6f: begin d0 <= PIX; d1 <= PIX; end
8'h70: begin d0 <= PIX; d1 <= PIX; end
8'h71: begin d0 <= PIX; d1 <= PIX; end
8'h72: begin d0 <= BS; d1 <= VB_NVS; end
8'h73: begin d0 <= MVID; d1 <= MAUD; end
8'h74: begin d0 <= VB_NVS; d1 <= MVID; end
8'h75: begin d0 <= MAUD; d1 <= DUMMY; end
8'h76: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h77: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h78: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 4 - 4 white pixels and padding; d1 <= VB-ID (+vblank); d1 <= Mvid; d1 <= MAud and junk
8'h80: begin d0 <= PIX; d1 <= PIX; end
8'h81: begin d0 <= PIX; d1 <= PIX; end
8'h82: begin d0 <= PIX; d1 <= PIX; end
8'h83: begin d0 <= PIX; d1 <= PIX; end
8'h84: begin d0 <= PIX; d1 <= PIX; end // Three Pixels
8'h85: begin d0 <= PIX; d1 <= PIX; end
8'h86: begin d0 <= PIX; d1 <= PIX; end
8'h87: begin d0 <= PIX; d1 <= PIX; end
8'h88: begin d0 <= PIX; d1 <= PIX; end
8'h89: begin d0 <= PIX; d1 <= PIX; end
8'h8A: begin d0 <= PIX; d1 <= PIX; end
8'h8B: begin d0 <= PIX; d1 <= PIX; end
8'h8C: begin d0 <= PIX; d1 <= PIX; end
8'h8D: begin d0 <= PIX; d1 <= PIX; end
8'h8E: begin d0 <= PIX; d1 <= PIX; end
8'h8F: begin d0 <= PIX; d1 <= PIX; end
8'h90: begin d0 <= PIX; d1 <= PIX; end
8'h91: begin d0 <= PIX; d1 <= PIX; end
8'h92: begin d0 <= BS; d1 <= VB_VS; end
8'h93: begin d0 <= MVID; d1 <= MAUD; end
8'h94: begin d0 <= VB_VS; d1 <= MVID; end
8'h95: begin d0 <= MAUD; d1 <= DUMMY; end
8'h96: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h97: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h98: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 5 - DUMMY;Blank Start; d1 <= VB-ID (+vblank); d1 <= Mvid; d1 <= MAud and junk
8'hA0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAA: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAB: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAC: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAD: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAE: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAF: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB2: begin d0 <= BS; d1 <= VB_VS; end
8'hB3: begin d0 <= MVID; d1 <= MAUD; end
8'hB4: begin d0 <= VB_VS; d1 <= MVID; end
8'hB5: begin d0 <= MAUD; d1 <= DUMMY; end
8'hB6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB8: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 6 - just blank end
8'hC0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hC9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCA: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCB: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCC: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCD: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCE: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hCF: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hD8: begin d0 <= DUMMY; d1 <= BE; end
default: begin d0 <= SPARE; d1 <= SPARE; end
endcase
if(index[4:0] == 5'd24) begin // TU Length / 2 - 1 = 19
index[4:0] <= 5'd0;
if(block_count == TUs_per_line-1) begin
block_count <= 8'b0;
if(line_count == V_total-1) begin
line_count <= 11'b0;
end else begin
line_count <= line_count + 1;
end
end else begin
block_count <= block_count +1;
end
// Block 0 - empty
// Block 1 - 11 pixels FS padding FE
// Block 2 - 3 pixels, BS, VB-ID (-vsync), Mvid, Maud, VB-ID (-vsync), Mvid, Maud, empty
// Block 2 - 3 pixels, BS, VB-ID (+vsync), Mvid, Maud, VB-ID (+vsync), Mvid, Maud, empty
// Block 4 - empty space for 3 pixels ,BS, VB-ID (+vsync), Mvid, MAud. VB-ID (+vsync), Mvid, MAud, empty
// Block 5 - last symbol is blank end
index[7:5] <= 3'b000; // Dummy symbols for the default block
switch_point <= 1'b0;
if(line_count < V_visible-1) begin // lines of active video (except last)
if(block_count < 1) begin
index[7:5] <= 3'b110; // Just blank ending in BE
end else if(block_count < last_active_TU) begin
if(block_count[1:0] == 2'b00 && block_count[4:2] != 3'b111) begin
index[7:5] <= 3'b010; // Pixels plus fill
end else begin
index[7:5] <= 3'b001; // Pixels plus fill
end
end else if(block_count == last_active_TU) begin
index[7:5] <= 3'b011; // Pixels BS and VS-ID block (no VBLANK flag)
end
end else if(line_count == V_visible-1) begin // Last line of active video
if(block_count < 1) begin
index[7:5] <= 3'b110; // Just blank ending in BE
end else if(block_count < last_active_TU) begin
if(block_count[1:0] == 2'b00 && block_count[4:2] != 3'b111) begin
index[7:5] <= 3'b010; // Pixels plus fill
end else begin
index[7:5] <= 3'b001; // Pixels plus fill
end
end else if(block_count == last_active_TU) begin
index[7:5] <= 3'b100; // Pixels BS and VS-ID block (with VBLANK flag)
end
end else begin
//---------------------------------------------------------------
// Allow switching to/from the idle pattern during the vertical blank
//---------------------------------------------------------------
if(block_count < last_active_TU) begin
switch_point <= 1'b1;
end else if(block_count == last_active_TU) begin
index[7:5] <= 3'b101; // Dummy symbols, BS and VS-ID block (with VBLANK flag)
end
end
end else begin
index <= index + 1;
end
end
endmodule |
module insert_main_stream_attrbutes_one_channel(
input clk,
//---------------------------------------------------
// This determines how the MSA is packed
//---------------------------------------------------
input active,
//---------------------------------------------------
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//---------------------------------------------------
input [23:0] M_value,
input [23:0] N_value,
input [11:0] H_visible,
input [11:0] V_visible,
input [11:0] H_total,
input [11:0] V_total,
input [11:0] H_sync_width,
input [11:0] V_sync_width,
input [11:0] H_start,
input [11:0] V_start,
input H_vsync_active_high,
input V_vsync_active_high,
input flag_sync_clock,
input flag_YCCnRGB,
input flag_422n444,
input flag_range_reduced,
input flag_interlaced_even,
input flag_YCC_colour_709,
input [1:0] flags_3d_Indicators,
input [4:0] bits_per_colour,
//---------------------------------------------------
// The stream of pixel data coming in and out
//---------------------------------------------------
input [72:0] in_data,
output reg [72:0] out_data);
localparam [8:0] SS = 9'b101011100; // K28.2
localparam [8:0] SE = 9'b111111101; // K29.7
localparam [8:0] BS = 9'b110111100; // K28.5
// wire [8:0] msa [39:0];
reg [7:0] misc0;
reg [7:0] misc1;
reg [4:0] count;
reg [0:0] last_was_bs;
reg [0:0] armed;
initial begin
count <= 5'b00000;
armed <= 1'b0;
last_was_bs <= 1'b0;
end
always @(*) begin
case(bits_per_colour)
5'b00110: misc0[7:5] = 3'b000; // 6 bpc
5'b01000: misc0[7:5] = 3'b001; // 8 bpp
5'b01010: misc0[7:5] = 3'b010; // 10 bpp
5'b01100: misc0[7:5] = 3'b011; // 12 bpp
5'b10000: misc0[7:5] = 3'b100; // 16 bpp
default: misc0[7:5] = 3'b001; // default to 8
endcase
misc0[4] = flag_YCC_colour_709;
misc0[3] = flag_range_reduced;
if(flag_YCCnRGB == 1'b0) begin
misc0[2:1] = 2'b00; // RGB444
end else if(flag_422n444 == 1'b1) begin
misc0[2:1] = 2'b01; // YCC422
end else begin
misc0[2:1] = 2'b10; // YCC444
end
misc0[0] = flag_sync_clock;
misc1 = {5'b00000, flags_3d_Indicators, flag_interlaced_even};
end
always @(posedge clk) begin
// default to copying the input data across
out_data <= in_data;
case(count)
5'b00000: out_data[17:0] <= in_data[17:0]; // while waiting for BS symbol
5'b00001: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00010: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00011: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00100: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00101: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00110: out_data[17:0] <= in_data[17:0]; // reserved for VB-ID, Maud, Mvid
5'b00111: out_data[17:0] <= {SS, SS};
5'b01000: out_data[17:0] <= {1'b0, M_value[15:8], 1'b0, M_value[23:16]};
5'b01001: out_data[17:0] <= {1'b0, 4'b0000, H_total[11:8], 1'b0, M_value[7:0]};
5'b01010: out_data[17:0] <= {1'b0, 4'b0000, V_total[11:8], 1'b0, H_total[7:0]};
5'b01011: out_data[17:0] <= {1'b0, H_vsync_active_high, 3'b000, H_sync_width[11:8], 1'b0, V_total[7:0]};
5'b01100: out_data[17:0] <= {1'b0, M_value[23:16], 1'b0, H_sync_width[7:0]};
5'b01101: out_data[17:0] <= {1'b0, M_value[7:0], 1'b0, M_value[15:8]};
5'b01110: out_data[17:0] <= {1'b0, H_start[7:0], 1'b0, 4'b0000, H_start[11:8]};
5'b01111: out_data[17:0] <= {1'b0, V_start[7:0], 1'b0, 4'b0000, V_start[11:8]};
5'b10000: out_data[17:0] <= {1'b0, V_sync_width[7:0], 1'b0, V_vsync_active_high, 3'b000, V_sync_width[11:8]};
5'b10001: out_data[17:0] <= {1'b0, M_value[15:8], 1'b0, M_value[23:16]};
5'b10010: out_data[17:0] <= {1'b0, 4'b0000, H_visible[11:8], 1'b0, M_value[7:0]};
5'b10011: out_data[17:0] <= {1'b0, 4'b0000, V_visible[11:8], 1'b0, H_visible[7:0]};
5'b10100: out_data[17:0] <= {1'b0, 8'b00000000, 1'b0, V_visible[7:0]};
5'b10101: out_data[17:0] <= {1'b0, M_value[23:16], 1'b0, 8'b00000000};
5'b10110: out_data[17:0] <= {1'b0, M_value[7:0], 1'b0, M_value[15: 8]};
5'b10111: out_data[17:0] <= {1'b0, N_value[15: 8], 1'b0, N_value[23:16]};
5'b11000: out_data[17:0] <= {1'b0, misc0, 1'b0, N_value[7:0]};
5'b11001: out_data[17:0] <= {1'b0, 8'b00000000, 1'b0, misc1};
5'b11010: out_data[17:0] <= {1'b0, 8'b00000000, SE};
default: out_data[17:0] <= in_data[17:0];
endcase
//----------------------------------------------------------
// Update the counter
//----------------------------------------------------------
if(count == 5'b11011) begin
count <= 5'b00000;
end else if(count != 5'b00000) begin
count <= count + 1;
end
//-------------------------------------------
// Was the BS in the channel 0's data1 symbol
// during the last cycle?
//-------------------------------------------
if(last_was_bs == 1'b1) begin
//-------------------------------
// This time in_ch0_data0 = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[0] == 1'b1) begin
if(armed == 1'b1) begin
count <= 5'b00001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= active;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data0 symbol?
//-------------------------------------------
if(in_data[8:0] == BS) begin
//-------------------------------
// This time in_data(17 downto 9) = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[9] == 1'b1) begin
if(armed == 1'b1) begin
count <= 5'b00001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= 1'b1;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data1 symbol?
//-------------------------------------------
if(in_data[17:9] == BS) begin
last_was_bs <= 1'b1;
end else begin
last_was_bs <= 1'b0;
end
end
endmodule |
module insert_main_stream_attrbutes_two_channels(
input clk,
//---------------------------------------------------
// This determines how the MSA is packed
//---------------------------------------------------
input active,
//---------------------------------------------------
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//---------------------------------------------------
input [23:0] M_value,
input [23:0] N_value,
input [11:0] H_visible,
input [11:0] V_visible,
input [11:0] H_total,
input [11:0] V_total,
input [11:0] H_sync_width,
input [11:0] V_sync_width,
input [11:0] H_start,
input [11:0] V_start,
input H_vsync_active_high,
input V_vsync_active_high,
input flag_sync_clock,
input flag_YCCnRGB,
input flag_422n444,
input flag_range_reduced,
input flag_interlaced_even,
input flag_YCC_colour_709,
input [1:0] flags_3d_Indicators,
input [4:0] bits_per_colour,
//---------------------------------------------------
// The stream of pixel data coming in and out
//---------------------------------------------------
input [72:0] in_data,
output reg [72:0] out_data);
localparam [8:0] SS = 9'b101011100; // K28.2
localparam [8:0] SE = 9'b111111101; // K29.7
localparam [8:0] BS = 9'b110111100; // K28.5
// wire [8:0] msa [39:0];
reg [7:0] misc0;
reg [7:0] misc1;
reg [3:0] count;
reg [0:0] last_was_bs;
reg [0:0] armed;
initial begin
count <= 5'b00000;
armed <= 1'b0;
last_was_bs <= 1'b0;
out_data <= 72'b0;
end
always @(*) begin
case(bits_per_colour)
5'b00110: misc0[7:5] = 3'b000; // 6 bpc
5'b01000: misc0[7:5] = 3'b001; // 8 bpp
5'b01010: misc0[7:5] = 3'b010; // 10 bpp
5'b01100: misc0[7:5] = 3'b011; // 12 bpp
5'b10000: misc0[7:5] = 3'b100; // 16 bpp
default: misc0[7:5] = 3'b001; // default to 8
endcase
misc0[4] = flag_YCC_colour_709;
misc0[3] = flag_range_reduced;
if(flag_YCCnRGB == 1'b0) begin
misc0[2:1] = 2'b00; // RGB444
end else if(flag_422n444 == 1'b1) begin
misc0[2:1] = 2'b01; // YCC422
end else begin
misc0[2:1] = 2'b10; // YCC444
end
misc0[0] = flag_sync_clock;
misc1 = {5'b00000, flags_3d_Indicators, flag_interlaced_even};
end
always @(posedge clk) begin
out_data[72] <= in_data[72];
case(count)
// 4'b0000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid
// 4'b0010: // reserved for VB-ID, Maud, Mvid
// 4'b0011: // reserved for VB-ID, Maud, Mvid
4'b0100: out_data[17:0] <= { SS, SS };
4'b0101: out_data[17:0] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16] };
4'b0110: out_data[17:0] <= { 1'b0, 4'b0000, H_total[11:8], 1'b0, M_value[7:0] };
4'b0111: out_data[17:0] <= { 1'b0, 4'b0000, V_total[11:8], 1'b0, H_total[7:0] };
4'b1000: out_data[17:0] <= { 1'b0, H_vsync_active_high, 3'b000, H_sync_width[11:8], 1'b0, V_total[7:0] };
4'b1001: out_data[17:0] <= { 1'b0, M_value[23:16], 1'b0, H_sync_width[7:0] };
4'b1010: out_data[17:0] <= { 1'b0, M_value[7:0], 1'b0, M_value[15:8] };
4'b1011: out_data[17:0] <= { 1'b0, H_visible[7:0], 1'b0, 4'b0000, H_visible[11:8] };
4'b1100: out_data[17:0] <= { 1'b0, V_visible[7:0], 1'b0, 4'b0000, V_visible[11:8] };
4'b1101: out_data[17:0] <= { 1'b0, 8'b00000000, 1'b0, 8'b00000000 };
4'b1110: out_data[17:0] <= { in_data[17:9], SE };
default: out_data[17:0] <= { in_data[17:9], in_data[8:0]};
endcase
case(count)
// 4'b00000: // while waiting for BS symbol
// 4'b0001: // reserved for VB-ID, Maud, Mvid
// 4'b0010: // reserved for VB-ID, Maud, Mvid
// 4'b0011: // reserved for VB-ID, Maud, Mvid
4'b0100: out_data[35:18] <= { SS, SS};
4'b0101: out_data[35:18] <= { 1'b0, M_value[15:8], 1'b0, M_value[23:16]};
4'b0110: out_data[35:18] <= { 1'b0, 4'b0000, H_start[11:8], 1'b0, M_value[7:0]};
4'b0111: out_data[35:18] <= { 1'b0, 4'b0000, V_start[11:8], 1'b0, H_start[7:0]};
4'b1000: out_data[35:18] <= { 1'b0, V_vsync_active_high, 3'b000, V_sync_width[11:8], 1'b0, V_start[7:0]};
4'b1001: out_data[35:18] <= { 1'b0, M_value[23:16], 1'b0, V_sync_width[7:0]};
4'b1010: out_data[35:18] <= { 1'b0, M_value[7:0], 1'b0, M_value[15:8]};
4'b1011: out_data[35:18] <= { 1'b0, N_value[15:8], 1'b0, N_value[23:16]};
4'b1100: out_data[35:18] <= { 1'b0, misc0, 1'b0, N_value[7:0]};
4'b1101: out_data[35:18] <= { 1'b0, 8'b00000000, 1'b0, misc1};
4'b1110: out_data[35:18] <= { in_data[35:27], SE};
default: out_data[35:18] <= { in_data[35:27], in_data[26:18] };
endcase
//---------------------------------------------------------
// Update the counter
//----------------------------------------------------------
if(count == 4'b1110) begin
count <= 4'b0000;
end else if(count != 4'b0000) begin
count <= count + 1;
end
//------------------------------------------
// Was the BS in the channel 0's data1 symbol
// during the last cycle?
//-------------------------------------------
if(last_was_bs == 1'b1) begin
//-------------------------------
// This time in_ch0_data0 = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[0] == 1'b1) begin
if(armed == 1'b1) begin
count <= 4'b0001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= active;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data0 symbol?
//-------------------------------------------
if(in_data[8:0] == BS) begin
//-------------------------------
// This time in_data[17:9] = VB-ID
// First, see if this is a line in
// the VSYNC
//-------------------------------
if(in_data[9] == 1'b1) begin
if(armed == 1'b1) begin
count <= 4'b0001;
armed <= 1'b0;
end
end else begin
// Not in the Vblank. so arm the trigger to send the MSA
// when the next BS with Vblank asserted occurs
armed <= 1'b1;
end
end
//-------------------------------------------
// Is the BS in the channel 0's data1 symbol?
//-------------------------------------------
last_was_bs <= (in_data[17:9] == BS) ? 1'b1 : 1'b0;
end
endmodule |
module test_source_3840_2180_YCC_422_ch2(
output reg [23:0] M_value,
output reg [23:0] N_value,
output reg [11:0] H_visible,
output reg [11:0] V_visible,
output reg [11:0] H_total,
output reg [11:0] V_total,
output reg [11:0] H_sync_width,
output reg [11:0] V_sync_width,
output reg [11:0] H_start,
output reg [11:0] V_start,
output reg H_vsync_active_high,
output reg V_vsync_active_high,
output reg flag_sync_clock,
output reg flag_YCCnRGB,
output reg flag_422n444,
output reg flag_YCC_colour_709,
output reg flag_range_reduced,
output reg flag_interlaced_even,
output reg [1:0] flags_3d_Indicators,
output reg [4:0] bits_per_colour,
output reg [2:0] stream_channel_count,
input clk,
output reg ready,
output [72:0] data
);
localparam [8:0] DUMMY = 9'b000000011; // 0x03
localparam [8:0] SPARE = 9'b011111111; // 0xFF
localparam [8:0] ZERO = 9'b000000000; // 0x00
localparam [8:0] PIX_80 = 9'b011001100; // 0x80
localparam [8:0] SS = 9'b101011100; // K28.2
localparam [8:0] SE = 9'b111111101; // K29.7
localparam [8:0] BE = 9'b111111011; // K27.7
localparam [8:0] BS = 9'b110111100; // K28.5
localparam [8:0] SR = 9'b100011100; // K28.0
localparam [8:0] FS = 9'b111111110; // K30.7
localparam [8:0] FE = 9'b111110111; // K23.7
localparam [8:0] VB_VS = 9'b000000001; // 0x00 VB-ID with Vertical blank asserted
localparam [8:0] VB_NVS = 9'b000000000; // 0x00 VB-ID without Vertical blank asserted
localparam [8:0] MVID = 9'b001101000; // 0x68
localparam [8:0] MAUD = 9'b000000000; // 0x00
reg [7:0] index = 0;
reg [8:0] d0 = 0;
reg [8:0] d1 = 0;
reg [11:0] line_count = 0;
reg [7:0] row_count = 0;
reg switch_point = 0;
initial begin
M_value = 24'h07DA1C;
N_value = 24'h080000;
H_total = 12'hFC0;
H_visible = 12'hF00;
H_start = 12'h0A0;
H_sync_width = 12'h030;
V_total = 12'h890;
V_visible = 12'h870;
V_sync_width = 12'h003;
V_start = 12'h01A;
H_vsync_active_high = 1'b1;
V_vsync_active_high = 1'b1;
flag_sync_clock = 1'b1;
flag_YCCnRGB = 1'b1; // YCC
flag_422n444 = 1'b1; // 422
flag_range_reduced = 1'b1;
flag_interlaced_even = 1'b0;
flag_YCC_colour_709 = 1'b0;
flags_3d_Indicators = 2'b00;
bits_per_colour = 5'b01000;
stream_channel_count = 3'b010;
ready = 1'b1;
end
assign data[72] = switch_point;
assign data[71:36] = 54'b0;
assign data[35:27] = d1;
assign data[26:18] = d0;
assign data[17:9] = d1;
assign data[8:0] = d0;
always @(posedge clk) begin
case(index)
8'h00: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h01: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h02: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h03: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h04: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h05: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h06: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h07: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h08: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h09: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0B: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0C: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h10: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h11: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h12: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h13: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h14: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h15: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h16: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h17: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h18: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h19: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h1A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h1B: begin d0 <= SPARE; d1 <= SPARE; end
8'h1C: begin d0 <= SPARE; d1 <= SPARE; end
8'h1D: begin d0 <= SPARE; d1 <= SPARE; end
8'h1E: begin d0 <= SPARE; d1 <= SPARE; end
8'h1F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 1 - 4 white pixels and padding
8'h20: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h21: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h22: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h23: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h24: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h25: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h26: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h27: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h28: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h29: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2A: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2B: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2C: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2D: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2E: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h2F: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h30: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h31: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h32: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h33: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h34: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h35: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h36: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h37: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h38: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h39: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h3A: begin d0 <= PIX_80; d1 <= FE; end
8'h3B: begin d0 <= SPARE; d1 <= SPARE; end
8'h3C: begin d0 <= SPARE; d1 <= SPARE; end
8'h3D: begin d0 <= SPARE; d1 <= SPARE; end
8'h3E: begin d0 <= SPARE; d1 <= SPARE; end
8'h3F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 2 - 4 white pixels and padding; d1 <= VB-ID (-vsync); d1 <= Mvid; d1 <= MAud and junk
8'h40: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h41: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h42: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h43: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h44: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h45: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h46: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h47: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h48: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h49: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h4A: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h4B: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h4C: begin d0 <= BS; d1 <= VB_NVS; end
8'h4D: begin d0 <= MVID; d1 <= MAUD; end
8'h4E: begin d0 <= VB_NVS; d1 <= MVID; end
8'h4F: begin d0 <= MAUD; d1 <= DUMMY; end
8'h50: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h51: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h52: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h53: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h54: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h55: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h56: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h57: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h58: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h59: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h5A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h5B: begin d0 <= SPARE; d1 <= SPARE; end
8'h5C: begin d0 <= SPARE; d1 <= SPARE; end
8'h5D: begin d0 <= SPARE; d1 <= SPARE; end
8'h5E: begin d0 <= SPARE; d1 <= SPARE; end
8'h5F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 3 - 8 white pixels and padding; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h60: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h61: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h62: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h63: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h64: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h65: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h66: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h67: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h68: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h69: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h6A: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h6B: begin d0 <= PIX_80; d1 <= PIX_80; end
8'h6C: begin d0 <= BS; d1 <= VB_VS; end
8'h6D: begin d0 <= MVID; d1 <= MAUD; end
8'h6E: begin d0 <= VB_VS; d1 <= MVID; end
8'h6F: begin d0 <= MAUD; d1 <= DUMMY; end
8'h70: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h71: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h72: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h73: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h74: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h75: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h76: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h77: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h78: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h79: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7B: begin d0 <= SPARE; d1 <= SPARE; end
8'h7C: begin d0 <= SPARE; d1 <= SPARE; end
8'h7D: begin d0 <= SPARE; d1 <= SPARE; end
8'h7E: begin d0 <= SPARE; d1 <= SPARE; end
8'h7F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 4 - DUMMY;Blank Start; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h80: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h81: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h82: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h83: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h84: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h85: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h86: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h87: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h88: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h89: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8a: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8b: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8c: begin d0 <= BS; d1 <= VB_VS; end
8'h8d: begin d0 <= MVID; d1 <= MAUD; end
8'h8e: begin d0 <= VB_VS; d1 <= MVID; end
8'h8f: begin d0 <= MAUD; d1 <= DUMMY; end
8'h90: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h91: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h92: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h93: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h93: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h94: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h95: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h96: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h97: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h98: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h99: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h9A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h9B: begin d0 <= SPARE; d1 <= SPARE; end
8'h9C: begin d0 <= SPARE; d1 <= SPARE; end
8'h9D: begin d0 <= SPARE; d1 <= SPARE; end
8'h9E: begin d0 <= SPARE; d1 <= SPARE; end
8'h9F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 5 - just blank end
8'hA0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAA: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAB: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAC: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAD: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAE: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAF: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hBA: begin d0 <= DUMMY; d1 <= BE; end
8'hBB: begin d0 <= SPARE; d1 <= SPARE; end
8'hBC: begin d0 <= SPARE; d1 <= SPARE; end
8'hBD: begin d0 <= SPARE; d1 <= SPARE; end
8'hBE: begin d0 <= SPARE; d1 <= SPARE; end
8'hBF: begin d0 <= SPARE; d1 <= SPARE; end
default: begin d0 <= SPARE; d1 <= SPARE; end
endcase
if(index[4:0] == 5'd26) begin
index[4:0] <= 5'd0;
if(row_count == 76) begin
row_count <= 8'b0;
index[4:0] <= 5'd25;
if(line_count == V_total-1)
begin
line_count <= 12'b0;
end else begin
line_count <= line_count + 1;
end
end else begin
row_count <= row_count +1;
end
// Block 0 - Junk
// Block 1- 8 white pixels and padding
// Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
// Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
// Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
// Block 5 - just blank end
index[7:5] <= 3'b000; // Dummy symbols
switch_point <= 1'b0;
if(line_count < V_visible-1) begin //-- lines of active video (except first and last)
if (row_count < 1) index[7:5] <= 3'b101; // Just blank end BE
else if(row_count < 73) index[7:5] <= 3'b001; // Pixels plus fill
else if(row_count == 73) index[7:5] <= 3'b010; // Pixels BS and VS-ID block (no VBLANK flag)
end else if(line_count == V_visible-1) begin // Last line of active video
if(row_count < 1) begin
index[7:5] <= 3'b101; // Just blank end BE
end else if(row_count < 73) begin
index[7:5] <= 3'b001; // Pixels plus fill
end else if(row_count == 73) begin
index[7:5] <= 3'b011; // Pixels BS and VS-ID block (with VBLANK flag)
end
end else begin
//---------------------------------------------------------------
// Allow switching to/from the idle pattern during the vertical blank
//---------------------------------------------------------------
if(row_count < 73) begin
switch_point <= 1'b1;
end else if(row_count == 73) begin
index[7:5] <= 3'b100; // Dummy symbols, BS and VS-ID block (with VBLANK flag)
end
end
end else begin
index <= index + 1;
end
end
endmodule |
module test_source_800_600_RGB_444_stream(
output reg [23:0] M_value,
output reg [23:0] N_value,
output reg [11:0] H_visible,
output reg [11:0] V_visible,
output reg [11:0] H_total,
output reg [11:0] V_total,
output reg [11:0] H_sync_width,
output reg [11:0] V_sync_width,
output reg [11:0] H_start,
output reg [11:0] V_start,
output reg H_vsync_active_high,
output reg V_vsync_active_high,
output reg flag_sync_clock,
output reg flag_YCCnRGB,
output reg flag_422n444,
output reg flag_YCC_colour_709,
output reg flag_range_reduced,
output reg flag_interlaced_even,
output reg [1:0] flags_3d_Indicators,
output reg [4:0] bits_per_colour,
output reg [2:0] stream_channel_count,
input clk,
output reg ready,
output reg [72:0] data
);
/////////////////////////////////////////////////////
//
// Transfer Units (TUs) are 0 to 26 pairs of symbols
// Making them 54 symbols long. Each TU can transfer
// 8 pixels, making the pixel clock 8/54ths of the
// symbol rate. The symbol rate is 270M Symbols/s.
//
// So pixel clock is 8/54*270 = 40M pixels/sec
/////////////////////////////////////////////////////
localparam [8:0] DUMMY = 9'b000000000; // 0x03
localparam [8:0] SPARE = 9'b011111111; // 0xFF
localparam [8:0] ZERO = 9'b000000000; // 0x00
localparam [8:0] PIX_00 = 9'b010000000; // Byte 0 of pixel 0
localparam [8:0] PIX_01 = 9'b010000001; // Byte 1 of pixel 0
localparam [8:0] PIX_02 = 9'b010000010; // Byte 2 of pixel 0
localparam [8:0] PIX_10 = 9'b010000100; // Byte 0 of pixel 1
localparam [8:0] PIX_11 = 9'b010000101; // Byte 1 of pixel 1
localparam [8:0] PIX_12 = 9'b010000110; // Byte 2 of pixel 1
localparam [8:0] BE = 9'b111111011; // K27.7 Blank End
localparam [8:0] BS = 9'b110111100; // K28.5 Blank Start
localparam [8:0] FS = 9'b111111110; // K30.7 Fill Start
localparam [8:0] FE = 9'b111110111; // K23.7 Fill End
localparam [8:0] VB_VS = 9'b000000001; // 0x00 VB-ID with Vertical blank asserted
localparam [8:0] VB_NVS = 9'b000000000; // 0x00 VB-ID without Vertical blank asserted
localparam [8:0] MVID = 9'b001101000; // 0x68
localparam [8:0] MAUD = 9'b000000000; // 0x00
reg [7:0] index = 0;
reg [8:0] d0 = 0;
reg [8:0] d1 = 0;
reg [9:0] line_count = 0;
reg [7:0] row_count = 0;
reg switch_point = 0;
reg [47:0] pixels_next;
reg new_next;
reg [18:0] pixel_count;
reg [47:0] pixels;
reg switch_point_last;
initial begin
M_value = 24'h012F68;
N_value = 24'h080000;
H_visible = 12'h320; // 800
V_visible = 12'h258; // 600
H_total = 12'h420; // 1056
V_total = 12'h274; // 628
H_sync_width = 12'h080; // 128
V_sync_width = 12'h004; // 4
H_start = 12'h0D8; // 216
V_start = 12'h01b; // 37
H_vsync_active_high = 1'b0;
V_vsync_active_high = 1'b0;
flag_sync_clock = 1'b1;
flag_YCCnRGB = 1'b0;
flag_422n444 = 1'b0;
flag_range_reduced = 1'b0;
flag_interlaced_even = 1'b0;
flag_YCC_colour_709 = 1'b0;
flags_3d_Indicators = 2'b00;
bits_per_colour = 5'b01000;
stream_channel_count = 3'b001;
ready = 1'b1;
data = 73'b0;
pixel_count = 19'b0;
switch_point_last = 1'b0;
end
always @(posedge clk) begin
//////////////////////////////////
// Pixel value generation
//////////////////////////////////
/////////////////////////////////////////////
// Detect the start of frame to reset counter
/////////////////////////////////////////////
if(switch_point_last == 1'b0 && switch_point == 1'b1) begin
pixel_count <= 19'b0;
pixels <= 48'h010001000000; // pixel 0 & 1
end
////////////////////////////////////////////////////
// Advance the counter when last byte of pixel is used
////////////////////////////////////////////////////
if(d1 == PIX_12) begin // Can only be sed for d1
if(pixel_count == 798) begin
pixels[7:0] <= 8'h00; // Reset Red in pixel 0
pixels[15:8] <= pixels[15:8] + 1; // Change Green in pixel 0
pixels[23:16] <= pixels[15:8] + 1; // Change Blue in pixel 0
pixels[31:24] <= 8'h01; // Reset Red in pixel 1
pixels[39:32] <= pixels[39:32] + 1; // Change Green in pixel 1
pixels[47:40] <= pixels[39:32] + 1; // Change Blue in pixel 1
pixel_count <= 19'b0;
end else begin
pixels[7:0] <= pixels[7:0] + 2; // Change Red in pixel 0
pixels[23:16] <= pixels[23:16] + 2; // Change Blue in pixel 0
pixels[31:24] <= pixels[31:24] + 2; // Change Red in pixel 1
pixels[47:40] <= pixels[47:40] + 2; // Change Blue in pixel 1
pixel_count <= pixel_count + 2;
end
end
switch_point_last <= switch_point;
///////////////////////////////////////////////
// Scheduling the data out to the pipeline
///////////////////////////////////////////////
///////////////////////////////////////////////
// Stage 1 of video pipeline
//
// Replace the sentinel values with pixel data
///////////////////////////////////////////////
case(d1)
// Data from pixel 0
PIX_01: begin data[17:9] <= {1'b0, pixels[15:8]}; end
// Data from pixel 1
PIX_10: begin data[17:9] <= {1'b0, pixels[31:24]}; end
PIX_12: begin data[17:9] <= {1'b0, pixels[47:40]}; end
default: data[17:9] <= d1;
endcase
case(d0)
// Data from pixel 0
PIX_00: begin data[8:0] <= {1'b0, pixels[7:0]}; end
PIX_02: begin data[8:0] <= {1'b0, pixels[23:16]}; end
// Data from pixel 1
PIX_11: begin data[8:0] <= {1'b0, pixels[39:32]}; end
default: data[8:0] <= d0;
endcase
data[71:18] <= 54'b0;
data[72] <= switch_point;
///////////////////////////////////////////////
// Stage 0 of pipeline
//
// Lookup what type of values to send
///////////////////////////////////////////////
// Now load the next byte of the sequence into d0 and d1
case(index)
8'h00: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h01: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h02: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h03: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h04: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h05: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h06: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h07: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h08: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h09: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0B: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0C: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h10: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h11: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h12: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h13: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h14: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h15: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h16: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h17: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h18: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h19: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h1A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h1B: begin d0 <= SPARE; d1 <= SPARE; end
8'h1C: begin d0 <= SPARE; d1 <= SPARE; end
8'h1D: begin d0 <= SPARE; d1 <= SPARE; end
8'h1E: begin d0 <= SPARE; d1 <= SPARE; end
8'h1F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 1 - 8 white pixels and padding
8'h20: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h21: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h22: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h23: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h24: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h25: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h26: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h27: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h28: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h29: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h2A: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h2B: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h2C: begin d0 <= FS; d1 <= DUMMY; end
8'h2D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h2E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h2F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h30: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h31: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h32: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h33: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h34: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h35: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h36: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h37: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h38: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h39: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h3A: begin d0 <= DUMMY; d1 <= FE; end
8'h3B: begin d0 <= SPARE; d1 <= SPARE; end
8'h3C: begin d0 <= SPARE; d1 <= SPARE; end
8'h3D: begin d0 <= SPARE; d1 <= SPARE; end
8'h3E: begin d0 <= SPARE; d1 <= SPARE; end
8'h3F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 2 - 8 white pixels and padding; d1 <= VB-ID (-vsync); d1 <= Mvid; d1 <= MAud and junk
8'h40: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h41: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h42: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h43: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h44: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h45: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h46: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h47: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h48: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h49: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h4A: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h4B: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h4C: begin d0 <= BS; d1 <= VB_NVS; end
8'h4D: begin d0 <= MVID; d1 <= MAUD; end
8'h4E: begin d0 <= VB_NVS; d1 <= MVID; end
8'h4F: begin d0 <= MAUD; d1 <= VB_NVS; end
8'h50: begin d0 <= MVID; d1 <= MAUD; end
8'h51: begin d0 <= VB_NVS; d1 <= MVID; end
8'h52: begin d0 <= MAUD; d1 <= DUMMY; end
8'h53: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h54: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h55: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h56: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h57: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h58: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h59: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h5A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h5B: begin d0 <= SPARE; d1 <= SPARE; end
8'h5C: begin d0 <= SPARE; d1 <= SPARE; end
8'h5D: begin d0 <= SPARE; d1 <= SPARE; end
8'h5E: begin d0 <= SPARE; d1 <= SPARE; end
8'h5F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 3 - 8 white pixels and padding; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h60: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h61: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h62: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h63: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h64: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h65: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h66: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h67: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h68: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h69: begin d0 <= PIX_00; d1 <= PIX_01; end
8'h6A: begin d0 <= PIX_02; d1 <= PIX_10; end
8'h6B: begin d0 <= PIX_11; d1 <= PIX_12; end
8'h6C: begin d0 <= BS; d1 <= VB_VS; end
8'h6D: begin d0 <= MVID; d1 <= MAUD; end
8'h6E: begin d0 <= VB_VS; d1 <= MVID; end
8'h6F: begin d0 <= MAUD; d1 <= VB_VS; end
8'h70: begin d0 <= MVID; d1 <= MAUD; end
8'h71: begin d0 <= VB_VS; d1 <= MVID; end
8'h72: begin d0 <= MAUD; d1 <= DUMMY; end
8'h73: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h74: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h75: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h76: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h77: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h78: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h79: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7B: begin d0 <= SPARE; d1 <= SPARE; end
8'h7C: begin d0 <= SPARE; d1 <= SPARE; end
8'h7D: begin d0 <= SPARE; d1 <= SPARE; end
8'h7E: begin d0 <= SPARE; d1 <= SPARE; end
8'h7F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 4 - DUMMY;Blank Start; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h80: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h81: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h82: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h83: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h84: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h85: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h86: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h87: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h88: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h89: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8B: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8C: begin d0 <= BS; d1 <= VB_VS; end
8'h8D: begin d0 <= MVID; d1 <= MAUD; end
8'h8E: begin d0 <= VB_VS; d1 <= MVID; end
8'h8F: begin d0 <= MAUD; d1 <= VB_VS; end
8'h90: begin d0 <= MVID; d1 <= MAUD; end
8'h91: begin d0 <= VB_VS; d1 <= MVID; end
8'h92: begin d0 <= MAUD; d1 <= DUMMY; end
8'h93: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h94: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h95: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h96: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h97: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h98: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h99: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h9A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h9B: begin d0 <= SPARE; d1 <= SPARE; end
8'h9C: begin d0 <= SPARE; d1 <= SPARE; end
8'h9D: begin d0 <= SPARE; d1 <= SPARE; end
8'h9E: begin d0 <= SPARE; d1 <= SPARE; end
8'h9F: begin d0 <= SPARE; d1 <= SPARE; end
// Block 5 - just blank end
8'hA0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAA: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAB: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAC: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAD: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAE: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAF: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hBA: begin d0 <= DUMMY; d1 <= BE; end
8'hBB: begin d0 <= SPARE; d1 <= SPARE; end
8'hBC: begin d0 <= SPARE; d1 <= SPARE; end
8'hBD: begin d0 <= SPARE; d1 <= SPARE; end
8'hBE: begin d0 <= SPARE; d1 <= SPARE; end
8'hBF: begin d0 <= SPARE; d1 <= SPARE; end
endcase
if(index[4:0] == 5'd26) begin
index[4:0] <= 5'd0;
if(row_count == 131) begin
row_count <= 8'b0;
if(line_count == 627) begin
line_count <= 10'b0;
end else begin
line_count <= line_count + 1;
end
end else begin
row_count <= row_count +1;
end
// Block 0 - Junk
// Block 1- 8 white pixels and padding
// Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
// Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
// Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
// Block 5 - just blank end
index[7:5] <= 3'b000; // Dummy symbols
switch_point <= 1'b0;
if(line_count < 599) begin //-- lines of active video (except first and last)
if (row_count < 1) index[7:5] <= 3'b101; // Just blank end BE
else if(row_count < 100) index[7:5] <= 3'b001; // Pixels plus fill
else if(row_count == 100) index[7:5] <= 3'b010; // Pixels BS and VS-ID block (no VBLANK flag)
end else if(line_count == 599) begin // Last line of active video
if(row_count < 1) begin
index[7:5] <= 3'b101; // Just blank end BE
end else if(row_count < 100) begin
index[7:5] <= 3'b001; // Pixels plus fill
end else if(row_count == 100) begin
index[7:5] <= 3'b011; // Pixels BS and VS-ID block (with VBLANK flag)
end
end else begin
//---------------------------------------------------------------
// Allow switching to/from the idle pattern during the vertical blank
//---------------------------------------------------------------
if(row_count < 100) begin
switch_point <= 1'b1;
end else if(row_count == 100) begin
index[7:5] <= 3'b100; // Dummy symbols, BS and VS-ID block (with VBLANK flag)
end
end
end else begin
index <= index + 1;
end
end
endmodule |
module test_source_720p_RGB_444_colourbar(
output reg [23:0] M_value,
output reg [23:0] N_value,
output reg [11:0] H_visible,
output reg [11:0] V_visible,
output reg [11:0] H_total,
output reg [11:0] V_total,
output reg [11:0] H_sync_width,
output reg [11:0] V_sync_width,
output reg [11:0] H_start,
output reg [11:0] V_start,
output reg H_vsync_active_high,
output reg V_vsync_active_high,
output reg flag_sync_clock,
output reg flag_YCCnRGB,
output reg flag_422n444,
output reg flag_YCC_colour_709,
output reg flag_range_reduced,
output reg flag_interlaced_even,
output reg [1:0] flags_3d_Indicators,
output reg [4:0] bits_per_colour,
output reg [2:0] stream_channel_count,
input clk,
output reg ready,
output reg [72:0] data
);
/////////////////////////////////////////////////////
//
// Transfer Units (TUs) are 0 to 19 pairs of symbols
// Making them 40 symbols long. Each normal TU transfers
// 11 pixels, making the pixel clock 11/40ths of the
// symbol rate. The symbol rate is 270M Symbols/s.
//
// So pixel clock is 11/40*270 = 74.25M pixels/sec
/////////////////////////////////////////////////////
localparam [8:0] DUMMY = 9'b000000000; // 0x03
localparam [8:0] SPARE = 9'b011111111; // 0xFF
localparam [8:0] ZERO = 9'b000000000; // 0x00
localparam [8:0] PIX_0 = 9'b010000000; // Byte 0 of pixel 0
localparam [8:0] PIX_1 = 9'b010000001; // Byte 1 of pixel 0
localparam [8:0] PIX_2 = 9'b010000010; // Byte 2 of pixel 0
localparam [8:0] BE = 9'b111111011; // K27.7 Blank End
localparam [8:0] BS = 9'b110111100; // K28.5 Blank Start
localparam [8:0] FS = 9'b111111110; // K30.7 Fill Start
localparam [8:0] FE = 9'b111110111; // K23.7 Fill End
localparam [8:0] VB_VS = 9'b000000001; // 0x00 VB-ID with Vertical blank asserted
localparam [8:0] VB_NVS = 9'b000000000; // 0x00 VB-ID without Vertical blank asserted
localparam [8:0] MVID = 9'b001101000; // 0x68
localparam [8:0] MAUD = 9'b000000000; // 0x00
reg [7:0] index = 0;
reg [8:0] d0 = 0;
reg [8:0] d1 = 0;
reg [9:0] line_count = 0;
reg [7:0] row_count = 0;
reg switch_point = 0;
reg [47:0] pixels_next;
reg new_next;
reg [18:0] pixel_count;
reg [23:0] pixel;
reg [23:0] pixel_next;
reg switch_point_last;
initial begin
M_value = 24'h023333;
N_value = 24'h080000;
H_visible = 12'd1280;
H_total = 12'd1650;
H_start = 12'd260; // Pulse width (40) + pack porch (220)
H_sync_width = 12'd40;
V_visible = 12'd720;
V_total = 12'd750;
V_start = 12'd25;
V_sync_width = 12'd5;
H_vsync_active_high = 1'b0;
V_vsync_active_high = 1'b0;
flag_sync_clock = 1'b1;
flag_YCCnRGB = 1'b0;
flag_422n444 = 1'b0;
flag_range_reduced = 1'b0;
flag_interlaced_even = 1'b0;
flag_YCC_colour_709 = 1'b0;
flags_3d_Indicators = 2'b00;
bits_per_colour = 5'b01000;
stream_channel_count = 3'b001;
ready = 1'b1;
data = 73'b0;
pixel_count = 19'b0;
switch_point_last = 1'b0;
end
always @(posedge clk) begin
//////////////////////////////////
// Pixel value generation
//////////////////////////////////
/////////////////////////////////////////////
// Detect the start of frame to reset counter
/////////////////////////////////////////////
if(switch_point_last == 1'b0 && switch_point == 1'b1) begin
pixel_count <= 19'b0;
end
////////////////////////////////////////////////////
// Advance the counter when last byte of pixel is used
////////////////////////////////////////////////////
if (pixel_count < 183*1) begin pixel[23:0] = 24'hCCCCCC; end
else if(pixel_count < 183*2) begin pixel[23:0] = 24'h00CCCC; end
else if(pixel_count < 183*3) begin pixel[23:0] = 24'hCCCC00; end
else if(pixel_count < 183*4) begin pixel[23:0] = 24'h00CC00; end
else if(pixel_count < 183*5) begin pixel[23:0] = 24'hCC00CC; end
else if(pixel_count < 183*6) begin pixel[23:0] = 24'h0000CC; end
else begin pixel[23:0] = 24'hCC0000; end
if (pixel_count < 183*1-1) begin pixel_next[23:0] = 24'hfCCCCC; end
else if(pixel_count < 183*2-1) begin pixel_next[23:0] = 24'h00CCCC; end
else if(pixel_count < 183*3-1) begin pixel_next[23:0] = 24'hCCCC00; end
else if(pixel_count < 183*4-1) begin pixel_next[23:0] = 24'h00CC00; end
else if(pixel_count < 183*5-1) begin pixel_next[23:0] = 24'hCC00CC; end
else if(pixel_count < 183*6-1) begin pixel_next[23:0] = 24'h0000CC; end
else begin pixel_next[23:0] = 24'hCC0000; end
if(d0 == PIX_2 || d1 == PIX_2) begin
if(pixel_count == 1279) begin
pixel_count <= 19'b0;
end else begin
pixel_count <= pixel_count + 1;
end
end
switch_point_last <= switch_point;
///////////////////////////////////////////////
// Scheduling the data out to the pipeline
///////////////////////////////////////////////
///////////////////////////////////////////////
// Stage 1 of video pipeline
//
// Replace the sentinel values with pixel data
///////////////////////////////////////////////
case(d1)
// Data from pixel 0
PIX_0: begin data[17:9] <= {1'b0, pixel_next[7:0]}; end
PIX_1: begin data[17:9] <= {1'b0, pixel[15:8]}; end
PIX_2: begin data[17:9] <= {1'b0, pixel[23:16]}; end
default: data[17:9] <= d1;
endcase
case(d0)
PIX_0: begin data[8:0] <= {1'b0, pixel[7:0]}; end
PIX_1: begin data[8:0] <= {1'b0, pixel[15:8]}; end
PIX_2: begin data[8:0] <= {1'b0, pixel[23:16]}; end
default: data[8:0] <= d0;
endcase
data[71:18] <= 54'b0;
data[72] <= switch_point;
///////////////////////////////////////////////
// Stage 0 of pipeline
//
// Lookup what type of values to send
///////////////////////////////////////////////
// Now load the next byte of the sequence into d0 and d1
case(index)
8'h00: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h01: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h02: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h03: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h04: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h05: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h06: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h07: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h08: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h09: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0A: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0B: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0C: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h0F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h10: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h11: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h12: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h13: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 1 - 11 white pixels and padding
8'h20: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h21: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h22: begin d0 <= PIX_1; d1 <= PIX_2; end
8'h23: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h24: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h25: begin d0 <= PIX_1; d1 <= PIX_2; end
8'h26: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h27: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h28: begin d0 <= PIX_1; d1 <= PIX_2; end
8'h29: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h2A: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h2B: begin d0 <= PIX_1; d1 <= PIX_2; end // 8 pixels
8'h2C: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h2D: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h2E: begin d0 <= PIX_1; d1 <= PIX_2; end // 2 more pixels
8'h2F: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h30: begin d0 <= PIX_2; d1 <= FS; end // 1 more pixel
8'h31: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h32: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h33: begin d0 <= DUMMY; d1 <= FE; end
// Block 2 - 4 white pixels and padding; d1 <= VB-ID (-vsync); d1 <= Mvid; d1 <= MAud and junk
8'h40: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h41: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h42: begin d0 <= PIX_1; d1 <= PIX_2; end
8'h43: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h44: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h45: begin d0 <= PIX_1; d1 <= PIX_2; end // Four pixels
8'h46: begin d0 <= BS; d1 <= VB_NVS; end
8'h47: begin d0 <= MVID; d1 <= MAUD; end
8'h48: begin d0 <= VB_NVS; d1 <= MVID; end
8'h49: begin d0 <= MAUD; d1 <= VB_NVS; end
8'h4a: begin d0 <= MVID; d1 <= MAUD; end
8'h4b: begin d0 <= VB_NVS; d1 <= MVID; end
8'h4c: begin d0 <= MAUD; d1 <= DUMMY; end
8'h4d: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h4e: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h4f: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h50: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h51: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h52: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h53: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 3 - 4 white pixels and padding; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h60: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h61: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h62: begin d0 <= PIX_1; d1 <= PIX_2; end
8'h63: begin d0 <= PIX_0; d1 <= PIX_1; end
8'h64: begin d0 <= PIX_2; d1 <= PIX_0; end
8'h65: begin d0 <= PIX_1; d1 <= PIX_2; end // Four pixels
8'h66: begin d0 <= BS; d1 <= VB_VS; end
8'h67: begin d0 <= MVID; d1 <= MAUD; end
8'h68: begin d0 <= VB_VS; d1 <= MVID; end
8'h69: begin d0 <= MAUD; d1 <= VB_VS; end
8'h7A: begin d0 <= MVID; d1 <= MAUD; end
8'h7B: begin d0 <= VB_VS; d1 <= MVID; end
8'h7C: begin d0 <= MAUD; d1 <= DUMMY; end
8'h7D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h7F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h80: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h81: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h82: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h83: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 4 - DUMMY;Blank Start; d1 <= VB-ID (+vsync); d1 <= Mvid; d1 <= MAud and junk
8'h80: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h81: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h82: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h83: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h84: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h85: begin d0 <= DUMMY; d1 <= DUMMY; end // Space for four (non-present pixels)
8'h86: begin d0 <= BS; d1 <= VB_VS; end
8'h87: begin d0 <= MVID; d1 <= MAUD; end
8'h88: begin d0 <= VB_VS; d1 <= MVID; end
8'h89: begin d0 <= MAUD; d1 <= VB_VS; end
8'h8A: begin d0 <= MVID; d1 <= MAUD; end
8'h8B: begin d0 <= VB_VS; d1 <= MVID; end
8'h8C: begin d0 <= MAUD; d1 <= DUMMY; end
8'h8D: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8E: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h8F: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h90: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h91: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h92: begin d0 <= DUMMY; d1 <= DUMMY; end
8'h93: begin d0 <= DUMMY; d1 <= DUMMY; end
// Block 5 - just blank end
8'hA0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA3: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA4: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA5: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA6: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA7: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA8: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hA9: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAA: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAB: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAC: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAD: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAE: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hAF: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB0: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB1: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB2: begin d0 <= DUMMY; d1 <= DUMMY; end
8'hB3: begin d0 <= DUMMY; d1 <= BE; end
default: begin d0 <= SPARE; d1 <= SPARE; end
endcase
if(index[4:0] == 5'd19) begin
index[4:0] <= 5'd0;
if(row_count == 149) begin // 1650 / 11 - 1
row_count <= 8'b0;
if(line_count == 749) begin
line_count <= 10'b0;
end else begin
line_count <= line_count + 1;
end
end else begin
row_count <= row_count +1;
end
// Block 0 - Junk
// Block 1 - 11 white pixels and padding
// Block 2 - 4 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
// Block 3 - 4 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
// Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
// Block 5 - just blank end
index[7:5] <= 3'b000; // Dummy symbols for the default block
switch_point <= 1'b0;
if(line_count < 719) begin //-- lines of active video (except first and last)
if(row_count < 1) begin
index[7:5] <= 3'b101; // Just blank ending in BE
end else if(row_count < 117) begin
index[7:5] <= 3'b001; // Pixels plus fill
end else if(row_count == 117) begin
index[7:5] <= 3'b010; // Pixels BS and VS-ID block (no VBLANK flag)
end
end else if(line_count == 719) begin // Last line of active video
if(row_count < 1) begin
index[7:5] <= 3'b101; // Just blank ending in BE
end else if(row_count < 117) begin
index[7:5] <= 3'b001; // Pixels plus fill
end else if(row_count == 117) begin
index[7:5] <= 3'b011; // Pixels BS and VS-ID block (with VBLANK flag)
end
end else begin
//---------------------------------------------------------------
// Allow switching to/from the idle pattern during the vertical blank
//---------------------------------------------------------------
if(row_count < 117) begin
switch_point <= 1'b1;
end else if(row_count == 117) begin
index[7:5] <= 3'b100; // Dummy symbols, BS and VS-ID block (with VBLANK flag)
end
end
end else begin
index <= index + 1;
end
end
endmodule |
module test_source(
input clk,
output [2:0] stream_channel_count,
output ready,
output reg [72:0] data
);
wire [23:0] M_value;
wire [23:0] N_value;
wire [11:0] H_visible;
wire [11:0] V_visible;
wire [11:0] H_total;
wire [11:0] V_total;
wire [11:0] H_sync_width;
wire [11:0] V_sync_width;
wire [11:0] H_start;
wire [11:0] V_start;
wire H_vsync_active_high;
wire V_vsync_active_high;
wire flag_sync_clock;
wire flag_YCCnRGB;
wire flag_422n444;
wire flag_YCC_colour_709;
wire flag_range_reduced;
wire flag_interlaced_even;
wire [1:0] flags_3d_Indicators;
wire [4:0] bits_per_colour;
wire [72:0] raw_data;
wire [72:0] data_ch_1;
wire [72:0] data_ch_2;
wire [72:0] data_ch_4;
always @(*) begin
case(stream_channel_count)
3'b100: data <= data_ch_4;
3'b010: data <= data_ch_2;
default: data <= data_ch_1;
endcase
end
//test_source_800_600_RGB_444_colourbar i_test_source(
//test_source_1080p_RGB_444_gutted i_test_source(
//test_source_720p_RGB_444_colourbar i_test_source(
//test_source_800_600_RGB_444_ch2 i_test_source(
//test_source_1080p_RGB_444_colourbar i_test_source(
//test_source_1080p_RGB_444_colourbar i_test_source(
test_source_3840_2180_YCC_422_ch2 i_test_source(
.M_value (M_value),
.N_value (N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width (H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even (flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
.stream_channel_count (stream_channel_count),
.clk (clk),
.ready (ready),
.data (raw_data)
);
insert_main_stream_attrbutes_one_channel i_insert_main_stream_attrbutes_one_channel(
.clk (clk),
.active (1'b1),
//////////////////////////////////////////////////////
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//////////////////////////////////////////////////////
.M_value (M_value),
.N_value (N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width (H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even (flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
//////////////////////////////////////////////////////
// The stream of pixel data coming in
//////////////////////////////////////////////////////
.in_data (raw_data),
//////////////////////////////////////////////////////
// The stream of pixel data going out
//////////////////////////////////////////////////////
.out_data (data_ch_1)
);
insert_main_stream_attrbutes_two_channels i_insert_main_stream_attrbutes_two_channels(
.clk (clk),
.active (1'b1),
//////////////////////////////////////////////////////
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//////////////////////////////////////////////////////
.M_value (M_value),
.N_value (N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width (H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even (flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
//////////////////////////////////////////////////////
// The stream of pixel data coming in
//////////////////////////////////////////////////////
.in_data (raw_data),
//////////////////////////////////////////////////////
// The stream of pixel data going out
//////////////////////////////////////////////////////
.out_data (data_ch_2)
);
insert_main_stream_attrbutes_four_channels i_insert_main_stream_attrbutes_four_channels(
.clk (clk),
.active (1'b1),
//////////////////////////////////////////////////////
// The MSA values (some are range reduced and could
// be 16 bits ins size)
//////////////////////////////////////////////////////
.M_value (M_value),
.N_value (N_value),
.H_visible (H_visible),
.H_total (H_total),
.H_sync_width (H_sync_width),
.H_start (H_start),
.V_visible (V_visible),
.V_total (V_total),
.V_sync_width (V_sync_width),
.V_start (V_start),
.H_vsync_active_high (H_vsync_active_high),
.V_vsync_active_high (V_vsync_active_high),
.flag_sync_clock (flag_sync_clock),
.flag_YCCnRGB (flag_YCCnRGB),
.flag_422n444 (flag_422n444),
.flag_range_reduced (flag_range_reduced),
.flag_interlaced_even (flag_interlaced_even),
.flag_YCC_colour_709 (flag_YCC_colour_709),
.flags_3d_Indicators (flags_3d_Indicators),
.bits_per_colour (bits_per_colour),
//////////////////////////////////////////////////////
// The stream of pixel data coming in
//////////////////////////////////////////////////////
.in_data (raw_data),
//////////////////////////////////////////////////////
// The stream of pixel data going out
//////////////////////////////////////////////////////
.out_data (data_ch_4)
);
endmodule |
module merge_colourbars(
input clk,
input [72:0] data_in,
output reg [72:0] data_out
);
localparam [8:0] PIX = 9'b011001100;
localparam [8:0] BE = 9'b111111011; // K27.7 Blank End
localparam [8:0] BS = 9'b110111100; // K28.5 Blank Start
reg [11:0] pixel_count;
reg [23:0] ch0_pixel;
reg [23:0] ch0_pixel_next;
reg [23:0] ch1_pixel;
reg [23:0] ch1_pixel_next;
reg [1:0] r_g_b;
initial begin
pixel_count = 12'b0;
r_g_b = 2'b00;
end
always @(posedge clk) begin
//////////////////////////////////
// Pixel value generation
//////////////////////////////////
////////////////////////////////////////////////////
// Advance the counter when last byte of pixel is used
////////////////////////////////////////////////////
if (pixel_count < 274*1) begin ch0_pixel[23:0] = 24'hCCCCCC; end
else if(pixel_count < 274*2) begin ch0_pixel[23:0] = 24'h00CCCC; end
else if(pixel_count < 274*3) begin ch0_pixel[23:0] = 24'hCCCC00; end
else if(pixel_count < 274*4) begin ch0_pixel[23:0] = 24'h00CC00; end
else if(pixel_count < 274*5) begin ch0_pixel[23:0] = 24'hCC00CC; end
else if(pixel_count < 274*6) begin ch0_pixel[23:0] = 24'h0000CC; end
else begin ch0_pixel[23:0] = 24'hCC0000; end
if (pixel_count < 274*1-1) begin ch1_pixel[23:0] = 24'hCCCCCC; end
else if(pixel_count < 274*2-1) begin ch1_pixel[23:0] = 24'h00CCCC; end
else if(pixel_count < 274*3-1) begin ch1_pixel[23:0] = 24'hCCCC00; end
else if(pixel_count < 274*4-1) begin ch1_pixel[23:0] = 24'h00CC00; end
else if(pixel_count < 274*5-1) begin ch1_pixel[23:0] = 24'hCC00CC; end
else if(pixel_count < 274*6-1) begin ch1_pixel[23:0] = 24'h0000CC; end
else begin ch1_pixel[23:0] = 24'hCC0000; end
if (pixel_count < 274*1-2) begin ch0_pixel_next[23:0] = 24'hfCCCCC; end
else if(pixel_count < 274*2-2) begin ch0_pixel_next[23:0] = 24'h00CCCC; end
else if(pixel_count < 274*3-2) begin ch0_pixel_next[23:0] = 24'hCCCC00; end
else if(pixel_count < 274*4-2) begin ch0_pixel_next[23:0] = 24'h00CC00; end
else if(pixel_count < 274*5-2) begin ch0_pixel_next[23:0] = 24'hCC00CC; end
else if(pixel_count < 274*6-2) begin ch0_pixel_next[23:0] = 24'h0000CC; end
else begin ch0_pixel_next[23:0] = 24'hCC0000; end
if (pixel_count < 274*1-3) begin ch1_pixel_next[23:0] = 24'hfCCCCC; end
else if(pixel_count < 274*2-3) begin ch1_pixel_next[23:0] = 24'h00CCCC; end
else if(pixel_count < 274*3-3) begin ch1_pixel_next[23:0] = 24'hCCCC00; end
else if(pixel_count < 274*4-3) begin ch1_pixel_next[23:0] = 24'h00CC00; end
else if(pixel_count < 274*5-3) begin ch1_pixel_next[23:0] = 24'hCC00CC; end
else if(pixel_count < 274*6-3) begin ch1_pixel_next[23:0] = 24'h0000CC; end
else begin ch1_pixel_next[23:0] = 24'hCC0000; end
///////////////////////////////////////////////
// Scheduling the data out to the pipeline
///////////////////////////////////////////////
data_out <= data_in;
///////////////////////////////////////////////
// Replace the sentinel values with pixel data
///////////////////////////////////////////////
if(data_in[17:9] == PIX && data_in[8:0] == PIX) begin
case(r_g_b)
2'b00: begin
r_g_b = 2'b10;
data_out[7:0] <= ch0_pixel[7:0];
data_out[25:18] <= ch1_pixel[7:0];
data_out[16:9] <= ch0_pixel[15:8];
data_out[34:27] <= ch1_pixel[15:8];
end
2'b01: begin
r_g_b = 2'b00;
pixel_count = pixel_count + 2;
data_out[7:0] <= ch0_pixel[15:8];
data_out[25:18] <= ch1_pixel[15:8];
data_out[16:9] <= ch0_pixel[23:16];
data_out[34:27] <= ch1_pixel[23:16];
ch0_pixel <= ch0_pixel_next;
ch1_pixel <= ch1_pixel_next;
end
default: begin
r_g_b = 2'b01;
pixel_count = pixel_count + 2;
data_out[7:0] <= ch0_pixel[23:16];
data_out[25:18] <= ch1_pixel[23:16];
data_out[16:9] <= ch0_pixel_next[7:0];
data_out[34:27] <= ch1_pixel_next[7:0];
ch0_pixel <= ch0_pixel_next;
ch1_pixel <= ch1_pixel_next;
end
endcase
end else if(data_in[17:9] == PIX) begin
case(r_g_b)
2'b00: begin
r_g_b = 2'b01;
data_out[17:9] <= ch0_pixel[7:0];
data_out[35:27] <= ch1_pixel[7:0];
end
2'b01: begin
r_g_b = 2'b10;
data_out[17:9] <= ch0_pixel[15:8];
data_out[35:27] <= ch1_pixel[15:8];
end
default: begin
r_g_b = 2'b00;
pixel_count = pixel_count + 2;
data_out[17:9] <= ch0_pixel[23:16];
data_out[35:27] <= ch1_pixel[23:16];
ch0_pixel <= ch0_pixel_next;
ch1_pixel <= ch1_pixel_next;
end
endcase
end else if(data_in[8:0] == PIX) begin
case(r_g_b)
2'b00: begin
r_g_b = 2'b01;
data_out[8:0] <= ch0_pixel[7:0];
data_out[26:18] <= ch1_pixel[7:0];
end
2'b01: begin
r_g_b = 2'b10;
data_out[8:0] <= ch0_pixel[15:8];
data_out[26:18] <= ch1_pixel[15:8];
end
default: begin
r_g_b = 2'b00;
pixel_count = pixel_count + 2;
data_out[8:0] <= ch0_pixel[23:16];
data_out[26:18] <= ch1_pixel[23:16];
ch0_pixel <= ch0_pixel_next;
ch1_pixel <= ch1_pixel_next;
end
endcase
end
if(data_in[17:9] == BS || data_in[8:0] == BS) begin
pixel_count = 12'b0;
end
end
endmodule |
module four_bit_4(SIM_RST, SIM_CLK, p4VSW, GND, A2XG_n, CAG, CBG, CGG, CLG1G, CLG2G, CLXC, CQG, CUG, CZG, L2GDG_n, RAG_n, RCG_n, RGG_n, RLG_n, RQG_n, RZG_n, WAG_n, WALSG_n, WBG_n, WLG_n, WQG_n, WZG_n, CI13_n, CO14, BXVX, MONEX, XUY01_n, XUY02_n, CH13, CH14, CH16, L12_n, L16_n, G2LSG_n, WL01_n, WL02_n, G01_n, MDT13, MDT14, MDT15, MDT16, SA13, SA14, SA16, RBHG_n, RULOG_n, RUG_n, G16SW_n, WG1G_n, WG2G_n, WG3G_n, WG4G_n, WG5G_n, WYDG_n, WYHIG_n, R1C, US2SG, WL12_n, WHOMPA, Z15_n, Z16_n, A15_n, A16_n, EAC_n, G13, G13_n, G14, G14_n, G15, G15_n, G16, L15_n, RL13_n, RL14_n, RL15_n, RL16_n, SUMA13_n, SUMB13_n, SUMA14_n, SUMB14_n, SUMA15_n, SUMB15_n, SUMA16_n, SUMB16_n, WL13, WL13_n, WL14, WL14_n, WL15, WL15_n, WL16, WL16_n, XUY13_n, XUY14_n, GEM13, GEM14, GEM16, MWL13, MWL14, MWL15, MWL16);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
output wire A15_n;
output wire A16_n;
input wire A2XG_n;
input wire BXVX;
input wire CAG;
input wire CBG;
input wire CGG;
input wire CH13;
input wire CH14;
input wire CH16;
input wire CI13_n;
input wire CLG1G;
input wire CLG2G;
input wire CLXC;
input wire CO14;
input wire CQG;
input wire CUG;
input wire CZG;
output wire EAC_n;
input wire G01_n;
output wire G13;
inout wire G13_n; //FPGA#wand
output wire G14;
inout wire G14_n; //FPGA#wand
output wire G15;
inout wire G15_n; //FPGA#wand
output wire G16;
input wire G16SW_n;
input wire G2LSG_n;
output wire GEM13;
output wire GEM14;
output wire GEM16;
input wire L12_n;
inout wire L15_n; //FPGA#wand
inout wire L16_n; //FPGA#wand
input wire L2GDG_n;
input wire MDT13;
input wire MDT14;
input wire MDT15;
input wire MDT16;
input wire MONEX;
output wire MWL13; //FPGA#wand
output wire MWL14; //FPGA#wand
output wire MWL15; //FPGA#wand
output wire MWL16; //FPGA#wand
input wire R1C;
input wire RAG_n;
input wire RBHG_n;
input wire RCG_n;
input wire RGG_n;
inout wire RL13_n; //FPGA#wand
inout wire RL14_n; //FPGA#wand
inout wire RL15_n; //FPGA#wand
inout wire RL16_n; //FPGA#wand
input wire RLG_n;
input wire RQG_n;
input wire RUG_n;
input wire RULOG_n;
input wire RZG_n;
input wire SA13;
input wire SA14;
input wire SA16;
output wire SUMA13_n;
output wire SUMA14_n;
output wire SUMA15_n;
output wire SUMA16_n;
output wire SUMB13_n;
output wire SUMB14_n;
output wire SUMB15_n;
output wire SUMB16_n;
input wire US2SG;
input wire WAG_n;
input wire WALSG_n;
input wire WBG_n;
input wire WG1G_n;
input wire WG2G_n;
input wire WG3G_n;
input wire WG4G_n;
input wire WG5G_n;
input wire WHOMPA;
input wire WL01_n;
input wire WL02_n;
input wire WL12_n;
output wire WL13;
output wire WL13_n;
output wire WL14;
output wire WL14_n;
output wire WL15;
output wire WL15_n;
output wire WL16;
output wire WL16_n;
input wire WLG_n;
input wire WQG_n;
input wire WYDG_n;
input wire WYHIG_n;
input wire WZG_n;
input wire XUY01_n;
input wire XUY02_n;
output wire XUY13_n;
output wire XUY14_n;
inout wire Z15_n; //FPGA#wand
inout wire Z16_n; //FPGA#wand
wire __A11_1__X1;
wire __A11_1__X1_n;
wire __A11_1__X2;
wire __A11_1__X2_n;
wire __A11_1__Y1;
wire __A11_1__Y1_n;
wire __A11_1__Y2;
wire __A11_1__Y2_n;
wire __A11_1___A1_n;
wire __A11_1___A2_n;
wire __A11_1___B1_n;
wire __A11_1___B2_n;
wire __A11_1___CI_INTERNAL;
wire __A11_1___Q1_n;
wire __A11_1___Q2_n;
wire __A11_1___RL_OUT_1;
wire __A11_1___RL_OUT_2;
wire __A11_1___Z1_n; //FPGA#wand
wire __A11_1___Z2_n; //FPGA#wand
wire __A11_2__X1;
wire __A11_2__X1_n;
wire __A11_2__X2;
wire __A11_2__X2_n;
wire __A11_2__Y1;
wire __A11_2__Y1_n;
wire __A11_2__Y2;
wire __A11_2__Y2_n;
wire __A11_2___B1_n;
wire __A11_2___B2_n;
wire __A11_2___CI_INTERNAL;
wire __A11_2___CO_OUT; //FPGA#wand
wire __A11_2___GEM1;
wire __A11_2___Q1_n;
wire __A11_2___Q2_n;
wire __A11_2___RL_OUT_1;
wire __CI15_n;
wire __CO16; //FPGA#wand
wire __G16_n; //FPGA#wand
wire __L13_n; //FPGA#wand
wire __L14_n; //FPGA#wand
wire __RL16;
wire __XUY15_n;
wire __XUY16_n;
wire net_U11001_Pad1;
wire net_U11001_Pad10;
wire net_U11001_Pad4;
wire net_U11003_Pad1;
wire net_U11003_Pad10;
wire net_U11004_Pad1;
wire net_U11004_Pad12;
wire net_U11004_Pad13;
wire net_U11004_Pad2;
wire net_U11004_Pad6;
wire net_U11004_Pad8;
wire net_U11005_Pad12;
wire net_U11005_Pad2;
wire net_U11006_Pad10;
wire net_U11006_Pad13;
wire net_U11006_Pad4;
wire net_U11007_Pad11;
wire net_U11007_Pad13;
wire net_U11007_Pad3;
wire net_U11007_Pad5;
wire net_U11007_Pad9;
wire net_U11008_Pad1;
wire net_U11008_Pad10;
wire net_U11008_Pad13;
wire net_U11008_Pad4;
wire net_U11009_Pad1;
wire net_U11009_Pad13;
wire net_U11009_Pad4;
wire net_U11010_Pad1;
wire net_U11010_Pad13;
wire net_U11010_Pad4;
wire net_U11011_Pad10;
wire net_U11011_Pad11;
wire net_U11011_Pad13;
wire net_U11011_Pad8;
wire net_U11011_Pad9;
wire net_U11012_Pad13;
wire net_U11012_Pad4;
wire net_U11013_Pad1;
wire net_U11013_Pad11;
wire net_U11013_Pad13;
wire net_U11013_Pad5;
wire net_U11013_Pad9;
wire net_U11014_Pad10;
wire net_U11014_Pad13;
wire net_U11016_Pad1;
wire net_U11016_Pad4;
wire net_U11018_Pad11;
wire net_U11018_Pad12;
wire net_U11018_Pad13;
wire net_U11019_Pad1;
wire net_U11019_Pad10;
wire net_U11019_Pad4;
wire net_U11021_Pad1;
wire net_U11021_Pad13;
wire net_U11022_Pad1;
wire net_U11022_Pad12;
wire net_U11022_Pad8;
wire net_U11023_Pad10;
wire net_U11023_Pad13;
wire net_U11023_Pad4;
wire net_U11024_Pad10;
wire net_U11024_Pad11;
wire net_U11024_Pad4;
wire net_U11024_Pad9;
wire net_U11026_Pad4;
wire net_U11026_Pad5;
wire net_U11026_Pad6;
wire net_U11026_Pad8;
wire net_U11027_Pad1;
wire net_U11027_Pad10;
wire net_U11028_Pad13;
wire net_U11028_Pad3;
wire net_U11028_Pad9;
wire net_U11029_Pad1;
wire net_U11029_Pad10;
wire net_U11030_Pad1;
wire net_U11030_Pad10;
wire net_U11030_Pad13;
wire net_U11031_Pad13;
wire net_U11031_Pad2;
wire net_U11031_Pad3;
wire net_U11031_Pad4;
wire net_U11031_Pad8;
wire net_U11035_Pad1;
wire net_U11035_Pad10;
wire net_U11035_Pad4;
wire net_U11037_Pad1;
wire net_U11037_Pad10;
wire net_U11038_Pad1;
wire net_U11038_Pad12;
wire net_U11038_Pad2;
wire net_U11038_Pad6;
wire net_U11038_Pad8;
wire net_U11039_Pad12;
wire net_U11039_Pad2;
wire net_U11040_Pad10;
wire net_U11040_Pad13;
wire net_U11040_Pad4;
wire net_U11041_Pad11;
wire net_U11041_Pad13;
wire net_U11041_Pad3;
wire net_U11041_Pad5;
wire net_U11041_Pad9;
wire net_U11042_Pad10;
wire net_U11042_Pad11;
wire net_U11042_Pad4;
wire net_U11042_Pad9;
wire net_U11044_Pad1;
wire net_U11044_Pad6;
wire net_U11045_Pad13;
wire net_U11045_Pad4;
wire net_U11046_Pad1;
wire net_U11046_Pad13;
wire net_U11046_Pad4;
wire net_U11047_Pad1;
wire net_U11047_Pad13;
wire net_U11047_Pad4;
wire net_U11048_Pad1;
wire net_U11048_Pad10;
wire net_U11048_Pad13;
wire net_U11048_Pad4;
wire net_U11049_Pad11;
wire net_U11049_Pad8;
wire net_U11050_Pad11;
wire net_U11050_Pad13;
wire net_U11050_Pad5;
wire net_U11052_Pad11;
wire net_U11052_Pad12;
wire net_U11052_Pad13;
wire net_U11053_Pad1;
wire net_U11053_Pad10;
wire net_U11053_Pad4;
wire net_U11055_Pad13;
wire net_U11056_Pad10;
wire net_U11056_Pad13;
wire net_U11056_Pad4;
wire net_U11057_Pad10;
wire net_U11057_Pad11;
wire net_U11057_Pad4;
wire net_U11057_Pad9;
wire net_U11059_Pad4;
wire net_U11059_Pad5;
wire net_U11059_Pad6;
wire net_U11059_Pad8;
wire net_U11060_Pad1;
wire net_U11060_Pad10;
wire net_U11061_Pad3;
wire net_U11062_Pad1;
wire net_U11062_Pad10;
wire net_U11063_Pad1;
wire net_U11063_Pad10;
pullup R11001(__CO16);
pullup R11002(RL13_n);
pullup R11003(__L13_n);
pullup R11005(__A11_1___Z1_n);
pullup R11006(G13_n);
pullup R11007(RL14_n);
pullup R11008(__L14_n);
pullup R11009(__A11_1___Z2_n);
pullup R11010(G14_n);
pullup R11011(__A11_2___CO_OUT);
pullup R11012(RL15_n);
pullup R11013(L15_n);
pullup R11015(Z15_n);
pullup R11016(G15_n);
pullup R11017(RL16_n);
pullup R11018(L16_n);
pullup R11019(Z16_n);
pullup R11020(__G16_n);
U74HC02 U11001(net_U11001_Pad1, A2XG_n, __A11_1___A1_n, net_U11001_Pad4, WYHIG_n, WL13_n, GND, WL12_n, WYDG_n, net_U11001_Pad10, __A11_1__Y1_n, CUG, __A11_1__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11002(MONEX, net_U11001_Pad1, __A11_1__X1_n, CLXC, CUG, __A11_1__X1, GND, __A11_1__Y1_n, net_U11001_Pad4, net_U11001_Pad10, __A11_1__Y1, __A11_1__X1_n, __A11_1__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11003(net_U11003_Pad1, __A11_1__X1_n, __A11_1__Y1_n, XUY13_n, __A11_1__X1, __A11_1__Y1, GND, net_U11003_Pad1, XUY13_n, net_U11003_Pad10, net_U11003_Pad1, SUMA13_n, __A11_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11004(net_U11004_Pad1, net_U11004_Pad2, SUMA13_n, SUMB13_n, RULOG_n, net_U11004_Pad6, GND, net_U11004_Pad8, __XUY15_n, XUY13_n, CI13_n, net_U11004_Pad12, net_U11004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U11005(CI13_n, net_U11005_Pad2, G13_n, GEM13, RL13_n, WL13, GND, WL13_n, WL13, , , net_U11005_Pad12, __A11_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11006(SUMB13_n, net_U11003_Pad10, net_U11005_Pad2, net_U11006_Pad4, WAG_n, WL13_n, GND, WL15_n, WALSG_n, net_U11006_Pad10, __A11_1___A1_n, CAG, net_U11006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11007(net_U11004_Pad8, __CO16, net_U11007_Pad3, RL13_n, net_U11007_Pad5, __L13_n, GND, __A11_1___Z1_n, net_U11007_Pad9, RL13_n, net_U11007_Pad11, RL13_n, net_U11007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U11008(net_U11008_Pad1, RAG_n, __A11_1___A1_n, net_U11008_Pad4, WLG_n, WL13_n, GND, WL01_n, WALSG_n, net_U11008_Pad10, __L13_n, CLG2G, net_U11008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11009(net_U11009_Pad1, WG2G_n, WL16_n, net_U11009_Pad4, WQG_n, WL13_n, GND, net_U11009_Pad4, net_U11009_Pad13, __A11_1___Q1_n, __A11_1___Q1_n, CQG, net_U11009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11010(net_U11010_Pad1, RQG_n, __A11_1___Q1_n, net_U11010_Pad4, WZG_n, WL13_n, GND, net_U11010_Pad4, net_U11010_Pad13, net_U11007_Pad9, __A11_1___Z1_n, CZG, net_U11010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11011(__A11_1___RL_OUT_1, net_U11010_Pad1, MDT13, R1C, GND, net_U11007_Pad13, GND, net_U11011_Pad8, net_U11011_Pad9, net_U11011_Pad10, net_U11011_Pad11, net_U11007_Pad11, net_U11011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11012(net_U11011_Pad13, RZG_n, __A11_1___Z1_n, net_U11012_Pad4, WBG_n, WL13_n, GND, net_U11012_Pad4, net_U11012_Pad13, __A11_1___B1_n, __A11_1___B1_n, CBG, net_U11012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11013(net_U11013_Pad1, __CO16, net_U11011_Pad8, RL13_n, net_U11013_Pad5, G13_n, GND, G13_n, net_U11013_Pad9, RL14_n, net_U11013_Pad11, __L14_n, net_U11013_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U11014(net_U11011_Pad9, RBHG_n, __A11_1___B1_n, net_U11011_Pad10, net_U11012_Pad13, RCG_n, GND, WL12_n, WG3G_n, net_U11014_Pad10, WL14_n, WG4G_n, net_U11014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11015(net_U11006_Pad4, net_U11006_Pad10, net_U11004_Pad6, net_U11008_Pad1, CH13, net_U11007_Pad3, GND, net_U11007_Pad5, net_U11008_Pad4, net_U11008_Pad10, net_U11008_Pad13, __A11_1___A1_n, net_U11006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11016(net_U11016_Pad1, L2GDG_n, L12_n, net_U11016_Pad4, WG1G_n, WL13_n, GND, G13_n, CGG, G13, RGG_n, G13_n, net_U11011_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U11017(net_U11016_Pad1, net_U11016_Pad4, GND, __XUY16_n, XUY14_n, net_U11013_Pad1, GND, __A11_1___RL_OUT_1, RLG_n, __L13_n, GND, net_U11013_Pad9, G13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U11018(net_U11013_Pad5, GND, SA13, net_U11014_Pad10, net_U11014_Pad13, , GND, , GND, SA14, net_U11018_Pad11, net_U11018_Pad12, net_U11018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11019(net_U11019_Pad1, A2XG_n, __A11_1___A2_n, net_U11019_Pad4, WYHIG_n, WL14_n, GND, WL13_n, WYDG_n, net_U11019_Pad10, __A11_1__Y2_n, CUG, __A11_1__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11020(MONEX, net_U11019_Pad1, __A11_1__X2_n, CLXC, CUG, __A11_1__X2, GND, __A11_1__Y2_n, net_U11019_Pad4, net_U11019_Pad10, __A11_1__Y2, __A11_1__X2_n, __A11_1__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11021(net_U11021_Pad1, __A11_1__X2_n, __A11_1__Y2_n, XUY14_n, __A11_1__X2, __A11_1__Y2, GND, __G16_n, CGG, G16, net_U11021_Pad1, XUY14_n, net_U11021_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U11022(net_U11022_Pad1, net_U11009_Pad1, net_U11021_Pad1, SUMA14_n, CO14, __CI15_n, GND, net_U11022_Pad8, SUMA14_n, SUMB14_n, RULOG_n, net_U11022_Pad12, G16, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11023(SUMB14_n, net_U11021_Pad13, net_U11005_Pad12, net_U11023_Pad4, WAG_n, WL14_n, GND, WL16_n, WALSG_n, net_U11023_Pad10, __A11_1___A2_n, CAG, net_U11023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11024(net_U11023_Pad4, net_U11023_Pad10, net_U11022_Pad8, net_U11024_Pad4, CH14, net_U11013_Pad11, GND, net_U11013_Pad13, net_U11024_Pad9, net_U11024_Pad10, net_U11024_Pad11, __A11_1___A2_n, net_U11023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11025(net_U11024_Pad4, RAG_n, __A11_1___A2_n, net_U11024_Pad9, WLG_n, WL14_n, GND, WL02_n, WALSG_n, net_U11024_Pad10, __L14_n, CLG2G, net_U11024_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11026(RLG_n, __L14_n, __A11_1___RL_OUT_2, net_U11026_Pad4, net_U11026_Pad5, net_U11026_Pad6, GND, net_U11026_Pad8, MDT14, R1C, GND, __A11_1___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11027(net_U11027_Pad1, WQG_n, WL14_n, __A11_1___Q2_n, net_U11027_Pad1, net_U11027_Pad10, GND, __A11_1___Q2_n, CQG, net_U11027_Pad10, RQG_n, __A11_1___Q2_n, net_U11026_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11028(net_U11026_Pad6, RL14_n, net_U11028_Pad3, __A11_1___Z2_n, net_U11026_Pad8, RL14_n, GND, RL14_n, net_U11028_Pad9, G14_n, net_U11018_Pad13, G14_n, net_U11028_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11029(net_U11029_Pad1, WZG_n, WL14_n, net_U11028_Pad3, net_U11029_Pad1, net_U11029_Pad10, GND, __A11_1___Z2_n, CZG, net_U11029_Pad10, RZG_n, __A11_1___Z2_n, net_U11026_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11030(net_U11030_Pad1, WBG_n, WL14_n, __A11_1___B2_n, net_U11030_Pad1, net_U11030_Pad10, GND, __A11_1___B2_n, CBG, net_U11030_Pad10, RBHG_n, __A11_1___B2_n, net_U11030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U11031(net_U11030_Pad13, net_U11031_Pad2, net_U11031_Pad3, net_U11031_Pad4, G14, net_U11028_Pad13, GND, net_U11031_Pad8, GND, XUY02_n, __XUY16_n, net_U11028_Pad9, net_U11031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11032(net_U11031_Pad2, net_U11030_Pad10, RCG_n, net_U11018_Pad11, WL13_n, WG3G_n, GND, WL16_n, WG4G_n, net_U11018_Pad12, L2GDG_n, __L13_n, net_U11031_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11033(net_U11031_Pad4, WG1G_n, WL14_n, G14, G14_n, CGG, GND, RGG_n, G14_n, net_U11031_Pad13, RGG_n, __G16_n, net_U11004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U11034(G14_n, GEM14, RL14_n, WL14, WL14, WL14_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11035(net_U11035_Pad1, A2XG_n, A15_n, net_U11035_Pad4, WYHIG_n, WL15_n, GND, WL14_n, WYDG_n, net_U11035_Pad10, __A11_2__Y1_n, CUG, __A11_2__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11036(BXVX, net_U11035_Pad1, __A11_2__X1_n, CLXC, CUG, __A11_2__X1, GND, __A11_2__Y1_n, net_U11035_Pad4, net_U11035_Pad10, __A11_2__Y1, __A11_2__X1_n, __A11_2__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11037(net_U11037_Pad1, __A11_2__X1_n, __A11_2__Y1_n, __XUY15_n, __A11_2__X1, __A11_2__Y1, GND, net_U11037_Pad1, __XUY15_n, net_U11037_Pad10, net_U11037_Pad1, SUMA15_n, __A11_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U11038(net_U11038_Pad1, net_U11038_Pad2, SUMA15_n, SUMB15_n, RULOG_n, net_U11038_Pad6, GND, net_U11038_Pad8, XUY01_n, __XUY15_n, __CI15_n, net_U11038_Pad12, G15, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U11039(__CI15_n, net_U11039_Pad2, G15_n, __A11_2___GEM1, RL15_n, WL15, GND, WL15_n, WL15, , , net_U11039_Pad12, __A11_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11040(SUMB15_n, net_U11037_Pad10, net_U11039_Pad2, net_U11040_Pad4, WAG_n, WL15_n, GND, G16SW_n, WALSG_n, net_U11040_Pad10, A15_n, CAG, net_U11040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11041(net_U11038_Pad8, __A11_2___CO_OUT, net_U11041_Pad3, RL15_n, net_U11041_Pad5, L15_n, GND, Z15_n, net_U11041_Pad9, RL15_n, net_U11041_Pad11, RL15_n, net_U11041_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 #(1'b1, 1'b0, 1'b1) U11042(net_U11040_Pad4, net_U11040_Pad10, net_U11038_Pad6, net_U11042_Pad4, CH16, net_U11041_Pad3, GND, net_U11041_Pad5, net_U11042_Pad9, net_U11042_Pad10, net_U11042_Pad11, A15_n, net_U11040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11043(net_U11042_Pad4, RAG_n, A15_n, net_U11042_Pad9, WLG_n, WL15_n, GND, G01_n, G2LSG_n, net_U11042_Pad10, L15_n, CLG1G, net_U11042_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11044(net_U11044_Pad1, SUMA16_n, SUMA16_n, SUMB16_n, RUG_n, net_U11044_Pad6, GND, __A11_2___RL_OUT_1, RLG_n, L15_n, p4VSW, EAC_n, __CO16, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11045( , , , net_U11045_Pad4, WQG_n, WL15_n, GND, net_U11045_Pad4, net_U11045_Pad13, __A11_2___Q1_n, __A11_2___Q1_n, CQG, net_U11045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11046(net_U11046_Pad1, RQG_n, __A11_2___Q1_n, net_U11046_Pad4, WZG_n, WL15_n, GND, net_U11046_Pad4, net_U11046_Pad13, net_U11041_Pad9, Z15_n, CZG, net_U11046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U11047(net_U11047_Pad1, RZG_n, Z15_n, net_U11047_Pad4, WBG_n, WL15_n, GND, net_U11047_Pad4, net_U11047_Pad13, __A11_2___B1_n, __A11_2___B1_n, CBG, net_U11047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11048(net_U11048_Pad1, RBHG_n, __A11_2___B1_n, net_U11048_Pad4, net_U11047_Pad13, RCG_n, GND, GND, p4VSW, net_U11048_Pad10, GND, p4VSW, net_U11048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11049(__A11_2___RL_OUT_1, net_U11046_Pad1, MDT15, R1C, __RL16, net_U11041_Pad13, GND, net_U11049_Pad8, net_U11048_Pad1, net_U11048_Pad4, net_U11049_Pad11, net_U11041_Pad11, net_U11047_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11050(net_U11031_Pad8, __A11_2___CO_OUT, net_U11049_Pad8, RL15_n, net_U11050_Pad5, G15_n, GND, G15_n, net_U11038_Pad12, RL16_n, net_U11050_Pad11, L16_n, net_U11050_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U11051(net_U11038_Pad1, L2GDG_n, __L14_n, net_U11038_Pad2, WG1G_n, WL15_n, GND, G15_n, CGG, G15, RGG_n, G15_n, net_U11049_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U11052(net_U11050_Pad5, GND, SA16, net_U11048_Pad10, net_U11048_Pad13, , GND, , GND, SA16, net_U11052_Pad11, net_U11052_Pad12, net_U11052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11053(net_U11053_Pad1, A2XG_n, A16_n, net_U11053_Pad4, WYHIG_n, WL16_n, GND, WL16_n, WYDG_n, net_U11053_Pad10, __A11_2__Y2_n, CUG, __A11_2__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11054(MONEX, net_U11053_Pad1, __A11_2__X2_n, CLXC, CUG, __A11_2__X2, GND, __A11_2__Y2_n, net_U11053_Pad4, net_U11053_Pad10, __A11_2__Y2, __A11_2__X2_n, __A11_2__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11055(net_U11044_Pad1, __A11_2__X2_n, __A11_2__Y2_n, __XUY16_n, __A11_2__X2, __A11_2__Y2, GND, , , , net_U11044_Pad1, __XUY16_n, net_U11055_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11056(SUMB16_n, net_U11055_Pad13, net_U11039_Pad12, net_U11056_Pad4, WAG_n, WL16_n, GND, G16SW_n, WALSG_n, net_U11056_Pad10, A16_n, CAG, net_U11056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U11057(net_U11056_Pad4, net_U11056_Pad10, net_U11044_Pad6, net_U11057_Pad4, CH16, net_U11050_Pad11, GND, net_U11050_Pad13, net_U11057_Pad9, net_U11057_Pad10, net_U11057_Pad11, A16_n, net_U11056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11058(net_U11057_Pad4, RAG_n, A16_n, net_U11057_Pad9, WLG_n, WL16_n, GND, __G16_n, G2LSG_n, net_U11057_Pad10, L16_n, CLG1G, net_U11057_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U11059(RLG_n, L16_n, __RL16, net_U11059_Pad4, net_U11059_Pad5, net_U11059_Pad6, GND, net_U11059_Pad8, MDT16, R1C, US2SG, __RL16, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11060(net_U11060_Pad1, WQG_n, WL16_n, __A11_2___Q2_n, net_U11060_Pad1, net_U11060_Pad10, GND, __A11_2___Q2_n, CQG, net_U11060_Pad10, RQG_n, __A11_2___Q2_n, net_U11059_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U11061(net_U11059_Pad6, RL16_n, net_U11061_Pad3, Z16_n, net_U11059_Pad8, RL16_n, GND, RL16_n, net_U11004_Pad12, __G16_n, net_U11052_Pad13, __G16_n, net_U11022_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11062(net_U11062_Pad1, WZG_n, WL16_n, net_U11061_Pad3, net_U11062_Pad1, net_U11062_Pad10, GND, Z16_n, CZG, net_U11062_Pad10, RZG_n, Z16_n, net_U11059_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U11063(net_U11063_Pad1, WBG_n, WL16_n, __A11_2___B2_n, net_U11063_Pad1, net_U11063_Pad10, GND, __A11_2___B2_n, CBG, net_U11063_Pad10, RBHG_n, __A11_2___B2_n, net_U11004_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U11064(net_U11004_Pad2, net_U11063_Pad10, RCG_n, net_U11052_Pad11, WL14_n, WG3G_n, GND, WL01_n, WG5G_n, net_U11052_Pad12, L2GDG_n, L16_n, net_U11022_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U11065(__G16_n, GEM16, RL16_n, WL16, WL16, WL16_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U11066(SUMA13_n, net_U11003_Pad1, XUY13_n, CI13_n, GND, , GND, , net_U11021_Pad1, XUY14_n, __A11_1___CI_INTERNAL, GND, SUMA14_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U11067(SUMA15_n, net_U11037_Pad1, __XUY15_n, __CI15_n, GND, , GND, , net_U11044_Pad1, __XUY16_n, __A11_2___CI_INTERNAL, WHOMPA, SUMA16_n, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U11068(RL13_n, MWL13, RL14_n, MWL14, RL15_n, MWL15, GND, MWL16, RL16_n, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
endmodule |
module rupt_service(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, T10, S10, S10_n, S11_n, S12_n, WL01_n, WL02_n, WL03_n, WL09_n, WL10_n, WL11_n, WL12_n, WL13_n, WL14_n, WL16_n, SUMA01_n, SUMB01_n, SUMA02_n, SUMB02_n, SUMA03_n, SUMB03_n, SUMA11_n, SUMB11_n, SUMA12_n, SUMB12_n, SUMA13_n, SUMB13_n, SUMA14_n, SUMB14_n, SUMA16_n, SUMB16_n, XB0_n, XB1_n, XB4_n, XB6_n, XB7_n, XT0_n, XT1_n, XT2_n, XT3_n, XT4_n, XT5_n, E5, E6, E7_n, STRGAT, CEBG, CFBG, OVF_n, R6, RB1F, RBBEG_n, REBG_n, RFBG_n, RRPA, RSTRT, U2BBKG_n, WBBEG_n, WEBG_n, WFBG_n, WOVR_n, ZOUT_n, DLKPLS, HNDRPT, KRPT, KYRPT1, KYRPT2, RADRPT, UPRUPT, CA2_n, CA3_n, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, MKRPT, EB9, EB10, EB11_n, RL01_n, RL02_n, RL03_n, RL04_n, RL05_n, RL06_n, RL09_n, RL10_n, RL11_n, RL12_n, RL13_n, RL14_n, RL15_n, RL16_n, RUPTOR_n, ROPER, ROPES, ROPET, HIMOD, LOMOD, STR19, STR210, STR311, STR412, STR14, STR58, STR912, T6RPT, DRPRST, STRT2);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire CA2_n;
input wire CA3_n;
input wire CAD1;
input wire CAD2;
input wire CAD3;
input wire CAD4;
input wire CAD5;
input wire CAD6;
input wire CEBG;
input wire CFBG;
input wire DLKPLS;
output wire DRPRST;
input wire E5;
input wire E6;
input wire E7_n;
output wire EB10;
output wire EB11_n;
output wire EB9;
input wire GOJAM;
output wire HIMOD;
input wire HNDRPT;
input wire KRPT;
input wire KYRPT1;
input wire KYRPT2;
output wire LOMOD;
input wire MKRPT;
input wire OVF_n;
input wire R6;
input wire RADRPT;
input wire RB1F;
input wire RBBEG_n;
input wire REBG_n;
input wire RFBG_n;
output wire RL01_n; //FPGA#wand
output wire RL02_n; //FPGA#wand
output wire RL03_n; //FPGA#wand
output wire RL04_n; //FPGA#wand
output wire RL05_n; //FPGA#wand
output wire RL06_n; //FPGA#wand
output wire RL09_n; //FPGA#wand
output wire RL10_n; //FPGA#wand
output wire RL11_n; //FPGA#wand
output wire RL12_n; //FPGA#wand
output wire RL13_n; //FPGA#wand
output wire RL14_n; //FPGA#wand
output wire RL15_n; //FPGA#wand
output wire RL16_n; //FPGA#wand
output wire ROPER;
output wire ROPES;
output wire ROPET;
input wire RRPA;
input wire RSTRT;
output wire RUPTOR_n;
input wire S10;
input wire S10_n;
input wire S11_n;
input wire S12_n;
output wire STR14;
output wire STR19;
output wire STR210;
output wire STR311;
output wire STR412;
output wire STR58;
output wire STR912;
input wire STRGAT;
input wire STRT2;
input wire SUMA01_n;
input wire SUMA02_n;
input wire SUMA03_n;
input wire SUMA11_n;
input wire SUMA12_n;
input wire SUMA13_n;
input wire SUMA14_n;
input wire SUMA16_n;
input wire SUMB01_n;
input wire SUMB02_n;
input wire SUMB03_n;
input wire SUMB11_n;
input wire SUMB12_n;
input wire SUMB13_n;
input wire SUMB14_n;
input wire SUMB16_n;
input wire T10;
output wire T6RPT;
input wire U2BBKG_n;
input wire UPRUPT;
input wire WBBEG_n;
input wire WEBG_n;
input wire WFBG_n;
input wire WL01_n;
input wire WL02_n;
input wire WL03_n;
input wire WL09_n;
input wire WL10_n;
input wire WL11_n;
input wire WL12_n;
input wire WL13_n;
input wire WL14_n;
input wire WL16_n;
input wire WOVR_n;
input wire XB0_n;
input wire XB1_n;
input wire XB4_n;
input wire XB6_n;
input wire XB7_n;
input wire XT0_n;
input wire XT1_n;
input wire XT2_n;
input wire XT3_n;
input wire XT4_n;
input wire XT5_n;
input wire ZOUT_n;
wire __A15_1__BBK1;
wire __A15_1__BBK2;
wire __A15_1__BBK3;
wire __A15_1__BK16;
wire __A15_1__DNRPTA;
wire __A15_1__EB10_n;
wire __A15_1__EB11;
wire __A15_1__EB9_n;
wire __A15_1__F11;
wire __A15_1__F11_n;
wire __A15_1__F12;
wire __A15_1__F12_n;
wire __A15_1__F13;
wire __A15_1__F13_n;
wire __A15_1__F14;
wire __A15_1__F14_n;
wire __A15_1__F15;
wire __A15_1__F15_n;
wire __A15_1__F16;
wire __A15_1__F16_n;
wire __A15_1__FB11;
wire __A15_1__FB11_n;
wire __A15_1__FB12;
wire __A15_1__FB12_n;
wire __A15_1__FB13;
wire __A15_1__FB13_n;
wire __A15_1__FB14;
wire __A15_1__FB14_n;
wire __A15_1__FB16;
wire __A15_1__FB16_n;
wire __A15_1__KRPTA_n;
wire __A15_1__PRPOR1;
wire __A15_1__PRPOR2;
wire __A15_1__PRPOR3;
wire __A15_1__PRPOR4;
wire __A15_1__RPTA12;
wire __A15_1__RPTAD6;
wire __A15_1__RRPA1_n;
wire __A15_2__036H;
wire __A15_2__036L;
wire __A15_2__147H;
wire __A15_2__147L;
wire __A15_2__2510H;
wire __A15_2__2510L;
wire __A15_2__KY1RST;
wire __A15_2__KY2RST;
wire __A15_2__NE00;
wire __A15_2__NE01;
wire __A15_2__NE012_n;
wire __A15_2__NE02;
wire __A15_2__NE03;
wire __A15_2__NE036_n;
wire __A15_2__NE04;
wire __A15_2__NE05;
wire __A15_2__NE06;
wire __A15_2__NE07;
wire __A15_2__NE10;
wire __A15_2__NE147_n;
wire __A15_2__NE2510_n;
wire __A15_2__NE345_n;
wire __A15_2__NE6710_n;
wire __A15_2__RPTAD3;
wire __A15_2__RPTAD4;
wire __A15_2__RPTAD5;
wire net_R15001_Pad2; //FPGA#wand
wire net_R15002_Pad2; //FPGA#wand
wire net_U15001_Pad1;
wire net_U15001_Pad13;
wire net_U15002_Pad2;
wire net_U15002_Pad8;
wire net_U15003_Pad10;
wire net_U15003_Pad11;
wire net_U15003_Pad12;
wire net_U15003_Pad13;
wire net_U15003_Pad2;
wire net_U15003_Pad4;
wire net_U15003_Pad5;
wire net_U15003_Pad6;
wire net_U15003_Pad8;
wire net_U15003_Pad9;
wire net_U15004_Pad11;
wire net_U15004_Pad13;
wire net_U15005_Pad10;
wire net_U15005_Pad9;
wire net_U15007_Pad13;
wire net_U15007_Pad4;
wire net_U15008_Pad12;
wire net_U15009_Pad1;
wire net_U15009_Pad10;
wire net_U15009_Pad12;
wire net_U15010_Pad12;
wire net_U15010_Pad8;
wire net_U15011_Pad1;
wire net_U15011_Pad4;
wire net_U15012_Pad10;
wire net_U15012_Pad11;
wire net_U15012_Pad9;
wire net_U15014_Pad10;
wire net_U15014_Pad6;
wire net_U15014_Pad9;
wire net_U15015_Pad10;
wire net_U15015_Pad13;
wire net_U15016_Pad11;
wire net_U15016_Pad13;
wire net_U15016_Pad5;
wire net_U15016_Pad9;
wire net_U15018_Pad13;
wire net_U15020_Pad3;
wire net_U15021_Pad4;
wire net_U15022_Pad10;
wire net_U15022_Pad11;
wire net_U15022_Pad13;
wire net_U15022_Pad3;
wire net_U15022_Pad4;
wire net_U15022_Pad8;
wire net_U15022_Pad9;
wire net_U15023_Pad10;
wire net_U15023_Pad6;
wire net_U15023_Pad8;
wire net_U15023_Pad9;
wire net_U15024_Pad12;
wire net_U15024_Pad4;
wire net_U15024_Pad6;
wire net_U15024_Pad8;
wire net_U15027_Pad4;
wire net_U15028_Pad3;
wire net_U15028_Pad5;
wire net_U15028_Pad6;
wire net_U15029_Pad10;
wire net_U15029_Pad11;
wire net_U15029_Pad12;
wire net_U15029_Pad13;
wire net_U15029_Pad4;
wire net_U15029_Pad5;
wire net_U15029_Pad6;
wire net_U15029_Pad8;
wire net_U15029_Pad9;
wire net_U15030_Pad5;
wire net_U15031_Pad5;
wire net_U15032_Pad5;
wire net_U15033_Pad1;
wire net_U15033_Pad10;
wire net_U15033_Pad13;
wire net_U15033_Pad3;
wire net_U15033_Pad4;
wire net_U15033_Pad6;
wire net_U15034_Pad11;
wire net_U15034_Pad8;
wire net_U15035_Pad11;
wire net_U15037_Pad10;
wire net_U15037_Pad13;
wire net_U15037_Pad3;
wire net_U15038_Pad1;
wire net_U15038_Pad10;
wire net_U15038_Pad8;
wire net_U15039_Pad11;
wire net_U15039_Pad13;
wire net_U15039_Pad3;
wire net_U15039_Pad5;
wire net_U15039_Pad9;
wire net_U15041_Pad1;
wire net_U15044_Pad10;
wire net_U15044_Pad12;
wire net_U15044_Pad4;
wire net_U15044_Pad6;
wire net_U15044_Pad8;
wire net_U15048_Pad1;
wire net_U15048_Pad10;
wire net_U15048_Pad4;
wire net_U15049_Pad10;
wire net_U15049_Pad12;
wire net_U15049_Pad2;
wire net_U15049_Pad4;
wire net_U15049_Pad6;
wire net_U15049_Pad8;
wire net_U15052_Pad9;
wire net_U15053_Pad11;
wire net_U15053_Pad3;
wire net_U15053_Pad9;
wire net_U15057_Pad13;
wire net_U15058_Pad6;
pullup R15001(net_R15001_Pad2);
pullup R15002(net_R15002_Pad2);
U74HC02 U15001(net_U15001_Pad1, WL16_n, WFBG_n, __A15_1__FB16, __A15_1__FB16_n, CFBG, GND, __A15_1__FB16_n, RFBG_n, __A15_1__BK16, WL14_n, WFBG_n, net_U15001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U15002(net_U15001_Pad1, net_U15002_Pad2, SUMA16_n, U2BBKG_n, SUMB16_n, net_U15002_Pad2, GND, net_U15002_Pad8, SUMA14_n, U2BBKG_n, SUMB14_n, __A15_1__FB16_n, __A15_1__FB16, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15003(__A15_1__BK16, net_U15003_Pad2, __A15_1__BK16, net_U15003_Pad4, net_U15003_Pad5, net_U15003_Pad6, GND, net_U15003_Pad8, net_U15003_Pad9, net_U15003_Pad10, net_U15003_Pad11, net_U15003_Pad12, net_U15003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U15004(net_U15003_Pad2, RL16_n, net_U15003_Pad4, RL15_n, net_U15003_Pad6, RL14_n, GND, RL13_n, net_U15003_Pad8, RL12_n, net_U15004_Pad11, RL11_n, net_U15004_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 #(1'b1, 1'b0, 1'b1) U15005(net_U15001_Pad13, net_U15002_Pad8, SUMA13_n, U2BBKG_n, SUMB13_n, net_U15005_Pad10, GND, __A15_1__FB13_n, net_U15005_Pad9, net_U15005_Pad10, __A15_1__FB13, __A15_1__FB14_n, __A15_1__FB14, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15006(__A15_1__FB14, __A15_1__FB14_n, CFBG, net_U15003_Pad5, __A15_1__FB14_n, RFBG_n, GND, WL13_n, WFBG_n, net_U15005_Pad9, __A15_1__FB13_n, CFBG, __A15_1__FB13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15007(net_U15003_Pad9, __A15_1__FB13_n, RFBG_n, net_U15007_Pad4, WL12_n, WFBG_n, GND, __A15_1__FB12_n, CFBG, __A15_1__FB12, __A15_1__FB12_n, RFBG_n, net_U15007_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U15008(SUMA12_n, U2BBKG_n, net_U15007_Pad4, net_U15008_Pad12, __A15_1__FB12, __A15_1__FB12_n, GND, net_U15004_Pad11, RSTRT, net_U15007_Pad13, __A15_1__RPTA12, net_U15008_Pad12, SUMB12_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15009(net_U15009_Pad1, WFBG_n, WL11_n, __A15_1__FB11, __A15_1__FB11_n, CFBG, GND, __A15_1__FB11_n, RFBG_n, net_U15009_Pad10, net_U15009_Pad10, net_U15009_Pad12, net_U15004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U15010(SUMA11_n, U2BBKG_n, net_U15009_Pad1, net_U15010_Pad12, __A15_1__FB11, __A15_1__FB11_n, GND, net_U15010_Pad8, SUMA03_n, U2BBKG_n, SUMB03_n, net_U15010_Pad12, SUMB11_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15011(net_U15011_Pad1, WL11_n, WEBG_n, net_U15011_Pad4, WL03_n, WBBEG_n, GND, EB11_n, CEBG, __A15_1__EB11, REBG_n, EB11_n, net_U15009_Pad12, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U15012(EB11_n, net_U15010_Pad8, net_U15011_Pad1, net_U15011_Pad4, __A15_1__EB11, , GND, , net_U15012_Pad9, net_U15012_Pad10, net_U15012_Pad11, EB10, __A15_1__EB10_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15013(__A15_1__BBK3, EB11_n, RBBEG_n, net_U15012_Pad10, WL10_n, WEBG_n, GND, WL02_n, WBBEG_n, net_U15012_Pad11, __A15_1__EB10_n, CEBG, EB10, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15014(SUMA02_n, U2BBKG_n, SUMA01_n, U2BBKG_n, SUMB01_n, net_U15014_Pad6, GND, __A15_1__F14, net_U15014_Pad9, net_U15014_Pad10, __A15_1__FB14_n, net_U15012_Pad9, SUMB02_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15015(net_U15003_Pad11, REBG_n, __A15_1__EB10_n, __A15_1__BBK2, __A15_1__EB10_n, RBBEG_n, GND, WL09_n, WEBG_n, net_U15015_Pad10, WL01_n, WBBEG_n, net_U15015_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U15016(net_U15003_Pad10, RL10_n, net_U15003_Pad12, RL09_n, net_U15016_Pad5, RL06_n, GND, net_R15001_Pad2, net_U15016_Pad9, net_R15001_Pad2, net_U15016_Pad11, net_R15002_Pad2, net_U15016_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC4002 #(1'b1, 1'b1) U15017(__A15_1__EB9_n, net_U15014_Pad6, net_U15015_Pad10, net_U15015_Pad13, EB9, , GND, , __A15_1__FB14_n, __A15_1__FB16_n, E7_n, net_U15014_Pad9, __A15_1__F16, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15018(EB9, __A15_1__EB9_n, CEBG, net_U15003_Pad13, REBG_n, __A15_1__EB9_n, GND, __A15_1__EB9_n, RBBEG_n, __A15_1__BBK1, __A15_1__FB11_n, net_U15014_Pad9, net_U15018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15019(S12_n, net_U15014_Pad9, __A15_1__F11_n, __A15_1__F11, __A15_1__F12_n, __A15_1__F12, GND, __A15_1__F13_n, __A15_1__F13, __A15_1__F14_n, __A15_1__F14, __A15_1__F15_n, __A15_1__F15, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15020(__A15_1__F11_n, net_U15018_Pad13, net_U15020_Pad3, net_U15020_Pad3, S11_n, S12_n, GND, net_U15014_Pad9, __A15_1__FB12, __A15_1__F12_n, net_U15014_Pad9, __A15_1__FB13_n, __A15_1__F13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15021(E5, __A15_1__FB16_n, __A15_1__FB16_n, net_U15021_Pad4, net_U15014_Pad9, __A15_1__F15, GND, net_U15021_Pad4, E7_n, __A15_1__FB14_n, E6, net_U15014_Pad10, E7_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15022(__A15_1__F16, __A15_1__F16_n, net_U15022_Pad3, net_U15022_Pad4, KRPT, __A15_1__KRPTA_n, GND, net_U15022_Pad8, net_U15022_Pad9, net_U15022_Pad10, net_U15022_Pad11, __A15_1__PRPOR1, net_U15022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15023(XB4_n, XT4_n, __A15_1__KRPTA_n, XB0_n, XT5_n, net_U15023_Pad6, GND, net_U15023_Pad8, net_U15023_Pad9, net_U15023_Pad10, GOJAM, net_U15023_Pad10, __A15_1__KRPTA_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b1, 1'b0) U15024(net_U15023_Pad9, RADRPT, net_U15023_Pad8, net_U15024_Pad4, HNDRPT, net_U15024_Pad6, GND, net_U15024_Pad8, __A15_1__RRPA1_n, __A15_1__RPTAD6, __A15_1__RRPA1_n, net_U15024_Pad12, __A15_1__RPTA12, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15025(net_U15024_Pad4, net_U15023_Pad6, __A15_1__PRPOR1, net_U15023_Pad9, __A15_1__DNRPTA, __A15_1__PRPOR3, GND, net_U15024_Pad8, __A15_1__PRPOR2, __A15_1__PRPOR3, __A15_1__PRPOR4, net_U15024_Pad6, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U15026(__A15_1__PRPOR4, __A15_1__PRPOR1, __A15_1__DNRPTA, net_U15023_Pad8, net_U15024_Pad4, , GND, , net_U15024_Pad6, net_U15023_Pad8, __A15_1__PRPOR1, __A15_1__DNRPTA, net_U15024_Pad12, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U15027(net_U15016_Pad5, CAD6, __A15_1__RPTAD6, net_U15027_Pad4, net_U15024_Pad12, RUPTOR_n, GND, net_U15027_Pad4, T10, RUPTOR_n, WOVR_n, OVF_n, net_U15022_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15028(CA3_n, XB1_n, net_U15028_Pad3, GOJAM, net_U15028_Pad5, net_U15028_Pad6, GND, net_U15028_Pad5, XT0_n, XB4_n, __A15_1__KRPTA_n, T6RPT, ZOUT_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b1, 1'b1) U15029(net_U15028_Pad3, T6RPT, net_U15028_Pad6, net_U15029_Pad4, net_U15029_Pad5, net_U15029_Pad6, GND, net_U15029_Pad8, net_U15029_Pad9, net_U15029_Pad10, net_U15029_Pad11, net_U15029_Pad12, net_U15029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15030(CA3_n, XB0_n, net_U15029_Pad4, GOJAM, net_U15030_Pad5, net_U15029_Pad6, GND, net_U15030_Pad5, XB0_n, XT1_n, __A15_1__KRPTA_n, net_U15029_Pad5, net_U15022_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15031(CA2_n, XB6_n, net_U15029_Pad10, GOJAM, net_U15031_Pad5, net_U15029_Pad9, GND, net_U15031_Pad5, XT1_n, XB4_n, __A15_1__KRPTA_n, net_U15029_Pad8, net_U15022_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15032(CA2_n, XB7_n, net_U15029_Pad13, GOJAM, net_U15032_Pad5, net_U15029_Pad12, GND, net_U15032_Pad5, XT2_n, XB0_n, __A15_1__KRPTA_n, net_U15029_Pad11, net_U15022_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b1, 1'b0) U15033(net_U15033_Pad1, KYRPT1, net_U15033_Pad3, net_U15033_Pad4, UPRUPT, net_U15033_Pad6, GND, DLKPLS, __A15_1__DNRPTA, net_U15033_Pad10, net_U15028_Pad6, net_U15029_Pad4, net_U15033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b0, 1'b1) U15034(net_U15033_Pad1, GOJAM, XB4_n, XT2_n, __A15_1__KRPTA_n, __A15_2__KY1RST, GND, net_U15034_Pad8, KYRPT2, MKRPT, net_U15034_Pad11, net_U15033_Pad3, __A15_2__KY1RST, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15035(net_U15034_Pad8, GOJAM, XT3_n, XB0_n, __A15_1__KRPTA_n, __A15_2__KY2RST, GND, net_U15033_Pad6, net_U15033_Pad4, GOJAM, net_U15035_Pad11, net_U15034_Pad11, __A15_2__KY2RST, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15036(XT3_n, XB4_n, net_U15033_Pad10, GOJAM, DRPRST, __A15_1__DNRPTA, GND, DRPRST, XB0_n, XT4_n, __A15_1__KRPTA_n, net_U15035_Pad11, __A15_1__KRPTA_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15037(net_U15016_Pad9, net_U15028_Pad6, net_U15037_Pad3, net_U15016_Pad13, net_U15033_Pad13, net_U15037_Pad3, GND, net_U15022_Pad8, net_U15029_Pad13, net_U15037_Pad10, net_U15022_Pad10, net_U15034_Pad8, net_U15037_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15038(net_U15038_Pad1, net_U15038_Pad10, net_U15028_Pad6, net_U15029_Pad10, net_U15029_Pad6, net_U15037_Pad3, GND, net_U15038_Pad8, net_U15037_Pad13, net_U15038_Pad10, __A15_1__PRPOR4, net_U15016_Pad11, __A15_1__PRPOR3, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U15039(net_U15038_Pad8, net_R15002_Pad2, net_U15039_Pad3, RL03_n, net_U15039_Pad5, RL04_n, GND, RL05_n, net_U15039_Pad9, RL02_n, net_U15039_Pad11, RL01_n, net_U15039_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 U15040(net_U15028_Pad6, net_U15029_Pad9, net_U15022_Pad8, net_U15033_Pad1, net_U15029_Pad12, net_U15038_Pad1, GND, net_U15022_Pad11, net_U15022_Pad8, net_U15033_Pad3, net_U15029_Pad12, net_U15022_Pad9, net_U15029_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U15041(net_U15041_Pad1, net_U15038_Pad1, net_U15037_Pad10, net_U15037_Pad13, net_U15038_Pad10, , GND, , __A15_2__RPTAD3, __A15_1__BBK3, CAD3, R6, net_U15039_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15042(net_U15022_Pad10, net_U15033_Pad4, net_U15022_Pad10, net_U15033_Pad6, net_U15034_Pad11, net_U15022_Pad13, GND, , , , , net_U15038_Pad10, net_U15034_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15043(__A15_1__PRPOR2, __A15_1__PRPOR1, net_U15033_Pad10, __A15_2__RPTAD3, __A15_1__RRPA1_n, net_R15001_Pad2, GND, __A15_1__RRPA1_n, net_R15002_Pad2, __A15_2__RPTAD4, __A15_2__RPTAD4, CAD4, net_U15039_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15044(RRPA, __A15_1__RRPA1_n, STRGAT, net_U15044_Pad4, __A15_1__F11, net_U15044_Pad6, GND, net_U15044_Pad8, __A15_1__F11_n, net_U15044_Pad10, S10, net_U15044_Pad12, S10_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15045(net_U15039_Pad9, __A15_2__RPTAD5, CAD5, __A15_2__RPTAD5, __A15_1__RRPA1_n, net_U15041_Pad1, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15046(CAD2, __A15_1__BBK2, CAD1, __A15_1__BBK1, RB1F, net_U15039_Pad13, GND, STR412, net_U15044_Pad4, net_U15044_Pad10, net_U15044_Pad6, net_U15039_Pad11, R6, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15047(net_U15044_Pad4, net_U15044_Pad12, net_U15044_Pad4, net_U15044_Pad10, net_U15044_Pad8, STR210, GND, STR19, net_U15044_Pad4, net_U15044_Pad12, net_U15044_Pad8, STR311, net_U15044_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15048(net_U15048_Pad1, __A15_1__F16, __A15_1__F15, net_U15048_Pad4, __A15_1__F16, __A15_1__F15_n, GND, __A15_1__F15, __A15_1__F16_n, net_U15048_Pad10, __A15_2__NE036_n, __A15_1__F12, __A15_2__036L, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15049(net_U15048_Pad1, net_U15049_Pad2, __A15_1__F14_n, net_U15049_Pad4, __A15_1__F13_n, net_U15049_Pad6, GND, net_U15049_Pad8, __A15_1__F13, net_U15049_Pad10, __A15_1__F14, net_U15049_Pad12, net_U15048_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15050(net_U15049_Pad2, net_U15049_Pad4, net_U15049_Pad2, net_U15049_Pad4, net_U15049_Pad8, __A15_2__NE01, GND, __A15_2__NE02, net_U15049_Pad2, net_U15049_Pad10, net_U15049_Pad6, __A15_2__NE00, net_U15049_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15051(net_U15049_Pad2, net_U15049_Pad10, net_U15049_Pad12, net_U15049_Pad4, net_U15049_Pad6, __A15_2__NE04, GND, __A15_2__NE05, net_U15049_Pad12, net_U15049_Pad4, net_U15049_Pad8, __A15_2__NE03, net_U15049_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15052(net_U15049_Pad12, net_U15049_Pad10, net_U15049_Pad12, net_U15049_Pad10, net_U15049_Pad8, __A15_2__NE07, GND, __A15_2__NE10, net_U15052_Pad9, net_U15049_Pad4, net_U15049_Pad6, __A15_2__NE06, net_U15049_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15053(net_U15048_Pad10, net_U15052_Pad9, net_U15053_Pad3, STR14, , , GND, LOMOD, net_U15053_Pad9, STR58, net_U15053_Pad11, , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15054(__A15_2__NE00, __A15_2__NE03, __A15_2__NE00, __A15_2__NE01, __A15_2__NE02, __A15_2__NE012_n, GND, __A15_2__NE147_n, __A15_2__NE01, __A15_2__NE04, __A15_2__NE07, __A15_2__NE036_n, __A15_2__NE06, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15055(__A15_2__NE04, __A15_2__NE03, __A15_2__NE02, __A15_2__NE05, __A15_2__NE10, __A15_2__NE2510_n, GND, __A15_2__NE6710_n, __A15_2__NE06, __A15_2__NE07, __A15_2__NE10, __A15_2__NE345_n, __A15_2__NE05, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15056(__A15_2__147H, __A15_2__NE147_n, __A15_1__F12_n, __A15_2__2510L, __A15_2__NE2510_n, __A15_1__F12, GND, __A15_2__NE036_n, __A15_1__F12_n, __A15_2__036H, __A15_2__NE147_n, __A15_1__F12, __A15_2__147L, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15057(__A15_2__2510H, __A15_2__NE2510_n, __A15_1__F12_n, net_U15053_Pad3, __A15_2__036L, __A15_2__147H, GND, __A15_2__2510L, __A15_2__036H, net_U15053_Pad11, __A15_2__147L, __A15_2__2510H, net_U15057_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U15058(__A15_2__036L, __A15_2__147L, __A15_2__147H, __A15_2__2510H, __A15_2__2510L, net_U15058_Pad6, GND, , , , , net_U15053_Pad9, __A15_2__036H, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U15059(net_U15058_Pad6, HIMOD, net_U15057_Pad13, STR912, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U15060(ROPER, __A15_2__NE012_n, STRT2, ROPES, __A15_2__NE345_n, STRT2, GND, __A15_2__NE6710_n, STRT2, ROPET, , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module inout_i(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, CCHG_n, WCHG_n, CCH11, RCH11_n, WCH11_n, FLASH, FLASH_n, XT0_n, XT1_n, XB2_n, XB5_n, XB6_n, CHWL01_n, CHWL02_n, CHWL03_n, CHWL04_n, CHWL05_n, CHWL06_n, CHWL07_n, CHWL08_n, CHWL09_n, CHWL10_n, CHWL11_n, CHWL12_n, CHWL13_n, CHWL14_n, CH0705, CH0706, CH0707, CH1501, CH1502, CH1503, CH1504, CH3201, CH3202, CH3203, CH3204, CH3205, CH3206, CH3207, CH3208, CCH12, RCH12_n, WCH12_n, TMPOUT, CH1213, CH1214, CH1208, CH1209, CH1210, CH1211, CH1212, CHOR01_n, CHOR02_n, CHOR03_n, CHOR04_n, CHOR05_n, CHOR06_n, CHOR07_n, CHOR08_n, COMACT, UPLACT, KYRLS, VNFLSH, OPEROR);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire CCH11;
output wire CCH12;
input wire CCHG_n;
input wire CH0705;
input wire CH0706;
input wire CH0707;
output wire CH1208;
output wire CH1209;
output wire CH1210;
output wire CH1211;
output wire CH1212;
output wire CH1213;
output wire CH1214;
input wire CH1501;
input wire CH1502;
input wire CH1503;
input wire CH1504;
input wire CH3201;
input wire CH3202;
input wire CH3203;
input wire CH3204;
input wire CH3205;
input wire CH3206;
input wire CH3207;
input wire CH3208;
output wire CHOR01_n; //FPGA#wand
output wire CHOR02_n; //FPGA#wand
output wire CHOR03_n; //FPGA#wand
output wire CHOR04_n; //FPGA#wand
output wire CHOR05_n; //FPGA#wand
output wire CHOR06_n; //FPGA#wand
output wire CHOR07_n; //FPGA#wand
output wire CHOR08_n; //FPGA#wand
input wire CHWL01_n;
input wire CHWL02_n;
input wire CHWL03_n;
input wire CHWL04_n;
input wire CHWL05_n;
input wire CHWL06_n;
input wire CHWL07_n;
input wire CHWL08_n;
input wire CHWL09_n;
input wire CHWL10_n;
input wire CHWL11_n;
input wire CHWL12_n;
input wire CHWL13_n;
input wire CHWL14_n;
output wire COMACT;
input wire FLASH;
input wire FLASH_n;
input wire GOJAM;
output wire KYRLS;
output wire OPEROR;
input wire RCH11_n;
output wire RCH12_n;
output wire TMPOUT;
output wire UPLACT;
output wire VNFLSH;
input wire WCH11_n;
output wire WCH12_n;
input wire WCHG_n;
input wire XB2_n;
input wire XB5_n;
input wire XB6_n;
input wire XT0_n;
input wire XT1_n;
wire __A16_1__CCH05;
wire __A16_1__CCH06;
wire __A16_1__CH1207;
wire __A16_1__OT1207;
wire __A16_1__OT1207_n;
wire __A16_1__RCH05_n;
wire __A16_1__RCH06_n;
wire __A16_1__RCmXmP;
wire __A16_1__RCmXmY;
wire __A16_1__RCmXpP;
wire __A16_1__RCmXpY;
wire __A16_1__RCmYmR;
wire __A16_1__RCmYpR;
wire __A16_1__RCmZmR;
wire __A16_1__RCmZpR;
wire __A16_1__RCpXmP;
wire __A16_1__RCpXmY;
wire __A16_1__RCpXpP;
wire __A16_1__RCpXpY;
wire __A16_1__RCpYmR;
wire __A16_1__RCpYpR;
wire __A16_1__RCpZmR;
wire __A16_1__RCpZpR;
wire __A16_1__TVCNAB;
wire __A16_1__WCH05_n;
wire __A16_1__WCH06_n;
wire __A16_2__COARSE;
wire __A16_2__DISDAC;
wire __A16_2__ENERIM;
wire __A16_2__ENEROP;
wire __A16_2__ISSWAR;
wire __A16_2__MROLGT;
wire __A16_2__S4BOFF;
wire __A16_2__S4BSEQ;
wire __A16_2__S4BTAK;
wire __A16_2__STARON;
wire __A16_2__ZEROPT;
wire __A16_2__ZIMCDU;
wire __A16_2__ZOPCDU;
wire net_U16001_Pad1;
wire net_U16001_Pad10;
wire net_U16001_Pad11;
wire net_U16001_Pad13;
wire net_U16002_Pad11;
wire net_U16002_Pad13;
wire net_U16002_Pad3;
wire net_U16002_Pad5;
wire net_U16002_Pad9;
wire net_U16003_Pad1;
wire net_U16003_Pad10;
wire net_U16003_Pad12;
wire net_U16003_Pad3;
wire net_U16003_Pad4;
wire net_U16003_Pad6;
wire net_U16003_Pad8;
wire net_U16003_Pad9;
wire net_U16004_Pad11;
wire net_U16004_Pad13;
wire net_U16004_Pad9;
wire net_U16005_Pad1;
wire net_U16005_Pad10;
wire net_U16006_Pad1;
wire net_U16006_Pad10;
wire net_U16007_Pad1;
wire net_U16007_Pad10;
wire net_U16008_Pad1;
wire net_U16008_Pad10;
wire net_U16009_Pad1;
wire net_U16009_Pad10;
wire net_U16010_Pad1;
wire net_U16010_Pad10;
wire net_U16010_Pad11;
wire net_U16010_Pad13;
wire net_U16011_Pad11;
wire net_U16011_Pad13;
wire net_U16011_Pad3;
wire net_U16011_Pad5;
wire net_U16011_Pad9;
wire net_U16012_Pad1;
wire net_U16012_Pad10;
wire net_U16012_Pad3;
wire net_U16012_Pad4;
wire net_U16012_Pad9;
wire net_U16013_Pad1;
wire net_U16013_Pad10;
wire net_U16014_Pad1;
wire net_U16014_Pad10;
wire net_U16015_Pad1;
wire net_U16015_Pad10;
wire net_U16016_Pad1;
wire net_U16016_Pad10;
wire net_U16017_Pad1;
wire net_U16017_Pad10;
wire net_U16018_Pad1;
wire net_U16018_Pad10;
wire net_U16018_Pad11;
wire net_U16018_Pad13;
wire net_U16019_Pad11;
wire net_U16019_Pad13;
wire net_U16019_Pad3;
wire net_U16019_Pad5;
wire net_U16019_Pad9;
wire net_U16020_Pad1;
wire net_U16020_Pad12;
wire net_U16020_Pad3;
wire net_U16020_Pad4;
wire net_U16020_Pad6;
wire net_U16021_Pad11;
wire net_U16021_Pad13;
wire net_U16021_Pad5;
wire net_U16021_Pad9;
wire net_U16022_Pad1;
wire net_U16022_Pad10;
wire net_U16023_Pad1;
wire net_U16023_Pad10;
wire net_U16024_Pad1;
wire net_U16024_Pad10;
wire net_U16025_Pad6;
wire net_U16025_Pad8;
wire net_U16026_Pad1;
wire net_U16026_Pad11;
wire net_U16026_Pad13;
wire net_U16026_Pad3;
wire net_U16026_Pad5;
wire net_U16026_Pad9;
wire net_U16028_Pad1;
wire net_U16028_Pad10;
wire net_U16029_Pad1;
wire net_U16029_Pad10;
wire net_U16030_Pad11;
wire net_U16030_Pad13;
wire net_U16030_Pad3;
wire net_U16030_Pad5;
wire net_U16030_Pad9;
wire net_U16031_Pad1;
wire net_U16031_Pad10;
wire net_U16031_Pad13;
wire net_U16032_Pad10;
wire net_U16032_Pad2;
wire net_U16032_Pad3;
wire net_U16032_Pad4;
wire net_U16032_Pad9;
wire net_U16033_Pad1;
wire net_U16033_Pad10;
wire net_U16034_Pad1;
wire net_U16034_Pad10;
wire net_U16035_Pad1;
wire net_U16035_Pad10;
wire net_U16036_Pad1;
wire net_U16036_Pad10;
wire net_U16037_Pad1;
wire net_U16037_Pad10;
wire net_U16037_Pad11;
wire net_U16038_Pad11;
wire net_U16038_Pad13;
wire net_U16038_Pad3;
wire net_U16038_Pad5;
wire net_U16038_Pad9;
wire net_U16039_Pad1;
wire net_U16039_Pad10;
wire net_U16039_Pad13;
wire net_U16040_Pad1;
wire net_U16040_Pad10;
wire net_U16040_Pad13;
wire net_U16041_Pad10;
wire net_U16041_Pad3;
wire net_U16041_Pad4;
wire net_U16041_Pad6;
wire net_U16041_Pad8;
wire net_U16041_Pad9;
wire net_U16042_Pad1;
wire net_U16042_Pad10;
wire net_U16043_Pad1;
wire net_U16043_Pad10;
wire net_U16043_Pad11;
wire net_U16044_Pad5;
wire net_U16045_Pad1;
wire net_U16045_Pad10;
wire net_U16046_Pad1;
wire net_U16046_Pad10;
wire net_U16046_Pad11;
wire net_U16047_Pad11;
wire net_U16047_Pad13;
wire net_U16047_Pad8;
wire net_U16048_Pad1;
wire net_U16048_Pad10;
wire net_U16049_Pad1;
wire net_U16049_Pad10;
wire net_U16049_Pad11;
wire net_U16050_Pad11;
wire net_U16050_Pad13;
wire net_U16050_Pad3;
wire net_U16050_Pad5;
wire net_U16050_Pad9;
wire net_U16051_Pad1;
wire net_U16051_Pad10;
wire net_U16052_Pad1;
wire net_U16052_Pad10;
wire net_U16052_Pad13;
wire net_U16054_Pad1;
wire net_U16054_Pad10;
wire net_U16055_Pad1;
wire net_U16055_Pad10;
wire net_U16056_Pad1;
wire net_U16056_Pad10;
wire net_U16057_Pad3;
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16001(net_U16001_Pad1, CHWL01_n, __A16_1__WCH05_n, net_U16001_Pad11, net_U16001_Pad1, net_U16001_Pad10, GND, net_U16001_Pad11, __A16_1__CCH05, net_U16001_Pad10, net_U16001_Pad11, __A16_1__RCH05_n, net_U16001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16002(net_U16001_Pad11, __A16_1__RCpXpP, net_U16002_Pad3, __A16_1__RCpZpR, net_U16002_Pad5, __A16_1__RCmXmP, GND, __A16_1__RCmZmR, net_U16002_Pad9, __A16_1__RCmXpP, net_U16002_Pad11, __A16_1__RCmZpR, net_U16002_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16003(net_U16003_Pad1, net_U16001_Pad13, net_U16003_Pad3, net_U16003_Pad4, CH3202, net_U16003_Pad6, GND, net_U16003_Pad8, net_U16003_Pad9, net_U16003_Pad10, CH3203, net_U16003_Pad12, CH3201, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U16004(net_U16003_Pad12, CHOR01_n, net_U16003_Pad6, CHOR02_n, net_U16003_Pad8, CHOR03_n, GND, CHOR04_n, net_U16004_Pad9, CHOR05_n, net_U16004_Pad11, CHOR06_n, net_U16004_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16005(net_U16005_Pad1, CHWL01_n, __A16_1__WCH06_n, net_U16002_Pad3, net_U16005_Pad1, net_U16005_Pad10, GND, net_U16002_Pad3, __A16_1__CCH06, net_U16005_Pad10, net_U16002_Pad3, __A16_1__RCH06_n, net_U16003_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16006(net_U16006_Pad1, CHWL02_n, __A16_1__WCH05_n, net_U16002_Pad5, net_U16006_Pad1, net_U16006_Pad10, GND, net_U16002_Pad5, __A16_1__CCH05, net_U16006_Pad10, net_U16002_Pad5, __A16_1__RCH05_n, net_U16003_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16007(net_U16007_Pad1, CHWL02_n, __A16_1__WCH06_n, net_U16002_Pad9, net_U16007_Pad1, net_U16007_Pad10, GND, net_U16002_Pad9, __A16_1__CCH06, net_U16007_Pad10, net_U16002_Pad9, __A16_1__RCH06_n, net_U16003_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16008(net_U16008_Pad1, CHWL03_n, __A16_1__WCH05_n, net_U16002_Pad11, net_U16008_Pad1, net_U16008_Pad10, GND, net_U16002_Pad11, __A16_1__CCH05, net_U16008_Pad10, net_U16002_Pad11, __A16_1__RCH05_n, net_U16003_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16009(net_U16009_Pad1, CHWL03_n, __A16_1__WCH06_n, net_U16002_Pad13, net_U16009_Pad1, net_U16009_Pad10, GND, net_U16002_Pad13, __A16_1__CCH06, net_U16009_Pad10, net_U16002_Pad13, __A16_1__RCH06_n, net_U16003_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16010(net_U16010_Pad1, CHWL04_n, __A16_1__WCH05_n, net_U16010_Pad11, net_U16010_Pad1, net_U16010_Pad10, GND, net_U16010_Pad11, __A16_1__CCH05, net_U16010_Pad10, net_U16010_Pad11, __A16_1__RCH05_n, net_U16010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16011(net_U16010_Pad11, __A16_1__RCpXmP, net_U16011_Pad3, __A16_1__RCpZmR, net_U16011_Pad5, __A16_1__RCpXpY, GND, __A16_1__RCpYpR, net_U16011_Pad9, __A16_1__RCmXmY, net_U16011_Pad11, __A16_1__RCmYmR, net_U16011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16012(net_U16012_Pad1, net_U16010_Pad13, net_U16012_Pad3, net_U16012_Pad4, CH3205, net_U16004_Pad11, GND, net_U16004_Pad13, net_U16012_Pad9, net_U16012_Pad10, CH3206, net_U16004_Pad9, CH3204, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16013(net_U16013_Pad1, CHWL04_n, __A16_1__WCH06_n, net_U16011_Pad3, net_U16013_Pad1, net_U16013_Pad10, GND, net_U16011_Pad3, __A16_1__CCH06, net_U16013_Pad10, net_U16011_Pad3, __A16_1__RCH06_n, net_U16012_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16014(net_U16014_Pad1, CHWL05_n, __A16_1__WCH05_n, net_U16011_Pad5, net_U16014_Pad1, net_U16014_Pad10, GND, net_U16011_Pad5, __A16_1__CCH05, net_U16014_Pad10, net_U16011_Pad5, __A16_1__RCH05_n, net_U16012_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16015(net_U16015_Pad1, CHWL05_n, __A16_1__WCH06_n, net_U16011_Pad9, net_U16015_Pad1, net_U16015_Pad10, GND, net_U16011_Pad9, __A16_1__CCH06, net_U16015_Pad10, net_U16011_Pad9, __A16_1__RCH06_n, net_U16012_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16016(net_U16016_Pad1, CHWL06_n, __A16_1__WCH05_n, net_U16011_Pad11, net_U16016_Pad1, net_U16016_Pad10, GND, net_U16011_Pad11, __A16_1__CCH05, net_U16016_Pad10, net_U16011_Pad11, __A16_1__RCH05_n, net_U16012_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16017(net_U16017_Pad1, CHWL06_n, __A16_1__WCH06_n, net_U16011_Pad13, net_U16017_Pad1, net_U16017_Pad10, GND, net_U16011_Pad13, __A16_1__CCH06, net_U16017_Pad10, net_U16011_Pad13, __A16_1__RCH06_n, net_U16012_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16018(net_U16018_Pad1, CHWL07_n, __A16_1__WCH05_n, net_U16018_Pad11, net_U16018_Pad1, net_U16018_Pad10, GND, net_U16018_Pad11, __A16_1__CCH05, net_U16018_Pad10, net_U16018_Pad11, __A16_1__RCH05_n, net_U16018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16019(net_U16018_Pad11, __A16_1__RCmXpY, net_U16019_Pad3, __A16_1__RCmYpR, net_U16019_Pad5, __A16_1__RCpXmY, GND, __A16_1__RCpYmR, net_U16019_Pad9, __A16_1__WCH05_n, net_U16019_Pad11, __A16_1__WCH06_n, net_U16019_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16020(net_U16020_Pad1, net_U16018_Pad13, net_U16020_Pad3, net_U16020_Pad4, CH3208, net_U16020_Pad6, GND, net_U16019_Pad11, WCHG_n, XT0_n, XB5_n, net_U16020_Pad12, CH3207, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U16021(net_U16020_Pad12, CHOR07_n, net_U16020_Pad6, CHOR08_n, net_U16021_Pad5, CHOR01_n, GND, CHOR02_n, net_U16021_Pad9, CHOR03_n, net_U16021_Pad11, CHOR04_n, net_U16021_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16022(net_U16022_Pad1, CHWL07_n, __A16_1__WCH06_n, net_U16019_Pad3, net_U16022_Pad1, net_U16022_Pad10, GND, net_U16019_Pad3, __A16_1__CCH06, net_U16022_Pad10, net_U16019_Pad3, __A16_1__RCH06_n, net_U16020_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16023(net_U16023_Pad1, CHWL08_n, __A16_1__WCH05_n, net_U16019_Pad5, net_U16023_Pad1, net_U16023_Pad10, GND, net_U16019_Pad5, __A16_1__CCH05, net_U16023_Pad10, net_U16019_Pad5, __A16_1__RCH05_n, net_U16020_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16024(net_U16024_Pad1, CHWL08_n, __A16_1__WCH06_n, net_U16019_Pad9, net_U16024_Pad1, net_U16024_Pad10, GND, net_U16019_Pad9, __A16_1__CCH06, net_U16024_Pad10, net_U16019_Pad9, __A16_1__RCH06_n, net_U16020_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16025(WCHG_n, XT0_n, CCHG_n, XT0_n, XB5_n, net_U16025_Pad6, GND, net_U16025_Pad8, CCHG_n, XT0_n, XB6_n, net_U16019_Pad13, XB6_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16026(net_U16026_Pad1, __A16_1__CCH05, net_U16026_Pad3, __A16_1__RCH05_n, net_U16026_Pad5, __A16_1__RCH06_n, GND, __A16_1__CCH06, net_U16026_Pad9, __A16_1__TVCNAB, net_U16026_Pad11, __A16_1__OT1207, net_U16026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U16027(net_U16026_Pad1, net_U16025_Pad6, GOJAM, net_U16026_Pad3, XT0_n, XB5_n, GND, XT0_n, XB6_n, net_U16026_Pad5, net_U16025_Pad8, GOJAM, net_U16026_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16028(net_U16028_Pad1, CHWL08_n, WCH12_n, net_U16026_Pad11, net_U16028_Pad1, net_U16028_Pad10, GND, net_U16026_Pad11, CCH12, net_U16028_Pad10, RCH12_n, net_U16026_Pad11, CH1208, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16029(net_U16029_Pad1, WCH12_n, CHWL07_n, net_U16026_Pad13, net_U16029_Pad1, net_U16029_Pad10, GND, net_U16026_Pad13, CCH12, net_U16029_Pad10, RCH12_n, net_U16026_Pad13, __A16_1__CH1207, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16030(net_U16029_Pad10, __A16_1__OT1207_n, net_U16030_Pad3, __A16_2__ZOPCDU, net_U16030_Pad5, __A16_2__ISSWAR, GND, __A16_2__ENEROP, net_U16030_Pad9, COMACT, net_U16030_Pad11, __A16_2__STARON, net_U16030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16031(net_U16031_Pad1, CHWL01_n, WCH12_n, net_U16030_Pad3, net_U16031_Pad1, net_U16031_Pad10, GND, net_U16030_Pad3, CCH12, net_U16031_Pad10, net_U16030_Pad3, RCH12_n, net_U16031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16032(net_U16031_Pad13, net_U16032_Pad2, net_U16032_Pad3, net_U16032_Pad4, CH1502, net_U16021_Pad9, GND, net_U16021_Pad11, net_U16032_Pad9, net_U16032_Pad10, CH1503, net_U16021_Pad5, CH1501, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16033(net_U16033_Pad1, CHWL01_n, WCH11_n, net_U16030_Pad5, net_U16033_Pad1, net_U16033_Pad10, GND, net_U16030_Pad5, CCH11, net_U16033_Pad10, net_U16030_Pad5, RCH11_n, net_U16032_Pad2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16034(net_U16034_Pad1, CHWL02_n, WCH12_n, net_U16030_Pad9, net_U16034_Pad1, net_U16034_Pad10, GND, net_U16030_Pad9, CCH12, net_U16034_Pad10, net_U16030_Pad9, RCH12_n, net_U16032_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16035(net_U16035_Pad1, CHWL02_n, WCH11_n, net_U16030_Pad11, net_U16035_Pad1, net_U16035_Pad10, GND, net_U16030_Pad11, CCH11, net_U16035_Pad10, net_U16030_Pad11, RCH11_n, net_U16032_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16036(net_U16036_Pad1, CHWL03_n, WCH12_n, net_U16030_Pad13, net_U16036_Pad1, net_U16036_Pad10, GND, net_U16030_Pad13, CCH12, net_U16036_Pad10, net_U16030_Pad13, RCH12_n, net_U16032_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16037(net_U16037_Pad1, CHWL03_n, WCH11_n, net_U16037_Pad11, net_U16037_Pad1, net_U16037_Pad10, GND, net_U16037_Pad11, CCH11, net_U16037_Pad10, net_U16037_Pad11, RCH11_n, net_U16032_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16038(net_U16037_Pad11, UPLACT, net_U16038_Pad3, __A16_2__COARSE, net_U16038_Pad5, TMPOUT, GND, __A16_2__ZIMCDU, net_U16038_Pad9, __A16_2__ENERIM, net_U16038_Pad11, __A16_2__S4BTAK, net_U16038_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16039(net_U16039_Pad1, CHWL04_n, WCH12_n, net_U16038_Pad3, net_U16039_Pad1, net_U16039_Pad10, GND, net_U16038_Pad3, CCH12, net_U16039_Pad10, net_U16038_Pad3, RCH12_n, net_U16039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16040(net_U16040_Pad1, CHWL04_n, WCH11_n, net_U16038_Pad5, net_U16040_Pad1, net_U16040_Pad10, GND, net_U16038_Pad5, CCH11, net_U16040_Pad10, net_U16038_Pad5, RCH11_n, net_U16040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16041(net_U16039_Pad13, net_U16040_Pad13, net_U16041_Pad3, net_U16041_Pad4, CH0705, net_U16041_Pad6, GND, net_U16041_Pad8, net_U16041_Pad9, net_U16041_Pad10, CH0706, net_U16021_Pad13, CH1504, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16042(net_U16042_Pad1, CHWL05_n, WCH12_n, net_U16038_Pad9, net_U16042_Pad1, net_U16042_Pad10, GND, net_U16038_Pad9, CCH12, net_U16042_Pad10, net_U16038_Pad9, RCH12_n, net_U16041_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16043(net_U16043_Pad1, CHWL05_n, WCH11_n, net_U16043_Pad11, net_U16043_Pad1, net_U16043_Pad10, GND, net_U16043_Pad11, CCH11, net_U16043_Pad10, net_U16043_Pad11, RCH11_n, net_U16041_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U16044(net_U16041_Pad6, CHOR05_n, net_U16041_Pad8, CHOR06_n, net_U16044_Pad5, CHOR07_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16045(net_U16045_Pad1, CHWL06_n, WCH12_n, net_U16038_Pad11, net_U16045_Pad1, net_U16045_Pad10, GND, net_U16038_Pad11, CCH12, net_U16045_Pad10, net_U16038_Pad11, RCH12_n, net_U16041_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16046(net_U16046_Pad1, CHWL06_n, WCH11_n, net_U16046_Pad11, net_U16046_Pad1, net_U16046_Pad10, GND, net_U16046_Pad11, CCH11, net_U16046_Pad10, net_U16046_Pad11, RCH11_n, net_U16041_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U16047(KYRLS, net_U16043_Pad11, FLASH, VNFLSH, net_U16046_Pad11, FLASH_n, GND, net_U16047_Pad8, FLASH, OPEROR, net_U16047_Pad11, GOJAM, net_U16047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16048(net_U16048_Pad1, CHWL09_n, WCH12_n, net_U16038_Pad13, net_U16048_Pad1, net_U16048_Pad10, GND, net_U16038_Pad13, CCH12, net_U16048_Pad10, net_U16038_Pad13, RCH12_n, CH1209, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16049(net_U16049_Pad1, CHWL10_n, WCH12_n, net_U16049_Pad11, net_U16049_Pad1, net_U16049_Pad10, GND, net_U16049_Pad11, CCH12, net_U16049_Pad10, net_U16049_Pad11, RCH12_n, CH1210, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16050(net_U16049_Pad11, __A16_2__ZEROPT, net_U16050_Pad3, __A16_2__DISDAC, net_U16050_Pad5, __A16_2__MROLGT, GND, __A16_2__S4BSEQ, net_U16050_Pad9, __A16_2__S4BOFF, net_U16050_Pad11, WCH12_n, net_U16050_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16051(net_U16051_Pad1, CHWL11_n, WCH12_n, net_U16050_Pad3, net_U16051_Pad1, net_U16051_Pad10, GND, net_U16050_Pad3, CCH12, net_U16051_Pad10, net_U16050_Pad3, RCH12_n, CH1211, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16052(net_U16052_Pad1, CHWL07_n, WCH11_n, net_U16047_Pad8, net_U16052_Pad1, net_U16052_Pad10, GND, net_U16047_Pad8, CCH11, net_U16052_Pad10, net_U16047_Pad8, RCH11_n, net_U16052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U16053(__A16_1__CH1207, net_U16052_Pad13, WCHG_n, XB2_n, XT1_n, net_U16050_Pad13, GND, net_U16047_Pad11, CCHG_n, XB2_n, XT1_n, net_U16044_Pad5, CH0707, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16054(net_U16054_Pad1, CHWL12_n, WCH12_n, net_U16050_Pad5, net_U16054_Pad1, net_U16054_Pad10, GND, net_U16050_Pad5, CCH12, net_U16054_Pad10, net_U16050_Pad5, RCH12_n, CH1212, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16055(net_U16055_Pad1, CHWL13_n, WCH12_n, net_U16050_Pad9, net_U16055_Pad1, net_U16055_Pad10, GND, net_U16050_Pad9, CCH12, net_U16055_Pad10, net_U16050_Pad9, RCH12_n, CH1213, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U16056(net_U16056_Pad1, CHWL14_n, WCH12_n, net_U16050_Pad11, net_U16056_Pad1, net_U16056_Pad10, GND, net_U16050_Pad11, CCH12, net_U16056_Pad10, net_U16050_Pad11, RCH12_n, CH1214, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U16057(net_U16047_Pad13, CCH12, net_U16057_Pad3, RCH12_n, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U16058(net_U16057_Pad3, XT1_n, XB2_n, , , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module memory_timing_addressing(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, STRT2, PHS2_n, PHS3_n, PHS4_n, T01, T01_n, T02_n, T03, T03_n, T04_n, T05, T05_n, T06, T06_n, T07, T07_n, T08, T08_n, T09, T10, T10_n, T11, T12_n, T12A, S01, S01_n, S02, S02_n, S03, S03_n, S04, S04_n, S05, S05_n, S06, S06_n, S07, S07_n, S08, S08_n, S09, S09_n, S10_n, S11, S12, EB9, EB10, EB11_n, CHINC, DV3764, GOJ1, INOUT, MP1, TCSAJ3, SCAD, TIMR, MAMU, MNHSBF, STBE, STBF, SBF, STRGAT, TPARG_n, XB0, XB0_n, XB1, XB1_n, XB2, XB2_n, XB3, XB3_n, XB4, XB4_n, XB5, XB5_n, XB6, XB6_n, XB7, XB7_n, XT0_n, XT1_n, XT2_n, XT3_n, XT4_n, XT5_n, XT6_n, YB0_n, YT0_n, SETAB, SETCD, RESETA, RESETB, RESETC, RESETD, CLROPE, IL01, IL02, IL03, IL04, IL05, IL06, IL07, SBE, SETEK, RSTKX_n, RSTKY_n, REX, REY, WEX, WEY, ZID, XB7E, XB1E, XB2E, XB3E, XB4E, XB5E, XB6E, XT7E, XT1E, XT2E, XT3E, XT4E, XT5E, XT6E, YB3E, YB1E, YB2E, YT7E, YT1E, YT2E, YT3E, YT4E, YT5E, YT6E);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire CHINC;
output wire CLROPE;
input wire DV3764;
input wire EB10;
input wire EB11_n;
input wire EB9;
input wire GOJ1;
input wire GOJAM;
output wire IL01;
output wire IL02;
output wire IL03;
output wire IL04;
output wire IL05;
output wire IL06;
output wire IL07;
input wire INOUT;
input wire MAMU;
input wire MNHSBF;
input wire MP1;
input wire PHS2_n;
input wire PHS3_n;
input wire PHS4_n;
output wire RESETA;
output wire RESETB;
output wire RESETC;
output wire RESETD;
output wire REX;
output wire REY;
output wire RSTKX_n;
output wire RSTKY_n;
input wire S01;
input wire S01_n;
input wire S02;
input wire S02_n;
input wire S03;
input wire S03_n;
input wire S04;
input wire S04_n;
input wire S05;
input wire S05_n;
input wire S06;
input wire S06_n;
input wire S07;
input wire S07_n;
input wire S08;
input wire S08_n;
input wire S09;
input wire S09_n;
input wire S10_n;
input wire S11;
input wire S12;
output wire SBE;
output wire SBF;
input wire SCAD;
output wire SETAB;
output wire SETCD;
output wire SETEK;
output wire STBE;
output wire STBF;
output wire STRGAT;
input wire STRT2;
input wire T01;
input wire T01_n;
input wire T02_n;
input wire T03;
input wire T03_n;
input wire T04_n;
input wire T05;
input wire T05_n;
input wire T06;
input wire T06_n;
input wire T07;
input wire T07_n;
input wire T08;
input wire T08_n;
input wire T09;
input wire T10;
input wire T10_n;
input wire T11;
input wire T12A;
input wire T12_n;
input wire TCSAJ3;
input wire TIMR;
output wire TPARG_n;
output wire WEX;
output wire WEY;
output wire XB0;
output wire XB0_n;
output wire XB1;
output wire XB1E;
output wire XB1_n;
output wire XB2;
output wire XB2E;
output wire XB2_n;
output wire XB3;
output wire XB3E;
output wire XB3_n;
output wire XB4;
output wire XB4E;
output wire XB4_n;
output wire XB5;
output wire XB5E;
output wire XB5_n;
output wire XB6;
output wire XB6E;
output wire XB6_n;
output wire XB7;
output wire XB7E;
output wire XB7_n;
output wire XT0_n;
output wire XT1E;
output wire XT1_n;
output wire XT2E;
output wire XT2_n;
output wire XT3E;
output wire XT3_n;
output wire XT4E;
output wire XT4_n;
output wire XT5E;
output wire XT5_n;
output wire XT6E;
output wire XT6_n;
output wire XT7E;
output wire YB0_n;
output wire YB1E;
output wire YB2E;
output wire YB3E;
output wire YT0_n;
output wire YT1E;
output wire YT2E;
output wire YT3E;
output wire YT4E;
output wire YT5E;
output wire YT6E;
output wire YT7E;
output wire ZID;
wire __A14_1__CLEARA;
wire __A14_1__CLEARB;
wire __A14_1__CLEARC;
wire __A14_1__CLEARD;
wire __A14_1__ERAS; //FPGA#wand
wire __A14_1__ERAS_n;
wire __A14_1__FNERAS_n;
wire __A14_1__IHENV;
wire __A14_1__REDRST;
wire __A14_1__ROP_n;
wire __A14_1__RSTK_n;
wire __A14_1__S08A;
wire __A14_1__S08A_n;
wire __A14_1__SBESET;
wire __A14_1__SBFSET; //FPGA#wand
wire __A14_1__SETAB_n;
wire __A14_1__SETCD_n;
wire __A14_1__TPGE; //FPGA#wand
wire __A14_1__TPGF; //FPGA#wand
wire __A14_2__EAD09;
wire __A14_2__EAD09_n;
wire __A14_2__EAD10;
wire __A14_2__EAD10_n;
wire __A14_2__EAD11;
wire __A14_2__EAD11_n;
wire __A14_2__IL01_n;
wire __A14_2__IL02_n;
wire __A14_2__IL03_n;
wire __A14_2__IL04_n;
wire __A14_2__IL05_n;
wire __A14_2__IL06_n;
wire __A14_2__IL07_n;
wire __A14_2__ILP;
wire __A14_2__ILP_n;
wire __A14_2__RILP1;
wire __A14_2__RILP1_n;
wire __A14_2__XB0E;
wire __A14_2__XT0;
wire __A14_2__XT0E;
wire __A14_2__XT1;
wire __A14_2__XT2;
wire __A14_2__XT3;
wire __A14_2__XT4;
wire __A14_2__XT5;
wire __A14_2__XT6;
wire __A14_2__XT7;
wire __A14_2__XT7_n;
wire __A14_2__YB0;
wire __A14_2__YB0E;
wire __A14_2__YB1;
wire __A14_2__YB1_n;
wire __A14_2__YB2;
wire __A14_2__YB2_n;
wire __A14_2__YB3;
wire __A14_2__YB3_n;
wire __A14_2__YT0;
wire __A14_2__YT0E;
wire __A14_2__YT1;
wire __A14_2__YT1_n;
wire __A14_2__YT2;
wire __A14_2__YT2_n;
wire __A14_2__YT3;
wire __A14_2__YT3_n;
wire __A14_2__YT4;
wire __A14_2__YT4_n;
wire __A14_2__YT5;
wire __A14_2__YT5_n;
wire __A14_2__YT6;
wire __A14_2__YT6_n;
wire __A14_2__YT7;
wire __A14_2__YT7_n;
wire net_U14001_Pad10;
wire net_U14001_Pad11;
wire net_U14001_Pad12;
wire net_U14001_Pad13;
wire net_U14001_Pad4;
wire net_U14001_Pad9;
wire net_U14002_Pad10;
wire net_U14003_Pad11;
wire net_U14003_Pad5;
wire net_U14004_Pad12;
wire net_U14004_Pad13;
wire net_U14004_Pad6;
wire net_U14004_Pad8;
wire net_U14005_Pad12;
wire net_U14005_Pad13;
wire net_U14006_Pad6;
wire net_U14006_Pad8;
wire net_U14007_Pad1;
wire net_U14007_Pad10;
wire net_U14007_Pad12;
wire net_U14007_Pad13;
wire net_U14007_Pad4;
wire net_U14007_Pad9;
wire net_U14009_Pad10;
wire net_U14009_Pad11;
wire net_U14011_Pad10;
wire net_U14011_Pad13;
wire net_U14012_Pad11;
wire net_U14012_Pad4;
wire net_U14012_Pad9;
wire net_U14013_Pad12;
wire net_U14013_Pad6;
wire net_U14014_Pad11;
wire net_U14014_Pad13;
wire net_U14014_Pad5;
wire net_U14014_Pad9;
wire net_U14016_Pad12;
wire net_U14016_Pad13;
wire net_U14016_Pad6;
wire net_U14016_Pad8;
wire net_U14016_Pad9;
wire net_U14017_Pad1;
wire net_U14017_Pad12;
wire net_U14017_Pad13;
wire net_U14018_Pad10;
wire net_U14018_Pad11;
wire net_U14018_Pad12;
wire net_U14018_Pad3;
wire net_U14019_Pad11;
wire net_U14019_Pad6;
wire net_U14019_Pad8;
wire net_U14020_Pad13;
wire net_U14020_Pad3;
wire net_U14020_Pad6;
wire net_U14021_Pad1;
wire net_U14021_Pad12;
wire net_U14021_Pad2;
wire net_U14021_Pad6;
wire net_U14021_Pad8;
wire net_U14022_Pad10;
wire net_U14022_Pad13;
wire net_U14022_Pad4;
wire net_U14022_Pad8;
wire net_U14024_Pad12;
wire net_U14024_Pad13;
wire net_U14024_Pad3;
wire net_U14024_Pad6;
wire net_U14024_Pad8;
wire net_U14024_Pad9;
wire net_U14025_Pad10;
wire net_U14027_Pad11;
wire net_U14028_Pad5;
wire net_U14030_Pad10;
wire net_U14030_Pad13;
wire net_U14030_Pad2;
wire net_U14031_Pad4;
wire net_U14032_Pad12;
wire net_U14039_Pad13;
wire net_U14047_Pad4;
wire net_U14052_Pad12;
wire net_U14052_Pad13;
wire net_U14053_Pad11;
wire net_U14053_Pad8;
wire net_U14055_Pad11;
wire net_U14055_Pad2;
wire net_U14055_Pad5;
wire net_U14056_Pad12;
wire net_U14056_Pad6;
wire net_U14056_Pad8;
pullup R14001(__A14_1__SBFSET);
pullup R14002(__A14_1__TPGF);
pullup R14003(__A14_1__ERAS);
pullup R14004(__A14_1__TPGE);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b1) U14001(__A14_1__ROP_n, S11, S12, net_U14001_Pad4, T08_n, PHS3_n, GND, net_U14001_Pad4, net_U14001_Pad9, net_U14001_Pad10, net_U14001_Pad11, net_U14001_Pad12, net_U14001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14002(net_U14001_Pad10, T09, __A14_1__ROP_n, net_U14001_Pad10, T08, net_U14001_Pad11, GND, net_U14001_Pad12, net_U14001_Pad13, net_U14002_Pad10, TIMR, net_U14001_Pad9, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14003(T01_n, net_U14002_Pad10, net_U14001_Pad13, __A14_1__IHENV, net_U14003_Pad5, __A14_1__SETAB_n, GND, SETAB, __A14_1__SETAB_n, __A14_1__SETCD_n, net_U14003_Pad11, SETCD, __A14_1__SETCD_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14004(TIMR, net_U14002_Pad10, PHS4_n, __A14_1__ROP_n, T10_n, net_U14004_Pad6, GND, net_U14004_Pad8, T05_n, PHS3_n, __A14_1__ROP_n, net_U14004_Pad12, net_U14004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U14005(net_U14004_Pad13, net_U14004_Pad12, net_U14004_Pad6, net_U14003_Pad5, S09, net_U14004_Pad13, GND, net_U14004_Pad13, S09_n, net_U14003_Pad11, net_U14004_Pad8, net_U14005_Pad12, net_U14005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14006(net_U14005_Pad13, T08, net_U14005_Pad13, S09, S08, net_U14006_Pad6, GND, net_U14006_Pad8, net_U14005_Pad13, S09, S08_n, net_U14005_Pad12, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U14007(net_U14007_Pad1, __A14_1__CLEARA, net_U14006_Pad6, net_U14007_Pad4, __A14_1__CLEARB, net_U14006_Pad8, GND, __A14_1__CLEARC, net_U14007_Pad9, net_U14007_Pad10, __A14_1__CLEARD, net_U14007_Pad12, net_U14007_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14008(net_U14007_Pad1, RESETA, net_U14007_Pad4, RESETB, net_U14007_Pad10, RESETC, GND, RESETD, net_U14007_Pad13, __A14_1__S08A_n, S08, __A14_1__S08A, S08_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14009(net_U14005_Pad13, S08, net_U14005_Pad13, S09_n, S08_n, net_U14007_Pad12, GND, STBF, GOJAM, net_U14009_Pad10, net_U14009_Pad11, net_U14007_Pad9, S09_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U14010(__A14_1__CLEARA, __A14_1__SETAB_n, __A14_1__S08A_n, __A14_1__CLEARB, __A14_1__SETAB_n, __A14_1__S08A, GND, __A14_1__SETCD_n, __A14_1__S08A_n, __A14_1__CLEARC, __A14_1__SETCD_n, __A14_1__S08A, __A14_1__CLEARD, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U14011(net_U14009_Pad11, STBF, __A14_1__SBFSET, net_U14009_Pad10, T07_n, PHS3_n, GND, T02_n, __A14_1__ROP_n, net_U14011_Pad10, net_U14011_Pad10, STRGAT, net_U14011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14012(net_U14009_Pad11, SBF, __A14_1__ROP_n, net_U14012_Pad4, S07_n, __A14_2__IL07_n, GND, WEX, net_U14012_Pad9, WEY, net_U14012_Pad11, __A14_1__ERAS_n, __A14_1__ERAS, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14013(MNHSBF, MP1, __A14_1__ROP_n, T06_n, DV3764, net_U14013_Pad6, GND, STRGAT, net_U14011_Pad13, T08, GOJAM, net_U14013_Pad12, PHS4_n, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U14014(net_U14013_Pad12, __A14_1__SBFSET, net_U14013_Pad6, __A14_1__SBFSET, net_U14014_Pad5, __A14_1__TPGF, GND, __A14_1__TPGF, net_U14014_Pad9, __A14_1__ERAS, net_U14014_Pad11, __A14_1__ERAS, net_U14014_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC4002 U14015(net_U14014_Pad5, __A14_1__ROP_n, T08_n, DV3764, GOJ1, , GND, , GOJAM, TCSAJ3, PHS2_n, MP1, net_U14014_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14016(T02_n, net_U14012_Pad4, net_U14016_Pad13, T03, GOJAM, net_U14016_Pad6, GND, net_U14016_Pad8, net_U14016_Pad9, T07, GOJAM, net_U14016_Pad12, net_U14016_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U14017(net_U14017_Pad1, __A14_1__ROP_n, T10_n, net_U14016_Pad13, net_U14017_Pad1, net_U14016_Pad6, GND, net_U14016_Pad12, net_U14016_Pad8, net_U14016_Pad9, T01, net_U14017_Pad12, net_U14017_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U14018(net_U14017_Pad12, net_U14017_Pad13, net_U14018_Pad3, net_U14018_Pad3, T12_n, PHS3_n, GND, T12A, net_U14017_Pad12, net_U14018_Pad10, net_U14018_Pad11, net_U14018_Pad12, net_U14012_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14019(net_U14018_Pad10, TIMR, net_U14018_Pad10, TIMR, net_U14012_Pad11, net_U14019_Pad6, GND, net_U14019_Pad8, TIMR, T11, net_U14019_Pad11, net_U14018_Pad11, net_U14012_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b0, 1'b0) U14020(net_U14012_Pad11, net_U14019_Pad6, net_U14020_Pad3, net_U14019_Pad11, net_U14019_Pad8, net_U14020_Pad6, GND, net_U14019_Pad11, T10, net_U14018_Pad12, T05_n, __A14_1__ERAS_n, net_U14020_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14021(net_U14021_Pad1, net_U14021_Pad2, __A14_1__ERAS_n, PHS3_n, T03_n, net_U14021_Pad6, GND, net_U14021_Pad8, __A14_1__FNERAS_n, T12A, GOJAM, net_U14021_Pad12, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U14022(__A14_1__FNERAS_n, net_U14020_Pad13, net_U14021_Pad8, net_U14022_Pad4, __A14_1__FNERAS_n, T10_n, GND, net_U14022_Pad8, net_U14020_Pad6, net_U14022_Pad10, T02_n, PHS4_n, net_U14022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14023(T10_n, __A14_1__FNERAS_n, __A14_1__FNERAS_n, T10_n, PHS3_n, net_U14020_Pad6, GND, net_U14022_Pad8, TIMR, net_U14022_Pad13, net_U14022_Pad10, net_U14020_Pad3, PHS4_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14024(TIMR, T01, net_U14024_Pad3, GOJAM, __A14_1__REDRST, net_U14024_Pad6, GND, net_U14024_Pad8, net_U14024_Pad9, GOJAM, __A14_1__REDRST, net_U14024_Pad12, net_U14024_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U14025(net_U14024_Pad13, net_U14024_Pad12, net_U14022_Pad4, ZID, net_U14024_Pad13, STRT2, GND, __A14_1__ERAS_n, T03_n, net_U14025_Pad10, net_U14025_Pad10, net_U14021_Pad12, net_U14021_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U14026(net_U14014_Pad11, TCSAJ3, S11, S12, INOUT, , GND, , CHINC, GOJ1, MP1, MAMU, net_U14014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b1) U14027(SETEK, STRT2, net_U14021_Pad1, net_U14021_Pad2, T06_n, PHS3_n, GND, net_U14021_Pad6, net_U14024_Pad6, net_U14024_Pad3, net_U14027_Pad11, net_U14024_Pad8, net_U14024_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14028(net_U14024_Pad3, REY, net_U14024_Pad9, REX, net_U14028_Pad5, SBE, GND, __A14_1__RSTK_n, net_U14022_Pad10, RSTKY_n, __A14_1__RSTK_n, RSTKX_n, __A14_1__RSTK_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14029(__A14_1__ERAS_n, T03_n, GOJAM, T05, net_U14028_Pad5, STBE, GND, __A14_1__SBESET, T04_n, __A14_1__ERAS_n, SCAD, net_U14027_Pad11, PHS4_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U14030(__A14_1__REDRST, net_U14030_Pad2, T05, net_U14030_Pad2, net_U14030_Pad13, net_U14030_Pad10, GND, net_U14030_Pad2, T06, net_U14030_Pad10, T05_n, PHS3_n, net_U14030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U14031(net_U14028_Pad5, STBE, __A14_1__SBESET, net_U14031_Pad4, T05_n, PHS3_n, GND, __A14_1__TPGF, __A14_1__TPGE, TPARG_n, S07, S08, __A14_2__YB0, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14032(SCAD, __A14_1__ERAS_n, S01, S02, S03, XB0, GND, XB1, S01_n, S02, S03, net_U14032_Pad12, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U14033(net_U14032_Pad12, __A14_1__TPGE, net_U14031_Pad4, __A14_1__TPGE, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4
U74HC04 U14034(XB0, XB0_n, XB0_n, __A14_2__XB0E, XB1, XB1_n, GND, XB1E, XB1_n, XB2_n, XB2, XB2E, XB2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14035(S01, S02_n, S01_n, S02_n, S03, XB3, GND, XB4, S01, S02, S03_n, XB2, S03, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14036(XB3, XB3_n, XB3_n, XB3E, XB4, XB4_n, GND, XB4E, XB4_n, XB5_n, XB5, XB5E, XB5_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14037(S01_n, S02, S01, S02_n, S03_n, XB6, GND, XB7, S01_n, S02_n, S03_n, XB5, S03_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14038(XB6, XB6_n, XB6_n, XB6E, XB7, XB7_n, GND, XB7E, XB7_n, YB0_n, __A14_2__YB0, __A14_2__YB0E, YB0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U14039(__A14_2__YB1, S07_n, S08, __A14_2__YB2, S07, S08_n, GND, S07_n, S08_n, __A14_2__YB3, EB9, S10_n, net_U14039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14040(__A14_2__YB1, __A14_2__YB1_n, __A14_2__YB1_n, YB1E, __A14_2__YB2, __A14_2__YB2_n, GND, YB2E, __A14_2__YB2_n, __A14_2__YB3_n, __A14_2__YB3, YB3E, __A14_2__YB3_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14041(S04, S05, S04_n, S05, S06, __A14_2__XT1, GND, __A14_2__XT2, S04, S05_n, S06, __A14_2__XT0, S06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14042(__A14_2__XT0, XT0_n, XT0_n, __A14_2__XT0E, __A14_2__XT1, XT1_n, GND, XT1E, XT1_n, XT2_n, __A14_2__XT2, XT2E, XT2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14043(S04_n, S05_n, S04, S05, S06_n, __A14_2__XT4, GND, __A14_2__XT5, S04_n, S05, S06_n, __A14_2__XT3, S06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14044(__A14_2__XT3, XT3_n, XT3_n, XT3E, __A14_2__XT4, XT4_n, GND, XT4E, XT4_n, XT5_n, __A14_2__XT5, XT5E, XT5_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14045(S04, S05_n, S04_n, S05_n, S06_n, __A14_2__XT7, GND, __A14_2__EAD11, S09_n, S10_n, EB11_n, __A14_2__XT6, S06_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14046(__A14_2__XT6, XT6_n, XT6_n, XT6E, __A14_2__XT7, __A14_2__XT7_n, GND, XT7E, __A14_2__XT7_n, __A14_2__EAD09_n, __A14_2__EAD09, __A14_2__EAD10_n, __A14_2__EAD10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U14047(__A14_2__EAD09, net_U14039_Pad13, S09_n, net_U14047_Pad4, EB10, S09_n, GND, S10_n, net_U14047_Pad4, __A14_2__EAD10, __A14_2__YB0, __A14_2__YB3, __A14_2__RILP1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14048(__A14_2__EAD11, __A14_2__EAD11_n, __A14_2__YT0, YT0_n, YT0_n, __A14_2__YT0E, GND, __A14_2__YT1_n, __A14_2__YT1, YT1E, __A14_2__YT1_n, __A14_2__YT2_n, __A14_2__YT2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14049(__A14_2__EAD09, __A14_2__EAD10, __A14_2__EAD09_n, __A14_2__EAD10, __A14_2__EAD11, __A14_2__YT1, GND, __A14_2__YT2, __A14_2__EAD09, __A14_2__EAD10_n, __A14_2__EAD11, __A14_2__YT0, __A14_2__EAD11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14050(__A14_2__YT2_n, YT2E, __A14_2__YT3, __A14_2__YT3_n, __A14_2__YT3_n, YT3E, GND, __A14_2__YT4_n, __A14_2__YT4, YT4E, __A14_2__YT4_n, __A14_2__YT5_n, __A14_2__YT5, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14051(__A14_2__EAD09_n, __A14_2__EAD10_n, __A14_2__EAD09, __A14_2__EAD10, __A14_2__EAD11_n, __A14_2__YT4, GND, __A14_2__YT5, __A14_2__EAD09_n, __A14_2__EAD10, __A14_2__EAD11_n, __A14_2__YT3, __A14_2__EAD11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14052(__A14_2__YT5_n, YT5E, __A14_2__YT6, __A14_2__YT6_n, __A14_2__YT6_n, YT6E, GND, __A14_2__YT7_n, __A14_2__YT7, YT7E, __A14_2__YT7_n, net_U14052_Pad12, net_U14052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14053(__A14_2__EAD09, __A14_2__EAD10_n, __A14_2__EAD09_n, __A14_2__EAD10_n, __A14_2__EAD11_n, __A14_2__YT7, GND, net_U14053_Pad8, net_U14052_Pad13, __A14_2__RILP1, net_U14053_Pad11, __A14_2__YT6, __A14_2__EAD11_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U14054(net_U14052_Pad13, XB0, XB3, XB5, XB6, , GND, , __A14_2__XT0, __A14_2__XT3, __A14_2__XT5, __A14_2__XT6, net_U14053_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14055(net_U14053_Pad11, net_U14055_Pad2, __A14_2__RILP1, __A14_2__RILP1_n, net_U14055_Pad5, net_U14055_Pad11, GND, __A14_2__ILP_n, net_U14055_Pad5, __A14_2__ILP, net_U14055_Pad11, IL01, S01, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U14056(net_U14052_Pad12, __A14_2__RILP1, net_U14052_Pad12, __A14_2__RILP1_n, net_U14053_Pad11, net_U14056_Pad6, GND, net_U14056_Pad8, net_U14052_Pad13, __A14_2__RILP1_n, net_U14055_Pad2, net_U14056_Pad12, net_U14055_Pad2, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U14057(net_U14055_Pad5, net_U14053_Pad8, net_U14056_Pad12, net_U14056_Pad6, net_U14056_Pad8, , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14058(S01_n, __A14_2__IL01_n, S02, IL02, S02_n, __A14_2__IL02_n, GND, IL03, S03, __A14_2__IL03_n, S03_n, IL04, S04, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U14059(S04_n, __A14_2__IL04_n, S05, IL05, S05_n, __A14_2__IL05_n, GND, IL06, S06, __A14_2__IL06_n, S06_n, IL07, S07, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U14060(CLROPE, STRT2, net_U14016_Pad9, , , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module timer(SIM_RST, SIM_CLK, p4VDC, p4VSW, GND, CLOCK, ALGA, STRT1, STRT2, MSTP, MSTRTP, SBY, GOJ1, WL15, WL15_n, WL16, WL16_n, CLK, GOJAM, STOP, PHS2_n, PHS3_n, PHS4, PHS4_n, CT, CT_n, RT_n, WT_n, TT_n, P02, P02_n, P03, P03_n, P04_n, SB0_n, SB1_n, SB2, SB2_n, SB4, FS01, FS01_n, F01A, F01B, T01, T01_n, T02, T02_n, T03, T03_n, T04, T04_n, T05, T05_n, T06, T06_n, T07, T07_n, T08, T08_n, T09, T09_n, T10, T10_n, T11, T11_n, T12, T12_n, T12A, TIMR, OVF_n, UNF_n, MGOJAM, MSTPIT_n, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12, MONWT);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VDC;
input wire p4VSW;
input wire GND;
input wire ALGA;
output wire CLK;
input wire CLOCK;
output wire CT;
output wire CT_n;
output wire F01A;
output wire F01B;
output wire FS01;
output wire FS01_n;
input wire GOJ1;
output wire GOJAM;
wire GOJAM_n;
output wire MGOJAM; //FPGA#wand
output wire MONWT; //FPGA#wand
input wire MSTP;
output wire MSTPIT_n; //FPGA#wand
input wire MSTRTP;
output wire MT01; //FPGA#wand
output wire MT02; //FPGA#wand
output wire MT03; //FPGA#wand
output wire MT04; //FPGA#wand
output wire MT05; //FPGA#wand
output wire MT06; //FPGA#wand
output wire MT07; //FPGA#wand
output wire MT08; //FPGA#wand
output wire MT09; //FPGA#wand
output wire MT10; //FPGA#wand
output wire MT11; //FPGA#wand
output wire MT12; //FPGA#wand
output wire OVF_n;
wire P01;
wire P01_n;
output wire P02;
output wire P02_n;
output wire P03;
output wire P03_n;
wire P04;
output wire P04_n;
wire P05;
wire P05_n;
wire PHS2;
output wire PHS2_n;
output wire PHS3_n;
output wire PHS4;
output wire PHS4_n;
wire RT;
output wire RT_n;
output wire SB0_n;
output wire SB1_n;
output wire SB2;
output wire SB2_n;
output wire SB4;
input wire SBY;
output wire STOP;
wire STOPA;
wire STOP_n;
input wire STRT1;
input wire STRT2;
output wire T01;
output wire T01_n;
output wire T02;
output wire T02_n;
output wire T03;
output wire T03_n;
output wire T04;
output wire T04_n;
output wire T05;
output wire T05_n;
output wire T06;
output wire T06_n;
output wire T07;
output wire T07_n;
output wire T08;
output wire T08_n;
output wire T09;
output wire T09_n;
output wire T10;
output wire T10_n;
output wire T11;
output wire T11_n;
output wire T12;
output wire T12A;
output wire T12_n;
output wire TIMR;
output wire TT_n;
output wire UNF_n;
input wire WL15;
input wire WL15_n;
input wire WL16;
input wire WL16_n;
wire WT;
output wire WT_n;
wire __A02_1__EVNSET_n;
wire __A02_1__ODDSET_n;
wire __A02_1__OVFSTB_n;
wire __A02_1__Q2A; //FPGA#wand
wire __A02_1__RINGA_n;
wire __A02_1__RINGB_n;
wire __A02_1__cdiv_1__A;
wire __A02_1__cdiv_1__B;
wire __A02_1__cdiv_1__D;
wire __A02_1__cdiv_1__FS;
wire __A02_1__cdiv_1__FS_n;
wire __A02_1__cdiv_2__A;
wire __A02_1__cdiv_2__B;
wire __A02_1__cdiv_2__C;
wire __A02_1__cdiv_2__D;
wire __A02_1__cdiv_2__F;
wire __A02_1__cdiv_2__FS;
wire __A02_1__cdiv_2__FS_n;
wire __A02_1__evnset;
wire __A02_1__oddset;
wire __A02_1__ovfstb_r1;
wire __A02_1__ovfstb_r2;
wire __A02_1__ovfstb_r3;
wire __A02_1__ovfstb_r4;
wire __A02_1__ovfstb_r5;
wire __A02_1__ovfstb_r6;
wire __A02_2__EDSET;
wire __A02_2__F01C;
wire __A02_2__F01D;
wire __A02_2__SB0;
wire __A02_2__SB1;
wire __A02_2__T12DC_n;
wire __A02_3__OVF;
wire __A02_3__T01DC_n;
wire __A02_3__T02DC_n;
wire __A02_3__T03DC_n;
wire __A02_3__T04DC_n;
wire __A02_3__T05DC_n;
wire __A02_3__T06DC_n;
wire __A02_3__T07DC_n;
wire __A02_3__T08DC_n;
wire __A02_3__T09DC_n;
wire __A02_3__T10DC_n;
wire __A02_3__T12SET; //FPGA#wand
wire __A02_3__UNF;
wire net_R2001_Pad2; //FPGA#wand
wire net_U2024_Pad10;
wire net_U2024_Pad13;
wire net_U2024_Pad4;
wire net_U2024_Pad6;
wire net_U2025_Pad11;
wire net_U2026_Pad1;
wire net_U2026_Pad13;
wire net_U2027_Pad10;
wire net_U2028_Pad10;
wire net_U2028_Pad2;
wire net_U2028_Pad4;
wire net_U2029_Pad11;
wire net_U2030_Pad1;
wire net_U2031_Pad10;
wire net_U2031_Pad2;
wire net_U2031_Pad4;
wire net_U2032_Pad1;
wire net_U2032_Pad13;
wire net_U2033_Pad10;
wire net_U2034_Pad10;
wire net_U2034_Pad11;
wire net_U2034_Pad2;
wire net_U2034_Pad4;
wire net_U2035_Pad4;
wire net_U2036_Pad1;
wire net_U2037_Pad12;
wire net_U2037_Pad6;
wire net_U2037_Pad8;
wire net_U2038_Pad1;
wire net_U2042_Pad9;
wire net_U2043_Pad1;
wire net_U2043_Pad4;
wire net_U2044_Pad10;
wire net_U2103_Pad11;
wire net_U2107_Pad10;
wire net_U2111_Pad12;
wire net_U2111_Pad6;
wire net_U2111_Pad8;
wire net_U2112_Pad10;
wire net_U2112_Pad13;
wire net_U2113_Pad13;
wire net_U2114_Pad10;
wire net_U2114_Pad13;
wire net_U2115_Pad10;
wire net_U2115_Pad13;
wire net_U2116_Pad10;
wire net_U2116_Pad12;
wire net_U2116_Pad13;
wire net_U2119_Pad10;
wire net_U2119_Pad12;
wire net_U2119_Pad6;
wire net_U2119_Pad8;
wire net_U2122_Pad1;
wire net_U2122_Pad9;
wire net_U2123_Pad1;
wire net_U2123_Pad10;
pullup R2001(net_R2001_Pad2);
pullup R2002(__A02_3__T12SET);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2101(__A02_1__cdiv_1__D, __A02_1__cdiv_1__FS_n, __A02_1__cdiv_1__B, __A02_1__cdiv_1__FS_n, __A02_1__cdiv_1__B, __A02_1__cdiv_1__FS, GND, __A02_1__cdiv_1__FS_n, __A02_1__cdiv_1__A, __A02_1__cdiv_1__FS, __A02_1__cdiv_1__A, __A02_1__cdiv_1__FS, PHS2, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U2102(__A02_1__cdiv_1__D, CLOCK, __A02_1__cdiv_1__B, CLOCK, PHS2, __A02_1__cdiv_1__A, GND, __A02_2__EDSET, P02, P03_n, P04, __A02_1__cdiv_1__B, __A02_1__cdiv_1__A, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1) U2103(__A02_1__cdiv_1__D, __A02_1__cdiv_2__F, PHS2, PHS2_n, PHS4, PHS4_n, GND, net_U2103_Pad11, __A02_1__cdiv_1__B, CT, net_U2103_Pad11, CT_n, CT, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U2104(PHS4, __A02_1__cdiv_2__F, __A02_1__cdiv_1__A, __A02_1__oddset, STOP, __A02_1__RINGA_n, GND, P02_n, P04, SB4, P02_n, P05, __A02_2__SB0, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1) U2105(__A02_1__cdiv_1__FS_n, WT, WT, WT_n, WT, TT_n, GND, __A02_1__ovfstb_r5, __A02_1__ovfstb_r4, __A02_1__ovfstb_r6, __A02_1__ovfstb_r5, __A02_1__OVFSTB_n, __A02_1__ovfstb_r2, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2106(__A02_1__cdiv_2__D, __A02_1__cdiv_2__FS_n, __A02_1__cdiv_2__B, __A02_1__cdiv_2__FS_n, __A02_1__cdiv_2__B, __A02_1__cdiv_2__FS, GND, __A02_1__cdiv_2__FS_n, __A02_1__cdiv_2__A, __A02_1__cdiv_2__FS, __A02_1__cdiv_2__A, __A02_1__cdiv_2__FS, __A02_1__cdiv_2__C, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U2107(__A02_1__cdiv_2__D, __A02_1__cdiv_2__F, __A02_1__cdiv_2__B, __A02_1__cdiv_2__F, __A02_1__cdiv_2__C, __A02_1__cdiv_2__A, GND, P03, __A02_2__EDSET, net_U2107_Pad10, P03_n, __A02_1__cdiv_2__B, __A02_1__cdiv_2__A, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0) U2108(__A02_1__cdiv_2__D, __A02_1__RINGA_n, __A02_1__oddset, __A02_1__ODDSET_n, __A02_1__cdiv_2__C, __A02_1__RINGB_n, GND, __A02_1__evnset, __A02_1__RINGB_n, __A02_1__EVNSET_n, __A02_1__evnset, RT, __A02_1__cdiv_1__A, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U2109(__A02_1__ovfstb_r1, CT_n, __A02_1__ovfstb_r2, __A02_1__ovfstb_r2, __A02_1__ovfstb_r6, __A02_1__ovfstb_r1, GND, __A02_1__ovfstb_r4, __A02_1__ovfstb_r2, __A02_1__ovfstb_r3, __A02_1__ovfstb_r3, __A02_1__ovfstb_r1, __A02_1__ovfstb_r4, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U2110(CT, PHS3_n, WT_n, CLK, , , GND, , , RT_n, RT, , , p4VDC, SIM_RST, SIM_CLK);
U74HC27 U2111(__A02_1__RINGB_n, P05_n, P04, P05, __A02_1__RINGA_n, net_U2111_Pad6, GND, net_U2111_Pad8, __A02_2__T12DC_n, net_R2001_Pad2, __A02_1__EVNSET_n, net_U2111_Pad12, P04_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2112(P01, net_U2111_Pad12, P01_n, P01_n, P01, net_U2111_Pad6, GND, __A02_1__RINGA_n, P01, net_U2112_Pad10, P01_n, __A02_1__RINGB_n, net_U2112_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2113(P02, net_U2112_Pad10, P02_n, P02_n, P02, net_U2112_Pad13, GND, __A02_1__RINGB_n, P02, net_U2107_Pad10, P02_n, __A02_1__RINGA_n, net_U2113_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2114(__A02_2__SB1, P05_n, P03_n, P03_n, P03, net_U2113_Pad13, GND, __A02_1__RINGA_n, P03, net_U2114_Pad10, P03_n, __A02_1__RINGB_n, net_U2114_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2115(P04, net_U2114_Pad10, P04_n, P04_n, P04, net_U2114_Pad13, GND, __A02_1__RINGB_n, P04, net_U2115_Pad10, P04_n, __A02_1__RINGA_n, net_U2115_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2116(P05, net_U2115_Pad10, P05_n, P05_n, P05, net_U2115_Pad13, GND, net_R2001_Pad2, GOJ1, net_U2116_Pad10, __A02_1__EVNSET_n, net_U2116_Pad12, net_U2116_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2117(__A02_2__F01D, FS01_n, F01B, FS01_n, F01B, FS01, GND, FS01_n, F01A, FS01, F01A, FS01, __A02_2__F01C, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U2118(__A02_2__F01D, P01_n, F01B, P01_n, __A02_2__F01C, F01A, GND, , , , , F01B, F01A, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b1, 1'b0) U2119(SBY, ALGA, STRT1, STRT2, net_U2116_Pad10, net_U2119_Pad6, GND, net_U2119_Pad8, __A02_2__T12DC_n, net_U2119_Pad10, __A02_1__EVNSET_n, net_U2119_Pad12, MSTRTP, p4VDC, SIM_RST, SIM_CLK);
U74LVC07 U2120(net_U2119_Pad12, net_R2001_Pad2, net_U2119_Pad6, net_R2001_Pad2, , , GND, , , , , , , p4VDC, SIM_RST, SIM_CLK); //FPGA#OD:2,4
U74HC04 #(1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0) U2121(net_R2001_Pad2, net_U2116_Pad12, MSTP, net_U2119_Pad10, GOJAM_n, GOJAM, GND, , , STOP, STOP_n, , , p4VDC, SIM_RST, SIM_CLK);
U74HC02 U2122(net_U2122_Pad1, __A02_1__EVNSET_n, MSTP, GOJAM_n, STRT2, STOPA, GND, STOPA, net_U2122_Pad9, STOP_n, P05_n, P02, SB2, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U2123(net_U2123_Pad1, net_U2111_Pad8, STOPA, STOPA, net_U2123_Pad1, net_U2116_Pad13, GND, net_U2119_Pad8, net_U2122_Pad9, net_U2123_Pad10, net_U2123_Pad10, net_U2122_Pad1, net_U2122_Pad9, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U2024(__A02_3__T12SET, GOJAM, __A02_3__T01DC_n, net_U2024_Pad4, GOJAM, net_U2024_Pad6, GND, net_U2024_Pad4, __A02_3__T02DC_n, net_U2024_Pad10, GOJAM, __A02_2__T12DC_n, net_U2024_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U2025(net_U2024_Pad13, __A02_2__T12DC_n, net_U2024_Pad6, net_U2025_Pad11, __A02_2__T12DC_n, __A02_1__ODDSET_n, GND, __A02_2__T12DC_n, __A02_1__EVNSET_n, T12, net_U2025_Pad11, net_U2024_Pad6, __A02_3__T01DC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U2026(net_U2026_Pad1, __A02_3__T01DC_n, __A02_1__EVNSET_n, T01, __A02_3__T01DC_n, __A02_1__ODDSET_n, GND, net_U2026_Pad1, net_U2024_Pad4, __A02_3__T02DC_n, __A02_3__T02DC_n, __A02_1__ODDSET_n, net_U2026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2027(T02, __A02_3__T02DC_n, __A02_1__EVNSET_n, __A02_3__T03DC_n, net_U2026_Pad13, net_U2024_Pad10, GND, __A02_3__T03DC_n, __A02_1__EVNSET_n, net_U2027_Pad10, __A02_3__T03DC_n, __A02_1__ODDSET_n, T03, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U2028(__A02_3__T03DC_n, net_U2028_Pad2, __A02_3__T04DC_n, net_U2028_Pad4, GOJAM, net_U2028_Pad2, GND, net_U2028_Pad4, __A02_3__T05DC_n, net_U2028_Pad10, GOJAM, net_U2024_Pad10, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U2029(__A02_3__T04DC_n, net_U2027_Pad10, net_U2028_Pad2, net_U2029_Pad11, __A02_3__T04DC_n, __A02_1__ODDSET_n, GND, __A02_3__T04DC_n, __A02_1__EVNSET_n, T04, net_U2029_Pad11, net_U2028_Pad4, __A02_3__T05DC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U2030(net_U2030_Pad1, __A02_3__T05DC_n, __A02_1__EVNSET_n, T05, __A02_3__T05DC_n, __A02_1__ODDSET_n, GND, net_U2028_Pad10, net_U2030_Pad1, __A02_3__T06DC_n, __A02_1__EVNSET_n, __A02_3__T06DC_n, T06, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U2031(GOJAM, net_U2031_Pad2, GOJAM, net_U2031_Pad4, __A02_3__T07DC_n, net_U2031_Pad2, GND, net_U2031_Pad4, GOJAM, net_U2031_Pad10, __A02_3__T08DC_n, net_U2028_Pad10, __A02_3__T06DC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2032(net_U2032_Pad1, __A02_1__ODDSET_n, __A02_3__T06DC_n, __A02_3__T07DC_n, net_U2031_Pad2, net_U2032_Pad1, GND, __A02_1__ODDSET_n, __A02_3__T07DC_n, T07, __A02_1__EVNSET_n, __A02_3__T07DC_n, net_U2032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U2033(__A02_3__T08DC_n, net_U2031_Pad4, net_U2032_Pad13, T08, __A02_1__EVNSET_n, __A02_3__T08DC_n, GND, __A02_1__ODDSET_n, __A02_3__T08DC_n, net_U2033_Pad10, net_U2031_Pad10, net_U2033_Pad10, __A02_3__T09DC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U2034(GOJAM, net_U2034_Pad2, GOJAM, net_U2034_Pad4, __A02_3__T10DC_n, net_U2034_Pad2, GND, net_U2034_Pad4, GOJAM, net_U2034_Pad10, net_U2034_Pad11, net_U2031_Pad10, __A02_3__T09DC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U2035(T09, __A02_1__ODDSET_n, __A02_3__T09DC_n, net_U2035_Pad4, __A02_1__EVNSET_n, __A02_3__T09DC_n, GND, net_U2034_Pad2, net_U2035_Pad4, __A02_3__T10DC_n, __A02_1__EVNSET_n, net_U2034_Pad2, net_U2034_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U2036(net_U2036_Pad1, __A02_1__ODDSET_n, __A02_3__T10DC_n, net_U2034_Pad11, net_U2034_Pad4, net_U2036_Pad1, GND, __A02_1__EVNSET_n, __A02_3__T10DC_n, T10, __A02_1__ODDSET_n, net_U2034_Pad11, T11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U2037(net_U2028_Pad4, net_U2028_Pad2, net_U2031_Pad10, net_U2034_Pad2, __A02_1__EVNSET_n, net_U2037_Pad6, GND, net_U2037_Pad8, net_U2028_Pad10, net_U2031_Pad2, net_U2031_Pad4, net_U2037_Pad12, net_U2024_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U2038(net_U2038_Pad1, __A02_3__T12SET, net_U2037_Pad12, __A02_3__T12SET, net_U2037_Pad6, __A02_3__T12SET, GND, __A02_3__T12SET, net_U2037_Pad8, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1) U2039(T01, T01_n, T02, T02_n, T03, T03_n, GND, T04_n, T04, T05_n, T05, T06_n, T06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1) U2040(T07, T07_n, T08, T08_n, T09, T09_n, GND, T10_n, T10, T11_n, T11, T12_n, T12, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U2041(WL15_n, WL16, __A02_1__OVFSTB_n, WL15, WL16_n, __A02_3__UNF, GND, , , , , __A02_3__OVF, __A02_1__OVFSTB_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U2042(__A02_3__OVF, OVF_n, __A02_3__UNF, UNF_n, T12_n, T12A, GND, TIMR, net_U2042_Pad9, , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U2043(net_U2043_Pad1, P04, P05_n, net_U2043_Pad4, STOP_n, , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U2044(net_U2038_Pad1, net_U2024_Pad4, net_U2024_Pad6, net_U2043_Pad4, P01, net_U2044_Pad10, GND, net_U2043_Pad4, STOP_n, net_U2044_Pad10, STRT2, net_U2043_Pad1, net_U2042_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0) U2145(__A02_2__SB0, SB0_n, __A02_2__SB1, SB1_n, SB2, SB2_n, GND, , , , , , , p4VDC, SIM_RST, SIM_CLK);
U74LVC06 U2046(T01_n, MT01, T02_n, MT02, T03_n, MT03, GND, MT04, T04_n, MT05, T05_n, MT06, T06_n, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74LVC06 U2047(T07_n, MT07, T08_n, MT08, T09_n, MT09, GND, MT10, T10_n, MT11, T11_n, MT12, T12_n, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74LVC06 U2148(WT_n, MONWT, WT_n, __A02_1__Q2A, GOJAM_n, MGOJAM, GND, MSTPIT_n, STOP, , , , , p4VDC, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
endmodule |
module fixed_erasable_memory(SIM_RST, SIM_CLK, p4VSW, GND, ROPER, ROPES, ROPET, HIMOD, LOMOD, STR14, STR58, STR912, STR19, STR210, STR311, STR412, SETAB, SETCD, RESETA, RESETB, RESETC, RESETD, CLROPE, IL07, IL06, IL05, IL04, IL03, IL02, IL01, SBF, XB7E, XB1E, XB2E, XB3E, XB4E, XB5E, XB6E, XT7E, XT1E, XT2E, XT3E, XT4E, XT5E, XT6E, YB3E, YB1E, YB2E, YT7E, YT1E, YT2E, YT3E, YT4E, YT5E, YT6E, GEMP, GEM01, GEM02, GEM03, GEM04, GEM05, GEM06, GEM07, GEM08, GEM09, GEM10, GEM11, GEM12, GEM13, GEM14, GEM16, SETEK, RSTKX_n, RSTKY_n, SBE, REX, REY, WEX, WEY, ZID, SA01, SA02, SA03, SA04, SA05, SA06, SA07, SA08, SA09, SA10, SA11, SA12, SA13, SA14, SAP, SA16);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire CLROPE;
input wire GEM01;
input wire GEM02;
input wire GEM03;
input wire GEM04;
input wire GEM05;
input wire GEM06;
input wire GEM07;
input wire GEM08;
input wire GEM09;
input wire GEM10;
input wire GEM11;
input wire GEM12;
input wire GEM13;
input wire GEM14;
input wire GEM16;
input wire GEMP;
input wire HIMOD;
input wire IL01;
input wire IL02;
input wire IL03;
input wire IL04;
input wire IL05;
input wire IL06;
input wire IL07;
input wire LOMOD;
input wire RESETA;
input wire RESETB;
input wire RESETC;
input wire RESETD;
input wire REX;
input wire REY;
input wire ROPER;
input wire ROPES;
input wire ROPET;
input wire RSTKX_n;
input wire RSTKY_n;
output wire SA01; //FPGA#wor
output wire SA02; //FPGA#wor
output wire SA03; //FPGA#wor
output wire SA04; //FPGA#wor
output wire SA05; //FPGA#wor
output wire SA06; //FPGA#wor
output wire SA07; //FPGA#wor
output wire SA08; //FPGA#wor
output wire SA09; //FPGA#wor
output wire SA10; //FPGA#wor
output wire SA11; //FPGA#wor
output wire SA12; //FPGA#wor
output wire SA13; //FPGA#wor
output wire SA14; //FPGA#wor
output wire SA16; //FPGA#wor
output wire SAP; //FPGA#wor
input wire SBE;
input wire SBF;
input wire SETAB;
input wire SETCD;
input wire SETEK;
input wire STR14;
input wire STR19;
input wire STR210;
input wire STR311;
input wire STR412;
input wire STR58;
input wire STR912;
input wire WEX;
input wire WEY;
input wire XB1E;
input wire XB2E;
input wire XB3E;
input wire XB4E;
input wire XB5E;
input wire XB6E;
input wire XB7E;
input wire XT1E;
input wire XT2E;
input wire XT3E;
input wire XT4E;
input wire XT5E;
input wire XT6E;
input wire XT7E;
input wire YB1E;
input wire YB2E;
input wire YB3E;
input wire YT1E;
input wire YT2E;
input wire YT3E;
input wire YT4E;
input wire YT5E;
input wire YT6E;
input wire YT7E;
input wire ZID;
wire __B01_1__CQA;
wire __B01_1__CQB;
wire __B01_1__CQC;
wire __B01_1__FADDR1;
wire __B01_1__FADDR10;
wire __B01_1__FADDR11;
wire __B01_1__FADDR12;
wire __B01_1__FADDR13;
wire __B01_1__FADDR14;
wire __B01_1__FADDR15;
wire __B01_1__FADDR16;
wire __B01_1__FADDR2;
wire __B01_1__FADDR3;
wire __B01_1__FADDR4;
wire __B01_1__FADDR5;
wire __B01_1__FADDR6;
wire __B01_1__FADDR7;
wire __B01_1__FADDR8;
wire __B01_1__FADDR9;
wire __B01_1__NOROPE;
wire __B01_1__QUARTERA;
wire __B01_1__QUARTERB;
wire __B01_1__QUARTERC;
wire __B01_2__EDESTROY;
wire __B01_2__ES01_n;
wire __B01_2__ES02_n;
wire __B01_2__ES03_n;
wire __B01_2__ES04_n;
wire __B01_2__ES05_n;
wire __B01_2__ES06_n;
wire __B01_2__ES07_n;
wire __B01_2__ES08_n;
wire __B01_2__ES09_n;
wire __B01_2__ES10_n;
wire __B01_2__ES11_n;
wire __B01_2__RADDR1;
wire __B01_2__RADDR10;
wire __B01_2__RADDR11;
wire __B01_2__RADDR2;
wire __B01_2__RADDR3;
wire __B01_2__RADDR4;
wire __B01_2__RADDR5;
wire __B01_2__RADDR6;
wire __B01_2__RADDR7;
wire __B01_2__RADDR8;
wire __B01_2__RADDR9;
wire __B01_2__RESETK;
wire net_U31001_Pad26;
wire net_U31001_Pad28;
wire net_U31002_Pad10;
wire net_U31002_Pad12;
wire net_U31002_Pad2;
wire net_U31002_Pad4;
wire net_U31002_Pad6;
wire net_U31002_Pad8;
wire net_U31003_Pad4;
wire net_U31003_Pad5;
wire net_U31004_Pad6;
wire net_U31004_Pad8;
wire net_U31005_Pad1;
wire net_U31005_Pad10;
wire net_U31005_Pad13;
wire net_U31005_Pad4;
wire net_U31006_Pad10;
wire net_U31006_Pad11;
wire net_U31006_Pad12;
wire net_U31006_Pad9;
wire net_U31010_Pad11;
wire net_U31010_Pad12;
wire net_U31010_Pad13;
wire net_U31010_Pad4;
wire net_U31012_Pad10;
wire net_U31012_Pad11;
wire net_U31012_Pad12;
wire net_U31012_Pad13;
wire net_U31012_Pad3;
wire net_U31014_Pad1;
wire net_U31014_Pad12;
wire net_U31014_Pad13;
wire net_U31014_Pad3;
wire net_U31014_Pad4;
wire net_U31015_Pad10;
wire net_U31015_Pad11;
wire net_U31015_Pad12;
wire net_U31015_Pad2;
wire net_U31015_Pad4;
wire net_U31015_Pad5;
wire net_U31015_Pad6;
wire net_U31016_Pad11;
wire net_U31016_Pad12;
wire net_U31016_Pad6;
wire net_U31016_Pad8;
wire net_U31017_Pad1;
wire net_U31017_Pad10;
wire net_U31017_Pad8;
wire net_U31025_Pad17;
wire net_U31025_Pad41;
wire net_U31026_Pad1;
wire net_U31026_Pad10;
wire net_U31026_Pad2;
wire net_U31026_Pad3;
wire net_U31026_Pad4;
wire net_U31026_Pad6;
wire net_U31027_Pad12;
wire net_U31027_Pad13;
wire net_U31027_Pad5;
wire net_U31027_Pad6;
wire net_U31028_Pad1;
wire net_U31028_Pad13;
wire net_U31028_Pad4;
wire net_U31029_Pad1;
wire net_U31029_Pad10;
wire net_U31029_Pad13;
wire net_U31030_Pad10;
wire net_U31030_Pad4;
wire net_U31031_Pad1;
wire net_U31031_Pad13;
wire net_U31031_Pad4;
wire net_U31032_Pad1;
wire net_U31032_Pad10;
wire net_U31032_Pad13;
wire net_U31033_Pad10;
wire net_U31033_Pad4;
wire net_U31034_Pad1;
wire net_U31034_Pad13;
wire net_U31034_Pad4;
wire net_U31035_Pad1;
wire net_U31035_Pad13;
wire net_U31035_Pad4;
wire net_U31035_Pad6;
wire net_U31035_Pad9;
wire net_U31036_Pad10;
wire net_U31037_Pad10;
wire net_U31037_Pad11;
wire net_U31037_Pad12;
wire net_U31037_Pad6;
wire net_U31038_Pad10;
wire net_U31038_Pad11;
wire net_U31038_Pad12;
wire net_U31038_Pad3;
wire net_U31038_Pad5;
wire net_U31038_Pad6;
wire net_U31039_Pad10;
wire net_U31039_Pad3;
wire net_U31040_Pad11;
pulldown R31001(SA01);
pulldown R31002(SA02);
pulldown R31003(SA03);
pulldown R31004(SA04);
pulldown R31005(SA05);
pulldown R31006(SA06);
pulldown R31007(SA07);
pulldown R31008(SA08);
pulldown R31009(SA09);
pulldown R31010(SA10);
pulldown R31011(SA11);
pulldown R31012(SA12);
pulldown R31013(SA13);
pulldown R31014(SA14);
pulldown R31015(SAP);
pulldown R31016(SA16);
SST39VF200A U31001(__B01_1__FADDR16, __B01_1__FADDR15, __B01_1__FADDR14, __B01_1__FADDR13, __B01_1__FADDR12, __B01_1__FADDR11, __B01_1__FADDR10, __B01_1__FADDR9, , , p4VSW, , , , , , , __B01_1__FADDR8, __B01_1__FADDR7, __B01_1__FADDR6, __B01_1__FADDR5, __B01_1__FADDR4, __B01_1__FADDR3, __B01_1__FADDR2, __B01_1__FADDR1, net_U31001_Pad26, GND, net_U31001_Pad28, SA01, SA09, SA02, SA10, SA03, SA11, SA04, SA12, p4VSW, SA05, SA13, SA06, SA14, SA07, SAP, SA08, SA16, GND, , GND, SIM_RST, SIM_CLK); //FPGA#inputs:EPCS_DATA;FPGA#outputs:EPCS_CSN,EPCS_DCLK,EPCS_ASDI;FPGA#OD:29,30,31,32,33,34,35,36,38,39,40,41,42,43,44,45
U74HC04 U31002(ROPER, net_U31002_Pad2, ROPES, net_U31002_Pad4, ROPET, net_U31002_Pad6, GND, net_U31002_Pad8, STR14, net_U31002_Pad10, STR58, net_U31002_Pad12, STR912, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U31003(net_U31002_Pad6, LOMOD, ROPER, net_U31003_Pad4, net_U31003_Pad5, __B01_1__FADDR15, GND, net_U31003_Pad4, ROPES, LOMOD, STR14, __B01_1__FADDR16, STR14, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U31004(ROPET, HIMOD, ROPER, LOMOD, STR14, net_U31004_Pad6, GND, net_U31004_Pad8, ROPET, LOMOD, net_U31002_Pad8, net_U31003_Pad5, STR912, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U31005(net_U31005_Pad1, net_U31002_Pad4, net_U31002_Pad12, net_U31005_Pad4, net_U31002_Pad2, HIMOD, GND, HIMOD, STR58, net_U31005_Pad10, LOMOD, net_U31002_Pad10, net_U31005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U31006(__B01_1__FADDR14, net_U31005_Pad1, net_U31004_Pad6, net_U31004_Pad8, net_U31005_Pad4, , GND, , net_U31006_Pad9, net_U31006_Pad10, net_U31006_Pad11, net_U31006_Pad12, __B01_1__FADDR13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U31007(ROPES, HIMOD, ROPES, LOMOD, STR14, net_U31006_Pad10, GND, net_U31006_Pad11, net_U31002_Pad4, HIMOD, net_U31002_Pad12, net_U31006_Pad9, STR912, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U31008(net_U31002_Pad4, LOMOD, RSTKX_n, RSTKY_n, ZID, __B01_2__RESETK, GND, __B01_1__NOROPE, ROPER, ROPES, ROPET, net_U31006_Pad12, net_U31002_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U31009(__B01_1__FADDR12, net_U31005_Pad10, net_U31005_Pad13, __B01_1__FADDR11, STR210, STR19, GND, STR19, STR311, __B01_1__FADDR10, __B01_1__QUARTERB, __B01_1__QUARTERA, __B01_1__FADDR9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U31010(__B01_1__FADDR8, __B01_1__QUARTERA, __B01_1__QUARTERC, net_U31010_Pad4, net_U31010_Pad13, __B01_1__QUARTERA, GND, net_U31010_Pad4, __B01_1__CQA, __B01_1__QUARTERA, net_U31010_Pad11, net_U31010_Pad12, net_U31010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U31011(IL07, __B01_1__FADDR7, IL06, __B01_1__FADDR6, IL05, __B01_1__FADDR5, GND, __B01_1__FADDR4, IL04, __B01_1__FADDR3, IL03, __B01_1__FADDR2, IL02, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1) U31012(IL01, __B01_1__FADDR1, net_U31012_Pad3, net_U31001_Pad28, SETAB, net_U31010_Pad11, GND, net_U31010_Pad12, RESETB, net_U31012_Pad10, net_U31012_Pad11, net_U31012_Pad12, net_U31012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b0) U31013(net_U31001_Pad26, STR19, STR210, STR311, STR412, , GND, , XB1E, XB3E, XB5E, XB7E, __B01_2__ES01_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U31014(net_U31014_Pad1, RESETA, net_U31014_Pad3, net_U31014_Pad4, net_U31014_Pad1, net_U31012_Pad13, GND, net_U31014_Pad4, RESETA, net_U31012_Pad13, net_U31010_Pad11, net_U31014_Pad12, net_U31014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1) U31015(net_U31012_Pad12, net_U31015_Pad2, net_U31015_Pad2, net_U31015_Pad4, net_U31015_Pad5, net_U31015_Pad6, GND, net_U31015_Pad11, net_U31015_Pad6, net_U31015_Pad10, net_U31015_Pad11, net_U31015_Pad12, net_U31015_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b1, 1'b0, 1'b1) U31016(net_U31015_Pad4, net_U31014_Pad3, RESETA, net_U31014_Pad12, SETCD, net_U31016_Pad6, GND, net_U31016_Pad8, RESETD, __B01_1__CQA, net_U31016_Pad11, net_U31016_Pad12, ZID, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U31017(net_U31017_Pad1, net_U31014_Pad13, __B01_1__QUARTERB, __B01_1__QUARTERB, net_U31017_Pad1, __B01_1__CQB, GND, net_U31017_Pad8, __B01_1__QUARTERC, net_U31017_Pad10, net_U31017_Pad10, __B01_1__CQC, __B01_1__QUARTERC, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U31018(net_U31017_Pad8, net_U31016_Pad6, net_U31016_Pad8, net_U31016_Pad11, CLROPE, net_U31014_Pad1, GND, YB1E, YB3E, __B01_2__ES07_n, YB2E, YB3E, __B01_2__ES08_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U31019(__B01_2__ES02_n, XB2E, XB3E, XB6E, XB7E, , GND, , XB4E, XB5E, XB6E, XB7E, __B01_2__ES03_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U31020(__B01_2__ES04_n, XT1E, XT3E, XT5E, XT7E, , GND, , XT2E, XT3E, XT6E, XT7E, __B01_2__ES05_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U31021(__B01_2__ES06_n, XT4E, XT5E, XT6E, XT7E, , GND, , YT1E, YT3E, YT5E, YT7E, __B01_2__ES09_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U31022(__B01_2__ES10_n, YT2E, YT3E, YT6E, YT7E, , GND, , YT4E, YT5E, YT6E, YT7E, __B01_2__ES11_n, p4VSW, SIM_RST, SIM_CLK);
U74HC244 U31023(net_U31016_Pad12, GEMP, SA07, GEM01, SA06, GEM02, SA05, GEM03, SA04, GND, GEM04, SA03, GEM05, SA02, GEM06, SA01, GEM07, SAP, net_U31016_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:3,5,7,9,12,14,16,18
U74HC244 U31024(net_U31016_Pad12, GEM08, SA16, GEM09, SA14, GEM10, SA13, GEM11, SA12, GND, GEM12, SA11, GEM13, SA10, GEM14, SA09, GEM16, SA08, net_U31016_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:3,5,7,9,12,14,16,18
MR0A16A U31025(__B01_2__RADDR1, __B01_2__RADDR2, __B01_2__RADDR3, __B01_2__RADDR4, __B01_2__RADDR5, GND, SA01, SA02, SA03, SA04, p4VSW, GND, SA05, SA06, SA07, SA08, net_U31025_Pad17, __B01_2__RADDR6, __B01_2__RADDR7, __B01_2__RADDR8, __B01_2__RADDR9, __B01_2__RADDR10, __B01_2__RADDR11, GND, GND, GND, p4VSW, , SA09, SA10, SA11, SA12, p4VSW, GND, SA13, SA14, SAP, SA16, GND, GND, net_U31025_Pad41, GND, GND, GND, SIM_RST, SIM_CLK); //FPGA#bidir:7,8,9,10,13,14,15,16,29,30,31,32,35,36,37,38;FPGA#OD:7,8,9,10,13,14,15,16,29,30,31,32,35,36,37,38
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U31026(net_U31026_Pad1, net_U31026_Pad2, net_U31026_Pad3, net_U31026_Pad4, __B01_2__ES01_n, net_U31026_Pad6, GND, net_U31026_Pad4, __B01_2__RADDR1, net_U31026_Pad10, net_U31026_Pad10, __B01_2__RESETK, __B01_2__RADDR1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b0, 1'b1, 1'b1, 1'b1) U31027(WEX, net_U31026_Pad2, WEY, net_U31026_Pad3, net_U31027_Pad5, net_U31027_Pad6, GND, net_U31025_Pad41, SBE, net_U31026_Pad6, SETEK, net_U31027_Pad12, net_U31027_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U31028(net_U31028_Pad1, __B01_2__ES02_n, net_U31026_Pad6, net_U31028_Pad4, net_U31028_Pad1, __B01_2__RADDR2, GND, net_U31028_Pad4, __B01_2__RESETK, __B01_2__RADDR2, __B01_2__ES03_n, net_U31026_Pad6, net_U31028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U31029(net_U31029_Pad1, net_U31028_Pad13, __B01_2__RADDR3, __B01_2__RADDR3, net_U31029_Pad1, __B01_2__RESETK, GND, __B01_2__ES04_n, net_U31026_Pad6, net_U31029_Pad10, net_U31029_Pad10, __B01_2__RADDR4, net_U31029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U31030(__B01_2__RADDR4, net_U31029_Pad13, __B01_2__RESETK, net_U31030_Pad4, __B01_2__ES05_n, net_U31026_Pad6, GND, net_U31030_Pad4, __B01_2__RADDR5, net_U31030_Pad10, net_U31030_Pad10, __B01_2__RESETK, __B01_2__RADDR5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U31031(net_U31031_Pad1, __B01_2__ES06_n, net_U31026_Pad6, net_U31031_Pad4, net_U31031_Pad1, __B01_2__RADDR6, GND, net_U31031_Pad4, __B01_2__RESETK, __B01_2__RADDR6, __B01_2__ES07_n, net_U31026_Pad6, net_U31031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U31032(net_U31032_Pad1, net_U31031_Pad13, __B01_2__RADDR7, __B01_2__RADDR7, net_U31032_Pad1, __B01_2__RESETK, GND, __B01_2__ES08_n, net_U31026_Pad6, net_U31032_Pad10, net_U31032_Pad10, __B01_2__RADDR8, net_U31032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U31033(__B01_2__RADDR8, net_U31032_Pad13, __B01_2__RESETK, net_U31033_Pad4, __B01_2__ES09_n, net_U31026_Pad6, GND, net_U31033_Pad4, __B01_2__RADDR9, net_U31033_Pad10, net_U31033_Pad10, __B01_2__RESETK, __B01_2__RADDR9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U31034(net_U31034_Pad1, __B01_2__ES10_n, net_U31026_Pad6, net_U31034_Pad4, net_U31034_Pad1, __B01_2__RADDR10, GND, net_U31034_Pad4, __B01_2__RESETK, __B01_2__RADDR10, __B01_2__ES11_n, net_U31026_Pad6, net_U31034_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U31035(net_U31035_Pad1, net_U31034_Pad13, __B01_2__RADDR11, net_U31035_Pad4, CLROPE, net_U31035_Pad6, GND, net_U31027_Pad6, net_U31035_Pad9, __B01_2__EDESTROY, __B01_2__EDESTROY, net_U31027_Pad13, net_U31035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U31036(net_U31027_Pad13, net_U31035_Pad13, net_U31027_Pad6, net_U31035_Pad6, RESETB, net_U31015_Pad12, GND, net_U31035_Pad6, net_U31015_Pad5, net_U31036_Pad10, net_U31036_Pad10, RESETB, net_U31015_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1) U31037(net_U31027_Pad12, net_U31012_Pad11, net_U31035_Pad4, __B01_1__CQB, net_U31012_Pad10, net_U31037_Pad6, GND, net_U31037_Pad11, net_U31037_Pad6, net_U31037_Pad10, net_U31037_Pad11, net_U31037_Pad12, net_U31037_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b1) U31038(net_U31037_Pad12, net_U31035_Pad9, net_U31038_Pad3, __B01_1__CQC, net_U31038_Pad5, net_U31038_Pad6, GND, net_U31038_Pad11, net_U31038_Pad6, net_U31038_Pad10, net_U31038_Pad11, net_U31038_Pad12, net_U31038_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U31039(net_U31038_Pad3, CLROPE, net_U31039_Pad3, net_U31039_Pad3, RESETC, net_U31038_Pad12, GND, net_U31039_Pad3, net_U31038_Pad5, net_U31039_Pad10, net_U31039_Pad10, RESETC, net_U31038_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U31040(__B01_2__RADDR11, net_U31035_Pad1, __B01_2__RESETK, net_U31027_Pad5, REX, REY, GND, net_U31026_Pad1, __B01_2__EDESTROY, net_U31025_Pad17, net_U31040_Pad11, __B01_1__NOROPE, net_U31012_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U31041(SBF, net_U31040_Pad11, , , , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module sq_register(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, T01_n, T02, T12_n, PHS2_n, RT_n, CT_n, WT_n, WL16_n, WL14_n, WL13_n, WL12_n, WL11_n, WL10_n, INKL, INHPLS, RELPLS, RUPTOR_n, RPTSET, KRPT, ST0_n, ST1_n, STD2, ST3_n, BR2_n, BR1B2B, RXOR0, EXT, EXTPLS, NISQ, NISQ_n, n5XP4, A15_n, A16_n, MTCSAI, MNHRPT, NISQL_n, RBSQ, SQ0_n, SQ1_n, SQ2_n, QC0_n, QC1_n, QC2_n, QC3_n, SQR12_n, SQR10, SQR10_n, SQEXT, SQEXT_n, EXST0_n, EXST1_n, FUTEXT, IIP, IIP_n, STRTFC, AD0, ADS0, AUG0_n, CCS0, CCS0_n, DAS0, DAS0_n, DAS1, DAS1_n, DCA0, DCS0, DIM0_n, DXCH0, GOJ1, GOJ1_n, INCR0, MASK0, MASK0_n, MP0, MP0_n, MP1, MP1_n, MP3, MP3_n, MP3A, MSU0, MSU0_n, NDX0_n, NDXX1_n, QXCH0_n, RSM3, RSM3_n, SU0, TC0, TC0_n, TCF0, TCSAJ3, TCSAJ3_n, TS0, TS0_n, IC1, IC2, IC2_n, IC3, IC4, IC5, IC5_n, IC6, IC7, IC8_n, IC9, IC10, IC10_n, IC11, IC11_n, IC12, IC12_n, IC13, IC14, IC15, IC15_n, IC16, IC16_n, IC17, MSQ16, MSQ14, MSQ13, MSQ12, MSQ11, MSQ10, MSQEXT, MINHL, MIIP, MTCSA_n);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire A15_n;
input wire A16_n;
output wire AD0;
output wire ADS0;
output wire AUG0_n;
input wire BR1B2B;
input wire BR2_n;
output wire CCS0;
output wire CCS0_n;
input wire CT_n;
output wire DAS0;
output wire DAS0_n;
output wire DAS1;
output wire DAS1_n;
output wire DCA0;
output wire DCS0;
output wire DIM0_n;
output wire DXCH0;
output wire EXST0_n;
output wire EXST1_n;
input wire EXT;
input wire EXTPLS;
output wire FUTEXT;
output wire GOJ1;
output wire GOJ1_n;
input wire GOJAM;
output wire IC1;
output wire IC10;
output wire IC10_n;
output wire IC11;
output wire IC11_n;
output wire IC12;
output wire IC12_n;
output wire IC13;
output wire IC14;
output wire IC15;
output wire IC15_n;
output wire IC16;
output wire IC16_n;
output wire IC17;
output wire IC2;
output wire IC2_n;
output wire IC3;
output wire IC4;
output wire IC5;
output wire IC5_n;
output wire IC6;
output wire IC7;
output wire IC8_n;
output wire IC9;
output wire IIP;
output wire IIP_n;
output wire INCR0;
input wire INHPLS;
input wire INKL;
input wire KRPT;
output wire MASK0;
output wire MASK0_n;
output wire MIIP; //FPGA#wand
output wire MINHL; //FPGA#wand
input wire MNHRPT;
output wire MP0;
output wire MP0_n;
output wire MP1;
output wire MP1_n;
output wire MP3;
output wire MP3A;
output wire MP3_n;
output wire MSQ10; //FPGA#wand
output wire MSQ11; //FPGA#wand
output wire MSQ12; //FPGA#wand
output wire MSQ13; //FPGA#wand
output wire MSQ14; //FPGA#wand
output wire MSQ16; //FPGA#wand
output wire MSQEXT; //FPGA#wand
output wire MSU0;
output wire MSU0_n;
input wire MTCSAI;
output wire MTCSA_n; //FPGA#wand
output wire NDX0_n;
output wire NDXX1_n;
input wire NISQ;
output wire NISQL_n;
input wire NISQ_n;
input wire PHS2_n;
output wire QC0_n;
output wire QC1_n;
output wire QC2_n;
output wire QC3_n;
output wire QXCH0_n;
output wire RBSQ;
input wire RELPLS;
inout wire RPTSET; //FPGA#wand
output wire RSM3;
output wire RSM3_n;
input wire RT_n;
input wire RUPTOR_n;
input wire RXOR0;
output wire SQ0_n;
output wire SQ1_n;
output wire SQ2_n;
output wire SQEXT;
output wire SQEXT_n;
output wire SQR10;
output wire SQR10_n;
output wire SQR12_n;
input wire ST0_n;
input wire ST1_n;
input wire ST3_n;
input wire STD2;
output wire STRTFC;
output wire SU0;
input wire T01_n;
input wire T02;
input wire T12_n;
output wire TC0;
output wire TC0_n;
output wire TCF0;
output wire TCSAJ3;
output wire TCSAJ3_n;
output wire TS0;
output wire TS0_n;
input wire WL10_n;
input wire WL11_n;
input wire WL12_n;
input wire WL13_n;
input wire WL14_n;
input wire WL16_n;
input wire WT_n;
wire __A03_1__CSQG;
wire __A03_1__INHINT;
wire __A03_1__INKBT1;
wire __A03_1__NISQL;
wire __A03_1__OVNHRP;
wire __A03_1__QC0;
wire __A03_1__RPTFRC;
wire __A03_1__SQ3_n;
wire __A03_1__SQ4_n;
wire __A03_1__SQ5_n;
wire __A03_1__SQ6_n;
wire __A03_1__SQ7_n;
wire __A03_1__SQR11;
wire __A03_1__SQR12;
wire __A03_1__SQR13;
wire __A03_1__SQR14;
wire __A03_1__SQR16;
wire __A03_1__WSQG_n;
wire __A03_1__wsqg;
wire __A03_2__AUG0;
wire __A03_2__BMF0;
wire __A03_2__BMF0_n;
wire __A03_2__BZF0;
wire __A03_2__BZF0_n;
wire __A03_2__DIM0;
wire __A03_2__IC13_n; //FPGA#wand
wire __A03_2__IC3_n;
wire __A03_2__IC4_n;
wire __A03_2__IC9_n;
wire __A03_2__LXCH0;
wire __A03_2__NDX0;
wire __A03_2__NDXX1;
wire __A03_2__NEXST0;
wire __A03_2__NEXST0_n;
wire __A03_2__QXCH0;
wire __A03_2__SQ5QC0_n;
input wire n5XP4;
wire net_U3001_Pad1;
wire net_U3001_Pad11;
wire net_U3001_Pad4;
wire net_U3001_Pad6;
wire net_U3003_Pad11;
wire net_U3003_Pad13;
wire net_U3003_Pad9;
wire net_U3004_Pad1;
wire net_U3004_Pad10;
wire net_U3004_Pad11;
wire net_U3004_Pad12;
wire net_U3004_Pad13;
wire net_U3004_Pad4;
wire net_U3005_Pad10;
wire net_U3005_Pad12;
wire net_U3005_Pad13;
wire net_U3005_Pad4;
wire net_U3007_Pad1;
wire net_U3007_Pad10;
wire net_U3009_Pad8;
wire net_U3010_Pad12;
wire net_U3010_Pad6;
wire net_U3010_Pad8;
wire net_U3010_Pad9;
wire net_U3011_Pad11;
wire net_U3011_Pad9;
wire net_U3012_Pad10;
wire net_U3012_Pad13;
wire net_U3012_Pad4;
wire net_U3014_Pad1;
wire net_U3014_Pad10;
wire net_U3014_Pad13;
wire net_U3014_Pad4;
wire net_U3015_Pad1;
wire net_U3015_Pad11;
wire net_U3015_Pad12;
wire net_U3015_Pad2;
wire net_U3015_Pad6;
wire net_U3015_Pad8;
wire net_U3016_Pad11;
wire net_U3016_Pad12;
wire net_U3016_Pad6;
wire net_U3016_Pad8;
wire net_U3017_Pad10;
wire net_U3017_Pad12;
wire net_U3017_Pad6;
wire net_U3017_Pad8;
wire net_U3019_Pad11;
wire net_U3019_Pad4;
wire net_U3020_Pad4;
wire net_U3020_Pad5;
wire net_U3020_Pad6;
wire net_U3021_Pad2;
wire net_U3021_Pad4;
wire net_U3022_Pad10;
wire net_U3022_Pad13;
wire net_U3022_Pad4;
wire net_U3026_Pad1;
wire net_U3026_Pad10;
wire net_U3026_Pad4;
wire net_U3027_Pad5;
wire net_U3028_Pad13;
wire net_U3028_Pad4;
wire net_U3031_Pad13;
wire net_U3032_Pad9;
wire net_U3033_Pad13;
wire net_U3034_Pad1;
wire net_U3036_Pad13;
wire net_U3040_Pad10;
wire net_U3040_Pad11;
wire net_U3047_Pad8;
wire net_U3052_Pad2;
pullup R3001(RPTSET);
pullup R3002(__A03_2__IC13_n);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U3001(net_U3001_Pad1, NISQ, __A03_1__NISQL, net_U3001_Pad4, STRTFC, net_U3001_Pad6, GND, RT_n, net_U3001_Pad11, RBSQ, net_U3001_Pad11, WT_n, __A03_1__wsqg, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3002(net_U3001_Pad1, __A03_1__INKBT1, T12_n, net_U3001_Pad1, __A03_1__RPTFRC, net_U3001_Pad6, GND, __A03_1__CSQG, T12_n, CT_n, net_U3001_Pad4, __A03_1__NISQL, STRTFC, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1) U3003(__A03_1__NISQL, NISQL_n, net_U3001_Pad6, net_U3001_Pad11, __A03_1__wsqg, __A03_1__WSQG_n, GND, STRTFC, net_U3003_Pad9, SQEXT, net_U3003_Pad11, SQEXT_n, net_U3003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U3004(net_U3004_Pad1, WL16_n, __A03_1__WSQG_n, net_U3004_Pad4, WL14_n, __A03_1__WSQG_n, GND, WL13_n, __A03_1__WSQG_n, net_U3004_Pad10, net_U3004_Pad11, net_U3004_Pad12, net_U3004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3005(net_U3003_Pad9, GOJAM, MTCSAI, net_U3005_Pad4, NISQL_n, T12_n, GND, STRTFC, net_U3005_Pad4, net_U3005_Pad10, net_U3005_Pad10, net_U3005_Pad12, net_U3005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U3006(EXTPLS, EXT, net_U3005_Pad12, __A03_1__INKBT1, STRTFC, FUTEXT, GND, net_U3003_Pad11, __A03_1__RPTFRC, net_U3005_Pad13, net_U3003_Pad13, net_U3005_Pad12, FUTEXT, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b1) U3007(net_U3007_Pad1, net_U3005_Pad10, FUTEXT, net_U3003_Pad13, net_U3003_Pad11, net_U3007_Pad1, GND, INHPLS, __A03_1__INHINT, net_U3007_Pad10, KRPT, IIP, IIP_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3009(net_U3007_Pad10, RELPLS, IIP_n, GOJAM, n5XP4, IIP, GND, net_U3009_Pad8, FUTEXT, NISQL_n, T12_n, __A03_1__INHINT, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3010(PHS2_n, RUPTOR_n, __A03_1__OVNHRP, __A03_1__INHINT, IIP, net_U3010_Pad6, GND, net_U3010_Pad8, net_U3010_Pad9, STRTFC, T02, net_U3010_Pad12, MNHRPT, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U3011(net_U3009_Pad8, RPTSET, net_U3010_Pad12, RPTSET, net_U3010_Pad6, RPTSET, GND, __A03_2__IC13_n, net_U3011_Pad9, __A03_2__IC13_n, net_U3011_Pad11, , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10
U74HC02 #(1'b1, 1'b1, 1'b1, 1'b1) U3012(net_U3010_Pad9, RPTSET, net_U3010_Pad8, net_U3012_Pad4, net_U3004_Pad1, __A03_1__SQR16, GND, net_U3004_Pad4, __A03_1__SQR14, net_U3012_Pad10, net_U3004_Pad10, __A03_1__SQR13, net_U3012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3013(net_U3012_Pad4, __A03_1__RPTFRC, net_U3012_Pad10, __A03_1__RPTFRC, __A03_1__CSQG, __A03_1__SQR14, GND, __A03_1__SQR13, net_U3012_Pad13, __A03_1__RPTFRC, __A03_1__CSQG, __A03_1__SQR16, __A03_1__CSQG, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U3014(net_U3014_Pad1, net_U3012_Pad4, INKL, net_U3014_Pad4, INKL, __A03_1__SQR16, GND, net_U3014_Pad13, __A03_1__OVNHRP, net_U3014_Pad10, net_U3004_Pad13, NISQ_n, net_U3014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U3015(net_U3015_Pad1, net_U3015_Pad2, net_U3012_Pad13, net_U3015_Pad2, net_U3015_Pad11, net_U3015_Pad6, GND, net_U3015_Pad8, net_U3015_Pad1, net_U3012_Pad10, net_U3015_Pad11, net_U3015_Pad12, net_U3015_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3016(net_U3012_Pad13, net_U3012_Pad10, net_U3015_Pad1, net_U3015_Pad2, net_U3016_Pad11, net_U3016_Pad6, GND, net_U3016_Pad8, net_U3012_Pad13, net_U3015_Pad2, net_U3016_Pad11, net_U3016_Pad12, net_U3015_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b0, 1'b1) U3017(net_U3015_Pad1, net_U3016_Pad11, net_U3012_Pad13, net_U3012_Pad10, net_U3016_Pad11, net_U3017_Pad6, GND, net_U3017_Pad8, __A03_1__RPTFRC, net_U3017_Pad10, __A03_1__SQR12, net_U3017_Pad12, net_U3012_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3018(net_U3015_Pad6, SQ1_n, net_U3015_Pad8, SQ2_n, net_U3016_Pad12, __A03_1__SQ3_n, GND, __A03_1__SQ4_n, net_U3016_Pad6, __A03_1__SQ6_n, net_U3017_Pad12, __A03_1__SQ7_n, net_U3017_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3019(net_U3017_Pad10, WL12_n, __A03_1__WSQG_n, net_U3019_Pad4, WL11_n, __A03_1__WSQG_n, GND, net_U3017_Pad8, __A03_1__CSQG, __A03_1__SQR12, net_U3019_Pad11, __A03_1__CSQG, __A03_1__SQR11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b1, 1'b0) U3020(__A03_1__RPTFRC, net_U3019_Pad4, __A03_1__RPTFRC, net_U3020_Pad4, net_U3020_Pad5, net_U3020_Pad6, GND, __A03_1__INKBT1, INKL, T01_n, STD2, net_U3019_Pad11, __A03_1__SQR11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3021(A16_n, net_U3021_Pad2, A15_n, net_U3021_Pad4, , , GND, SQR12_n, __A03_1__SQR12, __A03_1__RPTFRC, net_U3010_Pad9, __A03_1__SQ5_n, net_U3016_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3022(__A03_1__QC0, __A03_1__SQR11, __A03_1__SQR12, net_U3022_Pad4, net_U3019_Pad11, __A03_1__SQR12, GND, __A03_1__SQR11, net_U3017_Pad8, net_U3022_Pad10, net_U3017_Pad8, net_U3019_Pad11, net_U3022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3023(__A03_1__QC0, QC0_n, net_U3022_Pad4, QC1_n, net_U3022_Pad10, QC2_n, GND, QC3_n, net_U3022_Pad13, SQR10, net_U3020_Pad6, SQR10_n, net_U3020_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3024(net_U3020_Pad4, WL10_n, __A03_1__WSQG_n, net_U3020_Pad5, net_U3020_Pad6, __A03_1__CSQG, GND, net_U3021_Pad2, A15_n, net_U3004_Pad11, A16_n, net_U3021_Pad4, net_U3004_Pad12, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3025(net_U3014_Pad1, net_U3016_Pad11, net_U3014_Pad4, net_U3015_Pad11, net_U3012_Pad10, net_U3015_Pad2, GND, net_U3015_Pad1, net_U3012_Pad13, SQ0_n, net_U3015_Pad12, MP3A, MP3_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3026(net_U3026_Pad1, __A03_1__SQ5_n, QC0_n, net_U3026_Pad4, __A03_1__SQ5_n, SQEXT_n, GND, net_U3026_Pad1, net_U3026_Pad4, net_U3026_Pad10, net_U3026_Pad10, ST0_n, IC1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U3027(net_U3026_Pad1, __A03_2__SQ5QC0_n, IC2, IC2_n, net_U3027_Pad5, EXST1_n, GND, TC0_n, TC0, IC3, __A03_2__IC3_n, __A03_2__NEXST0_n, __A03_2__NEXST0, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3028(IC2, net_U3026_Pad10, ST1_n, net_U3028_Pad4, SQEXT_n, __A03_1__QC0, GND, SQEXT_n, ST1_n, net_U3027_Pad5, net_U3027_Pad5, __A03_2__NEXST0, net_U3028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3029(net_U3028_Pad4, __A03_1__SQ6_n, SQ1_n, __A03_2__NEXST0_n, __A03_1__QC0, TCF0, GND, __A03_2__IC3_n, TC0, STD2, TCF0, IC11, ST0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3030(IC6, net_U3028_Pad13, __A03_1__SQ3_n, IC7, net_U3028_Pad13, __A03_1__SQ4_n, GND, SQ0_n, __A03_2__NEXST0_n, TC0, SQEXT, ST0_n, __A03_2__NEXST0, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3031(DCS0, __A03_1__SQ4_n, EXST0_n, DCA0, EXST0_n, __A03_1__SQ3_n, GND, DCS0, DCA0, __A03_2__IC4_n, QC1_n, ST1_n, net_U3031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3032(IC7, IC6, IC1, DCS0, DCA0, net_U3011_Pad11, GND, IC5, net_U3032_Pad9, __A03_1__SQ5_n, SQEXT, net_U3011_Pad9, IC11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3033(__A03_2__IC4_n, IC4, __A03_2__IC13_n, IC13, IC5, IC5_n, GND, IC9, __A03_2__IC9_n, QXCH0_n, __A03_2__QXCH0, EXST0_n, net_U3033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3034(net_U3034_Pad1, QC3_n, ST0_n, net_U3032_Pad9, net_U3031_Pad13, net_U3034_Pad1, GND, __A03_2__LXCH0, DXCH0, IC8_n, ST0_n, SQEXT_n, net_U3033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3035(__A03_2__NEXST0_n, QC1_n, SQ2_n, QC1_n, EXST0_n, __A03_2__QXCH0, GND, TS0, __A03_1__SQ5_n, QC2_n, __A03_2__NEXST0_n, __A03_2__LXCH0, SQ2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U3036(__A03_2__IC9_n, IC5, TS0, __A03_2__QXCH0, __A03_2__LXCH0, , GND, , SQ2_n, QC0_n, SQEXT, ST1_n, net_U3036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3037(TS0, TS0_n, IC10_n, IC10, DAS0, DAS0_n, GND, __A03_2__BZF0_n, __A03_2__BZF0, __A03_2__BMF0_n, __A03_2__BMF0, IC16, IC16_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3038(__A03_1__SQ5_n, __A03_2__NEXST0_n, SQ2_n, __A03_2__NEXST0_n, QC0_n, DAS0, GND, IC10_n, IC4, DXCH0, DAS0, DXCH0, QC1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3039(SQ1_n, __A03_1__QC0, EXST0_n, __A03_1__QC0, __A03_1__SQ6_n, __A03_2__BMF0, GND, CCS0, SQ1_n, QC0_n, __A03_2__NEXST0_n, __A03_2__BZF0, EXST0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3040(IC15_n, __A03_2__BMF0, __A03_2__BZF0, net_U3040_Pad11, __A03_2__BZF0_n, BR2_n, GND, __A03_2__BMF0_n, BR1B2B, net_U3040_Pad10, net_U3040_Pad11, net_U3040_Pad10, IC16_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U3041(IC17, IC16, IC15_n, DAS1_n, net_U3036_Pad13, ADS0, GND, CCS0, MSU0, IC12_n, __A03_1__SQ7_n, __A03_2__NEXST0_n, MASK0, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3042(IC15_n, IC15, CCS0, CCS0_n, DAS1_n, DAS1, GND, IC12, IC12_n, MSU0_n, MSU0, AUG0_n, __A03_2__AUG0, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b0, 1'b1) U3043(SQ2_n, QC3_n, QC2_n, SQ2_n, __A03_2__NEXST0_n, INCR0, GND, MSU0, SQ2_n, EXST0_n, QC0_n, ADS0, __A03_2__NEXST0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3044(SQ2_n, EXST0_n, SQ2_n, EXST0_n, QC3_n, __A03_2__DIM0, GND, MP3, ST3_n, __A03_1__SQ7_n, SQEXT_n, __A03_2__AUG0, QC2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0) U3045(__A03_2__DIM0, DIM0_n, MP3, MP3_n, MP1, MP1_n, GND, MP0_n, MP0, TCSAJ3_n, TCSAJ3, RSM3_n, RSM3, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3046(ST1_n, __A03_1__SQ7_n, ST0_n, __A03_1__SQ7_n, SQEXT_n, MP0, GND, TCSAJ3, SQ0_n, SQEXT, ST3_n, MP1, SQEXT_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3047(ST3_n, __A03_2__SQ5QC0_n, __A03_1__SQ6_n, EXST0_n, QC0_n, SU0, GND, net_U3047_Pad8, MP0, MASK0, RXOR0, RSM3, SQEXT, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U3048(MASK0, MASK0_n, net_U3047_Pad8, IC14, __A03_2__NDX0, NDX0_n, GND, NDXX1_n, __A03_2__NDXX1, GOJ1_n, GOJ1, IC11_n, IC11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U3049(AD0, __A03_2__NEXST0_n, __A03_1__SQ6_n, , , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3050(__A03_2__NEXST0_n, __A03_1__SQ5_n, SQEXT_n, __A03_1__SQ5_n, ST1_n, __A03_2__NDXX1, GND, GOJ1, SQEXT, ST1_n, SQ0_n, __A03_2__NDX0, QC0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U3052(net_U3014_Pad10, net_U3052_Pad2, net_U3004_Pad11, net_U3004_Pad12, NISQ_n, net_U3052_Pad2, GND, , , , , __A03_1__OVNHRP, MP3, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U3053(net_U3020_Pad6, MSQ10, net_U3007_Pad10, MINHL, IIP_n, MIIP, GND, MTCSA_n, TCSAJ3, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
U74LVC06 U3054(net_U3003_Pad11, MSQEXT, net_U3012_Pad4, MSQ16, net_U3012_Pad10, MSQ14, GND, MSQ13, net_U3012_Pad13, MSQ12, net_U3017_Pad8, MSQ11, net_U3019_Pad11, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
endmodule |
module four_bit_3(SIM_RST, SIM_CLK, p4VSW, GND, A2XG_n, CAG, CBG, CGG, CLG1G, CLXC, CQG, CUG, CZG, L2GDG_n, RAG_n, RCG_n, RGG_n, RLG_n, RQG_n, RZG_n, WAG_n, WALSG_n, WBG_n, WLG_n, WQG_n, WZG_n, CI09_n, CO10, MONEX, XUY13_n, XUY14_n, CH09, CH10, CH11, CH12, L08_n, G2LSG_n, G13_n, G14_n, G15_n, MDT09, MDT10, MDT11, MDT12, SA09, SA10, SA11, SA12, RBHG_n, RBLG_n, RULOG_n, WL13_n, WL14_n, WG1G_n, WG3G_n, WG4G_n, WYDG_n, WYLOG_n, R1C, WL08_n, WHOMP, WHOMPA, CI13_n, CO14, G09, G09_n, G10, G10_n, G11, G11_n, G12, L12_n, RL09_n, RL10_n, RL11_n, RL12_n, SUMA11_n, SUMB11_n, SUMA12_n, SUMB12_n, WL09, WL09_n, WL10, WL10_n, WL11, WL11_n, WL12, WL12_n, XUY09_n, XUY10_n, GEM09, GEM10, GEM11, GEM12, MWL09, MWL10, MWL11, MWL12);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire A2XG_n;
input wire CAG;
input wire CBG;
input wire CGG;
input wire CH09;
input wire CH10;
input wire CH11;
input wire CH12;
input wire CI09_n;
output wire CI13_n;
input wire CLG1G;
input wire CLXC;
input wire CO10;
output wire CO14; //FPGA#wand
input wire CQG;
input wire CUG;
input wire CZG;
output wire G09;
inout wire G09_n; //FPGA#wand
output wire G10;
inout wire G10_n; //FPGA#wand
output wire G11;
inout wire G11_n; //FPGA#wand
output wire G12;
input wire G13_n;
input wire G14_n;
input wire G15_n;
input wire G2LSG_n;
output wire GEM09;
output wire GEM10;
output wire GEM11;
output wire GEM12;
input wire L08_n;
inout wire L12_n; //FPGA#wand
input wire L2GDG_n;
input wire MDT09;
input wire MDT10;
input wire MDT11;
input wire MDT12;
input wire MONEX;
output wire MWL09; //FPGA#wand
output wire MWL10; //FPGA#wand
output wire MWL11; //FPGA#wand
output wire MWL12; //FPGA#wand
input wire R1C;
input wire RAG_n;
input wire RBHG_n;
input wire RBLG_n;
input wire RCG_n;
input wire RGG_n;
inout wire RL09_n; //FPGA#wand
inout wire RL10_n; //FPGA#wand
inout wire RL11_n; //FPGA#wand
inout wire RL12_n; //FPGA#wand
input wire RLG_n;
input wire RQG_n;
input wire RULOG_n;
input wire RZG_n;
input wire SA09;
input wire SA10;
input wire SA11;
input wire SA12;
output wire SUMA11_n;
output wire SUMA12_n;
output wire SUMB11_n;
output wire SUMB12_n;
input wire WAG_n;
input wire WALSG_n;
input wire WBG_n;
input wire WG1G_n;
input wire WG3G_n;
input wire WG4G_n;
input wire WHOMP;
input wire WHOMPA;
input wire WL08_n;
output wire WL09;
output wire WL09_n;
output wire WL10;
output wire WL10_n;
output wire WL11;
output wire WL11_n;
output wire WL12;
output wire WL12_n;
input wire WL13_n;
input wire WL14_n;
input wire WLG_n;
input wire WQG_n;
input wire WYDG_n;
input wire WYLOG_n;
input wire WZG_n;
output wire XUY09_n;
output wire XUY10_n;
input wire XUY13_n;
input wire XUY14_n;
wire __A10_1__X1;
wire __A10_1__X1_n;
wire __A10_1__X2;
wire __A10_1__X2_n;
wire __A10_1__Y1;
wire __A10_1__Y1_n;
wire __A10_1__Y2;
wire __A10_1__Y2_n;
wire __A10_1___A1_n;
wire __A10_1___A2_n;
wire __A10_1___B1_n;
wire __A10_1___B2_n;
wire __A10_1___CI_INTERNAL;
wire __A10_1___Q1_n;
wire __A10_1___Q2_n;
wire __A10_1___RL_OUT_1;
wire __A10_1___RL_OUT_2;
wire __A10_1___SUMA1;
wire __A10_1___SUMA2;
wire __A10_1___SUMB1;
wire __A10_1___SUMB2;
wire __A10_1___Z1_n; //FPGA#wand
wire __A10_1___Z2_n; //FPGA#wand
wire __A10_2__X1;
wire __A10_2__X1_n;
wire __A10_2__X2;
wire __A10_2__X2_n;
wire __A10_2__Y1;
wire __A10_2__Y1_n;
wire __A10_2__Y2;
wire __A10_2__Y2_n;
wire __A10_2___A1_n;
wire __A10_2___A2_n;
wire __A10_2___B1_n;
wire __A10_2___B2_n;
wire __A10_2___CI_INTERNAL;
wire __A10_2___Q1_n;
wire __A10_2___Q2_n;
wire __A10_2___RL_OUT_1;
wire __A10_2___RL_OUT_2;
wire __A10_2___Z1_n; //FPGA#wand
wire __A10_2___Z2_n; //FPGA#wand
wire __CI11_n;
wire __CO12; //FPGA#wand
wire __G12_n; //FPGA#wand
wire __L09_n; //FPGA#wand
wire __L10_n; //FPGA#wand
wire __L11_n; //FPGA#wand
wire __XUY11_n;
wire __XUY12_n;
wire net_U10001_Pad1;
wire net_U10001_Pad10;
wire net_U10001_Pad4;
wire net_U10003_Pad1;
wire net_U10003_Pad10;
wire net_U10004_Pad1;
wire net_U10004_Pad12;
wire net_U10004_Pad13;
wire net_U10004_Pad2;
wire net_U10004_Pad6;
wire net_U10004_Pad8;
wire net_U10005_Pad12;
wire net_U10005_Pad2;
wire net_U10006_Pad10;
wire net_U10006_Pad13;
wire net_U10006_Pad4;
wire net_U10007_Pad11;
wire net_U10007_Pad13;
wire net_U10007_Pad3;
wire net_U10007_Pad5;
wire net_U10007_Pad9;
wire net_U10008_Pad1;
wire net_U10008_Pad10;
wire net_U10008_Pad13;
wire net_U10008_Pad4;
wire net_U10009_Pad1;
wire net_U10009_Pad13;
wire net_U10009_Pad4;
wire net_U10010_Pad1;
wire net_U10010_Pad13;
wire net_U10010_Pad4;
wire net_U10011_Pad10;
wire net_U10011_Pad11;
wire net_U10011_Pad13;
wire net_U10011_Pad8;
wire net_U10011_Pad9;
wire net_U10012_Pad13;
wire net_U10012_Pad4;
wire net_U10013_Pad1;
wire net_U10013_Pad11;
wire net_U10013_Pad13;
wire net_U10013_Pad5;
wire net_U10013_Pad9;
wire net_U10014_Pad10;
wire net_U10014_Pad13;
wire net_U10016_Pad1;
wire net_U10016_Pad4;
wire net_U10018_Pad11;
wire net_U10018_Pad12;
wire net_U10018_Pad13;
wire net_U10019_Pad1;
wire net_U10019_Pad10;
wire net_U10019_Pad4;
wire net_U10021_Pad1;
wire net_U10021_Pad13;
wire net_U10022_Pad1;
wire net_U10022_Pad12;
wire net_U10022_Pad8;
wire net_U10023_Pad10;
wire net_U10023_Pad13;
wire net_U10023_Pad4;
wire net_U10024_Pad10;
wire net_U10024_Pad11;
wire net_U10024_Pad4;
wire net_U10024_Pad9;
wire net_U10026_Pad4;
wire net_U10026_Pad5;
wire net_U10026_Pad6;
wire net_U10026_Pad8;
wire net_U10027_Pad1;
wire net_U10027_Pad10;
wire net_U10028_Pad13;
wire net_U10028_Pad3;
wire net_U10028_Pad9;
wire net_U10029_Pad1;
wire net_U10029_Pad10;
wire net_U10030_Pad1;
wire net_U10030_Pad10;
wire net_U10030_Pad13;
wire net_U10031_Pad13;
wire net_U10031_Pad2;
wire net_U10031_Pad3;
wire net_U10031_Pad4;
wire net_U10031_Pad8;
wire net_U10035_Pad1;
wire net_U10035_Pad10;
wire net_U10035_Pad4;
wire net_U10037_Pad1;
wire net_U10037_Pad10;
wire net_U10038_Pad1;
wire net_U10038_Pad12;
wire net_U10038_Pad2;
wire net_U10038_Pad6;
wire net_U10038_Pad8;
wire net_U10039_Pad12;
wire net_U10039_Pad2;
wire net_U10040_Pad10;
wire net_U10040_Pad13;
wire net_U10040_Pad4;
wire net_U10041_Pad11;
wire net_U10041_Pad13;
wire net_U10041_Pad3;
wire net_U10041_Pad5;
wire net_U10041_Pad9;
wire net_U10042_Pad10;
wire net_U10042_Pad11;
wire net_U10042_Pad4;
wire net_U10042_Pad9;
wire net_U10044_Pad1;
wire net_U10044_Pad6;
wire net_U10045_Pad13;
wire net_U10045_Pad4;
wire net_U10046_Pad1;
wire net_U10046_Pad13;
wire net_U10046_Pad4;
wire net_U10047_Pad1;
wire net_U10047_Pad13;
wire net_U10047_Pad4;
wire net_U10048_Pad1;
wire net_U10048_Pad10;
wire net_U10048_Pad13;
wire net_U10048_Pad4;
wire net_U10049_Pad11;
wire net_U10049_Pad8;
wire net_U10050_Pad11;
wire net_U10050_Pad13;
wire net_U10050_Pad5;
wire net_U10052_Pad11;
wire net_U10052_Pad12;
wire net_U10052_Pad13;
wire net_U10053_Pad1;
wire net_U10053_Pad10;
wire net_U10053_Pad4;
wire net_U10055_Pad13;
wire net_U10056_Pad10;
wire net_U10056_Pad13;
wire net_U10056_Pad4;
wire net_U10057_Pad10;
wire net_U10057_Pad11;
wire net_U10057_Pad4;
wire net_U10057_Pad9;
wire net_U10059_Pad4;
wire net_U10059_Pad5;
wire net_U10059_Pad6;
wire net_U10059_Pad8;
wire net_U10060_Pad1;
wire net_U10060_Pad10;
wire net_U10061_Pad3;
wire net_U10062_Pad1;
wire net_U10062_Pad10;
wire net_U10063_Pad1;
wire net_U10063_Pad10;
pullup R10001(__CO12);
pullup R10002(RL09_n);
pullup R10003(__L09_n);
pullup R10005(__A10_1___Z1_n);
pullup R10006(G09_n);
pullup R10007(RL10_n);
pullup R10008(__L10_n);
pullup R10009(__A10_1___Z2_n);
pullup R10010(G10_n);
pullup R10011(CO14);
pullup R10012(RL11_n);
pullup R10013(__L11_n);
pullup R10015(__A10_2___Z1_n);
pullup R10016(G11_n);
pullup R10017(RL12_n);
pullup R10018(L12_n);
pullup R10019(__A10_2___Z2_n);
pullup R10020(__G12_n);
U74HC02 U10001(net_U10001_Pad1, A2XG_n, __A10_1___A1_n, net_U10001_Pad4, WYLOG_n, WL09_n, GND, WL08_n, WYDG_n, net_U10001_Pad10, __A10_1__Y1_n, CUG, __A10_1__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10002(MONEX, net_U10001_Pad1, __A10_1__X1_n, CLXC, CUG, __A10_1__X1, GND, __A10_1__Y1_n, net_U10001_Pad4, net_U10001_Pad10, __A10_1__Y1, __A10_1__X1_n, __A10_1__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10003(net_U10003_Pad1, __A10_1__X1_n, __A10_1__Y1_n, XUY09_n, __A10_1__X1, __A10_1__Y1, GND, net_U10003_Pad1, XUY09_n, net_U10003_Pad10, net_U10003_Pad1, __A10_1___SUMA1, __A10_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10004(net_U10004_Pad1, net_U10004_Pad2, __A10_1___SUMA1, __A10_1___SUMB1, RULOG_n, net_U10004_Pad6, GND, net_U10004_Pad8, __XUY11_n, XUY09_n, CI09_n, net_U10004_Pad12, net_U10004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U10005(CI09_n, net_U10005_Pad2, G09_n, GEM09, RL09_n, WL09, GND, WL09_n, WL09, , , net_U10005_Pad12, __A10_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10006(__A10_1___SUMB1, net_U10003_Pad10, net_U10005_Pad2, net_U10006_Pad4, WAG_n, WL09_n, GND, WL11_n, WALSG_n, net_U10006_Pad10, __A10_1___A1_n, CAG, net_U10006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10007(net_U10004_Pad8, __CO12, net_U10007_Pad3, RL09_n, net_U10007_Pad5, __L09_n, GND, __A10_1___Z1_n, net_U10007_Pad9, RL09_n, net_U10007_Pad11, RL09_n, net_U10007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U10008(net_U10008_Pad1, RAG_n, __A10_1___A1_n, net_U10008_Pad4, WLG_n, WL09_n, GND, __G12_n, G2LSG_n, net_U10008_Pad10, __L09_n, CLG1G, net_U10008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10009(net_U10009_Pad1, WG1G_n, WL12_n, net_U10009_Pad4, WQG_n, WL09_n, GND, net_U10009_Pad4, net_U10009_Pad13, __A10_1___Q1_n, __A10_1___Q1_n, CQG, net_U10009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10010(net_U10010_Pad1, RQG_n, __A10_1___Q1_n, net_U10010_Pad4, WZG_n, WL09_n, GND, net_U10010_Pad4, net_U10010_Pad13, net_U10007_Pad9, __A10_1___Z1_n, CZG, net_U10010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10011(__A10_1___RL_OUT_1, net_U10010_Pad1, MDT09, R1C, GND, net_U10007_Pad13, GND, net_U10011_Pad8, net_U10011_Pad9, net_U10011_Pad10, net_U10011_Pad11, net_U10007_Pad11, net_U10011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10012(net_U10011_Pad13, RZG_n, __A10_1___Z1_n, net_U10012_Pad4, WBG_n, WL09_n, GND, net_U10012_Pad4, net_U10012_Pad13, __A10_1___B1_n, __A10_1___B1_n, CBG, net_U10012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10013(net_U10013_Pad1, __CO12, net_U10011_Pad8, RL09_n, net_U10013_Pad5, G09_n, GND, G09_n, net_U10013_Pad9, RL10_n, net_U10013_Pad11, __L10_n, net_U10013_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U10014(net_U10011_Pad9, RBLG_n, __A10_1___B1_n, net_U10011_Pad10, net_U10012_Pad13, RCG_n, GND, WL08_n, WG3G_n, net_U10014_Pad10, WL10_n, WG4G_n, net_U10014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10015(net_U10006_Pad4, net_U10006_Pad10, net_U10004_Pad6, net_U10008_Pad1, CH09, net_U10007_Pad3, GND, net_U10007_Pad5, net_U10008_Pad4, net_U10008_Pad10, net_U10008_Pad13, __A10_1___A1_n, net_U10006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10016(net_U10016_Pad1, L2GDG_n, L08_n, net_U10016_Pad4, WG1G_n, WL09_n, GND, G09_n, CGG, G09, RGG_n, G09_n, net_U10011_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U10017(net_U10016_Pad1, net_U10016_Pad4, WHOMPA, __XUY12_n, XUY10_n, net_U10013_Pad1, GND, __A10_1___RL_OUT_1, RLG_n, __L09_n, GND, net_U10013_Pad9, G09, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U10018(net_U10013_Pad5, GND, SA09, net_U10014_Pad10, net_U10014_Pad13, , GND, , GND, SA10, net_U10018_Pad11, net_U10018_Pad12, net_U10018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10019(net_U10019_Pad1, A2XG_n, __A10_1___A2_n, net_U10019_Pad4, WYLOG_n, WL10_n, GND, WL09_n, WYDG_n, net_U10019_Pad10, __A10_1__Y2_n, CUG, __A10_1__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10020(MONEX, net_U10019_Pad1, __A10_1__X2_n, CLXC, CUG, __A10_1__X2, GND, __A10_1__Y2_n, net_U10019_Pad4, net_U10019_Pad10, __A10_1__Y2, __A10_1__X2_n, __A10_1__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10021(net_U10021_Pad1, __A10_1__X2_n, __A10_1__Y2_n, XUY10_n, __A10_1__X2, __A10_1__Y2, GND, __G12_n, CGG, G12, net_U10021_Pad1, XUY10_n, net_U10021_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U10022(net_U10022_Pad1, net_U10009_Pad1, net_U10021_Pad1, __A10_1___SUMA2, CO10, __CI11_n, GND, net_U10022_Pad8, __A10_1___SUMA2, __A10_1___SUMB2, RULOG_n, net_U10022_Pad12, G12, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10023(__A10_1___SUMB2, net_U10021_Pad13, net_U10005_Pad12, net_U10023_Pad4, WAG_n, WL10_n, GND, WL12_n, WALSG_n, net_U10023_Pad10, __A10_1___A2_n, CAG, net_U10023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10024(net_U10023_Pad4, net_U10023_Pad10, net_U10022_Pad8, net_U10024_Pad4, CH10, net_U10013_Pad11, GND, net_U10013_Pad13, net_U10024_Pad9, net_U10024_Pad10, net_U10024_Pad11, __A10_1___A2_n, net_U10023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10025(net_U10024_Pad4, RAG_n, __A10_1___A2_n, net_U10024_Pad9, WLG_n, WL10_n, GND, G13_n, G2LSG_n, net_U10024_Pad10, __L10_n, CLG1G, net_U10024_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10026(RLG_n, __L10_n, __A10_1___RL_OUT_2, net_U10026_Pad4, net_U10026_Pad5, net_U10026_Pad6, GND, net_U10026_Pad8, MDT10, R1C, GND, __A10_1___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10027(net_U10027_Pad1, WQG_n, WL10_n, __A10_1___Q2_n, net_U10027_Pad1, net_U10027_Pad10, GND, __A10_1___Q2_n, CQG, net_U10027_Pad10, RQG_n, __A10_1___Q2_n, net_U10026_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10028(net_U10026_Pad6, RL10_n, net_U10028_Pad3, __A10_1___Z2_n, net_U10026_Pad8, RL10_n, GND, RL10_n, net_U10028_Pad9, G10_n, net_U10018_Pad13, G10_n, net_U10028_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10029(net_U10029_Pad1, WZG_n, WL10_n, net_U10028_Pad3, net_U10029_Pad1, net_U10029_Pad10, GND, __A10_1___Z2_n, CZG, net_U10029_Pad10, RZG_n, __A10_1___Z2_n, net_U10026_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10030(net_U10030_Pad1, WBG_n, WL10_n, __A10_1___B2_n, net_U10030_Pad1, net_U10030_Pad10, GND, __A10_1___B2_n, CBG, net_U10030_Pad10, RBLG_n, __A10_1___B2_n, net_U10030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U10031(net_U10030_Pad13, net_U10031_Pad2, net_U10031_Pad3, net_U10031_Pad4, G10, net_U10028_Pad13, GND, net_U10031_Pad8, GND, XUY14_n, __XUY12_n, net_U10028_Pad9, net_U10031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10032(net_U10031_Pad2, net_U10030_Pad10, RCG_n, net_U10018_Pad11, WL09_n, WG3G_n, GND, WL11_n, WG4G_n, net_U10018_Pad12, L2GDG_n, __L09_n, net_U10031_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10033(net_U10031_Pad4, WG1G_n, WL10_n, G10, G10_n, CGG, GND, RGG_n, G10_n, net_U10031_Pad13, RGG_n, __G12_n, net_U10004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U10034(G10_n, GEM10, RL10_n, WL10, WL10, WL10_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10035(net_U10035_Pad1, A2XG_n, __A10_2___A1_n, net_U10035_Pad4, WYLOG_n, WL11_n, GND, WL10_n, WYDG_n, net_U10035_Pad10, __A10_2__Y1_n, CUG, __A10_2__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10036(MONEX, net_U10035_Pad1, __A10_2__X1_n, CLXC, CUG, __A10_2__X1, GND, __A10_2__Y1_n, net_U10035_Pad4, net_U10035_Pad10, __A10_2__Y1, __A10_2__X1_n, __A10_2__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10037(net_U10037_Pad1, __A10_2__X1_n, __A10_2__Y1_n, __XUY11_n, __A10_2__X1, __A10_2__Y1, GND, net_U10037_Pad1, __XUY11_n, net_U10037_Pad10, net_U10037_Pad1, SUMA11_n, __A10_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U10038(net_U10038_Pad1, net_U10038_Pad2, SUMA11_n, SUMB11_n, RULOG_n, net_U10038_Pad6, GND, net_U10038_Pad8, XUY13_n, __XUY11_n, __CI11_n, net_U10038_Pad12, G11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U10039(__CI11_n, net_U10039_Pad2, G11_n, GEM11, RL11_n, WL11, GND, WL11_n, WL11, , , net_U10039_Pad12, __A10_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10040(SUMB11_n, net_U10037_Pad10, net_U10039_Pad2, net_U10040_Pad4, WAG_n, WL11_n, GND, WL13_n, WALSG_n, net_U10040_Pad10, __A10_2___A1_n, CAG, net_U10040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10041(net_U10038_Pad8, CO14, net_U10041_Pad3, RL11_n, net_U10041_Pad5, __L11_n, GND, __A10_2___Z1_n, net_U10041_Pad9, RL11_n, net_U10041_Pad11, RL11_n, net_U10041_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 #(1'b1, 1'b0, 1'b1) U10042(net_U10040_Pad4, net_U10040_Pad10, net_U10038_Pad6, net_U10042_Pad4, CH11, net_U10041_Pad3, GND, net_U10041_Pad5, net_U10042_Pad9, net_U10042_Pad10, net_U10042_Pad11, __A10_2___A1_n, net_U10040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10043(net_U10042_Pad4, RAG_n, __A10_2___A1_n, net_U10042_Pad9, WLG_n, WL11_n, GND, G14_n, G2LSG_n, net_U10042_Pad10, __L11_n, CLG1G, net_U10042_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10044(net_U10044_Pad1, SUMA12_n, SUMA12_n, SUMB12_n, RULOG_n, net_U10044_Pad6, GND, __A10_2___RL_OUT_1, RLG_n, __L11_n, GND, CI13_n, __CO12, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10045( , , , net_U10045_Pad4, WQG_n, WL11_n, GND, net_U10045_Pad4, net_U10045_Pad13, __A10_2___Q1_n, __A10_2___Q1_n, CQG, net_U10045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10046(net_U10046_Pad1, RQG_n, __A10_2___Q1_n, net_U10046_Pad4, WZG_n, WL11_n, GND, net_U10046_Pad4, net_U10046_Pad13, net_U10041_Pad9, __A10_2___Z1_n, CZG, net_U10046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U10047(net_U10047_Pad1, RZG_n, __A10_2___Z1_n, net_U10047_Pad4, WBG_n, WL11_n, GND, net_U10047_Pad4, net_U10047_Pad13, __A10_2___B1_n, __A10_2___B1_n, CBG, net_U10047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10048(net_U10048_Pad1, RBHG_n, __A10_2___B1_n, net_U10048_Pad4, net_U10047_Pad13, RCG_n, GND, WL10_n, WG3G_n, net_U10048_Pad10, WL12_n, WG4G_n, net_U10048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10049(__A10_2___RL_OUT_1, net_U10046_Pad1, MDT11, R1C, GND, net_U10041_Pad13, GND, net_U10049_Pad8, net_U10048_Pad1, net_U10048_Pad4, net_U10049_Pad11, net_U10041_Pad11, net_U10047_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10050(net_U10031_Pad8, CO14, net_U10049_Pad8, RL11_n, net_U10050_Pad5, G11_n, GND, G11_n, net_U10038_Pad12, RL12_n, net_U10050_Pad11, L12_n, net_U10050_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U10051(net_U10038_Pad1, L2GDG_n, __L10_n, net_U10038_Pad2, WG1G_n, WL11_n, GND, G11_n, CGG, G11, RGG_n, G11_n, net_U10049_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U10052(net_U10050_Pad5, GND, SA11, net_U10048_Pad10, net_U10048_Pad13, , GND, , GND, SA12, net_U10052_Pad11, net_U10052_Pad12, net_U10052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10053(net_U10053_Pad1, A2XG_n, __A10_2___A2_n, net_U10053_Pad4, WYLOG_n, WL12_n, GND, WL11_n, WYDG_n, net_U10053_Pad10, __A10_2__Y2_n, CUG, __A10_2__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10054(MONEX, net_U10053_Pad1, __A10_2__X2_n, CLXC, CUG, __A10_2__X2, GND, __A10_2__Y2_n, net_U10053_Pad4, net_U10053_Pad10, __A10_2__Y2, __A10_2__X2_n, __A10_2__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10055(net_U10044_Pad1, __A10_2__X2_n, __A10_2__Y2_n, __XUY12_n, __A10_2__X2, __A10_2__Y2, GND, , , , net_U10044_Pad1, __XUY12_n, net_U10055_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10056(SUMB12_n, net_U10055_Pad13, net_U10039_Pad12, net_U10056_Pad4, WAG_n, WL12_n, GND, WL14_n, WALSG_n, net_U10056_Pad10, __A10_2___A2_n, CAG, net_U10056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U10057(net_U10056_Pad4, net_U10056_Pad10, net_U10044_Pad6, net_U10057_Pad4, CH12, net_U10050_Pad11, GND, net_U10050_Pad13, net_U10057_Pad9, net_U10057_Pad10, net_U10057_Pad11, __A10_2___A2_n, net_U10056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10058(net_U10057_Pad4, RAG_n, __A10_2___A2_n, net_U10057_Pad9, WLG_n, WL12_n, GND, G15_n, G2LSG_n, net_U10057_Pad10, L12_n, CLG1G, net_U10057_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U10059(RLG_n, L12_n, __A10_2___RL_OUT_2, net_U10059_Pad4, net_U10059_Pad5, net_U10059_Pad6, GND, net_U10059_Pad8, MDT12, R1C, GND, __A10_2___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10060(net_U10060_Pad1, WQG_n, WL12_n, __A10_2___Q2_n, net_U10060_Pad1, net_U10060_Pad10, GND, __A10_2___Q2_n, CQG, net_U10060_Pad10, RQG_n, __A10_2___Q2_n, net_U10059_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U10061(net_U10059_Pad6, RL12_n, net_U10061_Pad3, __A10_2___Z2_n, net_U10059_Pad8, RL12_n, GND, RL12_n, net_U10004_Pad12, __G12_n, net_U10052_Pad13, __G12_n, net_U10022_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10062(net_U10062_Pad1, WZG_n, WL12_n, net_U10061_Pad3, net_U10062_Pad1, net_U10062_Pad10, GND, __A10_2___Z2_n, CZG, net_U10062_Pad10, RZG_n, __A10_2___Z2_n, net_U10059_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U10063(net_U10063_Pad1, WBG_n, WL12_n, __A10_2___B2_n, net_U10063_Pad1, net_U10063_Pad10, GND, __A10_2___B2_n, CBG, net_U10063_Pad10, RBHG_n, __A10_2___B2_n, net_U10004_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U10064(net_U10004_Pad2, net_U10063_Pad10, RCG_n, net_U10052_Pad11, WL11_n, WG3G_n, GND, WL13_n, WG4G_n, net_U10052_Pad12, L2GDG_n, __L11_n, net_U10022_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U10065(__G12_n, GEM12, RL12_n, WL12, WL12, WL12_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U10066(__A10_1___SUMA1, net_U10003_Pad1, XUY09_n, CI09_n, GND, , GND, , net_U10021_Pad1, XUY10_n, __A10_1___CI_INTERNAL, GND, __A10_1___SUMA2, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U10067(SUMA11_n, net_U10037_Pad1, __XUY11_n, __CI11_n, GND, , GND, , net_U10044_Pad1, __XUY12_n, __A10_2___CI_INTERNAL, WHOMP, SUMA12_n, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U10068(RL09_n, MWL09, RL10_n, MWL10, RL11_n, MWL11, GND, MWL12, RL12_n, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
endmodule |
module inout_iii(SIM_RST, SIM_CLK, p4VDC, p4VSW, GND, GOJAM, STOP, T05, T11, F08B, FS09_n, F09A, F09B, F09B_n, F10A, F10A_n, F17A, F17B, SB0_n, SB2_n, F5ASB2_n, F5BSB2_n, CCH13, RCH13_n, WCH13_n, CHWL01_n, CHWL02_n, CHWL03_n, CHWL04_n, CHWL11_n, GTSET_n, GTRST_n, MKEY1, MKEY2, MKEY3, MKEY4, MKEY5, MAINRS, NKEY1, NKEY2, NKEY3, NKEY4, NKEY5, NAVRST, MARK, MRKREJ, MRKRST, SBYBUT, LRIN0, LRIN1, RRIN0, RRIN1, XT1_n, XB5_n, XB6_n, ALTEST, TPOR_n, SBY, STNDBY_n, SBYLIT, SBYREL_n, KYRPT1, KYRPT2, MKRPT, RADRPT, RNRADP, RNRADM, CH1301, CH1302, CH1303, CH1304, CH1311, CH1501, CH1502, CH1503, CH1504, CH1505, CH1601, CH1602, CH1603, CH1604, CH1605, CH1606, CH1607);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VDC;
input wire p4VSW;
input wire GND;
input wire ALTEST;
input wire CCH13;
output wire CH1301;
output wire CH1302;
output wire CH1303;
output wire CH1304;
output wire CH1311;
output wire CH1501;
output wire CH1502;
output wire CH1503;
output wire CH1504;
output wire CH1505;
output wire CH1601;
output wire CH1602;
output wire CH1603;
output wire CH1604;
output wire CH1605;
output wire CH1606;
output wire CH1607;
input wire CHWL01_n;
input wire CHWL02_n;
input wire CHWL03_n;
input wire CHWL04_n;
input wire CHWL11_n;
input wire F08B;
input wire F09A;
input wire F09B;
input wire F09B_n;
input wire F10A;
input wire F10A_n;
input wire F17A;
input wire F17B;
input wire F5ASB2_n;
input wire F5BSB2_n;
input wire FS09_n;
input wire GOJAM;
input wire GTRST_n;
input wire GTSET_n;
output wire KYRPT1;
output wire KYRPT2;
input wire LRIN0;
input wire LRIN1;
input wire MAINRS;
input wire MARK;
input wire MKEY1;
input wire MKEY2;
input wire MKEY3;
input wire MKEY4;
input wire MKEY5;
output wire MKRPT;
input wire MRKREJ;
input wire MRKRST;
input wire NAVRST;
input wire NKEY1;
input wire NKEY2;
input wire NKEY3;
input wire NKEY4;
input wire NKEY5;
output wire RADRPT;
input wire RCH13_n;
output wire RNRADM;
output wire RNRADP;
input wire RRIN0;
input wire RRIN1;
input wire SB0_n;
input wire SB2_n;
output wire SBY;
input wire SBYBUT;
output wire SBYLIT;
output wire SBYREL_n;
output wire STNDBY_n;
input wire STOP;
input wire T05;
input wire T11;
output wire TPOR_n;
input wire WCH13_n;
input wire XB5_n;
input wire XB6_n;
input wire XT1_n;
wire __A18_1__F08B_n;
wire __A18_1__F09A_n;
wire __A18_1__F09D;
wire __A18_1__F17A_n;
wire __A18_1__F17B_n;
wire __A18_1__RCH15_n;
wire __A18_1__RCH16_n;
wire __A18_1__STNDBY;
wire __A18_2__ACTV_n;
wire __A18_2__ADVCNT;
wire __A18_2__CNTOF9; //FPGA#wand
wire __A18_2__F10AS0;
wire __A18_2__HERB;
wire __A18_2__LRRANG;
wire __A18_2__LRSYNC;
wire __A18_2__LRXVEL;
wire __A18_2__LRYVEL;
wire __A18_2__LRZVEL;
wire __A18_2__RRRANG;
wire __A18_2__RRRARA;
wire __A18_2__RRSYNC;
wire net_R18001_Pad2; //FPGA#wand
wire net_R18002_Pad2; //FPGA#wand
wire net_U18001_Pad1;
wire net_U18001_Pad12;
wire net_U18001_Pad13;
wire net_U18001_Pad3;
wire net_U18001_Pad6;
wire net_U18002_Pad10;
wire net_U18002_Pad11;
wire net_U18002_Pad12;
wire net_U18002_Pad2;
wire net_U18002_Pad4;
wire net_U18002_Pad5;
wire net_U18002_Pad6;
wire net_U18002_Pad8;
wire net_U18002_Pad9;
wire net_U18003_Pad13;
wire net_U18004_Pad10;
wire net_U18005_Pad13;
wire net_U18005_Pad3;
wire net_U18006_Pad10;
wire net_U18006_Pad12;
wire net_U18006_Pad6;
wire net_U18007_Pad11;
wire net_U18007_Pad13;
wire net_U18007_Pad5;
wire net_U18007_Pad9;
wire net_U18008_Pad10;
wire net_U18008_Pad11;
wire net_U18008_Pad13;
wire net_U18008_Pad3;
wire net_U18008_Pad6;
wire net_U18009_Pad2;
wire net_U18009_Pad3;
wire net_U18009_Pad8;
wire net_U18010_Pad12;
wire net_U18010_Pad13;
wire net_U18010_Pad5;
wire net_U18011_Pad1;
wire net_U18011_Pad10;
wire net_U18012_Pad1;
wire net_U18012_Pad12;
wire net_U18012_Pad13;
wire net_U18012_Pad3;
wire net_U18013_Pad10;
wire net_U18013_Pad11;
wire net_U18013_Pad12;
wire net_U18013_Pad2;
wire net_U18013_Pad4;
wire net_U18013_Pad5;
wire net_U18013_Pad6;
wire net_U18013_Pad8;
wire net_U18013_Pad9;
wire net_U18014_Pad13;
wire net_U18015_Pad10;
wire net_U18016_Pad3;
wire net_U18017_Pad10;
wire net_U18017_Pad6;
wire net_U18018_Pad13;
wire net_U18018_Pad4;
wire net_U18023_Pad10;
wire net_U18023_Pad6;
wire net_U18025_Pad10;
wire net_U18025_Pad11;
wire net_U18025_Pad2;
wire net_U18025_Pad4;
wire net_U18025_Pad5;
wire net_U18025_Pad6;
wire net_U18025_Pad8;
wire net_U18025_Pad9;
wire net_U18026_Pad13;
wire net_U18026_Pad3;
wire net_U18027_Pad11;
wire net_U18027_Pad12;
wire net_U18027_Pad13;
wire net_U18028_Pad12;
wire net_U18028_Pad13;
wire net_U18028_Pad5;
wire net_U18028_Pad9;
wire net_U18029_Pad10;
wire net_U18029_Pad11;
wire net_U18029_Pad8;
wire net_U18029_Pad9;
wire net_U18030_Pad1;
wire net_U18030_Pad10;
wire net_U18030_Pad11;
wire net_U18031_Pad10;
wire net_U18031_Pad11;
wire net_U18031_Pad12;
wire net_U18031_Pad3;
wire net_U18031_Pad4;
wire net_U18031_Pad5;
wire net_U18031_Pad8;
wire net_U18031_Pad9;
wire net_U18032_Pad1;
wire net_U18032_Pad13;
wire net_U18033_Pad13;
wire net_U18034_Pad1;
wire net_U18034_Pad13;
wire net_U18034_Pad3;
wire net_U18035_Pad1;
wire net_U18035_Pad3;
wire net_U18036_Pad10;
wire net_U18036_Pad12;
wire net_U18036_Pad13;
wire net_U18036_Pad3;
wire net_U18037_Pad11;
wire net_U18037_Pad8;
wire net_U18037_Pad9;
wire net_U18038_Pad12;
wire net_U18038_Pad13;
wire net_U18038_Pad4;
wire net_U18039_Pad12;
wire net_U18039_Pad13;
wire net_U18039_Pad9;
wire net_U18040_Pad10;
wire net_U18040_Pad12;
wire net_U18040_Pad13;
wire net_U18041_Pad3;
wire net_U18041_Pad5;
wire net_U18041_Pad6;
wire net_U18042_Pad12;
wire net_U18042_Pad13;
wire net_U18042_Pad4;
wire net_U18044_Pad10;
wire net_U18044_Pad13;
wire net_U18044_Pad9;
wire net_U18048_Pad1;
wire net_U18048_Pad10;
wire net_U18048_Pad12;
wire net_U18048_Pad13;
wire net_U18048_Pad4;
wire net_U18048_Pad6;
wire net_U18049_Pad9;
wire net_U18050_Pad10;
wire net_U18050_Pad12;
wire net_U18050_Pad5;
wire net_U18050_Pad8;
wire net_U18051_Pad10;
wire net_U18051_Pad4;
wire net_U18051_Pad5;
wire net_U18051_Pad6;
wire net_U18051_Pad8;
wire net_U18119_Pad1;
wire net_U18119_Pad10;
wire net_U18119_Pad11;
wire net_U18120_Pad13;
wire net_U18120_Pad2;
wire net_U18121_Pad1;
wire net_U18121_Pad10;
wire net_U18121_Pad12;
wire net_U18121_Pad13;
wire net_U18122_Pad1;
wire net_U18122_Pad10;
wire net_U18122_Pad13;
wire net_U18122_Pad3;
wire net_U18122_Pad8;
wire net_U18124_Pad1;
wire net_U18124_Pad4;
pullup R18001(net_R18001_Pad2);
pullup R18002(net_R18002_Pad2);
pullup R18003(__A18_2__CNTOF9);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U18001(net_U18001_Pad1, MKEY1, net_U18001_Pad3, net_U18001_Pad3, net_U18001_Pad1, net_U18001_Pad6, GND, net_U18001_Pad1, __A18_1__RCH15_n, CH1501, MKEY2, net_U18001_Pad12, net_U18001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U18002(net_U18001_Pad1, net_U18002_Pad2, net_U18001_Pad13, net_U18002_Pad4, net_U18002_Pad5, net_U18002_Pad6, GND, net_U18002_Pad8, net_U18002_Pad9, net_U18002_Pad10, net_U18002_Pad11, net_U18002_Pad12, MAINRS, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18003(net_U18001_Pad12, net_U18001_Pad13, net_U18001_Pad6, CH1502, net_U18001_Pad13, __A18_1__RCH15_n, GND, MKEY3, net_U18003_Pad13, net_U18002_Pad5, net_U18002_Pad5, net_U18001_Pad6, net_U18003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18004(CH1503, net_U18002_Pad5, __A18_1__RCH15_n, net_U18002_Pad9, MKEY4, net_U18004_Pad10, GND, net_U18002_Pad9, net_U18001_Pad6, net_U18004_Pad10, net_U18002_Pad9, __A18_1__RCH15_n, CH1504, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18005(net_U18002_Pad11, MKEY5, net_U18005_Pad3, net_U18005_Pad3, net_U18002_Pad11, net_U18001_Pad6, GND, net_U18002_Pad11, __A18_1__RCH15_n, CH1505, net_U18002_Pad8, net_U18002_Pad10, net_U18005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18006(net_U18002_Pad2, net_U18002_Pad4, net_U18006_Pad10, net_R18001_Pad2, __A18_1__F09D, net_U18006_Pad6, GND, KYRPT1, TPOR_n, net_U18006_Pad10, F09B_n, net_U18006_Pad12, net_U18002_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U18007(net_U18006_Pad12, net_R18001_Pad2, net_U18005_Pad13, net_R18001_Pad2, net_U18007_Pad5, net_R18002_Pad2, GND, net_R18002_Pad2, net_U18007_Pad9, __A18_2__CNTOF9, net_U18007_Pad11, __A18_2__CNTOF9, net_U18007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0) U18008(net_U18002_Pad12, net_U18001_Pad6, net_U18008_Pad3, __A18_1__RCH15_n, net_R18001_Pad2, net_U18008_Pad6, GND, net_U18008_Pad11, NAVRST, net_U18008_Pad10, net_U18008_Pad11, __A18_1__RCH16_n, net_U18008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18009(__A18_2__RRSYNC, net_U18009_Pad2, net_U18009_Pad3, net_U18008_Pad3, XT1_n, XB5_n, GND, net_U18009_Pad8, net_U18006_Pad6, net_U18006_Pad10, T05, T11, TPOR_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U18010(net_U18009_Pad8, __A18_1__F09A_n, net_R18001_Pad2, net_U18001_Pad6, net_U18010_Pad5, , GND, , __A18_1__F09A_n, net_R18002_Pad2, net_U18008_Pad10, net_U18010_Pad12, net_U18010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18011(net_U18011_Pad1, net_U18008_Pad6, net_U18002_Pad12, net_U18010_Pad5, net_U18011_Pad1, net_U18011_Pad10, GND, net_U18010_Pad5, KYRPT1, net_U18011_Pad10, XT1_n, XB6_n, net_U18008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U18012(net_U18012_Pad1, NKEY1, net_U18012_Pad3, net_U18012_Pad3, net_U18012_Pad1, net_U18008_Pad10, GND, net_U18012_Pad1, __A18_1__RCH16_n, CH1601, NKEY2, net_U18012_Pad12, net_U18012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18013(net_U18012_Pad1, net_U18013_Pad2, net_U18012_Pad13, net_U18013_Pad4, net_U18013_Pad5, net_U18013_Pad6, GND, net_U18013_Pad8, net_U18013_Pad9, net_U18013_Pad10, net_U18013_Pad11, net_U18013_Pad12, net_R18002_Pad2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18014(net_U18012_Pad12, net_U18012_Pad13, net_U18008_Pad10, CH1602, net_U18012_Pad13, __A18_1__RCH16_n, GND, NKEY3, net_U18014_Pad13, net_U18013_Pad5, net_U18013_Pad5, net_U18008_Pad10, net_U18014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18015(CH1603, net_U18013_Pad5, __A18_1__RCH16_n, net_U18013_Pad9, NKEY4, net_U18015_Pad10, GND, net_U18013_Pad9, net_U18008_Pad10, net_U18015_Pad10, net_U18013_Pad9, __A18_1__RCH16_n, CH1604, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18016(net_U18013_Pad11, NKEY5, net_U18016_Pad3, net_U18016_Pad3, net_U18013_Pad11, net_U18008_Pad10, GND, net_U18013_Pad11, __A18_1__RCH16_n, CH1605, net_U18013_Pad8, net_U18013_Pad10, net_U18007_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18017(net_U18013_Pad2, net_U18013_Pad4, net_U18017_Pad10, net_R18002_Pad2, __A18_1__F09D, net_U18017_Pad6, GND, KYRPT2, TPOR_n, net_U18017_Pad10, F09B_n, net_U18007_Pad5, net_U18013_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18018(net_U18017_Pad10, net_U18010_Pad13, net_U18017_Pad6, net_U18018_Pad4, net_U18013_Pad12, net_U18008_Pad11, GND, net_U18018_Pad4, net_U18018_Pad13, net_U18010_Pad12, net_U18010_Pad12, KYRPT2, net_U18018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18119(net_U18119_Pad1, WCH13_n, CHWL11_n, net_U18119_Pad11, net_U18119_Pad1, net_U18119_Pad10, GND, net_U18119_Pad11, CCH13, net_U18119_Pad10, net_U18119_Pad11, RCH13_n, CH1311, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0) U18120(SBYBUT, net_U18120_Pad2, F17A, __A18_1__F17A_n, F17B, __A18_1__F17B_n, GND, STNDBY_n, __A18_1__STNDBY, SBY, STNDBY_n, SBYLIT, net_U18120_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18121(net_U18121_Pad1, __A18_1__F17A_n, net_U18120_Pad2, net_U18121_Pad12, net_U18121_Pad1, net_U18121_Pad10, GND, net_U18121_Pad12, net_U18120_Pad2, net_U18121_Pad10, __A18_1__F17B_n, net_U18121_Pad12, net_U18121_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18122(net_U18122_Pad1, net_U18121_Pad13, net_U18122_Pad3, net_U18122_Pad3, net_U18122_Pad1, net_U18120_Pad2, GND, net_U18122_Pad8, net_U18122_Pad13, net_U18122_Pad10, net_U18122_Pad10, net_U18122_Pad1, net_U18122_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U18023( , , __A18_2__ACTV_n, RADRPT, CCH13, net_U18023_Pad6, GND, __A18_2__ADVCNT, F10A_n, net_U18023_Pad10, SB2_n, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18124(net_U18124_Pad1, net_U18122_Pad13, net_U18122_Pad1, net_U18124_Pad4, net_U18122_Pad13, __A18_1__STNDBY, GND, net_U18124_Pad4, net_U18124_Pad1, __A18_1__STNDBY, __A18_1__STNDBY, ALTEST, net_U18120_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U18025(MRKRST, net_U18025_Pad2, net_U18025_Pad2, net_U18025_Pad4, net_U18025_Pad5, net_U18025_Pad6, GND, net_U18025_Pad8, net_U18025_Pad9, net_U18025_Pad10, net_U18025_Pad11, __A18_1__F08B_n, F08B, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18026(net_U18025_Pad5, MARK, net_U18026_Pad3, net_U18026_Pad3, net_U18025_Pad5, net_U18025_Pad4, GND, MRKREJ, net_U18026_Pad13, net_U18025_Pad9, net_U18025_Pad9, net_U18025_Pad4, net_U18026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U18027(CH1606, net_U18025_Pad5, __A18_1__RCH16_n, CH1607, net_U18025_Pad9, __A18_1__RCH16_n, GND, net_U18025_Pad6, net_U18025_Pad8, net_U18025_Pad11, net_U18027_Pad11, net_U18027_Pad12, net_U18027_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b0, 1'b1) U18028(net_U18027_Pad11, __A18_1__F09A_n, net_U18025_Pad11, net_U18025_Pad4, net_U18028_Pad5, , GND, , net_U18028_Pad9, RADRPT, __A18_2__ADVCNT, net_U18028_Pad12, net_U18028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18029(TPOR_n, net_U18027_Pad13, net_U18027_Pad13, net_U18025_Pad11, __A18_1__F09D, net_U18027_Pad12, GND, net_U18029_Pad8, net_U18029_Pad9, net_U18029_Pad10, net_U18029_Pad11, MKRPT, F09B_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18030(net_U18030_Pad1, net_U18025_Pad10, net_U18025_Pad2, net_U18028_Pad5, net_U18030_Pad1, net_U18030_Pad10, GND, net_U18028_Pad5, MKRPT, net_U18030_Pad10, net_U18030_Pad11, FS09_n, __A18_1__F09D, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1) U18031(__A18_1__F08B_n, net_U18030_Pad11, net_U18031_Pad3, net_U18031_Pad4, net_U18031_Pad5, net_U18029_Pad9, GND, net_U18031_Pad8, net_U18031_Pad9, net_U18031_Pad10, net_U18031_Pad11, net_U18031_Pad12, __A18_2__CNTOF9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18032(net_U18032_Pad1, CHWL04_n, WCH13_n, __A18_2__ACTV_n, net_U18032_Pad1, net_U18023_Pad6, GND, RCH13_n, __A18_2__ACTV_n, CH1304, CHWL03_n, WCH13_n, net_U18032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18033(net_U18031_Pad3, net_U18032_Pad13, net_U18031_Pad5, net_U18031_Pad5, net_U18031_Pad3, CCH13, GND, RCH13_n, net_U18031_Pad3, CH1303, CHWL02_n, WCH13_n, net_U18033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18034(net_U18034_Pad1, net_U18033_Pad13, net_U18034_Pad3, net_U18034_Pad3, net_U18034_Pad1, CCH13, GND, RCH13_n, net_U18034_Pad1, CH1302, CHWL01_n, WCH13_n, net_U18034_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18035(net_U18035_Pad1, net_U18034_Pad13, net_U18035_Pad3, net_U18035_Pad3, net_U18035_Pad1, CCH13, GND, RCH13_n, net_U18035_Pad1, CH1301, F10A_n, SB0_n, __A18_2__F10AS0, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18036(net_U18023_Pad10, __A18_2__F10AS0, net_U18036_Pad3, net_U18036_Pad3, net_U18023_Pad10, __A18_2__ACTV_n, GND, net_U18028_Pad12, net_U18036_Pad12, net_U18036_Pad10, net_U18028_Pad13, net_U18036_Pad12, net_U18036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18037(net_U18028_Pad13, __A18_2__ADVCNT, net_U18036_Pad13, RADRPT, net_U18028_Pad13, net_U18028_Pad9, GND, net_U18037_Pad8, net_U18037_Pad9, net_U18028_Pad9, net_U18037_Pad11, net_U18028_Pad12, net_U18036_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18038(net_U18036_Pad12, net_U18036_Pad13, net_U18028_Pad12, net_U18038_Pad4, net_U18038_Pad13, net_U18037_Pad9, GND, net_U18037_Pad8, net_U18038_Pad12, net_U18037_Pad11, net_U18037_Pad9, net_U18038_Pad12, net_U18038_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U18039(net_U18037_Pad9, net_U18038_Pad4, RADRPT, net_U18028_Pad9, net_U18037_Pad8, , GND, , net_U18039_Pad9, RADRPT, net_U18038_Pad4, net_U18039_Pad12, net_U18039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18040(net_U18038_Pad12, net_U18038_Pad13, net_U18037_Pad8, net_U18039_Pad9, net_U18040_Pad13, net_U18039_Pad13, GND, net_U18039_Pad12, net_U18040_Pad12, net_U18040_Pad10, net_U18039_Pad13, net_U18040_Pad12, net_U18040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18041(net_U18039_Pad13, net_U18038_Pad4, net_U18041_Pad3, net_U18039_Pad9, net_U18041_Pad5, net_U18041_Pad6, GND, net_U18007_Pad13, net_U18038_Pad12, net_U18036_Pad13, F10A, net_U18039_Pad12, net_U18040_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18042(net_U18040_Pad12, net_U18040_Pad13, net_U18039_Pad12, net_U18042_Pad4, net_U18042_Pad13, net_U18041_Pad3, GND, net_U18041_Pad6, net_U18042_Pad12, net_U18041_Pad5, net_U18041_Pad3, net_U18042_Pad12, net_U18042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b0) U18043(net_U18041_Pad3, net_U18042_Pad4, RADRPT, net_U18039_Pad9, net_U18041_Pad6, , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U18044(net_U18042_Pad12, net_U18042_Pad13, net_U18041_Pad6, net_U18007_Pad11, net_U18042_Pad13, net_U18040_Pad12, GND, __A18_2__ADVCNT, net_U18044_Pad9, net_U18044_Pad10, net_U18034_Pad3, net_U18035_Pad3, net_U18044_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18045(net_U18044_Pad10, __A18_2__CNTOF9, net_U18031_Pad4, net_U18044_Pad10, F5BSB2_n, net_U18031_Pad9, GND, net_U18031_Pad11, F5BSB2_n, net_U18044_Pad10, net_U18029_Pad9, net_U18044_Pad9, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18046(net_U18034_Pad3, net_U18035_Pad1, net_U18031_Pad8, net_U18035_Pad3, net_U18034_Pad1, __A18_2__RRRARA, GND, __A18_2__LRXVEL, net_U18035_Pad3, net_U18034_Pad3, net_U18031_Pad10, __A18_2__RRRANG, net_U18031_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18047(net_U18031_Pad10, net_U18035_Pad1, net_U18031_Pad10, net_U18034_Pad1, net_U18035_Pad3, __A18_2__LRZVEL, GND, __A18_2__LRRANG, net_U18031_Pad10, net_U18034_Pad1, net_U18035_Pad1, __A18_2__LRYVEL, net_U18034_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U18048(net_U18048_Pad1, net_U18031_Pad12, GTSET_n, net_U18048_Pad4, net_U18048_Pad1, net_U18048_Pad6, GND, F5ASB2_n, net_U18048_Pad4, net_U18048_Pad10, net_U18048_Pad10, net_U18048_Pad12, net_U18048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18049(net_U18048_Pad4, RADRPT, net_U18048_Pad13, F09B, GOJAM, net_U18048_Pad12, GND, RADRPT, net_U18049_Pad9, net_U18048_Pad13, GTRST_n, net_U18048_Pad6, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0) U18050(TPOR_n, __A18_2__HERB, __A18_2__HERB, net_U18049_Pad9, net_U18050_Pad5, net_U18009_Pad2, GND, net_U18050_Pad8, RRIN1, net_U18050_Pad10, RRIN0, net_U18050_Pad12, LRIN1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U18051(net_U18050_Pad5, net_U18044_Pad13, net_U18031_Pad4, net_U18051_Pad4, net_U18051_Pad5, net_U18051_Pad6, GND, net_U18051_Pad8, net_U18029_Pad8, net_U18051_Pad10, net_U18009_Pad3, net_U18029_Pad9, __A18_2__LRSYNC, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18052(net_U18009_Pad2, net_U18050_Pad8, net_U18009_Pad2, net_U18050_Pad10, net_U18029_Pad11, net_U18051_Pad8, GND, net_U18051_Pad6, net_U18029_Pad9, net_U18050_Pad12, net_U18029_Pad11, net_U18051_Pad5, net_U18029_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18053(LRIN0, net_U18029_Pad10, net_U18023_Pad6, net_U18029_Pad11, F09A, __A18_1__F09A_n, GND, RNRADP, net_U18051_Pad4, RNRADM, net_U18051_Pad10, net_U18009_Pad3, net_U18048_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18154(SBY, SBYREL_n, , , , , GND, , , , , , , p4VDC, SIM_RST, SIM_CLK);
U74HC27 U18155(net_U18122_Pad1, STOP, , , , , GND, , , , , net_U18122_Pad8, net_U18119_Pad11, p4VDC, SIM_RST, SIM_CLK);
endmodule |
module service_gates(SIM_RST, SIM_CLK, p4VSW, GND, T10_n, CT_n, RT_n, TT_n, WT_n, MP3A, STFET1_n, A2X_n, CGMC, CI_n, L2GD_n, NEAC, PIFL_n, RA_n, RB_n, RC_n, RCH_n, RG_n, RL_n, RL10BB, RQ_n, RSC_n, RU_n, RUS_n, RZ_n, U2BBK, WA_n, WB_n, WCH_n, WG_n, WL_n, WQ_n, WS_n, WSC_n, WY_n, WY12_n, WYD_n, WZ_n, ZAP_n, CYL_n, CYR_n, EDOP_n, SR_n, EAC_n, GINH, L15_n, SCAD_n, SHIFT, SUMA15_n, SUMB15_n, XB0_n, XB1_n, XB2_n, XB3_n, XB4_n, XB5_n, XB6_n, XT0_n, A2XG_n, CAG, CBG, CCHG_n, CEBG, CFBG, CGG, CLG1G, CLG2G, CQG, CSG, CUG, CZG, CI01_n, G2LSG_n, L2GDG_n, RAG_n, RBBEG_n, RBHG_n, RBLG_n, RCG_n, RCHG_n, REBG_n, RFBG_n, RGG_n, RLG_n, RQG_n, RUG_n, RULOG_n, RZG_n, U2BBKG_n, US2SG, WAG_n, WALSG_n, WBBEG_n, WBG_n, WCHG_n, WEDOPG_n, WEBG_n, WFBG_n, WG1G_n, WG2G_n, WG3G_n, WG4G_n, WG5G_n, WLG_n, WQG_n, WSG_n, WYDG_n, WYDLOG_n, WYHIG_n, WYLOG_n, WZG_n, MWG, MWAG, MWBG, MWLG, MWQG, MWSG, MWYG, MWZG, MRAG, MRGG, MRLG, MRULOG, MWBBEG, MWEBG, MWFBG);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
output wire A2XG_n;
input wire A2X_n;
output wire CAG;
output wire CBG;
output wire CCHG_n;
output wire CEBG;
output wire CFBG;
output wire CGG;
input wire CGMC;
output wire CI01_n;
input wire CI_n;
output wire CLG1G;
output wire CLG2G;
output wire CQG;
output wire CSG;
input wire CT_n;
output wire CUG;
input wire CYL_n;
input wire CYR_n;
output wire CZG;
input wire EAC_n;
input wire EDOP_n;
output wire G2LSG_n;
input wire GINH;
input wire L15_n;
output wire L2GDG_n;
input wire L2GD_n;
input wire MP3A;
output wire MRAG; //FPGA#wand
output wire MRGG; //FPGA#wand
output wire MRLG; //FPGA#wand
output wire MRULOG; //FPGA#wand
output wire MWAG; //FPGA#wand
output wire MWBBEG; //FPGA#wand
output wire MWBG; //FPGA#wand
output wire MWEBG; //FPGA#wand
output wire MWFBG; //FPGA#wand
output wire MWG; //FPGA#wand
output wire MWLG; //FPGA#wand
output wire MWQG; //FPGA#wand
output wire MWSG; //FPGA#wand
output wire MWYG; //FPGA#wand
output wire MWZG; //FPGA#wand
input wire NEAC;
input wire PIFL_n;
output wire RAG_n;
input wire RA_n;
output wire RBBEG_n;
output wire RBHG_n;
output wire RBLG_n;
input wire RB_n;
output wire RCG_n;
output wire RCHG_n;
input wire RCH_n;
input wire RC_n;
output wire REBG_n;
output wire RFBG_n;
output wire RGG_n;
input wire RG_n;
input wire RL10BB;
output wire RLG_n;
input wire RL_n;
output wire RQG_n;
input wire RQ_n;
input wire RSC_n;
input wire RT_n;
output wire RUG_n;
output wire RULOG_n;
input wire RUS_n;
input wire RU_n;
output wire RZG_n;
input wire RZ_n;
input wire SCAD_n;
input wire SHIFT;
input wire SR_n;
input wire STFET1_n;
input wire SUMA15_n;
input wire SUMB15_n;
input wire T10_n;
input wire TT_n;
input wire U2BBK;
output wire U2BBKG_n;
output wire US2SG;
output wire WAG_n;
output wire WALSG_n;
input wire WA_n;
output wire WBBEG_n;
output wire WBG_n;
input wire WB_n;
output wire WCHG_n;
input wire WCH_n;
output wire WEBG_n;
output wire WEDOPG_n;
output wire WFBG_n;
output wire WG1G_n;
output wire WG2G_n;
output wire WG3G_n;
output wire WG4G_n;
output wire WG5G_n;
input wire WG_n;
output wire WLG_n;
input wire WL_n;
output wire WQG_n;
input wire WQ_n;
input wire WSC_n;
output wire WSG_n;
input wire WS_n;
input wire WT_n;
input wire WY12_n;
output wire WYDG_n;
output wire WYDLOG_n;
input wire WYD_n;
output wire WYHIG_n;
output wire WYLOG_n;
input wire WY_n;
output wire WZG_n;
input wire WZ_n;
input wire XB0_n;
input wire XB1_n;
input wire XB2_n;
input wire XB3_n;
input wire XB4_n;
input wire XB5_n;
input wire XB6_n;
input wire XT0_n;
input wire ZAP_n;
wire __A07_1__WALSG;
wire __A07_1__WGA_n;
wire __A07_1__WGNORM;
wire __A07_1__WSCG_n;
wire __A07_2__CIFF;
wire __A07_2__CINORM;
wire __A07_2__G2LSG;
wire __A07_2__RBBK;
wire __A07_2__RSCG_n;
wire __A07_2__RUSG_n;
wire net_R7001_Pad2; //FPGA#wand
wire net_U7001_Pad10;
wire net_U7001_Pad13;
wire net_U7001_Pad4;
wire net_U7001_Pad5;
wire net_U7001_Pad6;
wire net_U7003_Pad1;
wire net_U7003_Pad13;
wire net_U7003_Pad3;
wire net_U7004_Pad5;
wire net_U7005_Pad1;
wire net_U7005_Pad12;
wire net_U7006_Pad12;
wire net_U7008_Pad12;
wire net_U7008_Pad6;
wire net_U7008_Pad8;
wire net_U7010_Pad10;
wire net_U7010_Pad11;
wire net_U7011_Pad10;
wire net_U7011_Pad11;
wire net_U7011_Pad4;
wire net_U7012_Pad10;
wire net_U7012_Pad12;
wire net_U7012_Pad8;
wire net_U7012_Pad9;
wire net_U7013_Pad1;
wire net_U7015_Pad13;
wire net_U7015_Pad4;
wire net_U7016_Pad11;
wire net_U7017_Pad13;
wire net_U7017_Pad2;
wire net_U7018_Pad13;
wire net_U7019_Pad10;
wire net_U7019_Pad13;
wire net_U7019_Pad2;
wire net_U7019_Pad9;
wire net_U7021_Pad10;
wire net_U7021_Pad4;
wire net_U7022_Pad13;
wire net_U7022_Pad5;
wire net_U7023_Pad1;
wire net_U7023_Pad10;
wire net_U7023_Pad11;
wire net_U7023_Pad4;
wire net_U7024_Pad11;
wire net_U7024_Pad8;
wire net_U7026_Pad13;
wire net_U7026_Pad3;
wire net_U7027_Pad13;
wire net_U7027_Pad4;
wire net_U7028_Pad1;
wire net_U7028_Pad10;
wire net_U7028_Pad12;
wire net_U7028_Pad4;
wire net_U7029_Pad13;
wire net_U7030_Pad10;
wire net_U7030_Pad13;
wire net_U7031_Pad10;
wire net_U7031_Pad9;
wire net_U7032_Pad10;
wire net_U7033_Pad11;
wire net_U7033_Pad13;
wire net_U7033_Pad8;
wire net_U7035_Pad1;
wire net_U7036_Pad1;
wire net_U7036_Pad10;
wire net_U7036_Pad4;
wire net_U7037_Pad11;
wire net_U7038_Pad11;
wire net_U7038_Pad13;
wire net_U7040_Pad5;
pullup R7001(net_R7001_Pad2);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U7001(__A07_1__WALSG, ZAP_n, WT_n, net_U7001_Pad4, net_U7001_Pad5, net_U7001_Pad6, GND, net_U7001_Pad4, WT_n, net_U7001_Pad10, WY_n, WT_n, net_U7001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0) U7002(__A07_1__WALSG, WALSG_n, WY12_n, net_U7001_Pad5, WY_n, net_U7001_Pad6, GND, WYLOG_n, net_U7001_Pad10, WYHIG_n, net_U7001_Pad13, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U7003(net_U7003_Pad1, net_U7001_Pad10, net_U7003_Pad3, net_U7003_Pad3, WYD_n, WT_n, GND, net_U7003_Pad1, CT_n, CUG, L15_n, PIFL_n, net_U7003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b1) U7004(net_U7003_Pad3, WYDG_n, net_R7001_Pad2, WYDLOG_n, net_U7004_Pad5, WBG_n, GND, , , , , WG1G_n, __A07_1__WGNORM, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U7005(net_U7005_Pad1, WYD_n, WT_n, net_U7004_Pad5, WB_n, WT_n, GND, WBG_n, CT_n, CBG, __A07_1__WGNORM, net_U7005_Pad12, WG2G_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U7006(SHIFT, NEAC, __A07_1__WGA_n, WT_n, GINH, __A07_1__WGNORM, GND, net_U7005_Pad12, __A07_1__WGA_n, WT_n, SR_n, net_U7006_Pad12, net_U7003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U7007(net_U7005_Pad1, net_R7001_Pad2, net_U7006_Pad12, net_R7001_Pad2, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4
U74HC27 U7008(__A07_1__WGA_n, WT_n, __A07_1__WGA_n, WT_n, CYL_n, net_U7008_Pad6, GND, net_U7008_Pad8, __A07_1__WGA_n, WT_n, EDOP_n, net_U7008_Pad12, CYR_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0) U7009(net_U7008_Pad12, WG5G_n, net_U7008_Pad6, WG3G_n, net_U7008_Pad8, WEDOPG_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U7010(WG4G_n, net_U7005_Pad12, net_U7008_Pad12, net_U7010_Pad11, WT_n, WZ_n, GND, __A07_1__WSCG_n, XB5_n, net_U7010_Pad10, net_U7010_Pad11, net_U7010_Pad10, WZG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7011(CZG, WZG_n, CT_n, net_U7011_Pad4, WL_n, WT_n, GND, __A07_1__WSCG_n, XB1_n, net_U7011_Pad10, net_U7011_Pad11, CT_n, CLG1G, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U7012(XB1_n, XT0_n, net_U7011_Pad4, net_U7012_Pad12, net_U7011_Pad10, WLG_n, GND, net_U7012_Pad8, net_U7012_Pad9, net_U7012_Pad10, __A07_1__WALSG, net_U7012_Pad12, WCHG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U7013(net_U7013_Pad1, net_U7011_Pad4, net_U7012_Pad12, net_U7011_Pad10, __A07_1__WALSG, , GND, , net_U7011_Pad10, net_U7012_Pad12, net_U7011_Pad4, __A07_2__G2LSG, net_U7011_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U7014(CLG2G, net_U7013_Pad1, CT_n, net_U7012_Pad9, WT_n, WA_n, GND, __A07_1__WSCG_n, XB0_n, net_U7012_Pad10, net_U7012_Pad9, net_U7012_Pad10, WAG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7015(CAG, net_U7012_Pad8, CT_n, net_U7015_Pad4, WT_n, WS_n, GND, WSG_n, CT_n, CSG, WT_n, WQ_n, net_U7015_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U7016(net_U7015_Pad4, WSG_n, , , , , GND, , , RCG_n, net_U7016_Pad11, G2LSG_n, __A07_2__G2LSG, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U7017(net_U7015_Pad13, net_U7017_Pad2, XB2_n, XT0_n, WCHG_n, net_U7017_Pad13, GND, , , , , WQG_n, net_U7017_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7018(net_U7017_Pad2, __A07_1__WSCG_n, XB2_n, CQG, WQG_n, CT_n, GND, RT_n, RC_n, net_U7016_Pad11, RT_n, RQ_n, net_U7018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U7019(net_U7018_Pad13, net_U7019_Pad2, XB2_n, XT0_n, RCHG_n, net_U7019_Pad13, GND, RFBG_n, net_U7019_Pad9, net_U7019_Pad10, __A07_2__RBBK, RQG_n, net_U7019_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7020(net_U7019_Pad2, __A07_2__RSCG_n, XB2_n, net_U7019_Pad9, __A07_2__RSCG_n, XB4_n, GND, __A07_2__RSCG_n, XB6_n, net_U7019_Pad10, net_U7019_Pad10, __A07_2__RBBK, RBBEG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7021(__A07_2__G2LSG, TT_n, ZAP_n, net_U7021_Pad4, TT_n, L2GD_n, GND, TT_n, A2X_n, net_U7021_Pad10, T10_n, STFET1_n, __A07_2__RBBK, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b1, 1'b0, 1'b0, 1'b0, 1'b1) U7022(net_U7021_Pad4, L2GDG_n, net_U7021_Pad10, A2XG_n, net_U7022_Pad5, CGG, GND, , , , , WBBEG_n, net_U7022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7023(net_U7023_Pad1, L2GD_n, CT_n, net_U7023_Pad4, CT_n, WG_n, GND, __A07_1__WSCG_n, XB3_n, net_U7023_Pad10, net_U7023_Pad11, CT_n, CEBG, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U7024(net_U7023_Pad1, net_U7023_Pad4, net_U7023_Pad10, U2BBK, net_U7022_Pad13, net_U7023_Pad11, GND, net_U7024_Pad8, net_U7022_Pad13, U2BBK, net_U7024_Pad11, net_U7022_Pad5, CGMC, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U7025(CFBG, net_U7024_Pad8, CT_n, net_U7024_Pad11, __A07_1__WSCG_n, XB4_n, GND, net_U7024_Pad11, net_U7022_Pad13, WFBG_n, __A07_1__WSCG_n, XB6_n, net_U7022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U7026( , , net_U7026_Pad3, RGG_n, , , GND, , , , , REBG_n, net_U7026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7027(net_U7026_Pad3, RT_n, RG_n, net_U7027_Pad4, RT_n, RA_n, GND, net_U7027_Pad4, net_U7027_Pad13, RAG_n, XB0_n, __A07_2__RSCG_n, net_U7027_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7028(net_U7028_Pad1, RT_n, RL_n, net_U7028_Pad4, __A07_2__RSCG_n, XB1_n, GND, RT_n, RZ_n, net_U7028_Pad10, net_U7028_Pad10, net_U7028_Pad12, RZG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U7029(net_U7028_Pad1, net_U7028_Pad4, XB1_n, XT0_n, RCHG_n, net_U7029_Pad13, GND, US2SG, __A07_2__RUSG_n, SUMA15_n, SUMB15_n, RLG_n, net_U7029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7030(net_U7028_Pad12, XB5_n, __A07_2__RSCG_n, net_U7026_Pad13, __A07_2__RSCG_n, XB3_n, GND, RT_n, RU_n, net_U7030_Pad10, RT_n, RUS_n, net_U7030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U7031(net_U7030_Pad10, RUG_n, net_U7030_Pad13, __A07_2__RUSG_n, , , GND, RBHG_n, net_U7031_Pad9, net_U7031_Pad10, RL10BB, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7032(RULOG_n, net_U7030_Pad10, net_U7030_Pad13, net_U7031_Pad9, RT_n, RB_n, GND, RT_n, net_U7031_Pad10, net_U7032_Pad10, net_U7031_Pad9, net_U7032_Pad10, RBLG_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0) U7033(net_U7023_Pad10, WEBG_n, , , , , GND, net_U7033_Pad8, CI_n, __A07_1__WSCG_n, net_U7033_Pad11, __A07_2__RSCG_n, net_U7033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U7034( , , NEAC, EAC_n, MP3A, __A07_2__CINORM, GND, net_U7033_Pad13, RT_n, RSC_n, SCAD_n, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U7035(net_U7035_Pad1, net_U7033_Pad8, __A07_2__CIFF, __A07_2__CIFF, net_U7035_Pad1, CUG, GND, __A07_2__CIFF, __A07_2__CINORM, CI01_n, WSC_n, SCAD_n, net_U7033_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U7036(net_U7036_Pad1, RT_n, RCH_n, net_U7036_Pad4, WT_n, WCH_n, GND, WCH_n, CT_n, net_U7036_Pad10, , , , p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b0, 1'b0, 1'b1, 1'b1) U7037(net_U7036_Pad1, RCHG_n, net_U7036_Pad4, WCHG_n, net_U7036_Pad10, CCHG_n, GND, net_U7037_Pad11, WG_n, __A07_1__WGA_n, net_U7037_Pad11, U2BBKG_n, U2BBK, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U7038(net_U7003_Pad1, MWYG, WBG_n, MWBG, __A07_1__WGA_n, MWG, GND, MWZG, WZG_n, MWLG, net_U7038_Pad11, MWAG, net_U7038_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74LVC06 U7039(WSG_n, MWSG, WQG_n, MWQG, WEBG_n, MWEBG, GND, MWFBG, WFBG_n, MWBBEG, WBBEG_n, MRGG, RGG_n, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74LVC06 U7040(RAG_n, MRAG, RLG_n, MRLG, net_U7040_Pad5, MRULOG, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U7041(net_U7040_Pad5, net_U7030_Pad10, net_U7030_Pad13, net_U7038_Pad13, net_U7012_Pad9, net_U7012_Pad10, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U7042(net_U7011_Pad4, net_U7012_Pad12, , , , , GND, , , , , net_U7038_Pad11, net_U7011_Pad10, p4VSW, SIM_RST, SIM_CLK);
endmodule |
module inout_vi(SIM_RST, SIM_CLK, p4VSW, GND, P04_n, SB2_n, F18A, F18B, F5ASB0_n, F5ASB2, F5ASB2_n, CCHG_n, WCHG_n, CCH11, CCH12, CCH13, CCH14, CCH33, RCH11_n, RCH12_n, RCH13_n, RCH14_n, WCH11_n, WCH12_n, WCH13_n, WCH14_n, POUT_n, MOUT_n, ZOUT_n, T6RPT, PIPPLS_n, PIPAXp, PIPAXm, PIPAYp, PIPAYm, PIPAZp, PIPAZm, OCTAD5, CHWL05_n, CHWL06_n, CHWL07_n, CHWL08_n, CHWL10_n, CHWL11_n, CHWL12_n, CHWL13_n, CHWL14_n, CHWL16_n, XT0_n, XB0_n, XB1_n, XB2_n, XB3_n, XB4_n, XB7_n, T6ON_n, ALTEST, E5, E6, E7_n, CDUXD, CDUYD, CDUZD, PIPAFL, PIPXP, PIPXM, PIPYP, PIPYM, PIPZP, PIPZM, TRUND, SHAFTD, CH0705, CH0706, CH0707, CH1310, CH1316, CH1411, CH1412, CH1413, CH1414, CH1416, CH1108, CH1113, CH1114, CH1116, CH1216, CDUXDP, CDUXDM, CDUYDP, CDUYDM, CDUZDP, CDUZDM);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
output wire ALTEST;
input wire CCH11;
input wire CCH12;
input wire CCH13;
input wire CCH14;
input wire CCH33;
input wire CCHG_n;
output wire CDUXD;
output wire CDUXDM;
output wire CDUXDP;
output wire CDUYD;
output wire CDUYDM;
output wire CDUYDP;
output wire CDUZD;
output wire CDUZDM;
output wire CDUZDP;
output wire CH0705;
output wire CH0706;
output wire CH0707;
output wire CH1108;
output wire CH1113;
output wire CH1114;
output wire CH1116;
output wire CH1216;
output wire CH1310;
output wire CH1316;
output wire CH1411;
output wire CH1412;
output wire CH1413;
output wire CH1414;
output wire CH1416;
input wire CHWL05_n;
input wire CHWL06_n;
input wire CHWL07_n;
input wire CHWL08_n;
input wire CHWL10_n;
input wire CHWL11_n;
input wire CHWL12_n;
input wire CHWL13_n;
input wire CHWL14_n;
input wire CHWL16_n;
output wire E5;
output wire E6;
output wire E7_n;
input wire F18A;
input wire F18B;
input wire F5ASB0_n;
input wire F5ASB2;
input wire F5ASB2_n;
input wire MOUT_n;
input wire OCTAD5;
input wire P04_n;
output wire PIPAFL;
input wire PIPAXm;
input wire PIPAXp;
input wire PIPAYm;
input wire PIPAYp;
input wire PIPAZm;
input wire PIPAZp;
input wire PIPPLS_n;
output wire PIPXM;
output wire PIPXP;
output wire PIPYM;
output wire PIPYP;
output wire PIPZM;
output wire PIPZP;
input wire POUT_n;
input wire RCH11_n;
input wire RCH12_n;
input wire RCH13_n;
input wire RCH14_n;
input wire SB2_n;
output wire SHAFTD;
output wire T6ON_n;
input wire T6RPT;
output wire TRUND;
input wire WCH11_n;
input wire WCH12_n;
input wire WCH13_n;
input wire WCH14_n;
input wire WCHG_n;
input wire XB0_n;
input wire XB1_n;
input wire XB2_n;
input wire XB3_n;
input wire XB4_n;
input wire XB7_n;
input wire XT0_n;
input wire ZOUT_n;
wire __A23_1__BOTHX;
wire __A23_1__BOTHY;
wire __A23_1__BOTHZ;
wire __A23_1__F18AX;
wire __A23_1__F18A_n;
wire __A23_1__F18B_n;
wire __A23_1__MISSX;
wire __A23_1__MISSY;
wire __A23_1__MISSZ;
wire __A23_1__NOXM;
wire __A23_1__NOXP;
wire __A23_1__NOYM;
wire __A23_1__NOYP;
wire __A23_1__NOZM;
wire __A23_1__NOZP;
wire __A23_1__P04A;
wire __A23_1__PIPAXm_n;
wire __A23_1__PIPAXp_n;
wire __A23_1__PIPAYm_n;
wire __A23_1__PIPAYp_n;
wire __A23_1__PIPAZm_n;
wire __A23_1__PIPAZp_n;
wire __A23_1__PIPGXm;
wire __A23_1__PIPGXp;
wire __A23_1__PIPGYm;
wire __A23_1__PIPGYp;
wire __A23_1__PIPGZm;
wire __A23_1__PIPGZp;
wire __A23_1__PIPSAM;
wire __A23_1__PIPSAM_n;
wire __A23_2__CCH07;
wire __A23_2__ISSTDC;
wire __A23_2__OT1108;
wire __A23_2__OT1113;
wire __A23_2__OT1114;
wire __A23_2__OT1116;
wire __A23_2__RCH07_n;
wire __A23_2__SHFTDM;
wire __A23_2__SHFTDP;
wire __A23_2__TRNDM;
wire __A23_2__TRNDP;
wire __A23_2__WCH07_n;
wire net_R23001_Pad2; //FPGA#wand
wire net_R23002_Pad2; //FPGA#wand
wire net_U23001_Pad12;
wire net_U23001_Pad6;
wire net_U23001_Pad8;
wire net_U23002_Pad5;
wire net_U23002_Pad9;
wire net_U23003_Pad10;
wire net_U23003_Pad12;
wire net_U23003_Pad4;
wire net_U23003_Pad6;
wire net_U23003_Pad8;
wire net_U23004_Pad1;
wire net_U23004_Pad11;
wire net_U23004_Pad12;
wire net_U23004_Pad13;
wire net_U23004_Pad4;
wire net_U23005_Pad10;
wire net_U23005_Pad8;
wire net_U23005_Pad9;
wire net_U23006_Pad13;
wire net_U23007_Pad10;
wire net_U23007_Pad11;
wire net_U23008_Pad10;
wire net_U23008_Pad11;
wire net_U23008_Pad13;
wire net_U23008_Pad6;
wire net_U23008_Pad8;
wire net_U23009_Pad12;
wire net_U23009_Pad6;
wire net_U23009_Pad8;
wire net_U23010_Pad11;
wire net_U23011_Pad13;
wire net_U23012_Pad10;
wire net_U23012_Pad3;
wire net_U23014_Pad10;
wire net_U23014_Pad12;
wire net_U23014_Pad13;
wire net_U23014_Pad3;
wire net_U23014_Pad6;
wire net_U23014_Pad8;
wire net_U23015_Pad10;
wire net_U23015_Pad12;
wire net_U23015_Pad6;
wire net_U23015_Pad8;
wire net_U23016_Pad1;
wire net_U23016_Pad10;
wire net_U23016_Pad11;
wire net_U23016_Pad12;
wire net_U23016_Pad13;
wire net_U23017_Pad11;
wire net_U23017_Pad12;
wire net_U23017_Pad13;
wire net_U23018_Pad4;
wire net_U23018_Pad6;
wire net_U23018_Pad8;
wire net_U23019_Pad1;
wire net_U23019_Pad4;
wire net_U23020_Pad13;
wire net_U23021_Pad3;
wire net_U23022_Pad10;
wire net_U23022_Pad11;
wire net_U23022_Pad8;
wire net_U23023_Pad1;
wire net_U23023_Pad12;
wire net_U23023_Pad6;
wire net_U23023_Pad8;
wire net_U23024_Pad11;
wire net_U23024_Pad12;
wire net_U23024_Pad2;
wire net_U23024_Pad6;
wire net_U23025_Pad1;
wire net_U23025_Pad13;
wire net_U23025_Pad3;
wire net_U23026_Pad12;
wire net_U23026_Pad13;
wire net_U23027_Pad13;
wire net_U23027_Pad3;
wire net_U23028_Pad1;
wire net_U23028_Pad10;
wire net_U23028_Pad4;
wire net_U23029_Pad13;
wire net_U23030_Pad11;
wire net_U23030_Pad3;
wire net_U23030_Pad5;
wire net_U23030_Pad6;
wire net_U23030_Pad8;
wire net_U23030_Pad9;
wire net_U23031_Pad12;
wire net_U23031_Pad13;
wire net_U23032_Pad10;
wire net_U23032_Pad11;
wire net_U23032_Pad12;
wire net_U23032_Pad13;
wire net_U23032_Pad2;
wire net_U23032_Pad5;
wire net_U23032_Pad6;
wire net_U23032_Pad8;
wire net_U23032_Pad9;
wire net_U23033_Pad13;
wire net_U23035_Pad13;
wire net_U23036_Pad1;
wire net_U23036_Pad3;
wire net_U23037_Pad11;
wire net_U23037_Pad13;
wire net_U23037_Pad3;
wire net_U23037_Pad5;
wire net_U23037_Pad6;
wire net_U23037_Pad8;
wire net_U23037_Pad9;
wire net_U23038_Pad13;
wire net_U23040_Pad13;
wire net_U23042_Pad13;
wire net_U23043_Pad1;
wire net_U23043_Pad13;
wire net_U23044_Pad1;
wire net_U23044_Pad13;
wire net_U23045_Pad13;
wire net_U23045_Pad3;
wire net_U23046_Pad12;
wire net_U23046_Pad8;
wire net_U23047_Pad11;
wire net_U23047_Pad13;
wire net_U23047_Pad5;
wire net_U23047_Pad9;
wire net_U23048_Pad1;
wire net_U23048_Pad10;
wire net_U23049_Pad1;
wire net_U23049_Pad10;
wire net_U23050_Pad1;
wire net_U23050_Pad10;
wire net_U23051_Pad1;
wire net_U23051_Pad10;
wire net_U23052_Pad1;
wire net_U23052_Pad10;
wire net_U23052_Pad12;
wire net_U23053_Pad5;
wire net_U23054_Pad1;
wire net_U23054_Pad13;
wire net_U23055_Pad3;
pullup R23001(net_R23001_Pad2);
pullup R23002(net_R23002_Pad2);
U74HC27 #(1'b1, 1'b1, 1'b1) U23001(__A23_1__NOXP, __A23_1__NOXM, __A23_1__NOYM, __A23_1__NOZP, __A23_1__NOZM, net_U23001_Pad6, GND, net_U23001_Pad8, __A23_1__MISSX, __A23_1__MISSY, __A23_1__MISSZ, net_U23001_Pad12, __A23_1__NOYP, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U23002(net_U23001_Pad12, net_R23001_Pad2, net_U23001_Pad6, net_R23001_Pad2, net_U23002_Pad5, net_R23002_Pad2, GND, net_R23002_Pad2, net_U23002_Pad9, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
U74HC04 #(1'b1, 1'b1, 1'b1, 1'b0, 1'b1, 1'b1) U23003(F18B, __A23_1__F18B_n, __A23_1__PIPGXp, net_U23003_Pad4, __A23_1__PIPGXm, net_U23003_Pad6, GND, net_U23003_Pad8, F5ASB2, net_U23003_Pad10, __A23_1__PIPGYp, net_U23003_Pad12, __A23_1__PIPGYm, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23004(net_U23004_Pad1, __A23_1__F18B_n, net_R23001_Pad2, net_U23004_Pad4, F5ASB0_n, net_U23001_Pad8, GND, net_R23002_Pad2, CCH33, PIPAFL, net_U23004_Pad11, net_U23004_Pad12, net_U23004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b1, 1'b0) U23005(__A23_1__BOTHX, __A23_1__BOTHY, net_U23004_Pad1, net_U23004_Pad4, PIPAFL, net_U23002_Pad9, GND, net_U23005_Pad8, net_U23005_Pad9, net_U23005_Pad10, net_U23003_Pad4, net_U23002_Pad5, __A23_1__BOTHZ, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23006(net_U23003_Pad6, net_U23005_Pad10, PIPPLS_n, SB2_n, __A23_1__P04A, __A23_1__PIPSAM, GND, , , , , net_U23004_Pad11, net_U23006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23007(net_U23004_Pad12, net_U23004_Pad13, net_U23005_Pad8, net_U23007_Pad11, net_U23003_Pad8, net_U23004_Pad13, GND, net_U23004_Pad12, net_U23003_Pad8, net_U23007_Pad10, net_U23007_Pad11, net_U23006_Pad13, net_U23005_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23008(net_U23006_Pad13, net_U23005_Pad9, net_U23007_Pad10, net_U23008_Pad11, net_U23003_Pad8, net_U23008_Pad6, GND, net_U23008_Pad8, net_U23003_Pad8, net_U23008_Pad10, net_U23008_Pad11, net_U23005_Pad10, net_U23008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23009(net_U23006_Pad13, net_U23005_Pad10, net_U23005_Pad9, net_U23005_Pad10, net_U23003_Pad6, net_U23009_Pad6, GND, net_U23009_Pad8, net_U23006_Pad13, net_U23008_Pad13, net_U23003_Pad6, net_U23009_Pad12, net_U23003_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b0, 1'b1) U23010(net_U23005_Pad9, net_U23008_Pad13, net_U23009_Pad12, net_U23009_Pad6, net_U23008_Pad8, net_U23008_Pad6, GND, net_U23008_Pad8, net_U23008_Pad6, net_U23009_Pad8, net_U23010_Pad11, net_U23010_Pad11, net_U23003_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U23011(net_U23005_Pad10, net_U23008_Pad13, net_U23008_Pad10, __A23_1__BOTHX, net_U23003_Pad6, net_U23003_Pad4, GND, __A23_1__PIPGXm, net_U23011_Pad13, __A23_1__NOXM, __A23_1__NOXM, __A23_1__F18AX, net_U23011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23012(__A23_1__NOXP, __A23_1__PIPGXp, net_U23012_Pad3, net_U23012_Pad3, __A23_1__NOXP, __A23_1__F18AX, GND, __A23_1__MISSX, F5ASB2, net_U23012_Pad10, net_U23003_Pad12, net_U23003_Pad10, __A23_1__BOTHY, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U23013(__A23_1__PIPGXp, __A23_1__PIPGXm, net_U23006_Pad13, net_U23008_Pad13, net_U23003_Pad4, PIPXP, GND, PIPXM, net_U23005_Pad9, net_U23008_Pad13, net_U23003_Pad6, __A23_1__MISSX, net_U23012_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23014(net_U23003_Pad12, net_U23014_Pad10, net_U23014_Pad3, net_U23014_Pad10, net_U23003_Pad10, net_U23014_Pad6, GND, net_U23014_Pad8, net_U23014_Pad13, net_U23014_Pad10, net_U23003_Pad10, net_U23014_Pad12, net_U23014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23015(net_U23014_Pad3, net_U23014_Pad10, net_U23014_Pad13, net_U23015_Pad10, net_U23003_Pad12, net_U23015_Pad6, GND, net_U23015_Pad8, net_U23014_Pad3, net_U23015_Pad10, net_U23003_Pad10, net_U23015_Pad12, net_U23003_Pad12, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23016(net_U23016_Pad1, net_U23014_Pad12, net_U23016_Pad11, net_U23016_Pad11, net_U23016_Pad1, net_U23014_Pad6, GND, net_U23016_Pad12, net_U23016_Pad1, net_U23016_Pad10, net_U23016_Pad11, net_U23016_Pad12, net_U23016_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b1) U23017(net_U23014_Pad8, net_U23015_Pad12, net_U23017_Pad12, net_U23015_Pad6, net_U23015_Pad8, net_U23017_Pad13, GND, __A23_1__MISSY, __A23_1__PIPGYp, __A23_1__PIPGYm, net_U23017_Pad11, net_U23017_Pad12, net_U23017_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0) U23018(F5ASB2, net_U23016_Pad12, __A23_1__PIPGZp, net_U23018_Pad4, __A23_1__PIPGZm, net_U23018_Pad6, GND, net_U23018_Pad8, F5ASB2, __A23_1__F18A_n, F18A, __A23_1__F18AX, __A23_1__F18A_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U23019(net_U23019_Pad1, net_U23016_Pad12, net_U23017_Pad12, net_U23019_Pad4, net_U23017_Pad13, net_U23016_Pad12, GND, net_U23016_Pad10, net_U23014_Pad13, net_U23014_Pad3, net_U23014_Pad3, net_U23016_Pad13, net_U23014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U23020(net_U23015_Pad10, net_U23019_Pad1, net_U23014_Pad10, net_U23014_Pad10, net_U23015_Pad10, net_U23019_Pad4, GND, __A23_1__PIPGYm, net_U23020_Pad13, __A23_1__NOYM, __A23_1__NOYM, __A23_1__F18AX, net_U23020_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23021(__A23_1__NOYP, __A23_1__PIPGYp, net_U23021_Pad3, net_U23021_Pad3, __A23_1__NOYP, __A23_1__F18AX, GND, __A23_1__MISSY, F5ASB2, net_U23017_Pad11, net_U23018_Pad6, net_U23018_Pad4, __A23_1__BOTHZ, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23022(net_U23014_Pad13, net_U23015_Pad10, net_U23014_Pad3, net_U23015_Pad10, net_U23003_Pad12, PIPYM, GND, net_U23022_Pad8, net_U23018_Pad6, net_U23022_Pad10, net_U23022_Pad11, PIPYP, net_U23003_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23023(net_U23023_Pad1, net_U23022_Pad10, net_U23022_Pad11, net_U23022_Pad10, net_U23018_Pad4, net_U23023_Pad6, GND, net_U23023_Pad8, net_U23023_Pad1, net_U23022_Pad10, net_U23018_Pad6, net_U23023_Pad12, net_U23018_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b0, 1'b1) U23024(net_U23022_Pad11, net_U23024_Pad2, net_U23023_Pad1, net_U23024_Pad2, net_U23018_Pad4, net_U23024_Pad6, GND, __A23_1__MISSZ, __A23_1__PIPGZp, __A23_1__PIPGZm, net_U23024_Pad11, net_U23024_Pad12, net_U23018_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U23025(net_U23025_Pad1, net_U23022_Pad8, net_U23025_Pad3, net_U23025_Pad3, net_U23025_Pad1, net_U23023_Pad12, GND, __A23_1__PIPGZm, net_U23025_Pad13, __A23_1__NOZM, __A23_1__NOZM, __A23_1__F18AX, net_U23025_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U23026(net_U23023_Pad6, net_U23023_Pad8, net_U23026_Pad12, net_U23024_Pad12, net_U23024_Pad6, net_U23026_Pad13, GND, PIPZP, net_U23022_Pad11, net_U23024_Pad2, net_U23018_Pad4, net_U23026_Pad12, net_U23026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23027(__A23_1__NOZP, __A23_1__PIPGZp, net_U23027_Pad3, net_U23027_Pad3, __A23_1__NOZP, __A23_1__F18AX, GND, __A23_1__MISSZ, F5ASB2, net_U23024_Pad11, net_U23018_Pad8, net_U23025_Pad1, net_U23027_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23028(net_U23028_Pad1, net_U23025_Pad3, net_U23018_Pad8, net_U23028_Pad4, net_U23018_Pad8, net_U23026_Pad12, GND, net_U23026_Pad13, net_U23018_Pad8, net_U23028_Pad10, net_U23027_Pad13, net_U23022_Pad11, net_U23023_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U23029(net_U23022_Pad11, net_U23023_Pad1, net_U23028_Pad1, net_U23024_Pad2, net_U23028_Pad4, net_U23022_Pad10, GND, net_U23024_Pad2, net_U23028_Pad10, net_U23022_Pad10, CHWL16_n, WCH14_n, net_U23029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23030(net_U23023_Pad1, net_U23024_Pad2, net_U23030_Pad3, CCH14, net_U23030_Pad5, net_U23030_Pad6, GND, net_U23030_Pad8, net_U23030_Pad9, CCH14, net_U23030_Pad11, PIPZM, net_U23018_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23031(net_U23030_Pad3, net_U23029_Pad13, net_U23030_Pad6, CH1416, RCH14_n, net_U23030_Pad3, GND, net_U23030_Pad3, F5ASB2_n, CDUXD, XB0_n, net_U23031_Pad12, net_U23031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b1, 1'b1, 1'b0, 1'b0) U23032(net_U23031_Pad13, net_U23032_Pad2, OCTAD5, net_U23031_Pad12, net_U23032_Pad5, net_U23032_Pad6, GND, net_U23032_Pad8, net_U23032_Pad9, net_U23032_Pad10, net_U23032_Pad11, net_U23032_Pad12, net_U23032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23033(CDUXDP, POUT_n, net_U23032_Pad2, CDUXDM, MOUT_n, net_U23032_Pad2, GND, ZOUT_n, net_U23032_Pad2, net_U23030_Pad5, CHWL14_n, WCH14_n, net_U23033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23034(net_U23030_Pad9, net_U23033_Pad13, net_U23030_Pad8, CH1414, RCH14_n, net_U23030_Pad9, GND, net_U23030_Pad9, F5ASB2_n, CDUYD, XB1_n, net_U23031_Pad12, net_U23032_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23035(CDUYDP, POUT_n, net_U23032_Pad6, CDUYDM, MOUT_n, net_U23032_Pad6, GND, ZOUT_n, net_U23032_Pad6, net_U23030_Pad11, CHWL13_n, WCH14_n, net_U23035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23036(net_U23036_Pad1, net_U23035_Pad13, net_U23036_Pad3, CH1413, RCH14_n, net_U23036_Pad1, GND, net_U23036_Pad1, F5ASB2_n, CDUZD, XB2_n, net_U23031_Pad12, net_U23032_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23037(net_U23036_Pad1, CCH14, net_U23037_Pad3, CCH14, net_U23037_Pad5, net_U23037_Pad6, GND, net_U23037_Pad8, net_U23037_Pad9, CCH14, net_U23037_Pad11, net_U23036_Pad3, net_U23037_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23038(CDUZDP, POUT_n, net_U23032_Pad8, CDUZDM, MOUT_n, net_U23032_Pad8, GND, ZOUT_n, net_U23032_Pad8, net_U23037_Pad13, CHWL12_n, WCH14_n, net_U23038_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23039(net_U23037_Pad3, net_U23038_Pad13, net_U23037_Pad6, CH1412, RCH14_n, net_U23037_Pad3, GND, net_U23037_Pad3, F5ASB2_n, TRUND, XB3_n, net_U23031_Pad12, net_U23032_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23040(__A23_2__TRNDP, POUT_n, net_U23032_Pad10, __A23_2__TRNDM, MOUT_n, net_U23032_Pad10, GND, ZOUT_n, net_U23032_Pad10, net_U23037_Pad5, CHWL11_n, WCH14_n, net_U23040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23041(net_U23037_Pad9, net_U23040_Pad13, net_U23037_Pad8, CH1411, RCH14_n, net_U23037_Pad9, GND, net_U23037_Pad9, F5ASB2_n, SHAFTD, XB4_n, net_U23031_Pad12, net_U23032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23042(__A23_2__SHFTDP, POUT_n, net_U23032_Pad12, __A23_2__SHFTDM, MOUT_n, net_U23032_Pad12, GND, ZOUT_n, net_U23032_Pad12, net_U23037_Pad11, CHWL05_n, __A23_2__WCH07_n, net_U23042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23043(net_U23043_Pad1, net_U23042_Pad13, E5, E5, net_U23043_Pad1, __A23_2__CCH07, GND, __A23_2__RCH07_n, net_U23043_Pad1, CH0705, CHWL06_n, __A23_2__WCH07_n, net_U23043_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23044(net_U23044_Pad1, net_U23043_Pad13, E6, E6, net_U23044_Pad1, __A23_2__CCH07, GND, __A23_2__RCH07_n, net_U23044_Pad1, CH0706, CHWL07_n, __A23_2__WCH07_n, net_U23044_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23045(E7_n, net_U23044_Pad13, net_U23045_Pad3, net_U23045_Pad3, E7_n, __A23_2__CCH07, GND, __A23_2__RCH07_n, E7_n, CH0707, XB7_n, XT0_n, net_U23045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U23046(WCHG_n, XT0_n, CCHG_n, XB7_n, XT0_n, __A23_2__CCH07, GND, net_U23046_Pad8, T6ON_n, T6RPT, CCH13, net_U23046_Pad12, XB7_n, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U23047(net_U23046_Pad12, __A23_2__WCH07_n, net_U23045_Pad13, __A23_2__RCH07_n, net_U23047_Pad5, __A23_2__OT1108, GND, __A23_2__OT1113, net_U23047_Pad9, __A23_2__OT1114, net_U23047_Pad11, __A23_2__OT1116, net_U23047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23048(net_U23048_Pad1, CHWL08_n, WCH11_n, net_U23047_Pad5, net_U23048_Pad1, net_U23048_Pad10, GND, net_U23047_Pad5, CCH11, net_U23048_Pad10, RCH11_n, net_U23047_Pad5, CH1108, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23049(net_U23049_Pad1, CHWL13_n, WCH11_n, net_U23047_Pad9, net_U23049_Pad1, net_U23049_Pad10, GND, net_U23047_Pad9, CCH11, net_U23049_Pad10, RCH11_n, net_U23047_Pad9, CH1113, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23050(net_U23050_Pad1, CHWL14_n, WCH11_n, net_U23047_Pad11, net_U23050_Pad1, net_U23050_Pad10, GND, net_U23047_Pad11, CCH11, net_U23050_Pad10, RCH11_n, net_U23047_Pad11, CH1114, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23051(net_U23051_Pad1, CHWL16_n, WCH11_n, net_U23047_Pad13, net_U23051_Pad1, net_U23051_Pad10, GND, net_U23047_Pad13, CCH11, net_U23051_Pad10, RCH11_n, net_U23047_Pad13, CH1116, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23052(net_U23052_Pad1, CHWL16_n, WCH12_n, net_U23052_Pad12, net_U23052_Pad1, net_U23052_Pad10, GND, net_U23052_Pad12, CCH12, net_U23052_Pad10, RCH12_n, net_U23052_Pad12, CH1216, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0) U23053(net_U23052_Pad12, __A23_2__ISSTDC, , , net_U23053_Pad5, ALTEST, GND, __A23_1__P04A, P04_n, __A23_1__PIPSAM_n, __A23_1__PIPSAM, __A23_1__PIPAXp_n, PIPAXp, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U23054(net_U23054_Pad1, CHWL16_n, WCH13_n, T6ON_n, net_U23054_Pad1, net_U23046_Pad8, GND, RCH13_n, T6ON_n, CH1316, CHWL10_n, WCH13_n, net_U23054_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U23055(net_U23053_Pad5, net_U23054_Pad13, net_U23055_Pad3, net_U23055_Pad3, net_U23053_Pad5, CCH13, GND, RCH13_n, net_U23053_Pad5, CH1310, __A23_1__PIPSAM_n, __A23_1__PIPAXp_n, __A23_1__PIPGXp, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U23056(PIPAXm, __A23_1__PIPAXm_n, PIPAYp, __A23_1__PIPAYp_n, PIPAYm, __A23_1__PIPAYm_n, GND, __A23_1__PIPAZp_n, PIPAZp, __A23_1__PIPAZm_n, PIPAZm, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23057(__A23_1__PIPGXm, __A23_1__PIPSAM_n, __A23_1__PIPAXm_n, __A23_1__PIPGYp, __A23_1__PIPSAM_n, __A23_1__PIPAYp_n, GND, __A23_1__PIPSAM_n, __A23_1__PIPAYm_n, __A23_1__PIPGYm, __A23_1__PIPSAM_n, __A23_1__PIPAZp_n, __A23_1__PIPGZp, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U23058(__A23_1__PIPGZm, __A23_1__PIPSAM_n, __A23_1__PIPAZm_n, , , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module ch77_alarm_box(SIM_RST, SIM_CLK, p4VSW, GND, MDT01, MT01, MDT02, MT05, MDT03, MT12, MDT04, MWL01, MDT05, MWL02, MDT06, MWL03, MDT07, MWL04, MDT08, MWL05, MDT09, MWL06, MDT10, MRCH, MDT11, MWCH, MDT12, MWSG, MDT13, MPAL_n, MDT14, MTCAL_n, MDT15, MRPTAL_n, MDT16, MWATCH_n, MNHSBF, MVFAIL_n, MNHNC, MCTRAL_n, MNHRPT, MSCAFL_n, MTCSAI, MSCDBL_n, MSTRT, MAMU, MSTP, MSBSTP, MRDCH, MLDCH, MONPAR, MONWBK, MLOAD, MREAD, NHALGA, DOSCAL, DBLTST);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
output wire DBLTST;
output wire DOSCAL;
output wire MAMU;
input wire MCTRAL_n;
output wire MDT01;
output wire MDT02;
output wire MDT03;
output wire MDT04;
output wire MDT05;
output wire MDT06;
output wire MDT07;
output wire MDT08;
output wire MDT09;
output wire MDT10;
output wire MDT11;
output wire MDT12;
output wire MDT13;
output wire MDT14;
output wire MDT15;
output wire MDT16;
output wire MLDCH;
output wire MLOAD;
output wire MNHNC;
output wire MNHRPT;
output wire MNHSBF;
output wire MONPAR;
output wire MONWBK;
input wire MPAL_n;
input wire MRCH;
output wire MRDCH;
output wire MREAD;
input wire MRPTAL_n;
output wire MSBSTP;
input wire MSCAFL_n;
input wire MSCDBL_n;
output wire MSTP;
output wire MSTRT;
input wire MT01;
input wire MT05;
input wire MT12;
input wire MTCAL_n;
output wire MTCSAI;
input wire MVFAIL_n;
input wire MWATCH_n;
input wire MWCH;
input wire MWL01;
input wire MWL02;
input wire MWL03;
input wire MWL04;
input wire MWL05;
input wire MWL06;
input wire MWSG;
output wire NHALGA;
wire __RestartMonitor__CCH77;
wire __RestartMonitor__RCH77_n;
wire net_R77009_Pad2; //FPGA#wand
wire net_U77001_Pad10;
wire net_U77001_Pad12;
wire net_U77001_Pad2;
wire net_U77001_Pad4;
wire net_U77001_Pad6;
wire net_U77001_Pad8;
wire net_U77002_Pad11;
wire net_U77002_Pad12;
wire net_U77002_Pad2;
wire net_U77002_Pad4;
wire net_U77002_Pad6;
wire net_U77002_Pad8;
wire net_U77003_Pad1;
wire net_U77003_Pad13;
wire net_U77005_Pad1;
wire net_U77005_Pad12;
wire net_U77006_Pad1;
wire net_U77006_Pad10;
wire net_U77006_Pad13;
wire net_U77006_Pad3;
wire net_U77006_Pad8;
wire net_U77007_Pad10;
wire net_U77007_Pad11;
wire net_U77007_Pad12;
wire net_U77007_Pad13;
wire net_U77007_Pad3;
wire net_U77007_Pad4;
wire net_U77007_Pad5;
wire net_U77008_Pad10;
wire net_U77008_Pad12;
wire net_U77008_Pad8;
wire net_U77009_Pad10;
wire net_U77009_Pad12;
wire net_U77009_Pad13;
wire net_U77009_Pad4;
wire net_U77010_Pad10;
wire net_U77010_Pad11;
wire net_U77010_Pad12;
wire net_U77010_Pad13;
wire net_U77010_Pad4;
wire net_U77011_Pad10;
wire net_U77011_Pad4;
wire net_U77011_Pad5;
pullup R77001(MWL01);
pullup R77002(MWL02);
pullup R77003(MWL03);
pullup R77004(MWL04);
pullup R77005(MWL05);
pullup R77006(MWL06);
pullup R77007(MT01);
pullup R77008(MWSG);
pullup R77009(net_R77009_Pad2);
pullup R77010(MT12);
pullup R77011(MWCH);
pullup R77012(MRCH);
pullup R77013(MT05);
pullup R77014(MTCAL_n);
pullup R77015(MRPTAL_n);
pullup R77016(MWATCH_n);
pullup R77017(MVFAIL_n);
pullup R77018(MCTRAL_n);
pullup R77019(MSCAFL_n);
pullup R77020(MSCDBL_n);
pulldown R77021(MDT10);
pulldown R77022(MDT11);
pulldown R77023(MDT12);
pulldown R77024(MDT13);
pulldown R77025(MDT14);
pulldown R77026(MDT15);
pulldown R77027(MDT16);
pulldown R77028(MNHSBF);
pulldown R77029(MNHNC);
pulldown R77030(MNHRPT);
pulldown R77031(MTCSAI);
pulldown R77032(MSTRT);
pulldown R77033(MSTP);
pulldown R77034(MSBSTP);
pulldown R77035(MRDCH);
pulldown R77036(MLDCH);
pulldown R77037(MONPAR);
pulldown R77038(MONWBK);
pulldown R77039(MLOAD);
pulldown R77040(MREAD);
pulldown R77041(NHALGA);
pulldown R77042(DOSCAL);
pulldown R77043(DBLTST);
pulldown R77044(MAMU);
pullup R77045(MPAL_n);
U74HC04 U77001(MWL01, net_U77001_Pad2, MWL02, net_U77001_Pad4, MWL03, net_U77001_Pad6, GND, net_U77001_Pad8, MWL04, net_U77001_Pad10, MWL05, net_U77001_Pad12, MWL06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0) U77002(MT01, net_U77002_Pad2, MWSG, net_U77002_Pad4, MWCH, net_U77002_Pad6, GND, net_U77002_Pad8, MRCH, __RestartMonitor__RCH77_n, net_U77002_Pad11, net_U77002_Pad12, MPAL_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U77003(net_U77003_Pad1, net_U77001_Pad2, net_U77001_Pad4, net_U77001_Pad6, net_U77001_Pad8, , GND, , net_U77001_Pad10, net_U77001_Pad12, net_U77002_Pad2, net_U77002_Pad4, net_U77003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U77004(net_U77003_Pad1, net_R77009_Pad2, net_U77003_Pad13, net_R77009_Pad2, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U77005(net_U77005_Pad1, MT12, net_U77005_Pad12, net_U77005_Pad12, net_U77005_Pad1, net_R77009_Pad2, GND, net_U77002_Pad8, net_U77005_Pad12, net_U77002_Pad11, net_U77002_Pad6, net_U77005_Pad12, __RestartMonitor__CCH77, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U77006(net_U77006_Pad1, net_U77002_Pad12, net_U77006_Pad3, net_U77006_Pad3, net_U77006_Pad1, __RestartMonitor__CCH77, GND, net_U77006_Pad8, net_U77006_Pad13, net_U77006_Pad10, net_U77006_Pad10, __RestartMonitor__CCH77, net_U77006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77007(net_U77006_Pad8, MPAL_n, net_U77007_Pad3, net_U77007_Pad4, net_U77007_Pad5, net_U77007_Pad10, GND, net_U77007_Pad4, __RestartMonitor__CCH77, net_U77007_Pad10, net_U77007_Pad11, net_U77007_Pad12, net_U77007_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U77008(MT05, net_U77007_Pad3, MTCAL_n, net_U77007_Pad5, MRPTAL_n, net_U77007_Pad11, GND, net_U77008_Pad8, MWATCH_n, net_U77008_Pad10, MVFAIL_n, net_U77008_Pad12, MCTRAL_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77009(net_U77007_Pad12, net_U77007_Pad13, __RestartMonitor__CCH77, net_U77009_Pad4, net_U77008_Pad8, net_U77009_Pad10, GND, net_U77009_Pad4, __RestartMonitor__CCH77, net_U77009_Pad10, net_U77008_Pad10, net_U77009_Pad12, net_U77009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77010(net_U77009_Pad12, net_U77009_Pad13, __RestartMonitor__CCH77, net_U77010_Pad4, net_U77008_Pad12, net_U77010_Pad10, GND, net_U77010_Pad4, __RestartMonitor__CCH77, net_U77010_Pad10, net_U77010_Pad11, net_U77010_Pad12, net_U77010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U77011(net_U77010_Pad12, net_U77010_Pad13, __RestartMonitor__CCH77, net_U77011_Pad4, net_U77011_Pad5, net_U77011_Pad10, GND, net_U77011_Pad4, __RestartMonitor__CCH77, net_U77011_Pad10, , , , p4VSW, SIM_RST, SIM_CLK);
U74HC04 U77012(MSCAFL_n, net_U77010_Pad11, MSCDBL_n, net_U77011_Pad5, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77013(__RestartMonitor__RCH77_n, net_U77006_Pad1, __RestartMonitor__RCH77_n, net_U77006_Pad10, GND, MDT02, GND, MDT03, __RestartMonitor__RCH77_n, net_U77007_Pad4, GND, MDT01, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77014(__RestartMonitor__RCH77_n, net_U77007_Pad13, __RestartMonitor__RCH77_n, net_U77009_Pad4, GND, MDT05, GND, MDT06, __RestartMonitor__RCH77_n, net_U77009_Pad13, GND, MDT04, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77015(__RestartMonitor__RCH77_n, net_U77010_Pad4, __RestartMonitor__RCH77_n, net_U77010_Pad13, GND, MDT08, GND, MDT09, __RestartMonitor__RCH77_n, net_U77011_Pad4, GND, MDT07, GND, p4VSW, SIM_RST, SIM_CLK);
endmodule |
module four_bit_1(SIM_RST, SIM_CLK, p4VSW, GND, A2XG_n, CAG, CBG, CGG, CLG1G, CLXC, CQG, CUG, CZG, L2GDG_n, RAG_n, RCG_n, RGG_n, RLG_n, RQG_n, RZG_n, WAG_n, WALSG_n, WBG_n, WLG_n, WQG_n, WZG_n, CI01_n, MONEX, PONEX, TWOX, XUY05_n, XUY06_n, CH01, CH02, CH03, CH04, G01ED, G02ED, G03ED, G04ED, MCRO_n, G2LSG_n, G05_n, G06_n, G07_n, MDT01, MDT02, MDT03, MDT04, SA01, SA02, SA03, SA04, RBLG_n, RULOG_n, WL05_n, WL06_n, WG1G_n, WG3G_n, WG4G_n, WYDLOG_n, WYDG_n, WYLOG_n, RB1, R1C, R15, RB2, WL16_n, WHOMP, WHOMPA, CI05_n, CO06, G01, G01_n, G02, G03, G04, L01_n, L02_n, L04_n, RL01_n, RL02_n, RL03_n, RL04_n, SUMA01_n, SUMB01_n, SUMA02_n, SUMB02_n, SUMA03_n, SUMB03_n, WL01, WL01_n, WL02, WL02_n, WL03, WL03_n, WL04, WL04_n, XUY01_n, XUY02_n, GEM01, GEM02, GEM03, GEM04, MWL01, MWL02, MWL03, MWL04);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire A2XG_n;
input wire CAG;
input wire CBG;
input wire CGG;
input wire CH01;
input wire CH02;
input wire CH03;
input wire CH04;
input wire CI01_n;
output wire CI05_n;
input wire CLG1G;
input wire CLXC;
output wire CO06; //FPGA#wand
input wire CQG;
input wire CUG;
input wire CZG;
output wire G01;
input wire G01ED;
inout wire G01_n; //FPGA#wand
output wire G02;
input wire G02ED;
output wire G03;
input wire G03ED;
output wire G04;
input wire G04ED;
input wire G05_n;
input wire G06_n;
input wire G07_n;
input wire G2LSG_n;
output wire GEM01;
output wire GEM02;
output wire GEM03;
output wire GEM04;
inout wire L01_n; //FPGA#wand
inout wire L02_n; //FPGA#wand
inout wire L04_n; //FPGA#wand
input wire L2GDG_n;
input wire MCRO_n;
input wire MDT01;
input wire MDT02;
input wire MDT03;
input wire MDT04;
input wire MONEX;
output wire MWL01; //FPGA#wand
output wire MWL02; //FPGA#wand
output wire MWL03; //FPGA#wand
output wire MWL04; //FPGA#wand
input wire PONEX;
input wire R15;
input wire R1C;
input wire RAG_n;
input wire RB1;
input wire RB2;
input wire RBLG_n;
input wire RCG_n;
input wire RGG_n;
inout wire RL01_n; //FPGA#wand
inout wire RL02_n; //FPGA#wand
inout wire RL03_n; //FPGA#wand
inout wire RL04_n; //FPGA#wand
input wire RLG_n;
input wire RQG_n;
input wire RULOG_n;
input wire RZG_n;
input wire SA01;
input wire SA02;
input wire SA03;
input wire SA04;
output wire SUMA01_n;
output wire SUMA02_n;
output wire SUMA03_n;
output wire SUMB01_n;
output wire SUMB02_n;
output wire SUMB03_n;
input wire TWOX;
input wire WAG_n;
input wire WALSG_n;
input wire WBG_n;
input wire WG1G_n;
input wire WG3G_n;
input wire WG4G_n;
input wire WHOMP;
input wire WHOMPA;
output wire WL01;
output wire WL01_n;
output wire WL02;
output wire WL02_n;
output wire WL03;
output wire WL03_n;
output wire WL04;
output wire WL04_n;
input wire WL05_n;
input wire WL06_n;
input wire WL16_n;
input wire WLG_n;
input wire WQG_n;
input wire WYDG_n;
input wire WYDLOG_n;
input wire WYLOG_n;
input wire WZG_n;
output wire XUY01_n;
output wire XUY02_n;
input wire XUY05_n;
input wire XUY06_n;
wire __A08_1__X1;
wire __A08_1__X1_n;
wire __A08_1__X2;
wire __A08_1__X2_n;
wire __A08_1__Y1;
wire __A08_1__Y1_n;
wire __A08_1__Y2;
wire __A08_1__Y2_n;
wire __A08_1___A1_n;
wire __A08_1___A2_n;
wire __A08_1___B1_n;
wire __A08_1___B2_n;
wire __A08_1___CI_INTERNAL;
wire __A08_1___G2_n; //FPGA#wand
wire __A08_1___Q1_n;
wire __A08_1___Q2_n;
wire __A08_1___RL_OUT_1;
wire __A08_1___RL_OUT_2;
wire __A08_1___Z1_n; //FPGA#wand
wire __A08_1___Z2_n; //FPGA#wand
wire __A08_2__X1;
wire __A08_2__X1_n;
wire __A08_2__X2;
wire __A08_2__X2_n;
wire __A08_2__Y1;
wire __A08_2__Y1_n;
wire __A08_2__Y2;
wire __A08_2__Y2_n;
wire __A08_2___A1_n;
wire __A08_2___A2_n;
wire __A08_2___B1_n;
wire __A08_2___B2_n;
wire __A08_2___CI_INTERNAL;
wire __A08_2___G1_n; //FPGA#wand
wire __A08_2___Q1_n;
wire __A08_2___Q2_n;
wire __A08_2___RL_OUT_1;
wire __A08_2___RL_OUT_2;
wire __A08_2___SUMA2;
wire __A08_2___SUMB2;
wire __A08_2___Z1_n; //FPGA#wand
wire __A08_2___Z2_n; //FPGA#wand
wire __CI03_n;
wire __CO04; //FPGA#wand
wire __G04_n; //FPGA#wand
wire __L03_n; //FPGA#wand
wire __XUY03_n;
wire __XUY04_n;
wire net_U8001_Pad1;
wire net_U8001_Pad10;
wire net_U8001_Pad4;
wire net_U8003_Pad1;
wire net_U8003_Pad10;
wire net_U8004_Pad1;
wire net_U8004_Pad12;
wire net_U8004_Pad13;
wire net_U8004_Pad2;
wire net_U8004_Pad6;
wire net_U8004_Pad8;
wire net_U8005_Pad12;
wire net_U8005_Pad2;
wire net_U8006_Pad10;
wire net_U8006_Pad13;
wire net_U8006_Pad4;
wire net_U8007_Pad11;
wire net_U8007_Pad13;
wire net_U8007_Pad3;
wire net_U8007_Pad5;
wire net_U8007_Pad9;
wire net_U8008_Pad1;
wire net_U8008_Pad10;
wire net_U8008_Pad13;
wire net_U8008_Pad4;
wire net_U8009_Pad1;
wire net_U8009_Pad13;
wire net_U8009_Pad4;
wire net_U8010_Pad1;
wire net_U8010_Pad13;
wire net_U8010_Pad4;
wire net_U8011_Pad10;
wire net_U8011_Pad11;
wire net_U8011_Pad13;
wire net_U8011_Pad8;
wire net_U8011_Pad9;
wire net_U8012_Pad13;
wire net_U8012_Pad4;
wire net_U8013_Pad1;
wire net_U8013_Pad11;
wire net_U8013_Pad13;
wire net_U8013_Pad5;
wire net_U8013_Pad9;
wire net_U8014_Pad10;
wire net_U8014_Pad13;
wire net_U8016_Pad1;
wire net_U8016_Pad4;
wire net_U8018_Pad11;
wire net_U8018_Pad12;
wire net_U8018_Pad13;
wire net_U8019_Pad1;
wire net_U8019_Pad10;
wire net_U8019_Pad4;
wire net_U8021_Pad1;
wire net_U8021_Pad13;
wire net_U8022_Pad1;
wire net_U8022_Pad12;
wire net_U8022_Pad8;
wire net_U8023_Pad10;
wire net_U8023_Pad13;
wire net_U8023_Pad4;
wire net_U8024_Pad10;
wire net_U8024_Pad11;
wire net_U8024_Pad4;
wire net_U8024_Pad9;
wire net_U8026_Pad4;
wire net_U8026_Pad5;
wire net_U8026_Pad6;
wire net_U8026_Pad8;
wire net_U8027_Pad1;
wire net_U8027_Pad10;
wire net_U8028_Pad13;
wire net_U8028_Pad3;
wire net_U8028_Pad9;
wire net_U8029_Pad1;
wire net_U8029_Pad10;
wire net_U8030_Pad1;
wire net_U8030_Pad10;
wire net_U8030_Pad13;
wire net_U8031_Pad13;
wire net_U8031_Pad2;
wire net_U8031_Pad3;
wire net_U8031_Pad4;
wire net_U8031_Pad8;
wire net_U8035_Pad1;
wire net_U8035_Pad10;
wire net_U8035_Pad4;
wire net_U8037_Pad1;
wire net_U8037_Pad10;
wire net_U8038_Pad1;
wire net_U8038_Pad12;
wire net_U8038_Pad2;
wire net_U8038_Pad6;
wire net_U8038_Pad8;
wire net_U8039_Pad12;
wire net_U8039_Pad2;
wire net_U8040_Pad10;
wire net_U8040_Pad13;
wire net_U8040_Pad4;
wire net_U8041_Pad11;
wire net_U8041_Pad13;
wire net_U8041_Pad3;
wire net_U8041_Pad5;
wire net_U8041_Pad9;
wire net_U8042_Pad10;
wire net_U8042_Pad11;
wire net_U8042_Pad4;
wire net_U8042_Pad9;
wire net_U8044_Pad1;
wire net_U8044_Pad6;
wire net_U8045_Pad13;
wire net_U8045_Pad4;
wire net_U8046_Pad1;
wire net_U8046_Pad13;
wire net_U8046_Pad4;
wire net_U8047_Pad1;
wire net_U8047_Pad13;
wire net_U8047_Pad4;
wire net_U8048_Pad1;
wire net_U8048_Pad10;
wire net_U8048_Pad13;
wire net_U8048_Pad4;
wire net_U8049_Pad11;
wire net_U8049_Pad8;
wire net_U8050_Pad11;
wire net_U8050_Pad13;
wire net_U8050_Pad5;
wire net_U8052_Pad11;
wire net_U8052_Pad12;
wire net_U8052_Pad13;
wire net_U8053_Pad1;
wire net_U8053_Pad10;
wire net_U8053_Pad4;
wire net_U8055_Pad13;
wire net_U8056_Pad10;
wire net_U8056_Pad13;
wire net_U8056_Pad4;
wire net_U8057_Pad10;
wire net_U8057_Pad11;
wire net_U8057_Pad4;
wire net_U8057_Pad9;
wire net_U8059_Pad4;
wire net_U8059_Pad5;
wire net_U8059_Pad6;
wire net_U8059_Pad8;
wire net_U8060_Pad1;
wire net_U8060_Pad10;
wire net_U8061_Pad3;
wire net_U8062_Pad1;
wire net_U8062_Pad10;
wire net_U8063_Pad1;
wire net_U8063_Pad10;
pullup R8001(__CO04);
pullup R8002(RL01_n);
pullup R8003(L01_n);
pullup R8005(__A08_1___Z1_n);
pullup R8006(G01_n);
pullup R8007(RL02_n);
pullup R8008(L02_n);
pullup R8009(__A08_1___Z2_n);
pullup R8010(__A08_1___G2_n);
pullup R8011(CO06);
pullup R8012(RL03_n);
pullup R8013(__L03_n);
pullup R8015(__A08_2___Z1_n);
pullup R8016(__A08_2___G1_n);
pullup R8017(RL04_n);
pullup R8018(L04_n);
pullup R8019(__A08_2___Z2_n);
pullup R8020(__G04_n);
U74HC02 U8001(net_U8001_Pad1, A2XG_n, __A08_1___A1_n, net_U8001_Pad4, WYLOG_n, WL01_n, GND, WL16_n, WYDLOG_n, net_U8001_Pad10, __A08_1__Y1_n, CUG, __A08_1__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8002(PONEX, net_U8001_Pad1, __A08_1__X1_n, CLXC, CUG, __A08_1__X1, GND, __A08_1__Y1_n, net_U8001_Pad4, net_U8001_Pad10, __A08_1__Y1, __A08_1__X1_n, __A08_1__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8003(net_U8003_Pad1, __A08_1__X1_n, __A08_1__Y1_n, XUY01_n, __A08_1__X1, __A08_1__Y1, GND, net_U8003_Pad1, XUY01_n, net_U8003_Pad10, net_U8003_Pad1, SUMA01_n, __A08_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8004(net_U8004_Pad1, net_U8004_Pad2, SUMA01_n, SUMB01_n, RULOG_n, net_U8004_Pad6, GND, net_U8004_Pad8, __XUY03_n, XUY01_n, CI01_n, net_U8004_Pad12, net_U8004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U8005(CI01_n, net_U8005_Pad2, G01_n, GEM01, RL01_n, WL01, GND, WL01_n, WL01, , , net_U8005_Pad12, __A08_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8006(SUMB01_n, net_U8003_Pad10, net_U8005_Pad2, net_U8006_Pad4, WAG_n, WL01_n, GND, WL03_n, WALSG_n, net_U8006_Pad10, __A08_1___A1_n, CAG, net_U8006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8007(net_U8004_Pad8, __CO04, net_U8007_Pad3, RL01_n, net_U8007_Pad5, L01_n, GND, __A08_1___Z1_n, net_U8007_Pad9, RL01_n, net_U8007_Pad11, RL01_n, net_U8007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U8008(net_U8008_Pad1, RAG_n, __A08_1___A1_n, net_U8008_Pad4, WLG_n, WL01_n, GND, __G04_n, G2LSG_n, net_U8008_Pad10, L01_n, CLG1G, net_U8008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8009(net_U8009_Pad1, WG1G_n, WL04_n, net_U8009_Pad4, WQG_n, WL01_n, GND, net_U8009_Pad4, net_U8009_Pad13, __A08_1___Q1_n, __A08_1___Q1_n, CQG, net_U8009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8010(net_U8010_Pad1, RQG_n, __A08_1___Q1_n, net_U8010_Pad4, WZG_n, WL01_n, GND, net_U8010_Pad4, net_U8010_Pad13, net_U8007_Pad9, __A08_1___Z1_n, CZG, net_U8010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8011(__A08_1___RL_OUT_1, net_U8010_Pad1, MDT01, RB1, R15, net_U8007_Pad13, GND, net_U8011_Pad8, net_U8011_Pad9, net_U8011_Pad10, net_U8011_Pad11, net_U8007_Pad11, net_U8011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8012(net_U8011_Pad13, RZG_n, __A08_1___Z1_n, net_U8012_Pad4, WBG_n, WL01_n, GND, net_U8012_Pad4, net_U8012_Pad13, __A08_1___B1_n, __A08_1___B1_n, CBG, net_U8012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8013(net_U8013_Pad1, __CO04, net_U8011_Pad8, RL01_n, net_U8013_Pad5, G01_n, GND, G01_n, net_U8013_Pad9, RL02_n, net_U8013_Pad11, L02_n, net_U8013_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U8014(net_U8011_Pad9, RBLG_n, __A08_1___B1_n, net_U8011_Pad10, net_U8012_Pad13, RCG_n, GND, WL16_n, WG3G_n, net_U8014_Pad10, WL02_n, WG4G_n, net_U8014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8015(net_U8006_Pad4, net_U8006_Pad10, net_U8004_Pad6, net_U8008_Pad1, CH01, net_U8007_Pad3, GND, net_U8007_Pad5, net_U8008_Pad4, net_U8008_Pad10, net_U8008_Pad13, __A08_1___A1_n, net_U8006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8016(net_U8016_Pad1, L2GDG_n, MCRO_n, net_U8016_Pad4, WG1G_n, WL01_n, GND, G01_n, CGG, G01, RGG_n, G01_n, net_U8011_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U8017(net_U8016_Pad1, net_U8016_Pad4, WHOMPA, __XUY04_n, XUY02_n, net_U8013_Pad1, GND, __A08_1___RL_OUT_1, RLG_n, L01_n, GND, net_U8013_Pad9, G01, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U8018(net_U8013_Pad5, G01ED, SA01, net_U8014_Pad10, net_U8014_Pad13, , GND, , G02ED, SA02, net_U8018_Pad11, net_U8018_Pad12, net_U8018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8019(net_U8019_Pad1, A2XG_n, __A08_1___A2_n, net_U8019_Pad4, WYLOG_n, WL02_n, GND, WL01_n, WYDG_n, net_U8019_Pad10, __A08_1__Y2_n, CUG, __A08_1__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8020(TWOX, net_U8019_Pad1, __A08_1__X2_n, CLXC, CUG, __A08_1__X2, GND, __A08_1__Y2_n, net_U8019_Pad4, net_U8019_Pad10, __A08_1__Y2, __A08_1__X2_n, __A08_1__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8021(net_U8021_Pad1, __A08_1__X2_n, __A08_1__Y2_n, XUY02_n, __A08_1__X2, __A08_1__Y2, GND, __G04_n, CGG, G04, net_U8021_Pad1, XUY02_n, net_U8021_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U8022(net_U8022_Pad1, net_U8009_Pad1, net_U8021_Pad1, SUMA02_n, GND, __CI03_n, GND, net_U8022_Pad8, SUMA02_n, SUMB02_n, RULOG_n, net_U8022_Pad12, G04, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8023(SUMB02_n, net_U8021_Pad13, net_U8005_Pad12, net_U8023_Pad4, WAG_n, WL02_n, GND, WL04_n, WALSG_n, net_U8023_Pad10, __A08_1___A2_n, CAG, net_U8023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8024(net_U8023_Pad4, net_U8023_Pad10, net_U8022_Pad8, net_U8024_Pad4, CH02, net_U8013_Pad11, GND, net_U8013_Pad13, net_U8024_Pad9, net_U8024_Pad10, net_U8024_Pad11, __A08_1___A2_n, net_U8023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8025(net_U8024_Pad4, RAG_n, __A08_1___A2_n, net_U8024_Pad9, WLG_n, WL02_n, GND, G05_n, G2LSG_n, net_U8024_Pad10, L02_n, CLG1G, net_U8024_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8026(RLG_n, L02_n, __A08_1___RL_OUT_2, net_U8026_Pad4, net_U8026_Pad5, net_U8026_Pad6, GND, net_U8026_Pad8, MDT02, R1C, RB2, __A08_1___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8027(net_U8027_Pad1, WQG_n, WL02_n, __A08_1___Q2_n, net_U8027_Pad1, net_U8027_Pad10, GND, __A08_1___Q2_n, CQG, net_U8027_Pad10, RQG_n, __A08_1___Q2_n, net_U8026_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8028(net_U8026_Pad6, RL02_n, net_U8028_Pad3, __A08_1___Z2_n, net_U8026_Pad8, RL02_n, GND, RL02_n, net_U8028_Pad9, __A08_1___G2_n, net_U8018_Pad13, __A08_1___G2_n, net_U8028_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8029(net_U8029_Pad1, WZG_n, WL02_n, net_U8028_Pad3, net_U8029_Pad1, net_U8029_Pad10, GND, __A08_1___Z2_n, CZG, net_U8029_Pad10, RZG_n, __A08_1___Z2_n, net_U8026_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8030(net_U8030_Pad1, WBG_n, WL02_n, __A08_1___B2_n, net_U8030_Pad1, net_U8030_Pad10, GND, __A08_1___B2_n, CBG, net_U8030_Pad10, RBLG_n, __A08_1___B2_n, net_U8030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U8031(net_U8030_Pad13, net_U8031_Pad2, net_U8031_Pad3, net_U8031_Pad4, G02, net_U8028_Pad13, GND, net_U8031_Pad8, GND, XUY06_n, __XUY04_n, net_U8028_Pad9, net_U8031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8032(net_U8031_Pad2, net_U8030_Pad10, RCG_n, net_U8018_Pad11, WL01_n, WG3G_n, GND, WL03_n, WG4G_n, net_U8018_Pad12, L2GDG_n, L01_n, net_U8031_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8033(net_U8031_Pad4, WG1G_n, WL02_n, G02, __A08_1___G2_n, CGG, GND, RGG_n, __A08_1___G2_n, net_U8031_Pad13, RGG_n, __G04_n, net_U8004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U8034(__A08_1___G2_n, GEM02, RL02_n, WL02, WL02, WL02_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8035(net_U8035_Pad1, A2XG_n, __A08_2___A1_n, net_U8035_Pad4, WYLOG_n, WL03_n, GND, WL02_n, WYDG_n, net_U8035_Pad10, __A08_2__Y1_n, CUG, __A08_2__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8036(MONEX, net_U8035_Pad1, __A08_2__X1_n, CLXC, CUG, __A08_2__X1, GND, __A08_2__Y1_n, net_U8035_Pad4, net_U8035_Pad10, __A08_2__Y1, __A08_2__X1_n, __A08_2__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8037(net_U8037_Pad1, __A08_2__X1_n, __A08_2__Y1_n, __XUY03_n, __A08_2__X1, __A08_2__Y1, GND, net_U8037_Pad1, __XUY03_n, net_U8037_Pad10, net_U8037_Pad1, SUMA03_n, __A08_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U8038(net_U8038_Pad1, net_U8038_Pad2, SUMA03_n, SUMB03_n, RULOG_n, net_U8038_Pad6, GND, net_U8038_Pad8, XUY05_n, __XUY03_n, __CI03_n, net_U8038_Pad12, G03, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U8039(__CI03_n, net_U8039_Pad2, __A08_2___G1_n, GEM03, RL03_n, WL03, GND, WL03_n, WL03, , , net_U8039_Pad12, __A08_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8040(SUMB03_n, net_U8037_Pad10, net_U8039_Pad2, net_U8040_Pad4, WAG_n, WL03_n, GND, WL05_n, WALSG_n, net_U8040_Pad10, __A08_2___A1_n, CAG, net_U8040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8041(net_U8038_Pad8, CO06, net_U8041_Pad3, RL03_n, net_U8041_Pad5, __L03_n, GND, __A08_2___Z1_n, net_U8041_Pad9, RL03_n, net_U8041_Pad11, RL03_n, net_U8041_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 #(1'b1, 1'b0, 1'b1) U8042(net_U8040_Pad4, net_U8040_Pad10, net_U8038_Pad6, net_U8042_Pad4, CH03, net_U8041_Pad3, GND, net_U8041_Pad5, net_U8042_Pad9, net_U8042_Pad10, net_U8042_Pad11, __A08_2___A1_n, net_U8040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8043(net_U8042_Pad4, RAG_n, __A08_2___A1_n, net_U8042_Pad9, WLG_n, WL03_n, GND, G06_n, G2LSG_n, net_U8042_Pad10, __L03_n, CLG1G, net_U8042_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8044(net_U8044_Pad1, __A08_2___SUMA2, __A08_2___SUMA2, __A08_2___SUMB2, RULOG_n, net_U8044_Pad6, GND, __A08_2___RL_OUT_1, RLG_n, __L03_n, GND, CI05_n, __CO04, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8045( , , , net_U8045_Pad4, WQG_n, WL03_n, GND, net_U8045_Pad4, net_U8045_Pad13, __A08_2___Q1_n, __A08_2___Q1_n, CQG, net_U8045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8046(net_U8046_Pad1, RQG_n, __A08_2___Q1_n, net_U8046_Pad4, WZG_n, WL03_n, GND, net_U8046_Pad4, net_U8046_Pad13, net_U8041_Pad9, __A08_2___Z1_n, CZG, net_U8046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U8047(net_U8047_Pad1, RZG_n, __A08_2___Z1_n, net_U8047_Pad4, WBG_n, WL03_n, GND, net_U8047_Pad4, net_U8047_Pad13, __A08_2___B1_n, __A08_2___B1_n, CBG, net_U8047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8048(net_U8048_Pad1, RBLG_n, __A08_2___B1_n, net_U8048_Pad4, net_U8047_Pad13, RCG_n, GND, WL02_n, WG3G_n, net_U8048_Pad10, WL04_n, WG4G_n, net_U8048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8049(__A08_2___RL_OUT_1, net_U8046_Pad1, MDT03, R1C, R15, net_U8041_Pad13, GND, net_U8049_Pad8, net_U8048_Pad1, net_U8048_Pad4, net_U8049_Pad11, net_U8041_Pad11, net_U8047_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8050(net_U8031_Pad8, CO06, net_U8049_Pad8, RL03_n, net_U8050_Pad5, __A08_2___G1_n, GND, __A08_2___G1_n, net_U8038_Pad12, RL04_n, net_U8050_Pad11, L04_n, net_U8050_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U8051(net_U8038_Pad1, L2GDG_n, L02_n, net_U8038_Pad2, WG1G_n, WL03_n, GND, __A08_2___G1_n, CGG, G03, RGG_n, __A08_2___G1_n, net_U8049_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U8052(net_U8050_Pad5, G03ED, SA03, net_U8048_Pad10, net_U8048_Pad13, , GND, , G04ED, SA04, net_U8052_Pad11, net_U8052_Pad12, net_U8052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8053(net_U8053_Pad1, A2XG_n, __A08_2___A2_n, net_U8053_Pad4, WYLOG_n, WL04_n, GND, WL03_n, WYDG_n, net_U8053_Pad10, __A08_2__Y2_n, CUG, __A08_2__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8054(MONEX, net_U8053_Pad1, __A08_2__X2_n, CLXC, CUG, __A08_2__X2, GND, __A08_2__Y2_n, net_U8053_Pad4, net_U8053_Pad10, __A08_2__Y2, __A08_2__X2_n, __A08_2__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8055(net_U8044_Pad1, __A08_2__X2_n, __A08_2__Y2_n, __XUY04_n, __A08_2__X2, __A08_2__Y2, GND, , , , net_U8044_Pad1, __XUY04_n, net_U8055_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8056(__A08_2___SUMB2, net_U8055_Pad13, net_U8039_Pad12, net_U8056_Pad4, WAG_n, WL04_n, GND, WL06_n, WALSG_n, net_U8056_Pad10, __A08_2___A2_n, CAG, net_U8056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U8057(net_U8056_Pad4, net_U8056_Pad10, net_U8044_Pad6, net_U8057_Pad4, CH04, net_U8050_Pad11, GND, net_U8050_Pad13, net_U8057_Pad9, net_U8057_Pad10, net_U8057_Pad11, __A08_2___A2_n, net_U8056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8058(net_U8057_Pad4, RAG_n, __A08_2___A2_n, net_U8057_Pad9, WLG_n, WL04_n, GND, G07_n, G2LSG_n, net_U8057_Pad10, L04_n, CLG1G, net_U8057_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U8059(RLG_n, L04_n, __A08_2___RL_OUT_2, net_U8059_Pad4, net_U8059_Pad5, net_U8059_Pad6, GND, net_U8059_Pad8, MDT04, R1C, R15, __A08_2___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8060(net_U8060_Pad1, WQG_n, WL04_n, __A08_2___Q2_n, net_U8060_Pad1, net_U8060_Pad10, GND, __A08_2___Q2_n, CQG, net_U8060_Pad10, RQG_n, __A08_2___Q2_n, net_U8059_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U8061(net_U8059_Pad6, RL04_n, net_U8061_Pad3, __A08_2___Z2_n, net_U8059_Pad8, RL04_n, GND, RL04_n, net_U8004_Pad12, __G04_n, net_U8052_Pad13, __G04_n, net_U8022_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8062(net_U8062_Pad1, WZG_n, WL04_n, net_U8061_Pad3, net_U8062_Pad1, net_U8062_Pad10, GND, __A08_2___Z2_n, CZG, net_U8062_Pad10, RZG_n, __A08_2___Z2_n, net_U8059_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U8063(net_U8063_Pad1, WBG_n, WL04_n, __A08_2___B2_n, net_U8063_Pad1, net_U8063_Pad10, GND, __A08_2___B2_n, CBG, net_U8063_Pad10, RBLG_n, __A08_2___B2_n, net_U8004_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U8064(net_U8004_Pad2, net_U8063_Pad10, RCG_n, net_U8052_Pad11, WL03_n, WG3G_n, GND, WL05_n, WG4G_n, net_U8052_Pad12, L2GDG_n, __L03_n, net_U8022_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U8065(__G04_n, GEM04, RL04_n, WL04, WL04, WL04_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U8066(SUMA01_n, net_U8003_Pad1, XUY01_n, CI01_n, GND, , GND, , net_U8021_Pad1, XUY02_n, __A08_1___CI_INTERNAL, WHOMP, SUMA02_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U8067(SUMA03_n, net_U8037_Pad1, __XUY03_n, __CI03_n, GND, , GND, , net_U8044_Pad1, __XUY04_n, __A08_2___CI_INTERNAL, WHOMP, __A08_2___SUMA2, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U8068(RL01_n, MWL01, RL02_n, MWL02, RL03_n, MWL03, GND, MWL04, RL04_n, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
endmodule |
module four_bit_2(SIM_RST, SIM_CLK, p4VSW, GND, A2XG_n, CAG, CBG, CGG, CLG1G, CLXC, CQG, CUG, CZG, L2GDG_n, RAG_n, RCG_n, RGG_n, RLG_n, RQG_n, RZG_n, WAG_n, WALSG_n, WBG_n, WLG_n, WQG_n, WZG_n, CI05_n, CO06, MONEX, XUY09_n, XUY10_n, CH05, CH06, CH07, CH08, G05ED, G06ED, G07ED, L04_n, G2LSG_n, G09_n, G10_n, G11_n, MDT05, MDT06, MDT07, MDT08, SA05, SA06, SA07, SA08, RBLG_n, RULOG_n, WL09_n, WL10_n, WG1G_n, WG3G_n, WG4G_n, WYDG_n, WYLOG_n, R1C, WL04_n, WHOMP, CI09_n, CO10, G05, G05_n, G06, G06_n, G07, G07_n, G08, L08_n, RL05_n, RL06_n, XUY05_n, XUY06_n, WL05, WL05_n, WL06, WL06_n, WL07, WL07_n, WL08, WL08_n, GEM05, GEM06, GEM07, GEM08, MWL05, MWL06, MWL07, MWL08);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire A2XG_n;
input wire CAG;
input wire CBG;
input wire CGG;
input wire CH05;
input wire CH06;
input wire CH07;
input wire CH08;
input wire CI05_n;
output wire CI09_n;
input wire CLG1G;
input wire CLXC;
input wire CO06;
output wire CO10; //FPGA#wand
input wire CQG;
input wire CUG;
input wire CZG;
output wire G05;
input wire G05ED;
inout wire G05_n; //FPGA#wand
output wire G06;
input wire G06ED;
inout wire G06_n; //FPGA#wand
output wire G07;
input wire G07ED;
inout wire G07_n; //FPGA#wand
output wire G08;
input wire G09_n;
input wire G10_n;
input wire G11_n;
input wire G2LSG_n;
output wire GEM05;
output wire GEM06;
output wire GEM07;
output wire GEM08;
input wire L04_n;
inout wire L08_n; //FPGA#wand
input wire L2GDG_n;
input wire MDT05;
input wire MDT06;
input wire MDT07;
input wire MDT08;
input wire MONEX;
output wire MWL05; //FPGA#wand
output wire MWL06; //FPGA#wand
output wire MWL07; //FPGA#wand
output wire MWL08; //FPGA#wand
input wire R1C;
input wire RAG_n;
input wire RBLG_n;
input wire RCG_n;
input wire RGG_n;
inout wire RL05_n; //FPGA#wand
inout wire RL06_n; //FPGA#wand
input wire RLG_n;
input wire RQG_n;
input wire RULOG_n;
input wire RZG_n;
input wire SA05;
input wire SA06;
input wire SA07;
input wire SA08;
input wire WAG_n;
input wire WALSG_n;
input wire WBG_n;
input wire WG1G_n;
input wire WG3G_n;
input wire WG4G_n;
input wire WHOMP;
input wire WL04_n;
output wire WL05;
output wire WL05_n;
output wire WL06;
output wire WL06_n;
output wire WL07;
output wire WL07_n;
output wire WL08;
output wire WL08_n;
input wire WL09_n;
input wire WL10_n;
input wire WLG_n;
input wire WQG_n;
input wire WYDG_n;
input wire WYLOG_n;
input wire WZG_n;
output wire XUY05_n;
output wire XUY06_n;
input wire XUY09_n;
input wire XUY10_n;
wire __A09_1__X1;
wire __A09_1__X1_n;
wire __A09_1__X2;
wire __A09_1__X2_n;
wire __A09_1__Y1;
wire __A09_1__Y1_n;
wire __A09_1__Y2;
wire __A09_1__Y2_n;
wire __A09_1___A1_n;
wire __A09_1___A2_n;
wire __A09_1___B1_n;
wire __A09_1___B2_n;
wire __A09_1___CI_INTERNAL;
wire __A09_1___Q1_n;
wire __A09_1___Q2_n;
wire __A09_1___RL_OUT_1;
wire __A09_1___RL_OUT_2;
wire __A09_1___SUMA1;
wire __A09_1___SUMA2;
wire __A09_1___SUMB1;
wire __A09_1___SUMB2;
wire __A09_1___Z1_n; //FPGA#wand
wire __A09_1___Z2_n; //FPGA#wand
wire __A09_2__X1;
wire __A09_2__X1_n;
wire __A09_2__X2;
wire __A09_2__X2_n;
wire __A09_2__Y1;
wire __A09_2__Y1_n;
wire __A09_2__Y2;
wire __A09_2__Y2_n;
wire __A09_2___A1_n;
wire __A09_2___A2_n;
wire __A09_2___B1_n;
wire __A09_2___B2_n;
wire __A09_2___CI_INTERNAL;
wire __A09_2___Q1_n;
wire __A09_2___Q2_n;
wire __A09_2___RL1_n; //FPGA#wand
wire __A09_2___RL2_n; //FPGA#wand
wire __A09_2___RL_OUT_1;
wire __A09_2___RL_OUT_2;
wire __A09_2___SUMA1;
wire __A09_2___SUMA2;
wire __A09_2___SUMB1;
wire __A09_2___SUMB2;
wire __A09_2___Z1_n; //FPGA#wand
wire __A09_2___Z2_n; //FPGA#wand
wire __CI07_n;
wire __CO08; //FPGA#wand
wire __G08_n; //FPGA#wand
wire __L05_n; //FPGA#wand
wire __L06_n; //FPGA#wand
wire __L07_n; //FPGA#wand
wire __XUY07_n;
wire __XUY08_n;
wire net_U9001_Pad1;
wire net_U9001_Pad10;
wire net_U9001_Pad4;
wire net_U9003_Pad1;
wire net_U9003_Pad10;
wire net_U9004_Pad1;
wire net_U9004_Pad12;
wire net_U9004_Pad13;
wire net_U9004_Pad2;
wire net_U9004_Pad6;
wire net_U9004_Pad8;
wire net_U9005_Pad12;
wire net_U9005_Pad2;
wire net_U9006_Pad10;
wire net_U9006_Pad13;
wire net_U9006_Pad4;
wire net_U9007_Pad11;
wire net_U9007_Pad13;
wire net_U9007_Pad3;
wire net_U9007_Pad5;
wire net_U9007_Pad9;
wire net_U9008_Pad1;
wire net_U9008_Pad10;
wire net_U9008_Pad13;
wire net_U9008_Pad4;
wire net_U9009_Pad1;
wire net_U9009_Pad13;
wire net_U9009_Pad4;
wire net_U9010_Pad1;
wire net_U9010_Pad13;
wire net_U9010_Pad4;
wire net_U9011_Pad10;
wire net_U9011_Pad11;
wire net_U9011_Pad13;
wire net_U9011_Pad8;
wire net_U9011_Pad9;
wire net_U9012_Pad13;
wire net_U9012_Pad4;
wire net_U9013_Pad1;
wire net_U9013_Pad11;
wire net_U9013_Pad13;
wire net_U9013_Pad5;
wire net_U9013_Pad9;
wire net_U9014_Pad10;
wire net_U9014_Pad13;
wire net_U9016_Pad1;
wire net_U9016_Pad4;
wire net_U9018_Pad11;
wire net_U9018_Pad12;
wire net_U9018_Pad13;
wire net_U9019_Pad1;
wire net_U9019_Pad10;
wire net_U9019_Pad4;
wire net_U9021_Pad1;
wire net_U9021_Pad13;
wire net_U9022_Pad1;
wire net_U9022_Pad12;
wire net_U9022_Pad8;
wire net_U9023_Pad10;
wire net_U9023_Pad13;
wire net_U9023_Pad4;
wire net_U9024_Pad10;
wire net_U9024_Pad11;
wire net_U9024_Pad4;
wire net_U9024_Pad9;
wire net_U9026_Pad4;
wire net_U9026_Pad5;
wire net_U9026_Pad6;
wire net_U9026_Pad8;
wire net_U9027_Pad1;
wire net_U9027_Pad10;
wire net_U9028_Pad13;
wire net_U9028_Pad3;
wire net_U9028_Pad9;
wire net_U9029_Pad1;
wire net_U9029_Pad10;
wire net_U9030_Pad1;
wire net_U9030_Pad10;
wire net_U9030_Pad13;
wire net_U9031_Pad13;
wire net_U9031_Pad2;
wire net_U9031_Pad3;
wire net_U9031_Pad4;
wire net_U9031_Pad8;
wire net_U9035_Pad1;
wire net_U9035_Pad10;
wire net_U9035_Pad4;
wire net_U9037_Pad1;
wire net_U9037_Pad10;
wire net_U9038_Pad1;
wire net_U9038_Pad12;
wire net_U9038_Pad2;
wire net_U9038_Pad6;
wire net_U9038_Pad8;
wire net_U9039_Pad12;
wire net_U9039_Pad2;
wire net_U9040_Pad10;
wire net_U9040_Pad13;
wire net_U9040_Pad4;
wire net_U9041_Pad11;
wire net_U9041_Pad13;
wire net_U9041_Pad3;
wire net_U9041_Pad5;
wire net_U9041_Pad9;
wire net_U9042_Pad10;
wire net_U9042_Pad11;
wire net_U9042_Pad4;
wire net_U9042_Pad9;
wire net_U9044_Pad1;
wire net_U9044_Pad6;
wire net_U9045_Pad13;
wire net_U9045_Pad4;
wire net_U9046_Pad1;
wire net_U9046_Pad13;
wire net_U9046_Pad4;
wire net_U9047_Pad1;
wire net_U9047_Pad13;
wire net_U9047_Pad4;
wire net_U9048_Pad1;
wire net_U9048_Pad10;
wire net_U9048_Pad13;
wire net_U9048_Pad4;
wire net_U9049_Pad11;
wire net_U9049_Pad8;
wire net_U9050_Pad11;
wire net_U9050_Pad13;
wire net_U9050_Pad5;
wire net_U9052_Pad11;
wire net_U9052_Pad12;
wire net_U9052_Pad13;
wire net_U9053_Pad1;
wire net_U9053_Pad10;
wire net_U9053_Pad4;
wire net_U9055_Pad13;
wire net_U9056_Pad10;
wire net_U9056_Pad13;
wire net_U9056_Pad4;
wire net_U9057_Pad10;
wire net_U9057_Pad11;
wire net_U9057_Pad4;
wire net_U9057_Pad9;
wire net_U9059_Pad4;
wire net_U9059_Pad5;
wire net_U9059_Pad6;
wire net_U9059_Pad8;
wire net_U9060_Pad1;
wire net_U9060_Pad10;
wire net_U9061_Pad3;
wire net_U9062_Pad1;
wire net_U9062_Pad10;
wire net_U9063_Pad1;
wire net_U9063_Pad10;
pullup R9001(__CO08);
pullup R9002(RL05_n);
pullup R9003(__L05_n);
pullup R9005(__A09_1___Z1_n);
pullup R9006(G05_n);
pullup R9007(RL06_n);
pullup R9008(__L06_n);
pullup R9009(__A09_1___Z2_n);
pullup R9010(G06_n);
pullup R9011(CO10);
pullup R9012(__A09_2___RL1_n);
pullup R9013(__L07_n);
pullup R9015(__A09_2___Z1_n);
pullup R9016(G07_n);
pullup R9017(__A09_2___RL2_n);
pullup R9018(L08_n);
pullup R9019(__A09_2___Z2_n);
pullup R9020(__G08_n);
U74HC02 U9001(net_U9001_Pad1, A2XG_n, __A09_1___A1_n, net_U9001_Pad4, WYLOG_n, WL05_n, GND, WL04_n, WYDG_n, net_U9001_Pad10, __A09_1__Y1_n, CUG, __A09_1__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9002(MONEX, net_U9001_Pad1, __A09_1__X1_n, CLXC, CUG, __A09_1__X1, GND, __A09_1__Y1_n, net_U9001_Pad4, net_U9001_Pad10, __A09_1__Y1, __A09_1__X1_n, __A09_1__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9003(net_U9003_Pad1, __A09_1__X1_n, __A09_1__Y1_n, XUY05_n, __A09_1__X1, __A09_1__Y1, GND, net_U9003_Pad1, XUY05_n, net_U9003_Pad10, net_U9003_Pad1, __A09_1___SUMA1, __A09_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9004(net_U9004_Pad1, net_U9004_Pad2, __A09_1___SUMA1, __A09_1___SUMB1, RULOG_n, net_U9004_Pad6, GND, net_U9004_Pad8, __XUY07_n, XUY05_n, CI05_n, net_U9004_Pad12, net_U9004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U9005(CI05_n, net_U9005_Pad2, G05_n, GEM05, RL05_n, WL05, GND, WL05_n, WL05, , , net_U9005_Pad12, __A09_1___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9006(__A09_1___SUMB1, net_U9003_Pad10, net_U9005_Pad2, net_U9006_Pad4, WAG_n, WL05_n, GND, WL07_n, WALSG_n, net_U9006_Pad10, __A09_1___A1_n, CAG, net_U9006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9007(net_U9004_Pad8, __CO08, net_U9007_Pad3, RL05_n, net_U9007_Pad5, __L05_n, GND, __A09_1___Z1_n, net_U9007_Pad9, RL05_n, net_U9007_Pad11, RL05_n, net_U9007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U9008(net_U9008_Pad1, RAG_n, __A09_1___A1_n, net_U9008_Pad4, WLG_n, WL05_n, GND, __G08_n, G2LSG_n, net_U9008_Pad10, __L05_n, CLG1G, net_U9008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9009(net_U9009_Pad1, WG1G_n, WL08_n, net_U9009_Pad4, WQG_n, WL05_n, GND, net_U9009_Pad4, net_U9009_Pad13, __A09_1___Q1_n, __A09_1___Q1_n, CQG, net_U9009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9010(net_U9010_Pad1, RQG_n, __A09_1___Q1_n, net_U9010_Pad4, WZG_n, WL05_n, GND, net_U9010_Pad4, net_U9010_Pad13, net_U9007_Pad9, __A09_1___Z1_n, CZG, net_U9010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9011(__A09_1___RL_OUT_1, net_U9010_Pad1, MDT05, R1C, GND, net_U9007_Pad13, GND, net_U9011_Pad8, net_U9011_Pad9, net_U9011_Pad10, net_U9011_Pad11, net_U9007_Pad11, net_U9011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9012(net_U9011_Pad13, RZG_n, __A09_1___Z1_n, net_U9012_Pad4, WBG_n, WL05_n, GND, net_U9012_Pad4, net_U9012_Pad13, __A09_1___B1_n, __A09_1___B1_n, CBG, net_U9012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9013(net_U9013_Pad1, __CO08, net_U9011_Pad8, RL05_n, net_U9013_Pad5, G05_n, GND, G05_n, net_U9013_Pad9, RL06_n, net_U9013_Pad11, __L06_n, net_U9013_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U9014(net_U9011_Pad9, RBLG_n, __A09_1___B1_n, net_U9011_Pad10, net_U9012_Pad13, RCG_n, GND, WL04_n, WG3G_n, net_U9014_Pad10, WL06_n, WG4G_n, net_U9014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9015(net_U9006_Pad4, net_U9006_Pad10, net_U9004_Pad6, net_U9008_Pad1, CH05, net_U9007_Pad3, GND, net_U9007_Pad5, net_U9008_Pad4, net_U9008_Pad10, net_U9008_Pad13, __A09_1___A1_n, net_U9006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9016(net_U9016_Pad1, L2GDG_n, L04_n, net_U9016_Pad4, WG1G_n, WL05_n, GND, G05_n, CGG, G05, RGG_n, G05_n, net_U9011_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U9017(net_U9016_Pad1, net_U9016_Pad4, GND, __XUY08_n, XUY06_n, net_U9013_Pad1, GND, __A09_1___RL_OUT_1, RLG_n, __L05_n, GND, net_U9013_Pad9, G05, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U9018(net_U9013_Pad5, G05ED, SA05, net_U9014_Pad10, net_U9014_Pad13, , GND, , G06ED, SA06, net_U9018_Pad11, net_U9018_Pad12, net_U9018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9019(net_U9019_Pad1, A2XG_n, __A09_1___A2_n, net_U9019_Pad4, WYLOG_n, WL06_n, GND, WL05_n, WYDG_n, net_U9019_Pad10, __A09_1__Y2_n, CUG, __A09_1__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9020(MONEX, net_U9019_Pad1, __A09_1__X2_n, CLXC, CUG, __A09_1__X2, GND, __A09_1__Y2_n, net_U9019_Pad4, net_U9019_Pad10, __A09_1__Y2, __A09_1__X2_n, __A09_1__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9021(net_U9021_Pad1, __A09_1__X2_n, __A09_1__Y2_n, XUY06_n, __A09_1__X2, __A09_1__Y2, GND, __G08_n, CGG, G08, net_U9021_Pad1, XUY06_n, net_U9021_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U9022(net_U9022_Pad1, net_U9009_Pad1, net_U9021_Pad1, __A09_1___SUMA2, CO06, __CI07_n, GND, net_U9022_Pad8, __A09_1___SUMA2, __A09_1___SUMB2, RULOG_n, net_U9022_Pad12, G08, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9023(__A09_1___SUMB2, net_U9021_Pad13, net_U9005_Pad12, net_U9023_Pad4, WAG_n, WL06_n, GND, WL08_n, WALSG_n, net_U9023_Pad10, __A09_1___A2_n, CAG, net_U9023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9024(net_U9023_Pad4, net_U9023_Pad10, net_U9022_Pad8, net_U9024_Pad4, CH06, net_U9013_Pad11, GND, net_U9013_Pad13, net_U9024_Pad9, net_U9024_Pad10, net_U9024_Pad11, __A09_1___A2_n, net_U9023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9025(net_U9024_Pad4, RAG_n, __A09_1___A2_n, net_U9024_Pad9, WLG_n, WL06_n, GND, G09_n, G2LSG_n, net_U9024_Pad10, __L06_n, CLG1G, net_U9024_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9026(RLG_n, __L06_n, __A09_1___RL_OUT_2, net_U9026_Pad4, net_U9026_Pad5, net_U9026_Pad6, GND, net_U9026_Pad8, MDT06, R1C, GND, __A09_1___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9027(net_U9027_Pad1, WQG_n, WL06_n, __A09_1___Q2_n, net_U9027_Pad1, net_U9027_Pad10, GND, __A09_1___Q2_n, CQG, net_U9027_Pad10, RQG_n, __A09_1___Q2_n, net_U9026_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9028(net_U9026_Pad6, RL06_n, net_U9028_Pad3, __A09_1___Z2_n, net_U9026_Pad8, RL06_n, GND, RL06_n, net_U9028_Pad9, G06_n, net_U9018_Pad13, G06_n, net_U9028_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9029(net_U9029_Pad1, WZG_n, WL06_n, net_U9028_Pad3, net_U9029_Pad1, net_U9029_Pad10, GND, __A09_1___Z2_n, CZG, net_U9029_Pad10, RZG_n, __A09_1___Z2_n, net_U9026_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9030(net_U9030_Pad1, WBG_n, WL06_n, __A09_1___B2_n, net_U9030_Pad1, net_U9030_Pad10, GND, __A09_1___B2_n, CBG, net_U9030_Pad10, RBLG_n, __A09_1___B2_n, net_U9030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U9031(net_U9030_Pad13, net_U9031_Pad2, net_U9031_Pad3, net_U9031_Pad4, G06, net_U9028_Pad13, GND, net_U9031_Pad8, GND, XUY10_n, __XUY08_n, net_U9028_Pad9, net_U9031_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9032(net_U9031_Pad2, net_U9030_Pad10, RCG_n, net_U9018_Pad11, WL05_n, WG3G_n, GND, WL07_n, WG4G_n, net_U9018_Pad12, L2GDG_n, __L05_n, net_U9031_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9033(net_U9031_Pad4, WG1G_n, WL06_n, G06, G06_n, CGG, GND, RGG_n, G06_n, net_U9031_Pad13, RGG_n, __G08_n, net_U9004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U9034(G06_n, GEM06, RL06_n, WL06, WL06, WL06_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9035(net_U9035_Pad1, A2XG_n, __A09_2___A1_n, net_U9035_Pad4, WYLOG_n, WL07_n, GND, WL06_n, WYDG_n, net_U9035_Pad10, __A09_2__Y1_n, CUG, __A09_2__Y1, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9036(MONEX, net_U9035_Pad1, __A09_2__X1_n, CLXC, CUG, __A09_2__X1, GND, __A09_2__Y1_n, net_U9035_Pad4, net_U9035_Pad10, __A09_2__Y1, __A09_2__X1_n, __A09_2__X1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9037(net_U9037_Pad1, __A09_2__X1_n, __A09_2__Y1_n, __XUY07_n, __A09_2__X1, __A09_2__Y1, GND, net_U9037_Pad1, __XUY07_n, net_U9037_Pad10, net_U9037_Pad1, __A09_2___SUMA1, __A09_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U9038(net_U9038_Pad1, net_U9038_Pad2, __A09_2___SUMA1, __A09_2___SUMB1, RULOG_n, net_U9038_Pad6, GND, net_U9038_Pad8, XUY09_n, __XUY07_n, __CI07_n, net_U9038_Pad12, G07, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U9039(__CI07_n, net_U9039_Pad2, G07_n, GEM07, __A09_2___RL1_n, WL07, GND, WL07_n, WL07, , , net_U9039_Pad12, __A09_2___CI_INTERNAL, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9040(__A09_2___SUMB1, net_U9037_Pad10, net_U9039_Pad2, net_U9040_Pad4, WAG_n, WL07_n, GND, WL09_n, WALSG_n, net_U9040_Pad10, __A09_2___A1_n, CAG, net_U9040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9041(net_U9038_Pad8, CO10, net_U9041_Pad3, __A09_2___RL1_n, net_U9041_Pad5, __L07_n, GND, __A09_2___Z1_n, net_U9041_Pad9, __A09_2___RL1_n, net_U9041_Pad11, __A09_2___RL1_n, net_U9041_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 #(1'b1, 1'b0, 1'b1) U9042(net_U9040_Pad4, net_U9040_Pad10, net_U9038_Pad6, net_U9042_Pad4, CH07, net_U9041_Pad3, GND, net_U9041_Pad5, net_U9042_Pad9, net_U9042_Pad10, net_U9042_Pad11, __A09_2___A1_n, net_U9040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9043(net_U9042_Pad4, RAG_n, __A09_2___A1_n, net_U9042_Pad9, WLG_n, WL07_n, GND, G10_n, G2LSG_n, net_U9042_Pad10, __L07_n, CLG1G, net_U9042_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9044(net_U9044_Pad1, __A09_2___SUMA2, __A09_2___SUMA2, __A09_2___SUMB2, RULOG_n, net_U9044_Pad6, GND, __A09_2___RL_OUT_1, RLG_n, __L07_n, GND, CI09_n, __CO08, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9045( , , , net_U9045_Pad4, WQG_n, WL07_n, GND, net_U9045_Pad4, net_U9045_Pad13, __A09_2___Q1_n, __A09_2___Q1_n, CQG, net_U9045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9046(net_U9046_Pad1, RQG_n, __A09_2___Q1_n, net_U9046_Pad4, WZG_n, WL07_n, GND, net_U9046_Pad4, net_U9046_Pad13, net_U9041_Pad9, __A09_2___Z1_n, CZG, net_U9046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U9047(net_U9047_Pad1, RZG_n, __A09_2___Z1_n, net_U9047_Pad4, WBG_n, WL07_n, GND, net_U9047_Pad4, net_U9047_Pad13, __A09_2___B1_n, __A09_2___B1_n, CBG, net_U9047_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9048(net_U9048_Pad1, RBLG_n, __A09_2___B1_n, net_U9048_Pad4, net_U9047_Pad13, RCG_n, GND, WL06_n, WG3G_n, net_U9048_Pad10, WL08_n, WG4G_n, net_U9048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9049(__A09_2___RL_OUT_1, net_U9046_Pad1, MDT07, R1C, GND, net_U9041_Pad13, GND, net_U9049_Pad8, net_U9048_Pad1, net_U9048_Pad4, net_U9049_Pad11, net_U9041_Pad11, net_U9047_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9050(net_U9031_Pad8, CO10, net_U9049_Pad8, __A09_2___RL1_n, net_U9050_Pad5, G07_n, GND, G07_n, net_U9038_Pad12, __A09_2___RL2_n, net_U9050_Pad11, L08_n, net_U9050_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 U9051(net_U9038_Pad1, L2GDG_n, __L06_n, net_U9038_Pad2, WG1G_n, WL07_n, GND, G07_n, CGG, G07, RGG_n, G07_n, net_U9049_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U9052(net_U9050_Pad5, G07ED, SA07, net_U9048_Pad10, net_U9048_Pad13, , GND, , GND, SA08, net_U9052_Pad11, net_U9052_Pad12, net_U9052_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9053(net_U9053_Pad1, A2XG_n, __A09_2___A2_n, net_U9053_Pad4, WYLOG_n, WL08_n, GND, WL07_n, WYDG_n, net_U9053_Pad10, __A09_2__Y2_n, CUG, __A09_2__Y2, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9054(MONEX, net_U9053_Pad1, __A09_2__X2_n, CLXC, CUG, __A09_2__X2, GND, __A09_2__Y2_n, net_U9053_Pad4, net_U9053_Pad10, __A09_2__Y2, __A09_2__X2_n, __A09_2__X2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9055(net_U9044_Pad1, __A09_2__X2_n, __A09_2__Y2_n, __XUY08_n, __A09_2__X2, __A09_2__Y2, GND, , , , net_U9044_Pad1, __XUY08_n, net_U9055_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9056(__A09_2___SUMB2, net_U9055_Pad13, net_U9039_Pad12, net_U9056_Pad4, WAG_n, WL08_n, GND, WL10_n, WALSG_n, net_U9056_Pad10, __A09_2___A2_n, CAG, net_U9056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b1) U9057(net_U9056_Pad4, net_U9056_Pad10, net_U9044_Pad6, net_U9057_Pad4, CH08, net_U9050_Pad11, GND, net_U9050_Pad13, net_U9057_Pad9, net_U9057_Pad10, net_U9057_Pad11, __A09_2___A2_n, net_U9056_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9058(net_U9057_Pad4, RAG_n, __A09_2___A2_n, net_U9057_Pad9, WLG_n, WL08_n, GND, G11_n, G2LSG_n, net_U9057_Pad10, L08_n, CLG1G, net_U9057_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U9059(RLG_n, L08_n, __A09_2___RL_OUT_2, net_U9059_Pad4, net_U9059_Pad5, net_U9059_Pad6, GND, net_U9059_Pad8, MDT08, R1C, GND, __A09_2___RL_OUT_2, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9060(net_U9060_Pad1, WQG_n, WL08_n, __A09_2___Q2_n, net_U9060_Pad1, net_U9060_Pad10, GND, __A09_2___Q2_n, CQG, net_U9060_Pad10, RQG_n, __A09_2___Q2_n, net_U9059_Pad4, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U9061(net_U9059_Pad6, __A09_2___RL2_n, net_U9061_Pad3, __A09_2___Z2_n, net_U9059_Pad8, __A09_2___RL2_n, GND, __A09_2___RL2_n, net_U9004_Pad12, __G08_n, net_U9052_Pad13, __G08_n, net_U9022_Pad12, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9062(net_U9062_Pad1, WZG_n, WL08_n, net_U9061_Pad3, net_U9062_Pad1, net_U9062_Pad10, GND, __A09_2___Z2_n, CZG, net_U9062_Pad10, RZG_n, __A09_2___Z2_n, net_U9059_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U9063(net_U9063_Pad1, WBG_n, WL08_n, __A09_2___B2_n, net_U9063_Pad1, net_U9063_Pad10, GND, __A09_2___B2_n, CBG, net_U9063_Pad10, RBLG_n, __A09_2___B2_n, net_U9004_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U9064(net_U9004_Pad2, net_U9063_Pad10, RCG_n, net_U9052_Pad11, WL07_n, WG3G_n, GND, WL09_n, WG4G_n, net_U9052_Pad12, L2GDG_n, __L07_n, net_U9022_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U9065(__G08_n, GEM08, __A09_2___RL2_n, WL08, WL08, WL08_n, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U9066(__A09_1___SUMA1, net_U9003_Pad1, XUY05_n, CI05_n, GND, , GND, , net_U9021_Pad1, XUY06_n, __A09_1___CI_INTERNAL, GND, __A09_1___SUMA2, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U9067(__A09_2___SUMA1, net_U9037_Pad1, __XUY07_n, __CI07_n, WHOMP, , GND, , net_U9044_Pad1, __XUY08_n, __A09_2___CI_INTERNAL, GND, __A09_2___SUMA2, p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U9068(RL05_n, MWL05, RL06_n, MWL06, __A09_2___RL1_n, MWL07, GND, MWL08, __A09_2___RL2_n, , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8
endmodule |
module parity_s_register(SIM_RST, SIM_CLK, p4VSW, GND, GOJAM, PHS4_n, T02_n, T07_n, T12A, TPARG_n, TSUDO_n, FUTEXT, CGG, CSG, WEDOPG_n, WSG_n, G01, G02, G03, G04, G05, G06, G07, G08, G09, G10, G11, G12, G13, G14, G15, G16, WL01_n, WL02_n, WL03_n, WL04_n, WL05_n, WL06_n, WL07_n, WL08_n, WL09_n, WL10_n, WL11_n, WL12_n, WL13_n, WL14_n, SUMA16_n, SUMB16_n, RAD, SAP, SCAD, OCTAD2, n8XP5, MONPAR, XB0_n, XB1_n, XB2_n, XB3_n, CYL_n, CYR_n, EDOP_n, GINH, SR_n, EXTPLS, INHPLS, RELPLS, G01ED, G02ED, G03ED, G04ED, G05ED, G06ED, G07ED, GEQZRO_n, RADRG, RADRZ, S01, S01_n, S02, S02_n, S03, S03_n, S04, S04_n, S05, S05_n, S06, S06_n, S07, S07_n, S08, S08_n, S09, S09_n, S10, S10_n, S11, S11_n, S12, S12_n, GEMP, G16SW_n, PC15_n, PALE, MGP_n, MSP, MPAL_n);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire CGG;
input wire CSG;
output wire CYL_n;
output wire CYR_n;
output wire EDOP_n;
output wire EXTPLS;
input wire FUTEXT;
input wire G01;
output wire G01ED;
input wire G02;
output wire G02ED;
input wire G03;
output wire G03ED;
input wire G04;
output wire G04ED;
input wire G05;
output wire G05ED;
input wire G06;
output wire G06ED;
input wire G07;
output wire G07ED;
input wire G08;
input wire G09;
input wire G10;
input wire G11;
input wire G12;
input wire G13;
input wire G14;
input wire G15;
input wire G16;
output wire G16SW_n;
output wire GEMP;
output wire GEQZRO_n;
output wire GINH;
input wire GOJAM;
inout wire INHPLS; //FPGA#wand
output wire MGP_n;
input wire MONPAR;
output wire MPAL_n; //FPGA#wand
output wire MSP;
input wire OCTAD2;
inout wire PALE; //FPGA#wand
output wire PC15_n;
input wire PHS4_n;
input wire RAD;
output wire RADRG;
output wire RADRZ;
inout wire RELPLS; //FPGA#wand
output wire S01;
output wire S01_n;
output wire S02;
output wire S02_n;
output wire S03;
output wire S03_n;
output wire S04;
output wire S04_n;
output wire S05;
output wire S05_n;
output wire S06;
output wire S06_n;
output wire S07;
output wire S07_n;
output wire S08;
output wire S08_n;
output wire S09;
output wire S09_n;
output wire S10;
output wire S10_n;
output wire S11;
output wire S11_n;
output wire S12;
output wire S12_n;
input wire SAP;
input wire SCAD;
output wire SR_n;
input wire SUMA16_n;
input wire SUMB16_n;
input wire T02_n;
input wire T07_n;
input wire T12A;
input wire TPARG_n;
input wire TSUDO_n;
input wire WEDOPG_n;
input wire WL01_n;
input wire WL02_n;
input wire WL03_n;
input wire WL04_n;
input wire WL05_n;
input wire WL06_n;
input wire WL07_n;
input wire WL08_n;
input wire WL09_n;
input wire WL10_n;
input wire WL11_n;
input wire WL12_n;
input wire WL13_n;
input wire WL14_n;
input wire WSG_n;
input wire XB0_n;
input wire XB1_n;
input wire XB2_n;
input wire XB3_n;
wire __A12_1__G01A_n;
wire __A12_1__G16A_n;
wire __A12_1__GNZRO; //FPGA#wand
wire __A12_1__PA03;
wire __A12_1__PA03_n;
wire __A12_1__PA06;
wire __A12_1__PA06_n;
wire __A12_1__PA09;
wire __A12_1__PA09_n;
wire __A12_1__PA12;
wire __A12_1__PA12_n;
wire __A12_1__PA15;
wire __A12_1__PA15_n;
wire __A12_1__PB09;
wire __A12_1__PB09_n;
wire __A12_1__PB15;
wire __A12_1__PB15_n;
wire __A12_1__PC15;
wire __A12_1__T7PHS4;
wire __A12_1__T7PHS4_n;
wire __A12_1__uG02_n;
wire __A12_1__uG03_n;
wire __A12_2__G01A;
input wire n8XP5;
wire net_U12001_Pad10;
wire net_U12001_Pad12;
wire net_U12002_Pad12;
wire net_U12002_Pad6;
wire net_U12002_Pad8;
wire net_U12003_Pad11;
wire net_U12003_Pad12;
wire net_U12003_Pad6;
wire net_U12003_Pad8;
wire net_U12004_Pad11;
wire net_U12004_Pad12;
wire net_U12005_Pad10;
wire net_U12005_Pad12;
wire net_U12005_Pad4;
wire net_U12005_Pad8;
wire net_U12006_Pad8;
wire net_U12007_Pad12;
wire net_U12007_Pad6;
wire net_U12007_Pad8;
wire net_U12008_Pad10;
wire net_U12008_Pad11;
wire net_U12008_Pad12;
wire net_U12008_Pad9;
wire net_U12009_Pad10;
wire net_U12009_Pad12;
wire net_U12009_Pad2;
wire net_U12009_Pad6;
wire net_U12009_Pad8;
wire net_U12011_Pad10;
wire net_U12011_Pad6;
wire net_U12011_Pad8;
wire net_U12012_Pad10;
wire net_U12012_Pad4;
wire net_U12013_Pad12;
wire net_U12013_Pad6;
wire net_U12013_Pad8;
wire net_U12014_Pad12;
wire net_U12014_Pad13;
wire net_U12015_Pad1;
wire net_U12015_Pad10;
wire net_U12015_Pad13;
wire net_U12015_Pad4;
wire net_U12016_Pad11;
wire net_U12016_Pad5;
wire net_U12017_Pad10;
wire net_U12017_Pad2;
wire net_U12017_Pad4;
wire net_U12017_Pad6;
wire net_U12017_Pad9;
wire net_U12019_Pad10;
wire net_U12019_Pad11;
wire net_U12019_Pad12;
wire net_U12019_Pad9;
wire net_U12020_Pad13;
wire net_U12022_Pad10;
wire net_U12022_Pad3;
wire net_U12022_Pad6;
wire net_U12022_Pad8;
wire net_U12023_Pad1;
wire net_U12023_Pad10;
wire net_U12023_Pad13;
wire net_U12025_Pad13;
wire net_U12026_Pad11;
wire net_U12026_Pad12;
wire net_U12026_Pad8;
wire net_U12028_Pad10;
wire net_U12028_Pad13;
wire net_U12028_Pad4;
wire net_U12029_Pad11;
wire net_U12029_Pad13;
wire net_U12029_Pad5;
wire net_U12029_Pad9;
wire net_U12030_Pad4;
wire net_U12031_Pad4;
wire net_U12032_Pad10;
wire net_U12032_Pad13;
wire net_U12032_Pad4;
wire net_U12033_Pad11;
wire net_U12033_Pad13;
wire net_U12033_Pad5;
wire net_U12033_Pad9;
wire net_U12034_Pad10;
wire net_U12034_Pad4;
wire net_U12035_Pad10;
wire net_U12036_Pad10;
wire net_U12036_Pad13;
wire net_U12036_Pad4;
wire net_U12037_Pad11;
wire net_U12037_Pad13;
wire net_U12037_Pad5;
wire net_U12037_Pad9;
wire net_U12038_Pad1;
wire net_U12038_Pad13;
wire net_U12039_Pad10;
wire net_U12039_Pad12;
wire net_U12039_Pad13;
wire net_U12040_Pad10;
wire net_U12040_Pad13;
wire net_U12040_Pad4;
wire net_U12041_Pad11;
wire net_U12041_Pad13;
wire net_U12042_Pad1;
wire net_U12043_Pad9;
wire net_U12044_Pad10;
wire net_U12044_Pad11;
wire net_U12044_Pad9;
wire net_U12045_Pad11;
wire net_U12046_Pad6;
wire net_U12046_Pad8;
wire net_U12048_Pad6;
wire net_U12049_Pad1;
pullup R12001(__A12_1__GNZRO);
pullup R12002(RELPLS);
pullup R12003(INHPLS);
pullup R12004(PALE);
U74HC04 U12001(G01, __A12_1__G01A_n, G02, __A12_1__uG02_n, G03, __A12_1__uG03_n, GND, __A12_1__PA03_n, __A12_1__PA03, net_U12001_Pad10, G04, net_U12001_Pad12, G05, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12002(G01, G02, G01, __A12_1__uG02_n, __A12_1__uG03_n, net_U12002_Pad6, GND, net_U12002_Pad8, __A12_1__G01A_n, G02, __A12_1__uG03_n, net_U12002_Pad12, G03, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12003(__A12_1__G01A_n, __A12_1__uG02_n, G04, G05, G06, net_U12003_Pad6, GND, net_U12003_Pad8, G04, net_U12001_Pad12, net_U12003_Pad11, net_U12003_Pad12, G03, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U12004(__A12_1__PA03, net_U12002_Pad12, net_U12002_Pad6, net_U12002_Pad8, net_U12003_Pad12, , GND, , net_U12003_Pad6, net_U12003_Pad8, net_U12004_Pad11, net_U12004_Pad12, __A12_1__PA06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12005(G06, net_U12003_Pad11, net_U12003_Pad6, net_U12005_Pad4, __A12_1__PA06, __A12_1__PA06_n, GND, net_U12005_Pad8, G07, net_U12005_Pad10, G08, net_U12005_Pad12, G09, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12006(net_U12001_Pad10, G05, net_U12001_Pad10, net_U12001_Pad12, G06, net_U12004_Pad12, GND, net_U12006_Pad8, G07, G08, G09, net_U12004_Pad11, net_U12003_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12007(G07, net_U12005_Pad10, net_U12005_Pad8, G08, net_U12005_Pad12, net_U12007_Pad6, GND, net_U12007_Pad8, net_U12005_Pad8, net_U12005_Pad10, G09, net_U12007_Pad12, net_U12005_Pad12, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U12008(__A12_1__PA09, net_U12006_Pad8, net_U12007_Pad12, net_U12007_Pad6, net_U12007_Pad8, , GND, , net_U12008_Pad9, net_U12008_Pad10, net_U12008_Pad11, net_U12008_Pad12, __A12_1__PA12, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12009(net_U12006_Pad8, net_U12009_Pad2, __A12_1__PA09, __A12_1__PA09_n, G10, net_U12009_Pad6, GND, net_U12009_Pad8, G11, net_U12009_Pad10, G12, net_U12009_Pad12, net_U12008_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12010(G10, G11, G10, net_U12009_Pad8, net_U12009_Pad10, net_U12008_Pad10, GND, net_U12008_Pad11, net_U12009_Pad6, G11, net_U12009_Pad10, net_U12008_Pad9, G12, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12011(net_U12009_Pad6, net_U12009_Pad8, G13, G14, G16, net_U12011_Pad6, GND, net_U12011_Pad8, G13, net_U12011_Pad10, __A12_1__G16A_n, net_U12008_Pad12, G12, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12012(__A12_1__PA12, __A12_1__PA12_n, G13, net_U12012_Pad4, G14, net_U12011_Pad10, GND, __A12_1__G16A_n, G16, net_U12012_Pad10, net_U12011_Pad6, __A12_1__PA15_n, __A12_1__PA15, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12013(net_U12012_Pad4, G14, net_U12012_Pad4, net_U12011_Pad10, G16, net_U12013_Pad6, GND, net_U12013_Pad8, net_U12005_Pad4, net_U12009_Pad2, net_U12009_Pad12, net_U12013_Pad12, __A12_1__G16A_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b0, 1'b1) U12014(__A12_1__PA15, net_U12011_Pad6, net_U12011_Pad8, net_U12013_Pad12, net_U12013_Pad6, , GND, , EXTPLS, RELPLS, INHPLS, net_U12014_Pad12, net_U12014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12015(net_U12015_Pad1, net_U12012_Pad10, G15, net_U12015_Pad4, TSUDO_n, __A12_1__T7PHS4_n, GND, __A12_1__uG02_n, G03, net_U12015_Pad10, G02, __A12_1__uG03_n, net_U12015_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U12016(net_U12013_Pad8, __A12_1__GNZRO, net_U12015_Pad1, __A12_1__GNZRO, net_U12016_Pad5, RELPLS, GND, RELPLS, net_U12015_Pad10, INHPLS, net_U12016_Pad11, INHPLS, net_U12015_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC04 U12017(__A12_1__GNZRO, net_U12017_Pad2, net_U12002_Pad6, net_U12017_Pad4, net_U12015_Pad4, net_U12017_Pad6, GND, GEQZRO_n, net_U12017_Pad9, net_U12017_Pad10, RAD, __A12_1__PB09_n, __A12_1__PB09, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12018(net_U12017_Pad4, net_U12017_Pad2, net_U12017_Pad2, net_U12017_Pad6, __A12_1__G01A_n, net_U12016_Pad5, GND, net_U12016_Pad11, net_U12017_Pad2, G01, net_U12017_Pad6, EXTPLS, net_U12017_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U12019(net_U12017_Pad9, net_U12017_Pad2, G02, G01, G03, , GND, , net_U12019_Pad9, net_U12019_Pad10, net_U12019_Pad11, net_U12019_Pad12, __A12_1__PB09, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12020(net_U12014_Pad12, net_U12014_Pad13, T12A, RADRZ, net_U12014_Pad13, net_U12017_Pad10, GND, net_U12017_Pad10, net_U12014_Pad12, RADRG, __A12_1__PA12, __A12_1__PA15, net_U12020_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12021(__A12_1__PA03, __A12_1__PA06, __A12_1__PA03, __A12_1__PA06_n, __A12_1__PA09_n, net_U12019_Pad10, GND, net_U12019_Pad11, __A12_1__PA03_n, __A12_1__PA06, __A12_1__PA09_n, net_U12019_Pad9, __A12_1__PA09, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U12022(__A12_1__PA03_n, __A12_1__PA06_n, net_U12022_Pad3, MONPAR, SAP, net_U12022_Pad6, GND, net_U12022_Pad8, SCAD, net_U12022_Pad10, GOJAM, net_U12019_Pad12, __A12_1__PA09, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12023(net_U12023_Pad1, __A12_1__PA12_n, __A12_1__PA15_n, __A12_1__PB15, net_U12020_Pad13, net_U12023_Pad1, GND, __A12_1__PB09_n, __A12_1__PB15, net_U12023_Pad10, __A12_1__PB09, __A12_1__PB15_n, net_U12023_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12024(__A12_1__PB15, __A12_1__PB15_n, __A12_1__PC15, PC15_n, __A12_1__PC15, MGP_n, GND, GEMP, PC15_n, MSP, net_U12022_Pad6, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12025(__A12_1__PC15, net_U12023_Pad10, net_U12023_Pad13, net_U12022_Pad3, CGG, net_U12022_Pad6, GND, __A12_1__PC15, net_U12022_Pad3, net_U12022_Pad10, PC15_n, net_U12022_Pad6, net_U12025_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12026(TPARG_n, n8XP5, T07_n, PHS4_n, FUTEXT, __A12_1__T7PHS4, GND, net_U12026_Pad8, XB0_n, T02_n, net_U12026_Pad11, net_U12026_Pad12, net_U12025_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U12027(net_U12022_Pad8, PALE, net_U12026_Pad12, PALE, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12028(G01ED, WEDOPG_n, WL08_n, net_U12028_Pad4, WL08_n, WSG_n, GND, net_U12028_Pad4, net_U12028_Pad13, net_U12028_Pad10, net_U12028_Pad10, CSG, net_U12028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12029(net_U12028_Pad10, S08, net_U12028_Pad13, S08_n, net_U12029_Pad5, S09, GND, S09_n, net_U12029_Pad9, S10, net_U12029_Pad11, S10_n, net_U12029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12030(G02ED, WEDOPG_n, WL09_n, net_U12030_Pad4, WL09_n, WSG_n, GND, net_U12030_Pad4, net_U12029_Pad9, net_U12029_Pad5, net_U12029_Pad5, CSG, net_U12029_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12031(G03ED, WEDOPG_n, WL10_n, net_U12031_Pad4, WL10_n, WSG_n, GND, net_U12031_Pad4, net_U12029_Pad13, net_U12029_Pad11, net_U12029_Pad11, CSG, net_U12029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12032(G04ED, WEDOPG_n, WL11_n, net_U12032_Pad4, WL11_n, WSG_n, GND, net_U12032_Pad4, net_U12032_Pad13, net_U12032_Pad10, net_U12032_Pad10, CSG, net_U12032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12033(net_U12032_Pad10, S11, net_U12032_Pad13, S11_n, net_U12033_Pad5, S12, GND, S12_n, net_U12033_Pad9, S01, net_U12033_Pad11, S01_n, net_U12033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12034(G05ED, WEDOPG_n, WL12_n, net_U12034_Pad4, WL12_n, WSG_n, GND, EDOP_n, T12A, net_U12034_Pad10, net_U12033_Pad5, CSG, net_U12033_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U12035(G06ED, WEDOPG_n, WL13_n, G07ED, WEDOPG_n, WL14_n, GND, WL01_n, WSG_n, net_U12035_Pad10, net_U12035_Pad10, net_U12033_Pad13, net_U12033_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12036(net_U12033_Pad13, net_U12033_Pad11, CSG, net_U12036_Pad4, WL02_n, WSG_n, GND, net_U12036_Pad4, net_U12036_Pad13, net_U12036_Pad10, net_U12036_Pad10, CSG, net_U12036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12037(net_U12036_Pad10, S02, net_U12036_Pad13, S02_n, net_U12037_Pad5, S03, GND, S03_n, net_U12037_Pad9, S04, net_U12037_Pad11, S04_n, net_U12037_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U12038(net_U12038_Pad1, WL03_n, WSG_n, net_U12037_Pad5, net_U12038_Pad1, net_U12037_Pad9, GND, net_U12037_Pad5, CSG, net_U12037_Pad9, WL04_n, WSG_n, net_U12038_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U12039(net_U12037_Pad11, net_U12038_Pad13, net_U12037_Pad13, net_U12037_Pad13, net_U12037_Pad11, CSG, GND, WL05_n, WSG_n, net_U12039_Pad10, net_U12039_Pad10, net_U12039_Pad12, net_U12039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U12040(net_U12039_Pad12, net_U12039_Pad13, CSG, net_U12040_Pad4, WL06_n, WSG_n, GND, net_U12040_Pad4, net_U12040_Pad13, net_U12040_Pad10, net_U12040_Pad10, CSG, net_U12040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12041(net_U12039_Pad13, S05, net_U12039_Pad12, S05_n, net_U12040_Pad10, S06, GND, S06_n, net_U12040_Pad13, S07, net_U12041_Pad11, S07_n, net_U12041_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U12042(net_U12042_Pad1, WL07_n, WSG_n, net_U12041_Pad11, net_U12042_Pad1, net_U12041_Pad13, GND, net_U12041_Pad11, CSG, net_U12041_Pad13, , , , p4VSW, SIM_RST, SIM_CLK);
U74HC04 U12043(__A12_1__T7PHS4, __A12_1__T7PHS4_n, , , OCTAD2, net_U12026_Pad11, GND, GINH, net_U12043_Pad9, __A12_2__G01A, __A12_1__G01A_n, , , p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U12044( , , , , , , GND, , net_U12044_Pad9, net_U12044_Pad10, net_U12044_Pad11, net_U12034_Pad10, net_U12043_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U12045( , , , CYR_n, net_U12026_Pad8, net_U12044_Pad9, GND, CYR_n, T12A, net_U12044_Pad9, net_U12045_Pad11, net_U12044_Pad10, SR_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U12046(net_U12026_Pad11, T02_n, net_U12026_Pad11, T02_n, XB2_n, net_U12046_Pad6, GND, net_U12046_Pad8, net_U12026_Pad11, T02_n, XB3_n, net_U12045_Pad11, XB1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U12047(net_U12044_Pad10, SR_n, T12A, CYL_n, net_U12046_Pad6, net_U12044_Pad11, GND, CYL_n, T12A, net_U12044_Pad11, net_U12046_Pad8, net_U12034_Pad10, EDOP_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 #(1'b1, 1'b0, 1'b0) U12048(n8XP5, net_U12034_Pad4, SUMA16_n, SUMB16_n, __A12_1__G01A_n, net_U12048_Pad6, GND, , , , , net_U12033_Pad5, net_U12033_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U12049(net_U12049_Pad1, __A12_2__G01A, __A12_1__G16A_n, G16SW_n, net_U12049_Pad1, net_U12048_Pad6, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74LVC06 U12050(PALE, MPAL_n, , , , , , , , , , , , , SIM_RST, SIM_CLK); //FPGA#OD:2
endmodule |
module counter_cell_ii(SIM_RST, SIM_CLK, p4VSW, GND, T12, T12A, INCSET_n, RSCT, BKTF_n, RSSB, BMAGXP, BMAGXM, BMAGYP, BMAGYM, EMSD, OTLNKM, ALTM, BMAGZP, BMAGZM, INLNKP, INLNKM, RNRADP, RNRADM, GYROD, XB0, XB1, XB2, XB3, XB4, XB5, XB6, XB7, OCTAD2, OCTAD3, OCTAD4, OCTAD5, OCTAD6, CG13, CG23, C24A, C25A, C26A, C27A, C30A, C31A, C32A, C32P, C32M, C33A, C33P, C33M, C34A, C34P, C34M, C35A, C35P, C35M, C36A, C36P, C36M, C37A, C37P, C37M, C40A, C40P, C40M, C41A, C41P, C41M, C50A, C51A, C52A, C53A, C54A, C55A, CA2_n, CA3_n, CA4_n, CA5_n, CA6_n, CXB0_n, CXB1_n, CXB2_n, CXB3_n, CXB4_n, CXB5_n, CXB6_n, CXB7_n, CAD1, CAD2, CAD3, CAD4, CAD5, CAD6, CG26, C45R, PINC, MINC, DINC, DINC_n, PCDU, MCDU, SHINC_n, SHANC_n, SHIFT, SHIFT_n, CTROR, CTROR_n);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire ALTM;
input wire BKTF_n;
input wire BMAGXM;
input wire BMAGXP;
input wire BMAGYM;
input wire BMAGYP;
input wire BMAGZM;
input wire BMAGZP;
input wire C24A;
input wire C25A;
input wire C26A;
input wire C27A;
input wire C30A;
input wire C31A;
input wire C32A;
input wire C32M;
input wire C32P;
input wire C33A;
input wire C33M;
input wire C33P;
input wire C34A;
input wire C34M;
input wire C34P;
input wire C35A;
input wire C35M;
input wire C35P;
input wire C36A;
input wire C36M;
input wire C36P;
input wire C37A;
input wire C37M;
input wire C37P;
input wire C40A;
input wire C40M;
input wire C40P;
input wire C41A;
input wire C41M;
input wire C41P;
output wire C45R;
input wire C50A;
input wire C51A;
input wire C52A;
input wire C53A;
input wire C54A;
input wire C55A;
output wire CA2_n;
output wire CA3_n;
output wire CA4_n;
output wire CA5_n;
output wire CA6_n;
output wire CAD1;
output wire CAD2;
output wire CAD3;
output wire CAD4;
output wire CAD5;
output wire CAD6;
input wire CG13;
input wire CG23;
output wire CG26;
output wire CTROR;
output wire CTROR_n;
output wire CXB0_n;
output wire CXB1_n;
output wire CXB2_n;
output wire CXB3_n;
output wire CXB4_n;
output wire CXB5_n;
output wire CXB6_n;
output wire CXB7_n;
output wire DINC;
output wire DINC_n;
input wire EMSD;
input wire GYROD;
input wire INCSET_n;
input wire INLNKM;
input wire INLNKP;
output wire MCDU;
output wire MINC;
input wire OCTAD2;
input wire OCTAD3;
input wire OCTAD4;
input wire OCTAD5;
input wire OCTAD6;
input wire OTLNKM;
output wire PCDU;
output wire PINC;
input wire RNRADM;
input wire RNRADP;
input wire RSCT;
input wire RSSB;
output wire SHANC_n;
output wire SHIFT;
output wire SHIFT_n;
output wire SHINC_n;
input wire T12;
input wire T12A;
input wire XB0;
input wire XB1;
input wire XB2;
input wire XB3;
input wire XB4;
input wire XB5;
input wire XB6;
input wire XB7;
wire __A21_1__30SUM;
wire __A21_1__32004K; //FPGA#wand
wire __A21_1__50SUM;
wire __A21_1__C42A;
wire __A21_1__C42M;
wire __A21_1__C42P;
wire __A21_1__C43A;
wire __A21_1__C43M;
wire __A21_1__C43P;
wire __A21_1__C44A;
wire __A21_1__C44M;
wire __A21_1__C44P;
wire __A21_1__C45A;
wire __A21_1__C45M;
wire __A21_1__C45P;
wire __A21_1__C46A;
wire __A21_1__C46M;
wire __A21_1__C46P;
wire __A21_1__C47A;
wire __A21_1__C56A;
wire __A21_1__C57A;
wire __A21_1__C60A;
wire __A21_1__DINCNC_n;
wire __A21_1__MCDU_n;
wire __A21_1__MINC_n;
wire __A21_1__PCDU_n;
wire __A21_1__PINC_n;
wire __A21_1__RSCT_n;
wire __A21_1__SHANC;
wire __A21_1__SHINC;
wire __A21_3__C42R;
wire __A21_3__C43R;
wire __A21_3__C44R;
wire __A21_3__C46R;
wire __A21_3__C47R;
wire __A21_3__C56R;
wire __A21_3__C57R;
wire __A21_3__C60R;
wire __A21_3__CG15;
wire __A21_3__CG16;
wire net_R21001_Pad2; //FPGA#wand
wire net_R21002_Pad2; //FPGA#wand
wire net_R21003_Pad2; //FPGA#wand
wire net_R21005_Pad2; //FPGA#wand
wire net_R21006_Pad2; //FPGA#wand
wire net_R21007_Pad2; //FPGA#wand
wire net_R21008_Pad2; //FPGA#wand
wire net_R21009_Pad2; //FPGA#wand
wire net_R21010_Pad2; //FPGA#wand
wire net_R21011_Pad2; //FPGA#wand
wire net_R21012_Pad2; //FPGA#wand
wire net_U21001_Pad1;
wire net_U21001_Pad13;
wire net_U21002_Pad11;
wire net_U21002_Pad13;
wire net_U21002_Pad5;
wire net_U21002_Pad9;
wire net_U21004_Pad10;
wire net_U21004_Pad13;
wire net_U21004_Pad4;
wire net_U21005_Pad13;
wire net_U21006_Pad11;
wire net_U21006_Pad13;
wire net_U21006_Pad5;
wire net_U21006_Pad9;
wire net_U21009_Pad1;
wire net_U21009_Pad13;
wire net_U21010_Pad11;
wire net_U21010_Pad5;
wire net_U21010_Pad9;
wire net_U21013_Pad13;
wire net_U21014_Pad11;
wire net_U21014_Pad13;
wire net_U21014_Pad3;
wire net_U21014_Pad9;
wire net_U21015_Pad13;
wire net_U21016_Pad1;
wire net_U21017_Pad13;
wire net_U21019_Pad1;
wire net_U21019_Pad10;
wire net_U21019_Pad4;
wire net_U21021_Pad4;
wire net_U21022_Pad1;
wire net_U21022_Pad13;
wire net_U21023_Pad11;
wire net_U21023_Pad13;
wire net_U21023_Pad5;
wire net_U21023_Pad9;
wire net_U21025_Pad1;
wire net_U21025_Pad13;
wire net_U21026_Pad6;
wire net_U21027_Pad5;
wire net_U21028_Pad1;
wire net_U21029_Pad1;
wire net_U21029_Pad11;
wire net_U21029_Pad13;
wire net_U21030_Pad1;
wire net_U21030_Pad10;
wire net_U21030_Pad13;
wire net_U21030_Pad3;
wire net_U21031_Pad10;
wire net_U21031_Pad12;
wire net_U21031_Pad2;
wire net_U21031_Pad4;
wire net_U21031_Pad5;
wire net_U21032_Pad1;
wire net_U21032_Pad10;
wire net_U21032_Pad13;
wire net_U21032_Pad4;
wire net_U21033_Pad12;
wire net_U21033_Pad13;
wire net_U21035_Pad10;
wire net_U21035_Pad12;
wire net_U21035_Pad13;
wire net_U21035_Pad4;
wire net_U21036_Pad10;
wire net_U21036_Pad12;
wire net_U21036_Pad13;
wire net_U21039_Pad1;
wire net_U21039_Pad12;
wire net_U21039_Pad13;
wire net_U21039_Pad3;
wire net_U21040_Pad10;
wire net_U21040_Pad13;
wire net_U21040_Pad4;
wire net_U21042_Pad1;
wire net_U21042_Pad10;
wire net_U21042_Pad12;
wire net_U21042_Pad13;
wire net_U21042_Pad3;
wire net_U21043_Pad10;
wire net_U21043_Pad12;
wire net_U21043_Pad13;
wire net_U21043_Pad4;
wire net_U21045_Pad10;
wire net_U21045_Pad12;
wire net_U21045_Pad13;
wire net_U21045_Pad4;
wire net_U21046_Pad10;
wire net_U21046_Pad13;
wire net_U21048_Pad1;
wire net_U21048_Pad10;
wire net_U21048_Pad13;
wire net_U21048_Pad3;
wire net_U21049_Pad1;
wire net_U21049_Pad10;
wire net_U21049_Pad13;
wire net_U21049_Pad3;
wire net_U21051_Pad6;
wire net_U21052_Pad3;
wire net_U21053_Pad1;
wire net_U21053_Pad10;
wire net_U21053_Pad12;
wire net_U21053_Pad3;
wire net_U21054_Pad1;
wire net_U21054_Pad11;
wire net_U21054_Pad12;
wire net_U21054_Pad13;
wire net_U21054_Pad3;
wire net_U21055_Pad10;
wire net_U21055_Pad12;
pullup R21001(net_R21001_Pad2);
pullup R21002(net_R21002_Pad2);
pullup R21003(net_R21003_Pad2);
pullup R21004(__A21_1__32004K);
pullup R21005(net_R21005_Pad2);
pullup R21006(net_R21006_Pad2);
pullup R21007(net_R21007_Pad2);
pullup R21008(net_R21008_Pad2);
pullup R21009(net_R21009_Pad2);
pullup R21010(net_R21010_Pad2);
pullup R21011(net_R21011_Pad2);
pullup R21012(net_R21012_Pad2);
U74HC4002 U21001(net_U21001_Pad1, C25A, C27A, C31A, C33A, , GND, , C35A, C37A, C41A, __A21_1__C43A, net_U21001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21002(net_U21001_Pad1, net_R21001_Pad2, net_U21001_Pad13, net_R21001_Pad2, net_U21002_Pad5, net_R21001_Pad2, GND, net_R21001_Pad2, net_U21002_Pad9, net_R21002_Pad2, net_U21002_Pad11, net_R21002_Pad2, net_U21002_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC4002 U21003(net_U21002_Pad5, __A21_1__C45A, __A21_1__C47A, C51A, C53A, , GND, , C26A, C27A, C32A, C33A, net_U21002_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U21004(net_U21002_Pad9, C55A, __A21_1__C57A, net_U21004_Pad4, __A21_1__C56A, __A21_1__C57A, GND, __A21_1__30SUM, __A21_1__C60A, net_U21004_Pad10, __A21_1__50SUM, __A21_1__C60A, net_U21004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21005(net_U21002_Pad13, C36A, C37A, __A21_1__C42A, __A21_1__C43A, , GND, , __A21_1__C46A, __A21_1__C47A, C52A, C53A, net_U21005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21006(net_U21005_Pad13, net_R21002_Pad2, net_U21004_Pad4, net_R21002_Pad2, net_U21006_Pad5, net_R21003_Pad2, GND, net_R21003_Pad2, net_U21006_Pad9, net_R21003_Pad2, net_U21006_Pad11, net_R21003_Pad2, net_U21006_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC4002 U21007(net_U21006_Pad5, C24A, C25A, C26A, C27A, , GND, , C34A, C35A, C36A, C37A, net_U21006_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21008(net_U21006_Pad11, __A21_1__C44A, __A21_1__C45A, __A21_1__C46A, __A21_1__C47A, , GND, , C54A, C55A, __A21_1__C56A, __A21_1__C57A, net_U21006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21009(net_U21009_Pad1, C30A, C31A, C32A, C33A, , GND, , C34A, C35A, C36A, C37A, net_U21009_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21010(net_U21009_Pad1, __A21_1__32004K, net_U21009_Pad13, __A21_1__32004K, net_U21010_Pad5, net_R21005_Pad2, GND, net_R21005_Pad2, net_U21010_Pad9, net_R21006_Pad2, net_U21010_Pad11, net_R21006_Pad2, net_U21004_Pad10, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC04 U21011(__A21_1__32004K, __A21_1__30SUM, net_R21005_Pad2, __A21_1__50SUM, DINC, DINC_n, GND, CXB0_n, XB0, CXB1_n, XB1, CXB2_n, XB2, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21012(net_U21010_Pad5, C50A, C51A, C52A, C53A, , GND, , C54A, C55A, __A21_1__C56A, __A21_1__C57A, net_U21010_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21013(net_U21010_Pad11, C24A, C25A, C26A, C27A, , GND, , C40A, C41A, __A21_1__C42A, __A21_1__C43A, net_U21013_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21014(net_U21013_Pad13, net_R21007_Pad2, net_U21014_Pad3, net_R21007_Pad2, net_U21004_Pad13, net_R21007_Pad2, GND, net_R21008_Pad2, net_U21014_Pad9, net_R21008_Pad2, net_U21014_Pad11, net_R21008_Pad2, net_U21014_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC4002 U21015(net_U21014_Pad3, __A21_1__C44A, __A21_1__C45A, __A21_1__C46A, __A21_1__C47A, , GND, , __A21_1__C45M, __A21_1__C46M, __A21_1__C57A, __A21_1__C60A, net_U21015_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U21016(net_U21016_Pad1, __A21_1__30SUM, __A21_1__50SUM, CAD1, __A21_1__RSCT_n, net_R21001_Pad2, GND, __A21_1__RSCT_n, net_R21002_Pad2, CAD2, __A21_1__RSCT_n, net_R21003_Pad2, CAD3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 U21017(CAD4, __A21_1__RSCT_n, net_U21016_Pad1, CAD5, __A21_1__RSCT_n, net_R21006_Pad2, GND, __A21_1__RSCT_n, net_R21007_Pad2, CAD6, __A21_1__C45P, __A21_1__C46P, net_U21017_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21018(C31A, __A21_1__C47A, C51A, C52A, C53A, net_U21014_Pad11, GND, net_U21014_Pad13, C54A, C55A, __A21_1__C56A, net_U21014_Pad9, C50A, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U21019(net_U21019_Pad1, INCSET_n, net_U21015_Pad13, net_U21019_Pad4, INCSET_n, net_U21017_Pad13, GND, INCSET_n, net_R21008_Pad2, net_U21019_Pad10, net_U21019_Pad1, __A21_1__SHINC, SHINC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21020(__A21_1__SHINC, SHINC_n, T12A, SHANC_n, net_U21019_Pad4, __A21_1__SHANC, GND, SHANC_n, T12A, __A21_1__SHANC, net_U21019_Pad10, DINC, __A21_1__DINCNC_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U21021(DINC, __A21_1__DINCNC_n, T12A, net_U21021_Pad4, INCSET_n, net_R21009_Pad2, GND, net_U21021_Pad4, PINC, __A21_1__PINC_n, __A21_1__PINC_n, T12, PINC, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21022(net_U21022_Pad1, C24A, C25A, C26A, C27A, , GND, , C30A, C37P, C40P, C41P, net_U21022_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21023(net_U21022_Pad1, net_R21009_Pad2, net_U21022_Pad13, net_R21009_Pad2, net_U21023_Pad5, net_R21009_Pad2, GND, net_R21010_Pad2, net_U21023_Pad9, net_R21010_Pad2, net_U21023_Pad11, net_R21011_Pad2, net_U21023_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC27 U21024(__A21_1__C42P, __A21_1__C43P, __A21_1__C42M, __A21_1__C43M, __A21_1__C44M, net_U21023_Pad9, GND, net_U21023_Pad11, C37M, C40M, C41M, net_U21023_Pad5, __A21_1__C44P, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U21025(net_U21025_Pad1, INCSET_n, net_R21010_Pad2, __A21_1__MINC_n, net_U21025_Pad1, MINC, GND, __A21_1__MINC_n, T12A, MINC, C35P, C36P, net_U21025_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21026(C32P, C33P, C32M, C33M, C34M, net_U21026_Pad6, GND, , , , , net_U21023_Pad13, C34P, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U21027(net_U21025_Pad13, net_R21011_Pad2, net_U21026_Pad6, net_R21012_Pad2, net_U21027_Pad5, net_R21012_Pad2, GND, , , , , , , p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U21028(net_U21028_Pad1, INCSET_n, net_R21011_Pad2, __A21_1__PCDU_n, net_U21028_Pad1, PCDU, GND, __A21_1__PCDU_n, T12A, PCDU, C35M, C36M, net_U21027_Pad5, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U21029(net_U21029_Pad1, INCSET_n, net_R21012_Pad2, __A21_1__MCDU_n, net_U21029_Pad1, MCDU, GND, __A21_1__MCDU_n, T12A, MCDU, net_U21029_Pad11, __A21_3__C43R, net_U21029_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U21030(net_U21030_Pad1, BMAGXP, net_U21030_Pad3, net_U21030_Pad3, net_U21030_Pad1, __A21_3__C42R, GND, BMAGXM, net_U21030_Pad13, net_U21030_Pad10, net_U21030_Pad10, __A21_3__C42R, net_U21030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b0) U21031(BKTF_n, net_U21031_Pad2, RSSB, net_U21031_Pad4, net_U21031_Pad5, __A21_3__CG15, GND, CTROR, CTROR_n, net_U21031_Pad10, RSSB, net_U21031_Pad12, BKTF_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U21032(net_U21032_Pad1, net_U21030_Pad3, net_U21030_Pad13, net_U21032_Pad4, net_U21031_Pad2, net_U21032_Pad1, GND, net_U21032_Pad4, net_U21032_Pad13, net_U21032_Pad10, net_U21032_Pad10, __A21_3__C42R, net_U21032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21033(__A21_1__C42A, CG13, net_U21032_Pad10, net_U21029_Pad11, BMAGYP, net_U21029_Pad13, GND, __A21_1__SHINC, __A21_1__SHANC, SHIFT_n, BMAGYM, net_U21033_Pad12, net_U21033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21034(net_U21031_Pad4, CA4_n, net_U21030_Pad1, CA4_n, CXB2_n, __A21_1__C42P, GND, __A21_1__C42M, net_U21030_Pad10, CA4_n, CXB2_n, __A21_3__C42R, CXB2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21035(net_U21033_Pad12, net_U21033_Pad13, __A21_3__C43R, net_U21035_Pad4, net_U21029_Pad13, net_U21033_Pad12, GND, net_U21031_Pad2, net_U21035_Pad4, net_U21035_Pad10, net_U21035_Pad10, net_U21035_Pad12, net_U21035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U21036(net_U21035_Pad12, net_U21035_Pad13, __A21_3__C43R, net_U21036_Pad12, EMSD, net_U21036_Pad10, GND, net_U21036_Pad12, __A21_3__C56R, net_U21036_Pad10, net_U21031_Pad2, net_U21036_Pad12, net_U21036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21037(net_U21031_Pad4, CA4_n, net_U21029_Pad11, CA4_n, CXB3_n, __A21_1__C43P, GND, __A21_1__C43M, net_U21033_Pad13, CA4_n, CXB3_n, __A21_3__C43R, CXB3_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21038(CG13, net_U21032_Pad13, CG13, net_U21032_Pad13, net_U21035_Pad12, net_U21031_Pad5, GND, __A21_3__C56R, net_U21031_Pad4, CA5_n, CXB6_n, __A21_1__C43A, net_U21035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U21039(net_U21039_Pad1, net_U21036_Pad13, net_U21039_Pad3, net_U21039_Pad3, net_U21039_Pad1, __A21_3__C56R, GND, CG23, net_U21039_Pad1, __A21_1__C56A, OTLNKM, net_U21039_Pad12, net_U21039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U21040(net_U21039_Pad12, net_U21039_Pad13, __A21_3__C57R, net_U21040_Pad4, net_U21031_Pad2, net_U21039_Pad13, GND, net_U21040_Pad4, net_U21040_Pad13, net_U21040_Pad10, net_U21040_Pad10, __A21_3__C57R, net_U21040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21041(net_U21031_Pad4, CA5_n, CG23, net_U21039_Pad3, net_U21040_Pad10, __A21_1__C57A, GND, __A21_3__C60R, net_U21031_Pad4, CA6_n, CXB0_n, __A21_3__C57R, CXB7_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U21042(net_U21042_Pad1, ALTM, net_U21042_Pad3, net_U21042_Pad3, net_U21042_Pad1, __A21_3__C60R, GND, net_U21031_Pad2, net_U21042_Pad1, net_U21042_Pad10, net_U21042_Pad10, net_U21042_Pad12, net_U21042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21043(net_U21042_Pad12, net_U21042_Pad13, __A21_3__C60R, net_U21043_Pad4, BMAGZP, net_U21043_Pad10, GND, net_U21043_Pad4, __A21_3__C44R, net_U21043_Pad10, BMAGZM, net_U21043_Pad12, net_U21043_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U21044(__A21_1__C60A, CG23, net_U21039_Pad3, net_U21040_Pad13, net_U21042_Pad13, , GND, , CG23, net_U21039_Pad3, net_U21040_Pad13, net_U21042_Pad12, CTROR_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21045(net_U21043_Pad12, net_U21043_Pad13, __A21_3__C44R, net_U21045_Pad4, net_U21043_Pad10, net_U21043_Pad12, GND, net_U21031_Pad12, net_U21045_Pad4, net_U21045_Pad10, net_U21045_Pad10, net_U21045_Pad12, net_U21045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U21046(net_U21045_Pad12, net_U21045_Pad13, __A21_3__C44R, __A21_1__C44A, __A21_3__CG15, net_U21045_Pad13, GND, INLNKP, net_U21046_Pad13, net_U21046_Pad10, net_U21046_Pad10, C45R, net_U21046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21047(net_U21031_Pad10, CA4_n, net_U21043_Pad4, CA4_n, CXB4_n, __A21_1__C44P, GND, __A21_1__C44M, net_U21043_Pad13, CA4_n, CXB4_n, __A21_3__C44R, CXB4_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U21048(net_U21048_Pad1, INLNKM, net_U21048_Pad3, net_U21048_Pad3, net_U21048_Pad1, C45R, GND, net_U21046_Pad13, net_U21048_Pad3, net_U21048_Pad10, net_U21031_Pad12, net_U21048_Pad10, net_U21048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U21049(net_U21049_Pad1, net_U21048_Pad13, net_U21049_Pad3, net_U21049_Pad3, net_U21049_Pad1, C45R, GND, RNRADP, net_U21049_Pad13, net_U21049_Pad10, net_U21049_Pad10, __A21_3__C46R, net_U21049_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21050(net_U21031_Pad10, CA4_n, net_U21046_Pad10, CA4_n, CXB5_n, __A21_1__C45P, GND, __A21_1__C45M, net_U21048_Pad1, CA4_n, CXB5_n, C45R, CXB5_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21051(__A21_3__CG15, net_U21045_Pad12, __A21_3__CG15, net_U21045_Pad12, net_U21049_Pad3, net_U21051_Pad6, GND, __A21_3__C46R, net_U21031_Pad10, CA4_n, CXB6_n, __A21_1__C45A, net_U21049_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U21052(net_U21051_Pad6, __A21_3__CG16, net_U21052_Pad3, CG26, XB3, CXB3_n, GND, CXB4_n, XB4, CXB5_n, XB5, CXB6_n, XB6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U21053(net_U21053_Pad1, net_U21031_Pad12, net_U21053_Pad3, net_U21053_Pad12, net_U21053_Pad1, net_U21053_Pad10, GND, net_U21053_Pad12, __A21_3__C46R, net_U21053_Pad10, __A21_3__CG16, net_U21053_Pad12, __A21_1__C46A, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U21054(net_U21054_Pad1, RNRADM, net_U21054_Pad3, net_U21054_Pad3, net_U21054_Pad1, __A21_3__C46R, GND, net_U21049_Pad13, net_U21054_Pad3, net_U21053_Pad3, net_U21054_Pad11, net_U21054_Pad12, net_U21054_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U21055(net_U21054_Pad12, net_U21054_Pad13, __A21_3__C47R, net_U21055_Pad12, GYROD, net_U21055_Pad10, GND, net_U21055_Pad12, __A21_3__C47R, net_U21055_Pad10, net_U21031_Pad12, net_U21055_Pad12, net_U21054_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21056(net_U21049_Pad10, CA4_n, CA4_n, CXB6_n, net_U21054_Pad1, __A21_1__C46M, GND, __A21_3__C47R, net_U21031_Pad10, CA4_n, CXB7_n, __A21_1__C46P, CXB6_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U21057(__A21_3__CG16, net_U21053_Pad10, __A21_3__CG16, net_U21053_Pad10, net_U21054_Pad12, net_U21052_Pad3, GND, , , , , __A21_1__C47A, net_U21054_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U21058(XB7, CXB7_n, OCTAD2, CA2_n, OCTAD3, CA3_n, GND, CA4_n, OCTAD4, CA5_n, OCTAD5, CA6_n, OCTAD6, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U21059(SHIFT_n, SHIFT, RSCT, __A21_1__RSCT_n, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
endmodule |
module counter_cell_i(SIM_RST, SIM_CLK, p4VSW, GND, BKTF_n, RSSB, CA2_n, CA3_n, CA4_n, CA5_n, CXB0_n, CXB1_n, CXB2_n, CXB3_n, CXB4_n, CXB5_n, CXB6_n, CXB7_n, CG26, CDUXP, CDUXM, CDUXD, CDUYP, CDUYM, CDUYD, CDUZP, CDUZM, CDUZD, T2P, T1P, T3P, T4P, T5P, T6P, TRNP, TRNM, PIPXP, PIPXM, PIPYP, PIPYM, PIPZP, PIPZM, TRUND, SHAFTP, SHAFTM, SHAFTD, THRSTD, C32A, C32P, C32M, C33A, C33P, C33M, C24A, C25A, C26A, C34A, C34P, C34M, C35A, C35P, C35M, C27A, C30A, C31A, C40A, C40P, C40M, C41A, C41P, C41M, C53A, C54A, C55A, C36A, C36P, C36M, C37A, C37P, C37M, C50A, C51A, C52A, CG13, CG23);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VSW;
input wire GND;
input wire BKTF_n;
output wire C24A;
output wire C25A;
output wire C26A;
output wire C27A;
output wire C30A;
output wire C31A;
output wire C32A;
output wire C32M;
output wire C32P;
output wire C33A;
output wire C33M;
output wire C33P;
output wire C34A;
output wire C34M;
output wire C34P;
output wire C35A;
output wire C35M;
output wire C35P;
output wire C36A;
output wire C36M;
output wire C36P;
output wire C37A;
output wire C37M;
output wire C37P;
output wire C40A;
output wire C40M;
output wire C40P;
output wire C41A;
output wire C41M;
output wire C41P;
output wire C50A;
output wire C51A;
output wire C52A;
output wire C53A;
output wire C54A;
output wire C55A;
input wire CA2_n;
input wire CA3_n;
input wire CA4_n;
input wire CA5_n;
input wire CDUXD;
input wire CDUXM;
input wire CDUXP;
input wire CDUYD;
input wire CDUYM;
input wire CDUYP;
input wire CDUZD;
input wire CDUZM;
input wire CDUZP;
output wire CG13;
output wire CG23;
input wire CG26;
input wire CXB0_n;
input wire CXB1_n;
input wire CXB2_n;
input wire CXB3_n;
input wire CXB4_n;
input wire CXB5_n;
input wire CXB6_n;
input wire CXB7_n;
input wire PIPXM;
input wire PIPXP;
input wire PIPYM;
input wire PIPYP;
input wire PIPZM;
input wire PIPZP;
input wire RSSB;
input wire SHAFTD;
input wire SHAFTM;
input wire SHAFTP;
input wire T1P;
input wire T2P;
input wire T3P;
input wire T4P;
input wire T5P;
input wire T6P;
input wire THRSTD;
input wire TRNM;
input wire TRNP;
input wire TRUND;
wire __A20_1__C10R;
wire __A20_1__C1R;
wire __A20_1__C2R;
wire __A20_1__C3R;
wire __A20_1__C4R;
wire __A20_1__C5R;
wire __A20_1__C6R;
wire __A20_1__C7R;
wire __A20_1__C8R;
wire __A20_1__C9R;
wire __A20_2__C10R;
wire __A20_2__C1R;
wire __A20_2__C2R;
wire __A20_2__C3R;
wire __A20_2__C4R;
wire __A20_2__C5R;
wire __A20_2__C6R;
wire __A20_2__C7R;
wire __A20_2__C8R;
wire __A20_2__C9R;
wire __CG11;
wire __CG12;
wire __CG14;
wire __CG21;
wire __CG22;
wire __CG24;
wire net_U20001_Pad1;
wire net_U20001_Pad10;
wire net_U20001_Pad13;
wire net_U20001_Pad3;
wire net_U20002_Pad10;
wire net_U20002_Pad12;
wire net_U20002_Pad2;
wire net_U20002_Pad4;
wire net_U20002_Pad5;
wire net_U20002_Pad9;
wire net_U20003_Pad1;
wire net_U20003_Pad10;
wire net_U20003_Pad13;
wire net_U20003_Pad4;
wire net_U20004_Pad10;
wire net_U20004_Pad12;
wire net_U20004_Pad13;
wire net_U20004_Pad4;
wire net_U20006_Pad10;
wire net_U20006_Pad12;
wire net_U20006_Pad13;
wire net_U20006_Pad4;
wire net_U20007_Pad10;
wire net_U20007_Pad12;
wire net_U20007_Pad13;
wire net_U20010_Pad1;
wire net_U20010_Pad12;
wire net_U20010_Pad13;
wire net_U20010_Pad3;
wire net_U20011_Pad10;
wire net_U20011_Pad13;
wire net_U20011_Pad4;
wire net_U20013_Pad1;
wire net_U20013_Pad10;
wire net_U20013_Pad12;
wire net_U20013_Pad13;
wire net_U20013_Pad3;
wire net_U20014_Pad10;
wire net_U20014_Pad12;
wire net_U20014_Pad13;
wire net_U20014_Pad4;
wire net_U20016_Pad10;
wire net_U20016_Pad12;
wire net_U20016_Pad13;
wire net_U20016_Pad4;
wire net_U20017_Pad10;
wire net_U20017_Pad13;
wire net_U20019_Pad1;
wire net_U20019_Pad10;
wire net_U20019_Pad13;
wire net_U20019_Pad3;
wire net_U20020_Pad1;
wire net_U20020_Pad10;
wire net_U20020_Pad13;
wire net_U20020_Pad3;
wire net_U20022_Pad6;
wire net_U20023_Pad3;
wire net_U20023_Pad5;
wire net_U20023_Pad9;
wire net_U20024_Pad1;
wire net_U20024_Pad10;
wire net_U20024_Pad12;
wire net_U20025_Pad1;
wire net_U20025_Pad10;
wire net_U20025_Pad12;
wire net_U20025_Pad13;
wire net_U20025_Pad3;
wire net_U20026_Pad10;
wire net_U20026_Pad12;
wire net_U20026_Pad13;
wire net_U20028_Pad1;
wire net_U20028_Pad10;
wire net_U20028_Pad13;
wire net_U20028_Pad3;
wire net_U20028_Pad8;
wire net_U20030_Pad1;
wire net_U20030_Pad10;
wire net_U20030_Pad13;
wire net_U20030_Pad3;
wire net_U20031_Pad10;
wire net_U20031_Pad12;
wire net_U20031_Pad2;
wire net_U20031_Pad4;
wire net_U20031_Pad5;
wire net_U20031_Pad9;
wire net_U20032_Pad1;
wire net_U20032_Pad10;
wire net_U20032_Pad13;
wire net_U20032_Pad4;
wire net_U20033_Pad10;
wire net_U20033_Pad12;
wire net_U20033_Pad13;
wire net_U20033_Pad4;
wire net_U20035_Pad10;
wire net_U20035_Pad12;
wire net_U20035_Pad13;
wire net_U20035_Pad4;
wire net_U20036_Pad10;
wire net_U20036_Pad12;
wire net_U20036_Pad13;
wire net_U20039_Pad1;
wire net_U20039_Pad12;
wire net_U20039_Pad13;
wire net_U20039_Pad3;
wire net_U20040_Pad10;
wire net_U20040_Pad13;
wire net_U20040_Pad4;
wire net_U20042_Pad1;
wire net_U20042_Pad10;
wire net_U20042_Pad12;
wire net_U20042_Pad13;
wire net_U20042_Pad3;
wire net_U20043_Pad10;
wire net_U20043_Pad12;
wire net_U20043_Pad13;
wire net_U20043_Pad4;
wire net_U20045_Pad10;
wire net_U20045_Pad12;
wire net_U20045_Pad13;
wire net_U20045_Pad4;
wire net_U20046_Pad10;
wire net_U20046_Pad13;
wire net_U20048_Pad1;
wire net_U20048_Pad10;
wire net_U20048_Pad13;
wire net_U20048_Pad3;
wire net_U20049_Pad1;
wire net_U20049_Pad10;
wire net_U20049_Pad13;
wire net_U20049_Pad3;
wire net_U20052_Pad1;
wire net_U20052_Pad10;
wire net_U20052_Pad12;
wire net_U20053_Pad1;
wire net_U20053_Pad10;
wire net_U20053_Pad12;
wire net_U20053_Pad13;
wire net_U20053_Pad3;
wire net_U20054_Pad10;
wire net_U20054_Pad12;
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20001(net_U20001_Pad1, CDUXP, net_U20001_Pad3, net_U20001_Pad3, net_U20001_Pad1, __A20_1__C1R, GND, CDUXM, net_U20001_Pad13, net_U20001_Pad10, net_U20001_Pad10, __A20_1__C1R, net_U20001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U20002(BKTF_n, net_U20002_Pad2, RSSB, net_U20002_Pad4, net_U20002_Pad5, __CG11, GND, __CG21, net_U20002_Pad9, net_U20002_Pad10, RSSB, net_U20002_Pad12, BKTF_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20003(net_U20003_Pad1, net_U20001_Pad3, net_U20001_Pad13, net_U20003_Pad4, net_U20002_Pad2, net_U20003_Pad1, GND, net_U20003_Pad4, net_U20003_Pad13, net_U20003_Pad10, net_U20003_Pad10, __A20_1__C1R, net_U20003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20004(C32A, __CG22, net_U20003_Pad10, net_U20004_Pad4, CDUYP, net_U20004_Pad10, GND, net_U20004_Pad4, __A20_1__C2R, net_U20004_Pad10, CDUYM, net_U20004_Pad12, net_U20004_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20005(net_U20002_Pad4, CA3_n, net_U20001_Pad1, CA3_n, CXB2_n, C32P, GND, C32M, net_U20001_Pad10, CA3_n, CXB2_n, __A20_1__C1R, CXB2_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20006(net_U20004_Pad12, net_U20004_Pad13, __A20_1__C2R, net_U20006_Pad4, net_U20004_Pad10, net_U20004_Pad12, GND, net_U20002_Pad2, net_U20006_Pad4, net_U20006_Pad10, net_U20006_Pad10, net_U20006_Pad12, net_U20006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U20007(net_U20006_Pad12, net_U20006_Pad13, __A20_1__C2R, net_U20007_Pad12, T2P, net_U20007_Pad10, GND, net_U20007_Pad12, __A20_1__C3R, net_U20007_Pad10, net_U20002_Pad2, net_U20007_Pad12, net_U20007_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20008(net_U20002_Pad4, CA3_n, net_U20004_Pad4, CA3_n, CXB3_n, C33P, GND, C33M, net_U20004_Pad13, CA3_n, CXB3_n, __A20_1__C2R, CXB3_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20009(__CG22, net_U20003_Pad13, __CG22, net_U20003_Pad13, net_U20006_Pad12, net_U20002_Pad5, GND, __A20_1__C3R, net_U20002_Pad4, CA2_n, CXB4_n, C33A, net_U20006_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U20010(net_U20010_Pad1, net_U20007_Pad13, net_U20010_Pad3, net_U20010_Pad3, net_U20010_Pad1, __A20_1__C3R, GND, GND, net_U20010_Pad1, C24A, T1P, net_U20010_Pad12, net_U20010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U20011(net_U20010_Pad12, net_U20010_Pad13, __A20_1__C4R, net_U20011_Pad4, net_U20002_Pad2, net_U20010_Pad13, GND, net_U20011_Pad4, net_U20011_Pad13, net_U20011_Pad10, net_U20011_Pad10, __A20_1__C4R, net_U20011_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20012(net_U20002_Pad4, CA2_n, GND, net_U20010_Pad3, net_U20011_Pad10, C25A, GND, __A20_1__C5R, net_U20002_Pad4, CA2_n, CXB6_n, __A20_1__C4R, CXB5_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U20013(net_U20013_Pad1, T3P, net_U20013_Pad3, net_U20013_Pad3, net_U20013_Pad1, __A20_1__C5R, GND, net_U20002_Pad2, net_U20013_Pad1, net_U20013_Pad10, net_U20013_Pad10, net_U20013_Pad12, net_U20013_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20014(net_U20013_Pad12, net_U20013_Pad13, __A20_1__C5R, net_U20014_Pad4, CDUZP, net_U20014_Pad10, GND, net_U20014_Pad4, __A20_1__C6R, net_U20014_Pad10, CDUZM, net_U20014_Pad12, net_U20014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U20015(C26A, GND, net_U20010_Pad3, net_U20011_Pad13, net_U20013_Pad13, , GND, , GND, net_U20010_Pad3, net_U20011_Pad13, net_U20013_Pad12, net_U20002_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20016(net_U20014_Pad12, net_U20014_Pad13, __A20_1__C6R, net_U20016_Pad4, net_U20014_Pad10, net_U20014_Pad12, GND, net_U20002_Pad12, net_U20016_Pad4, net_U20016_Pad10, net_U20016_Pad10, net_U20016_Pad12, net_U20016_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U20017(net_U20016_Pad12, net_U20016_Pad13, __A20_1__C6R, C34A, __CG11, net_U20016_Pad13, GND, TRNP, net_U20017_Pad13, net_U20017_Pad10, net_U20017_Pad10, __A20_1__C7R, net_U20017_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20018(net_U20002_Pad10, CA3_n, net_U20014_Pad4, CA3_n, CXB4_n, C34P, GND, C34M, net_U20014_Pad13, CA3_n, CXB4_n, __A20_1__C6R, CXB4_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20019(net_U20019_Pad1, TRNM, net_U20019_Pad3, net_U20019_Pad3, net_U20019_Pad1, __A20_1__C7R, GND, net_U20017_Pad13, net_U20019_Pad3, net_U20019_Pad10, net_U20002_Pad12, net_U20019_Pad10, net_U20019_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20020(net_U20020_Pad1, net_U20019_Pad13, net_U20020_Pad3, net_U20020_Pad3, net_U20020_Pad1, __A20_1__C7R, GND, T4P, net_U20020_Pad13, net_U20020_Pad10, net_U20020_Pad10, __A20_1__C8R, net_U20020_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20021(net_U20002_Pad10, CA3_n, net_U20017_Pad10, CA3_n, CXB5_n, C35P, GND, C35M, net_U20019_Pad1, CA3_n, CXB5_n, __A20_1__C7R, CXB5_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20022(__CG11, net_U20016_Pad12, __CG11, net_U20016_Pad12, net_U20020_Pad3, net_U20022_Pad6, GND, __A20_1__C8R, net_U20002_Pad10, CA2_n, CXB7_n, C35A, net_U20020_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U20023(net_U20022_Pad6, __CG12, net_U20023_Pad3, __CG22, net_U20023_Pad5, __CG14, GND, __CG24, net_U20023_Pad9, , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20024(net_U20024_Pad1, net_U20002_Pad12, net_U20020_Pad10, net_U20024_Pad12, net_U20024_Pad1, net_U20024_Pad10, GND, net_U20024_Pad12, __A20_1__C8R, net_U20024_Pad10, __CG21, net_U20024_Pad12, C27A, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U20025(net_U20025_Pad1, T5P, net_U20025_Pad3, net_U20025_Pad3, net_U20025_Pad1, __A20_1__C9R, GND, net_U20002_Pad12, net_U20025_Pad1, net_U20025_Pad10, net_U20025_Pad10, net_U20025_Pad12, net_U20025_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U20026(net_U20025_Pad12, net_U20025_Pad13, __A20_1__C9R, net_U20026_Pad12, T6P, net_U20026_Pad10, GND, net_U20026_Pad12, __A20_1__C10R, net_U20026_Pad10, net_U20002_Pad12, net_U20026_Pad12, net_U20026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20027(net_U20002_Pad10, CA3_n, __CG21, net_U20024_Pad10, net_U20025_Pad13, C30A, GND, __A20_1__C10R, net_U20002_Pad10, CA3_n, CXB1_n, __A20_1__C9R, CXB0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20028(net_U20028_Pad1, net_U20026_Pad13, net_U20028_Pad3, net_U20028_Pad3, net_U20028_Pad1, __A20_1__C10R, GND, net_U20028_Pad8, net_U20028_Pad13, net_U20028_Pad10, net_U20028_Pad10, __A20_2__C10R, net_U20028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U20029(C31A, __CG21, net_U20024_Pad10, net_U20025_Pad12, net_U20028_Pad1, , GND, , __CG21, net_U20024_Pad10, net_U20025_Pad12, net_U20028_Pad3, net_U20023_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20030(net_U20030_Pad1, PIPYP, net_U20030_Pad3, net_U20030_Pad3, net_U20030_Pad1, __A20_2__C1R, GND, PIPYM, net_U20030_Pad13, net_U20030_Pad10, net_U20030_Pad10, __A20_2__C1R, net_U20030_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U20031(BKTF_n, net_U20031_Pad2, RSSB, net_U20031_Pad4, net_U20031_Pad5, CG13, GND, CG23, net_U20031_Pad9, net_U20031_Pad10, RSSB, net_U20031_Pad12, BKTF_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20032(net_U20032_Pad1, net_U20030_Pad3, net_U20030_Pad13, net_U20032_Pad4, net_U20031_Pad2, net_U20032_Pad1, GND, net_U20032_Pad4, net_U20032_Pad13, net_U20032_Pad10, net_U20032_Pad10, __A20_2__C1R, net_U20032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20033(C40A, __CG14, net_U20032_Pad10, net_U20033_Pad4, PIPZP, net_U20033_Pad10, GND, net_U20033_Pad4, __A20_2__C2R, net_U20033_Pad10, PIPZM, net_U20033_Pad12, net_U20033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20034(net_U20031_Pad4, CA4_n, net_U20030_Pad1, CA4_n, CXB0_n, C40P, GND, C40M, net_U20030_Pad10, CA4_n, CXB0_n, __A20_2__C1R, CXB0_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20035(net_U20033_Pad12, net_U20033_Pad13, __A20_2__C2R, net_U20035_Pad4, net_U20033_Pad10, net_U20033_Pad12, GND, net_U20031_Pad2, net_U20035_Pad4, net_U20035_Pad10, net_U20035_Pad10, net_U20035_Pad12, net_U20035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U20036(net_U20035_Pad12, net_U20035_Pad13, __A20_2__C2R, net_U20036_Pad12, TRUND, net_U20036_Pad10, GND, net_U20036_Pad12, __A20_2__C3R, net_U20036_Pad10, net_U20031_Pad2, net_U20036_Pad12, net_U20036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20037(net_U20031_Pad4, CA4_n, net_U20033_Pad4, CA4_n, CXB1_n, C41P, GND, C41M, net_U20033_Pad13, CA4_n, CXB1_n, __A20_2__C2R, CXB1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20038(__CG14, net_U20032_Pad13, __CG14, net_U20032_Pad13, net_U20035_Pad12, net_U20031_Pad5, GND, __A20_2__C3R, net_U20031_Pad4, CA5_n, CXB3_n, C41A, net_U20035_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U20039(net_U20039_Pad1, net_U20036_Pad13, net_U20039_Pad3, net_U20039_Pad3, net_U20039_Pad1, __A20_2__C3R, GND, __CG24, net_U20039_Pad1, C53A, SHAFTD, net_U20039_Pad12, net_U20039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U20040(net_U20039_Pad12, net_U20039_Pad13, __A20_2__C4R, net_U20040_Pad4, net_U20031_Pad2, net_U20039_Pad13, GND, net_U20040_Pad4, net_U20040_Pad13, net_U20040_Pad10, net_U20040_Pad10, __A20_2__C4R, net_U20040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20041(net_U20031_Pad4, CA5_n, __CG24, net_U20039_Pad3, net_U20040_Pad10, C54A, GND, __A20_2__C5R, net_U20031_Pad4, CA5_n, CXB5_n, __A20_2__C4R, CXB4_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U20042(net_U20042_Pad1, THRSTD, net_U20042_Pad3, net_U20042_Pad3, net_U20042_Pad1, __A20_2__C5R, GND, net_U20031_Pad2, net_U20042_Pad1, net_U20042_Pad10, net_U20042_Pad10, net_U20042_Pad12, net_U20042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20043(net_U20042_Pad12, net_U20042_Pad13, __A20_2__C5R, net_U20043_Pad4, SHAFTP, net_U20043_Pad10, GND, net_U20043_Pad4, __A20_2__C6R, net_U20043_Pad10, SHAFTM, net_U20043_Pad12, net_U20043_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U20044(C55A, __CG24, net_U20039_Pad3, net_U20040_Pad13, net_U20042_Pad13, , GND, , __CG24, net_U20039_Pad3, net_U20040_Pad13, net_U20042_Pad12, net_U20031_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20045(net_U20043_Pad12, net_U20043_Pad13, __A20_2__C6R, net_U20045_Pad4, net_U20043_Pad10, net_U20043_Pad12, GND, net_U20031_Pad12, net_U20045_Pad4, net_U20045_Pad10, net_U20045_Pad10, net_U20045_Pad12, net_U20045_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U20046(net_U20045_Pad12, net_U20045_Pad13, __A20_2__C6R, C36A, __CG12, net_U20045_Pad13, GND, PIPXP, net_U20046_Pad13, net_U20046_Pad10, net_U20046_Pad10, __A20_2__C7R, net_U20046_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20047(net_U20031_Pad10, CA3_n, net_U20043_Pad4, CA3_n, CXB6_n, C36P, GND, C36M, net_U20043_Pad13, CA3_n, CXB6_n, __A20_2__C6R, CXB6_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20048(net_U20048_Pad1, PIPXM, net_U20048_Pad3, net_U20048_Pad3, net_U20048_Pad1, __A20_2__C7R, GND, net_U20046_Pad13, net_U20048_Pad3, net_U20048_Pad10, net_U20031_Pad12, net_U20048_Pad10, net_U20048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U20049(net_U20049_Pad1, net_U20048_Pad13, net_U20049_Pad3, net_U20049_Pad3, net_U20049_Pad1, __A20_2__C7R, GND, CDUXD, net_U20049_Pad13, net_U20049_Pad10, net_U20049_Pad10, __A20_2__C8R, net_U20049_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20050(net_U20031_Pad10, CA3_n, net_U20046_Pad10, CA3_n, CXB7_n, C37P, GND, C37M, net_U20048_Pad1, CA3_n, CXB7_n, __A20_2__C7R, CXB7_n, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20051(__CG12, net_U20045_Pad12, __CG12, net_U20045_Pad12, net_U20049_Pad3, net_U20023_Pad5, GND, __A20_2__C8R, net_U20031_Pad10, CA5_n, CXB0_n, C37A, net_U20049_Pad1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U20052(net_U20052_Pad1, net_U20031_Pad12, net_U20049_Pad10, net_U20052_Pad12, net_U20052_Pad1, net_U20052_Pad10, GND, net_U20052_Pad12, __A20_2__C8R, net_U20052_Pad10, CG26, net_U20052_Pad12, C50A, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U20053(net_U20053_Pad1, CDUYD, net_U20053_Pad3, net_U20053_Pad3, net_U20053_Pad1, __A20_2__C9R, GND, net_U20031_Pad12, net_U20053_Pad1, net_U20053_Pad10, net_U20053_Pad10, net_U20053_Pad12, net_U20053_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U20054(net_U20053_Pad12, net_U20053_Pad13, __A20_2__C9R, net_U20054_Pad12, CDUZD, net_U20054_Pad10, GND, net_U20054_Pad12, __A20_2__C10R, net_U20054_Pad10, net_U20031_Pad12, net_U20054_Pad12, net_U20028_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U20055(net_U20031_Pad10, CA5_n, CG26, net_U20052_Pad10, net_U20053_Pad13, C51A, GND, __A20_2__C10R, net_U20031_Pad10, CA5_n, CXB2_n, __A20_2__C9R, CXB1_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U20056(C52A, CG26, net_U20052_Pad10, net_U20053_Pad12, net_U20028_Pad10, , GND, , CG26, net_U20052_Pad10, net_U20053_Pad12, net_U20028_Pad13, net_U20023_Pad9, p4VSW, SIM_RST, SIM_CLK);
endmodule |
module scaler(SIM_RST, SIM_CLK, p4VDC, GND, FS01_n, RCHAT_n, RCHBT_n, FS02, F02B, FS03, F03B, FS04, F04A, F04B, FS05, FS05_n, F05A_n, F05B_n, FS06, F06B, FS07A, FS07_n, F07A, F07B, F07B_n, FS08, F08B, FS09, FS09_n, F09A, F09B, F09B_n, FS10, F10A, F10A_n, F10B, F12B, FS13, FS14, F14B, FS16, FS17, F17A, F17B, F18A, F18B, CHAT01, CHAT02, CHAT03, CHAT04, CHAT05, CHAT06, CHAT07, CHAT08, CHAT09, CHAT10, CHAT11, CHAT12, CHAT13, CHAT14, CHBT01, CHBT02, CHBT03, CHBT04, CHBT05, CHBT06, CHBT07, CHBT08, CHBT09, CHBT10, CHBT11, CHBT12, CHBT13, CHBT14);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VDC;
input wire GND;
output wire CHAT01;
output wire CHAT02;
output wire CHAT03;
output wire CHAT04;
output wire CHAT05;
output wire CHAT06;
output wire CHAT07;
output wire CHAT08;
output wire CHAT09;
output wire CHAT10;
output wire CHAT11;
output wire CHAT12;
output wire CHAT13;
output wire CHAT14;
output wire CHBT01;
output wire CHBT02;
output wire CHBT03;
output wire CHBT04;
output wire CHBT05;
output wire CHBT06;
output wire CHBT07;
output wire CHBT08;
output wire CHBT09;
output wire CHBT10;
output wire CHBT11;
output wire CHBT12;
output wire CHBT13;
output wire CHBT14;
output wire F02B;
output wire F03B;
output wire F04A;
output wire F04B;
output wire F05A_n;
output wire F05B_n;
output wire F06B;
output wire F07A;
output wire F07B;
output wire F07B_n;
output wire F08B;
output wire F09A;
output wire F09B;
output wire F09B_n;
output wire F10A;
output wire F10A_n;
output wire F10B;
output wire F12B;
output wire F14B;
output wire F17A;
output wire F17B;
output wire F18A;
output wire F18B;
input wire FS01_n;
output wire FS02;
output wire FS03;
output wire FS04;
output wire FS05;
output wire FS05_n;
output wire FS06;
output wire FS07A;
output wire FS07_n;
output wire FS08;
output wire FS09;
output wire FS09_n;
output wire FS10;
output wire FS13;
output wire FS14;
output wire FS16;
output wire FS17;
input wire RCHAT_n;
input wire RCHBT_n;
wire __A01_1__F02A;
wire __A01_1__F03A;
wire __A01_1__F05A;
wire __A01_1__F05B;
wire __A01_1__F06A;
wire __A01_1__F08A;
wire __A01_1__F11A;
wire __A01_1__F11B;
wire __A01_1__F12A;
wire __A01_1__F13A;
wire __A01_1__F13B;
wire __A01_1__F14A;
wire __A01_1__F15A;
wire __A01_1__F15B;
wire __A01_1__F16A;
wire __A01_1__F16B;
wire __A01_1__FS02A;
wire __A01_1__FS03A;
wire __A01_1__FS04A;
wire __A01_1__FS05A;
wire __A01_1__FS07;
wire __A01_1__FS11;
wire __A01_1__FS12;
wire __A01_1__FS15;
wire __A01_1__scaler_s10__FS_n;
wire __A01_1__scaler_s11__FS_n;
wire __A01_1__scaler_s12__FS_n;
wire __A01_1__scaler_s13__FS_n;
wire __A01_1__scaler_s14__FS_n;
wire __A01_1__scaler_s15__FS_n;
wire __A01_1__scaler_s16__FS_n;
wire __A01_1__scaler_s17__FS_n;
wire __A01_1__scaler_s2__FS_n;
wire __A01_1__scaler_s3__FS_n;
wire __A01_1__scaler_s4__FS_n;
wire __A01_1__scaler_s5__FS_n;
wire __A01_1__scaler_s6__FS_n;
wire __A01_1__scaler_s7__FS_n;
wire __A01_1__scaler_s8__FS_n;
wire __A01_1__scaler_s9__FS_n;
wire __A01_2__F19A;
wire __A01_2__F19B;
wire __A01_2__F20A;
wire __A01_2__F20B;
wire __A01_2__F21A;
wire __A01_2__F21B;
wire __A01_2__F22A;
wire __A01_2__F22B;
wire __A01_2__F23A;
wire __A01_2__F23B;
wire __A01_2__F24A;
wire __A01_2__F24B;
wire __A01_2__F25A;
wire __A01_2__F25B;
wire __A01_2__F26A;
wire __A01_2__F26B;
wire __A01_2__F27A;
wire __A01_2__F27B;
wire __A01_2__F28A;
wire __A01_2__F28B;
wire __A01_2__F29A;
wire __A01_2__F29B;
wire __A01_2__F30A;
wire __A01_2__F30B;
wire __A01_2__F31A;
wire __A01_2__F31B;
wire __A01_2__F32A;
wire __A01_2__F32B;
wire __A01_2__F33A;
wire __A01_2__F33B;
wire __A01_2__FS18;
wire __A01_2__FS19;
wire __A01_2__FS20;
wire __A01_2__FS21;
wire __A01_2__FS22;
wire __A01_2__FS23;
wire __A01_2__FS24;
wire __A01_2__FS25;
wire __A01_2__FS26;
wire __A01_2__FS27;
wire __A01_2__FS28;
wire __A01_2__FS29;
wire __A01_2__FS30;
wire __A01_2__FS31;
wire __A01_2__FS32;
wire __A01_2__FS33;
wire __A01_2__scaler_s18__FS_n;
wire __A01_2__scaler_s19__FS_n;
wire __A01_2__scaler_s20__FS_n;
wire __A01_2__scaler_s21__FS_n;
wire __A01_2__scaler_s22__FS_n;
wire __A01_2__scaler_s23__FS_n;
wire __A01_2__scaler_s24__FS_n;
wire __A01_2__scaler_s25__FS_n;
wire __A01_2__scaler_s26__FS_n;
wire __A01_2__scaler_s27__FS_n;
wire __A01_2__scaler_s28__FS_n;
wire __A01_2__scaler_s29__FS_n;
wire __A01_2__scaler_s30__FS_n;
wire __A01_2__scaler_s31__FS_n;
wire __A01_2__scaler_s32__FS_n;
wire __A01_2__scaler_s33__FS_n;
wire net_U1101_Pad12;
wire net_U1101_Pad3;
wire net_U1102_Pad11;
wire net_U1102_Pad8;
wire net_U1104_Pad5;
wire net_U1104_Pad6;
wire net_U1106_Pad12;
wire net_U1106_Pad3;
wire net_U1107_Pad11;
wire net_U1107_Pad8;
wire net_U1109_Pad5;
wire net_U1109_Pad6;
wire net_U1111_Pad12;
wire net_U1111_Pad3;
wire net_U1112_Pad11;
wire net_U1112_Pad8;
wire net_U1114_Pad5;
wire net_U1114_Pad6;
wire net_U1116_Pad12;
wire net_U1116_Pad3;
wire net_U1117_Pad11;
wire net_U1117_Pad8;
wire net_U1119_Pad5;
wire net_U1119_Pad6;
wire net_U1121_Pad12;
wire net_U1121_Pad3;
wire net_U1122_Pad11;
wire net_U1122_Pad8;
wire net_U1124_Pad5;
wire net_U1124_Pad6;
wire net_U1126_Pad12;
wire net_U1126_Pad3;
wire net_U1132_Pad12;
wire net_U1132_Pad3;
wire net_U1133_Pad11;
wire net_U1133_Pad8;
wire net_U1135_Pad5;
wire net_U1135_Pad6;
wire net_U1137_Pad12;
wire net_U1137_Pad3;
wire net_U1138_Pad11;
wire net_U1138_Pad8;
wire net_U1140_Pad5;
wire net_U1140_Pad6;
wire net_U1142_Pad12;
wire net_U1142_Pad3;
wire net_U1143_Pad11;
wire net_U1143_Pad8;
wire net_U1145_Pad5;
wire net_U1145_Pad6;
wire net_U1147_Pad12;
wire net_U1147_Pad3;
wire net_U1148_Pad11;
wire net_U1148_Pad8;
wire net_U1150_Pad5;
wire net_U1150_Pad6;
wire net_U1152_Pad12;
wire net_U1152_Pad3;
wire net_U1153_Pad11;
wire net_U1153_Pad8;
wire net_U1155_Pad5;
wire net_U1155_Pad6;
wire net_U1157_Pad12;
wire net_U1157_Pad3;
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1101(__A01_1__F02A, __A01_1__scaler_s2__FS_n, net_U1101_Pad3, F02B, net_U1101_Pad12, FS02, GND, net_U1101_Pad3, FS02, __A01_1__scaler_s2__FS_n, __A01_1__scaler_s2__FS_n, net_U1101_Pad12, FS02, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1102(__A01_1__F02A, FS01_n, net_U1101_Pad3, FS01_n, F02B, net_U1101_Pad12, GND, net_U1102_Pad8, __A01_1__F03A, __A01_1__F02A, net_U1102_Pad11, net_U1101_Pad3, net_U1101_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1103(__A01_1__F03A, __A01_1__scaler_s3__FS_n, net_U1102_Pad8, F03B, net_U1102_Pad11, FS03, GND, net_U1102_Pad8, FS03, __A01_1__scaler_s3__FS_n, __A01_1__scaler_s3__FS_n, net_U1102_Pad11, FS03, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1104(net_U1102_Pad8, __A01_1__F02A, F04A, __A01_1__F03A, net_U1104_Pad5, net_U1104_Pad6, GND, net_U1104_Pad5, net_U1104_Pad6, __A01_1__F03A, F04B, net_U1102_Pad11, F03B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1105(F04A, __A01_1__scaler_s4__FS_n, net_U1104_Pad6, F04B, net_U1104_Pad5, FS04, GND, net_U1104_Pad6, FS04, __A01_1__scaler_s4__FS_n, __A01_1__scaler_s4__FS_n, net_U1104_Pad5, FS04, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1106(__A01_1__F05A, __A01_1__scaler_s5__FS_n, net_U1106_Pad3, __A01_1__F05B, net_U1106_Pad12, FS05, GND, net_U1106_Pad3, FS05, __A01_1__scaler_s5__FS_n, __A01_1__scaler_s5__FS_n, net_U1106_Pad12, FS05, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1107(__A01_1__F05A, F04A, net_U1106_Pad3, F04A, __A01_1__F05B, net_U1106_Pad12, GND, net_U1107_Pad8, __A01_1__F06A, __A01_1__F05A, net_U1107_Pad11, net_U1106_Pad3, net_U1106_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1108(__A01_1__F06A, __A01_1__scaler_s6__FS_n, net_U1107_Pad8, F06B, net_U1107_Pad11, FS06, GND, net_U1107_Pad8, FS06, __A01_1__scaler_s6__FS_n, __A01_1__scaler_s6__FS_n, net_U1107_Pad11, FS06, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1109(net_U1107_Pad8, __A01_1__F05A, F07A, __A01_1__F06A, net_U1109_Pad5, net_U1109_Pad6, GND, net_U1109_Pad5, net_U1109_Pad6, __A01_1__F06A, F07B, net_U1107_Pad11, F06B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1110(F07A, __A01_1__scaler_s7__FS_n, net_U1109_Pad6, F07B, net_U1109_Pad5, __A01_1__FS07, GND, net_U1109_Pad6, __A01_1__FS07, __A01_1__scaler_s7__FS_n, __A01_1__scaler_s7__FS_n, net_U1109_Pad5, __A01_1__FS07, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1111(__A01_1__F08A, __A01_1__scaler_s8__FS_n, net_U1111_Pad3, F08B, net_U1111_Pad12, FS08, GND, net_U1111_Pad3, FS08, __A01_1__scaler_s8__FS_n, __A01_1__scaler_s8__FS_n, net_U1111_Pad12, FS08, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1112(__A01_1__F08A, F07A, net_U1111_Pad3, F07A, F08B, net_U1111_Pad12, GND, net_U1112_Pad8, F09A, __A01_1__F08A, net_U1112_Pad11, net_U1111_Pad3, net_U1111_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1113(F09A, __A01_1__scaler_s9__FS_n, net_U1112_Pad8, F09B, net_U1112_Pad11, FS09, GND, net_U1112_Pad8, FS09, __A01_1__scaler_s9__FS_n, __A01_1__scaler_s9__FS_n, net_U1112_Pad11, FS09, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1114(net_U1112_Pad8, __A01_1__F08A, F10A, F09A, net_U1114_Pad5, net_U1114_Pad6, GND, net_U1114_Pad5, net_U1114_Pad6, F09A, F10B, net_U1112_Pad11, F09B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1115(F10A, __A01_1__scaler_s10__FS_n, net_U1114_Pad6, F10B, net_U1114_Pad5, FS10, GND, net_U1114_Pad6, FS10, __A01_1__scaler_s10__FS_n, __A01_1__scaler_s10__FS_n, net_U1114_Pad5, FS10, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1116(__A01_1__F11A, __A01_1__scaler_s11__FS_n, net_U1116_Pad3, __A01_1__F11B, net_U1116_Pad12, __A01_1__FS11, GND, net_U1116_Pad3, __A01_1__FS11, __A01_1__scaler_s11__FS_n, __A01_1__scaler_s11__FS_n, net_U1116_Pad12, __A01_1__FS11, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1117(__A01_1__F11A, F10A, net_U1116_Pad3, F10A, __A01_1__F11B, net_U1116_Pad12, GND, net_U1117_Pad8, __A01_1__F12A, __A01_1__F11A, net_U1117_Pad11, net_U1116_Pad3, net_U1116_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1118(__A01_1__F12A, __A01_1__scaler_s12__FS_n, net_U1117_Pad8, F12B, net_U1117_Pad11, __A01_1__FS12, GND, net_U1117_Pad8, __A01_1__FS12, __A01_1__scaler_s12__FS_n, __A01_1__scaler_s12__FS_n, net_U1117_Pad11, __A01_1__FS12, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1119(net_U1117_Pad8, __A01_1__F11A, __A01_1__F13A, __A01_1__F12A, net_U1119_Pad5, net_U1119_Pad6, GND, net_U1119_Pad5, net_U1119_Pad6, __A01_1__F12A, __A01_1__F13B, net_U1117_Pad11, F12B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1120(__A01_1__F13A, __A01_1__scaler_s13__FS_n, net_U1119_Pad6, __A01_1__F13B, net_U1119_Pad5, FS13, GND, net_U1119_Pad6, FS13, __A01_1__scaler_s13__FS_n, __A01_1__scaler_s13__FS_n, net_U1119_Pad5, FS13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1121(__A01_1__F14A, __A01_1__scaler_s14__FS_n, net_U1121_Pad3, F14B, net_U1121_Pad12, FS14, GND, net_U1121_Pad3, FS14, __A01_1__scaler_s14__FS_n, __A01_1__scaler_s14__FS_n, net_U1121_Pad12, FS14, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1122(__A01_1__F14A, __A01_1__F13A, net_U1121_Pad3, __A01_1__F13A, F14B, net_U1121_Pad12, GND, net_U1122_Pad8, __A01_1__F15A, __A01_1__F14A, net_U1122_Pad11, net_U1121_Pad3, net_U1121_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1123(__A01_1__F15A, __A01_1__scaler_s15__FS_n, net_U1122_Pad8, __A01_1__F15B, net_U1122_Pad11, __A01_1__FS15, GND, net_U1122_Pad8, __A01_1__FS15, __A01_1__scaler_s15__FS_n, __A01_1__scaler_s15__FS_n, net_U1122_Pad11, __A01_1__FS15, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1124(net_U1122_Pad8, __A01_1__F14A, __A01_1__F16A, __A01_1__F15A, net_U1124_Pad5, net_U1124_Pad6, GND, net_U1124_Pad5, net_U1124_Pad6, __A01_1__F15A, __A01_1__F16B, net_U1122_Pad11, __A01_1__F15B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1125(__A01_1__F16A, __A01_1__scaler_s16__FS_n, net_U1124_Pad6, __A01_1__F16B, net_U1124_Pad5, FS16, GND, net_U1124_Pad6, FS16, __A01_1__scaler_s16__FS_n, __A01_1__scaler_s16__FS_n, net_U1124_Pad5, FS16, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1126(F17A, __A01_1__scaler_s17__FS_n, net_U1126_Pad3, F17B, net_U1126_Pad12, FS17, GND, net_U1126_Pad3, FS17, __A01_1__scaler_s17__FS_n, __A01_1__scaler_s17__FS_n, net_U1126_Pad12, FS17, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1127(F17A, __A01_1__F16A, net_U1126_Pad3, __A01_1__F16A, F17B, net_U1126_Pad12, GND, , , , , net_U1126_Pad3, net_U1126_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U1128(__A01_1__scaler_s2__FS_n, __A01_1__FS02A, __A01_1__scaler_s3__FS_n, __A01_1__FS03A, __A01_1__scaler_s4__FS_n, __A01_1__FS04A, GND, __A01_1__FS05A, __A01_1__scaler_s5__FS_n, F05A_n, __A01_1__F05A, F05B_n, __A01_1__F05B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1129(CHAT01, RCHAT_n, __A01_1__scaler_s6__FS_n, CHAT02, RCHAT_n, __A01_1__scaler_s7__FS_n, GND, RCHAT_n, __A01_1__scaler_s8__FS_n, CHAT03, RCHAT_n, __A01_1__scaler_s9__FS_n, CHAT04, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1130(CHAT05, RCHAT_n, __A01_1__scaler_s10__FS_n, CHAT06, RCHAT_n, __A01_1__scaler_s11__FS_n, GND, RCHAT_n, __A01_1__scaler_s12__FS_n, CHAT07, RCHAT_n, __A01_1__scaler_s13__FS_n, CHAT08, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1131(CHAT09, RCHAT_n, __A01_1__scaler_s14__FS_n, CHAT10, RCHAT_n, __A01_1__scaler_s15__FS_n, GND, RCHAT_n, __A01_1__scaler_s16__FS_n, CHAT11, RCHAT_n, __A01_1__scaler_s17__FS_n, CHAT12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1132(F18A, __A01_2__scaler_s18__FS_n, net_U1132_Pad3, F18B, net_U1132_Pad12, __A01_2__FS18, GND, net_U1132_Pad3, __A01_2__FS18, __A01_2__scaler_s18__FS_n, __A01_2__scaler_s18__FS_n, net_U1132_Pad12, __A01_2__FS18, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1133(F18A, F17A, net_U1132_Pad3, F17A, F18B, net_U1132_Pad12, GND, net_U1133_Pad8, __A01_2__F19A, F18A, net_U1133_Pad11, net_U1132_Pad3, net_U1132_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1134(__A01_2__F19A, __A01_2__scaler_s19__FS_n, net_U1133_Pad8, __A01_2__F19B, net_U1133_Pad11, __A01_2__FS19, GND, net_U1133_Pad8, __A01_2__FS19, __A01_2__scaler_s19__FS_n, __A01_2__scaler_s19__FS_n, net_U1133_Pad11, __A01_2__FS19, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1135(net_U1133_Pad8, F18A, __A01_2__F20A, __A01_2__F19A, net_U1135_Pad5, net_U1135_Pad6, GND, net_U1135_Pad5, net_U1135_Pad6, __A01_2__F19A, __A01_2__F20B, net_U1133_Pad11, __A01_2__F19B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1136(__A01_2__F20A, __A01_2__scaler_s20__FS_n, net_U1135_Pad6, __A01_2__F20B, net_U1135_Pad5, __A01_2__FS20, GND, net_U1135_Pad6, __A01_2__FS20, __A01_2__scaler_s20__FS_n, __A01_2__scaler_s20__FS_n, net_U1135_Pad5, __A01_2__FS20, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1137(__A01_2__F21A, __A01_2__scaler_s21__FS_n, net_U1137_Pad3, __A01_2__F21B, net_U1137_Pad12, __A01_2__FS21, GND, net_U1137_Pad3, __A01_2__FS21, __A01_2__scaler_s21__FS_n, __A01_2__scaler_s21__FS_n, net_U1137_Pad12, __A01_2__FS21, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1138(__A01_2__F21A, __A01_2__F20A, net_U1137_Pad3, __A01_2__F20A, __A01_2__F21B, net_U1137_Pad12, GND, net_U1138_Pad8, __A01_2__F22A, __A01_2__F21A, net_U1138_Pad11, net_U1137_Pad3, net_U1137_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1139(__A01_2__F22A, __A01_2__scaler_s22__FS_n, net_U1138_Pad8, __A01_2__F22B, net_U1138_Pad11, __A01_2__FS22, GND, net_U1138_Pad8, __A01_2__FS22, __A01_2__scaler_s22__FS_n, __A01_2__scaler_s22__FS_n, net_U1138_Pad11, __A01_2__FS22, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1140(net_U1138_Pad8, __A01_2__F21A, __A01_2__F23A, __A01_2__F22A, net_U1140_Pad5, net_U1140_Pad6, GND, net_U1140_Pad5, net_U1140_Pad6, __A01_2__F22A, __A01_2__F23B, net_U1138_Pad11, __A01_2__F22B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1141(__A01_2__F23A, __A01_2__scaler_s23__FS_n, net_U1140_Pad6, __A01_2__F23B, net_U1140_Pad5, __A01_2__FS23, GND, net_U1140_Pad6, __A01_2__FS23, __A01_2__scaler_s23__FS_n, __A01_2__scaler_s23__FS_n, net_U1140_Pad5, __A01_2__FS23, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1142(__A01_2__F24A, __A01_2__scaler_s24__FS_n, net_U1142_Pad3, __A01_2__F24B, net_U1142_Pad12, __A01_2__FS24, GND, net_U1142_Pad3, __A01_2__FS24, __A01_2__scaler_s24__FS_n, __A01_2__scaler_s24__FS_n, net_U1142_Pad12, __A01_2__FS24, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1143(__A01_2__F24A, __A01_2__F23A, net_U1142_Pad3, __A01_2__F23A, __A01_2__F24B, net_U1142_Pad12, GND, net_U1143_Pad8, __A01_2__F25A, __A01_2__F24A, net_U1143_Pad11, net_U1142_Pad3, net_U1142_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1144(__A01_2__F25A, __A01_2__scaler_s25__FS_n, net_U1143_Pad8, __A01_2__F25B, net_U1143_Pad11, __A01_2__FS25, GND, net_U1143_Pad8, __A01_2__FS25, __A01_2__scaler_s25__FS_n, __A01_2__scaler_s25__FS_n, net_U1143_Pad11, __A01_2__FS25, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1145(net_U1143_Pad8, __A01_2__F24A, __A01_2__F26A, __A01_2__F25A, net_U1145_Pad5, net_U1145_Pad6, GND, net_U1145_Pad5, net_U1145_Pad6, __A01_2__F25A, __A01_2__F26B, net_U1143_Pad11, __A01_2__F25B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1146(__A01_2__F26A, __A01_2__scaler_s26__FS_n, net_U1145_Pad6, __A01_2__F26B, net_U1145_Pad5, __A01_2__FS26, GND, net_U1145_Pad6, __A01_2__FS26, __A01_2__scaler_s26__FS_n, __A01_2__scaler_s26__FS_n, net_U1145_Pad5, __A01_2__FS26, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1147(__A01_2__F27A, __A01_2__scaler_s27__FS_n, net_U1147_Pad3, __A01_2__F27B, net_U1147_Pad12, __A01_2__FS27, GND, net_U1147_Pad3, __A01_2__FS27, __A01_2__scaler_s27__FS_n, __A01_2__scaler_s27__FS_n, net_U1147_Pad12, __A01_2__FS27, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1148(__A01_2__F27A, __A01_2__F26A, net_U1147_Pad3, __A01_2__F26A, __A01_2__F27B, net_U1147_Pad12, GND, net_U1148_Pad8, __A01_2__F28A, __A01_2__F27A, net_U1148_Pad11, net_U1147_Pad3, net_U1147_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1149(__A01_2__F28A, __A01_2__scaler_s28__FS_n, net_U1148_Pad8, __A01_2__F28B, net_U1148_Pad11, __A01_2__FS28, GND, net_U1148_Pad8, __A01_2__FS28, __A01_2__scaler_s28__FS_n, __A01_2__scaler_s28__FS_n, net_U1148_Pad11, __A01_2__FS28, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1150(net_U1148_Pad8, __A01_2__F27A, __A01_2__F29A, __A01_2__F28A, net_U1150_Pad5, net_U1150_Pad6, GND, net_U1150_Pad5, net_U1150_Pad6, __A01_2__F28A, __A01_2__F29B, net_U1148_Pad11, __A01_2__F28B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1151(__A01_2__F29A, __A01_2__scaler_s29__FS_n, net_U1150_Pad6, __A01_2__F29B, net_U1150_Pad5, __A01_2__FS29, GND, net_U1150_Pad6, __A01_2__FS29, __A01_2__scaler_s29__FS_n, __A01_2__scaler_s29__FS_n, net_U1150_Pad5, __A01_2__FS29, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1152(__A01_2__F30A, __A01_2__scaler_s30__FS_n, net_U1152_Pad3, __A01_2__F30B, net_U1152_Pad12, __A01_2__FS30, GND, net_U1152_Pad3, __A01_2__FS30, __A01_2__scaler_s30__FS_n, __A01_2__scaler_s30__FS_n, net_U1152_Pad12, __A01_2__FS30, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1153(__A01_2__F30A, __A01_2__F29A, net_U1152_Pad3, __A01_2__F29A, __A01_2__F30B, net_U1152_Pad12, GND, net_U1153_Pad8, __A01_2__F31A, __A01_2__F30A, net_U1153_Pad11, net_U1152_Pad3, net_U1152_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1154(__A01_2__F31A, __A01_2__scaler_s31__FS_n, net_U1153_Pad8, __A01_2__F31B, net_U1153_Pad11, __A01_2__FS31, GND, net_U1153_Pad8, __A01_2__FS31, __A01_2__scaler_s31__FS_n, __A01_2__scaler_s31__FS_n, net_U1153_Pad11, __A01_2__FS31, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1155(net_U1153_Pad8, __A01_2__F30A, __A01_2__F32A, __A01_2__F31A, net_U1155_Pad5, net_U1155_Pad6, GND, net_U1155_Pad5, net_U1155_Pad6, __A01_2__F31A, __A01_2__F32B, net_U1153_Pad11, __A01_2__F31B, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1156(__A01_2__F32A, __A01_2__scaler_s32__FS_n, net_U1155_Pad6, __A01_2__F32B, net_U1155_Pad5, __A01_2__FS32, GND, net_U1155_Pad6, __A01_2__FS32, __A01_2__scaler_s32__FS_n, __A01_2__scaler_s32__FS_n, net_U1155_Pad5, __A01_2__FS32, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U1157(__A01_2__F33A, __A01_2__scaler_s33__FS_n, net_U1157_Pad3, __A01_2__F33B, net_U1157_Pad12, __A01_2__FS33, GND, net_U1157_Pad3, __A01_2__FS33, __A01_2__scaler_s33__FS_n, __A01_2__scaler_s33__FS_n, net_U1157_Pad12, __A01_2__FS33, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U1158(__A01_2__F33A, __A01_2__F32A, net_U1157_Pad3, __A01_2__F32A, __A01_2__F33B, net_U1157_Pad12, GND, , , , , net_U1157_Pad3, net_U1157_Pad12, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1159(CHAT13, RCHAT_n, __A01_2__scaler_s18__FS_n, CHAT14, RCHAT_n, __A01_2__scaler_s19__FS_n, GND, RCHBT_n, __A01_2__scaler_s20__FS_n, CHBT01, RCHBT_n, __A01_2__scaler_s21__FS_n, CHBT02, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1160(CHBT03, RCHBT_n, __A01_2__scaler_s22__FS_n, CHBT04, RCHBT_n, __A01_2__scaler_s23__FS_n, GND, RCHBT_n, __A01_2__scaler_s24__FS_n, CHBT05, RCHBT_n, __A01_2__scaler_s25__FS_n, CHBT06, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1161(CHBT07, RCHBT_n, __A01_2__scaler_s26__FS_n, CHBT08, RCHBT_n, __A01_2__scaler_s27__FS_n, GND, RCHBT_n, __A01_2__scaler_s28__FS_n, CHBT09, RCHBT_n, __A01_2__scaler_s29__FS_n, CHBT10, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U1162(CHBT11, RCHBT_n, __A01_2__scaler_s30__FS_n, CHBT12, RCHBT_n, __A01_2__scaler_s31__FS_n, GND, RCHBT_n, __A01_2__scaler_s32__FS_n, CHBT13, RCHBT_n, __A01_2__scaler_s33__FS_n, CHBT14, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U1163(F07B, F07B_n, F10A, F10A_n, F09B, F09B_n, GND, FS07_n, __A01_1__FS07, FS07A, FS07_n, FS05_n, FS05, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U1164(FS09, FS09_n, , , , , GND, , , , , , , p4VDC, SIM_RST, SIM_CLK);
endmodule |
module inout_v(SIM_RST, SIM_CLK, p4VDC, p4VSW, GND, GOJAM, T10_n, F10A, CCH13, CCH33, CCH34, CCH35, RCH13_n, RCH33_n, WCH13_n, WCH34_n, WCH35_n, DKSTRT, DKEND, DKBSNC, DRPRST, PC15_n, CHWL01_n, CHWL02_n, CHWL03_n, CHWL04_n, CHWL05_n, CHWL06_n, CHWL07_n, CHWL08_n, CHWL09_n, CHWL10_n, CHWL11_n, CHWL12_n, CHWL13_n, CHWL14_n, CHWL16_n, DLKPLS, DKDATA, CH1307, CH3312);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VDC;
input wire p4VSW;
input wire GND;
input wire CCH13;
input wire CCH33;
input wire CCH34;
input wire CCH35;
output wire CH1307;
output wire CH3312;
input wire CHWL01_n;
input wire CHWL02_n;
input wire CHWL03_n;
input wire CHWL04_n;
input wire CHWL05_n;
input wire CHWL06_n;
input wire CHWL07_n;
input wire CHWL08_n;
input wire CHWL09_n;
input wire CHWL10_n;
input wire CHWL11_n;
input wire CHWL12_n;
input wire CHWL13_n;
input wire CHWL14_n;
input wire CHWL16_n;
input wire DKBSNC;
output wire DKDATA;
input wire DKEND;
input wire DKSTRT;
output wire DLKPLS;
input wire DRPRST;
input wire F10A;
input wire GOJAM;
input wire PC15_n;
input wire RCH13_n;
input wire RCH33_n;
input wire T10_n;
input wire WCH13_n;
input wire WCH34_n;
input wire WCH35_n;
wire __A22_1__16CNT;
wire __A22_1__1CNT;
wire __A22_1__32CNT;
wire __A22_1__ADVCTR;
wire __A22_1__BSYNC_n;
wire __A22_1__DATA_n; //FPGA#wand
wire __A22_1__DKCTR1;
wire __A22_1__DKCTR1_n;
wire __A22_1__DKCTR2;
wire __A22_1__DKCTR2_n;
wire __A22_1__DKCTR3;
wire __A22_1__DKCTR3_n;
wire __A22_1__DKCTR4;
wire __A22_1__DKCTR4_n;
wire __A22_1__DKCTR5;
wire __A22_1__DKCTR5_n;
wire __A22_1__DKDATB;
wire __A22_1__DKDAT_n;
wire __A22_1__DLKCLR;
wire __A22_1__DLKRPT;
wire __A22_1__END;
wire __A22_1__HIGH0_n;
wire __A22_1__HIGH1_n;
wire __A22_1__HIGH2_n;
wire __A22_1__HIGH3_n;
wire __A22_1__LOW0_n;
wire __A22_1__LOW1_n;
wire __A22_1__LOW2_n;
wire __A22_1__LOW3_n;
wire __A22_1__LOW4_n;
wire __A22_1__LOW5_n;
wire __A22_1__LOW6_n;
wire __A22_1__LOW7_n;
wire __A22_1__ORDRBT;
wire __A22_1__RDOUT_n;
wire __A22_1__WDORDR;
wire __A22_1__WRD1B1;
wire __A22_1__WRD1BP;
wire __A22_1__WRD2B2;
wire __A22_1__WRD2B3;
wire net_U22001_Pad1;
wire net_U22001_Pad12;
wire net_U22001_Pad13;
wire net_U22001_Pad3;
wire net_U22001_Pad8;
wire net_U22002_Pad6;
wire net_U22003_Pad10;
wire net_U22003_Pad11;
wire net_U22003_Pad13;
wire net_U22003_Pad6;
wire net_U22004_Pad10;
wire net_U22004_Pad13;
wire net_U22004_Pad3;
wire net_U22005_Pad13;
wire net_U22006_Pad11;
wire net_U22006_Pad12;
wire net_U22006_Pad5;
wire net_U22006_Pad8;
wire net_U22007_Pad11;
wire net_U22007_Pad12;
wire net_U22007_Pad13;
wire net_U22008_Pad11;
wire net_U22008_Pad5;
wire net_U22008_Pad9;
wire net_U22009_Pad11;
wire net_U22009_Pad5;
wire net_U22010_Pad10;
wire net_U22010_Pad11;
wire net_U22010_Pad13;
wire net_U22010_Pad9;
wire net_U22012_Pad10;
wire net_U22012_Pad11;
wire net_U22012_Pad4;
wire net_U22012_Pad8;
wire net_U22014_Pad10;
wire net_U22014_Pad11;
wire net_U22014_Pad12;
wire net_U22014_Pad8;
wire net_U22015_Pad13;
wire net_U22015_Pad3;
wire net_U22015_Pad5;
wire net_U22017_Pad1;
wire net_U22017_Pad10;
wire net_U22017_Pad11;
wire net_U22017_Pad13;
wire net_U22018_Pad10;
wire net_U22019_Pad10;
wire net_U22019_Pad13;
wire net_U22019_Pad4;
wire net_U22020_Pad11;
wire net_U22020_Pad13;
wire net_U22020_Pad9;
wire net_U22021_Pad10;
wire net_U22021_Pad13;
wire net_U22021_Pad4;
wire net_U22022_Pad8;
wire net_U22023_Pad11;
wire net_U22023_Pad13;
wire net_U22023_Pad3;
wire net_U22023_Pad5;
wire net_U22023_Pad9;
wire net_U22025_Pad8;
wire net_U22026_Pad1;
wire net_U22026_Pad10;
wire net_U22026_Pad13;
wire net_U22026_Pad4;
wire net_U22027_Pad11;
wire net_U22027_Pad6;
wire net_U22027_Pad8;
wire net_U22028_Pad11;
wire net_U22028_Pad13;
wire net_U22028_Pad5;
wire net_U22028_Pad9;
wire net_U22029_Pad10;
wire net_U22029_Pad13;
wire net_U22029_Pad4;
wire net_U22032_Pad1;
wire net_U22032_Pad10;
wire net_U22032_Pad13;
wire net_U22032_Pad4;
wire net_U22033_Pad10;
wire net_U22033_Pad4;
wire net_U22033_Pad6;
wire net_U22033_Pad8;
wire net_U22034_Pad10;
wire net_U22034_Pad12;
wire net_U22034_Pad3;
wire net_U22035_Pad10;
wire net_U22035_Pad11;
wire net_U22035_Pad12;
wire net_U22035_Pad4;
wire net_U22035_Pad5;
wire net_U22035_Pad9;
wire net_U22036_Pad10;
wire net_U22036_Pad13;
wire net_U22036_Pad4;
wire net_U22037_Pad10;
wire net_U22037_Pad4;
wire net_U22038_Pad1;
wire net_U22038_Pad10;
wire net_U22038_Pad13;
wire net_U22039_Pad10;
wire net_U22039_Pad12;
wire net_U22039_Pad13;
wire net_U22039_Pad3;
wire net_U22040_Pad10;
wire net_U22040_Pad13;
wire net_U22040_Pad4;
wire net_U22041_Pad10;
wire net_U22042_Pad1;
wire net_U22042_Pad10;
wire net_U22042_Pad13;
wire net_U22043_Pad1;
wire net_U22043_Pad10;
wire net_U22043_Pad12;
wire net_U22043_Pad13;
wire net_U22043_Pad3;
wire net_U22044_Pad10;
wire net_U22044_Pad12;
wire net_U22044_Pad6;
wire net_U22044_Pad8;
wire net_U22045_Pad13;
wire net_U22045_Pad4;
wire net_U22046_Pad10;
wire net_U22046_Pad11;
wire net_U22046_Pad12;
wire net_U22046_Pad5;
wire net_U22046_Pad9;
wire net_U22047_Pad1;
wire net_U22047_Pad10;
wire net_U22047_Pad13;
wire net_U22047_Pad4;
wire net_U22048_Pad10;
wire net_U22048_Pad4;
wire net_U22049_Pad10;
wire net_U22049_Pad12;
wire net_U22049_Pad3;
wire net_U22050_Pad10;
wire net_U22050_Pad13;
wire net_U22050_Pad4;
wire net_U22051_Pad10;
wire net_U22051_Pad4;
wire net_U22051_Pad8;
wire net_U22052_Pad1;
wire net_U22052_Pad10;
wire net_U22052_Pad13;
wire net_U22053_Pad10;
wire net_U22053_Pad12;
wire net_U22053_Pad13;
wire net_U22053_Pad3;
wire net_U22054_Pad10;
wire net_U22054_Pad13;
wire net_U22054_Pad4;
wire net_U22055_Pad10;
wire net_U22055_Pad12;
wire net_U22055_Pad6;
wire net_U22055_Pad8;
wire net_U22056_Pad1;
wire net_U22056_Pad10;
wire net_U22056_Pad11;
wire net_U22056_Pad12;
wire net_U22056_Pad13;
wire net_U22056_Pad9;
wire net_U22057_Pad5;
wire net_U22058_Pad1;
wire net_U22058_Pad10;
wire net_U22058_Pad13;
wire net_U22059_Pad1;
wire net_U22059_Pad10;
wire net_U22059_Pad12;
wire net_U22059_Pad13;
wire net_U22059_Pad3;
wire net_U22060_Pad10;
wire net_U22061_Pad13;
wire net_U22061_Pad4;
wire net_U22062_Pad1;
wire net_U22062_Pad10;
wire net_U22062_Pad13;
wire net_U22062_Pad4;
wire net_U22063_Pad10;
wire net_U22063_Pad4;
wire net_U22064_Pad10;
wire net_U22064_Pad12;
wire net_U22064_Pad3;
wire net_U22065_Pad10;
wire net_U22065_Pad13;
wire net_U22065_Pad4;
wire net_U22066_Pad12;
wire net_U22066_Pad4;
wire net_U22066_Pad6;
wire net_U22067_Pad1;
wire net_U22067_Pad10;
pullup R22001(__A22_1__DATA_n);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U22001(net_U22001_Pad1, __A22_1__DLKRPT, net_U22001_Pad3, DLKPLS, T10_n, net_U22001_Pad1, GND, net_U22001_Pad8, net_U22001_Pad13, __A22_1__DLKRPT, __A22_1__DLKRPT, net_U22001_Pad12, net_U22001_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22002(net_U22001_Pad1, DRPRST, net_U22001_Pad8, __A22_1__DLKRPT, net_U22001_Pad12, net_U22002_Pad6, GND, __A22_1__ADVCTR, __A22_1__RDOUT_n, __A22_1__WDORDR, __A22_1__BSYNC_n, net_U22001_Pad3, GOJAM, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b1, 1'b0, 1'b0, 1'b0) U22003(DKEND, net_U22001_Pad8, net_U22001_Pad8, __A22_1__END, DKSTRT, net_U22003_Pad6, GND, __A22_1__DLKCLR, net_U22003_Pad6, net_U22003_Pad10, net_U22003_Pad11, __A22_1__DKCTR1_n, net_U22003_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U22004(net_U22001_Pad12, __A22_1__DLKRPT, net_U22004_Pad3, net_U22004_Pad3, net_U22001_Pad12, F10A, GND, net_U22002_Pad6, net_U22004_Pad13, net_U22004_Pad10, net_U22004_Pad10, CCH33, net_U22004_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U22005(CH3312, RCH33_n, net_U22004_Pad13, net_U22003_Pad11, __A22_1__DLKCLR, __A22_1__ADVCTR, GND, __A22_1__DLKCLR, net_U22005_Pad13, __A22_1__RDOUT_n, __A22_1__RDOUT_n, __A22_1__END, net_U22005_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U22006(__A22_1__1CNT, net_U22003_Pad10, net_U22006_Pad12, net_U22003_Pad10, net_U22006_Pad5, net_U22006_Pad11, GND, net_U22006_Pad8, net_U22003_Pad13, __A22_1__DLKCLR, net_U22006_Pad11, net_U22006_Pad12, net_U22006_Pad11, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U22007(__A22_1__1CNT, net_U22003_Pad13, net_U22006_Pad12, net_U22006_Pad5, net_U22006_Pad11, net_U22006_Pad8, GND, net_U22006_Pad12, net_U22006_Pad8, net_U22003_Pad13, net_U22007_Pad11, net_U22007_Pad12, net_U22007_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U22008(net_U22006_Pad8, __A22_1__DKCTR1, net_U22007_Pad11, __A22_1__DKCTR2_n, net_U22008_Pad5, __A22_1__DKCTR2, GND, __A22_1__DKCTR3_n, net_U22008_Pad9, __A22_1__DKCTR3, net_U22008_Pad11, , , p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U22009(net_U22007_Pad13, net_U22006_Pad5, net_U22007_Pad12, net_U22006_Pad5, net_U22009_Pad5, net_U22009_Pad11, GND, net_U22008_Pad5, net_U22007_Pad11, __A22_1__DLKCLR, net_U22009_Pad11, net_U22007_Pad12, net_U22009_Pad11, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U22010(net_U22009_Pad5, net_U22009_Pad11, net_U22008_Pad5, net_U22007_Pad11, net_U22007_Pad12, net_U22008_Pad5, GND, net_U22008_Pad9, net_U22010_Pad9, net_U22010_Pad10, net_U22010_Pad11, net_U22008_Pad11, net_U22010_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U22011(net_U22010_Pad10, net_U22009_Pad5, net_U22010_Pad9, net_U22009_Pad5, net_U22010_Pad13, net_U22010_Pad11, GND, net_U22008_Pad11, net_U22008_Pad9, __A22_1__DLKCLR, net_U22010_Pad11, net_U22010_Pad9, net_U22010_Pad11, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b1, 1'b0, 1'b1) U22012(net_U22008_Pad9, net_U22010_Pad9, net_U22008_Pad11, net_U22012_Pad4, __A22_1__DKCTR4, net_U22012_Pad11, GND, net_U22012_Pad8, __A22_1__DKCTR4_n, net_U22012_Pad10, net_U22012_Pad11, __A22_1__DKCTR4_n, __A22_1__DKCTR4, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U22013(net_U22012_Pad4, net_U22010_Pad13, net_U22012_Pad11, net_U22010_Pad13, net_U22012_Pad10, net_U22012_Pad8, GND, __A22_1__DKCTR4_n, __A22_1__DKCTR4, __A22_1__DLKCLR, net_U22012_Pad8, net_U22012_Pad11, net_U22012_Pad8, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U22014( , , , , , , GND, net_U22014_Pad8, __A22_1__BSYNC_n, net_U22014_Pad10, net_U22014_Pad11, net_U22014_Pad12, net_U22014_Pad10, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U22015(__A22_1__16CNT, __A22_1__DKCTR5, net_U22015_Pad3, __A22_1__32CNT, net_U22015_Pad5, __A22_1__DKCTR5_n, GND, net_U22015_Pad3, __A22_1__DKCTR5_n, __A22_1__DKCTR5, net_U22014_Pad8, net_U22014_Pad12, net_U22015_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 #(1'b0, 1'b1, 1'b0) U22016(__A22_1__16CNT, net_U22012_Pad10, net_U22015_Pad3, net_U22012_Pad10, __A22_1__32CNT, net_U22015_Pad5, GND, __A22_1__DKCTR5_n, __A22_1__DKCTR5, __A22_1__DLKCLR, net_U22015_Pad5, net_U22015_Pad3, net_U22015_Pad5, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22017(net_U22017_Pad1, net_U22015_Pad13, net_U22014_Pad11, net_U22014_Pad11, net_U22014_Pad8, net_U22017_Pad1, GND, CHWL07_n, WCH13_n, net_U22017_Pad10, net_U22017_Pad11, net_U22017_Pad10, net_U22017_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U22018(net_U22017_Pad11, CCH13, net_U22017_Pad13, CH1307, RCH13_n, net_U22017_Pad13, GND, __A22_1__DLKCLR, __A22_1__WDORDR, net_U22018_Pad10, net_U22018_Pad10, net_U22015_Pad13, __A22_1__WDORDR, p4VDC, SIM_RST, SIM_CLK);
U74HC02 U22019(__A22_1__ORDRBT, net_U22017_Pad13, net_U22018_Pad10, net_U22019_Pad4, __A22_1__DKCTR5, __A22_1__DKCTR4, GND, __A22_1__DKCTR5, __A22_1__DKCTR4_n, net_U22019_Pad10, __A22_1__DKCTR4, __A22_1__DKCTR5_n, net_U22019_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U22020(net_U22019_Pad4, __A22_1__HIGH0_n, net_U22019_Pad10, __A22_1__HIGH1_n, net_U22019_Pad13, __A22_1__HIGH2_n, GND, __A22_1__HIGH3_n, net_U22020_Pad9, __A22_1__LOW0_n, net_U22020_Pad11, __A22_1__LOW1_n, net_U22020_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22021(net_U22020_Pad9, __A22_1__DKCTR4_n, __A22_1__DKCTR5_n, net_U22021_Pad4, CHWL16_n, WCH34_n, GND, net_U22021_Pad4, net_U22021_Pad13, net_U22021_Pad10, net_U22021_Pad10, CCH34, net_U22021_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22022(__A22_1__DKCTR1, __A22_1__DKCTR2, __A22_1__DKCTR1_n, __A22_1__DKCTR2, __A22_1__DKCTR3, net_U22020_Pad13, GND, net_U22022_Pad8, __A22_1__DKCTR1, __A22_1__DKCTR2_n, __A22_1__DKCTR3, net_U22020_Pad11, __A22_1__DKCTR3, p4VDC, SIM_RST, SIM_CLK);
U74HC04 U22023(net_U22022_Pad8, __A22_1__LOW2_n, net_U22023_Pad3, __A22_1__LOW3_n, net_U22023_Pad5, __A22_1__LOW4_n, GND, __A22_1__LOW5_n, net_U22023_Pad9, __A22_1__LOW6_n, net_U22023_Pad11, __A22_1__LOW7_n, net_U22023_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22024(__A22_1__DKCTR1_n, __A22_1__DKCTR2_n, __A22_1__DKCTR1, __A22_1__DKCTR2, __A22_1__DKCTR3_n, net_U22023_Pad5, GND, net_U22023_Pad9, __A22_1__DKCTR1_n, __A22_1__DKCTR2, __A22_1__DKCTR3_n, net_U22023_Pad3, __A22_1__DKCTR3, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22025(__A22_1__DKCTR1, __A22_1__DKCTR2_n, __A22_1__DKCTR1_n, __A22_1__DKCTR2_n, __A22_1__DKCTR3_n, net_U22023_Pad13, GND, net_U22025_Pad8, __A22_1__LOW0_n, net_U22021_Pad10, __A22_1__HIGH0_n, net_U22023_Pad11, __A22_1__DKCTR3_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22026(net_U22026_Pad1, WCH34_n, CHWL14_n, net_U22026_Pad4, net_U22026_Pad1, net_U22026_Pad10, GND, net_U22026_Pad4, CCH34, net_U22026_Pad10, __A22_1__DATA_n, __A22_1__WDORDR, net_U22026_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22027(__A22_1__HIGH0_n, net_U22026_Pad4, __A22_1__WRD1BP, __A22_1__WRD1B1, __A22_1__WRD2B2, net_U22027_Pad6, GND, net_U22027_Pad8, __A22_1__WRD2B3, net_U22025_Pad8, net_U22027_Pad11, net_U22027_Pad11, __A22_1__LOW1_n, p4VDC, SIM_RST, SIM_CLK);
U74LVC07 U22028(net_U22027_Pad6, __A22_1__DATA_n, net_U22027_Pad8, __A22_1__DATA_n, net_U22028_Pad5, __A22_1__DATA_n, GND, __A22_1__DATA_n, net_U22028_Pad9, __A22_1__DATA_n, net_U22028_Pad11, __A22_1__DATA_n, net_U22028_Pad13, p4VDC, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22029(__A22_1__DKDAT_n, net_U22026_Pad13, __A22_1__ORDRBT, net_U22029_Pad4, WCH34_n, PC15_n, GND, net_U22029_Pad4, net_U22029_Pad13, net_U22029_Pad10, net_U22029_Pad10, CCH34, net_U22029_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22130(__A22_1__BSYNC_n, __A22_1__RDOUT_n, , , , , GND, , , , , DKDATA, __A22_1__DKDAT_n, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U22131(DKBSNC, __A22_1__BSYNC_n, , , , , GND, , , , , , , p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22032(net_U22032_Pad1, WCH34_n, CHWL01_n, net_U22032_Pad4, net_U22032_Pad1, net_U22032_Pad10, GND, net_U22032_Pad4, CCH34, net_U22032_Pad10, WCH34_n, CHWL02_n, net_U22032_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22033(__A22_1__HIGH1_n, net_U22032_Pad4, __A22_1__HIGH1_n, net_U22033_Pad4, __A22_1__LOW5_n, net_U22033_Pad6, GND, net_U22033_Pad8, __A22_1__HIGH0_n, net_U22033_Pad10, __A22_1__LOW2_n, __A22_1__WRD1B1, __A22_1__LOW6_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22034(net_U22033_Pad4, net_U22032_Pad13, net_U22034_Pad3, net_U22034_Pad3, net_U22033_Pad4, CCH34, GND, WCH34_n, CHWL13_n, net_U22034_Pad10, net_U22034_Pad10, net_U22034_Pad12, net_U22033_Pad10, p4VDC, SIM_RST, SIM_CLK);
U74HC4002 U22035(net_U22028_Pad5, net_U22033_Pad6, net_U22033_Pad8, net_U22035_Pad4, net_U22035_Pad5, , GND, , net_U22035_Pad9, net_U22035_Pad10, net_U22035_Pad11, net_U22035_Pad12, net_U22028_Pad9, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22036(net_U22034_Pad12, net_U22033_Pad10, CCH34, net_U22036_Pad4, WCH34_n, CHWL12_n, GND, net_U22036_Pad4, net_U22036_Pad13, net_U22036_Pad10, net_U22036_Pad10, CCH34, net_U22036_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22037(__A22_1__HIGH0_n, net_U22036_Pad10, __A22_1__HIGH0_n, net_U22037_Pad4, __A22_1__LOW4_n, net_U22035_Pad5, GND, net_U22035_Pad9, __A22_1__HIGH0_n, net_U22037_Pad10, __A22_1__LOW5_n, net_U22035_Pad4, __A22_1__LOW3_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22038(net_U22038_Pad1, WCH34_n, CHWL11_n, net_U22037_Pad4, net_U22038_Pad1, net_U22038_Pad10, GND, net_U22037_Pad4, CCH34, net_U22038_Pad10, WCH34_n, CHWL10_n, net_U22038_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22039(net_U22037_Pad10, net_U22038_Pad13, net_U22039_Pad3, net_U22039_Pad3, net_U22037_Pad10, CCH34, GND, WCH34_n, CHWL09_n, net_U22039_Pad10, net_U22039_Pad10, net_U22039_Pad12, net_U22039_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22040(net_U22039_Pad12, net_U22039_Pad13, CCH34, net_U22040_Pad4, WCH34_n, CHWL08_n, GND, net_U22040_Pad4, net_U22040_Pad13, net_U22040_Pad10, net_U22040_Pad10, CCH34, net_U22040_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22041(__A22_1__HIGH0_n, net_U22039_Pad13, __A22_1__HIGH0_n, net_U22040_Pad10, __A22_1__LOW7_n, net_U22035_Pad11, GND, net_U22035_Pad12, __A22_1__HIGH1_n, net_U22041_Pad10, __A22_1__LOW0_n, net_U22035_Pad10, __A22_1__LOW6_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22042(net_U22042_Pad1, WCH34_n, CHWL07_n, net_U22041_Pad10, net_U22042_Pad1, net_U22042_Pad10, GND, net_U22041_Pad10, CCH34, net_U22042_Pad10, WCH34_n, CHWL06_n, net_U22042_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22043(net_U22043_Pad1, net_U22042_Pad13, net_U22043_Pad3, net_U22043_Pad3, net_U22043_Pad1, CCH34, GND, WCH34_n, CHWL05_n, net_U22043_Pad10, net_U22043_Pad10, net_U22043_Pad12, net_U22043_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22044(__A22_1__HIGH1_n, net_U22043_Pad1, __A22_1__HIGH1_n, net_U22043_Pad13, __A22_1__LOW2_n, net_U22044_Pad6, GND, net_U22044_Pad8, __A22_1__HIGH1_n, net_U22044_Pad10, __A22_1__LOW3_n, net_U22044_Pad12, __A22_1__LOW1_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22045(net_U22043_Pad12, net_U22043_Pad13, CCH34, net_U22045_Pad4, WCH34_n, CHWL04_n, GND, net_U22045_Pad4, net_U22045_Pad13, net_U22044_Pad10, net_U22044_Pad10, CCH34, net_U22045_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC4002 U22046(net_U22028_Pad11, net_U22044_Pad12, net_U22044_Pad6, net_U22044_Pad8, net_U22046_Pad5, , GND, , net_U22046_Pad9, net_U22046_Pad10, net_U22046_Pad11, net_U22046_Pad12, net_U22028_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22047(net_U22047_Pad1, WCH34_n, CHWL03_n, net_U22047_Pad4, net_U22047_Pad1, net_U22047_Pad10, GND, net_U22047_Pad4, CCH34, net_U22047_Pad10, WCH35_n, CHWL16_n, net_U22047_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22048(__A22_1__HIGH1_n, net_U22047_Pad4, __A22_1__HIGH2_n, net_U22048_Pad4, __A22_1__LOW0_n, net_U22046_Pad9, GND, net_U22046_Pad10, __A22_1__HIGH2_n, net_U22048_Pad10, __A22_1__LOW1_n, net_U22046_Pad5, __A22_1__LOW4_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22049(net_U22048_Pad4, net_U22047_Pad13, net_U22049_Pad3, net_U22049_Pad3, net_U22048_Pad4, CCH35, GND, WCH35_n, CHWL14_n, net_U22049_Pad10, net_U22049_Pad10, net_U22049_Pad12, net_U22048_Pad10, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22050(net_U22049_Pad12, net_U22048_Pad10, CCH35, net_U22050_Pad4, WCH35_n, CHWL13_n, GND, net_U22050_Pad4, net_U22050_Pad13, net_U22050_Pad10, net_U22050_Pad10, CCH35, net_U22050_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22051(__A22_1__HIGH2_n, net_U22050_Pad10, __A22_1__HIGH2_n, net_U22051_Pad4, __A22_1__LOW3_n, net_U22046_Pad12, GND, net_U22051_Pad8, __A22_1__HIGH2_n, net_U22051_Pad10, __A22_1__LOW4_n, net_U22046_Pad11, __A22_1__LOW2_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22052(net_U22052_Pad1, WCH35_n, CHWL12_n, net_U22051_Pad4, net_U22052_Pad1, net_U22052_Pad10, GND, net_U22051_Pad4, CCH35, net_U22052_Pad10, WCH35_n, CHWL11_n, net_U22052_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22053(net_U22051_Pad10, net_U22052_Pad13, net_U22053_Pad3, net_U22053_Pad3, net_U22051_Pad10, CCH35, GND, WCH35_n, CHWL10_n, net_U22053_Pad10, net_U22053_Pad10, net_U22053_Pad12, net_U22053_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22054(net_U22053_Pad12, net_U22053_Pad13, CCH35, net_U22054_Pad4, WCH35_n, CHWL09_n, GND, net_U22054_Pad4, net_U22054_Pad13, net_U22054_Pad10, net_U22054_Pad10, CCH35, net_U22054_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22055(__A22_1__HIGH2_n, net_U22053_Pad13, __A22_1__HIGH2_n, net_U22054_Pad10, __A22_1__LOW6_n, net_U22055_Pad6, GND, net_U22055_Pad8, __A22_1__HIGH2_n, net_U22055_Pad10, __A22_1__LOW7_n, net_U22055_Pad12, __A22_1__LOW5_n, p4VDC, SIM_RST, SIM_CLK);
U74HC4002 U22056(net_U22056_Pad1, net_U22051_Pad8, net_U22055_Pad12, net_U22055_Pad6, net_U22055_Pad8, , GND, , net_U22056_Pad9, net_U22056_Pad10, net_U22056_Pad11, net_U22056_Pad12, net_U22056_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74LVC07 U22057(net_U22056_Pad1, __A22_1__DATA_n, net_U22056_Pad13, __A22_1__DATA_n, net_U22057_Pad5, __A22_1__DATA_n, GND, , , , , , , p4VDC, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22058(net_U22058_Pad1, WCH35_n, CHWL08_n, net_U22055_Pad10, net_U22058_Pad1, net_U22058_Pad10, GND, net_U22055_Pad10, CCH35, net_U22058_Pad10, WCH35_n, CHWL07_n, net_U22058_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22059(net_U22059_Pad1, net_U22058_Pad13, net_U22059_Pad3, net_U22059_Pad3, net_U22059_Pad1, CCH35, GND, WCH35_n, CHWL06_n, net_U22059_Pad10, net_U22059_Pad10, net_U22059_Pad12, net_U22059_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22060(__A22_1__HIGH3_n, net_U22059_Pad1, __A22_1__HIGH3_n, net_U22059_Pad13, __A22_1__LOW1_n, net_U22056_Pad10, GND, net_U22056_Pad11, __A22_1__HIGH3_n, net_U22060_Pad10, __A22_1__LOW2_n, net_U22056_Pad9, __A22_1__LOW0_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22061(net_U22059_Pad12, net_U22059_Pad13, CCH35, net_U22061_Pad4, WCH35_n, CHWL05_n, GND, net_U22061_Pad4, net_U22061_Pad13, net_U22060_Pad10, net_U22060_Pad10, CCH35, net_U22061_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22062(net_U22062_Pad1, WCH35_n, CHWL04_n, net_U22062_Pad4, net_U22062_Pad1, net_U22062_Pad10, GND, net_U22062_Pad4, CCH35, net_U22062_Pad10, WCH35_n, CHWL03_n, net_U22062_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22063(__A22_1__HIGH3_n, net_U22062_Pad4, __A22_1__HIGH3_n, net_U22063_Pad4, __A22_1__LOW4_n, __A22_1__WRD2B3, GND, __A22_1__WRD2B2, __A22_1__HIGH3_n, net_U22063_Pad10, __A22_1__LOW5_n, net_U22056_Pad12, __A22_1__LOW3_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U22064(net_U22063_Pad4, net_U22062_Pad13, net_U22064_Pad3, net_U22064_Pad3, net_U22063_Pad4, CCH35, GND, WCH35_n, CHWL02_n, net_U22064_Pad10, net_U22064_Pad10, net_U22064_Pad12, net_U22063_Pad10, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U22065(net_U22064_Pad12, net_U22063_Pad10, CCH35, net_U22065_Pad4, WCH35_n, CHWL01_n, GND, net_U22065_Pad4, net_U22065_Pad13, net_U22065_Pad10, net_U22065_Pad10, CCH35, net_U22065_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22066(__A22_1__HIGH3_n, net_U22065_Pad10, __A22_1__HIGH3_n, net_U22066_Pad4, __A22_1__LOW7_n, net_U22066_Pad6, GND, , , , , net_U22066_Pad12, __A22_1__LOW6_n, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U22067(net_U22067_Pad1, WCH35_n, PC15_n, net_U22066_Pad4, net_U22067_Pad1, net_U22067_Pad10, GND, net_U22066_Pad4, CCH35, net_U22067_Pad10, net_U22066_Pad12, net_U22066_Pad6, net_U22057_Pad5, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U22068(__A22_1__BSYNC_n, __A22_1__RDOUT_n, __A22_1__HIGH1_n, net_U22029_Pad10, __A22_1__LOW7_n, __A22_1__WRD1BP, GND, , , , , __A22_1__DKDATB, __A22_1__DKDAT_n, p4VDC, SIM_RST, SIM_CLK);
endmodule |
module nor_4(y, a, b, c, d, rst, clk);
parameter delay = 9;
parameter iv = 1'b0;
input wire a, b, c, d, rst, clk;
`ifdef TARGET_FPGA
output reg y = iv;
reg next_val = iv;
reg prev_val = iv;
wire result;
assign result = ~(a|b|c|d);
always @(posedge clk)
begin
prev_val = y;
y = next_val;
end
always @(negedge clk)
begin
next_val = ((result == prev_val) && (y == iv)) ? iv : result;
end
`else
output wire y;
assign #delay y = (rst) ? iv : ~(a|b|c|d);
`endif
endmodule |
module nor_1(y, a, rst, clk);
parameter delay = 9;
parameter iv = 1'b0;
input wire a, rst, clk;
`ifdef TARGET_FPGA
output reg y = iv;
reg next_val = iv;
always @(posedge clk)
begin
y = next_val;
end
always @(negedge clk)
begin
next_val = ~a;
end
`else
output wire y;
assign #delay y = (rst) ? iv : ~a;
`endif
endmodule |
module U74HC244(oe1_n, a11, y24, a12, y23, a13, y22, a14, y21, gnd, a21, y14, a22, y13, a23, y12, a24, y11, oe2_n, vcc, rst, clk);
localparam delay = 18;
input wire vcc, gnd, rst, clk;
input wire a11, a12, a13, a14, a21, a22, a23, a24;
output wire y11, y12, y13, y14, y21, y22, y23, y24;
input wire oe1_n, oe2_n;
tri_buf #(delay) A(y11, a11, oe1_n);
tri_buf #(delay) B(y12, a12, oe1_n);
tri_buf #(delay) C(y13, a13, oe1_n);
tri_buf #(delay) D(y14, a14, oe1_n);
tri_buf #(delay) E(y21, a21, oe2_n);
tri_buf #(delay) F(y22, a22, oe2_n);
tri_buf #(delay) G(y23, a23, oe2_n);
tri_buf #(delay) H(y24, a24, oe2_n);
endmodule |
module MR0A16A (A0, A1, A2, A3, A4, E_n, DQL0, DQL1, DQL2, DQL3, VDD1, VSS1, DQL4, DQL5, DQL6, DQL7, W_n, A5, A6, A7, A8, A9, A10, A11, A12, VSS2, VDD2, DC, DQU8, DQU9, DQU10, DQU11, VDD3, VSS3, DQU12, DQU13, DQU14, DQU15, LB_n, UB_n, G_n, A13, A14, A15, SIM_RST, SIM_CLK
`ifdef TARGET_FPGA
, DQL0_in, DQL1_in, DQL2_in, DQL3_in, DQL4_in, DQL5_in, DQL6_in, DQL7_in, DQU8_in, DQU9_in, DQU10_in, DQU11_in, DQU12_in, DQU13_in, DQU14_in, DQU15_in
`endif
);
localparam delay = 30;
input wire SIM_RST;
input wire SIM_CLK;
input wire VDD1;
input wire VDD2;
input wire VDD3;
input wire VSS1;
input wire VSS2;
input wire VSS3;
input wire E_n;
input wire G_n;
input wire W_n;
input wire LB_n;
input wire UB_n;
input wire A0;
input wire A1;
input wire A2;
input wire A3;
input wire A4;
input wire A5;
input wire A6;
input wire A7;
input wire A8;
input wire A9;
input wire A10;
input wire A11;
input wire A12;
input wire A13;
input wire A14;
input wire A15;
inout wire DQL0;
inout wire DQL1;
inout wire DQL2;
inout wire DQL3;
inout wire DQL4;
inout wire DQL5;
inout wire DQL6;
inout wire DQL7;
inout wire DQU8;
inout wire DQU9;
inout wire DQU10;
inout wire DQU11;
inout wire DQU12;
inout wire DQU13;
inout wire DQU14;
inout wire DQU15;
input wire DC;
`ifdef TARGET_FPGA
input wire DQL0_in;
input wire DQL1_in;
input wire DQL2_in;
input wire DQL3_in;
input wire DQL4_in;
input wire DQL5_in;
input wire DQL6_in;
input wire DQL7_in;
input wire DQU8_in;
input wire DQU9_in;
input wire DQU10_in;
input wire DQU11_in;
input wire DQU12_in;
input wire DQU13_in;
input wire DQU14_in;
input wire DQU15_in;
`endif
wire [10:0] addr;
assign addr = {A10, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0};
wire [15:0] sensed_word;
wire [15:0] write_word;
assign DQL0 = sensed_word[0];
assign DQL1 = sensed_word[1];
assign DQL2 = sensed_word[2];
assign DQL3 = sensed_word[3];
assign DQL4 = sensed_word[4];
assign DQL5 = sensed_word[5];
assign DQL6 = sensed_word[6];
assign DQL7 = sensed_word[7];
assign DQU8 = sensed_word[8];
assign DQU9 = sensed_word[9];
assign DQU10 = sensed_word[10];
assign DQU11 = sensed_word[11];
assign DQU12 = sensed_word[12];
assign DQU13 = sensed_word[13];
assign DQU14 = sensed_word[14];
assign DQU15 = sensed_word[15];
`ifdef TARGET_FPGA
wire wren;
assign wren = !W_n;
wire [15:0] read_word;
assign sensed_word = (!E_n && !G_n) ? read_word : 16'b0;
assign write_word = {DQU15_in, DQU14_in, DQU13_in, DQU12_in, DQU11_in, DQU10_in, DQU9_in, DQU8_in, DQL7_in, DQL6_in, DQL5_in, DQL4_in, DQL3_in, DQL2_in, DQL1_in, DQL0_in};
core_memory ram(addr, SIM_CLK, write_word, wren, read_word);
`else
reg [15:0] ram[0:2047];
assign #delay write_word = {DQU15, DQU14, DQU13, DQU12, DQU11, DQU10, DQU9, DQU8, DQL7, DQL6, DQL5, DQL4, DQL3, DQL2, DQL1, DQL0};
assign #delay sensed_word = (!E_n && !G_n) ? ram[addr] : 16'bZ;
reg [11:0] i;
initial begin
for (i = 0; i < 2048; i = i + 1)
begin
ram[i] = 16'o40000;
end
end
always @(E_n or W_n or G_n) begin
if (!E_n && G_n && !W_n) begin
ram[addr] = write_word;
end else if (!E_n && !G_n && !W_n) begin
$display("ERROR: Write and read on MRAM");
$finish;
end
end
`endif
endmodule |
module U74LVC07(a1, y1, a2, y2, a3, y3, gnd, y4, a4, y5, a5, y6, a6, vcc, rst, clk);
localparam delay = 2;
localparam od_value = 1'b1;
input wire vcc, gnd, rst, clk;
input wire a1, a2, a3, a4, a5, a6;
output wire y1, y2, y3, y4, y5, y6;
od_buf #(delay, od_value) A(y1, a1);
od_buf #(delay, od_value) B(y2, a2);
od_buf #(delay, od_value) C(y3, a3);
od_buf #(delay, od_value) D(y4, a4);
od_buf #(delay, od_value) E(y5, a5);
od_buf #(delay, od_value) F(y6, a6);
endmodule |
module tri_buf(y, a, oe_n);
parameter delay = 13;
input wire a;
input wire oe_n;
output wire y;
`ifdef TARGET_FPGA
assign y = (oe_n == 1'b0) ? a : 1'b0;
`else
assign #delay y = (oe_n == 1'b0) ? a : 1'bZ;
`endif
endmodule |
module U74HC02(y1, a1, b1, y2, a2, b2, gnd, a3, b3, y3, a4, b4, y4, vcc, rst, clk);
parameter ic1 = 1'b0;
parameter ic2 = 1'b0;
parameter ic3 = 1'b0;
parameter ic4 = 1'b0;
localparam delay = 9;
input wire vcc, gnd, rst, clk;
input wire a1, b1, a2, b2, a3, b3, a4, b4;
output wire y1, y2, y3, y4;
// Treat loss of power like a reset hold
wire vrst;
assign vrst = (rst || !vcc);
nor_2 #(delay, ic1) A(y1, a1, b1, vrst, clk);
nor_2 #(delay, ic2) B(y2, a2, b2, vrst, clk);
nor_2 #(delay, ic3) C(y3, a3, b3, vrst, clk);
nor_2 #(delay, ic4) D(y4, a4, b4, vrst, clk);
endmodule |
module U74HC27(a1, b1, a2, b2, c2, y2, gnd, y3, a3, b3, c3, y1, c1, vcc, rst, clk);
parameter ic1 = 1'b0;
parameter ic2 = 1'b0;
parameter ic3 = 1'b0;
localparam delay = 9;
input wire vcc, gnd, rst, clk;
input wire a1, b1, c1, a2, b2, c2, a3, b3, c3;
output wire y1, y2, y3;
// Treat loss of power like a reset hold
wire vrst;
assign vrst = (rst || !vcc);
nor_3 #(delay, ic1) A(y1, a1, b1, c1, vrst, clk);
nor_3 #(delay, ic2) B(y2, a2, b2, c2, vrst, clk);
nor_3 #(delay, ic3) C(y3, a3, b3, c3, vrst, clk);
endmodule |
module od_buf(y, a);
parameter delay = 2;
parameter od_value = 1'b1;
input wire a;
output wire y;
`ifdef TARGET_FPGA
assign y = (od_value == 1'b1) ? a : ~a;
`else
assign #delay y = (a == od_value) ? 1'bZ : 1'b0;
`endif
endmodule |
module U74HC04(a1, y1, a2, y2, a3, y3, gnd, y4, a4, y5, a5, y6, a6, vcc, rst, clk);
parameter ic1 = 1'b0;
parameter ic2 = 1'b0;
parameter ic3 = 1'b0;
parameter ic4 = 1'b0;
parameter ic5 = 1'b0;
parameter ic6 = 1'b0;
localparam delay = 9;
input wire vcc, gnd, rst, clk;
input wire a1, a2, a3, a4, a5, a6;
output wire y1, y2, y3, y4, y5, y6;
// Treat loss of power like a reset hold
wire vrst;
assign vrst = (rst || !vcc);
nor_1 #(delay, ic1) A(y1, a1, vrst, clk);
nor_1 #(delay, ic2) B(y2, a2, vrst, clk);
nor_1 #(delay, ic3) C(y3, a3, vrst, clk);
nor_1 #(delay, ic4) D(y4, a4, vrst, clk);
nor_1 #(delay, ic5) E(y5, a5, vrst, clk);
nor_1 #(delay, ic6) F(y6, a6, vrst, clk);
endmodule |
module U74HC4002(y1, a1, b1, c1, d1, nc1, gnd, nc2, a2, b2, c2, d2, y2, vcc, rst, clk);
parameter ic1 = 1'b0;
parameter ic2 = 1'b0;
localparam delay = 9;
input wire vcc, gnd, rst, clk;
input wire a1, b1, c1, d1, a2, b2, c2, d2;
input wire nc1, nc2;
output wire y1, y2;
// Treat loss of power like a reset hold
wire vrst;
assign vrst = (rst || !vcc);
nor_4 #(delay, ic1) A(y1, a1, b1, c1, d1, vrst, clk);
nor_4 #(delay, ic2) B(y2, a2, b2, c2, d2, vrst, clk);
endmodule |
module pll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 125,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 128,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3125,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 128,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule |
module core_memory (
address,
clock,
data,
wren,
q);
input [10:0] address;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../ram.rif"
`else
altsyncram_component.init_file = "../ram.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 1;
endmodule |
module fpga_ch77_alarm_box(p4VDC, p4VSW, GND, SIM_RST, SIM_CLK, MCTRAL_n, MPAL_n, MRCH, MRPTAL_n, MSCAFL_n, MSCDBL_n, MT01, MT05, MT12, MTCAL_n, MVFAIL_n, MWATCH_n, MWCH, MWL01, MWL02, MWL03, MWL04, MWL05, MWL06, MWSG, DBLTST, DOSCAL, MAMU, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MLDCH, MLOAD, MNHNC, MNHRPT, MNHSBF, MONPAR, MONWBK, MRDCH, MREAD, MSBSTP, MSTP, MSTRT, MTCSAI, NHALGA);
input wire p4VDC;
input wire p4VSW;
input wire GND;
input wire SIM_RST;
input wire SIM_CLK;
input wire MCTRAL_n;
input wire MPAL_n;
input wire MRCH;
input wire MRPTAL_n;
input wire MSCAFL_n;
input wire MSCDBL_n;
input wire MT01;
input wire MT05;
input wire MT12;
input wire MTCAL_n;
input wire MVFAIL_n;
input wire MWATCH_n;
input wire MWCH;
input wire MWL01;
input wire MWL02;
input wire MWL03;
input wire MWL04;
input wire MWL05;
input wire MWL06;
input wire MWSG;
output wire DBLTST;
output wire DOSCAL;
output wire MAMU;
output wire MDT01;
output wire MDT02;
output wire MDT03;
output wire MDT04;
output wire MDT05;
output wire MDT06;
output wire MDT07;
output wire MDT08;
output wire MDT09;
output wire MDT10;
output wire MDT11;
output wire MDT12;
output wire MDT13;
output wire MDT14;
output wire MDT15;
output wire MDT16;
output wire MLDCH;
output wire MLOAD;
output wire MNHNC;
output wire MNHRPT;
output wire MNHSBF;
output wire MONPAR;
output wire MONWBK;
output wire MRDCH;
output wire MREAD;
output wire MSBSTP;
output wire MSTP;
output wire MSTRT;
output wire MTCSAI;
output wire NHALGA;
wire __RestartMonitor__CCH77;
wire __RestartMonitor__RCH77_n;
wand __Z99_NET_100;
wire __Z99_NET_100_U77004_2;
wire __Z99_NET_100_U77004_4;
wire __Z99_NET_101;
wire __Z99_NET_102;
wire __Z99_NET_105;
wire __Z99_NET_56;
wire __Z99_NET_57;
wire __Z99_NET_58;
wire __Z99_NET_59;
wire __Z99_NET_60;
wire __Z99_NET_61;
wire __Z99_NET_62;
wire __Z99_NET_63;
wire __Z99_NET_64;
wire __Z99_NET_65;
wire __Z99_NET_66;
wire __Z99_NET_67;
wire __Z99_NET_68;
wire __Z99_NET_69;
wire __Z99_NET_70;
wire __Z99_NET_71;
wire __Z99_NET_72;
wire __Z99_NET_73;
wire __Z99_NET_74;
wire __Z99_NET_75;
wire __Z99_NET_76;
wire __Z99_NET_77;
wire __Z99_NET_78;
wire __Z99_NET_79;
wire __Z99_NET_80;
wire __Z99_NET_81;
wire __Z99_NET_82;
wire __Z99_NET_83;
wire __Z99_NET_84;
wire __Z99_NET_87;
wire __Z99_NET_88;
wire __Z99_NET_89;
wire __Z99_NET_90;
wire __Z99_NET_91;
wire __Z99_NET_92;
wire __Z99_NET_94;
wire __Z99_NET_95;
wire __Z99_NET_96;
wire __Z99_NET_98;
wire __Z99_NET_99;
assign MDT10 = GND;
assign MDT11 = GND;
assign MDT12 = GND;
assign MDT13 = GND;
assign MDT14 = GND;
assign MDT15 = GND;
assign MDT16 = GND;
assign MNHSBF = GND;
assign MNHNC = GND;
assign MNHRPT = GND;
assign MTCSAI = GND;
assign MSTRT = GND;
assign MSTP = GND;
assign MSBSTP = GND;
assign MRDCH = GND;
assign MLDCH = GND;
assign MONPAR = GND;
assign MONWBK = GND;
assign MLOAD = GND;
assign MREAD = GND;
assign NHALGA = GND;
assign DOSCAL = GND;
assign DBLTST = GND;
assign MAMU = GND;
U74HC04 U77001(MWL01, __Z99_NET_102, MWL02, __Z99_NET_91, MWL03, __Z99_NET_92, GND, __Z99_NET_105, MWL04, __Z99_NET_89, MWL05, __Z99_NET_90, MWL06, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b1, 1'b1, 1'b1, 1'b0) U77002(MT01, __Z99_NET_101, MWSG, __Z99_NET_94, MWCH, __Z99_NET_87, GND, __Z99_NET_88, MRCH, __RestartMonitor__RCH77_n, __Z99_NET_73, __Z99_NET_75, MPAL_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U77003(__Z99_NET_96, __Z99_NET_102, __Z99_NET_91, __Z99_NET_92, __Z99_NET_105, , GND, , __Z99_NET_89, __Z99_NET_90, __Z99_NET_101, __Z99_NET_94, __Z99_NET_95, p4VSW, SIM_RST, SIM_CLK);
assign __Z99_NET_100 = __Z99_NET_100_U77004_2;
assign __Z99_NET_100 = __Z99_NET_100_U77004_4;
U74LVC07 U77004(__Z99_NET_96, __Z99_NET_100_U77004_2, __Z99_NET_95, __Z99_NET_100_U77004_4, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U77005(__Z99_NET_98, MT12, __Z99_NET_99, __Z99_NET_99, __Z99_NET_98, __Z99_NET_100, GND, __Z99_NET_88, __Z99_NET_99, __Z99_NET_73, __Z99_NET_87, __Z99_NET_99, __RestartMonitor__CCH77, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U77006(__Z99_NET_56, __Z99_NET_75, __Z99_NET_74, __Z99_NET_74, __Z99_NET_56, __RestartMonitor__CCH77, GND, __Z99_NET_69, __Z99_NET_76, __Z99_NET_64, __Z99_NET_64, __RestartMonitor__CCH77, __Z99_NET_76, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77007(__Z99_NET_69, MPAL_n, __Z99_NET_70, __Z99_NET_65, __Z99_NET_72, __Z99_NET_71, GND, __Z99_NET_65, __RestartMonitor__CCH77, __Z99_NET_71, __Z99_NET_82, __Z99_NET_81, __Z99_NET_66, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U77008(MT05, __Z99_NET_70, MTCAL_n, __Z99_NET_72, MRPTAL_n, __Z99_NET_82, GND, __Z99_NET_84, MWATCH_n, __Z99_NET_78, MVFAIL_n, __Z99_NET_80, MCTRAL_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77009(__Z99_NET_81, __Z99_NET_66, __RestartMonitor__CCH77, __Z99_NET_63, __Z99_NET_84, __Z99_NET_83, GND, __Z99_NET_63, __RestartMonitor__CCH77, __Z99_NET_83, __Z99_NET_78, __Z99_NET_77, __Z99_NET_67, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U77010(__Z99_NET_77, __Z99_NET_67, __RestartMonitor__CCH77, __Z99_NET_68, __Z99_NET_80, __Z99_NET_79, GND, __Z99_NET_68, __RestartMonitor__CCH77, __Z99_NET_79, __Z99_NET_59, __Z99_NET_57, __Z99_NET_58, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U77011(__Z99_NET_57, __Z99_NET_58, __RestartMonitor__CCH77, __Z99_NET_62, __Z99_NET_60, __Z99_NET_61, GND, __Z99_NET_62, __RestartMonitor__CCH77, __Z99_NET_61, , , , p4VSW, SIM_RST, SIM_CLK);
U74HC04 U77012(MSCAFL_n, __Z99_NET_59, MSCDBL_n, __Z99_NET_60, , , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77013(__RestartMonitor__RCH77_n, __Z99_NET_56, __RestartMonitor__RCH77_n, __Z99_NET_64, GND, MDT02, GND, MDT03, __RestartMonitor__RCH77_n, __Z99_NET_65, GND, MDT01, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77014(__RestartMonitor__RCH77_n, __Z99_NET_66, __RestartMonitor__RCH77_n, __Z99_NET_63, GND, MDT05, GND, MDT06, __RestartMonitor__RCH77_n, __Z99_NET_67, GND, MDT04, GND, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U77015(__RestartMonitor__RCH77_n, __Z99_NET_68, __RestartMonitor__RCH77_n, __Z99_NET_58, GND, MDT08, GND, MDT09, __RestartMonitor__RCH77_n, __Z99_NET_62, GND, MDT07, GND, p4VSW, SIM_RST, SIM_CLK);
endmodule |
module jtag_monitor(SIM_CLK, MSTRT, MSTP, MDT01, MDT02, MDT03, MDT04, MDT05, MDT06, MDT07, MDT08, MDT09, MDT10, MDT11, MDT12, MDT13, MDT14, MDT15, MDT16, MONPAR, MREAD, MLOAD, MRDCH, MLDCH, MTCSAI, MONWBK, MNHRPT, MNHNC, MNHSBF, MAMU, NHALGA, DBLTST, DOSCAL, MT01, MT02, MT03, MT04, MT05, MT06, MT07, MT08, MT09, MT10, MT11, MT12, MWL01, MWL02, MWL03, MWL04, MWL05, MWL06, MWL07, MWL08, MWL09, MWL10, MWL11, MWL12, MWL13, MWL14, MWL15, MWL16, MSQ16, MSQ14, MSQ13, MSQ12, MSQ11, MSQ10, MSQEXT, MST1, MST2, MST3, MNISQ, MWAG, MWLG, MWQG, MWZG, MWBBEG, MWEBG, MWFBG, MWG, MWSG, MWBG, MWCH, MRGG, MREQIN, MTCSA_n);
input wire SIM_CLK;
output wire MSTRT; // Inject a Fresh Start when pulsed
output wire MSTP; // While asserted, the timepulse generator is stuck in timepulse 12. Allows MCT-by-MCT stepping
output wire MDT01; // Monitor data bus. Directly fed onto the write bus without gating.
output wire MDT02;
output wire MDT03;
output wire MDT04;
output wire MDT05;
output wire MDT06;
output wire MDT07;
output wire MDT08;
output wire MDT09;
output wire MDT10;
output wire MDT11;
output wire MDT12;
output wire MDT13;
output wire MDT14;
output wire MDT15;
output wire MDT16;
output reg MONPAR = 0; // Monitor parity input. Handled indentically to SAP (Sense Amplifier Parity)
output reg MREAD = 0; // Reads the value of a memory location by starting the FETCH unprogrammed sequence
output reg MLOAD = 0; // Writes to a memory location by starting the STORE unprogrammed sequence
output reg MRDCH = 0; // Reads the value of a channel by starting the INOTRD (In/Out Read) unprogrammed sequence
output reg MLDCH = 0; // Writes to a channel by starting the INOTLD (In/Out Load) unprogrammed sequence
output reg MTCSAI = 0; // Transfers control to the address specified by starting the TCSAJ unprogrammed sequence
output reg MONWBK = 0; // Inhibits U2BBK during STORE and FETCH sequences
output reg MNHRPT = 0; // Inhibits interrupts while asserted
output reg MNHNC = 0; // Inhibits counter interrupts while asserted
output reg MNHSBF = 0; // Inhibits fixed memory reads while asserted
output reg MAMU = 0; // Inhibits erasable memory access
output wire NHALGA; // Inhibits alarm gate alarms while asserted
output reg DBLTST = 0; // Tests the scaler double alarm, probably making use of MON800
output reg DOSCAL = 0; // Tests the scaler fail alarm by inhibiting SCAS17
input wire MT01; // Timepulses
input wire MT02;
input wire MT03;
input wire MT04;
input wire MT05;
input wire MT06;
input wire MT07;
input wire MT08;
input wire MT09;
input wire MT10;
input wire MT11;
input wire MT12;
input wire MWL01; // Write bus
input wire MWL02;
input wire MWL03;
input wire MWL04;
input wire MWL05;
input wire MWL06;
input wire MWL07;
input wire MWL08;
input wire MWL09;
input wire MWL10;
input wire MWL11;
input wire MWL12;
input wire MWL13;
input wire MWL14;
input wire MWL15;
input wire MWL16;
input wire MSQ16; // SQ register bits
input wire MSQ14;
input wire MSQ13;
input wire MSQ12;
input wire MSQ11;
input wire MSQ10;
input wire MSQEXT;
input wire MST1; // Stage registers
input wire MST2;
input wire MST3;
input wire MNISQ; // New instruction loaded into the SQ register
input wire MWAG; // Write into the A register
input wire MWLG; // Write into the L register
input wire MWQG; // Write into the Q register
input wire MWZG; // Write into the Z register
input wire MWBBEG; // Write into the BB register
input wire MWEBG; // Write into the EB register
input wire MWFBG; // Write into the FB register
input wire MWG; // Write into the G register
input wire MWSG; // Write into the S register
input wire MWBG; // Write into the B register
input wire MWCH; // Write to a channel
input wire MRGG; // Read from G register
input wire MREQIN; // Monitor sequence request has been latched
input wire MTCSA_n; // Monitor transfer control instruction sequence is selected
wire [15:0] write_bus;
assign write_bus = {MWL16, MWL15, MWL14, MWL13, MWL12, MWL11, MWL10, MWL09, MWL08, MWL07, MWL06, MWL05, MWL04, MWL03, MWL02, MWL01};
wire [15:0] direct_sq;
assign direct_sq = {MSQEXT, MSQ16, MSQ14, MSQ13, MSQ12, MSQ11, MSQ10, 9'b0};
wire [2:0] stage;
assign stage = {MST3, MST2, MST1};
reg suppress_mstp = 1'b0;
reg tcsaj_in_progress = 1'b0;
reg [15:0] monitor_data;
assign MDT01 = monitor_data[0];
assign MDT02 = monitor_data[1];
assign MDT03 = monitor_data[2];
assign MDT04 = monitor_data[3];
assign MDT05 = monitor_data[4];
assign MDT06 = monitor_data[5];
assign MDT07 = monitor_data[6];
assign MDT08 = monitor_data[7];
assign MDT09 = monitor_data[8];
assign MDT10 = monitor_data[9];
assign MDT11 = monitor_data[10];
assign MDT12 = monitor_data[11];
assign MDT13 = monitor_data[12];
assign MDT14 = monitor_data[13];
assign MDT15 = monitor_data[14];
assign MDT16 = monitor_data[15];
// JTAG Registers
reg bypass_reg = 0;
reg [15:0] tmp_reg;
reg [15:0] cntrl_reg = 16'o0;
reg [15:0] break_bank = 16'o0;
reg [15:0] break_addr = 16'o0;
reg [15:0] rw_bank = 16'o0;
reg [15:0] rw_addr = 16'o0;
reg [15:0] rw_data = 16'o0;
reg [15:0] a_reg = 16'o0;
reg [15:0] l_reg = 16'o0;
reg [15:0] q_reg = 16'o0;
reg [15:0] z_reg = 16'o0;
reg [15:0] bb_reg = 16'o0;
reg [15:0] g_reg = 16'o0;
reg [15:0] s_reg = 16'o0;
reg [15:0] b_reg = 16'o0;
reg [15:0] x_reg = 16'o0;
reg [15:0] y_reg = 16'o0;
reg [15:0] u_reg = 16'o0;
// JTAG control wires
wire step;
wire step_type;
wire break_inst;
wire fetch_data;
wire store_data;
wire read_chan;
wire load_chan;
wire transfer_control;
// CONTROL register bits
assign MSTP = cntrl_reg[0] && !suppress_mstp; // Bit 0 = MSTP
assign MSTRT = cntrl_reg[1]; // Bit 1 = MSTRT
assign step = cntrl_reg[2]; // Bit 2 = Single-step
assign step_type = cntrl_reg[3]; // Bit 3 = Step type
assign break_inst = cntrl_reg[4]; // Bit 4 = Break on instruction
assign fetch_data = cntrl_reg[5]; // Bit 5 = Fetch data at specified address
assign store_data = cntrl_reg[6]; // Bit 6 = Store data to specified address
assign read_chan = cntrl_reg[7]; // Bit 7 = Read the specified channel
assign load_chan = cntrl_reg[8]; // Bit 8 = Load the specified channel
assign transfer_control = cntrl_reg[9]; // Bit 9 = Transfer control to specified address
assign NHALGA = cntrl_reg[10]; // Bit 10 = NHALGA
// Virtual JTAG implementation
wire tck, tdi;
reg tdo = 0;
wire [4:0] ir_in;
wire cdr, sdr, e1dr;
vjtag VJTAG (
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr (cdr),
.virtual_state_sdr (sdr),
.virtual_state_e1dr (e1dr),
.tck (tck)
);
always @(posedge SIM_CLK) begin
// Latch completed words into their target registers
if (e1dr) begin
case (ir_in)
`CONTROL: begin
if (tmp_reg[15] == 1'b1) begin
cntrl_reg[14:0] <= tmp_reg[14:0];
end
end
`BRKBANK: begin
if (tmp_reg[15] == 1'b1) begin
break_bank[15] <= tmp_reg[14];
break_bank[14:0] <= tmp_reg[14:0];
end
end
`BRKADDR: begin
if (tmp_reg[15] == 1'b1) begin
break_addr[14:0] <= tmp_reg[14:0];
end
end
`RWBANK: begin
if (tmp_reg[15] == 1'b1) begin
rw_bank[15] <= tmp_reg[14];
rw_bank[14:0] <= tmp_reg[14:0];
end
end
`RWADDR: begin
if (tmp_reg[15] == 1'b1) begin
rw_addr[14:0] <= tmp_reg[14:0];
end
end
`RWDATA: begin
// We care about all 16 bits, so RWDATA has no write bit.
rw_data[15:0] <= tmp_reg[15:0];
end
endcase
end else begin
// Internal state logic
if (step) begin
// Instruction steps end on MNISQ. MCT steps end on MT01.
if ((MT01 && step_type == `STEP_MCT) || (MNISQ && step_type == `STEP_INST)) begin
cntrl_reg[2] <= 0;
suppress_mstp <= 0;
end else begin
// Suppress MSTP while stepping
suppress_mstp <= 1;
end
end
end
// Update registers
if (MWAG) begin
a_reg <= write_bus;
end
if (MWLG) begin
l_reg <= write_bus;
end
if (MWQG) begin
q_reg <= write_bus;
end
if (MWZG) begin
z_reg <= write_bus;
end
if (MWBBEG) begin
bb_reg[14] <= write_bus[15];
bb_reg[13:10] <= write_bus[13:10];
bb_reg[2:0] <= write_bus[2:0];
end
if (MWEBG) begin
bb_reg[2:0] <= write_bus[10:8];
end
if (MWFBG) begin
bb_reg[14] <= write_bus[15];
bb_reg[13:10] <= write_bus[13:10];
end
if (MWG || MRGG) begin
g_reg <= write_bus;
end
if (MWSG) begin
s_reg[11:0] <= write_bus[11:0];
end
if (MWBG) begin
b_reg <= write_bus;
end
if (MWCH && s_reg[8:0] == 9'o7) begin
bb_reg[6:4] <= write_bus[6:4];
end
// Check breakpoints. Breakpoints in switched-erasable not yet supported.
if (break_inst && MNISQ && s_reg[11:0] == break_addr[11:0] && // S should always completely match what was requested
(s_reg[11:10] != 2'b01 || (s_reg[11:10] == 2'b01 && // If S is in the 2000..3777 range, our fixed bank must match
(bb_reg[14:13] == 2'b11 && bb_reg[14:4] == break_bank[14:4]) || // If the fixed bank is in the 30..37 range, the FEB applies
(bb_reg[14:13] != 2'b11 && bb_reg[14:10] == break_bank[14:10])))) begin // Otherwise only use the FB bits
// We just loaded the breakpointed instruction. Issue MSTP.
cntrl_reg[0] <= 1;
end
// Handle STORE/FETCH sequences
if (fetch_data || store_data) begin
if (!MREQIN) begin
// Allow progression until our request is latched and T01 of the sequence starts
if (fetch_data) MREAD <= 1'b1;
else MLOAD <= 1'b1;
suppress_mstp <= 1'b1;
end else begin
if (stage == 3'o0) begin
if (MT01) begin
MREAD <= 1'b0;
MLOAD <= 1'b0;
end else if (MT04) begin
monitor_data <= rw_bank;
end else if (MT05) begin
monitor_data <= 16'o0;
end else if (MT08) begin
monitor_data <= rw_addr;
end else if (MT09) begin
monitor_data <= 16'o0;
end
end else if (stage == 3'o1) begin
if (MT04 && store_data) begin
if (rw_addr == 16'o6) MONWBK <= 1'b1;
monitor_data <= rw_data;
end else if (MT05) begin
monitor_data <= 16'b0;
end else if (MT07 && fetch_data) begin
rw_data <= write_bus;
end else if (MT09 && store_data) begin
monitor_data <= rw_data;
end else if (MT10) begin
monitor_data <= 16'b0;
bb_reg[14] <= write_bus[15];
bb_reg[13:10] <= write_bus[13:10];
bb_reg[2:0] <= write_bus[2:0];
end else if (MT11) begin
if (fetch_data) cntrl_reg[5] <= 1'b0;
else cntrl_reg[6] <= 1'b0;
suppress_mstp <= 1'b0;
MONWBK <= 1'b0;
end
end
end
end
// Handle INOTLD/INOTRD sequences
if (read_chan || load_chan) begin
if (!MREQIN) begin
// Allow progression until our request is latched and T01 of the sequence starts
if (read_chan) MRDCH <= 1'b1;
else MLDCH <= 1'b1;
suppress_mstp <= 1'b1;
end else begin
if (MT01) begin
MRDCH <= 1'b0;
MLDCH <= 1'b0;
monitor_data <= rw_addr;
end else if (MT02) begin
monitor_data <= 16'o0;
end else if (MT05 && read_chan) begin
rw_data <= write_bus;
end else if (MT07 && load_chan) begin
monitor_data <= rw_data;
end else if (MT08) begin
monitor_data <= 16'o0;
end else if (MT11) begin
if (read_chan) cntrl_reg[7] <= 1'b0;
else cntrl_reg[8] <= 1'b0;
suppress_mstp <= 1'b0;
end
end
end
// Handle TCSAJ
if (transfer_control) begin
if (!(!MTCSA_n || tcsaj_in_progress)) begin
MTCSAI <= 1'b1;
suppress_mstp <= 1'b1;
end else begin
if (stage == 3'o3) begin
if (MT01) begin
MTCSAI <= 1'b0;
tcsaj_in_progress <= 1'b1;
end else if (MT08) begin
monitor_data <= rw_addr;
end else if (MT09) begin
monitor_data <= 16'o0;
end
end else begin
if (MT11) begin
tcsaj_in_progress <= 1'b0;
cntrl_reg[9] <= 1'b0;
suppress_mstp <= 1'b0;
end
end
end
end
end
// During SDR, shift into either the temporary shift register or the bypass register, depending on whether
// or not a real instruction has been selected. During CDR, copy the current register value into the
// temporary register to prepare for shifting it out.
always @(posedge tck) begin
if (ir_in == `BYPASS) begin
bypass_reg <= tdi;
end else begin
if (cdr) begin
case (ir_in)
`CONTROL: tmp_reg <= cntrl_reg;
`BRKBANK: begin
tmp_reg[15] <= 1'b0;
tmp_reg[14:0] <= break_bank[14:0];
end
`BRKADDR: tmp_reg <= break_addr;
`RWBANK: begin
tmp_reg[15] <= 1'b0;
tmp_reg[14:0] <= rw_bank[14:0];
end
`RWADDR: tmp_reg <= rw_addr;
`RWDATA: tmp_reg <= rw_data;
`REG_A: tmp_reg <= a_reg;
`REG_L: tmp_reg <= l_reg;
`REG_Q: tmp_reg <= q_reg;
`REG_Z: tmp_reg <= z_reg;
`REG_BB: tmp_reg <= bb_reg;
`REG_G: tmp_reg <= g_reg;
`REG_SQ: tmp_reg <= direct_sq;
`REG_S: tmp_reg <= s_reg;
`REG_B: tmp_reg <= b_reg;
endcase
end else if (sdr) begin
tmp_reg <= {tdi, tmp_reg[15:1]};
end
end
end
// Shift out previously prepared data, or the bypass reg if not hitting a real register
always @(tmp_reg[0] or bypass_reg) begin
if (ir_in == `BYPASS) begin
tdo <= bypass_reg;
end else begin
tdo <= tmp_reg[0];
end
end
endmodule |
module vjtag (
output wire tdi, // jtag.tdi
input wire tdo, // .tdo
output wire [4:0] ir_in, // .ir_in
input wire [4:0] ir_out, // .ir_out
output wire virtual_state_cdr, // .virtual_state_cdr
output wire virtual_state_sdr, // .virtual_state_sdr
output wire virtual_state_e1dr, // .virtual_state_e1dr
output wire virtual_state_pdr, // .virtual_state_pdr
output wire virtual_state_e2dr, // .virtual_state_e2dr
output wire virtual_state_udr, // .virtual_state_udr
output wire virtual_state_cir, // .virtual_state_cir
output wire virtual_state_uir, // .virtual_state_uir
output wire tck // tck.clk
);
sld_virtual_jtag #(
.sld_auto_instance_index ("NO"),
.sld_instance_index (2),
.sld_ir_width (5)
) virtual_jtag_0 (
.tdi (tdi), // jtag.tdi
.tdo (tdo), // .tdo
.ir_in (ir_in), // .ir_in
.ir_out (ir_out), // .ir_out
.virtual_state_cdr (virtual_state_cdr), // .virtual_state_cdr
.virtual_state_sdr (virtual_state_sdr), // .virtual_state_sdr
.virtual_state_e1dr (virtual_state_e1dr), // .virtual_state_e1dr
.virtual_state_pdr (virtual_state_pdr), // .virtual_state_pdr
.virtual_state_e2dr (virtual_state_e2dr), // .virtual_state_e2dr
.virtual_state_udr (virtual_state_udr), // .virtual_state_udr
.virtual_state_cir (virtual_state_cir), // .virtual_state_cir
.virtual_state_uir (virtual_state_uir), // .virtual_state_uir
.tck (tck) // tck.clk
);
endmodule |
module ym6045c_cell_1_not ( i2, o3);
input wire i2;
output wire o3;
assign o3 = ~i2;
endmodule // ym6045c_cell_1_not |
module ym6045c_cell_6_and ( o2, i3, i4);
output wire o2;
input wire i3;
input wire i4;
assign o2 = i3 & i4;
endmodule // ym6045c_cell_6_and |
module ym6045c_cell_5_nand ( i1, i2, o3);
input wire i1;
input wire i2;
output wire o3;
assign o3 = ~(i1 & i2);
endmodule // ym6045c_cell_5_nand |
module ym6045c_cell_7_buf ( o2, i3);
output wire o2;
input wire i3;
assign o2 = i3;
endmodule // ym6045c_cell_7_buf |
module ym6045c_cell_4_nand3 ( i1, i2, i3, o4);
input wire i1;
input wire i2;
input wire i3;
output wire o4;
assign o4 = ~(i1 & i2 & i3);
endmodule // ym6045c_cell_4_nand3 |
module ym6045c_cell_16_buf ( o2, i4);
output wire o2;
input wire i4;
assign o2 = i4;
endmodule // ym6045c_cell_16_buf |
module ym6045c_cell_29_and6 ( o1, i2, i3, i4, i5, i6, i7);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
input wire i5;
input wire i6;
input wire i7;
assign o1 = i2 & i3 & i4 & i5 & i6 & i7;
endmodule // ym6045c_cell_29_and6 |
module ym6045c_cell_30_nor4 ( o2, i3, i4, i5, i6);
output wire o2;
input wire i3;
input wire i4;
input wire i5;
input wire i6;
assign o2 = ~(i3 | i4 | i5 | i6);
endmodule // ym6045c_cell_30_nor4 |
module ym6045c_cell_19_and4 ( o1, i2, i3, i4, i5);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
input wire i5;
assign o1 = i2 & i3 & i4 & i5;
endmodule // ym6045c_cell_19_and4 |
module ym6045c_cell_10_or ( i2, o3, i4);
input wire i2;
output wire o3;
input wire i4;
assign o3 = i2 | i4;
endmodule // ym6045c_cell_10_or |
module ym6045c_cell_8_nor ( o1, i2, i3);
output wire o1;
input wire i2;
input wire i3;
assign o1 = ~(i2 | i3);
endmodule // ym6045c_cell_8_nor |
module ym6045c_cell_18_or3 ( o1, i2, i3, i4);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
assign o1 = i2 | i3 | i4;
endmodule // ym6045c_cell_18_or3 |
module ym6045c_cell_3_nand4 ( i2h, i2l, i3h, i3l, o4);
input wire i2h;
input wire i2l;
input wire i3h;
input wire i3l;
output wire o4;
assign o4 = ~(i2h & i2l & i3h & i3l);
endmodule // ym6045c_cell_3_nand4 |
module ym6045c_cell_15_and3 ( o1, i2, i3, i4);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
assign o1 = i2 & i3 & i4;
endmodule // ym6045c_cell_15_and3 |
module ym6045c_cell_24_nand6 ( i1h, i1l, i2h, i2l, i4h, i4l, o7);
input wire i1h;
input wire i1l;
input wire i2h;
input wire i2l;
input wire i4h;
input wire i4l;
output wire o7;
assign o7 = ~(i1h & i1l & i2h & i2l & i4h & i4l);
endmodule // ym6045c_cell_24_nand6 |
module ym6045c_cell_21_or4 ( o1, i2, i3, i4, i5);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
input wire i5;
assign o1 = i2 | i3 | i4 | i5;
endmodule // ym6045c_cell_21_or4 |
module ym6045c_cell_12_nor3 ( o1, i2, i3, i4);
output wire o1;
input wire i2;
input wire i3;
input wire i4;
assign o1 = ~(i2 | i3 | i4);
endmodule // ym6045c_cell_12_nor3 |
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